SH7058

REJ09B0046-0300H The revision list can be viewed directly by clicking the title page. The rivision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SH-2E SH7058 F-ZTAT TM Hardware Manual Renesas SuperHTM RISC engine Rev. 3.00 Revision date: Sep. 17, 2004 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins.The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level.Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass-through current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined.The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed. Preface The SH7058 is a single-chip RISC (reduced instruction set computer) microcomputer that has the 32-bit internal architecture CPU, SH-2E, as its core, and also includes peripheral functions necessary for system configuration. The SH7058 is equipped with on-chip peripheral functions necessary for system configuration, including a floating-point unit (FPU), large-capacity ROM and RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), controller area network (HCAN), A/D converter, and I/O ports, therefore, it can be used as a microprocessor built in a high-level control system. The SH7058 is an F-ZTAT™* (Flexible Zero Turn-Around Time) version with flash memory as its on-chip ROM, and it can rapidly and flexibly deal with each situation on an application system with fluid specifications from an early stage of mass production to full-scale production. Note: * F-ZTAT™ is a trademark of Renesas Technology, Corp. Target users: This manual was written for users who will be using the SH7058 F-ZTAT in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical curcuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the SH7058 F-ZTAT to the above users. Refer to the SH-2E Programming Manual for a detailed description of the instruction set. Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. • In order to understand the details of the CPU's functions Read the SH-2E Programming Manual. Rule: Bit order: The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right. Releated Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ Rev. 3.0, 09/04, page i of xxxviii SH7058 F-ZTAT manuals: Manual Title SH7058 F-ZTAT Hardware Manual SH-2E Programming Manual Document No. This manual Users manuals for development tools: Manual Title SH Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual SH Series Simulator/Debugger (for Windows) User's Manual SH Series Simulator/Debugger (for UNIX) User's Manual High-performance Embedded Workshop User's Manual Document No. ADE-702-246 ADE-702-186 ADE-702-203 ADE-702-201 Application note: Manual Title C/C++ Compiler Document No. Rev. 3.0, 09/04, page ii of xxxviii Main Revisions for this Edition Item 1.2 Block Diagram Figure 1.1 Block Diagram RES HSTBY FWE MD2 MD1 MD0 NMI WDTOVF Page 7 Revisions (See Manual for Details) Corrected errors PF13/CS3 PF12/CS2 PF11/CS1 PF10/CS0 PF5/A21/POD PF4/A20 PF3/A19 PF2/A18 PF1/A17 PF0/A16 PE15/A15 PE14/A14 PE13/A13 PE12/A12 PE11/A11 PE10/A10 PE9/A9 PE8/A8 PE7/A7 PE6/A6 PE5/A5 PE4/A4 PE3/A3 PE2/A2 PE1/A1 PE0/A0 Port/address signals RAM 48 kB DMAC (4 channels) PH15/D15 PH14/D14 PH13/D13 PH12/D12 PH11/D11 PH10/D10 PH9/D9 PH8/D8 PH7/D7 PH6/D6 PH5/D5 PH4/D4 PH3/D3 PH2/D2 PH1/D1 PH0/D0 BSC PA0/TI0A PA1/TI0B PA2/TI0C PA3/TI0D PA4/TIO3A PA5/TIO3B PA6/TIO3C PA7/TIO3D PA8/TIO4A/ADTO0A PA9/TIO4B/ADTO0B PA10/TIO4C/ADTO1A PA11/TIO4D/ADTO1B PA12/TIO5A PA13/TIO5B PA14/TxD0 PA15/RxD0 PB0/TO6A PB1/TO6B PB2/TO6C PB3/TO6D PB4/TO7A/TO8A PB5/TO7B/TO8B PB6/TO7C/TO8C PB7/TO7D/TO8D PB8/TxD3/TO8E PB9/RxD3/TO8F PB10/TxD4/HTxD0/TO8G PB11/RxD4/HRxD0/TO8H PB12/TCLKA/UBCTRG PB13/SCK0 PB14/SCK1/TCLKB/TI10 PB15/PULS5/SCK2 PC0/TxD1 PC1/RxD1 PC2/TxD2 PC3/RxD2 PC4/IRQ0 PG0/PULS7/HRxD0/HRxD1 PG1/IRQ1 PG2/IRQ2/ADEND PG3/IRQ3/ADTRG0 ATU-II A/D converter WDT Port Port/control signals PF15/BREQ PF14/BACK PF8/WAIT PF9/RD PF7/WRH PF6/WRL ROM (flash) 1 MB CK EXTAL XTAL PLLVCC PLLVSS PLLCAP Vcc (×8) PVcc1 (×4) PVcc2 (×6) VCL(×3) Vss (×21) AVref (×2) AVcc (×2) AVss (×2) AN31–0 AUDRST AUDMD AUDATA3–0 AUDCK AUDSYNC TMS TRST TDI TDO TCK PD0/TIO1A PD1/TIO1B PD2/TIO1C PD3/TIO1D PD4/TIO1E PD5/TIO1F PD6/TIO1G PD7/TIO1H PD8/PULS0 PD9/PULS1 PD10/PULS2 PD11/PULS3 PD12/PULS4 PD13/PULS6/HTxD0/HTxD1 PL0/TI10 PL1/TIO11A/IRQ6 PL2/TIO11B/IRQ7 PL3/TCLKB PL4/ADTRG0 PL5/ADTRG1 PL6/ADEND PL7/SCK2 PL8/SCK3 PL9/SCK4/IRQ5 PL10/HTxD0/HTxD1/HTxD0 & HTxD1 PL11/HRxD0/HRxD1/HRxD0 & HRxD1 PL12/IRQ4 PL13/IRQOUT Clock pulse generator CPU FPU Multiplier Interrupt controller SCI (5 channels) HCAN II (2 channels) CMT (2 channels) AUD H-UDI Port PK15/TO8P PK14/TO8O PK13/TO8N PK12/TO8M PK11/TO8L PK10/TO8K PK9/TO8J PK8/TO8I PK7/TO8H PK6/TO8G PK5/TO8F PK4/TO8E PK3/TO8D PK2/TO8C PK1/TO8B PK0/TO8A PJ15/TI9F PJ14/TI9E PJ13/TI9D PJ12/TI9C PJ11/TI9B PJ10/TI9A PJ9/TIO5D PJ8/TIO5C PJ7/TIO2H PJ6/TIO2G PJ5/TIO2F PJ4/TIO2E PJ3/TIO2D PJ2/TIO2C PJ1/TIO2B PJ0/TIO2A Port : Peripheral address bus (9 bits) : Peripheral data bus (16 bits) : Internal address bus (32 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) 1.3.1 Pin Arrangement Figure 1.3 Pin Assignments 1.3.2 Pin Functions Table 1.2 Pin Functions 1.3.3 Pin Assignments Table 1.3 Pin Assignments 7.1.1 Features 9 Newly added 10-18 BP-272 added 19-27 BP-272 added 101 • Notification of interrupt occurrence can be reported externally (IRQOUT pin) For example, it is possible to request the bus if an external bus master is informed that an on-chip peripheral module interrupt request has occurred when the chip has released the bus. 7.4.1 Interrupt Sequence Figure 7.2 Interrupt Sequence Flowchart 120 Note amended 1. As IRQOUT is synchronized with a peripheral clock Pφ, it may be output later than a CPU interrupt request. Rev. 3.0, 09/04, page iii of xxxviii Port Port/data signals Item 7.5 Interrupt Response Time Table 7.5 Interrupt Response Time Page 122 Revisions (See Manual for Details) Table amended Number of States Item Synchronizing input signal (synchronized with peripheral clock Pφ) with internal clock φ and DMAC activation judgment Compare identified interrupt priority with SR mask level Wait for completion of sequence currently being executed by CPU Peripheral Module 0 or 6 [0 or 3] NMI 1 to 4 [1 or 2] IRQ 6 to 9 [3 to 5] Notes For the number of states required for each interrupt, see the note (*) below. The values enclosed in [ ] are values for when the multiplication ratio is 4. 2 X (≥ 0) 2 2 The longest sequence is for interrupt or address-error exception processing (X = 4 + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Performs the PC and SR saves and vector address fetch. (13 to 16) + m1 + m2 + m3 + X 16 Time from start of interrupt 5 + m1 + m2 + m3 exception processing until fetch of first instruction of exception service routine starts Interrupt Total: (7 or 13) + (8 to 11) + response time m1 + m2 + m1 + m2 + m3 + X m3 + X Minimum: 10 11 Maximum: 17 + 2 (m1 + 15 + 2 (m1 + 20 + 2 (m1 + m2 + m3) + m2 + m3) + m2 + m3) + m4 m4 m4 Note: * Number of states needed for synchronization and DMAC activation judgment The relations between numbers of states needed for synchronizing an input signal (synchronized with the peripheral clock Pφ) with the internal clock φ and DMAC activation judgment and vector numbers are shown below. 0 state: 9, 10, 12, 13, 14, 72, 74, 76, 78, 189, 193, and 224 6 states: Peripheral module interrupts other than the above. However, vector number 222 (HCAN0/RM0) is different from the others. For an interrupt with vector number 222 (HCAN0/RM0), the needed states differ from other interrupts since the interrupt by HCAN0 mailbox 0 can activate the DMAC. HCAN0 mailbox 0: 7 states Other than above: 6 states The same number of states is needed to cancel interrupt sources. If the necessary number of states is not secured after flag clear of the interrupt source, the interrupt may occur again. 7.5 Interrupt Response Time Figure 7.4 Example of Pipeline Operation when an IRQ Interrupt is Accepted 123 Figure amended Interrupt acceptance IRQ 6 to 9 Synchronization of IRQ 2 Interrupt controller processing Instruction Overrun fetch Interrupt service routine start instruction F D F F D E E E M M E M E E 3 5 + m1 + m2 + m3 m1 m2 1 m3 1 9.1.5 Address Map Table 9.3 Address Map • Number of Access Cycles for On-Chip Peripheral Module Registers 10.3.2 DMA Transfer Requests 146 Newly added 179 Description added In on-chip peripheral module request mode, when the DMAC accepts the transfer request, the next transfer request is ignored until a single transfer ends in cycle steal mode or all transfers end in burst mode. Only when the address reload function is used, the next transfer request is accepted after the fourth transfer. Rev. 3.0, 09/04, page iv of xxxviii Item 10.3.2 DMA Transfer Requests Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits Page 180, 182 Revisions (See Manual for Details) Table amended DMAC Transfer Request DMAC Transfer Transfer RS4 RS3 RS2 RS1 RS0 Source Request Signal Source 0 0 0 1 1 HCAN0 Transfer Destination Bus Mode RM0 (HCAN0 MB0-MB15 Don't care* Burst/cyclereceive interrupt) steal MB0-MB15: HCAN0 message data 10.3.11 DMAC Access from CPU 193 Description amended The space addressed by the DMAC is 4-cycle space. Therefore, when the CPU becomes the bus master and accesses the DMAC, a minimum of four internal clock cycles (φ) are required for one bus cycle. Also, since the DMAC is located in word space, while a word-size access to the DMAC is completed in one bus cycle, a longword-size access is automatically divided into two word accesses, requiring two bus cycles (eight basic clock cycles). These two bus cycles are executed consecutively; a different bus cycle is never inserted between the two word accesses. This applies to both write accesses and read accesses. 11.2.21 Offset Base Registers (OSBR) 341 Bit table amended Dedicated input capture registers with the same input trigger signal as that for channel 0 ICR0A Offset Base Registers 1 and 2 (OSBR1, OSBR2) Description amended OSBR1 and OSBR2 are 16-bit read-only registers used exclusively for input capture. Same as the channel 0 input capture register (ICR0A), OSBR1 and OSBR2 use the TI0A input as their trigger signal, and store the TCNT1A or TCNT2A value on detection of an edge. 366 Description amended …When the 16-bit correction counter 10F (TCNT10F) value exceeds that in 16-bit correction counter 10E (TCNT10E) , no count-up operation is performed. Figure amended Pφ 11.3.1 Overview Channel 10: (3) Multiplied clock correction block 11.3.2 Free-Running Counter Operation 367 and Cyclic Counter Operation Figure 11.13 Free-Running Counter Operation and Overflow Timing TSTR1 STR0 TCNT0 Clock TCNT0 00000001 00000002 00000003 00000004 00000005 00000006 TSR0 OVF0 Rev. 3.0, 09/04, page v of xxxviii Item 11.3.8 Twin-Capture Function Page 373 Revisions (See Manual for Details) Description amended When TCNT0, TCNT1A, and TCNT2A in channel 0, channel 1, and channel 2 are started by a setting in the timer start register (TSTR), and an edge of TI0A input (a trigger signal) is detected, the TCNT1A value is transferred to OSBR1, and the TCNT2A value to OSBR2. 11.3.9 PWM Timer Function Figure 11.21 PWM Timer Operation 375 Figure amended Pφ STR TCNT6A Clock TCNT6A 0001 0002 0003 0004 CYLR6A Write to BFR6A BFR6A 0002 DTR6A TO6A * PWM output does not change for one cycle after activation TSR6 CMF6A Cycle 11.3.9 PWM Timer Function Figure 11.22 Complementary PWM Mode Operation 11.3.12 Channel 10 Functions Figure 11.28 TCNT10A Capture Operation and Compare-Match Operation 376 Figure replaced 381 Figure amended Pφ TSTR1 STR10 TCNT10A TCNT10A 00000001 00000002 00000003 12345677 1234 5678 00000001 55555555 55555556 55555557 AGCK Capture transfer signal TCNT reset signal ICR10A 00000000 12345678 TSR10 IMF10A Cleared by software OCR10A 55555556 TSR10 CMF10A Cleared by software Multiplied Clock Generation Function: Figure 11.30 TCNT10C Operation 383 Description amended TST10→STR10 Rev. 3.0, 09/04, page vi of xxxviii Item Multiplied Clock Correction Function: Figure 11.32 TCNT10D Operation Figure 11.33 TCNT10E Operation Figure 11.34 TCNT10F Operation (At Startup) Multiplied Clock Correction Function: Figure 11.35 TCNT10F Operation (End of Cycle, Acceleration, Deceleration) Page 384, 385 Revisions (See Manual for Details) Description amended TST10→STR10 When the TCNT10F value exceeds the TCNT10E value , no count-up operation is performed. 386 Description amended TST10→STR10 Figure amended Pφ STR10 AGCK TCNT10E Clock 00 00 TCNT10E 005A 0060 0061 0062 0063 0064 0065 0066 0076 0077 0078 0079 007A 0001 0080 0002 0003 TCNT10F 005A 00 62 0063 0064 0065 0066 0076 0077 0078 0079 007A 00 01 0002 0003 AGCKM TCNT clock operating on AGCKM 00 62 00 66 00 0002 01 0000 TCNT1, TCNT2 TCNT1, TCNT2 reset trigger TCNT10D 03 005A 0063 0064 0065 0076 0077 0078 0079 007A 0003 Cleared to H'00 by software 04 00 01 Note: Multiplication factor of 32, TCCLR10 = H'0080 Multiplied Clock Correction Function: Figure 11.36 TCNT10F Operation (End of Cycle, Steady-State) 387 Pφ STR10 AGCK TCNT10E Clock 00 00 TCNT10E 005A 0060 0061 0062 0063 0064 0065 0066 007E 007F 0080 0081 0082 0001 0002 0003 TCNT10F 005A 00 62 0063 0064 0065 0066 007E 007F 0080 0001 0002 0003 AGCKM TCNT clock operating on AGCKM 00 62 00 0065 66 TCNT1, TCNT2 TCNT1, TCNT2 reset trigger 005A 0063 0064 007E 007F 0000 0001 0002 Set to H'00 by software TCNT10D 03 04 00 01 Note: Multiplication factor of 32, TCCLR10 = H'0080 11.7 Usage Notes Contention between DCNT Write and Counter Clearing by Underflow: 420 Note amended Note: In the SH7055, a write to DCNT from the CPU is not attempted, but retention of H’0000 takes precedence. Note that its operation is different Rev. 3.0, 09/04, page vii of xxxviii Item 11.7 Usage Notes Figure 11.72 Contention between DCNT Write and Underflow Page 420 Revisions (See Manual for Details) Figure amended Underflow signal H'5555 is written because DCNT write is given priority DCNT 0001 0000 5555 Interrupt status flag (OSF) 12.1.4 Register Configuration Table 12.2 Advanced Pulse Controller Register 14.1.3 Register Configuration Table 14.1 Register Configuration 429 Note amended Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. 453 Note amended Notes: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles for byte access and word access, and eight or nine internal clock (φ) cycles for longword access. 15.1.4 Register Configuration Table 15.2 Registers 467 Note amended Notes: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles for byte access and word access, and eight or nine internal clock (φ) cycles for longword access. Section 16 Controller Area Network-II (HCAN-II) 519616 Description amended Register name Before HCAN-II_bit configuration register Transmit wait register Transmit wait cancel register Receive complete register Remote request register After HCAN-II_bit timing configuration register Transmit Pending Request Register Transmit Cancel Register Data Frame Receive Pending Register Remote Frame Receive Pending Register 16.1.1 Features 519, 520 Description amended • Supports CAN specification 2.0A/2.0B and ISO11898-1 Description deleted • Flexible interrupt structure • Read section 16.8, Usage Notes carefully. The following features have been added in the HCANII. • IRR0 function to notify a software reset and halt Rev. 3.0, 09/04, page viii of xxxviii Item 16.1.1 Features Page 520 Revisions (See Manual for Details) Description deleted • Halt mode status bit and error passive status bit added to GSR. • Supports various test modes 16.2.2 Each Block Function (1) Microprocessor Interface (MPI) 522 Description deleted The MPI allows communication between the host CPU and the HCAN's registers/mailboxes to control . the memory interface, and the data controller, etc. Description deleted • CAN message data (for CAN data frames) • Local acceptance filter mask (LAFM) during reception . • 3-bit mailbox configuration, automatic transmit bit for remote request, new message control bit . (2) Mailboxes (4) Timer Important: added Important: The timer function is not supported by the SH7058. 16.3.1 Mailbox Configuration 526 Note amended Note: The message control (STDID/EXTID/RTR/ZDE), timestamp, and LAFM/transmission trigger time fields can only be accessed in word size (16 bits), whereas the message control (NMC/ATX/MBC/DLC) and the message data area can be accessed in word (16-bit) or byte (8-bit) size. Also, when the setting of the MBC bits makes the mailbox inactive, all settings other than the MBC bits must be initialized to 0 because an unused mailbox affects the RAM configuration. When the LAFM is not used to receive messages, it must be cleared to 0. 16.3.1 Mailbox Configuration Figure 16.3 Mailbox-N Configuration 528 Note amended Notes: 1. All bits shadowed in gray are reserved and the write value should be 0. The value read as the initial value is not guaranteed. Rev. 3.0, 09/04, page ix of xxxviii Item 16.3.2 Message Control Field Page 530532 Revisions (See Manual for Details) Table amended Register Name MBx[4], MBx[5]* Address H'104 + N x 32 Bit 15 Bit Name CCM Description CAN-ID Compare Match When this bit is set, message reception in the corresponding mailbox can generate two triggers. If TCR9 is set to 1, TCR14 is cleared to freeze ICR0. If TCR10 is set to 1, TCNTR (timer counter register) is automatically cleared and the LOSR (local offset register) value is set. Important: This function is not supported by the SH7058. Thus the write value should be 0. Time Trigger Enable When this bit is set, a mailbox in which TXPR has been already set transmits a message at a time set in the Tx trigger time field. Important: If this bit is set, a failure occurs during message transmission. Therefore setting is prohibited. The write value should be 0. The value read as the initial value is not guaranteed. 14 TTE MBx[4], MBx[5]* H'104 + N x 32 13 NMC New Message Control When this bit is cleared, a mailbox in which PXPR/PFPR has been already set does not store the new message but retains the previous one and sets the UMSR corresponding bit. When this bit is set, a mailbox in which PXPR/PFPR has been already set stores the new message and sets the UMSR corresponding bit. If a message is received in a mailbox in overwrite mode (NMC = 1), the host CPU must perform an additional check at the end of the data reading from the mailbox in order to guarantee that the mailbox data have not been corrupted during such operation by another receive message. The additional check, to be performed at the end of the mailbox access, consists in verifying that the associated bit of UMSR has not been set and so no overwrite has occurred; in case such bit is set data have been corrupted and so the message must be discarded. MBx[4], MBx[5]* H'104 + N x 32 11 DART Disable Automatic Retransmission When this bit is set, it disables the automatic retransmission of a message in the event of an error on the CAN bus or an arbitration lost on the CAN bus. When this function is used, the corresponding TXCR bit is automatically set at the start of transmission. When this bit is cleared, the HCAN tries to transmit the message as many times as required until it is successfully transmitted or it is cancelled by the TXCR. Important: This function is not supported by the SH7058. Thus the write value should be 0. The value read as the initial value is not guaranteed. Rev. 3.0, 09/04, page x of xxxviii Item 16.3.2 Message Control Field Page 533534, 537 Revisions (See Manual for Details) MBx[4], MBx[5]* H'104 + N x 32 6 TCT Timer Counter Transfer When this bit is set, a mailbox is set for transmission, and the DLC is set to 4, the TCNTR value, at the SOF, is embedded in the second and third bytes of the message data, instead of MSG_DATA_2 and MSG_DATA_3, and the CYCLE_COUNT in the first byte instead of MSG_DATA_0[3:0] when this mailbox starts transmission. This function will be useful when the HCAN performs a time master role to transmit the time reference message. For example, considering that two HCAN controllers are connected in the same network and that the receiver stores the message in mailbox N, the data format is shown as figure 16.4 depending on the endian setting for the CAN bus (MCR4). Important: This function is not supported by the SH7058. Thus the write value should be 0. The value read as the initial value is not guaranteed. MBx[4], MBx[5]* H'104 + N x 32 5 CBE CAN Bus Error An external fault-tolerant CAN transceiver can be used together with the HCAN module. If the error output pin of the transceiver (normally active low) is connected to the CAN_NERR pin of this LSI, the value of the CAN_NERR pin is stored into this bit at the end of each transmission/reception (if the message is stored). The inverted value of the CAN_NERR pin is set to this bit. If the error output pin is active high, the setting value is not inverted. When this bit is set, it indicates a potential physical error with the CAN bus. As the CAN_NERR value is updated after the transmission or reception in the corresponding mailbox, non-interrupt is dedicated to this function but instead the normal transmit end interrupt (IRR6) and normal receive end interrupt (IRR2) should be considered. Important: This function is not supported by the SH7058. Thus the write value should be 0. The value read as the initial value is not guaranteed. Transmit Clear Enable When this bit is set, message reception in the corresponding mailbox cancels the wait messages in the transmission queue. This action is notified by IRR8 and ABACK. Important: This function is not supported by the SH7058. Thus the write value should be 0. The value read as the initial value is not guaranteed. 4 CLE MBx[6]* H'106 + N x 32 15 TimeStamp Message Reception: to 0 [15:0] During message reception, when the SOF or EOF is detected, ICR1 (input capture register 1) always captures the TCNTR (timer counter register) value or the value of Cycle_Counter + TCNTR[15:4], depending on the value of bit 3 in TMR (Timer mode register), at either SOF or EOF depending on the value in TCR13 (timer control register), and the ICR1 value is stored into the timestamp field of the corresponding mailbox. Important: Capturing at the SOF is not supported by the SH7058. Thus TCR13 should be set to EOF detection mode. Message Transmission: During message transmission, the TCNTR (timer counter register) value or the value of Cycle_Counter + TCNTR[15:4], depending on the value of bit 3 in TMR (timer mode register) is captured when either the TXPR bit or TXACK bit is set depending on the value in TCR12, and the captured value is stored into the timestamp field of the corresponding mailbox. Important: Capturing when the TXPR bit is set is not supported by the SH7058. Activation of the TCNR (timer) causes a problem in the SH7058 (timer usage is prohibited). Therefore, the timestamp function is not supported. The write value should be 0. The value read as the initial value is not guaranteed. Rev. 3.0, 09/04, page xi of xxxviii Item 16.3.4 Local Acceptance Filter Mask (LAFM)/Tx-Trigger Time (TTT) LAFM Field: Page 539, 540 Revisions (See Manual for Details) Table amended MBx[15], MBx[16] H'110 + N x 32 Reserved The write value should be 0. The value read as the initial value is not guaranteed. 14 STDID_LAFM Filter Mask Bits[10:0] for CAN Base to 4 [10:0] ID[10:0] 0: Corresponding bit to CAN base ID set in mailbox is valid 1: Corresponding bit to CAN base ID set in mailbox is invalid 3, 2  Reserved The write value should be 0. The value read as the initial value is not guaranteed. Reserved The write value should be 0. The value read as the initial value is not guaranteed. Reserved The write value should be 0. The value read as the initial value is not guaranteed. 15  Tx-Trigger Time Field: MBx[17], MBx[18]* H'112 + N x 32 15 to 12  7 to  4 16.4.2 Master Control Register_n (MCR_n) (n = 0, 1) 544, 545 Bit 7: Description amended Auto-wake Mode Bit 5: Important: added Important: Usage of sleep mode is limited. Be sure to carefully read section 16.8, Usage Notes. 16.4.3 General Status Register_n (GSR_n) (n = 0, 1) 550 Bit 2: Description amended Message Transmission In Progress Flag Important: added Important: When BRP[7:0] = H'00, TSEG2[2:0] ≠ B'001 Bit table amended Bit: 9 8 IRR9 IRR8 0 R 0 R 16.4.4 HCAN-II_Bit timing Configuration 554 Register n (HCAN-II_BCR0_n, HCANII_BCR1_n)(n = 0, 1) Table 16.5 TSEG1 and TSEG2 Settings 16.4.5 Interrupt Register_n (IRR_n) (n = 5550, 1) 557, 559, 560 Initial Value: R/W: Bit 12: Description amended Wake-up on Bus Activity Interrupt Flag Bit 9: R/W amended R Bit 4: Description amended Receive Overload Warning Interrupt Flag Bit 3: Description amended Transmit Overload Warning Interrupt Flag Bit 1: Description amended Data Frame Received Interrupt Flag Rev. 3.0, 09/04, page xii of xxxviii Item 16.6 Timer Registers Table 16.7 HCAN Timer Registers 16.7.2 HCAN Settings • Reset Sequence Figure 16.7 Reset Sequence Page 581 598 Revisions (See Manual for Details) Address amended Channel 0 : H'D08C Figure and notes amended Reset Sequence Configuration Mode Power-on/software reset*1 Clear MCR[0] Transmission mode Clear all mailboxes*2 (MSG-control, data, timestamp, LAFM ) GSR3 = 0? Yes No Clear IRR[0] HCAN-II is in normal mode Set TXPR to start transmission or stay idle to receive Clear required IMR bits Set LAFM Normal Mode Mailbox setting (STD-ID, EXT-ID, DLC, RTR, IDE, MBC, MBIMR, ATX, NMC, LAFM, message data) Detect 11 recessive bits and join the CAN bus activity Set bit configuration register (BCR) Receive*3 Transmit*3 Notes: 1. A software reset can be performed at any time by setting MCR [0] = 1 4. Deleted 16.7.3 Message Transmission Sequence (1) Event Triggered Transmission • Message Transmission Request Figure 16.8 Transmission Request 16.7.4 Message Transmission Cancellation Sequence Figure 16.10 Transmission Cancellation Sequence 16.7.8 Interrupt Sources Table 16.10 Interrupt Sources 607 602 Figure amended Set ABACK[N] * 2 599 Figure amended HCAN is in normal mode (MBC[x]=0x000 or 0x001 ) Set TXACK[N] . Note added Interrupt Vector HCAN0 HCAN1 Description Data frame reception Remote frame reception Note: * Mailbox 0 only RM0 RM1 Interrupt Flag (IRR Bit) IRR1 IRR2 DMAC Activation HCAN0 Possible* HCAN1 Rev. 3.0, 09/04, page xiii of xxxviii Item 16.7.10 HCAN-II Port Settings Page 609 Revisions (See Manual for Details) Note added Note: * When the HCAN-II is used as a 64-buffer with one channel, care is required. Be sure to carefully read section 16.8, Usage Notes. 16.7.11 CAN Bus Interface Figure 16.16 High-Speed Interface Using HA13721 16.8.4 TXPR Setting during Transmission 610 Newly added 612 Descrioption amended When the HCAN-II is used with the baud rate set to 1 Mbps and the TXPR setting is made during transmission, there are the following limitations on the number of transmit mailboxes (MB) and the number of accesses to mailboxes until transmission is completed. Note that there is no limitation when 500 kbps of baud rate is used. Newly added 16.8.6 Mailbox Access in HCAN Sleep 614, Mode 615 Figure 16.17 HCAN Sleep Mode Flowchart 16.8.7 Notes on Port Settings for 64Buffer HCAN-II with One Channel 17.1.1 Features 616 617 Newly added • High-speed conversion Conversion time: minimum 13.3 µs per channel (when peripheral clock (Pφ) = 20 MHz) 17.1.3 Pin Configuration 620 Description amended The ADTRG0 and ADTRG1 pins are used to provide A/D conversion start timing from off-chip. When the low level of a pulse is applied to one of these pins, A/D0, A/D1, or A/D2 starts conversion. 17.1.4 Register Configuration Table 17.2 A/D Converter Registers 624 Note replaced Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. Rev. 3.0, 09/04, page xiv of xxxviii Item 17.2.3 A/D Control Registers 0 to 2 (ADCR0 to ADCR2) • Bit 7—Trigger Enable (TRGE): Page 631 Revisions (See Manual for Details) Description amended When ATU triggering is selected, clear bit 7 of registers ADTRGR0 to ADTRGR2 to 0. When external triggering is selected, upon input of the low level of a pulse to the ADTRG0 or ADTRG1 pin after TRGE has been set to 1, the A/D converter detects the falling edge of a pulse and sets the ADST bit to 1 in ADCR. The same operation is subsequently performed when 1 is written in the ADST bit by software. External triggering of A/D conversion is only enabled when the ADST bit is cleared to 0. When external triggering is used, the low level input to the ADTRG0 or ADTRG1 pin must be at least 1.5 Pφ clock cycles in width. Table amended CKS = 0: CKS = 1: Peripheral Clock (Pφ) Peripheral Clock (Pφ) = 10 to 20 MHz = 10 MHz Unit Min Typ Max Min Typ Max 10 − 259 − 64 − 17 − 266 6 − 131 − 32 − 9 − 134 States (peripheral clock (Pφ)) 17.4.3 Analog Input Sampling and A/D 644 Conversion Time Table 17.4 A/D Conversion Time (Single Mode) Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV 17.4.4 External Triggering of A/D Conversion 646 Description amended The A/D converter can be activated by input of an external A/D conversion start trigger. To activate the A/D converter with an external trigger, first set the pin functions with the PFC (pin function controller), then set the TRGE bit to 1 in the A/D control register (ADCR), and set the EXTRG bit to 1 in the A/D trigger register (ADTRGR). When a low level is input to the ADTRG pin after these settings have been made, the A/D converter detects the falling edge of a pulse and sets the ADST bit to 1. Figure 17.7 shows the timing for external trigger input. The ADST bit is set to 1 two states after the A/D converter samples the falling edge on the ADTRG pin. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written into the ADST bit by software. 18.5.7 Operation Waveform Examples (C) Hardware Operation 690 Description amended 2. An interrupt is generated if the A/D cycle enable bit (ADCYLR) in the A/D trigger interrupt enable register (ADTIER) is set. Rev. 3.0, 09/04, page xv of xxxviii Item 18.5.7 Operation Waveform Examples (C) Software Operation Figure 18.5 Example of Output Waveform from MTAD PWM Page 691 Revisions (See Manual for Details) Title amended Figure amended ADCYLRx ADGRxA ADGRxB ADDRxA ADDRxB ADGRxA ADGRxB ADTOxA ADTOxB (A) (A) (B) (B) (A) (A) (C) (A) (A) DTSELxA, DTSELxB=0 (On-duty output is selected for PWM.) Note: x = 0 or 1 20.5.1 Initialization 737 Description amended 4. When the AUDSRST bit is set to 1 in the SYSCR1 register (see section 25.2.2) 5. When the MSTOP3 bit is set to 1 in the SYSCR2 register (see section 25.2.3) 21.3.8 Port D IO Register (PDIOR) 22.2.1 Register Configuration Table 22.1 Register Configuration 759 804 Bit table amended Bit 8 : PD8IOR Note amended Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. 22.3.1 Register Configuration Table 22.3 Register Configuration 806 Note amended Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. 22.4.1 Register Configuration Table 22.5 Register Configuration 808 Note amended Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. 22.5.1 Register Configuration Table 22.7 Register Configuration 810 Note amended Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. Rev. 3.0, 09/04, page xvi of xxxviii Item 22.6.1 Register Configuration Table 22.9 Register Configuration Page 813 Revisions (See Manual for Details) Note amended Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. 22.7.1 Register Configuration Table 22.11 Register Configuration 816 Note amended Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. 22.8.1 Register Configuration Table 22.13 Register Configuration 819 Note amended Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. 22.9.1 Register Configuration Table 22.15 Register Configuration 822 Note amended Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. 22.10.1 Register Configuration Table 22.17 Register Configuration 824 Note amended Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. 22.11.1 Register Configuration Table 22.19 Register Configuration 826 Note amended Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. 22.12.1 Register Configuration Table 22.21 Register Configuration 828 Note amended Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. 23.4.1 Registers Table 23.4 (1) Register Configuration 844 Note added 4. The registers except RAMER can be accessed only in bytes, and the access requires four cycles. Since RAMER is in the BSC, when it is accessed in bytes or words, the access requires four cycles, and when it is accessed in longwords, the access requires eight cycles. 23.4.3 Programming/Erasing Interface Parameters (2.2) Flash user branch address setting parameter (FUBRA: general register R5 of CPU) 855 Description amended Store general registers R8 to R15 and the control register GBR. General registers R0 to R7 are available without storing them. Rev. 3.0, 09/04, page xvii of xxxviii Item 23.5.2 User Program Mode (2.3) VBR is cleared to 0 and 1 is written to the SCO bit of FCCS, and then download is executed. 24.1 Overview Page 872 Revisions (See Manual for Details) Description amended If an access by the DMAC or AUD occurs during download, operation cannot be guaranteed. Therefore, access by the DMAC or AUD must not be executed. 941 Description amended On-chip RAM data can always be accessed in one cycle for a read and two states for a write, making the RAM ideal for use as a program area, stack area, or data area, which require high-speed access. 25.1.3 Related Registers Table 25.3 Related Registers 945 Note amended 1. Register access with an internal clock multiplication ratio of 4 requires four internal clock (φ) cycles for SBYCR, and four or five internal clock (φ) cycles for SYSCR1 and SYSCR2. 27.2 DC Characteristics Table 27.2 Correspondence between Power Supply Names and Pins 27.5 Flash Memory Characteristics Table 27.20 Flash Memory Characteristics 959968 1001 Description amended Pin No. (FP-256H) Table amended Item Programming time*1*2*4 Erase time*1*3*5 Reprogramming count Symbol tP tE NWEC Min − − 100 Typ 3 2 − Max 200 20 − Unit ms/128 bytes s/block Times 4. The total reprogramming time (programming time + erasing time) is as follows. 40 s (typ.), reference value: 60 s, 80 s (max.) However, 90% of the values are within the reference value. 5. tP, tE distributes focusing on near the typ. value. A.1 Address Table A.1 Address 1065 Table amended Register AbbreviName ation H'FFFFF70A SYCSR2*1 Bit Names Bit 7 − Bit 3 − Bit 2 − Bit 1 − Bit 0 − Appendix B Pin States Table B.1 Pin States 1080 Table amended AUD Module Standby O Type UBC Pin Name UBCTRG Appendix C Product Lineup Table C.1 SH7058 F-ZTAT Product Lineup 1083 Table amended Product Type Model Name F-ZTAT HD64F7058BF80L SH7058 HD64F7058BF80K HD64F7058BP80L HD64F7058BP80K Mark Model Name 64F7058F80 64F7058F80 64F7058BP80 64F7058BP80 Package 256-pin (FP-256H) 256-pin (FP-256H) 272-pin (BP-272) 272-pin (BP-272) Operating Temperature (Except for W/E of Flash Memory) -40˚C to 105°C -40˚C to 125°C -40˚C to 105°C -40˚C to 125°C Rev. 3.0, 09/04, page xviii of xxxviii Item Appendix D Package Dimensions Figure D.2 SH7058 Package Dimensions (BP-272) Page 1086 Revisions (See Manual for Details) Newly added Rev. 3.0, 09/04, page xix of xxxviii Rev. 3.0, 09/04, page xx of xxxviii Contents Section 1 Overview............................................................................................1 1.1 1.2 1.3 Features ............................................................................................................................. 1 Block Diagram .................................................................................................................. 7 Pin Description.................................................................................................................. 8 1.3.1 Pin Arrangement .................................................................................................. 8 1.3.2 Pin Functions ....................................................................................................... 10 1.3.3 Pin Assignments................................................................................................... 19 Section 2 CPU....................................................................................................29 2.1 Register Configuration...................................................................................................... 29 2.1.1 General Registers (Rn)......................................................................................... 29 2.1.2 Control Registers ................................................................................................. 30 2.1.3 System Registers.................................................................................................. 31 2.1.4 Floating-Point Registers....................................................................................... 32 2.1.5 Floating-Point System Registers .......................................................................... 33 2.1.6 Initial Values of Registers.................................................................................... 33 Data Formats..................................................................................................................... 34 2.2.1 Data Format in Registers...................................................................................... 34 2.2.2 Data Formats in Memory ..................................................................................... 34 2.2.3 Immediate Data Format ....................................................................................... 34 Instruction Features........................................................................................................... 35 2.3.1 RISC-Type Instruction Set................................................................................... 35 2.3.2 Addressing Modes ............................................................................................... 38 2.3.3 Instruction Format................................................................................................ 41 Instruction Set by Classification ....................................................................................... 43 2.4.1 Instruction Set by Classification .......................................................................... 43 Processing States............................................................................................................... 58 2.5.1 State Transitions................................................................................................... 58 2.2 2.3 2.4 2.5 Section 3 Floating-Point Unit (FPU) .................................................................61 3.1 3.2 Overview........................................................................................................................... 61 Floating-Point Registers and Floating-Point System Registers......................................... 62 3.2.1 Floating-Point Register File ................................................................................. 62 3.2.2 Floating-Point Communication Register (FPUL) ................................................ 62 3.2.3 Floating-Point Status/Control Register (FPSCR)................................................. 62 Floating-Point Format ....................................................................................................... 65 3.3.1 Floating-Point Format.......................................................................................... 65 3.3.2 Non-Numbers (NaN) ........................................................................................... 66 3.3.3 Denormalized Number Values............................................................................. 66 Rev. 3.0, 09/04, page xxi of xxxviii 3.3 3.4 3.5 3.6 3.3.4 Other Special Values............................................................................................ 67 Floating-Point Exception Model ....................................................................................... 68 3.4.1 Enable State Exceptions....................................................................................... 68 3.4.2 Disable State Exceptions...................................................................................... 68 3.4.3 FPU Exception Event and Code........................................................................... 68 3.4.4 Floating-Point Data Arrangement in Memory ..................................................... 68 3.4.5 Arithmetic Operations Involving Special Operands ............................................ 68 Synchronization with CPU................................................................................................ 69 Usage Notes ...................................................................................................................... 70 Section 4 Operating Modes ...............................................................................71 4.1 Operating Mode Selection ................................................................................................ 71 Section 5 Clock Pulse Generator (CPG)............................................................73 5.1 Overview........................................................................................................................... 73 5.1.1 Block Diagram ..................................................................................................... 73 5.1.2 Pin Configuration................................................................................................. 74 5.1.3 Related Register ................................................................................................... 74 Frequency Ranges and Clock Selection ............................................................................ 74 5.2.1 Frequency Ranges................................................................................................ 74 5.2.2 Clock Selection .................................................................................................... 75 5.2.3 Notes on Register Access..................................................................................... 76 Clock Source..................................................................................................................... 77 5.3.1 Connecting a Crystal Oscillator ........................................................................... 77 5.3.2 External Clock Input Method............................................................................... 78 Oscillation Stop Detection Function ................................................................................. 79 5.4.1 Overview.............................................................................................................. 79 5.4.2 Settings of Oscillation Stop Detection Function .................................................. 79 5.4.3 Related Register ................................................................................................... 81 5.4.4 Precautions for Performing Oscillation Stop Detection Function........................ 81 Usage Notes ...................................................................................................................... 82 5.2 5.3 5.4 5.5 Section 6 Exception Processing.........................................................................85 6.1 Overview........................................................................................................................... 85 6.1.1 Types of Exception Processing and Priority ........................................................ 85 6.1.2 Exception Processing Operations......................................................................... 86 6.1.3 Exception Processing Vector Table ..................................................................... 87 Resets ................................................................................................................................ 90 6.2.1 Types of Reset ..................................................................................................... 90 6.2.2 Power-On Reset ................................................................................................... 90 6.2.3 Manual Reset ....................................................................................................... 91 Address Errors .................................................................................................................. 92 6.3.1 Address Error Sources ......................................................................................... 92 6.2 6.3 Rev. 3.0, 09/04, page xxii of xxxviii 6.4 6.5 6.6 6.7 6.8 6.3.2 Address Error Exception Processing.................................................................... 93 Interrupts ........................................................................................................................... 93 6.4.1 Interrupt Sources.................................................................................................. 93 6.4.2 Interrupt Priority Level ........................................................................................ 94 6.4.3 Interrupt Exception Processing ............................................................................ 94 Exceptions Triggered by Instructions ............................................................................... 95 6.5.1 Types of Exceptions Triggered by Instructions ................................................... 95 6.5.2 Trap Instructions .................................................................................................. 95 6.5.3 Illegal Slot Instructions ........................................................................................ 96 6.5.4 General Illegal Instructions.................................................................................. 96 6.5.5 Floating-Point Instructions................................................................................... 96 When Exception Sources Are Not Accepted .................................................................... 97 Stack Status after Exception Processing Ends .................................................................. 98 Usage Notes ...................................................................................................................... 99 6.8.1 Value of Stack Pointer (SP) ................................................................................. 99 6.8.2 Value of Vector Base Register (VBR) ................................................................. 99 6.8.3 Address Errors Caused by Stacking of Address Error Exception Processing ...... 99 Section 7 Interrupt Controller (INTC) ...............................................................101 7.1 Overview........................................................................................................................... 101 7.1.1 Features................................................................................................................ 101 7.1.2 Block Diagram ..................................................................................................... 102 7.1.3 Pin Configuration................................................................................................. 103 7.1.4 Register Configuration......................................................................................... 103 Interrupt Sources............................................................................................................... 104 7.2.1 NMI Interrupts ..................................................................................................... 104 7.2.2 User Break Interrupt ............................................................................................ 104 7.2.3 H-UDI Interrupt ................................................................................................... 104 7.2.4 IRQ Interrupts ...................................................................................................... 104 7.2.5 On-Chip Peripheral Module Interrupts ................................................................ 105 7.2.6 Interrupt Exception Vectors and Priority Rankings ............................................. 106 Description of Registers.................................................................................................... 115 7.3.1 Interrupt Priority Registers A–L (IPRA–IPRL) ................................................... 115 7.3.2 Interrupt Control Register (ICR).......................................................................... 117 7.3.3 IRQ Status Register (ISR).................................................................................... 118 Interrupt Operation............................................................................................................ 119 7.4.1 Interrupt Sequence ............................................................................................... 119 7.4.2 Stack after Interrupt Exception Processing .......................................................... 121 Interrupt Response Time................................................................................................... 122 Data Transfer with Interrupt Request Signals ................................................................... 124 7.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources ............... 124 7.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources ................ 124 Rev. 3.0, 09/04, page xxiii of xxxviii 7.2 7.3 7.4 7.5 7.6 Section 8 User Break Controller (UBC)............................................................125 8.1 Overview........................................................................................................................... 125 8.1.1 Features................................................................................................................ 125 8.1.2 Block Diagram ..................................................................................................... 126 8.1.3 Register Configuration......................................................................................... 127 Register Descriptions ........................................................................................................ 127 8.2.1 User Break Address Register (UBAR) ................................................................ 127 8.2.2 User Break Address Mask Register (UBAMR) ................................................... 128 8.2.3 User Break Bus Cycle Register (UBBR) ............................................................. 130 8.2.4 User Break Control Register (UBCR).................................................................. 132 Operation .......................................................................................................................... 133 8.3.1 Flow of the User Break Operation ....................................................................... 133 8.3.2 Break on On-Chip Memory Instruction Fetch Cycle ........................................... 135 8.3.3 Program Counter (PC) Values Saved................................................................... 135 Examples of Use ............................................................................................................... 135 8.4.1 Break on CPU Instruction Fetch Cycle................................................................ 135 8.4.2 Break on CPU Data Access Cycle ....................................................................... 136 8.4.3 Break on DMA Cycle .......................................................................................... 137 Usage Notes ...................................................................................................................... 138 8.5.1 Simultaneous Fetching of Two Instructions ........................................................ 138 8.5.2 Instruction Fetches at Branches ........................................................................... 138 8.5.3 Contention between User Break and Exception Processing ................................ 139 8.5.4 Break at Non-Delay Branch Instruction Jump Destination.................................. 139 8.5.5 User Break Trigger Output .................................................................................. 139 8.5.6 Module Standby ................................................................................................... 140 8.5.7 Internal Clock (φ) Multiplication Ratio and UBCTRG Pulse Width ................... 140 8.2 8.3 8.4 8.5 Section 9 Bus State Controller (BSC) ...............................................................141 9.1 Overview........................................................................................................................... 141 9.1.1 Features................................................................................................................ 141 9.1.2 Block Diagram ..................................................................................................... 142 9.1.3 Pin Configuration................................................................................................. 143 9.1.4 Register Configuration......................................................................................... 143 9.1.5 Address Map ........................................................................................................ 144 Description of Registers.................................................................................................... 146 9.2.1 Bus Control Register 1 (BCR1) ........................................................................... 146 9.2.2 Bus Control Register 2 (BCR2) ........................................................................... 148 9.2.3 Wait Control Register (WCR).............................................................................. 151 9.2.4 RAM Emulation Register (RAMER)................................................................... 152 Accessing External Space ................................................................................................. 154 9.3.1 Basic Timing........................................................................................................ 154 9.3.2 Wait State Control................................................................................................ 155 9.3.3 CS Assert Period Extension ................................................................................. 157 9.2 9.3 Rev. 3.0, 09/04, page xxiv of xxxviii 9.4 9.5 9.6 Waits between Access Cycles ........................................................................................... 158 9.4.1 Prevention of Data Bus Conflicts......................................................................... 158 9.4.2 Simplification of Bus Cycle Start Detection ........................................................ 159 Bus Arbitration.................................................................................................................. 160 Memory Connection Examples......................................................................................... 161 Section 10 Direct Memory Access Controller (DMAC) ...................................163 10.1 Overview........................................................................................................................... 163 10.1.1 Features................................................................................................................ 163 10.1.2 Block Diagram ..................................................................................................... 165 10.1.3 Register Configuration......................................................................................... 166 10.2 Register Descriptions ........................................................................................................ 167 10.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 167 10.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. 168 10.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......................... 169 10.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 170 10.2.5 DMAC Operation Register (DMAOR) ................................................................ 175 10.3 Operation .......................................................................................................................... 177 10.3.1 DMA Transfer Flow ............................................................................................ 177 10.3.2 DMA Transfer Requests ...................................................................................... 179 10.3.3 Channel Priority ................................................................................................... 182 10.3.4 DMA Transfer Types........................................................................................... 182 10.3.5 Dual Address Mode ............................................................................................. 183 10.3.6 Bus Modes ........................................................................................................... 189 10.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category ................................................................................. 190 10.3.8 Bus Mode and Channel Priorities ........................................................................ 191 10.3.9 Source Address Reload Function ......................................................................... 191 10.3.10 DMA Transfer Ending Conditions....................................................................... 192 10.3.11 DMAC Access from CPU.................................................................................... 193 10.4 Examples of Use ............................................................................................................... 194 10.4.1 Example of DMA Transfer between On-Chip SCI and External Memory .......... 194 10.4.2 Example of DMA Transfer between A/D Converter and On-Chip Memory (Address Reload On)............................................................................................ 194 10.4.3 Example of DMA Transfer between External Memory and SCI1 Transmitting Side (Indirect Address on).............................................. 196 10.5 Usage Notes ...................................................................................................................... 198 Section 11 Advanced Timer Unit-II (ATU-II)...................................................199 11.1 Overview........................................................................................................................... 199 11.1.1 Features................................................................................................................ 199 11.1.2 Pin Configuration................................................................................................. 204 11.1.3 Register Configuration......................................................................................... 208 Rev. 3.0, 09/04, page xxv of xxxviii 11.1.4 Block Diagrams ................................................................................................... 218 11.1.5 Inter-Channel and Inter-Module Signal Communication Diagram...................... 228 11.1.6 Prescaler Diagram................................................................................................ 229 11.2 Register Descriptions ........................................................................................................ 230 11.2.1 Timer Start Registers (TSTR) .............................................................................. 230 11.2.2 Prescaler Registers (PSCR).................................................................................. 234 11.2.3 Timer Control Registers (TCR) ........................................................................... 235 11.2.4 Timer I/O Control Registers (TIOR).................................................................... 244 11.2.5 Timer Status Registers (TSR) .............................................................................. 256 11.2.6 Timer Interrupt Enable Registers (TIER) ............................................................ 285 11.2.7 Interval Interrupt Request Registers (ITVRR) ..................................................... 306 11.2.8 Trigger Mode Register (TRGMDR) .................................................................... 311 11.2.9 Timer Mode Register (TMDR) ............................................................................ 312 11.2.10 PWM Mode Register (PMDR) ............................................................................ 313 11.2.11 Down-Count Start Register (DSTR) .................................................................... 315 11.2.12 Timer Connection Register (TCNR).................................................................... 322 11.2.13 One-Shot Pulse Terminate Register (OTR) ......................................................... 327 11.2.14 Reload Enable Register (RLDENR) .................................................................... 331 11.2.15 Free-Running Counters (TCNT) .......................................................................... 332 11.2.16 Down-Counters (DCNT) ..................................................................................... 334 11.2.17 Event Counters (ECNT)...................................................................................... 336 11.2.18 Output Compare Registers (OCR) ....................................................................... 336 11.2.19 Input Capture Registers (ICR) ............................................................................. 337 11.2.20 General Registers (GR)........................................................................................ 338 11.2.21 Offset Base Registers (OSBR) ............................................................................. 341 11.2.22 Cycle Registers (CYLR) ...................................................................................... 341 11.2.23 Buffer Registers (BFR) ........................................................................................ 342 11.2.24 Duty Registers (DTR) .......................................................................................... 343 11.2.25 Reload Register (RLDR)...................................................................................... 344 11.2.26 Channel 10 Registers ........................................................................................... 344 11.3 Operation .......................................................................................................................... 360 11.3.1 Overview.............................................................................................................. 360 11.3.2 Free-Running Counter Operation and Cyclic Counter Operation........................ 367 11.3.3 Compare-Match Function .................................................................................... 368 11.3.4 Input Capture Function ........................................................................................ 369 11.3.5 One-Shot Pulse Function ..................................................................................... 370 11.3.6 Offset One-Shot Pulse Function and Output Cutoff Function ............................. 371 11.3.7 Interval Timer Operation ..................................................................................... 372 11.3.8 Twin-Capture Function........................................................................................ 373 11.3.9 PWM Timer Function .......................................................................................... 374 11.3.10 Channel 3 to 5 PWM Function ............................................................................ 376 11.3.11 Event Count Function and Event Cycle Measurement ........................................ 378 11.3.12 Channel 10 Functions .......................................................................................... 379 Rev. 3.0, 09/04, page xxvi of xxxviii 11.4 Interrupts ........................................................................................................................... 388 11.4.1 Status Flag Setting Timing................................................................................... 388 11.4.2 Status Flag Clearing ............................................................................................. 393 11.5 CPU Interface.................................................................................................................... 395 11.5.1 Registers Requiring 32-Bit Access ...................................................................... 395 11.5.2 Registers Permitting 8-Bit, 16-Bit, or 32-Bit Access........................................... 397 11.5.3 Registers Requiring 16-Bit Access ...................................................................... 398 11.5.4 8-Bit or 16-Bit Accessible Registers.................................................................... 399 11.5.5 Registers Requiring 8-Bit Access ........................................................................ 400 11.6 Sample Setup Procedures.................................................................................................. 400 11.7 Usage Notes ...................................................................................................................... 412 11.8 ATU-II Registers and Pins ................................................................................................ 425 Section 12 Advanced Pulse Controller (APC)...................................................427 12.1 Overview........................................................................................................................... 427 12.1.1 Features................................................................................................................ 427 12.1.2 Block Diagram ..................................................................................................... 428 12.1.3 Pin Configuration................................................................................................. 429 12.1.4 Register Configuration......................................................................................... 429 12.2 Register Descriptions ........................................................................................................ 430 12.2.1 Pulse Output Port Control Register (POPCR)...................................................... 430 12.3 Operation .......................................................................................................................... 431 12.3.1 Overview.............................................................................................................. 431 12.3.2 Advanced Pulse Controller Output Operation ..................................................... 432 12.4 Usage Notes ...................................................................................................................... 435 Section 13 Watchdog Timer (WDT)..................................................................437 13.1 Overview........................................................................................................................... 437 13.1.1 Features................................................................................................................ 437 13.1.2 Block Diagram ..................................................................................................... 438 13.1.3 Pin Configuration................................................................................................. 438 13.1.4 Register Configuration......................................................................................... 439 13.2 Register Descriptions ........................................................................................................ 439 13.2.1 Timer Counter (TCNT)........................................................................................ 439 13.2.2 Timer Control/Status Register (TCSR) ................................................................ 440 13.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 442 13.2.4 Register Access.................................................................................................... 443 13.3 Operation .......................................................................................................................... 444 13.3.1 Watchdog Timer Mode ........................................................................................ 444 13.3.2 Interval Timer Mode ............................................................................................ 446 13.3.3 Timing of Setting the Overflow Flag (OVF) ....................................................... 446 13.3.4 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 447 13.4 Usage Notes ...................................................................................................................... 447 Rev. 3.0, 09/04, page xxvii of xxxviii 13.4.1 13.4.2 13.4.3 13.4.4 13.4.5 13.4.6 13.4.7 TCNT Write and Increment Contention .............................................................. 447 Changing CKS2 to CKS0 Bit Values................................................................... 448 Changing between Watchdog Timer/Interval Timer Modes................................ 448 System Reset by WDTOVF Signal...................................................................... 448 Internal Reset in Watchdog Timer Mode............................................................. 449 Manual Reset in Watchdog Timer ....................................................................... 449 Multiplication Factor for Internal Clock Signal (φ) and Overflow Time............. 449 Section 14 Compare Match Timer (CMT) ........................................................451 14.1 Overview........................................................................................................................... 451 14.1.1 Features................................................................................................................ 451 14.1.2 Block Diagram ..................................................................................................... 452 14.1.3 Register Configuration......................................................................................... 453 14.2 Register Descriptions ........................................................................................................ 454 14.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 454 14.2.2 Compare Match Timer Control/Status Register (CMCSR) ................................. 455 14.2.3 Compare Match Timer Counter (CMCNT) ......................................................... 456 14.2.4 Compare Match Timer Constant Register (CMCOR).......................................... 457 14.3 Operation .......................................................................................................................... 457 14.3.1 Cyclic Count Operation ....................................................................................... 457 14.3.2 CMCNT Count Timing........................................................................................ 458 14.4 Interrupts ........................................................................................................................... 458 14.4.1 Interrupt Sources and DTC Activation ................................................................ 458 14.4.2 Compare Match Flag Set Timing......................................................................... 458 14.4.3 Compare Match Flag Clear Timing ..................................................................... 459 14.5 Usage Notes ...................................................................................................................... 460 14.5.1 Contention between CMCNT Write and Compare Match................................... 460 14.5.2 Contention between CMCNT Word Write and Incrementation .......................... 461 14.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 462 Section 15 Serial Communication Interface (SCI) ............................................463 15.1 Overview........................................................................................................................... 463 15.1.1 Features................................................................................................................ 463 15.1.2 Block Diagram ..................................................................................................... 464 15.1.3 Pin Configuration................................................................................................. 465 15.1.4 Register Configuration......................................................................................... 466 15.2 Register Descriptions ........................................................................................................ 468 15.2.1 Receive Shift Register (RSR) .............................................................................. 468 15.2.2 Receive Data Register (RDR) .............................................................................. 468 15.2.3 Transmit Shift Register (TSR) ............................................................................. 468 15.2.4 Transmit Data Register (TDR)............................................................................. 469 15.2.5 Serial Mode Register (SMR)................................................................................ 469 15.2.6 Serial Control Register (SCR).............................................................................. 472 Rev. 3.0, 09/04, page xxviii of xxxviii 15.2.7 Serial Status Register (SSR) ................................................................................ 476 15.2.8 Bit Rate Register (BRR) ...................................................................................... 480 15.2.9 Serial Direction Control Register (SDCR)........................................................... 486 15.2.10 Inversion of SCK Pin Signal................................................................................ 487 15.3 Operation .......................................................................................................................... 488 15.3.1 Overview.............................................................................................................. 488 15.3.2 Operation in Asynchronous Mode ....................................................................... 490 15.3.3 Multiprocessor Communication........................................................................... 500 15.3.4 Synchronous Operation........................................................................................ 507 15.4 SCI Interrupt Sources and the DMAC .............................................................................. 515 15.5 Usage Notes ...................................................................................................................... 515 15.5.1 TDR Write and TDRE Flag ................................................................................. 515 15.5.2 Simultaneous Multiple Receive Errors ................................................................ 516 15.5.3 Break Detection and Processing (Asynchoronous Mode Only)........................... 516 15.5.4 Sending a Break Signal (Asynchoronous Mode Only) ........................................ 516 15.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only)....... 517 15.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode.... 517 15.5.7 Constraints on DMAC Use .................................................................................. 518 15.5.8 Cautions on Synchronous External Clock Mode ................................................. 518 15.5.9 Caution on Synchronous Internal Clock Mode .................................................... 518 Section 16 Controller Area Network-II (HCAN-II) ..........................................519 16.1 Overview........................................................................................................................... 519 16.1.1 Features................................................................................................................ 519 16.2 Architecture....................................................................................................................... 521 16.2.1 Block Diagram ..................................................................................................... 521 16.2.2 Each Block Function............................................................................................ 522 16.2.3 Pin Configuration................................................................................................. 523 16.2.4 Memory Map ....................................................................................................... 523 16.3 Mailboxes.......................................................................................................................... 526 16.3.1 Mailbox Configuration......................................................................................... 526 16.3.2 Message Control Field ......................................................................................... 529 16.3.3 Message Data Fields ............................................................................................ 538 16.3.4 Local Acceptance Filter Mask (LAFM)/Tx-Trigger Time (TTT)........................ 538 16.4 HCAN Control Registers .................................................................................................. 541 16.4.1 Register Descriptions ........................................................................................... 542 16.4.2 Master Control Register_n (MCR_n) (n = 0, 1)................................................... 542 16.4.3 General Status Register_n (GSR_n) (n = 0, 1)..................................................... 549 16.4.4 HCAN-II_Bit timing Configuration Register n (HCAN-II_BCR0_n, HCAN-II_BCR1_n) (n = 0, 1) ............................................................................. 550 16.4.5 Interrupt Register_n (IRR_n) (n = 0, 1) ............................................................... 555 16.4.6 Interrupt Mask Register_n (IMR_n) (n = 0, 1) .................................................... 561 Rev. 3.0, 09/04, page xxix of xxxviii 16.5 16.6 16.7 16.8 16.4.7 Transmit Error Counter_n (TEC_n) (n = 0, 1)/ Receive Error Counter_n (REC_n) (n = 0, 1) ............................................................................................... 562 HCAN Mailbox Registers ................................................................................................. 563 16.5.1 Transmit Pending Request Register n (TXPR0n, TXPR1n) (n = 0, 1) ................ 566 16.5.2 Transmit Cancel Register n (TXCR1n, TXCR0n) (n = 0, 1) ............................... 569 16.5.3 Transmit Acknowledge Register n (TXACK1n, TXACK0n) (n = 0, 1) .............. 571 16.5.4 Abort Acknowledge Register n (ABACK1n, ABACK0n) (n = 0, 1)................... 573 16.5.5 Data Frame Receive Pending Register n (RXPR1n, RXPR0n) (n = 0, 1)............ 574 16.5.6 Remote Frame Receive Pending Register n (RFPR1n, RFPR0n) (n = 0, 1) ........ 576 16.5.7 Mailbox Interrupt Mask Register n (MBIMR1n, MBIMR0n) (n = 0, 1) ............. 577 16.5.8 Unread Message Status Register n (UMSR1n, UMSR0n) (n = 0, 1) ................... 579 Timer Registers ................................................................................................................. 580 16.6.1 Timer Counter Register n (TCNTRn) (n = 0, 1) .................................................. 582 16.6.2 Timer Control Register_n (TCR_n) (n = 0, 1) ..................................................... 583 16.6.3 Timer Status Register_n (TSR_n) (n = 0, 1) ........................................................ 586 16.6.4 Timer Mode Register_n (TMR_n) (n = 0, 1) ....................................................... 589 16.6.5 Timer Drift Correction Register n (TDCRn) (n = 0, 1)........................................ 590 16.6.6 Local Offset Register n (LOSRn) (n = 0, 1)......................................................... 590 16.6.7 Cycle Counter Register n (CCRn) (n = 0, 1)........................................................ 591 16.6.8 Cycle Counter Double-Buffer Register n (CCR_buf n) (n = 0, 1) ....................... 591 16.6.9 Cycle Maximum Register n (CMAXn) (n = 0, 1) ................................................ 593 16.6.10 Input Capture Registers n (ICR0_cc n, ICR0_buf, ICR0_tm n, ICR1 n) (n = 0, 1) .............................................................................................................. 593 16.6.11 Timer Compare Match Registers n (TCMR0n, TCMR1n, TCMR2n) (n = 0, 1) .............................................................................................................. 595 Operation .......................................................................................................................... 597 16.7.1 Test Mode Settings .............................................................................................. 597 16.7.2 HCAN Settings .................................................................................................... 598 16.7.3 Message Transmission Sequence......................................................................... 599 16.7.4 Message Transmission Cancellation Sequence.................................................... 601 16.7.5 Message Receive Sequence ................................................................................. 603 16.7.6 Reconfiguration of Mailboxes ............................................................................. 604 16.7.7 List of Registers ................................................................................................... 606 16.7.8 Interrupt Sources.................................................................................................. 607 16.7.9 DMAC Interface .................................................................................................. 608 16.7.10 HCAN-II Port Settings......................................................................................... 609 16.7.11 CAN Bus Interface............................................................................................... 610 Usage Notes ...................................................................................................................... 611 16.8.1 TXPR Setting during Reception .......................................................................... 611 16.8.2 Transmit Cancellation Setting immediately after Transmission Setting in Bus Idle............................................................................................................ 611 16.8.3 Failure on Transmit Cancellation at Mailbox 31 ................................................. 612 16.8.4 TXPR Setting during Transmission ..................................................................... 612 Rev. 3.0, 09/04, page xxx of xxxviii 16.8.5 Time Triggered Transmission Setting/Timer Operation Disabled....................... 614 16.8.6 Mailbox Access in HCAN Sleep Mode ............................................................... 614 16.8.7 Notes on Port Settings for 64-Buffer HCAN-II with One Channel ..................... 616 Section 17 A/D Converter..................................................................................617 17.1 Overview........................................................................................................................... 617 17.1.1 Features................................................................................................................ 617 17.1.2 Block Diagram ..................................................................................................... 618 17.1.3 Pin Configuration................................................................................................. 620 17.1.4 Register Configuration......................................................................................... 623 17.2 Register Descriptions ........................................................................................................ 625 17.2.1 A/D Data Registers 0 to 31 (ADDR0 to ADDR31) ............................................. 625 17.2.2 A/D Control/Status Registers 0 and 1 (ADCSR0, ADCSR1) .............................. 626 17.2.3 A/D Control Registers 0 to 2 (ADCR0 to ADCR2)............................................. 631 17.2.4 A/D Control/Status Register 2 (ADCSR2)........................................................... 633 17.2.5 A/D Trigger Registers 0 to 2 (ADTRGR0 to ADTRGR2) .................................. 636 17.3 CPU Interface.................................................................................................................... 637 17.4 Operation .......................................................................................................................... 638 17.4.1 Single Mode......................................................................................................... 638 17.4.2 Scan Mode ........................................................................................................... 640 17.4.3 Analog Input Sampling and A/D Conversion Time............................................. 644 17.4.4 External Triggering of A/D Conversion .............................................................. 646 17.4.5 A/D Converter Activation by ATU-II.................................................................. 647 17.4.6 ADEND Output Pin ............................................................................................. 647 17.5 Interrupt Sources and DMA Transfer Requests ................................................................ 648 17.6 Usage Notes ...................................................................................................................... 648 17.6.1 A/D conversion accuracy definitions ................................................................... 649 Section 18 Multi-Trigger A/D Converter (MTAD) ...........................................651 18.1 Overview........................................................................................................................... 651 18.1.1 Feature ................................................................................................................. 651 18.1.2 Block Diagram ..................................................................................................... 651 18.1.3 Input/Output Pins ................................................................................................. 653 18.1.4 Register Configuration......................................................................................... 653 18.2 Register Descriptions ........................................................................................................ 655 18.2.1 A/D Trigger Control Registers 0 and 1 (ADTCR0 and ADTCR1)...................... 655 18.2.2 A/D Trigger Status Registers 0 and 1 (ADTSR0 and ADTSR1) ......................... 657 18.2.3 A/D Trigger Interrupt Enable Registers 0 and 1 (ADTIER0 and ADTIER1)...... 660 18.2.4 A/D Free-Running Counters (ADCNT0 and ADCNT1) ..................................... 663 18.2.5 A/D General Registers A and B (ADGR0A, ADGR0B, ADGR1A, and ADGR1B) ..................................................................................................... 664 18.2.6 A/D Cycle Registers 0 and 1 (ADCYLR0 and ADCYLR1)................................ 664 Rev. 3.0, 09/04, page xxxi of xxxviii 18.3 18.4 18.5 18.6 18.2.7 A/D Duty Registers A and B (ADDR0A, ADDR0B, ADDR1A, and ADDR1B) ..................................................................................................... 665 Interrupt Interface ............................................................................................................. 666 18.3.1 On-Chip Peripheral Module Interrupts ................................................................ 666 18.3.2 Interrupt Exception Vectors and Priority Rankings ............................................. 666 18.3.3 Interrupt Priority Registers A–L (IPRA–IPRL) ................................................... 675 PFC and I/O Port Interfaces .............................................................................................. 677 18.4.1 PFC Interface ....................................................................................................... 677 18.4.2 Port A Control Registers H and L (PACRH, PACRL) ........................................ 677 18.4.3 I/O Port A............................................................................................................. 681 Operation .......................................................................................................................... 682 18.5.1 Overview.............................................................................................................. 682 18.5.2 PWM Operation ................................................................................................... 683 18.5.3 Compare Match Operation................................................................................... 683 18.5.4 Multi-Trigger A/D Conversion Operation ........................................................... 683 18.5.5 Interrupts.............................................................................................................. 688 18.5.6 Usage Notes ......................................................................................................... 689 18.5.7 Operation Waveform Examples........................................................................... 689 Appendices........................................................................................................................ 692 18.6.1 On-Chip Peripheral Module Registers ................................................................. 692 18.6.2 Pin States.............................................................................................................. 693 18.6.3 AC Characteristics ............................................................................................... 693 Section 19 High-performance User Debug Interface (H-UDI) ........................695 19.1 Overview........................................................................................................................... 695 19.1.1 Features................................................................................................................ 695 19.1.2 H-UDI Block Diagram......................................................................................... 696 19.1.3 Pin Configuration................................................................................................. 697 19.1.4 Register Configuration......................................................................................... 697 19.2 External Signals ................................................................................................................ 698 19.2.1 Test Clock (TCK) ................................................................................................ 698 19.2.2 Test Mode Select (TMS)...................................................................................... 698 19.2.3 Test Data Input (TDI) .......................................................................................... 698 19.2.4 Test Data Output (TDO) ...................................................................................... 698 19.2.5 Test Reset (TRST) ............................................................................................... 699 19.3 Register Descriptions ........................................................................................................ 699 19.3.1 Instruction Register (SDIR) ................................................................................. 699 19.3.2 Status Register (SDSR)........................................................................................ 701 19.3.3 Data Register (SDDR) ......................................................................................... 702 19.3.4 Bypass Register (SDBPR) ................................................................................... 702 19.3.5 Boundary scan register (SDBSR)......................................................................... 702 19.3.6 ID code register (SDIDR) .................................................................................... 719 19.4 Operation .......................................................................................................................... 720 Rev. 3.0, 09/04, page xxxii of xxxviii 19.4.1 TAP Controller .................................................................................................... 720 19.4.2 H-UDI Interrupt and Serial Transfer.................................................................... 721 19.4.3 H-UDI Reset ........................................................................................................ 724 19.5 Boundary Scan .................................................................................................................. 724 19.5.1 Supported Instructions ......................................................................................... 724 19.5.2 Notes on Use........................................................................................................ 725 19.6 Usage Notes ...................................................................................................................... 726 Section 20 Advanced User Debugger (AUD)....................................................729 20.1 Overview........................................................................................................................... 729 20.1.1 Features................................................................................................................ 729 20.1.2 Block Diagram ..................................................................................................... 730 20.2 Pin Configuration.............................................................................................................. 730 20.2.1 Pin Descriptions ................................................................................................... 731 20.3 Branch Trace Mode........................................................................................................... 733 20.3.1 Overview.............................................................................................................. 733 20.3.2 Operation ............................................................................................................. 733 20.4 RAM Monitor Mode ......................................................................................................... 735 20.4.1 Overview.............................................................................................................. 735 20.4.2 Communication Protocol ..................................................................................... 735 20.4.3 Operation ............................................................................................................. 736 20.5 Usage Notes ...................................................................................................................... 737 20.5.1 Initialization ......................................................................................................... 737 20.5.2 Operation in Software Standby Mode.................................................................. 737 Section 21 Pin Function Controller (PFC).........................................................739 21.1 Overview........................................................................................................................... 739 21.2 Register Configuration...................................................................................................... 744 21.3 Register Descriptions ........................................................................................................ 745 21.3.1 Port A IO Register (PAIOR) ................................................................................ 745 21.3.2 Port A Control Registers H and L (PACRH, PACRL) ........................................ 746 21.3.3 Port B IO Register (PBIOR) ................................................................................ 750 21.3.4 Port B Control Registers H and L (PBCRH, PBCRL) ......................................... 751 21.3.5 Port B Invert Register (PBIR) .............................................................................. 756 21.3.6 Port C IO Register (PCIOR) ................................................................................ 757 21.3.7 Port C Control Register (PCCR) .......................................................................... 758 21.3.8 Port D IO Register (PDIOR) ................................................................................ 759 21.3.9 Port D Control Registers H and L (PDCRH, PDCRL) ........................................ 760 21.3.10 Port E IO Register (PEIOR)................................................................................. 764 21.3.11 Port E Control Register (PECR) .......................................................................... 765 21.3.12 Port F IO Register (PFIOR) ................................................................................. 770 21.3.13 Port F Control Registers H and L (PFCRH, PFCRL) .......................................... 771 21.3.14 Port G IO Register (PGIOR) ................................................................................ 776 Rev. 3.0, 09/04, page xxxiii of xxxviii 21.3.15 Port G Control Register (PGCR).......................................................................... 777 21.3.16 Port H IO Register (PHIOR) ................................................................................ 778 21.3.17 Port H Control Register (PHCR).......................................................................... 779 21.3.18 Port J IO Register (PJIOR)................................................................................... 785 21.3.19 Port J Control Registers H and L (PJCRH, PJCRL) ............................................ 786 21.3.20 Port K IO Register (PKIOR) ................................................................................ 790 21.3.21 Port K Control Registers H and L (PKCRH, PKCRL) ........................................ 790 21.3.22 Port K Invert Register (PKIR) ............................................................................. 795 21.3.23 Port L IO Register (PLIOR)................................................................................. 796 21.3.24 Port L Control Registers H and L (PLCRH, PLCRL).......................................... 797 21.3.25 Port L Invert Register (PLIR) .............................................................................. 801 Section 22 I/O Ports (I/O)..................................................................................803 22.1 Overview........................................................................................................................... 803 22.2 Port A................................................................................................................................ 803 22.2.1 Register Configuration......................................................................................... 804 22.2.2 Port A Data Register (PADR) .............................................................................. 804 22.2.3 Port A Port Register (PAPR) ............................................................................... 805 22.3 Port B ................................................................................................................................ 806 22.3.1 Register Configuration......................................................................................... 806 22.3.2 Port B Data Register (PBDR) .............................................................................. 807 22.3.3 Port B Port Register (PBPR) ................................................................................ 808 22.4 Port C ................................................................................................................................ 808 22.4.1 Register Configuration......................................................................................... 808 22.4.2 Port C Data Register (PCDR) .............................................................................. 809 22.5 Port D................................................................................................................................ 810 22.5.1 Register Configuration......................................................................................... 810 22.5.2 Port D Data Register (PDDR) .............................................................................. 811 22.5.3 Port D Port Register (PDPR) ............................................................................... 812 22.6 Port E ................................................................................................................................ 813 22.6.1 Register Configuration......................................................................................... 813 22.6.2 Port E Data Register (PEDR)............................................................................... 814 22.7 Port F................................................................................................................................. 816 22.7.1 Register Configuration......................................................................................... 816 22.7.2 Port F Data Register (PFDR) ............................................................................... 817 22.8 Port G................................................................................................................................ 818 22.8.1 Register Configuration......................................................................................... 819 22.8.2 Port G Data Register (PGDR) .............................................................................. 819 22.9 Port H................................................................................................................................ 821 22.9.1 Register Configuration......................................................................................... 822 22.9.2 Port H Data Register (PHDR) .............................................................................. 822 22.10 Port J ................................................................................................................................. 823 22.10.1 Register Configuration......................................................................................... 824 Rev. 3.0, 09/04, page xxxiv of xxxviii 22.10.2 Port J Data Register (PJDR)................................................................................. 824 22.10.3 Port J Port Register (PJPR) .................................................................................. 825 22.11 Port K................................................................................................................................ 826 22.11.1 Register Configuration......................................................................................... 826 22.11.2 Port K Data Register (PKDR) .............................................................................. 827 22.12 Port L ................................................................................................................................ 828 22.12.1 Register Configuration......................................................................................... 828 22.12.2 Port L Data Register (PLDR)............................................................................... 829 22.12.3 Port L Port Register (PLPR) ................................................................................ 830 22.13 POD (Port Output Disable) Control.................................................................................. 831 Section 23 ROM ................................................................................................833 23.1 Features ............................................................................................................................. 833 23.2 Overview........................................................................................................................... 835 23.2.1 Block Diagram ..................................................................................................... 835 23.2.2 Operating Mode ................................................................................................... 836 23.2.3 Mode Comparison................................................................................................ 838 23.2.4 Flash Memory Configuration............................................................................... 839 23.2.5 Block Division ..................................................................................................... 840 23.2.6 Programming/Erasing Interface ........................................................................... 841 23.3 Pin Configuration.............................................................................................................. 843 23.4 Register Configuration...................................................................................................... 843 23.4.1 Registers............................................................................................................... 843 23.4.2 Programming/Erasing Interface Registers ........................................................... 846 23.4.3 Programming/Erasing Interface Parameters ........................................................ 851 23.4.4 RAM Emulation Register (RAMER)................................................................... 862 23.5 On-Board Programming Mode ......................................................................................... 864 23.5.1 Boot Mode ........................................................................................................... 864 23.5.2 User Program Mode............................................................................................. 868 23.5.3 User Boot Mode................................................................................................... 878 23.6 Protection .......................................................................................................................... 881 23.6.1 Hardware Protection ............................................................................................ 881 23.6.2 Software Protection.............................................................................................. 882 23.6.3 Error Protection.................................................................................................... 883 23.7 Flash Memory Emulation in RAM ................................................................................... 885 23.8 Usage Notes ...................................................................................................................... 888 23.8.1 Switching between User MAT and User Boot MAT........................................... 888 23.8.2 Interrupts during Programming/Erasing .............................................................. 889 23.8.3 Other Notes .......................................................................................................... 893 23.9 Programmer Mode ............................................................................................................ 894 23.9.1 Pin Arrangement of Socket Adapter .................................................................... 895 23.9.2 Programmer Mode Operation .............................................................................. 897 23.9.3 Memory-Read Mode............................................................................................ 898 Rev. 3.0, 09/04, page xxxv of xxxviii 23.9.4 Auto-Program Mode ............................................................................................ 899 23.9.5 Auto-Erase Mode................................................................................................. 899 23.9.6 Status-Read Mode................................................................................................ 900 23.9.7 Status Polling ....................................................................................................... 900 23.9.8 Time Taken in Transition to Programmer Mode ................................................. 901 23.9.9 Notes on Programming in Programmer Mode ..................................................... 901 23.10 Further Information........................................................................................................... 901 23.10.1 Serial Communication Interface Specification for Boot Mode............................ 901 23.10.2 AC Characteristics and Timing in Programmer Mode......................................... 927 23.10.3 Storable Area for Procedure Program and Programming Data .......................... 933 Section 24 RAM ................................................................................................941 24.1 Overview........................................................................................................................... 941 24.2 Operation .......................................................................................................................... 942 Section 25 Power-Down State...........................................................................943 25.1 Overview........................................................................................................................... 943 25.1.1 Power-Down States.............................................................................................. 943 25.1.2 Pin Configuration................................................................................................. 945 25.1.3 Related Registers ................................................................................................. 945 25.2 Register Descriptions ........................................................................................................ 945 25.2.1 Standby Control Register (SBYCR) .................................................................... 945 25.2.2 System Control Register 1 (SYSCR1) ................................................................. 946 25.2.3 System Control Register 2 (SYSCR2) ................................................................. 947 25.2.4 Notes on Register Access..................................................................................... 949 25.3 Hardware Standby Mode .................................................................................................. 949 25.3.1 Transition to Hardware Standby Mode ................................................................ 949 25.3.2 Canceling Hardware Standby Mode .................................................................... 949 25.3.3 Hardware Standby Mode Timing......................................................................... 950 25.4 Software Standby Mode.................................................................................................... 950 25.4.1 Transition to Software Standby Mode ................................................................. 950 25.4.2 Canceling Software Standby Mode...................................................................... 950 25.4.3 Software Standby Mode Application Example.................................................... 952 25.5 Sleep Mode ....................................................................................................................... 953 25.5.1 Transition to Sleep Mode..................................................................................... 953 25.5.2 Canceling Sleep Mode ......................................................................................... 953 Section 26 Reliability ........................................................................................955 26.1 Reliability.......................................................................................................................... 955 Section 27 Electrical Characteristics .................................................................957 27.1 Absolute Maximum Ratings ............................................................................................. 957 27.2 DC Characteristics ............................................................................................................ 959 Rev. 3.0, 09/04, page xxxvi of xxxviii 27.3 AC Characteristics ............................................................................................................ 975 27.3.1 Timing for swicthing the power supply on/off .................................................... 975 27.3.2 Clock timing ........................................................................................................ 976 27.3.3 Control Signal Timing ......................................................................................... 978 27.3.4 Bus Timing .......................................................................................................... 982 27.3.5 Advanced Timer Unit Timing and Advance Pulse Controller Timing ................ 986 27.3.6 I/O Port Timing.................................................................................................... 987 27.3.7 Watchdog Timer Timing...................................................................................... 988 27.3.8 Serial Communication Interface Timing.............................................................. 989 27.3.9 HCAN Timing ..................................................................................................... 991 27.3.10 A/D Converter Timing......................................................................................... 992 27.3.11 H-UDI Timing ..................................................................................................... 994 27.3.12 AUD Timing ........................................................................................................ 996 27.3.13 UBC Trigger Timing............................................................................................ 998 27.3.14 Measuring Conditions for AC Characteristics ..................................................... 999 27.4 A/D Converter Characteristics ........................................................................................ 1000 27.5 Flash Memory Characteristics......................................................................................... 1001 27.6 Usage Note...................................................................................................................... 1002 27.6.1 Notes on Connecting External Capacitor for Current Stabilization ................... 1002 27.6.2 Notes on Mode Pin Input ................................................................................... 1002 Appendix A On-chip peripheral module Registers.........................................1005 A.1 A.2 Address ........................................................................................................................... 1005 Register States in Reset and Power-Down States ........................................................... 1073 Appendix B Pin States ....................................................................................1079 Appendix C Product Lineup ...........................................................................1083 Appendix D Package Dimensions ..................................................................1085 Rev. 3.0, 09/04, page xxxvii of xxxviii Rev. 3.0, 09/04, page xxxviii of xxxviii Section 1 Overview 1.1 Features The SH7058 is a single-chip RISC microcontroller that integrates a RISC CPU core using an original Renesas architecture with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Basic instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance/high-functionality systems even for applications such as real-time control, which could not previously be handled by microcontrollers because of their high-speed processing requirements. In addition, the SH7058 includes on-chip peripheral functions necessary for system configuration, such as a floating-point unit (FPU) , ROM , RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), controller area network-II (HCAN-II), A/D converter, interrupt controller (INTC), and I/O ports. ROM and SRAM can be directly connected by means of an external memory access support function, greatly reducing system cost. On-chip ROM is available as flash memory in the F-ZTAT™* (Flexible Zero Turn Around Time) version. The flash memory can be programmed with a programmer that supports SH7058 programming, and can also be programmed and erased by software. Since the programming/erasing control program is included as firmware, programming and erasing can be performed by calling this program with a user program. This enables the chip to be programmed by the user while mounted on a board. The features of the SH7058 are summarized in table 1.1. Note: * F-ZTAT is a trademark of Renesas Technology, Corp. Rev. 3.0, 09/04, page 1 of 1086 Table 1.1 Item CPU SH7058 Features Features • • • • Maximum operating frequency: 80 MHz Original Renesas SH-2E CPU 32-bit internal architecture General register machine    • • • Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers Instruction execution time: Basic instructions execute in one state (12.5 ns/instruction at 80 MHz operation) Address space: Architecture supports 4 Gbytes Five-stage pipeline Operating modes   Single-chip mode 8/16-bit bus expanded mode • Mode with on-chip ROM • Mode with no on-chip ROM Operating states • • Processing states  Reset state  Program execution state  Exception handling state  Bus-released state  Power-down state • Power-down state  Sleep mode  Software standby mode  Hardware standby mode  Module standby Multiplier • 32 × 32 → 64 multiply operations executed in two to four cycles 32 × 32 + 64 → 64 multiply-and-accumulate operations executed in two to four cycles Rev. 3.0, 09/04, page 2 of 1086 Table 1.1 Item SH7058 Features (cont) Features • • • • • • • • • • • SuperH architecture coprocessor Supports single-precision floating-point operations Supports a subset of the data types specified by the IEEE standard Supports invalid operation and division-by-zero exception detection (subset of IEEE standard) Supports Round to Zero as the rounding mode (subset of IEEE standard) Sixteen 32-bit floating-point data registers Supports the FMAC instruction (multiply-and-accumulate instruction) Supports the FDIV instruction (divide instruction) Supports the FLDI0/FLDI1 instructions (constant 0/1 load instructions) Instruction delay time: Two cycles for each of FMAC, FADD, FSUB, and FMUL instructions Execution pitch: One cycle for each of FMAC, FADD, FSUB, and FMUL instructions On-chip clock pulse generator (maximum operating frequency: 80 MHz) Independent generation of CPU system clock and peripheral clock for peripheral modules On-chip clock-multiplication PLL circuit (×4, ×8) Internal clock frequency range: 5 to 10 MHz Nine external interrupt pins (NMI, IRQ0 to IRQ7) 117 internal interrupt sources (ATU-II × 75, SCI × 20, DMAC × 4, A/D × 5, WDT × 1, UBC × 1, CMT × 2, HCAN-II × 8, H-UDI × 1) • 16 programmable priority levels Requests an interrupt when the CPU or DMAC generates a bus cycle with specified conditions (interrupt can also be masked) Trigger pulse output (UBCTRG) on break condition  Selection of trigger pulse width (φ ×1, ×4, ×8, ×16) • Simplifies configuration of an on-chip debugger Floating-point unit (FPU) Clock pulse generator (CPG/PLL) • • • • Interrupt controller (INTC) • • User break controller (UBC) • • Rev. 3.0, 09/04, page 3 of 1086 Table 1.1 Item SH7058 Features (cont) Features • • • Supports external memory access (SRAM and ROM directly connectable)  8/16-bit bus space 3.3 V bus interface 16 MB address space divided into four areas, with the following parameters settable for each area:  Bus size (8 or 16 bits)  Number of wait cycles  Chip select signals (CS0 to CS3) output for each area • • • Wait cycles can be inserted using an external WAIT signal External access in minimum of two cycles Provision for idle cycle insertion to prevent bus collisions DMA transfer possible for the following devices:  External memory, on-chip memory, on-chip peripheral modules (excluding DMAC, UBC, BSC) • • • DMA transfer requests by on-chip modules  SCI, A/D converter, ATU-II, HCAN-II Cycle steal or burst mode transfer Dual address mode  Direct transfer mode  Indirect transfer mode (channel 3 only) • • Address reload function (channel 2 only) Transfer data width: Byte/word/longword Maximum 65 inputs or outputs can be processed  Four 32-bit input capture inputs  Thirty 16-bit input capture inputs/output compare outputs  Sixteen 16-bit one-shot pulse outputs  Eight 16-bit PWM outputs  Six 8-bit event counters  One gap detection function • I/O pin output inversion function Maximum eight pulse outputs on reception of ATU-II (channel 11) compare-match signal Bus state controller (BSC) Direct memory access controller (DMAC) (4 channels) • Advanced timer unit-II (ATU-II) • Advanced pulse controller (APC) • Rev. 3.0, 09/04, page 4 of 1086 Table 1.1 Item SH7058 Features (cont) Features • • • Can be switched between watchdog timer and interval timer function Internal reset, external signal, or interrupt generated by counter overflow Two kinds of internal reset  Power-on reset  Manual reset Watchdog timer (WDT) (1 channel) Compare-match timer (CMT) (2 channels) Serial communication interface (SCI) (5 channels) • • Selection of 4 counter input clocks A compare-match interrupt can be requested independently for each channel Selection of asynchronous or synchronous mode Simultaneous transmission/reception (full-duplex) capability Serial data communication possible between multiple processors (asynchronous mode) Clock inversion function LSB-/MSB-first selection function for transmission CAN version: Bosch 2.0B active compatible Buffer size (per channel): Transmit/receive × 31, receive-only × 1 Receive message filtering capability Thirty-two channels Three sample-and-hold circuits  Independent operation of 12 channels × 2 and 8 channels × 1 Selection of two conversion modes  Single conversion mode  Scan mode • Continuous scan mode • Single-cycle scan mode • • • • • Controller area network-II (HCAN-II) (2 channels) A/D converter • • • • • • • • • Multi-trigger A/D (MTAD) • Can be activated by external trigger or ATU-II compare-match 10-bit resolution Accuracy: ±2 LSB While performing conversion on the specified channels in scan mode, A/D conversion on the channels for which conversion has been requested can be performed prior to the other channels when a compare match occurs with respect to the timer in the A/D converter Rev. 3.0, 09/04, page 5 of 1086 Table 1.1 Item SH7058 Features (cont) Features • Compliant with IEEE1149.1  Five test signals (TCK, TDI, TD0, TMS, and TRST)  TAP controller  Instruction register  Data register  Bypass register • Test mode compliant with IEEE1149.1  Standard instructions: BYPASS, SAMPLE/PRELOAD, EXTEST  Optional instructions: CLAMP, HIGHZ, IDCODE • H-UDI interrupt  H-UDI interrupt request to INTC High-performance user debug interface (H-UDI) Advanced user debugger (AUD) • • Eight dedicated pins RAM monitor mode  Data input/output frequency: 10 MHz or less  Possible to read/write to a module connected to the internal/external bus • I/O ports (including timer I/O pins, address and data buses) • • • • • Branch address output mode Dual-function input/output pins: 149 Schmitt input pins: NMI, IRQn, RES, HSTBY, FWE, TCLK, IC, IC/OC, SCK, ADTRG Input port protection 1-MB flash memory 1-MB divided into 16 blocks  Small blocks:  Medium block:  Large blocks: 4 kB × 8 96 kB × 1 128 kB × 7 ROM • • • RAM emulation function (using 4 kB small block) Programming/erasing control program included as firmware Flash memory programming methods  Boot mode  User program mode  User boot mode  Programmer mode Rev. 3.0, 09/04, page 6 of 1086 Table 1.1 Item RAM SH7058 Features (cont) Features • 48 kB SRAM 1.2 Block Diagram PF13/CS3 PF12/CS2 PF11/CS1 PF10/CS0 PF5/A21/POD PF4/A20 PF3/A19 PF2/A18 PF1/A17 PF0/A16 PE15/A15 PE14/A14 PE13/A13 PE12/A12 PE11/A11 PE10/A10 PE9/A9 PE8/A8 PE7/A7 PE6/A6 PE5/A5 PE4/A4 PE3/A3 PE2/A2 PE1/A1 PE0/A0 PF15/BREQ PF14/BACK PF8/WAIT PF9/RD PF7/WRH PF6/WRL RES HSTBY FWE MD2 MD1 MD0 NMI WDTOVF Port/control signals Port/address signals ROM (flash) 1 MB RAM 48 kB Port/data signals CK EXTAL XTAL PLLVCC PLLVSS PLLCAP Vcc (×8) PVcc1 (×4) PVcc2 (×6) VCL(×3) Vss (×21) AVref (×2) AVcc (×2) AVss (×2) AN31–0 AUDRST AUDMD AUDATA3–0 AUDCK AUDSYNC TMS TRST TDI TDO TCK PD0/TIO1A PD1/TIO1B PD2/TIO1C PD3/TIO1D PD4/TIO1E PD5/TIO1F PD6/TIO1G PD7/TIO1H PD8/PULS0 PD9/PULS1 PD10/PULS2 PD11/PULS3 PD12/PULS4 PD13/PULS6/HTxD0/HTxD1 PL0/TI10 PL1/TIO11A/IRQ6 PL2/TIO11B/IRQ7 PL3/TCLKB PL4/ADTRG0 PL5/ADTRG1 PL6/ADEND PL7/SCK2 PL8/SCK3 PL9/SCK4/IRQ5 PL10/HTxD0/HTxD1/HTxD0 & HTxD1 PL11/HRxD0/HRxD1/HRxD0 & HRxD1 PL12/IRQ4 PL13/IRQOUT Clock pulse generator CPU FPU Multiplier Interrupt controller BSC DMAC (4 channels) PH15/D15 PH14/D14 PH13/D13 PH12/D12 PH11/D11 PH10/D10 PH9/D9 PH8/D8 PH7/D7 PH6/D6 PH5/D5 PH4/D4 PH3/D3 PH2/D2 PH1/D1 PH0/D0 SCI (5 channels) HCAN II (2 channels) CMT (2 channels) AUD H-UDI ATU-II A/D converter WDT Port PK15/TO8P PK14/TO8O PK13/TO8N PK12/TO8M PK11/TO8L PK10/TO8K PK9/TO8J PK8/TO8I PK7/TO8H PK6/TO8G PK5/TO8F PK4/TO8E PK3/TO8D PK2/TO8C PK1/TO8B PK0/TO8A Port : Peripheral address bus (9 bits) : Peripheral data bus (16 bits) : Internal address bus (32 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) PA0/TI0A PA1/TI0B PA2/TI0C PA3/TI0D PA4/TIO3A PA5/TIO3B PA6/TIO3C PA7/TIO3D PA8/TIO4A/ADTO0A PA9/TIO4B/ADTO0B PA10/TIO4C/ADTO1A PA11/TIO4D/ADTO1B PA12/TIO5A PA13/TIO5B PA14/TxD0 PA15/RxD0 PB0/TO6A PB1/TO6B PB2/TO6C PB3/TO6D PB4/TO7A/TO8A PB5/TO7B/TO8B PB6/TO7C/TO8C PB7/TO7D/TO8D PB8/TxD3/TO8E PB9/RxD3/TO8F PB10/TxD4/HTxD0/TO8G PB11/RxD4/HRxD0/TO8H PB12/TCLKA/UBCTRG PB13/SCK0 PB14/SCK1/TCLKB/TI10 PB15/PULS5/SCK2 PC0/TxD1 PC1/RxD1 PC2/TxD2 PC3/RxD2 PC4/IRQ0 PG0/PULS7/HRxD0/HRxD1 PG1/IRQ1 PG2/IRQ2/ADEND PG3/IRQ3/ADTRG0 PJ15/TI9F PJ14/TI9E PJ13/TI9D PJ12/TI9C PJ11/TI9B PJ10/TI9A PJ9/TIO5D PJ8/TIO5C PJ7/TIO2H PJ6/TIO2G PJ5/TIO2F PJ4/TIO2E PJ3/TIO2D PJ2/TIO2C PJ1/TIO2B PJ0/TIO2A Port Figure 1.1 Block Diagram Rev. 3.0, 09/04, page 7 of 1086 Port 1.3 1.3.1 TDI TDO TCK Vcc Vss AUDMD AUDATA0 AUDATA1 AUDATA2 AUDATA3 AUDCK Vss PK8/TO8I PK9/TO8J PK10/TO8K PK11/TO8L PK12/TO8M PK13/TO8N PVcc2 PK14/TO8O Vss PK15/TO8P PL0/TI10 PL1/TIO11A/ PL2/TIO11B/ PL3/TCLKB PL4/ PL5/ PL6/ADEND PL7/SCK2 PL8/SCK3 VCL PL9/SCK4/ Vss PL10/HTxD0/HTxD1/HTxD0 & HTxD1 PL11/HRxD0/HRxD1/HRxD0 & HRxD1 PL12/ PL13/ TMS Pin Arrangement Pin Description PVcc2 PD0/TIO1A Vss PD1/TIO1B PD2/TIO1C PD3/TIO1D PD4/TIO1E PD5/TIO1F PD6/TIO1G PD7/TIO1H 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 INDEX Rev. 3.0, 09/04, page 8 of 1086 FP-256H (Top view) Figure 1.2 Pin Assignments (FP-256H) MD0 PLLVcc PLLCAP PLLVss PH0/D0 PH1/D1 PH2/D2 PH3/D3 PH4/D4 PH5/D5 PH6/D6 PVcc1 PH7/D7 Vss PH8/D8 PH9/D9 Vcc PH10/D10 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 PVcc2 PA1/TI0B Vss PA0/TI0A AN31 AN30 AVss AVref AVcc AN29 AN28 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 AN15 AN14 AN13 AVcc AVref AVss AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Vss NMI PVcc1 PH15/D15 PH14/D14 PH13/D13 PH12/D12 PH11/D11 Vss PD8/PULS0 PD9/PULS1 PD10/PULS2 PD11/PULS3 PD12/PULS4 PD13//PULS6/HTxD0/HTxD1 PE0/A0 PE1/A1 PE2/A2 PE3/A3 Vcc PE4/A4 Vss PE5/A5 PE6/A6 PE7/A7 PE8/A8 PE9/A9 PE10/A10 PVcc1 PE11/A11 Vss PE12/A12 PE13/A13 PE14/A14 PE15/A15 PF0/A16 PF1/A17 PF2/A18 VCL PF3/A19 Vss PF4/A20 PF5/A21/ PF6/ PF7/ PF8/ PF9/ PVcc1 PF10/ Vss PF11/ PF12/ PF13/ PF14/ PF15/ Vss CK Vcc MD2 EXTAL Vcc XTAL Vss MD1 FWE PK7/TO8H Vcc PK6/TO8G PK5/TO8F PK4/TO8E PK3/TO8D PK2/TO8C PK1/TO8B Vss PK0/TO8A PVcc2 PJ15/TI9F PJ14/TI9E PJ13/TI9D PJ12/TI9C PJ11/TI9B PJ10/TI9A Vcc PJ9/TIO5D Vss PJ8/TIO5C PJ7/TIO2H PJ6/TIO2G PJ5/TIO2F PJ4/TIO2E PJ3/TIO2D PJ2/TIO2C PJ1/TIO2B PJ0/TIO2A / PG3/ Vss /ADEND PG2/ PVcc2 PG1/ PG0/PULS7/HRxD0/HRxD1 PC4/ PC3/RxD2 PC2/TxD2 PC1/RxD1 PC0/TxD1 PB15/PULS5/SCK2 Vss PB14/SCK1/TCLKB/TI10 VCL PB13/SCK0 PB12/TCLKA/ PB11/RxD4/HRxD0/TO8H PB10/TxD4/HTxD0/TO8G PB9/RxD3/TO8F PB8/TxD3/TO8E PB7/TO7D/TO8D PB6/TO7C/TO8C PB5/TO7B/TO8B PB4/TO7A/TO8A Vss PB3/TO6D PVcc2 PB2/TO6C PB1/TO6B PB0/TO6A PA15/RxD0 PA14/TxD0 PA13/TIO5B Vss PA12/TIO5A Vcc PA11/TIO4D/ADTO1B PA10/TIO4C/ADTO1A PA9/TIO4B/ADTO0B PA8/TIO4A/ADTO0A PA7/TIO3D PA6/TIO3C PA5/TIO3B PA4/TIO3A PA3/TI0D PA2/TI0C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 20 PH5 /D5 PH13/D13 PH15/D15 NMI AN3 AN5 AN8 AVss AVcc AN15 AN16 AN19 AN21 AN24 AVcc AVss PA2/TI0C PA4/TIO3A 19 PH2/D2 PH4/D4 PH7/D7 PH12/D12 PH14/D14 Vss AN2 AN7 AN9 AVref AN13 AN18 AN22 AN23 AN28 AVref PVcc2 PA3/TI0D PA6/TIO3C PA7/TIO3D 18 PLLVss PH1/D1 PH3/D3 PH8/D8 PH11/D11 PVcc1 AN1 AN4 AN10 AN11 AN14 AN20 AN26 AN27 AN31 Vss PA0/TI0A PA5/TIO3B PA8/TIO4A/ PA10/TIO4C/ ADTO0A ADTO1A 17 PLLVcc PLLCAP PH6/D6 PH9/D9 PH10/D10 Vcc Vss AN0 AN6 AN12 AN17 AN25 AN29 AN30 WDTOVF PA1/TI0B PA9/TIO4B/ PA11/TIO4D/ ADTO1B ADTO0B PA12/ TIO5A PA14/ TxD0 16 15 HSTBY RES MD0 PVcc1 Vcc Vss PA13/ TIO5B PA15/ RxD0 XTAL Vss MD1 PH0/D0 PB0/TO6A PVcc2 PB1/TO6B PB2/TO6C 14 EXTAL Vcc MD2 FWE PB4/TO7A/ PB5/TO7B/ PB6/TO7C PB3/TO6D /TO8C TO8A TO8B 13 CK Vss PF15/ BREQ Vcc PB9/RxD3 PB10/TxD4/ PB8/TxD3 PB7/TO7D/ HTxD0/TO8G /TO8E TO8D /TO8F 12 PF11/CS1 PF13/CS3 PF12/CS2 PF14/ BACK Vss Vss Vss Vss PB15/PULS5/ PB11/RxD4/ PB12/TCLKA/ SCK2 HRxD0/TO8H UBCTRG PB13/ SCK0 11 PF10/CS0 PF9/RD PVcc1 Vss Vss Vss Vss Vss PC1/RxD1 PC0/TxD1 Vss VCL 10 PF8/WAIT PF6/WRL PF5/A21/ POD PF7/WRH Vss Vss Vss Vss PC3/RxD2 PC4/IRQ0 PB14/SCK1/ PC2TxD2 TCLKB/TI10 9 Vss VCL PF4/A20 PF3/A19 Vss Vss Vss Vss Vss PVcc2 PG2/IRQ2/ PG0/PULS7/ ADEND HRxD0/HRxD1 8 PF2/A18 PF1/A17 PF0/A16 PE15/A15 PG3/IRQ3/ PJ3/TIO2D PJ2/TIO2C ADTRG0 PG1/IRQ1 7 PE14/A14 PE13/A13 PE12/A12 Vss PJ8/TIO5C PJ7/TIO2H PJ4/TIO2E PJ0/TIO2A 6 PE11/A11 PE10/A10 PVcc1 PE9/A9 Vcc Vss PJ6/TIO2G PJ1/TIO2B 5 PE8/A8 PE7/A7 PE6/A6 Vcc Vss PVcc2 PJ11/TI9B PJ5/TIO2F 4 PE5/A5 PE4/A4 PE2/A2 PE1/A1 PD8/ PULS0 PD6/ TIO1G PD1/ TIO1B PVcc2 Vss TDI PL8/SCK3 PL4/ ADTRG0 PL0/TI10 Vss PK8/TO8I PK6/ TO8G Vcc PJ15/TI9F PJ13/TI9D PJ9/TIO5D 3 PE3/A3 PE0/A0 PD11/ PULS3 PD9/ PULS1 PD7/ TIO1H PD5/ TIO1F Vss AUDMD Vcc TMS PL9/SCK4/ PL7/SCK2 IRQ5 PL3/ TCLKB PVcc2 PK12/ TO8M PK10/ TO8K PK9/TO8J PK1/TO8B PJ14/TI9E PJ10/TI9A 2 PD13/PULS6/ HTxD0/HTxD1 PD12/ PULS4 PD10/ PULS2 PD4/ TIO1E PD2/ TIO1C AUDSYNC AUDATA2 AUDRST TCK PL12/ IRQ4 PL11/HRxD0/ HRxD1/ HRxD0&HRxD1 PL10/HTxD0/ HTxD1/ HTxD0&HTxD1 VCL PL6/ ADEND PL1/TIO11A/ IRQ6 PK14/ TO8O PK11/ TO8L PK7/TO8H PK3/TO8D PK2/TO8C PJ12/TI9C 1 A PD3/ TIO1D PD0/ TIO1A AUDCK AUDATA3 AUDATA1 AUDATA0 TDO TRST PL13/ IRQOUT Vss PL5 / ADTRG1 PL2/TIO11B/ IRQ7 PK15/ TO8P PK13/ TO8N PK5/TO8F PK4/TO8E PK0/TO8A B C D E F G H J K L M N P R T U V W Y Index TOP View Figure 1.3 Pin Assignments Rev. 3.0, 09/04, page 9 of 1086 1.3.2 Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Pin No. Type Power supply Symbol VCC FP-256H 11, 49, 52, 75, 139, 187, 203, 237 BP-272 I/O Name Function Input D5, D13, B14, F17, U16, U6, U4, J3 Power supply Power supply for chipinternal and system ports (RES, MD2–MD0, FWE, HSTBY, NMI, CK, EXTAL, XTAL, H-UDI port). Connect all VCC pins to the system power supply. The chip will not operate if there are any open pins. Port power supply 1 Power supply for bus ports (ports E, F, and H). Connect all PVCC1 pins to the system bus power supply. The chip will not operate if there are any open pins. Power supply for peripheral module ports (ports A, B, C, D, G, J, K, and L, the AUD port, and WDTOVF). Connect all PVCC2 pins to the system peripheral module power supply. The chip will not operate if there are any open pins. PVCC1 20, 39, 70, C6, V11, 83 D16, F18 Input PVCC2 128, 148, 172, 194, 212, 247 U19, V15, Input V9, V5, P3, H4 Port power supply 2 VCL 30, 161, 225 B9, Y11, M2 Input Internal step- Pins for connection to a down power capacitor used for stablizing the voltage of the internal supply step-down power supply. Connect VSS to this pin through a (0.33,0.47)-µF capacitor. The capacitor should be located near the pin. Do not connect an external power supply to the pin. Rev. 3.0, 09/04, page 10 of 1086 Table 1.2 Pin Functions (cont) Pin No. Type Power supply Symbol VSS FP-256H 13, 22, 32, 41, 47, 54, 72, 77, 85, 126, 141, 150, 163, 174, 185, 196, 205, 214, 227, 239, 249 56 BP-272 I/O Name Ground Function For connection to ground. Connect all VSS pins to the system ground. The chip will not operate if there are any open pins. Input A9, B13, B15, D7, D11, F19, G3, G17, J4, J9-12, K9-12, L9-12, M1, M9-12, P4, T18, U5, U9, V6, V16, W11 D14 Input Flash memory FWE Flash write enable Connected to ground in normal operation. Apply VCC during on-board programming. Clock PLLVCC 60 A17 Input PLL power supply On-chip PLL oscillator power supply. For power supply connection, see section 5, Clock Pulse Generator (CPG). PLLVSS 62 A18 Input PLL ground On-chip PLL oscillator ground. For power supply connection, see section 5, Clock Pulse Generator (CPG). PLLCAP 61 B17 Input PLL capacitance On-chip PLL oscillator external capacitance connection pin. For external capacitance connection, see section 5, Clock Pulse Generator (CPG). EXTAL 51 A14 Input External clock For connection to a crystal resonator. An external clock source can also be connected to the EXTAL pin. Crystal For connection to a crystal resonator. Supplies the peripheral clock to peripheral devices. XTAL CK 53 48 A15 A13 Input Output Peripheral clock Rev. 3.0, 09/04, page 11 of 1086 Table 1.2 Pin Functions (cont) Pin No. Type Symbol FP-256H 58 124 46 45 BP-272 B16 R17 C13 D12 I/O Input Name Power-on reset Function Executes a power-on reset when driven low. System control RES WDTOVF BREQ BACK Output Watchdog WDT overflow output signal. timer overflow Input Bus request Driven low when an external device requests the bus. Output Bus request Indicates that the bus has acknowledge been granted to an external device. The device that output the BREQ signal recognizes that the bus has been acquired when it receives the BACK signal. Input Mode setting These pins determine the operating mode. Do not change the input values during operation. Hardware standby When driven low, this pin forces a transition to hardware standby mode. Operating mode control MD0 to MD2 59, 55, 50 C16, C15, C14 HSTBY 57 A16 Input Interrupts NMI 84 E20 Input Nonmaskable Nonmaskable interrupt interrupt request pin. Acceptance on the rising edge or falling edge can be selected. IRQ0 to IRQ7 169, 171, 173, 175, 230, 226, 217, 218 231 V10, Y8, Input W9, W8, K2, L3, P2, P1 Interrupt requests 0 to 7 Maskable interrupt request pins. Level input or edge input can be selected. Indicates that an interrupt has been generated. Enables interrupt generation to be recognized in the busreleased state. IRQOUT K1 Output Interrupt request output Rev. 3.0, 09/04, page 12 of 1086 Table 1.2 Pin Functions (cont) Pin No. Type Address bus Symbol A0–A21 FP-256H 7–10, 12, 14–19, 21, 23–29, 31, 33, 34 BP-272 I/O Name Function Address output pins. B3, D4, C4, Output Address bus A3, B4, A4, C5, B5, A5, D6, B6, A6, C7, B7, A7, D8, C8, B8, A8, D9, C9, C10 D15, B18, A19, C18, B19, B20, C17, C19, D18, D17, E17, E18, D19, C20, E19, D20 A11, A12, C12, B12 B11 D10 B10 A10 Input/ output Data bus Data bus D0–D15 63–69, 71, 73, 74, 76, 78–82 16-bit bidirectional data bus pins. Bus control CS0–CS3 RD WRH WRL WAIT 40, 42–44 38 36 35 37 Output Chip select 0 to 3 Output Read Output Upper write Output Lower write Input Wait Chip select signals for external memory or devices. Indicates reading from an external device. Indicates writing of the upper 8 bits of external data. Indicates writing of the lower 8 bits of external data. Input for wait cycle insertion in bus cycles during external space access. ATU-II counter external clock Input pins. Channel 0 input capture input pins. Advanced timer unit-II (ATU-II) TCLKA TCLKB TI0A–TI0D 159, 162, 219 125, 127, 129, 130 248, 250–256 W12, Y10, N3 U18, T17, V20, V19 Input Input ATU-II timer clock input ATU-II input capture (channel 0) TIO1A– TIO1H C1, G4, E2, Input/ B1, D2, F3, output F4, E3 Y7, Y6, V8, Input/ U8, W7, Y5, output W6, V7 ATU-II input Channel 1 input capture capture/output input/output compare output pins. compare (channel 1) ATU-II input Channel 2 input capture capture/output input/output compare output pins. compare (channel 2) TIO2A– TIO2H 176–183 Rev. 3.0, 09/04, page 13 of 1086 Table 1.2 Pin Functions (cont) Pin No. Type Advanced timer unit-II (ATU-II) Symbol TIO3A– TIO3D FP-256H 131–134 BP-272 W20, V18, W19, Y19 I/O Input/ output Name Function ATU-II input Channel 3 input capture capture/output input/output compare/PWM output pins. compare/ PWM output (channel 3) ATU-II input Channel 4 input capture capture/output input/output compare/PWM output pins. compare/ PWM output (channel 4) ATU-II input Channel 5 input capture capture/output input/output compare/PWM output pins. compare/ PWM output (channel 5) Channel 6 PWM output pins. TIO4A– TIO4D 135–138 W18, U17, Y18, V17 Input/ output TIO5A– TIO5D 140, 142, 184, 186 W17, W16, U7, Y4 Input/ output TO6A–TO6D 145–147, 149 TO7A–TO7D 151–154 U15, W15, Y15, Y14 U14, V14, W14, Y13 Output ATU-II PWM output (channel 6) Output ATU-II PWM output (channel 7) Channel 7 PWM output pins. TO8A– TO8P 151–158, 195, 197–202, 204, 206–211, 213, 215 Output ATU-II Channel 8 down-counter U14, V14, one-shot pulse one-shot pulse output pins. W14, Y13, (channel 8) W13, U13, V13, V12, W1, V3, W2, V2, V1, U1, T4, U2, R4, U3, T3, T2, R3, T1, R2, R1 Y3, W5, Y2, Input W4, W3, V4 Y10, N4 Input ATU-II event input (channel 9) ATU-II multiplied clock generation (channel 10) Channel 9 event counter input pins. Channel 10 external clock input pin. TI9A– TI9F TI10 188–193 162, 216 Rev. 3.0, 09/04, page 14 of 1086 Table 1.2 Pin Functions (cont) Pin No. Type Advanced timer unit-II (ATU-II) Symbol TIO11A, TIO11B FP-256H 217, 218 BP-272 P2, P1 I/O Input/ output Name Function ATU-II input Channel 11 input capture capture/output input/output compare output pins. compare Advanced PULS0– pulse controller PULS7 (APC) Serial TxD0– communication TxD4 interface (SCI) RxD0– RxD4 SCK0– SCK4 Controller area HTxD0, network-II HTxD1 (HCAN-II) HRxD0, HRxD1 A/D converter AVCC AVSS AVref 1–6, 164, 170 143, 165, 167, 155, 157 144, 166, 168, 156, 158 160, 162, 223, 224, 226, 164 E4, D3, C2, Output APC pulse APC pulse output pins. C3, B2, A2, outputs 0 to 7 U12, Y9 Y17, V11, W10, W13, V13 Y16, U11, U10, U13, V12 Output Transmit data SCI0 to SCI4 transmit data output pins. (channels 0 to 4) Input Receive data SCI0 to SCI4 receive data (channels input pins. 0 to 4) Serial clock (channels 0 to 4) SCI0 to SCI4 clock input/output pins. Input/ Y12, Y10, M3, L4, L3, output U12 157, 228, 6 V13, L1, A2 Output Transmit data CAN bus transmit data output pins. 158, 229, 170 101, 119 99, 121 100, 120 V12, L2, Y9 input K20, T20 J20, U20 K19, T19 Input Input Input Receive data CAN bus receive data input pins. Analog power A/D converter power supply. supply Analog ground A/D converter power supply. Analog Analog reference power reference supply input pins. power supply Analog input Analog signal input pins. AN0–AN31 86–98, 102–118, 122, 123 H17, G18, G19, F20, H18, G20, J17, H19, H20, J19, J18, K18, K17, L19, L18, L20, M20, L17, M19, N20, M18, P20, N19, P19, R20, M17, N18, P18, R19, N17, P17, R18 Input Rev. 3.0, 09/04, page 15 of 1086 Table 1.2 Pin Functions (cont) Pin No. Type A/D converter Symbol ADTRG0, ADTRG1 ADEND ADTO0A ADTO0B ADTO1A ADTO1B FP-256H 175, 220, 221 173, 222 135 136 137 138 159 236 232 234 235 BP-272 I/O Name A/D conversion trigger input Function External trigger input pins for starting A/D conversion. W8, M4, N1 Input W9, N2 W18 U17 Y18 V17 W12 J2 K3 K4 H1 Output ADEND output A/D2 channel 31 conversion timing monitor output pins. Output PWM output Output PWM output Output PWM output Output PWM output PWM output pin for multitrigger A/D conversion. PWM output pin for multitrigger A/D conversion. PWM output pin for multitrigger A/D conversion. PWM output pin for multitrigger A/D conversion. User break UBCTRG controller (UBC) Highperformance user debug interface (H-UDI) TCK TMS TDI TDO Output User break UBC condition match trigger trigger output output pin. Input Input Input Test clock Test mode select Test data input Test clock input pin. Test mode select signal input pin. Instruction/data serial input pin. Instruction/data serial output pin. Output Test data output TRST Advanced user debugger (AUD) 233 J1 Input Test reset AUD data Initialization signal input pin. Branch trace mode: Branch destination address output pins. RAM monitor mode: Monitor address input / data input/output pins. AUDATA0– 241–244 AUDATA3 G1, F1, G2, Input/ E1 output AUDRST AUDMD 238 240 H2 H3 Input Input AUD reset AUD mode Reset signal input pin. Mode select signal input pin. Branch trace mode: Low RAM monitor mode: High Rev. 3.0, 09/04, page 16 of 1086 Table 1.2 Pin Functions (cont) Pin No. Type Advanced user debugger (AUD) Symbol AUDCK FP-256H 245 BP-272 D1 I/O Input/ output Name AUD clock Function Branch trace mode: Serial clock output pin. RAM monitor mode: Serial clock input pin. AUDSYNC 246 F2 Input/ output AUD Branch trace mode: Data synchronizatio start position identification n signal signal output pin. RAM monitor mode: Data start position identification signal input pin. I/O ports POD 34 C10 Input Port output disable Port A Input pin for port pin drive control when general port is set for output. General input/output port pins. Input or output can be specified bit by bit. PA0–PA15 125, 127, 129–138, 140, 142–144 U18, T17, V20, V19, W20, V18, W19, Y19, W18, U17, Y18, V17, W17, W16, Y17, Y16 U15, W15, Y15, Y14, U14, V14, W14, Y13, W13, U13, V13, V12, W12, Y12, Y10, U12 V11, U11, W10, U10, V10 Input/ output PB0–PB15 145–147, 149, 151–160, 162, 164 Input/ output Port B General input/output port pins. Input or output can be specified bit by bit. PC0–PC4 165–169 Input/ output Port C General input/output port pins. Input or output can be specified bit by bit. PD0–PD13 248, 250–256, 1–6 C1, G4, E2, Input/ B1, D2, F3, output F4, E3, E4, D3, C2, C3, B2, A2 Port D General input/output port pins. Input or output can be specified bit by bit. Rev. 3.0, 09/04, page 17 of 1086 Table 1.2 Pin Functions (cont) Pin No. Type I/O ports Symbol PE0–PE15 FP-256H BP-272 I/O Name Port E Function General input/output port pins. Input or output can be specified bit by bit. B3, D4, C4, Input/ 7–10, 12, 14–19, 21, A3, B4, A4, output C5, B5, A5, 23–26 D6, B6, A6, C7, B7, A7, D8 27–29, 31, C8, B8, A8, Input/ 33–38, 40, D9, C9, C10, output 42–46 B10, D10, A10, B11, A11, A12, C12, B12, D12, C13 170, 171, 173, 175 Y9, Y8, W9, Input/ W8 output PF0–PF15 Port F General input/output port pins. Input or output can be specified bit by bit. PG0–PG3 Port G General input/output port pins. Input or output can be specified bit by bit. PH0–PH15 63–69, 71, D15, B18, 73, 74, 76, A19, C18, 78–82 B19, B20, C17, C19, D18, D17, E17, E18, D19, C20, E19, D20 PJ0–PJ15 176–184, 186, 188–193 Input/ output Port H General input/output port pins. Input or output can be specified bit by bit. Y7, Y6, V8, Input/ U8, W7, Y5, output W6, V7, U7, Y4, Y3, W5, Y2, W4, W3, V4 W1, V3, W2, Input/ V2, V1, U1, output T4, U2, R4, U3, T3, T2, R3, T1, R2, R1 N4, P2, P1, Input/ N3, M4, N1, output N2, M3, L4, L3, L1, L2, K2, K1 Port J General input/output port pins. Input or output can be specified bit by bit. PK0–PK15 195, 197–202, 204, 206–211, 213, 215 216–224, 226, 228–231 Port K General input/output port pins. Input or output can be specified bit by bit. PL0–PL13 Port L General input/output port pins. Input or output can be specified bit by bit. Rev. 3.0, 09/04, page 18 of 1086 1.3.3 Table 1.3 Pin Assignments Pin Assignments Pin No. FP-256H BP-272 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 E4 D3 C2 C3 B2 A2 B3 D4 C4 A3 D5 B4 * A4 C5 B5 A5 D6 B6 C6 A6 * C7 B7 A7 D8 C8 B8 A8 B9 MCU Mode PD8/PULS0 PD9/PULS1 PD10/PULS2 PD11/PULS3 PD12/PULS4 PD13/PULS6/HTxD0/HTxD1 PE0/A0 PE1/A1 PE2/A2 PE3/A3 Vcc PE4/A4 Vss PE5/A5 PE6/A6 PE7/A7 PE8/A8 PE9/A9 PE10/A10 PVcc1 PE11/A11 Vss PE12/A12 PE13/A13 PE14/A14 PE15/A15 PF0/A16 PF1/A17 PF2/A18 VCL Programmer Mode NC NC NC NC NC NC A0 A1 A2 A3 Vcc A4 Vss A5 A6 A7 A8 A9 A10 Vcc A11 Vss A12 A13 A14 A15 A16 A17 A18 VCL Rev. 3.0, 09/04, page 19 of 1086 Table 1.3 Pin Assignments (cont) Pin No. FP-256H BP-272 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 D9 * C9 C10 B10 D10 A10 B11 C11 A11 * A12 C12 B12 D12 C13 * A13 D13 C14 A14 B14 A15 * C15 D14 A16 B16 C16 A17 B17 MCU Mode PF3/A19 Vss PF4/A20 PF5/A21/POD PF6/WRL PF7/WRH PF8/WAIT PF9/RD PVcc1 PF10/CS0 Vss PF11/CS1 PF12/CS2 PF13/CS3 PF14/BACK PF15/BREQ Vss CK Vcc MD2 EXTAL Vcc XTAL Vss MD1 FWE HSTBY RES MD0 PLLVcc PLLCAP Programmer Mode A19 Vss NC NC NC NC Vcc NC Vcc NC Vss Vcc Vcc Vss NC Vcc Vss NC Vcc Vss EXTAL Vcc XTAL Vss Vcc FWE Vcc RES Vcc PLLVcc PLLCAP Rev. 3.0, 09/04, page 20 of 1086 Table 1.3 Pin Assignments (cont) Pin No. FP-256H BP-272 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 A18 D15 B18 A19 C18 B19 B20 C17 D16 C19 * D18 D17 F17 E17 * E18 D19 C20 E19 D20 F18 E20 * H17 G18 G19 F20 H18 G20 J17 MCU Mode PLLVss PH0/D0 PH1/D1 PH2/D2 PH3/D3 PH4/D4 PH5/D5 PH6/D6 PVcc1 PH7/D7 Vss PH8/D8 PH9/D9 Vcc PH10/D10 Vss PH11/D11 PH12/D12 PH13/D13 PH14/D14 PH15/D15 PVcc1 NMI Vss AN0 AN1 AN2 AN3 AN4 AN5 AN6 Programmer Mode PLLVss D0 D1 D2 D3 D4 D5 D6 Vcc D7 Vss NC NC Vcc NC Vss NC NC NC NC NC Vcc Vss Vss NC NC NC NC NC NC NC Rev. 3.0, 09/04, page 21 of 1086 Table 1.3 Pin Assignments (cont) Pin No. FP-256H BP-272 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 H19 H20 J19 J18 K18 K17 J20 K19 K20 L19 L18 L20 M20 L17 M19 N20 M18 P20 N19 P19 R20 M17 N18 P18 R19 N17 T20 T19 U20 P17 R18 MCU Mode AN7 AN8 AN9 AN10 AN11 AN12 AVss AVref AVcc AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AVcc AVref AVss AN30 AN31 Programmer Mode NC NC NC NC NC NC Vss Vcc Vcc NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Vcc Vcc Vss NC NC Rev. 3.0, 09/04, page 22 of 1086 Table 1.3 Pin Assignments (cont) Pin No. FP-256H BP-272 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 R17 U18 * T17 U19 V20 V19 W20 V18 W19 Y19 W18 U17 Y18 V17 U16 W17 * W16 Y17 Y16 U15 W15 Y15 V15 Y14 * U14 V14 W14 Y13 MCU Mode WDTOVF PA0/TI0A Vss PA1/TI0B PVcc2 PA2/TI0C PA3/TI0D PA4/TIO3A PA5/TIO3B PA6/TIO3C PA7/TIO3D PA8/TIO4A/ADTO0A PA9/TIO4B/ADTO0B PA10/TIO4C/ADTO1A PA11/TIO4D/ADTO1B Vcc PA12/TIO5A Vss PA13/TIO5B PA14/TxD0 PA15/RxD0 PB0/TO6A PB1/TO6B PB2/TO6C PVcc2 PB3/TO6D Vss PB4/TO7A/TO8A PB5/TO7B/TO8B PB6/TO7C/TO8C PB7/TO7D/TO8D Programmer Mode NC NC Vss NC Vcc NC NC NC NC NC NC NC NC NC NC Vcc NC Vss NC NC NC NC NC NC Vcc NC Vss NC NC NC NC Rev. 3.0, 09/04, page 23 of 1086 Table 1.3 Pin Assignments (cont) Pin No. FP-256H BP-272 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 W13 U13 V13 V12 W12 Y12 Y11 Y10 * U12 V11 U11 W10 U10 V10 Y9 Y8 V9 W9 * W8 Y7 Y6 V8 U8 W7 Y5 W6 V7 U7 * MCU Mode PB8/TxD3/TO8E PB9/RxD3/TO8F PB10/TxD4/HTxD0/TO8G PB11/RxD4/HRxD0/TO8H PB12/TCLKA/UBCTRG PB13/SCK0 VCL PB14/SCK1/TCLKB/TI10 Vss PB15/PULS5/SCK2 PC0/TxD1 PC1/RxD1 PC2/TxD2 PC3/RxD2 PC4/IRQ0 PG0/PULS7/HRxD0/HRxD1 PG1/IRQ1 PVcc2 PG2/IRQ2/ADEND Vss PG3/IRQ3/ADTRG0 PJ0/TIO2A PJ1/TIO2B PJ2/TIO2C PJ3/TIO2D PJ4/TIO2E PJ5/TIO2F PJ6/TIO2G PJ7/TIO2H PJ8/TIO5C Vss Programmer Mode NC NC NC NC NC NC VCL NC Vss NC NC NC NC NC NC NC NC Vcc NC Vss NC NC NC NC NC NC NC NC NC NC Vss Rev. 3.0, 09/04, page 24 of 1086 Table 1.3 Pin Assignments (cont) Pin No. FP-256H BP-272 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 Y4 U6 Y3 W5 Y2 W4 W3 V4 V5 W1 * V3 W2 V2 V1 U1 T4 U4 U2 * R4 U3 T3 T2 R3 T1 P3 R2 * R1 N4 MCU Mode PJ9/TIO5D Vcc PJ10/TI9A PJ11/TI9B PJ12/TI9C PJ13/TI9D PJ14/TI9E PJ15/TI9F PVcc2 PK0/TO8A Vss PK1/TO8B PK2/TO8C PK3/TO8D PK4/TO8E PK5/TO8F PK6/TO8G Vcc PK7/TO8H Vss PK8/TO8I PK9/TO8J PK10/TO8K PK11/TO8L PK12/TO8M PK13/TO8N PVcc2 PK14/TO8O Vss PK15/TO8P PL0/TI10 Programmer Mode NC Vcc NC NC NC NC NC NC Vcc NC Vss NC NC NC NC NC NC Vcc NC Vss NC NC NC NC NC NC Vcc NC Vss NC NC Rev. 3.0, 09/04, page 25 of 1086 Table 1.3 Pin Assignments (cont) Pin No. FP-256H BP-272 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 P2 P1 N3 M4 N1 N2 M3 L4 M2 L3 * L1 L2 K2 K1 K3 J1 K4 H1 J2 J3 H2 * H3 G1 F1 G2 E1 D1 F2 H4 MCU Mode PL1/TIO11A/IRQ6 PL2/TIO11B/IRQ7 PL3/TCLKB PL4/ADTRG0 PL5/ADTRG1 PL6/ADEND PL7/SCK2 PL8/SCK3 VCL PL9/SCK4/IRQ5 Vss PL10/HTxD0/HTxD1/HTxD0 & HTxD1 PL12/IRQ4 PL13/IRQOUT TMS TRST TDI TDO TCK Vcc AUDRST Vss AUDMD AUDATA0 AUDATA1 AUDATA2 AUDATA3 AUDCK AUDSYNC PVcc2 Programmer Mode NC CE NC NC NC NC NC NC VCL WE Vss NC OE NC NC NC NC NC NC Vcc NC Vss NC NC NC NC NC NC NC Vcc PL11/HRxD0/HRxD1/HRxD0 & HRxD1 NC Rev. 3.0, 09/04, page 26 of 1086 Table 1.3 Pin Assignments (cont) Pin No. FP-256H BP-272 248 249 250 251 252 253 254 255 256 — — — — * C1 * G4 E2 B1 D2 F3 F4 E3 A1 A20 Y1 Y20 MCU Mode PD0/TIO1A Vss PD1/TIO1B PD2/TIO1C PD3/TIO1D PD4/TIO1E PD5/TIO1F PD6/TIO1G PD7/TIO1H NC NC NC NC Programmer Mode NC Vss NC NC NC NC NC NC NC NC NC NC NC Vss is connected in the board. Rev. 3.0, 09/04, page 27 of 1086 Rev. 3.0, 09/04, page 28 of 1086 Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. In addition, the FPU has eighteen internal registers: sixteen 32-bit floating-point registers and two 32-bit floating-point system registers. 2.1.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0–R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15. Figure 2.1 shows the general registers. 31 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 Notes: 1. R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. R15 functions as a hardware stack pointer (SP) during exception processing. 0 2. Figure 2.1 General Registers Rev. 3.0, 09/04, page 29 of 1086 2.1.2 Control Registers The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception processing vector area (including interrupts). Figure 2.2 shows the control registers. 31 SR 9 8 7 6 5 4 32 1 0 M Q I3 I2 I1 I0 ST SR: Status register T bit: The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, CLRT, and FCMP/cond instructions use the T bit to indicate true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, and ROTCL instructions also use the T bit to indicate carry/borrow or overflow/underflow. S bit: Used by the MAC instruction. Reserved bits. These bits always read 0. The write value should always be 0. Bits I3–I0: Interrupt mask bits. M and Q bits: Used by the DIV0U, DIV0S, and DIV1 instructions. Reserved bits. These bits always read 0. The write value should always be 0. 31 GBR 0 Global base register (GBR): Indicates the base address of the indirect GBR addressing mode. The indirect GBR addressing mode is used in data transfer for on-chip peripheral module register areas and in logic operations. 0 VBR Vector base register (VBR): Stores the base address of the exception processing vector area. 31 Figure 2.2 Control Register Configuration Rev. 3.0, 09/04, page 30 of 1086 2.1.3 System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The multiplyand-accumulate registers store the results of multiply-and-accumulate operations. The procedure register stores the return address from a subroutine procedure. The program counter stores program addresses to control the flow of the processing. Figure 2.3 shows the system registers. 31 MACH MACL 0 Multiply-and-accumulate (MAC) registers high and low (MACH, MACL): Store the results of multiply-and-accumulate operations. Procedure register (PR): Stores the return address from a subroutine procedure. Program counter (PC): Indicates the fourth byte (second instruction) after the current instruction. 31 PR 0 31 PC 0 Figure 2.3 System Register Configuration Rev. 3.0, 09/04, page 31 of 1086 2.1.4 Floating-Point Registers There are sixteen 32-bit floating-point registers, designated FR0 to FR15, which are used by floating-point instructions. FR0 functions as the index register for the FMAC instruction. These registers are incorporated into the floating-point unit (FPU). For details, see section 3, FloatingPoint Unit (FPU). 31 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 0 FR0 functions as the index register for the FMAC instruction. Figure 2.4 Floating-Point Registers Rev. 3.0, 09/04, page 32 of 1086 2.1.5 Floating-Point System Registers There are two 32-bit floating-point system registers: the floating-point communication register (FPUL) and the floating-point status/control register (FPSCR). FPUL is used for communication between the CPU and the floating-point unit (FPU). FPSCR indicates and stores status/control information relating to FPU exceptions. These registers are incorporated into the floating-point unit (FPU). For details, see section 3, Floating-Point Unit (FPU). 31 FPUL 31 FPSCR 0 FPSCR: Floating-point status/control register Indicates and stores status/control information relating to FPU exceptions. 0 FPUL: Floating-point communication register Used for communication between the CPU and the FPU. Figure 2.5 Floating-Point System Registers 2.1.6 Initial Values of Registers Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers Register R0–R14 R15 (SP) Control registers SR GBR VBR System registers MACH, MACL, PR PC Floating-point registers Floating-point system registers FR0–FR15 FPUL FPSCR Initial Value Undefined Value of the stack pointer in the vector address table Bits I3–I0 are 1111 (H'F), reserved bits are 0, and other bits are undefined Undefined H'00000000 Undefined Value of the program counter in the vector address table Undefined Undefined H'00040001 Classification General registers Rev. 3.0, 09/04, page 33 of 1086 2.2 2.2.1 Data Formats Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure 2.6). 31 Longword 0 Figure 2.6 Data Format in Registers 2.2.2 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address, but an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, referred to by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register (figure 2.7). Address m + 1 Address m 31 Byte Address 2n Address 4n 23 Byte Word Longword 15 Byte Address m + 3 7 Byte Word 0 Address m + 2 Figure 2.7 Data Formats in Memory 2.2.3 Immediate Data Format Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. Rev. 3.0, 09/04, page 34 of 1086 Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. 2.3 2.3.1 Instruction Features RISC-Type Instruction Set All instructions are RISC type. This section details their functions. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using the pipeline system. Instructions are executed in 25 ns at 40 MHz. Data Length: Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations. It also is handled as longword data (table 2.2). Table 2.2 Sign Extension of Word Data Description Example of Conventional CPU ADD.W #H'1234,R0 SH7058 CPU MOV.W ADD .DATA.W @(disp,PC),R1 Data is sign-extended to 32 bits, and R1 becomes R1,R0 H'00001234. It is next ......... operated upon by an ADD instruction. H'1234 Note: @(disp, PC) accesses the immediate data. Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction following the delayed branch instruction. There are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions. Rev. 3.0, 09/04, page 35 of 1086 Table 2.3 Delayed Branch Instructions Description Executes the ADD before branching to TRGET. Example of Conventional CPU ADD.W BRA R1,R0 TRGET SH7058 CPU BRA ADD TRGET R1,R0 Multiply/Multiply-and-Accumulate Operations: 16-bit × 16-bit → 32-bit multiply operations are executed in one to two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiply-and-accumulate operations are executed in two to three cycles. 32-bit × 32-bit → 64-bit multiply and 32-bit × 32bit + 64bit → 64-bit multiply-and-accumulate operations are executed in two to four cycles. T Bit: The T bit in the status register changes according to the result of the comparison, and in turn is the condition (true/false) that determines if the program will branch. The number of instructions that change the T bit is kept to a minimum to improve the processing speed (table 2.4). Table 2.4 T Bit Description Example of Conventional CPU R1,R0 TRGET0 TRGET1 #1,R0 TRGET SH7058 CPU CMP/GE BT BF ADD CMP/EQ BT R1,R0 TRGET0 TRGET1 #1,R0 #0,R0 TRGET T bit is set when R0 ≥ R1. The CMP.W program branches to TRGET0 BGE when R0 ≥ R1 and to BLT TRGET1 when R0 < R1. T bit is not changed by ADD. SUB.W T bit is set when R0 = 0. The BEQ program branches if R0 = 0. Immediate Data: Byte (8-bit) immediate data resides in the instruction code. Word or longword immediate data is not input via instruction codes but is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement (table 2.5). Rev. 3.0, 09/04, page 36 of 1086 Table 2.5 Immediate Data Accessing SH7058 CPU MOV MOV.W #H'12,R0 @(disp,PC),R0 ................. .DATA.W H'1234 @(disp,PC),R0 ................. .DATA.L H'12345678 MOV.L #H'12345678,R0 Example of Conventional CPU MOV.B MOV.W #H'12,R0 #H'1234,R0 Classification 8-bit immediate 16-bit immediate 32-bit immediate MOV.L Note: @(disp, PC) accesses the immediate data. Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect register addressing mode (table 2.6). Table 2.6 Absolute Address Accessing SH7058 CPU MOV.L MOV.B @(disp,PC),R1 @R1,R0 .................. .DATA.L H'12345678 Note: @(disp,PC) accesses the immediate data. Example of Conventional CPU MOV.B @H'12345678,R0 Classification Absolute address 16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the preexisting displacement value is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect indexed register addressing mode (table 2.7). Table 2.7 Displacement Accessing SH7058 CPU @(disp,PC),R0 @(R0,R1),R2 .................. .DATA.W H'1234 Note: @(disp,PC) accesses the immediate data. Example of Conventional CPU MOV.W @(H'1234,R1),R2 Classification 16-bit displacement MOV.W MOV.W Rev. 3.0, 09/04, page 37 of 1086 2.3.2 Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Mode Direct register addressing Indirect register addressing Post-increment indirect register addressing Addressing Modes and Effective Addresses Instruction Format Effective Address Calculation Rn @Rn Equation The effective address is register Rn. (The operand — is the contents of register Rn.) The effective address is the contents of register Rn. Rn Rn @Rn+ Rn Rn (After the instruction executes) Byte: Rn + 1 → Rn Word: Rn + 2 → Rn Longword: Rn + 4 → Rn Byte: Rn – 1 → Rn Word: Rn – 2 → Rn Longword: Rn – 4 → Rn (Instruction executed with Rn after calculation) Byte: Rn + disp Word: Rn + disp × 2 Longword: Rn + disp × 4 The effective address is the contents of register Rn. A constant is added to the content of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn + 1/2/4 1/2/4 + Rn Pre-decrement indirect register addressing @–Rn The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn – 1/2/4 1/2/4 – Rn – 1/2/4 Indirect register addressing with displacement @(disp:4, The effective address is Rn plus a 4-bit Rn) displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Rn disp (zero-extended) × 1/2/4 + Rn + disp × 1/2/4 Rev. 3.0, 09/04, page 38 of 1086 Table 2.8 Addressing Mode Addressing Modes and Effective Addresses (cont) Instruction Format Effective Address Calculation Equation Rn + R0 Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0. register Rn addressing + R0 Rn + R0 Indirect GBR addressing with displacement @(disp:8, The effective address is the GBR value plus an GBR) 8-bit displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR disp (zero-extended) × 1/2/4 + GBR + disp × 1/2/4 Byte: GBR + disp Word: GBR + disp × 2 Longword: GBR + disp × 4 Indirect indexed @(R0, GBR addressing GBR) The effective address is the GBR value plus R0. GBR + R0 GBR + R0 GBR + R0 Indirect PC addressing with displacement @(disp:8, The effective address is the PC value plus an 8-bit displacement (disp). The value of disp is zeroPC) extended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword†operation, the lowest two bits of the PC value are masked. PC & H'FFFFFFFC disp (zero-extended) × 2/4 (for longword) PC + disp × 2 or PC & H'FFFFFFFC + disp × 4 Word: PC + disp × 2 Longword: PC & H'FFFFFFFC + disp × 4 + Rev. 3.0, 09/04, page 39 of 1086 Table 2.8 Addressing Mode PC relative addressing Addressing Modes and Effective Addresses (cont) Instruction Format Effective Addresses Calculation disp:8 The effective address is the PC value signextended with an 8-bit displacement (disp), doubled, and added†to the PC value. PC disp (sign-extended) × 2 + PC + disp × 2 Equation PC + disp × 2 disp:12 The effective address is the PC value signextended with a 12-bit displacement (disp), doubled, and added†to the PC value. PC disp (sign-extended) × 2 + PC + disp × 2 PC + disp ׆2 Rn The effective address is the register PC value plus Rn. PC + Rn PC + Rn PC + Rn Immediate addressing #imm:8 #imm:8 #imm:8 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended. — The 8-bit immediate data (imm) for the MOV, ADD, — and CMP/EQ instructions is sign-extended. The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and quadrupled. — Rev. 3.0, 09/04, page 40 of 1086 2.3.3 Instruction Format Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols used are as follows: • xxxx: Instruction code • mmmm: Source register • nnnn: Destination register • iiii: Immediate data • dddd: Displacement Table 2.9 Instruction Formats Source Operand — 0 xxxx xxxx xxxx xxxx Instruction Formats 0 format 15 Destination Operand — Example NOP n format 15 xxxx nnnn xxxx xxxx 0 — Control register or system register Control register or system register nnnn: Direct register nnnn: Direct register MOVT STS Rn MACH,Rn nnnn: Indirect pre- STC.L decrement register Control register or system register Control register or system register — — LDC LDC.L SR,@-Rn m format 15 xxxx mmmm xxxx xxxx 0 mmmm: Direct register mmmm: Indirect post-increment register mmmm: Direct register mmmm: PC relative using Rm Rm,SR @Rm+,SR JMP BRAF @Rm Rm Rev. 3.0, 09/04, page 41 of 1086 Table 2.9 Instruction Formats (cont) Destination Source Operand Operand 0 Instruction Formats nm format 15 xxxx nnnn mmmm xxxx Example ADD MOV.L Rm,Rn Rm,@Rn mmmm: Direct register mmmm: Direct register mmmm: Indirect post-increment register (multiplyand-accumulate) nnnn*: Indirect post-increment register (multiplyand-accumulate) mmmm: Indirect post-increment register mmmm: Direct register mmmm: Direct register nnnn: Direct register nnnn: Indirect register MACH, MACL MAC.W @Rm+,@Rn+ nnnn: Direct register nnnn: Indirect predecrement register nnnn: Indirect indexed register R0 (Direct register) MOV.L @Rm+,Rn MOV.L Rm,@-Rn MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rn),R0 md format 15 xxxx xxxx mmmm dddd 0 mmmmdddd: Indirect register with displacement R0 (Direct register) nd4 format 15 xxxx xxxx nnnn dddd 0 nnnndddd: Indirect register with displacement nnnndddd: Indirect register with displacement nnnn: Direct register MOV.B R0,@(disp,Rn) nmd format 15 0 xxxx nnnn mmmm dddd mmmm: Direct register mmmmdddd: Indirect register with displacement MOV.L Rm,@(disp,Rn) MOV.L @(disp,Rm),Rn Note: * In multiply-and-accumulate instructions, nnnn is the source register. Rev. 3.0, 09/04, page 42 of 1086 Table 2.9 Instruction Formats (cont) Destination Source Operand Operand 0 Instruction Formats d format 15 xxxx xxxx dddd dddd Example MOV.L @(disp,GBR),R0 dddddddd: Indirect GBR with displacement R0 (Direct register) dddddddd: PC relative with displacement — R0 (Direct register) dddddddd: Indirect GBR with displacement R0 (Direct register) dddddddd: PC relative dddddddddddd: PC relative MOV.L R0,@(disp,GBR) MOVA @(disp,PC),R0 BF BRA label label d12 format — 15 xxxx dddd dddd dddd nd8 format 15 xxxx nnnn dddd dddd 0 dddddddd: PC relative with displacement iiiiiiii: Immediate (label = disp + PC) MOV.L @(disp,PC),Rn 0 nnnn: Direct register i format 15 xxxx 0 xxxx iiii iiii iiiiiiii: Immediate iiiiiiii: Immediate Indirect indexed GBR R0 (Direct register) — nnnn: Direct register AND.B #imm,@(R0,GBR) AND TRAPA ADD #imm,R0 #imm #imm,Rn ni format 15 xxxx nnnn iiii iiii 0 iiiiiiii: Immediate 2.4 2.4.1 Instruction Set by Classification Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Rev. 3.0, 09/04, page 43 of 1086 Table 2.10 Classification of Instructions Operation Classification Types Code Data transfer 5 MOV Function No. of Instructions Data transfer, immediate data transfer, 39 peripheral module data transfer, structure data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of the middle of registers connected Binary addition Binary addition with carry Binary addition with overflow check Comparison Division Initialization of signed division Initialization of unsigned division Signed double-length multiplication Unsigned double-length multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate, double-length multiply-and-accumulate operation Double-length multiply operation Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow 33 MOVA MOVT SWAP XTRCT Arithmetic operations 21 ADD ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULS MULU NEG NEGC SUB SUBC SUBV Rev. 3.0, 09/04, page 44 of 1086 Table 2.10 Classification of Instructions (cont) Operation Classification Types Code Logic operations 6 AND NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch 9 BF BT BRA BRAF BSR BSRF JMP JSR RTS Function Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Conditional branch, conditional branch with delay (Branch when T = 0) Conditional branch, conditional branch with delay (Branch when T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure 11 14 No. of Instructions 14 Rev. 3.0, 09/04, page 45 of 1086 Table 2.10 Classification of Instructions (cont) Operation Classification Types Code System control 11 CLRT CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Floating-point 15 instructions FABS FADD FCMP FDIV FLDI0 FLDI1 FLDS FLOAT FMAC FMOV FMUL FNEG FSTS FSUB FTRC FPU-related CPU instructions Total: 2 LDS STS 79 Function T bit clear MAC register clear Load to control register Load to system register No operation Return from exception processing T bit set Transition to power-down mode Store control register data Store system register data Trap exception handling Floating-point absolute value Floating-point addition Floating-point comparison Floating-point division Floating-point load immediate 0 Floating-point load immediate 1 Floating-point load into system register FPUL Integer-to-floating-point conversion Floating-point multiply-and-accumulate operation Floating-point data transfer Floating-point multiplication Floating-point sign inversion Floating-point store from system register FPUL Floating-point subtraction Floating-point conversion with rounding to integer Load into floating-point system register Store from floating-point system register 172 8 22 No. of Instructions 31 Rev. 3.0, 09/04, page 46 of 1086 Table 2.11 shows the format used in tables 2.12 to 2.19, which list instruction codes, operation, and execution states in order by classification. Table 2.11 Instruction Code Format Item Instruction Format OP.Sz SRC,DEST Explanation OP: Operation code Sz: Size (B: byte, W: word, or L: longword) SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement*1 mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ⋅ ⋅ ⋅ 1111: R15 iiii: Immediate data dddd: Displacement Direction of transfer Memory operand Flag bits in the SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n-bit left shift n-bit right shift Value when no wait states are inserted*2 Value of T bit after instruction is executed. An em-dash (—) in the column means no change. Instruction code MSB ↔ LSB Operation →, ← (xx) M/Q/T & | ^ ~ n Execution cycles — T bit — Notes: 1. Depending on the operand size, displacement is scaled ×1, ×2, or ×4. For details, see the SH-2E Programming Manual. 2. Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory → register) and the register used by the next instruction are the same. Rev. 3.0, 09/04, page 47 of 1086 Table 2.12 Data Transfer Instructions Execution Cycles T Bit — — — — — — — — — — — — — — — — — — — — — — — Instruction MOV #imm,Rn Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100 Operation #imm → Sign extension → 1 Rn (disp × 2 + PC) → Sign extension → Rn (disp × 4 + PC) → Rn Rm → Rn Rm → (Rn) Rm → (Rn) Rm → (Rn) (Rm) → Sign extension → Rn (Rm) → Sign extension → Rn (Rm) → Rn Rn–1 → Rn, Rm → (Rn) Rn–2 → Rn, Rm → (Rn) Rn–4 → Rn, Rm → (Rn) (Rm) → Sign extension → Rn,Rm + 1 → Rm (Rm) → Sign extension → Rn,Rm + 2 → Rm (Rm) → Rn,Rm + 4 → Rm R0 → (disp + Rn) R0 → (disp × 2 + Rn) Rm → (disp × 4 + Rn) (disp + Rm) → Sign extension → R0 (disp × 2 + Rm) → Sign extension → R0 (disp × 4 + Rm) → Rn Rm → (R0 + Rn) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn MOV Rm,Rn MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@–Rn MOV.W Rm,@–Rn MOV.L Rm,@–Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn MOV.B R0,@(disp,Rn) MOV.W R0,@(disp,Rn) MOV.L Rm,@(disp,Rn) MOV.B @(disp,Rm),R0 MOV.W @(disp,Rm),R0 MOV.L @(disp,Rm),Rn MOV.B Rm,@(R0,Rn) Rev. 3.0, 09/04, page 48 of 1086 Table 2.12 Data Transfer Instructions (cont) Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit — — — — — — — — — — — — — — — — Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn Instruction Code 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 Operation Rm → (R0 + Rn) Rm → (R0 + Rn) (R0 + Rm) → Sign extension → Rn (R0 + Rm) → Sign extension → Rn (R0 + Rm) → Rn R0 → (disp + GBR) R0 → (disp × 2 + GBR) R0 → (disp × 4 + GBR) (disp + GBR) → Sign extension → R0 (disp × 2 + GBR) → Sign extension → R0 (disp × 4 + GBR) → R0 disp × 4 + PC → R0 T → Rn Rm → Swap bottom two bytes → Rn Rm → Swap two consecutive words → Rn Rm: Middle 32 bits of Rn → Rn R0,@(disp,GBR) 11000000dddddddd R0,@(disp,GBR) 11000001dddddddd R0,@(disp,GBR) 11000010dddddddd @(disp,GBR),R0 11000100dddddddd @(disp,GBR),R0 11000101dddddddd @(disp,GBR),R0 11000110dddddddd @(disp,PC),R0 Rn 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101 SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn Rev. 3.0, 09/04, page 49 of 1086 Table 2.13 Arithmetic Operation Instructions Execution Cycles 1 1 1 1 1 1 Instruction ADD ADD ADDC ADDV Rm,Rn #imm,Rn Rm,Rn Rm,Rn Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010101 0100nnnn00010001 0010nnnnmmmm1100 Operation Rn + Rm → Rn Rn + imm → Rn Rn + Rm + T → Rn, Carry → T Rn + Rm → Rn, Overflow → T If R0 = imm, 1 → T If Rn = Rm, 1 → T T Bit — — Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0 CMP/EQ #imm,R0 CMP/EQ Rm,Rn CMP/HS Rm,Rn CMP/GE Rm,Rn CMP/HI Rm,Rn CMP/GT Rm,Rn CMP/PL Rn CMP/PZ Rn CMP/STR Rm,Rn If Rn=Rm with unsigned 1 data, 1 → T If Rn = Rm with signed data, 1 → T If Rn > Rm with unsigned data, 1 → T If Rn > Rm with signed data, 1 → T If Rn > 0, 1 → T If Rn = 0, 1 → T If Rn and Rm have an equivalent byte, 1→T Single-step division (Rn ÷ Rm) 1 1 1 1 1 1 DIV1 DIV0S DIV0U Rm,Rn Rm,Rn 0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 1 MSB of Rn → Q, MSB 1 of Rm → M, M ^ Q → T 0 → M/Q/T 1 Rev. 3.0, 09/04, page 50 of 1086 Table 2.13 Arithmetic Operation Instructions (cont) Execution Cycles Instruction DMULS.L Rm,Rn Instruction Code 0011nnnnmmmm1101 Operation T Bit — Signed operation of Rn 2 to 4* × Rm → MACH, MACL 32 × 32 → 64 bits Unsigned operation of 2 to 4* Rn × Rm → MACH, MACL 32 × 32 → 64 bits Rn – 1 → Rn, when Rn 1 is 0, 1 → T. When Rn is nonzero, 0 → T Byte in Rm is signextended → Rn Word in Rm is signextended → Rn Byte in Rm is zeroextended → Rn Word in Rm is zeroextended → Rn Signed operation of (Rn) × (Rm) + MAC → MAC 32 × 32 + 64 → 64 bits Signed operation of (Rn) × (Rm) + MAC → MAC 16 × 16 + 64 → 64 bits Rn × Rm → MACL, 32 × 32 → 32 bits 1 1 1 1 3/(2 to 4)* DMULU.L Rm,Rn 0011nnnnmmmm0101 — DT Rn 0100nnnn00010000 Comparison result — — — — — EXTS.B Rm,Rn EXTS.W Rm,Rn EXTU.B Rm,Rn EXTU.W Rm,Rn MAC.L 0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 @Rm+,@Rn+ 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 3/(2)* — MUL.L Rm,Rn 0000nnnnmmmm0111 0010nnnnmmmm1111 2 to 4* — — MULS.W Rm,Rn Signed operation of 1 to 3* Rn × Rm → MACL 16 × 16 → 32 bits Unsigned operation of 1 to 3* Rn × Rm → MACL 16 × 16 → 32 bits 0 – Rm → Rn 0 – Rm – T → Rn, Borrow → T 1 1 MULU.W Rm,Rn 0010nnnnmmmm1110 — NEG NEGC Rm,Rn Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 — Borrow Rev. 3.0, 09/04, page 51 of 1086 Table 2.13 Arithmetic Operation Instructions (cont) Execution Cycles 1 1 1 Instruction SUB SUBC SUBV Rm,Rn Rm,Rn Rm,Rn Instruction Code 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 Operation Rn – Rm → Rn Rn – Rm – T → Rn, Borrow → T Rn – Rm → Rn, Underflow → T T Bit — Borrow Overflow Note: * The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there is contention with following instructions.) Table 2.14 Logic Operation Instructions Execution Cycles 1 1 3 1 1 1 3 Instruction AND AND Rm,Rn #imm,R0 Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 0010nnnnmmmm1000 11001000iiiiiiii 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii Operation Rn & Rm → Rn R0 & imm → R0 (R0 + GBR) & imm → (R0 + GBR) ~Rm → Rn Rn | Rm → Rn R0 | imm → R0 (R0 + GBR) | imm → (R0 + GBR) T Bit — — — — — — — Test result Test result Test result Test result — — — AND.B #imm,@(R0,GBR) NOT OR OR OR.B Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) TAS.B @Rn TST TST Rm,Rn #imm,R0 If (Rn) is 0, 1 → T; 1 → 4 MSB of (Rn) Rn & Rm; if the result is 1 0, 1 → T R0 & imm; if the result is 1 0, 1 → T (R0 + GBR) & imm; if the result is 0, 1 → T Rn ^ Rm → Rn R0 ^ imm → R0 (R0 + GBR) ^ imm → (R0 + GBR) 3 1 1 3 TST.B #imm,@(R0,GBR) XOR XOR Rm,Rn #imm,R0 XOR.B #imm,@(R0,GBR) Rev. 3.0, 09/04, page 52 of 1086 Table 2.15 Shift Instructions Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 Operation T ← Rn ← MSB LSB → Rn → T T ← Rn ← T T → Rn → T T ← Rn ← 0 MSB → Rn → T T ← Rn ← 0 0 → Rn → T Rn2 → Rn Rn8 → Rn Rn16 → Rn T Bit MSB LSB MSB LSB MSB LSB MSB LSB — — — — — — SHLL16 Rn SHLR16 Rn Rev. 3.0, 09/04, page 53 of 1086 Table 2.16 Branch Instructions Execution Cycles 3/1* 3/1* 3/1* 2/1* 2 2 2 2 2 2 2 Instruction BF label Instruction Code Operation T Bit — — — — — — — — — — — 10001011dddddddd If T = 0, disp × 2 + PC → PC; if T = 1, nop 10001111dddddddd Delayed branch, if T = 0, disp × 2 + PC → PC; if T = 1, nop 10001001dddddddd If T = 1, disp × 2 + PC → PC; if T = 0, nop 10001101dddddddd Delayed branch, if T = 1, disp × 2 + PC → PC; if T = 0, nop 1010dddddddddddd Delayed branch, disp × 2 + PC → PC 0000mmmm00100011 Delayed branch, Rm + PC → PC 1011dddddddddddd Delayed branch, PC → PR, disp × 2 + PC → PC 0000mmmm00000011 Delayed branch, PC → PR, Rm + PC → PC 0100mmmm00101011 Delayed branch, Rm → PC 0100mmmm00001011 Delayed branch, PC → PR, Rm → PC 0000000000001011 Delayed branch, PR → PC BF/S label BT label BT/S label BRA label BRAF Rm BSR label BSRF Rm JMP JSR RTS @Rm @Rm Note: * One state when the program does not branch. Rev. 3.0, 09/04, page 54 of 1086 Table 2.17 System Control Instructions Execution Cycles 1 1 1 1 1 3 3 3 1 1 1 Instruction CLRT CLRMAC LDC LDC LDC Rm,SR Rm,GBR Rm,VBR Instruction Code 0000000000001000 0000000000101000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000000000101011 0000000000011000 0000000000011011 Operation 0→T 0 → MACH, MACL Rm → SR Rm → GBR Rm → VBR (Rm) → SR, Rm + 4 → Rm (Rm) → GBR, Rm + 4 → Rm (Rm) → VBR, Rm + 4 → Rm Rm → MACH Rm → MACL Rm → PR T Bit 0 — LSB — — LSB — — — — — — — — — — 1 — — — — — — — — — — LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDS LDS LDS Rm,MACH Rm,MACL Rm,PR LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR NOP RTE SETT SLEEP STC STC STC STC.L STC.L STC.L STS STS STS SR,Rn GBR,Rn VBR,Rn SR,@–Rn GBR,@–Rn VBR,@–Rn MACH,Rn MACL,Rn PR,Rn (Rm) → MACH, Rm + 4 → Rm 1 (Rm) → MACL, Rm + 4 → Rm 1 (Rm) → PR, Rm + 4 → Rm No operation Delayed branch, stack area → PC/SR 1→T Sleep SR → Rn GBR → Rn VBR → Rn Rn – 4 → Rn, SR → (Rn) Rn – 4 → Rn, GBR → (Rn) Rn – 4 → Rn, BR → (Rn) MACH → Rn MACL → Rn PR → Rn 1 1 4 1 3* 1 1 1 2 2 2 1 1 1 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 Rev. 3.0, 09/04, page 55 of 1086 Table 2.17 System Control Instructions (cont) Execution Cycles 1 1 1 Instruction STS.L STS.L STS.L TRAPA MACH,@–Rn MACL,@–Rn PR,@–Rn #imm Instruction Code 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Operation Rn – 4 → Rn, MACH → (Rn) Rn – 4 → Rn, MACL → (Rn) Rn – 4 → Rn, PR → (Rn) T Bit — — — — PC/SR → stack area, (imm × 4 8 + VBR) → PC Note: * The number of execution cycles before the chip enters sleep mode: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory → register) and the register used by the next instruction are the same. Rev. 3.0, 09/04, page 56 of 1086 Table 2.18 Floating-Point Instructions Execution Cycles T Bit 1 1 — — Comparison result Comparison result — — — — — — — — — — — — — — — — — — Instruction FABS FADD FRn FRm,FRn Instruction Code Operation 1111nnnn01011101 |FRn| → FRn 1111nnnnmmmm0000 FRn + FRm → FRn FCMP/EQ FRm,FRn FCMP/GT FRm,FRn FDIV FLDI0 FLDI1 FLDS FLOAT FMAC FMOV FRm,FRn FRn FRn FRm,FPUL FPUL,FRn FR0,FRm,FRn FRm, FRn 1111nnnnmmmm0100 (FRn = FRm)? 1:0 → T 1 1111nnnnmmmm0101 (FRn > FRm)? 1:0 → T 1 1111nnnnmmmm0011 FRn/FRm → FRn 1111nnnn10001101 0x00000000 → FRn 1111nnnn10011101 0x3F800000 → FRn 1111mmmm00011101 FRm → FPUL 1111nnnn00101101 (float) FPUL → FRn 1111nnnnmmmm1110 FR0 × FRm + FRn → FRn 1111nnnnmmmm1100 FRm → FRn 1111nnnnmmmm0110 (R0 + Rm) → FRn 1111nnnnmmmm1001 (Rm) → FRn, Rm+ = 4 1111nnnnmmmm1000 (Rm) → FRn 1111nnnnmmmm0111 FRm → (R0 + Rn) 1111nnnnmmmm1011 Rn– = 4, FRm → (Rn) 1111nnnnmmmm1010 FRm → (Rn) 1111nnnnmmmm0010 FRn × FRm → FRn 1111nnnn01001101 –FRn → FRn 1111nnnn00001101 FPUL → FRn 1111nnnnmmmm0001 FRn – FRm → FRn 1111mmmm00111101 (long) FRm → FPUL 13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FMOV.S @(R0,Rm),FRn FMOV.S @Rm+,FRn FMOV.S @Rm,FRn FMOV.S FRm,@(R0,Rn) FMOV.S FRm,@-Rn FMOV.S FRm,@Rn FMUL FNEG FSTS FSUB FTRC FRm,FRn FRn FPUL,FRn FRm,FRn FRm,FPUL Rev. 3.0, 09/04, page 57 of 1086 Table 2.19 FPU-Related CPU Instructions Execution Cycles 1 1 Instruction LDS LDS LDS.L LDS.L STS STS STS.L STS.L Rm,FPSCR Rm,FPUL @Rm+, FPSCR @Rm+, FPUL FPSCR, Rn FPUL,Rn FPSCR,@-Rn FPUL,@-Rn Instruction Code Operation T Bit — — — — — — — — 0100mmmm01101010 Rm → FPSCR 0100mmmm01011010 Rm → FPUL 0100mmmm01010110 @Rm → FPUL, Rm+ = 4 0000nnnn01101010 FPSCR → Rn 0000nnnn01011010 FPUL → Rn 0100nnnn01100010 Rn– = 4, FPCSR → @Rn 0100nnnn01010010 Rn– = 4, FPUL → @Rn 0100mmmm01100110 @Rm → FPSCR, Rm+ = 4 1 1 1 1 1 1 2.5 2.5.1 Processing States State Transitions The CPU has five processing states: power-on reset, exception processing, bus release, program execution and power-down. Figure 2.8 shows the transitions between the states. Rev. 3.0, 09/04, page 58 of 1086 From any state =0 when =1 and Power-on reset state =0 =1 =1 When an interrupt source or DMA address error occurs Exception processing state Bus request cleared Bus request generated Bus release state Exception processing source occurs Bus request cleared NMI interrupt source occurs Exception processing ends Bus request generated Bus request generated Bus request cleared Program execution state SBY bit set for SLEEP instruction SBY bit cleared for SLEEP instruction Sleep mode Software standby mode Hardware standby mode Power-down state From any state when = 0 and =0 Note: An internal reset due to the WDT causes a transition from the program execution state or sleep mode to the exception processing state. Figure 2.8 Transitions between Processing States Rev. 3.0, 09/04, page 59 of 1086 Power-On Reset State: The CPU resets in the reset state. When the HSTBY pin is driven high and the RES pin level goes low, the power-on reset state is entered. Exception Processing State: The exception processing state is a transient state that occurs when exception processing sources such as resets or interrupts alter the CPU’s processing state flow. For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception processing vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. Program Execution State: In the program execution state, the CPU sequentially executes the program. Power-Down State: In the power-down state, the CPU operation halts and power consumption declines. The SLEEP instruction places the CPU in the sleep mode or the software standby mode. If the HSTBY pin is driven low when the RES pin is low, the CPU will enter the hardware standby mode. Bus Release State: In the bus release state, the CPU releases access rights to the bus to the device that has requested them. Rev. 3.0, 09/04, page 60 of 1086 Section 3 Floating-Point Unit (FPU) 3.1 Overview The SH7058 has an on-chip floating-point unit (FPU), The FPU’s register configuration is shown in figure 3.1. Floating-point registers 31 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 0 FR0 functions as the index register for the FMAC instruction. Floating-point system registers 31 FPUL 31 FPSCR 0 0 Floating-point communication register Specifies buffer as communication register between CPU and FPU*. Floating-point status/control register Indicates status/control information relating to FPU exceptions*. Note: * For details, see section 3.2, Floating-Point Registers and Floating-Point System Registers. Figure 3.1 Overview of Register Configuration (Floating-Point Registers and Floating-Point System Registers) Rev. 3.0, 09/04, page 61 of 1086 3.2 3.2.1 Floating-Point Registers and Floating-Point System Registers Floating-Point Register File The SH7058 has sixteen 32-bit single-precision floating-point registers. Register specifications are always made as 4 bits. In assembly language, the floating-point registers are specified as FR0, FR1, FR2, and so on. FR0 functions as the index register for the FMAC instruction. 3.2.2 Floating-Point Communication Register (FPUL) Information for transfer between the FPU and the CPU is transferred via the FPUL communication register, which resembles MACL and MACH in the integer unit. The SH7058 is provided with this communication register since the integer and floating-point formats are different. The 32-bit FPUL is a system register, and is accessed by the CPU by means of LDS and STS instructions. 3.2.3 Floating-Point Status/Control Register (FPSCR) The SH7058 has a floating-point status/control register (FPSCR) that functions as a system register accessed by means of LDS and STS instructions (figure 3.2). FPSCR can be written to by a user program. This register is part of the process context, and must be saved when the context is switched. It may also be necessary to save this register when a procedure call is made. FPSCR is a 32-bit register that controls the storage of detailed information relating to the rounding mode, asymptotic underflow (denormalized numbers), and FPU exceptions. The module stop bit that disables the FPU itself is provided in the module standby control register (MSTCR). For details, see section 25, Power-Down State. After a reset start, the FPU is enabled. Table 3.1 shows the flags corresponding the five kinds of FPU exception. A sixth flag is also provided as an FPU error flag that indicates an floating-point unit error state not covered by the other five flags. Table 3.1 Flag E V Z O U I Floating-Point Exception Flags Meaning FPU error Invalid operation Division by zero Overflow (value not expressed) Underflow (value not expressed) Inexact (result not expressed) Support in SH7058 — Yes Yes — — — Rev. 3.0, 09/04, page 62 of 1086 The bits in the cause field indicate the exception cause for the instruction executing at the time. The cause bits are modified by a floating-point instruction. These bits are set to 1 or cleared to 0 according to whether or not an exception state occurred during execution of a single instruction. The bits in the enable field specify the kinds of exception to be enabled, allowing the flow to be changed to exception processing. If the cause bit corresponding to an enable bit is set by the currently executing instruction, an exception occurs. The bits in the flag field are used to keep a tally of all exceptions that occur during a series of instructions. Once one of these bits is set by an instruction, it is not reset by a subsequent instruction. The bits in this field can only be reset by the explicit execution of a store operation on FPSCR. Rev. 3.0, 09/04, page 63 of 1086 31 Reserved 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cause field Enable field Flag field DN CE CV CZ CO CU CI EV EZ EO EU EI FV FZ FO FU FI RM DN: Denormalized bit In the SH7058 this bit is always set to 1, and the source or destination operand of a denormalized number is 0. This bit cannot be modified even by an LDS instruction. Invalid operation cause bit When 1: Indicates that an invalid operation exception occurred during execution of the current instruction. When 0: Indicates that an invalid operation exception has not occurred. Division-by-zero cause bit When 1: Indicates that a division-by-zero exception occurred during execution of the current instruction. When 0: Indicates that a division-by-zero exception has not occurred. Invalid operation exception enable When 1: Enables invalid operation exception generation. When 0: An invalid operation exception is not generated, and a qNAN is returned as the result. Division-by-zero exception enable When 1: Enables exception generation due to division-by-zero during execution of the current instruction. When 0: A division-by-zero exception is not generated, and infinity with the sign (+ or ) of the current expression is returned as the result. CV: CZ: EV: EZ: FV: Invalid operation exception flag bit When 1: Indicates that an invalid operation exception occurred during instruction execution. When 0: Indicates that an invalid operation exception has not occurred. FZ: Division-by-zero exception flag bit When 1: Indicates that a division-by-zero exception occurred during instruction execution. When 0: Indicates that a division-by-zero exception has not occurred. RM: Rounding bit. In the SH7058, the value of these bits is always 01, meaning that rounding to zero (RZ mode) is being used. These bits cannot be modified even by an LDS instruction. In the SH7058, the cause field EOUI bits (CE, CO, CU, and CI), enable field OUI bits (EO, EU, and EI), and flag field OUI bits (FO, FU, and FI), and the reserved area, are preset to 0, and cannot be modified even by using an LDS instruction. Figure 3.2 Floating-Point Status/Control Register Rev. 3.0, 09/04, page 64 of 1086 3.3 3.3.1 Floating-Point Format Floating-Point Format The SH7058 supports single-precision floating-point operations, and fully complies with the IEEE754 floating-point standard. A floating-point number consists of the following three fields: • Sign (s) • Exponent (e) • Fraction (f) The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is Emin – 1 to Emax + 1. The two values Emin – 1 and Emax + 1 are distinguished as follows. Emin – 1 indicates zero (both positive and negative sign) and a denormalized number, and Emax + 1 indicates positive or negative infinity or a non-number (NaN). In a single-precision operation, the bias value is 127, Emin is –126, and Emax is 127. 31 30 s e 23 22 f 0 Figure 3.3 Floating-Point Number Format Floating-point number value v is determined as follows: If E = Emax + 1 and f! = 0, v is a non-number (NaN) irrespective of sign s s If E = Emax + 1 and f = 0, v = (-1) (infinity) [positive or negative infinity] sE If Emin DMAC > CPU Therefore, an external device that generates a bus request is given priority even if the request is made during a DMAC burst transfer. The AUD does not acquire the bus during DMAC burst transfer, but at the end of the transfer. When the CPU has possession of the bus, the AUD has higher priority than the DMAC for bus acquisition. A bus request by an external device should be input at the BREQ pin. The signal indicating that the bus has been released is output from the BACK pin. Figure 9.9 shows the bus right release procedure. SH7058 accepted Strobe pin: high-level output Address, data, strobe pin: high impedance Bus right release response Bus right release status = Low = Low External device Bus right request confirmation Bus right acquisition Figure 9.9 Bus Right Release Procedure Rev. 3.0, 09/04, page 160 of 1086 9.6 Memory Connection Examples Figures 9.10–9.13 show examples of the memory connections. 32 k × 8-bit ROM SH7058 A0–A14 D0–D7 A0–A14 I/O0–I/O7 Figure 9.10 Example of 8-Bit Data Bus Width ROM Connection 256 k × 16-bit ROM SH7058 A0 A1–A18 D0–D15 A0–A17 I/O0–I/O15 Figure 9.11 Example of 16-Bit Data Bus Width ROM Connection 128 k × 8-bit SRAM SH7058 A0–A16 A0–A16 D0–D7 I/O0–I/O7 Figure 9.12 Example of 8-Bit Data Bus Width SRAM Connection Rev. 3.0, 09/04, page 161 of 1086 SH7058 128 k × 8-bit SRAM A0 A1–A17 D8–D15 A0–A16 I/O0–I/O7 D0–D7 A0–A16 I/O0–I/O7 Figure 9.13 Example of 16-Bit Data Bus Width SRAM Connection Rev. 3.0, 09/04, page 162 of 1086 Section 10 Direct Memory Access Controller (DMAC) 10.1 Overview The SH7058 includes an on-chip four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external memories, memory-mapped external devices, and on-chip peripheral modules (except for the DMAC, BSC, and UBC). Using the DMAC reduces the burden on the CPU and increases the operating efficiency of the chip as a whole. 10.1.1 Features The DMAC has the following features: • Four channels • 4-Gbyte address space in the architecture • 8-, 16-, or 32-bit selectable data transfer length • Maximum of 16 M (16,777,216) transfers • Address modes Both the transfer source and transfer destination are accessed by address. There are two transfer modes: direct address and indirect address.  Direct address transfer mode: Values set in a DMAC internal register indicate the accessed address for both the transfer source and transfer destination. Two bus cycles are required for one data transfer.  Indirect address transfer mode: The value stored at the location pointed to by the address set in the DMAC internal transfer source register is used as the address. Operation is otherwise the same as for direct access. This function can only be set for channel 3. Four bus cycles are required for one data transfer. • Channel function: Dual address mode is supported on all channels. Channel 2 has a source address reload function that reloads the source address every fourth transfer. Direct address transfer mode or indirect address transfer mode can be specified for channel 3. • Reload function Enables automatic reloading of the value set in the first source address register every fourth DMA transfer. This function can be executed on channel 2 only. • Transfer requests There are two DMAC transfer activation requests, as indicated below. Rev. 3.0, 09/04, page 163 of 1086  Requests from on-chip peripheral modules: Transfer requests from on-chip modules such as the SCI or A/D. These can be received by all channels.  Auto-request: The transfer request is generated automatically within the DMAC. • Selectable bus modes: Cycle-steal mode or burst mode • Fixed DMAC channel priority ranking • CPU can be interrupted when the specified number of data transfers are complete. Rev. 3.0, 09/04, page 164 of 1086 10.1.2 Block Diagram Figure 10.1 is a block diagram of the DMAC. DMAC module On-chip ROM Circuit control Register control Peripheral bus Internal bus SARn On-chip RAM On-chip peripheral module DARn DMATCRn Activation control CHCRn DMAOR HCAN0 ATU-II SCI0–SCI4 A/D converter 0–2 DEIn Request priority control External ROM External RAM External I/O (memory mapped) External bus Bus interface Bus state controller SARn: DARn: DMATCRn: CHCRn: DMAOR: n: DMA source address register DMA destination address register DMA transfer count register DMA channel control register DMA operation register 0, 1, 2, 3 Figure 10.1 DMAC Block Diagram Rev. 3.0, 09/04, page 165 of 1086 10.1.3 Register Configuration Table 10.1 summarizes the DMAC registers. The DMAC has a total of 17 registers. Each channel has four registers, and one overall DMAC control register is shared by all channels. Table 10.1 DMAC Registers Channel Name 0 DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0 1 DMA source address register 1 DMA destination address register 1 DMA transfer count register 1 DMA channel control register 1 2 DMA source address register 2 DMA destination address register 2 DMA transfer count register 2 DMA channel control register 2 Abbr. SAR0 DAR0 R/W R/W R/W Initial Value Undefined Undefined Undefined 1 Address Register Access Size Size 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 2 H'FFFFECC0 32 bits H'FFFFECC4 32 bits H'FFFFECC8 32 bits 2 DMATCR0 R/W CHCR0 SAR1 DAR1 R/W* R/W R/W 2 H'00000000 H'FFFFECCC 32 bits Undefined Undefined Undefined H'FFFFECD0 32 bits H'FFFFECD4 32 bits H'FFFFECD8 32 bits 2 2 2 DMATCR1 R/W CHCR1 SAR2 DAR2 R/W* R/W R/W 1 3 H'00000000 H'FFFFECDC 32 bits Undefined Undefined Undefined H'FFFFECE0 32 bits H'FFFFECE4 32 bits H'FFFFECE8 32 bits 2 2 2 DMATCR2 R/W CHCR2 R/W* 1 3 H'00000000 H'FFFFECEC 32 bits 2 Rev. 3.0, 09/04, page 166 of 1086 Table 10.1 DMAC Registers (cont) Channel Name 3 DMA source address register 3 DMA destination address register 3 DMA transfer count register 3 DMA channel control register 3 Shared Notes: DMA operation register Abbr. SAR3 DAR3 R/W R/W R/W Initial Value Undefined Undefined Undefined 1 Address Register Access Size Size 16, 32* 16, 32* 16, 32* 16, 32* 16* 4 2 H'FFFFECF0 32 bits H'FFFFECF4 32 bits H'FFFFECF8 32 bits 2 DMATCR3 R/W CHCR3 DMAOR R/W* R/W* 3 H'00000000 H'FFFFECFC 32 bits H'0000 H'FFFFECB0 16 bits 2 1 1. 2. 3. 4. Word access to a register takes four cycles, and longword access eight cycles. Do not attempt to access an empty address, as operation canot be guaranteed if this is done. Write 0 after reading 1 in bit 1 of CHCR0–CHCR3 and in bits 1 and 2 of DMAOR to clear flags. No other writes are allowed. For 16-bit access of SAR0–SAR3, DAR0–DAR3, and CHCR0–CHCR3, the 16-bit value on the side not accessed is held. DMATCR has a 24-bit configuration: bits 0–23. Writing to the upper 8 bits (bits 24–31) is invalid, and these bits always read 0. Do not use 32-bit access on DMAOR. 10.2 10.2.1 Register Descriptions DMA Source Address Registers 0–3 (SAR0–SAR3) Bit: 31 30 29 28 27 26 25 24 Initial value: R/W: Bit: — R/W 23 — R/W 22 — R/W 21 — R/W … … — R/W … … … … — R/W 2 — R/W 1 — R/W 0 Initial value: R/W: — R/W — R/W — R/W … … — R/W — R/W — R/W Rev. 3.0, 09/04, page 167 of 1086 DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that specify the source address of a DMA transfer. These registers have a count function, and during a DMA transfer, they indicate the next source address. Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set. The initial value after a power-on reset and in standby mode is undefined. 10.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) Bit: 31 30 29 28 27 26 25 24 Initial value: R/W: Bit: — R/W 23 — R/W 22 — R/W 21 — R/W … … — R/W … … … … — R/W 2 — R/W 1 — R/W 0 Initial value: R/W: — R/W — R/W — R/W … … — R/W — R/W — R/W DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. These registers have a count function, and during a DMA transfer, they indicate the next destination address. Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set. The value after a power-on reset and in standby mode is undefined. Rev. 3.0, 09/04, page 168 of 1086 10.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) Bit: 31 — Initial value: R/W: Bit: 0 R 23 30 — 0 R 22 29 — 0 R 21 28 — 0 R 20 27 — 0 R 19 26 — 0 R 18 25 — 0 R 17 24 — 0 R 16 Initial value: R/W: Bit: — R/W 15 — R/W 14 — R/W 13 — R/W 12 — R/W 11 — R/W 10 — R/W 9 — R/W 8 Initial value: R/W: Bit: — R/W 7 — R/W 6 — R/W 5 — R/W 4 — R/W 3 — R/W 2 — R/W 1 — R/W 0 Initial value: R/W: — R/W — R/W — R/W — R/W — R/W — R/W — R/W — R/W DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 24-bit read/write registers that specify the transfer count for the channel (byte count, word count, or longword count) in bits 23 to 0. Specifying H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 16,777,216 transfers. During DMAC operation, these registers indicate the remaining number of transfers. The upper 8 bits of DMATCR always read 0. The write value, also, should always be 0. The value after a power-on reset and in standby mode is undefined. Rev. 3.0, 09/04, page 169 of 1086 10.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) Bit: 31 — Initial value: R/W: Bit: 0 R 23 — Initial value: R/W: Bit: 0 R 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 30 — 0 R 22 — 0 R 14 — 0 R 6 — 0 R 29 — 0 R 21 — 0 R 13 SM1 0 R/W 5 TS1 0 R/W 28 DI 0 R/W* 20 RS4 0 R/W 12 SM0 0 R/W 4 TS0 0 R/W 2 27 — 0 R 19 RS3 0 R/W 11 — 0 R 3 TM 0 R/W 26 — 0 R 18 RS2 0 R/W 10 — 0 R 2 IE 0 R/W 25 — 0 R 17 RS1 0 R/W* 9 DM1 0 R/W 1 TE 0 R/(W)* 1 1 24 RO 0 R/W* 16 RS0 0 R/W 8 DM0 0 R/W 0 DE 0 R/W 2 Notes: 1. TE bit: Allows only a 0 write after reading 1. 2. The DI and RO bits may be absent, depending on the channel. DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that designate the operation and transmission of each channel. CHCR register bits are initialized to H'00000000 by a power-on reset and in standby mode. Rev. 3.0, 09/04, page 170 of 1086 • Bits 31–29, 27–25, 23–21, 15, 14, 11, 10, 7, 6—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 28—Direct/Indirect Select (DI): Specifies either direct address mode operation or indirect address mode operation for the channel 3 source address. This bit is valid only in CHCR3. This bit is always read as 0 in CHCR0–CHCR2, and the write value should always be 0. Bit 28: DI 0 1 Description Direct access mode operation for channel 3 Indirect access mode operation for channel 3 (Initial value) • Bit 24—Source Address Reload (RO): Selects whether to reload the source address initial value during channel 2 transfer. This bit is valid only for channel 2. This bit is always read as 0 in CHCR0, CHCR1, and CHCR3, and the write value should always be 0. Bit 24: RO 0 1 Description Does not reload source address Reloads source address (Initial value) Rev. 3.0, 09/04, page 171 of 1086 • Bits 20–16—Resource Select 4–0 (RS4–RS0): These bits specify the transfer request source. Bit 20: RS4 0 Bit 19: RS3 0 Bit 18: RS2 0 Bit 17: RS1 0 Bit 16: RS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 Note: * Refer to no. 12 in section 10.5, Usage Notes. 0 1 Description No request* (Initial value) SCI0 transmission SCI0 reception SCI1 transmission SCI1 reception SCI2 transmission SCI2 reception SCI3 transmission SCI3 reception SCI4 transmission SCI4 reception On-chip A/D0 On-chip A/D1 On-chip A/D2 No request* HCAN0 (RM0) No request* ATU-II (ICI0A) ATU-II (ICI0B) ATU-II (ICI0C) ATU-II (ICI0D) ATU-II (CMI6A) ATU-II (CMI6B) ATU-II (CMI6C) ATU-II (CMI6D) ATU-II (CMI7A) ATU-II (CMI7B) ATU-II (CMI7C) ATU-II (CMI7D) No request* No request* Auto-request Rev. 3.0, 09/04, page 172 of 1086 • Bits 13 and 12—Source Address Mode 1, 0 (SM1, SM0): These bits specify increment/decrement of the DMA transfer source address. Bit 13: SM1 0 0 1 1 Bit 12: SM0 0 1 0 1 Description Source address fixed (Initial value) Source address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) Source address decremented (–1 during 8-bit transfer, –2 during 16-bit transfer, –4 during 32-bit transfer) Setting prohibited When the transfer source is specified at an indirect address, specify in source address register 3 (SAR3) the actual storage address of the data to be transferred as the data storage address (indirect address). During indirect address mode, SAR3 obeys the SM1/SM0 setting for increment/decrement. In this case, SAR3’s increment/decrement is fixed at +4/–4 or 0, irrespective of the transfer data size specified by TS1 and TS0. • Bits 9 and 8—Destination Address Mode 1, 0 (DM1, DM0): These bits specify increment/decrement of the DMA transfer source address. Bit 9: DM1 0 0 1 1 Bit 8: DM0 0 1 0 1 Description Destination address fixed (Initial value) Destination address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) Destination address decremented (–1 during 8-bit transfer, –2 during 16-bit transfer, –4 during 32-bit transfer) Setting prohibited • Bits 5 and 4—Transfer Size 1, 0 (TS1, TS0): These bits specify the size of the data for transfer. Bit 5: TS1 0 0 1 1 Bit 4: TS0 0 1 0 1 Description Specifies byte size (8 bits) Specifies word size (16 bits) Specifies longword size (32 bits) Setting prohibited (Initial value) Rev. 3.0, 09/04, page 173 of 1086 • Bit 3—Transfer Mode (TM): Specifies the bus mode for data transfer. Bit 3: TM 0 1 Description Cycle-steal mode Burst mode (Initial value) • Bit 2—Interrupt Enable (IE): When this bit is set to 1, interrupt requests are generated after the number of data transfers specified in DMATCR (when TE = 1). Bit 2: IE 0 1 Description Interrupt request not generated on completion of DMATCR-specified number of transfers (Initial value) Interrupt request enabled on completion of DMATCR-specified number of transfers • Bit 1—Transfer End (TE): This bit is set to 1 after the number of data transfers specified by DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI or address error, or clearing of the DE bit or DME bit of DMAOR) TE is not set to 1. With this bit set to 1, data transfer is disabled even if the DE bit is set to 1. Bit 1: TE 0 Description DMATCR-specified number of transfers not completed [Clearing condition] 0 write after TE = 1 read, power-on reset, standby mode 1 DMATCR-specified number of transfers completed (Initial value) • Bit 0—DMAC Enable (DE): DE enables operation in the corresponding channel. Bit 0: DE 0 1 Description Operation of the corresponding channel disabled Operation of the corresponding channel enabled (Initial value) Transfer is initiated if this bit is set to 1 when auto-request is specified (RS4–RS0 settings). With an on-chip module request, when a transfer request occurs after this bit is set to 1, transfer is initiated. If this bit is cleared during a data transfer, transfer is suspended. If the DE bit has been set, but TE = 1, then if the DME bit of DMAOR is 0, and the NMIF or AE bit of DMAOR is 1, the transfer enable state is not entered. Rev. 3.0, 09/04, page 174 of 1086 10.2.5 DMAC Operation Register (DMAOR) Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 — 0 R 12 — 0 R 4 — 0 R 11 — 0 R 3 — 0 R 10 — 0 R 2 AE 0 R/(W)* 9 — 0 R 1 NMIF 0 R/(W)* 8 — 0 R 0 DME 0 R/W Note: * Only a 0 write is valid after 1 is read at the AE and NMIF bits. DMAOR is a 16-bit readable/writable register that controls the overall operation of the DMAC. Register values are initialized to H'0000 by a power-on reset and in standby mode. • Bits 15–3—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU cannot write a 1 to the AE bit. Clearing is effected by a 0 write after a 1 read. Bit 2: AE 0 Description No address error, DMA transfer enabled [Clearing condition] Write AE = 0 after reading AE = 1 1 Address error, DMA transfer disabled [Setting condition] Address error due to DMAC (Initial value) Rev. 3.0, 09/04, page 175 of 1086 • Bit 1—NMI Flag (NMIF): Indicates input of an NMI. This bit is set irrespective of whether the DMAC is operating or suspended. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU is unable to write a 1 to the NMIF. Clearing is effected by a 0 write after a 1 read. Bit 1: NMIF 0 Description No NMI interrupt, DMA transfer enabled [Clearing condition] Write NMIF = 0 after reading NMIF = 1 1 NMI has occurred, DMC transfer disabled [Setting condition] NMI interrupt occurrence (Initial value) • Bit 0—DMAC Master Enable (DME): This bit enables activation of the entire DMAC. When the DME bit and DE bit of the CHCR register for the corresponding channel are set to 1, that channel is transfer-enabled. If this bit is cleared during a data transfer, transfers on all channels are suspended. Even when the DME bit is set, when the TE bit of CHCR is 1, or its DE bit is 0, transfer is disabled if the NMIF or AE bit in DMAOR is set to 1. Bit 0: DME 0 1 Description Operation disabled on all channels Operation enabled on all channels (Initial value) Rev. 3.0, 09/04, page 176 of 1086 10.3 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in two modes: auto-request and on-chip peripheral module request. Transfer is performed only in dual address mode, and either direct or indirect address transfer mode can be used. The bus mode can be either burst or cycle-steal. 10.3.1 DMA Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count register (DMATCR), DMA channel control registers (CHCR), and DMA operation register (DMAOR) are set to the desired transfer conditions, the DMAC transfers data according to the following procedure: 1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0). 2. When a transfer request comes and transfer has been enabled, the DMAC transfers 1 transfer unit of data (determined by the TS0 and TS1 setting). For an auto-request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented by 1 upon each transfer. The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfers have been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit of CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is aborted. Transfer is also aborted when the DE bit of CHCR or the DME bit of DMAOR is cleared to 0. Rev. 3.0, 09/04, page 177 of 1086 Figure 10.2 is a flowchart of this procedure. Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1 and NMIF, AE, TE = 0? Yes Transfer request occurs?*1 Yes No No *2 *3 Bus mode Transfer (1 transfer unit); DMATCR – 1 → DMATCR, SAR, and DAR updated Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Yes Transfer aborted DMATCR = 0? Yes No No DEI interrupt request (when IE = 1) Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Yes Transfer ends No Normal end Notes: 1. In auto-request mode, transfer begins when NMIF, AE, and TE are all 0, and the DE and DME bits are set to 1. 2. Cycle-steal mode 3. Burst mode Figure 10.2 DMAC Transfer Flowchart Rev. 3.0, 09/04, page 178 of 1086 10.3.2 DMA Transfer Requests DMA transfer requests are generated in either the data transfer source or destination. Transfers can be requested in two modes: auto-request and on-chip peripheral module request. The request mode is selected in the RS4–RS0 bits of DMA channel control registers 0–3 (CHCR0–CHCR3). Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits of CHCR0–CHCR3 and the DME bit of DMAOR are set to 1, the transfer begins (so long as the TE bits of CHCR0–CHCR3 and the NMIF and AE bits of DMAOR are all 0). On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 10.2, there are 26 transfer request signals: 12 from the advanced timer unit (ATU-II), which are compare match or input capture interrupts; the receive data full interrupts (RXI) and transmit data empty interrupts (TXI) of the five serial communication interfaces (SCI); the receive interrupt of HCAN0; and the A/D conversion end interrupts (ADI) of the three A/D converters. When DMA transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request signal. When the transfer request is set to RXI (transfer request because the SCI’s receive data register is full), the transfer source must be the SCI’s receive data register (RDR). When the transfer request is set to TXI (transfer request because the SCI’s transmit data register is empty), the transfer destination must be the SCI’s transmit data register (TDR). If the transfer request is set to the A/D converter, the data transfer source must be the A/D converter register; if set to HCAN0, the transfer source must be HCAN0 message data. In on-chip peripheral module request mode, when the DMAC accepts the transfer request, the next transfer request is ignored until a single transfer ends in cycle steal mode or all transfers end in burst mode. Only when the address reload function is used, the next transfer request is accepted after the fourth transfer. Rev. 3.0, 09/04, page 179 of 1086 Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits DMAC Transfer Request Source SCI0 transmit block SCI0 receive block SCI1 transmit block SCI1 receive block SCI2 transmit block SCI2 receive block SCI3 transmit block SCI3 receive block SCI4 transmit block SCI4 receive block A/D0 RS4 0 RS3 0 RS2 0 RS1 0 RS0 1 DMAC Transfer Request Signal TXI0 (SCI0 transmitdata-empty transfer request) RXI0 (SCI0 receivedata-full transfer request) TXI1 (SCI1 transmitdata-empty transfer request) RXI1 (SCI1 receivedata-full transfer request) TXI2 (SCI2 transmitdata-empty transfer request) RXI2 (SCI2 receivedata-full transfer request) TXI3 (SCI3 transmitdata-empty transfer request) RXI3 (SCI3 receivedata-full transfer request) TXI4 (SCI4 transmitdata-empty transfer request) RXI4 (SCI4 receivedata-full transfer request) ADI0 (A/D0 conversion end interrupt) ADI1 (A/D1 conversion end interrupt) ADI2 (A/D2 conversion end interrupt) RM0 (HCAN0 receive interrupt) Transfer Source Don’t care* Transfer Destination TDR0 Bus Mode Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal 1 0 RDR0 Don’t care* 1 Don’t care* TDR1 1 0 0 RDR1 Don’t care* 1 Don’t care* TDR2 1 0 RDR2 Don’t care* 1 Don’t care* TDR3 1 0 0 0 RDR3 Don’t care* 1 Don’t care* TDR4 1 0 RDR4 Don’t care* 1 ADDR0– ADDR11 ADDR12– ADDR23 ADDR24– ADDR31 MB0–MB15 Don’t care* 1 0 0 A/D1 Don’t care* 1 A/D2 Don’t care* 1 1 HCAN0 Don’t care* Rev. 3.0, 09/04, page 180 of 1086 Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits (cont) DMAC Transfer Request Source ATU-II ATU-II ATU-II ATU-II ATU-II RS4 1 RS3 0 RS2 0 RS1 0 1 RS0 1 0 1 DMAC Transfer Request Signal ICI0A (ICR0A input capture generation) ICI0B (ICR0B input capture generation) ICI0C (ICR0C input capture generation) ICI0D (ICR0D input capture generation) CMI6A (CYLR6A compare-match generation) CMI6B (CYLR6B compare-match generation) CMI6C (CYLR6C compare-match generation) CMI6D (CYLR6D compare-match generation) CMI7A (CYLR7A compare-match generation) CMI7B (CYLR7B compare-match generation) CMI7C (CYLR7C compare-match generation) CMI7D (CYLR7D compare-match generation) Transfer Source Don’t care* Don’t care* Don’t care* Don’t care* Don’t care* Transfer Destination Don’t care* Don’t care* Don’t care* Don’t care* Don’t care* Bus Mode Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal Burst/cyclesteal 1 0 0 1 1 0 ATU-II Don’t care* Don’t care* 1 ATU-II Don’t care* Don’t care* 1 0 0 0 ATU-II Don’t care* Don’t care* 1 ATU-II Don’t care* Don’t care* 1 0 ATU-II Don’t care* Don’t care* 1 ATU-II Don’t care* Don’t care* 1 0 0 ATU-II Don’t care* Don’t care* Rev. 3.0, 09/04, page 181 of 1086 Legend: SCI0, SCI1, SCI2, SCI3, SCI4: Serial communication interface channels 0–4 A/D0, A/D1, A/D2: A/D converter channels 0–2 HCAN0: Controller area network-II channel 0 ATU-II: Advanced timer unit TDR0, TDR1, TDR2, TDR3, TDR4: SCI0–SCI4 transmit data registers RDR0, RDR1, RDR2, RDR3, RDR4: SCI0–SCI4 receive data registers ADDR0–ADDR11: A/D0 data registers ADDR12–ADDR23: A/D1 data registers ADDR24–ADDR31: A/D2 data registers MB0–MB15: HCAN0 message data Note: * External memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding DMAC, BSC, and UBC) 10.3.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to the following priority order: • CH0 > CH1 > CH2 > CH3 10.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 10.3. It operates in dual address mode, in which both the transfer source and destination addresses are output. The dual address mode consists of a direct address mode, in which the output address value is the object of a direct data transfer, and an indirect address mode, in which the output address value is not the object of the data transfer, but the value stored at the output address becomes the transfer object address. The actual transfer operation timing varies with the bus mode. The DMAC has two bus modes: cycle-steal mode and burst mode. Table 10.3 Supported DMA Transfers Transfer Destination Transfer Source External memory Memory-mapped external device On-chip memory On-chip peripheral module External Memory Supported Supported Supported Supported Memory-Mapped External Device Supported Supported Supported Supported On-Chip Memory Supported Supported Supported Supported On-Chip Peripheral Module Supported Supported Supported Supported Rev. 3.0, 09/04, page 182 of 1086 10.3.5 Dual Address Mode Dual address mode is used for access of both the transfer source and destination by address. Transfer source and destination can be accessed either internally or externally. Dual address mode is subdivided into two other modes: direct address transfer mode and indirect address transfer mode. Direct Address Transfer Mode: Data is read from the transfer source during the data read cycle, and written to the transfer destination during the write cycle, so transfer is conducted in two bus cycles. At this time, the transfer data is temporarily stored in the DMAC. With the kind of external memory transfer shown in figure 10.3, data is read from one of the memories by the DMAC during a read cycle, then written to the other external memory during the subsequent write cycle. Figure 10.4 shows the timing for this operation. Rev. 3.0, 09/04, page 183 of 1086 1st bus cycle DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The SAR value is taken as the address, and data is read from the transfer source module and stored temporarily in the DMAC. 2nd bus cycle DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The DAR value is taken as the address, and data stored in the DMAC's data buffer is written to the transfer destination module. Figure 10.3 Direct Address Operation in Dual Address Mode Rev. 3.0, 09/04, page 184 of 1086 CK Transfer source address Transfer destination address A21–A0 CSn D15–D0 RD WRH, WRL Figure 10.4 Direct Address Transfer Timing in Dual Address Mode Indirect Address Transfer Mode: In this mode the memory address storing the data actually to be transferred is specified in the DMAC internal transfer source address register (SAR3). Therefore, in indirect address transfer mode, the DMAC internal transfer source address register value is read first. This value is first stored in the DMAC. Next, the read value is output as the address, and the value stored at that address is again stored in the DMAC. Finally, the subsequent read value is written to the address specified by the transfer destination address register, ending one cycle of DMAC transfer. In indirect address mode (figure 10.5), the transfer destination, transfer source, and indirect address storage destination are all 16-bit external memory locations, and transfer in this example is conducted in 16-bit or 8-bit units. Timing for this transfer example is shown in figure 10.6. In indirect address mode, one NOP cycle (figure 10.6) is required until the data read as the indirect address is output to the address bus. When transfer data is 32-bit, the third and fourth bus cycles each need to be doubled, giving a required total of six bus cycles and one NOP cycle for the whole operation. Rev. 3.0, 09/04, page 185 of 1086 1st and 2nd bus cycles DMAC SAR3 Memory Data bus DAR3 Temporary buffer Data buffer Address bus Transfer source module Transfer destination module The SAR3 value is taken as the address, memory data is read, and the value is stored in the temporary buffer. Since the value read at this time is used as the address, it must be 32 bits. If data bus is 16 bits wide when accessed to an external memory space, two bus cycles are necessary. 3rd bus cycle DMAC SAR3 DAR3 Temporary buffer Data buffer Memory Address bus Data bus Transfer source module Transfer destination module The value in the temporary buffer is taken as the address, and data is read from the transfer source module to the data buffer. 4th bus cycle DMAC SAR3 DAR3 Temporary buffer Data buffer Memory Address bus Data bus Transfer source module Transfer destination module The DAR3 value is taken as the address, and the value in the data buffer is written to the transfer destination module. Note: Memory, transfer source, and transfer destination modules are shown here. In practice, any connection can be made as long as it is within the address space. Figure 10.5 Dual Address Mode and Indirect Address Operation (16-Bit-Width External Memory Space) Rev. 3.0, 09/04, page 186 of 1086 CK A21–A0 Transfer source address (H) Transfer source address (L) Indirect address Transfer destination address NOP CSn D15–D0 Internal address bus Internal data bus DMAC indirect address buffer DMAC data buffer RD WRH, WRL Indirect address (H) Indirect address (L) Transfer data Indirect address Transfer data Transfer data Transfer source address ∗1 NOP Indirect address ∗2 Transfer data Indirect address Transfer data Address read cycle NOP cycle Data read cycle (3rd) Data write cycle (4th) (1st) (2nd) Notes: 1. The internal address bus is controlled by the port and does not change. 2. The DMAC does not latch the value until 32-bit data is read from the internal data bus. Figure 10.6 Dual Address Mode and Indirect Address Transfer Timing Example 1 External Memory Space → External Memory Space (External memory space has 16-bit width) Rev. 3.0, 09/04, page 187 of 1086 Figure 10.7 shows an example of timing in indirect address mode when transfer source and indirect address storage locations are in internal memory, the transfer destination is an on-chip peripheral module with 2-cycle access space, and transfer data is 8-bit. Since the indirect address storage destination and the transfer source are in internal memory, these can be accessed in one cycle. The transfer destination is 2-cycle access space, so two data write cycles are required. One NOP cycle is required until the data read as the indirect address is output to the address bus. CK Internal address bus Transfer source address NOP Indirect address Transfer destination address Internal data bus DMAC indirect address buffer DMAC data buffer Indirect address NOP Transfer data Transfer data Indirect address Transfer data Address read cycle (1st) NOP cycle (2nd) Data read cycle (3rd) Data write cycle (4th) Figure 10.7 Dual Address Mode and Indirect Address Transfer Timing Example 2 Internal Memory Space → Internal Memory Space Rev. 3.0, 09/04, page 188 of 1086 10.3.6 Bus Modes Select the appropriate bus mode in the TM bits of CHCR0–CHCR3. There are two bus modes: cycle-steal and burst. Cycle-Steal Mode: In cycle-steal mode, the bus right is given to another bus master after each one-transfer-unit (8-bit, 16-bit, or 32-bit) DMAC transfer. When the next transfer request occurs, the bus right is obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. Cycle-steal mode can be used with all categories of transfer destination, transfer source and transfer request. Figure 10.8 shows an example of DMA transfer timing in cycle-steal mode. Bus control returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read/Write CPU DMAC DMAC CPU Read/Write CPU Figure 10.8 DMA Transfer Timing Example in Cycle-Steal Mode Burst Mode: Once the bus right is obtained, transfer is performed continuously until the transfer end condition is satisfied. Figure 10.9 shows an example of DMA transfer timing in burst mode. Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC Read/Write Read/Write Read/Write CPU Figure 10.9 DMA Transfer Timing Example in Burst Mode Rev. 3.0, 09/04, page 189 of 1086 10.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category Table 10.4 shows the relationship between request modes and bus modes by DMA transfer category. Table 10.4 Relationship between Request Modes and Bus Modes by DMA Transfer Category Address Mode Transfer Category Dual Request Mode 1 1 Bus Mode B/C B/C B/C B/C B/C* B/C B/C* B/C B/C* B/C* 3 3 3 Transfer Usable Size (Bits) Channels 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32* 8/16/32 8/16/32* 8/16/32 8/16/32* 8/16/32* 4 4 4 External memory and external memory Any* External memory and memory-mapped Any* external device Memory-mapped external device and memory-mapped external device External memory and on-chip memory External memory and on-chip peripheral module Memory-mapped external device and on-chip memory Memory-mapped external device and on-chip peripheral module On-chip memory and on-chip memory On-chip memory and on-chip peripheral module On-chip peripheral module and onchip peripheral module Any* Any* Any* Any* Any* Any* Any* Any* 0–3 0–3 0–3 0–3 0–3 0–3 0–3 0–3 0–3 0–3 1 1 2 1 2 1 2 2 3 4 B: Burst, C: Cycle-steal Notes: 1. Auto-request or on-chip peripheral module request enabled. However, in the case of an on-chip peripheral module request, it is not possible to specify the SCI, HCAN0, or A/D converter for the transfer request source. 2. Auto-request or on-chip peripheral module request possible. However, if the transfer request source is also the SCI, HCAN0, or A/D converter, the transfer source or transfer destination must be same as the transfer source. 3. When the transfer request source is the SCI, only cycle-steal mode is possible. 4. Access size permitted by the on-chip peripheral module register that is the transfer source or transfer destination. Rev. 3.0, 09/04, page 190 of 1086 10.3.8 Bus Mode and Channel Priorities If, for example, a transfer request is issued for channel 0 while transfer is in progress on lowerpriority channel 1 in burst mode, transfer is started immediately on channel 0. In this case, if channel 0 is set to burst mode, channel 1 transfer is continued after completion of all transfers on channel 0. If channel 0 is set to cycle-steal mode, channel 1 transfer is continued only if a channel 0 transfer request has not been issued; if a transfer request is issued, channel 0 transfer is started immediately. 10.3.9 Source Address Reload Function Channel 2 has a source address reload function. This returns to the first value set in the source address register (SAR2) every four transfers by setting the RO bit of CHCR2 to 1. Figure 10.10 illustrates this operation. Figure 10.11 is a timing chart for use of channel 2 only with the following transfer conditions set: burst mode, auto-request, 16-bit transfer data size, SAR2 incremented, DAR2 fixed, reload function on. DMAC DMAC control block RO bit = 1 CHCR2 Reload control Reload signal SAR2 (initial value) Reload signal 4th count SAR2 Figure 10.10 Source Address Reload Function Rev. 3.0, 09/04, page 191 of 1086 Address bus Transfer request Count signal DMATCR2 CK Internal address bus Internal data bus SAR2 DAR2 SAR2+2 DAR2 SAR2+4 DAR2 SAR2+6 DAR2 SAR2 DAR2 SAR2 data SAR2+2 data SAR2+4 data SAR2+6 data SAR2 data 1st channel 2 transfer SAR2 output DAR2 output 2nd channel 2 transfer SAR2+2 output DAR2 output 3rd channel 2 transfer SAR2+4 output DAR2 output 4th channel 2 transfer SAR2+6 output DAR2 output 5th channel 2 transfer SAR2 output DAR2 output After SAR2+6 output, SAR2 is reloaded Bus right is returned one time in four Figure 10.11 Source Address Reload Function Timing Chart The reload function can be executed whether the transfer data size is 8, 16, or 32 bits. DMATCR2, which specifies the number of transfers, is decremented by 1 at the end of every single-transfer-unit transfer, regardless of whether the reload function is on or off. Therefore, when using the reload function in the on state, a multiple of 4 must be specified in DMATCR2. Operation will not be guaranteed if any other value is set. Also, the counter which counts the occurrence of four transfers for address reloading is reset by clearing of the DME bit in DMAOR or the DE bit in CHCR2, setting of the transfer end flag (the TE bit in CHCR2), NMI input, and setting of the AE flag (address error generation in DMAC transfer), as well as by a reset and in software standby mode, but SAR2, DAR2, DMATCR2, and other registers are not reset. Consequently, when one of these sources occurs, there is a mixture of initialized counters and uninitialized registers in the DMAC, and incorrect operation may result if a restart is executed in this state. Therefore, when one of the above sources, other than TE setting, occurs during use of the address reload function, SAR, DAR2, and DMATCR2 settings must be carried out before reexecution. 10.3.10 DMA Transfer Ending Conditions The DMA transfer ending conditions vary for individual channels ending and for all channels ending together. Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when the value of the channel’s DMA transfer count register (DMATCR) is 0, or when the DE bit of the channel’s CHCR is cleared to 0. Rev. 3.0, 09/04, page 192 of 1086 • When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's DMA transfer ends, the transfer end flag bit (TE) is set in CHCR. If the IE (interrupt enable) bit has been set, a DMAC interrupt (DEI) request is sent to the CPU. • When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the channel’s CHCR. The TE bit is not set when this happens. Conditions for Ending on All Channels Simultaneously: Transfers on all channels end when the NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in DMAOR, or when the DME bit in DMAOR is cleared to 0. • When the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or DMAC address error occurs, the NMIF or AE bit is set to 1 in DMAOR and all channels stop their transfers. The DMAC obtains the bus right, and if these flags are set to 1 during execution of a transfer, DMAC halts operation when the transfer processing currently being executed ends, and transfers the bus right to the other bus master. Consequently, even if the NMIF or AE bit is set to 1 during a transfer, the DMA source address register (SAR), designation address register (DAR), and transfer count register (DMATCR) are all updated. The TE bit is not set. To resume the transfers after NMI interrupt or address error processing, the NMIF or AE flag must be cleared. To avoid restarting a transfer on a particular channel, clear its DE bit to 0 in CHCR. When the processing of a one-unit transfer is complete: In a dual address mode direct address transfer, even if an address error occurs or the NMI flag is set during read processing, the transfer will not be halted until after completion of the following write processing. In such a case, SAR, DAR, and DMATCR values are updated. In the same manner, the transfer is not halted in indirect address transfers until after the final write processing has ended. • When DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in DMAOR aborts the transfers on all channels. The TE bit is not set. 10.3.11 DMAC Access from CPU The space addressed by the DMAC is 4-cycle space. Therefore, when the CPU becomes the bus master and accesses the DMAC, a minimum of four internal clock cycles (φ) are required for one bus cycle. Also, since the DMAC is located in word space, while a word-size access to the DMAC is completed in one bus cycle, a longword-size access is automatically divided into two word accesses, requiring two bus cycles (eight basic clock cycles). These two bus cycles are executed consecutively; a different bus cycle is never inserted between the two word accesses. This applies to both write accesses and read accesses. Rev. 3.0, 09/04, page 193 of 1086 10.4 10.4.1 Examples of Use Example of DMA Transfer between On-Chip SCI and External Memory In this example, on-chip serial communication interface channel 0 (SCI0) receive data is transferred to external memory using DMAC channel 0. Table 10.5 indicates the transfer conditions and the set values of each of the registers. Table 10.5 Transfer Conditions and Register Set Values for Transfer between On-chip SCI and External Memory Transfer Conditions Transfer source: RDR0 of on-chip SCI0 Transfer destination: external memory Transfer count: 64 times Transfer source address: fixed Transfer destination address: incremented Transfer request source: SCI0 (RDR0) Bus mode: cycle-steal Transfer unit: byte Interrupt request generation at end of transfer DMAC master enable on DMAOR H'0001 Register SAR0 DAR0 DMATCR0 CHCR0 Value H'FFFFF005 H'00400000 H'00000040 H'00020105 10.4.2 Example of DMA Transfer between A/D Converter and On-Chip Memory (Address Reload On) In this example, on-chip A/D converter channel 0 is the transfer source and on-chip memory is the transfer destination, and the address reload function is on. Table 10.6 indicates the transfer conditions and the set values of each of the registers. Rev. 3.0, 09/04, page 194 of 1086 Table 10.6 Transfer Conditions and Register Set Values for Transfer between A/D Converter and On-Chip Memory Transfer Conditions Transfer source: on-chip A/D converter ch1 (A/D1) Transfer destination: on-chip memory Transfer count: 128 times (reload count 32 times) Transfer source address: incremented Transfer destination address: incremented Transfer request source: A/D converter ch1 (A/D1) Bus mode: burst Transfer unit: byte Interrupt request generation at end of transfer DMAC master enable on DMAOR H'0001 Register SAR2 DAR2 DMATCR2 CHCR2 Value H'FFFFF820 H'FFFF6000 H'00000080 H'010C110D When address reload is on, the SAR2 value returns to its initially set value every four transfers. In the above example, when a transfer request is input from the A/D1, the byte-size data is first read in from the H'FFFFF820 register of on-chip A/D1 and that data is written to internal address H'FFFF6000. Because a byte-size transfer was performed, the SAR2 and DAR2 values at this point are H'FFFFF821 and H'FFFF6001, respectively. Also, because this is a burst transfer, the bus right remains secured, so continuous data transfer is possible. When four transfers are completed, if address reload is off, execution continues with the fifth and sixth transfers and the SAR2 value continues to increment from H'FFFFF824 to H'FFFFF825 to H'FFFFF826 and so on. However, when address reload is on, DMAC transfer is halted upon completion of the fourth transfer and the bus right request signal to the CPU is cleared. At this time, the value stored in SAR2 is not H'FFFFF823 → H'FFFFF824, but H'FFFFF823 → H'FFFFF820, a return to the initially set address. The DAR2 value always continues to be decremented regardless of whether address reload is on or off. The DMAC internal status, due to the above operation after completion of the fourth transfer, is indicated in table 10.7 for both address reload on and off. Rev. 3.0, 09/04, page 195 of 1086 Table 10.7 DMAC Internal Status Item SAR2 DAR2 DMATCR2 Bus right DMAC operation Interrupts Transfer request source flag clear Address Reload On H'FFFFF820 H'FFFF6004 H'0000007C Released Halted Not issued Executed Address Reload Off H'FFFFF824 H'FFFF6004 H'0000007C Retained Processing continues Not issued Not executed Notes: 1. Interrupts are executed until the DMATCR2 value becomes 0, and if the IE bit of CHCR2 is set to 1, are issued regardless of whether address reload is on or off. 2. If transfer request source flag clears are executed until the DMATCR2 value becomes 0, they are executed regardless of whether address reload is on or off. 3. Designate burst mode when using the address reload function. There are cases where abnormal operation will result if it is used in cycle-steal mode. 4. Designate a multiple of four for the DMATCR2 value when using the address reload function. There are cases where abnormal operation will result if anything else is designated. To execute transfers after the fifth transfer when address reload is on, have the transfer request source issue another transfer request signal. 10.4.3 Example of DMA Transfer between External Memory and SCI1 Transmitting Side (Indirect Address on) In this example, DMAC channel 3 is used, indirect address designated external memory is the transfer source, and the SCI1 transmitting side is the transfer destination. Table 10.8 indicates the transfer conditions and the set values of each of the registers. Rev. 3.0, 09/04, page 196 of 1086 Table 10.8 Transfer Conditions and Register Set Values for Transfer between External Memory and SCI1 Transmitting Side Transfer Conditions Transfer source: external memory Value stored in address H'00400000 Value stored in address H'00450000 Transfer destination: on-chip SCI TDR1 Transfer count: 10 times Transfer source address: incremented Transfer destination address: fixed Transfer request source: SCI1 (TDR1) Bus mode: cycle-steal Transfer unit: byte Interrupt request not generated at end of transfer DMAC master enable on DMAOR H'0001 Register SAR3 — — DAR3 DMATCR3 CHCR3 Value H'00400000 H'00450000 H'55 H'FFFFF00B H'0000000A H'10031001 When indirect address mode is on, the data stored in the address set in SAR is not used as the transfer source data. In the case of indirect addressing, the value stored in the SAR address is read, then that value is used as the address and the data read from that address is used as the transfer source data, then that data is stored in the address designated by DAR. In the table 10.8 example, when a transfer request from TDR1 of SCI1 is generated, a read of the address located at H'00400000, which is the value set in SAR3, is performed first. The data H'00450000 is stored at this H'00400000 address, and the DMAC first reads this H'00450000 value. It then uses this read value of H'00450000 as an address and reads the value of H'55 that is stored in the H'00450000 address. It then writes the value H'55 to address H'FFFFF00B designated by DAR3 to complete one indirect address transfer. With indirect addressing, the first executed data read from the address set in SAR3 always results in a longword size transfer regardless of the TS0 and TS1 bit designations for transfer data size. However, the transfer source address fixed and increment or decrement designations are according to the SM0 and SM1 bits. Consequently, despite the fact that the transfer data size designation is byte in this example, the SAR3 value at the end of one transfer is H'00400004. The write operation is exactly the same as an ordinary dual address transfer write operation. Rev. 3.0, 09/04, page 197 of 1086 10.5 Usage Notes 1. Only word (16-bit) access can be used on the DMA operation register (DMAOR). All other registers can be accessed in word (16-bit) or longword (32-bit) units. 2. When rewriting the RS0–RS4 bits of CHCR0–CHCR3, first clear the DE bit to 0 (clear the DE bit to 0 before modifying CHCR). 3. When an NMI interrupt is input, the NMIF bit of DMAOR is set even when the DMAC is not operating. 4. Clear the DME bit of DMAOR to 0 and make certain that any transfer request processing accepted by the DMAC has been completed before entering standby mode. 5. Do not access the DMAC, BSC, or UBC on-chip peripheral modules from the DMAC. 6. When activating the DMAC, make the CHCR settings as the final step. Abnormal operation may result if any other registers are set last. 7. After the DMATCR count becomes 0 and the DMA transfer ends normally, always write 0 to DMATCR, even when executing the maximum number of transfers on the same channel. Abnormal operation may result if this is not done. 8. Designate burst mode as the transfer mode when using the address reload function. Abnormal operation may result in cycle-steal mode. 9. Designate a multiple of four for the DMATCR value when using the address reload function, otherwise abnormal operation may result. 10. Do not access empty DMAC register addresses. Operation cannot be guaranteed when empty addresses are accessed. 11. If DMAC transfer is aborted by NMIF or AE setting, or DME or DE clearing, during DMAC execution with address reload on, the SAR2, DAR2, and DMATCR2 settings should be made before re-executing the transfer. The DMAC may not operate correctly if this is not done. 12. Do not set the DE bit to 1 while bits RS0 to RS4 in CHCR0 to CHCR3 are still set to “no request.” Rev. 3.0, 09/04, page 198 of 1086 Section 11 Advanced Timer Unit-II (ATU-II) 11.1 Overview The SH7058 has an on-chip advanced timer unit-II (ATU-II) with one 32-bit timer channel and eleven 16-bit timer channels. 11.1.1 Features ATU-II features are summarized below. • Capability to process up to 65 pulse inputs and outputs • Prescaler  Input clock to channels 0 and 10 scaled in 1 stage, input clock to channels 1 to 8 and 11 scaled in 2 stages  1/1 to 1/32 clock scaling possible in initial stage for channels 0 to 8, 10, and 11  1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 scaling possible in second stage for channels 1 to 8 and 11  External clock TCLKA, TCLKB selection also possible for channels 1 to 5 and 11  TI10, TI10 multiplication (compensation) selection possible for channels 1 to 5: AGCK, AGCKM • Channel 0 has four 32-bit input capture lines, allowing the following operations:  Rising-edge, falling-edge, or both-edge detection selectable  DMAC can be activated at capture timing  Channel 10 compare-match signal can be captured as a trigger  Interval interrupt generation function generates three interval interrupts as selected. CPU interruption or A/D converter (AD0, 1, 2) activation possible  Capture interrupt and counter overflow interrupt can be generated • Channel 1 has one 16-bit output compare register, eight general registers, and one dedicated input capture register. The output compare register can also be selected for one-shot pulse offset in combination with the channel 8 down-counter.  General registers (GR1A–H) can be used as input capture or output compare registers  Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output  Input capture function: Rising-edge, falling-edge, or both-edge detection  Channel 0 input signal (TI0A) can be captured as trigger  Provision for forcible cutoff of channel 8 down-counters (DCNT8A–H)  Compare-match interrupts/capture interrupts and counter overflow interrupts can be generated Rev. 3.0, 09/04, page 199 of 1086 • Channel 2 has eight 16-bit output compare registers, eight general registers, and one dedicated input capture register. The output compare registers can also be selected for one-shot pulse offset in combination with the channel 8 down-counter.  General registers (GR2A–H) can be used as input capture or output compare registers  Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output  Input capture function: Rising-edge, falling-edge, or both-edge detection  Channel 0 input signal (TI0A) can be captured as trigger  Provision for forcible cutoff of channel 8 down-counters (DCNT8I–P)  Compare-match interrupts/capture interrupts and counter overflow interrupts can be generated • Channels 3 to 5 each have four general registers, allowing the following operations:  Selection of input capture, output compare, PWM mode  Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output  Input capture function: Rising-edge, falling-edge, or both-edge detection  Channel 9 compare-match signal can be captured as trigger (channel 3 only)  Compare-match interrupts/capture interrupts can be generated • Channels 6 and 7 have four 16-bit duty registers, four cycle registers, and four buffer registers, allowing the following operations:  Any cycle and duty from 0 to 100% can be set  Duty buffer register value transferred to duty register every cycle  Interrupts can be generated every cycle  Complementary PWM output can be set (channel 6 only) • Channel 8 has sixteen 16-bit down-counters for one-shot pulse output, allowing the following operations:  One-shot pulse generation by down-counter  Down-counter can be rewritten during count  Interrupt can be generated at end of down-count  Offset one-shot pulse function available  Can be linked to channel 1 and 2 output compare functions  Reload function can be set to eight 16-bit down-counters (DCNT8I to DCNT8P) • Channel 9 has six event counters and six general registers, allowing the following operations:  Event counters can be cleared by compare-match  Rising-edge, falling-edge, or both-edge detection available for external input  Compare-match signal can be input to channel 3 • Channel 10 has a 32-bit output compare and input capture register, free-running counter, 16-bit free-running counter, output compare/input capture register, reload register, 8-bit event Rev. 3.0, 09/04, page 200 of 1086 counter, and output compare register, and 16-bit reload counter, allowing the following operations:  Capture on external input pin edge input  Reload count possible with 1/32, 1/64, 1/128, or 1/256 times the captured value  Internal clock generated by reload counter underflow can be used as 16-bit free-running counter input  Channel 1 and 2 free-running counter clearing capability • Channel 11 has one 16-bit free-running counter and two 16-bit general registers, allowing the following operations:  Two general registers can be used for input capture/output compare  Waveform output at compare-match: Selection of 0, 1, or toggle output  Input capture function: Selection of rising edge, falling edge, or both edge detection  Compare-match signal can be output to APC by using a general register as an output compare register • High-speed access to internal 16-bit bus  High-speed access to 16-bit bus for 16-bit registers: timer counters, compare registers, and capture registers • 75 interrupt sources  Four input capture interrupt requests, one overflow interrupt request, and one interval interrupt request for channel 0  Sixteen dual input capture/compare-match interrupt requests and two counter overflow interrupt requests for channels 1 and 2  Twelve dual input capture/compare-match interrupt requests and three overflow interrupt requests for channels 3 to 5  Eight compare-match interrupts for channels 6 and 7  Sixteen one-shot end interrupt requests for channel 8  Six compare-match interrupts for channel 9  Two compare-match interrupts and one dual-function input capture/compare-match interrupt for channel 10  Two dual input capture/compare-match interrupt requests and one overflow interrupt request for channel 11 • Direct memory access controller (DMAC) activation  The DMAC can be activated by a channel 0 input capture interrupt (ICI0A–D)  The DMAC can be activated by a channel 6 cycle register 6 compare-match interrupt (CMI6A–D)  The DMAC can be activated by a channel 7 cycle register 7 compare-match interrupt (CMI7A–D) • A/D converter activation Rev. 3.0, 09/04, page 201 of 1086  The A/D converter can be activated by detection of 1 in bits ITVA6–13 of the channel 0 interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B) Table 11.1 lists the functions of the ATU-II. Table 11.1 ATU-II Functions Item Counter configuration Clock sources Channel 0 φ–φ/32 Channel 1 (φ–φ/32) × (1/2 ) n Channel 2 (φ–φ/32) × (1/2 ) n Channels 3–5 (φ–φ/32) × (1/2n ) (n = 0–5) TCLKA, TCLKB, AGCK, AGCKM TCNT3–5 GR3A–D, GR4A–D, GR5A–D — (n = 0–5) TCLKA, TCLKB, AGCK, AGCKM (n = 0–5) TCLKA, TCLKB, AGCK, AGCKM TCNT2A, TCNT2B GR2A–H OSBR2 Counters General registers Dedicated input capture Dedicated output compare PWM output TCNT0H, TCNT0L — ICR0AH, ICR0AL, ICR0BH, ICR0BL, ICR0CH, ICR0CL, ICR0DH, ICR0DL — TCNT1A, TCNT1B GR1A–H OSBR1 OCR1 OCR2A–2H — — — — Duty: GR3A–C, GR4A–C, GR5A–C Cycle: GR3D, GR4D, GR5D Input pins I/O pins Output pins Counter clearing function Interrupt sources TI0A–D — — — 6 sources Interval × 1, input capture × 4, overflow × 1 — TIO1A–H — — 9 sources — TIO2A–H — — 9 sources — TIO3A–D, TIO4A–D, TIO5A–D — O 15 sources Dual input capture/ Dual input capture/ Dual input capture/ compare-match × 8, compare-match × 8, compare-match × 12, overflow × 1 overflow × 1* overflow × 3 (* Same vector) Inter-channel and inter-module connection signals A/D converter activation by interval interrupt request, DMAC activation by input capture interrupt, channel 10 compare-match signal capture trigger input Compare-match signal trigger output to channel 8 one-shot pulse output down-counter Compare-match signal trigger output to channel 8 one-shot pulse output down-counter Channel 9 comparematch signal input to capture trigger (Channel 3 only) Channel 10 compare- Channel 10 comparematch signal counter match signal counter clear input clear input Rev. 3.0, 09/04, page 202 of 1086 Table 11.1 ATU-II Functions (cont) Item Counter configuration Clock sources Channels 6, 7 (φ–φ/32) × (1/2n) (n = 0–5) Counters TCNT6A–D, TCNT7A–D — — Channel 8 (φ–φ/32) × (1/2n) (n = 0–5) DCNT8A–P ECNT9A–F TCNT10AH, TCNT10AL, TCNT10B–H — ICR10AH, ICR10AL GR10G, OCR/0AH, OCR/0AL, OCR/0B, NCR10, TCCLR10 — Channel 9 — Channel 10 (φ–φ/32) Channel 11 (φ–φ/32) × (1/2n) (n = 0-5) TCLKA, TCLKB TCNT11 General registers Dedicated input capture Dedicated output compare — — — — GR11A, GR11B — — — GR9A–F — PWM output CYLR6A–D, CYLR7A–D, DTR6A–D, DTR7A–D, BFR6A–D, BFR7A–D — — TO6A–D, TO7A–D O 8 sources — — — Input pins I/O pins Output pins Counter clearing function Interrupt sources — — TO8A–P — 16 sources TI9A–F — — O 6 sources TI10 — — O 3 sources — TIO11A, TIO11B — — 3 sources Dual input capture/compare match × 2, overflow × 1 Compare-match Underflow × 16 ×8 Compare-match Compare-match ×6 × 2, dual input capture/compare -match × 1 Compare-match signal channel 3 capture trigger output Inter-channel and inter-module connection signals DMAC activation Channel 1 and 2 compare-match compare-match signal output signal trigger input to one-shot pulse output down-counter Compare-match Compare-match signal channel 0 signal output to capture trigger APC output Channel 1 and 2 counter clear output O: Available —: Not available Rev. 3.0, 09/04, page 203 of 1086 11.1.2 Pin Configuration Table 11.2 shows the pin configuration of the ATU-II. When these external pin functions are used, the pin function controller (PFC) should also be set in accordance with the ATU-II settings. If there are a number of pins with the same function, make settings so that only one of the pins is used. For details, see section 21, Pin Function Controller (PEC). Table 11.2 ATU-II Pins Channel Common Name Clock input A Clock input B 0 Input capture 0A Input capture 0B Input capture 0C Input capture 0D 1 Input capture/output compare 1A Input capture/output compare 1B Input capture/output compare 1C Input capture/output compare 1D Input capture/output compare 1E Input capture/output compare 1F Input capture/output compare 1G Input capture/output compare 1H Abbreviation TCLKA TCLKB TI0A TI0B TI0C TI0D TIO1A TIO1B TIO1C TIO1D TIO1E TIO1F TIO1G TIO1H I/O Input Input Input Input Input Input Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Function External clock A input pin External clock B input pin ICR0AH, ICR0AL input capture input pin ICR0BH, ICR0BL input capture input pin ICR0CH, ICR0CL input capture input pin ICR0DH, ICR0DL input capture input pin GR1A output compare output/input capture input GR1B output compare output/input capture input GR1C output compare output/input capture input GR1D output compare output/input capture input GR1E output compare output/input capture input GR1F output compare output/input capture input GR1G output compare output/input capture input GR1H output compare output/input capture input Rev. 3.0, 09/04, page 204 of 1086 Table 11.2 ATU-II Pins (cont) Channel 2 Name Input capture/output compare 2A Input capture/output compare 2B Input capture/output compare 2C Input capture/output compare 2D Input capture/output compare 2E Input capture/output compare 2F Input capture/output compare 2G Input capture/output compare 2H 3 Input capture/output compare 3A Input capture/output compare 3B Input capture/output compare 3C Input capture/output compare 3D 4 Input capture/output compare 4A Input capture/output compare 4B Input capture/output compare 4C Input capture/output compare 4D Abbreviation TIO2A TIO2B TIO2C TIO2D TIO2E TIO2F TIO2G TIO2H TIO3A I/O Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Function GR2A output compare output/input capture input GR2B output compare output/input capture input GR2C output compare output/input capture input GR2D output compare output/input capture input GR2E output compare output/input capture input GR2F output compare output/input capture input GR2G output compare output/input capture input GR2H output compare output/input capture input GR3A output compare output/input capture input/PWM output pin (PWM mode) GR3B output compare output/input capture input/PWM output pin (PWM mode) GR3C output compare output/input capture input/PWM output pin (PWM mode) GR3D output compare output/input capture input GR4A output compare output/input capture input/PWM output pin (PWM mode) GR4B output compare output/input capture input/PWM output pin (PWM mode) GR4C output compare output/input capture input/PWM output pin (PWM mode) GR4D output compare output/input capture input TIO3B TIO3C TIO3D TIO4A TIO4B TIO4C TIO4D Rev. 3.0, 09/04, page 205 of 1086 Table 11.2 ATU-II Pins (cont) Channel 5 Name Input capture/output compare 5A Input capture/output compare 5B Input capture/output compare 5C Input capture/output compare 5D 6 Output compare 6A Output compare 6B Output compare 6C Output compare 6D 7 Output compare 7A Output compare 7B Output compare 7C Output compare 7D 8 One-shot pulse 8A One-shot pulse 8B One-shot pulse 8C One-shot pulse 8D One-shot pulse 8E One-shot pulse 8F One-shot pulse 8G One-shot pulse 8H One-shot pulse 8I One-shot pulse 8J One-shot pulse 8K One-shot pulse 8L One-shot pulse 8M One-shot pulse 8N Abbreviation TIO5A I/O Input/ output Input/ output Input/ output Input/ output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Function GR5A output compare output/input capture input/PWM output pin (PWM mode) GR5B output compare output/input capture input/PWM output pin (PWM mode) GR5C output compare output/input capture input/PWM output pin (PWM mode) GR5D output compare output/input capture input PWM output pin PWM output pin PWM output pin PWM output pin PWM output pin PWM output pin PWM output pin PWM output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin One-shot pulse output pin TIO5B TIO5C TIO5D TO6A TO6B TO6C TO6D TO7A TO7B TO7C TO7D TO8A TO8B TO8C TO8D TO8E TO8F TO8G TO8H TO8I TO8J TO8K TO8L TO8M TO8N Rev. 3.0, 09/04, page 206 of 1086 Table 11.2 ATU-II Pins (cont) Channel 8 Name One-shot pulse 8O One-shot pulse 8P 9 Event input 9A Event input 9B Event input 9C Event input 9D Event input 9E Event input 9F 10 11 Input capture Input capture/output compare 11A Input capture/output compare 11B Abbreviation TO8O TO8P TI9A TI9B TI9C TI9D TI9E TI9F TI10 TIO11A TIO11B I/O Output Output Input Input Input Input Input Input Input Input/ output Input/ output Function One-shot pulse output pin One-shot pulse output pin GR9A event input GR9B event input GR9C event input GR9D event input GR9E event input GR9F event input ICR10AH, ICR10AL input capture input GR11A output compare output/input capture input GR11B output compare output/input capture input Rev. 3.0, 09/04, page 207 of 1086 11.1.3 Register Configuration Table 11.3 summarizes the ATU-II registers. Table 11.3 ATU-II Registers Channel Name Common Timer start register 1 Timer start register 2 Timer start register 3 Prescaler register 1 Prescaler register 2 Prescaler register 3 Prescaler register 4 0 Free-running counter 0H Free-running counter 0L Input capture register 0AH Input capture register 0AL Input capture register 0BH Input capture register 0BL Input capture register 0CH Input capture register 0CL Input capture register 0DH Input capture register 0DL AbbreviaR/W tion TSTR1 TSTR2 TSTR3 PSCR1 PSCR2 PSCR3 PSCR4 TCNT0H TCNT0L ICR0AH ICR0AL ICR0BH ICR0BL ICR0CH ICR0CL ICR0DH ICR0DL R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R/W R/W Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address H'FFFFF401 H'FFFFF400 H'FFFFF402 H'FFFFF404 H'FFFFF406 H'FFFFF408 H'FFFFF40A 32 11.2.15 8 11.2.2 Access Section Size (Bits) No. 8, 16, 32 11.2.1 H'0000 H'FFFFF430 H'0000 H'0000 H'FFFFF434 H'0000 H'0000 H'FFFFF438 H'0000 H'0000 H'FFFFF43C H'0000 H'0000 H'FFFFF420 H'0000 H'00 H'00 H'FFFFF424 H'FFFFF426 11.2.19 Timer interval interrupt ITVRR1 request register 1 Timer interval interrupt ITVRR2A request register 2A 8 11.2.7 Rev. 3.0, 09/04, page 208 of 1086 Table 11.3 ATU-II Registers (cont) Channel Name 0 AbbreviaR/W tion R/W R/W Initial Value H'00 H'00 Address H'FFFFF428 H'FFFFF42A Access Section Size (Bits) No. 8 11.2.7 11.2.4 11.2.5 11.2.6 16 11.2.15 Timer interval interrupt ITVRR2B request register 2B Timer I/O control register TIOR0 Timer status register 0 TSR0 Timer interrupt enable register 0 1 Free-running counter 1A Free-running counter 1B General register 1A General register 1B General register 1C General register 1D General register 1E General register 1F General register 1G General register 1H Output compare register 1 Offset base register 1 Timer I/O control register 1A Timer I/O control register 1B Timer I/O control register 1C Timer I/O control register 1D Timer control register 1A Timer control register 1B TIER0 TCNT1A TCNT1B GR1A GR1B GR1C GR1D GR1E GR1F GR1G GR1H OCR1 OSBR1 TIOR1A TIOR1B TIOR1C TIOR1D TCR1A TCR1B R/(W)* H'0000 H'FFFFF42C 16 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF42E H'0000 H'FFFFF440 H'0000 H'FFFFF442 H'FFFF H'FFFFF444 H'FFFF H'FFFFF446 H'FFFF H'FFFFF448 H'FFFF H'FFFFF44A H'FFFF H'FFFFF44C H'FFFF H'FFFFF44E H'FFFF H'FFFFF450 H'FFFF H'FFFFF452 H'FFFF H'FFFFF454 H'0000 H'FFFFF456 H'00 H'00 H'00 H'00 H'00 H'00 H'FFFFF459 H'FFFFF458 H'FFFFF45B H'FFFFF45A H'FFFFF45D H'FFFFF45C 8, 16 11.2.20 11.2.18 11.2.21 11.2.4 11.2.3 Rev. 3.0, 09/04, page 209 of 1086 Table 11.3 ATU-II Registers (cont) Channel Name 1 Timer status register 1A Timer status register 1B Timer interrupt enable register 1A Timer interrupt enable register 1B Trigger mode register 2 Free-running counter 2A Free-running counter 2B General register 2A General register 2B General register 2C General register 2D General register 2E General register 2F General register 2G General register 2H Output compare register 2A Output compare register 2B Output compare register 2C Output compare register 2D Output compare register 2E Output compare register 2F AbbreviaR/W tion TSR1A TSR1B TIER1A TIER1B TRGMDR TCNT2A TCNT2B GR2A GR2B GR2C GR2D GR2E GR2F GR2G GR2H OCR2A OCR2B OCR2C OCR2D OCR2E OCR2F Initial Value Address Access Section Size (Bits) No. 11.2.5 R/(W)* H'0000 H'FFFFF45E 16 R/(W)* H'0000 H'FFFFF460 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF462 H'0000 H'FFFFF464 H'00 H'FFFFF466 8 16 11.2.6 11.2.8 11.2.15 H'0000 H'FFFFF600 H'0000 H'FFFFF602 H'FFFF H'FFFFF604 H'FFFF H'FFFFF606 H'FFFF H'FFFFF608 H'FFFF H'FFFFF60A H'FFFF H'FFFFF60C H'FFFF H'FFFFF60E H'FFFF H'FFFFF610 H'FFFF H'FFFFF612 H'FFFF H'FFFFF614 H'FFFF H'FFFFF616 H'FFFF H'FFFFF618 H'FFFF H'FFFFF61A H'FFFF H'FFFFF61C H'FFFF H'FFFFF61E 11.2.20 11.2.18 Rev. 3.0, 09/04, page 210 of 1086 Table 11.3 ATU-II Registers (cont) Channel Name 2 Output compare register 2G Output compare register 2H Offset base register 2 Timer I/O control register 2A Timer I/O control register 2B Timer I/O control register 2C Timer I/O control register 2D Timer control register 2A Timer control register 2B Timer status register 2A Timer status register 2B Timer interrupt enable register 2A Timer interrupt enable register 2B 3–5 AbbreviaR/W tion OCR2G OCR2H OSBR2 TIOR2A TIOR2B TIOR2C TIOR2D TCR2A TCR2B TSR2A TSR2B TIER2A TIER2B R/W R/W R R/W R/W R/W R/W R/W R/W Initial Value Address Access Section Size (Bits) No. 16 11.2.18 H'FFFF H'FFFFF620 H'FFFF H'FFFFF622 H'0000 H'FFFFF624 H'00 H'00 H'00 H'00 H'00 H'00 H'FFFFF627 H'FFFFF626 H'FFFFF629 H'FFFFF628 H'FFFFF62B H'FFFFF62A 11.2.21 8, 16 11.2.4 11.2.3 R/(W)* H'0000 H'FFFFF62C 16 R/(W)* H'0000 H'FFFFF62E R/W R/W H'0000 H'FFFFF630 H'0000 H'FFFFF632 16 11.2.5 11.2.6 Timer status register 3 TSR3 Timer interrupt enable register 3 Timer mode register TIER3 TMDR R/(W)* H'0000 H'FFFFF480 R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF482 H'00 H'FFFFF484 11.2.5 11.2.6 8 11.2.9 11.2.15 11.2.20 3 Free-running counter 3 TCNT3 General register 3A General register 3B General register 3C General register 3D GR3A GR3B GR3C GR3D H'0000 H'FFFFF4A0 16 H'FFFF H'FFFFF4A2 H'FFFF H'FFFFF4A4 H'FFFF H'FFFFF4A6 H'FFFF H'FFFFF4A8 Rev. 3.0, 09/04, page 211 of 1086 Table 11.3 ATU-II Registers (cont) Channel Name 3 Timer I/O control register 3A Timer I/O control register 3B AbbreviaR/W tion TIOR3A TIOR3B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'00 Address Access Section Size (Bits) No. 11.2.4 H'FFFFF4AB 8, 16 H'FFFFF4AA H'FFFFF4AC 8 Timer control register 3 TCR3 4 Free-running counter 4 TCNT4 General register 4A General register 4B General register 4C General register 4D Timer I/O control register 4A Timer I/O control register 4B GR4A GR4B GR4C GR4D TIOR4A TIOR4B 11.2.3 11.2.15 11.2.20 H'0000 H'FFFFF4C0 16 H'FFFF H'FFFFF4C2 H'FFFF H'FFFFF4C4 H'FFFF H'FFFFF4C6 H'FFFF H'FFFFF4C8 H'00 H'00 H'00 H'FFFFF4CB 8, 16 H'FFFFF4CA H'FFFFF4CC 8 11.2.4 Timer control register 4 TCR4 5 Free-running counter 5 TCNT5 General register 5A General register 5B General register 5C General register 5D Timer I/O control register 5A Timer I/O control register 5B GR5A GR5B GR5C GR5D TIOR5A TIOR5B 11.2.3 11.2.15 11.2.20 H'0000 H'FFFFF4E0 16 H'FFFF H'FFFFF4E2 H'FFFF H'FFFFF4E4 H'FFFF H'FFFFF4E6 H'FFFF H'FFFFF4E8 H'00 H'00 H'00 H'FFFFF4EB 8, 16 H'FFFFF4EA H'FFFFF4EC 8 16 11.2.4 Timer control register 5 TCR5 6 Free-running counter 6A Free-running counter 6B Free-running counter 6C Free-running counter 6D TCNT6A TCNT6B TCNT6C TCNT6D 11.2.3 11.2.15 H'0001 H'FFFFF500 H'0001 H'FFFFF502 H'0001 H'FFFFF504 H'0001 H'FFFFF506 Rev. 3.0, 09/04, page 212 of 1086 Table 11.3 ATU-II Registers (cont) Channel Name 6 Cycle register 6A Cycle register 6B Cycle register 6C Cycle register 6D Buffer register 6A Buffer register 6B Buffer register 6C Buffer register 6D Duty register 6A Duty register 6B Duty register 6C Duty register 6D Timer control register 6A Timer control register 6B AbbreviaR/W tion CYLR6A CYLR6B CYLR6C CYLR6D BFR6A BFR6B BFR6C BFR6D DTR6A DTR6B DTR6C DTR6D TCR6A TCR6B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address Access Section Size (Bits) No. 16 11.2.22 H'FFFF H'FFFFF508 H'FFFF H'FFFFF50A H'FFFF H'FFFFF50C H'FFFF H'FFFFF50E H'FFFF H'FFFFF510 H'FFFF H'FFFFF512 H'FFFF H'FFFFF514 H'FFFF H'FFFFF516 H'FFFF H'FFFFF518 H'FFFF H'FFFFF51A H'FFFF H'FFFFF51C H'FFFF H'FFFFF51E H'00 H'00 H'FFFFF521 H'FFFFF520 11.2.23 11.2.24 8, 16 11.2.3 Timer status register 6 TSR6 Timer interrupt enable register 6 PWM mode register 7 Free-running counter 7A Free-running counter 7B Free-running counter 7C Free-running counter 7D Cycle register 7A Cycle register 7B Cycle register 7C Cycle register 7D TIER6 PMDR TCNT7A TCNT7B TCNT7C TCNT7D CYLR7A CYLR7B CYLR7C CYLR7D R/(W)* H'0000 H'FFFFF522 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF524 H'00 H'FFFFF526 16 11.2.5 11.2.6 8 16 11.2.10 11.2.15 H'0001 H'FFFFF580 H'0001 H'FFFFF582 H'0001 H'FFFFF584 H'0001 H'FFFFF586 H'FFFF H'FFFFF588 H'FFFF H'FFFFF58A H'FFFF H'FFFFF58C H'FFFF H'FFFFF58E 11.2.22 Rev. 3.0, 09/04, page 213 of 1086 Table 11.3 ATU-II Registers (cont) Channel Name 7 Buffer register 7A Buffer register 7B Buffer register 7C Buffer register 7D Duty register 7A Duty register 7B Duty register 7C Duty register 7D Timer control register 7A Timer control register 7B Timer status register 7 Timer interrupt enable register 7 8 Down-counter 8A Down-counter 8B Down-counter 8C Down-counter 8D Down-counter 8E Down-counter 8F Down-counter 8G Down-counter 8H Down-counter 8I Down-counter 8J Down-counter 8K Down-counter 8L Down-counter 8M Down-counter 8N Down-counter 8O Down-counter 8P AbbreviaR/W tion BFR7A BFR7B BFR7C BFR7D DTR7A DTR7B DTR7C DTR7D TCR7A TCR7B TSR7 TIER7 DCNT8A DCNT8B DCNT8C DCNT8D DCNT8E DCNT8F DCNT8G DCNT8H DCNT8I DCNT8J DCNT8K DCNT8L DCNT8M DCNT8N DCNT8O DCNT8P R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address Access Section Size (Bits) No. 16 11.2.23 H'FFFF H'FFFFF590 H'FFFF H'FFFFF592 H'FFFF H'FFFFF594 H'FFFF H'FFFFF596 H'FFFF H'FFFFF598 H'FFFF H'FFFFF59A H'FFFF H'FFFFF59C H'FFFF H'FFFFF59E H'00 H'00 11.2.24 H'FFFFF5A1 8, 16 H'FFFFF5A0 11.2.3 R/(W)* H'0000 H'FFFFF5A2 16 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF5A4 H'0000 H'FFFFF640 H'0000 H'FFFFF642 H'0000 H'FFFFF644 H'0000 H'FFFFF646 H'0000 H'FFFFF648 H'0000 H'FFFFF64A H'0000 H'FFFFF64C H'0000 H'FFFFF64E H'0000 H'FFFFF650 H'0000 H'FFFFF652 H'0000 H'FFFFF654 H'0000 H'FFFFF656 H'0000 H'FFFFF658 H'0000 H'FFFFF65A H'0000 H'FFFFF65C H'0000 H'FFFFF65E 16 11.2.5 11.2.6 11.2.16 Rev. 3.0, 09/04, page 214 of 1086 Table 11.3 ATU-II Registers (cont) Channel Name 8 Reload register 8 Timer connection register One-shot pulse terminate register Down-count start register AbbreviaR/W tion RLDR8 TCNR OTR DSTR R/W R/W R/W R/W R/W Initial Value Address Access Section Size (Bits) No. 16 11.2.25 11.2.12 11.2.13 11.2.11 8 11.2.3 11.2.5 11.2.6 11.2.14 11.2.17 H'0000 H'FFFFF660 H'0000 H'FFFFF662 H'0000 H'FFFFF664 H'0000 H'FFFFF666 H'00 H'FFFFF668 Timer control register 8 TCR8 Timer status register 8 TSR8 Timer interrupt enable register 8 TIER8 R/(W)* H'0000 H'FFFFF66A 16 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF66C H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'FF H'FF H'FF H'FF H'FF H'FF H'00 H'00 H'00 H'FFFFF66E 8 H'FFFFF680 H'FFFFF682 H'FFFFF684 H'FFFFF686 H'FFFFF688 H'FFFFF68A H'FFFFF68C H'FFFFF68E H'FFFFF690 H'FFFFF692 H'FFFFF694 H'FFFFF696 H'FFFFF698 H'FFFFF69A H'FFFFF69C 8 Reload enable register RLDENR 9 Event counter 9A Event counter 9B Event counter 9C Event counter 9D Event counter 9E Event counter 9F General register 9A General register 9B General register 9C General register 9D General register 9E General register 9F Timer control register 9A Timer control register 9B Timer control register 9C ECNT9A ECNT9B ECNT9C ECNT9D ECNT9E ECNT9F GR9A GR9B GR9C GR9D GR9E GR9F TCR9A TCR9B TCR9C 11.2.20 11.2.3 Timer status register 9 TSR9 Timer interrupt enable register 9 TIER9 R/(W)* H'0000 H'FFFFF69E 16 R/W H'0000 H'FFFFF6A0 11.2.5 11.2.6 Rev. 3.0, 09/04, page 215 of 1086 Table 11.3 ATU-II Registers (cont) Channel Name 10 Free-running counter 10AH Free-running counter 10AL Event counter 10B Reload counter 10C Correction counter 10D Correction angle counter 10E Correction angle counter 10F Free-running counter 10G Input capture register 10AH Input capture register 10AL Output compare register 10AH Output compare register 10AL Output compare register 10B Reload register 10C General register 10G Noise canceler counter 10H Noise canceler register 10 Timer I/O control register 10 Timer control register 10 AbbreviaR/W tion TCNT10AH R/W TCNT10AL R/W TCNT10B TCNT10C TCNT10D TCNT10E TCNT10F R/W R/W R/W R/W R/W Initial Value Address Access Section Size (Bits) No. 11.2.26 H'0000 H'FFFFF6C0 32 H'0001 H'00 H'FFFFF6C4 8 H'0001 H'FFFFF6C6 16 H'00 H'FFFFF6C8 8 H'0000 H'FFFFF6CA 16 H'0001 H'FFFFF6CC H'0000 H'FFFFF6CE H'0000 H'FFFFF6D0 32 H'0000 H'FFFF H'FFFFF6D4 H'FFFF H'FF H'FFFFF6D8 8 TCNT10G R/W ICR10AH ICR10AL R R OCR10AH R/W OCR10AL OCR10B RLD10C GR10G TCNT10H NCR10 TIOR10 TCR10 R/W R/W R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF6DA 16 H'FFFF H'FFFFF6DC H'00 H'FF H'00 H'00 H'FFFFF6DE 8 H'FFFFF6E0 H'FFFFF6E2 H'FFFFF6E4 Rev. 3.0, 09/04, page 216 of 1086 Table 11.3 ATU-II Registers (cont) Channel Name 10 Correction counter clear register 10 Timer status register 10 Timer interrupt enable register 10 11 Free-running counter 11 General register 11A General register 11B Timer I/O control register 11 Timer control register 11 Timer status register 11 Timer interrupt enable register 11 AbbreviaR/W tion TCCLR10 TSR10 TIER10 TCNT11 GR11A GR11B TIOR11 TCR11 TSR11 TIER11 R/W Initial Value Address Access Section Size (Bits) No. 11.2.26 H'0000 H'FFFFF6E6 16 R/(W)* H'0000 H'FFFFF6E8 R/W R/W R/W R/W R/W R/W H'0000 H'FFFFF6EA H'0000 H'FFFFF5C0 16 H'FFFF H'FFFFF5C2 H'FFFF H'FFFFF5C4 H'00 H'00 H'FFFFF5C6 8 H'FFFFF5C8 11.2.4 11.2.3 11.2.5 11.2.6 11.2.15 11.2.20 R/(W)* H'0000 H'FFFFF5CA 16 R/W H'0000 H'FFFFF5CC Note: * Only a 0 write after a read is enabled. Rev. 3.0, 09/04, page 217 of 1086 11.1.4 Block Diagrams Overall Block Diagram of ATU-II: Figure 11.1 shows an overall block diagram of the ATU-II. Clock selection TCLKA TCLKB Interrupts IC/OC control I/O interrupt control Inter-module connection signals External pins Inter-module address bus Counter and register control, and comparator 16-bit timer channel 11 32-bit timer channel 0 16-bit timer channel 1 Channel 10 Prescaler TSTR1 TSTR2 TSTR3 ........ P Bus interface Module data bus Inter-module data bus Legend: TSTR1, 2, 3: Timer start registers (8 bits) Interrupts: ITV0–ITV2, OVI0, OVI1A, OVI1B, OVI2A, OVI2B, OVI3–OVI5, OVI11, ICI0A–ICI0D, IMI1A–IMI1H, CMI1, IMI2A–IMI2H, CMI2A–CMI2H, IMI3A–IMI3D, IMI4A–IMI4D, IMI5A–IMI5D, CMI6A–CMI6D, CMI7A–CMI7D, OSI8A–OSI8P, CMI9A–CMI9F, CMI10A, CMI10B, ICI10A, CMI10G, IMI11A, IMI11B External pins: TI0A–TI0D, TIO1A–TIO1H, TIO2A–TIO2H, TIO3A–TIO3D, TIO4A–TIO4D, TIO5A–TIO5D, TO6A–TO6D, TO7A–TO7D, TO8A–TO8P, TI9A–TI9F, TI10, TIO11A–TIO11B Inter-module connection signals: Signals to A/D converter, signals to direct memory access controller (DMAC), signals to advanced pulse controller (APC) Figure 11.1 Overall Block Diagram of ATU-II Rev. 3.0, 09/04, page 218 of 1086 Block Diagram of Channel 0: Figure 11.2 shows a block diagram of ATU-II channel 0. STR0 Prescaler 1 ICR0AH ICR0BH ICR0CH ICR0DH TCNT0H ICR0AL ICR0BL ICR0CL ICR0DL TCNT0L TRGOD (OCR10B compare-match signal) TIOR0 TIER0 ITVRR1 ITVRR2A ITVRR2B TSR0 TI0A TI0B TI0C TI0D Control logic A/D converter trigger Overflow interrupt signal Interval interrupt I/O control OSBR (ch1, ch2) Internal data bus and address bus Figure 11.2 Block Diagram of Channel 0 Rev. 3.0, 09/04, page 219 of 1086 Block Diagram of Channel 1: Figure 11.3 shows a block diagram of ATU-II channel 1. STR1A/1B, 2B Prescaler 1 TCLKA TCLKB TI10 (AGCK) TI10 multiplication (AGCKM) Clock selection logic (2 systems: A, B) GR1A GR1B GR1C GR1D GR1E GR1F GR1G GR1H OSBR1 TCNT1A OCR1 TCNT1B TIOR1A TIOR1B TIOR1C TIOR1D TCR1A TCR1B TSR1A TSR1B TIER1A TIER1B TRGMDR TIO1A TIO1B TIO1C TIO1D TIO1E TIO1F TIO1G TIO1H One-shot start trigger (CH8) One-shot terminate trigger (CH8) I/O control Overflow interrupt × 1 Input capture/output compare interrupts × 8 Comparator TI0A(capture signal from CH0) TRG1A (counter clear trigger from CH10) TRG1B (counter clear trigger from CH10) Control logic Internal data bus and address bus Figure 11.3 Block Diagram of Channel 1 Rev. 3.0, 09/04, page 220 of 1086 Block Diagram of Channel 2: Figure 11.4 shows a block diagram of ATU-II channel 2. STR2A/1B, 2B Prescaler 1 TCLKA TCLKB TI10 (AGCKM) TI10 multiplication (AGCK) Clock selection logic Comparator TI0A (couter clear trigger from CH0) GR2A GR2B GR2C GR2D GR2E GR2F GR2G GR2H OSBR2 TCNT2A OCR2A OCR2B OCR2C OCR2D OCR2E OCR2F OCR2G OCR2H TCNT2B TIOR2A TIOR2B TIOR2C TIOR2D TCR2A TCR2B TSR2A TSR2B TIER2A TIER2B TIO2A TIO2B TIO2C TIO2D TIO2E TIO2F TIO2G TIO2H One-shot start trigger (CH8) One-shot terminate trigger (CH8) Overflow interrupt × 1 Input capture/output compare interrupts × 8 Control logic TRG2A (counter clear trigger from CH10) TRG2B (counter clear trigger from CH10) I/O control Internal data bus and address bus Figure 11.4 Block Diagram of Channel 2 Rev. 3.0, 09/04, page 221 of 1086 Block Diagram of Channels 3 to 5: Figure 11.5 shows a block diagram of ATU-II channels 3, 4, and 5. STR3 to 5 Prescaler 1 TCLKA TCLKB TI10 (AGCK) TI10 multiplication (AGCKM) GR3A • • • Clock selection logic (3 systems: CH3, 4, 5) Comparator Channel 9 comparematch trigger GR3D TCNT3 TIOR3A TIOR3B TCR3 GR4A • • • GR4D TCNT4 TIOR4A TIOR4B TCR4 GR5A • • • Control logic GR5D TCNT5 TIOR5A TIOR5B TCR5 TMDR TIER3 TSR3 TIO3A TIO3B TIO3C TIO3D TIO4A TIO4B TIO4C TIO4D TIO5A TIO5B TIO5C TIO5D I/O control Overflow interrupts × 3 Input capture/output compare interrupts × 12 Internal data bus and address bus Figure 11.5 Block Diagram of Channels 3 to 5 Rev. 3.0, 09/04, page 222 of 1086 Block Diagram of Channels 6 and 7: Figure 11.6 shows a block diagram of ATU-II channels 6 and 7. STR6×, 7× Prescaler 2 Clock selection logic (A–D independent) BFR6A CYLR6A DTR6A TCNT6A BFR6B CYLR6B DTR6B TCNT6B BFR6C CYLR6C DTR6C TCNT6C BFR6D CYLR6D DTR6D TCNT6D TCR6A TCR6B TSR6 TIER6 PMDR TO6A TO6B TO6C TO6D Comparator Control logic I/O control Compare-match interrupts × 4 Internal data bus and address bus Note: Channel 7 has no PMDR7. Figure 11.6 Block Diagram of Channel 6 (Same Configuration for Channel 7) Rev. 3.0, 09/04, page 223 of 1086 Block Diagram of Channel 8: Figure 11.7 shows a block diagram of ATU-II channel 8. Prescaler 1 Clock selection (2 systems: A–H, I–P) DCNT8A DCNT8B DCNT8C DCNT8D • • • • Comparator One-shot start trigger (CH1, 2) One-shot terminate trigger (CH1, 2) DCNT8M DCNT8N DCNT8O DCNT8P RLDR8 TCNR OTR DSTR TCR8 TSR8 TIER8 RLDENR Control logic TO8A TO8B • • • • TO8O TO8P I/O control Down-count end interrupts × 16 (OSI) Internal data bus and address bus Figure 11.7 Block Diagram of Channel 8 Rev. 3.0, 09/04, page 224 of 1086 Block Diagram of Channel 9: Figure 11.8 shows a block diagram of ATU-II channel 9. GR9A ECNT9A GR9B ECNT9B GR9C ECNT9C GR9D ECNT9D GR9E ECNT9E GR9F ECNT9F TCR9A TCR9B TCR9C TSR9 TIER9 TI9A TI9B TI9C TI9D TI9E TI9F Control logic Comparator Channel 3 capture trigger × 4 I/O control Compare-match interrupts × 6 Internal data bus and address bus Figure 11.8 Block Diagram of Channel 9 Rev. 3.0, 09/04, page 225 of 1086 Block Diagram of Channel 10: Figure 11.9 shows a block diagram of ATU-II channel 10. STR10 Prescaler 4 ICR10AH OCR10AH TCNT10AH ICR10AL OCR10AL TCNT10AL OCR10B TCNT10B RLD10C TCNT10C TCNT10D TCNT10E TCNT10F GR10G TCNT10G NCR10 TCNT10H TCCLR10 TIOR10 TCR10 TIER10 TSR10 TI10 I/O control Internal data bus and address bus Control logic TRG1A, 1B, 2A, 2B (Counter clear trigger) TRG0D (OCR10B comparematch signal) Frequency multiplication clock Frequency multiplication correction clock Output compare interrupts × 2 Input capture / output compare interrupt × 1 Figure 11.9 Block Diagram of Channel 10 Rev. 3.0, 09/04, page 226 of 1086 Block Diagram of Channel 11: Figure 11.10 shows a block diagram of ATU-II channel 11. STR11 Prescaler 4 TCLKA TCLKB Clock selection logic Comparator GR11A GR11B TCNT11 TIOR11 TCR11 TSR11 TIER11 Control logic TIO11A TIO11B APC output compare-match timing signals × 2 I/O control Overflow interrupt × 1 Input capture/output compare interrupts × 2 Internal data bus and address bus Figure 11.10 Block Diagram of Channel 11 Rev. 3.0, 09/04, page 227 of 1086 11.1.5 Inter-Channel and Inter-Module Signal Communication Diagram Figure 11.11 shows the connections between channels and between modules in the ATU-II. Channel 0 TI0A ICR0A ICR0B ICR0C ICR0D ITVRR1 ITVRR2A ITVRR2B A/D converter activation DMAC activation Capture trigger OCR10B Channel 10 Channel 1 Capture trigger OSBR1 TCNT1A TCNT1B GR1A GR1B • • • TCNT10F OCR1 GR1H TI10(AGCK) TI10 multiplication (AGCKM) Counter clear trigger Channel 2 OSBR2 OCR2A OCR2B • • • TCNT2A TCNT2B GR2A GR2B • • • OCR2H GR2H TI10(AGCK) TI10 multiplication (AGCKM) Channel 8 One-shot start One-shot terminate DCNT8A DCNT8B DCNT8C DCNT8D DCNT8E DCNT8F DCNT8G DCNT8H DCNT8I DCNT8J DCNT8K DCNT8L DCNT8M DCNT8N DCNT8O DCNT8P Channel 3 GR3A GR3B GR3C GR3D TI10(AGCK) TI10 multiplication (AGCKM) Channel 4 Capture trigger TI10(AGCK) TI10 multiplication (AGCKM) TI10(AKCK) TI10 multiplication (AGCKM) Channel 6, 7 GR9A GR9B GR9C GR9D GR9E GR9F CYLR6, 7x DTR6, 7x BFR6, 7x Channel 5 Channel 9 TCNT6, 7x DMAC activation (compare-match) X: A, B, C, D Channel 11 TCNT11 GR11A GR11B Compare-match signal transmission to advanced pulse controller (APC) Figure 11.11 Inter-Module Communication Signals Rev. 3.0, 09/04, page 228 of 1086 11.1.6 Prescaler Diagram Figure 11.12 shows a diagram of the ATU-II prescalers. Input clock φ/2 Prescaler 1 Channel 0 Channel 1 Channel 2 TCLKA TCLKB Channel 3 Edge detection Channel 4 Channel 5 Channel 8 Channel 10 TI10 Prescaler 2 Channel 6 Prescaler 3 TI9A TI9B TI9C TI9D TI9E TI9F Channel 7 Prescaler 4 Channel 11 Channel 9 Timer control register Figure 11.12 Prescaler Diagram Rev. 3.0, 09/04, page 229 of 1086 11.2 11.2.1 Register Descriptions Timer Start Registers (TSTR) The timer start registers (TSTR) are 8-bit registers. The ATU-II has three TSTR registers. Channel 0, 1, 2, 3, 4, 5, 10 6, 7 11 Abbreviation TSTR1 TSTR2 TSTR3 Function Free-running counter operation/stop setting Timer Start Register 1 (TSTR1) Bit: 7 STR10 Initial value: R/W: 0 R/W 6 STR5 0 R/W 5 STR4 0 R/W 4 STR3 0 R/W 3 STR1B, 2B 0 R/W 2 STR2A 0 R/W 1 STR1A 0 R/W 0 STR0 0 R/W TSTR1 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT) in channels 0 to 5 and 10. TSTR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—Counter Start 10 (STR10): Starts and stops channel 10 counters (TCNT10A, 10C, 10D, 10E, 10F, and 10G). TCNT10B and 10H are not stopped. Bit 7: STR10 0 1 Description TCNT10 is halted TCNT10 counts (Initial value) • Bit 6—Counter Start 5 (STR5): Starts and stops free-running counter 5 (TCNT5). Bit 6: STR5 0 1 Description TCNT5 is halted TCNT5 counts (Initial value) Rev. 3.0, 09/04, page 230 of 1086 • Bit 5—Counter Start 4 (STR4): Starts and stops free-running counter 4 (TCNT4). Bit 5: STR4 0 1 Description TCNT4 is halted TCNT4 counts (Initial value) • Bit 4—Counter Start 3 (STR3): Starts and stops free-running counter 3 (TCNT3). Bit 4: STR3 0 1 Description TCNT3 is halted TCNT3 counts (Initial value) • Bit 3—Counter Start 1B, 2B (STR1B, STR2B): Starts and stops free-running counters 1B and 2B (TCNT1B, TCNT2B). Bit 3: STR1B, STR2B 0 1 Description TCNT1B and TCNT2B are halted TCNT1B and TCNT2B count (Initial value) • Bit 2—Counter Start 2A (STR2A): Starts and stops free-running counter 2A (TCNT2A). Bit 2: STR2A 0 1 Description TCNT2A is halted TCNT2A counts (Initial value) • Bit 1—Counter Start 1A (STR1A): Starts and stops free-running counter 1A (TCNT1A). Bit 1: STR1A 0 1 Description TCNT1A is halted TCNT1A counts (Initial value) • Bit 0—Counter Start 0 (STR0): Starts and stops free-running counter 0 (TCNT0). Bit 0: STR0 0 1 Description TCNT0 is halted TCNT0 counts (Initial value) Rev. 3.0, 09/04, page 231 of 1086 Timer Start Register 2 (TSTR2) Bit: 7 STR7D Initial value: R/W: 0 R/W 6 STR7C 0 R/W 5 STR7B 0 R/W 4 STR7A 0 R/W 3 STR6D 0 R/W 2 STR6C 0 R/W 1 STR6B 0 R/W 0 STR6A 0 R/W TSTR2 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT) in channels 6 and 7. TSTR2 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—Counter Start 7D (STR7D): Starts and stops free-running counter 7D (TCNT7D). Bit 7: STR7D 0 1 Description TCNT7D is halted TCNT7D counts (Initial value) • Bit 6—Counter Start 7C (STR7C): Starts and stops free-running counter 7C (TCNT7C). Bit 6: STR7C 0 1 Description TCNT7C is halted TCNT7C counts (Initial value) • Bit 5—Counter Start 7B (STR7B): Starts and stops free-running counter 7B (TCNT7B). Bit 5: STR7B 0 1 Description TCNT7B is halted TCNT7B counts (Initial value) • Bit 4—Counter Start 7A (STR7A): Starts and stops free-running counter 7A (TCNT7A). Bit 4: STR7A 0 1 Description TCNT7A is halted TCNT7A counts (Initial value) Rev. 3.0, 09/04, page 232 of 1086 • Bit 3—Counter Start 6D (STR6D): Starts and stops free-running counter 6D (TCNT6D). Bit 3: STR6D 0 1 Description TCNT6D is halted TCNT6D counts (Initial value) • Bit 2—Counter Start 6C (STR6C): Starts and stops free-running counter 6C (TCNT6C). Bit 2: STR6C 0 1 Description TCNT6C is halted TCNT6C counts (Initial value) • Bit 1—Counter Start 6B (STR6B): Starts and stops free-running counter 6B (TCNT6B). Bit 1: STR6B 0 1 Description TCNT6B is halted TCNT6B counts (Initial value) • Bit 0—Counter Start 6A (STR6A): Starts and stops free-running counter 6A (TCNT6A). Bit 0: STR6A 0 1 Description TCNT6A is halted TCNT6A counts (Initial value) Timer Start Register 3 (TSTR3) Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 STR11 0 R/W TSTR3 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT11) in channel 11. TSTR3 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bits 7 to 1—Reserved: These bits are always read as 0. The write value should always be 0. Rev. 3.0, 09/04, page 233 of 1086 • Bit 0—Counter Start 11 (STR11): Starts and stops free-running counter 11 (TCNT11). Bit 0: STR11 0 1 Description TCNT11 is halted TCNT11 counts (Initial value) 11.2.2 Prescaler Registers (PSCR) The prescaler registers (PSCR) are 8-bit registers. The ATU-II has four PSCR registers. Channel 0, 1, 2, 3, 4, 5, 8, 11 6 7 10 Abbreviation PSCR1 PSCR2 PSCR3 PSCR4 Function Prescaler setting for respective channels PSCRx is an 8-bit writable register that enables the first-stage counter clock φ' input to each channel to be set to any value from Pφ/1 to Pφ/32. Bit: 7 — Initial value: R/W: x = 1 to 4 0 R 6 — 0 R 5 — 0 R 4 PSCxE 0 R/W 3 PSCxD 0 R/W 2 PSCxC 0 R/W 1 PSCxB 0 R/W 0 PSCxA 0 R/W Input counter clock φ' is determined by setting PSCxA to PSCxE: φ' is Pφ/1 when the set value is H'00, and Pφ/32 when H'1F. PSCRx is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. The internal clock φ' set with this register can undergo further second-stage scaling to create clock φ" for channels 1 to 8 and 11, the setting being made in the timer control register (TCR). • Bits 7 to 5—Reserved: These bits cannot be modified. • Bits 4 to 0—Prescaler (PSCxE, PSCxD, PSCxC, PSCxB, PSCxA): These bits specify frequency division of first-stage counter clock ø' input to the corresponding channel. Rev. 3.0, 09/04, page 234 of 1086 11.2.3 Timer Control Registers (TCR) The timer control registers (TCR) are 8-bit registers. The ATU-II has 16 TCR registers: two each for channels 1 and 2, one each for channels 3, 4, 5, 8, and 11, two each for channels 6 and 7, and three for channel 9. For details of channel 10, see section 11.2.26, Channel 10 Registers. Channel 1 2 3 4 5 6 7 8 9 11 Abbreviation TCR1A, TCR1B TCR2A, TCR2B TCR3 TCR4 TCR5 TCR6A, TCR6B TCR7A, TCR7B TCR8 TCR9A, TCR9B, TCR9C TCR11 External clock selection/setting of channel 3 trigger in event of compare-match Internal clock/external clock selection Internal clock selection Function Internal clock/external clock/TI10 input clock selection Each TCR is an 8-bit readable/writable register that selects whether an internal clock or external clock is used for channels 1 to 5 and 11. For channels 6 to 8, TCR selects an internal clock, and for channel 9, an external clock. When an internal clock is selected, TCR selects the value of φ" further scaled from clock φ' scaled with prescaler register (PSCR). Scaled clock φ" can be selected, for channels 1 to 8 and 11 only, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32 (only φ' is available for channel 0). Edge detection is performed on the rising edge. When an external clock is selected, TCR selects whether TCLKA, TCLKB (channels 1 to 5 and 11 only), TI10 pin input (channels 1 to 5 only), or a TI10 pin input multiplied clock (channels 1 to 5 only) is used, and also performs edge selection. Each TCR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev. 3.0, 09/04, page 235 of 1086 Timer Control Registers 1A, 1B, 2A, 2B (TCR1A, TCR1B, TCR2A, TCR2B) TCR1A, TCR2A Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 CKEGA1 4 3 2 1 0 CKEGA0 CKSELA3 CKSELA2 CKSELA1 CKSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCR1B, TCR2B Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 CKEGB1 4 3 2 1 0 CKEGB0 CKSELB3 CKSELB2 CKSELB1 CKSELB0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W • Bits 7 and 6—Reserved: These bits are always read as 0. The write value should always be 0. • Bits 5 and 4—Clock Edge 1 and 0 (CKEGx1, CKEGx0): These bits select the count edge(s) for external clock TCLKA and TCLKB input. Bit 5: CKEGx1 0 Bit 4: CKEGx0 0 1 1 x = A or B 0 1 Description Rising edges counted Falling edges counted Both rising and falling edges counted Count disabled (Initial value) • Bits 3 to 0—Clock Select A3 to A0, B3 to B0 (CKSELA3 to CKSELA0, CKSELB3 to CKSELB0): These bits select whether an internal clock or external clock is used. When an internal clock is selected, scaled clock φ" is selected from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. When an external clock is selected, TCLKA, TCLKB, TI10 pin input, or a TI10 pin input multiplied clock is selected. When TI10 pin input and TI10 pin input clock multiplication are selected, set CKEG1 and CKEG0 in TCR10 so that TI10 input is possible. Rev. 3.0, 09/04, page 236 of 1086 Bit 3: CKSELx3 0 Bit 2: CKSELx2 0 Bit 1: CKSELx1 0 Bit 0: CKSELx0 0 1 Description Internal clock φ": counting on φ' Internal clock φ": counting on φ'/2 Internal clock φ": counting on φ'/4 Internal clock φ": counting on φ'/8 Internal clock φ": counting on φ'/16 Internal clock φ": counting on φ'/32 External clock: counting on TCLKA pin input External clock: counting on TCLKB pin input Counting on TI10 pin input (AGCK) Counting on multiplied (corrected)(AGCKM) TI10 pin input clock Setting prohibited Setting prohibited (Initial value) 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x = A or B *: Don't care * * * Timer Control Registers 3 to 5 (TCR3, TCR4, TCR5) Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 CKEG1 0 R/W 4 3 2 1 0 CKEG0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W • Bits 7 and 6—Reserved: These bits are always read as 0. The write value should always be 0. • Bits 5 and 4—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the count edge(s) for external clock TCLKA and TCLKB input. Bit 5: CKEG1 0 Bit 4: CKEG0 0 1 1 0 1 Description Rising edges counted Falling edges counted Both rising and falling edges counted Count disabled (Initial value) Rev. 3.0, 09/04, page 237 of 1086 • Bits 3 to 0—Clock Select 3 to 0 (CKSEL3 to CKSEL0): These bits select whether an internal clock or external clock is used. When an internal clock is selected, scaled clock φ" is selected from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. When an external clock is selected, TCLKA, TCLKB, TI10 pin input, or a TI10 pin input multiplied clock is selected. When TI10 pin input and TI10 pin input clock multiplication are selected, set CKEG1 and CKEG0 in TCR10 so that TI10 input is possible. Bit 3: CKSEL3 0 Bit 2: CKSEL2 0 Bit 1: CKSEL1 0 Bit 0: CKSEL0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 *: Don't care * * * Description Internal clock φ": counting on φ' Internal clock φ": counting on φ'/2 Internal clock φ": counting on φ'/4 Internal clock φ": counting on φ'/8 Internal clock φ": counting on φ'/16 Internal clock φ": counting on φ'/32 External clock: counting on TCLKA pin input External clock: counting on TCLKB pin input Counting on TI10 pin input (AGCK) Counting on multiplied (corrected)(AGCKM) TI10 pin input clock Setting prohibited Setting prohibited (Initial value) Rev. 3.0, 09/04, page 238 of 1086 Timer Control Registers 6A, 6B, 7A, 7B (TCR6A, TCR6B, TCR7A, TCR7B) TCR6A, TCR7A Bit: 7 — Initial value: R/W: 0 R 6 5 4 3 — 0 R 2 1 0 CKSELB2 CKSELB1 CKSELB0 CKSELA2 CKSELA1 CKSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCR6B, TCR7B Bit: 7 — Initial value: R/W: 0 R 6 5 4 3 — 0 R 2 1 0 CKSELD2 CKSELD1 CKSELD0 CKSELC2 CKSELC1 CKSELC0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W • Bit 7—Reserved: This bit is always read as 0. The write value should always be 0. • Bits 6 to 4—Clock Select B2 to B0, D2 to D0 (CKSELB2 to CKSELB0, CKSELD2 to CKSELD0): These bits select clock φ", scaled from the internal clock source, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. Bit 6: CKSELx2 0 Bit 5: CKSELx1 0 Bit 4: CKSELx0 0 1 1 0 1 1 0 0 1 1 x = B or D 0 1 Description Internal clock φ": counting on φ' Internal clock φ": counting on φ'/2 Internal clock φ": counting on φ'/4 Internal clock φ": counting on φ'/8 Internal clock φ": counting on φ'/16 Internal clock φ": counting on φ'/32 Setting prohibited Setting prohibited (Initial value) • Bit 3—Reserved: This bit is always read as 0. The write value should always be 0. • Bits 2 to 0—Clock Select A2 to A0, C2 to C0 (CKSELA2 to CKSELA0, CKSELC2 to CKSELC0): These bits select clock φ", scaled from the internal clock source, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. Rev. 3.0, 09/04, page 239 of 1086 Bit 2: CKSELx2 0 Bit 1 CKSELx1 0 Bit 0 CKSELx0 0 1 Description Internal clock φ": counting on φ' Internal clock φ": counting on φ'/2 Internal clock φ": counting on φ'/4 Internal clock φ": counting on φ'/8 Internal clock φ": counting on φ'/16 Internal clock φ": counting on φ'/32 Setting prohibited Setting prohibited (Initial value) 1 0 1 1 0 0 1 1 x = A or C 0 1 Timer Control Register 8 (TCR8) Bit: 7 — Initial value: R/W: 0 R 6 5 4 3 — 0 R 2 1 0 CKSELB2 CKSELB1 CKSELB0 CKSELA2 CKSELA1 CKSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The CKSELAx bits relate to DCNT8A to DCNT8H, and the CKSELBx bits relate to DCNT8I to DCNT8P. • Bit 7—Reserved: This bit is always read as 0. The write value should always be 0. • Bits 6 to 4—Clock Select B2 to B0 (CKSELB2 to CKSELB0): These bits, relating to counters DCNT8I to DCNT8P, select clock φ", scaled from the internal clock source, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. Bit 6: CKSELB2 0 Bit 5: CKSELB1 0 Bit 4: CKSELB0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock φ": counting on φ' Internal clock φ": counting on φ'/2 Internal clock φ": counting on φ'/4 Internal clock φ": counting on φ'/8 Internal clock φ": counting on φ'/16 Internal clock φ": counting on φ'/32 Setting prohibited Setting prohibited (Initial value) • Bit 3—Reserved: This bit is always read as 0. The write value should always be 0. Rev. 3.0, 09/04, page 240 of 1086 • Bits 2 to 0—Clock Select A2 to A0 (CKSELA2 to CKSELA0): These bits, relating to counters DCNT8A to DCNT8H, select clock φ", scaled from the internal clock source, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. Bit 2: CKSELA2 0 Bit 1: CKSELA1 0 Bit 0: CKSELA0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock φ": counting on φ' Internal clock φ": counting on φ'/2 Internal clock φ": counting on φ'/4 Internal clock φ": counting on φ'/8 Internal clock φ": counting on φ'/16 Internal clock φ": counting on φ'/32 Setting prohibited Setting prohibited (Initial value) Timer Control Registers 9A, 9B, 9C (TCR9A, TCR9B, TCR9C) TCR9A Bit: 7 — Initial value: R/W: 0 R 6 5 4 3 — 0 R 2 1 0 TRG3BEN EGSELB1 EGSELB0 TRG3AEN EGSELA1 EGSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCR9B Bit: 7 — Initial value: R/W: 0 R 6 5 4 3 — 0 R 2 1 0 TRG3DEN EGSELD1 EGSELD0 TRG3CEN EGSELC1 EGSELC0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCR9C Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 4 3 — 0 R 2 — 0 R 1 0 EGSELF1 EGSELF0 EGSELE1 EGSELE0 0 R/W 0 R/W 0 R/W 0 R/W • Bit 7—Reserved: This bit is always read as 0. The write value should always be 0. Rev. 3.0, 09/04, page 241 of 1086 • Bit 6—Trigger Channel 3BEN, 3DEN (TRG3BEN, TRG3DEN): These bits select the channel 9 event counter compare-match signal channel 3 input capture trigger. Bit 6: TRG3xEN 0 1 x = B or D Description Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is disabled (Initial value) Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is enabled • Bits 5 and 4—Edge Select B1, B0, D1, D0, F1, F0 (EGSELB1, EGSELB0, EGSELD1, EGSELD0, EGSELF1, EGSELF0): These bits select the event counter counted edge(s). Bit 5: EGSELx1 0 Bit 4: EGSELx0 0 1 1 x = B, D, or F 0 1 Description Count disabled Rising edges counted Falling edges counted Both rising and falling edges counted (Initial value) • Bit 3—Reserved: This bit is always read as 0. The write value should always be 0. • Bit 2—Trigger Channel 3AEN, 3CEN (TRG3AEN, TRG3CEN): These bits select the channel 9 event counter compare-match signal channel 3 input capture trigger. Bit 2: TRG3xEN 0 1 x = A or C Description Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is disabled (Initial value) Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is enabled • Bits 1 and 0—Edge Select A1, A0, C1, C0, E1, E0 (EGSELA1, EGSELA0, EGSELC1, EGSELC0, EGSELE1, EGSELE0): These bits select the event counter counted edge(s). Rev. 3.0, 09/04, page 242 of 1086 Bit 1: EGSELx1 0 Bit 0: EGSELx0 0 1 Description Count disabled Rising edges counted Falling edges counted Both rising and falling edges counted (Initial value) 1 x = A, C, or E 0 1 Timer Control Register 11 (TCR11) Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 CKEG1 4 CKEG0 3 — 0 R 2 1 0 CKSELA2 CKSELA1 CKSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W • Bits 7, 6, and 3—Reserved: These bits are always read as 0. The write value should always be 0. • Bits 5 and 4—Edge Select: These bits select the event counter counted edge(s). Bit 5: CKEG1 0 Bit 4: CKEG0 0 1 1 0 1 Description Rising edges counted Falling edges counted Both rising and falling edges counted Count disabled (Initial value) • Bits 2 to 0—Clock Select A2 to A0 (CKSELA2 to CKSELA0): These bits select clock φ", scaled from the internal clock source, from φ', φ'/2, φ'/4, φ'/8, φ'/16, and φ'/32. Bit 2: CKSELA2 0 Bit 1: CKSELA1 0 Bit 0: CKSELA0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock φ": counting on φ' Internal clock φ": counting on φ'/2 Internal clock φ": counting on φ'/4 Internal clock φ": counting on φ'/8 Internal clock φ": counting on φ'/16 Internal clock φ": counting on φ'/32 External clock: counting on TCLKA pin input External clock: counting on TCLKB pin input (Initial value) Rev. 3.0, 09/04, page 243 of 1086 11.2.4 Timer I/O Control Registers (TIOR) The timer I/O control registers (TIOR) are 8-bit registers. The ATU-II has 16 TIOR registers: one for channel 0, four each for channels 1 and 2, two each for channels 3 to 5, and one for channel 11. For details of channel 10, see section 11.2.26, Channel 10 Registers. Channel 0 1 2 3 4 5 11 Abbreviation TIOR0 TIOR1A–1D TIOR2A–2D TIOR3A, TIOR3B TIOR4A, TIOR4B TIOR5A, TIOR5B TIOR11 GR input capture/compare-match switching, edge detection/output value setting Function ICR0 edge detection setting GR input capture/compare-match switching, edge detection/output value setting GR input capture/compare-match switching, edge detection/output value setting, TCNT3 to TCNT5 clear enable/disable setting Each TIOR is an 8-bit readable/writable register used to select the functions of dedicated input capture registers and general registers. For dedicated input capture registers (ICR), TIOR performs edge detection setting. For general registers (GR), TIOR selects use as an input capture register or output compare register, and performs edge detection setting. For channels 3 to 5, TIOR also selects enabling or disabling of free-running counter (TCNT) clearing in the event of a compare-match. Timer I/O Control Register 0 (TIOR0) Bit: 7 IO0D1 Initial value: R/W: 0 R/W 6 IO0D0 0 R/W 5 IO0C1 0 R/W 4 IO0C0 0 R/W 3 IO0B1 0 R/W 2 IO0B0 0 R/W 1 IO0A1 0 R/W 0 IO0A0 0 R/W TIOR0 specifies edge detection for input capture registers ICR0A to ICR0D. TIOR0 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev. 3.0, 09/04, page 244 of 1086 • Bits 7 and 6—I/O Control 0D1 and 0D0 (IO0D1, IO0D0): These bits select TI0D pin input capture signal edge detection. Bit 7: IO0D1 0 Bit 6: IO0D0 0 1 1 0 1 Description Input capture disabled (input capture possible in TCNT10B compare-match) (Initial value) Input capture in ICR0D on rising edge Input capture in ICR0D on falling edge Input capture in ICR0D on both rising and falling edges • Bits 5 and 4—I/O Control 0C1 and 0C0 (IO0C1, IO0C0): These bits select TI0C pin input capture signal edge detection. Bit 5: IO0C1 0 Bit 4: IO0C0 0 1 1 0 1 Description Input capture disabled Input capture in ICR0C on rising edge Input capture in ICR0C on falling edge Input capture in ICR0C on both rising and falling edges (Initial value) • Bits 3 and 2—I/O Control 0B1 and 0B0 (IO0B1, IO0B0): These bits select TI0B pin input capture signal edge detection. Bit 3: IO0B1 0 Bit 2: IO0B0 0 1 1 0 1 Description Input capture disabled Input capture in ICR0B on rising edge Input capture in ICR0B on falling edge Input capture in ICR0B on both rising and falling edges (Initial value) • Bits 1 and 0—I/O Control 0A1 and 0A0 (IO0A1, IO0A0): These bits select TI0A pin input capture signal edge detection. Bit 1: IO0A1 0 Bit 0: IO0A0 0 1 1 0 1 Description Input capture disabled Input capture in ICR0A on rising edge Input capture in ICR0A on falling edge Input capture in ICR0A on both rising and falling edges (Initial value) Rev. 3.0, 09/04, page 245 of 1086 Timer I/O Control Registers 1A to 1D (TIOR1A to TIOR1D) TIOR1A Bit: 7 — 6 IO1B2 0 R/W 5 IO1B1 0 R/W 4 IO1B0 0 R/W 3 — 0 R 2 IO1A2 0 R/W 1 IO1A1 0 R/W 0 IO1A0 0 R/W Initial value: R/W: 0 R TIOR1B Bit: 7 — Initial value: R/W: 0 R 6 IO1D2 0 R/W 5 IO1D1 0 R/W 4 IO1D0 0 R/W 3 — 0 R 2 IO1C2 0 R/W 1 IO1C1 0 R/W 0 IO1C0 0 R/W TIOR1C Bit: 7 — Initial value: R/W: 0 R 6 IO1F2 0 R/W 5 IO1F1 0 R/W 4 IO1F0 0 R/W 3 — 0 R 2 IO1E2 0 R/W 1 IO1E1 0 R/W 0 IO1E0 0 R/W TIOR1D Bit: 7 — Initial value: R/W: 0 R 6 IO1H2 0 R/W 5 IO1H1 0 R/W 4 IO1H0 0 R/W 3 — 0 R 2 IO1G2 0 R/W 1 IO1G1 0 R/W 0 IO1G0 0 R/W Registers TIOR1A to TIOR1D specify whether general registers GR1A to GR1H are used as input capture or compare-match registers, and also perform edge detection and output value setting. Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—Reserved: This bit is always read as 0. The write value should always be 0. Rev. 3.0, 09/04, page 246 of 1086 • Bits 6 to 4—I/O Control 1B2 to 1B0, 1D2 to 1D0, 1F2 to 1F0, 1H2 to 1H0 (IO1B2 to IO1B0, IO1D2 to IO1D0, IOF12 to IO1F0, IO1H2 to IO1H0): These bits select the general register (GR) function. Bit 6: IO1x2 0 Bit 5: IO1x1 0 Bit 4: IO1x0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled (GR cannot be written to) Input capture in GR on rising edge at TIO1x pin (GR cannot be written to) Input capture in GR on falling edge at TIO1x pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIO1x pin (GR cannot be written to) x = B, D, F, or H • Bit 3—Reserved: This bit is always read as 0. The write value should always be 0. Rev. 3.0, 09/04, page 247 of 1086 • Bits 2 to 0—I/O Control 1A2 to 1A0, 1C2 to 1C0, 1E2 to 1E0, 1G2 to 1G0 (IO1A2 to IO1A0, IO1C2 to IO1C0, IO1E2 to IO1E0, IO1G2 to IO1G0): These bits select the general register (GR) function. Bit 2: IO1x2 0 Bit 1: IO1x1 0 Bit 0: IO1x0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled Input capture in GR on rising edge at TIO1x pin (GR cannot be written to) Input capture in GR on falling edge at TIO1x pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIO1x pin (GR cannot be written to) x = A, C, E, or G Rev. 3.0, 09/04, page 248 of 1086 Timer I/O Control Registers 2A to 2D (TIOR2A to TIOR2D) TIOR2A Bit: 7 — Initial value: R/W: 0 R 6 IO2B2 0 R/W 5 IO2B1 0 R/W 4 IO2B0 0 R/W 3 — 0 R 2 IO2A2 0 R/W 1 IO2A1 0 R/W 0 IO2A0 0 R/W TIOR2B Bit: 7 — Initial value: R/W: 0 R 6 IO2D2 0 R/W 5 IO2D1 0 R/W 4 IO2D0 0 R/W 3 — 0 R 2 IO2C2 0 R/W 1 IO2C1 0 R/W 0 IO2C0 0 R/W TIOR2C Bit: 7 — Initial value: R/W: 0 R 6 IO2F2 0 R/W 5 IO2F1 0 R/W 4 IO2F0 0 R/W 3 — 0 R 2 IO2E2 0 R/W 1 IO2E1 0 R/W 0 IO2E0 0 R/W TIOR2D Bit: 7 — Initial value: R/W: 0 R 6 IO2H2 0 R/W 5 IO2H1 0 R/W 4 IO2H0 0 R/W 3 — 0 R 2 IO2G2 0 R/W 1 IO2G1 0 R/W 0 IO2G0 0 R/W Registers TIOR2A to TIOR2D specify whether general registers GR2A to GR2H are used as input capture or compare-match registers, and also perform edge detection and output value setting. Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev. 3.0, 09/04, page 249 of 1086 • Bit 7—Reserved: This bit is always read as 0. The write value should always be 0. • Bits 6 to 4—I/O Control 2B2 to 2B0, 2D2 to 2D0, 2F2 to 2F0, 2H2 to 2H0 (IO2B2 to IO2B0, IO2D2 to IO2D0, IO2F2 to IO2F0, IO2H2 to IO2H0): These bits select the general register (GR) function. Bit 6: IO2x2 0 Bit 5: IO2x1 0 Bit 4: IO2x0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled Input capture in GR on rising edge at TIO2x pin (GR cannot be written to) Input capture in GR on falling edge at TIO2x pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIO2x pin (GR cannot be written to) x = B, D, F, or H • Bit 3—Reserved: This bit is always read as 0. The write value should always be 0. Rev. 3.0, 09/04, page 250 of 1086 • Bits 2 to 0—I/O Control 2A2 to 2A0, 2C2 to 2C0, 2E2 to 2E0, 2G2 to 2G0 (IO2A2 to IO2A0, IO2C2 to IO2C0, IO2E2 to IO2E0, IO2G2 to IO2G0): These bits select the general register (GR) function. Bit 2: IO2x2 0 Bit 1: IO2x1 0 Bit 0: IO2x0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled Input capture in GR on rising edge at TIO2x pin (GR cannot be written to) Input capture in GR on falling edge at TIO2x pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIO2x pin (GR cannot be written to) x = A, C, E, or G Rev. 3.0, 09/04, page 251 of 1086 Timer I/O Control Registers 3A, 3B, 4A, 4B, 5A, 5B (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B) TIOR3A, TIOR4A, TIOR5A Bit: 7 CCIxB Initial value: R/W: x = 3 to 5 0 R/W 6 IOxB2 0 R/W 5 IOxB1 0 R/W 4 IOxB0 0 R/W 3 CCIxA 0 R/W 2 IOxA2 0 R/W 1 IOxA1 0 R/W 0 IOxA0 0 R/W TIOR3B, TIOR4B, TIOR5B Bit: 7 CCIxD Initial value: R/W: x = 3 to 5 0 R/W 6 IOxD2 0 R/W 5 IOxD1 0 R/W 4 IOxD0 0 R/W 3 CCIxC 0 R/W 2 IOxC2 0 R/W 1 IOxC1 0 R/W 0 IOxC0 0 R/W TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, and TIOR5B specify whether general registers GR3A to GR3D, GR4A to GR4D, and GR5A to GR5D are used as input capture or comparematch registers, and also perform edge detection and output value setting. They also select enabling or disabling of free-running counter (TCNT3 to TCNT5) clearing on compare-match. Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—Clear Counter Enable Flag 3B, 4B, 5B, 3D, 4D, 5D (CCI3B, CCI4B, CCI5B, CCI3D, CCI4D, CCI5D): These bits select enabling or disabling of free-running counter (TCNT) clearing. Bit 7: CCIxx 0 1 Description TCNT clearing disabled TCNT cleared on GR compare-match (Initial value) xx = 3B, 4B, 5B, 3D, 4D, or 5D TCNT is cleared on compare-match only when GR is functioning as an output compare register. Rev. 3.0, 09/04, page 252 of 1086 • Bits 6 to 4—I/O Control 3B2 to 3B0, 4B2 to 4B0, 5B2 to 5B0, 3D2 to 3D0, 4D2 to 4D0, 5D2 to 5D0 (IO3B2 to IO3B0, IO4B2 to IO4B0, IO5B2 to IO5B0, IO3D2 to IO3D0, IO4D2 to IO4D0, IO5D2 to IO5D0): These bits select the general register (GR) function. Bit 6: IOxx2 0 Bit 5: IOxx1 0 Bit 4: IOxx0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register (input capture by channel 3 and 9 compare-match enabled) Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled (In channel 3 only, GR cannot be written to) Input capture in GR on rising edge at TIOxx pin (GR cannot be written to) Input capture in GR on falling edge at TIOxx pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIOxx pin (GR cannot be written to) xx = 3B, 4B, 5B, 3D, 4D, or 5D • Bit 3—Clear Counter Enable Flag 3A, 4A, 5A, 3C, 4C, 5C (CCI3A, CCI4A, CCI5A, CCI3C, CCI4C, CCI5C): These bits select enabling or disabling of free-running counter (TCNT) clearing. Bit 3: CCIxx 0 1 Description TCNT clearing disabled TCNT cleared on GR compare-match (Initial value) xx = 3A, 4A, 5A, 3C, 4C, or 5C TCNT is cleared on compare-match only when GR is functioning as an output compare register. Rev. 3.0, 09/04, page 253 of 1086 • Bits 2 to 0—I/O Control 3A2 to 3A0, 4A2 to 4A0, 5A2 to 5A0, 3C2 to 3C0, 4C2 to 4C0, 5C2 to 5C0 (IO3A2 to IO3A0, IO4A2 to IO4A0, IO5A2 to IO5A0, IO3C2 to IO3C0, IO4C2 to IO4C0, IO5C2 to IO5C0): These bits select the general register (GR) function. Bit 2: IOxx2 0 Bit 1: IOxx1 0 Bit 0: IOxx0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register (input capture by channel 3 and 9 compare-match enabled) Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled (In channel 3 only, GR cannot be written to) Input capture in GR on rising edge at TIOxx pin (GR connot be written to) Input capture in GR on falling edge at TIOxx pin (GR connot be written to) Input capture in GR on both rising and falling edges at TIOxx pin (GR connot be written to) xx = 3A, 4A, 5A, 3C, 4C, or 5C Timer I/O Control Register 11 (TIOR11) TIOR11 Bit: 7 — Initial value: R/W: 0 R 6 IO11B2 0 R/W 5 IO11B1 0 R/W 4 IO11B0 0 R/W 3 — 0 R 2 IO11A2 0 R/W 1 IO11A1 0 R/W 0 IO11A0 0 R/W TIOR11 specifies whether general registers GR11A and GR11B are used as input capture or compare-match registers, and also performs edge detection and output value setting. TIOR11 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—Reserved: This bit is always read as 0. The write value should always be 0. Rev. 3.0, 09/04, page 254 of 1086 • Bits 6 to 4—I/O Control 11B2 to 11B0 (IO11B2 to IO11B0): These bits select the general register (GR) function. Bit 6: IO11B2 0 Bit 5: IO11B1 0 Bit 4: IO11B0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled Input capture in GR on rising edge at TIO11B pin (GR cannot be written to) Input capture in GR on falling edge at TIO11B pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIO11B pin (GR cannot be written to) • Bit 3—Reserved: This bit is always read as 0. The write value should always be 0. • Bits 2 to 0—I/O Control 11A2 to 11A0 (IO11A2 to IO11A0): These bits select the general register (GR) function. Bit 2: IO11A2 0 Bit 1: IO11A1 0 Bit 0: IO11A0 0 1 1 0 1 1 0 0 1 1 0 1 GR is an input capture register Description GR is an output compare register Compare-match disabled; pin output undefined (Initial value) 0 output on GR compare-match 1 output on GR compare-match Toggle output on GR compare-match Input capture disabled Input capture in GR on rising edge at TIO11A pin (GR cannot be written to) Input capture in GR on falling edge at TIO11A pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIO11A pin (GR cannot be written to) Rev. 3.0, 09/04, page 255 of 1086 11.2.5 Timer Status Registers (TSR) The timer status registers (TSR) are 16-bit registers. The ATU-II has 11 TSR registers: one each for channels 0, 6 to 9, and 11, two each for channels 1 and 2, and one for channels 3 to 5. For details of channel 10, see section 11.2.26, Channel 10 Registers. Channel 0 1 2 3 4 5 6 7 8 9 11 TSR6 TSR7 TSR8 TSR9 TSR11 Indicates down-counter output end (low) status Indicates event counter compare-match status Indicates input capture, compare-match, and overflow status Indicate cycle register compare-match status Abbreviation TSR0 TSR1A, TSR1B TSR2A, TSR2B TSR3 Indicates input capture, compare-match, and overflow status Function Indicates input capture, interval interrupt, and overflow status Indicate input capture, compare-match, and overflow status The TSR registers are 16-bit readable/writable registers containing flags that indicate free-running counter (TCNT) overflow, channel 0 input capture or interval interrupt generation, channel 3, 4, 5, and 11 general register input capture or compare-match, channel 6 and 7 compare-matches, channel 8 down-counter output end, and channel 9 event counter compare-matches. Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is enabled by the corresponding bit in the timer interrupt enable register (TIER). Each TSR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Rev. 3.0, 09/04, page 256 of 1086 Timer Status Register 0 (TSR0) TSR0 indicates the status of channel 0 interval interrupts, input capture, and overflow. Bit: 15 — Initial value: R/W: Bit: 0 R 7 IIF2B Initial value: R/W: 0 R/(W)* 14 — 0 R 6 IIF2A 0 R/(W)* 13 — 0 R 5 IIF1 0 R/(W)* 12 — 0 R 4 OVF0 0 R/(W)* 11 — 0 R 3 ICF0D 0 R/(W)* 10 — 0 R 2 ICF0C 0 R/(W)* 9 — 0 R 1 ICF0B 0 R/(W)* 8 — 0 R 0 ICF0A 0 R/(W)* Note: * Only 0 can be written to clear the flag. • Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 7—Interval Interrupt Flag 2B (IIF2B): Status flag that indicates the generation of an interval interrupt. Bit 7: IIF2B 0 1 Description [Clearing condition] When IIF2B is read while set to 1, then 0 is written to IIF2B [Setting condition] When interval interrupt selected by ITVRR2B is generated (Initial value) • Bit 6—Interval Interrupt Flag 2A (IIF2A): Status flag that indicates the generation of an interval interrupt. Bit 6: IIF2A 0 1 Description [Clearing condition] When IIF2A is read while set to 1, then 0 is written to IIF2A [Setting condition] When interval interrupt selected by ITVRR2A is generated (Initial value) Rev. 3.0, 09/04, page 257 of 1086 • Bit 5—Interval Interrupt Flag 1 (IIF1): Status flag that indicates the generation of an interval interrupt. Bit 5: IIF1 0 1 Description [Clearing condition] When IIF1 is read while set to 1, then 0 is written to IIF1 [Setting condition] When interval interrupt selected by ITVRR1 is generated (Initial value) • Bit 4—Overflow Flag 0 (OVF0): Status flag that indicates TCNT0 overflow. Bit 4: OVF0 0 1 Description [Clearing condition] When OVF0 is read while set to 1, then 0 is written to OVF0 (Initial value) [Setting condition] When the TCNT0 value overflows (from H'FFFFFFFF to H'00000000) • Bit 3—Input Capture Flag 0D (ICF0D): Status flag that indicates ICR0D input capture. Bit 3: ICF0D 0 1 Description [Clearing condition] When ICF0D is read while set to 1, then 0 is written to ICF0D (Initial value) [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal. Also set by input capture with a channel 10 compare match as the trigger • Bit 2—Input Capture Flag 0C (ICF0C): Status flag that indicates ICR0C input capture. Bit 2: ICF0C 0 1 Description [Clearing condition] When ICF0C is read while set to 1, then 0 is written to ICF0C (Initial value) [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal Rev. 3.0, 09/04, page 258 of 1086 • Bit 1—Input Capture Flag 0B (ICF0B): Status flag that indicates ICR0B input capture. Bit 1: ICF0B 0 1 Description [Clearing condition] When ICF0B is read while set to 1, then 0 is written to ICF0B (Initial value) [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal • Bit 0—Input Capture Flag 0A (ICF0A): Status flag that indicates ICR0A input capture. Bit 0: ICF0A 0 1 Description [Clearing condition] When ICF0A is read while set to 1, then 0 is written to ICF0A (Initial value) [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal Timer Status Registers 1A and 1B (TSR1A, TSR1B) TSR1A: TSR1A indicates the status of channel 1 input capture, compare-match, and overflow. Bit: 15 — Initial value: R/W: Bit: 0 R 7 IMF1H Initial value: R/W: 0 R/(W)* 14 — 0 R 6 IMF1G 0 R/(W)* 13 — 0 R 5 IMF1F 0 R/(W)* 12 — 0 R 4 IMF1E 0 R/(W)* 11 — 0 R 3 IMF1D 0 R/(W)* 10 — 0 R 2 IMF1C 0 R/(W)* 9 — 0 R 1 IMF1B 0 R/(W)* 8 OVF1A 0 R/(W)* 0 IMF1A 0 R/(W)* Note: * Only 0 can be written, to clear the flag. • Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0. Rev. 3.0, 09/04, page 259 of 1086 • Bit 8—Overflow Flag 1A (OVF1A): Status flag that indicates TCNT1A overflow. Bit 8: OVF1A 0 1 Description [Clearing condition] (Initial value) When OVF1A is read while set to 1, then 0 is written to OVF1A [Setting condition] When the TCNT1A value overflows (from H'FFFF to H'0000) • Bit 7—Input Capture/Compare-Match Flag 1H (IMF1H): Status flag that indicates GR1H input capture or compare-match. Bit 7: IMF1H 0 1 Description [Clearing condition] When IMF1H is read while set to 1, then 0 is written to IMF1H (Initial value) [Setting conditions] • When the TCNT1A value is transferred to GR1H by an input capture signal while GR1H is functioning as an input capture register • When TCNT1A = GR1H while GR1H is functioning as an output compare register • Bit 6—Input Capture/Compare-Match Flag 1G (IMF1G): Status flag that indicates GR1G input capture or compare-match. Bit 6: IMF1G 0 1 Description [Clearing condition] (Initial value) When IMF1G is read while set to 1, then 0 is written to IMF1G [Setting conditions] • When the TCNT1A value is transferred to GR1G by an input capture signal while GR1G is functioning as an input capture register • When TCNT1A = GR1G while GR1G is functioning as an output compare register Rev. 3.0, 09/04, page 260 of 1086 • Bit 5—Input Capture/Compare-Match Flag 1F (IMF1F): Status flag that indicates GR1F input capture or compare-match. Bit 5: IMF1F 0 1 Description [Clearing condition] When IMF1F is read while set to 1, then 0 is written to IMF1F (Initial value) [Setting conditions] • When the TCNT1A value is transferred to GR1F by an input capture signal while GR1F is functioning as an input capture register • When TCNT1A = GR1F while GR1F is functioning as an output compare register • Bit 4—Input Capture/Compare-Match Flag 1E (IMF1E): Status flag that indicates GR1E input capture or compare-match. Bit 4: IMF1E 0 1 Description [Clearing condition] When IMF1E is read while set to 1, then 0 is written to IMF1E (Initial value) [Setting conditions] • When the TCNT1A value is transferred to GR1E by an input capture signal while GR1E is functioning as an input capture register • When TCNT1A = GR1E while GR1E is functioning as an output compare register • Bit 3—Input Capture/Compare-Match Flag 1D (IMF1D): Status flag that indicates GR1D input capture or compare-match. Bit 3: IMF1D 0 1 Description [Clearing condition] When IMF1D is read while set to 1, then 0 is written to IMF1D (Initial value) [Setting conditions] • When the TCNT1A value is transferred to GR1D by an input capture signal while GR1D is functioning as an input capture register • When TCNT1A = GR1D while GR1D is functioning as an output compare register Rev. 3.0, 09/04, page 261 of 1086 • Bit 2—Input Capture/Compare-Match Flag 1C (IMF1C): Status flag that indicates GR1C input capture or compare-match. Bit 2: IMF1C 0 1 Description [Clearing condition] When IMF1C is read while set to 1, then 0 is written to IMF1C (Initial value) [Setting conditions] • When the TCNT1A value is transferred to GR1C by an input capture signal while GR1C is functioning as an input capture register • When TCNT1A = GR1C while GR1C is functioning as an output compare register • Bit 1—Input Capture/Compare-Match Flag 1B (IMF1B): Status flag that indicates GR1B input capture or compare-match. Bit 1: IMF1B 0 1 Description [Clearing condition] When IMF1B is read while set to 1, then 0 is written to IMF1B (Initial value) [Setting conditions] • When the TCNT1A value is transferred to GR1B by an input capture signal while GR1B is functioning as an input capture register • When TCNT1A = GR1B while GR1B is functioning as an output compare register • Bit 0—Input Capture/Compare-Match Flag 1A (IMF1A): Status flag that indicates GR1A input capture or compare-match. Bit 0: IMF1A 0 1 Description [Clearing condition] When IMF1A is read while set to 1, then 0 is written to IMF1A (Initial value) [Setting conditions] • When the TCNT1A value is transferred to GR1A by an input capture signal while GR1A is functioning as an input capture register • When TCNT1A = GR1A while GR1A is functioning as an output compare register Rev. 3.0, 09/04, page 262 of 1086 TSR1B: TSR1B indicates the status of channel 1 compare-match and overflow. Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 — 0 R 12 — 0 R 4 — 0 R 11 — 0 R 3 — 0 R 10 — 0 R 2 — 0 R 9 — 0 R 1 — 0 R 8 OVF1B 0 R/(W)* 0 CMF1 0 R/(W)* Note: * Only 0 can be written, to clear the flag. • Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 8—Overflow Flag 1B (OVF1B): Status flag that indicates TCNT1B overflow. Bit 8: OVF1B 0 1 Description [Clearing condition] (Initial value) When OVF1B is read while set to 1, then 0 is written to OVF1B [Setting condition] When the TCNT1B value overflows (from H'FFFF to H'0000) • Bits 7 to 1—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 0—Compare-Match Flag 1 (CMF1): Status flag that indicates OCR1 compare-match. Bit 0: CMF1 0 1 Description [Clearing condition] When CMF1 is read while set to 1, then 0 is written to CMF1 [Setting condition] When TCNT1B = OCR1 (Initial value) Rev. 3.0, 09/04, page 263 of 1086 Timer Status Registers 2A and 2B (TSR2A, TSR2B) TSR2A: TSR2A indicates the status of channel 2 input capture, compare-match, and overflow. Bit: 15 — Initial value: R/W: Bit: 0 R 7 IMF2H Initial value: R/W: 0 R/(W)* 14 — 0 R 6 IMF2G 0 R/(W)* 13 — 0 R 5 IMF2F 0 R/(W)* 12 — 0 R 4 IMF2E 0 R/(W)* 11 — 0 R 3 IMF2D 0 R/(W)* 10 — 0 R 2 IMF2C 0 R/(W)* 9 — 0 R 1 IMF2B 0 R/(W)* 8 OVF2A 0 R/(W)* 0 IMF2A 0 R/(W)* Note: * Only 0 can be written to clear the flag. • Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 8—Overflow Flag 2A (OVF2A): Status flag that indicates TCNT2A overflow. Bit 8: OVF2A 0 1 Description [Clearing condition] (Initial value) When OVF2A is read while set to 1, then 0 is written to OVF2A [Setting condition] When the TCNT2A value overflows (from H'FFFF to H'0000) • Bit 7—Input Capture/Compare-Match Flag 2H (IMF2H): Status flag that indicates GR2H input capture or compare-match. Bit 7: IMF2H 0 1 Description [Clearing condition] When IMF2H is read while set to 1, then 0 is written to IMF2H (Initial value) [Setting conditions] • When the TCNT2A value is transferred to GR2H by an input capture signal while GR2H is functioning as an input capture register • When TCNT2A = GR2H while GR2H is functioning as an output compare register Rev. 3.0, 09/04, page 264 of 1086 • Bit 6—Input Capture/Compare-Match Flag 2G (IMF2G): Status flag that indicates GR2G input capture or compare-match. Bit 6: IMF2G 0 1 Description [Clearing condition] (Initial value) When IMF2G is read while set to 1, then 0 is written to IMF2G [Setting conditions] • When the TCNT2A value is transferred to GR2G by an input capture signal while GR2G is functioning as an input capture register • When TCNT2A = GR2G while GR2G is functioning as an output compare register • Bit 5—Input Capture/Compare-Match Flag 2F (IMF2F): Status flag that indicates GR2F input capture or compare-match. Bit 5: IMF2F 0 1 Description [Clearing condition] When IMF2F is read while set to 1, then 0 is written to IMF2F (Initial value) [Setting conditions] • When the TCNT2A value is transferred to GR2F by an input capture signal while GR2F is functioning as an input capture register • When TCNT2A = GR2F while GR2F is functioning as an output compare register • Bit 4—Input Capture/Compare-Match Flag 2E (IMF2E): Status flag that indicates GR2E input capture or compare-match. Bit 4: IMF2E 0 1 Description [Clearing condition] When IMF2E is read while set to 1, then 0 is written to IMF2E (Initial value) [Setting conditions] • When the TCNT2A value is transferred to GR2E by an input capture signal while GR2E is functioning as an input capture register • When TCNT2A = GR2E while GR2E is functioning as an output compare register Rev. 3.0, 09/04, page 265 of 1086 • Bit 3—Input Capture/Compare-Match Flag 2D (IMF2D): Status flag that indicates GR2D input capture or compare-match. Bit 3: IMF2D 0 1 Description [Clearing condition] When IMF2D is read while set to 1, then 0 is written to IMF2D (Initial value) [Setting conditions] • When the TCNT2A value is transferred to GR2D by an input capture signal while GR2D is functioning as an input capture register • When TCNT2A = GR2D while GR2D is functioning as an output compare register • Bit 2—Input Capture/Compare-Match Flag 2C (IMF2C): Status flag that indicates GR2C input capture or compare-match. Bit 2: IMF2C 0 1 Description [Clearing condition] When IMF2C is read while set to 1, then 0 is written to IMF2C (Initial value) [Setting conditions] • When the TCNT2A value is transferred to GR2C by an input capture signal while GR2C is functioning as an input capture register • When TCNT2A = GR2C while GR2C is functioning as an output compare register • Bit 1—Input Capture/Compare-Match Flag 2B (IMF2B): Status flag that indicates GR2B input capture or compare-match. Bit 1: IMF2B 0 1 Description [Clearing condition] When IMF2B is read while set to 1, then 0 is written to IMF2B [Setting conditions] • • When the TCNT2A value is transferred to GR2B by an input capture signal while GR2B is functioning as an input capture register When TCNT2A = GR2B while GR2B is functioning as an output compare register (Initial value) Rev. 3.0, 09/04, page 266 of 1086 • Bit 0—Input Capture/Compare-Match Flag 2A (IMF2A): Status flag that indicates GR2A input capture or compare-match. Bit 0: IMF2A 0 1 Description [Clearing condition] When IMF2A is read while set to 1, then 0 is written to IMF2A (Initial value) [Setting conditions] • When the TCNT2A value is transferred to GR2A by an input capture signal while GR2A is functioning as an input capture register • When TCNT2A = GR2A while GR2A is functioning as an output compare register TSR2B: TSR2B indicates the status of channel 2 compare-match and overflow. Bit: 15 — Initial value: R/W: Bit: 0 R 7 14 — 0 R 6 13 — 0 R 5 12 — 0 R 4 11 — 0 R 3 10 — 0 R 2 9 — 0 R 1 8 OVF2B 0 R/(W)* 0 CMF2A 0 R/(W)* CMF2H CMF2G CMF2F Initial value: R/W: 0 R/(W)* 0 R/(W)* 0 R/(W)* CMF2E CMF2D CMF2C CMF2B 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* Note: * Only 0 can be written to clear the flag. • Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 8—Overflow Flag 2B (OVF2B): Status flag that indicates TCNT2B overflow. Bit 8: OVF2B 0 1 Description [Clearing condition] (Initial value) When OVF2B is read while set to 1, then 0 is written to OVF2B [Setting condition] When the TCNT2B value overflows (from H'FFFF to H'0000) Rev. 3.0, 09/04, page 267 of 1086 • Bit 7—Compare-Match Flag 2H (CMF2H): Status flag that indicates OCR2H compare-match. Bit 7: CMF2H 0 1 Description [Clearing condition] (Initial value) When CMF2H is read while set to 1, then 0 is written to CMF2H [Setting condition] When TCNT2B = OCR2H • Bit 6—Compare-Match Flag 2G (CMF2G): Status flag that indicates OCR2G compare-match. Bit 6: CMF2G 0 1 Description [Clearing condition] (Initial value) When CMF2G is read while set to 1, then 0 is written to CMF2G [Setting condition] When TCNT2B = OCR2G • Bit 5—Compare-Match Flag 2F (CMF2F): Status flag that indicates OCR2F compare-match. Bit 5: CMF2F 0 1 Description [Clearing condition] (Initial value) When CMF2F is read while set to 1, then 0 is written to CMF2F [Setting condition] When TCNT2B = OCR2F • Bit 4—Compare-Match Flag 2E (CMF2E): Status flag that indicates OCR2E compare-match. Bit 4: CMF2E 0 1 Description [Clearing condition] (Initial value) When CMF2E is read while set to 1, then 0 is written to CMF2E [Setting condition] When TCNT2B = OCR2E • Bit 3—Compare-Match Flag 2D (CMF2D): Status flag that indicates OCR2D compare-match. Bit 3: CMF2D 0 1 Description [Clearing condition] (Initial value) When CMF2D is read while set to 1, then 0 is written to CMF2D [Setting condition] When TCNT2B = OCR2D Rev. 3.0, 09/04, page 268 of 1086 • Bit 2—Compare-Match Flag 2C (CMF2C): Status flag that indicates OCR2C compare-match. Bit 2: CMF2C 0 1 Description [Clearing condition] (Initial value) When CMF2C is read while set to 1, then 0 is written to CMF2C [Setting condition] When TCNT2B = OCR2C • Bit 1—Compare-Match Flag 2B (CMF2B): Status flag that indicates OCR2B compare-match. Bit 1: CMF2B 0 1 Description [Clearing condition] (Initial value) When CMF2B is read while set to 1, then 0 is written to CMF2B [Setting condition] When TCNT2B = OCR2B • Bit 0—Compare-Match Flag 2A (CMF2A): Status flag that indicates OCR2A compare-match. Bit 0: CMF2A 0 1 Description [Clearing condition] (Initial value) When CMF2A is read while set to 1, then 0 is written to CMF2A [Setting condition] When TCNT2B = OCR2A Timer Status Register 3 (TSR3) TSR3 indicates the status of channel 3 to 5 input capture, compare-match, and overflow. Bit: 15 — Initial value: R/W: Bit: 0 R 7 IMF4C Initial value: R/W: 0 R/(W)* 14 OVF5 0 R/(W)* 6 IMF4B 0 R/(W)* 13 IMF5D 0 R/(W)* 5 IMF4A 0 R/(W)* 12 IMF5C 0 R/(W)* 4 OVF3 0 R/(W)* 11 IMF5B 0 R/(W)* 3 IMF3D 0 R/(W)* 10 IMF5A 0 R/(W)* 2 IMF3C 0 R/(W)* 9 OVF4 0 R/(W)* 1 IMF3B 0 R/(W)* 8 IMF4D 0 R/(W)* 0 IMF3A 0 R/(W)* Note: * Only 0 can be written to clear the flag. Rev. 3.0, 09/04, page 269 of 1086 • Bit 15—Reserved: This bit is always read as 0. The write value should always be 0. • Bit 14—Overflow Flag 5 (OVF5): Status flag that indicates TCNT5 overflow. Bit 14: OVF5 0 1 Description [Clearing condition] When OVF5 is read while set to 1, then 0 is written to OVF5 [Setting condition] When the TCNT5 value overflows (from H'FFFF to H'0000) (Initial value) • Bit 13—Input Capture/Compare-Match Flag 5D (IMF5D): Status flag that indicates GR5D input capture or compare-match. Bit 13: IMF5D 0 1 Description [Clearing condition] When IMF5D is read while set to 1, then 0 is written to IMF5D (Initial value) [Setting conditions] • When the TCNT5 value is transferred to GR5D by an input capture signal while GR5D is functioning as an input capture register • • When TCNT5 = GR5D while GR5D is functioning as an output compare register When TCNT5 = GR5D while GR5D is functioning as a cycle register in PWM mode • Bit 12—Input Capture/Compare-Match Flag 5C (IMF5C): Status flag that indicates GR5C input capture or compare-match. The flag is not set in PWM mode. Bit 12: IMF5C 0 1 Description [Clearing condition] When IMF5C is read while set to 1, then 0 is written to IMF5C (Initial value) [Setting conditions] • When the TCNT5 value is transferred to GR5C by an input capture signal while GR5C is functioning as an input capture register • When TCNT5 = GR5C while GR5C is functioning as an output compare register Rev. 3.0, 09/04, page 270 of 1086 • Bit 11—Input Capture/Compare-Match Flag 5B (IMF5B): Status flag that indicates GR5B input capture or compare-match. The flag is not set in PWM mode. Bit 11: IMF5B 0 1 Description [Clearing condition] When IMF5B is read while set to 1, then 0 is written to IMF5B (Initial value) [Setting conditions] • When the TCNT5 value is transferred to GR5B by an input capture signal while GR5B is functioning as an input capture register • When TCNT5 = GR5B while GR5B is functioning as an output compare register • Bit 10—Input Capture/Compare-Match Flag 5A (IMF5A): Status flag that indicates GR5A input capture or compare-match. The flag is not set in PWM mode. Bit 10: IMF5A 0 1 Description [Clearing condition] When IMF5A is read while set to 1, then 0 is written to IMF5A (Initial value) [Setting conditions] • When the TCNT5 value is transferred to GR5A by an input capture signal while GR5A is functioning as an input capture register • When TCNT5 = GR5A while GR5A is functioning as an output compare register • Bit 9—Overflow Flag 4 (OVF4): Status flag that indicates TCNT4 overflow. Bit 9: OVF4 0 1 Description [Clearing condition] When OVF4 is read while set to 1, then 0 is written to OVF4 [Setting condition] When the TCNT4 value overflows (from H'FFFF to H'0000) (Initial value) Rev. 3.0, 09/04, page 271 of 1086 • Bit 8—Input Capture/Compare-Match Flag 4D (IMF4D): Status flag that indicates GR4D input capture or compare-match. Bit 8: IMF4D 0 1 Description [Clearing condition] When IMF4D is read while set to 1, then 0 is written to IMF4D (Initial value) [Setting conditions] • When the TCNT4 value is transferred to GR4D by an input capture signal while GR4D is functioning as an input capture register • • When TCNT4 = GR4D while GR4D is functioning as an output compare register When TCNT4 = GR4D while GR4D is functioning as a PWM mode synchronous register • Bit 7—Input Capture/Compare-Match Flag 4C (IMF4C): Status flag that indicates GR4C input capture or compare-match. The flag is not set in PWM mode. Bit 7: IMF4C 0 1 Description [Clearing condition] When IMF4C is read while set to 1, then 0 is written to IMF4C (Initial value) [Setting conditions] • When the TCNT4 value is transferred to GR4C by an input capture signal while GR4C is functioning as an input capture register • When TCNT4 = GR4C while GR4C is functioning as an output compare register • Bit 6—Input Capture/Compare-Match Flag 4B (IMF4B): Status flag that indicates GR4B input capture or compare-match. The flag is not set in PWM mode. Bit 6: IMF4B 0 1 Description [Clearing condition] When IMF4B is read while set to 1, then 0 is written to IMF4B (Initial value) [Setting conditions] • When the TCNT4 value is transferred to GR4B by an input capture signal while GR4B is functioning as an input capture register • When TCNT4 = GR4B while GR4B is functioning as an output compare register Rev. 3.0, 09/04, page 272 of 1086 • Bit 5—Input Capture/Compare-Match Flag 4A (IMF4A): Status flag that indicates GR4A input capture or compare-match. The flag is not set in PWM mode. Bit 5: IMF4A 0 1 Description [Clearing condition] When IMF4A is read while set to 1, then 0 is written to IMF4A (Initial value) [Setting conditions] • When the TCNT4 value is transferred to GR4A by an input capture signal while GR4A is functioning as an input capture register • When TCNT4 = GR4A while GR4A is functioning as an output compare register • Bit 4—Overflow Flag 3 (OVF3): Status flag that indicates TCNT3 input capture or comparematch. Bit 4: OVF3 0 1 Description [Clearing condition] When OVF3 is read while set to 1, then 0 is written to OVF3 [Setting condition] When the TCNT3 value overflows (from H'FFFF to H'0000) (Initial value) • Bit 3—Input Capture/Compare-Match Flag 3D (IMF3D): Status flag that indicates GR5D input capture or compare-match. Bit 3: IMF3D 0 1 Description [Clearing condition] When IMF3D is read while set to 1, then 0 is written to IMF3D (Initial value) [Setting conditions] • When the TCNT3 value is transferred to GR3D by an input capture signal while GR3D is functioning as an input capture register. However, IMF3D is not set by input capture with a channel 9 compare match as the trigger • • When TCNT3 = GR3D while GR3D is functioning as an output compare register When TCNT3 = GR3D while GR3D is functioning as a synchronous register in PWM mode Rev. 3.0, 09/04, page 273 of 1086 • Bit 2—Input Capture/Compare-Match Flag 3C (IMF3C): Status flag that indicates GR3C input capture or compare-match. The flag is not set in PWM mode. Bit 2: IMF3C 0 1 Description [Clearing condition] When IMF3C is read while set to 1, then 0 is written to IMF3C (Initial value) [Setting conditions] • When the TCNT3 value is transferred to GR3C by an input capture signal while GR3C is functioning as an input capture register. However, IMF3C is not set by input capture with a channel 9 compare match as the trigger • When TCNT3 = GR3C while GR3C is functioning as an output compare register • Bit 1—Input Capture/Compare-Match Flag 3B (IMF3B): Status flag that indicates GR3B input capture or compare-match. The flag is not set in PWM mode. Bit 1: IMF3B 0 1 Description [Clearing condition] When IMF3B is read while set to 1, then 0 is written to IMF3B (Initial value) [Setting conditions] • When the TCNT3 value is transferred to GR3B by an input capture signal while GR3B is functioning as an input capture register. However, IMF3B is not set by input capture with a channel 9 compare match as the trigger • When TCNT3 = GR3B while GR3B is functioning as an output compare register • Bit 0—Input Capture/Compare-Match Flag 3A (IMF3A): Status flag that indicates GR3A input capture or compare-match. The flag is not set in PWM mode. Bit 0: IMF3A 0 1 Description [Clearing condition] When IMF3A is read while set to 1, then 0 is written to IMF3A (Initial value) [Setting conditions] • When the TCNT3 value is transferred to GR3A by an input capture signal while GR3A is functioning as an input capture register. However, IMF3A is not set by input capture with a channel 9 compare match as the trigger • When TCNT3 = GR3A while GR3A is functioning as an output compare register Rev. 3.0, 09/04, page 274 of 1086 Timer Status Registers 6 and 7 (TSR6, TSR7) TSR6 and TRS7 indicate the channel 6 and 7 free-running counter up-count and down-count status, and cycle register compare status. Bit: 15 — Initial value: R/W: Bit: 0 R 7 UDxD Initial value: R/W: 0 R 14 — 0 R 6 UDxC 0 R 13 — 0 R 5 UDxB 0 R 12 — 0 R 4 UDxA 0 R 11 — 0 R 3 CMFxD 0 R/(W)* 10 — 0 R 2 CMFxC 0 R/(W)* 9 — 0 R 1 CMFxB 0 R/(W)* 8 — 0 R 0 CMFxA 0 R/(W)* Note: * Only 0 can be written to clear the flag. x = 6 or 7 UDxA to UDxD relate to TSR6 only. Bits relating to TSR7 always read 0. • Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 7—Count-Up/Count-Down Flag 6D (UD6D): Status flag that indicates the TCNT6D count operation. Bit 7: UD6D 0 1 Description Free-running counter TCNT6D operates as an up-counter Free-running counter TCNT6D operates as a down-counter • Bit 6—Count-Up/Count-Down Flag 6C (UD6C): Status flag that indicates the TCNT6C count operation. Bit 6: UD6C 0 1 Description Free-running counter TCNT6C operates as an up-counter Free-running counter TCNT6C operates as a down-counter Rev. 3.0, 09/04, page 275 of 1086 • Bit 5—Count-Up/Count-Down Flag 6B (UD6B): Status flag that indicates the TCNT6B count operation. Bit 5: UD6B 0 1 Description Free-running counter TCNT6B operates as an up-counter Free-running counter TCNT6B operates as a down-counter • Bit 4—Count-Up/Count-Down Flag 6A (UD6A): Status flag that indicates the TCNT6A count operation. Bit 4: UD6A 0 1 Description Free-running counter TCNT6A operates as an up-counter Free-running counter TCNT6A operates as a down-counter • Bit 3—Cycle Register Compare-Match Flag 6D/7D (CMF6D/CMF7D): Status flag that indicates CYLRxD compare-match. Bit 3: CMFxD 0 1 Description [Clearing condition] (Initial value) When CMFxD is read while set to 1, then 0 is written to CMFxD [Setting conditions] • When TCNTxD = CYLRxD (in non-complementary PWM mode) • When TCNT6D = H'0000 in a down-count (in complementary PWM mode) x = 6 or 7 • Bit 2—Cycle Register Compare-Match Flag 6C/7C (CMF6C/CMF7C): Status flag that indicates CYLRxC compare-match. Bit 2: CMFxC 0 1 Description [Clearing condition] (Initial value) When CMFxC is read while set to 1, then 0 is written to CMFxC [Setting conditions] • When TCNTxC = CYLRxC (in non-complementary PWM mode) • When TCNT6C = H'0000 in a down-count (in complementary PWM mode) x = 6 or 7 Rev. 3.0, 09/04, page 276 of 1086 • Bit 1—Cycle Register Compare-Match Flag 6B/7B (CMF6B/CMF7B): Status flag that indicates CYLRxB compare-match. Bit 1: CMFxB 0 1 Description [Clearing condition] (Initial value) When CMFxB is read while set to 1, then 0 is written to CMFxB [Setting conditions] • When TCNTxB = CYLRxB (in non-complementary PWM mode) • x = 6 or 7 When TCNT6B = H'0000 in a down-count (in complementary PWM mode) • Bit 0—Cycle Register Compare-Match Flag 6A/7A (CMF6A/CMF7A): Status flag that indicates CYLRxA compare-match. Bit 0: CMFxA 0 1 Description [Clearing condition] (Initial value) When CMFxA is read while set to 1, then 0 is written to CMFxA [Setting conditions] • When TCNTxA = CYLRxA (in non-complementary PWM mode) • x = 6 or 7 When TCNT6A = H'0000 in a down-count (in complementary PWM mode) Timer Status Register 8 (TSR8) TSR8 indicates the channel 8 one-shot pulse status. Bit: 15 OSF8P Initial value: R/W: Bit: 0 R/(W)* 7 OSF8H Initial value: R/W: 0 R/(W)* 14 OSF8O 0 R/(W)* 6 OSF8G 0 R/(W)* 13 OSF8N 0 R/(W)* 5 OSF8F 0 R/(W)* 12 OSF8M 0 R/(W)* 4 OSF8E 0 R/(W)* 11 OSF8L 0 R/(W)* 3 OSF8D 0 R/(W)* 10 OSF8K 0 R/(W)* 2 OSF8C 0 R/(W)* 9 OSF8J 0 R/(W)* 1 OSF8B 0 R/(W)* 8 OSF8I 0 R/(W)* 0 OSF8A 0 R/(W)* Note: * Only 0 can be written to clear the flag. Rev. 3.0, 09/04, page 277 of 1086 • Bit 15—One-Shot Pulse Flag 8P (OSF8P): Status flag that indicates a DCNT8P one-shot pulse. Bit 15: OSF8P 0 1 Description [Clearing condition] (Initial value) When OSF8P is read while set to 1, then 0 is written to OSF8P [Setting condition] When DCNT8P underflows • Bit 14—One-Shot Pulse Flag 8O (OSF8O): Status flag that indicates a DCNT8O one-shot pulse. Bit 14: OSF8O 0 1 Description [Clearing condition] (Initial value) When OSF8O is read while set to 1, then 0 is written to OSF8O [Setting condition] When DCNT8O underflows • Bit 13—One-Shot Pulse Flag 8N (OSF8N): Status flag that indicates a DCNT8N one-shot pulse. Bit 13: OSF8N 0 1 Description [Clearing condition] (Initial value) When OSF8N is read while set to 1, then 0 is written to OSF8N [Setting condition] When DCNT8N underflows • Bit 12—One-Shot Pulse Flag 8M (OSF8M): Status flag that indicates a DCNT8M one-shot pulse. Bit 12: OSF8M 0 1 Description [Clearing condition] (Initial value) When OSF8M is read while set to 1, then 0 is written to OSF8M [Setting condition] When DCNT8M underflows Rev. 3.0, 09/04, page 278 of 1086 • Bit 11—One-Shot Pulse Flag 8L (OSF8L): Status flag that indicates a DCNT8L one-shot pulse. Bit 11: OSF8L 0 1 Description [Clearing condition] (Initial value) When OSF8L is read while set to 1, then 0 is written to OSF8L [Setting condition] When DCNT8L underflows • Bit 10—One-Shot Pulse Flag 8K (OSF8K): Status flag that indicates a DCNT8K one-shot pulse. Bit 10: OSF8K 0 1 Description [Clearing condition] (Initial value) When OSF8K is read while set to 1, then 0 is written to OSF8K [Setting condition] When DCNT8K underflows • Bit 9—One-Shot Pulse Flag 8J (OSF8J): Status flag that indicates a DCNT8J one-shot pulse. Bit 9: OSF8J 0 1 Description [Clearing condition] (Initial value) When OSF8J is read while set to 1, then 0 is written to OSF8J [Setting condition] When DCNT8J underflows • Bit 8—One-Shot Pulse Flag 8I (OSF8I): Status flag that indicates a DCNT8I one-shot pulse. Bit 8: OSF8I 0 1 Description [Clearing condition] When OSF8I is read while set to 1, then 0 is written to OSF8I [Setting condition] When DCNT8I underflows (Initial value) Rev. 3.0, 09/04, page 279 of 1086 • Bit 7—One-Shot Pulse Flag 8H (OSF8H): Status flag that indicates a DCNT8H one-shot pulse. Bit 7: OSF8H 0 1 Description [Clearing condition] (Initial value) When OSF8H is read while set to 1, then 0 is written to OSF8H [Setting condition] When DCNT8H underflows • Bit 6—One-Shot Pulse Flag 8G (OSF8G): Status flag that indicates a DCNT8G one-shot pulse. Bit 6: OSF8G 0 1 Description [Clearing condition] (Initial value) When OSF8G is read while set to 1, then 0 is written to OSF8G [Setting condition] When DCNT8G underflows • Bit 5—One-Shot Pulse Flag 8F (OSF8F): Status flag that indicates a DCNT8F one-shot pulse. Bit 5: OSF8F 0 1 Description [Clearing condition] (Initial value) When OSF8F is read while set to 1, then 0 is written to OSF8F [Setting condition] When DCNT8F underflows • Bit 4—One-Shot Pulse Flag 8E (OSF8E): Status flag that indicates a DCNT8E one-shot pulse. Bit 4: OSF8E 0 1 Description [Clearing condition] (Initial value) When OSF8E is read while set to 1, then 0 is written to OSF8E [Setting condition] When DCNT8E underflows Rev. 3.0, 09/04, page 280 of 1086 • Bit 3—One-Shot Pulse Flag 8D (OSF8D): Status flag that indicates a DCNT8D one-shot pulse. Bit 3: OSF8D 0 1 Description [Clearing condition] (Initial value) When OSF8D is read while set to 1, then 0 is written to OSF8D [Setting condition] When DCNT8D underflows • Bit 2—One-Shot Pulse Flag 8C (OSF8C): Status flag that indicates a DCNT8C one-shot pulse. Bit 2: OSF8C 0 1 Description [Clearing condition] (Initial value) When OSF8C is read while set to 1, then 0 is written to OSF8C [Setting condition] When DCNT8C underflows • Bit 1—One-Shot Pulse Flag 8B (OSF8B): Status flag that indicates a DCNT8B one-shot pulse. Bit 1: OSF8B 0 1 Description [Clearing condition] (Initial value) When OSF8B is read while set to 1, then 0 is written to OSF8B [Setting condition] When DCNT8B underflows • Bit 0—One-Shot Pulse Flag 8A (OSF8A): Status flag that indicates a DCNT8A one-shot pulse. Bit 0: OSF8A 0 1 Description [Clearing condition] (Initial value) When OSF8A is read while set to 1, then 0 is written to OSF8A [Setting condition] When DCNT8A underflows Rev. 3.0, 09/04, page 281 of 1086 Timer Status Register 9 (TSR9) TSR9 indicates the channel 9 event counter compare-match status. Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 CMF9F 0 R/(W)* 12 — 0 R 4 11 — 0 R 3 10 — 0 R 2 9 — 0 R 1 8 — 0 R 0 CMF9A 0 R/(W)* CMF9E CMF9D CMF9C CMF9B 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* Note: * Only 0 can be written to clear the flag. • Bits 15 to 6—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 5—Compare-Match Flag 9F (CMF9F): Status flag that indicates GR9F compare-match. Bit 5: CMF9F 0 1 Description [Clearing condition] (Initial value) When CMF9F is read while set to 1, then 0 is written to CMF9F [Setting condition] When the next edge is input while ECNT9F = GR9F • Bit 4—Compare-Match Flag 9E (CMF9E): Status flag that indicates GR9E compare-match. Bit 4: CMF9E 0 1 Description [Clearing condition] (Initial value) When CMF9E is read while set to 1, then 0 is written to CMF9E [Setting condition] When the next edge is input while ECNT9E = GR9E • Bit 3—Compare-Match Flag 9D (CMF9D): Status flag that indicates GR9D compare-match. Bit 3: CMF9D 0 1 Description [Clearing condition] (Initial value) When CMF9D is read while set to 1, then 0 is written to CMF9D [Setting condition] When the next edge is input while ECNT9D = GR9D Rev. 3.0, 09/04, page 282 of 1086 • Bit 2—Compare-Match Flag 9C (CMF9C): Status flag that indicates GR9C compare-match. Bit 2: CMF9C 0 1 Description [Clearing condition] (Initial value) When CMF9C is read while set to 1, then 0 is written to CMF9C [Setting condition] When the next edge is input while ECNT9C = GR9C • Bit 1—Compare-Match Flag 9B (CMF9B): Status flag that indicates GR9B compare-match. Bit 1: CMF9B 0 1 Description [Clearing condition] (Initial value) When CMF9B is read while set to 1, then 0 is written to CMF9B [Setting condition] When the next edge is input while ECNT9B = GR9B • Bit 0—Compare-Match Flag 9A (CMF9A): Status flag that indicates GR9A compare-match. Bit 0: CMF9A 0 1 Description [Clearing condition] (Initial value) When CMF9A is read while set to 1, then 0 is written to CMF9A [Setting condition] When the next edge is input while ECNT9A = GR9A Rev. 3.0, 09/04, page 283 of 1086 Timer Status Register 11 (TSR11) TSR11 indicates the status of channel 11 input capture, compare-match, and overflow. Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 — 0 R 12 — 0 R 4 — 0 R 11 — 0 R 3 — 0 R 10 — 0 R 2 — 0 R 9 — 0 R 1 8 OVF11 0 R/(W)* 0 IMF11B IMF11A 0 R/(W)* 0 R/(W)* Note: * Only 0 can be written to clear the flag. • Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 8—Overflow Flag 11 (OVF11): Status flag that indicates TCNT11 overflow. Bit 8: OVF11 0 1 Description [Clearing condition] (Initial value) When OVF11 is read while set to 1, then 0 is written to OVF11 [Setting condition] When the TCNT11 value overflows (from H'FFFF to H'0000) • Bits 7 to 2—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 1—Input Capture/Compare-Match Flag 11B (IMF11B): Status flag that indicates GR11B input capture or compare-match. Bit 1: IMF11B 0 1 Description [Clearing condition] (Initial value) When IMF11B is read while set to 1, then 0 is written to IMF11B [Setting conditions] • When the TCNT11 value is transferred to GR11B by an input capture signal while GR11B is functioning as an input capture register • When TCNT11 = GR11B while GR11B is functioning as an output compare register Rev. 3.0, 09/04, page 284 of 1086 • Bit 0—Input Capture/Compare-Match Flag 11A (IMF11A): Status flag that indicates GR11A input capture or compare-match. Bit 0: IMF11A 0 1 Description [Clearing condition] (Initial value) When IMF11A is read while set to 1, then 0 is written to IMF11A [Setting conditions] • When the TCNT11 value is transferred to GR11A by an input capture signal while GR11A is functioning as an input capture register • When TCNT11 = GR11A while GR11A is functioning as an output compare register 11.2.6 Timer Interrupt Enable Registers (TIER) The timer interrupt enable registers (TIER) are 16-bit registers. The ATU-II has 11 TIER registers: one each for channels 0, 6 to 9, and 11, two each for channels 1 and 2, and one for channels 3 to 5. For details of channel 10, see section 11.2.26, Channel 10 Registers. Channel 0 1 2 3 4 5 6 7 8 9 11 TIER6 TIER7 TIER8 TIER9 TIER11 Control cycle register compare-match interrupt request enabling/disabling. Controls down-counter output end (low) interrupt request enabling/disabling. Controls event counter compare-match interrupt request enabling/disabling. Controls input capture, compare-match, and overflow interrupt request enabling/disabling. Abbreviation TIER0 TIER1A, TIER1B TIER2A, TIER2B TIER3 Function Controls input capture, and overflow interrupt request enabling/disabling. Control input capture, compare-match, and overflow interrupt request enabling/disabling. Controls input capture, compare-match, and overflow interrupt request enabling/disabling. The TIER registers are 16-bit readable/writable registers that control enabling/disabling of freerunning counter (TCNT) overflow interrupt requests, channel 0 input capture interrupt requests, channel 1 to 5 and 11 general register input capture/compare-match interrupt requests, channel 6 and 7 compare-match interrupt requests, channel 8 down-counter output end interrupt requests, and channel 9 event counter compare-match interrupt requests. Rev. 3.0, 09/04, page 285 of 1086 Each TIER is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Timer Interrupt Enable Register 0 (TIER0) TIER0 controls enabling/disabling of channel 0 input capture and overflow interrupt requests. Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 — 0 R 12 — 0 R 4 OVE0 0 R/W 11 — 0 R 3 ICE0D 0 R/W 10 — 0 R 2 ICE0C 0 R/W 9 — 0 R 1 ICE0B 0 R/W 8 — 0 R 0 ICE0A 0 R/W • Bits 15 to 5—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 4—Overflow Interrupt Enable 0 (OVE0): Enables or disables interrupt requests by the overflow flag (OVF0) in TSR0 when OVF0 is set to 1. Bit 4: OVE0 0 1 Description OVI0 interrupt requested by OVF0 is disabled OVI0 interrupt requested by OVF0 is enabled (Initial value) • Bit 3—Input Capture Interrupt Enable 0D (ICE0D): Enables or disables interrupt requests by the input capture flag (ICF0D) in TSR0 when ICF0D is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 3: ICE0D 0 1 Description ICI0D interrupt requested by ICF0D is disabled ICI0D interrupt requested by ICF0D is enabled (Initial value) Rev. 3.0, 09/04, page 286 of 1086 • Bit 2—Input Capture Interrupt Enable 0C (ICE0C): Enables or disables interrupt requests by the input capture flag (ICF0C) in TSR0 when ICF0C is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 2: ICE0C 0 1 Description ICI0C interrupt requested by ICF0C is disabled ICI0C interrupt requested by ICF0C is enabled (Initial value) • Bit 1—Input Capture Interrupt Enable 0B (ICE0B): Enables or disables interrupt requests by the input capture flag (ICF0B) in TSR0 when ICF0B is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 1: ICE0B 0 1 Description ICI0B interrupt requested by ICF0B is disabled ICI0B interrupt requested by ICF0B is enabled (Initial value) • Bit 0—Input Capture Interrupt Enable 0A (ICE0A): Enables or disables interrupt requests by the input capture flag (ICF0A) in TSR0 when ICF0A is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 0: ICE0A 0 1 Description ICI0A interrupt requested by ICF0A is disabled ICI0A interrupt requested by ICF0A is enabled (Initial value) Timer Interrupt Enable Registers 1A and 1B (TIER1A, TIER1B) TIER1A: TIER1A controls enabling/disabling of channel 1 input capture, compare-match, and overflow interrupt requests. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 — 0 R 7 IME1H 0 R/W 14 — 0 R 6 IME1G 0 R/W 13 — 0 R 5 IME1F 0 R/W 12 — 0 R 4 IME1E 0 R/W 11 — 0 R 3 IME1D 0 R/W 10 — 0 R 2 IME1C 0 R/W 9 — 0 R 1 IME1B 0 R/W 8 OVE1A 0 R/W 0 IME1A 0 R/W Rev. 3.0, 09/04, page 287 of 1086 • Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 8—Overflow Interrupt Enable 1A (OVE1A): Enables or disables interrupt requests by OVF1A in TSR1A when OVF1A is set to 1. Bit 8: OVE1A 0 1 Description OVI1A interrupt requested by OVF1A is disabled OVI1A interrupt requested by OVF1A is enabled (Initial value) • Bit 7—Input Capture/Compare-Match Interrupt Enable 1H (IME1H): Enables or disables interrupt requests by IMF1H in TSR1A when IMF1H is set to 1. Bit 7: IME1H 0 1 Description IMI1H interrupt requested by IMF1H is disabled IMI1H interrupt requested by IMF1H is enabled (Initial value) • Bit 6—Input Capture/Compare-Match Interrupt Enable 1G (IME1G): Enables or disables interrupt requests by IMF1G in TSR1A when IMF1G is set to 1. Bit 6: IME1G 0 1 Description IMI1G interrupt requested by IMF1G is disabled IMI1G interrupt requested by IMF1G is enabled (Initial value) • Bit 5—Input Capture/Compare-Match Interrupt Enable 1F (IME1F): Enables or disables interrupt requests by IMF1F in TSR1A when IMF1F is set to 1. Bit 5: IME1F 0 1 Description IMI1F interrupt requested by IMF1F is disabled IMI1F interrupt requested by IMF1F is enabled (Initial value) • Bit 4—Input Capture/Compare-Match Interrupt Enable 1E (IME1E): Enables or disables interrupt requests by IMF1E in TSR1A when IMF1E is set to 1. Bit 4: IME1E 0 1 Description IMI1E interrupt requested by IMF1E is disabled IMI1E interrupt requested by IMF1E is enabled (Initial value) Rev. 3.0, 09/04, page 288 of 1086 • Bit 3—Input Capture/Compare-Match Interrupt Enable 1D (IME1D): Enables or disables interrupt requests by IMF1D in TSR1A when IMF1D is set to 1. Bit 3: IME1D 0 1 Description IMI1D interrupt requested by IMF1D is disabled IMI1D interrupt requested by IMF1D is enabled (Initial value) • Bit 2—Input Capture/Compare-Match Interrupt Enable 1C (IME1C): Enables or disables interrupt requests by IMF1C in TSR1A when IMF1C is set to 1. Bit 2: IME1C 0 1 Description IMI1C interrupt requested by IMF1C is disabled IMI1C interrupt requested by IMF1C is enabled (Initial value) • Bit 1—Input Capture/Compare-Match Interrupt Enable 1B (IME1B): Enables or disables interrupt requests by IMF1B in TSR1A when IMF1B is set to 1. Bit 1: IME1B 0 1 Description IMI1B interrupt requested by IMF1B is disabled IMI1B interrupt requested by IMF1B is enabled (Initial value) • Bit 0—Input Capture/Compare-Match Interrupt Enable 1A (IME1A): Enables or disables interrupt requests by IMF1A in TSR1A when IMF1A is set to 1. Bit 0: IME1A 0 1 Description IMI1A interrupt requested by IMF1A is disabled IMI1A interrupt requested by IMF1A is enabled (Initial value) Rev. 3.0, 09/04, page 289 of 1086 TIER1B: TIER1B controls enabling/disabling of channel 1 compare-match and overflow interrupt requests. Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 — 0 R 12 — 0 R 4 — 0 R 11 — 0 R 3 — 0 R 10 — 0 R 2 — 0 R 9 — 0 R 1 — 0 R 8 OVE1B 0 R/W 0 CME1 0 R/W • Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 8—Overflow Interrupt Enable 1B (OVE1B): Enables or disables interrupt requests by OVF1B in TSR1B when OVF1B is set to 1. Bit 8: OVE1B 0 1 Description OVI1B interrupt requested by OVF1B is disabled OVI1B interrupt requested by OVF1B is enabled (Initial value) • Bits 7 to 1—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 0—Compare-Match Interrupt Enable 1 (CME1): Enables or disables interrupt requests by CMF1 in TSR1B when CMF1 is set to 1. Bit 0: CME1 0 1 Description CMI1 interrupt requested by CMF1 is disabled CMI1 interrupt requested by CMF1 is enabled (Initial value) Rev. 3.0, 09/04, page 290 of 1086 Timer Interrupt Enable Registers 2A and 2B (TIER2A, TIER2B) TIER2A: TIER2A controls enabling/disabling of channel 2 input capture, compare-match, and overflow interrupt requests. Bit: 15 — Initial value: R/W: Bit: 0 R 7 IME2H Initial value: R/W: 0 R/W 14 — 0 R 6 IME2G 0 R/W 13 — 0 R 5 IME2F 0 R/W 12 — 0 R 4 IME2E 0 R/W 11 — 0 R 3 IME2D 0 R/W 10 — 0 R 2 IME2C 0 R/W 9 — 0 R 1 IME2B 0 R/W 8 OVE2A 0 R/W 0 IME2A 0 R/W • Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 8—Overflow Interrupt Enable 2A (OVE2A): Enables or disables interrupt requests by OVF2A in TSR2A when OVF2A is set to 1. Bit 8: OVE2A 0 1 Description OVI2A interrupt requested by OVF2A is disabled OVI2A interrupt requested by OVF2A is enabled (Initial value) • Bit 7—Input Capture/Compare-Match Interrupt Enable 2H (IME2H): Enables or disables interrupt requests by IMF2H in TSR2A when IMF2H is set to 1. Bit 7: IME2H 0 1 Description IMI2H interrupt requested by IMF2H is disabled IMI2H interrupt requested by IMF2H is enabled (Initial value) • Bit 6—Input Capture/Compare-Match Interrupt Enable 2G (IME2G): Enables or disables interrupt requests by IMF2G in TSR2A when IMF2G is set to 1. Bit 6: IME2G 0 1 Description IMI2G interrupt requested by IMF2G is disabled IMI2G interrupt requested by IMF2G is enabled (Initial value) Rev. 3.0, 09/04, page 291 of 1086 • Bit 5—Input Capture/Compare-Match Interrupt Enable 2F (IME2F): Enables or disables interrupt requests by IMF2F in TSR2A when IMF2F is set to 1. Bit 5: IME2F 0 1 Description IMI2F interrupt requested by IMF2F is disabled IMI2F interrupt requested by IMF2F is enabled (Initial value) • Bit 4—Input Capture/Compare-Match Interrupt Enable 2E (IME2E): Enables or disables interrupt requests by IMF2E in TSR2A when IMF2E is set to 1. Bit 4: IME2E 0 1 Description IMI2E interrupt requested by IMF2E is disabled IMI2E interrupt requested by IMF2E is enabled (Initial value) • Bit 3—Input Capture/Compare-Match Interrupt Enable 2D (IME2D): Enables or disables interrupt requests by IMF2D in TSR2A when IMF2D is set to 1. Bit 3: IME2D 0 1 Description IMI2D interrupt requested by IMF2D is disabled IMI2D interrupt requested by IMF2D is enabled (Initial value) • Bit 2—Input Capture/Compare-Match Interrupt Enable 2C (IME2C): Enables or disables interrupt requests by IMF2C in TSR2A when IMF2C is set to 1. Bit 2: IME2C 0 1 Description IMI2C interrupt requested by IMF2C is disabled IMI2C interrupt requested by IMF2C is enabled (Initial value) • Bit 1—Input Capture/Compare-Match Interrupt Enable 2B (IME2B): Enables or disables interrupt requests by IMF2B in TSR2A when IMF2B is set to 1. Bit 1: IME2B 0 1 Description IMI2B interrupt requested by IMF2B is disabled IMI2B interrupt requested by IMF2B is enabled (Initial value) Rev. 3.0, 09/04, page 292 of 1086 • Bit 0—Input Capture/Compare-Match Interrupt Enable 2A (IME2A): Enables or disables interrupt requests by IMF2A in TSR2A when IMF2A is set to 1. Bit 0: IME2A 0 1 Description IMI2A interrupt requested by IMF2A is disabled IMI2A interrupt requested by IMF2A is enabled (Initial value) TIER2B: TIER2B controls enabling/disabling of channel 2 compare-match and overflow interrupt requests. Bit: 15 — Initial value: R/W: Bit: 0 R 7 CME2H Initial value: R/W: 0 R/W 14 — 0 R 6 CME2G 0 R/W 13 — 0 R 5 CME2F 0 R/W 12 — 0 R 4 CME2E 0 R/W 11 — 0 R 3 CME2D 0 R/W 10 — 0 R 2 CME2C 0 R/W 9 — 0 R 1 CME2B 0 R/W 8 OVE2B 0 R/W 0 CME2A 0 R/W • Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 8—Overflow Interrupt Enable 2B (OVE2B): Enables or disables interrupt requests by OVF2B in TSR2B when OVF2B is set to 1. Bit 8: OVE2B 0 1 Description OVI2B interrupt requested by OVF2B is disabled OVI2B interrupt requested by OVF2B is enabled (Initial value) • Bit 7—Compare-Match Interrupt Enable 2H (CME2H): Enables or disables interrupt requests by CMF2F in TSR2B when CMF2H is set to 1. Bit 7: CME2H 0 1 Description CMI2H interrupt requested by CMF2H is disabled CMI2H interrupt requested by CMF2H is enabled (Initial value) Rev. 3.0, 09/04, page 293 of 1086 • Bit 6—Compare-Match Interrupt Enable 2G (CME2G): Enables or disables interrupt requests by CMF2G in TSR2B when CMF2G is set to 1. Bit 6: CME2G 0 1 Description CMI2G interrupt requested by CMF2G is disabled CMI2G interrupt requested by CMF2G is enabled (Initial value) • Bit 5—Compare-Match Interrupt Enable 2F (CME2F): Enables or disables interrupt requests by CMF2F in TSR2B when CMF2F is set to 1. Bit 5: CME2F 0 1 Description CMI2F interrupt requested by CMF2F is disabled CMI2F interrupt requested by CMF2F is enabled (Initial value) • Bit 4—Compare-Match Interrupt Enable 2E (CME2E): Enables or disables interrupt requests by CMF2E in TSR2B when CMF2E is set to 1. Bit 4: CME2E 0 1 Description CMI2E interrupt requested by CMF2E is disabled CMI2E interrupt requested by CMF2E is enabled (Initial value) • Bit 3—Compare-Match Interrupt Enable 2D (CME2D): Enables or disables interrupt requests by CMF2D in TSR2B when CMF2D is set to 1. Bit 3: CME2D 0 1 Description CMI2D interrupt requested by CMF2D is disabled CMI2D interrupt requested by CMF2D is enabled (Initial value) • Bit 2—Compare-Match Interrupt Enable 2C (CME2C): Enables or disables interrupt requests by CMF2C in TSR2B when CMF2C is set to 1. Bit 2: CME2C 0 1 Description CMI2C interrupt requested by CMF2C is disabled CMI2C interrupt requested by CMF2C is enabled (Initial value) Rev. 3.0, 09/04, page 294 of 1086 • Bit 1—Compare-Match Interrupt Enable 2B (CME2BB): Enables or disables interrupt requests by CMF2B in TSR2B when CMF2B is set to 1. Bit 1: CME2B 0 1 Description CMI2B interrupt requested by CMF2B is disabled CMI2B interrupt requested by CMF2B is enabled (Initial value) • Bit 0—Compare-Match Interrupt Enable 2A (CME2A): Enables or disables interrupt requests by CMF2A in TSR2B when CMF2A is set to 1. Bit 0: CME2A 0 1 Description CMI2A interrupt requested by CMF2A is disabled CMI2A interrupt requested by CMF2A is enabled (Initial value) Timer Interrupt Enable Register 3 (TIER3) TIER3 controls enabling/disabling of channel 3 to 5 input capture, compare-match, and overflow interrupt requests. Bit: 15 — Initial value: R/W: Bit: 0 R 7 IME4C Initial value: R/W: 0 R/W 14 OVE5 0 R/W 6 IME4B 0 R/W 13 IME5D 0 R/W 5 IME4A 0 R/W 12 IME5C 0 R/W 4 OVE3 0 R/W 11 IME5B 0 R/W 3 IME3D 0 R/W 10 IME5A 0 R/W 2 IME3C 0 R/W 9 OVE4 0 R/W 1 IME3B 0 R/W 8 IME4D 0 R/W 0 IME3A 0 R/W • Bit 15—Reserved: This bit is always read as 0. The write value should always be 0. • Bit 14—Overflow Interrupt Enable 5 (OVE5): Enables or disables interrupt requests by OVF5 in TSR3 when OVF5 is set to 1. Bit 14: OVE5 0 1 Description OVI5 interrupt requested by OVF5 is disabled OVI5 interrupt requested by OVF5 is enabled (Initial value) Rev. 3.0, 09/04, page 295 of 1086 • Bit 13—Input Capture/Compare-Match Interrupt Enable 5D (IME5D): Enables or disables interrupt requests by IMF5D in TSR3 when IMF5D is set to 1. Bit 13: IME5D 0 1 Description IMI5D interrupt requested by IMF5D is disabled IMI5D interrupt requested by IMF5D is enabled (Initial value) • Bit 12—Input Capture/Compare-Match Interrupt Enable 5C (IME5C): Enables or disables interrupt requests by IMF5C in TSR3 when IMF5C is set to 1. Bit 12: IME5C 0 1 Description IMI5C interrupt requested by IMF5C is disabled IMI5C interrupt requested by IMF5C is enabled (Initial value) • Bit 11—Input Capture/Compare-Match Interrupt Enable 5B (IME5B): Enables or disables interrupt requests by IMF5B in TSR3 when IMF5B is set to 1. Bit 11: IME5B 0 1 Description IMI5B interrupt requested by IMF5B is disabled IMI5B interrupt requested by IMF5B is enabled (Initial value) • Bit 10—Input Capture/Compare-Match Interrupt Enable 5A (IME5A): Enables or disables interrupt requests by IMF5A in TSR3 when IMF5A is set to 1. Bit 10: IME5A 0 1 Description IMI5A interrupt requested by IMF5A is disabled IMI5A interrupt requested by IMF5A is enabled (Initial value) • Bit 9—Overflow Interrupt Enable 4 (OVE4): Enables or disables interrupt requests by OVF4 in TSR3 when OVF4 is set to 1. Bit 9: OVE4 0 1 Description OVI4 interrupt requested by OVF4 is disabled OVI4 interrupt requested by OVF4 is enabled (Initial value) Rev. 3.0, 09/04, page 296 of 1086 • Bit 8—Input Capture/Compare-Match Interrupt Enable 4D (IME4D): Enables or disables interrupt requests by IMF4D in TSR3 when IMF4D is set to 1. Bit 8: IME4D 0 1 Description IMI4D interrupt requested by IMF4D is disabled IMI4D interrupt requested by IMF4D is enabled (Initial value) • Bit 7—Input Capture/Compare-Match Interrupt Enable 4C (IME4C): Enables or disables interrupt requests by IMF4C in TSR3 when IMF4C is set to 1. Bit 7: IME4C 0 1 Description IMI4C interrupt requested by IMF4C is disabled IMI4C interrupt requested by IMF4C is enabled (Initial value) • Bit 6—Input Capture/Compare-Match Interrupt Enable 4B (IME4B): Enables or disables interrupt requests by IMF4B in TSR3 when IMF4B is set to 1. Bit 6: IME4B 0 1 Description IMI4B interrupt requested by IMF4B is disabled IMI4B interrupt requested by IMF4B is enabled (Initial value) • Bit 5—Input Capture/Compare-Match Interrupt Enable 4A (IME4A): Enables or disables interrupt requests by IMF4A in TSR3 when IMF4A is set to 1. Bit 5: IME4A 0 1 Description IMI4A interrupt requested by IMF4A is disabled IMI4A interrupt requested by IMF4A is enabled (Initial value) • Bit 4—Overflow Interrupt Enable 3 (OVE3): Enables or disables interrupt requests by OVF3 in TSR3 when OVF3 is set to 1. Bit 4: OVE3 0 1 Description OVI3 interrupt requested by OVF3 is disabled OVI3 interrupt requested by OVF3 is enabled (Initial value) Rev. 3.0, 09/04, page 297 of 1086 • Bit 3—Input Capture/Compare-Match Interrupt Enable 3D (IME3D): Enables or disables interrupt requests by IMF3D in TSR3 when IMF3D is set to 1. Bit 3: IME3D 0 1 Description IMI3D interrupt requested by IMF3D is disabled IMI3D interrupt requested by IMF3D is enabled (Initial value) • Bit 2—Input Capture/Compare-Match Interrupt Enable 3C (IME3C): Enables or disables interrupt requests by IMF3C in TSR3 when IMF3C is set to 1. Bit 2: IME3C 0 1 Description IMI3C interrupt requested by IMF3C is disabled IMI3C interrupt requested by IMF3C is enabled (Initial value) • Bit 1—Input Capture/Compare-Match Interrupt Enable 3B (IME3B): Enables or disables interrupt requests by IMF3B in TSR3 when IMF3B is set to 1. Bit 1: IME3B 0 1 Description IMI3B interrupt requested by IMF3B is disabled IMI3B interrupt requested by IMF3B is enabled (Initial value) • Bit 0—Input Capture/Compare-Match Interrupt Enable 3A (IME3A): Enables or disables interrupt requests by IMF3A in TSR3 when IMF3A is set to 1. Bit 0: IME3A 0 1 Description IMI3A interrupt requested by IMF3A is disabled IMI3A interrupt requested by IMF3A is enabled (Initial value) Rev. 3.0, 09/04, page 298 of 1086 Timer Interrupt Enable Registers 6 and 7 (TIER6, TIER7) TIER6 and TIER7 control enabling/disabling of channel 6 and 7 cycle register compare interrupt requests. Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: x = 6 or 7 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 — 0 R 12 — 0 R 4 — 0 R 11 — 0 R 3 10 — 0 R 2 9 — 0 R 1 8 — 0 R 0 CMExA 0 R/W CMExD CMExC CMExB 0 R/W 0 R/W 0 R/W • Bits 15 to 4—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 3—Cycle Register Compare-Match Interrupt Enable 6D/7D (CME6D/CME7D): Enables or disables interrupt requests by CMFxD in TSR6 or TSR7 when CMFxD is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 3: CMExD 0 1 x = 6 or 7 Description CMIxD interrupt requested by CMFxD is disabled CMIxD interrupt requested by CMFxD is enabled (Initial value) • Bit 2—Cycle Register Compare-Match Interrupt Enable 6C/7C (CME6C/CME7C): Enables or disables interrupt requests by CMFxC in TSR6 or TSR7 when CMFxC is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 2: CMExC 0 1 x = 6 or 7 Description CMIxC interrupt requested by CMFxC is disabled CMIxC interrupt requested by CMFxC is enabled (Initial value) Rev. 3.0, 09/04, page 299 of 1086 • Bit 1—Cycle Register Compare-Match Interrupt Enable 6B/7B (CME6B/CME7B): Enables or disables interrupt requests by CMFxB in TSR6 or TSR7 when CMFxB is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 1: CMExB 0 1 x = 6 or 7 Description CMIxB interrupt requested by CMFxB is disabled CMIxB interrupt requested by CMFxB is enabled (Initial value) • Bit 0—Cycle Register Compare-Match Interrupt Enable 6A/7A (CME6A/CME7A): Enables or disables interrupt requests by CMFxA in TSR6 or TSR7 when CMFxA is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 0: CMExA 0 1 x = 6 or 7 Description CMIxA interrupt requested by CMFxA is disabled CMIxA interrupt requested by CMFxA is enabled (Initial value) Timer Interrupt Enable Register 8 (TIER8) TIER8 controls enabling/disabling of channel 8 one-shot pulse interrupt requests. Bit: 15 OSE8P Initial value: R/W: Bit: 0 R/W 7 14 13 12 11 OSE8L 0 R/W 3 OSE8D 0 R/W 10 OSE8K 0 R/W 2 OSE8C 0 R/W 9 OSE8J 0 R/W 1 OSE8B 0 R/W 8 OSE8I 0 R/W 0 OSE8A 0 R/W OSE8O OSE8N OSE8M 0 R/W 6 0 R/W 5 OSE8F 0 R/W 0 R/W 4 OSE8E 0 R/W OSE8H OSE8G Initial value: R/W: 0 R/W 0 R/W Rev. 3.0, 09/04, page 300 of 1086 • Bit 15—One-Shot Pulse Interrupt Enable 8P (OSE8P): Enables or disables interrupt requests by OSF8P in TSR8 when OSF8P is set to 1. Bit 15: OSE8P 0 1 Description OSI8P interrupt requested by OSF8P is disabled OSI8P interrupt requested by OSF8P is enabled (Initial value) • Bit 14—One-Shot Pulse Interrupt Enable 8O (OSE8O): Enables or disables interrupt requests by OSF8O in TSR8 when OSF8O is set to 1. Bit 14: OSE8O 0 1 Description OSI8O interrupt requested by OSF8O is disabled OSI8O interrupt requested by OSF8O is enabled (Initial value) • Bit 13—One-Shot Pulse Interrupt Enable 8N (OSE8N): Enables or disables interrupt requests by OSF8N in TSR8 when OSF8N is set to 1. Bit 13: OSE8N 0 1 Description OSI8N interrupt requested by OSF8N is disabled OSI8N interrupt requested by OSF8N is enabled (Initial value) • Bit 12—One-Shot Pulse Interrupt Enable 8M (OSE8M): Enables or disables interrupt requests by OSF8M in TSR8 when OSF8M is set to 1. Bit 12: OSE8M 0 1 Description OSI8M interrupt requested by OSF8M is disabled OSI8M interrupt requested by OSF8M is enabled (Initial value) • Bit 11—One-Shot Pulse Interrupt Enable 8L (OSE8L): Enables or disables interrupt requests by OSF8L in TSR8 when OSF8L is set to 1. Bit 11: OSE8L 0 1 Description OSI8L interrupt requested by OSF8L is disabled OSI8L interrupt requested by OSF8L is enabled (Initial value) • Bit 10—One-Shot Pulse Interrupt Enable 8K (OSE8K): Enables or disables interrupt requests by OSF8K in TSR8 when OSF8K is set to 1. Rev. 3.0, 09/04, page 301 of 1086 Bit 10: OSE8K 0 1 Description OSI8K interrupt requested by OSF8K is disabled OSI8K interrupt requested by OSF8K is enabled (Initial value) • Bit 9—One-Shot Pulse Interrupt Enable 8J (OSE8J): Enables or disables interrupt requests by OSF8J in TSR8 when OSF8J is set to 1. Bit 9: OSE8J 0 1 Description OSI8J interrupt requested by OSF8J is disabled OSI8J interrupt requested by OSF8J is enabled (Initial value) • Bit 8—One-Shot Pulse Interrupt Enable 8I (OSE8I): Enables or disables interrupt requests by OSF8I in TSR8 when OSF8I is set to 1. Bit 8: OSE8I 0 1 Description OSI8I interrupt requested by OSF8I is disabled OSI8I interrupt requested by OSF8I is enabled (Initial value) • Bit 7—One-Shot Pulse Interrupt Enable 8H (OSE8H): Enables or disables interrupt requests by OSF8H in TSR8 when OSF8H is set to 1. Bit 7: OSE8H 0 1 Description OSI8H interrupt requested by OSF8H is disabled OSI8H interrupt requested by OSF8H is enabled (Initial value) • Bit 6—One-Shot Pulse Interrupt Enable 8G (OSE8G): Enables or disables interrupt requests by OSF8G in TSR8 when OSF8G is set to 1. Bit 6: OSE8G 0 1 Description OSI8G interrupt requested by OSF8G is disabled OSI8G interrupt requested by OSF8G is enabled (Initial value) • Bit 5—One-Shot Pulse Interrupt Enable 8F (OSE8F): Enables or disables interrupt requests by OSF8F in TSR8 when OSF8F is set to 1. Bit 5: OSE8F 0 1 Description OSI8F interrupt requested by OSF8F is disabled OSI8F interrupt requested by OSF8F is enabled (Initial value) Rev. 3.0, 09/04, page 302 of 1086 • Bit 4—One-Shot Pulse Interrupt Enable 8E (OSE8E): Enables or disables interrupt requests by OSF8E in TSR8 when OSF8E is set to 1. Bit 4: OSE8E 0 1 Description OSI8E interrupt requested by OSF8E is disabled OSI8E interrupt requested by OSF8E is enabled (Initial value) • Bit 3—One-Shot Pulse Interrupt Enable 8D (OSE8D): Enables or disables interrupt requests by OSF8D in TSR8 when OSF8D is set to 1. Bit 3: OSE8D 0 1 Description OSI8D interrupt requested by OSF8D is disabled OSI8D interrupt requested by OSF8D is enabled (Initial value) • Bit 2—One-Shot Pulse Interrupt Enable 8C (OSE8C): Enables or disables interrupt requests by OSF8C in TSR8 when OSF8C is set to 1. Bit 2: OSE8C 0 1 Description OSI8C interrupt requested by OSF8C is disabled OSI8C interrupt requested by OSF8C is enabled (Initial value) • Bit 1—One-Shot Pulse Interrupt Enable 8B (OSE8B): Enables or disables interrupt requests by OSF8B in TSR8 when OSF8B is set to 1. Bit 1: OSE8B 0 1 Description OSI8B interrupt requested by OSF8B is disabled OSI8B interrupt requested by OSF8B is enabled (Initial value) • Bit 0—One-Shot Pulse Interrupt Enable 8A (OSE8A): Enables or disables interrupt requests by OSF8A in TSR8 when OSF8A is set to 1. Bit 0: OSE8A 0 1 Description OSI8A interrupt requested by OSF8A is disabled OSI8A interrupt requested by OSF8A is enabled (Initial value) Rev. 3.0, 09/04, page 303 of 1086 Timer Interrupt Enable Register 9 (TIER9) TIER9 controls enabling/disabling of channel 9 event counter compare-match interrupt requests. Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 12 — 0 R 4 11 — 0 R 3 10 — 0 R 2 9 — 0 R 1 8 — 0 R 0 CME9F CME9E CME9D CME9C CME9B CME9A 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W • Bits 15 to 6—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 5—Compare-Match Interrupt Enable 9F (CME9F): Enables or disables interrupt requests by CMF9F in TSR9 when CMF9F is set to 1. Bit 5: CME9F 0 1 Description CMI9F interrupt requested by CMF9F is disabled CMI9F interrupt requested by CMF9F is enabled (Initial value) • Bit 4—Compare-Match Interrupt Enable 9E (CME9E): Enables or disables interrupt requests by CMF9E in TSR9 when CMF9E is set to 1. Bit 4: CME9E 0 1 Description CMI9E interrupt requested by CMF9E is disabled CMI9E interrupt requested by CMF9E is enabled (Initial value) • Bit 3—Compare-Match Interrupt Enable 9D (CME9D): Enables or disables interrupt requests by CMF9D in TSR9 when CMF9D is set to 1. Bit 3: CME9D 0 1 Description CMI9D interrupt requested by CMF9D is disabled CMI9D interrupt requested by CMF9D is enabled (Initial value) Rev. 3.0, 09/04, page 304 of 1086 • Bit 2—Compare-Match Interrupt Enable 9C (CME9C): Enables or disables interrupt requests by CMF9C in TSR9 when CMF9C is set to 1. Bit 2: CME9C 0 1 Description CMI9C interrupt requested by CMF9C is disabled CMI9C interrupt requested by CMF9C is enabled (Initial value) • Bit 1—Compare-Match Interrupt Enable 9B (CME9B): Enables or disables interrupt requests by CMF9B in TSR9 when CMF9B is set to 1. Bit 1: CME9B 0 1 Description CMI9B interrupt requested by CMF9B is disabled CMI9B interrupt requested by CMF9B is enabled (Initial value) • Bit 0—Compare-Match Interrupt Enable 9A (CME9A): Enables or disables interrupt requests by CMF9A in TSR9 when CMF9A is set to 1. Bit 0: CME9A 0 1 Description CMI9A interrupt requested by CMF9A is disabled CMI9A interrupt requested by CMF9A is enabled (Initial value) Timer Interrupt Enable Register 11 (TIER11) TIER11 controls enabling/disabling of channel 11 input capture, compare-match, and overflow interrupt requests. Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 — 0 R 12 — 0 R 4 — 0 R 11 — 0 R 3 — 0 R 10 — 0 R 2 — 0 R 9 — 0 R 1 8 OVE11 0 R/W 0 IME11B IME11A 0 R/W 0 R/W • Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0. Rev. 3.0, 09/04, page 305 of 1086 • Bit 8—Overflow Interrupt Enable 11 (OVE11): Enables or disables interrupt requests by OVF11 in TSR11 when OVF11 is set to 1. Bit 8: OVE11 0 1 Description OVI11 interrupt requested by OVF11 is disabled OVI11 interrupt requested by OVF11 is enabled (Initial value) • Bits 7 to 2—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 1—Input Capture/Compare-Match Interrupt Enable 11B (IME11B): Enables or disables interrupt requests by IMF11B in TSR11 when IMF11B is set to 1. Bit 1: IME11B 0 1 Description IMI11B interrupt requested by IMF11B is disabled IMI11B interrupt requested by IMF11B is enabled (Initial value) • Bit 0—Input Capture/Compare-Match Interrupt Enable 11A (IME11A): Enables or disables interrupt requests by IMF11A in TSR11 when IMF11A is set to 1. Bit 0: IME11A 0 1 Description IMI11A interrupt requested by IMF11A is disabled IMI11A interrupt requested by IMF11A is enabled (Initial value) 11.2.7 Interval Interrupt Request Registers (ITVRR) The interval interrupt request registers (ITVRR) are 8-bit registers. The ATU-II has three ITVRR registers in channel 0. Channel 0 Abbreviation ITVRR1 ITVRR2A ITVRR2B Function TCNT0 bit 6 to 9 interval interrupt generation and A/D2 converter activation TCNT0 bit 10 to 13 interval interrupt generation and A/D0 converter activation TCNT0 bit 10 to 13 interval interrupt generation and A/D1 converter activation Rev. 3.0, 09/04, page 306 of 1086 Interval Interrupt Request Register 1 (ITVRR1) Bit: 7 ITVA9 Initial value: R/W: 0 R/W 6 ITVA8 0 R/W 5 ITVA7 0 R/W 4 ITVA6 0 R/W 3 ITVE9 0 R/W 2 ITVE8 0 R/W 1 ITVE7 0 R/W 0 ITVE6 0 R/W ITVRR1 is an 8-bit readable/writable register that detects the rise of bits corresponding to the channel 0 free-running counter (TCNT0) and controls cyclic interrupt output and A/D2 converter activation. ITVRR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—A/D2 Converter Interval Activation Bit 9 (ITVA9): A/D2 converter activation setting bit corresponding to bit 9 in TCNT0. The rise of bit 9 in TCNT0 is ANDed with ITVA9, and the result is output to the A/D2 converter as an activation signal. Bit 7: ITVA9 0 1 Description A/D2 converter activation by rise of TCNT0 bit 9 is disabled A/D2 converter activation by rise of TCNT0 bit 9 is enabled (Initial value) • Bit 6—A/D2 Converter Interval Activation Bit 8 (ITVA8): A/D2 converter activation setting bit corresponding to bit 8 in TCNT0. The rise of bit 8 in TCNT0 is ANDed with ITVA8, and the result is output to the A/D2 converter as an activation signal. Bit 6: ITVA8 0 1 Description A/D2 converter activation by rise of TCNT0 bit 8 is disabled A/D2 converter activation by rise of TCNT0 bit 8 is enabled (Initial value) • Bit 5—A/D2 Converter Interval Activation Bit 7 (ITVA7): A/D2 converter activation setting bit corresponding to bit 7 in TCNT0. The rise of bit 7 in TCNT0 is ANDed with ITVA7, and the result is output to the A/D2 converter as an activation signal. Bit 5: ITVA7 0 1 Description A/D2 converter activation by rise of TCNT0 bit 7 is disabled A/D2 converter activation by rise of TCNT0 bit 7 is enabled (Initial value) Rev. 3.0, 09/04, page 307 of 1086 • Bit 4—A/D2 Converter Interval Activation Bit 6 (ITVA6): A/D2 converter activation setting bit corresponding to bit 6 in TCNT0. The rise of bit 6 in TCNT0 is ANDed with ITVA6, and the result is output to the A/D2 converter as an activation signal. Bit 4: ITVA6 0 1 Description A/D2 converter activation by rise of TCNT0 bit 6 is disabled A/D2 converter activation by rise of TCNT0 bit 6 is enabled (Initial value) • Bit 3—Interval Interrupt Bit 9 (ITVE9): INTC interval interrupt setting bit corresponding to bit 9 in TCNT0. The rise of bit 9 in TCNT0 is ANDed with ITVE9, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 3: ITVE9 0 1 Description Interrupt request (ITV1) by rise of TCNT0 bit 9 is disabled Interrupt request (ITV1) by rise of TCNT0 bit 9 is enabled (Initial value) • Bit 2—Interval Interrupt Bit 8 (ITVE8): INTC interval interrupt setting bit corresponding to bit 8 in TCNT0. The rise of bit 8 in TCNT0 is ANDed with ITVE8, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 2: ITVE8 0 1 Description Interrupt request (ITV1) by rise of TCNT0 bit 8 is disabled Interrupt request (ITV1) by rise of TCNT0 bit 8 is enabled (Initial value) • Bit 1—Interval Interrupt Bit 7 (ITVE7): INTC interval interrupt setting bit corresponding to bit 7 in TCNT0. The rise of bit 7 in TCNT0 is ANDed with ITVE7, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 1: ITVE7 0 1 Description Interrupt request (ITV1) by rise of TCNT0 bit 7 is disabled Interrupt request (ITV1) by rise of TCNT0 bit 7 is enabled (Initial value) • Bit 0—Interval Interrupt Bit 6 (ITVE6): INTC interval interrupt setting bit corresponding to bit 6 in TCNT0. The rise of bit 6 in TCNT0 is ANDed with ITVE6, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 0: ITVE6 0 1 Description Interrupt request (ITV1) by rise of TCNT0 bit 6 is disabled Interrupt request (ITV1) by rise of TCNT0 bit 6 is enabled (Initial value) Rev. 3.0, 09/04, page 308 of 1086 Interval Interrupt Request Registers 2A and 2B (ITVRR2A, ITVRR2B) Bit: 7 6 5 4 3 2 1 0 ITVA13x ITVA12x ITVA11x ITVA10x ITVE13x ITVE12x ITVE11x ITVE10x Initial value: R/W: x = A or B 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W • Bit 7—A/D0 / A/D1 Converter Interval Activation Bit 13A/13B (ITVA13A/ITVA13B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 13 in TCNT0. The rise of bit 13 in TCNT0 is ANDed with ITVA13x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 7: ITVA13x 0 1 x = A or B Description A/D0 or A/D1 converter activation by rise of TCNT0 bit 13 is disabled (Initial value) A/D0 or A/D1 converter activation by rise of TCNT0 bit 13 is enabled • Bit 6—A/D0 / A/D1 Converter Interval Activation Bit 12A/12B (ITVA12A/ITVA12B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 12 in TCNT0. The rise of bit 12 in TCNT0 is ANDed with ITVA12x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 6: ITVA12x 0 1 x = A or B Description A/D0 or A/D1 converter activation by rise of TCNT0 bit 12 is disabled (Initial value) A/D0 or A/D1 converter activation by rise of TCNT0 bit 12 is enabled • Bit 5—A/D0 / A/D1 Converter Interval Activation Bit 11A/11B (ITVA11A/ITVA11B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 11 in TCNT0. The rise of bit 11 in TCNT0 is ANDed with ITVA11x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 5: ITVA11x 0 1 x = A or B Description A/D0 or A/D1 converter activation by rise of TCNT0 bit 11 is disabled (Initial value) A/D0 or A/D1 converter activation by rise of TCNT0 bit 11 is enabled Rev. 3.0, 09/04, page 309 of 1086 • Bit 4—A/D0 / A/D1 Converter Interval Activation Bit 10A/10B (ITVA10A/ITVA10B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 10 in TCNT0. The rise of bit 10 in TCNT0 is ANDed with ITVA10x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 4: ITVA10x 0 1 x = A or B Description A/D0 or A/D1 converter activation by rise of TCNT0 bit 10 is disabled (Initial value) A/D0 or A/D1 converter activation by rise of TCNT0 bit 10 is enabled • Bit 3—Interval Interrupt Bit 13A/13B (ITVE13A/ITVE13B): INTC interval interrupt setting bit corresponding to bit 13 in TCNT0. The rise of bit 13 in TCNT0 is ANDed with ITVE13x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 3: ITVE13x 0 1 x = A or B Description Interrupt request (ITV2x) by rise of TCNT0 bit 13 is disabled Interrupt request (ITV2x) by rise of TCNT0 bit 13 is enabled (Initial value) • Bit 2—Interval Interrupt Bit 12A/12B (ITVE12A/ITVE12B): INTC interval interrupt setting bit corresponding to bit 12 in TCNT0. The rise of bit 12 in TCNT0 is ANDed with ITVE12x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 2: ITVE12x 0 1 x = A or B Description Interrupt request (ITV2x) by rise of TCNT0 bit 12 is disabled Interrupt request (ITV2x) by rise of TCNT0 bit 12 is enabled (Initial value) • Bit 1—Interval Interrupt Bit 11A/11B (ITVE11A/ITVE11B): INTC interval interrupt setting bit corresponding to bit 11 in TCNT0. The rise of bit 11 in TCNT0 is ANDed with ITVE11x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 1: ITVE11x 0 1 x = A or B Description Interrupt request (ITV2x) by rise of TCNT0 bit 11 is disabled Interrupt request (ITV2x) by rise of TCNT0 bit 11 is enabled (Initial value) Rev. 3.0, 09/04, page 310 of 1086 • Bit 0—Interval Interrupt Bit 10 (ITVE10): INTC interval interrupt setting bit corresponding to bit 10 in TCNT0. The rise of bit 10 in TCNT0 is ANDed with ITVE10x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 0: ITVE10x 0 1 x = A or B Description Interrupt request (ITV2x) by rise of TCNT0 bit 10 is disabled Interrupt request (ITV2x) by rise of TCNT0 bit 10 is enabled (Initial value) For details, see section 11.3.7, Interval Timer Operation. 11.2.8 Trigger Mode Register (TRGMDR) The trigger mode register (TRGMDR) is an 8-bit register. The ATU-II has one TRGMDR register. Bit: 7 TRGMD Initial value: R/W: 0 R/W 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R TRGMDR is an 8-bit readable/writable register that selects whether a channel 1 compare-match is used as a channel 8 one-shot pulse start trigger or as a one-shot pulse terminate trigger when channel 1 and channel 8 are used in combination. TRGMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—Trigger Mode Selection Register (TRGMD): Selects the channel 8 one-shot pulse start trigger/one-shot pulse terminate trigger setting. Bit 7: TRGMD 0 1 Description One-shot pulse start trigger (TCNT1B = OCR1) One-shot pulse terminate trigger (TCNT1A = GR1A–GR1H) One-shot pulse start trigger (TCNT1A = GR1A–GR1H) One-shot pulse terminate trigger (TCNT1B = OCR1) (Initial value) • Bits 6 to 0—Reserved: These bits are always read as 0. The write value should always be 0. Rev. 3.0, 09/04, page 311 of 1086 11.2.9 Timer Mode Register (TMDR) The timer mode register (TMDR) is an 8-bit register. The ATU-II has one TDR register. Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 1 0 T5PWM T4PWM T3PWM 0 R/W 0 R/W 0 R/W TMDR is an 8-bit readable/writable register that specifies whether channels 3 to 5 are used in input capture/output compare mode or PWM mode. TMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 2—PWM Mode 5 (T5PWM): Selects whether channel 5 operates in input capture/output compare mode or PWM mode. Bit 2: T5PWM 0 1 Description Channel 5 operates in input capture/output compare mode Channel 5 operates in PWM mode (Initial value) When bit T5PWM is set to 1 to select PWM mode, pins TIO5A to TIO5C become PWM output pins, general register 5D (GR5D) functions as a cycle register, and general registers 5A to 5C (GR5A to GR5C) function as duty registers. Settings in the timer I/O control registers (TIOR5A, TIOR5B) are invalid, and general registers 5A to 5D (GR5A to GR5D) can be written to. Do not use the TIO5D pin as a timer output. • Bit 1—PWM Mode 4 (T4PWM): Selects whether channel 4 operates in input capture/output compare mode or PWM mode. Bit 1: T4PWM 0 1 Description Channel 4 operates in input capture/output compare mode Channel 4 operates in PWM mode (Initial value) When bit T4PWM is set to 1 to select PWM mode, pins TIO4A to TIO4C become PWM output pins, general register 4D (GR4D) functions as a cycle register, and general registers 4A to 4C (GR4A to GR4C) function as duty registers. Settings in the timer I/O control registers (TIOR4A, TIOR4B) are invalid, and general registers 4A to 4D (GR4A to GR4D) can be written to. Do not use the TIO4D pin as a timer output. Rev. 3.0, 09/04, page 312 of 1086 • Bit 0—PWM Mode 3 (T3PWM): Selects whether channel 3 operates in input capture/output compare mode or PWM mode. Bit 0: T3PWM 0 1 Description Channel 3 operates in input capture/output compare mode Channel 3 operates in PWM mode (Initial value) When bit T3PWM is set to 1 to select PWM mode, pins TIO3A to TIO3C become PWM output pins, general register 3D (GR3D) functions as a cycle register, and general registers 3A to 3C (GR3A to GR3C) function as duty registers. Settings in the timer I/O control registers (TIOR3A, TIOR3B) are invalid, and general registers 3A to 3D (GR3A to GR3D) can be written to. Do not use the TIO3D pin as a timer output. 11.2.10 PWM Mode Register (PMDR) The PWM mode register (PMDR) is an 8-bit register. The ATU-II has one PMDR register. Bit: 7 DTSELD 6 DTSELC 5 DTSELB 4 3 2 1 0 DTSELA CNTSELD CNTSELC CNTSELB CNTSELA Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PMDR is an 8-bit readable/writable register that selects whether channel 6 PWM output is set to on-duty/off-duty, or to non-complementary PWM mode/complementary PWM mode. PMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 7—Duty Selection Register D (DTSELD): Selects whether channel 6D TO6D output PWM is set to on-duty or to off-duty. Bit 7: DTSELD 0 1 Description TO6D PWM output is on-duty TO6D PWM output is off-duty (Initial value) Rev. 3.0, 09/04, page 313 of 1086 • Bit 6—Duty Selection Register C (DTSELC): Selects whether channel 6C TO6C output PWM is set to on-duty or to off-duty. Bit 6: DTSELC 0 1 Description TO6C PWM output is on-duty TO6C PWM output is off-duty (Initial value) • Bit 5—Duty Selection Register B (DTSELB): Selects whether channel 6B TO6B output PWM is set to on-duty or to off-duty. Bit 5: DTSELB 0 1 Description TO6B PWM output is on-duty TO6B PWM output is off-duty (Initial value) • Bit 4—Duty Selection Register A (DTSELA): Selects whether channel 6A TO6A output PWM is set to on-duty or to off-duty. Bit 4: DTSELA 0 1 Description TO6A PWM output is on-duty TO6A PWM output is off-duty (Initial value) • Bit 3—Counter Selection Register D (CNTSELD): Selects whether channel 6D PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 3: CNTSELD 0 1 Description TCNT6D is set to non-complementary PWM mode TCNT6D is set to complementary PWM mode (Initial value) • Bit 2—Counter Selection Register C (CNTSELC): Selects whether channel 6C PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 2: CNTSELC 0 1 Description TCNT6C is set to non-complementary PWM mode TCNT6C is set to complementary PWM mode (Initial value) Rev. 3.0, 09/04, page 314 of 1086 • Bit 1—Counter Selection Register B (CNTSELB): Selects whether channel 6B PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 1: CNTSELB 0 1 Description TCNT6B is set to non-complementary PWM mode TCNT6B is set to complementary PWM mode (Initial value) • Bit 0—Counter Selection Register A (CNTSELA): Selects whether channel 6A PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 0: CNTSELA 0 1 Description TCNT6A is set to non-complementary PWM mode TCNT6A is set to complementary PWM mode (Initial value) 11.2.11 Down-Count Start Register (DSTR) The down-count start register (DSTR) is a 16-bit register. The ATU-II has one DSTR register in channel 8. Bit: 15 DST8P Initial value: R/W: Bit: 0 R/W* 7 DST8H Initial value: R/W: 0 R/W* 14 DST8O 0 R/W* 6 DST8G 0 R/W* 13 DST8N 0 R/W* 5 DST8F 0 R/W* 12 DST8M 0 R/W* 4 DST8E 0 R/W* 11 DST8L 0 R/W* 3 DST8D 0 R/W* 10 DST8K 0 R/W* 2 DST8C 0 R/W* 9 DST8J 0 R/W* 1 DST8B 0 R/W* 8 DST8I 0 R/W* 0 DST8A 0 R/W* Note: * Only 1 can be written. DSTR is a 16-bit readable/writable register that starts the channel 8 down-counter (DCNT). When the one-shot pulse function is used, a value of 1 can be set in a DST8x bit at any time by the user program, except when the corresponding DCNT8x value is H'0000. The DST8x bits are cleared to 0 automatically when the DCNT value overflows. When the offset one-shot pulse function is used, DST8x is automatically set to 1 (except when the DCNT8x value is H'0000) when a compare-match occurs between the channel 1 or 2 free-running counter (TCNT) and a general register (GR) or the output compare register (OCR1) while the corresponding timer connection register (TCNR) bit is set to 1. As regards DST8I to DST8P, if the Rev. 3.0, 09/04, page 315 of 1086 RLDEN bit in the reload enable register (RLDENR) is set to 1 and the reload register (RLDR8) value is not H'0000, a reload is performed into the corresponding DCNT8x, and the DST8x bit is set to 1. DST8x is automatically cleared to 0 when the DCNT8x vaue underflows, or by input of a channel 1 or 2 one-shot terminate trigger signal set in the trigger mode register (TRGMDR) while the corresponding one-shot pulse terminate register (OTR) bit is set to 1, whichever occurs first. DCNT8x is cleared to H'0000 when underflow occurs. DSTR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 11.3.5, One-Shot Pulse Function, and 11.3.6, Offset One-Shot Pulse Function and Output Cutoff Function. • Bit 15—Down-Count Start 8P (DST8P): Starts down-counter 8P (DCNT8P). Bit 15: DST8P 0 Description DCNT8P is halted (Initial value) [Clearing condition] When the DCNT8P value underflows, or on channel 2 (GR2H) comparematch 1 DCNT8P counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8P ≠ H'0000) • Offset one-shot pulse function: Set on OCR2H compare-match (DCNT8P ≠ H'0000 or reload possible) or by user program (DCNT8P ≠ H'0000) • Bit 14—Down-Count Start 8O (DST8O): Starts down-counter 8O (DCNT8O). Bit 14: DST8O 0 Description DCNT8O is halted (Initial value) [Clearing condition] When the DCNT8O value underflows, or on channel 2 (GR2G) comparematch 1 DCNT8O counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8O ≠ H'0000) • Offset one-shot pulse function: Set on OCR2G compare-match (DCNT8O ≠ H'0000 or reload possible) or by user program (DCNT8O ≠ H'0000) Rev. 3.0, 09/04, page 316 of 1086 • Bit 13—Down-Count Start 8N (DST8N): Starts down-counter 8N (DCNT8N). Bit 13: DST8N 0 Description DCNT8N is halted (Initial value) [Clearing condition] When the DCNT8N value underflows, or on channel 2 (GR2F) comparematch 1 DCNT8N counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8N ≠ H'0000) • Offset one-shot pulse function: Set on OCR2F compare-match (DCNT8N ≠ H'0000 or reload possible) or by user program (DCNT8N ≠ H'0000) • Bit 12—Down-Count Start 8M (DST8M): Starts down-counter 8M (DCNT8M). Bit 12: DST8M 0 Description DCNT8M is halted (Initial value) [Clearing condition] When the DCNT8M value underflows, or on channel 2 (GR2E) comparematch 1 DCNT8M counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8M ≠ H'0000) • Offset one-shot pulse function: Set on OCR2E compare-match (DCNT8M ≠ H'0000 or reload possible) or by user program (DCNT8M ≠ H'0000) Rev. 3.0, 09/04, page 317 of 1086 • Bit 11—Down-Count Start 8L (DST8L): Starts down-counter 8L (DCNT8L). Bit 11: DST8L 0 Description DCNT8L is halted (Initial value) [Clearing condition] When the DCNT8L value underflows, or on channel 2 (GR2D) comparematch 1 DCNT8L counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8L ≠ H'0000) • Offset one-shot pulse function: Set on OCR2D compare-match (DCNT8L ≠ H'0000 or reload possible) or by user program (DCNT8L ≠ H'0000) • Bit 10—Down-Count Start 8K (DST8K): Starts down-counter 8K (DCNT8K). Bit 10: DST8K 0 Description DCNT8K is halted (Initial value) [Clearing condition] When the DCNT8K value underflows, or on channel 2 (GR2C) comparematch 1 DCNT8K counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8K ≠ H'0000) • Offset one-shot pulse function: Set on OCR2C compare-match (DCNT8K ≠ H'0000 or reload possible) or by user program (DCNT8K ≠ H'0000) • Bit 9—Down-Count Start 8J (DST8J): Starts down-counter 8J (DCNT8J). Bit 9: DST8J 0 Description DCNT8J is halted (Initial value) [Clearing condition] When the DCNT8J value underflows, or on channel 2 (GR2B) comparematch 1 DCNT8J counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8J ≠ H'0000) • Offset one-shot pulse function: Set on OCR2B compare-match (DCNT8J ≠ H'0000 or reload possible) or by user program (DCNT8J ≠ H'0000) Rev. 3.0, 09/04, page 318 of 1086 • Bit 8—Down-Count Start 8I (DST8I): Starts down-counter 8I (DCNT8I). Bit 8: DST8I 0 Description DCNT8I is halted (Initial value) [Clearing condition] When the DCNT8I value underflows, or on channel 2 (GR2A) compare-match 1 DCNT8I counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8I ≠ H'0000) • Offset one-shot pulse function: Set on OCR2A compare-match (DCNT8I ≠ H'0000 or reload possible) or by user program (DCNT8I ≠ H'0000) • Bit 7—Down-Count Start 8H (DST8H): Starts down-counter 8H (DCNT8H). Bit 7: DST8H 0 Description DCNT8H is halted (Initial value) [Clearing condition] When the DCNT8H value underflows, or on channel 1 (GR1H or OCR1) compare-match 1 DCNT8H counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8H ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1H compare-match, or by user program (DCNT8H ≠ H'0000) • Bit 6—Down-Count Start 8G (DST8G): Starts down-counter 8G (DCNT8G). Bit 6: DST8G 0 Description DCNT8G is halted (Initial value) [Clearing condition] When the DCNT8G value underflows, or on channel 1 (GR1G or OCR1) compare-match 1 DCNT8G counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8G ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1G compare-match, or by user program (DCNT8G ≠ H'0000) Rev. 3.0, 09/04, page 319 of 1086 • Bit 5—Down-Count Start 8F (DST8F): Starts down-counter 8F (DCNT8F). Bit 5: DST8F 0 Description DCNT8F is halted (Initial value) [Clearing condition] When the DCNT8F value underflows, or on channel 1 (GR1F or OCR1) compare-match 1 DCNT8F counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8F ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1F compare-match, or by user program (DCNT8F ≠ H'0000) • Bit 4—Down-Count Start 8E (DST8E): Starts down-counter 8E (DCNT8E). Bit 4: DST8E 0 Description DCNT8E is halted (Initial value) [Clearing condition] When the DCNT8E value underflows, or on channel 1 (GR1E or OCR1) compare-match 1 DCNT8E counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8E ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1E compare-match, or by user program (DCNT8E ≠ H'0000) • Bit 3—Down-Count Start 8D (DST8D): Starts down-counter 8D (DCNT8D). Bit 3: DST8D 0 Description DCNT8D is halted (Initial value) [Clearing condition] When the DCNT8D value underflows, or on channel 1 (GR1D or OCR1) compare-match 1 DCNT8D counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8D ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1D compare-match, or by user program (DCNT8D ≠ H'0000) Rev. 3.0, 09/04, page 320 of 1086 • Bit 2—Down-Count Start 8C (DST8C): Starts down-counter 8C (DCNT8C). Bit 2: DST8C 0 Description DCNT8C is halted (Initial value) [Clearing condition] When the DCNT8C value underflows, or on channel 1 (GR1C or OCR1) compare-match 1 DCNT8C counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8C ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1C compare-match, or by user program (DCNT8C ≠ H'0000) • Bit 1—Down-Count Start 8B (DST8B): Starts down-counter 8B (DCNT8B). Bit 1: DST8B 0 Description DCNT8B is halted (Initial value) [Clearing condition] When the DCNT8B value underflows, or on channel 1 (GR1B or OCR1) compare-match 1 DCNT8B counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8B ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1B compare-match, or by user program (DCNT8B ≠ H'0000) • Bit 0—Down-Count Start 8A (DST8A): Starts down-counter 8A (DCNT8A). Bit 0: DST8A 0 Description DCNT8A is halted (Initial value) [Clearing condition] When the DCNT8A value underflows, or on channel 1 (GR1A or OCR1) compare-match 1 DCNT8A counts [Setting conditions] • One-shot pulse function: Set by user program (DCNT8A ≠ H'0000) • Offset one-shot pulse function: Set on OCR1 compare-match or GR1A compare-match, or by user program (DCNT8A ≠ H'0000) Rev. 3.0, 09/04, page 321 of 1086 11.2.12 Timer Connection Register (TCNR) The timer connection register (TCNR) is a 16-bit register. The ATU-II has one TCNR register in channel 8. Bit: 15 CN8P Initial value: R/W: Bit: 0 R/W 7 CN8H Initial value: R/W: 0 R/W 14 CN8O 0 R/W 6 CN8G 0 R/W 13 CN8N 0 R/W 5 CN8F 0 R/W 12 CN8M 0 R/W 4 CN8E 0 R/W 11 CN8L 0 R/W 3 CN8D 0 R/W 10 CN8K 0 R/W 2 CN8C 0 R/W 9 CN8J 0 R/W 1 CN8B 0 R/W 8 CN8I 0 R/W 0 CN8A 0 R/W TCNR is a 16-bit readable/writable register that enables or disables connection between the channel 8 down-count start register (DSTR) and channel 1 and 2 compare-match signals (downcount start triggers). Channel 1 down-count start triggers A to H are channel 1 OCR1 comparematch signals or GR1x compare-match signals (set in TRGMDR). Channel 2 down-count start triggers A to H are channel 2 OCR2x compare-match signals. When GR1x compare-matches are used, set TIOR1A to TIOR1D to allow compare-matches. TCNR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 11.3.5, One-Shot Pulse Function, and 11.3.6, Offset One-Shot Pulse Function and Output Cutoff Function. • Bit 15—Connection Flag 8P (CN8P): Enables or disables connection between DST8P and the channel 2 down-count start trigger. Bit 15: CN8P 0 1 Description Connection between DST8P and channel 2 down-count start trigger H is disabled (Initial value) Connection between DST8P and channel 2 down-count start trigger H is enabled Rev. 3.0, 09/04, page 322 of 1086 • Bit 14—Connection Flag 8O (CN8O): Enables or disables connection between DST8O and the channel 2 down-count start trigger. Bit 14: CN8O 0 1 Description Connection between DST8O and channel 2 down-count start trigger G is disabled (Initial value) Connection between DST8O and channel 2 down-count start trigger G is enabled • Bit 13—Connection Flag 8N (CN8N): Enables or disables connection between DST8N and the channel 2 down-count start trigger. Bit 13: CN8N 0 1 Description Connection between DST8N and channel 2 down-count start trigger F is disabled (Initial value) Connection between DST8N and channel 2 down-count start trigger F is enabled • Bit 12—Connection Flag 8M (CN8M): Enables or disables connection between DST8M and the channel 2 down-count start trigger. Bit 12: CN8M 0 1 Description Connection between DST8M and channel 2 down-count start trigger E is disabled (Initial value) Connection between DST8M and channel 2 down-count start trigger E is enabled • Bit 11—Connection Flag 8L (CN8L): Enables or disables connection between DST8L and the channel 2 down-count start trigger. Bit 11: CN8L 0 1 Description Connection between DST8L and channel 2 down-count start trigger D is disabled (Initial value) Connection between DST8L and channel 2 down-count start trigger D is enabled Rev. 3.0, 09/04, page 323 of 1086 • Bit 10—Connection Flag 8K (CN8K): Enables or disables connection between DST8K and the channel 2 down-count start trigger. Bit 10: CN8K 0 1 Description Connection between DST8K and channel 2 down-count start trigger C is disabled (Initial value) Connection between DST8K and channel 2 down-count start trigger C is enabled • Bit 9—Connection Flag 8J (CN8J): Enables or disables connection between DST8J and the channel 2 down-count start trigger. Bit 9: CN8J 0 1 Description Connection between DST8J and channel 2 down-count start trigger B is disabled (Initial value) Connection between DST8J and channel 2 down-count start trigger B is enabled • Bit 8—Connection Flag 8I (CN8I): Enables or disables connection between DST8I and the channel 2 down-count start trigger. Bit 8: CN8I 0 1 Description Connection between DST8I and channel 2 down-count start trigger A is disabled (Initial value) Connection between DST8I and channel 2 down-count start trigger A is enabled • Bit 7—Connection Flag 8H (CN8H): Enables or disables connection between DST8H and the channel 1 down-count start trigger. Bit 7: CN8H 0 1 Description Connection between DST8H and channel 1 down-count start trigger H is disabled (Initial value) Connection between DST8H and channel 1 down-count start trigger H is enabled Rev. 3.0, 09/04, page 324 of 1086 • Bit 6—Connection Flag 8G (CN8G): Enables or disables connection between DST8G and the channel 1 down-count start trigger. Bit 6: CN8G 0 1 Description Connection between DST8G and channel 1 down-count start trigger G is disabled (Initial value) Connection between DST8G and channel 1 down-count start trigger G is enabled • Bit 5—Connection Flag 8F (CN8F): Enables or disables connection between DST8F and the channel 1 down-count start trigger. Bit 5: CN8F 0 1 Description Connection between DST8F and channel 1 down-count start trigger F is disabled (Initial value) Connection between DST8F and channel 1 down-count start trigger F is enabled • Bit 4—Connection Flag 8E (CN8E): Enables or disables connection between DST8E and the channel 1 down-count start trigger. Bit 4: CN8E 0 1 Description Connection between DST8E and channel 1 down-count start trigger E is disabled (Initial value) Connection between DST8E and channel 1 down-count start trigger E is enabled • Bit 3—Connection Flag 8D (CN8D): Enables or disables connection between DST8D and the channel 1 down-count start trigger. Bit 3: CN8D 0 1 Description Connection between DST8D and channel 1 down-count start trigger D is disabled (Initial value) Connection between DST8D and channel 1 down-count start trigger D is enabled Rev. 3.0, 09/04, page 325 of 1086 • Bit 2—Connection Flag 8C (CN8C): Enables or disables connection between DST8C and the channel 1 down-count start trigger. Bit 2: CN8C 0 1 Description Connection between DST8C and channel 1 down-count start trigger C is disabled (Initial value) Connection between DST8C and channel 1 down-count start trigger C is enabled • Bit 1—Connection Flag 8B (CN8B): Enables or disables connection between DST8B and the channel 1 down-count start trigger. Bit 1: CN8B 0 1 Description Connection between DST8B and channel 1 down-count start trigger B is disabled (Initial value) Connection between DST8B and channel 1 down-count start trigger B is enabled • Bit 0—Connection Flag 8A (CN8A): Enables or disables connection between DST8A and the channel 1 down-count start trigger. Bit 0: CN8A 0 1 Description Connection between DST8A and channel 1 down-count start trigger A is disabled (Initial value) Connection between DST8A and channel 1 down-count start trigger A is enabled Rev. 3.0, 09/04, page 326 of 1086 11.2.13 One-Shot Pulse Terminate Register (OTR) The one-shot pulse terminate register (OTR) is a 16-bit register. The ATU-II has one OTR register in channel 8. Bit: 15 OTEP Initial value: R/W: Bit: 0 R/W 7 OTEH Initial value: R/W: 0 R/W 14 OTEO 0 R/W 6 OTEG 0 R/W 13 OTEN 0 R/W 5 OTEF 0 R/W 12 OTEM 0 R/W 4 OTEE 0 R/W 11 OTEL 0 R/W 3 OTED 0 R/W 10 OTEK 0 R/W 2 OTEC 0 R/W 9 OTEJ 0 R/W 1 OTEB 0 R/W 8 OTEI 0 R/W 0 OTEA 0 R/W OTR is a 16-bit readable/writable register that enables or disables forced termination of channel 8 one-shot pulse output by channel 1 and 2 compare-match signals. When one-shot pulse output is forcibly terminated, the corresponding DSTR bit and down-counter are cleared, and the corresponding TSR8 bit is set. The channel 1 one-shot pulse terminate signal is generated by GR1A to GR1H compare-matches and OCR1 compare-match (see TRGMDR). The channel 2 one-shot pulse terminate signal is generated by GR2A to GR2H compare-matches. To generate the terminate signal with GR1A to GR1H and GR2A to GR2H, select the respective compare-matches in TIOR1A to TIOR1D. OTR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. • Bit 15—One-Shot Pulse Terminate Enable P (OTEP): Enables or disables forced termination of output by channel 2 down-counter terminate trigger H. Bit 15: OTEP 0 1 Description Forced termination of TO8P by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8P by down-counter terminate trigger is enabled Rev. 3.0, 09/04, page 327 of 1086 • Bit 14—One-Shot Pulse Terminate Enable O (OTEO): Enables or disables forced termination of output by channel 2 down-counter terminate trigger G. Bit 14: OTEO 0 1 Description Forced termination of TO8O by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8O by down-counter terminate trigger is enabled • Bit 13—One-Shot Pulse Terminate Enable N (OTEN): Enables or disables forced termination of output by channel 2 down-counter terminate trigger F. Bit 13: OTEN 0 1 Description Forced termination of TO8N by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8N by down-counter terminate trigger is enabled • Bit 12—One-Shot Pulse Terminate Enable M (OTEM): Enables or disables forced termination of output by channel 2 down-counter terminate trigger E. Bit 12: OTEM 0 1 Description Forced termination of TO8M by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8M by down-counter terminate trigger is enabled • Bit 11—One-Shot Pulse Terminate Enable L (OTEL): Enables or disables forced termination of output by channel 2 down-counter terminate trigger D. Bit 11: OTEL 0 1 Description Forced termination of TO8L by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8L by down-counter terminate trigger is enabled • Bit 10—One-Shot Pulse Terminate Enable K (OTEK): Enables or disables forced termination of output by channel 2 down-counter terminate trigger C. Bit 10: OTEK 0 1 Description Forced termination of TO8K by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8K by down-counter terminate trigger is enabled Rev. 3.0, 09/04, page 328 of 1086 • Bit 9—One-Shot Pulse Terminate Enable J (OTEJ): Enables or disables forced termination of output by channel 2 down-counter terminate trigger B. Bit 9: OTEJ 0 1 Description Forced termination of TO8J by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8J by down-counter terminate trigger is enabled • Bit 8—One-Shot Pulse Terminate Enable I (OTEI): Enables or disables forced termination of output by channel 2 down-counter terminate trigger A. Bit 8: OTEI 0 1 Description Forced termination of TO8I by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8I by down-counter terminate trigger is enabled • Bit 7—One-Shot Pulse Terminate Enable H (OTEH): Enables or disables forced termination of output by channel 1 down-counter terminate trigger H. Bit 7: OTEH 0 1 Description Forced termination of TO8H by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8H by down-counter terminate trigger is enabled • Bit 6—One-Shot Pulse Terminate Enable G (OTEG): Enables or disables forced termination of output by channel 1 down-counter terminate trigger G. Bit 6: OTEG 0 1 Description Forced termination of TO8G by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8G by down-counter terminate trigger is enabled • Bit 5—One-Shot Pulse Terminate Enable F (OTEF): Enables or disables forced termination of output by channel 1 down-counter terminate trigger F. Bit 5: OTEF 0 1 Description Forced termination of TO8F by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8F by down-counter terminate trigger is enabled Rev. 3.0, 09/04, page 329 of 1086 • Bit 4—One-Shot Pulse Terminate Enable E (OTEE): Enables or disables forced termination of output by channel 1 down-counter terminate trigger E. Bit 4: OTEE 0 1 Description Forced termination of TO8E by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8E by down-counter terminate trigger is enabled • Bit 3—One-Shot Pulse Terminate Enable D (OTED): Enables or disables forced termination of output by channel 1 down-counter terminate trigger D. Bit 3: OTED 0 1 Description Forced termination of TO8D by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8D by down-counter terminate trigger is enabled • Bit 2—One-Shot Pulse Terminate Enable C (OTEC): Enables or disables forced termination of output by channel 1 down-counter terminate trigger C. Bit 2: OTEC 0 1 Description Forced termination of TO8C by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8C by down-counter terminate trigger is enabled • Bit 1—One-Shot Pulse Terminate Enable B (OTEB): Enables or disables forced termination of output by channel 1 down-counter terminate trigger B. Bit 1: OTEB 0 1 Description Forced termination of TO8B by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8B by down-counter terminate trigger is enabled • Bit 0—One-Shot Pulse Terminate Enable A (OTEA): Enables or disables forced termination of output by channel 1 down-counter terminate trigger A. Bit 0: OTEA 0 1 Description Forced termination of TO8A by down-counter terminate trigger is disabled (Initial value) Forced termination of TO8A by down-counter terminate trigger is enabled Rev. 3.0, 09/04, page 330 of 1086 11.2.14 Reload Enable Register (RLDENR) The reload enable register (RLDENR) is an 8-bit register. The ATU-II has one RLDENR register in channel 8. Bit: 7 RLDEN Initial value: R/W: 0 R/W 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R RLDENR is an 8-bit readable/writable register that enables or disables loading of the reload register8 (RLDR8) value into the down-counters (DCNT8I to DCNT8P). Loading is performed on generation of a channel 2 compare-match signal one-shot pulse start trigger. Reloading is not performed if there is no linkage with channel 2 (one-shot pulse function), or while the downcounter (DCNT8I to DCNT8P) is running. RLDENR is initialized to H'00 by a power-on reset and in hardware standby mode and software standby mode. • Bit 7—Reload Enable (RLDEN): Enables or disables loading of the RLDR value into DCNT8I to DCNT8P. Bit 7: RLDEN 0 1 Description Loading of reload register value into down-counters is disabled (Initial value) Loading of reload register value into down-counters is enabled • Bits 6 to 0—Reserved: These bits are always read as 0. The write value should always be 0. Rev. 3.0, 09/04, page 331 of 1086 11.2.15 Free-Running Counters (TCNT) The free-running counters (TCNT) are 32- or 16-bit up- or up/down-counters. The ATU-II has 17 TCNT counters: one 32-bit TCNT in channel 0, and sixteen 16-bit TCNTs in each of channels 1 to 7 and 11. For details of the channel 10 free-running counters, see section 11.2.26, Channel 10 Registers. Channel 0 1 2 3 4 5 6 7 11 Abbreviation TCNT0H, TCNT0L TCNT1A, TCNT1B TCNT2A, TCNT2B TCNT3 TCNT4 TCNT5 TCNT6A–D TCNT7A–D TCNT11 16-bit up/down-counters (initial value H'0001) 16-bit up-counters (initial value H'0001) 16-bit up-counter (initial value H'0000) Function 32-bit up-counter (initial value H'00000000) 16-bit up-counters (initial value H'0000) Free-Running Counter 0 (TCNT0H, TCNT0L): Free-running counter 0 (comprising TCNT0H and TCNT0L) is a 32-bit readable/writable register that counts on an input clock. The counter is started when the corresponding bit in the timer start register (TSTR1) is set to 1. The input clock is selected with prescaler register 1 (PSCR1). Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When TCNT0 overflows (from H'FFFFFFFF to H'00000000), the OVF0 overflow flag in the timer status register (TSR0) is set to 1. TCNT0 can only be accessed by a longword read or write. Word reads or writes should not be used. Rev. 3.0, 09/04, page 332 of 1086 TCNT0 is initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode. Free-Running Counters 1A, 1B, 2A, 2B, 3, 4, 5, 11 (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, TCNT11): Free-running counters 1A, 1B, 2A, 2B, 3, 4, 5, and 11 (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, TCNT11) are 16-bit readable/writable registers that count on an input clock. Counting is started when the corresponding bit in the timer start register (TSTR1 or TSTR3) is set to 1. The input clock is selected with prescaler register 1 (PSCR1) and the timer control register (TCR). Bit: Bit name: Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The TCNT1A, TCNT1B, TCNT2A, and TCNT2B counters are cleared if incremented during counter clear trigger input from channel 10. TCNT3 to TCNT5 counter clearing is performed by a compare-match with the corresponding general register, according to the setting in TIOR. When one of counters TCNT1A/1B/2A/2B/3/4/5/11 overflows (from H'FFFF to H'0000), the overflow flag (OVF) for the corresponding channel in the timer status register (TSR) is set to 1. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, and TCNT11 can only be accessed by a word read or write. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, and TCNT11 are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, and TCNT5 can count on external clock (TCLKA or TCLKB) input. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, and TCNT5 can count on an external interrupt clock (TI10) (AGCK) generated in channel 10 and on a channel 10 multiplied clock (AGCKM). Rev. 3.0, 09/04, page 333 of 1086 Free-Running Counters 6A to 6D and 7A to 7D (TCNT6A to TCNT6D, TCNT7A to TCNT7D): Free-running counters 6A to 6D and 7A to 7D (TCNT6A to TCNT6D, TCNT7A to TCNT7D) are 16-bit readable/writable registers. Channel 6 and 7 counts are started by the timer start register (TSTR2). The clock input to channels 6 and 7 is selected with prescaler registers 2 and 3 (PSCR2, PSCR3) and timer control registers 6 and 7 (TCR6, TCR7). Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT6A to TCNT6D (in non-complementary PWM mode) and TCNT7A to TCNT7D are cleared by a compare-match with the cycle register (CYLR). TCNT6A to TCNT6D (in complementary PWM mode) count up and down between zero and the cycle register value. TCNT6A to TCNT6D and TCNT7A to TCNT7D are connected to the CPU by an internal 16-bit bus, and can only be accessed by a word read or write. TCNT6A to TCNT6D and TCNT7A to TCNT7D are initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode. 11.2.16 Down-Counters (DCNT) The DCNT registers are 16-bit down-counters. The ATU-II has 16 DCNT counters in channel 8. Channel 8 Abbreviation DCNT8A, DCNT8B, DCNT8C, DCNT8D, DCNT8E, DCNT8F, DCNT8G, DCNT8H, DCNT8I, DCNT8J, DCNT8K, DCNT8L, DCNT8M, DCNT8N, DCNT8O, DCNT8P Function 16-bit down-counters Rev. 3.0, 09/04, page 334 of 1086 Down-Counters 8A to 8P (DCNT8A to DCNT8P): Down-counters 8A to 8P (DCNT8A to DCNT8P) are 16-bit readable/writable registers that count on an input clock. The input clock is selected with prescaler register 1 (PSCR1) and the timer control register (TCR). Bit: Bit name: Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 When the one-shot pulse function is used, DCNT8x starts counting down when the corresponding DSTR bit is set to 1 by the user program after the DCNT8x value has been set. When the DCNT8x value underflows, DSTR and DCNT8x are automatically cleared to 0, and the count is stopped. At the same time, the corresponding channel 8 timer status register 8 (TSR8) status flag is set to 1. When the offset one-shot pulse function is used, on compare-match with a channel 1 or 2 general register (GR) or output compare register (OCR) (the compare-match setting being made in the trigger mode register (TRGMDR) (for channel 1 only) ) when the corresponding timer connection register (TCNR) bit is 1, the corresponding down-count start register (DSTR) bit is automatically set to 1 and the down-count is started. When the DCNT8x value underflows, the corresponding DSTR bit and DCNT8x are automatically cleared to 0, the count is stopped, and the output is inverted, or, if a one-shot terminate register (OTR) setting has been made to forcibly terminate output by means of a trigger, DSTR is cleared to 0 by a channel 1 or 2 compare-match between GR and OCR, the count is forcibly terminated, and the output is inverted. The output is inverted for whichever is first. When the output is inverted, the corresponding channel 8 TSR8 status flag is set to 1. The DCNT8x counters can only be accessed by a word read or write. The DCNT8x counters are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 11.3.5, One-Shot Pulse Function, and 11.3.6, Offset One-Shot Pulse Function and Output Cutoff Function. Rev. 3.0, 09/04, page 335 of 1086 11.2.17 Event Counters (ECNT) The event counters (ECNT) are 8-bit up-counters. The ATU-II has six ECNT counters in channel 9. Channel 9 Abbreviation ECNT9A, ECNT9B, ECNT9C, ECNT9D, ECNT9E, ECNT9F Function 8-bit event counters The ECNT counters are 8-bit readable/writable registers that count on detection of an input signal from input pins TI9A to TI9F. Rising edge, falling edge, or both rising and falling edges can be selected for edge detection. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W When a compare-match with GR9 corresponding to an ECNT9x counter occurs, the comparematch flag (CMF9) in the timer status register (TSR9) is set to 1. When a compare-match with GR occurs, the ECNT9x counter is cleared automatically. The ECNT9x counters can only be accessed by a byte read or write. The ECNT9x counters are initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. 11.2.18 Output Compare Registers (OCR) The output compare registers (OCR) are 16-bit registers. The ATU-II has nine OCR registers: one in channel 1 and eight in channel 2. For details of the channel 10 free-running counters, see section 11.2.26, Channel 10 Registers. Channel 1 2 Abbreviation OCR1 OCR2A, OCR2B, OCR2C, OCR2D, OCR2E, OCR2F, OCR2G, OCR2H Function Output compare registers Rev. 3.0, 09/04, page 336 of 1086 Output Compare Registers 1 and 2A to 2H (OCR1, OCR2A to OCR2H) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The OCR registers are 16-bit readable/writable registers that have an output compare register function. The OCR and free-running counter (TCNT1B, TCNT2B) values are constantly compared, and if the two values match, the CMF bit in the timer status register (TSR) is set to 1. If channels 1 and 2 and channel 8 are linked by the timer connection register (TCNR), the corresponding channel 8 down-counter (DCNT) is started at the same time. The OCR registers can only be accessed by a word read or write. The OCR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. 11.2.19 Input Capture Registers (ICR) The input capture registers (ICR) are 32-bit registers. The ATU-II has four 32-bit ICR registers in channel 0. For details of the channel 10 free-running counters, see section 11.2.26, Channel 10 Registers. Channel 0 Abbreviation ICR0AH, ICR0AL, ICR0BH, ICR0BL, ICR0CH, ICR0CL, ICR0DH, ICR0DL Function Dedicated input capture registers Rev. 3.0, 09/04, page 337 of 1086 Input Capture Registers 0AH, 0AL to 0DH, 0DL (ICR0AH, ICR0AL to ICR0DH, ICR0DL) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R The ICR registers are 32-bit read-only registers used exclusively for input capture. These dedicated input capture registers store the TCNT0 value on detection of an input capture signal from an external source. The corresponding TSR0 bit is set to 1 at this time. The input capture signal edge to be detected is specified by timer I/O control register TIOR0. By setting the TRG0DEN bit in TCR10, ICR0DH and ICR0DL can also be used for input capture in a compare match between TCNT10B and OCR10B. The ICR registers can only be accessed by a longword read. Word reads should not be used. The ICR registers are initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode. 11.2.20 General Registers (GR) The general registers (GR) are 16-bit registers. The ATU-II has 36 general registers: eight each in channels 1 and 2, four each in channels 3 to 5, six in channel 9, and two in channel 11. For details of the channel 10 free-running counters, see section 11.2.26, Channel 10 Registers. Channel 1 2 3 4 5 9 11 Abbreviation GR1A–GR1H GR2A–GR2H GR3A–GR3D GR4A–GR4D GR5A–GR5D GR9A–GR9F GR11A, GR11B Dedicated output compare registers Dual-purpose input capture and output compare registers Function Dual-purpose input capture and output compare registers Rev. 3.0, 09/04, page 338 of 1086 General Registers 1A to 1H and 2A to 2H (GR1A to GR1H, GR2A to GR2H) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W These GR registers are 16-bit readable/writable registers with both input capture and output compare functions. Function switching is performed by means of the timer I/O control registers (TIOR). When a general register is used for input capture, it stores the TCNT1A or TCNT2A value on detection of an input capture signal from an external source. The corresponding IMF bit in TSR is set to 1 at this time. The input capture signal edge to be detected is specified by the corresponding TIOR. When a general register is used for output compare, the GR value and free-running counter (TCNT1A, TCNT2A) value are constantly compared, and when both values match, the IMF bit in the timer status register (TSR) is set to 1. If connection of channels 1 and 2 and channel 8 is specified in the timer connection register (TCNR), the corresponding channel 8 down-counter (DCNT) is started. Compare-match output is specified by the corresponding TIOR. The GR registers can only be accessed by a word read or write. The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. General Registers 3A to 3D, 4A to 4D, 5A to 5D, 11A and 11B (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D, GR11A and GR11B) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W These GR registers are 16-bit readable/writable registers with both input capture and output compare functions. Function switching is performed by means of the timer I/O control registers (TIOR). When a general register is used for input capture, it stores the corresponding TCNT value on detection of an input capture signal from an external source. The corresponding IMF bit in TSR is set to 1 at this time. The input capture signal edge to be detected is specified by the corresponding Rev. 3.0, 09/04, page 339 of 1086 TIOR. GR3A to GR3D can also be used for input capture with a channel 9 compare-match as the trigger. In this case, the corresponding IMF bit in TSR is not set. When a general register is used for output compare, the GR value and free-running counter (TCNT) value are constantly compared, and when both values match, the IMF bit in the timer status register (TSR) is set to 1. Compare-match output is specified by the corresponding TIOR. GRIIA and GR11B compare-match signals are transmitted to the advanced pulse controller (APC). For details, see section 12, Advanced Pulse Controller (APC). The GR registers can only be accessed by a word read or write. The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. General Registers 9A to 9F (GR9A to GR9F) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W These GR registers are 8-bit readable/writable registers with a compare-match function. The GR value and event counter (ECNT) value are constantly compared, and when both values match a compare-match signal is generated and the next edge is input, the corresponding CMF bit in TSR is set to 1. In addition, channel 3 (GR3A to GR3D) input capture can be generated by GR9A to GR9D compare-matches. This function is set by TRG3xEN in the timer control register (TCR). The GR registers can be accessed by a byte read or write. The GR registers are initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. Rev. 3.0, 09/04, page 340 of 1086 11.2.21 Offset Base Registers (OSBR) The offset base registers (OSBR) are 16-bit registers. The ATU-II has two OSBR registers, one each in channels 1 and 2. Channel 1 2 Abbreviation OSBR1 OSBR2 Function Dedicated input capture registers with the same input trigger signal as that for channel 0 ICR0A Offset Base Registers 1 and 2 (OSBR1, OSBR2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R OSBR1 and OSBR2 are 16-bit read-only registers used exclusively for input capture. Same as the channel 0 input capture register (ICR0A), OSBR1 and OSBR2 use the TI0A input as their trigger signal, and store the TCNT1A or TCNT2A value on detection of an edge. The OSBR registers can only be accessed by a word read. The OSBR registers are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 11.3.8, Twin Capture Function (TRGMDR). 11.2.22 Cycle Registers (CYLR) The cycle registers (CYLR) are 16-bit registers. The ATU-II has eight cycle registers, four each in channels 6 and 7. Channel 6 7 Abbreviation CYLR6A– CYLR6D CYLR7A– CYLR7D Function 16-bit PWM cycle registers Rev. 3.0, 09/04, page 341 of 1086 Cycle Registers (CYLR6A to CYLR6D, CYLR7A to CYLR7D) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The CYLR registers are 16-bit readable/writable registers used for PWM cycle storage. The CYLR value is constantly compared with the corresponding free-running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D) value, and when the two values match, the corresponding timer start register (TSR) bit (CMF6A to CMF6D, CMF7A to CMF7D) is set to 1, and the freerunning counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D) is cleared. At the same time, the buffer register (BFR) value is transferred to the duty register (DTR). The corresponding output pins (TO6A to TO6D, TO7A to TO7D) go to 0 output when the BFR value is H'0000. In other cases, they go to 1 output. The CYLR registers can only be accessed by a word read or write. The CYLR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. For details of the CYLR, BFR, and DTR registers, see section 11.3.9, PWM Timer Function. 11.2.23 Buffer Registers (BFR) The buffer registers (BFR) are 16-bit registers. The ATU-II has eight buffer registers, four each in channels 6 and 7. Channel 6 Abbreviation BFR6A–BFR6D Function 16-bit PWM buffer registers Buffer register (BFR) value is transferred to duty register (DTR) on compare-match of corresponding cycle register (CYLR) 7 BFR7A–BFR7D Buffer Registers (BFR6A to BFR6D, BFR7A to BFR7D) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 3.0, 09/04, page 342 of 1086 The BFR registers are 16-bit readable/writable registers that store the value to be transferred to the duty register (DTR) in the event of a cycle register (CYLR) compare-match. The BFR registers can only be accessed by a word read or write. The BFR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. 11.2.24 Duty Registers (DTR) The duty registers (DTR) are 16-bit registers. The ATU-II has eight duty registers, four each in channels 6 and 7. Channel 6 7 Abbreviation DTR6A–DTR6D DTR7A–DTR7D Function 16-bit PWM duty registers Duty Registers (DTR6A to DTR6D, DTR7A to DTR7D) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The DTR registers are 16-bit readable/writable registers used for PWM duty storage. The DTR value is constantly compared with the corresponding free-running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D) value, and when the two values match, the corresponding channel output pin (TO6A to TO6D, TO7A to TO7D) goes to 0 output. Also, when CYLR and the corresponding the free-running counter match, the corresponding BFR value is loaded. Set a value in the range 0 to CYLR for DTR; do not set a value greater than CYLR. The DTR registers can only be accessed by a word read or write. The DTR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. Rev. 3.0, 09/04, page 343 of 1086 11.2.25 Reload Register (RLDR) The reload register is a 16-bit register. The ATU-II has one RLDR register in channel 8. Reload Register 8 (RLDR8) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RLDR8 is a 16-bit readable/writable register. When reload is enabled (by a setting in RLDENR) and DSTR8I to DSTR8P are set to 1 by the channel 2 compare-match signal one-shot pulse start trigger, the reload register value is transferred to DCNT8I to DCNT8P before the down-count is started. The reload register value is not transferred when the one-shot pulse function is used independently, without linkage to channel 2, or when down-counters DCNT8I to DCNT8P are running. RLDR8 can only be accessed by a word read or write. RLDR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. 11.2.26 Channel 10 Registers Counters (TCNT) Channel 10 has seven TCNT counters: one 32-bit TCNT, four 16-bit TCNTs, and two 8-bit TCNTs. The input clock is selected with prescaler register 4 (PSCR4). Count operations are performed by setting STR10 to 1 in timer start register 1 (TSTR1). Channel 10 Abbreviation TCNT10AH, AL TCNT10B TCNT10C TCNT10D TCNT10E TCNT10F TCNT10G Function 32-bit free-running counter (initial value H'00000001) 8-bit event counter (initial value H'00) 16-bit reload counter (initial value H'0001) 8-bit correction counter (initial value H'00) 16-bit correction counter (initial value H'0000) 16-bit correction counter (initial value H'0001) 16-bit free-running counter (initial value H'0000) Rev. 3.0, 09/04, page 344 of 1086 Free-Running Counter 10AH, AL (TCNT10AH, TCNT10AL): Free-running counter 10AH, AL (comprising TCNT10AH and TCNT10AL) is a 32-bit readable/writable register that counts on an input clock and is cleared to initial value by input capture input (TI10) (AGCK). Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10A can only be accessed by a longword read or write. Word reads or writes should not be used. TCNT10A is initialized to H'00000001 by a power-on reset, and in hardware standby mode and software standby mode. Event Counter 10B (TCNT10B): Event counter 10B (TCNT10B) is an 8-bit readable/writable register that counts on external clock input (TI10) (AGCK). For this operation, TI10 input must be set with bits CKEG1 and CKEG0 in TCR10. TI10 input will be counted even if halting of the count operation is specified by bit STR10 in TSTR1. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCNT10B can only be accessed by a byte read or write. TCNT10B is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev. 3.0, 09/04, page 345 of 1086 Reload Counter 10C (TCNT10C): Reload counter 10C (TCNT10C) is a 16-bit readable/writable register. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When TCNT10C = H'0001 in the down-count operation, the value in the reload register (RLD10C) is transferred to TCNT10C, and a multiplied clock (AGCK1) is generated. TCNT10C is connected to the CPU via an internal 16-bit bus, and can only be accessed by a word read or write. TCNT10C is initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode. Correction Counter 10D (TCNT10D): Correction counter 10D (TCNT10D) is an 8-bit readable/writable register that counts on external clock input (TI10) after transfer of the counter value to correction counter E (TCNT10E). Set TI10 input with bits CKEG1 and CKEG0 in TCR10. Transfer and counting will not be performed on TI10 input unless the count operation is enabled by bit STR10 in TSTR1. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W At the external clock input (TI10) (AGCK) timing, the value in this counter is shifted according to the multiplication factor set by bits PIM1 and PIM0 in timer I/O control register 10 (TIOR10) and transferred to correction counter E (TCNT10E). TCNT10D can only be accessed by a byte read or write. TCNT10D is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev. 3.0, 09/04, page 346 of 1086 Correction Counter 10E (TCNT10E): Correction counter 10E (TCNT10E) is a 16-bit readable/writable register that loads the TCNT10D shift value at the external input (TI10) timing, and counts on the multiplied clock (AGCK1) output by reload counter 10C (TCNT10C). However, if CCS in timer I/O control register 10 (TIOR10) is set to 1, when the TCNT10D shifted value is reached the count is halted. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10E can only be accessed by a word read or write. TCNT10E is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Correction Counter 10F (TCNT10F): Correction counter 10F (TCNT10F) is a 16-bit readable/writable register that counts up on Pφ clock cycles if the counter value is smaller than the correction counter 10E (TCNT10E) value when the STR10 bit in TSTR1 has been set for counter operation. The count is halted by a match with the correction counter clear register (TCCLR10). If TI10 is input when TCNT10D = H'00, TCNT10F is initialized and correction is carried out. When TCNT10F = TCCLR10, TCNT10F is cleared to H'0001. While TCNT10F ≠ TCCLR10, TCNT10F is incremented automatically until it reaches the TCCLR10 value, and is then cleared to H'0001. A corrected clock (AGCKM) is output following correction each time this counter is incremented. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10F is can only be accessed by a word read or write. TCNT10F is initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode. Rev. 3.0, 09/04, page 347 of 1086 Free-Running Counter 10G (TCNT10G): Free-running counter 10G (TCNT10G) is a 16-bit readable/writable register that counts up on the multiplied clock (AGCK1). TCNT10G is initialized to H'0000 by input from external input (TI10) (AGCK). Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10G can only be accessed by a word read or write. TCNT10G is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Registers There are six registers in channel 10: a 32-bit ICR, 32-bit OCR, 16-bit GR, 16-bit RLD, 16-bit TCCLR, and 8-bit OCR. Channel 10 Abbreviation ICR10AH, AL OCR10AH, AL OCR10B RLD10C GR10G TCCLR10 Function 32-bit input capture register (initial value H'00000000) 32-bit output compare register (initial value H'FFFFFFFF) 8-bit output compare register (initial value H'FF) 16-bit reload register (initial value H'0000) 16-bit general register (initial value H'FFFF) 16-bit correction counter clear register (initial value H'0000) Rev. 3.0, 09/04, page 348 of 1086 Input Capture Register 10AH, AL (ICR10AH, ICR10AL): Input capture register 10AH, AL (comprising ICR10AH and ICR10AL) is a 32-bit read-only register to which the TCNT10AH, AL value is transferred on external input (TI10) (AGCK). At the same time, ICF10A in timer status register 10 (TSR10) is set to 1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ICR10A is initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode. Output Compare Register 10AH, AL (OCR10AH, OCR10AL): Output compare register 10AH, AL (comprising OCR10AH and OCR10AL) is a 32-bit readable/writable register that is constantly compared with free-running counter 10AH, AL (TCNT10AH, TCNT10AL). When both values match, CMF10A in timer status register 10 (TSR10) is set to 1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCR10A is initialized to H'FFFFFFFF by a power-on reset, and in hardware standby mode and software standby mode. Rev. 3.0, 09/04, page 349 of 1086 Output Compare Register 10B (OCR10B): Output compare register 10B (OCR10B) is an 8-bit readable/writable register that is constantly compared with free-running counter 10B (TCNT10B). When AGCK is input with both values matching, CMF10B in timer status register 10 (TSR10) is set to 1. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W OCR10B is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. Reload Register 10C (RLD10C): Reload register 10C (RLD10C) is a 16-bit readable/writable register. When STR10 in timer start register 1 (TSTR1) is 1 and RLDEN in the timer I/O control register (TIOR10) is 0, and the value of TCNT10A is captured into input capture register 10A (ICR10A), the ICR10A capture value is shifted according to the multiplication factor set by bits PIM1 and PIM0 in TIOR10 before being transferred to RLD10C. The contents of reload register 10C (RLD10C) are loaded when reload counter 10C (TCNT10C) reaches H'0001. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RLD10C is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. General Register 10G (GR10G): General register 10G (GR10G) is a 16-bit readable/writable register with an output compare function. Function switching is performed by means of timer I/O control register 10 (TIOR10). The GR10G value and free-running counter 10G (TCNT10G) value are constantly compared, and when AGCK is input with both values matching, CMF10G in timer status register 10 (TSR10) is set to 1. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W GR10G is initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. Rev. 3.0, 09/04, page 350 of 1086 Correction Counter Clear Register 10 (TCCLR10): Correction counter clear register 10 (TCCLR10) is a 16-bit readable/writable register. TCCLR10 is constantly compared with TCNT10F, and when the two values match, TCNT10F halts. TCNTxx can be cleared at this time by setting TRGxxEN (xx = 1A, 1B, 2A, 2B) in TCR10. Then, when TCNT10D is H'00 and TI10 is input, TCNT10F is cleared to H'0001. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCCLR10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Noise Canceler Registers There are two 8-bit noise canceler registers in channel 10: TCNT10H and NCR10. Channel 10 Abbreviation TCNT10H NCR10 Function Noise canceler counter Noise canceler compare-match register (Initial value H'00) (Initial value H'FF) Noise Canceler Counter 10H (TCNT10H): Noise canceler counter 10H (TCNT10H) is an 8-bit readable/writable register. When the noise canceler function is enabled, TCNT10H starts counting up on Pφ × 10, with the signal from external input (TI10) (AGCK) as a trigger. The counter operates even if STR10 is cleared to 0 in the timer start register (TSTR1). TI10 input is masked while the counter is running. When the count matches the noise canceler register (NCR10) value, the counter is cleared and TI10 input masking is released. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCNT10H is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev. 3.0, 09/04, page 351 of 1086 Noise Canceler Register 10 (NCR10): Noise canceler register 10 (NCR10) is an 8-bit readable/writable register used to set the upper count limit of noise canceler counter 10H (TCNT10H). TCNT10H is constantly compared with NCR10 during the count, and when a compare-match occurs the TCNT10H counter is halted and input signal masking is released. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W NCR10 is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. Channel 10 Control Registers There are four control registers in channel 10. Channel 10 Abbreviation TIOR10 Function Reload setting, counter correction setting, external input (TI10) edge interval multiplier setting GR compare-match setting TCR10 TCCLR10 counter clear source Noise canceler function enabling/disabling selection External input (TI10) edge selection TSR10 TIER10 Input capture/compare-match status (Initial value H'00) (Initial value H'0000) (Initial value H'00) Input capture/compare-match interrupt request enabling/disabling selection (Initial value H'0000) Rev. 3.0, 09/04, page 352 of 1086 Timer I/O Control Register 10 (TIOR10): TIOR10 is an 8-bit readable/writable register that selects the value for multiplication of the external input (TI10) edge interval. It also makes a setting for using the general register (GR10G) for output compare, and makes the edge detection setting. TIOR10 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 RLDEN Initial value: R/W: 0 R/W 6 CCS 0 R/W 5 PIM1 0 R/W 4 PIM0 0 R/W 3 — 0 — 2 1 0 IO10G2 IO10G1 IO10G0 0 R/W 0 R/W 0 R/W • Bit 7—Reload Enable (RLDEN): Enables or disables transfer of the input capture register 10A (ICR10A) value to reload register 10C (RLD10C). Bit 7: RLDEN 0 1 Description Transfer of ICR10A value to RLD10C on input capture is enabled (Initial value) Transfer of ICR10A value to RLD10C on input capture is disabled • Bit 6—Counter Clock Select (CCS): Selects the operation of correction counter 10E (TCNT10E). Set the multiplication factor with bits PIM1 and PIM0. Bit 6: CCS 0 1 Description TCNT10E count is not halted when TCNT10D x multiplication factor = TCNT10E* (Initial value) TCNT10E count is halted when TCNT10D x multiplication factor = TCNT10E* Note: * When [TCNT10D × multiplication factor] matches the value of TCNT10E with bits 8 to 0 masked • Bits 5 and 4—Pulse Interval Multiplier (PIM1, PIM0): These bits select the external input (TI10) cycle multiplier. Bit 5: PIM1 0 Bit 4: PIM0 0 1 1 0 1 Description Counting on external input cycle × 32 Counting on external input cycle × 64 Counting on external input cycle × 128 Counting on external input cycle × 256 (Initial value) • Bit 3—Reserved: This bit is always read as 0. The write value should always be 0. Rev. 3.0, 09/04, page 353 of 1086 • Bits 2 to 0—I/O Control 10G2 to 10G0 (IO10G2 to IO10G0): These bits select the function of general register 10G (GR10G). Bit 2: IO10G2 0 Bit 1: IO10G1 0 Bit 0: IO10G0 0 1 1 1 *: Don't care * * * Cannot be used Description GR is an output compare register Compare-match disabled (Initial value) GR10G = TCNT10G compare-match Cannot be used Timer Control Register 10 (TCR10): TCR10 is an 8-bit readable/writable register that selects the correction counter clear register (TCCLR10) compare-match counter clear source, enables or disables the noise canceler function, and selects the external input (TI10) edge. TCR10 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 6 5 4 3 2 NCE 1 CKEG1 0 CKEG0 TRG2BEN TRG1BEN TRG2AEN TRG1AEN TRG0DEN Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W • Bit 7—Trigger 2B Enable (TRG2BEN): Enables or disables counter clearing for channel 2 TCNT2B. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT2B count clock. If TCNT2B counts while clearing is enabled, TCNT2B will be cleared. Bit 7: TRG2BEN 0 1 Description Channel 2 counter B (TCNT2B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) Channel 2 counter B (TCNT2B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled Rev. 3.0, 09/04, page 354 of 1086 • Bit 6—Trigger 1B Enable (TRG1BEN): Enables or disables counter clearing for channel 1 TCNT1B. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT1B count clock. If TCNT1B counts while clearing is enabled, TCNT1B will be cleared. Bit 6: TRG1BEN 0 1 Description Channel 1 counter B (TCNT1B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) Channel 1 counter B (TCNT1B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled • Bit 5—Trigger 2A Enable (TRG2AEN): Enables or disables counter clearing for channel 2 TCNT2A. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT2A count clock. If TCNT2A counts while clearing is enabled, TCNT2A will be cleared. Bit 5: TRG2AEN 0 1 Description Channel 2 counter 2A (TCNT2A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) Channel 2 counter 2A (TCNT2A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled • Bit 4—Trigger 1A Enable (TRG1AEN): Enables or disables counter clearing for channel 1 TCNT1A. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT1A count clock. If TCNT1A counts while clearing is enabled, TCNT1A will be cleared. Bit 4: TRG1AEN 0 1 Description Channel 1 counter 1A (TCNT1A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) Channel 1 counter 1A (TCNT1A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled • Bit 3—Trigger 0D Enable (TRG0DEN): Enables or disables channel 0 ICR0D input capture signal requests. Bit 3: TRG0DEN 0 1 Description Capture requests for channel 0 input capture register (ICR0D) on event counter (TCNT10B) compare-match are disabled (Initial value) Capture requests for channel 0 input capture register (ICR0D) on event counter (TCNT10B) compare-match are enabled Rev. 3.0, 09/04, page 355 of 1086 • Bit 2—Noise Canceler Enable (NCE): Enables or disables the noise canceler function. Bit 2: NCE 0 1 Description Noise canceler function is disabled Noise canceler function is enabled (Initial value) • Bits 1 and 0—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the channel 10 external input (TI10) edge(s). The clock (AGCK) is generated by the detected edge(s). Bit 1: CKEG1 0 Bit 0: CKEG0 0 1 1 0 1 Description TI10 input disabled TI10 input rising edges detected TI10 input falling edges detected TI10 input rising and falling edges both detected (Initial value) Timer Status Register 10 (TSR10): TSR10 is a 16-bit readable/writable register that indicates the occurrence of channel 10 input capture or compare-match. Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is enabled by the corresponding bit in timer interrupt enable register 10 (TIER10). TSR10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 — 0 R 12 — 0 R 4 — 0 R 11 — 0 R 3 10 — 0 R 2 9 — 0 R 1 8 — 0 R 0 CMF10G CMF10B ICF10A CMF10A 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* Note: * Only 0 can be written to clear the flag. • Bits 15 to 4—Reserved: These bits are always read as 0. The write value should always be 0. Rev. 3.0, 09/04, page 356 of 1086 • Bit 3—Compare-Match Flag 10G (CMF10G): Status flag that indicates GR10G comparematch. Bit 3: CMF10G 0 1 Description [Clearing condition] (Initial value) When CMF10G is read while set to 1, then 0 is written to IMF10G [Setting condition] When TCNT10G = GR10G • Bit 2—Compare-Match Flag 10B (CMF10B): Status flag that indicates OCR10B comparematch. Bit 2: CMF10B 0 1 Description [Clearing condition] (Initial value) When CMF10B is read while set to 1, then 0 is written to CMF10B [Setting condition] When TCNT10B is incremented while TCNT10B = OCR10B • Bit 1—Input Capture Flag 10A (ICF10A): Status flag that indicates ICR10A input capture. Bit 1: ICF10A 0 1 Description [Clearing condition] (Initial value) When ICR10A is read while set to 1, then 0 is written to ICR10A [Setting condition] When the TCNT10A value is transferred to ICR10A by an input capture signal • Bit 0—Compare-Match Flag 10A (CMF10A): Status flag that indicates OCR10A comparematch. Bit 0: CMF10A 0 1 Description [Clearing condition] (Initial value) When CMF10A is read while set to 1, then 0 is written to CMF10A [Setting condition] When TCNT10A = OCR10A Rev. 3.0, 09/04, page 357 of 1086 Timer Interrupt Enable Register 10 (TIER10): TIER10 is a 16-bit readable/writable register that controls enabling/disabling of channel 10 input capture and compare-match interrupt requests. TIER10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 — 0 R 12 — 0 R 4 IREG 0 R/W 11 — 0 R 3 10 — 0 R 2 9 — 0 R 1 8 — 0 R 0 CME10G CME10B ICE10A CME10A 0 R/W 0 R/W 0 R/W 0 R/W • Bits 15 to 5—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 4—Interrupt Enable Edge G (IREG): Specifies TSR10 CMF10G interrupt request timing. Bit 4: IREG 0 1 Description Interrupt is requested when CMF10G becomes 1 (Initial value) Interrupt is requested by next external input (TI10) (AGCK) after CMF10G becomes 1 • Bit 3—Compare-Match Interrupt Enable 10G (CME10G): Enables or disables interrupt requests by CMF10G in TSR10 when CMF10G is set to 1. Bit 3: CME10G 0 1 Description CMI10G interrupt requested by CMF10G is disabled CMI10G interrupt requested by CMF10G is enabled (Initial value) • Bit 2—Compare-Match Interrupt Enable 10B (CME10B): Enables or disables interrupt requests by CMF10B in TSR10 when CMF10B is set to 1. Bit 2: CME10B 0 1 Description CMI10B interrupt requested by CMF10B is disabled CMI10B interrupt requested by CMF10B is enabled (Initial value) Rev. 3.0, 09/04, page 358 of 1086 • Bit 1—Input Capture Interrupt Enable 10A (ICE10A): Enables or disables interrupt requests by ICF10A in TSR10 when ICF10A is set to 1. Bit 1: ICE10A 0 1 Description ICI10A interrupt requested by ICF10A is disabled ICI10A interrupt requested by ICF10A is enabled (Initial value) • Bit 0—Compare-Match Interrupt Enable 10A (CME10A): Enables or disables interrupt requests by CMF10A in TSR10 when CMF10A is set to 1. Bit 0: CME10A 0 1 Description CMI10A interrupt requested by CMF10A is disabled CMI10A interrupt requested by CMF10A is enabled (Initial value) Rev. 3.0, 09/04, page 359 of 1086 11.3 11.3.1 Operation Overview The ATU-II has twelve timers of eight kinds in channels 0 to 11. It also has a built-in prescaler that generates input clocks, and it is possible to generate or select internal clocks of the required frequency independently of circuitry outside the ATU-II. The operation of each channel and the prescaler is outlined below. Channel 0: Channel 0 has a 32-bit free-running counter (TCNT0) and four 32-bit input capture registers (ICR0A to ICR0D). TCNT0 is an up-counter that performs free-running operation. An interrupt request can be generated on counter overflow. The four input capture registers (ICR0A to ICR0D) capture the free-running counter (TCNT0) value by means of input from the corresponding external signal input pin (TI0A to TI0D). For capture by means of input from an external signal input pin, rising edge, falling edge, or both edges can be selected in the timer I/O control register (TIOR0). In the case of input capture register 0D (ICR0D) only, capture can be performed by means of a compare-match between free-running counter 10B (TCNT10B) and compare-match register 10B (OCR10B), by making a setting in timer control register 10 (TCR10). In this case, capture is performed even if an input capture disable setting has been made for TIOR0. In each case, the DMAC can be activated or an interrupt requested when capture occurs. Channel 0 also has three interval interrupt request registers (ITVRR1, ITVRR2A, and ITVRR2B). A/D converter (AD0 to AD2) activation can be selected by setting 1 in ITVA6 to ITVA13 in ITVRR, and an interrupt request to the CPU by setting 1 in ITVE6 to ITVE13. These operations are performed when the corresponding bit of bits 6 to 13 in TCNT0 changes to 1, enabling use as an interval timer function. Channel 1: Channel 1 has two 16-bit free-running counters (TCNT1A and TCNT1B), eight 16-bit general registers (GR1A to GR1H), and a 16-bit output compare register (OCR1). TCNT1A and TCNT1B are up-counters that perform free-running operation. When the clock generated in channel 10 (described below) is selected, these counters can be cleared at the count specified in channel 10. Each counter can generate an interrupt request when it overflows. The eight general registers (GR1A to GR1H) can be used as input capture or output compare registers using the corresponding external signal I/O pin (TIO1A to TIO1H). When used for input capture, the free-running counter (TCNT1A) value is captured by means of input from the corresponding external signal I/O pin (TIO1A to TIO1H). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control registers (TIOR1A to TIOR1D). When used for output compare, compare-match with the free-running counter (TCNT1A) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR1A to Rev. 3.0, 09/04, page 360 of 1086 TIOR1D). When used as output compare registers, a compare-match can be used as a one-shot pulse start/terminate trigger by setting the channel 8 timer connection register (TCNR) and oneshot pulse terminate register (OTR), and using these in combination with the down-counters (DCNT8A to DCNT8H). Start/terminate trigger selection is performed by means of the trigger mode register (TRGMDR). In the case of the output compare register (OCR1), a TCNT1B compare-match can be used as a one-shot pulse start trigger, in the same way as the general registers, in combination with channel 8 down-counters DCNT8A to DCNT8H. An interrupt can be requested on the occurrence of the respective input capture or compare-match. In addition, channel 1 has a 16-bit dedicated input capture register (OSBR1). The channel 0 TI0A input pin can also be used as the OSBR1 trigger input, enabling use of a twin-capture function. Channel 2: Channel 2 has two 16-bit free-running counters (TCNT2A and TCNT2B), eight 16-bit general registers (GR2A to GR2H), and eight 16-bit output compare registers (OCR2A to OCR2H). TCNT2A and TCNT2B are up-counters that perform free-running operation. When the clock generated in channel 10 (described below) is selected, these counters can be cleared at the count specified in channel 10. Each counter can generate an interrupt request when it overflows. The eight general registers (GR2A to GR2H) can be used as input capture or output compare registers using the corresponding external signal I/O pin (TIO2A to TIO2H). When used for input capture, the free-running counter (TCNT2A) value is captured by means of input from the corresponding external signal I/O pin (TIO2A to TIO2H). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control registers (TIOR2A to TIOR2D). When used for output compare, compare-match with the free-running counter (TCNT2A) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR2A to TIOR2D). When used as output compare registers, a compare-match can be used as a one-shot pulse terminate trigger by setting the channel 8 one-shot pulse terminate register (OTR), and using this in combination with the down-counters (DCNT8I to DCNT8P). In the case of the output compare registers (OCR2A to OCR2H), a TCNT2B compare-match can be used as a one-shot pulse start trigger by setting the channel 8 timer connection register (TCNR), and using this in combination with the down-counters (DCNT8I to DCNT8P). An interrupt can be requested on the occurrence of the respective input capture or compare-match. In addition, channel 2 has a 16-bit dedicated input capture register (OSBR2). The channel 0 TI0A input pin can also be used as the OSBR2 trigger input, enabling use of a twin-capture function. Channels 3 to 5: Channels 3 to 5 each have a 16-bit free-running counter (TCNT3 to TCNT5) and four 16-bit general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D). TCNT3 to TCNT5 are up-counters that perform free-running operation. Channels 3 to 5 each have a 16-bit Rev. 3.0, 09/04, page 361 of 1086 free-running counter (TCNT3 to TCNT5) and four 16-bit general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D). TCNT3 to TCNT5 are up-counters that perform free-running operation. In addition, counter clearing can be performed by compare-match by making a setting in the timer I/O control register (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). Each counter can generate an interrupt request when it overflows. The four general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D) each have corresponding external signal I/O pins (TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D), and can be used as input capture or output compare registers. When used for input capture, the free-running counter (TCNT3 to TCNT5) value is captured by means of input from the corresponding external signal I/O pin (TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control registers (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). Also, in use for input capture, input capture can be performed using a compare-match between a channel 9 event counter (ECNT9A to ECNT9D), described later, and a general register (GR9A to GR9D) as the trigger (channel 3 only). In this case, capture is performed even if an input capture disable setting has been made for TIOR3A to TIOR3D. When used for output compare, compare-match with the free-running counter (TCNT3 to TCNT5) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). An interrupt can be requested on the occurrence of the respective input capture or compare-match. However, in the case of input capture using channel 9 as a trigger, an interrupt request from channel 3 cannot be used. By selecting PWM mode in the timer mode register (TMDR), PWM output can be obtained, with three outputs for each. In this case, GR3D, GR4D, and GR5D are automatically used as cycle registers, and GR3A to GR3C, GR4A to GR4C, GR5A to GR5C, as duty registers. TCNT3 to TCNT5 are cleared by the corresponding GR3D, GR4D, or GR5D compare-match. Channels 6 and 7: Channels 6 and 7 each have 16-bit free-running counters (TCNT6A to TCNT6D, TCNT7A to TCNT7D), 16-bit cycle registers (CYLR6A to CYLR6D, CYLR7A to CYLR7D), 16-bit duty registers (DTR6A to DTR6D, DTR7A to DTR7D), and buffer registers (BFR6A to BFR6D, BFR7A to BFR7D). Channels 6 and 7 also each have external output pins (TO6A to TO6D, TO7A to TO7D), and can be used as buffered PWM timers. The TCNT registers are up-counters, and 0 is output to the corresponding external output pin when the TCNT value matches the DTR value (when DTR ≠ CYLR). When the TCNT value matches the CYLR value (when DTR ≠ H'0000), 1 is output to the external output pin, TCNT is initialized to H'0001, and the BFR value is transferred to DTR. Thus, the configuration of channels 6 and 7 enables them to perform waveform output with the CYLR value as the cycle and the DTR value as the duty, and to use BFR to absorb the time lag between setting of data in DTR and compare-match occurrence. When DTR = CYLR, 1 is output continuously to the external output pin, giving a duty of 100%. When DTR = H'0000, 0 is output continuously to the external output pin, giving a duty of 0%. Do not set a value in DTR that will result in the condition DTR > CYLR. To set H'0000 to DTR, not Rev. 3.0, 09/04, page 362 of 1086 write H'0000 directly to DTR but set H'0000 to BFR and then transfer the value to DTR. Writing H'0000 directly to DTR may not give a duty of 0%. In channel 6, TCNT can also be designated for complementary PWM output by means of the PWM mode register (PMDR). When the corresponding TSTR is set to 1, TCNT starts counting up, then switches to a down-count when the count matches the CYLR value. When TCNT reaches H'0000, it starts counting up again. When TCNT = DTR, the corresponding TO6A to TO6D output changes. Whether TCNT is counting up or down can be ascertained from the timer status register (TSR6). DMAC activation and interrupt request generation, respectively, are possible when TCNT = CYLR in asynchronous PWM mode, and when TCNT = H'0000 in complementary PWM mode. Channel 8: Channel 8 has sixteen 16-bit down-counters (DCNT8A to DCNT8P). The downcounters have corresponding external signal output pins, and can generate one-shot pulses. Setting a value in DCNT and setting the corresponding bit to 1 in the down-count start register (DSTR) starts DCNT operation and simultaneously outputs 1 to the external output pin. When DCNT counts down to H'0000, it stops and outputs 0 to the external output pin. An interrupt can be requested when DCNT underflows. Down-counter operation can be coupled with the channel 1 or channel 2 output compare function by means of settings in the timer connection register (TCNR) and one-shot pulse terminate register (OTR), respectively, so that DCNT8I to DCNT8H count operations are started and stopped from channel 1, and DCNT8I to DCNT8P count operations from channel 2. DCNT8I to DCNT8P have a reload register (RLDR), and a setting in the reload enable register (RLDEN) enables count operations to be started after reading the value from this register. Channel 9: Channel 9 has six 8-bit event counters (ECNT9A to ECNT9F) and six 8-bit general registers (GR9A to GR9F). The event counters are up-counters, each with a corresponding external input pin (ECNT9A to ECNT9F). The event counter value is incremented by input from the corresponding external input pin. Incrementing on the rising edge, falling edge, or both edges can be selected by means of settings in the timer control registers (TCR9A to TCR9C). An event counter is cleared by edge input after a match with the corresponding general register. An interrupt can requested when an event counter is cleared. Timer control register (TCR9A, TCR9B) settings can be made to enable event counters ECNT9A to ECNT9D to send a compare-match signal to channel 3 when the count matches the corresponding general register (GR9A to GR9D), allowing input capture to be performed on channel 3. This enables the pulse input interval to be measured. Channel 10: Channel 10 generates a multiplied clock based on external input, and supplies this to channels 1 to 5. Channel 10 is divided into three blocks: (1) an inter-edge measurement block, (2) a multiplied clock generation block, and (3) a multiplied clock correction block. Rev. 3.0, 09/04, page 363 of 1086 (1) Inter-edge measurement block This block has a 32-bit free-running counter (TCNT10A), 32-bit input capture register (ICR10A), 32-bit output compare register (OCR10A), 8-bit event counter (TCNT10B), 8-bit output compare register (OCR10B), 8-bit noise canceler counter (TCNT10H), and 8-bit noise canceler compare-match register (NCR10). The 32-bit free-running counter (TCNT10A) is an up-counter that performs free-running operations. When input capture is performed by means of TI10 input, this counter is cleared to H'00000001. When free-running counter (TCNT10A) reaches the value set in the output compare register (OCR10A), a compare-match interrupt can be requested. The input capture register (ICR10A) has an external signal input pin (TI10), and the freerunning counter (TCNT10A) value can be captured by means of input from TI10. Rising edge, falling edge, or both edges can be selected by making a setting in bits CKEG1 and CKEG0 in the timer control register (TCR10). The TI10 input has a noise canceler function, which can be enabled by setting the NCE bit in the timer control register (TCR10). When the counter value is captured, TCNT10A is cleared to 0 and an interrupt can be requested. The captured value can be transferred to the multiplied clock generation block reload register (RLD10C). The 8-bit event counter (TCNT10B) is an up-counter that is incremented by TI10 input. When the event counter (TCNT10B) value reaches the value set in the output compare register (OCR10B), a compare-match interrupt can be requested. By setting the TRG0DEN bit in the timer control register (TCR10), a capture request can also be issued for the channel 0 input capture register 0D (ICR0D) when compare-match occurs. The 8-bit noise canceler counter (TCNT10H) and 8-bit noise canceler compare-match register (NCR10) are used to set the period for which the noise canceler functions. By setting a value in the noise canceler compare-match register (TCNT10H) and setting the NCE bit in the timer control register (TCR10), TI10 input is masked when it occurs. At the same time as TI10 input is masked, the noise canceler counter (TCNT10H) starts counting up on the Pφx10 clock. When the noise canceler counter (TCNT10H) value matches the noise canceler compare-match register (NCR10) value, the noise canceler counter (TCNT10H) is cleared to H'0000 and TI10 input masking is cleared. (2) Multiplied clock generation block This block has 16-bit reload counters (TCNT10C, RLD10C), a 16-bit register free-running counter (TCNT10G), and a 16-bit general register (GR10G). 16-bit reload counter 10C (RLD10C) is captured by 32-bit input capture register 10A (ICR10A), and when RLDEN in the timer I/O control register (TIOR10) is 0, the value captured in input capture register 10A is transferred to the multiplied clock generation block reload register (RLD10C). The value transferred can be selected from 1/32, 1/64, 1/128, or 1/256 the original value, according to the setting of bits PIM1 and PIM0 in TIOR10. Rev. 3.0, 09/04, page 364 of 1086 16-bit reload counter 10C (TCNT10C) performs down-count operations. When TCNT10C reaches H'0001, the value is read automatically from the reload buffer (RLD10C), internal clock AGCK1 is generated, and the down-count operation is repeated. Internally generated AGCK1 is input as a clock to the multiplied clock correction block 16-bit correction counter (TCNT10E) and 16-bit free-running counter 10G (TCNT10G). 16-bit register free-running counter 10G (TCNT10G) counts on AGCK1 generated by TCNT10C. It is initialized to H'0000 by external input from TI10. The 16-bit general register (GR10G) can be used in a compare-match with free-running counter 10G (TCNT10G) by setting bits IO10G2 to IO10G0 in the timer I/O control register (TIOR10). An interrupt can be requested when a compare-match occurs. Also, by setting timer interrupt enable register 10 (TIER10), an interrupt can be request in the event of TI10 input after a compare-match. (3) Multiplied clock correction block This block has three 16-bit correction counters (TCNT10D, TCNT10E, TCNT10F) and a 16bit correction counter clear register (TCCLR10). When 32-bit input capture register 10A (ICR10A) performs a capture operation due to input from external input pin TI10, the value in correction counter 10D (TCNT10D) is transferred to TCNT10E and TCNT10D is incremented. The value transferred to TCNT10E is 32, 64, 128, or 256 times the TCNT10D value, according to the setting of bits PIM1 and PIM0 in the timer I/O control register (TIOR10). 16-bit correction counter 10E (TCNT10E) counts up on AGCK1 generated by reload counter 10C (TCNT10C, RLD10C) in the multiplied clock generation block. However, by setting the CCS bit in the timer I/O control register (TIOR10), it is possible to stop free-running counter 10E (TCNT10E) when the free-running counter 10D (TCNT10D) multiplication value specified by PIM1 and PIM0 and the free-running counter 10E (TCNT10E) value match. The multiplied TCNT10D value is transferred when input capture register 10A (ICR10A) performs a capture operation due to TI10 input. Rev. 3.0, 09/04, page 365 of 1086 16-bit correction counter 10F (TCNT10F) has Pφ as its input and is constantly compared with 16-bit correction counter 10E (TCNT10E). When the 16-bit correction counter 10F (TCNT10F) value is smaller than that in 16-bit correction counter 10E (TCNT10E), it is incremented and generates count-up AGCKM. When the 16-bit correction counter 10F (TCNT10F) value exceeds that in 16-bit correction counter 10E (TCNT10E), no count-up operation is performed. The TI10 multiplied signal (AGCKM) generated when TCNT10F is incremented is output to the channel 1 to 5 free-running counters (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5), and an up-count can be performed on AGCKM by setting this as the counter clock on each channel. TCNT10F is constantly compared with the 16-bit correction counter clear register (TCCLR10), and when the freerunning counter 10F (TCNT10F) and correction counter clear register (TCCLR10) values match, the TCNT10F up-count stops. Setting TRG1AEN, TRG1BEN, TRG2AEN, and TRG2BEN in the timer control register (TCR10) enables the channel 1 and 2 free-running counters (TCNT1A, TCNT1B, TCNT2A, TCNT2B) to be cleared at this time. If TI10 is input when TCNT10D = H'0000, initialization and correction operations are performed. When TCNT10F = TCCLR10, TCNT10F is cleared to H'0001. When TCNT10F ≠ TCCLR10, TCNT10F automatically counts up to the TCCLR10 value, and is cleared to H'0001. Channel 11: Channel 11 has a 16-bit free-running counter (TCNT11) and two 16-bit general registers (GR11A and GR11B). TCNT11 is an up-counter that performs free-running operation. The counter can generate an interrupt request when it overflows. The two general registers (GR11A and GR11B) each have a corresponding external signal I/O pin (TIO11A, TIO11B), and can be used as input capture or output compare registers. When used for input capture, the free-running counter (TCNT11) value is captured by means of input from the corresponding external signal I/O pin (TIO11A, TIO11B). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control register (TIOR11). When used for output compare, compare-match with the free-running counter (TCNT11) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control register (TIOR11). An interrupt can be requested on the occurrence of the respective input capture or compare-match. When the two general registers (GR11A and GR11B) are designated for compare-match use, a compare-match signal can be output to the APC. Prescaler: The ATU-II has a dedicated prescaler with a 2-stage configuration. The first stage comprises 5-bit prescalers (PSCR1 to PSCR4) that generate a 1/m clock (where m = 1 to 32) with respect to clock Pφ. The second prescaler stage allows selection of a clock obtained by further scaling the clock from the first stage by 2n (where n = 0 to 5) according to the timer control registers for the respective channels (TCR1A, TCR1B, TCR2A, TCR2B, TCR3 to TCR5, TCR6A, TCR6B, TCR7A, TCR7B, TCR8, TCR11). The prescalers of channels 1 to 8 and 11 have a 2-stage configuration, while the channel 0 and 10 prescalers only have a first stage. The first-stage prescaler is common to channels 0 to 5, 8, and Rev. 3.0, 09/04, page 366 of 1086 11, and it is not possible to set different first-stage division ratios for each. Channels 6, 7, and 10 each have a first-stage prescaler, and different first-stage division ratios can be set for each. 11.3.2 Free-Running Counter Operation and Cyclic Counter Operation The free-running counters (TCNT) in ATU-II channels 0 to 5 and 11 start counting up as freerunning counters when the corresponding timer start register (TSTR) bit is set to 1. When TCNT overflows (channel 0: from H'FFFFFFFF to H'00000000; channels 1 to 5 and 11: from H'FFFF to H'0000), the OVF bit in the timer status register (TSR) is set to 1. If the OVE bit in the corresponding timer interrupt enable register (TIER) is set to 1 at this time, an interrupt request is sent to the CPU. After overflowing, TCNT starts counting up again from H'00000000 or H'0000. If the TSTR value is cleared to 0 during TCNT operation, the corresponding TCNT halts. In this case, TCNT is not reset. If external output is being performed from the GR for the corresponding TCNT, the output value does not change. Channel 0 free-running counter operation is shown in figure 11.13. Pφ TSTR STR0 TCNT0 Clock TCNT0 00000001 00000002 00000003 00000004 00000005 00000006 FFFFFFFD FFFFFFFE FFFFFFFF 00000000 00000001 00000002 Cleared by software TSR0 OVF0 Figure 11.13 Free-Running Counter Operation and Overflow Timing The free-running counters (TCNT) in ATU-II channels 6 and 7 perform cyclic count operations unconditionally. With channel 3 to 5 free-running counters (TCNT), when the corresponding T3PWM to T5PWM bit in the timer mode register (TMDR) is set to 1, or the corresponding CCI bit in the timer I/O control register (TIOR) is set to 1 when bits T3PWM to T5PWM are 0, the counter for the relevant channel performs a cyclic count. The relevant TCNT counter is cleared by a compare-match of TCNT with GR3D, GR4D, or GR5D in channel 3 to 5, or CYLR in channels 6 and 7 (counter clear function). TCNT starts counting up as a cyclic counter when the corresponding STR bit in TSTR is set to 1 after the TMDR setting is made. When the count value matches the GR3D, GR4D, GR5D, or CYLR value, the corresponding IMF3D, IMF4D, or IMF5D bit in the timer status register (TSR) (or the CMF bit in TSR6 or TSR7 for channels 6 and 7) is set to 1, and TCNT is cleared to H'0000 (H'0001 in channels 6 and 7). Rev. 3.0, 09/04, page 367 of 1086 If the corresponding TIER bit is set to 1 at this time, an interrupt request is sent to the CPU. After the compare-match, TCNT starts counting up again from H'0000 (H'0001 in channels 6 and 7). Figure 11.14 shows the operation when channel 3 is used as a cyclic counter (with a cycle setting of H'0008). P TCNT3 Clock TCNT3 GR3D (period) 0008 0000 0001 0002 0003 0007 0008 0000 0001 0002 0003 0004 0005 0008 Cleared by software 0008 Cleared by software TSR3 IMF3D Figure 11.14 Example of Cyclic Counter Operation 11.3.3 Compare-Match Function Designating general registers in channels 1 to 5 and 11 (GR1A to GR1H, GR2A to GR2H, GR3A to GR3D, GR4A to GR4D, GR5A to GR5D, GR11A, GR11B) for compare-match operation in the timer I/O control registers (TIOR1 to TIOR5, TIOR11) enables compare-match output to be performed at the corresponding external pins (TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D, TIO11A, TIO11B). A free-running counter (TCNT) starts counting up when 1 is set in the timer status register (TSTR). When the desired number is set beforehand in GR, and the TCNT value matches the GR value, the timer status register (TSR) bit corresponding to GR is set and a waveform is output from the corresponding external pin. 1 output, 0 output, or toggle output can be selected by means of a setting in TIOR. If the appropriate interrupt enable register (TIER) setting is made, an interrupt request will be sent to the CPU when a compare-match occurs. To perform internal interrupts by compare-match or compare-match flag polling processing without performing compare-match output, designate the corresponding compare-match output pin as a general I/O pin and select 1 output, 0 output, or toggle output on compare-match in TIOR. Channel 1 and 2 compare-match registers (OCR1, OCR2A to OCR2H) perform compare-match operations unconditionally. However, there are no corresponding output pins. If the appropriate TIER setting is made, an interrupt request will be sent to the CPU when a compare-match occurs. Rev. 3.0, 09/04, page 368 of 1086 Channel 1 and 2 GR and OCR registers can send a trigger/terminate signal to channel 8 when a compare-match occurs. In this case, settings should be made in the trigger mode register (TRGMDR), timer connection register (TCNR), and one-shot pulse terminate register (OTR). An example of compare-match operation is shown in figure 11.15. In the example in figure 11.15, channel 1 is activated, and external output is performed with toggle output specified for GR1A, 1 output for GR1B, and 0 output for GR1C. P TCNT1 Clock TCNT1 003C 003D 003E 003F 0040 007E 007F 0080 0081 0082 0083 0084 0085 GR1A–1C 003E 0081 TIO1A TIO1B TIO1C TSR1 IMF1A–1D Channel 8 start/terminate trigger signal Cleared by software Cleared by software Figure 11.15 Compare-Match Operation 11.3.4 Input Capture Function If input capture registers (ICR0A to ICR0D) and general registers (GR1A to GR1H, GR2A to GR2H, GR3A to GR3D, GR4A to GR4D, GR5A to GR5D, GR11A, GR11B) in channels 1 to 5 and 11 are designated for input capture operation in the timer I/O control registers (TIOR0 to TIOR5, TIOR11), input capture is performed when an edge is input at the corresponding external pins (TI0A to TI0D, TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D). A free-running counter (TCNT) starts counting up when a setting is made in the timer start register (TSTR). When an edge is input at an external pin corresponding to ICR or GR, the corresponding timer status register (TSR) bit is set and the TCNT value is transferred to ICR or GR. Rising-edge, falling-edge, or both-edge detection can be selected. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. Rev. 3.0, 09/04, page 369 of 1086 An example of input capture operation is shown in figure 11.16. In the example in figure 11.16, channel 1 is activated, and input capture operation is performed with both-edge detection specified for TIO1A, rising-edge detection for TIO1B, and falling-edge detection for TIO1C. P TCNT1 Clock TCNT1 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E TIO1A–1C GR1A GR1B GR1C 0003 0003 567A 0003 567A Cleared by software Cleared by software TSR1 IMF1A TSR1 IMF1B TSR1 IMF1C Figure 11.16 Input Capture Operation 11.3.5 One-Shot Pulse Function Channel 8 has sixteen down-counters (DCNT8A to DCNT8P) and corresponding external pins (TO8A to TO8P) which can be used as one-shot pulse output pins. When a value is set beforehand in DCNT and the corresponding bit in the down-counter start register (DSTR) is set, DCNT starts counting down, and at the same time 1 is output from the corresponding external pin. When DCNT reaches H'0000 the down-count stops, the corresponding bit in the timer status register (TSR) is set, and 0 is output from the external pin. The corresponding bit in DSTR is cleared automatically. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. An example of one-shot pulse operation is shown in figure 11.17. In the example in figure 11.17, H'0005 is set in DCNT and a down-count is started. Rev. 3.0, 09/04, page 370 of 1086 P DSTR DST8A DCNT Clock Synchronized with down-counter clock TO8A DCNT8A 0005 0004 0003 0002 0001 0000 Cleared by software TSR8 Figure 11.17 One-Shot Pulse Output Operation 11.3.6 Offset One-Shot Pulse Function and Output Cutoff Function By making an appropriate setting in the timer connection register (TCNR), down-counting by channel 8 down-counters (DCNT8A to DCNT8P) can be started using compare-match signals from channel 1 general registers (GR1A to GR1H) or channel 1 and 2 compare-match registers (OCR1, OCR2A to OCR2H). DCNT8A to DCNT8H are connected to channel 1 OCR1 or GR1A to GR1H, and DCNT8I to DCNT8P are connected to channel 2 OCR2A to OCR2H or GR2A to GR2H. This enables one-shot pulse output from the external pin (TO8A to TO8P) corresponding to DCNT. The down-count can be forcibly stopped by making a setting in the one-shot pulse terminate register (OTR). On channel 1, down-count start or termination by a GR or OCR compare-match can be selected with the trigger mode register (TRGMDR). Making a setting in the timer start register (TSTR) starts an up-count by a free-running counter (TCNT) in channel 1 or 2. When TCNT matches GR or OCR while connection is enabled by TCNR, the corresponding DSTR is automatically set and DCNT starts counting down. At the same time, 1 is output from the corresponding external pin (TO8A to TO8P). By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. When TCNT1 matches GR or OCR, or TCNT2 matches GR, while channel 8 one-shot pulse termination by a channel 1 or 2 compare-match signal is enabled by OTR, the corresponding DSTR is automatically cleared and DCNT stops counting down. DCNT is cleared to H'0000 at this time, and must be rewritten before the down-count is restarted. DCNT8I to DCNT8P are connected to the reload register (RLDR8), and when the DSTR corresponding to DCNT8I to DCNT8P is set, the DCNT8I to DCNT8P counter loads RLDR8 before starting the down-count. Rev. 3.0, 09/04, page 371 of 1086 An example of the offset one-shot pulse output function and output cutoff function is shown in figure 11.18. Pφ First prescaler 1 Second prescaler 1 Start trigger (OSTRG1A-P) Terminate trigger (OSTRG0A-P) Down-count start trigger (corresponding bit) Down-counter 10A-10P clock One-shot pulse (TOA10-TOP10) Down-counter 10A-10P Synchronized with down-counter clock 0009 0008 0007 0006 0005 0004 0003 0000 One-shot end detection signal One-shot end interrupt (flag) Figure 11.18 Offset One-Shot Pulse Output Function and Output Cutoff Function Operation 11.3.7 Interval Timer Operation The interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B) are connected to bits 6 to 9 and 10 to 13 of the channel 0 free-running counter (TCNT0). The ITVRR registers are 8-bit registers; the upper 4 bits (ITVA) are used for A/D converter activation, and the lower 4 bits (ITVE) are used for interrupt requests. ITVRR1 is connected to A/D converter 2 (AD2), ITVRR2A to A/D converter 0 (AD0), and ITVRR2B to A/D converter 1 (AD1). When the ITVA bit for the desired timing is set, the A/D converter is activated when the corresponding bit of TCNT0 changes to 1. When the ITVE bit for the desired timing is set, an interrupt can be requested when the corresponding bit of TCNT0 changes to 1. At this time, the corresponding bit of the timer status register (TSR0) is set. There are four interrupt sources for the respective ITVRR registers, but there is only one interrupt vector. To suppress interrupts and A/D converter activation, ITVRR bits should be cleared to 0. Rev. 3.0, 09/04, page 372 of 1086 An example of interval timer function operation is shown in figure 11.19. In the example in figure 11.19, TCNT0 is started by setting ITVE to 1 in ITVRR1. Pφ TCNT0 Clock TCNT0 0000003C 0000003D 0000003E 0000003F 00000040 0000007E 0000007F Internal detection signal AD activation trigger In case of bit 6 detection 00000080 00000081 00000082 00000083 00000084 00000085 In case of bit 7 detection Figure 11.19 Interval Timer Function 11.3.8 Twin-Capture Function Channel 0 input capture register ICR0A, channel 1 offset base register 1 (OSBR1), and channel 2 offset base register 2 (OSBR2) can be made to perform input capture in response to the same trigger by means of a setting in timer I/O control register 0 (TIOR0). When TCNT0, TCNT1A, and TCNT2A in channel 0, channel 1, and channel 2 are started by a setting in the timer start register (TSTR), and an edge of TI0A input (a trigger signal) is detected, the TCNT1A value is transferred to OSBR1, and the TCNT2A value to OSBR2. Edge detection is as described in section 11.3.4, Input Capture Function. An example of twin-capture operation is shown in figure 11.20. Pφ TCNT1A Clock TCNT1A 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E Edge detection signal (from channel 0) OSBR1 0003 567A Figure 11.20 Twin-Capture Operation Rev. 3.0, 09/04, page 373 of 1086 11.3.9 PWM Timer Function Channels 6 and 7 can be used unconditionally as PWM timers using external pins (TO6A to TO6D, TO7A to TO7D). In channels 6 and 7, when the corresponding bit is set in the timer start register (TSTR) and the free-running counter (TCNT) is started, the counter counts up until its value matches the corresponding cycle register (CYLR). When TCNT matches CYLR, it is cleared to H'0001 and starts counting up again from that value. At this time, 1 is output from the corresponding external pin. An interrupt request can be sent to the CPU by setting the corresponding bit in the timer interrupt enable register (TIER). If a value has been set in the duty register (DTR), when TCNT matches DTR, 0 is output to the corresponding external pin. If the DTR value is H'0000, the output does not change (0% duty). To set H'0000 to DTR, not write H'0000 directly to DTR but set H'0000 to BFR and then transfer the value to DTR. Writing H'0000 directly to DTR may not give a duty of 0%. A duty of 100% is specified by setting DTR = CYLR. Do not set a value in DTR that will result in the condition DTR > CYLR. Channels 6 and 7 have buffers (BFR); the BFR value is transferred to DTR when TCNT matches CYLR. The duty value written into BFR is reflected in the output value in the cycle following that in which BFR is written to. An example of PWM timer operation is shown in figure 11.21. In the example in figure 11.21, H'0004 is set in channel 6 CYLR6A, and H'0002, H'0000 (0%), H'0004 (100%), and H'0001 in BFR6A. Rev. 3.0, 09/04, page 374 of 1086 Pφ STR TCNT6A Clock TCNT6A 0001 0002 0003 0004 0003 0002 0001 0000 0001 0002 0003 0004 0003 0002 0001 0000 0001 0002 0003 CYLR6A Data = 0000 Write to BFR6A 0004 Data = 0004 Data = 0001 BFR6A 0002 0000 0004 0001 DTR6A 0002 0000 0004 0001 TO6A * PWM output does not change for one cycle after activation Cleared by software Cleared by software Cleared by software TSR6 CMF6A Cycle Cycle Cycle Duty = 0% Cycle Duty = 100% Cycle Note: * Since the retained value is output, the PWM output is not guaranteed for one cycle after activation. Figure 11.21 PWM Timer Operation Channel 6 can be used in complementary PWM mode by making a setting in the PWM mode control register (PMDR). On-duty or off-duty can also be selected with a setting in PMDR. When TCNT6 is started by a setting in TSTR, it starts counting up. When TCNT6 reaches the CYLR6 value, it starts counting down, and on reaching H'000, starts counting up again. The counter status is shown by TSR6. When TCNT6 underflows, an interrupt request can be sent to the CPU by setting the corresponding bit in TIER. When TCNT6 matches the duty register (DTR6) value, the output is inverted. The output prior to the match depends on the PMDR setting. When a value including dead time is set in DTR6, a maximum of 4-phase PWM output is possible. Data transfer from BFR6 to DTR6 is performed when TCNT6 underflows. An example of channel 6 complementary PWM mode operation is shown in figure 11.22. In the example in figure 11.22, H'0004 is set in channel 6 CYLR6A, and H'0002, H'0003, H'0004 (100%), and H'0000 (0%) in BFR6A. Rev. 3.0, 09/04, page 375 of 1086 Pφ STR6A TCNT6A Clock 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 Down Up Up Down Up 0004 Data=0003 Write to BFR6A BFR6A Data=0004 Data=0000 Down Up Down Up Down TCNT6A TSR6 UD6A CYLR6A 0002 0003 0004 0000 DTR6A 0002 * 0003 0004 0000 TO6A PWM output does not change for one cycle after activation TSR6 CMF6A Cycle Cleared by software Cleared by software Cleared by software Cleared by software Cycle Cycle Cycle Duty=100% Cycle Duty=0% Note: * Since the retained value is output, the PWM output is not guaranteed for one cycle after activation. Figure 11.22 Complementary PWM Mode Operation 11.3.10 Channel 3 to 5 PWM Function PWM mode is selected for channels 3 to 5 by setting the corresponding bits to 1 in the timer mode register (TMDR), enabling the channels to operate as PWM timers with the same cycle. In PWM mode, general registers D (GR3D, GR4D, GR5D) are used as cycle registers, and general registers A to C (GR3A to GR3C, GR4A to GR4C, GR5A to GR5C) as duty registers. The external pins (TIO3A to TIO3C, TIO4A to TIO4C, TIO5A to TIO5C) corresponding to the GRs used as duty registers are used as PWM outputs. External pins TIO3D, TIO4D, and TIO5D should not be used as timer outputs. The free-running counter (TCNT) is started by making a setting in the timer start register (TSTR), and when TCNT reaches the cycle register (GR3D, GR4D, GR5D) value, a compare-match is generated and TCNT starts counting up again from H'0000. At the same time, the corresponding bit is set in the timer status register (TSR) and 1 is output from the corresponding external pin. When TCNT reaches the duty register (GR3A to GR3C, GR4A to GR4C, GR5A to GR5C) value, 0 is output to the external pin. The corresponding status flag is not set. When PWM operation is performed by starting the free-running counter from its initial value of H'0000, PWM output is not performed for one cycle. To perform immediate PWM output, the value in the cycle register must be set in the free-running counter before the counter is started. If PWM operation is performed after setting H'FFFF in the cycle register, the cycle register’s compare-match flag and overflow flag will be set simultaneously. Rev. 3.0, 09/04, page 376 of 1086 Note that 0% or 100% duty output is not possible in channel 3 to 5 PWM mode. An example of channel 3 to 5 PWM mode operation is shown in figure 11.23. In the example in figure 11.23, H'0008 is set in GR3D, H'0002 is set in GR3A, GR3B, and GR3C, and channel 3 is activated; then, during operation, H'0000 is set in GR3A, GR3B, and GR3C, and output is performed to external pins TIOA3 to TIOC3. Note that 0% duty output is not possible even though H'0000 is set. Pφ TCNT3 Clock TCNT3 0008 0000 0001 0002 0003 0007 0008 0000 0001 0002 0003 0004 0005 GR3D 0008 0008 Rewritten by software GR3A 3C (pulse width) TIO3A TIO3C 0002 0000 Cleared by software TSR3 Cleared by software Figure 11.23 Channel 3 to 5 PWM Mode Operation Rev. 3.0, 09/04, page 377 of 1086 11.3.11 Event Count Function and Event Cycle Measurement Channel 9 has six 8-bit event counters (ECNT9A to ECNT9F) and corresponding general registers (GR9A to GR9F). Each event counter has an external pin (TI9A to TI9F). Each ECNT9 operates unconditionally as an event counter. When an edge is input from the external pin, ECNT9 is incremented. When ECNT9 matches the value set in GR9, it is cleared, and then counts up when an edge is again input at the external pin. By making the appropriate setting in the interrupt enable register (TIER) beforehand, an interrupt request can be sent to the CPU on compare-match. For ECNT9A to ECNT9D, a trigger can be transmitted to channel 3 when a compare-match occurs. In channel 3, if the channel 9 trigger input is set in the timer I/O control register (TIOR) and the corresponding bit is set to 1 in the timer start register (TSTR), the TCNT3 value is captured in the corresponding general register (GR3A to GR3D) when an ECNT9A to ECNT9D compare-match occurs. This enables the event cycle to be measured. An example of event count operation is shown in figure 11.24. In this example, ECNT9A counts up on both-edge, falling-edge, and rising-edge detection, H'10 is set in GR9A, and a comparematch is generated. An example of event cycle measurement operation is shown in figure 11.25. In this example, GR3A in channel 3 captures TCNT3 in response to a trigger from channel 9. Pφ TI9A Edge detection signal ECNT9A Clock ECNT9A 00 01 02 03 10 00 05 06 GR9A 10 TSR9 CMF9A Capture trigger To channel 3 Rising and falling edges Falling edge Cleared by software Rising edge Figure 11.24 Event Count Operation Rev. 3.0, 09/04, page 378 of 1086 Pφ TCNT3 Clock TCNT3 Compare-match trigger (from channel 9) 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E GR3A 0003 567A TSR3 IMF3A Cleared by software Figure 11.25 Event Cycle Measurement Operation 11.3.12 Channel 10 Functions Inter-Edge Measurement Function and Edge Input Cessation Detection Function:32-bit input capture register 10A (ICR10A) and 32-bit output compare register 10A (OCR10A) in channel 10 unconditionally perform input capture and compare-match operations, respectively. These registers are connected to 32-bit free-running counter TCNT10A. When the corresponding bit is set in the timer start register (TSTR), the entire channel 10 starts operating. ICR10A has an external input pin (TI10), and when an edge is input at this input pin, ICR10A captures the TCNT10A value. At this time, TCNT10A is cleared to H'00000001. The captured value is transferred to the read register (RLD10C) in the multiplied clock generation block. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. This allows inter-edge measurement to be carried out. When TCNT10A reaches the value set in OCR10A, a compare-match interrupt can be requested. In this way it is possible to detect the cessation of edge input beyond the time set in OCR10A. The input edge from TI10 is synchronized internally; the internal signal is AGCK. Noise cancellation is possible for edges input at TI10 using the timer 10H (TCNT10H) input cancellation function by setting the NCE bit in timer control register TCR10. When an edge is input at TI10, TCNT10H starts and input is disabled until it reaches compare-match register NCR10. Edge input operation without noise cancellation is shown in figure 11.26, edge input operation with noise cancellation in figure 11.27, and TCNT10A capture operation and compare-match operation in figure 11.28. Rev. 3.0, 09/04, page 379 of 1086 Pφ TI10 After internal synchronization 1 After internal synchronization 2 AGCK AGCK operation TCNT clock When rising edge is set When falling edge is set When rising and falling edges are set Figure 11.26 Edge Input Operation (Without Noise Cancellation) Pφ TI10 AGCK Noise cancellation period External edge mask period External edge mask period Pφ × 10 (clock) 0 1 0 TCNT10H NCR10 AGCK operation TCNT clock 1 Note: When rising and falling edges are set Figure 11.27 Edge Input Operation (With Noise Cancellation) Rev. 3.0, 09/04, page 380 of 1086 Pφ TSTR1 STR10 TCNT10A TCNT10A 00000001 00000002 00000003 12345677 1234 5678 00000001 55555555 55555556 55555557 AGCK Capture transfer signal TCNT reset signal ICR10A 00000000 12345678 TSR10 IMF10A Cleared by software OCR10A 55555556 TSR10 CMF10A Cleared by software Figure 11.28 TCNT10A Capture Operation and Compare-Match Operation Internally synchronized AGCK is counted by event count 10B (TCNT10B), and when TCNT10B reaches the value set beforehand in compare-match register 10B (OCR10B), a compare-match occurs, and the compare-match trigger signal is transmitted to channel 0. By setting the corresponding bit in TIER, an interrupt request can be sent to the CPU. Figure 11.29 shows TCNT10B compare-match operation. Pφ AGCK TCNT10B Clock 00 01 55 56 TCNT10B OCR10B 55 TSR10 CMF10B Cleared by software Channel 0 trigger Figure 11.29 TCNT10B Compare-Match Operation Rev. 3.0, 09/04, page 381 of 1086 Multiplied Clock Generation Function: The channel 10 16-bit reload counter (TCNT10C, RLD10C) and 16-bit free-running counter 10G (TCNT10G) can be used to multiply the interval between edges input from external pin TI10 by 32, 64, 128, or 256. The value captured in ICR10A above is multiplied by 1/32, 1/64, 1/128, or 1/256 according to the value set in the timer I/O control register (TIOR10), and transferred to the reload buffer (RLD10C). At the same time, the same value is transferred to 16-bit reload counter 10C (TCNT10C) and a down-count operation is started. When this counter reaches H'0001, the value is read automatically from RLD10C and the down-count operation is repeated. When this reload occurs, a multiplied clock signal (AGCK1) is generated. AGCK1 is converted to a corrected clock (AGCKM) by the multiplied clock correction function described in the following section. Channel 10 can also perform compare-match operation by means of the multiplied clock (AGCK1) using general register 10G (GR10G) and 16-bit free-running counter 10G (TCNT10G). TCNT10G is incremented unconditionally by AGCK1. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU when TCNT10G and GR10G match. The timing of this interrupt can be selected with the IREG bit in TIER as either on occurrence of the compare-match or on input of the first TI10 edge after the compare-match. TCNT10C operation is shown in figure 11.30, and TCNT10G compare-match operation in figure 11.31. Rev. 3.0, 09/04, page 382 of 1086 Pφ STR10 AGCK ICR10A 1ck 00000000 00000020 1ck Shifter output 0000 Initial value set by software 0001 RLD10C 0002 0001 RLD10C write enable signal Not loaded when RLDEN = 1 TCNT10C 0001 0002 0001 0002 0001 0002 0001 0001 0001 0001 RLD10C load signal AGCK1 RLDEN RLDEN set to 1 by software RLDEN set to 0 by software Note: In case of multiplication factor of 32 Figure 11.30 TCNT10C Operation Pφ AGCK AGCK1 Write by software TCNT10G 0000 0001 0002 0034 0035 0036 Cleared by AGCK 0000 0001 GR10G 0034 TSR10 CMF10G When IREG = 1 TSR10 CMF10G When IREG = 0 Figure 11.31 TCNT10G Compare-Match Operation Rev. 3.0, 09/04, page 383 of 1086 Multiplied Clock Correction Function: Channel 10’s three 16-bit correction counters (TCNT10D, TCNT10E, TCNT10F) and correction counter clear register (TCCLR10) have a correction function that makes the interval between edges input from TI10 the frequency multiplication value set in TIOR10. When AGCK is input, the value in TCNT10D multiplied by the multiplication factor set in TIOR10 is transferred to TCNT10E. At the same time, TCNT10D is incremented. TCNT10E counts up on AGCK1. For example, TCNT10E loads TCNT10D on AGCK, and counts up again on AGCK1. Using the counter correction select bit (CCS) in TIOR10, it is possible to select whether or not TCNT10E is halted when TCNT10D = TCNT10E. TCNT10F has the peripheral clock (Pφ) as its input and is constantly compared with TCNT10E. When the TCNT10F value is smaller than that in TCNT10E, TCNT10F is incremented and outputs a corrected multiplied clock signal (AGCKM). When the TCNT10F value exceeds the TCNT10E value, no count-up operation is performed. AGCKM is output to the channel 1 to 5 free-running counters (TCNT1 to TCNT5). Channel 10 also has a correction counter clear register (TCCLR10). The correction counters (TCNT10D, TCNT10E, TCNT10F) and channel 1 and 2 free-running counters (TCNT1 and TCNT2) can be cleared when TCNT10F reaches the value set in TCCLR10. TCNT10D operation is shown in figure 11.32, TCNT10E operation in figure 11.33, TCNT10F operation (at startup) in figure 11.34, TCNT10F operation (end of cycle, acceleration, deceleration) in figure 11.35, and TCNT10F operation (end of cycle, steady-state) in figure 11.36. Pφ STR10 AGCK TCNT10D Clock TCNT10D 00 01 02 03 Shifter output 0000 0020 0040 0060 Note: In case of multiplication factor of 32 Figure 11.32 TCNT10D Operation Rev. 3.0, 09/04, page 384 of 1086 Pφ STR10 AGCK AGCK1 Initial value load 0024 00 00 0001 0002 0003 0004 0022 0023 0020 0021 0022 0038 0039 0040 00 41 00 42 00 43 00 44 Corrected value load Corrected value load TCNT10E valid TCNT10E TCNT10D (shift amount) 0000 0020 0040 0060 Note: In case of multiplication factor of 32 Figure 11.33 TCNT10E Operation Pφ STR10 AGCK TCNT10E Clock 0000 TCNT10E 0001 0002 0003 0004 0022 0024 0023 0020 0021 0022 0023 0024 0025 0026 0027 TCNT10F 0080 0001 0002 0003 0004 0022 0023 0024 0025 0026 0027 Same value as cycle register set by software AGCKM TCNT clock operating on AGCKM TCNT1, TCNT2 TCNT1, TCNT2 reset trigger 0000 0001 0002 0003 0022 0023 0024 0025 0026 TCNT10D 00 01 02 Note: Multiplication factor of 32, TCCLR10 = H'0080 Figure 11.34 TCNT10F Operation (At Startup) Rev. 3.0, 09/04, page 385 of 1086 Pφ STR10 AGCK TCNT10E Clock 00 00 TCNT10E 005A 0060 0061 0062 0063 0064 0065 0066 0076 0077 0078 0079 007A 0001 0080 0002 0003 TCNT10F 005A 00 62 0063 0064 0065 0066 0076 0077 0078 0079 007A 00 01 0002 0003 AGCKM TCNT clock operating on AGCKM 00 62 00 66 00 0002 01 0000 TCNT1, TCNT2 TCNT1, TCNT2 reset trigger TCNT10D 03 005A 0063 0064 0065 0076 0077 0078 0079 007A 0003 Cleared to H'00 by software 04 00 01 Note: Multiplication factor of 32, TCCLR10 = H'0080 Figure 11.35 TCNT10F Operation (End of Cycle, Acceleration, Deceleration) Rev. 3.0, 09/04, page 386 of 1086 Pφ STR10 AGCK TCNT10E Clock 00 00 TCNT10E 005A 0060 0061 0062 0063 0064 0065 0066 007E 007F 0080 0081 0082 0001 0002 0003 TCNT10F 005A 00 62 0063 0064 0065 0066 007E 007F 0080 0001 0002 0003 AGCKM TCNT clock operating on AGCKM 00 62 00 66 TCNT1, TCNT2 TCNT1, TCNT2 reset trigger 005A 0063 0064 0065 007E 007F 0000 0001 0002 Set to H'00 by software TCNT10D 03 04 00 01 Note: Multiplication factor of 32, TCCLR10 = H'0080 Figure 11.36 TCNT10F Operation (End of Cycle, Steady-State) Rev. 3.0, 09/04, page 387 of 1086 11.4 Interrupts The ATU has 75 interrupt sources of five kinds: input capture interrupts, compare-match interrupts, overflow interrupts, underflow interrupts, and interval interrupts. 11.4.1 Status Flag Setting Timing IMF (ICF) Setting Timing in Input Capture: When an input capture signal is generated, the IMF bit and ICF bit are set to 1 in the timer status register (TSR), and the TCNT value is simultaneously transferred to the corresponding GR, ICR, and OSBR. The timing in this case is shown in figure 11.37. In the example in figure 11.37, a signal is input from an external pin, and input capture is performed on detection of a rising edge. CK tTICS (input capture input setup time) Input capture input Internal input capture signal TCNT N GR (ICR) Interrupt status flag IMF (ICF) Interrupt request signal IMI (ICI) N Figure 11.37 IMF (ICF) Setting Timing in Input Capture Rev. 3.0, 09/04, page 388 of 1086 IMF (ICF) Setting Timing in Compare-Match: The IMF bit and CMF bit are set to 1 in the timer status register (TSR) by the compare-match signal generated when the general register (GR) output compare register (OCR), or cycle register (CYLR) value matches the timer counter (TCNT) value. The compare-match signal is generated in the last state of the match (when the matched TCNT count value is updated). The timing in this case is shown in figure 11.38. CK TCNT input clock TCNT N N+1 GR (OCR, CYLR) N Compare-match signal Interrupt status flag IMF (CMF) Interrupt request signal IMI (CMI) Figure 11.38 IMF (CMF) Setting Timing in Compare-Match Rev. 3.0, 09/04, page 389 of 1086 OVF Setting Timing in Overflow: When TCNT overflows (from H'FFFF to H'0000, or from H'FFFFFFFF to H'00000000), the OVF bit is set to 1 in the timer status register (TSR). The timing in this case is shown in figure 11.39. CK TCNT input clock TCNT H'FFFF H'0000 Overflow signal Interrupt status flag OVF Interrupt request signal OVI Figure 11.39 OVF Setting Timing in Overflow Rev. 3.0, 09/04, page 390 of 1086 OSF Setting Timing in Underflow: When a down-counter (DCNT) counts down from H'0001 to H'0000 on DCNT input clock input, the OSF bit is set to 1 in the timer status register (TSR) when the next DCNT input clock pulse is input (when underflow occurs). However, when DCNT is H'0000, it remains unchanged at H'0000 no matter how many DCNT input clock pulses are input. When DCNT is cleared by means of the one-shot pulse function, the OSF bit is cleared when the next DCNT input clock is input. The timing in this case is shown in figure 11.40. CK DCNT input clock DCNT H'0001 H'0000 H'0000 Underflow signal Interrupt status flag OSF Interrupt request signal OSI Figure 11.40 OSF Setting Timing in Underflow Rev. 3.0, 09/04, page 391 of 1086 Timing of IIF Setting by Interval Timer: When 1 is generated by ANDing the rise of bit 10–13 in free-running counter TCNT0L with bit ITVE0–ITVE3 in the interval interrupt request register (ITVRR), the IIF bit is set to 1 in the timer status register (TSR). The timing in this case is shown in figure 11.41. TCNT0 value N in the figure is the counter value when TCNT0L bit 6–13 changes to 1. (For example, N = H'00000400 in the case of bit 10, H'00000800 in the case of bit 11, etc.) CK TCNT input clock TCNT0 N–1 N Internal interval signal Interrupt status flag IIF Interrupt request signal Figure 11.41 Timing of IIF Setting Timing by Interval Timer Rev. 3.0, 09/04, page 392 of 1086 11.4.2 Status Flag Clearing Clearing by CPU Program: The interrupt status flag is cleared when the CPU writes 0 to the flag after reading it while set to 1. The procedure and timing in this case are shown in figure 11.42. TSR write cycle T1 T2 CK Read 1 from TSR Address TSR address Start Write 0 to TSR Internal write signal Interrupt status flag IMF, ICF, CMF, OVF, OSF, IIF Interrupt request signal Interrupt status flag cleared Figure 11.42 Procedure and Timing for Clearing by CPU Program Rev. 3.0, 09/04, page 393 of 1086 Clearing by DMAC: The interrupt status flag (ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D) is cleared automatically during data transfer when the DMAC is activated by input capture or compare-match. The procedure and timing in this case are shown in figure 11.43. CK Start Clear request signal from DMAC Interrupt status flag clear signal Interrupt status flag ICF0B, CMF6 Interrupt request signal Activate DMAC Interrupt status flag cleared during data transfer Figure 11.43 Procedure and Timing for Clearing by DMAC Rev. 3.0, 09/04, page 394 of 1086 11.5 11.5.1 CPU Interface Registers Requiring 32-Bit Access Free-running counters 0 and 10A (TCNT0, TCNT10A), input capture registers 0A to 0D and 10A (ICR0A to ICR0D, ICR10A), and output compare register 10A (OCR10A) are 32-bit registers. As these registers are connected to the CPU via an internal 16-bit data bus, a read or write (read only, in the case of ICR0A to ICR0D and ICR10A) is automatically divided into two 16-bit accesses. Figure 11.44 shows a read from TCNT0, and figure 11.45 a write to TCNT0. When reading TCNT0, in the first read the TCNT0H (upper 16-bit) value is output to the internal data bus, and at the same time, the TCNT0L (lower 16-bit) value is output to an internal buffer register. Then, in the second read, the TCNT0L (lower 16-bit) value held in the internal buffer register is output to the internal data bus. When writing to TCNT0, in the first write the upper 16 bits are output to an internal buffer register. Then, in the second write, the lower 16 bits are output to TCNT0L, and at the same time, the upper 16 bits held in the internal buffer register are output to TCNT0H to complete the write. The above method performs simultaneous reading and simultaneous writing of 32-bit data, preventing contention with an up-count. 1st read operation Bus interface Module data bus H TCNT0H Internal buffer register L TCNT0L Module data bus Internal data bus H CPU Internal data bus L CPU 2nd read operation Bus interface Module data bus L Internal buffer register TCNT0H TCNT0L Figure 11.44 Read from TCNT0 Rev. 3.0, 09/04, page 395 of 1086 1st write operation Internal data bus H CPU Bus interface H Module data bus Internal buffer register TCNT0H TCNT0L Internal data bus L CPU 2nd write operation Bus interface L Module data bus Internal buffer H register TCNT0H TCNT0L Module data bus Figure 11.45 Write to TCNT0 Rev. 3.0, 09/04, page 396 of 1086 11.5.2 Registers Permitting 8-Bit, 16-Bit, or 32-Bit Access Timer registers 1, 2, and 3 (TSTR1, TSTR2, TSTR3) are 8-bit registers. As these registers are connected to the CPU via an internal 16-bit data bus, a simultaneous 32-bit read or write access to TSTR1, TSTR2, and TSTR3 is automatically divided into two 16-bit accesses. Figure 11.46 shows a read from TSTR, and figure 11.47 a write to TSTR. When reading TSTR, in the first read the TSTR1 and TSTR2 (upper 16-bit) value is output to the internal data bus. Then, in the second read, the TSTR3 (lower 16-bit) value is output to the internal data bus. When writing to TSTR, in the first write the upper 16 bits are written to TSTR1 and TSTR2. Then, in the second write, the lower 16 bits are written to TSTR3. Note that, with the above method, in a 32-bit write the write timing is not the same for TSTR1/TSTR2 and TSTR3. For information on 8-bit and 16-bit access, see section 11.5.4, 8-Bit or 16-Bit Accessible Registers. 1st read operation Bus interface Module data bus H TSTR2 TSTR1 TSTR3 Internal data bus H CPU Internal data bus L CPU 2nd read operation Bus interface Module data bus L TSTR2 TSTR1 TSTR3 Figure 11.46 Read from TSTR1, TSTR2, and TSTR3 Rev. 3.0, 09/04, page 397 of 1086 1st write operation Internal data bus H CPU Bus interface H Module data bus TSTR2 TSTR1 TSTR3 Internal data bus L CPU 2nd write operation Bus interface L TSTR2 TSTR1 TSTR3 Module data bus Figure 11.47 Write to TSTR1, TSTR2 and TSTR3 11.5.3 Registers Requiring 16-Bit Access The free-running counters (TCNT; but excluding TCNT0, TCNT10A, TCNT10B, TCNT10D, and TCNT10H), the general registers (GR; but excluding GR9A to GR9D), down-counters (DCNT), offset base register (OSBR), cycle registers (CYLR), buffer registers (BFR), duty registers (DTR), timer connection register (TCNR), one-shot pulse terminate register (OTR), down-count start register (DSTR), output compare registers (OCR: but excluding OCR10B), reload registers (RLDR8, RLD10C), correction counter clear register (TCCLR10), timer interrupt enable register (TIER), and timer status register (TSR) are 16-bit registers. These registers are connected to the CPU via an internal 16-bit data bus, and can be read or written (read only, in the case of OSBR) a word at a time. Figure 11.48 shows the operation when performing a word read or write access to TCNT1A. Internal data bus CPU Bus interface Module data bus TCNT1A Figure 11.48 TCNT1A Read/Write Operation Rev. 3.0, 09/04, page 398 of 1086 11.5.4 8-Bit or 16-Bit Accessible Registers The timer control registers (TCR1A, TCR1B, TCR2A, TCR2B, TCR6A, TCR6B, TCR7A, TCR7B), timer I/O control registers (TIOR1A to TIOR1D, TIOR2A to TIOR2D, TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B), and the timer start register (TSTR1, TSTR2, TSTR3) are 8-bit registers. These registers are connected to the CPU with the upper 8 bits or lower 8 bits of the internal 16-bit data bus, and can be read or written a byte at a time. In addition, a pair of 8-bit registers for which only the least significant bit of the address is different, such as timer I/O control register 1A (TIOR1A) and timer I/O control register 1B (TIOR1B), can be read or written in combination a word at a time. Figures 11.49 and 11.50 show the operation when performing individual byte read or write accesses to TIOR1A and TIOR1B. Figure 11.51 shows the operation when performing a word read or write access to TIOR1A and TIOR1B simultaneously. Internal data bus CPU Only upper 8 bits used Module data bus Only upper 8 bits used Bus interface TIOR1B TIOR1A Figure 11.49 Byte Read/Write Access to TIOR1B Internal data bus CPU Only lower 8 bits used Module data bus Only lower 8 bits used Bus interface TIOR1B TIOR1A Figure 11.50 Byte Read/Write Access to TIOR1A Internal data bus CPU Module data bus Bus interface TIOR1B TIOR1A Figure 11.51 Word Read/Write Access to TIOR1A and TIOR1B Rev. 3.0, 09/04, page 399 of 1086 11.5.5 Registers Requiring 8-Bit Access The timer mode register (TMDR), prescaler register (PSCR), timer I/O control registers (TIOR0, TIOR10, TIOR11), trigger mode register (TRGMDR), interval interrupt request register (ITVRR), timer control registers (TCR3, TCR4, TCR5, TCR8, TCR9A to TCR9C, TCR10, TCR11), PWM mode register (PMDR), reload enable register (RLDENR), free-running counters (TCNT10B, TCNT10D, TCNT10H), event counter (ECNT), general registers (GR9A to GR9F), output compare register (OCR10B), and noise canceler register (NCR) are 8-bit registers. These registers are connected to the CPU with the upper 8 bits of the internal 16-bit data bus, and can be read or written a byte at a time. Figure 11.52 shows the operation when performing individual byte read or write accesses to ITVRR1. Internal data bus CPU Only upper 8 bits used Module data bus Only upper 8 bits used Bus interface ITVRR1 Figure 11.52 Byte Read/Write Access to ITVRR1 11.6 Sample Setup Procedures Sample setup procedures for activating the various ATU-II functions are shown below. Sample Setup Procedure for Input Capture: An example of the setup procedure for input capture is shown in figure 11.53. Rev. 3.0, 09/04, page 400 of 1086 Start Select counter clock 1 Set port-ATU-II connection 2 Set input waveform edge detection 3 1. Select the first-stage counter clock ' in prescaler register (PSCR) and the second-stage counter clock " with the CKSEL bit in the timer control register (TCR). When selecting an external clock, also select the external clock edge type with the CKEG bit in TCR. 2. Set the port control register, corresponding to the port for signal input as the input capture trigger, to ATU input capture input. 3. Select rising edge, falling edge, or both edges as the input capture signal input edge(s) with the timer I/O control register (TIOR). If necessary, a timer interrupt request can be sent to the CPU on input capture by making the appropriate setting in the interrupt enable register (TIER). In channel 0, setting the DMAC allows DMAC activation to be performed. 4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running counter (TCNT) for the relevant channel. Note: When input capture occurs, the counter value is always captured, irrespective of free-running counter (TCNT) activation. Start counter 4 Input capture operation Figure 11.53 Sample Setup Procedure for Input Capture Rev. 3.0, 09/04, page 401 of 1086 Sample Setup Procedure for Waveform Output by Output Compare-Match: An example of the setup procedure for waveform output by output compare-match is shown in figure 11.54. Start Select counter clock 1 Set port-ATU-II connection 2 Select waveform output mode 3 Set output timing 4 Start counter 5 1. Select the first-stage counter clock ' in prescaler register (PSCR), and the second-stage counter clock " with the CKSEL bit in the timer control register (TCR). When selecting an external clock, also select the external clock edge type with the CKEG bit in TCR. 2. Set the port control register corresponding to the waveform output port to ATU output compare-match output. Also set the corresponding bit to 1 in the port IO register to specify the output attribute for the port. 3. Select 0, 1, or toggle output for output compare-match output with the timer I/O control register (TIOR). If necessary, a timer interrupt request can be sent to the CPU on output compare-match by making the appropriate setting in the interrupt enable register (TIER). 4. Set the timing for compare-match generation in the ATU general register (GR) corresponding to the port set in (2). 5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running counter (TCNT). Waveform output is performed from the relevant port when the TCNT value and GR value match. Waveform output Figure 11.54 Sample Setup Procedure for Waveform Output by Output Compare-Match Rev. 3.0, 09/04, page 402 of 1086 Sample Setup Procedure for Channel 0 Input Capture Triggered by Channel 10 CompareMatch: An example of the setup procedure for compare-match signal transmission is shown in figure 11.55. Start Set compare-match 1 Set TCR10 2 1. Set the timing for compare-match generation in the channel 10 output compare register (OCR10B). 2. Set the TRG0DEN bit to 1 in the channel 10 timer control register (TCR10). 3. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 10 free-running counter (TCNT10B). On compare-match between TCNT10 and OCR10B, the compare-match signal is transmitted to channel 0 as the channel 0 ICR0D input capture signal. Start counter 3 Signal transmission Figure 11.55 Sample Setup Procedure for Compare-Match Signal Transmission Rev. 3.0, 09/04, page 403 of 1086 Sample Setup Procedure for One-Shot pulse Output: An example of the setup procedure for one-shot pulse output is shown in figure 11.56. Start Select counter clock 1 Set port-ATU-II connection 2 Set pulse width 3 Start down-count 4 1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1), and select the second-stage counter clock " with the CKSEL bit in timer control register8 TCR8. 2. Set port K control registers H and L (PKCRH, PKCRL) corresponding to the waveform output port to ATU one-shot pulse output. Also set the corresponding bit to 1 in the port K IO register (PKIOR) to specify the output attribute. 3. Set the one-shot pulse width in the down-counter (DCNT) corresponding to the port set in (2). If necessary, a timer interrupt request can be sent to the CPU when the downcounter underflows by making the appropriate setting in the interrupt enable register (TIER8). 4. Set the corresponding bit (DST8A to DST8P) to 1 in the down-count start register (DSTR) to start the down-counter (DCNT). One-shot pulse output Figure 11.56 Sample Setup Procedure for One-Shot Pulse Output Rev. 3.0, 09/04, page 404 of 1086 Sample Setup Procedure for Offset One-Shot Pulse Output/Cutoff Operation: An example of the setup procedure for offset one-shot pulse output is shown in figure 11.57. Start 1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1), and select the second-stage counter clock " with the CKSEL bit in the timer control register (TCR1, TCR2, TCR8). 2. Set port K control registers H and L (PKCRH, PKCRL) corresponding to the waveform output port to ATU one-shot pulse output. Also set the corresponding bit to 1 in the port K IO register (PKIOR) to specify the output attribute 3. Set the one-shot pulse width in the down-counter (DCNT) corresponding to the port set in (2). If necessary, a timer interrupt request can be sent to the CPU when the downcounter underflows by making the appropriate setting in the interrupt enable register (TIER8). 4. Set the offset width in the channel 1 or 2 general register (GR1A—GR1H, GR2A—GR2H) connected to the downcounter (DCNT) corresponding to the port set in (2), and in the output compare register (OCR1, OCR2A—OCR2H). Set the timer I/O control register (TIOR1A—TIOR1D, TIOR2A—TIOR2D) to the compare-match enabled state. 5. Set the start/terminate trigger by means of the trigger mode register (TRGMDR), timer connection register (TCNR), and one-shot pulse terminate register (OTR), so that it corresponds to the port set in (2). 6. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 1 or 2 free-running counter (TCNT1, TCNT2). When the TCNT value and GR value or OCR value match, the corresponding DCNT starts counting down or is forcibly cleared, and one-shot pulse output is performed. Select counter clock 1 Set port-ATU-II connection 2 Set pulse width 3 Set offset width 4 Set offset operation 5 Start count 6 Offset one-shot pulse output Figure 11.57 Sample Setup Procedure for Offset One-Shot Pulse Output Rev. 3.0, 09/04, page 405 of 1086 Sample Setup Procedure for Interval Timer Operation: An example of the setup procedure for interval timer operation is shown in figure 11.58. Start Select counter clock Set interval Start counter 1 1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1). 2. Set the ITVE bit to be used in the interval interrupt request register (ITVRR) to 1. An interrupt request can be sent to the CPU when the corresponding bit changes to 1 in the 2 channel 0 free-running counter (TCNT0). To start A/D converter sampling, set the ITVA bit to be used in ITVRR to 1. 3. Set bit 0 to 1 in the timer start register (TSTR) to start 3 TCNT0. Interrupt request to CPU or start of A/D sampling Figure 11.58 Sample Setup Procedure for Interval Timer Operation Rev. 3.0, 09/04, page 406 of 1086 Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5 ): An example of the setup procedure for PWM timer operation (channels 3 to 5 ) is shown in figure 11.59. Start Select counter clock 1 Set port-ATU-II connection 2 Set PWM timer 3 Set GR 4 Start count 5 1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1), and select the second-stage counter clock " with the CKSEL bit in the timer control register (TCR). When selecting an external clock, at the same time select the external clock edge type with the CKEG bit in TCR. 2. Set the port control registers (PxCRH, PxCRL) corresponding to the waveform output port to ATU output compare-match output. Also set the corresponding bit to 1 in the port IO register (PxIOR) to specify the output attribute. 3. Set bit T3PWM–T5PWM in the timer mode register (TMDR) to PWM mode. When PWM mode is set, the timer operates in PWM mode irrespective of the timer I/O control register (TIOR) contents, and general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D) can be written to. 4. The GR3A–GR3C, GR4A–GR4C, and GR5A–GR5C ATU general registers are used as duty registers (DTR), and the GR3D, GR4D, and GR5D ATU general registers as cycle registers (CYLR). Set the PWM waveform output 0 output timing in DTR, and the PWM waveform output 1 output timing in CYLR. Also, if necessary, interrupt requests can be sent to the CPU at the 0/1 output timing by making a setting in the timer interrupt enable register (TIER). 5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running counter (TCNT) for the relevant channel. PWM waveform output Figure 11.59 Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5) Rev. 3.0, 09/04, page 407 of 1086 Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7): An example of the setup procedure for PWM timer operation (channels 6 and 7) is shown in figure 11.60. 1. Set the first-stage counter clock ' in prescaler register 2 and 3 (PSCR2, PSCR3), and select the second-stage counter clock " with the CKSEL bit in the timer control register (TCR6A, TCR6B, TCR7A, TCR7B). 2. Set the port B control register L (PBCRL) corresponding to the waveform output port to ATU PWM output. Also set the corresponding bit to 1 in the port B IO register (PBIOR) to specify the output attribute. 3. Set PWM waveform output 1 output timing in the cycle register (CYLR6A to CYLR6D, CYLR7A to CYLR7D), and set the PWM waveform output 0 output timing in the buffer register (BFR6A to BFR6D, BFR7A to BFR7D) and duty register (DTR6A to DTR6D, DTR7A to DTR7D). If necessary, an interrupt request can be sent to the CPU on a compare-match between the CYLR value and the freerunning counter (TCNT) value by making the appropriate setting in the interrupt enable register (TIERE). In addition, setting the DMAC allows DMAC activation to be performed. 4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the TCNT counter for the relevant channel. Start Select counter clock 1 Set port-ATU-II connection 2 Set CYLR, BFR, DTR 3 Start count 4 PWM waveform output Notes: 1. Do not make a setting in DTR after the counter is started. Use BFR to make a DTR setting. 2. 0% duty is specified by setting H'0000 in the duty register (DTR), and 100% duty is specified by setting buffer register (BFR) = cycle register (CYLR). Do not set BFR > CYLR. Figure 11.60 Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7) Rev. 3.0, 09/04, page 408 of 1086 Sample Setup Procedure for Event Counter Operation: An example of the setup procedure for event counter operation is shown in figure 11.61. Start Set number of events 1 Set port-ATU-II connection 2 1. Set the number of events to be counted in a general register (GR9A to GR9D). Also, if necessary, an interrupt request can be sent to the CPU upon compare-match by making a setting in the timer interrupt enable register (TIER). 2. Set the port control register, corresponding to the port for signal input to the event counter, to ATU event counter input. 3. Select the event counter count edge with the EGSEL bits in the channel 9 timer control register (TCR9A to TCR9C). 4. Input a signal to the event counter input pin. Select counter clock 3 Start event input 4 Event counter operation Figure 11.61 Sample Setup Procedure for Event Counter Operation Rev. 3.0, 09/04, page 409 of 1086 Sample Setup Procedure for Channel 3 Input Capture Triggered by Channel 9 CompareMatch: An example of the setup procedure for compare-match signal transmission is shown in figure 11.62. Start Set port-ATU-II commection 1 Set input capture 2 Select compare-match 3 Start counter 4 1. Set the port control register, corresponding to the port for signal input to the event counter, to ATU event counter input. 2. Set the channel 3 timer I/O control register (TIOR3A, TIOR3B), and select the input capture disable setting for the general registers (GR3A to GR3D). Input from pins TIO3A to TIO3D is masked. 3. Select the event counter count edge with the EGSEL bits in the channel 9 timer control register (TCR9A, TCR9B), and set the TRG3xEN bit to 1. Set the timing for capture in the general register (GR9A to GR9D). 4. Set bit STR3 to 1 in the timer start register (TSTR) to start the channel 3 free-running counter (TCNT3). 5. Input a signal to the event counter input pin. Note: An interrupt request can be sent to the CPU upon channel 9 compare-match by making a setting in the timer interrupt enable register (TIER), but an interrupt request cannot be sent to the CPU upon channel 3 input capture. Start event input 5 Input capture operation Figure 11.62 Sample Setup Procedure for Compare-Match Signal Transmission Rev. 3.0, 09/04, page 410 of 1086 Sample Setup Procedure for Channel 10 Missing-Teeth Detection: An example of the setup procedure for missing-teeth detection is shown in figure 11.63. 1. Set port B control register H (PBCRH) or port L control register L (PLCRL), corresponding to the port for input of the external signal (missing-teeth signal), to ATU edge input (TI10). 2. Set 1st-stage counter clock ' in prescaler register 4 (PSCR4). Set the external input (TI10) cycle multiplication factor with the PIM bits in timer I/O control register 10 (TIOR10), and enable reload register 10C (RLD10C) updating with the RLDEN bit. Select the external input edge type with the CKEG bits in timer control register 10 (TCR10). 3. Set general register 10G (GR10G) to the compare-match function with bit IO10G in TIOR10. Also, an interrupt request can be sent to the CPU upon compare-match by making a setting in interrupt enable register 10 (TIER10). 4. Set the timing for compare-match generation in GR10G according to the multiplication factor and number of missingteeths in the missing-teeth interval set in (1). 5. Set the corresponding bit to 1 in timer start register 1 (TSTR1) to start the channel 10 count. A compare-match occurs when the values in free-running counter 10G (TCNT10G) and GR10G match. Note: The TCNT10G counter clock is generated according to the external input edge interval and multiplication factor selected in (1), and the counter is cleared to H'0000 by an external input edge. Start Set port-ATU-II connection 1 Select counter clock 2 Set compare-match 3 Set missing-teeth timing 4 Start counter 5 Interrupt requests to CPU Figure 11.63 Sample Setup Procedure for Missing-Teeth Detection Rev. 3.0, 09/04, page 411 of 1086 11.7 Usage Notes Note that the kinds of operation and contention described below occur during ATU operation. Contention between TCNT Write and Clearing by Compare-Match: With channel 3 to 7 freerunning counters (TCNT3 to TCNT5, TCNT6A to TCNT6D, TCNT7A to TCNT7D), if a compare-match occurs in the T2 state of a CPU write cycle when counter clearing by comparematch has been set, or when PWM mode is used, the write to TCNT has priority and TCNT clearing is not performed. The compare-match remains valid, and writing of 1 to the interrupt status flag and waveform output to an external destination are performed in the same way as for a normal compare-match. The timing in this case is shown in figure 11.64. T1 P Address TCNT address T2 Internal write signal Compare-match signal Counter clear signal TCNT CPU write value Interrupt status flag External output signal (1 output) Figure 11.64 Contention between TCNT Write and Clear Rev. 3.0, 09/04, page 412 of 1086 Contention between TCNT Write and Increment: If a write to a channel 0 to 11 free-running counter (TCNT0, TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3 to TCNT5, TCNT6A to TCNT6D, TCNT7A to TCNT7D, TCNT10A to TCNT10H, TCNT11), down-counter (DCNT8A to DCNT8P), or event counter 9 (ECNT9A to ECNT9F) is performed while that counter is counting up or down, the write to the counter has priority and the counter is not incremented or decremented. The timing in this case is shown in figure 11.65. In this example, the CPU writes H'5555 at the point at which TCNT is to be incremented from H'1001 to H'1002. T1 P T2 TCNT input clock Address TCNT address Internal write signal TCNT 1001 5555 (CPU write value) 5556 Figure 11.65 Contention between TCNT Write and Increment Rev. 3.0, 09/04, page 413 of 1086 Contention between TCNT Write and Counter Clearing by Overflow: With channel 0 to 5 and 11 free-running counters (TCNT0, TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3 to TCNT5, TCNT11), if overflow occurs in the T2 state of a CPU write cycle, the write to TCNT has priority and TCNT is not cleared. Writing of 1 to the interrupt status flag (OVF) due to the overflow is performed in the same way as for normal overflow. The timing in this case is shown in figure 11.66. In this example, H'5555 is written at the point at which TCNT overflows. T1 P T2 TCNT input clock Address TCNT address Internal write signal Overflow signal TCNT FFFF 5555 (CPU write value) 5556 Interrupt status flag (OVF) Figure 11.66 Contention between TCNT Write and Overflow Rev. 3.0, 09/04, page 414 of 1086 Contention between Interrupt Status Flag Setting by Interrupt Generation and Clearing: If an event such as input capture/compare-match or overflow/underflow occurs in the T2 state of an interrupt status flag 0 write cycle by the CPU, clearing by the 0 write has priority and the interrupt status flag is cleared. The timing in this case is shown in figure 11.67. TSR write cycle T1 T2 P Address TSR address 0 written to TSR N N+1 Internal write signal TCNT GR N Compare-match signal Interrupt status flag IMF Figure 11.67 Contention between Interrupt Status Flag Setting by Compare-Match and Clearing Rev. 3.0, 09/04, page 415 of 1086 Contention between DTR Write and BFR Value transfer by Buffer Function: In channels 6 and 7, if there is contention between transfer of the buffer register (BFR) value to the corresponding duty register (DTR) due to a cycle register (CYLR) compare-match, and a write to DTR by the CPU, the CPU write value is written to DTR. Figure 11.68 shows an example in which contention arises when the BFR value is H'AAAA and the value to be written to DTR is H'5555. P Address Internal write signal DTR address H'5555 written to DTR Compare-match signal BFR H'AAAA DTR H'5555 Figure 11.68 Contention between DTR Write and BFR Value Transfer by Buffer Function Rev. 3.0, 09/04, page 416 of 1086 Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input Capture/Compare-Match: If a clear request signal is generated by the DMAC when the interrupt status flag (ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D) is set by input capture (ICR0A to ICR0D) or compare-match (CYLR6A to CYLR6D, CYLR7A to CYLR7D), clearing by the DMAC has priority and the interrupt status flag is not set. The timing in this case is shown in figure 11.69. P DMAC clear request signal Interrupt status flag clear signal Input capture/ compare-match signal Interrupt status flag ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D Figure 11.69 Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input Capture/Compare-Match Rev. 3.0, 09/04, page 417 of 1086 Halting of a Down-Counter by the CPU: A down-counter (DCNT) can be halted by writing H'0000 to it. The CPU cannot write 0 directly to the down-count start register (DSTR); instead, by setting DCNT to H'0000, the corresponding DSTR bit is cleared to 0 and the count is stopped. However, the OSF bit in the timer status register (TSR) is set when DCNT underflows. Note that when H'0000 is written to DCNT, the corresponding DSTR bit is not cleared to 0 immediately; it is cleared to 0, and the down-counter is stopped, when underflow occurs following the H'0000 write. The timing in this case is shown in figure 11.70. P DCNT input clock DCNT N H'0000 written to DCNT H'0000 H'0000 Internal write signal DSTR TSR Port output (one-shot pulse) Figure 11.70 Halting of a Down-Counter by the CPU Rev. 3.0, 09/04, page 418 of 1086 Input Capture Operation when Free-Running Counter is Halted: In channels 0 to 5, channel 10, or channel 11, if input capture setting is performed and a trigger signal is input from the input pin, the TCNT value will be transferred to the corresponding general register (GR) or input capture register (ICR) irrespective of whether the free-running counter (TCNT) is running or halted, and the IMF or ICF bit will be set in the timer status register (TSR). The timing in this case is shown in figure 11.71. P Timer status register TSR Internal input capture signal TCNT N GR (ICR) Interrupt status flag IMF (ICF) N Figure 11.71 Input Capture Operation before Free-Running Counter is Started Rev. 3.0, 09/04, page 419 of 1086 Contention between DCNT Write and Counter Clearing by Underflow: If an underflow occurs in the T2 state of the channel 8 down-counter (DCNT8A to DCNT8P) write cycle by the CPU and the DCNT is stopped, the retention of the H’0000 value has priority and the write to the DCNT by the CPU is not performed. Setting the status flag (OSF) to 1 at the underflow timing is performed in the same way as for a normal underflow. The timing in this case is shown in figure 11.72. In this example, a write of H'5555 to DCNT is attempted at the same time as DCNT underflows. Note: In the SH7055, a write to DCNT from the CPU is not attempted, but retention of H’0000 takes precedence. Note that its operation is different. T1 Pφ T2 DCNT input clock Address DCNT address Write data 5555 Internal write signal Underflow signal H'5555 is written because DCNT write is given priority DCNT Interrupt status flag (OSF) 0001 0000 5555 Figure 11.72 Contention between DCNT Write and Underflow Rev. 3.0, 09/04, page 420 of 1086 Contention between DSTR Bit Setting by CPU and Clearing by Underflow: If underflow occurs in the T2 state of a down-counter start register (DSTR) “1” write cycle by the CPU, clearing to 0 by the underflow has priority, and the corresponding bit of DSTR is not set to 1. The timing in this case is shown in figure 11.73. STR write cycle T1 T2 P Address DSTR address 1 written to DSTR Internal write signal DCNT 0001 0000 0000 Underflow signal Down-count start register Figure 11.73 Contention between DSTR Bit Setting by CPU and Clearing by Underflow Rev. 3.0, 09/04, page 421 of 1086 Timing of Prescaler Register (PSCR), Timer Control Register (TCR), and Timer Mode Register (TMDR) Setting: Settings in the prescaler register (PSCR), timer control register (TCR), and timer mode register (TMDR) should be made before the counter is started. Operation is not guaranteed if these registers are modified while the counter is running. Also, the counter must not be started until Pø has been input 32 times after setting PSCR1 to PSCR4. Interrupt Status Flag Clearing Procedure: When an interrupt status flag is cleared to 0 by the CPU, it must first be read before 0 is written to it. Correct operation cannot be guaranteed if 0 is written without first reading the flag. Setting H'0000 in Free-Running Counters 6A to 6D, 7A to 7D (TCNT6A to TCNT6D, TCNT7A to TCNT7D): If H'0000 is written to a channel 6 and 7 free-running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D), and the counter is started, the interval up to the first compare-match with the cycle register (CYLR) and duty register (DTR) will be a maximum of one TCNT input clock cycle longer than the set value. With subsequent compare-matches, the correct waveform will be output for the CYLR and DTR values. Register Values when a Free-Running Counter (TCNT) Halts: If the timer start register (TSTR) value is set to 0 during counter operation, only incrementing of the corresponding freerunning counter (TCNT) is stopped, and neither the free-running counter (TCNT) nor any other ATU registers are initialized. The external output value at the time TSTR is cleared to 0 will continue to be output. TCNT0 Writing and Interval Timer Operation: If the CPU program writes 1 to a bit in freerunning counter 0 (TCNT0) corresponding to a bit set to 1 in the interval interrupt request register (ITVRR) when that TCNT0 bit is 0, TCNT0 bit 6, 7, 8, 9, 10, 11, 12, or 13 will be detected as having changed from 0 to 1, and an interrupt request will be sent to INTC and A/D sampling will be started. While the count is halted with the STR0 bit cleared to 0 in timer start register 1 (TSTR1), the bit transition from 0 to 1 will still be detected. Automatic TSR Clearing by DMAC Activation by the ATU: Automatic clearing of TSR is performed after completion of the transfer when the DMAC is in burst mode, and each time the DMAC returns the bus in cycle steal mode. Interrupt Status Flag Setting/Resetting: With TSR, a 0 write to a bit is possible even if overlapping events occur for the same bit before writing 0 after reading 1 to clear that bit. (The duplicate events are not accepted.) Rev. 3.0, 09/04, page 422 of 1086 External Output Value in Software Standby Mode: In software standby mode, the ATU register and external output values are cleared to 0. However, while the channel 1, 2, and 11 TIO1A to TIO1H, TIO2A to TIO2H, TIO11A, and TIO11B external output values are cleared to 0 immediately after software standby mode is exited, other external output values and all registers are cleared to 0 immediately after a transition to software standby mode. Also, when pin output is inverted by the pin function controller's port B invert register (PBIR) or port K invert register (PKIR), the corresponding pins are set to 1. Software standby mode CK TIO1A to 1H, TIO2A to 2H, TIO11A, 11B Other external outputs Figure 11.74 External Output Value Transition Points in Relation to Software Standby Mode Contention between TCNT Clearing from Channel 10 and TCNT Overflow: When a channel 1 or 2 free-running counter (TCNT1A, TCNT1B, TCNT2A, TCNT2B) overflows, it is cleared to H'0000. If a clear signal from the channel 10 correction counter clear register (TCCLR) is input at the same time, setting 1 to the overflow interrupt status flag (OVF) due to the overflow is still performed in the same way as for a normal overflow. Contention between Channel 10 Reload Register Transfer Timing and Write: If there is contention between a multiplied-output transfer from the input capture register (ICR10A) to the channel 10 reload register (RLDR10C), and the timing of a CPU write to that register, the CPU write has priority and the multiplied output is ignored. Contention between Channel 10 Reload Timing and Write to TCNT10C: If there is contention between a multiplied-output transfer from the input capture register (ICR10A) to the channel 10 reload register (RLDR10C), and a CPU write to the reload counter (TCNT10C), the CPU write has priority and the multiplied output is ignored. Rev. 3.0, 09/04, page 423 of 1086 ATU Pin Setting: Since input capture or count operation may be occurred when a port is set to the ATU pin function, the following points must be noted. When using a port for input capture input, the corresponding TIOR register must be in the input capture disabled state when the port is set. Regarding channel 10 TI10 input, TCR10 must be in the TI10 input disabled state when the port is set. When using a port for external clock input, the STR bit for the corresponding channel must be in the count operation disabled state when the port is set. When using a port for event input, the corresponding TCR register must be in the count operation disabled state when the port is set. Regarding TCLKB and TI10 input, although input is assigned to a number of pins, when using TCLKB and TI10 input, only one pin should be enabled. Writing to ROM Area Immediately after ATU Register Write: If a write cycle for a ROM address for which address bit 11 = 0 and address bit 12 = 1 (H'00001000 to H'000017FF, H'00003000 to H'000037FF, H'00005000 to H'000057FF, ..., H'0007F000 to H'0007F7FF, ..., H'000FF000 to H'000FF7FF) occurs immediately after an ATU register write cycle, the value, or part of the value, written to ROM will be written to the ATU register. The following measures should be taken to prevent this. • Do not perform a CPU write to a ROM address immediately after an ATU register write cycle. For example, an instruction arrangement in which an MOV instruction that writes to the ATU is located at an even-word address (4n address), and is immediately followed by an MOV instruction that writes to a ROM area, will meet the bug conditions. • Do not perform an AUD write to any of the above ROM addresses immediately after an ATU register write cycle. For example, in the case of a write to overlap RAM when using the RAM emulation function, the write should be performed to the on-chip RAM area address, not the overlapping ROM area address. • Do not perform a DMAC write to an ATU register when a ROM address write operation occurs. Rev. 3.0, 09/04, page 424 of 1086 11.8 ATU-II Registers and Pins Table 11.4 ATU-II Registers and Pins Channel Register 1 Name* Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel 0 1 2 3 4 5 6 7 8 9 10 TSTR1 PSCR1 TSTR1 TSTR1 TSTR1 TSTR1 TSTR2 TSTR2 – – TSTR1 PSCR4 Channel 11 TSTR3 PSCR1 TSTR (3) TSTR1 PSCR (4) PSCR1 PSCR1 PSCR1 PSCR1 PSCR1 PSCR2 PSCR3 PSCR1 – – TCNT (25) TCNT0H, TCNT1A, TCNT2A, TCNT3 TCNT4 TCNT5 TCNT6A TCNT7A – TCNT0L TCNT1B TCNT2B to to TCNT6D TCNT7D TCNT10AH, TCNT11 TCNT10AL, TCNT10B to TCNT10H DCNT (16) – – – – – – – – DCNT8A – to DCNT8P – – – ECNT (6) – – – – – – – – ECNT9A – to ECNT9F TCR9A TCR10 to TCR9C – TIOR10 – TCR (17) – TCR1A, TCR1B TCR2A, TCR3 TCR2B TCR4 TCR5 TCR6A, TCR7A, TCR8 TCR6B TCR7B – – TCR11 TIOR (17) TIOR0 TIOR1A TIOR2A TIOR3A, TIOR4A, TIOR5A, – to to TIOR3B TIOR4B TIOR5B TIOR1D TIOR2D TSR1A, TSR1B TSR2A, TSR3 TSR2B TSR3 TIER3 – TSR3 TIER3 – TSR6 TIER6 – TIOR11 TSR (12) TSR0 TIER (12) TIER0 TSR7 TIER7 – TSR8 TIER8 – TSR9 TIER9 – TSR10 TIER10 – TSR11 TIER11 – TIER1A, TIER2A, TIER3 TIER1B TIER2B – – ITVRR (3) ITVRR1, – ITVRR2A, ITVRR2B GR (37) ICR (5) – GR1A to GR2A to GR3A to GR4A to GR5A to – GR1H GR2H GR3D GR4D GR5D – – – – – – – – – GR9A to GR10G GR9F – GR11A, GR11B ICR0AH, – ICR0AL to ICR0DH, ICR0DL OCR1 ICR10AH, – ICR10AL OCR (11) – OCR2A – to OCR2H OSBR2 – – TMDR – – – – – – OCR10AH, – OCR10AL, OCR10B – – – – – – OSBR (2) – TRGMDR – (1) TMDR (1) – OSBR1 – – TMDR – – TMDR – – – – – – – – – – – – TRGMDR – – – Rev. 3.0, 09/04, page 425 of 1086 Table 11.4 ATU-II Registers and Pins (cont) Channel Register 1 Name* Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel 0 1 2 3 4 5 6 7 8 9 10 – – – – – CYLR6A CYLR7A – to to CYLR6D CYLR7D BFR6A BFR7A – to to BFR6D BFR7D DTR6A DTR7A – to to DTR6D DTR7D PMDR – – – – – – – – – – – – – – – – – TO7A to D – RLDR TCNR OTR DSTR – – Channel 11 – CYLR (8) – BFR (8) – – – – – – – – – DTR (8) – – – – – – – – – PMDR (1) – RLDR (1) – TCNR (1) – OTR (1) – – – – – – – – – – TIO1A to H, TCLKA, TCLKB – – – – – – – – – TIO2A to H, TCLKA, TCLKB – – – – – – – – – TIO3A to D, TCLKA, TCLKB – – – – – – – – – TIO4A to D, TCLKA, TCLKB – – – – – – – – – – – – – – – – – – – – RLD10C NCR10 – – – – – – – – DSTR (1) – RLDENR – (1) RLD (1) NCR (1) – – RLDENR – – – – TO8A to P – – – TI9A to F TCCLR (1) – Pins* 2 TCCLR10 – T10 TIO11A, TIO11B, TCLKA, TCLKB TI0A to D TIO5A TO6A to D, to D TCLKA, TCLKB Notes: 1. Figures in parentheses show the number of registers. A 32-bit register is shown as a single register. 2. Pin functions should be set as described in section 21, Pin Function Controller (PFC). Rev. 3.0, 09/04, page 426 of 1086 Section 12 Advanced Pulse Controller (APC) 12.1 Overview The SH7058 has an on-chip advanced pulse controller (APC) that can generate a maximum of eight pulse outputs, using the advanced timer unit II (ATU-II) as the time base. 12.1.1 Features The features of the APC are summarized below. • Maximum eight pulse outputs The pulse output pins can be selected from among eight pins. Multiple settings are possible. • Output trigger provided by advanced timer unit II (ATU-II) channel 11 Pulse 0 output and 1 output is performed using the compare-match signal generated by the ATU-II channel 11 compare-match register as the trigger. Rev. 3.0, 09/04, page 427 of 1086 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the advanced pulse controller. ATU-II Internal/external clock TCNT11 Compare GR11B GR11A Comparematch signal Comparematch signal Set Bit 7 Bit 15 Reset Set Bit 6 POPCR (pulse output port setting register) PULS7 Bit 14 Reset Set PULS6 Bit 5 Bit 13 Reset Set PULS5 Bit 4 Bit 12 Reset Set PULS4 Bit 3 Bit 11 Reset Set PULS3 Bit 2 Bit 10 Reset Set PULS2 Bit 1 Bit 9 Reset Set PULS1 Bit 0 Bit 8 Reset PULS0 APC POPCR: Pulse output port control register Figure 12.1 Advanced Pulse Controller Block Diagram Rev. 3.0, 09/04, page 428 of 1086 12.1.3 Pin Configuration Table 12.1 summarizes the advanced pulse controller’s output pins. Table 12.1 Advanced Pulse Controller Pins Pin Name PULS0 PULS1 PULS2 PULS3 PULS4 PULS5 PULS6 PULS7 I/O Output Output Output Output Output Output Output Output Function APC pulse output 0 APC pulse output 1 APC pulse output 2 APC pulse output 3 APC pulse output 4 APC pulse output 5 APC pulse output 6 APC pulse output 7 12.1.4 Register Configuration Table 12.2 summarizes the advanced pulse controller’s register. Table 12.2 Advanced Pulse Controller Register Name Pulse output port control register Abbreviation POPCR R/W R/W Initial Value H'0000 Address H'FFFFF700 Access Size 8, 16 Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles. Rev. 3.0, 09/04, page 429 of 1086 12.2 12.2.1 Register Descriptions Pulse Output Port Control Register (POPCR) The pulse output port control register (POPCR) is a 16-bit readable/writable register. POPCR is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not initialized in software standby mode. Bit: 15 PULS7 ROE Initial value: R/W: Bit: 0 R/W 7 PULS7 SOE Initial value: R/W: 0 R/W 14 PULS6 ROE 0 R/W 6 PULS6 SOE 0 R/W 13 PULS5 ROE 0 R/W 5 PULS5 SOE 0 R/W 12 PULS4 ROE 0 R/W 4 PULS4 SOE 0 R/W 11 PULS3 ROE 0 R/W 3 PULS3 SOE 0 R/W 10 PULS2 ROE 0 R/W 2 PULS2 SOE 0 R/W 9 PULS1 ROE 0 R/W 1 PULS1 SOE 0 R/W 8 PULS0 ROE 0 R/W 0 PULS0 SOE 0 R/W • Bits 15 to 8—PULS7 to PULS0 Reset Output Enable (PULS7ROE to PULS0ROE): These bits enable or disable 0 output to the APC pulse output pins (PULS7 to PULS0) bit by bit. Bits 15 to 8: PULS7ROE to PULS0ROE 0 1 Description 0 output to APC pulse output pin (PULS7—PULS0) is disabled (Initial value) 0 output to APC pulse output pin (PULS7—PULS0) is enabled When one of these bits is set to 1, 0 is output from the corresponding pin on a compare-match between the GR11B and TCNT11 values. • Bits 7 to 0—PULS7 to PULS0 Set Output Enable (PULS7SOE to PULS0SOE): These bits enable or disable 1 output to the APC pulse output pins (PULS7 to PULS0) bit by bit. Bits 7 to 0: PULS7SOE to PULS0SOE 0 1 Description 1 output to APC pulse output pin (PULS7—PULS0) is disabled (Initial value) 1 output to APC pulse output pin (PULS7—PULS0) is enabled Rev. 3.0, 09/04, page 430 of 1086 When one of these bits is set to 1, 1 is output from the corresponding pin on a compare-match between the GR11A and TCNT11 values. 12.3 12.3.1 Operation Overview APC pulse output is enabled by designating multiplex pins for APC pulse output with the pin function controller (PFC), and setting the corresponding bits to 1 in the pulse output port control register (POPCR). When general register 11A (GR11A) in the advanced timer unit II (ATU-II) subsequently generates a compare-match signal, 1 is output from the pins set to 1 by bits 7 to 0 in POPCR. When general register 11B (GR11B) generates a compare-match signal, 0 is output from the pins set to 1 by bits 15 to 8 in POPCR. 0 is output from the output-enabled state until the first compare-match occurs. The advanced pulse controller output operation is shown in figure 12.2. CR Upper 8 bits of POPCR GR11B Compare-match signal Reset signal Port function selection APC output pins (PULS0 to PULS7) Set signal Compare-match signal GR11A Lower 8 bits of POPCR Figure 12.2 Advanced Pulse Controller Output Operation Rev. 3.0, 09/04, page 431 of 1086 12.3.2 Advanced Pulse Controller Output Operation Example of Setting Procedure for Advanced Pulse Controller Output Operation: Figure 12.3 shows an example of the setting procedure for advanced pulse controller output operation. 1. Set general registers GR11A and GR11B as output compare registers with the timer I/O control register (TIOR). 2. Set the pulse rise point with GR11A and the pulse fall point with GR11B. 3. Select the timer counter 11 (TCNT11) counter clock with the timer prescale register (PSCR). TCNT11 can only be cleared by an overflow. 4. Enable the respective interrupts with the timer interrupt enable register (TIER). 5. Set the pins for 1 output and 0 output with POPCR. 6. Set the control register for the port to be used by the APC to the APC output pin function. 7. Set the STR bit to 1 in the timer start register (TSTR) to start timer counter 11 (TCNT11). 8. Each time a compare-match interrupt is generated, update the GR value and set the next pulse output time. 9. Each time a compare-match interrupt is generated, update the POPCR value and set the next pin for pulse output. Rev. 3.0, 09/04, page 432 of 1086 APC output operation GR function selection GR setting ATU-II settings Count operation setting Interrupt request setting APC setting Port setting ATU-II setting Rise/fall port setting Port output setting Start count 3 4 5 6 7 1 2 Compare-match? Yes ATU-II setting APC setting GR setting Rise/fall port setting No 8 9 Figure 12.3 Example of Setting Procedure for Advanced Pulse Controller Output Operation Rev. 3.0, 09/04, page 433 of 1086 Example of Advanced Pulse Controller Output Operation: Figure 12.4 shows an example of advanced pulse controller output operation. 1. Set ATU-II registers GR11A and GR11B (to be used for output trigger generation) as output compare registers. Set the rise point in GR11A and the fall point in GR11B, and enable the respective compare-match interrupts. 2. Write H'0101 to POPCR. 3. Start the TCNT11 count, when a GR11A compare-match occurs, 1 is output from the PULS0 pin. When a GR11B compare-match occurs, 0 is output from the PULS0 pin. 4. Pulse output widths and output pins can be continually changed by successively rewriting GR11A, GR11B, and POPCR in response to compare-match interrupts. 5. By setting POPCR to a value such as H'E0E0, pulses can be output from up to eight pins in response to a single compare-match. Cleared on overflow TCNT value Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten GR11B GR11A H'0000 POPCR 0101 0202 0404 0808 1010 E0E0 PULS0 PULS1 PULS2 PULS3 PULS4 PULS5 PULS6 PULS7 Figure 12.4 Example of Advanced Pulse Controller Output Operation Rev. 3.0, 09/04, page 434 of 1086 12.4 Usage Notes Contention between Compare-Match Signals: If the same value is set for both GR11A and GR11B, and 0 output and 1 output are both enabled for the same pin by the POPCR settings, 0 output has priority on pins PULS0 to PULS7 when compare-matches occur. TCNT value H'FFFF H'8000 GR11A GR11B POPCR H'8000 H'8000 H'0101 PULS0 pin Pin output is 0 Figure 12.5 Example of Compare-Match Contention Rev. 3.0, 09/04, page 435 of 1086 Rev. 3.0, 09/04, page 436 of 1086 Section 13 Watchdog Timer (WDT) 13.1 Overview The watchdog timer (WDT) is a 1-channel timer for monitoring system operations. If a system encounters a problem (crashes, for example) and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT can simultaneously generate an internal reset signal for the entire chip. When the watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer operation, an interval timer interrupt is generated at each counter overflow. 13.1.1 Features The WDT has the following features: • Works in watchdog timer mode or interval timer mode • Outputs WDTOVF in watchdog timer mode When the counter overflows in watchdog timer mode, overflow signal WDTOVF is output externally. It is possible to select whether to reset the chip internally when this happens. Either the power-on reset or manual reset signal can be selected as the internal reset signal. • Generates interrupts in interval timer mode When the counter overflows, it generates an interval timer interrupt. • Works with eight counter input clocks Rev. 3.0, 09/04, page 437 of 1086 13.1.2 Block Diagram Figure 13.1 is the block diagram of the WDT. ITI (interrupt signal) Overflow Interrupt control Clock Clock select Internal reset signal* Reset control φ/2 φ/64 φ/128 φ/256 φ/512 φ/1024 φ/4096 φ/8192 Internal clock sources RSTCSR TCNT TCSR Module bus WDT TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Bus interface Note: * The internal reset signal can be generated by making a register setting. Figure 13.1 WDT Block Diagram 13.1.3 Pin Configuration Table 13.1 shows the pin configuration. Table 13.1 Pin Configuration Pin Watchdog timer overflow Abbreviation WDTOVF I/O O Function Outputs the counter overflow signal in watchdog timer mode Rev. 3.0, 09/04, page 438 of 1086 Internal data bus 13.1.4 Register Configuration Table 13.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 13.2 WDT Registers Address Name Timer control/status register Timer counter Reset control/status register Abbreviation R/W TCSR TCNT RSTCSR R/(W)* R/W R/(W)* 3 3 Initial Value H'18 H'00 H'1F Write* 1 Read* 2 H'FFFFEC10 H'FFFFEC10 H'FFFFEC11 H'FFFFEC12 H'FFFFEC13 Notes: In register access, four cycles are required for both byte access and word access. 1. Write by word transfer. These registers cannot be written in bytes or longwords. 2. Read by byte transfer. These registers cannot be read in words or longwords. 3. Only 0 can be written to bit 7 to clear the flag. 13.2 13.2.1 Register Descriptions Timer Counter (TCNT) TCNT is an 8-bit readable/writable upcounter. (TCNT differs from other registers in that it is more difficult to write to. See section 13.2.4, Register Access, for details.) When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the watchdog timer counter starts counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows (changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit in TCSR. TCNT is initialized to H'00 by a power-on reset, in hardware and software standby modes, and when the TME bit is cleared to 0. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 3.0, 09/04, page 439 of 1086 13.2.2 Timer Control/Status Register (TCSR) The timer control/status register (TCSR) is an 8-bit readable/writable register. (TCSR differs from other registers in that it is more difficult to write to. See section 13.2.4, Register Access, for details.) TCSR performs selection of the timer counter (TCNT) input clock and mode. TCSR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 OVF Initial value: R/W: 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 – 1 R 3 – 1 R 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * The only operation permitted on the OVF bit is a write of 0 after reading 1. • Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00 in interval timer mode. This flag is not set in the watchdog timer mode. Bit 7: OVF 0 Description No overflow of TCNT in interval timer mode [Clearing condition] When 0 is written to OVF after reading OVF 1 TCNT overflow in interval timer mode (Initial value) • Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer. When TCNT overflows, the WDT either generates an interval timer interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected. Bit 6: WT/IT 0 1 Description Interval timer mode: interval timer interrupt (ITI) request to the CPU when TCNT overflows (Initial value) Watchdog timer mode: WDTOVF signal output externally when TCNT overflows. (Section 13.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in watchdog timer mode.) Rev. 3.0, 09/04, page 440 of 1086 • Bit 5—Timer Enable (TME): Enables or disables the timer. Bit 5: TME 0 1 Description Timer disabled: TCNT is initialized to H'00 and count-up stops (Initial value) Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows. • Bits 4 and 3—Reserved: These bits are always read as 1. The write value should always be 1. • Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources for input to TCNT. The clock signals are obtained by dividing the frequency of the system clock (φ). Description Bit 2: CKS2 Bit 1: CKS1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Bit 0: CKS0 0 1 0 1 0 1 0 1 Clock Source φ/2 φ/64 φ/128 φ/256 φ/512 φ/1024 φ/4096 φ/8192 (Initial value) Overflow Interval* (φ = 40 MHz) 12.8 µs 409.6 µs 0.8 ms 1.6 ms 3.3 ms 6.6 ms 26.2 ms 52.4 ms Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. Refer to section 13.4.7, Multiplication Factor for Internal Clock Signal (φ) and Overflow Time. Rev. 3.0, 09/04, page 441 of 1086 13.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable/writable register. (RSTCSR differs from other registers in that it is more difficult to write. See section 13.2.4, Register Access, for details.) It controls output of the internal reset signal generated by timer counter (TCNT) overflow. RSTCR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by overflow of the WDT. It is initialized to H'1F in hardware standby mode and software standby mode. Bit: 7 WOVF Initial value: R/W: 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 – 1 R 3 – 1 R 2 – 1 R 1 – 1 R 0 – 1 R Note: * Only 0 can be written to bit 7 to clear the flag. • Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that TCNT has overflowed (H'FF to H'00) in watchdog timer mode. This flag is not set in interval timer mode. Bit 7: WOVF 0 Description No TCNT overflow in watchdog timer mode [Clearing condition] When 0 is written to WOVF after reading WOVF 1 Set by TCNT overflow in watchdog timer mode (Initial value) • Bit 6—Reset Enable (RSTE): Selects whether to reset the chip internally if TCNT overflows in watchdog timer mode. Bit 6: RSTE 0 1 Description Not reset when TCNT overflows Reset when TCNT overflows (Initial value) LSI not reset internally, but TCNT and TCSR reset within WDT. • Bit 5—Reset Select (RSTS): Selects the kind of internal reset to be generated when TCNT overflows in watchdog timer mode. Bit 5: RSTS 0 1 Description Power-on reset Manual reset (Initial value) • Bits 4 to 0—Reserved: These bits are always read as 1. The write value should always be 1. Rev. 3.0, 09/04, page 442 of 1086 13.2.4 Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in that they are more difficult to write to. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions. TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure 13.2). This transfers the write data from the lower byte to TCNT or TCSR. Writing to TCNT 15 Address: H'FFFFEC10 H'5A 8 7 Write data 0 Writing to TCSR 15 Address: H'FFFFEC10 H'A5 8 7 Write data 0 Figure 13.2 Writing to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFFEC12. It cannot be written by byte transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 13.3. To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. Rev. 3.0, 09/04, page 443 of 1086 Writing 0 to the WOVF bit 15 Address: H'FFFFEC12 H'A5 8 7 H'00 0 Writing to the RSTE and RSTS bits 15 Address: H'FFFFEC12 H'5A 8 7 Write data 0 Figure 13.3 Writing to RSTCSR Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFFEC10 for TCSR, H'FFFFEC11 for TCNT, and H'FFFFEC13 for RSTCSR. 13.3 13.3.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits in TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. No TCNT overflows will occur while the system is operating normally, but if TCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF signal is output externally (figure 13.4). The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 128 φ clock cycles. If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally simultaneous with the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTS bit in RSTCSR. The internal reset signal is output for 512 φ clock cycles. When a WDT overflow reset is generated simultaneously with a reset input at the RES pin, the RES reset takes priority, and the WOVF bit in RSTCSR is cleared to 0. The following registers are not initialized by a WDT reset signal: • PFC (pin function controller) registers • I/O port registers These registers are initialized only by an external power-on reset. Rev. 3.0, 09/04, page 444 of 1086 TCNT value Overflow H'FF H'00 WT/ = 1 TME = 1 H'00 written in TCNT WOVF = 1 Time WT/ = 1 H'00 written in TCNT TME = 1 and internal reset generated signal 128 φ clock cycles Internal reset signal* 512 φ clock cycles WT/ : Timer mode select bit TME: Timer enable bit Note: * Internal reset signal occurs only when the RSTE bit is set to 1. Figure 13.4 Operation in Watchdog Timer Mode Rev. 3.0, 09/04, page 445 of 1086 13.3.2 Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1 in TCSR. An interval timer interrupt (ITI) is generated each time the timer counter overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 13.5). TCNT value H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 ITI ITI ITI ITI Time ITI: Interval timer interrupt request generation Figure 13.5 Operation in Interval Timer Mode 13.3.3 Timing of Setting the Overflow Flag (OVF) In interval timer mode, when TCNT overflows, the OVF flag in TCSR is set to 1 and an interval timer interrupt (ITI) is simultaneously requested (figure 13.6). CK TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 13.6 Timing of Setting OVF Rev. 3.0, 09/04, page 446 of 1086 13.3.4 Timing of Setting the Watchdog Timer Overflow Flag (WOVF) When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1 and a WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an internal reset signal to be generated for the entire chip (figure 13.7). CK TCNT H'FF H'00 Overflow signal (internal signal) WOVF Figure 13.7 Timing of Setting WOVF 13.4 13.4.1 Usage Notes TCNT Write and Increment Contention If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer counter is not incremented (figure 13.8). Rev. 3.0, 09/04, page 447 of 1086 TCNT write cycle T1 CK Address Internal write signal TCNT input clock TCNT N M Counter write data TCNT address T2 T3 Figure 13.8 Contention between TCNT Write and Increment 13.4.2 Changing CKS2 to CKS0 Bit Values If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 13.4.3 Changing between Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. 13.4.4 WDTOVF System Reset by WDTOVF Signal If a WDTOVF signal is input to the RES pin, the chip cannot be initialized correctly. Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 13.9. Rev. 3.0, 09/04, page 448 of 1086 This LSI Reset input RES Reset signal to entire system WDTOVF WDTOVF Figure 13.9 Example of System Reset Circuit Using WDTOVF Signal 13.4.5 Internal Reset in Watchdog Timer Mode If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a TCNT overflow occurs, but TCNT and TCSR in the WDT will be reset. Because the internal clock obtained by dividing the system clock(φ) is also reset at this time, the SCI, A/D converter, and CMT that use the internal clock may not operate correctly from hereafter. To continue using these modules, initialize them before use. 13.4.6 Manual Reset in Watchdog Timer When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits until the end of the bus cycle at the time of manual reset generation before making the transition to manual reset exception processing. Therefore, the bus cycle is retained in a manual reset, but if a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception processing will be deferred until the CPU acquires the bus. However, if the interval from generation of the manual reset until the CPU acquires the bus cycle is equal to or longer than the internal manual reset interval of 512 cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception processing is not executed. 13.4.7 Multiplication Factor for Internal Clock Signal (φ) and Overflow Time The watchdog timer operates synchronously with the internal clock signal (φ) (at four or eight times the frequency of the input clock signal). Therefore, even if the same clock signal is selected using the clock select bits (CKS2 to CKS0) in the timer control/status register (TCSR), the overflow timing differs depending on whether the multiplication factor for the internal clock signal (φ) is four or eight. Rev. 3.0, 09/04, page 449 of 1086 Rev. 3.0, 09/04, page 450 of 1086 Section 14 Compare Match Timer (CMT) 14.1 Overview The SH7058 has an on-chip compare match timer (CMT) comprising two 16-bit timer channels. The CMT has 16-bit counters and can generate interrupts at set intervals. 14.1.1 Features The CMT has the following features: • Four types of counter input clock can be selected  One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) can be selected independently for each channel. • Interrupt sources  A compare match interrupt can be requested independently for each channel. Rev. 3.0, 09/04, page 451 of 1086 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the CMT. Pφ/32 CM10 Pφ/8 Pφ/512 CMI1 Pφ/8 Pφ/32 Pφ/512 Pφ/128 Pφ/128 Control circuit Clock selection Control circuit Clock selection Comparator Comparator CMCOR0 CMCOR1 CMCSR0 CMCSR1 CMCNT0 CMCNT1 Bus interface Internal bus CMSTR Module bus CMT CMSTR: CMCSR: CMCOR: CMCNT: CMI: Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match timer counter Compare match interrupt Figure 14.1 CMT Block Diagram Rev. 3.0, 09/04, page 452 of 1086 14.1.3 Register Configuration Table 14.1 summarizes the CMT register configuration. Table 14.1 Register Configuration Channel Name Shared 0 Abbreviation R/W R/W R/(W)* R/W R/W R/(W)* R/W R/W Initial Value H'0000 H'0000 H'0000 Address Access Size (Bits) Compare match timer CMSTR start register Compare match timer CMCSR0 control/status register 0 Compare match timer CMCNT0 counter 0 Compare match timer CMCOR0 constant register 0 H'FFFFF710 8, 16, 32 H'FFFFF712 8, 16, 32 H'FFFFF714 8, 16, 32 H'FFFF H'FFFFF716 8, 16, 32 H'0000 H'0000 H'FFFFF718 8, 16, 32 H'FFFFF71A 8, 16, 32 1 Compare match timer CMCSR1 control/status register 1 Compare match timer CMCNT1 counter 1 Compare match timer CMCOR1 constant register 1 H'FFFF H'FFFFF71C 8, 16, 32 Notes: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles for byte access and word access, and eight or nine internal clock (φ) cycles for longword access. * Only 0 can be written to the CMCSR0 and CMCSR1 CMF bits to clear the flags. Rev. 3.0, 09/04, page 453 of 1086 14.2 14.2.1 Register Descriptions Compare Match Timer Start Register (CMSTR) The compare match timer start register (CMSTR) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT). It is initialized to H'0000 by a power-on reset and in the standby modes. Bit: 15 – Initial value: R/W: Bit: 0 R 7 – Initial value: R/W: 0 R 14 – 0 R 6 – 0 R 13 – 0 R 5 – 0 R 12 – 0 R 4 – 0 R 11 – 0 R 3 – 0 R 10 – 0 R 2 – 0 R 9 – 0 R 1 STR1 0 R/W 8 – 0 R 0 STR0 0 R/W • Bits 15–2—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 1—Count Start 1 (STR1): Selects whether to operate or halt compare match timer counter 1. Bit 1: STR1 0 1 Description CMCNT1 count operation halted CMCNT1 count operation (Initial value) • Bit 0—Count Start 0 (STR0): Selects whether to operate or halt compare match timer counter 0. Bit 0: STR0 0 1 Description CMCNT0 count operation halted CMCNT0 count operation (Initial value) Rev. 3.0, 09/04, page 454 of 1086 14.2.2 Compare Match Timer Control/Status Register (CMCSR) The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the clock used for incrementation. It is initialized to H'0000 by a power-on reset and in the standby modes. Bit: 15 – Initial value: R/W: Bit: 0 R 7 CMF Initial value: R/W: 0 R/(W)* 14 – 0 R 6 CMIE 0 R/W 13 – 0 R 5 – 0 R 12 – 0 R 4 – 0 R 11 – 0 R 3 – 0 R 10 – 0 R 2 – 0 R 9 – 0 R 1 CKS1 0 R/W 8 – 0 R 0 CKS0 0 R/W Note: * Only 0 can be written to clear the flag. • Bits 15–8 and 5–2—Reserved: These bits are always read as 0. The write value should always be 0. • Bit 7—Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and CMCOR values have matched. Bit 7: CMF 0 Description CMCNT and CMCOR values have not matched [Clearing condition] Write 0 to CMF after reading 1 from it 1 CMCNT and CMCOR values have matched (Initial value) • Bit 6—Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1). Bit 6: CMIE 0 1 Description Compare match interrupt (CMI) disabled Compare match interrupt (CMI) enabled (Initial value) Rev. 3.0, 09/04, page 455 of 1086 • Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock input to CMCNT from among the four internal clocks obtained by dividing the peripheral clock (Pφ). When the STR bit of CMSTR is set to 1, CMCNT begins incrementing with the clock selected by CKS1 and CKS0. Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Description Pφ/8 Pφ/32 Pφ/128 Pφ/512 (Initial value) 14.2.3 Compare Match Timer Counter (CMCNT) The compare match timer counter (CMCNT) is a 16-bit register used as an up-counter for generating interrupt requests. When an internal clock is selected with the CKS1 and CKS0 bits of the CMCSR register and the STR bit of CMSTR is set to 1, CMCNT begins incrementing with that clock. When the CMCNT value matches that of the compare match timer constant register (CMCOR), CMCNT is cleared to H'0000 and the CMF flag of CMCSR is set to 1. If the CMIE bit of CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested. CMCNT is initialized to H'0000 by a power-on reset and in the standby modes. It is not initialized by a manual reset. Bit: 15 14 13 12 11 10 9 8 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 3.0, 09/04, page 456 of 1086 14.2.4 Compare Match Timer Constant Register (CMCOR) The compare match timer constant register (CMCOR) is a 16-bit register that sets the period for compare match with CMCNT. CMCOR is initialized to H'FFFF by a power-on reset and in the standby modes. It is not initialized by a manual reset. Bit: 15 14 13 12 11 10 9 8 Initial value: R/W: Bit: 1 R/W 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 14.3 14.3.1 Operation Cyclic Count Operation When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR bit of CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the CMCNT counter value matches that of the compare match constant register (CMCOR), the CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT counter begins counting up again from H'0000. Figure 14.2 shows the compare match counter operation. CMCNT value CMCOR Counter cleared by CMCOR compare match H'0000 Time Figure 14.2 Counter Operation Rev. 3.0, 09/04, page 457 of 1086 14.3.2 CMCNT Count Timing One of four clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) obtained by dividing the peripheral clock (Pφ) can be selected by the CKS1 and CKS0 bits of CMCSR. Figure 14.3 shows the timing. Pφ Internal clock CMCNT input clock CMCNT N–1 N N+1 Figure 14.3 Count Timing 14.4 14.4.1 Interrupts Interrupt Sources and DTC Activation The CMT has a compare match interrupt for each channel, with independent vector addresses allocated to each of them. The corresponding interrupt request is output when interrupt request flag CMF is set to 1 and interrupt enable bit CMIE has also been set to 1. When activating CPU interrupts by interrupt request, the priority between the channels can be changed by means of interrupt controller settings. See section 7, Interrupt Controller (INTC), for details. 14.4.2 Compare Match Flag Set Timing The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the CMCOR register and the CMCNT counter match. The compare match signal is generated upon the final state of the match (timing at which the CMCNT counter matching count value is updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal will not be generated until a CMCNT counter input clock occurs. Figure 14.4 shows the CMF bit set timing. Rev. 3.0, 09/04, page 458 of 1086 Pφ CMCNT input clock CMCNT N 0 CMCOR N Compare match signal CMF CMI Figure 14.4 CMF Set Timing 14.4.3 Compare Match Flag Clear Timing The CMF bit of the CMCSR register is cleared by writing a 0 to it after reading a 1. Figure 14.5 shows the timing when the CMF bit is cleared by the CPU. CMCSR write cycle T1 Pφ T2 CMF Figure 14.5 Timing of CMF Clear by the CPU Rev. 3.0, 09/04, page 459 of 1086 14.5 Usage Notes Take care that the contentions described in sections 14.5.1 to 14.5.3 do not arise during CMT operation. 14.5.1 Contention between CMCNT Write and Compare Match If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure 14.6 shows the timing. CMCNT write cycle T1 Pφ T2 Address CMCNT Internal write signal Compare match signal CMCNT N H'0000 Figure 14.6 CMCNT Write and Compare Match Contention Rev. 3.0, 09/04, page 460 of 1086 14.5.2 Contention between CMCNT Word Write and Incrementation If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter write has priority, so no increment occurs. Figure 14.7 shows the timing. CMCNT write cycle T1 Pφ T2 Address CMCNT Internal write signal CMCNT input clock CMCNT N M CMCNT write data Figure 14.7 CMCNT Word Write and Increment Contention Rev. 3.0, 09/04, page 461 of 1086 14.5.3 Contention between CMCNT Byte Write and Incrementation If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the side on which the write was performed. The byte data on the side on which writing was not performed is also not incremented, so the contents are those before the write. Figure 14.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle. CMCNT write cycle T1 Pφ T2 Address CMCNTH Internal write signal CMCNT input clock CMCNTH N M CMCNTH write data CMCNTL X X Figure 14.8 CMCNT Byte Write and Increment Contention Rev. 3.0, 09/04, page 462 of 1086 Section 15 Serial Communication Interface (SCI) 15.1 Overview The SH7058 has a serial communication interface (SCI) with five independent channels. The SCI supports both asynchronous and synchronous serial communication. It also has a multiprocessor communication function for serial communication between two or more processors, and a clock inverted input/output function. 15.1.1 Features The SCI has the following features: • Selection of asynchronous or synchronous as the serial communication mode  Asynchronous mode Serial data communication is synchronized in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other chip that employs standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. • Data length: seven or eight bits • Stop bit length: one or two bits • Parity: even, odd, or none • Multiprocessor bit: one or none • Receive error detection: parity, overrun, and framing errors • Break detection: by reading the RxD level directly when a framing error occurs  Synchronous mode Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. There is one serial data communication format. • Data length: eight bits • Receive error detection: overrun errors • Serial clock inverted input/output • Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. • On-chip baud rate generator with selectable bit rates Rev. 3.0, 09/04, page 463 of 1086 • Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin (external) • Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receiveerror interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts can start the direct memory access controller (DMAC) to transfer data. • Selection of LSB-first or MSB-first transfer (8-bit length) This selection is available regardless of the communication mode. (The descriptions in this section are based on LSB-first transfer.) 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR SSR SCR SMR BRR RxD RSR TSR SDCR Transmit/ receive control Baud rate generator Pφ Pφ/4 Pφ/16 Pφ/64 TxD Parity generation Parity check SCK Clock External clock TEI TXI RXI ERI SCI RSR: RDR: TSR: TDR: Receive shift register Receive data register Transmit shift register Transmit data register SMR: SCR: SSR: BRR: SDCR: Serial mode register Serial control register Serial status register Bit rate register Serial direction control register Figure 15.1 SCI Block Diagram Rev. 3.0, 09/04, page 464 of 1086 15.1.3 Pin Configuration Table 15.1 summarizes the SCI pins by channel. Table 15.1 SCI Pins Channel 0 Pin Name Serial clock pin Receive data pin Transmit data pin 1 Serial clock pin Receive data pin Transmit data pin 2 Serial clock pin Receive data pin Transmit data pin 3 Serial clock pin Receive data pin Transmit data pin 4 Serial clock pin Receive data pin Transmit data pin Abbreviation Input/Output SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 SCK3 RxD3 TxD3 SCK4 RxD4 TxD4 Input/output Input Output Input/output Input Output Input/output Input Output Input/output Input Output Input/output Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output SCI3 clock input/output SCI3 receive data input SCI3 transmit data output SCI4 clock input/output SCI4 receive data input SCI4 transmit data output Note: In the text the pins are referred to as SCK, RxD, and TxD, omitting the channel number. Rev. 3.0, 09/04, page 465 of 1086 15.1.4 Register Configuration Table 15.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Table 15.2 Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Serial direction control register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Serial direction control register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Serial direction control register 2 Abbreviation R/W SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SDCR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SDCR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SDCR2 R/W R/W R/W R/W R/(W) * R R/W R/W R/W R/W R/W R/(W) * R R/W R/W R/W R/W R/W R/(W) * R R/W 1 1 1 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 Address* 2 Access Size 8, 16 H'FFFFF000 H'FFFFF001 H'FFFFF002 H'FFFFF003 H'FFFFF004 H'FFFFF005 H'FFFFF006 H'FFFFF008 H'FFFFF009 H'FFFFF00A H'FFFFF00B H'FFFFF00C H'FFFFF00D H'FFFFF00E H'FFFFF010 H'FFFFF011 H'FFFFF012 H'FFFFF013 H'FFFFF014 H'FFFFF015 H'FFFFF016 8 8, 16 8 8, 16 8 Rev. 3.0, 09/04, page 466 of 1086 Table 15.2 Registers (cont) Channel 3 Name Serial mode register 3 Bit rate register 3 Serial control register 3 Transmit data register 3 Serial status register 3 Receive data register 3 Serial direction control register 3 4 Serial mode register 4 Bit rate register 4 Serial control register 4 Transmit data register 4 Serial status register 4 Receive data register 4 Serial direction control register 4 Abbreviation R/W SMR3 BRR3 SCR3 TDR3 SSR3 RDR3 SDCR3 SMR4 BRR4 SCR4 TDR4 SSR4 RDR4 SDCR4 R/W R/W R/W R/W R/(W) * R R/W R/W R/W R/W R/W R/(W) * R R/W 1 1 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 Address* 2 Access Size 8, 16 H'FFFFF018 H'FFFFF019 H'FFFFF01A H'FFFFF01B H'FFFFF01C H'FFFFF01D H'FFFFF01E H'FFFFF020 H'FFFFF021 H'FFFFF022 H'FFFFF023 H'FFFFF024 H'FFFFF025 H'FFFFF026 8 8, 16 8 Notes: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock (φ) cycles for byte access and word access, and eight or nine internal clock (φ) cycles for longword access. 1. Only 0 can be written to clear the flags. 2. Do not access empty addresses. Rev. 3.0, 09/04, page 467 of 1086 15.2 15.2.1 Register Descriptions Receive Shift Register (RSR) Bit: 7 6 5 4 3 2 1 0 R/W: – – – – – – – – The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into RSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to RDR. The CPU cannot read or write to RSR directly. 15.2.2 Receive Data Register (RDR) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R The receive data register (RDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (RSR) into RDR for storage. RSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write to RDR. RDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. 15.2.3 Transmit Shift Register (TSR) Bit: 7 6 5 4 3 2 1 0 R/W: – – – – – – – – The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the transmit data register (TDR) into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from TDR into TSR and starts transmitting again. If the TDRE bit of SSR is 1, however, the SCI does not load the TDR contents into TSR. Rev. 3.0, 09/04, page 468 of 1086 The CPU cannot read or write to TSR directly. 15.2.4 Transmit Data Register (TDR) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in TDR into TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in TDR during serial transmission from TSR. The CPU can always read and write to TDR. TDR is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. 15.2.5 Serial Mode Register (SMR) Bit: 7 C/A Initial value: R/W: 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SMR. SMR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. • Bit 7—Communication Mode (C/A): Selects whether the SCI operates in asynchronous or synchronous mode. Bit 7: C/A 0 1 Description Asynchronous mode Synchronous mode (Initial value) Rev. 3.0, 09/04, page 469 of 1086 • Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In synchronous mode, the data length is always eight bits, regardless of the CHR setting. Bit 6: CHR 0 1 Description Eight-bit data Seven-bit data When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. LSB-first/MSB-first selection is not available. (Initial value) • Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In synchronous mode and when using a multiprocessor format, a parity bit is neither added nor checked, regardless of the PE bit setting. Bit 5: PE 0 1 Description Parity bit not added or checked Parity bit added and checked When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E bit) setting. Receive data parity is checked according to the even/odd (O/E bit) setting. (Initial value) • Bit 4—Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is invalid in synchronous mode, in asynchronous mode when parity bit addition and checking is disabled, and when using a multiprocessor format. Bit 4: O/E 0 Description Even parity (Initial value) If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 1 Odd parity If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. Rev. 3.0, 09/04, page 470 of 1086 • Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because no stop bits are added. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 3: STOP 0 Description One stop bit (Initial value) In transmitting, a single bit of 1 is added at the end of each transmitted character. 1 Two stop bits In transmitting, two 1-bits are added at the end of each transmitted character. • Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit setting is used only in asynchronous mode; it is ignored in synchronous mode. For the multiprocessor communication function, see section 15.3.3, Multiprocessor Communication. Bit 2: MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) • Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available: Pφ, Pφ/4, Pφ/16, or Pφ/64 (Pφ is the peripheral clock). For further information on the clock source, bit rate register settings, and baud rate, see section 15.2.8, Bit Rate Register (BRR). Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Description Pφ Pφ/4 Pφ/16 Pφ/64 (Initial value) Rev. 3.0, 09/04, page 471 of 1086 15.2.6 Serial Control Register (SCR) Bit: 7 TIE Initial value: R/W: 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W The serial control register (SCR) operates the SCI transmitter/receiver, selects the serial clock output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCR. SCR is initialized to H'00 by a poweron reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. • Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1 by transfer of serial transmit data from TDR to TSR. Bit 7: TIE 0 Description Transmit-data-empty interrupt request (TXI) is disabled (Initial value) The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. 1 Transmit-data-empty interrupt request (TXI) is enabled • Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1 by transfer of serial receive data from RSR to RDR. It also enables or disables receive-error interrupt (ERI) requests. Bit 6: RIE 0 Description Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled (Initial value) RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. 1 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled Rev. 3.0, 09/04, page 472 of 1086 • Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter. Bit 5: TE 0 Description Transmitter disabled (Initial value) The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked at 1. 1 Transmitter enabled Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SSR) is cleared to 0 after writing of transmit data into TDR. Select the transmit format in SMR before setting TE to 1. • Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver. Bit 4: RE 0 Description Receiver disabled (Initial value) Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. 1 Receiver enabled Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in synchronous mode. Select the receive format in SMR before setting RE to 1. Rev. 3.0, 09/04, page 473 of 1086 • Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1 during reception. The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE 0 Description Multiprocessor interrupts are disabled (normal receive operation) (Initial value) [Clearing conditions] • • 1 When the MPIE bit is cleared to 0 When data with MPB = 1 is received Multiprocessor interrupts are enabled. Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SSR) are disabled until data with the multiprocessor bit set to 1 is received. The SCI does not transfer receive data from RSR to RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SSR). When it receives data that includes MPB = 1, MPB is set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to 1), and allows the FER and ORER bits to be set. • Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted. Bit 2: TEIE 0 1 Description Transmit-end interrupt (TEI) requests are disabled* Transmit-end interrupt (TEI) requests are enabled* (Initial value) Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0; or by clearing the TEIE bit to 0. Rev. 3.0, 09/04, page 474 of 1086 • Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output, or serial clock input. Select the SCK pin function by using the pin function controller (PFC). The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external clock source is selected (CKE1 = 1). For further details on selection of the SCI clock source, see table 15.9 in section 15.3, Operation. Bit 1: Bit 0: 1 CKE1 CKE0 Description* 0 0 Asynchronous mode Synchronous mode 0 1 Asynchronous mode Synchronous mode 1 0 Asynchronous mode Synchronous mode 1 1 Asynchronous mode Synchronous mode Internal clock, SCK pin used for input pin (input signal 2 is ignored) or output pin (output level is undefined)* Internal clock, SCK pin used for synchronous clock 2 output* Internal clock, SCK pin used for clock output* 3 Internal clock, SCK pin used for synchronous clock output External clock, SCK pin used for clock input* 4 External clock, SCK pin used for synchronous clock input External clock, SCK pin used for clock input* 4 External clock, SCK pin used for synchronous clock input Notes: 1. The SCK pin is multiplexed with other functions. Use the pin function controller (PFC) to select the SCK function for this pin, as well as the I/O direction. 2. Initial value. 3. The output clock frequency is the same as the bit rate. 4. The input clock frequency is 16 times the bit rate. Rev. 3.0, 09/04, page 475 of 1086 15.2.7 Serial Status Register (SSR) Bit: 7 TDRE Initial value: R/W: 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Note: * Only 0 can be written to clear the flag. The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating status. The CPU can always read and write to SSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SSR is initialized to H'84 by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. • Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from TDR into TSR and new serial transmit data can be written in TDR. Bit 7: TDRE 0 Description TDR contains valid transmit data [Clearing conditions] • • 1 When 0 is written to TDRE after reading TDRE = 1 When the DMAC writes data in TDR (Initial value) TDR does not contain valid transmit data [Setting conditions] • • • Power-on reset, hardware standby mode, or software standby mode When the TE bit in SCR is 0 When data is transferred from TDR to TSR, enabling new data to be written in TDR Rev. 3.0, 09/04, page 476 of 1086 • Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains received data. Bit 6: RDRF 0 Description RDR does not contain valid receive data [Clearing conditions] • • • 1 Power-on reset, hardware standby mode, or software standby mode When 0 is written to RDRF after reading RDRF = 1 When the DMAC reads data from RDR (Initial value) RDR contains valid received data [Setting condition] RDRF is set to 1 when serial data is received normally and transferred from RSR to RDR Note: RDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the receive data is lost. • Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5: ORER 0 Description Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which retains its previous value. [Clearing conditions] • • 1 Power-on reset, hardware standby mode, or software standby mode When 0 is written to ORER after reading ORER = 1 A receive overrun error occurred RDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In synchronous mode, serial transmitting is disabled. [Setting condition] ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1 Rev. 3.0, 09/04, page 477 of 1086 • Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing error in asynchronous mode. Bit 4: FER 0 Description Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value. [Clearing conditions] • • 1 Power-on reset, hardware standby mode, or software standby mode When 0 is written to FER after reading FER = 1 A receive framing error occurred When the stop bit length is two bits, only the first bit is checked to see if it is a 1. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In synchronous mode, serial transmitting is also disabled. [Setting condition] FER is set to 1 if the stop bit at the end of receive data is checked and found to be 0 • Bit 3—Parity Error (PER): Indicates that data reception (with parity) ended abnormally due to a parity error in asynchronous mode. Bit 3: PER 0 Description Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which retains its previous value. [Clearing conditions] • • 1 Power-on reset, hardware standby mode, or software standby mode When 0 is written to PER after reading PER = 1 A receive parity error occurred When a parity error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. [Setting condition] PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR) Rev. 3.0, 09/04, page 478 of 1086 • Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, TDR did not contain valid data, so transmission has ended. TEND is a read-only bit and cannot be written. Bit 2: TEND 0 Description Transmission is in progress [Clearing conditions] • • 1 When 0 is written to TDRE after reading TDRE = 1 When the DMAC writes data in TDR (Initial value) End of transmission [Setting conditions] • • • Power-on reset, hardware standby mode, or software standby mode When the TE bit in SCR is 0 If TDRE = 1 when the last bit of a one-byte serial transmit character is transmitted • Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in asynchronous mode. MPB is a readonly bit and cannot be written. Bit 1: MPB 0 Description Multiprocessor bit value in receive data is 0 (Initial value) If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previous†value. 1 Multiprocessor bit value in receive data is 1 • Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting. Bit 0: MPBT 0 1 Description Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 (Initial value) Rev. 3.0, 09/04, page 479 of 1086 15.2.8 Bit Rate Register (BRR) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the serial transmit/receive bit rate. The CPU can always read and write to BRR. BRR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. Each channel has independent baud rate generator control, so different values can be set for each channel. Table 15.3 lists examples of BRR settings in the asynchronous mode; table 15.4 lists examples of BBR settings in the clock synchronous mode. Table 15.3 Bit Rates and BRR Settings in Asynchronous Mode Pφ (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 10 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 21 15 10 9 7 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 –1.36 –1.36 1.73 –1.36 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 195 143 71 143 71 143 71 35 23 19 11 10 8 11.0592 Error (%) 0.19 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.54 0.00 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 212 155 77 155 77 155 77 28 25 19 12 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 0.16 0.00 –2.34 Rev. 3.0, 09/04, page 480 of 1086 Table 15.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) Pφ (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 12.288 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 26 19 12 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.23 0.00 2.56 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 248 181 90 181 90 181 90 45 29 22 14 13 10 14 Error (%) –0.17 0.16 0.16 0.16 0.16 0.16 0.16 –0.93 1.27 –0.93 1.27 0.00 3.57 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 31 23 15 14 11 14.7456 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 Rev. 3.0, 09/04, page 481 of 1086 Table 15.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) Pφ (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 16 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 34 25 16 15 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –0.79 0.16 2.12 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 36 27 18 16 13 17.2032 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.90 0.00 –1.75 1.20 0.00 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 38 28 19 17 14 18 Error (%) –0.12 0.16 0.16 0.16 0.16 0.16 0.16 –0.69 0.16 1.02 –2.34 0.00 –2.34 Rev. 3.0, 09/04, page 482 of 1086 Table 15.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 18.432 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 81 239 119 239 119 239 119 59 39 29 19 17 14 Error (%) –0.22 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 255 127 63 42 31 20 19 15 19.6608 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –0.78 0.00 1.59 –1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 129 64 42 32 21 19 15 20 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.94 –1.36 –1.36 0.00 1.73 Rev. 3.0, 09/04, page 483 of 1086 Table 15.4 Bit Rates and BRR Settings in Synchronous Mode Pφ (MHz) Bit Rate (Bits/s) 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M Note: Settings with an error of 1% or less are recommended. Legend Blank: No setting available –: Setting possible, but error occurs *: Continuous transmission/reception not possible 0 0* 10 n – – – 1 1 0 0 0 0 0 0 N – – – 249 124 249 99 49 24 9 4 n 3 3 2 2 1 1 0 0 0 0 0 0 0 12 N 187 93 187 74 149 74 119 59 29 11 5 2 0* n 3 3 2 2 1 1 0 0 0 0 0 0 – 16 N 249 124 249 99 199 99 159 79 39 15 7 3 – – – 2 2 1 1 0 0 0 0 0 0 0 – – 124 249 124 199 99 49 19 9 4 1 0* n 20 N The BRR setting is calculated as follows: Asynchronous mode: N= Pφ 64 • 22n–1 • B • 106 – 1 Synchronous mode: N= Pφ 8 • 22n–1 • B • 106 – 1 Rev. 3.0, 09/04, page 484 of 1086 B: Bit rate (bits/s) N: Baud rate generator BRR setting (0 ≤ N ≤ 255) Pf: Peripheral module operating frequency (MHz) (1/2 of system clock) n: Baud rate generator input clock (n = 0 to 3) (See the following table for the clock sources and value of n.) SMR Settings n 0 1 2 3 Clock Source Pφ Pφ/4 Pφ/16 Pφ/64 CKS1 0 0 1 1 CKS2 0 1 0 1 The bit rate error in asynchronous mode is calculated as follows:   Pφ • 106 Error (%) =  – 1 • 100 (N + 1) • B • 64 • 22n–1   Table 15.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is being used for various frequencies. Tables 15.6 and 15.7 show the maximum rates for external clock input. Table 15.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ (MHz) 10 11.0592 12 12.288 14 14.7456 16 17.2032 18 18.432 19.6608 20 Maximum Bit Rate (Bits/s) 312500 345600 375000 384000 437500 460800 500000 537600 562500 576000 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 3.0, 09/04, page 485 of 1086 Table 15.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode) Pφ (MHz) 10 11.0592 12 12.288 14 14.7456 16 17.2032 18 18.432 19.6608 20 External Input Clock (MHz) 2.5000 2.7648 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.6080 4.9152 5.0000 Maximum Bit Rate (Bits/s) 156250 172800 187500 192000 218750 230400 250000 268800 281250 288000 307200 312500 Table 15.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode) Pφ (MHz) 10 12 14 16 18 20 External Input Clock (MHz) 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (Bits/s) 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 15.2.9 Serial Direction Control Register (SDCR) Bit: 7 – Initial value: R/W: 1 R 6 – 1 R 5 – 1 R 4 – 1 R 3 DIR 0 R/W 2 – 0 R 1 – 1 R 0 – 0 R The DIR bit in the serial direction control register (SDCR) selects LSB-first or MSB-first transfer. With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the communication mode. With a 7-bit data length, LSB-first transfer must be selected. The description in this section assumes LSB-first transfer. Rev. 3.0, 09/04, page 486 of 1086 SDCR is initialized to H'F2 by a power-on reset and in the hardware standby mode. It is not initialized by a manual reset and in software standby mode. • Bits 7–4—Reserved: The write value should always be 1. If 0 is written to these bits, correct operation cannot be guaranteed. • Bit 3—Data Transfer Direction (DIR): Selects the serial/parallel conversion format. Valid for an 8-bit transmit/receive format. Bit 3: DIR 0 1 Description TDR contents are transmitted in LSB-first order Receive data is stored in RDR in LSB-first order TDR contents are transmitted in MSB-first order Receive data is stored in RDR in MSB-first order (Initial value) • Bit 2—Reserved: The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. • Bit 1—Reserved: This bit is always read as 1, and cannot be modified. • Bit 0—Reserved: The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 15.2.10 Inversion of SCK Pin Signal The signal input from the SCK pin and the signal output from the SCK pin can be inverted by means of a port control register setting. See section 21, Pin function Controller (PFC), for details. Rev. 3.0, 09/04, page 487 of 1086 15.3 15.3.1 Operation Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Asynchronous synchronous mode and the transmission format are selected in the serial mode register (SMR), as shown in table 15.8. The SCI clock source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR), as shown in table 15.9. Asynchronous Mode: • Data length is selectable: seven or eight bits. • Parity and multiprocessor bits are selectable, as well as the stop bit length (one or two bits). These selections determine the transmit/receive format and character length. • In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors (ORER), and the break state. • An internal or external clock can be selected as the SCI clock source.  When an internal clock is selected, the SCI operates using the on-chip baud rate generator clock, and can output a clock with a frequency matching the bit rate.  When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode: • The communication format has a fixed 8-bit data length. • In receiving, it is possible to detect overrun errors (ORER). • An internal or external clock can be selected as the SCI clock source.  When an internal clock is selected, the SCI operates using the on-chip baud rate generator clock, and outputs a serial clock signal to external devices.  When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. Rev. 3.0, 09/04, page 488 of 1086 Table 15.8 Serial Mode Register Settings and SCI Communication Formats SMR Settings Mode Asynchronous Bit 7 C/A 0 Bit 6 CHR 0 Bit 5 PE 0 Bit 2 MP 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 Asynchronous (multiprocessor format) 0 * * 1 * * Synchronous 1 * * * 1 0 1 0 1 * 8-bit Absent 7-bit 8-bit Absent Present Present 7-bit Absent Present SCI Communication Format Data Length 8-bit Parity Bit Multipro- Stop Bit cessor Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None Absent Absent Note: Asterisks (*) in the table indicate don't-care bits. Table 15.9 SMR and SCR Settings and SCI Clock Source Selection SMR Mode Bit 7 C/A SCR Settings Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 Synchronous 1 0 0 1 1 0 1 External Internal External SCI Transmit/Receive Clock Clock Source SCK Pin Function* Internal SCI does not use the SCK pin Outputs a clock with frequency matching the bit rate Inputs a clock with frequency 16 times the bit rate Outputs the serial clock or the inverted serial clock Inputs the serial clock or the inverted serial clock Asynchronous 0 Note: * Select the function in combination with the pin function controller (PFC). Rev. 3.0, 09/04, page 489 of 1086 15.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 15.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the marking (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes on the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Idling (marking) 1 0/1 Parity bit Transmit/receive data 1 bit 7 or 8 bits 1 or no bit 1 or 2 bits 1 Stop bit 1 1 Serial data 0 Start bit (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 One unit of communication data (character or frame) Figure 15.2 Data Format in Asynchronous Communication (Example: 8-bit Data with Parity and Two Stop Bits) Rev. 3.0, 09/04, page 490 of 1086 Transmit/Receive Formats: Table 15.10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SMR). Table 15.10 Serial Communication Formats (Asynchronous Mode) SMR Bits CHR PE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 – – – – MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 START START START START START START START START START START START START Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP MPB MPB MPB MPB STOP STOP STOP STOP STOP STOP STOP STOP STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data Legend START: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Note –: Don't-care bits. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR) (table 15.9). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. Rev. 3.0, 09/04, page 491 of 1086 When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 15.3 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 15.3 Output Clock and Communication Data Phase Relationship (Asynchronous Mode) Data Transmit/Receive Operation SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the operation mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Rev. 3.0, 09/04, page 492 of 1086 Figure 15.4 is a sample flowchart for initializing the SCI. The procedure is as follows (the steps correspond to the numbers in the flowchart): Initialize Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) Select transmit/receive format in SMR and SDCR Set value in BRR Wait No 1. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in SCR. 2. Select the communication format in the serial mode register (SMR) and serial direction control register (SDCR). 3. Write the value corresponding to the bit rate in the bit rate register (BRR) (unless an external clock is used). 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1.* Also set RIE, TIE, TEIE, and MPIE as necessary. Setting TE or RE enables the SCI to use the TxD or RxD pin. Note: * In simultaneous transmit/receive operation, the TE bit and RE bit must be cleared to 0 or set to 1 simultaneously. 1 2 3 1-bit interval elapsed? Yes Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE as necessary 4 End Figure 15.4 Sample Flowchart for SCI Initialization Transmitting Serial Data (Asynchronous Mode): Figure 15.5 shows a sample flowchart for transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): Rev. 3.0, 09/04, page 493 of 1086 Initialization Start of transmission 1 Read TDRE bit in SSR 2 No TDRE = 1? Yes Write transmit data to TDR and clear TDRE bit in SSR to 0 3 All data transmitted? Yes Read TEND bit in SSR No TEND = 1? Yes Output break signal? 4 Yes Clear port DR to 0 Clear TE bit in SCR to 0; select theTxD pin as an output port with the PFC No 1. SCI initialization: Set the TxD pin using the PFC. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. 3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-empty interrupt request (TXI) in order to write data in TDR, the TDRE bit is checked and cleared automatically. 4. To output a break at the end of serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCR and use the PFC to establish the TxD pin as an output port. No End of transmission Figure 15.5 Sample Flowchart for Transmitting Serial Data Rev. 3.0, 09/04, page 494 of 1086 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0-bit is output. b. Transmit data: seven or eight bits of data are output, LSB first. c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit: one or two 1-bits (stop bits) are output. e. Marking: output of 1-bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in SSR, outputs the stop bit, then continues output of 1-bits (marking). If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmit-end interrupt (TEI) is requested. Figure 15.6 shows an example of SCI transmit operation in asynchronous mode. Rev. 3.0, 09/04, page 495 of 1086 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Data D1 Parity Stop bit bit D7 0/1 1 1 Idling (marking) TDRE TEND TXI TXI interrupt interrupt handler writes request data in TDR and clears TDRE to 0 1 frame TXI interrupt request TEI interrupt request Figure 15.6 SCI Transmit Operation in Asynchronous Mode (Example: 8-Bit Data with Parity and One Stop Bit) Receiving Serial Data (Asynchronous Mode): Figures 15.7 and 15.8 show a sample flowchart for receiving serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart). Rev. 3.0, 09/04, page 496 of 1086 Initialization 1 Start of reception Read ORER, PER, and FER bits in SSR PER, FER, ORER = 1? No Read RDRF bit in SSR Yes 2 Error handling 3 No RDRF = 1? Yes Read receive data in RDR and clear RDRF bit in SSR to 0 4 No All data received? Yes Clear RE bit in SCR to 0 1. SCI initialization: Set the RxD pin using the PFC. 2. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER bits of SSR to identify the error. After executing the necessary error handling, clear ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 3. SCI status check and receive-data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. Continue receiving serial data: Read RDR and the RDRF bit and clear RDRF to 0 before the stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. End of reception Figure 15.7 Sample Flowchart for Receiving Serial Data (1) Rev. 3.0, 09/04, page 497 of 1086 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit in SCR to 0 Yes No PER = 1? Yes Parity error handling Clear ORER, PER, and FER to 0 in SSR End Figure 15.8 Sample Flowchart for Receiving Serial Data (2) Rev. 3.0, 09/04, page 498 of 1086 In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into RSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check. The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SMR. b. Stop bit check. The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check. RDRF must be 0 so that receive data can be loaded from RSR into RDR. If the data passes these checks, the SCI sets RDRF to 1 and stores the receive data in RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 15.11. Note: When a receive error occurs, further receiving is disabled. While receiving, the RDRF bit is not set to 1, so be sure to clear the error flags. 4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Table 15.11 Receive Error Conditions and SCI Operation Receive Error Overrun error Framing error Parity error Abbreviation ORER FER PER Condition Receiving of next data ends while RDRF is still set to 1 in SSR Stop bit is 0 Parity of receive data differs from even/odd parity setting in SMR Data Transfer Receive data not loaded from RSR into RDR Receive data loaded from RSR into RDR Receive data loaded from RSR into RDR Figure 15.9 shows an example of SCI receive operation in asynchronous mode. Rev. 3.0, 09/04, page 499 of 1086 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Data D1 Parity Stop bit bit D7 0/1 1 1 Idling (marking) TDRF RXI interrupt request FER 1 frame RXI interrupt handler reads data in RDR and clears RDRF to 0. Framing error generates ERI interrupt request. Figure 15.9 SCI Receive Operation (Example: 8-Bit Data with Parity and One Stop Bit) 15.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line for sending and receiving data. The processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 15.10 shows an example of communication among processors using the multiprocessor format. Rev. 3.0, 09/04, page 500 of 1086 Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 15.8. Clock: See the description in the asynchronous mode section. Transmitting processor Serial communication line Receiving processor A (ID = 01) Receiving processor B (ID = 02) Receiving processor C (ID = 03) Receiving processor D (ID = 04) Serial data H'01 (MPB = 1) ID-transmit cycle: receiving processor address H'AA (MPB = 0) Data-transmit cycle: data sent to receiving processor specified by ID MPB: Multiprocessor bit Figure 15.10 Communication among Processors Using Multiprocessor Format (Example: Sending Data H'AA to Receiving Processor A) Data Transmit/Receive Operation Transmitting Multiprocessor Serial Data: Figure 15.11 shows a sample flowchart for transmitting multiprocessor serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): Rev. 3.0, 09/04, page 501 of 1086 Initialization Start of transmission Read TDRE bit in SSR 1 2 No TDRE = 1? Yes Write transmit data in TDR and set MPBT in SSR Clear TDRE bit to 0 All data transmitted? Yes Read TEND bit in SSR No 3 1. SCI initialization: Set the TxD pin using the PFC. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0. 3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. 4. Output a break at the end of serial transmission: Set the data register (DR) of the port to 0, then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC. TEND = 1? Yes Output break signal? Yes Clear port DR to 0 Clear TE bit in SCR to 0; select theTxD pin function as an output port with the PFC No No 4 End of transmission Figure 15.11 Sample Flowchart for Transmitting Multiprocessor Serial Data Rev. 3.0, 09/04, page 502 of 1086 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0-bit is output. b. Transmit data: seven or eight bits are output, LSB first. c. Multiprocessor bit: one multiprocessor bit (MPBT value) is output. d. Stop bit: one or two 1-bits (stop bits) are output. e. Marking: output of 1-bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, outputs the stop bit, then continues output of 1-bits in the marking state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. Figure 15.12 shows an example of SCI receive operation in the multiprocessor format. Multiprocessor bit Stop Start Data bit bit D0 D1 D7 0/1 1 0 D0 Multiprocessor bit Stop Data bit D1 D7 0/1 1 1 Serial data Start bit 0 1 Idling (marking) TDRE TEND TXI interrupt request TXI interrupt handler writes data in TDR and clears TDRE to 0 1 frame TXI interrupt request TEI interrupt request Figure 15.12 SCI Multiprocessor Transmit Operation (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) Rev. 3.0, 09/04, page 503 of 1086 Receiving Multiprocessor Serial Data: Figure 15.13 shows a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is as follows (the steps correspond to the numbers in the flowchart): Initialization Start of reception Set MPIE bit in SCR to 1 Read ORER and FER bits in SSR FER = 1? or ORER =1? No Read RDRF bit in SSR No 1 2 Yes 3 RDRF = 1? Yes Read receive data from RDR No Is ID the station’s ID? Yes Read ORER and FER bits in SSR FER = 1? or ORER =1? No Read RDRF bit in SSR RDRF = 1? Yes Read receive data from RDR 4 5 No Yes 1. SCI initialization: Set the RxD pin using the PFC. 2. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1. 3. SCI status check and compare to ID reception: Read the serial status register (SSR), check that RDRF is set to 1, then read data from the receive data register (RDR) and compare with the processor’s own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER bits in SSR to identify the error. After executing the necessary error handling, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 5. SCI status check and data receiving: Read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR). No All data received? Yes Clear RE bit in SCR to 0 End of reception Error handling Figure 15.13 Sample Flowchart for Receiving Multiprocessor Serial Data (1) Rev. 3.0, 09/04, page 504 of 1086 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit in SCR to 0 Yes Clear ORER and FER bits in SSR to 0 End Figure 15.14 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Figure 15.15 shows examples of SCI receive operation using a multiprocessor format. Rev. 3.0, 09/04, page 505 of 1086 1 Serial data Start bit 0 Data (ID1) D0 D1 D7 Stop Start Data bit (data 1) MPB bit 1 1 0 D0 D1 D7 Stop MPB bit 0 1 1 Idling (marking) MPB MPIE RDRF RDR value RXI interrupt request (multiprocessor interrupt), MPIE = 0 RXI interrupt handler reads data in RDR and clears RDRF to 0 (A) ID Does Not Match Start bit 0 Data (ID2) D0 D1 D7 Stop Start Data MPB bit bit (data 2) 1 1 0 D0 D1 ID1 Not station’s ID, so MPIE is set to 1 again No RXI interrupt, RDR maintains state 1 Serial data Stop MPB bit D7 0 1 1 Idling (marking) MPB MPIE RDRF RDR value ID1 ID2 Data 2 RXI interrupt request (multiprocessor interrupt), MPIE = 0 RXI interrupt handler reads data in RDR and clears RDRF to 0 (B) ID Matches Station’s ID, so receiving MPIE continues, with data bit is again received by the RXI set to 1 interrupt processing routine Figure 15.15 SCI Receive Operation (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) Rev. 3.0, 09/04, page 506 of 1086 15.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full duplex communication is possible while sharing the same clock. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 15.16 shows the general format in synchronous serial communication. Transfer direction One unit (character or frame) of communication data * Serial clock LSB Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 * Note: * High except in continuous transmitting or receiving. Figure 15.16 Data Format in Synchronous Communication In synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode, the SCI transmits or receives data by synchronizing with the rise of the serial clock. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR). See table 15.9. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. An overrun error occurs only during the Rev. 3.0, 09/04, page 507 of 1086 receive operation, and the serial clock is output until the RE bit is cleared to 0. To perform a receive operation in one-character units, select an external clock for the clock source. Transmitting and Receiving Data SCI Initialization (Synchronous Mode): Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. Figure 15.17 is a sample flowchart for initializing the SCI. Start of initialization 1. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. 2. Select the communication format in the serial mode register (SMR) and serial direction control register (SDCR). 3. Write the value corresponding to the bit rate in the bit rate register (BRR) (unless an external clock is used). 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1.* Also set RIE, TIE, TEIE, and MPIE. The TxD, RxD pins becomes usable in response to the PFC corresponding bits and the TE, RE bit settings. Note: * In simultaneous transmit/receive operation, the TE bit and RE bit must be cleared to 0 or set to 1 simultaneously. 4 Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (RIE, TIE, TEIE, MPIE,TE, and RE are 0) 1 Select transmit/receive format in SMR and SDCR 2 Set value in BRR Wait 1-bit interval elapsed? Yes Set TE and RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE bits No 3 End of initialization Figure 15.17 Sample Flowchart for SCI Initialization Rev. 3.0, 09/04, page 508 of 1086 Transmitting Serial Data (Synchronous Mode): Figure 15.18 shows a sample flowchart for transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): Initialization 1 Start of transmission Read TDRE flag in SSR 2 No TDRE = 1? Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR 1. SCI initialization: Set the TxD pin function with the PFC. 2. SCI status check and transmit data write: Read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. 3. To continue transmitting serial data: After checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. No All data transmitted? 3 Yes Read TEND flag in SSR TEND = 1? Yes Clear TE bit to 0 in SCR No End Figure 15.18 Sample Flowchart for Serial Transmitting Rev. 3.0, 09/04, page 509 of 1086 Figure 15.19 shows an example of SCI transmit operation. Transfer direction Serial clock LSB Serial data Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request TXI interrupt TXI interrupt handler writes request data in TDR and clears TDRE to 0 1 frame TEI interrupt request Figure 15.19 Example of SCI Transmit Operation SCI serial transmission operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output mode is selected, the SCI outputs eight serial clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmitend interrupt (TEI) is requested at this time. 4. After the end of serial transmission, the SCK pin is held in the high state. Rev. 3.0, 09/04, page 510 of 1086 Receiving Serial Data (Synchronous Mode): Figures 15.20 and 15.21 show a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. The procedure for receiving serial data is as follows (the steps correspond to the numbers in the flowchart): Initialization 1 Start of reception Read ORER bit in SSR Yes ORER = 1? No Read RDRF bit in SSR No 3 1. SCI initialization: Set the RxD pin using the PFC. 2. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 3. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. Continue receiving serial data: Read RDR, and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. 2 Error handling RDRF = 1? Yes Read receive data from RDR and clear RDRF bit in SSR to 0 4 No All data received? Yes Clear RE bit in SCR to 0 End of reception Figure 15.20 Sample Flowchart for Serial Receiving (1) Rev. 3.0, 09/04, page 511 of 1086 Error handling Overrun error handling Clear ORER bit in SSR to 0 End Figure 15.21 Sample Flowchart for Serial Receiving (2) Figure 15.22 shows an example of the SCI receive operation. Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request Read data with RXI interrupt processing routine and clear RDRF bit to 0 1 frame RXI interrupt request ERI interrupt request generated by overrun error Figure 15.22 Example of SCI Receive Operation Rev. 3.0, 09/04, page 512 of 1086 In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into RSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the receive data in RDR. If the check does not pass (receive error), the SCI operates as indicated in table 15.11 and no further transmission or reception is possible. If the error flag is set to 1, the RDRF bit is not set to 1 during reception, even if the RDRF bit is 0 cleared. When restarting reception, be sure to clear the error flag. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receivedata-full interrupt enable bit (RIE) in SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 15.23 shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure is as follows (the steps correspond to the numbers in the flowchart): Rev. 3.0, 09/04, page 513 of 1086 Initialization Start of transmission/reception 1 Read TDRE bit in SSR No 2 TDRE = 1? Yes Write transmit data in TDR and clear TDRE bit in SSR to 0 Read ORER bit in SSR Yes 3 Error handling 4 ORER = 1? No Read RDRF bit in SSR No RDRF = 1? Yes Read receive data in RDR, and clear RDRF bit in SSR to 0 All data transmitted/ received? Yes Clear TE and RE bits in SCR to 0 End of transmission/reception 5 No 1. SCI initialization: Set the TxD and RxD pins using the PFC. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1. 3. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 4. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 5. Continue transmitting and receiving serial data: Read the RDRF bit and RDR, and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. When the DMAC is started by a transmitdata-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. When the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically. Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both TE and RE to 0, then set both TE and RE to 1 simultaneously. Figure 15.23 Sample Flowchart for Serial Transmission and Reception Rev. 3.0, 09/04, page 514 of 1086 15.4 SCI Interrupt Sources and the DMAC The SCI has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 15.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCR). Each interrupt request is sent separately to the interrupt controller. TXI is requested when the TDRE bit in SSR is set to 1. TXI can start the direct memory access controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC writes data in the transmit data register (TDR). RXI is requested when the RDRF bit in SSR is set to 1. RXI can start the DMAC to transfer data. RDRF is automatically cleared to 0 when the DMAC reads the receive data register (RDR). ERI is requested when the ORER, PER, or FER bit in SSR is set to 1. ERI cannot start the DMAC. TEI is requested when the TEND bit in SSR is set to 1. TEI cannot start the DMAC. Where the TXI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is complete. Table 15.12 SCI Interrupt Sources Interrupt Source ERI RXI TXI TEI Description Receive error (ORER, PER, or FER) Receive data full (RDRF) Transmit data empty (TDRE) Transmit end (TEND) DMAC Activation No Yes Yes No Low Priority High 15.5 Usage Notes Sections 15.5.1 to 15.5.9 provide information concerning use of the SCI. 15.5.1 TDR Write and TDRE Flag The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can be written to TDR regardless of the TDRE bit status. If new data is written in TDR when TDRE is 0, however, the old data stored in TDR will be lost because the data has not yet been transferred to TSR. Before writing transmit data to TDR, be sure to check that TDRE is set to 1. Rev. 3.0, 09/04, page 515 of 1086 15.5.2 Simultaneous Multiple Receive Errors Table 15.13 indicates the state of the SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to RDR, so receive data is lost. Table 15.13 SSR Status Flags and Transfer of Receive Data SSR Status Flags Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer RSR → RDR X O O X X O X Notes: O: Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR. 15.5.3 Break Detection and Processing (Asynchoronous Mode Only) Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. 15.5.4 Sending a Break Signal (Asynchoronous Mode Only) The TxD pin becomes a general I/O pin with the I/O direction and level determined by the I/O port data register (DR) and pin function controller (PFC) control register (CR). These conditions allow break signals to be sent. The DR value is substituted for the marking status until the PFC is set. Consequently, the output port is set to initially output a 1. To send a break in serial transmission, first clear the DR to 0, then establish the TxD pin as an output port using the PFC. When TE is cleared to 0, the transmission section is initialized regardless of the present transmission status. Rev. 3.0, 09/04, page 516 of 1086 15.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only) When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. 15.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer rate. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure 15.24). 16 clocks 8 clocks 0 Base clock –7.5 clocks Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit +7.5 clocks D0 D1 78 15 0 78 15 0 5 Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as: M = 0.5 – D – 0.5 1 (1 + F) • 100% – (L – 0.5) F – N 2N M : Receive margin (%) N : Ratio of clock frequency to bit rate (N = 16) D : Clock duty cycle (D = 0 − 1.0) L : Frame length (L = 9 − 12) F : Absolute deviation of clock frequency From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%: D = 0.5, F = 0 M = (0.5 − 1/(2 • 16)) • 100% = 46.875% Rev. 3.0, 09/04, page 517 of 1086 This is a theoretical value. A reasonable margin to allow in system designs is 20–30%. 15.5.7 Constraints on DMAC Use • When using an external clock source for the serial clock, update TDR with the DMAC, and then after the elapse of five peripheral clocks (Pφ) or more, input a transmit clock. If a transmit clock is input in the first four Pφ clocks after TDR is written, an error may occur (figure 15.25). • Before reading the receive data register (RDR) with the DMAC, select the receive-data-full (RXI) interrupt of the SCI as a start-up source. SCK t TDRE D0 D1 D2 D3 D4 D5 D6 D7 Note: During external clock operation, an error may occur if t is 4 Pφ clocks or less. Figure 15.25 Example of Synchronous Transmission with DMAC 15.5.8 Cautions on Synchronous External Clock Mode • Set TE = RE = 1 only when external clock SCK is 1. • Do not set TE = RE = 1 until at least four Pφ clocks after external clock SCK has changed from 0 to 1. • When receiving, RDRF is 1 when RE is cleared to zero 2.5–3.5 Pφ clocks after the rising edge of the RxD D7 bit SCK input, but copying to RDR is not possible. 15.5.9 Caution on Synchronous Internal Clock Mode When receiving, RDRF is 1 when RE is cleared to zero 1.5 Pφ clocks after the rising edge of the RxD D7 bit SCK output, but copying to RDR is not possible. Rev. 3.0, 09/04, page 518 of 1086 Section 16 Controller Area Network-II (HCAN-II) 16.1 Overview The controller area network-II (HCAN-II) is a module that controls the controller area network (CAN) for realtime communication in the car and industrial device systems, etc. It serves to facilitate the hardware/software interface so that engineers involved in the CAN implementation can ensure the design is successful. The CAN data link controller function is not described in this document. The following CANspecification documents should be referred to. The interfaces from the CAN controller are described, in so far as they pertain to the connection with the user interface. References: 1. CAN License Specification, Robert Bosch GmbH, 1992 2. CAN Specification Version 2.0, Robert Bosch GmbH, 1991 3. Implementation Guide for the CAN Protocol, CAN Specification 2.0 Addendum, CAN In Automation, Erlangen, Germany 4. OSEK Communication Specification, Version 2.1 revision 1, OSEK /VDX, 17 June 1998 16.1.1 Features th • Supports CAN specification 2.0A/2.0B and ISO-11898-1 • 31 programmable mailboxes for transmission/reception and one receive-only mailbox (there is a limitation for usage only in mailbox 31) • Sleep mode for low power consumption and automatic recovery from sleep mode by detecting CAN bus activity • Programmable receive filter mask (standard and extended IDs) supported by all mailboxes • Programmable CAN data rate up to 500 kbits/s (or 1 Mbit/s with a limitation) • Transmit message queuing with an on-chip priority sorting mechanism against the problem of priority inversion for realtime applications • Flexible interrupt structure • Read section 16.8, Usage Notes carefully. Rev. 3.0, 09/04, page 519 of 1086 The following features have been added in the HCAN-II. • IRR0 function to notify a software reset and halt • Halt mode status bit and error passive status bit added to GSR • Supports various test modes • Data frame and remote frame are separated (IRR2 is independent from IRR1 and RXPR from RFRR) • When transmitting, the highest priority search is scanned from mailbox 31 down to mailbox 1 • When receiving, the matching ID search is scanned from mailbox 31 down to mailbox 0, and one received message is only stored into one mailbox • More flexible BCR • Bus off/bus off recover interrupt (IRR6) • Others: • HCAN-II connection method: Two connections are available 32-buffer HCAN-II × 2 channels (transmit pin × 2 and receive pin × 2) 64-buffer HCAN-II (wire AND) × 1 channel (transmit pin × 1 and receive pin × 1) • DMAC can be activated by a receive message of a mailbox (only mailbox 0 in HCAN0) Rev. 3.0, 09/04, page 520 of 1086 16.2 16.2.1 Architecture Block Diagram The HCAN-II device offers a flexible and sophisticated way to configure and control CAN frames, supporting CAN2.0B Active and ISO-11898. The module is configured of 5 different functional blocks. These are the Microprocessor Interface (MPI), mailbox, mailbox control, timer, and CAN interface. Figure 16.1 shows a block diagram of the HCAN-II module. The bus interface timing is designed based on the SuperH peripheral bus interface (P-Bus). HRxDn HTxDn (n: 0 to 1) CAN Interface REC TEC BCR Transmit buffer Receive buffer Control signals Status signals Data-In[15:0] Data-Out[15:0] msn/readn/psize Address[10:0] CLK IRQ Microprocessor interface MCR GSR IRR IMR TXPR0/1 TXCR0/1 RXPR0/1 MBIMR0/1 TXACK0/1 ABACK0/1 RFPR0/1 UMSR0/1 16-bit bus Mailbox control TCNTR TCR TSR CCR CCMAX TDCR LOSR ICRi TCMRi TMR Mailbox0 Mailbox1 Mailbox2 Mailbox3 Mailbox4 Mailbox5 Mailbox6 Mailbox7 Mailbox8 Mailbox9 Mailbox10 Mailbox11 Mailbox12 Mailbox13 Mailbox14 Mailbox15 Mailbox16 Mailbox24 Mailbox17 Mailbox25 Mailbox18 Mailbox26 Mailbox19 Mailbox27 Mailbox20 Mailbox28 Mailbox21 Mailbox29 Mailbox22 Mailbox30 Mailbox23 Mailbox31 Mailbox 0 to Mailbox 31 16-bit timer Figure 16.1 Block Diagram of HCAN-II (for One Channel) Rev. 3.0, 09/04, page 521 of 1086 Note: Since the HCAN-II is designed based on a 16-bit bus system, longword (32-bit) access is prohibited. Thus, word access must be used for all the registers, and word or byte access must be used for the mailboxes. 16.2.2 Each Block Function (1) Microprocessor Interface (MPI) The MPI allows communication between the host CPU and the HCAN's registers/mailboxes to control the memory interface, and the data controller, etc. It also contains the wakeup control logic that detects the CAN bus state and notifies the MPI and the other parts of the HCAN so that the HCAN can automatically exit sleep mode. Contains registers such as MCR, IRR, GSR, and IMR. (2) Mailboxes The mailboxes are message buffers which are configured of RAM. There are 32 mailboxes, and each mailbox stores the following information. • CAN message control (StdID, RTR, DLC, IDE, etc.) • CAN message data (for CAN data frames) • Local acceptance filter mask (LAFM) during reception • 3-bit mailbox configuration, automatic transmit bit for remote request, new message control bit (3) Mailbox Control The mailbox control handles the following functions. For receive messages, compares the IDs, generates appropriate RAM addresses to store messages from the CAN interface into the mailbox, and sets/clears corresponding registers. To transmit messages, runs the internal arbitration to select the correct priority message which is event-triggered, loads the message from the mailbox into the Tx-buffer of the CAN interface, and sets/clears corresponding registers accordingly. Arbitrates mailbox accesses between the host CPU and the CAN interface or mailbox control. Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, and MBIMR. (4) Timer The timer is a block which transmits and receives messages at a specific time frame and records the result. The timer is a 16-bit free-running up counter which is controlled by the host CPU. It provides three 16-bit compare match registers. They can generate interrupt signals, set or clear the counter value in the local offset value, and clear messages in the transmission queue. Two 16-bit input capture registers are included to record timestamps on CAN messages and synchronize the timer value globally within a CAN system. The clock period of this timer offers a wide selection generated from the peripheral clock. Contains registers such as TCNTR, TCR, TPSR, TDCR, LOSR, ICR0_tm, ICR0_cc, ICR0_buf, ICR1, TCMR0, TCMR1, TCMR2, TMR, CCR, CCR_buf, and CMAX. Important: The timer function is not supported by the SH7058. Rev. 3.0, 09/04, page 522 of 1086 (5) CAN Interface The CAN interface supports the requirements for a CAN bus data link controller which is specified in Reference 2 (section 16.1). It fulfils all the functions of a data link layer (DLC layer) as specified by the 7 layers of the OSI model. This block provides the receive error counter, transmit error counter, and bit timing set registers, and various test modes corresponding to the CAN bus specification. This block also stores transmit/receive data for the CAN data link controller. 16.2.3 Pin Configuration Table 16.1 lists the pin configuration and functions. Table 16.1 Pin Configuration Name HRxD0 HTxD0 HRxD1 HTxD1 Input/Output Input Output Input Output Function CAN bus receive signal of channel 0 CAN bus transmit signal of channel 0 CAN bus receive signal of channel 1 CAN bus transmit signal of channel 1 16.2.4 Memory Map Figures 16.2 (1) and 16.2 (2) show the memory maps of registers which can be accessed by software. Base address: Channel 0 → H'FFFFD000, channel 1 → H'FFFFD800 Rev. 3.0, 09/04, page 523 of 1086 Bit15 H'000 H'002 H'004 H'006 H'008 H'00A H'00C Master control register_0 (MCR_0) General status register_0 (GSR_0) Bit0 H'100 Mailbox 0_0 control (StdID, ExtID, RTR, IDE, DLC, ATX, DART, MBC) H'106 H'108 H'10A H'10C H'10E H'110 Mailbox 0_0 LAFM/Mailbox 0_0 TTT HCAN-II_bit timing configuration register 1_0 (HCAN-II_BCR1_0) HCAN-II_bit timing configuration register 0_0 (HCAN-II_BCR0_0) Interrupt register_0 (IRR_0) Interrupt mask register_0 (IMR_0) Transmit error counter_0 (TEC_0) Receive error counter_0 (REC_0) Mailbox 0_0 timestamp 0 2 4 6 Mailbox 0_0 data (8 bytes) 1 3 5 7 H'020 H'022 H'028 H'02A H'030 H'032 H'038 H'03A H'040 H'042 H'048 H'04A H'050 H'052 H'058 H'05A H'080 H'082 H'084 H'086 H'088 H'08A H'08C H'08E H'090 H'092 H'094 H'096 H'098 H'09A H'09C H'09E Transmit pending request register 1_0 (TXPR1_0) Transmit pending request register 0_0 (TXPR0_0) Transmit cancel register 1_0 (TXCR1_0) Transmit cancel register 0_0 (TXCR0_0) Transmit acknowledge register 1_0 (TXACK1_0) Transmit acknowledge register 0_0 (TXACK0_0) Abort acknowledge register 1_0 (ABACK1_0) Abort acknowledge register 0_0 (ABACK0_0) Data frame receive pending register 1_0 (RXPR1_0) Data frame receive pending register 0_0 (RXPR0_0) Remote frame receive pending register 1_0 (RFPR1_0) Remote frame receive pending register 0_0 (RFPR0_0) H'120 Mailbox 1_0 control/timestamp/data/LAFM H'140 Mailbox 2_0 control/timestamp/data/LAFM H'160 Mailbox 3_0 control/timestamp/data/LAFM H'2E0 H'2F3 H'300 Mailbox 15_0 control/timestamp/data/LAFM Mailbox interrupt mask register 1_0 (MBIMR1_0) Mailbox interrupt mask register 0_0 (MBIMR0_0) Unread message status register 1_0 (UMSR1_0) Unread message status register 0_0 (UMSR0_0) Timer counter register 0 (TCNTR0) Timer control register_0 (TCR_0) Timer status register_0 (TSR_0) Timer drift correction register 0 (TDCR0) Local offset register 0 (LOSR0) CCR input capture register 0 (ICR0_cc_0) TCNTR input capture register 0 (ICR0_tm_0) Input capture register 1_0 (ICR1_0) Timer compare match register 0_0 (TCMR0_0) Timer compare match register 1_0 (TCMR1_0) Timer compare match register 2_0 (TCMR2_0) Cycle counter register 0 (CCR0) Cycle maximum register 0 (CMAX0) Timer mode register_0 (TMR_0) Cycle counter register double buffer 0 (CCR_buf0) Input capture register double buffer 0 (ICR0_buf0) Mailbox 16_0 control/timestamp/data/LAFM H'4A0 Mailbox 29_0 control/timestamp/data/LAFM H'4C0 Mailbox 30_0 control/timestamp/data/LAFM H'4E0 H'4F3 Mailbox 31_0 control/timestamp/data/LAFM Figure 16.2 (1) HCAN-II Memory Map for Channel 0 (HCAN0) Rev. 3.0, 09/04, page 524 of 1086 Bit15 H'800 H'802 H'804 H'806 H'808 H'80A H'80C Master control register_1 (MCR_1) General status register_1 (GSR_1) Bit0 H'900 Mailbox 0_1 control (StdID, ExtID, RTR, IDE, DLC, ATX, DART, MBC) H'906 H'908 H'90A H'90C H'90E H'910 Mailbox 0_1 LAFM/Mailbox 0_1 TTT HCAN-II_bit timing configuration register 1_1 (HCAN-II_BCR1_1) HCAN-II_bit timing configuration register 0_1 (HCAN-II_BCR0_1) Interrupt register_1 (IRR_1) Interrupt mask register_1 (IMR_1) Transmit error counter_1 (TEC_1) Receive error counter_1 (REC_1) Mailbox 0_1 timestamp 0 2 4 6 Mailbox 0_1 data (8 bytes) 1 3 5 7 H'820 H'822 H'828 H'82A H'830 H'832 H'838 H'83A H'840 H'842 H'848 H'84A H'850 H'852 H'858 H'85A H'880 H'882 H'884 H'886 H'888 H'88A H'88C H'88E H'890 H'892 H'894 H'896 H'898 H'89A H'89C H'89E Transmit pending request register 1_1 (TXPR1_1) Transmit pending request register 0_1 (TXPR0_1) Transmit cancel register 1_1 (TXCR1_1) Transmit cancel register 0_1 (TXCR0_1) Transmit acknowledge register 1_1 (TXACK1_1) Transmit acknowledge register 0_1 (TXACK0_1) Abort acknowledge register 1_1 (ABACK1_1) Abort acknowledge register 0_1 (ABACK0_1) Data frame receive pending register 1_1 (RXPR1_1) Data frame receive pending register 0_1 (RXPR0_1) Remote frame receive pending register 1_1 (RFPR1_1) Remote frame receive pending register 0_1 (RFPR0_1) H'920 Mailbox 1_1 control/timestamp/data/LAFM H'940 Mailbox 2_1 control/timestamp/data/LAFM H'960 Mailbox 3_1 control/timestamp/data/LAFM H'AE0 H'AF3 H'B00 Mailbox 15_1 control/timestamp/data/LAFM Mailbox interrupt mask register 1_1 (MBIMR1_1) Mailbox interrupt mask register 0_1 (MBIMR0_1) Unread message status register 1_1 (UMSR1_1) Unread message status register 0_1 (UMSR0_1) Timer counter register 1 (TCNTR1) Timer control register_1 (TCR_1) Timer status register_1 (TSR_1) Timer drift correction register 1 (TDCR1) Local offset register 1 (LOSR1) CCR input capture register 1 (ICR1_cc_1) TCNTR input capture register 1 (ICR1_tm_1) Input capture register 1_1 (ICR1_1) Timer compare match register 0_1 (TCMR1_1) Timer compare match register 1_1 (TCMR1_1) Timer compare match register 2_1 (TCMR2_1) Cycle counter register 1 (CCR1) Cycle maximum register 1 (CMAX1) Timer mode register_1 (TMR_1) Cycle counter register double buffer 1 (CCR_buf1) Input capture register double buffer 1 (ICR0_buf1) Mailbox 16_1 control/timestamp/data/LAFM H'CA0 Mailbox 29_1 control/timestamp/data/LAFM H'CC0 Mailbox 30_1 control/timestamp/data/LAFM H'CE0 H'CF3 Mailbox 31_1 control/timestamp/data/LAFM Figure 16.2 (2) HCAN-II Memory Map for Channel 1 (HCAN1) Rev. 3.0, 09/04, page 525 of 1086 16.3 16.3.1 Mailboxes Mailbox Configuration Mailboxes play a role as message buffers to transmit/receive CAN frames. Each mailbox is comprised of 4 identical storage fields that are 1): Message control, 2): Message data, 3): Timestamp, and 4): Local acceptance filter mask (LAFM)/Transmission trigger time. Table 16.2 shows the memory map for each mailbox. Note: The message control (STDID/EXTID/RTR/ZDE), timestamp, and LAFM/transmission trigger time fields can only be accessed in word size (16 bits), whereas the message control (NMC/ATX/MBC/DLC) and the message data area can be accessed in word (16bit) or byte (8-bit) size. Also, when the setting of the MBC bits makes the mailbox inactive, all settings other than the MBC bits must be initialized to 0 because an unused mailbox affects the RAM configuration. When the LAFM is not used to receive messages, it must be cleared to 0. Rev. 3.0, 09/04, page 526 of 1086 Table 16.2 Mailbox Configuration Address Control Mailbox 0 (Receive only) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 6 Bytes 100 − 105 120 − 125 140 − 145 160 − 165 180 − 185 1A0 − 1A5 1C0 − 1C5 1E0 − IE5 200 − 205 220 − 225 240 − 245 260 − 265 280 − 285 2A0 − 2A5 2C0 − 2C5 2E0 − 2E5 300 − 305 320 − 325 340 − 345 360 − 365 380 − 385 3A0 − 3A5 3C0 − 3C5 3E0 − 3E5 400 − 405 420 − 425 440 − 445 460 − 465 480 − 485 4A0 − 4A5 4C0 − 4C5 4E0 − 4E5 Timestamp 2 Bytes 106 − 107 126 − 127 146 − 147 166 − 167 186 − 187 1A6 − 1A7 1C6 − 1C7 1E6 − 1E7 206 − 207 226 − 227 246 − 247 266 − 267 286 − 287 2A6 − 2A7 2C6 − 2C7 2E6 − 2E7 306 − 307 326 − 327 346 − 347 366 − 367 386 − 387 3A6 − 3A7 3C6 − 3C7 3E6 − 3E7 406 − 407 426 − 427 446 − 447 466 − 467 486 − 487 4A6 − 4A7 4C6 − 4C7 4E6 − 4E7 Data 8 Bytes 108 − 10F 128 − 12F 148 − 14F 168 − 16F 188 − 18F 1A8 − 1AF 1C8 − 1CF 1E8 − 1EF 208 − 20F 228 − 22F 248 − 24F 268 − 26F 288 − 28F 2A8 − 2AF 2C8 − 2CF 2E8 − 2EF 308 − 30F 328 − 32F 348 − 34F 368 − 36F 388 − 38F 3A8 − 3AF 3C8 − 3CF 3E8 − 3EF 408 − 40F 428 − 42F 448 − 44F 468 − 46F 488 − 48F 4A8 − 4AF 4C8 − 4CF 4E8 − 4EF LAFM/Trigger Time 4 Bytes 110 − 113 130 − 133 150 − 153 170 − 173 190 − 193 1B0 − 1B3 1D0 − 1D3 1F0 − 1F3 210 − 213 230 − 233 250 − 253 270 − 273 290 − 293 2B0 − 2B3 2D0 − 2D3 2F0 − 2F3 310 − 313 330 − 333 350 − 353 370 − 373 390 − 393 3B0 − 3B3 3D0 − 3D3 3F0 − 3F3 410 − 413 430 − 433 450 − 453 470 − 473 490 − 493 4B0 − 4B3 4D0 − 4D3 4F0 − 4F3 Rev. 3.0, 09/04, page 527 of 1086 Mailbox 0 is a receive-only mailbox, and all the rest of mailbox 1 to mailbox 31 can operate as both receive and transmit mailboxes according to the MBC (Mailbox Configuration) bits in the message control. Figure 16.3 shows the configuration of a mailbox in detail. Important: If mailbox 31 is used as a transmit buffer, there is a usage limitation. For details, see section 16.8, Usage Notes. Register Name MBx[0] to [1] MBx[2] to [3] MBx[4] to [5] MBx[6] MBx[7] to [8] Address HCAN0 HCAN1 15 0 14 13 12 11 10 9 Data Bus 8 7 6 5 4 3 RTR 2 1 0 Access Size 16 bits 16 bits TCT CBE CLE DLC[3:0] 8/16 bits 16 bits MSG_DATA_1 MSG_DATA_3 MSG_DATA_5 MSG_DATA_7 8/16 bits 8/16 bits Data Timestamp Control Field Name H'100+N×32 H'900+N×32 H'102+N×32 H'902+N×32 STDID[10:0] EXTID[15:0] MBC[2:0] 0 IDE EXIDT[17:16] H'104+N×32 H'904+N×32 CCM TTE NMC ATX DART H'106+N×32 H'906+N×32 H'108+N×32 H'908+N×32 Timestamp[15:0] MSG_DATA_0 (first Rx/Tx byte) MSG_DATA_2 MSG_DATA_4 MSG_DATA_6 MBx[9] to [10] H'10A+N×32 H'90A+N×32 MBx[11] to [12] H'10C+N×32 H'90C+N×32 MBx[13] to [14] H'10E+N×32 H'90E+N×32 MBx[15] to [16] H'110+N×32 H'910+N×32 MBx[17] to [18] H'112+N×32 H'912+N×32 8/16 bits 8/16 bits 16 bits 16 bits LAFM/Tx trigger control Local acceptance filter mask 0 (LAFM0)/Tx trigger time 0 (TTT0) Local acceptance filter mask 1 (LAFM1)/Tx trigger time 1 (TTT1) Notes: 1. All bits shadowed in gray are reserved and the write value should be 0. The value read as the initial value is not guaranteed. 2. ATX, DART, and CLE are not supported by mailbox 0 and the MBC setting of mailbox 0 is limited. 3. If the CAN bus is configured in little endian (MCR4 = 1), transmission is started from MSG_DATA_1 instead of MSG_DATA_0 (i.e. the sequence becomes: MSG_DATA_1, MSG_DATA_0, MSG_DATA_3, MSG_DATA_2, MSG_DATA_5, MSG_DATA_4, MSG_DATA_7, and MSG_DATA_6). 4. x/N: 0 to 31 (indicates the mailbox number) Figure 16.3 Mailbox-N Configuration Rev. 3.0, 09/04, page 528 of 1086 16.3.2 Message Control Field Address H'100 + N×32 Bit 15 Bit Name  Description Reserved The write value should be 0. The read value is not guaranteed. 14 to 4 3 STDID [10:0] RTR Standard ID Set the ID (standard ID) of data frames and remote frames. Remote Transmission Request Distinguishes between data frames and remote frames. This bit is overwritten by receive CAN frames depending on data frames or remote frames. Important: Note that, when the ATX bit is set with the setting MBC = 001 the RTR bit cannot be set. When a remote frame is received, the host CPU can be notified by the corresponding RFPR or IRR2 (remote frame request interrupt), however, as the HCAN needs to transmit the current message as a data frame, the RTR bit remains 0. 0: Data frame 1: Remote frame 2 IDE ID Extension Distinguishes between the standard format and extended format of CAN data frames and remote frames. 0: Standard format 1: Extended format 1, 0 EXTID [17:16] EXTID [15:0] Extended ID Set the ID (extended ID) of data frames and remote frames. Register Name MBx[0], MBx[1]* MBx[2], MBx[3]* Note: * H'102 + N×32 15 to 0 x/N: 0 to 31 (Indicates the mailbox number) Rev. 3.0, 09/04, page 529 of 1086 Register Name MBx[4], MBx[5]* Address H'104 + N×32 Bit 15 Bit Name CCM Description CAN-ID Compare Match When this bit is set, message reception in the corresponding mailbox can generate two triggers. If TCR9 is set to 1, TCR14 is cleared to freeze ICR0. If TCR10 is set to 1, TCNTR (timer counter register) is automatically cleared and the LOSR (local offset register) value is set. Important: This function is not supported by the SH7058. Thus the write value should be 0. 14 TTE Time Trigger Enable When this bit is set, a mailbox in which TXPR has been already set transmits a message at a time set in the Tx trigger time field. Important: If this bit is set, a failure occurs during message transmission. Therefore setting is prohibited. The write value should be 0. The value read as the initial value is not guaranteed. Rev. 3.0, 09/04, page 530 of 1086 Register Name MBx[4], MBx[5]* Address H'104 + N×32 Bit 13 Bit Name NMC Description New Message Control When this bit is cleared, a mailbox in which PXPR/PFPR has been already set does not store the new message but retains the previous one and sets the UMSR corresponding bit. When this bit is set, a mailbox in which PXPR/PFPR has been already set stores the new message and sets the UMSR corresponding bit. If a message is received in a mailbox in overwrite mode (NMC = 1), the host CPU must perform an additional check at the end of the data reading from the mailbox in order to guarantee that the mailbox data have not been corrupted during such operation by another receive message. The additional check, to be performed at the end of the mailbox access, consists in verifying that the associated bit of UMSR has not been set and so no overwrite has occurred; in case such bit is set data have been corrupted and so the message must be discarded. Note: * x/N: 0 to 31 (Indicates the mailbox number) Rev. 3.0, 09/04, page 531 of 1086 Register Name MBx[4], MBx[5]* Address H'104 + N×32 Bit 12 Bit Name ATX Description Automatic Transmission of Data Frame When this bit is set to 1 and a remote frame is received in the mailbox, a data frame is automatically transmitted from the same mailbox using the current contents of the message data. The scheduling of transmission is controlled by the CAN ID. In order to use this function, the MBC[2:0] bits should be set to 001. When transmission is performed by this function, the DLC (data length code) to be used is the one that has been received. Important: Note that, when this function is used, the RTR bit is not set even if a remote frame is received. When a remote frame is received, the host CPU will be notified by RFPR or IRR2 (remote frame request interrupt), however, as the HCAN needs to transmit the current message as a data frame, the RTR bit remains 0. 11 DART Disable Automatic Retransmission When this bit is set, it disables the automatic retransmission of a message in the event of an error on the CAN bus or an arbitration lost on the CAN bus. When this function is used, the corresponding TXCR bit is automatically set at the start of transmission. When this bit is cleared, the HCAN tries to transmit the message as many times as required until it is successfully transmitted or it is cancelled by the TXCR. Important: This function is not supported by the SH7058. Thus the write value should be 0. The value read as the initial value is not guaranteed. Note: * x/N: 0 to 31 (Indicates the mailbox number) Rev. 3.0, 09/04, page 532 of 1086 Register Name MBx[4], MBx[5]* Address H'104 + N×32 Bit 10 to 8 Bit Name MBC[2:0] Description Mailbox Configuration Mailbox functions are set as shown in table 16.3. When MBC = 111, the mailbox is inactive, i.e., it does not receive or transmit a message regardless of TXPR or other settings. When MBC = 000 and the TTE bit is set, the Tx-trigger time field becomes available. The MBC = 110 or 011 setting is prohibited. When MBC is set to any other value, the LAFM field becomes available. Important: MB0 should be used as receive-only (MBC = 010). 7  Reserved The write value should be 0. The read value is not guaranteed. 6 TCT Timer Counter Transfer When this bit is set, a mailbox is set for transmission, and the DLC is set to 4, the TCNTR value, at the SOF, is embedded in the second and third bytes of the message data, instead of MSG_DATA_2 and MSG_DATA_3, and the CYCLE_COUNT in the first byte instead of MSG_DATA_0[3:0] when this mailbox starts transmission. This function will be useful when the HCAN performs a time master role to transmit the time reference message. For example, considering that two HCAN controllers are connected in the same network and that the receiver stores the message in mailbox N, the data format is shown as figure 16.4 depending on the endian setting for the CAN bus (MCR4). Important: This function is not supported by the SH7058. Thus the write value should be 0. The value read as the initial value is not guaranteed. Note: * x/N: 0 to 31 (Indicates the mailbox number) Rev. 3.0, 09/04, page 533 of 1086 Register Name MBx[4], MBx[5]* Address H'104 + N×32 Bit 5 Bit Name CBE Description CAN Bus Error An external fault-tolerant CAN transceiver can be used together with the HCAN module. If the error output pin of the transceiver (normally active low) is connected to the CAN_NERR pin of this LSI, the value of the CAN_NERR pin is stored into this bit at the end of each transmission/reception (if the message is stored). The inverted value of the CAN_NERR pin is set to this bit. If the error output pin is active high, the setting value is not inverted. When this bit is set, it indicates a potential physical error with the CAN bus. As the CAN_NERR value is updated after the transmission or reception in the corresponding mailbox, non-interrupt is dedicated to this function but instead the normal transmit end interrupt (IRR6) and normal receive end interrupt (IRR2) should be considered. Important: This function is not supported by the SH7058. Thus the write value should be 0. The value read as the initial value is not guaranteed. 4 CLE Transmit Clear Enable When this bit is set, message reception in the corresponding mailbox cancels the wait messages in the transmission queue. This action is notified by IRR8 and ABACK. Important: This function is not supported by the SH7058. Thus the write value should be 0. The value read as the initial value is not guaranteed. Note: * x/N: 0 to 31 (Indicates the mailbox number) Rev. 3.0, 09/04, page 534 of 1086 Register Name MBx[4], MBx[5]* Address H'104 + N×32 Bit 3 to 0 Bit Name DLC[3:0] Description Data Length Code Indicate the number of data bytes to be transmitted in a data frame. DLC[3:0] Data Length 0000 0001 0010 0011 0100 0101 0110 0111 1xxx [Legend] x: Don’t care 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes Note: * x/N: 0 to 31 (Indicates the mailbox number) Table 16.3 Mailbox Configuration (Setting of MBC[2:0] Bits) Data Remote Data Remote Frame Frame Frame Frame MBC[2] MBC[1] MBC[0] Transmission Transmission Reception Reception Description 0 0 0 0 0 1 Yes Yes Yes Yes No No No Yes • • • • 0 1 0 No No Yes Yes • • 0 1 1 0 1 0 No Yes Setting prohibited Yes Yes • • 1 0 1 No Yes Yes No • • 1 1 1 1 0 1 Setting prohibited Mailbox inactive Not allowed for mailbox 0 LAFM can be used Not allowed for mailbox 0 LAFM can be used Not allowed for mailbox 0 Can be used with ATX Not allowed for mailbox 0 LAFM can be used Allowed for mailbox 0 LAFM can be used Rev. 3.0, 09/04, page 535 of 1086 Important: If mailbox 31 is used as a transmit buffer, there is a usage limitation. For details, see section 16.8, Usage Notes. Message Data Field when TCT = 1: Register Name MBx[7] to [8] MBx[9] to [10] Address HCAN0 H'108+N 32 H'10A+N 32 HCAN1 H'908+N 32 H'90A+N 32 H'90C+N 32 H'90E+N 32 15 14 13 12 11 10 9 Data Bus 8 7 6 5 4 3 2 1 0 Access Size 8/16 bits 8/16 bits Field Name Cycle_Counter (first Rx/Tx byte) TCNTR[7:0] MSG_DATA_4 MSG_DATA_6 Big endian MSG_DATA_1 TCNTR[15:8] MSG_DATA_5 MSG_DATA_7 Data MBx[11] to [12] H'10C+N 32 MBx[13] to [14] H'10E+N 32 8/16 bits 8/16 bits MBx[7] to [8] MBx[9] to [10] H'108+N 32 H'10A+N 32 H'908+N 32 H'90A+N 32 H'90C+N 32 H'90E+N 32 MSG_DATA_1 TCNTR[15:8] MSG_DATA_5 MSG_DATA_7 Little endian Cycle_Counter (first Rx/Tx byte) TCNTR[7:0] MSG_DATA_4 MSG_DATA_6 8/16 bits 8/16 bits Data 8/16 bits 8/16 bits MBx[11] to [12] H'10C+N 32 MBx[13] to [14] H'10E+N 32 [Legend] x/N: 0 to 31 (Indicates the mailbox number) Figure 16.4 Message Data Field Rev. 3.0, 09/04, page 536 of 1086 Timestamp Fields: Records the timestamp on messages for transmission/reception. The timestamp will be a useful function to monitor if messages are received/transmitted within expected schedule or if messages for transmission are scheduled in the appropriate order. Register Name MBx[6]* Address H'106 + N × 32 Bit 15 to 0 Bit Name TimeStamp [15:0] Description Message Reception: During message reception, when the SOF or EOF is detected, ICR1 (input capture register 1) always captures the TCNTR (timer counter register) value or the value of Cycle_Counter + TCNTR[15:4], depending on the value of bit 3 in TMR (Timer mode register), at either SOF or EOF depending on the value in TCR13 (timer control register), and the ICR1 value is stored into the timestamp field of the corresponding mailbox. Important: Capturing at the SOF is not supported by the SH7058. Thus TCR13 should be set to EOF detection mode. Message Transmission: During message transmission, the TCNTR (timer counter register) value or the value of Cycle_Counter + TCNTR[15:4], depending on the value of bit 3 in TMR (timer mode register) is captured when either the TXPR bit or TXACK bit is set depending on the value in TCR12, and the captured value is stored into the timestamp field of the corresponding mailbox. Important: Capturing when the TXPR bit is set is not supported by the SH7058. Activation of the TCNR (timer) causes a problem in the SH7058 (timer usage is prohibited). Therefore, the timestamp function is not supported. The write value should be 0. The value read as the initial value is not guaranteed. Note: * x/N: 0 to 31 (Indicates the mailbox number) Rev. 3.0, 09/04, page 537 of 1086 16.3.3 Register Name MBx[7], MBx[8]* MBx[9], MBx[10]* MBx[11], MBx[12]* MBx[13], MBx[14]* Note: * Message Data Fields Address H'108 + N'× 32 H'10A + N × 32 H'10C + N × 32 H'10E + N × 32 Bit 15 to 8, 7 to 0 15 to 8, 7 to 0 15 to 8, 7 to 0 15 to 8, 7 to 0 Bit Name MSG_DATA_0, MSG_DATA_1 MSG_DATA_2, MSG_DATA_3 MSG_DATA_4, MSG_DATA_5 MSG_DATA_6, MSG_DATA_7 Description Store the CAN message data that is transmitted or received. MSG_DATA_0 corresponds to the first data byte that is transmitted or received. x/N: 0 to 31 (Indicates the mailbox number) 16.3.4 Local Acceptance Filter Mask (LAFM)/Tx-Trigger Time (TTT) This area is used as the local acceptance filter mask (LAFM) for receive boxes or as the Tx-trigger time (TTT) for transmit boxes. LAFM: When the MBC bits are set to 001, 010, 011, 100, and 101, this field becomes the LAFM field. The LAFM is comprised of two 16-bit readable/writable areas. It allows a mailbox to accept more than one receive IDs. Address HCAN0 H'110+N 32 H'112+N 32 HCAN1 H'910+N 32 H'912+N 32 15 0 14 13 12 11 10 9 STDID[10:0] EXTID[15:0] Data Bus 8 7 6 5 4 3 0 2 0 1 0 Access Size Field Name 16 bits 16 bits Register Name MBx[15], MBx[16] MBx[17], MBx[18] EXTID[17:16] LAFM field [Legend] x/N: 0 to 31 (Indicates the mailbox number) Figure 16.5 Acceptance Filter If a bit is set in the LAFM, the corresponding bit of a received CAN ID is ignored when the HCAN searches a mailbox with the matching CAN ID. If the bit is cleared, the corresponding bit of a received CAN ID must match the STD_ID/EXT_ID set in the mailbox to be stored. The configuration of the LAFM is same as the message control in a mailbox. If this function is not required, it must be filled with 0. Notes: 1. When the LAFM is used, the HCAN starts to find a matching ID from mailbox 31 down to mailbox 0. As soon as the HCAN finds one, it stops the search and stores the message into the mailbox. This means that a received message can only be stored into one mailbox. 2. When a message is received and a matching mailbox is found, the whole message is stored into the mailbox. This means that, if the LAFM is used, the STD_ID, RTR, IDE, Rev. 3.0, 09/04, page 538 of 1086 and EXT_ID differ to the ones originally set as they are updated with the STD_ID, RTR, IDE, and EXT_ID of the received message. 3. If the setting of the LAFM register that has already been set is changed, the HCAN should be set to halt mode before changing the setting. Do not access the LAFM during operation. 4. Do not access the undefined addresses. Correct operation cannot be guaranteed. LAFM Field: Register Name MBx[15], MBx[16] Address H'110 + N×32 Bit 15  Bit Name  Description Reserved The write value should be 0. The value read as the initial value is not guaranteed. 14 to 4 STDID_LAFM [10:0] Filter Mask Bits[10:0] for CAN Base ID[10:0] 0: Corresponding bit to CAN base ID set in mailbox is valid 1: Corresponding bit to CAN base ID set in mailbox is invalid 3, 2  Reserved The write value should be 0. The value read as the initial value is not guaranteed. 1, 0 EXTID_LAFM [17:16] Filter Mask Bits[17:16] for CAN Extended ID[17:16] 0: Corresponding bit to extended CAN base ID is valid 1: Corresponding bit to extended CAN base ID is invalid MBx[17], MBx[18] H'112 + N×32 15 to 0 EXTID_LAFM [15:0] Filter Mask Bits[15:0] for CAN Extended ID[15:0] 0: Corresponding bit to extended CAN base ID is valid 1: Corresponding bit to extended CAN base ID is invalid Note: * x/N: 0 to 31 (Indicates the mailbox number) TTT: When the MBC bits are set to 000, this field becomes a Tx-trigger time (TTT) field. The TTT is comprised of two 16-bit readable/writable areas. Rev. 3.0, 09/04, page 539 of 1086 Register Name HCAN0 MBx[15], MBx[16] MBx[17], MBx[18] Address HCAN1 H'910+N 32 H'912+N 32 0 0 0 0 15 14 13 12 11 10 9 Data Bus Access Size Field Name 8 7 6 5 4 3 2 1 0 16 bits 0 0 Rep_Count[3:0] 16 bits Tx-trigger control field H'110+N 32 H'112+N 32 Tx-trigger time (absolute value) Offset[3:0] 0 0 [Legend] x/N: 0 to 31 (Indicates the mailbox number) Figure 16.6 Tx-Trigger Control Field Tx-Trigger Time Field: Register Name MBx[15], MBx[16]* MBx[17], MBx[18]* Address H'110 + N × 32 H'112 + N × 32 Bit 15 to 0 15 to 12 11 to 8 7 to 4 3 to 0 Note: * Bit Name TTT Description Tx-Trigger Time Set the time that triggers message transmission using the absolute value.  Reserved The write value should be 0. The value read as the initial value is not guaranteed. Offset  Offset Reserved The write value should be 0. The value read as the initial value is not guaranteed. Rep_Count [3:0] Repeat Counter Set the transmit cycle. x/N: 0 to 31 (Indicates the mailbox number) The first 16-bit area sets the time that triggers message transmission using the absolute value. The second 16-bit area sets the basic cycle in the system matrix where the transmission must start (offset) and in the system matrix of the frequency for periodic transmission. When TXPR is set, the corresponding Tx-trigger time (TTT), repeat counter, and offset are downloaded into an internal register. When the internal TTT register matches the TCNTR value and the internal offset matches the CCR (cycle counter register) value, the corresponding mailbox automatically starts transmission. In order to enable this function, the TTE (time trigger enable) bit must be enabled (set to 1) and the timer (TCNTR) must be running (TCR15 = 1). When the TTE is cleared to 0 and the corresponding TXPR bit is set, it joins the queue for transmission immediately. If the repeat counter is not 0, transmission occurs periodically every Rep_Count's basic cycle from CCR = offset to CCR = MAX_CYCLE. In such case once TXPR is set by software, the HCAN does not clear the corresponding TXPR bit to carry on performing the periodic transmission. In order to stop the periodic transmission, TXPR must be cleared by TXCR or the Rep_Count field must be cleared. If the repeat counter is 0, transmission occurs only once at the programmed basic cycle (i.e. CCR = offset and TCNTR = TTT). Rev. 3.0, 09/04, page 540 of 1086 The Tx-trigger time must not be set outside the TCNTR cycle if the compare-match timer clear/set function is used (by TCMR0 or CCM). During a time triggered transmission, only another one time triggered transmission can be triggered and a minimum difference of 200 peripheral clock cycles between them is allowed. 16.4 HCAN Control Registers The following sections describe the HCAN control registers. Table 16.4 shows the address map. Note: These registers can only be accessed in word size (16 bits). Table 16.4 HCAN Control Registers Channel Address 0 Register Name Abbreviation MCR_0 GSR_0 HCAN-II_ BCR1_0 HCAN-II_ BCR0_0 IRR_0 IMR_0 TEC_0/REC_0 MCR_1 GSR_1 HCAN-II_ BCR1_1 HCAN-II_ BCR0_1 IRR_1 IMR_1 TEC_1/REC_1 Access Size (Bits) 16 16 16 16 16 16 16 16 16 16 16 16 16 16 H'FFFFD000 Master control register_0 H'FFFFD002 General status register_0 H'FFFFD004 HCAN-II_bit timing configuration register 1_0 H'FFFFD006 HCAN-II_bit timing configuration register 0_0 H'FFFFD008 Interrupt register_0 H'FFFFD00A Interrupt mask register_0 H'FFFFD00C Transmit error counter_0/ Receive error counter_0 1 H'FFFFD800 Master control register_1 H'FFFFD802 General status register_1 H'FFFFD804 HCAN-II_bit timing configuration register 1_1 H'FFFFD806 HCAN-II_bit timing configuration register 0_1 H'FFFFD808 Interrupt register_1 H'FFFFD80A Interrupt mask register_1 H'FFFFD80C Transmit error counter_1/ Receive error counter_1 Rev. 3.0, 09/04, page 541 of 1086 16.4.1 Register Descriptions Legends for register descriptions are as follows: Initial Value — R/W R R/WC0 R/WC1 W —/W 16.4.2 : Register value after a reset : Undefined value : Readable/writable bit. The write value can be read. : Read-only bit. The write value should always be 0. : Readable/writable bit. If 0 is written to this bit, the bit is initialized; if 1 is written to this bit, it is ignored. : Readable/writable bit. If 1 is written to this bit, the bit is initialized; if 0 is written to this bit, it is ignored. : Write-only bit. Reading prohibited. If reserved, the write value should always be 0. : Write-only bit. The read value is undefined. Master Control Register_n (MCR_n) (n = 0, 1) The master control register (MCR) is a 16-bit readable/writable register that controls the HCAN. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TST TST TST TST TST TST TST TST MCR 7 6 5 4 3 2 1 0 7 Initial Value: 0 0 0 0 0 0 0 0 0 0 MCR MCR 5 4 0 0 0 MCR MCR MCR 2 1 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W  R/W R/W  R/W R/W R/W Bit 15 Bit Name TST7 Initial Value 0 R/W R/W Description Test Mode Enables/disables the test modes settable by TST[6:0]. When this bit is set, the following TST[6:0] are enabled. 0: HCAN is in normal mode 1: HCAN is in test mode 14 TST6 0 R/W Write CAN Error Counters Enables the TEC (transmit error counter) and REC (receive error counter) to be writable. The same value is written to TEC and REC at the same time. The maximum value that can be written to TEC and REC is D'255 (H'FF). This means that the HCAN cannot be forced into the bus off state. Before writing to TEC and REC, the HCAN needs to enter halt mode, and when writing to TEC and REC, the TST7 bit (MCR15) should be set to 1. The value written to TEC is used to write REC. 0: TEC/REC is not writable but read-only Rev. 3.0, 09/04, page 542 of 1086 Bit 14 13 Bit Name TST6 TST5 Initial Value 0 0 R/W R/W R/W Description 1: TEC/REC is writable with the same value at the same time Forced Error Passive Forces the HCAN to behave as an error passive node, regardless of the error counters. 0: State of HCAN depends on error counters 1: HCAN behaves as an error passive node, regardless of error counters 12 TST4 0 R/W Automatic Acknowledge Mode Allows the HCAN to generate its own acknowledge bit in order to enable the self test. In order to enter self-test mode, the message transmitted needs to be read back, and there are 2 settings for this. One is to set (Enable Internal Loop = 1, Disable Tx Output = 1, and Disable Rx Input = 1), so that the Tx value is internally provided to the Rx. The other way is to set (Enable Internal Loop = 0, Disable Tx Output = 0, and Disable Rx Input = 0) and connect the Tx and Rx onto the CAN bus so that the transmitted data can be received via the CAN bus. 0: HCAN does not generate its own acknowledge bit 1: HCAN generates its own acknowledge bit 11 TST3 0 R/W Disable Error Counters Enables/disables the error counters (TEC/REC). When this bit is disabled, the error counters (TEC/REC) remain unchanged and retain the current value. When this bit is enabled, the error counters (TEC/REC) operate according to the CAN specification. 0: Error counters (TEC/REC) operate according to the CAN specification 1: Error counters (TEC/REC) remain unchanged and retain the current value Rev. 3.0, 09/04, page 543 of 1086 Bit 10 Bit Name TST2 Initial Value 0 R/W R/W Description Disable Rx Input Controls the Rx to be supplied to the CAN Interface block. When this bit is enabled, the Rx pin value is supplied to the CAN interface block. When this bit is disabled, the Rx value for the CAN block is always retained or the Tx value internally connected if Enable Internal Loop = 1. 0: Value of external Rx pin is supplied to the CAN interface block 1: Enable Internal Loop = 0: Rx value is retained for the CAN interface block Enable Internal Loop = 1: Tx value is internally supplied to the CAN interface block Disable Tx Output Controls the Tx to output transmit data or retain data. When this bit is enabled, the value of the internal transmit output pin appears on the Tx pin. When this bit is disabled, the Tx pin always retains the value. 0: Value of external Tx pin is supplied from the CAN interface block 1: Enable Internal Loop = 0: Tx value is retained Enable Internal Loop = 1: Tx is supplied to the internal Rx Enable Internal Loop Enables/disables the internal Tx looped back to the internal Rx. For details, see section 16.7.1 Test Mode settings. 0: Rx is supplied from the Rx Pin 1: Rx is supplied from the internal Tx signal 9 TST1 0 R/W 8 TST0 0 R/W 7 MCR7 0 R/W Auto-wake Mode Enables or disables auto-wake mode. When this bit is set, the HCAN automatically cancels sleep mode (MCR5) by detecting CAN bus activity (dominant bit). When this bit is not set, the HCAN does not automatically cancel sleep mode. 0: Auto-wake by CAN bus activity disabled 1: Auto-wake by CAN bus activity enabled 6 — 0 R Reserved The write value should be 0. The read value is not guaranteed. Rev. 3.0, 09/04, page 544 of 1086 Bit 5 Bit Name MCR5 Initial Value 0 R/W R/W Description HCAN-II Sleep Mode Enables or disables sleep mode transition. When this bit is set, sleep mode is enabled. The HCAN waits for the completion of the current bus access before entering sleep mode. Until this mode is terminated the HCAN will ignore CAN bus operation. The two error counters (REC, TEC) will retain the same value during and after sleep mode. This mode will be exited in two ways: • • Write 0 to this bit If MCR7 is enabled, after detecting a dominant bit on the CAN bus When exiting this mode, the HCAN will synchronize with the CAN bus (by checking for 11 recessive bits) before restart. This means that, when the second way is used, the HCAN cannot receive the first message, however, CAN transceivers have the same feature, and software needs to be designed in this manner. Note: This mode is same as setting the module to halt mode and stopping the clock. This means that, the interrupt is generated from IRR0 when entering sleep mode. During sleep mode, only the MPI block is accessible, i.e., MCR/GSR/IRR/IMR are accessible. However, IRR1 cannot be cleared during sleep mode as it is an ORed signal of RXPR that cannot be cleared during sleep mode, therefore, it is recommended to set halt mode first and then make a transition to sleep mode. 0: HCAN sleep mode is exited 1: Transition to HCAN sleep mode enabled Important: Usage of sleep mode is limited. Be sure to carefully read section 16.8, Usage Notes. Rev. 3.0, 09/04, page 545 of 1086 Bit 4 Bit Name MCR4 Initial Value 0 R/W R/W Description CAN Endian Mode Controls whether the HCAN should transmit the messages in little endian mode or big endian mode. By using this bit, in other words, it is possible to set different endian mode to the HCAN and the external network. Note that this bit is only valid when data field is transmitted/received. 0: Data field transmitted/received in big endian mode 1: Data field transmitted/received in little endian mode 3 2 MCR3 MCR2 0 0 R/W R/W Reserved The initial value should be retained. Message Transmission Priority Selects the order of transmission for pending transmit data. When this bit is set, pending transmit data are sent in order of the bit position in the transmit wait register (TXPR). The order of transmission starts from mailbox 31 as the highest priority, and then down to mailbox 1 (if those mailboxes are configured for transmission). Important: This function cannot be used for timer triggered transmission. When this bit is cleared, all messages for transmission are queued with respect to their priority (by running internal arbitration). The highest priority message has the arbitration field with the lowest digital value and is transmitted first. The internal arbitration includes the RTR bit and the IDE bit. 0: Transmission order determined by message ID priority 1: Transmission order determined by mailbox number priority (mailbox 31 → mailbox 1) Rev. 3.0, 09/04, page 546 of 1086 Bit 1 Bit Name MCR1 Initial Value 0 R/W R/W Description Halt Request Setting this bit causes the CAN controller to complete its current operation and then to cut off the CAN bus. The HCAN remains in halt mode until this bit is cleared. During halt mode, the CAN interface does not join the CAN bus activity or does not store messages nor transmit messages. All of the registers and mailbox contents are retained. The HCAN will complete the current operation if it is a transmitter or a receiver, and then enter halt mode. If the CAN bus is in the idle or intermission state, the HCAN will enter halt mode immediately. Entering halt mode is notified by IRR0 and GSR4. If a halt request is made during bus off, the HCAN-II remains bus off even after 128 × 11 recessive bits. In order to exit this state, the halt state needs to be canceled by software. In halt mode, the HCAN configuration can be modified as it does not join the bus activity. This bit has to be cleared to 0 to re-join the CAN bus. After this bit is cleared, the CAN interface waits until it detects 11 recessive bits, and then joins the CAN bus. 0: Normal operating mode 1: Halt mode transition request Rev. 3.0, 09/04, page 547 of 1086 Bit 0 Bit Name MCR0 Initial Value 1 R/W R/W Description Reset Request Controls resetting of the HCAN module. After detecting a reset request, the HCAN controller enters its reset routine, re-initializes the internal logic, and then set GSR3 and IRR0 to notify reset mode. Then the HCAN enters reset mode. During re-initialization, all the registers are cleared. This bit has to be cleared by writing a 0 to join the CAN bus. After this bit is cleared, the HCAN needs to be re-configured, waits until it detects 11 recessive bits, and then joins the CAN bus. After a power-on reset, this bit and GSR3 are always set. This means that a reset request has been made and the HCAN is in re-configuration mode. 0: CAN interface normal operating mode (MCR0 = 0 and GSR3 = 0) Setting condition: When 0 is written after an HCAN reset 1: Reset mode transition request of CAN interface Rev. 3.0, 09/04, page 548 of 1086 16.4.3 General Status Register_n (GSR_n) (n = 0, 1) The general status register (GSR) is a 16-bit read-only register that indicates the status of the HCAN. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GSR GSR GSR GSR GSR GSR 5 4 3 2 1 0 Initial Value: 0 R/W:  Bit 15 to 6 Bit Name — 0  0  0  0  0  0  0  0  0  0 R 0 R 1 R 1 R 0 R 0 R Initial Value 0 R/W  Description Reserved The write value should be 0. The read value is not guaranteed. 5 GSR5 0 R Error Passive Status Indicates whether the CAN interface is error passive or not. This bit is set as soon as the HCAN enters the error passive state and is cleared when the module enters again the error active state. This means that this bit will remain high during error passive and during bus off. Thus to find out the correct state, both GSR5 and GRS0 must be considered. 0: HCAN is not error passive Setting condition: HCAN is in error active state 1: HCAN is error passive (if GSR0 = 0) Setting condition: When TEC ≥ 128 or REC ≥ 128 4 GSR4 0 R Halt/Sleep Status Indicates whether the CAN interface is in the halt/sleep state or not. 0: HCAN is not in the halt state nor sleep state 1: Halt mode (if MCR1 = 1) or sleep mode (if MCR5 = 1) Setting condition: If MCR1 is set and the CAN bus is either in intermission or idle state Rev. 3.0, 09/04, page 549 of 1086 Bit 3 Bit Name GSR3 Initial Value 1 R/W R Description Reset Status Indicates whether the CAN interface is in the reset state (configuration mode) or not. 0: Normal operating state Setting condition: After an HCAN internal reset 1: Reset state (configuration mode) 2 GSR2 1 R Message Transmission In Progress Flag Indicates to the host CPU if the HCAN is processing transmission requests or if a transmission is completed. This bit is an ORed signal of all the TXPR bits. Note that the IRR8 (slot empty) is an ORed signal of all the TXACK/ABACK bits. 0: Transmission in progress 1: There is no message requested for transmission 1 GSR1 0 R Transmit/Receive Warning Flag Indicates an error warning. 0: Reset condition: When TEC < 96, REC < 96, or TEC ≥ 256 1: When 96 ≤ TEC < 256 or 96 ≤ REC 0 GSR0 0 R Bus Off Flag Indicates that the HCAN is in the bus off state. 0: Reset condition: Recovery from bus off state 1: When TEC ≥ 256 (bus off state) 16.4.4 HCAN-II_Bit timing Configuration Register n (HCAN-II_BCR0_n, HCAN-II_BCR1_n) (n = 0, 1) The bit configuration registers (BCR0 and BCR1) are 16-bit readable/writable registers that set CAN bit timing parameters and the baud rate prescaler for the CAN interface. For the following description the following definition is used: Timequanta = BRP fclk Where: BRP (baud rate predivider) is stored in BCR0 and fclk is Pφ (peripheral clock). Rev. 3.0, 09/04, page 550 of 1086 • BCR1 For details on TSEG1 and TSEG2 settings, see table 16.4. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSEG1[3:0] Initial Value: 0 0 0 0 0 TSEG2[2:0] 0 0 0 0 0 SJW[1:0] 0 0 0 0  R/W R/W  EG BSP 0 0  R/W R/W R/W: R/W R/W R/W R/W  R/W R/W R/W  Bit 15 14 13 12 Bit Name TSEG1[3] TSEG1[2] TSEG1[1] TSEG1[0] Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Time Segment 1 (TSEG1[3:0] = BCR1[15:12]) Set the segment for absorbing output buffer, CAN bus, and input buffer delay. A value from 4 to 16 time quanta can be set. 0000: Setting prohibited 0001: Setting prohibited 0010: Setting prohibited 0011: PRSEG + PHSEG1 = 4 time quanta 0100: PRSEG + PHSEG1 = 5 time quanta : 1111: PRSEG + PHSEG1 = 16 time quanta Reserved The write value should be 0. The read value is not guaranteed. 11 — 0 — 10 9 8 TSEG2[2] TSEG2[1] TSEG2[0] 0 0 0 R/W R/W R/W Time Segment 2 (TSEG2[2:0] = BCR1[10:8]) Set the segment for correcting 1-bit time error. A value from 2 to 8 time quanta can be set. 000: Setting prohibited 001: PHSEG2 = 2 time quanta (setting prohibited depending on the condition so see table 16.5) 010: PHSEG2 = 3 time quanta 011: PHSEG2 = 4 time quanta 100: PHSEG2 = 5 time quanta 101: PHSEG2 = 6 time quanta 110: PHSEG2 = 7 time quanta 111: PHSEG2 = 8 time quanta 7, 6 — 0 — Reserved The write value should be 0. The read value is not guaranteed. Rev. 3.0, 09/04, page 551 of 1086 Bit 5 4 Bit Name SJW[1] SJW[0] Initial Value 0 0 R/W R/W R/W Description Re-Synchronization Jump Width (SJW[1:0] = BCR0[5:4]) Set the synchronization jump width. 00: 1 time quantum 01: 2 time quanta 10: 3 time quanta 11: 4 time quanta 3, 2 — 0 — Reserved The write value should be 0. The read value is not guaranteed. 1 EG 0 R/W Edge Select (EG = BCR1[1]) Selects at which edge is to be used for resynchronization. In order to comply with the standard CAN, 0 should be set. 0: Re-synchronization is performed at falling edge of Rx 1: Re-synchronization is performed at both rising and falling edges of Rx 0 BSP 0 R/W Bit Sample Point (BSP = BCR1[0]) Sets the point at which data is sampled. Important: Sampling at three points is only available when the BRP[7:0] is programmed to be less than 4. 0: Bit sampling at one point (end of time segment 1) 1: Bit sampling at three points (end of time segment 1, and 1 time quantum before and after) • BCR0 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRP7BRP6BRP5BRP4BRP3BRP2BRP1BRP0 Initial Value: 0 R/W:  0  0  0  0  0  0  0 0 0 0 0 0 0 0 0  R/W R/W R/W R/W R/W R/W R/W R/W Rev. 3.0, 09/04, page 552 of 1086 Bit 15 to 8 Bit Name — Initial Value 0 R/W — Description Reserved The write value should be 0. The read value is not guaranteed. 7 6 5 4 3 2 1 0 BRP[7] BRP[6] BRP[5] BRP[4] BRP[3] BRP[2] BRP[1] BRP[0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Baud Rate Prescale (BRP[7:0] = BCR0 [7:0]) Set the clock used for 1 time quantum. 00000000: 1 • Pφ (peripheral clock) 00000001: 2 • Pφ (peripheral clock) 00000010: 3 • Pφ (peripheral clock) : (BRP + 1) × Pφ (peripheral clock) 11111111: 256 × Pφ (peripheral clock) About Bit Configuration Register: 1-bit time (8-25 quanta) SYNC_SEG PRSEG TSEG1 PHSEG1 PHSEG2 TSEG2 2-8 Quantum 1 4-16 SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal bit edge transitions occur in this segment.) PRSEG: Segment for adjusting physical delay between networks. PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended when synchronization (re-synchronization) is established.) PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is shortened when synchronization (re-synchronization) is established.) The CAN-bus bit rate is calculate as follows: Bit rate = fclk /{(BRP[7:0]+1)×( (TSEG1[3:0]+1)+(TSEG2[2:0]+1)+SYNC_SEG )} The SYNC_SEG is fixed to 1 time quantum. fclk = Pφ (peripheral clock) Rev. 3.0, 09/04, page 553 of 1086 BCR setting constraints TSEG1[3:0] + 1 > TSEG2[2:0] + 1 ≥ SJW[1:0] + 1 TSEG1[3:0] + TSEG2[2:0] + 3 = 8 to 25 time quantum Register set values: TSEG1[3:0], TSEG2[2:0], and SJW[1:0] These constraints allow the setting range shown in table 16.5 for TSEG1 and TSEG2 in the bit configuration register. Table 16.5 TSEG1 and TSEG2 Settings TSEG2 (BCR[10:8]) 001* 2 TSEG1 (BCR[15:12]) 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4 5 6 7 8 9 10 11 12 13 14 15 16 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 010 3 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 011 4 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 100 5 No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 101 6 No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 110 7 No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes 111 8 No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Note: * When BRP[7:0] = 0, TSEG2[2:0] ≥ 2 When BRP[7:0] ≥ 1, TSEG2[2:0] ≥ 1 Examples: 1. To have a bit rate of 1 Mbps with a Pφ (peripheral clock) frequency of fclk = 20 MHz, it is possible to set: BRP[7:0] = 1, TSEG1[3:0] = 5, and TSEG2[2:0] = 2. Then BCR1 should be written to H'5200 and BCR0 to H'0001. 2. To have a bit rate of 500 kbps with a Pφ (peripheral clock) frequency of fclk = 16 MHz, it is possible to set: BRP[7:0] = 1, TSEG1[3:0] = 9, TSEG2[2:0] = 4. Then BCR1 should be written to H'9400 and BCR0 to H'0001. Important: When BRP[7:0] = H'00, TSEG2[2:0] ≠ B'001 Rev. 3.0, 09/04, page 554 of 1086 16.4.5 Interrupt Register_n (IRR_n) (n = 0, 1) The interrupt register (IRR) is a 16-bit readable/writable register that contains status flags for the various interrupt sources. • IRR Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRR IRR IRR IRR IRR IRR IRR9 IRR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 15 14 13 12 11 10 Initial Value: 0 0 0 0 0 0 0 R 0 R 0 0 0 0 0 0 R 0 R 1 R/W R/W: R/W R/W R/W R/W R/W R/W Bit 15 Bit Name IRR15 Initial Value 0 R/W R/W R/W R/W R/W R/W R/W Description Timer Compare Match Interrupt Flag 1 Indicates that a compare-match condition occurred to the timer compare match register 1 (TCMR1). When the value set in TCMR1 matches the timer value (TCMR1 = TCNTR), this bit is set. This bit is not set if the TCMR1 value is H'0000. 0: Timer compare match has not occurred to TCMR1 Clearing condition: Writing 1 1: Timer compare match has occurred to TCMR1 Setting condition: TCMR1 matches the timer value (TCMR1 = TCNTR) if TMR1 = 0 or matches Cycle_Count + TCNTR[15:4] if TMR1 =1 14 IRR14 0 R/W Timer Compare Match Interrupt Flag 0 Indicates that a compare-match condition occurred to the timer compare match register 0 (TCMR0). When the value set in TCMR0 matches the timer value (TCMR0 = TCNTR), this bit is set. This bit is not set if the TCMR0 value is H'0000. 0: Timer compare match has not occurred to the TCMR0 Clearing condition: Writing 1 1: Timer compare match has occurred to the TCMR0 Setting condition: TCMR0 matches the timer value (TCMR0 = TCNTR) Rev. 3.0, 09/04, page 555 of 1086 Bit 13 Bit Name IRR13 Initial Value 0 R/W R/W Description Timer Overrun Interrupt Flag Indicates that the timer has overrun and is reset to the LOSR (local offset register) value. This bit is set even when TCMR0 is enabled to clear/set the timer value and its value is set to H'FFFF. 0: Timer has not overrun Clearing condition: Writing 1 1: Timer has overrun Setting condition: When the timer (TCNTR) changes from H'FFFF to H'0000 12 IRR12 0 R/W Wake-up on Bus Activity Interrupt Flag Indicates that a CAN bus activity is present. While the HCAN is in sleep mode and a recessive to dominant bit transition takes place on the CAN bus, this bit is set. The operation of this interrupt is set in the master control register (MCR7: Autowake mode). This interrupt is cleared by writing a 1 to this bit. Writing a 0 is ignored. 0: Bus idle state Clearing condition: Writing 1 1: CAN bus activity detected in HCAN sleep mode Setting condition: Recessive → dominant bit transition detection while in sleep mode 11 IRR11 0 R/W Timer Compare Match Interrupt Flag 2 Indicates that a compare-match condition occurred to the timer compare match register 2 (TCMR2). When the value set in TCMR2 matches the timer value (TCMR2 = TCNTR) or matches Cycle_Count + TCNTR[15:4] depending on the TMR2 (timer mode register) setting, this bit is set. This bit is not set if the TCMR2 value is H'0000. 0: Timer compare match has not occurred to TCMR2 Clearing condition: Writing 1 1: Timer compare match has occurred to TCMR2 Setting condition: TCMR2 matches the timer value (TCMR2 = TCNTR) if TMR2 = 0 or matches Cycle_Count + TCNTR[15:4] if TMR2 =1 Rev. 3.0, 09/04, page 556 of 1086 Bit 10 Bit Name IRR10 Initial Value 0 R/W R/W Description Cycle Counter Overrun Interrupt Flag Indicates that the Cycle_Counter has reached the maximum value (CMAX). When the CCR counter matches the CMAX value (CCR = CMAX), this bit is set and CCR is cleared. Note that setting CMAX = 0 disables the Cycle_Counter and no interrupt is generated. 0: Cycle counter has not reached CMAX or CMAX =0 Clearing condition: Writing 1 1: Cycle counter has reached CMAX and CMAX ≠ 0 Setting condition: CCR matches the CMAX value (CCR = CMAX) 9 IRR9 0 R Message Overrun/Overwrite Interrupt Flag Status flag indicating that new message has been received but the existing message in the mailbox has not been read due to the corresponding RXPR or RFPR set to 1. The received message is either abandoned (overrun) or overwritten dependant upon the NMC (new message control) bit. This bit is cleared by writing 1 to the correspondent bit in UMSR (unread message status register). Writing 0 is ignored. 0: No message overrun/overwrite Clearing condition: Clearing of all bits in UMSR 1: Receive message overrun and its storage has been rejected or message overwrite Setting condition: Message is received while the corresponding RXPR or RFPR = 1 and MBIMR = 0 Rev. 3.0, 09/04, page 557 of 1086 Bit 8 Bit Name IRR8 Initial Value 0 R/W R Description Mailbox Empty Interrupt Flag Indicates that message transmission or transmission cancellation has been successfully made and this mailbox is now ready to accept a new message data for the next transmission. This bit is set when at least one TXPR bit is cleared. This bit is also set by an ORed signal of the TXACK and ABACK bits, therefore, this bit is automatically cleared when all the TXACK and ABACK bits are cleared. Writing 0 is ignored. Note that this bit does not represent that all TXPR bits are reset, whereas GSR2 does. 0: Messages set for transmission or transmission cancellation not processed Clearing condition: All the TXACK and ABACK bits are cleared 1: Message has been transmitted or canceled, and new message can be stored Setting condition: When one of the TXPR bits is cleared by completion of transmission or completion of transmission cancellation, i.e., when a TXACK or ABACK bit is set (if MBIMR = 0) 7 IRR7 0 R/W Overload Frame Interrupt Flag Indicates that the HCAN has transmitted an overload frame. It remains latched until a reset by writing 1 to this bit. Writing 0 is ignored. 0: Clearing condition: Writing 1 1: Setting condition: Overload frame transmitted Rev. 3.0, 09/04, page 558 of 1086 Bit 6 Bit Name IRR6 Initial Value 0 R/W R/W Description Bus Off/Bus Off Recover Interrupt Flag This bit is set when the HCAN enters the bus-off state or when the HCAN leaves bus-off and returns to error-active. This is because the existing condition that 11 recessive bits have received 128 times when TEC ≥ 256 at the node or in the bus-off state. This bit remains latched even when the HCAN node cancels the bus-off state, and needs to be cleared by software. GSR0 should be read to determine whether the HCAN has become bus-off or error active. This bit is cleared by writing 1 even if the HCAN is still in the bus-off state. Writing 0 is ignored. 0: Clearing condition: Writing 1 1: Bus off state caused by transmit error or error active state returning from bus-off Setting condition: When 11 recessive bits have received 128 times when TEC ≥ 256 at the node or in the bus-off state 5 IRR5 0 R/W Error Passive Interrupt Flag Indicates that the error passive state caused by the transmit or receive error counter. This bit is cleared by writing 1. Writing 0 is ignored. If this bit is cleared, the node may still be error passive. 0: Clearing condition: Writing 1 1: Error passive state caused by transmit/receive error Setting condition: When TEC ≥ 128 or REC ≥ 128 4 IRR4 0 R/W Receive Overload Warning Interrupt Flag This bit is set and latched if the receive error counter (REC) reaches a value greater than 96. This bit is cleared by writing 1. Writing 0 is ignored. When the interrupt is cleared, REC still holds its value greater than 96. 0: Clearing condition: Writing 1 1: Error warning state caused by receive error Setting condition: When REC ≥ 96 Rev. 3.0, 09/04, page 559 of 1086 Bit 3 Bit Name IRR3 Initial Value 0 R/W R/W Description Transmit Overload Warning Interrupt Flag This bit is set and latched if the transmit error counter (TEC) reaches a value greater than 96. This bit is cleared by writing 1. Writing 0 is ignored. When the interrupt is cleared, TEC still holds its value greater than 96. 0: Clearing condition: Writing 1 1: Error warning state caused by transmit error Setting condition: When TEC ≥ 96 2 IRR2 0 R Remote Frame Request Interrupt Flag Indicates that a remote frame has been received in a mailbox. This bit is set if at least one receive mailbox contains a remote frame transmission request. This bit is cleared by ensuring all bits in the remote request wait register (RFPR) are cleared. Writing to this bit is ignored. 0: Clearing condition: Clearing of all bits in RFPR 1: At least one remote request is waiting Setting condition: When a remote frame is received and the corresponding MBIMR = 0 1 IRR1 0 R Data Frame Received Interrupt Flag Indicates that there are waiting data frames received. If at least one receive mailbox contains a waiting message, this bit is set. This bit is cleared when all bits in the receive message waiting register (RXPR) are cleared, i.e. there is no waiting message in any receive mailbox. A logical OR from each set receive mailbox. Writing to this bit is ignored. 0: Clearing condition: Clearing of all bits in RXPR 1: Data frame received and stored in mailbox Setting condition: When data is received and the corresponding MBIMR = 0 Rev. 3.0, 09/04, page 560 of 1086 Bit 0 Bit Name IRR0 Initial Value 1 R/W R/W Description Reset/Halt/Sleep Interrupt Flag Indicates that the CAN interface has been reset or halted and the HCAN is now in configuration mode or in sleep mode. An interrupt signal will be generated through this bit to notify the change of the HCAN's state to the host CPU if an MCR0 (software reset), MCR1 (halt), or MCR5 (sleep) request occurs. GSR can be read after this bit is set to figure out which state the HCAN is in. Important: When a sleep mode request needs to be made, halt mode should be used beforehand. For details, see the MCR5 description. 0: Clearing condition: Writing 1 1: Transition to software reset mode, transition to halt mode, or transition to sleep mode without halt mode Setting condition: When reset/halt processing is completed after an MCR0 (software reset), MCR1 (halt), or MCR5 (sleep) is requested 16.4.6 Interrupt Mask Register_n (IMR_n) (n = 0, 1) The interrupt mask register (IMR) is a 16-bit register that masks output of corresponding interrupt requests in the interrupt register (IRR). An interrupt request is masked if the corresponding bit is set to 1. This register can be read or written to at any time. IMR directly controls the generation of an interrupt request, but does not control the setting of the corresponding bit in IRR. • IMR Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR IMR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial Value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 3.0, 09/04, page 561 of 1086 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name IMR15 IMR14 IMR13 IMR12 IMR11 IMR10 IMR9 IMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0 Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Mask the corresponding IRR[15:0] interrupts. When this bit is set, the interrupt signal is masked, although the IRR setting is retained. 0: Corresponding IRR is not masked (an interrupt request is generated for interrupt conditions) 1: Corresponding IRR interrupt is masked 16.4.7 Transmit Error Counter_n (TEC_n) (n = 0, 1)/ Receive Error Counter_n (REC_n) (n = 0, 1) The transmit error counter (TEC)/receive error counter (REC) is a 16-bit readable/(writable) register that functions as a counter indicating the number of transmit/receive message errors on the CAN interface. The count value is stipulated in the CAN protocol specification (References 2 and 3). In normal mode, this register is read-only, and can only be modified by the CAN interface. This register can be cleared by a reset request (MCR0) or bus off. In test mode (i.e. MCR[15] = MCR[14] = 1), it is possible to write to this register. A same value can only be written to TEC and REC, and the value set in TEC is written to TEC and REC. When writing to this register, the HCAN needs to be in halt mode. This function is only intended for test purposes. [Important] While the HCAN-II is in the bus-off status, the TEC and REC values are undefined. Rev. 3.0, 09/04, page 562 of 1086 • TEC/REC Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEC TEC TEC TEC TEC TEC TEC TEC REC REC REC REC REC REC REC REC 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: * Bit Name TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Receive Error Counter This register is incremented if an error is detected during reception as specified on the CAN specification (see CAN specification document). Description Transmit Error Counter This register is incremented if an error is detected during transmission as specified on the CAN specification (see CAN specification document). It is only possible to write the value in test mode when MCR15 = MCR14 = 1. 16.5 HCAN Mailbox Registers The HCAN mailbox registers control individual mailboxes. The address is mapped as follows. Note: These registers can only be accessed in word size (16 bits). Rev. 3.0, 09/04, page 563 of 1086 Table 16.6 HCAN Mailbox Registers Channel 0 Address (Bytes) H'D020 H'D022 H'D024 H'D026 H'D028 H'D02A H'D02C H'D02E H'D030 H'D032 H'D034 H'D036 H'D038 H'D03A H'D03C H'D03E H'D040 H'D042 H'D044 H'D046 H'D048 H'D04A H'D04C H'D04E H'D050 H'D052 H'D054 H'D056 H'D058 H'D05A H'D05C H'D05E Unread message status register 1_0 Unread message status register 0_0 UMSR1_0 UMSR0_0 R/W R/W 16 Mailbox interrupt mask register 1_0 Mailbox interrupt mask register 0_0 MBIMR1_0 MBIMR0_0 R/W R/W 16 Remote frame receive pending register 1_0 Remote frame receive pending register 0_0 RFPR1_0 RFPR0_0 R/W R/W 16 Data frame receive pending register 1_0 Data frame receive pending register 0_0 RXPR1_0 RXPR0_0 R/W R/W 16 Abort acknowledge register 1_0 Abort acknowledge register 0_0 ABACK1_0 ABACK0_0 R/W R/W 16 Transmit acknowledge register 1_0 Transmit acknowledge register 0_0 TXACK1_0 TXACK0_0 R/W R/W 16 Transmit cancel register 1_0 Transmit cancel register 0_0 TXCR1_0 TXCR0_0 R/W R/W 16 Register Name Transmit pending request register 1_0 Transmit pending request register 0_0 Abbreviation R/W TXPR1_0 TXPR0_0 R/W R/W Access Size (Bits) 16 Rev. 3.0, 09/04, page 564 of 1086 Channel 1 Address (Bytes) H'D820 H'D822 H'D824 H'D826 H'D828 H'D82A H'D82C H'D82E H'D830 H'D832 H'D834 H'D836 H'D838 H'D83A H'D83C H'D83E H'D840 H'D842 H'D844 H'D846 H'D848 H'D84A H'D84C H'D84E H'D850 H'D852 H'D854 H'D856 H'D858 H'D85A H'D85C H'D85E Register Name Transmit pending request register 1_1 Transmit pending request register 0_1 Abbreviation R/W TXPR1_1 TXPR0_1 R/W R/W Access Size (Bits) 16 Transmit cancel register 1_1 Transmit cancel register 0_1 TXCR1_1 TXCR0_1 R/W R/W 16 Transmit acknowledge register 1_1 Transmit acknowledge register 0_1 TXACK1_1 TXACK0_1 R/W R/W 16 Abort acknowledge register 1_1 Abort acknowledge register 0_1 ABACK1_1 ABACK0_1 R/W R/W 16 Data frame receive pending register 1_1 Data frame receive pending register 0_1 RXPR1_1 RXPR0_1 R/W R/W 16 Remote frame receive pending register 1_1 Remote frame receive pending register 0_1 RFPR1_1 RFPR0_1 R/W R/W 16 Mailbox interrupt mask register 1_1 Mailbox interrupt mask register 0_1 MBIMR1_1 MBIMR0_1 R/W R/W 16 Unread message status register 1_1 Unread message status register 0_1 UMSR1_1 UMSR0_1 R/W R/W 16 Rev. 3.0, 09/04, page 565 of 1086 16.5.1 Transmit Pending Request Register n (TXPR0n, TXPR1n) (n = 0, 1) TXPR1 and TXPR0 are 16-bit readable/conditionally-writable registers that contain any transmit wait flags for the CAN module. TXPR1 controls mailbox 31 to mailbox 16, and TXPR0 controls mailbox 15 to mailbox 1. The host CPU makes a transmit message stored in a mailbox be in a transmit wait state by writing 1 to the corresponding bit. Writing 0 is ignored, and TXPR cannot be cleared by writing 0 and must be cleared by setting the corresponding TXCR bits. TXPR may be read by the host CPU to determine which, if any, transmissions are waiting. There is a transmit wait bit for all mailboxes except for mailbox 0. Writing 1 to a bit when the mailbox is set for reception is ignored, and TXPR is automatically cleared when an internal arbitration for transmission runs. The HCAN will clear a transmit wait flag after successful transmission of its corresponding message or when a transmission wait cancellation is requested successfully from TXCR. TXPR is not cleared if the message is not transmitted due to the CAN node losing the arbitration processing or due to errors on the CAN bus, and the HCAN automatically tries to transmit it again unless its DART bit (disable automatic re-transmission) is set in the message control of the corresponding mailbox. In such case (DART set) the transmission wait is cleared and notified through mailbox empty interrupt flag (IRR8) and the correspondent bit in the abort acknowledgement register (ABACK). If the status of TXPR changes, the HCAN shall ensure that in the ID priority scheme (MCR[2] = 0), the highest priority message is always presented for transmission in an intelligent way even under circumstances such as bus arbitration losses or errors on the CAN bus. For details, see section 16.7, Operation. When the HCAN changes the state of any TXPR bit to 0, a mailbox empty interrupt (IRR8) may be generated. This indicates that either a successful or an aborted mailbox transmission has just been made. If a message transmission is successful, it is indicated in TXACK, and if a message transmission abortion is successful, it is indicated in ABACK. By checking these registers, the contents of the message data of the corresponding mailbox is modified to prepare for the next transmission. Important: If mailbox 31 is used as a transmit buffer, there is a usage limitation. For details, see section 16.8, Usage Notes. Rev. 3.0, 09/04, page 566 of 1086 • TXPR1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXPR1[15:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit 15 to 0 Bit Name TXPR1[15:0] Initial Value 0 R/W R/W* Description Request the corresponding mailbox to transmit a CAN frame. Bits 15 to 0 correspond to mailboxes 31 to 16 respectively. When multiple bits are set, the order of the transmissions is determined by MCR2 (CAN-ID or mailbox number). 0: Corresponding mailbox is in transmit message idle state Clearing condition: Completion of message transmission or message transmission wait abortion (automatically cleared) 1: Transmission request made for corresponding mailbox Note: * Only 1 can be written to set a mailbox for transmission. Rev. 3.0, 09/04, page 567 of 1086 • TXPR0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXPR0[15:1] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit 15 to 1 Bit Name TXPR0[15:1] Initial Value 0 R/W R/W* Description Request the corresponding mailbox to transmit a CAN frame. Bits 15 to 1 correspond to mailboxes 15 to 1 respectively. When multiple bits are set, the order of the transmissions is determined by MCR2 (CAN-ID or mailbox number). 0: Corresponding mailbox is in transmit message idle state Clearing condition: Completion of message transmission or message transmission wait abortion (automatically cleared) 1: Transmission request made for corresponding mailbox 0  0 R Reserved This bit is always 0 as this is a receive-only mailbox. Writing 1 to this bit is ignored. The read value is not guaranteed. Note: * Only 1 can be written to set a mailbox for transmission. Rev. 3.0, 09/04, page 568 of 1086 16.5.2 Transmit Cancel Register n (TXCR1n, TXCR0n) (n = 0, 1) TXCR1 and TXCR0 are 16-bit readable/conditionally-writable registers. TXCR1 controls mailbox 31 to mailbox 16, and TXCR0 controls mailbox 15 to mailbox 1. This register is used by the host CPU to request the transmission wait messages in TXPR to be cancelled. To clear the corresponding bit in TXPR, the host CPU must write 1 to the bit in TXCR. Writing 0 is ignored. When transmission cancellation has succeeded, the CAN controller clears the corresponding TXPR and TXCR bits, and sets the corresponding ABACK bit. However, once a mailbox has started a transmission, it cannot be cancelled by this bit. In such a case, if the transmission finishes in success, the CAN controller clears the corresponding TXPR and TXCR bits, and sets the corresponding TXACK bit, however, if the transmission fails due to a bus arbitration loss or an error on the bus, the CAN controller clears the corresponding TXPR and TXCR bits, and sets the corresponding ABACK bit. If an attempt is made by the host CPU to cancel a mailbox transmission that is not transmit-waiting, it shall have no effect, and will be automatically cleared when an internal arbitration for transmission runs. Important: For details on the method of canceling a transmit wait, see section 16.7, Operation. Important: If mailbox 31 is used as a transmit buffer, there is a usage limitation. For details, see section 16.8, Usage Notes. • TXCR1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCR1[15:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit 15 to 0 Bit Name TXCR1[15:0] Initial Value 0 R/W R/W* Description Request the corresponding mailbox, that is in the queue for transmission, to cancel its transmission wait. Bits 15 to 0 correspond to mailboxes 31 to 16 and TXPR1[15:0] respectively. 0: Corresponding mailbox is in transmit message cancellation idle state Clearing condition: Completion of transmit wait cancellation (automatically cleared) 1: Transmit wait cancellation request made for corresponding mailbox Note: * 1 can be written only to a mailbox that is requested for transmission or set for transmission. Rev. 3.0, 09/04, page 569 of 1086 • TXCR0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCR0[15:1] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit 15 to 1 Bit Name TXCR0[15:1] Initial Value 0 R/W R/W* Description Request the corresponding mailbox, that is in the queue for transmission, to cancel its transmission wait. Bits 15 to 1 correspond to mailboxes 15 to 1 and TXPR0[15:1] respectively. 0: Corresponding mailbox is in transmit message cancellation idle state Clearing condition: Completion of transmit wait cancellation (automatically cleared) 1: Transmit wait cancellation request made for corresponding mailbox 0  0 R Reserved This bit is always 0 as this is a receive-only mailbox. Writing 1 to this bit is ignored. The read value is always 0. Note: * 1 can be written only to a mailbox that is requested for transmission or set for transmission. Rev. 3.0, 09/04, page 570 of 1086 16.5.3 Transmit Acknowledge Register n (TXACK1n, TXACK0n) (n = 0, 1) TXACK1 and TXACK0 are 16-bit readable/conditionally-writable registers. These registers notify the host CPU that a mailbox transmission has been successfully made. When a transmission has succeeded, the HCAN sets the corresponding bit in TXACK. The host CPU can clear a TXACK bit by writing 1 to the corresponding bit. Writing 0 is ignored. • TXACK1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXACK1[15:0] Initial Value: 0 R/W: R / 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit 15 to 0 Bit Name TXACK1[15:0] Initial Value 0 R/W R/WC1 Description Notify that the requested transmission of the corresponding mailbox has been finished successfully. Bits 15 to 0 correspond to mailboxes 31 to 16 respectively. 0: Clearing condition: Writing 1 1: Corresponding mailbox has successfully transmitted message (data or remote frame) Setting condition: Completion of message transmission for corresponding mailbox Rev. 3.0, 09/04, page 571 of 1086 • TXACK0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXACK0[15:1] Initial Value: 0 R/W: R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit 15 to 1 Bit Name TXACK0[15:1] Initial Value 0 R/W R/WC1 Description Notify that the requested transmission of the corresponding mailbox has been finished successfully. Bits 15 to 1 correspond to mailboxes 15 to 1 respectively. 0: Clearing condition: Writing 1 1: Corresponding mailbox has successfully transmitted message (data or remote frame) Setting condition: Completion of message transmission for corresponding mailbox 0 TXACK0[0] 0 R Reserved This bit is always 0 as this is a receive-only mailbox. Writing 1 to this bit is ignored. The read value is always 0. Rev. 3.0, 09/04, page 572 of 1086 16.5.4 Abort Acknowledge Register n (ABACK1n, ABACK0n) (n = 0, 1) ABACK1 and ABACK0 are 16-bit readable/conditionally-writable registers. These registers notify the host CPU that a mailbox transmission has been aborted as per its request. When an abort has succeeded, the HCAN sets the corresponding bit in ABACK. The host CPU can clear the ABACK bit by writing 1 to the corresponding bit. Writing 0 is ignored. An ABACK bit is used by the HCAN to acknowledge that a TXPR bit has been cleared by the corresponding TXCR bit. • ABACK1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ABACK1[15:0] Initial Value: 0 R/W: R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit 15 to 0 Bit Name ABACK1[15:0] Initial Value 0 R/W R/WC1 Description Notify that the requested transmit wait cancellation of the corresponding mailbox has been finished successfully. Bits 15 to 0 correspond to mailboxes 31 to 16 respectively. 0: Clearing condition: Writing 1 1: Corresponding mailbox has cancelled transmission of message (data or remote frame) Setting condition: Completion of transmit wait cancellation for corresponding mailbox Rev. 3.0, 09/04, page 573 of 1086 • ABACK0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ABACK0[15:1] Initial Value: 0 R/W: R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit 15 to 1 Bit Name ABACK0[15:1] Initial Value 0 R/W R/WC1 Description Notify that the requested transmit wait cancellation of the corresponding mailbox has been finished successfully. Bits 15 to 1 correspond to mailboxes 15 to 1 respectively. 0: Clearing condition: Writing 1 1: Corresponding mailbox has cancelled transmission of message (data or remote frame) Setting condition: Completion of transmit wait cancellation for corresponding mailbox 0 0 0 R Reserved This bit is always 0 as this is a receive-only mailbox. Writing 1 to this bit is ignored. The read value is always 0. 16.5.5 Data Frame Receive Pending Register n (RXPR1n, RXPR0n) (n = 0, 1) RXPR1 and RXPR0 are 16-bit readable/conditionally-writable registers. RXPR is a register that contains the data frame receive complete flags associated with receive mailboxes. When a CAN data frame is successfully stored in a receive mailbox, the corresponding bit is set in RXPR. The corresponding bit is cleared by writing 1. Writing 0 is ignored. However, the bit may only be set if the mailbox is set by its MBC (mailbox configuration) to receive data frames. When an RXPR bit is set, IRR1 (data frame receive interrupt flag) is also set if its MBIMR (mailbox interrupt mask register) is not set, and the interrupt signal is generated if IMR1 is not set. These bits are only set by receiving data frames and not by receiving remote frames. If a data frame is overwritten/overrun with a remote frame or vice versa, UMSR, RXPR, and RFPR will be set for the same mailbox. In this case the application needs to check the RTR bit within the mailbox control field to understand the nature of the message on the mailbox. Consequently when UMSR is set, both RXPR and RFPR should be checked and, if necessary, cleared. Rev. 3.0, 09/04, page 574 of 1086 • RXPR1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXPR1[15:0] Initial Value: 0 R/W: R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit 15 to 0 Bit Name RXPR1[15:0] Initial Value 0 R/W R/WC1 Description Set receive mailboxes corresponding to mailboxes 31 to 16 respectively. 0: Clearing condition: Writing 1 1: Corresponding mailbox has received a CAN data frame Setting condition: Completion of data frame reception in corresponding mailbox • RXPR0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXPR0[15:0] Initial Value: 0 R/W: R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit 15 to 0 Bit Name RXPR0[15:0] Initial Value 0 R/W R/WC1 Description Set receive mailboxes corresponding to mailboxes 15 to 0 respectively. 0: Clearing condition: Writing 1 1: Corresponding mailbox has received a CAN data frame Setting condition: Completion of data frame reception in corresponding mailbox Rev. 3.0, 09/04, page 575 of 1086 16.5.6 Remote Frame Receive Pending Register n (RFPR1n, RFPR0n) (n = 0, 1) RFPR1 and RFPR0 are 16-bit readable/conditionally-writable registers. RFPR is a register that contains the remote request flags associated with the receive mailboxes. When a CAN remote frame is successfully stored in a receive mailbox, the corresponding bit is set in RFPR. The corresponding bit is cleared by writing 1. Writing 0 is ignored. There is a bit for all mailboxes. However, the bit is only set if the mailbox is set by its MBC (mailbox configuration) to receive remote frames. When an RFPR bit is set, IRR2 (remote frame request interrupt flag) is also set if its MBIMR (mailbox interrupt mask register) is not set, and the interrupt signal is generated if IMR2 is not set. These bits are only set by receiving remote frames and not by receiving data frames. If a data frame is overwritten/overrun with a remote frame or vice versa, UMSR, RXPR, and RFPR will be set for the same mailbox. In this case the application needs to check the RTR bit within the mailbox control field to understand the nature of the message on the mailbox. Consequently when UMSR is set, both RXPR and RFPR should be checked and, if necessary, cleared. • RFPR1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFPR1[15:0] Initial Value: 0 R/W: R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit 15 to 0 Bit Name RFPR1[15:0] Initial Value 0 R/W R/WC1 Description Remote request wait flags for receive mailboxes 31 to 16. 0: Clearing condition: Writing 1 1: Corresponding mailbox has received a remote frame Setting condition: Completion of remote frame reception in corresponding mailbox Rev. 3.0, 09/04, page 576 of 1086 • RFPR0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFPR0[15:0] Initial Value: 0 R/W: R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit 15 to 0 Bit Name RFPR0[15:0] Initial Value 0 R/W R/WC1 Description Remote request wait flags for receive mailboxes 15 to 0. 0: Clearing condition: Writing 1 1: Corresponding mailbox has received a remote frame Setting condition: Completion of remote frame reception in corresponding mailbox 16.5.7 Mailbox Interrupt Mask Register n (MBIMR1n, MBIMR0n) (n = 0, 1) MBIMR1 and MBIMR0 are 16-bit readable/writable registers. MBIMR only masks IRR (IRR1: data frame receive interrupt, IRR2: remote frame request interrupt, IRR8: mailbox empty interrupt, and IRR9: message overflow interrupt) related to the mailbox activities. If a mailbox is set for reception, the generation of a receive interrupt (IRR1, IRR2, and IRR9) is masked but the setting of the corresponding bit in RXPR, RFPR, or UMSR is not modified. Similarly when a mailbox is set for transmission, the generation of an interrupt signal and setting of an mailbox empty interrupt due to successful transmission or abortion of transmission (IRR8) are masked, however, clearing the corresponding TXPR/TXCR bit and setting the TXACK bit for successful transmission are not masked, or clearing the corresponding TXPR/TXCR bit and setting the ABACK bit for abortion of the transmission are not masked. A mask is set by writing 1 to the corresponding bit for the mailbox activity to be masked. At a reset all mailbox interrupts are masked. Rev. 3.0, 09/04, page 577 of 1086 • MBIMR1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBIMR1[15:0] Initial Value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 to 0 Bit Name MBIMR1[15:0] Initial Value 1 R/W R/W Description Enable or disable interrupts requests from individual mailbox 31 to mailbox 16 respectively. 0: Interrupt request from IRR1/IRR2/IRR8/ IRR9 enabled 1: Interrupt request from IRR1/IRR2/IRR8/ IRR9 disabled • MBIMR0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBIMR0[15:0] Initial Value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 to 0 Bit Name MBIMR0[15:0] Initial Value 1 R/W R/W Description Enable or disable interrupt requests from individual mailbox 15 to mailbox 0 respectively. 0: Interrupt request from IRR1/IRR2/IRR8/ IRR9 enabled 1: Interrupt request from IRR1/IRR2/IRR8/ IRR9 disabled Rev. 3.0, 09/04, page 578 of 1086 16.5.8 Unread Message Status Register n (UMSR1n, UMSR0n) (n = 0, 1) UMSR1 and UMSR0 are 16-bit readable/writable registers that record the receive mailboxes whose contents have not been accessed by the host CPU prior to a new message being received. If the host CPU has not cleared the corresponding bit in RXPR/RFPR when a new message for a mailbox is received, the corresponding UMSR bit is set. This bit is cleared by writing 1. Writing 0 is ignored. If a mailbox is set for transmission, the corresponding UMSR bit cannot be set. • UMSR1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UMSR1[15:0] Initial Value: 0 R/W: R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ 0 R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit 15 to 0 Bit Name UMSR1[15:0] Initial Value 0 R/W R/WC1 Description Indicate that an unread message has been overwritten/overrun for mailboxes 31 to 16. 0: Clearing condition: Writing 1 1: Unread message is overwritten by a new message or overrun Setting Condition: When a new message is received before RXPR/RFPR is cleared. Rev. 3.0, 09/04, page 579 of 1086 • UMSR0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UMSR0[15:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit 15 to 0 Bit Name UMSR0[15:0] Initial Value 0 R/W R/WC1 Description Indicate that an unread message has been overwritten for mailboxes 15 to 0. 0: Clearing condition: Writing 1 1: Unread message is overwritten by a new message Setting Condition: When a new message is received before RXPR/RFPR is cleared. 16.6 Timer Registers The timer is a new function for the HCAN-II. The timer is 16 bits and supports several clock sources. It is divided by a prescale counter to reduce the clock speed. It also supports two input capture registers (ICR1 and ICR0) and three compare match registers (TCMR2, TCMR1, and TCMR0). The address map is as follows. Note: These registers can only be accessed in word size (16 bits). Rev. 3.0, 09/04, page 580 of 1086 Table 16.7 HCAN Timer Registers Address Channel (Bytes) 0 H'D080 H'D082 H'D084 H'D086 H'D088 H'D08A H'D08C H'D08E H'D090 H'D092 H'D094 H'D096 H'D098 H'D09A H'D09C H'D09E 1 H'D880 H'D882 H'D884 H'D886 H'D8D8 H'D88A H'D88C H'D88E H'D890 H'D892 H'D894 H'D896 H'D898 H'D89A H'D89C H'D89E Register Name Timer counter register 0 Timer control register_0 Timer status register_0 Timer drift correction register 0 Local offset register 0 Abbreviation TCNTR0 TCR_0 TSR_0 TDCR0 LOSR0 Access Size (Bits) 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Input capture register for cycle counter 0 ICR0-cc0 Input capture register for timer counter 0 Input capture register 1_0 Timer compare match register 0_0 Timer compare match register 1_0 Timer compare match register 2_0 Cycle counter register 0 Cycle maximum register 0 Timer mode register_0 Cycle counter double buffer 0 Input capture double buffer 0 Timer counter register 1 Timer control register_1 Timer status register_1 Timer drift correction register 1 Local offset register 1 ICR0-tm0 ICR1_0 TCMR0_0 TCMR1_0 TCMR2_0 CCR0 CMAX0 TMR_0 CCR_buf0 ICR0_buf0 TCNTR1 TCR_1 TSR_1 TDCR1 LOSR1 Input capture register for cycle counter 1 ICR0-cc1 Input capture register for timer counter 1 Input capture register 1_1 Timer compare match register 0_1 Timer compare match register 1_1 Timer compare match register 2_1 Cycle counter register 1 Cycle maximum register 1 Timer mode register_1 Cycle counter double buffer 1 Input capture double buffer 1 ICR0-tm1 ICR1_1 TCMR0_1 TCMR1_1 TCMR2_1 CCR1 CMAX1 TMR_1 CCR_buf1 ICR0_buf1 Rev. 3.0, 09/04, page 581 of 1086 Note: It is recommended that the timer should be disabled (TCR15 = 0) to change the setting of the registers related to the timer. 16.6.1 Timer Counter Register n (TCNTRn) (n = 0, 1) The timer counter register (TCNTR) is a 16-bit readable/writable register that allows the CPU to monitor and modify the value of the free-running timer counter. When the timer matches TCMR0 (timer compare match register 0) and TCR11 is set to 1, TCNTR is set to LOSR (local offset register) and counting starts again. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCNTR[15:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit 15 to 0 Note: * Bit Name TCNTR[15:0] Initial Value 0 R/W R/W* Description Indicate the value of the free-running timer. This register is cleared by the compare match condition. Rev. 3.0, 09/04, page 582 of 1086 16.6.2 Timer Control Register_n (TCR_n) (n = 0, 1) The timer control register (TCR) is a 16-bit readable/writable register that controls the operation of the timer. This register should be set before each periodical transmission or the deadline monitor register is set and the timer operation starts. Bit: 15 14 13 12 11 10 9 8 7 TCR7 6 5 4 3 2 1 0 TCR TCR TCR TCR TCR TCR TCR9 14 13 12 11 10 15 TPSC TPSC TPSC TPSC TPSC TPSC 5 4 3 2 1 0 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0  0  0  R/W: R/W R/W R/W R/W R/W R/W R/W  R/W  R/W R/W  Bit 15 Bit Name TCR15 Initial Value 0 R/W R/W Description Enable Timer When this bit is set, the timer runs. When this bit is cleared, the timer completes the current cycle (notified by timer overrun or a compare match condition on TCMR0) and is cleared to 0. 0: Timer stops running and is cleared at the end of current cycle 1: Timer is running Important: There is a failure on the timer function in the SH7058. This bit must be written to 0 not to activate the timer. 14 TCR14 0 R/W Disable ICR0 Enables or disables the input capture register 0 (ICR0). When this bit is enabled, the timer value is always captured every time a start of frame (SOF) is output to the CAN bus, whether the HCAN is a transmitter or receiver. When this bit is disabled, the value of ICR0 remains latched. 0: ICR0 is disabled and holds the current value Clearing condition:TCR9 = 1 when CAN-ID of receive message is equal to the ID of a mailbox with CCM set 1: ICR0 is enabled and captures the timer value at every SOF Rev. 3.0, 09/04, page 583 of 1086 Bit 13 Bit Name TCR13 Initial Value 0 R/W R/W Description Timestamp Control for Reception Specifies whether the timestamp in the message control of each mailbox is recorded at the start of frame (SOF) or end of frame (EOF) when a message is received. This bit selects the trigger for the input capture register 1 (ICR1) that is used to timestamp for transmit mailboxes. 0: Timestamp is recorded at the SOF of every message received 1: Timestamp is recorded at the EOF of every message received Important: The timestamp recorded at the SOF of every message received is not supported by the SH7058. When a receive timestamp is used, this bit should be set to 1. 12 TCR12 0 R/W Timestamp Control for Transmission Specifies whether the timestamp of each transmit mailbox is recorded at the point that the corresponding TXPR bit is set or the corresponding TXACK bit is set when a transmit request is made. This bit selects the trigger for the input capture register 1 (ICR1) that is used for timestamp of receive mailboxes. The input capture register 1 (ICR1) is used for timestamp, regardless of whether ICR0 is enabled or disabled. 0: Timestamp is recorded at the point that the TXPR bit is set for message transmission 1: Timestamp is recorded at the point that the TXACK bit is set for message transmission 11 TCR11 0 R/W Timer Clear/Set Control by TCMR0 Specifies whether the timer is to be cleared and set to LOSR when TCMR0 matches TCNTR. TCMR0 is also capable of generating an interrupt signal to the host CPU via IRR15. 0: Timer is not cleared by TCMR0 1: Timer is cleared by TCMR0 Rev. 3.0, 09/04, page 584 of 1086 Bit 10 Bit Name TCR10 Initial Value 0 R/W R/W Description Timer Clear/Set Control by CCM Specifies whether the timer is to be cleared and set to LOSR by the CAN-ID compare match for receive mailboxes. When a mailbox stores a receive message, the timer counter (TCNTR) is automatically cleared and set to LOSR, if the CCM bit of the corresponding mailbox and this bit are set. CCM is not capable of generating an interrupt signal since this is performed by the message receive interrupt (IRR1) or remote frame request interrupt (IRR2). 0: Timer is not cleared/set by CCM 1: Timer is cleared and set to LOSR by CCM 9 TCR9 0 R/W ICR0 Automatic Disable by CCM Specifies whether ICR0 is to be disabled by the CAN-ID compare match (CCM) for receive mailboxes. When a mailbox stores a receive message, bit 14 of this register (TCR14) is automatically cleared and the value of ICR0 is retained, if the CCM bit of the corresponding mailbox and this bit are set. 0: TCR14 is not cleared by CCM 1: TCR14 is automatically cleared by CCM 8 — 0  Reserved Writing 0 to this bit is ignored. The read value is not guaranteed. 7 TCR7 0 R/W Drift Correction Control Specifies whether TCNTR is to be incremented by 2 or 0 every time TCNTR reaches the cycle specified by TDCR. If this function is not required, TDCR must be set to H'0000. 0: Timer is incremented by 0 (i.e. retains the same value for one clock cycle) every cycle specified by TDCR. 1: Timer is incremented by 2 every cycle specified by TDCR (see TDCR description). 6 — 0  Reserved Writing 0 to this bit is ignored. The read value is not guaranteed. Rev. 3.0, 09/04, page 585 of 1086 Bit 5 4 3 2 1 0 Bit Name TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Initial Value 0 0 0 0 0 0 R/W R/W R/W     Description HCAN-II Timer Prescaler Divide the source clock (2 • HCAN peripheral clock) before it is used for the timer. The following relationship exists between source clocks and the timer 000000: 1 • source clock 000001: 2 • source clock 000010: 4 • source clock 000011: 6 • source clock 000100: 8 • source clock : 111111: 126 • source clock 16.6.3 Timer Status Register_n (TSR_n) (n = 0, 1) The timer status register (TSR) is a 16-bit read-only register that allows the host CPU to monitor the timer compare match status and the timer overrun status. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSR TSR TSR TSR TSR 4 3 2 1 0 Initial Value: 0 R/W:  Bit 15 to 5 Bit Name — 0  0  0  0  0  R/W  0  0  0  0  0  0 R 0 R 0 R 0 R 0 R Initial Value 0 Description Reserved Writing 0 to this bit is ignored. The read value is not guaranteed. 4 to 0 TSR[4:0] 0 R These bits are read-only that allow the CPU to monitor the status of the cycle counter, the timer, and the compare match registers. Writing to these bits is ignored. Rev. 3.0, 09/04, page 586 of 1086 Bit 4 Bit Name TSR4 Initial Value 0 R/W R Description Cycle Counter Overflow Flag Indicates that the cycle counter has reached its maximum value and is reset to H'0. Setting CMAX = 0 makes the cycle counter be disabled and TSR4 be always cleared to 0. 0: Cycle counter has not overflow Clearing condition: Writing 1 to IRR10 (cycle counter overflow interrupt) 1: Cycle counter has overflow Setting condition: When the cycle counter value changes from the maximum value (CMAX) to H'0 3 TSR3 0 R Timer Compare Match Flag 2 Indicates that a compare-match condition occurred to the timer compare match register 2 (TCMR2). When the value set in TCMR2 matches the timer value (TCMR2 = TCNTR), this bit is set. This bit is not set if the TCMR2 value is H'0000. Also, this bit is read-only and is cleared when IRR11 (timer compare match interrupt 2) is cleared. 0: Timer compare match has not occurred to TCMR2 Clearing condition: Writing 1 to IRR11 (timer compare match interrupt 2) 1: Timer compare match has occurred to TCMR2 Setting condition: TCMR2 matches the timer value (TCMR2 = TCNTR) Rev. 3.0, 09/04, page 587 of 1086 Bit 2 Bit Name TSR2 Initial Value 0 R/W R Description Timer Compare Match Flag 1 Indicates that a compare-match condition occurred to the timer compare match register 1 (TCMR1). When the value set in TCMR1 matches the timer value (TCMR1 = TCNTR), this bit is set. This bit is not set if the TCMR1 value is H'0000. Also, this bit is read-only and is cleared when IRR15 (timer compare match interrupt 1) is cleared. 0: Timer compare match has not occurred to TCMR1 Clearing condition: Writing 1 to IRR15 (timer compare match interrupt 1) 1: Timer compare match has occurred to TCMR1 Setting condition: TCMR1 matches the timer value (TCMR1 = TCNTR) 1 TSR1 0 R Timer Compare Match Flag 0 Indicates that a compare-match condition occurred to the timer compare match register 0 (TCMR0). When the value set in TCMR0 matches the timer value (TCMR0 = TCNTR), this bit is set. This bit is not set if the TCMR0 value is H'0000. Also, this bit is read-only and is cleared when IRR14 (timer compare match interrupt 0) is cleared. 0: Timer compare match has not occurred to TCMR0 Clearing condition: Writing 1 to IRR14 (timer compare match interrupt 0) 1: Timer compare match has occurred to TCMR0 Setting condition: TCMR0 matches the timer value (TCMR0 = TCNTR) 0 TSR0 0 R Timer Overrun Flag Indicates that the timer has overrun and is reset to H'0000. This bit is set even when TCMR0 is set to H'FFFF and is enabled to clear the timer value. 0: Timer has not overrun Clearing condition: Writing 1 to IRR13 (timer overrun interrupt) 1: Timer has overrun Setting condition: When the timer value changes the value from H'FFFF to H'0000 Rev. 3.0, 09/04, page 588 of 1086 16.6.4 Timer Mode Register_n (TMR_n) (n = 0, 1) The timer mode register (TMR) is a 16-bit readable/writable register that specifies the value to be used for the timer functions. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMR TMR TMR 3 2 1 Initial Value: 0 R/W:  Bit 15 to 4 Bit Name — 0  0  0  0  0  R/W — 0  0  0  0  0  0 0 0 0 0  R/W R/W R/W  Initial Value 0 Description Reserved Writing 0 to this bit is ignored. The read value is not guaranteed. 3 TMR3 0 R/W Timestamp Value Specifies whether the timestamp for transmission and reception contains the timer value (TCNTR) or the value of Cycle_Counter + TCNTR[15:4]. This function is very useful for time triggered transmission. 0: TCNTR[15:0] is used for the timestamp 1: Cycle_Counter + TCNTR[15:4] is used for the timestamp 2 TMR2 0 R/W TCMR2 Control Specifies whether the timer compare match 2 is compared with the timer value (TCNTR) or with Cycle_Counter + TCNTR[15:4]. 0: TCNTR[15:0] is used for a compare match 1: Cycle_Counter + TCNTR[15:4] is used for a compare match 1 TMR1 0 R/W TCMR1 Control Specifies whether the timer compare match 1 is compared with the timer value (TCNTR) or with Cycle_Counter + TCNTR[15:4]. 0: TCNTR[15:0] is used for a compare match 1: Cycle_Counter + TCNTR[15:4] is used for a compare match 0 — 0 — Reserved Writing 0 to this bit is ignored. The read value is not guaranteed. Rev. 3.0, 09/04, page 589 of 1086 16.6.5 Timer Drift Correction Register n (TDCRn) (n = 0, 1) The timer drift correction register (TDCR) is a 16-bit readable/writable register. The purpose of this register is to adjust the drift of the timer caused by a different clock running at other CAN nodes on the same system. When TCNTR reaches to the cycle specified by this register, the timer value is incremented by 2 or 0 (i.e. retains the same value). This register does not point at a specific time nor a specific cycle. This means, if TCNTR/2 > TDCR, the drift correction will be performed more than twice (unless TCMR0 is used to clear TCNTR before it reaches the second cycle). When TDCR is set to H'0000, the drift correction will not be performed at all. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TDCR[15:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 to 0 Bit Name TDCR[15:0] Initial Value 0 R/W R/W Description Timer Drift Correction Register Set the value of the cycle to adjust the drift of the timer. Important: For a proper operation of the timer, the maximum value must be TDCR 105°C VRAM — 2.4 1.1 — 30 — µA V VCC [Operating precautions] 1. When the A/D converter is not used (including during standby), do not leave the AVCC, AVref, and AVSS pins open. 2. The current consumption is measured when VIHmin = VCC – 0.5 V/PVCC – 0.5 V, VIL = 0.5 V, with all output pins unloaded. 3. The guaranteed operating range of power supply PVCC1 in the MCU expanded modes is only PVCC1 = 3.3 V ±0.3 V. Do not use a voltage outside this range. 4. The guaranteed operating range of power supply PVCC1 in MCU single-chip mode is only PVCC1 = 5.0 V ±0.5 V. Do not use a voltage outside this range. Rev. 3.0, 09/04, page 974 of 1086 Table 27.5 Permitted Output Current Values Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) Symbol IOL Σ IOL IOH Σ IOL Min — — — — Typ — — — — Max 6.0 80 2.0 25 Unit mA mA mA mA [Operating precautions] To assure LSI reliability, do not exceed the output values listed in this table. 27.3 27.3.1 AC Characteristics Timing for swicthing the power supply on/off Table 27.6 Timing for swicthing the power supply on/off Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item Time taken to switch VCC on VCC hold-time when PVCC is swtched off Symbol tVCCS tVCCH Min 0 0 Max — — Unit ms ms Figures Figure 27.1 Rev. 3.0, 09/04, page 975 of 1086 VCC PLLVCC VCC min tVCCS tVCCH VCC min PVCC1 PVCC2 PVCC min PVCC min Figure 27.1 Power-On/Off Timing 27.3.2 Clock timing Table 27.7 shows the clock timing. Table 27.7 Clock Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item Clock frequency Clock cycle time Clock low-level pulse width Clock high-level pulse width Clock rise time Clock fall time EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input low-level pulse width EXTAL clock input rise time EXTAL clock input fall time Reset oscillation settling time Standby return clock settling time Symbol fop tcyc t t t t CL Min 10 50 12 12 — — 5 100 30 30 — — 30 30 Max 20 100 — — 10 10 10 200 — — 8 8 — — Unit MHz ns ns ns ns ns MHz ns ns ns ns ns ms ms Figures Figure 27.2 CH CR CF f t EX Figure 27.3 EXcyc t t t EXL EXH EXR t EXF tosc1 tosc2 Figure 27.4 The CK pin outputs the peripheral clock signal (Pφ). Rev. 3.0, 09/04, page 976 of 1086 [Operating precautions] The EXTAL, XTAL, and CK pins constitute a circuit requiring a power supply voltage of VCC = 3.3 V ±0.3 V. Comply with the input and output voltages specified in the DC characteristics. tcyc tCH tCL VOH 1/2VCC CK 1/2VCC VOH VOH VOL tCF VOL tCR Note: CK pin is VCC = 3.3 V ±0.3 V power supply circuit. Figure 27.2 Peripheral Clock Timing tEXcyc tEXH VIH 1/2VCC VIH VIL tEXF VIL tEXL EXTAL VIH 1/2VCC tEXR Note: EXTAL pin is VCC = 3.3 V ±0.3 V power supply circuit. Figure 27.3 EXTAL Clock Input Timing Rev. 3.0, 09/04, page 977 of 1086 CK VCC PVCC1 PVCC2 VCC min tosc2 PVCC min VIH tosc1 tosc1 Figure 27.4 Oscillation Settling Time 27.3.3 Control Signal Timing Table 27.8 shows control signal timing. Table 27.8 Control Signal Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item RES pulse width RES setup time MD2 to MD0 setup time 2* NMI setup time IRQ7–IRQ0 setup time* (edge detection) 2 2 1 Symbol tRESW tRESS tMDS tNMIS tIRQES tIRQLS tNMIH tIRQEH tIRQOD tBRQS tBACKD1 tBACKD2 tBZD Min 10 30 10 30 30 30 30 30 — 30 — — — Max — — — — — — — — 100 — 30 30 30 Unit tcyc ns tcyc ns ns ns ns ns ns ns ns ns ns Figures Figure 27.5 Figure 27.6 IRQ7–IRQ0 setup time* (level detection) NMI hold time IRQ7–IRQ0 hold time IRQOUT output delay time Bus request setup time Bus acknowledge delay time 1 Bus acknowledge delay time 2 Bus three-state delay time Figure 27.7 Figure 27.8* 3 Rev. 3.0, 09/04, page 978 of 1086 [Operating precautions] 1. Mode setup time during power-on reset by the RES pin depends on the combination of signals to be input to the FWE and MD2 to MD0 pins. If a low-level signal is input to the RES pin while this LSI operates by inputting a mode specified in table 27.3 to the FWE and MD2 to MD0 pins, the mode setup time is defined by tMDS2. If a signal other than the combination of signals specified in table 27.3 (undefined mode) is input to the FWE and MD2 to MD0 pins, the mode setup time is defined by tMSD1. See section 27.6.2, Notes on Mode Pin Input. 2. The RES, NMI, and IRQ7–IRQ0 signals are asynchronous inputs, but when the setup times shown here are provided, the signals are considered to have been changed at clock fall. If the setup times are not provided, recognition is delayed until the next clock rise or fall. 3. The guaranteed operating range of power supply PVCC1 in the MCU expanded modes is only PVCC1 = 3.3 V ±0.3 V. Do not use a voltage outside this range. CK tRESS tRESW VIL = 0.5 V tMD0 tRESS VOH VIH = VCC – 0.5 V VIH = VCC – 0.5 V VIL = 0.5 V VIH = VCC – 0.5 V MD2-0 VIL = 0.5 V Note: pin is controlled by VIL and VIH shown above. Figure 27.5 Reset Input Timing Rev. 3.0, 09/04, page 979 of 1086 CK VOL VOL tNMIH VIH = VCC – 0.5 V NMI VIL = 0.5 V tIRQEH edge tNMIS VIH = VCC – 0.5 V VIL = 0.5 V tIRQES VIH VIL tIRQLS level VIL Note: NMI pin is controlled by VIL and VIH shown above. Figure 27.6 Interrupt Signal Input Timing CK VOH tIRQOD VOH VOL tIRQOD Figure 27.7 Interrupt Signal Output Timing Rev. 3.0, 09/04, page 980 of 1086 VOH CK tBRQS (input) VOH VOL VOH tBRQS VIH tBACKD1 tBACKD2 VOH VOL (output) tBZD , , , Hi-Z tBZD A21–A0, D15–D0 Hi-Z VOL Figure 27.8 Bus Right Release Timing Rev. 3.0, 09/04, page 981 of 1086 27.3.4 Bus Timing Table 27.9 shows bus timing. Table 27.9 Bus Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item Address delay time CS delay time 1 CS delay time 2 Read strobe delay time 1 Read strobe delay time 2 Read data setup time Read data hold time Write strobe delay time 1 Write strobe delay time 2 Write data delay time Write data hold time WAIT setup time WAIT hold time Read data access time Access time from read strobe Write address setup time Write address hold time Symbol tAD tCSD1 tCSD2 tRSD1 tRSD2 tRDS tRDH tWSD1 tWSD2 tWDD tWDH tWTS tWTH tACC tOE tAS tWR Min — — — — — 15 0 — — — tcyc × m 15 0 tcyc × (n+1.5)-39 tcyc × (n+1.0)-39 0 5 Max 35 30 30 30 30 — — 30 30 30 — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figures 27.9, 27.10 Figure 27.11 Figures Figures 27.9, 27.10 n: Number of waits m = 1: CS assertion extension cycle m = 0: Normal cycle (CS assertion non-extension cycle) [Operating precautions] The guaranteed operating range of power supply PVCC1 in the MCU expanded modes is only PVCC1 = 3.3 V ±0.3 V. Do not use a voltage outside this range. Rev. 3.0, 09/04, page 982 of 1086 T1 VOH CK tAD A21–A0 tCSD1 VOL T2 tCSD2 tRSD1 tOE tRSD2 (read) tACC D15–D0 (read) tWSD1 tAS tWDD D15–D0 (write) tWDH tWSD2 tWR tRDS tRDH (write) Note: tRDH: Specified from the negate timing of A21–A0, , or , whichever is first. Figure 27.9 Basic Cycle (No Waits) Rev. 3.0, 09/04, page 983 of 1086 T1 VOH CK tAD A21–A0 tCSD1 VOL TW T2 tCSD2 tRSD1 tOE tRSD2 (read) tACC D15–D0 (read) tWSD1 tAS tWDD D15–D0 (write) tWDH tWSD2 tWR tRDS tRDH (write) Note: tRDH: Specified from the negate timing of A21–A0, , or , whichever is first. Figure 27.10 Basic Cycle (One Software Wait) Rev. 3.0, 09/04, page 984 of 1086 T1 CK TW TW TWO T2 A21–A0 (read) D15–D0 (read) (write) D15–D0 (write) tWTS tWTH tWTS tWTH Note: tRDH: Specified from the negate timing of A21–A0, , or , whichever is first. WAIT Figure 27.11 Basic Cycle (Two Software Waits + Waits by WAIT Signal) Rev. 3.0, 09/04, page 985 of 1086 27.3.5 Advanced Timer Unit Timing and Advance Pulse Controller Timing Table 27.10 shows advanced timer unit timing and advanced pulse controller timing. Table 27.10 Advanced Timer Unit Timing and Advanced Pulse Controller Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item Output compare output delay time Input capture input setup time PULS output delay time Timer clock input setup time Timer clock pulse width (single edge specified) Timer clock pulse width (both edges specified) Symbol tTOCD tTICS tPLSD tTCKS tTCKWH/L tTCKWH/L Min — 24 – 24 1.5 2.5 Max 100 — 100 — — — Unit ns ns ns ns tcyc tcyc Figure 27.13 Figures Figure 27.12 VOH CK tTOCD Timer output tTICS Input capture input PULS output tPLSD VOL VOL Figure 27.12 ATU Input/Output Timing and APC Output Timing Rev. 3.0, 09/04, page 986 of 1086 CK tTCKS VOL tTCKS VOL TCLKA, TCLKB tTCKWL tTCKWH Figure 27.13 ATU Clock Input Timing 27.3.6 I/O Port Timing Table 27.11 shows I/O port timing. Table 27.11 I/O Port Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ± 0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item Port output data delay time Port input hold time Port input setup time Symbol tPWD tPRH tPRS Min — 30 30 Max 100 — — Unit ns ns ns Figures Figure 27.14 [Operating precautions] The guaranteed operating range of power supply PVCC1 in MCU single-chip mode is only PVCC1 = 5.0 V ±0.5 V. Do not use a voltage outside this range. CK tPRS Port (read) tPWD Port (write) tPRH Figure 27.14 I/O Port Input/Output timing Rev. 3.0, 09/04, page 987 of 1086 27.3.7 Watchdog Timer Timing Table 27.12 shows watchdog timer timing. Table 27.12 Watchdog Timer Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item WDTOVF delay time Symbol tWOVD Min — Max 100 Unit ns Figures Figure 27.15 CK VOH tWOVD VOH tWOVD Figure 27.15 Watchdog Timer Timing Rev. 3.0, 09/04, page 988 of 1086 27.3.8 Serial Communication Interface Timing Table 27.13 shows serial communication interface timing. Table 27.13 Serial Communication Interface Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item Clock cycle Clock cycle (clock sync) Clock pulse width Input clock rise time Input clock fall time Transmit data delay time Transmit data setup time Transmit data hold time Symbol tscyc tscyc tsckw tsckr tsckf tTxD tRxS tRxH Min 4 6 0.4 — — — 100 100 Max — — 0.6 1.5 1.5 100 — — Unit tcyc tcyc tscyc tcyc tcyc ns ns ns Figure 27.17 Figures Figure 27.16 tsckw VIH SCK0–SCK4 VIH VIL VIL tsckr VIH VIH tsckf VIL tscyc Figure 27.16 SCI Input/Output Timing Rev. 3.0, 09/04, page 989 of 1086 tscyc SCK0 SCK4 (input/output) tTxD TxD0 TxD4 (transmit data) tRxS RxD0 RxD4 (receive data) SCI input/output timing (synchronous mode) tRxH VOH CK tTxD TxD0 TxD4 (transmit data) VOH tRxS RxD0 RxD4 (receive data) tRxH SCI input/output timing (asynchronous mode) Figure 27.17 SCI Input/Output Timing Rev. 3.0, 09/04, page 990 of 1086 27.3.9 HCAN Timing Table 27.14 shows HCAN timing. Table 27.14 HCAN Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item Transmit data delay time Transmit data setup time Transmit data hold time Symbol tHTxD tHRxS tHRxH Min — 100 100 Max 100 — — Unit ns ns ns Figures Figure 27.18 VOH CK tHTxD HTxD0, HTxD1 (transmit data) VOH tHRxS HRxD0, HRxD1 (receive data) tHRxH Figure 27.18 HCAN Input/Output timing Rev. 3.0, 09/04, page 991 of 1086 27.3.10 A/D Converter Timing Table 27.15 shows A/D converter timing. Table 27.15 A/D Converter Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. CSK = 0: fop = T.B.D. Item External trigger input start delay time A/D conversion time A/D conversion start delay time Input sampling time ADEND output delay time Symbol tTRGS tCONV tD tSPL tADENDD Min 50 259 10 — — Typ — — — 64 — Max — 266 17 — 100 Min 50 131 6 — — CSK = 1: fop = T.B.D. Typ — — — 32 — 100 Max — 134 9 Unit ns tcyc tcyc tcyc ns Figure Figure 27.19 Figure 27.20 CK VOL VOL input tTRGS ADCR (ADST = 1 set) Figure 27.19 External Trigger Input Timing Rev. 3.0, 09/04, page 992 of 1086 tCONV tD Write cycle A/D synchronization time (3 states) (up to 14 states) CK tSPL Address Analog input sampling signal ADF VOH CK VOH tADENDD tADENDD ADEND Figure 27.20 Analog Conversion Timing Rev. 3.0, 09/04, page 993 of 1086 27.3.11 H-UDI Timing Table 27.16 shows H-UDI timing. Table 27.16 H-UDI Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item TCK clock cycle TCK clock high-level width TCK clock low-level width TRST pulse width TRST setup time TMS setup time TMS hold time TDI setup time TDI hold time TDO delay time 1 TDO delay time 2 Symbol ttcyc tTCKH tTCKL tTRSW tTRSS tTMSS tTMSH tTDIS tTDIH tTDOD1 tTDOD2 Min 2 0.4 0.4 20 30 30 10 30 10 — — Max — 0.6 0.6 — — — — — — 30 30 Unit ttcyc ttcyc ttcyc tcyc ns ns ns ns ns ns ns Figure 27.24 Figure 27.23 Figure 27.22 Figures Figure 27.21 [Operating precautions] The H-UDI pins constitute a circuit requiring the voltage of VCC = 3.3 V ±0.3 V. Comply with the input and output voltages specified in the DC characteristics, for operation. tTCKH VIH TCK VIL ttcyc VIL VIH tTCKL VIH Figure 27.21 H-UDI Clock Timing Rev. 3.0, 09/04, page 994 of 1086 TCK tTRSS VIL tTRSS VIL VIL tTRSW VIL TRST Figure 27.22 H-UDI TRST Timing VIH TCK VIL tTMSS TMS tTDIS TDI tTDOD TDO tTDOD tTDIH tTMSH VIH Figure 27.23 H-UDI Input/Output Timing VIH TCK VIL tTMSS TMS tTDIS TDI tTDOD2 TDO tTDOD2 tTDIH tTMSH VIL VIL Figure 27.24 H-UDI Input/Output Timing (Instruction Corresponding to IEEE1149.1 is Executed) Rev. 3.0, 09/04, page 995 of 1086 27.3.12 AUD Timing Table 27.17 shows AUD timing. Table 27.17 AUD Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item AUDRST pulse width (Branch trace) AUDRST pulse width (RAM monitor) AUDMD setup time (Branch trace) AUDMD setup time (RAM monitor) Branch trace clock cycle Branch trace clock duty Branch trace data delay time Branch trace data hold time Branch trace SYNC delay time Branch trace SYNC hold time RAM monitor clock cycle RAM monitor clock low pulse width RAM monitor output data delay time RAM monitor output data hold time RAM monitor input data setup time RAM monitor input data hold time RAM monitor SYNC setup time RAM monitor SYNC hold time Symbol tAUDRSTW tAUDRSTW tAUDMDS tAUDMDS tBTCYC tBTCKW tBTDD tBTDH tBTSD tBTSH tRMCYC tRMCKW tRMDD tRMDHD tRMDS tRMDH tRMSS tRMSH Min 10 5 10 5 1 40 — 0 — 0 100 45 7 5 20 5 20 5 Max — — — — 1 60 40 — 40 — — — tRMCYC – 20 — — — — — Unit tcyc tRMCYC tcyc tRMCYC tcyc % ns ns ns ns ns ns ns ns ns ns ns ns Figure 27.27 Figure 27.26 Figures Figure 27.25 Load conditions: AUDCK (branch trace): CL = 30 pF: otherwise CL = 100 pF AUDSYNC: CL = 100 pF AUDATA3 to AUDATA0: CL = 100 pF Rev. 3.0, 09/04, page 996 of 1086 tcyc CK (Branch trace) tRMCYC AUDCK (input) (RAM monitor) tAUDRSTW tAUDMDS AUDMD Figure 27.25 AUD Reset Timing tBTCKW AUDCK (output) tBTDD AUDATA3 to AUDATA0 (output) tBTDH tBTCYC tBTSD tBTSH (output) Figure 27.26 Branch Trace Timing tRMCYC AUDCK (input) tRMDD AUDATA3 to AUDATA0 (output) AUDATA3 to AUDATA0 (input) tRMSS (input) tRMSH tRMDHD tRMCKW tRMDS tRMDH Figure 27.27 RAM Monitor Timing Rev. 3.0, 09/04, page 997 of 1086 27.3.13 UBC Trigger Timing Table 27.18 shows UBC trigger timing. Table 27.18 UBC Trigger Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item UBCTRG delay time Symbol tUBCTGD Min — Max 35 Unit ns Figures Figure 27.28 VOH CK tUBCTGD Note: See section 8.5.7, Internal Clock ( ) Multiplication Ratio and Pulse Width. Figure 27.28 UBC Trigger Timing Rev. 3.0, 09/04, page 998 of 1086 27.3.14 Measuring Conditions for AC Characteristics Input reference levels Output reference level High level: VIH min. value, low level: VIL max. value High level: 2.0 V, Low level: 0.8 V IOL LSI output pin DUT output CL V VREF IOH CL is a total value that includes the measuring instrument capacitance. The following CL values are used: 30 pF: 50 pF: 100 pF: 30 pF: Ð , , , , AUDCK CK, A21–A0, D15–D0, , , , TDO AUDATA3–0, AUDSYNC All port pins other than the above, and peripheral module output pins. IOL and IOH are the condition for the IOL = 1.6 mA, IOH = 200 µA. Figure 27.29 Output Test Circuit Rev. 3.0, 09/04, page 999 of 1086 27.4 A/D Converter Characteristics Table 27.19 shows A/D converter characteristics. Table 27.19 A/D Converter Characteristics Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. CSK = 0: fop = 10 to 20 MHz Item Resolution A/D conversion time Analog input capacitance Permitted analog signal source impedance Non-linear error Offset error Full-scale error Quantization error Absolute error Notes: 1. Ta ≤ 105°C 2. Ta > 105°C Min 10 — — — — — — — — Typ 10 — — — — — — — — Max 10 13.3 20 3 ±1.5* 2 ±2.0* 1 CSK = 1: fop =10 MHz Min 10 — — — — — — — 1 Typ 10 — — — — — — — — Max 10 13.4 20 3 ±1.5* 2 ±2.0* 1 Unit bit µs pF kΩ LSB LSB LSB LSB 1 ±1.5* 2 ±2.0* 1 ±1.5* 2 ±2.0* 1 ±1.5* 2 ±2.0* 1 ±1.5* 2 ±2.0* 1 ±0.5 ±2.0* 2 ±2.5* ±0.5 ±2.0* 2 ±2.5* — LSB Rev. 3.0, 09/04, page 1000 of 1086 27.5 Flash Memory Characteristics Table 27.20 shows the flash memory characteristics. Table 27.20 Flash Memory Characteristics Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V, PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C. When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = –40°C to 85°C. Item Programming time* * * Erase time* * * Notes: 1. 2. 3. 4. 135 124 Symbol tP tE NWEC Min — — 100 Typ 3 2 — Max 200 20 — Unit ms/128 bytes s/block Times Reprogramming count Use the on-chip programming/erasing routine for programming/erasure. When all 0 are programmed. 128 kbytes of block The total reprogramming time (programming time + erasing time) is as follows. 40 s (typ.), reference value: 60 s, 80 s (max.) However, 90% of the values are within the reference value. 5. tP, tE distributes focusing on near the typ. value. Rev. 3.0, 09/04, page 1001 of 1086 27.6 27.6.1 Usage Note Notes on Connecting External Capacitor for Current Stabilization The SH7058 includes an internal step-down curcuit to automatically reduce the microporocessor power supply voltage to an appropriate level. Between this internal stepped-down power supply (VCL pin) and the VSS pin, an capacitor (0.33 to 0.47 µF) for stabilizing the internal voltage. Connection of the external capacitor is shown in figure 27.30. The external capacitor should be located near the pin. Do not apply any power supply voltage to the VCL pin. External power-supply stabilizing capacitor One 0.33 to 0.47 µF capacitor VCL One 0.33 to 0.47 µF capacitor VSS VCL VSS VCL One 0.33 to 0.47 µF capacitor VSS Do not apply any power supply voltage to the VCL pin. Use multilayer ceramics capacitors (one 0.33 to 0.47 µF capacitor for each VCL pin), which should be located near the pin. Figure 27.30 Connection of VCL Capacitor 27.6.2 Notes on Mode Pin Input This electrical characteristics are specified for the combination of mode pins (FWE, MD2 to MD0) specified in table 27.3. Characteristics of combinations other than those in table 27.3 cannot be guaranteed. When power is supplied and in hardware standby mode, mode setup time is determined by tMDS1. When power-on reset is performed only by the RES pin, mode setup time is differs according to the combination of input to the FWE and MD2 to MD0. When low is input to the RES pin with the pins FWE and MD2 to MD0 operated in mode specified in table 27.3, the mode setup time is determined by tMDS2. When combination which is not specified in table 27.3 is input, the mode setup time is determined by tMDS1. Rev. 3.0, 09/04, page 1002 of 1086 Table 27.21 Mode Pin Input Timing Item Mode setup time 1 Mode setup time 2 Symbol tMDS1 tMDS2 Min 30 10 Typ   Max   Unit ms tcyc Remark Figure 27.31 Figure 27.31 Mode Pin Input Timing Rev. 3.0, 09/04, page 1003 of 1086 Rev. 3.0, 09/04, page 1004 of 1086 Appendix A On-chip peripheral module Registers A.1 Address On-chip peripheral module register addresses and bit names are shown in the following table. 16-bit and 32-bit registers are shown in two and four rows of 8 bits, respectively. Table A.1 Register Name Address AbbreviBit 7 ation — MCR7 — — TSEG13 — — BRP7 IRR15 IRR7 IMR15 IMR7 TEC7 REC7 Bit Names Bit 6 — — — — TSEG12 — — BRP6 IRR14 IRR6 IMR14 IMR6 TEC6 REC6 Bit 5 — MCR5 — GSR5 TSEG11 SJW1 — BRP5 IRR13 IRR5 IMR13 IMR5 TEC5 REC5 Bit 4 — — — GSR4 TSEG10 SJW0 — BRP4 IRR12 IRR4 IMR12 IMR4 TEC4 REC4 Bit 3 — — — GSR3 — — — BRP3 IRR11 IRR3 IMR11 IMR3 TEC3 REC3 Bit 2 — MCR2 — GSR2 TSEG22 — — BRP2 IRR10 IRR2 IMR10 IMR2 TEC2 REC2 Bit 1 — MCR1 — GSR1 TSEG21 — — BRP1 IRR9 IRR1 IMR9 IMR1 TEC1 REC1 Bit 0 — MCR0 — GSR0 TSEG20 BSP — BRP0 IRR8 IRR0 IMR8 IMR0 TEC0 REC0 Module HCAN0 (Channel 0) H'FFFFD000 MCR H'FFFFD001 H'FFFFD002 GSR H'FFFFD003 H'FFFFD004 BCR1 H'FFFFD005 H'FFFFD006 BCR0 H'FFFFD007 H'FFFFD008 IRR H'FFFFD009 H'FFFFD00A IMR H'FFFFD00B H'FFFFD00C TEC/ H'FFFFD00D REC H'FFFFD020 TXPR1 H'FFFFD021 H'FFFFD022 TXPR0 H'FFFFD023 TXPR1[15] TXPR1[14] TXPR1[13] TXPR1[12] TXPR1[11] TXPR1[10] TXPR1[9] TXPR1[7] TXPR1[6] TXPR1[5] TXPR1[4] TXPR1[3] TXPR1[2] TXPR1[1] TXPR1[8] TXPR1[0] TXPR0[8] — TXPR0[15] TXPR0[14] TXPR0[13] TXPR0[12] TXPR0[11] TXPR0[10] TXPR0[9] TXPR0[7] TXPR0[6] TXPR0[5] TXPR0[4] TXPR0[3] TXPR0[2] TXPR0[1] H'FFFFD028 TXCR1 H'FFFFD029 H'FFFFD02A TXCR0 H'FFFFD02B TXCR1[15] TXCR1[14] TXCR1[13] TXCR1[12] TXCR1[11] TXCR1[10] TXCR1[9] TXCR1[7] TXCR1[6] TXCR1[5] TXCR1[4] TXCR1[3] TXCR1[2] TXCR1[1] TXCR1[8] TXCR1[0] TXCR0[8] — TXCR0[15] TXCR0[14] TXCR0[13] TXCR0[12] TXCR0[11] TXCR0[10] TXCR0[9] TXCR0[7] TXCR0[6] TXCR0[5] TXCR0[4] TXCR0[3] TXCR0[2] TXCR0[1] Rev. 3.0, 09/04, page 1005 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 TXACK1 [14] Bit 5 TXACK1 [13] Bit 4 TXACK1 [12] Bit 3 TXACK1 [11] Bit 2 TXACK1 [10] Bit 1 TXACK1 [9] Bit 0 TXACK1 [8] Module HCAN0 (Channel 0) H'FFFFD030 TXACK1 TXACK1 [15] H'FFFFD031 TXACK1[7] TXACK1[6] TXACK1[5] TXACK1[4] TXACK1[3] TXACK1[2] TXACK1[1] TXACK1[0] TXACK0 [14] TXACK0 [13] TXACK0 [12] TXACK0 [11] TXACK0 [10] TXACK0 [9] TXACK0 [8] H'FFFFD032 TXACK0 TXACK0 [15] H'FFFFD033 TXACK0[7] TXACK0[6] TXACK0[5] TXACK0[4] TXACK0[3] TXACK0[2] TXACK0[1] TXACK0[0] H'FFFFD038 ABACK1 ABACK1 [15] H'FFFFD039 ABACK1 [7] ABACK1 [14] ABACK1 [6] ABACK0 [14] ABACK0 [6] ABACK1 [13] ABACK1 [5] ABACK0 [13] ABACK0 [5] ABACK1 [12] ABACK1 [4] ABACK0 [12] ABACK0 [4] ABACK1 [11] ABACK1 [3] ABACK0 [11] ABACK0 [3] ABACK1 [10] ABACK1 [2] ABACK0 [10] ABACK0 [2] ABACK1 [9] ABACK1 [1] ABACK0 [9] ABACK0 [1] ABACK1 [8] ABACK1 [0] ABACK0 [8] — H'FFFFD03A ABACK0 ABACK0 [15] H'FFFFD03B ABACK0 [7] H'FFFFD040 RXPR1 H'FFFFD041 H'FFFFD042 RXPR0 H'FFFFD043 RXPR1[15] RXPR1[14] RXPR1[13] RXPR1[12] RXPR1[11] RXPR1[10] RXPR1[9] RXPR1[7] RXPR1[6] RXPR1[5] RXPR1[4] RXPR1[3] RXPR1[2] RXPR1[1] RXPR1[8] RXPR1[0] RXPR0[8] RXPR0 [0] RXPR0[15] RXPR0[14] RXPR0[13] RXPR0[12] RXPR0[11] RXPR0[10] RXPR0[9] RXPR0 [7] RXPR0 [6] RXPR0[5] RXPR0[4] RXPR0 [3] RXPR0[2] RXPR0[1] H'FFFFD048 RFPR1 H'FFFFD049 H'FFFFD04A RFPR0 H'FFFFD04B RFPR1 [15] RFPR1[7] RFPR0 [15] RFPR0[7] RFPR1 [14] RFPR1[6] RFPR0 [14] RFPR0[6] RFPR1 [13] RFPR1[5] RFPR0 [13] RFPR0[5] RFPR1 [12] RFPR1[4] RFPR0 [12] RFPR0[4] RFPR1 [11] RFPR1[3] RFPR0 [11] RFPR0[3] RFPR1 [10] RFPR1[2] RFPR0 [10] RFPR0[2] RFPR1[9] RFPR1[1] RFPR1[8] RFPR1[0] RFPR0 [9] RFPR0 [8] RFPR0[1] RFPR0[0] H'FFFFD050 MBIMR1 MBIMR1 [15] H'FFFFD051 MBIMR1 [14] MBIMR1 [13] MBIMR1 [12] MBIMR1 [11] MBIMR1 [10] MBIMR1 [9] MBIMR1 [8] MBIMR1[7] MBIMR1[6] MBIMR1[5] MBIMR1[4] MBIMR1[3] MBIMR1[2] MBIMR1[1] MBIMR1[0] MBIMR0 [14] MBIMR0 [13] MBIMR0 [12] MBIMR0 [11] MBIMR0 [10] MBIMR0 [9] MBIMR0 [8] H'FFFFD052 MBIMR0 MBIMR0 [15] H'FFFFD053 MBIMR0[7] MBIMR0[6] MBIMR0[5] MBIMR0[4] MBIMR0[3] MBIMR0[2] MBIMR0[1] MBIMR0[0] H'FFFFD058 UMSR1 H'FFFFD059 H'FFFFD05A UMSR0 H'FFFFD05B H'FFFFD05C -7F UMSR1 [15] UMSR1 [14] UMSR1 [13] UMSR1 [12] UMSR1 [11] UMSR1 [10] UMSR1 [9] UMSR1 [8] UMSR1[7] UMSR1[6] UMSR1[5] UMSR1[4] UMSR1[3] UMSR1[2] UMSR1[1] UMSR1[0] UMSR0 [15] UMSR0 [14] UMSR0 [13] UMSR0 [12] UMSR0 [11] UMSR0 [10] UMSR0 [9] UMSR0 [8] UMSR0[7] UMSR0[6] UMSR0[5] UMSR0[4] UMSR0[3] UMSR0[2] UMSR0[1] UMSR0[0] — — — — — — — — Rev. 3.0, 09/04, page 1006 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCNTR8 TCNTR0 — TPSC0 — TSR0 TDCR8 TDCR0 LOSR8 LOSR0 — Module HCAN0 (Channel 0) H'FFFFD080 TCNTR H'FFFFD081 H'FFFFD082 TCR H'FFFFD083 H'FFFFD084 TSR H'FFFFD085 H'FFFFD086 TDCR H'FFFFD087 H'FFFFD088 LOSR H'FFFFD089 TCNTR15 TCNTR14 TCNTR13 TCNTR7 TCR15 TCR7 — — TDCR15 TDCR7 LOSR15 LOSR7 TCNTR6 TCR14 — — — TDCR14 TDCR6 LOSR14 LOSR6 — — ICR0_tm 14 TCNTR5 TCR13 TPSC5 — — TDCR13 TDCR5 LOSR13 LOSR5 — — ICR0_tm 13 TCNTR12 TCNTR11 TCNTR4 TCR12 TPSC4 — TSR4 TDCR12 TDCR4 LOSR12 LOSR4 — — ICR0_tm 12 TCNTR3 TCR11 TPSC3 — TSR3 TDCR11 TDCR3 LOSR11 LOSR3 — TCNTR10 TCNTR9 TCNTR2 TCR10 TPSC2 — TSR2 TDCR10 TDCR2 LOSR10 LOSR2 — TCNTR1 TCR9 TPSC1 — TSR1 TDCR9 TDCR1 LOSR9 LOSR1 — H'FFFFD08A ICR0_cc — H'FFFFD08B — ICCR0_cc ICCR0_cc ICCR0_cc ICCR0_cc 3 2 1 0 ICR0_tm 11 ICR0_tm 10 ICR0_tm2 ICR0_tm1 ICR1[10] ICR1[2] TCMR0 [10] ICR1[9] ICR1[1] TCMR0 [9] ICR0_tm0 ICR1[8] ICR1[0] TCMR0 [8] ICR0_tm9 ICR0_tm8 H'FFFFD08C ICR0_tm ICR0_tm 15 H'FFFFD08D H'FFFFD08E ICR1 H'FFFFD08F H'FFFFD090 TCMR0 H'FFFFD091 H'FFFFD092 TCMR1 H'FFFFD093 H'FFFFD094 TCMR2 H'FFFFD095 H'FFFFD096 CCR H'FFFFD097 H'FFFFD098 CMAX H'FFFFD099 H'FFFFD09A TMR H'FFFFD09B ICR0_tm7 ICR0_tm6 ICR0_tm5 ICR1[15] ICR1[7] TCMR0 [15] ICR1[14] ICR1[6] TCMR0 [14] ICR1[13] ICR1[5] TCMR0 [13] ICR0_tm4 ICR0_tm3 ICR1[12] ICR1[4] TCMR0 [12] ICR1[11] ICR1[3] TCMR0 [11] TCMR0[7] TCMR0[6] TCMR0[5] TCMR0[4] TCMR0[3] TCMR0[2] TCMR0[1] TCMR0[0] TCMR1 [15] TCMR1 [14] TCMR1 [13] TCMR1 [12] TCMR1 [11] TCMR1 [10] TCMR1 [9] TCMR1 [8] TCMR1[7] TCMR1[6] TCMR1[5] TCMR1[4] TCMR1[3] TCMR1[2] TCMR1[1] TCMR1[0] TCMR2 [15] TCMR2 [14] TCMR2 [13] TCMR2 [12] TCMR2 [11] TCMR2 [10] TCMR2 [9] TCMR2 [8] TCMR2[7] TCMR2[6] TCMR2[5] TCMR2[4] TCMR2[3] TCMR2[2] TCMR2[1] TCMR2[0] — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CCR3 — CMAX3 — TMR3 — CCRbuf3 — ICR0buf3 — CCR2 — CMAX2 — TMR2 — CCRbuf2 — ICR0buf2 — CCR1 — CMAX1 — TMR1 — CCRbuf1 — ICR0buf1 — CCR0 — CMAX0 — — — CCRbuf0 — ICR0buf0 H'FFFFD09C CCR-buf — H'FFFFD09D — H'FFFFD09E ICR0-buf — H'FFFFD09F — H'FFFFD0A0 — -FF — — — — — — — — — Rev. 3.0, 09/04, page 1007 of 1086 Register Name Abbreviation Bit 7 — STDID[3] Bit Names Bit 6 Bit 5 Bit 4 STDID[8] STDID[0] Bit 3 STDID[7] RTR Bit 2 STDID[6] IDE Bit 1 STDID[5] Bit 0 STDID[4] Module HCAN0 H'FFFFD100 MB0[0], [1]* H'FFFFD101 H'FFFFD102 MB0[2], [3] H'FFFFD103 H'FFFFD104 MB0[4], [5] H'FFFFD105 H'FFFFD106 MB0[6] H'FFFFD107 H'FFFFD108 MB0[7], [8]* H'FFFFD109 H'FFFFD10A MB0[9], [10] H'FFFFD10B STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] CCM — TMSTP [15] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[7] TMSTP[6] TMSTP[5] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD10C MBx[11], MSG_DATA_4 [12] H'FFFFD10D MSG_DATA_5 H'FFFFD10E MB0[13], MSG_DATA_6 [14] H'FFFFD10F MSG_DATA_7 H'FFFFD110 MB0[15], — [16] H'FFFFD111 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD112 MB0[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD113 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD114- — 1F H'FFFFD120 MB1[0], [1]* H'FFFFD121 H'FFFFD122 MB1[2], [3] H'FFFFD123 H'FFFFD124 MB1[4], [5] H'FFFFD125 H'FFFFD126 MB1[6] H'FFFFD127 H'FFFFD128 MB1[7], [8]* H'FFFFD129 H'FFFFD12A MB1[9], [10] H'FFFFD12B — STDID[3] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] (Channel 0) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] CCM — TMSTP [15] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[7] TMSTP[6] TMSTP[5] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD12C MB1[11], MSG_DATA_4 [12] H'FFFFD12D MSG_DATA_5 H'FFFFD12E MB1[13], MSG_DATA_6 [14] H'FFFFD12F MSG_DATA_7 Rev. 3.0, 09/04, page 1008 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD130 MB1[15], — [16] H'FFFFD131 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA HCAN0 FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] (Channel 0) — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD132 MB1[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD133 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD134 -3F H'FFFFD140 MB2[0], [1]* H'FFFFD141 H'FFFFD142 MB2[2], [3] H'FFFFD143 H'FFFFD144 MB2[4], [5] H'FFFFD145 H'FFFFD146 MB2[6] — STDID[3] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] CCM — TMSTP [15] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD147 H'FFFFD148 MB2[7], [8]* H'FFFFD149 H'FFFFD14A MB2[9], [10] H'FFFFD14B TMSTP[7] TMSTP[6] TMSTP[5] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD14C MB2[11], MSG_DATA_4 [12] H'FFFFD14D MSG_DATA_5 H'FFFFD14E MB2[13], MSG_DATA_6 [14] H'FFFFD14F MSG_DATA_7 H'FFFFD150 MB2[15], — [16] H'FFFFD151 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD152 MB2[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD153 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — HCAN0 H'FFFFD154 -5F H'FFFFD160 MB3[0], [1]* H'FFFFD161 H'FFFFD162 MB3[2], [3] H'FFFFD163 H'FFFFD164 MB3[4], H'FFFFD165 [5] — STDID[3] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] CCM — EXTID[6] TTE TCT EXTID[5] NMC — EXTID[4] ATX CLE EXTID[3] DART DLC[3] EXTID[2] MBC[2] DLC[2] EXTID[1] MBC[1] DLC[1] Rev. 3.0, 09/04, page 1009 of 1086 Register Name Abbreviation Bit 7 TMSTP [15] Bit Names Bit 6 TMSTP [14] Bit 5 TMSTP [13] Bit 4 TMSTP [12] Bit 3 TMSTP [11] Bit 2 TMSTP [10] Bit 1 TMSTP [9] Bit 0 TMSTP [8] TMSTP[0] Module HCAN0 (Channel 0) H'FFFFD166 MB3[6] H'FFFFD167 H'FFFFD168 MB3[7], [8]* H'FFFFD169 H'FFFFD16A MB3[9], [10] H'FFFFD16B TMSTP[7] TMSTP[6] TMSTP[5] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD16C MB3[11], MSG_DATA_4 [12] H'FFFFD16D MSG_DATA_5 H'FFFFD16E MB3[13], MSG_DATA_6 [14] H'FFFFD16F MSG_DATA_7 H'FFFFD170 MB3[15], — [16] H'FFFFD171 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD172 MB3[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD173 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — H'FFFFD1747F H'FFFFD180 MB4[0], [1]* H'FFFFD181 H'FFFFD182 MB4[2], [3] H'FFFFD183 H'FFFFD184 MB4[4], [5] H'FFFFD185 H'FFFFD186 MB4[6] — STDID[3] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] CCM — TMSTP [15] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD187 H'FFFFD188 MB4[7], [8]* H'FFFFD189 H'FFFFD18A MB4[9], [10] H'FFFFD18B TMSTP[7] TMSTP[6] TMSTP[5] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD18C MB4[11], MSG_DATA_4 [12] H'FFFFD18D MSG_DATA_5 H'FFFFD18E MB4[13], MSG_DATA_6 [14] H'FFFFD18F MSG_DATA_7 H'FFFFD190 MB4[15], — [16] H'FFFFD191 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] Rev. 3.0, 09/04, page 1010 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD192 MB4[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA HCAN0 FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [18] (Channel 0) H'FFFFD193 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] H'FFFFD1949F H'FFFFD1A0 MB5[0], [1]* H'FFFFD1A1 H'FFFFD1A2 MB5[2], [3] H'FFFFD1A3 H'FFFFD1A4 MB5[4], [5] H'FFFFD1A5 H'FFFFD1A6 MB5[6] H'FFFFD1A7 — — STDID[3] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] CCM — TMSTP [15] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD1A8 MB5 [7], MSG_DATA_0 [8]* H'FFFFD1A9 MSG_DATA_1 H'FFFFD1AA MB5 [9], MSG_DATA_2 [10] H'FFFFD1AB MSG_DATA_3 H'FFFFD1AC MB5[11], MSG_DATA_4 [12] H'FFFFD1AD MSG_DATA_5 H'FFFFD1AE MB5[13], MSG_DATA_6 [14] H'FFFFD1AF MSG_DATA_7 H'FFFFD1B0 MB5[15], — [16] H'FFFFD1B1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD1B2 MB5[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [18] H'FFFFD1B3 H'FFFFD1B4 -BF H'FFFFD1C0 MB6[0], [1]* H'FFFFD1C1 H'FFFFD1C2 MB6[2], [3] H'FFFFD1C3 H'FFFFD1C4 MB6[4], [5] H'FFFFD1C5 H'FFFFD1C6 MB6[6] H'FFFFD1C7 H'FFFFD1C8 MB6[7], [8]* H'FFFFD1C9 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN0 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] CCM — TMSTP [15] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[7] TMSTP[6] TMSTP[5] MSG_DATA_0 MSG_DATA_1 TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] Rev. 3.0, 09/04, page 1011 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN0 (Channel 0) H'FFFFD1CA MB6[9], [10] H'FFFFD1CB MSG_DATA_2 MSG_DATA_3 H'FFFFD1CC MB6[11], MSG_DATA_4 [12] H'FFFFD1CD MSG_DATA_5 H'FFFFD1CE MB6[13], MSG_DATA_6 [14] H'FFFFD1CF MSG_DATA_7 H'FFFFD1D0 MB6[15], — [16] H'FFFFD1D1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD1D2 MB6[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD1D3 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD1D4 -DF H'FFFFD1E0 MB7[0], [1]* H'FFFFD1E1 H'FFFFD1E2 MB7[2], [3] H'FFFFD1E3 H'FFFFD1E4 MB7[4], [5] H'FFFFD1E5 H'FFFFD1E6 MB7[6] — STDID[3] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] CCM — TMSTP [15] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD1E7 H'FFFFD1E8 MB7[7], [8]* H'FFFFD1E9 H'FFFFD1EA MB7[9], [10] H'FFFFD1EB TMSTP[7] TMSTP[6] TMSTP[5] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD1EC MB7[11], MSG_DATA_4 [12] H'FFFFD1ED MSG_DATA_5 H'FFFFD1EE MB7[13], MSG_DATA_6 [14] H'FFFFD1EF MSG_DATA_7 H'FFFFD1F0 MB7[15], — [16] H'FFFFD1F1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD1F2 MB7[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD1F3 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD1F4 -FF Rev. 3.0, 09/04, page 1012 of 1086 Register Name Abbreviation Bit 7 — STDID[3] Bit Names Bit 6 Bit 5 Bit 4 STDID[8] STDID[0] Bit 3 STDID[7] RTR Bit 2 STDID[6] IDE Bit 1 STDID[5] Bit 0 STDID[4] Module HCAN0 H'FFFFD200 MB8[0], [1]* H'FFFFD201 H'FFFFD202 MB8[2], [3] H'FFFFD203 H'FFFFD204 MB8[4], [5] H'FFFFD205 H'FFFFD206 MB8[6] H'FFFFD207 H'FFFFD208 MB8[7], [8]* H'FFFFD209 H'FFFFD20A MB8[9], [10] H'FFFFD20B STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] CCM — TMSTP [15] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[7] TMSTP[6] TMSTP[5] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD20C MB8[11], MSG_DATA_4 [12] H'FFFFD20D MSG_DATA_5 H'FFFFD20E MB8[13], MSG_DATA_6 [14] H'FFFFD20F MSG_DATA_7 H'FFFFD210 MB8[15], — [16] H'FFFFD211 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD212 MB8[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD213 H'FFFFD2141F H'FFFFD220 MB9[0], [1]* H'FFFFD221 H'FFFFD222 MB9[2], [3] H'FFFFD223 H'FFFFD224 MB9[4], [5] H'FFFFD225 H'FFFFD226 MB9[6] H'FFFFD227 H'FFFFD228 MB9[7], [8]* H'FFFFD229 H'FFFFD22A MB9[9], [10] H'FFFFD22B EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] CCM — TMSTP [15] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[7] TMSTP[6] TMSTP[5] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD22C MB9[11], MSG_DATA_4 [12] H'FFFFD22D MSG_DATA_5 H'FFFFD22E MB9[13], MSG_DATA_6 [14] H'FFFFD22F MSG_DATA_7 Rev. 3.0, 09/04, page 1013 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD230 MB9[15], — [16] H'FFFFD231 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA HCAN0 FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] (Channel 0) STDID_LA STDID_LA STDID_LA STDID_LA — — EXTID_LA EXTID_LA FM[3] FM[2] FM[1] FM[0] FM[17] FM[16] H'FFFFD232 MB9[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD233 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD2343F H'FFFFD240 MB10[0], — [1]* H'FFFFD241 STDID[3] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] H'FFFFD242 MB10[2], EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] [3] H'FFFFD243 EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] H'FFFFD244 MB10[4], CCM [5] H'FFFFD245 — H'FFFFD246 MB10[6] TMSTP [15] H'FFFFD247 TTE TCT TMSTP [14] NMC — TMSTP [13] ATX CLE TMSTP [12] DART DLC[3] TMSTP [11] MBC[2] DLC[2] TMSTP [10] MBC[1] DLC[1] TMSTP [9] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD248 MB10[7], MSG_DATA_0 [8]* MSG_DATA_1 H'FFFFD249 H'FFFFD24A MB10[9], MSG_DATA_2 [10] H'FFFFD24B MSG_DATA_3 H'FFFFD24C MB10 MSG_DATA_4 [11], [12] H'FFFFD24D MSG_DATA_5 H'FFFFD24E MB10 [13],[14] H'FFFFD24F MSG_DATA_6 MSG_DATA_7 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] H'FFFFD250 MB10 — [15], [16] H'FFFFD251 STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD252 MB10 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD253 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD2545F H'FFFFD260 MB11 [0], [1]* H'FFFFD261 H'FFFFD262 MB11 [2], [3] H'FFFFD263 — STDID[3] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] EXTID[6] TTE TCT EXTID[5] NMC — EXTID[4] ATX CLE EXTID[3] DART DLC[3] EXTID[2] MBC[2] DLC[2] EXTID[1] MBC[1] DLC[1] H'FFFFD264 MB11[4], CCM [5] H'FFFFD265 — Rev. 3.0, 09/04, page 1014 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 TMSTP [14] Bit 5 TMSTP [13] Bit 4 TMSTP [12] Bit 3 TMSTP [11] Bit 2 TMSTP [10] Bit 1 TMSTP [9] Bit 0 TMSTP [8] TMSTP[0] Module HCAN0 (Channel 0) H'FFFFD266 MB11[6] TMSTP [15] H'FFFFD267 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD268 MB11[7], MSG_DATA_0 [8]* H'FFFFD269 MSG_DATA_1 H'FFFFD26A MB11[9], MSG_DATA_2 [10] H'FFFFD26B MSG_DATA_3 H'FFFFD26C MB11 MSG_DATA_4 [11], [12] H'FFFFD26D MSG_DATA_5 H'FFFFD26E MB11 MSG_DATA_6 [13], [14] H'FFFFD26F MSG_DATA_7 H'FFFFD270 MB11 — [15], [16] H'FFFFD271 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD272 MB11 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD273 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD2747F H'FFFFD280 MB12[0], — [1]* STDID[3] H'FFFFD281 STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] H'FFFFD282 MB12[2], EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] [3] H'FFFFD283 EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] H'FFFFD284 MB12[4], CCM [5] H'FFFFD285 — H'FFFFD286 MB12[6] TMSTP [15] H'FFFFD287 TTE TCT TMSTP [14] NMC — TMSTP [13] ATX CLE TMSTP [12] DART DLC[3] TMSTP [11] MBC[2] DLC[2] TMSTP [10] MBC[1] DLC[1] TMSTP [9] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD288 MB12[7], MSG_DATA_0 H'FFFFD289 [8]* MSG_DATA_1 H'FFFFD28A MB12[9], MSG_DATA_2 H'FFFFD28B [10] MSG_DATA_3 H'FFFFD28C MB12 MSG_DATA_4 [11], [12] H'FFFFD28D MSG_DATA_5 H'FFFFD28E MB12 MSG_DATA_6 [13], [14] H'FFFFD28F MSG_DATA_7 H'FFFFD290 MB12 — [15], [16] H'FFFFD291 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] Rev. 3.0, 09/04, page 1015 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD292 MB12 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA HCAN0 FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [17], [18] FM[15] (Channel 0) H'FFFFD293 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] H'FFFFD2949F H'FFFFD2A0 MB13 [0], [1]* H'FFFFD2A1 H'FFFFD2A2 MB13 [2], [3] H'FFFFD2A3 — — STDID[3] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD2A4 MB13[4], CCM H'FFFFD2A5 [5] — H'FFFFD2A6 MB13[6] TMSTP [15] H'FFFFD2A7 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD2A8 MB13[7], MSG_DATA_0 [8]* H'FFFFD2A9 MSG_DATA_1 H'FFFFD2AA MB13[9], MSG_DATA_2 H'FFFFD2AB [10] MSG_DATA_3 H'FFFFD2AC MB13 MSG_DATA_4 [11], [12] H'FFFFD2AD MSG_DATA_5 H'FFFFD2AE MB13 MSG_DATA_6 [13], [14] H'FFFFD2AF MSG_DATA_7 H'FFFFD2B0 MB13 — [15], [16] H'FFFFD2B1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD2B2 MB13 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [17], [18] FM[15] H'FFFFD2B3 H'FFFFD2B4 -BF H'FFFFD2C0 MB14 [0], [1]* H'FFFFD2C1 H'FFFFD2C2 MB14 [2], [3] H'FFFFD2C3 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN0 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD2C4 MB14[4], CCM [5] H'FFFFD2C5 — H'FFFFD2C6 MB14[6] TMSTP [15] H'FFFFD2C7 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD2C8 MB14[7], MSG_DATA_0 H'FFFFD2C9 [8]* MSG_DATA_1 Rev. 3.0, 09/04, page 1016 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN0 (Channel 0) H'FFFFD2CA MB14[9], MSG_DATA_2 H'FFFFD2CB [10] MSG_DATA_3 H'FFFFD2CC MB14 MSG_DATA_4 [11], [12] H'FFFFD2CD MSG_DATA_5 H'FFFFD2CE MB14 MSG_DATA_6 [13], [14] H'FFFFD2CF MSG_DATA_7 H'FFFFD2D0 MB14 — [15], [16] H'FFFFD2D1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD2D2 MB14 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD2D3 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD2D4 -DF H'FFFFD2E0 MB15 [0], [1]* H'FFFFD2E1 H'FFFFD2E2 MB15 [2], [3] H'FFFFD2E3 — STDID[3] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD2E4 MB15[4], CCM [5] H'FFFFD2E5 — H'FFFFD2E6 MB15[6] TMSTP [15] H'FFFFD2E7 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD2E8 MB15[7], MSG_DATA_0 H'FFFFD2E9 [8]* MSG_DATA_1 H'FFFFD2EA MB15[9], MSG_DATA_2 [10] H'FFFFD2EB MSG_DATA_3 H'FFFFD2EC MB15 MSG_DATA_4 [11], [12] H'FFFFD2ED MSG_DATA_5 H'FFFFD2EE MB15 MSG_DATA_6 [13], [14] H'FFFFD2EF MSG_DATA_7 H'FFFFD2F0 MB15 — [15], [16] H'FFFFD2F1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD2F2 MB15 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD2F3 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD2F4 -FF Rev. 3.0, 09/04, page 1017 of 1086 Register Name Abbreviation Bit 7 — STDID[3] Bit Names Bit 6 Bit 5 Bit 4 STDID[8] STDID[0] Bit 3 STDID[7] RTR Bit 2 STDID[6] IDE Bit 1 STDID[5] Bit 0 STDID[4] Module HCAN0 H'FFFFD300 MB16 [0], [1]* H'FFFFD301 H'FFFFD302 MB16 [2], [3] H'FFFFD303 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD304 MB16[4], CCM [5] H'FFFFD305 — H'FFFFD306 MB16[6] TMSTP [15] H'FFFFD307 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD308 MB16[7], MSG_DATA_0 H'FFFFD309 [8]* MSG_DATA_1 H'FFFFD30A MB16[9], MSG_DATA_2 H'FFFFD30B [10] MSG_DATA_3 H'FFFFD30C MB16 MSG_DATA_4 [11], [12] H'FFFFD30D MSG_DATA_5 H'FFFFD30E MB16 MSG_DATA_6 [13], [14] H'FFFFD30F MSG_DATA_7 H'FFFFD310 MB16 — [15], [16] H'FFFFD311 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD312 MB16 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD313 H'FFFFD3141F EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN0 H'FFFFD320 MB17[0], — [1]* H'FFFFD321 STDID[3] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] H'FFFFD322 MB17[2], EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] [3] H'FFFFD323 EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] H'FFFFD324 MB17[4], CCM [5] H'FFFFD325 — H'FFFFD326 MB17[6] TMSTP [15] H'FFFFD327 TTE TCT TMSTP [14] NMC — TMSTP [13] ATX CLE TMSTP [12] DART DLC[3] TMSTP [11] MBC[2] DLC[2] TMSTP [10] MBC[1] DLC[1] TMSTP [9] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD328 MB17[7], MSG_DATA_0 [8]* H'FFFFD329 MSG_DATA_1 H'FFFFD32A MB17[9], MSG_DATA_2 [10] H'FFFFD32B MSG_DATA_3 H'FFFFD32C MB17 MSG_DATA_4 [11], [12] H'FFFFD32D MSG_DATA_5 H'FFFFD32E MB17 MSG_DATA_6 [13], [14] H'FFFFD32F MSG_DATA_7 Rev. 3.0, 09/04, page 1018 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD330 MB17 — [15], [16] H'FFFFD331 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA HCAN0 FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] (Channel 0) STDID_LA STDID_LA STDID_LA STDID_LA — — EXTID_LA EXTID_LA FM[3] FM[2] FM[1] FM[0] FM[17] FM[16] H'FFFFD332 MB17 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD333 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — H'FFFFD3343F H'FFFFD340 MB18 [0], [1]* H'FFFFD341 H'FFFFD342 MB18 [2], [3] H'FFFFD343 H'FFFFD344 MB18 [4], [5] H'FFFFD345 — STDID[3] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] CCM — EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD346 MB18[6] TMSTP [15] H'FFFFD347 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD348 MB18[7], MSG_DATA_0 [8]* MSG_DATA_1 H'FFFFD349 H'FFFFD34A MB18[9], MSG_DATA_2 [10] H'FFFFD34B MSG_DATA_3 H'FFFFD34C MB18 MSG_DATA_4 [11], [12] H'FFFFD34D MSG_DATA_5 H'FFFFD34E MB18 MSG_DATA_6 [13], [14] H'FFFFD34F MSG_DATA_7 H'FFFFD350 MB18 — [15], [16] H'FFFFD351 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD352 MB18 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD353 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — H'FFFFD3545F H'FFFFD360 MB19 [0], [1]* H'FFFFD361 H'FFFFD362 MB19 [2], [3] H'FFFFD363 H'FFFFD364 MB19 [4], [5] H'FFFFD365 — STDID[3] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] CCM — EXTID[6] TTE TCT EXTID[5] NMC — EXTID[4] ATX CLE EXTID[3] DART DLC[3] EXTID[2] MBC[2] DLC[2] EXTID[1] MBC[1] DLC[1] Rev. 3.0, 09/04, page 1019 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 TMSTP [14] Bit 5 TMSTP [13] Bit 4 TMSTP [12] Bit 3 TMSTP [11] Bit 2 TMSTP [10] Bit 1 TMSTP [9] Bit 0 TMSTP [8] TMSTP[0] Module HCAN0 (Channel 0) H'FFFFD366 MB19[6] TMSTP [15] H'FFFFD367 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD368 MB19[7], MSG_DATA_0 [8]* H'FFFFD369 MSG_DATA_1 H'FFFFD36A MB19[9], MSG_DATA_2 [10] H'FFFFD36B MSG_DATA_3 H'FFFFD36C MB19 MSG_DATA_4 [11], [12] H'FFFFD36D MSG_DATA_5 H'FFFFD36E MB19 MSG_DATA_6 [13], [14] H'FFFFD36F MSG_DATA_7 H'FFFFD370 MB19 — [15], [16] H'FFFFD371 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD372 MB19 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD373 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD3747F H'FFFFD380 MB20 [0], [1]* H'FFFFD381 H'FFFFD382 MB20 [2], [3] H'FFFFD383 — STDID[3] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] TMSTP[0] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[7] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD384 MB20[4], CCM [5] H'FFFFD385 — H'FFFFD386 MB20[6] TMSTP [15] H'FFFFD387 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] H'FFFFD388 MB20[7], MSG_DATA_0 [8]* H'FFFFD389 MSG_DATA_1 H'FFFFD38A MB20[9], MSG_DATA_2 [10] H'FFFFD38B MSG_DATA_3 H'FFFFD38C MB20 MSG_DATA_4 [11], [12] H'FFFFD38D MSG_DATA_5 H'FFFFD38E MB20 MSG_DATA_6 [13], [14] H'FFFFD38F MSG_DATA_7 H'FFFFD390 MB20 — [15], [16] H'FFFFD391 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] Rev. 3.0, 09/04, page 1020 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD392 MB20 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA HCAN0 FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [17], [18] FM[15] (Channel 0) H'FFFFD393 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] H'FFFFD3949F H'FFFFD3A0 MB21 [0], [1]* H'FFFFD3A1 H'FFFFD3A2 MB21 [2], [3] H'FFFFD3A3 H'FFFFD3A4 MB21 [4], [5] H'FFFFD3A5 — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN0 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD3A6 MB21[6] TMSTP [15] H'FFFFD3A7 H'FFFFD3A8 MB21 [7], [8]* H'FFFFD3A9 H'FFFFD3AA MB21 [9], [10] H'FFFFD3AB TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD3AC MB21 MSG_DATA_4 [11], [12] H'FFFFD3AD MSG_DATA_5 H'FFFFD3AE MB21 MSG_DATA_6 [13], [14] H'FFFFD3AF MSG_DATA_7 H'FFFFD3B0 MB21 — [15], [16] H'FFFFD3B1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD3B2 MB21 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [17], [18] FM[15] H'FFFFD3B3 H'FFFFD3B4 -BF H'FFFFD3C0 MB22 [0], [1]* H'FFFFD3C1 H'FFFFD3C2 MB22 [2], [3] H'FFFFD3C3 H'FFFFD3C4 MB22 [4], [5] H'FFFFD3C5 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN0 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD3C6 MB22[6] TMSTP [15] H'FFFFD3C7 H'FFFFD3C8 MB22 [7], [8]* H'FFFFD3C9 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 Rev. 3.0, 09/04, page 1021 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN0 (Channel 0) H'FFFFD3CA MB22 [9], [10] H'FFFFD3CB MSG_DATA_2 MSG_DATA_3 H'FFFFD3CC MB22 MSG_DATA_4 [11], [12] H'FFFFD3CD MSG_DATA_5 H'FFFFD3CE MB22 MSG_DATA_6 [13], [14] H'FFFFD3CF MSG_DATA_7 H'FFFFD3D0 MB22 — [15], [16] H'FFFFD3D1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD3D2 MB22 EXTID_LA [17], [18] FM[15] H'FFFFD3D3 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD3D4 -DF H'FFFFD3E0 MB23 [0], [1]* H'FFFFD3E1 H'FFFFD3E2 MB23 [2], [3] H'FFFFD3E3 H'FFFFD3E4 MB23 [4], [5] H'FFFFD3E5 — STDID[3] EXTID[15] EXTID[7] CCM — STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD3E6 MB23[6] TMSTP [15] H'FFFFD3E7 H'FFFFD3E8 MB23 [7], [8]* H'FFFFD3E9 H'FFFFD3EA MB23 [9], [10] H'FFFFD3EB TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD3EC MB23 MSG_DATA_4 [11], [12] H'FFFFD3ED MSG_DATA_5 H'FFFFD3EE MB23 MSG_DATA_6 [13], [14] H'FFFFD3EF MSG_DATA_7 H'FFFFD3F0 MB23 — [15], [16] H'FFFFD3F1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD3F2 MB23 EXTID_LA [17], [18] FM[15] H'FFFFD3F3 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD3F4 -FF Rev. 3.0, 09/04, page 1022 of 1086 Register Name Abbreviation Bit 7 — STDID[3] EXTID[15] EXTID[7] CCM — Bit Names Bit 6 Bit 5 Bit 4 STDID[8] STDID[0] Bit 3 STDID[7] RTR Bit 2 STDID[6] IDE Bit 1 STDID[5] Bit 0 STDID[4] Module HCAN0 H'FFFFD400 MB24 [0], [1]* H'FFFFD401 H'FFFFD402 MB24 [2], [3] H'FFFFD403 H'FFFFD404 MB24 [4], [5] H'FFFFD405 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD406 MB24[6] TMSTP [15] H'FFFFD407 H'FFFFD408 MB24 [7], [8]* H'FFFFD409 H'FFFFD40A MB24 [9], [10] H'FFFFD40B TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD40C MB24 MSG_DATA_4 [11], [12] H'FFFFD40D MSG_DATA_5 H'FFFFD40E MB24 MSG_DATA_6 [13], [14] H'FFFFD40F MSG_DATA_7 H'FFFFD410 MB24 — [15], [16] H'FFFFD411 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD412 MB24 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD413 H'FFFFD4141F H'FFFFD420 MB25 [0], [1]* H'FFFFD421 H'FFFFD422 MB25 [2], [3] H'FFFFD423 H'FFFFD424 MB25 [4], [5] H'FFFFD425 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD426 MB25[6] TMSTP [15] H'FFFFD427 H'FFFFD428 MB25 [7], [8]* H'FFFFD429 H'FFFFD42A MB25 [9], [10] H'FFFFD42B TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD42C MB25 MSG_DATA_4 [11], [12] H'FFFFD42D MSG_DATA_5 H'FFFFD42E MB25 MSG_DATA_6 [13], [14] H'FFFFD42F MSG_DATA_7 Rev. 3.0, 09/04, page 1023 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD430 MB25 — [15], [16] H'FFFFD431 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA HCAN0 (Channel 0) FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD432 MB25 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD433 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — H'FFFFD4343F H'FFFFD440 MB26 [0], [1]* H'FFFFD441 H'FFFFD442 MB26 [2], [3] H'FFFFD443 H'FFFFD444 MB26 [4], [5] H'FFFFD445 — STDID[3] EXTID[15] EXTID[7] CCM — STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD446 MB26[6] TMSTP [15] H'FFFFD447 H'FFFFD448 MB26 [7], [8]* H'FFFFD449 H'FFFFD44A MB26 [9], [10] H'FFFFD44B TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD44C MB26 MSG_DATA_4 [11], [12] H'FFFFD44D MSG_DATA_5 H'FFFFD44E MB26 MSG_DATA_6 [13] ,[14] H'FFFFD44F MSG_DATA_7 H'FFFFD450 MB26 — [15], [16] H'FFFFD451 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD452 MB26 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD453 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD4545F H'FFFFD460 MB27 [0], [1]* H'FFFFD461 H'FFFFD462 MB27 [2], [3] H'FFFFD463 H'FFFFD464 MB27 [4], [5] H'FFFFD465 — STDID[3] EXTID[15] EXTID[7] CCM — STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT EXTID[5] NMC — EXTID[4] ATX CLE EXTID[3] DART DLC[3] EXTID[2] MBC[2] DLC[2] EXTID[1] MBC[1] DLC[1] Rev. 3.0, 09/04, page 1024 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 TMSTP [14] Bit 5 TMSTP [13] Bit 4 TMSTP [12] Bit 3 TMSTP [11] Bit 2 TMSTP [10] Bit 1 TMSTP [9] Bit 0 TMSTP [8] Module HCAN0 (Channel 0) H'FFFFD466 MB27[6] TMSTP [15] H'FFFFD467 H'FFFFD468 MB27 [7], [8]* H'FFFFD469 H'FFFFD46A MB27 [9],[10] H'FFFFD46B TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD46C MB27 MSG_DATA_4 [11], [12] H'FFFFD46D MSG_DATA_5 H'FFFFD46E MB27 MSG_DATA_6 [13],[14] H'FFFFD46F MSG_DATA_7 H'FFFFD470 MB27 — [15], [16] H'FFFFD471 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD472 MB27 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD473 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD4747F H'FFFFD480 MB28 [0], [1]* H'FFFFD481 H'FFFFD482 MB28 [2], [3] H'FFFFD483 H'FFFFD484 MB28 [4], [5] H'FFFFD485 — STDID[3] EXTID[15] EXTID[7] CCM — STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD486 MB28[6] TMSTP [15] H'FFFFD487 H'FFFFD488 MB28 [7], [8]* H'FFFFD489 H'FFFFD48A MB28 [9], [10] H'FFFFD48B TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD48C MB28 MSG_DATA_4 [11], [12] H'FFFFD48D MSG_DATA_5 H'FFFFD48E MB28 MSG_DATA_6 [13], [14] H'FFFFD48F MSG_DATA_7 H'FFFFD490 MB28 — [15], [16] H'FFFFD491 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] Rev. 3.0, 09/04, page 1025 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD492 MB28 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA HCAN0 FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] (Channel 0) [17], [18] FM[15] H'FFFFD493 H'FFFFD4947F H'FFFFD4A0 MB29 [0], [1]* H'FFFFD4A1 H'FFFFD4A2 MB29 [2], [3] H'FFFFD4A3 H'FFFFD4A4 MB29 [4],[5] H'FFFFD4A5 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD4A6 MB29[6] TMSTP [15] H'FFFFD4A7 H'FFFFD4A8 MB29 [7],[8]* H'FFFFD4A9 H'FFFFD4AA MB29 [9],[10] H'FFFFD4AB TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD4AC MB29 MSG_DATA_4 [11],[12] H'FFFFD4AD MSG_DATA_5 H'FFFFD4AE MB29 MSG_DATA_6 [13],[14] H'FFFFD4AF MSG_DATA_7 H'FFFFD4B0 MB29 — [15], [16] H'FFFFD4B1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD4B2 MB29 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [17], [18] FM[15] H'FFFFD4B3 H'FFFFD4B4 -BF H'FFFFD4C0 MB30 [0], [1]* H'FFFFD4C1 H'FFFFD4C2 MB30 [2], [3] H'FFFFD4C3 H'FFFFD4C4 MB30 [4], [5] H'FFFFD4C5 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN0 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD4C6 MB30[6] TMSTP [15] H'FFFFD4C7 H'FFFFD4C8 MB30 [7], [8]* H'FFFFD4C9 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 Rev. 3.0, 09/04, page 1026 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN0 (Channel 0) H'FFFFD4CA MB30 [9],[10] H'FFFFD4CB MSG_DATA_2 MSG_DATA_3 H'FFFFD4CC MB30 MSG_DATA_4 [11],[12] H'FFFFD4CD MSG_DATA_5 H'FFFFD4CE MB30 MSG_DATA_6 [13],[14] H'FFFFD4CF MSG_DATA_7 H'FFFFD4D0 MB30 — [15], [16] H'FFFFD4D1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD4D2 MB30 EXTID_LA [17], [18] FM[15] H'FFFFD4D3 H'FFFFD4D4 -DF H'FFFFD4E0 MB31 [0], [1]* H'FFFFD4E1 H'FFFFD4E2 MB31 [2], [3] H'FFFFD4E3 H'FFFFD4E4 MB31 [4], [5] H'FFFFD4E5 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN0 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 0) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD4E6 MB31[6] TMSTP [15] H'FFFFD4E7 H'FFFFD4E8 MB31 [7], [8]* H'FFFFD4E9 H'FFFFD4EA MB31 [9], [10] H'FFFFD4EB TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD4EC MB31 MSG_DATA_4 [11], [12] H'FFFFD4ED MSG_DATA_5 H'FFFFD4EE MB31 MSG_DATA_6 [13], [14] H'FFFFD4EF MSG_DATA_7 H'FFFFD4F0 MB31 — [15], [16] H'FFFFD4F1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD4F2 MB31 EXTID_LA [17], [18] FM[15] H'FFFFD4F3 H'FFFFD4F4 -7FF EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — Rev. 3.0, 09/04, page 1027 of 1086 Register Name Abbreviation Bit 7 — MCR7 — — TSEG13 — — BRP7 IRR15 IRR7 IMR15 IMR7 TEC7 REC7 Bit Names Bit 6 — — — — TSEG12 — — BRP6 IRR14 IRR6 IMR14 IMR6 TEC6 REC6 Bit 5 — MCR5 — GSR5 TSEG11 SJW1 — BRP5 IRR13 IRR5 IMR13 IMR5 TEC5 REC5 Bit 4 — — — GSR4 TSEG10 SJW0 — BRP4 IRR12 IRR4 IMR12 IMR4 TEC4 REC4 Bit 3 — — — GSR3 — — — BRP3 IRR11 IRR3 IMR11 IMR3 TEC3 REC3 Bit 2 — MCR2 — GSR2 TSEG22 — — BRP2 IRR10 IRR2 IMR10 IMR2 TEC2 REC2 Bit 1 — MCR1 — GSR1 TSEG21 — — BRP1 IRR9 IRR1 IMR9 IMR1 TEC1 REC1 Bit 0 — MCR0 — GSR0 TSEG20 BSP — BRP0 IRR8 IRR0 IMR8 IMR0 TEC0 REC0 Module HCAN1 (Channel 1) H'FFFFD800 MCR H'FFFFD801 H'FFFFD802 GSR H'FFFFD803 H'FFFFD804 BCR1 H'FFFFD805 H'FFFFD806 BCR0 H'FFFFD807 H'FFFFD808 IRR H'FFFFD809 H'FFFFD80A IMR H'FFFFD80B H'FFFFD80C TEC/ REC H'FFFFD80D H'FFFFD820 TXPR1 H'FFFFD821 H'FFFFD822 TXPR0 H'FFFFD823 TXPR1[15] TXPR1[14] TXPR1[13] TXPR1[12] TXPR1[11] TXPR1[10] TXPR1[9] TXPR1[7] TXPR1[6] TXPR1[5] TXPR1[4] TXPR1[3] TXPR1[2] TXPR1[1] TXPR1[8] TXPR1[0] TXPR0[8] — TXPR0[15] TXPR0[14] TXPR0[13] TXPR0[12] TXPR0[11] TXPR0[10] TXPR0[9] TXPR0[7] TXPR0[6] TXPR0[5] TXPR0[4] TXPR0[3] TXPR0[2] TXPR0[1] H'FFFFD828 TXCR1 H'FFFFD829 H'FFFFD82A TXCR0 H'FFFFD82B TXCR1[15] TXCR1[14] TXCR1[13] TXCR1[12] TXCR1[11] TXCR1[10] TXCR1[9] TXCR1[7] TXCR1[6] TXCR1[5] TXCR1[4] TXCR1[3] TXCR1[2] TXCR1[1] TXCR1[8] TXCR1[0] TXCR0[8] — TXCR0[15] TXCR0[14] TXCR0[13] TXCR0[12] TXCR0[11] TXCR0[10] TXCR0[9] TXCR0[7] TXCR0[6] TXCR0[5] TXCR0[4] TXCR0[3] TXCR0[2] TXCR0[1] H'FFFFD830 TXACK1 TXACK1 [15] H'FFFFD831 TXACK1 [14] TXACK1 [13] TXACK1 [12] TXACK1 [11] TXACK1 [10] TXACK1 [9] TXACK1 [8] TXACK1[7] TXACK1[6] TXACK1[5] TXACK1[4] TXACK1[3] TXACK1[2] TXACK1[1] TXACK1[0] TXACK0 [14] TXACK0 [13] TXACK0 [12] TXACK0 [11] TXACK0 [10] TXACK0 [9] TXACK0 [8] H'FFFFD832 TXACK0 TXACK0 [15] H'FFFFD833 TXACK0[7] TXACK0[6] TXACK0[5] TXACK0[4] TXACK0[3] TXACK0[2] TXACK0[1] TXACK0[0] H'FFFFD838 ABACK1 ABACK1 [15] H'FFFFD839 ABACK1 [7] ABACK1 [14] ABACK1 [6] ABACK0 [14] ABACK0 [6] ABACK1 [13] ABACK1 [5] ABACK0 [13] ABACK0 [5] ABACK1 [12] ABACK1 [4] ABACK0 [12] ABACK0 [4] ABACK1 [11] ABACK1 [3] ABACK0 [11] ABACK0 [3] ABACK1 [10] ABACK1 [2] ABACK0 [10] ABACK0 [2] ABACK1 [9] ABACK1 [1] ABACK0 [9] ABACK0 [1] ABACK1 [8] ABACK1 [0] ABACK0 [8] — H'FFFFD83A ABACK0 ABACK0 [15] H'FFFFD83B ABACK0 [7] H'FFFFD840 RXPR1 H'FFFFD841 RXPR1[15] RXPR1[14] RXPR1[13] RXPR1[12] RXPR1[11] RXPR1[10] RXPR1[9] RXPR1[7] RXPR1[6] RXPR1[5] RXPR1[4] RXPR1[3] RXPR1[2] RXPR1[1] RXPR1[8] RXPR1[0] Rev. 3.0, 09/04, page 1028 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN1 H'FFFFD842 RXPR0 H'FFFFD843 RXPR0[15] RXPR0[14] RXPR0[13] RXPR0[12] RXPR0[11] RXPR0[10] RXPR0 [9] RXPR0[8] RXPR0 [7] RXPR0 [6] RXPR0[5] RXPR0[4] RXPR0 [3] RXPR0[2] RXPR0[1] RXPR0 [0] (Channel 1) H'FFFFD848 RFPR1 H'FFFFD849 H'FFFFD84A RFPR0 H'FFFFD84B RFPR1 [15] RFPR1 [14] RFPR1[7] RFPR1[6] RFPR1 [13] RFPR1[5] RFPR0 [13] RFPR0[5] RFPR1 [12] RFPR1[4] RFPR0 [12] RFPR0[4] RFPR1 [11] RFPR1[3] RFPR0 [11] RFPR0[3] RFPR1 [10] RFPR1[2] RFPR0 [10] RFPR0[2] RFPR1 [9] RFPR1[1] RFPR0 [9] RFPR0[1] RFPR1 [8] RFPR1[0] RFPR0 [8] RFPR0[0] RFPR0 [15] RFPR0 [14] RFPR0[7] RFPR0[6] H'FFFFD850 MBIMR1 MBIMR1 [15] H'FFFFD851 MBIMR1 [14] MBIMR1 [13] MBIMR1 [12] MBIMR1 [11] MBIMR1 [10] MBIMR1 [9] MBIMR1 [8] MBIMR1[7] MBIMR1[6] MBIMR1[5] MBIMR1[4] MBIMR1[3] MBIMR1[2] MBIMR1[1] MBIMR1[0] MBIMR0 [14] MBIMR0 [13] MBIMR0 [12] MBIMR0 [11] MBIMR0 [10] MBIMR0 [9] MBIMR0 [8] H'FFFFD852 MBIMR0 MBIMR0 [15] H'FFFFD853 MBIMR0[7] MBIMR0[6] MBIMR0[5] MBIMR0[4] MBIMR0[3] MBIMR0[2] MBIMR0[1] MBIMR0[0] H'FFFFD858 UMSR1 H'FFFFD859 H'FFFFD85A UMSR0 H'FFFFD85B H'FFFFD85C -7F UMSR1 [15] UMSR1[7] UMSR0 [15] UMSR0[7] — UMSR1 [14] UMSR1 [13] UMSR1 [12] UMSR1 [11] UMSR1 [10] UMSR1 [9] UMSR1 [8] UMSR1[6] UMSR1[5] UMSR1[4] UMSR1[3] UMSR1[2] UMSR1[1] UMSR1[0] UMSR0 [14] UMSR0 [13] UMSR0 [12] UMSR0 [11] UMSR0 [10] UMSR0 [9] UMSR0 [8] UMSR0[6] UMSR0[5] UMSR0[4] UMSR0[3] UMSR0[2] UMSR0[1] UMSR0[0] — — — — — — — H'FFFFD880 TCNTR H'FFFFD881 H'FFFFD882 TCR H'FFFFD883 H'FFFFD884 TSR H'FFFFD885 H'FFFFD886 TDCR H'FFFFD887 H'FFFFD888 LOSR H'FFFFD889 TCNTR15 TCNTR7 TCR15 TCR7 — — TDCR15 TDCR7 LOSR15 LOSR7 TCNTR14 TCNTR13 TCNTR12 TCNTR11 TCNTR10 TCNTR9 TCNTR6 TCR14 — — — TDCR14 TDCR6 LOSR14 LOSR6 — — ICR0_tm 14 TCNTR5 TCR13 TPSC5 — — TDCR13 TDCR5 LOSR13 LOSR5 — — ICR0_tm 13 TCNTR4 TCR12 TPSC4 — TSR4 TDCR12 TDCR4 LOSR12 LOSR4 — — ICR0_tm 12 TCNTR3 TCR11 TPSC3 — TSR3 TDCR11 TDCR3 LOSR11 LOSR3 — TCNTR2 TCR10 TPSC2 — TSR2 TDCR10 TDCR2 LOSR10 LOSR2 — TCNTR1 TCR9 TPSC1 — TSR1 TDCR9 TDCR1 LOSR9 LOSR1 — TCNTR8 TCNTR0 — TPSC0 — TSR0 TDCR8 TDCR0 LOSR8 LOSR0 — H'FFFFD88A ICR0_cc — H'FFFFD88B — ICCR0_cc ICCR0_cc ICCR0_cc ICCR0_cc 3 2 1 0 ICR0_tm 11 ICR0_tm 10 ICR0_tm9 ICR0_tm8 H'FFFFD88C ICR0_tm ICR0_tm 15 H'FFFFD88D H'FFFFD88E ICR1 H'FFFFD88F ICR0_tm7 ICR1[15] ICR1[7] ICR0_tm6 ICR0_tm5 ICR0_tm4 ICR0_tm3 ICR0_tm2 ICR0_tm1 ICR0_tm0 ICR1[14] ICR1[6] ICR1[13] ICR1[5] ICR1[12] ICR1[4] ICR1[11] ICR1[3] ICR1[10] ICR1[2] ICR1[9] ICR1[1] ICR1[8] ICR1[0] Rev. 3.0, 09/04, page 1029 of 1086 Register Name Abbreviation Bit 7 TCMR0 [15] TCMR0[7] TCMR1 [15] TCMR1[7] TCMR2 [15] TCMR2[7] — — — — — — — — — — Bit Names Bit 6 TCMR0 [14] Bit 5 TCMR0 [13] Bit 4 TCMR0 [12] Bit 3 TCMR0 [11] Bit 2 TCMR0 [10] Bit 1 TCMR0 [9] Bit 0 TCMR0 [8] Module HCAN1 (Channel 1) H'FFFFD890 TCMR0 H'FFFFD891 H'FFFFD892 TCMR1 H'FFFFD893 H'FFFFD894 TCMR2 H'FFFFD895 H'FFFFD896 CCR H'FFFFD897 H'FFFFD898 CMAX H'FFFFD899 H'FFFFD89A TMR H'FFFFD89B H'FFFFD89C CCRbuf H'FFFFD89D H'FFFFD89E ICR0buf H'FFFFD89F TCMR0[6] TCMR0[5] TCMR0[4] TCMR0[3] TCMR0[2] TCMR0[1] TCMR0[0] TCMR1 [14] TCMR1 [13] TCMR1 [12] TCMR1 [11] TCMR1 [10] TCMR1 [9] TCMR1 [8] TCMR1[6] TCMR1[5] TCMR1[4] TCMR1[3] TCMR1[2] TCMR1[1] TCMR1[0] TCMR2 [14] TCMR2 [13] TCMR2 [12] TCMR2 [11] TCMR2 [10] TCMR2 [9] TCMR2 [8] TCMR2[6] TCMR2[5] TCMR2[4] TCMR2[3] TCMR2[2] TCMR2[1] TCMR2[0] — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CCR3 — CMAX3 — TMR3 — CCRbuf3 — ICR0buf3 — CCR2 — CMAX2 — TMR2 — CCRbuf2 — ICR0buf2 — CCR1 — CMAX1 — TMR1 — CCRbuf1 — ICR0buf1 — CCR0 — CMAX0 — — — CCRbuf0 — ICR0buf0 H'FFFFD8A0 — -FF — — — — — — — — — H'FFFFD900 MB0[0], [1]* H'FFFFD901 H'FFFFD902 MB0[2], [3] H'FFFFD903 H'FFFFD904 MB0[4], [5] H'FFFFD905 H'FFFFD906 MB0[6] H'FFFFD907 H'FFFFD908 MB0[7], [8]* H'FFFFD909 H'FFFFD90A MB0[9], [10] H'FFFFD90B — STDID[3] EXTID[15] EXTID[7] CCM — TMSTP [15] TMSTP[7] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN1 EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD90C MBx[11], MSG_DATA_4 [12] H'FFFFD90D MSG_DATA_5 H'FFFFD90E MB0[13], MSG_DATA_6 [14] H'FFFFD90F MSG_DATA_7 H'FFFFD910 MB0[15], — [16] H'FFFFD911 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] Rev. 3.0, 09/04, page 1030 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD912 MB0[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA HCAN1 (Channel 1) [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD913 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — TMSTP [15] TMSTP[7] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 H'FFFFD914- — 1F H'FFFFD920 MB1[0], [1]* H'FFFFD921 H'FFFFD922 MB1[2], [3] H'FFFFD923 H'FFFFD924 MB1[4], [5] H'FFFFD925 H'FFFFD926 MB1[6] H'FFFFD927 H'FFFFD928 MB1[7], [8]* H'FFFFD929 H'FFFFD92A MB1[9], [10] H'FFFFD92B STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD92C MB1[11], MSG_DATA_4 [12] H'FFFFD92D MSG_DATA_5 H'FFFFD92E MB1[13], MSG_DATA_6 [14] H'FFFFD92F MSG_DATA_7 H'FFFFD930 MB1[15], — [16] H'FFFFD931 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD932 MB1[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD933 H'FFFFD9343F H'FFFFD940 MB2[0], [1]* H'FFFFD941 H'FFFFD942 MB2[2], [3] H'FFFFD943 H'FFFFD944 MB2[4], [5] H'FFFFD945 H'FFFFD946 MB2[6] H'FFFFD947 H'FFFFD948 MB2[7], [8]* H'FFFFD949 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — TMSTP [15] TMSTP[7] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 Rev. 3.0, 09/04, page 1031 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN1 (Channel 1) H'FFFFD94A MB2[9], [10] H'FFFFD94B MSG_DATA_2 MSG_DATA_3 H'FFFFD94C MB2[11], MSG_DATA_4 [12] H'FFFFD94D MSG_DATA_5 H'FFFFD94E MB2[13], MSG_DATA_6 [14] H'FFFFD94F MSG_DATA_7 H'FFFFD950 MB2[15], — [16] H'FFFFD951 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD952 MB2[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD953 H'FFFFD9545F H'FFFFD960 MB3[0], [1]* H'FFFFD961 H'FFFFD962 MB3[2], [3] H'FFFFD963 H'FFFFD964 MB3[4], [5] H'FFFFD965 H'FFFFD966 MB3[6] H'FFFFD967 H'FFFFD968 MB3[7], [8]* H'FFFFD969 H'FFFFD96A MB3[9], [10] H'FFFFD96B EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — TMSTP [15] TMSTP[7] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD96C MB3[11], MSG_DATA_4 [12] H'FFFFD96D MSG_DATA_5 H'FFFFD96E MB3[13], MSG_DATA_6 [14] H'FFFFD96F MSG_DATA_7 H'FFFFD970 MB3[15], — [16] H'FFFFD971 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD972 MB3[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD973 H'FFFFD9747F H'FFFFD980 MB4[0], [1]* H'FFFFD981 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] Rev. 3.0, 09/04, page 1032 of 1086 Register Name Abbreviation Bit 7 EXTID[15] EXTID[7] CCM — TMSTP [15] TMSTP[7] Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] Module HCAN1 (Channel 1) H'FFFFD982 MB4[2], [3] H'FFFFD983 H'FFFFD984 MB4[4], [5] H'FFFFD985 H'FFFFD986 MB4[6] H'FFFFD987 H'FFFFD988 MB4[7], [8]* H'FFFFD989 H'FFFFD98A MB4[9], [10] H'FFFFD98B EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD98C MB4[11], MSG_DATA_4 [12] H'FFFFD98D MSG_DATA_5 H'FFFFD98E MB4[13], MSG_DATA_6 [14] H'FFFFD98F MSG_DATA_7 H'FFFFD990 MB4[15], — [16] H'FFFFD991 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD992 MB4[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [18] H'FFFFD993 H'FFFFD9949F H'FFFFD9A0 MB5[0], [1]* H'FFFFD9A1 H'FFFFD9A2 MB5[2], [3] H'FFFFD9A3 H'FFFFD9A4 MB5[4], [5] H'FFFFD9A5 H'FFFFD9A6 MB5[6] H'FFFFD9A7 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — TMSTP [15] TMSTP[7] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFD9A8 MB5 [7], MSG_DATA_0 [8]* MSG_DATA_1 H'FFFFD9A9 H'FFFFD9AA MB5 [9], MSG_DATA_2 [10] H'FFFFD9AB MSG_DATA_3 H'FFFFD9AC MB5[11], MSG_DATA_4 [12] H'FFFFD9AD MSG_DATA_5 H'FFFFD9AE MB5[13], MSG_DATA_6 [14] H'FFFFD9AF MSG_DATA_7 Rev. 3.0, 09/04, page 1033 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD9B0 MB5[15], — [16] H'FFFFD9B1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA HCAN1 FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] (Channel 1) — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD9B2 MB5[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFD9B3 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD9B4 -BF H'FFFFD9C0 MB6[0], [1]* H'FFFFD9C1 H'FFFFD9C2 MB6[2], [3] H'FFFFD9C3 H'FFFFD9C4 MB6[4], [5] H'FFFFD9C5 H'FFFFD9C6 MB6[6] — STDID[3] EXTID[15] EXTID[7] CCM — TMSTP [15] TMSTP[7] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN1 EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFD9C7 H'FFFFD9C8 MB6[7], [8]* H'FFFFD9C9 H'FFFFD9CA MB6[9], [10] H'FFFFD9CB TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD9CC MB6[11], MSG_DATA_4 [12] H'FFFFD9CD MSG_DATA_5 H'FFFFD9CE MB6[13], MSG_DATA_6 [14] H'FFFFD9CF MSG_DATA_7 H'FFFFD9D0 MB6[15], — [16] H'FFFFD9D1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD9D2 MB6[17], EXTID_LA [18] FM[15] H'FFFFD9D3 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD9D4 -DF H'FFFFD9E0 MB7[0], [1]* H'FFFFD9E1 H'FFFFD9E2 MB7[2], [3] H'FFFFD9E3 H'FFFFD9E4 MB7[4], [5] H'FFFFD9E5 — STDID[3] EXTID[15] EXTID[7] CCM — STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN1 EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT EXTID[5] NMC — EXTID[4] ATX CLE EXTID[3] DART DLC[3] EXTID[2] MBC[2] DLC[2] EXTID[1] MBC[1] DLC[1] Rev. 3.0, 09/04, page 1034 of 1086 Register Name Abbreviation Bit 7 TMSTP [15] TMSTP[7] Bit Names Bit 6 TMSTP [14] Bit 5 TMSTP [13] Bit 4 TMSTP [12] Bit 3 TMSTP [11] Bit 2 TMSTP [10] Bit 1 TMSTP [9] Bit 0 TMSTP [8] Module HCAN1 (Channel 1) H'FFFFD9E6 MB7[6] H'FFFFD9E7 H'FFFFD9E8 MB7[7], [8]* H'FFFFD9E9 H'FFFFD9EA MB7[9], [10] H'FFFFD9EB TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFD9EC MB7[11], MSG_DATA_4 [12] H'FFFFD9ED MSG_DATA_5 H'FFFFD9EE MB7[13], MSG_DATA_6 [14] H'FFFFD9EF MSG_DATA_7 H'FFFFD9F0 MB7[15], — [16] H'FFFFD9F1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFD9F2 MB7[17], EXTID_LA [18] FM[15] H'FFFFD9F3 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFD9F4 -FF H'FFFFDA00 MB8[0], [1]* H'FFFFDA01 H'FFFFDA02 MB8[2], [3] H'FFFFDA03 H'FFFFDA04 MB8[4], [5] H'FFFFDA05 H'FFFFDA06 MB8[6] — STDID[3] EXTID[15] EXTID[7] CCM — TMSTP [15] TMSTP[7] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN1 EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDA07 H'FFFFDA08 MB8[7], [8]* H'FFFFDA09 H'FFFFDA0A MB8[9], [10] H'FFFFDA0B TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFDA0C MB8[11], MSG_DATA_4 [12] H'FFFFDA0D MSG_DATA_5 H'FFFFDA0E MB8[13], MSG_DATA_6 [14] H'FFFFDA0F MSG_DATA_7 H'FFFFDA10 MB8[15], — [16] H'FFFFDA11 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] Rev. 3.0, 09/04, page 1035 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFDA12 MB8[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA HCAN1 FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [18] (Channel 1) H'FFFFDA13 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] H'FFFFDA14 -1F H'FFFFDA20 MB9[0], [1]* H'FFFFDA21 H'FFFFDA22 MB9[2], [3] H'FFFFDA23 H'FFFFDA24 MB9[4], [5] H'FFFFDA25 H'FFFFDA26 MB9[6] H'FFFFDA27 H'FFFFDA28 MB9[7], [8]* H'FFFFDA29 H'FFFFDA2A MB9[9], [10] H'FFFFDA2B — — STDID[3] EXTID[15] EXTID[7] CCM — TMSTP [15] TMSTP[7] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFDA2C MB9[11], MSG_DATA_4 [12] H'FFFFDA2D MSG_DATA_5 H'FFFFDA2E MB9[13], MSG_DATA_6 [14] H'FFFFDA2F MSG_DATA_7 H'FFFFDA30 MB9[15], — [16] H'FFFFDA31 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDA32 MB9[17], EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [18] H'FFFFDA33 H'FFFFDA34 -3F EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 H'FFFFDA40 MB10[0], — [1]* H'FFFFDA41 STDID[3] H'FFFFDA42 MB10[2], EXTID[15] [3] H'FFFFDA43 EXTID[7] H'FFFFDA44 MB10[4], CCM [5] H'FFFFDA45 — H'FFFFDA46 MB10[6] TMSTP [15] H'FFFFDA47 TMSTP[7] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDA48 MB10[7], MSG_DATA_0 [8]* H'FFFFDA49 MSG_DATA_1 Rev. 3.0, 09/04, page 1036 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN1 (Channel 1) H'FFFFDA4A MB10[9], MSG_DATA_2 [10] H'FFFFDA4B MSG_DATA_3 H'FFFFDA4C MB10 MSG_DATA_4 [11], [12] H'FFFFDA4D MSG_DATA_5 H'FFFFDA4E MB10 MSG_DATA_6 [13],[14] H'FFFFDA4F MSG_DATA_7 H'FFFFDA50 MB10 — [15], [16] H'FFFFDA51 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDA52 MB10 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFDA53 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFDA54 -5F H'FFFFDA60 MB11 [0], [1]* H'FFFFDA61 H'FFFFDA62 MB11 [2], [3] H'FFFFDA63 — STDID[3] EXTID[15] EXTID[7] STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN1 EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDA64 MB11[4], CCM [5] H'FFFFDA65 — H'FFFFDA66 MB11[6] TMSTP [15] H'FFFFDA67 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDA68 MB11[7], MSG_DATA_0 [8]* H'FFFFDA69 MSG_DATA_1 H'FFFFDA6A MB11[9], MSG_DATA_2 [10] H'FFFFDA6B MSG_DATA_3 H'FFFFDA6C MB11 MSG_DATA_4 [11], [12] H'FFFFDA6D MSG_DATA_5 H'FFFFDA6E MB11 MSG_DATA_6 [13], [14] H'FFFFDA6F MSG_DATA_7 H'FFFFDA70 MB11 — [15], [16] H'FFFFDA71 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDA72 MB11 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFDA73 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFDA74 -7F Rev. 3.0, 09/04, page 1037 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 STDID[8] STDID[0] Bit 3 STDID[7] RTR Bit 2 STDID[6] IDE Bit 1 STDID[5] Bit 0 STDID[4] Module HCAN1 H'FFFFDA80 MB12[0], — [1]* H'FFFFDA81 STDID[3] H'FFFFDA82 MB12[2], EXTID[15] [3] H'FFFFDA83 EXTID[7] H'FFFFDA84 MB12[4], CCM [5] H'FFFFDA85 — H'FFFFDA86 MB12[6] TMSTP [15] H'FFFFDA87 TMSTP[7] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDA88 MB12[7], MSG_DATA_0 H'FFFFDA89 [8]* MSG_DATA_1 H'FFFFDA8A MB12[9], MSG_DATA_2 H'FFFFDA8B [10] MSG_DATA_3 H'FFFFDA8C MB12 MSG_DATA_4 [11], [12] H'FFFFDA8D MSG_DATA_5 H'FFFFDA8E MB12 MSG_DATA_6 [13], [14] H'FFFFDA8F MSG_DATA_7 H'FFFFDA90 MB12 — [15], [16] H'FFFFDA91 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDA92 MB12 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFDA93 H'FFFFDA94 -9F H'FFFFDAA0 MB13 [0], [1]* H'FFFFDAA1 H'FFFFDAA2 MB13 [2], [3] H'FFFFDAA3 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDAA4 MB13[4], CCM H'FFFFDAA5 [5] — H'FFFFDAA6 MB13[6] TMSTP [15] H'FFFFDAA7 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDAA8 MB13[7], MSG_DATA_0 [8]* H'FFFFDAA9 MSG_DATA_1 H'FFFFDAAA MB13[9], MSG_DATA_2 H'FFFFDAAB [10] H'FFFFDAA C H'FFFFDAA D MSG_DATA_3 MB13 MSG_DATA_4 [11], [12] MSG_DATA_5 H'FFFFDAAE MB13 MSG_DATA_6 [13], [14] H'FFFFDAAF MSG_DATA_7 Rev. 3.0, 09/04, page 1038 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFDAB0 MB13 — [15], [16] H'FFFFDAB1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA HCAN1 FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] (Channel 1) STDID_LA STDID_LA STDID_LA STDID_LA — — EXTID_LA EXTID_LA FM[3] FM[2] FM[1] FM[0] FM[17] FM[16] H'FFFFDAB2 MB13 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFDAB3 H'FFFFDAB4 -BF H'FFFFDAC0 MB14 [0], [1]* H'FFFFDAC1 H'FFFFDAC2 MB14 [2], [3] H'FFFFDAC3 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDAC4 MB14[4], CCM [5] H'FFFFDAC5 — H'FFFFDAC6 MB14[6] TMSTP [15] H'FFFFDAC7 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDAC8 MB14[7], MSG_DATA_0 H'FFFFDAC9 [8]* H'FFFFDAC A H'FFFFDAC B H'FFFFDAC C H'FFFFDAC D H'FFFFDAC E H'FFFFDACF MSG_DATA_1 MB14[9], MSG_DATA_2 [10] MSG_DATA_3 MB14 MSG_DATA_4 [11], [12] MSG_DATA_5 MB14 MSG_DATA_6 [13], [14] MSG_DATA_7 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] H'FFFFDAD0 MB14 — [15], [16] H'FFFFDAD1 STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDAD2 MB14 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [17], [18] FM[15] H'FFFFDAD3 H'FFFFDAD4 -DF H'FFFFDAE0 MB15 [0], [1]* H'FFFFDAE1 H'FFFFDAE2 MB15 [2], [3] H'FFFFDAE3 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT EXTID[5] NMC — EXTID[4] ATX CLE EXTID[3] DART DLC[3] EXTID[2] MBC[2] DLC[2] EXTID[1] MBC[1] DLC[1] H'FFFFDAE4 MB15[4], CCM [5] H'FFFFDAE5 — Rev. 3.0, 09/04, page 1039 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 TMSTP [14] Bit 5 TMSTP [13] Bit 4 TMSTP [12] Bit 3 TMSTP [11] Bit 2 TMSTP [10] Bit 1 TMSTP [9] Bit 0 TMSTP [8] Module HCAN1 (Channel 1) H'FFFFDAE6 MB15[6] TMSTP [15] H'FFFFDAE7 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDAE8 MB15[7], MSG_DATA_0 [8]* H'FFFFDAE9 MSG_DATA_1 H'FFFFDAEA MB15[9], MSG_DATA_2 [10] H'FFFFDAEB MSG_DATA_3 H'FFFFDAE C H'FFFFDAE D MSG_DATA_4 MB15 [11], [12] MSG_DATA_5 H'FFFFDAEE MB15 MSG_DATA_6 [13], [14] H'FFFFDAEF MSG_DATA_7 H'FFFFDAF0 MB15 — [15], [16] H'FFFFDAF1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDAF2 MB15 EXTID_LA [17], [18] FM[15] H'FFFFDAF3 H'FFFFDAF4 -FF H'FFFFDB00 MB16 [0], [1]* H'FFFFDB01 H'FFFFDB02 MB16 [2], [3] H'FFFFDB03 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDB04 MB16[4], CCM [5] H'FFFFDB05 — H'FFFFDB06 MB16[6] TMSTP [15] H'FFFFDB07 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDB08 MB16[7], MSG_DATA_0 [8]* H'FFFFDB09 MSG_DATA_1 H'FFFFDB0A MB16[9], MSG_DATA_2 [10] H'FFFFDB0B MSG_DATA_3 H'FFFFDB0C MB16 MSG_DATA_4 [11], [12] H'FFFFDB0D MSG_DATA_5 H'FFFFDB0E MB16 MSG_DATA_6 [13], [14] H'FFFFDB0F MSG_DATA_7 H'FFFFDB10 MB16 — [15], [16] H'FFFFDB11 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] Rev. 3.0, 09/04, page 1040 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFDB12 MB16 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA HCAN1 FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [17], [18] FM[15] (Channel 1) H'FFFFDB13 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] H'FFFFDB14 -1F — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 H'FFFFDB20 MB17[0], — [1]* H'FFFFDB21 STDID[3] H'FFFFDB22 MB17[2], EXTID[15] [3] H'FFFFDB23 EXTID[7] H'FFFFDB24 MB17[4], CCM [5] H'FFFFDB25 — H'FFFFDB26 MB17[6] TMSTP [15] H'FFFFDB27 TMSTP[7] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDB28 MB17[7], MSG_DATA_0 [8]* H'FFFFDB29 MSG_DATA_1 H'FFFFDB2A MB17[9], MSG_DATA_2 [10] H'FFFFDB2B MSG_DATA_3 H'FFFFDB2C MB17 MSG_DATA_4 [11], [12] H'FFFFDB2D MSG_DATA_5 H'FFFFDB2E MB17 MSG_DATA_6 [13], [14] H'FFFFDB2F MSG_DATA_7 H'FFFFDB30 MB17 — [15], [16] H'FFFFDB31 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDB32 MB17 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [17], [18] FM[15] H'FFFFDB33 H'FFFFDB34 -3F H'FFFFDB40 MB18 [0], [1]* H'FFFFDB41 H'FFFFDB42 MB18 [2], [3] H'FFFFDB43 H'FFFFDB44 MB18 [4], [5] H'FFFFDB45 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDB46 MB18[6] TMSTP [15] H'FFFFDB47 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDB48 MB18[7], MSG_DATA_0 [8]* H'FFFFDB49 MSG_DATA_1 Rev. 3.0, 09/04, page 1041 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN1 (Channel 1) H'FFFFDB4A MB18[9], MSG_DATA_2 [10] H'FFFFDB4B MSG_DATA_3 H'FFFFDB4C MB18 MSG_DATA_4 [11], [12] H'FFFFDB4D MSG_DATA_5 H'FFFFDB4E MB18 MSG_DATA_6 [13], [14] H'FFFFDB4F MSG_DATA_7 H'FFFFDB50 MB18 — [15], [16] H'FFFFDB51 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDB52 MB18 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFDB53 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — H'FFFFDB54 -5F H'FFFFDB60 MB19 [0], [1]* H'FFFFDB61 H'FFFFDB62 MB19 [2], [3] H'FFFFDB63 H'FFFFDB64 MB19 [4], [5] H'FFFFDB65 — STDID[3] EXTID[15] EXTID[7] CCM — STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDB66 MB19[6] TMSTP [15] H'FFFFDB67 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDB68 MB19[7], MSG_DATA_0 [8]* H'FFFFDB69 MSG_DATA_1 H'FFFFDB6A MB19[9], MSG_DATA_2 [10] H'FFFFDB6B MSG_DATA_3 H'FFFFDB6C MB19 MSG_DATA_4 [11], [12] H'FFFFDB6D MSG_DATA_5 H'FFFFDB6E MB19 MSG_DATA_6 [13], [14] H'FFFFDB6F MSG_DATA_7 H'FFFFDB70 MB19 — [15], [16] H'FFFFDB71 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDB72 MB19 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFDB73 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFDB74 -7F Rev. 3.0, 09/04, page 1042 of 1086 Register Name Abbreviation Bit 7 — STDID[3] EXTID[15] EXTID[7] Bit Names Bit 6 Bit 5 Bit 4 STDID[8] STDID[0] Bit 3 STDID[7] RTR Bit 2 STDID[6] IDE Bit 1 STDID[5] Bit 0 STDID[4] Module HCAN1 H'FFFFDB80 MB20 [0], [1]* H'FFFFDB81 H'FFFFDB82 MB20 [2], [3] H'FFFFDB83 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDB84 MB20[4], CCM [5] H'FFFFDB85 — H'FFFFDB86 MB20[6] TMSTP [15] H'FFFFDB87 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDB88 MB20[7], MSG_DATA_0 [8]* MSG_DATA_1 H'FFFFDB89 H'FFFFDB8A MB20[9], MSG_DATA_2 [10] H'FFFFDB8B MSG_DATA_3 H'FFFFDB8C MB20 MSG_DATA_4 [11], [12] H'FFFFDB8D MSG_DATA_5 H'FFFFDB8E MB20 MSG_DATA_6 [13], [14] H'FFFFDB8F MSG_DATA_7 H'FFFFDB90 MB20 — [15], [16] H'FFFFDB91 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDB92 MB20 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFDB93 H'FFFFDB94 -9F H'FFFFDBA0 MB21 [0], [1]* H'FFFFDBA1 H'FFFFDBA2 MB21 [2], [3] H'FFFFDBA3 H'FFFFDBA4 MB21 [4], [5] H'FFFFDBA5 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDBA6 MB21[6] TMSTP [15] H'FFFFDBA7 H'FFFFDBA8 MB21 [7], [8]* H'FFFFDBA9 H'FFFFDBAA MB21 [9], [10] H'FFFFDBAB H'FFFFDBA C H'FFFFDBA D TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MB21 MSG_DATA_4 [11], [12] MSG_DATA_5 H'FFFFDBAE MB21 MSG_DATA_6 [13], [14] H'FFFFDBAF MSG_DATA_7 Rev. 3.0, 09/04, page 1043 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFDBB0 MB21 — [15], [16] H'FFFFDBB1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA HCAN1 FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] (Channel 1) STDID_LA STDID_LA STDID_LA STDID_LA — — EXTID_LA EXTID_LA FM[3] FM[2] FM[1] FM[0] FM[17] FM[16] H'FFFFDBB2 MB21 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFDBB3 H'FFFFDBB4 -BF H'FFFFDBC0 MB22 [0], [1]* H'FFFFDBC1 H'FFFFDBC2 MB22 [2], [3] H'FFFFDBC3 H'FFFFDBC4 MB22 [4], [5] H'FFFFDBC5 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDBC6 MB22[6] TMSTP [15] H'FFFFDBC7 H'FFFFDBC8 MB22 [7], [8]* H'FFFFDBC9 H'FFFFDBC A H'FFFFDBC B H'FFFFDBC C H'FFFFDBC D H'FFFFDBC E H'FFFFDBCF MB22 [9], [10] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MB22 MSG_DATA_4 [11], [12] MSG_DATA_5 MB22 MSG_DATA_6 [13], [14] MSG_DATA_7 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] H'FFFFDBD0 MB22 — [15], [16] H'FFFFDBD1 STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDBD2 MB22 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [17], [18] FM[15] H'FFFFDBD3 H'FFFFDBD4 -DF H'FFFFDBE0 MB23 [0], [1]* H'FFFFDBE1 H'FFFFDBE2 MB23 [2], [3] H'FFFFDBE3 H'FFFFDBE4 MB23 [4], [5] H'FFFFDBE5 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT EXTID[5] NMC — EXTID[4] ATX CLE EXTID[3] DART DLC[3] EXTID[2] MBC[2] DLC[2] EXTID[1] MBC[1] DLC[1] Rev. 3.0, 09/04, page 1044 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 TMSTP [14] Bit 5 TMSTP [13] Bit 4 TMSTP [12] Bit 3 TMSTP [11] Bit 2 TMSTP [10] Bit 1 TMSTP [9] Bit 0 TMSTP [8] Module HCAN1 (Channel 1) H'FFFFDBE6 MB23[6] TMSTP [15] H'FFFFDBE7 H'FFFFDBE8 MB23 [7], [8]* H'FFFFDBE9 H'FFFFDBEA MB23 [9], [10] H'FFFFDBEB H'FFFFDBE C H'FFFFDBE D TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MB23 [11], [12] MSG_DATA_5 H'FFFFDBEE MB23 MSG_DATA_6 [13], [14] H'FFFFDBEF MSG_DATA_7 H'FFFFDBF0 MB23 — [15], [16] H'FFFFDBF1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDBF2 MB23 EXTID_LA [17], [18] FM[15] H'FFFFDBF3 H'FFFFDBF4 -FF H'FFFFDC00 MB24 [0], [1]* H'FFFFDC01 H'FFFFDC02 MB24 [2], [3] H'FFFFDC03 H'FFFFDC04 MB24 [4], [5] H'FFFFDC05 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDC06 MB24[6] TMSTP [15] H'FFFFDC07 H'FFFFDC08 MB24 [7], [8]* H'FFFFDC09 H'FFFFDC0A MB24 [9], [10] H'FFFFDC0B TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFDC0C MB24 MSG_DATA_4 [11], [12] H'FFFFDC0D MSG_DATA_5 H'FFFFDC0E MB24 MSG_DATA_6 [13], [14] H'FFFFDC0F MSG_DATA_7 H'FFFFDC10 MB24 — [15], [16] H'FFFFDC11 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] Rev. 3.0, 09/04, page 1045 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFDC12 MB24 EXTID_LA [17], [18] FM[15] H'FFFFDC13 H'FFFFDC14 -1F H'FFFFDC20 MB25 [0], [1]* H'FFFFDC21 H'FFFFDC22 MB25 [2], [3] H'FFFFDC23 H'FFFFDC24 MB25 [4], [5] H'FFFFDC25 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA HCAN1 FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] (Channel 1) EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — STDID[3] EXTID[15] EXTID[7] CCM — STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDC26 MB25[6] TMSTP [15] H'FFFFDC27 H'FFFFDC28 MB25 [7], [8]* H'FFFFDC29 H'FFFFDC2A MB25 [9], [10] H'FFFFDC2B TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFDC2C MB25 MSG_DATA_4 [11], [12] H'FFFFDC2D MSG_DATA_5 H'FFFFDC2E MB25 MSG_DATA_6 [13], [14] H'FFFFDC2F MSG_DATA_7 H'FFFFDC30 MB25 — [15], [16] H'FFFFDC31 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDC32 MB25 EXTID_LA [17], [18] FM[15] H'FFFFDC33 H'FFFFDC34 -3F H'FFFFDC40 MB26 [0], [1]* H'FFFFDC41 H'FFFFDC42 MB26 [2], [3] H'FFFFDC43 H'FFFFDC44 MB26 [4], [5] H'FFFFDC45 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDC46 MB26[6] TMSTP [15] H'FFFFDC47 H'FFFFDC48 MB26 [7], [8]* H'FFFFDC49 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 Rev. 3.0, 09/04, page 1046 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module HCAN1 (Channel 1) H'FFFFDC4A MB26 [9], [10] H'FFFFDC4B MSG_DATA_2 MSG_DATA_3 H'FFFFDC4C MB26 MSG_DATA_4 [11], [12] H'FFFFDC4D MSG_DATA_5 H'FFFFDC4E MB26 MSG_DATA_6 [13] ,[14] H'FFFFDC4F MSG_DATA_7 H'FFFFDC50 MB26 — [15], [16] H'FFFFDC51 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDC52 MB26 EXTID_LA [17], [18] FM[15] H'FFFFDC53 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFDC54 -5F H'FFFFDC60 MB27 [0], [1]* H'FFFFDC61 H'FFFFDC62 MB27 [2], [3] H'FFFFDC63 H'FFFFDC64 MB27 [4], [5] H'FFFFDC65 — STDID[3] EXTID[15] EXTID[7] CCM — STDID[10] STDID[9] STDID[2] STDID[1] STDID[8] STDID[0] STDID[7] RTR STDID[6] IDE STDID[5] STDID[4] HCAN1 EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDC66 MB27[6] TMSTP [15] H'FFFFDC67 H'FFFFDC68 MB27 [7], [8]* H'FFFFDC69 H'FFFFDC6A MB27 [9],[10] H'FFFFDC6B TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFDC6C MB27 MSG_DATA_4 [11], [12] H'FFFFDC6D MSG_DATA_5 H'FFFFDC6E MB27 MSG_DATA_6 [13],[14] H'FFFFDC6F MSG_DATA_7 H'FFFFDC70 MB27 — [15], [16] H'FFFFDC71 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDC72 MB27 EXTID_LA [17], [18] FM[15] H'FFFFDC73 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFDC74 -7F Rev. 3.0, 09/04, page 1047 of 1086 Register Name Abbreviation Bit 7 — STDID[3] EXTID[15] EXTID[7] CCM — Bit Names Bit 6 Bit 5 Bit 4 STDID[8] STDID[0] Bit 3 STDID[7] RTR Bit 2 STDID[6] IDE Bit 1 STDID[5] Bit 0 STDID[4] Module HCAN1 H'FFFFDC80 MB28 [0], [1]* H'FFFFDC81 H'FFFFDC82 MB28 [2], [3] H'FFFFDC83 H'FFFFDC84 MB28 [4], [5] H'FFFFDC85 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDC86 MB28[6] TMSTP [15] H'FFFFDC87 H'FFFFDC88 MB28 [7], [8]* H'FFFFDC89 H'FFFFDC8A MB28 [9], [10] H'FFFFDC8B TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 H'FFFFDC8C MB28 MSG_DATA_4 [11], [12] H'FFFFDC8D MSG_DATA_5 H'FFFFDC8E MB28 MSG_DATA_6 [13], [14] H'FFFFDC8F MSG_DATA_7 H'FFFFDC90 MB28 — [15], [16] H'FFFFDC91 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDC92 MB28 EXTID_LA [17], [18] FM[15] H'FFFFDC93 H'FFFFDC94 -7F H'FFFFDCA0 MB29 [0], [1]* H'FFFFDCA1 H'FFFFDCA2 MB29 [2], [3] H'FFFFDCA3 H'FFFFDCA4 MB29 [4],[5] H'FFFFDCA5 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDCA6 MB29[6] TMSTP [15] H'FFFFDCA7 H'FFFFDCA8 MB29 [7],[8]* H'FFFFDCA9 H'FFFFDCA A H'FFFFDCA B H'FFFFDCA C H'FFFFDCA D H'FFFFDCA E H'FFFFDCAF MB29 [13],[14] MB29 [9],[10] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MSG_DATA_4 MB29 [11],[12] MSG_DATA_5 MSG_DATA_6 MSG_DATA_7 Rev. 3.0, 09/04, page 1048 of 1086 Register Name Abbreviation Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFDCB0 MB29 — [15], [16] H'FFFFDCB1 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA HCAN1 FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] (Channel 1) — EXTID_LA EXTID_LA FM[17] FM[16] STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDCB2 MB29 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFDCB3 H'FFFFDCB4 -BF H'FFFFDCC0 MB30 [0], [1]* H'FFFFDCC1 H'FFFFDCC2 MB30 [2], [3] H'FFFFDCC3 H'FFFFDCC4 MB30 [4], [5] H'FFFFDCC5 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] TMSTP [8] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT TMSTP [14] EXTID[5] NMC — TMSTP [13] EXTID[4] ATX CLE TMSTP [12] EXTID[3] DART DLC[3] TMSTP [11] EXTID[2] MBC[2] DLC[2] TMSTP [10] EXTID[1] MBC[1] DLC[1] TMSTP [9] H'FFFFDCC6 MB30[6] TMSTP [15] H'FFFFDCC7 H'FFFFDCC8 MB30 [7], [8]* H'FFFFDCC9 H'FFFFDCC A H'FFFFDCC B H'FFFFDCC C H'FFFFDCC D H'FFFFDCC E H'FFFFDCC F MB30 [9],[10] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MB30 MSG_DATA_4 [11],[12] MSG_DATA_5 MSG_DATA_6 MB30 [13],[14] MSG_DATA_7 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] H'FFFFDCD0 MB30 — [15], [16] H'FFFFDCD1 STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDCD2 MB30 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] [17], [18] FM[15] H'FFFFDCD3 H'FFFFDCD4 -DF H'FFFFDCE0 MB31 [0], [1]* H'FFFFDCE1 H'FFFFDCE2 MB31 [2], [3] H'FFFFDCE3 H'FFFFDCE4 MB31 [4], [5] H'FFFFDCE5 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — STDID[3] EXTID[15] EXTID[7] CCM — — — — STDID[8] STDID[0] — STDID[7] RTR — STDID[6] IDE — STDID[5] — STDID[4] — HCAN1 STDID[10] STDID[9] STDID[2] STDID[1] EXTID[17] EXTID[16] (Channel 1) EXTID[8] EXTID[0] MBC[0] DLC[0] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[6] TTE TCT EXTID[5] NMC — EXTID[4] ATX CLE EXTID[3] DART DLC[3] EXTID[2] MBC[2] DLC[2] EXTID[1] MBC[1] DLC[1] Rev. 3.0, 09/04, page 1049 of 1086 Register Name Abbreviation Bit 7 TMSTP [15] TMSTP[7] Bit Names Bit 6 TMSTP [14] Bit 5 TMSTP [13] Bit 4 TMSTP [12] Bit 3 TMSTP [11] Bit 2 TMSTP [10] Bit 1 TMSTP [9] Bit 0 TMSTP [8] Module HCAN1 (Channel 1) H'FFFFDCE6 MB31[6] H'FFFFDCE7 H'FFFFDCE8 MB31 [7], [8]* H'FFFFDCE9 H'FFFFDCE A H'FFFFDCE B H'FFFFDCE C H'FFFFDCE D H'FFFFDCE E H'FFFFDCEF MB31 [9], [10] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 MB31 MSG_DATA_4 [11], [12] MSG_DATA_5 MB31 MSG_DATA_6 [13], [14] MSG_DATA_7 STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA STDID_LA FM[10] FM[9] FM[8] FM[7] FM[6] FM[5] FM[4] — EXTID_LA EXTID_LA FM[17] FM[16] H'FFFFDCF0 MB31 — [15], [16] H'FFFFDCF1 STDID_LA STDID_LA STDID_LA STDID_LA — FM[3] FM[2] FM[1] FM[0] H'FFFFDCF2 MB31 EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA [17], [18] FM[15] FM[14] FM[13] FM[12] FM[11] FM[10] FM[9] FM[8] H'FFFFDCF3 H'FFFFDCF4 -7FF EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA EXTID_LA FM[7] FM[6] FM[5] FM[4] FM[3] FM[2] FM[1] FM[0] — — — — — — — — — H'FFFFE730 to — H'FFFFE7FF H'FFFFE800 FCCS H'FFFFE801 FPCS H'FFFFE802 FECS H'FFFFE803 — H'FFFFE804 FKEY H'FFFFE805 FMATS H'FFFFE806 FTDAR H'FFFFE807 to — H'FFFFEBFF H'FFFFEC00 UBARH H'FFFFEC01 H'FFFFEC02 UBARL H'FFFFEC03 H'FFFFEC04 UBAMR H H'FFFFEC05 — FWE — — — — — — — — — — — FLER — — — — — — — — — — — — — — — SCO PPVS EPVB — FLASH System area (access prohibited) K7 MS7 TDER K6 MS6 TDA6 K5 MS5 TDA5 K4 MS4 TDA4 K3 MS3 TDA3 K2 MS2 TDA2 K1 MS1 TDA1 K0 MS0 TDA0 System area (access prohibited) UBA31 UBA23 UBA15 UBA7 UBM31 UBM23 UBA30 UBA22 UBA14 UBA6 UBM30 UBM22 UBM14 UBM6 UBA29 UBA21 UBA13 UBA5 UBM29 UBM21 UBM13 UBM5 UBA28 UBA20 UBA12 UBA4 UBM28 UBM20 UBM12 UBM4 UBA27 UBA19 UBA11 UBA3 UBM27 UBM19 UBM11 UBM3 UBA26 UBA18 UBA10 UBA2 UBM26 UBM18 UBM10 UBM2 UBA25 UBA17 UBA9 UBA1 UBM25 UBM17 UBM9 UBM1 UBA24 UBA16 UBA8 UBA0 UBM24 UBM16 UBM8 UBM0 UBC H'FFFFEC06 UBAMRL UBM15 H'FFFFEC07 UBM7 Rev. 3.0, 09/04, page 1050 of 1086 Register Name Abbreviation Bit 7 — CP1 — — Bit Names Bit 6 — CP0 — — Bit 5 — ID1 — — Bit 4 — ID0 — — Bit 3 — RW1 — — Bit 2 — RW0 — CKS1 Bit 1 — SZ1 — CKS0 Bit 0 — SZ0 — UBID Module UBC H'FFFFEC08 UBBR H'FFFFEC09 H'FFFFEC0A UBCR H'FFFFEC0B H'FFFFEC0C to — H'FFFFEC0F H'FFFFEC10 TCSR* H'FFFFEC11 TCNT* H'FFFFEC12 — — — — — — — — — — OVF WT/IT TME — — CKS2 CKS1 CKS0 WDT — — RSTE — RSTS — — — — — — — — — — H'FFFFEC13 RSTCSR WOVF * H'FFFFEC14 SBYCR SSBY HIZ — — — — — — Power-Down state H'FFFFEC15 to — H'FFFFEC1F H'FFFFEC20 BCR1 H'FFFFEC21 H'FFFFEC22 BCR2 H'FFFFEC23 H'FFFFEC24 WCR H'FFFFEC25 H'FFFFEC26 RAMER H'FFFFEC27 H'FFFFEC28 to — H'FFFFECAF — — — — — — — — — — — IW31 CW3 — — — — — — IW30 CW2 W32 W12 — — — — IW21 CW1 W31 W11 — — — — IW20 CW0 W30 W10 — — — A3SZ IW11 SW3 — — — RAMS — A2SZ IW10 SW2 W22 W02 — RAM2 — A1SZ IW01 SW1 W21 W01 — RAM1 — A0SZ IW00 SW0 W20 W00 — RAM0 BSC — — — — — — — — — Note: * This is the read address. The Write Address is H'FFFEC10 for TCSR and TCNT, and H'FFFEC12 for RSTCSR. For details, see section 13.2.4, Notes on Register Access. Rev. 3.0, 09/04, page 1051 of 1086 Register Name Abbreviation Bit Names Bit 7 — — — Bit 6 — — — Bit 5 — — — Bit 4 — — — Bit 3 — — — Bit 2 — AE — Bit 1 — NMIF — Bit 0 — DME — Module DMAC (Common) — DMAC (Channel 0) H'FFFFECB0 DMAOR H'FFFFECB1 H'FFFFECB2 to — H'FFFFECBF H'FFFFECC0 SAR0 H'FFFFECC1 H'FFFFECC2 H'FFFFECC3 H'FFFFECC4 DAR0 H'FFFFECC5 H'FFFFECC6 H'FFFFECC7 H'FFFFECC8 DMATCR0 — H'FFFFECC9 H'FFFFECCA H'FFFFECCB H'FFFFECCC CHCR0 H'FFFFECCD H'FFFFECCE H'FFFFECCF H'FFFFECD0 SAR1 H'FFFFECD1 H'FFFFECD2 H'FFFFECD3 H'FFFFECD4 DAR1 H'FFFFECD5 H'FFFFECD6 H'FFFFECD7 H'FFFFECD8 DMATCR1 — H'FFFFECD9 H'FFFFECDA H'FFFFECDB H'FFFFECDC CHCR1 H'FFFFECDD H'FFFFECDE H'FFFFECDF H'FFFFECE0 SAR2 H'FFFFECE1 H'FFFFECE2 H'FFFFECE3 — — — — — — — — — — — — — — — — — — — — — SM1 TS1 DI RS4 SM0 TS0 — RS3 — TM — RS2 — IE — RS1 DM1 TE RO RS0 DM0 DE DMAC (Channel 1) — — — — — — — — — — — — — SM1 TS1 DI RS4 SM0 TS0 — RS3 — TM — RS2 — IE — RS1 DM1 TE RO RS0 DM0 DE DMAC (Channel 2) Rev. 3.0, 09/04, page 1052 of 1086 Register Name Abbreviation Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DMAC (Channel 2) H'FFFFECE4 DAR2 H'FFFFECE5 H'FFFFECE6 H'FFFFECE7 H'FFFFECE8 DMATCR2 — H'FFFFECE9 H'FFFFECEA H'FFFFECEB H'FFFFECEC CHCR2 H'FFFFECED H'FFFFECEE H'FFFFECEF H'FFFFECF0 SAR3 H'FFFFECF1 H'FFFFECF2 H'FFFFECF3 H'FFFFECF4 DAR3 H'FFFFECF5 H'FFFFECF6 H'FFFFECF7 H'FFFFECF8 DMATCR3 — H'FFFFECF9 H'FFFFECFA H'FFFFECFB H'FFFFECFC CHCR3 H'FFFFECFD H'FFFFECFE H'FFFFECFF H'FFFFED00 IPRA H'FFFFED01 H'FFFFED02 IPRB H'FFFFED03 H'FFFFED04 IPRC H'FFFFED05 H'FFFFED06 IPRD H'FFFFED07 H'FFFFED08 IPRE H'FFFFED09 H'FFFFED0A IPRF H'FFFFED0B H'FFFFED0C IPRG H'FFFFED0D — — — — — — — — — — SM1 TS1 DI RS4 SM0 TS0 — RS3 — TM — RS2 — IE — RS1 DM1 TE RO RS0 DM0 DE — — — — — — — — — — — — — — — — — SM1 TS1 DI RS4 SM0 TS0 — RS3 — TM — RS2 — IE — RS1 DM1 TE RO RS0 DM0 DE — — — — — — — DMAC (Channel 3) INTC Rev. 3.0, 09/04, page 1053 of 1086 Register Name Abbreviation Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module INTC H'FFFFED0E IPRH H'FFFFED0F H'FFFFED10 IPRI H'FFFFED11 H'FFFFED12 IPRJ H'FFFFED13 H'FFFFED14 IPRK H'FFFFED15 H'FFFFED16 IPRL H'FFFFED17 H'FFFFED18 ICR H'FFFFED19 H'FFFFED1A ISR H'FFFFED1B H'FFFFED1C to — H'FFFFEFFF H'FFFFF000 H'FFFFF001 H'FFFFF002 H'FFFFF003 H'FFFFF004 H'FFFFF005 H'FFFFF006 H'FFFFF007 H'FFFFF008 H'FFFFF009 SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SDCR0 — SMR1 BRR1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 — — C/A — — CHR — — PE — — O/E DIR — STOP — — MP — — CKS1 — — CKS0 TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 NMIL IRQ0S — IRQ0F — C/A — IRQ1S — IRQ1F — CHR — IRQ2S — IRQ2F — PE — IRQ3S — IRQ3F — O/E — IRQ4S — IRQ4F — STOP — IRQ5S — IRQ5F — MP — IRQ6S — IRQ6F — CKS1 NMIE IRQ7S — IRQ7F — CKS0 — SCI (Channel 0) SCI (Channel 1) H'FFFFF00A SCR1 H'FFFFF00B TDR1 H'FFFFF00C SSR1 H'FFFFF00D RDR1 H'FFFFF00E SDCR1 H'FFFFF00F H'FFFFF010 H'FFFFF011 H'FFFFF012 H'FFFFF013 H'FFFFF014 H'FFFFF015 H'FFFFF016 H'FFFFF017 — SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SDCR2 — TDRE RDRF ORER FER PER TEND MPB MPBT — — C/A — — CHR — — PE — — O/E DIR — STOP — — MP — — CKS1 — — CKS0 SCI (Channel 2) TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT — — — — — — — — DIR — — — — — — — Rev. 3.0, 09/04, page 1054 of 1086 Register Name H'FFFFF018 H'FFFFF019 Abbreviation SMR3 BRR3 Bit Names Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module SCI (Channel 3) TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'FFFFF01A SCR3 H'FFFFF01B TDR3 H'FFFFF01C SSR3 H'FFFFF01D RDR3 H'FFFFF01E SDCR3 H'FFFFF01F H'FFFFF020 H'FFFFF021 H'FFFFF022 H'FFFFF023 H'FFFFF024 H'FFFFF025 H'FFFFF026 — SMR4 BRR4 SCR4 TDR4 SSR4 RDR4 SDCR4 TDRE RDRF ORER FER PER TEND MPB MPBT — — C/A — — CHR — — PE — — O/E DIR — STOP — — MP — — CKS1 — — CKS0 SCI (Channel 4) TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT — — STR7D STR10 — — — — — — STR7C STR5 — — — — — — STR7B STR4 — — — — — — STR7A STR3 — — PSC1E — PSC2E DIR — STR6D — — STR6C — — STR6B STR1A — — PSC1B — PSC2B — PSC3B — PSC4B — — — — STR6A STR0 STR11 — PSC1A — PSC2A — PSC3A — PSC4A — — — ATU-II (Channel 0) — ATU-II (Common) H'FFFFF027 to — H'FFFFF3FF H'FFFFF400 H'FFFFF401 H'FFFFF402 H'FFFFF403 H'FFFFF404 H'FFFFF405 H'FFFFF406 H'FFFFF407 H'FFFFF408 H'FFFFF409 TSTR2 TSTR1 TSTR3 — PSCR1 — PSCR2 — PSCR3 — STR1B,2B STR2A — — PSC1D — PSC2D — PSC3D — PSC4D — — — — PSC1C — PSC2C — PSC3C — PSC4C — — — — — — — — — — — — — — — — — — — — — PSC3E — PSC4E — — H'FFFFF40A PSCR4 H'FFFFF40B — H'FFFFF40C to — H'FFFFF41F H'FFFFF420 H'FFFFF421 H'FFFFF422 H'FFFFF423 H'FFFFF424 H'FFFFF425 H'FFFFF426 H'FFFFF427 H'FFFFF428 H'FFFFF429 ITVRR1 — ITVRR2A — ITVRR2B — ICR0DL ICR0DH ITVA9 — ITVA13A — ITVA13B — ITVA8 — ITVA12A — ITVA12B — ITVA7 — ITVA11A — ITVA11B — ITVA6 — ITVA10A — ITVA10B — ITVE9 — ITVE13A — ITVE13B — ITVE8 — ITVE12A — ITVE12B — ITVE7 — ITVE11A — ITVE11B — ITVE6 — ITVE10A — ITVE10B — Rev. 3.0, 09/04, page 1055 of 1086 Register Name Abbreviation Bit Names Bit 7 IO0D1 — — IIF2B — — Bit 6 IO0D0 — — IIF2A — — Bit 5 IO0C1 — — IIF1 — — Bit 4 IO0C0 — — OVF0 — OVE0 Bit 3 IO0B1 — — ICF0D — ICE0D Bit 2 IO0B0 — — ICF0C — ICE0C Bit 1 IO0A1 — — ICF0B — ICE0B Bit 0 IO0A0 — — ICF0A — ICE0A Module ATU-II (Channel 0) H'FFFFF42A TIOR0 H'FFFFF42B — H'FFFFF42C TSR0 H'FFFFF42D H'FFFFF42E TIER0 H'FFFFF42F H'FFFFF430 H'FFFFF431 H'FFFFF432 H'FFFFF433 H'FFFFF434 H'FFFFF435 H'FFFFF436 H'FFFFF437 H'FFFFF438 H'FFFFF439 H'FFFFF43A ICR0BL H'FFFFF43B H'FFFFF43C ICR0CH H'FFFFF43D H'FFFFF43E ICR0CL H'FFFFF43F H'FFFFF440 H'FFFFF441 H'FFFFF442 H'FFFFF443 H'FFFFF444 H'FFFFF445 H'FFFFF446 H'FFFFF447 H'FFFFF448 H'FFFFF449 H'FFFFF44A GR1D H'FFFFF44B H'FFFFF44C GR1E H'FFFFF44D H'FFFFF44E GR1F H'FFFFF44F H'FFFFF450 H'FFFFF451 H'FFFFF452 H'FFFFF453 GR1H GR1G GR1C GR1B GR1A TCNT1B TCNT1A ICR0BH ICR0AL ICR0AH TCNT0L TCNT0H ATU-II (Channel 1) Rev. 3.0, 09/04, page 1056 of 1086 Register Name H'FFFFF454 H'FFFFF455 H'FFFFF456 H'FFFFF457 H'FFFFF458 H'FFFFF459 Abbreviation OCR1 Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (Channel 1) OSBR1 TIOR1B TIOR1A — — — — — — — IMF1H IO1D2 IO1B2 IO1H2 IO1F2 — — — IMF1G — — — IME1G — — — — OVF5 IMF4B OVE5 IME4B — — IO1D1 IO1B1 IO1H1 IO1F1 CKEGB1 CKEGA1 — IMF1F — — — IME1F — — — — IMF5D IMF4A IME5D IME4A — — IO1D0 IO1B0 IO1H0 IO1F0 CKEGB0 CKEGA0 — IMF1E — — — IME1E — — — — IMF5C OVF3 IME5C OVE3 — — — — — — IO1C2 IO1A2 IO1G2 IO1E2 IO1C1 IO1A1 IO1G1 IO1E1 IO1C0 IO1A0 IO1G0 IO1E0 H'FFFFF45A TIOR1D H'FFFFF45B TIOR1C H'FFFFF45C TCR1B H'FFFFF45D TCR1A H'FFFFF45E H'FFFFF45F H'FFFFF460 H'FFFFF461 H'FFFFF462 H'FFFFF463 H'FFFFF464 H'FFFFF465 H'FFFFF466 H'FFFFF467 to H'FFFFF47F H'FFFFF480 H'FFFFF481 H'FFFFF482 H'FFFFF483 H'FFFFF484 H'FFFFF485 to H'FFFFF49F TMDR — TIER3 TIER1B TIER1A TSR1B TSR1A CKSELB3 CKSELB2 CKSELB1 CKSELB0 CKSELA3 CKSELA2 CKSELA1 CKSELA0 — IMF1D — — — IME1D — — — — IMF5B IMF3D IME5B IME3D — — — IMF1C — — — IME1C — — — — IMF5A IMF3C IME5A IME3C T5PWM — — IMF1B — — — IME1B — — — — OVF4 IMF3B OVE4 IME3B T4PWM — OVF1A IMF1A OVF1B CMF1 OVE1A IME1A OVE1B CME1 — — IMF4D IMF3A IME4D IME3A T3PWM — — ATU-II (Channel 3) — ATU-II (Channel 3 to 5) — — — IME1H — — TRGMDR TRGMD — TSR3 — — IMF4C — IME4C — — H'FFFFF4A0 TCNT3 H'FFFFF4A1 H'FFFFF4A2 GR3A H'FFFFF4A3 H'FFFFF4A4 GR3B H'FFFFF4A5 H'FFFFF4A6 GR3C H'FFFFF4A7 H'FFFFF4A8 GR3D H'FFFFF4A9 H'FFFFF4AA TIOR3B H'FFFFF4AB TIOR3A H'FFFFF4AC TCR3 CCI3D CCI3B — IO3D2 IO3B2 — IO3D1 IO3B1 CKEG1 IO3D0 IO3B0 CKEG0 CCI3C CCI3A CKSEL3 IO3C2 IO3A2 CKSEL2 IO3C1 IO3A1 CKSEL1 IO3C0 IO3A0 CKSEL0 Rev. 3.0, 09/04, page 1057 of 1086 Register Name Abbreviation Bit Names Bit 7 — Bit 6 — Bit 5 — Bit 4 — Bit 3 — Bit 2 — Bit 1 — Bit 0 — Module — ATU-II (Channel 4) H'FFFFF4AD to — H'FFFFF4BF H'FFFFF4C0 TCNT4 H'FFFFF4C1 H'FFFFF4C2 GR4A H'FFFFF4C3 H'FFFFF4C4 GR4B H'FFFFF4C5 H'FFFFF4C6 GR4C H'FFFFF4C7 H'FFFFF4C8 GR4D H'FFFFF4C9 H'FFFFF4CA TIOR4B H'FFFFF4CB TIOR4A H'FFFFF4CC TCR4 H'FFFFF4CD to — H'FFFFF4DF H'FFFFF4E0 TCNT5 H'FFFFF4E1 H'FFFFF4E2 GR5A H'FFFFF4E3 H'FFFFF4E4 GR5B H'FFFFF4E5 H'FFFFF4E6 GR5C H'FFFFF4E7 H'FFFFF4E8 GR5D H'FFFFF4E9 H'FFFFF4EA TIOR5B H'FFFFF4EB TIOR5A H'FFFFF4EC TCR5 H'FFFFF4ED to — H'FFFFF4EF H'FFFFF500 H'FFFFF501 H'FFFFF502 H'FFFFF503 H'FFFFF504 H'FFFFF505 H'FFFFF506 H'FFFFF507 TCNT6D TCNT6C TCNT6B TCNT6A CCI4D CCI4B — — IO4D2 IO4B2 — — IO4D1 IO4B1 CKEG1 — IO4D0 IO4B0 CKEG0 — CCI4C CCI4A CKSEL3 — IO4C2 IO4A2 CKSEL2 — IO4C1 IO4A1 CKSEL1 — IO4C0 IO4A0 CKSEL0 — — ATU-II (Channel 5) CCI5D CCI5B — — IO5D2 IO5B2 — — IO5D1 IO5B1 CKEG1 — IO5D0 IO5B0 CKEG0 — CCI5C CCI5A CKSEL3 — IO5C2 IO5A2 CKSEL2 — IO5C1 IO5A1 CKSEL1 — IO5C0 IO5A0 CKSEL0 — — ATU-II (Channel 6) Rev. 3.0, 09/04, page 1058 of 1086 Register Name H'FFFFF508 H'FFFFF509 Abbreviation CYLR6A Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (Channel 6) H'FFFFF50A CYLR6B H'FFFFF50B H'FFFFF50C CYLR6C H'FFFFF50D H'FFFFF50E CYLR6D H'FFFFF50F H'FFFFF510 H'FFFFF511 H'FFFFF512 H'FFFFF513 H'FFFFF514 H'FFFFF515 H'FFFFF516 H'FFFFF517 H'FFFFF518 H'FFFFF519 H'FFFFF51A DTR6B H'FFFFF51B H'FFFFF51C DTR6C H'FFFFF51D H'FFFFF51E DTR6D H'FFFFF51F H'FFFFF520 H'FFFFF521 H'FFFFF522 H'FFFFF523 H'FFFFF524 H'FFFFF525 H'FFFFF526 H'FFFFF527 to H'FFFFF57F H'FFFFF580 H'FFFFF581 H'FFFFF582 H'FFFFF583 H'FFFFF584 H'FFFFF585 H'FFFFF586 H'FFFFF587 TCNT7D TCNT7C TCNT7B PMDR — TCNT7A TIER6 TCR6B TCR6A TSR6 — — — UD6D — — DTSELD — CKSELD2 CKSELD1 CKSELD0 — CKSELB2 CKSELB1 CKSELB0 — — UD6C — — DTSELC — — UD6B — — DTSELB — — UD6A — — DTSELA — — CMF6D — CME6D CKSELC2 CKSELC1 CKSELC0 CKSELA2 CKSELA1 CKSELA0 — CMF6C — CME6C — CMF6B — CME6B — CMF6A — CME6A DTR6A BFR6D BFR6C BFR6B BFR6A CNTSELD CNTSELC CNTSELB CNTSELA — — — — — ATU-II (Channel 7) Rev. 3.0, 09/04, page 1059 of 1086 Register Name H'FFFFF588 H'FFFFF589 Abbreviation CYLR7A Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (Channel 7) H'FFFFF58A CYLR7B H'FFFFF58B H'FFFFF58C CYLR7C H'FFFFF58D H'FFFFF58E CYLR7D H'FFFFF58F H'FFFFF590 H'FFFFF591 H'FFFFF592 H'FFFFF593 H'FFFFF594 H'FFFFF595 H'FFFFF596 H'FFFFF597 H'FFFFF598 H'FFFFF599 H'FFFFF59A DTR7B H'FFFFF59B H'FFFFF59C DTR7C H'FFFFF59D H'FFFFF59E DTR7D H'FFFFF59F H'FFFFF5A0 TCR7B H'FFFFF5A1 TCR7A H'FFFFF5A2 TSR7 H'FFFFF5A3 H'FFFFF5A4 TIER7 H'FFFFF5A5 H'FFFFF5A6 to — H'FFFFF5BF H'FFFFF5C0 TCNT11 H'FFFFF5C1 H'FFFFF5C2 GR11A H'FFFFF5C3 H'FFFFF5C4 GR11B H'FFFFF5C5 H'FFFFF5C6 TIOR11 H'FFFFF5C7 — — — IO11B2 — IO11B1 — IO11B0 — — — IO11A2 — IO11A1 — IO11A0 — — — — UD7D — — — CKSELD2 CKSELD1 CKSELD0 — CKSELB2 CKSELB1 CKSELB0 — — UD7C — — — — UD7B — — — — UD7A — — — — CMF7D — CME7D — CKSELC2 CKSELC1 CKSELC0 CKSELA2 CKSELA1 CKSELA0 — CMF7C — CME7C — — CMF7B — CME7B — — CMF7A — CME7A — — ATU-II (Channel 11) DTR7A BFR7D BFR7C BFR7B BFR7A Rev. 3.0, 09/04, page 1060 of 1086 Register Name Abbreviation Bit Names Bit 7 — — — — — — — Bit 6 — — — — — — — Bit 5 CKEG1 — — — — — — Bit 4 CKEG0 — — — — — — Bit 3 — — — — — — — Bit 2 Bit 1 Bit 0 Module H'FFFFF5C8 TCR11 H'FFFFF5C9 — H'FFFFF5CA TSR11 H'FFFFF5CB H'FFFFF5CC TIER11 H'FFFFF5CD H'FFFFF5CE to — H'FFFFF5FF H'FFFFF600 H'FFFFF601 H'FFFFF602 H'FFFFF603 H'FFFFF604 H'FFFFF605 H'FFFFF606 H'FFFFF607 H'FFFFF608 H'FFFFF609 H'FFFFF60A GR2D H'FFFFF60B H'FFFFF60C GR2E H'FFFFF60D H'FFFFF60E GR2F H'FFFFF60F H'FFFFF610 H'FFFFF611 H'FFFFF612 H'FFFFF613 H'FFFFF614 H'FFFFF615 H'FFFFF616 H'FFFFF617 H'FFFFF618 H'FFFFF619 H'FFFFF61A OCR2D H'FFFFF61B H'FFFFF61C OCR2E H'FFFFF61D H'FFFFF61E OCR2F H'FFFFF61F OCR2C OCR2B OCR2A GR2H GR2G GR2C GR2B GR2A TCNT2B TCNT2A CKSELA2 CKSELA1 CKSELA0 ATU-II — — — — — — — — IMF11B — IME11B — — OVF11 IMF11A OVE11 IME11A — — ATU-II (Channel 2) (Channel 11) Rev. 3.0, 09/04, page 1061 of 1086 Register Name H'FFFFF620 H'FFFFF621 H'FFFFF622 H'FFFFF623 H'FFFFF624 H'FFFFF625 H'FFFFF626 H'FFFFF627 H'FFFFF628 H'FFFFF629 Abbreviation OCR2G Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (Channel 2) OCR2H OSBR2 TIOR2B TIOR2A TIOR2D TIOR2C — — — — — — — IMF2H IO2D2 IO2B2 IO2H2 IO2F2 — — — IMF2G — CMF2G — IME2G — CME2G — IO2D1 IO2B1 IO2H1 IO2F1 CKEGB1 CKEGA1 — IMF2F — CMF2F — IME2F — CME2F — IO2D0 IO2B0 IO2H0 IO2F0 CKEGB0 CKEGA0 — IMF2E — CMF2E — IME2E — CME2E — — — — — IO2C2 IO2A2 IO2G2 IO2E2 IO2C1 IO2A1 IO2G1 IO2E1 IO2C0 IO2A0 IO2G0 IO2E0 H'FFFFF62A TCR2B H'FFFFF62B TCR2A H'FFFFF62C TSR2A H'FFFFF62D H'FFFFF62E H'FFFFF62F H'FFFFF630 H'FFFFF631 H'FFFFF632 H'FFFFF633 H'FFFFF634 to H'FFFFF63F H'FFFFF640 H'FFFFF641 H'FFFFF642 H'FFFFF643 H'FFFFF644 H'FFFFF645 H'FFFFF646 H'FFFFF647 H'FFFFF648 H'FFFFF649 H'FFFFF64A DCNT8F H'FFFFF64B H'FFFFF64C DCNT8G H'FFFFF64D H'FFFFF64E DCNT8H H'FFFFF64F H'FFFFF650 H'FFFFF651 DCNT8I DCNT8E DCNT8D DNCT8C DNCT8B — DCNT8A TIER2B TIER2A TSR2B CKSELB3 CKSELB2 CKSELB1 CKSELB0 CKSELA3 CKSELA2 CKSELA1 CKSELA0 — IMF2D — CMF2D — IME2D — CME2D — — IMF2C — CMF2C — IME2C — CME2C — — IMF2B — CMF2B — IME2B — CME2B — OVF2A IMF2A OVF2B CMF2A OVE2A IME2A OVE2B CME2A — — ATU-II (Channel 8) — CMF2H — IME2H — CME2H — Rev. 3.0, 09/04, page 1062 of 1086 Register Name H'FFFFF652 H'FFFFF653 H'FFFFF654 H'FFFFF655 H'FFFFF656 H'FFFFF657 H'FFFFF658 H'FFFFF659 Abbreviation DCNT8J Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (Channel 8) DCNT8K DCNT8L DCNT8M H'FFFFF65A DCNT8N H'FFFFF65B H'FFFFF65C DCNT8O H'FFFFF65D H'FFFFF65E DCNT8P H'FFFFF65F H'FFFFF660 H'FFFFF661 H'FFFFF662 H'FFFFF663 H'FFFFF664 H'FFFFF665 H'FFFFF666 H'FFFFF667 H'FFFFF668 H'FFFFF669 H'FFFFF66A H'FFFFF66B H'FFFFF66C TIER8 H'FFFFF66D H'FFFFF66E RLDENR H'FFFFF66F to H'FFFFF67F H'FFFFF680 H'FFFFF681 H'FFFFF682 H'FFFFF683 H'FFFFF684 H'FFFFF685 H'FFFFF686 H'FFFFF687 H'FFFFF688 H'FFFFF689 — ECNT9A — ECNT9B — ECNT9C — ECNT9D — ECNT9E — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TCR8 — TSR8 DSTR OTR TCNR CN8P CN8H OTEP OTEH DST8P DST8H — — OSF8P OSF8H OSE8P OSE8H RLDEN — CN8O CN8G OTEO OTEG DST8O DST8G CN8N CN8F OTEN OTEF DST8N DST8F CN8M CN8E OTEM OTEE DST8M DST8E CN8L CN8D OTEL OTED DST8L DST8D CN8K CN8C OTEK OTEC DST8K DST8C CN8J CN8B OTEJ OTEB DST8J DST8B CN8I CN8A OTEI OTEA DST8I DST8A RLDR8 CKSELB2 CKSELB1 CKSELB0 — — OSF8O OSF8G OSE8O OSE8G — — — OSF8N OSF8F OSE8N OSE8F — — — OSF8M OSF8E OSE8M OSE8E — — — OSF8L OSF8D OSE8L OSE8D — — CKSELA2 CKSELA1 CKSELA0 — OSF8K OSF8C OSE8K OSE8C — — — OSF8J OSF8B OSE8J OSE8B — — — OSF8I OSF8A OSE8I OSE8A — — — ATU-II (Channel 9) Rev. 3.0, 09/04, page 1063 of 1086 Register Name Abbreviation Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II — — — — — — — — (Channel 9) H'FFFFF68A ECNT9F H'FFFFF68B — H'FFFFF68C GR9A H'FFFFF68D — H'FFFFF68E GR9B H'FFFFF68F H'FFFFF690 H'FFFFF691 H'FFFFF692 H'FFFFF693 H'FFFFF694 H'FFFFF695 H'FFFFF696 H'FFFFF697 H'FFFFF698 H'FFFFF699 — GR9C — GR9D — GR9E — GR9F — TCR9A — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRG3BEN EGSELB1 EGSELB0 — — — — — TRG3AEN EGSELA1 EGSELA0 — — — H'FFFFF69A TCR9B H'FFFFF69B — H'FFFFF69C TCR9C H'FFFFF69D — H'FFFFF69E TSR9 H'FFFFF69F H'FFFFF6A0 TIER9 H'FFFFF6A1 H'FFFFF6A2 to — H'FFFFF6BF H'FFFFF6C0 TCNT10A H H'FFFFF6C1 H'FFFFF6C2 TCNT10A L H'FFFFF6C3 H'FFFFF6C4 TCNT10B H'FFFFF6C5 — H'FFFFF6C6 TCNT10C H'FFFFF6C7 H'FFFFF6C8 TCNT10D H'FFFFF6C9 — H'FFFFF6CA TCNT10E H'FFFFF6CB H'FFFFF6CC TCNT10F H'FFFFF6CD TRG3DEN EGSELD1 EGSELD0 — — — — — — — — — — — — TRG3CEN EGSELC1 EGSELC0 — — — — CMF9C — CME9C — — — EGSELF1 EGSELF0 — — — CMF9F — CME9F — — — CMF9E — CME9E — — — CMF9D — CME9D — EGSELE1 EGSELE0 — — CMF9B — CME9B — — — CMF9A — CME9A — — ATU-II (Channel 10) — — — — — — — — — — — — — — — — Rev. 3.0, 09/04, page 1064 of 1086 Register Name Abbreviation Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ATU-II (Channel 10) H'FFFFF6CE TCNT10G H'FFFFF6CF H'FFFFF6D0 ICR10AH H'FFFFF6D1 H'FFFFF6D2 ICR10AL H'FFFFF6D3 H'FFFFF6D4 OCR10AH H'FFFFF6D5 H'FFFFF6D6 OCR10AL H'FFFFF6D7 H'FFFFF6D8 OCR10B H'FFFFF6D9 — H'FFFFF6DA RLD10C H'FFFFF6DB H'FFFFF6DC GR10G H'FFFFF6DD H'FFFFF6DE TCNT10H H'FFFFF6DF — H'FFFFF6E0 NCR10 H'FFFFF6E1 — H'FFFFF6E2 TIOR10 H'FFFFF6E3 — H'FFFFF6E4 TCR10 H'FFFFF6E5 — H'FFFFF6E6 TCCLR10 H'FFFFF6E7 H'FFFFF6E8 TSR10 H'FFFFF6E9 H'FFFFF6EA TIER10 H'FFFFF6EB H'FFFFF6EC to — H'FFFFF6FF H'FFFFF700 H'FFFFF701 H'FFFFF702 to H'FFFFF707 H'FFFFF708 H'FFFFF709 POPCR — — — — — — — — — — — — — — — — — — IREG — — CMF10G — CME10G — — CMF10B — CME10B — — ICF10A — ICE10A — — CMF10A — CME10A — — RLDEN — — CCS — — PIM1 — — PIM0 — — — — — IO10G2 — — IO10G1 — CKEG1 — — IO10G0 — CKEG0 — — — — — — — — — — — — — — — — — ATU-II (Channel 10) TRG2BEN TRG1BEN TRG2AEN TRG1AEN TRG0DEN NCE — — — — — — — PULS7RO PULS6RO PULS5RO PULS4RO PULS3RO PULS2RO PULS1RO PULS0RO APC E E E E E E E E PULS7SO PULS6SO PULS5SO PULS4SO PULS3SO PULS2SO PULS1SO PULS0SO E E E E E E E E — SYSCR1 — 1 — — — — — — — — — — — — — — — — MSTOP3 — — — — MSTOP2 — — — Power-Down State OSCSTOP INOSCE — — — — AUDSRST RAME — — MSTOP1 — — MSTOP0 H'FFFFF70A SYCSR2* — H'FFFFF70B SYCSR2* CKSEL 2 Rev. 3.0, 09/04, page 1065 of 1086 Register Name Abbreviation Bit Names Bit 7 — — — Bit 6 — — — — CMIE Bit 5 — — — — — Bit 4 — — — — — Bit 3 — — — — — Bit 2 — — — — — Bit 1 — — STR1 — CKS1 Bit 0 — — STR0 — CKS0 Module — CMT H'FFFFF70C to — H'FFFFF70F H'FFFFF710 H'FFFFF711 H'FFFFF712 H'FFFFF713 H'FFFFF714 CMCNT0 CMCSR0 CMSTR — CMF Notes: * This is the read address. The write address is H'FFFFF70A. For details, see section 25.2.4, Notes on Register Access. 1. Program in the word unit. Programming in the byte or longword unit is not enabled. 2. Read in the byte unit. Correct values cannot be read in the word or longword unit. Rev. 3.0, 09/04, page 1066 of 1086 Register Name Abbreviation Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module CMT H'FFFFF715 CMCNT0 H'FFFFF716 CMCOR0 H'FFFFF717 H'FFFFF718 CMCSR1 H'FFFFF719 H'FFFFF71A CMCNT1 H'FFFFF71B H'FFFFF71C CMCOR1 H'FFFFF71D H'FFFFF71E — H'FFFFF71F — H'FFFFF720 PAIOR H'FFFFF721 H'FFFFF722 PACRH H'FFFFF723 H'FFFFF724 PACRL H'FFFFF725 H'FFFFF726 PADR H'FFFFF727 H'FFFFF728 PHIOR H'FFFFF729 H'FFFFF72A PHCR H'FFFFF72B H'FFFFF72C PHDR H'FFFFF72D — — PA15IOR PA7IOR — — — PA14IOR PA6IOR PA15MD — — PA13IOR PA5IOR — — — PA12IOR PA4IOR PA14MD — — PA11IOR PA3IOR — — — PA10IOR PA2IOR PA13MD — — PA9IOR PA1IOR — PA8MD1 — — PA9DR PA1DR PH9IOR PH1IOR PH9MD PH1MD PH9DR PH1DR — — PB9IOR PB1IOR — — PA8IOR PA0IOR PA12MD PA8MD0 PA4MD PA0MD PA8DR PA0DR PH8IOR PH0IOR PH8MD PH0MD PH8DR PH0DR — — PB8IOR PB0IOR — CMF — CMIE — — — — — — — — — CKS1 — CKS0 Port A PA11MD1 PA11MD0 PA10MD1 PA10MD0 PA10MD1 PA9MD0 — — PA15DR PA7DR PH15IOR PH7IOR PH15MD PH7MD PH15DR PH7DR PA7MD PA3MD PA14DR PA6DR PH14IOR PH6IOR PH14MD PH6MD PH14DR PH6DR — — PB14IOR PB6IOR — — PA13DR PA5DR PH13IOR PH5IOR PH13MD PH5MD PH13DR PH5DR — — PB13IOR PB5IOR PA6MD PA2MD PA12DR PA4DR PH12IOR PH4IOR PH12MD PH4MD PH12DR PH4DR — — PB12IOR PB4IOR — — PA11DR PA3DR PH11IOR PH3IOR PH11MD PH3MD PH11DR PH3DR — — PB11IOR PB3IOR PA5MD PA1MD PA10DR PA2DR PH10IOR PH2IOR PH10MD PH2MD PH10DR PH2DR — — PB10IOR PB2IOR PB13MD PB9MD0 PB5MD0 PB1MD PB10IR PB2IR PB10DR PB2DR — PC2IOR — PC1MD Port H H'FFFFF72E ADTRGR1 EXTRG H'FFFFF72F ADTRGR2 EXTRG H'FFFFF730 PBIOR H'FFFFF731 H'FFFFF732 PBCRH H'FFFFF733 H'FFFFF734 PBCRL H'FFFFF735 H'FFFFF736 PBIR H'FFFFF737 H'FFFFF738 PBDR H'FFFFF739 H'FFFFF73A PCIOR H'FFFFF73B H'FFFFF73C PCCR H'FFFFF73D PB15IOR PB7IOR A/D Port B PB15MD1 PB15MD0 PB14MD1 PB14MD0 — PB11MD1 PB11MD0 PB10MD1 PB10MD0 PB9MD1 PB7MD1 — PB15IR PB7IR PB15DR PB7DR — — — — PB7MD0 PB3MD PB14IR PB6IR PB14DR PB6DR — — — PC3MD PB6MD1 — PB13IR PB5IR PB13DR PB5DR — — — — PB6MD0 PB2MD — PB4IR PB12DR PB4DR — PC4IOR — PC2MD PB5MD1 — PB11IR PB3IR PB11DR PB3DR — PC3IOR — — PB12MD1 PB12MD0 PB8MD1 PB4MD1 — PB9IR PB1IR PB9DR PB1DR — PC1IOR — — PB8MD0 PB4MD0 PB0MD PB8IR PB0IR PB8DR PB0DR — PC0IOR PC4MD PC0MD Port C Rev. 3.0, 09/04, page 1067 of 1086 Register Name Abbreviation Bit Names Bit 7 — — — PD7IOR — — — — — PD7DR PF15IOR PF7IOR CKHIZ — — — PF15DR PF7DR PE15IOR PE7IOR PE15MD PE7MD PE15DR PE7DR — PL7IOR — PL11MD1 — — — PL7IR — PL7DR — — — PG3MD1 — — Bit 6 — — — PD6IOR — PD11MD PD7MD PD3MD — PD6DR PF14IOR PF6IOR PF15MD PF11MD PF7MD PF3MD PF14DR PF6DR PE14IOR PE6IOR PE14MD PE6MD PE14DR PE6DR — PL6IOR — PL11MD0 PL7MD PL3MD — — — PL6DR — — — PG3MD0 — — Bit 5 — — PD13IOR PD5IOR — — — — PD13DR PD5DR PF13IOR PF5IOR — — — — PF13DR PF5DR PE13IOR PE5IOR PE13MD PE5MD PE13DR PE5DR PL13IOR PL5IOR — PL10MD1 — PL2MD1 — — PL13DR PL5DR — — — PG2MD1 — — Bit 4 — PC4DR PD12IOR PD4IOR — PD10MD PD6MD PD2MD PD12DR PD4DR PF12IOR PF4IOR PF14MD PF10MD PF6MD PF2MD PF12DR PF4DR PE12IOR PE4IOR PE12MD PE4MD PE12DR PE4DR PL12IOR PL4IOR — PL10MD0 PL6MD PL2MD0 — — PL12DR PL4DR — — — PG2MD0 — — Bit 3 — PC3DR PD11IOR PD3IOR Bit 2 — PC2DR PD10IOR PD2IOR Bit 1 — PC1DR PD9IOR PD1IOR Bit 0 — PC0DR PD8IOR PD0IOR PD12MD PD8MD PD4MD PD0MD PD8DR PD0DR PF8IOR PF0IOR PF12MD PF8MD PF4MD PF0MD PF8DR PF0DR PE8IOR PE0IOR PE8MD PE0MD PE8DR PE0DR PL8IOR PL0IOR PL12MD PL8MD PL4MD PL0MD0 PL8IR — PL8DR PL0DR — PG0IOR — PG0MD0 — PG0DR Port G Port L Port E Port F Port D Module Port C H'FFFFF73E PCDR H'FFFFF73F H'FFFFF740 PDIOR H'FFFFF741 H'FFFFF742 PDCRH H'FFFFF743 H'FFFFF744 PDCRL H'FFFFF745 H'FFFFF746 PDDR H'FFFFF747 H'FFFFF748 PFIOR H'FFFFF749 H'FFFFF74A PFCRH H'FFFFF74B H'FFFFF74C PFCRL H'FFFFF74D H'FFFFF74E PFDR H'FFFFF74F H'FFFFF750 PEIOR H'FFFFF751 H'FFFFF752 PECR H'FFFFF753 H'FFFFF754 PEDR H'FFFFF755 H'FFFFF756 PLIOR H'FFFFF757 H'FFFFF758 PLCRH H'FFFFF759 H'FFFFF75A PLCRL H'FFFFF75B H'FFFFF75C PLIR H'FFFFF75D H'FFFFF75E PLDR H'FFFFF75F H'FFFFF760 PGIOR H'FFFFF761 H'FFFFF762 PGCR H'FFFFF763 H'FFFFF764 PGDR H'FFFFF765 PD13MD1 PD13MD0 — — — — PD11DR PD3DR PF11IOR PF3IOR — — PF5MD1 — PF11DR PF3DR PE11IOR PE3IOR PE11MD PE3MD PE11DR PE3DR PL11IOR PL3IOR PL13MD1 PL9MD1 — PL1MD1 — — PL11DR PL3DR — PG3IOR — — — PG3DR PD9MD PD5MD PD1MD PD10DR PD2DR PF10IOR PF2IOR PF13MD PF9MD PF5MD0 PF1MD PF10DR PF2DR PE10IOR PE2IOR PE10MD PE2MD PE10DR PE2DR PL10IOR PL2IOR PL13MD0 PL9MD0 PL5MD PL1MD0 — — PL10DR PL2DR — PG2IOR — PG1MD — PG2DR — — — PD9DR PD1DR PF9IOR PF1IOR — — — — PF9DR PF1DR PE9IOR PE1IOR PE9MD PE1MD PE9DR PE1DR PL9IOR PL1IOR — — — — PL9IR — PL9DR PL1DR — PG1IOR — PG0MD1 — PG1DR Rev. 3.0, 09/04, page 1068 of 1086 Register Name Abbreviation Bit Names Bit 7 PJ15IOR PJ7IOR — — — — PJ15DR PJ7DR EXTRG — PK15IOR PK7IOR — — — — PK15IR PK7IR PK15DR PK7DR — PA15PR PA7PR PB15PR PB7PR PD15PR PD7PR PJ15PR PJ7PR PL15PR PL7PR — Bit 6 PJ14IOR PJ6IOR PJ15MD PJ11MD PJ7MD PJ3MD PJ14DR PJ6DR — — PK14IOR PK6IOR PK15MD PK11MD PK7MD PK3MD PK14IR PK6IR PK14DR PK6DR — PA14PR PA6PR PB14PR PB6PR PD14PR PD6PR PJ14PR PJ6PR PL14PR PL6PR — Bit 5 PJ13IOR PJ5IOR — — — — PJ13DR PJ5DR — — PK13IOR PK5IOR — — — — PK13IR PK5IR PK13DR PK5DR — PA13PR PA5PR PB13PR PB5PR PD13PR PD5PR PJ13PR PJ5PR PL13PR PL5PR — Bit 4 PJ12IOR PJ4IOR PJ14MD PJ10MD PJ6MD PJ2MD PJ12DR PJ4DR — — PK12IOR PK4IOR PK14MD PK10MD PK6MD PK2MD PK12IR PK4IR PK12DR PK4DR — PA12PR PA4PR PB12PR PB4PR PD12PR PD4PR PJ12PR PJ4PR PL12PR PL4PR — Bit 3 PJ11IOR PJ3IOR — — — — PJ11DR PJ3DR — — PK11IOR PK3IOR — — — — PK11IR PK3IR PK11DR PK3DR — PA11PR PA3PR PB11PR PB3PR PD11PR PD3PR PJ11PR PJ3PR PL11PR PL3PR — Bit 2 PJ10IOR PJ2IOR PJ13MD PJ9MD PJ5MD PJ1MD PJ10DR PJ2DR — — PK10IOR PK2IOR PK13MD PK9MD PK5MD PK1MD PK10IR PK2IR PK10DR PK2DR — PA10PR PA2PR PB10PR PB2PR PD10PR PD2PR PJ10PR PJ2PR PL10PR PL2PR — Bit 1 PJ9IOR PJ1IOR — — — — PJ9DR PJ1DR — — PK9IOR PK1IOR — — — — PK9IR PK1IR PK9DR PK1DR — PA9PR PA1PR PB9PR PB1PR PD9PR PD1PR PJ9PR PJ1PR PL9PR PL1PR — Bit 0 PJ8IOR PJ0IOR PJ12MD PJ8MD PJ4MD PJ0MD PJ8DR PJ0DR — — PK8IOR PK0IOR PK12MD PK8MD PK4MD PK0MD PK8IR PK0IR PK8DR PK0DR — PA8PR PA0PR PB8PR PB0PR PD8PR PD0PR PJ8PR PJ0PR PL8PR PL0PR — — Port L Port J Port D Port B — Port A Port K A/D Module Port J H'FFFFF766 PJIOR H'FFFFF767 H'FFFFF768 PJCRH H'FFFFF769 H'FFFFF76A PJCRL H'FFFFF76B H'FFFFF76C PJDR H'FFFFF76D H'FFFFF76E ADTRG0 H'FFFFF76F — H'FFFFF770 PKIOR H'FFFFF771 H'FFFFF772 PKCRH H'FFFFF773 H'FFFFF774 PKCRL H'FFFFF775 H'FFFFF776 PKIR H'FFFFF777 H'FFFFF778 PKDR H'FFFFF779 H'FFFFF77A to — H'FFFFF77F H'FFFFF780 PAPR H'FFFFF781 H'FFFFF782 PBPR H'FFFFF783 H'FFFFF784 PDPR H'FFFFF785 H'FFFFF786 PJPR H'FFFFF787 H'FFFFF788 PLPR H'FFFFF789 H'FFFFF78A — to H'FFFFF7BF Rev. 3.0, 09/04, page 1069 of 1086 Register Name Abbreviation Bit Names Bit 7 TS3 — — — Bit 6 TS2 — — — Bit 5 TS1 — — — Bit 4 TS0 — — — Bit 3 — — — — Bit 2 — — — — Bit 1 — — — — Bit 0 — — — SDTRF Module H-UDI H'FFFFF7C0 SDIR H'FFFFF7C1 H'FFFFF7C2 SDSR H'FFFFF7C3 H'FFFFF7C4 SDDRH H'FFFFF7C5 H'FFFFF7C6 SDDRL H'FFFFF7C7 H'FFFFF7C8 to — H'FFFFF7FF H'FFFFF800 ADDR0H H'FFFFF801 ADDR0L H'FFFFF802 ADDR1H H'FFFFF803 ADDR1L H'FFFFF804 ADDR2H H'FFFFF805 ADDR2L H'FFFFF806 ADDR3H H'FFFFF807 ADDR3L H'FFFFF808 ADDR4H H'FFFFF809 ADDR4L H'FFFFF80A ADDR5H H'FFFFF80B ADDR5L H'FFFFF80C ADDR6H H'FFFFF80D ADDR6L H'FFFFF80E ADDR7H H'FFFFF80F ADDR7L H'FFFFF810 ADDR8H H'FFFFF811 ADDR8L H'FFFFF812 ADDR9H H'FFFFF813 ADDR9L H'FFFFF814 ADDR10H H'FFFFF815 ADDR10L H'FFFFF816 ADDR11H H'FFFFF817 ADDR11L H'FFFFF818 ADCSR0 H'FFFFF819 ADCR0 H'FFFFF81A — to H'FFFFF81F H'FFFFF820 ADDR12H H'FFFFF821 ADDR12L — AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGE — — AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE CKS — — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — ADM1 ADST — — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — ADM0 ADCS — — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — CH3 — — — ADR — ADR — ADR — ADR — ADR — ADR — ADR — ADR — ADR — ADR — ADR — ADR — CH2 — — — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — CH1 — — — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — CH0 — — — A/D AD9 AD1 AD8 AD0 AD7 — AD6 — AD5 — ADR — AD3 — AD2 — Rev. 3.0, 09/04, page 1070 of 1086 Register Name Abbreviation Bit Names Bit 7 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGE — Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE CKS — Bit 5 AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — ADM1 ADST — Bit 4 AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — ADM0 ADCS — Bit 3 AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — CH3 — — Bit 2 ADR — ADR — ADR — ADR — ADR — ADR — ADR — ADR — ADR — ADR — ADR — CH2 — — Bit 1 AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — CH1 — — Bit 0 AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — CH0 — — Module A/D H'FFFFF822 ADDR13H H'FFFFF823 ADDR13L H'FFFFF824 ADDR14H H'FFFFF825 ADDR14L H'FFFFF826 ADDR15H H'FFFFF827 ADDR15L H'FFFFF828 ADDR16H H'FFFFF829 ADDR16L H'FFFFF82A ADDR17H H'FFFFF82B ADDR17L H'FFFFF82C ADDR18H H'FFFFF82D ADDR18L H'FFFFF82E ADDR19H H'FFFFF82F ADDR19L H'FFFFF830 ADDR20H H'FFFFF831 ADDR20L H'FFFFF832 ADDR21H H'FFFFF833 ADDR21L H'FFFFF834 ADDR22H H'FFFFF835 ADDR22L H'FFFFF836 ADDR23H H'FFFFF837 ADDR23L H'FFFFF838 ADCSR1 H'FFFFF839 ADCR1 H'FFFFF83A — to H'FFFFF83F H'FFFFF840 ADDR24H H'FFFFF841 ADDR24L H'FFFFF842 ADDR25H H'FFFFF843 ADDR25L H'FFFFF844 ADDR26H H'FFFFF845 ADDR26L H'FFFFF846 ADDR27H H'FFFFF847 ADDR27L H'FFFFF848 ADDR28H H'FFFFF849 ADDR28L H'FFFFF84A ADDR29H H'FFFFF84B ADDR29L H'FFFFF84C ADDR30H H'FFFFF84D ADDR30L H'FFFFF84E ADDR31H AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 ADR — ADR — ADR — ADR — ADR — ADR — ADR — ADR AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 Rev. 3.0, 09/04, page 1071 of 1086 Register Name Abbreviation Bit Names Bit 7 AD1 — Bit 6 AD0 — Bit 5 — — Bit 4 — — Bit 3 — — Bit 2 — — Bit 1 — — Bit 0 — — Module A/D H'FFFFF84F ADDR31L H'FFFFF850 — to H'FFFFF857 H'FFFFF858 ADCSR2 H'FFFFF859 ADCR2 H'FFFFF85A to — H'FFFFF85F H'FFFFF860 ADCNT0 H'FFFFF861 H'FFFFF862 ADCYLR0 H'FFFFF863 H'FFFFF864 ADDR0A H'FFFFF865 H'FFFFF866 ADDR0B H'FFFFF867 H'FFFFF868 ADGR0A H'FFFFF869 H'FFFFF86A ADGR0B H'FFFFF86B H'FFFFF86C ADTCR0 H'FFFFF86D ADTSR0 H'FFFFF86E ADTIER0 H'FFFFF86F H'FFFFF870 ADCNT1 H'FFFFF871 H'FFFFF872 ADCYLR1 H'FFFFF873 H'FFFFF874 ADDR1A H'FFFFF875 H'FFFFF876 ADDR1B H'FFFFF877 H'FFFFF878 ADGR1A H'FFFFF879 H'FFFFF87A ADGR1B H'FFFFF87B H'FFFFF87C ADTCR1 H'FFFFF87D ADTSR1 H'FFFFF87E ADTIER1 H'FFFFF87F ADF TRGE — ADIE CKS — ADM1 ADST — ADM0 ADCS — — — — CH2 — — CH1 — — CH0 — — — MTAD CKSEL1x — ADTRGx CKSEL0x TADFxB TADExB — TADFxA TADExA — ADDFxB ADDExB DTSELxB ADDFxA ADDExA DTSELxA ADCYLFx ADSELxB ADSELxA ADCMFxB ADCMFxA ADCYLEx ADCMExB ADCNExA CKSEL1x — ADTRGx CKSEL0x TADFxB TADExB — TADFxA TADExA — ADDFxB ADDExB DTSELxB ADDFxA ADDExA DTSELxA ADCYLFx ADSELxB ADSELxA ADCMFxB ADCMFxA ADCYLEx ADCMExB ADCNExA Rev. 3.0, 09/04, page 1072 of 1086 A.2 Register States in Reset and Power-Down States Register States in Reset and Power-Down States Reset State Power-Down State Hardware Standby Initialized Software Standby Held Sleep Held Table A.2 Type CPU Name R0 to R15 SR GBR VBR MACH, MACL PR PC Power-On Initialized FPU FR0 to FR15 FPUL FPSCR Initialized Initialized Held Held Interrupt controller (INTC) IPRA to IPRL ICR ISR Initialized Initialized Held Held User break controller (UBC) UBARH, UBARL UBAMRH, UBAMRL UBBR UBCR Initialized Initialized Held Held Bus state controller (BSC) Direct memory access controller (DMAC) BCR1, BCR2 WCR SAR0 to SAR3 DAR0 to DAR3 DMATCR0 to DMATCR3 CHCR0 to CHCR3 DMAOR Initialized Initialized Held Held Undefined Undefined Undefined Held Initialized Initialized Initialized Advanced timer unit-II (ATU-II) BFR6A-D, BFR7A-D CYLR6A-D, CYLR7A-D DCNT8A-P DSTR Initialized Initialized Initialized Held Rev. 3.0, 09/04, page 1073 of 1086 Table A.2 Register States in Reset and Power-Down States (cont) Reset State Power-Down State Hardware Standby Initialized Software Standby Initialized Sleep Held Type Advanced timer unit-II (ATU-II) Name DTR6A-D, DTR7A-D ECNT9A-F GR1A-H, GR2A-H GR3A-D, GR4A-D GR5A-D, GR9A-F GR10G, GR11A, 11B ICR0A-D, ICR10A ITVRR1, ITVRR2A, 2B NCR10 OCR1, OCR2A-H OCR10AH, 10AL OCR10B OSBR1, OSBR2 OTR PMDR PSCR1-4 PSTR RLD10C RLDENR RLDR8 TCCLR10 TCNR TCNT0H, L, TCNT1A, 1B, TCNT2A, 2B TCNT3-5, TCNT6A-D TCNT7A-D TCNT10AH, 10AL TCNT10B-H, TCNT11 TCR1A, 1B TCR2A, 2B, TCR3-5 TCR6A, 6B, TCR7A, 7B, TCR8, TCR9A-C TCR10, TCR11 Power-On Initialized Rev. 3.0, 09/04, page 1074 of 1086 Table A.2 Register States in Reset and Power-Down States (cont) Reset State Power-Down State Hardware Standby Initialized Software Standby Initialized Sleep Held Type Advanced timer unit-II (ATU-II) Name TIER0, TIER1A, 1B TIER2A, 2B, TIER3 TIER6-11 TIOR0, TIOR1A-D TIOR2A-D, TIOR3A, 3B, TIOR4A, 4B TIOR5A, 5B TIOR10,11 TMDR TNCT10E TRGMDR TSR0, TSR1A, 1B TSR2A, 2B, TSR3 TSR6-11 TSTR1-3 Power-On Initialized Advanced pulse controller (APC) Watchdog timer (WDT) POPCR TCNT TCSR RSTCSR Initialized Initialized Initialized Initialized Held Initialized Held Held Serial communication interface (SCI) SMR0 to SMR4 BRR0 to BRR4 SCR0 to SCR4 TDR0 to TDR4 SSR0 to SSR4 RDR0 to RDR4 SDCR0 to SDCR4 Initialized Initialized Held Held Intialized Held Initialized Initialized Initialized Held A/D converter ADDR0 (H/L) to ADDR31 (H/L) ADSCR0, ADCSR1 ADCSR2 ADCR0, ADCR1 ADCR2 Rev. 3.0, 09/04, page 1075 of 1086 Table A.2 Register States in Reset and Power-Down States (cont) Reset State Power-Down State Hardware Standby Initialized Initialized Software Standby Held Initialized Sleep Held Held Type A/D converter Compare match timer (CMT) Name ADTRGR0, ADTRGR1 ADTRGR2 CMSTR CMCSR0, CMCSR1 CMCNT0, CMCNT1 CMCOR0, CMCOR1 Power-On Initialized Initialized Initialized Initialized Initialized Held Pin function controller (PFC) PAIOR, PBIOR PCIOR, PDIOR PEIOR, PFIOR PGIOR, PHIOR PJIOR, PKIOR, PLIOR PACRH, PACRL PBCRH, PBCRL PBIR, PCCR, PDCRH PDCRL, PECR PFCRH, PFCRL PGCR, PHCR, PJCRH PJCRL, PKCRH PKCRL, PKIR, PLCRH PLCRL,PLIR Initialized Initialized Held Held I/O ports PADR, PBDR, PCDR PDDR, PEDR, PFDR PGDE, PHDR, PJDR PKDR, PLDR RAMER FCCS FPCS FECS FKEY FMATS FTDAR Initialized Initialized Held Held Flash ROM Initialized Initialized Held Initialized/ Held* Initialized Held Held Initialized Rev. 3.0, 09/04, page 1076 of 1086 Table A.2 Register States in Reset and Power-Down States (cont) Reset State Power-Down State Hardware Standby Initialized Software Standby Held Sleep Held Type Power-down state related Controller area network (HCAN) Name SBYCR SYSCR1, SYSCR2 MSTCR MCR GSR HCAN_BCR 0/1 IRP IMR TXPR 0/1 TXCR 0/1 TXACK 0/1 ABACK 0/1 RXPR 0/1 RFPR 0/1 MBIMR 0/1 UMSR 0/1 TCNTR TCR TSR TMR TDCR LOSR CCR CMAX ICR 0/1 TCMR 0-2 MB Power-On Initialized Initialized Initialized Initialized Held Undefined Held Held Held Held Held Held Held High-performance SDIR user debug SDSR interface (H-UDI) SDDRH, SDDRL Note: * Bit 7 (FLER) is held, and bit 0 (SCO) is initialized. Rev. 3.0, 09/04, page 1077 of 1086 Rev. 3.0, 09/04, page 1078 of 1086 Appendix B Pin States Tables B.1, B.2, and B.3 show the SH7058 pin states. Table B.1 Pin States Pin State Reset State Power-On ROMless Expanded Mode Type Clock Pin Name CK*2 XTAL EXTAL PLLCAP System RES control FWE HSTBY MD0 MD1 MD2 WDTOVF BREQ BACK Interrupt NMI IRQ0 to IRQ7 IRQOUT Address A0 to A21 bus Data bus D0 to D7 D8 to D15 Bus control WAIT WRH, WRL RD CS0 CS1 to CS3 Port ATU-II POD TI0A to TI0D TIO1A to TIO1H TIO2A to TIO2H TIO3A to TIO3D 8 Bits O O I I I I I I I I O — — I — — O Z — I H H H — — — — — — Z — — — — — — — 16 Bits Expanded SingleH-UDI Mode with Chip Hardware Software Module ROM Mode Standby Standby Standby Z L Z I Z I I I I I Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z H *1 L I I I I I I I I O* Z Z I Z O* Z Z Z Z Z Z Z Z Z Z K*1 K*1 K *1 1 1 Power-Down State AUD Module Standby O O I I I I I I I I O I O I I O O I/O I/O I O O O O I I I/O I/O I/O BusReleased State O O I I I I I I I I O I L I I O Z Z Z I Z Z Z Z I I I/O I/O I/O O O I I I I I I I I O I O I I O O I/O I/O I O O O O I I I/O I/O I/O Rev. 3.0, 09/04, page 1079 of 1086 Table B.1 Pin States (cont) Pin State Reset State Power-On ROMless Expanded Mode Expanded SingleH-UDI Mode with Chip Hardware Software Module ROM Mode Standby Standby Standby Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z I Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z — Z Z Z Z Z Z K*1 K*1 O*1 O*1 O*1 Z Z K*1 Z K*1 O*1 Z Z Z O*1 I O*1 O*1 Z O*1 K*1 K*1 K*1 K*1 K*1 K*1 K*1 K* 1 Power-Down State Type ATU-II Pin Name TIO4A to TIO4D TIO5A to TIO5D TO6A to TO6D TO7A to TO7D TO8A to TO8P TI9A to TI9F TI10 TIO11A, TIO11B TCLKA, TCLKB 8 Bits — — — — — — — — — — — — Z — — I 16 Bits AUD Module Standby I/O I/O O O O I I I/O I I/O O I I I O I O O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O BusReleased State I/O I/O O O O I I I/O I I/O O I I I O I O O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O I I I/O I I/O O I I I O I O O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SCI SCK0 to SCK4 TxD0 to TxD4 RxD0 to RxD4 A/D AN0 to AN31 converter ADTRG0, ADTRG1 ADEND AVref APC HCAN PULS0 to PULS7 — HTxD0, HTxD1 HRxD0, HRxD1 UBCTRG PA0 to PA15 PB0 to PB15 PC0 to PC4 PD0 to PD13 PE0 to PE15 PF0 to PF5 PF6 to PF10 PH11 to PF15 PG0 to PG3 PH0 to PH7 PH8 to PH15 PJ0 to PJ15 PK0 to PK15 PL0 to PL13 — — — Z Z Z Z — — — Z Z — Z Z Z Z UBC I/O port K*1 K*1 K*1 K*1 K*1 K *1 Rev. 3.0, 09/04, page 1080 of 1086 Table B.2 Pin States Pin State Reset State Power-On ROMless Expanded Mode 8 Bits I I I O/Z I 16 Bits Expanded SingleH-UDI Mode with Chip Hardware Software Module ROM Mode Standby Standby Standby Z Z Z Z Z I I I O/Z I Z Z Z Z Z AUD BusModule Released No Standby State Connection I I I O/Z I I I I O/Z I Pulled up internally Pulled up internally Pulled up internally O/Z Pulled up internally Power-Down State Type Pin Name H-UDI TMS TRST TDI TDO TCK Table B.3 Pin States Pin State Hardware Standby AUD Module Standby Z Z Z AUD Reset (AUDRST = L) L input I When AUDMD = H: I When AUDMD = L: H (pulled up internally) When AUDMD = H: I When AUDMD = L: H (pulled up internally) When AUDMD = H: I When AUDMD = L: H (pulled up internally) Software Standby AUDSRST = 1/ Normal Operation H input I When AUDMD = H: I/O When AUDMD = L: O When AUDMD = H: I When AUDMD = L: O When AUDMD = H: I When AUDMD = L: O Type AUD Pin Name AUDRST AUDMD AUDATA0 to AUDATA3 AUDCK No Connection Pulled down internally Pulled up internally Pulled up internally Z Pulled up internally AUDSYNC Z Pulled up internally — I O H L Z K : : : : : : : Not initial value Input Output High-level output Low-level output High impedance Input pins become high-impedance, output pins retain their state. Notes: 1. When the port impedance bit (HIZ) in the standby control register (SBYCR) is set to 1, output pins become high-impedance. 2. When the CKHIZ bit in PFCRH is set to 1, becomes high-impedance unconditionally. Rev. 3.0, 09/04, page 1081 of 1086 Rev. 3.0, 09/04, page 1082 of 1086 Appendix C Product Lineup Table C.1 SH7058 F-ZTAT Product Lineup Operating Temperature (Except for W/E of Flash Memory) Product Type SH7058 F-ZTAT Model Name HD64F7058BF80L HD64F7058BF80K HD64F7058BP80L Mark Model Name 64F7058F80 64F7058F80 Package 256-pin (FP-256H) –40°C to 105°C 256-pin (FP-256H) –40°C to 125°C –40°C to 105°C –40°C to 125°C 64F7058BP80 272-pin (BP-272) HD64F7058BP80K 64F7058BP80 272-pin (BP-272) Rev. 3.0, 09/04, page 1083 of 1086 Rev. 3.0, 09/04, page 1084 of 1086 Appendix D Package Dimensions Figure D.1 shows the FP-256H package dimensions of the SH7058. 42.6 ± 0.3 40 204 205 129 128 As of July, 2002 Unit: mm 30.6 ± 0.3 28 256 1 *0.22 ± 0.05 0.20 ± 0.04 0.10 M 1.25 76 77 3.56 Max 0.5 *0.17 ± 0.05 0.15 ± 0.04 1.3 1.25 0˚– 8˚ 0.5 ± 0.2 0.08 0.15 ± 0.10 3.20 *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) FP-256H — Conforms 7.5 g Figure D.1 SH7058 Package Dimensions (FP-256H) Rev. 3.0, 09/04, page 1085 of 1086 Unit: mm 0.30 C B 21.0 0.30 C A 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 A B C E G B J L N R 1.00 1.00 D F H K M P T V Y 21.0 U W 4× 0.20 1.00 A 272 × φ0.63 ± 0.10 φ0.10 M C A B 1.00 0.35 C C 0.15 C 0.46±0.10 2.10Max Package Code JEDEC JEITA Mass (reference value) BP-272 — Conforms 1.3 g Figure D.2 SH7058 Package Dimensions (BP-272) Rev. 3.0, 09/04, page 1086 of 1086 Renesas SuperHTM RISC engine Hardware Manual SH-2E SH7058 F-ZTATTM Publication Date: 1st Edition, July, 2002 Rev.3.00, September 17, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd.  2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: (21) 6472-1001, Fax: (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 http://www.renesas.com Colophon 2.0 SH-2E SH7058 F-ZTAT TM Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan