SH7137

APPLICATION NOTE SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer Introduction This application note describes an operation example of the clock synchronous serial transmit and receive functions of the serial communication interface (SCI), using the data transfer controller (DTC) of the SH7137. Target Device SH7137 Contents 1. 2. 3. Introduction ....................................................................................................................................... 2 Description of the Sample Application .............................................................................................. 3 Documents for Reference ............................................................................................................... 21 REJ06B0890-0100/Rev.1.00 July 2009 Page 1 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 1. 1.1 Introduction Specifications This application note describes simultaneous clock synchronous transmit and receive of serial data by the serial communication interface (SCI), using the data transfer functions of the data transfer controller (DTC). Figure 1 shows the configuration. • SCI channel 0 and the DTC are used. • The SCI communication format is 8-bit fixed. • The DTC is used to transfer the SCI transmit and receive data. The DTC uses two channels, one for SCI transmit and one for SCI receive. • The DTC is activated for transmit operation by an SCI transmit data empty interrupt request. The DTC is activated for receive operation by an SCI receive data full interrupt request. • The SCI transmit and receive data count is 32 bytes. Figure 1 Example of Clock Synchronous Serial Data Transmit/Receive Using DTC 1.2 Module Used • Data transfer controller (DTC) • Serial communication interface (SCI) channel 0 1.3 MCU: Applicable Conditions SH7137 Bus clock (Bφ) = 40 MHz Peripheral clock (Pφ) = 40 MHz MTU2 clock (MPφ) = 40 MHz MTU2S clock (MIφ) = 80 MHz Operating frequencies: Internal clock (Iφ) = 80 MHz C compiler: Compile options: Renesas Technology High-performance Embedded Workshop, Ver. 4.05.01.001, Renesas Technology SuperH RISC engine Family C/C++ Compiler Package, Ver. 9.03, Release 00 High-performance Embedded Workshop default settings REJ06B0890-0100/Rev.1.00 July 2009 Page 2 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 2. Description of the Sample Application In this application example, the transmit data empty interrupt (TXI) and receive data full interrupt (RXI) of the serial communication interface (SCI) are used to activate the data transfer controller (DTC) and perform clock synchronous serial data simultaneous transmit and receive. The DTC is set to use two channels, one for SCI transmit and one for SCI receive. The DTC’s normal transfer mode is used. 2.1 2.1.1 Operational Overview of Module Used Serial Communication Interface (SCI) The clock synchronous mode enables data transmit and receive operation in synchronization with a clock pulse, making it suitable for high-speed serial communication. Either an internal clock or an external clock input via the SCK pin may be selected as the clock source. When an internal clock is selected, the synchronization clock is output by the SCK pin. When an external clock is selected, the synchronization clock is input to the SCK pin. Internally, the SCI has independent transmit and receive blocks, and full-duplex communication is possible by using a common synchronization clock. The transmit and receive blocks each have a double-buffered configuration, so data can be read or written during transmission or reception, enabling continuous data transfer. For details of the SCI, see the Serial Communication Interface (SCI) section in the SH7137 Group Hardware Manual (RJJ09B0392). Table 1 shows an overview of clock synchronous communication. Figure 2 is a block diagram of the SCI. Table 1 Overview of Clock Synchronous Serial Communication Description 3 channels (SCI_0, SCI_1, SCI_2) • Internal clock: Pφ, Pφ/4, Pφ/16, Pφ/64 (Pφ: peripheral clock) • External clock: Clock input on SCK pin • Transfer data length: 8-bit data fixed • Transfer sequence: Selectable between LSB-first and MSB-first • When internal clock selected: 250 bps to 5,000,000 bps (Pφ = 40 MHz operation) • When external clock selected: Max. 6,666,666.7 bps (Pφ = 40 MHz and external clock input = 6.6667 MHz operation) Overrun error • Transmit data empty interrupt (TXI) • Transmit end interrupt (TEI) • Receive data full interrupt (RXI) • Receive error interrupt (ERI) • Selectable between internal clock and external clock • When internal clock selected: Clock of SCI’s internal on-chip baud rate generator is used for operation. Synchronization clock is output on SCK pin. • When external clock selected: On-chip baud rate generator is not used. External synchronization clock input via SCK pin is used for operation. Item Number of channels Clock sources Data format Baud rate Receive error detection Interrupt requests Clock source REJ06B0890-0100/Rev.1.00 July 2009 Page 3 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer Module data bus Bus interface Internal data bus SCRDR SCTDR SCSSR SCSCR SCSMR SCSPTR SCBRR Baud rate generator RXD TXD SCRSR SCTSR SCSDCR Transmission/reception control Pφ Pφ/4 Pφ/16 Pφ/64 Parity generation Parity check SCK Clock External clock TEI TXI RXI ERI SCI [Legend] SCRSR: SCRDR: SCTSR: SCTDR: SCSMR: SCSCR: SCSSR: SCBRR: SCSPTR: SCSDCR: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Serial direction control register Figure 2 SCI Block Diagram REJ06B0890-0100/Rev.1.00 July 2009 Page 4 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 2.1.2 Data Transfer Controller (DTC) The data transfer controller (DTC) can be activated by interrupt requests from on-chip peripheral modules to perform data transfers. The DTC has three transfer modes: normal transfer mode, repeat transfer mode, and block transfer mode. By storing transfer information in a data area, data transfer can be performed using a user-specified number of channels. When the DTC is activated, the transfer information is read from the data area, data transfer starts, and then updated transfer information is written back to the data area after the end of the data transfer. The transfer information can be assigned to a data area in the on-chip RAM or in an external memory space. For details of the DTC, see the Data Transfer Controller (DTC) section in the SH7137 Group Hardware Manual (RJJ09B0392). Table 2 shows an overview of the DTC. Figure 3 is a block diagram of the DTC. Table 2 Overview of DTC Description • Three transfer modes • Normal transfer mode • Repeat transfer mode • Block transfer mode Transfer count • Normal transfer mode: 1 to 65,536 • Repeat transfer mode: 1 to 256 • Block transfer mode: 1 to 65,536 Data size The data size for data transfers may be set to byte, word, or longword. CPU interrupt • An interrupt request can be set to the CPU at the end of a single data transfer. requests • An interrupt request can be set to the CPU at the end of a specified number of data transfers. Others • Support for chain transfer (multiple data transfers triggered by a single activation source) • Support for transfer information read skip mode • Support for skipping write-back for fixed transfer source addresses and transfer destination addresses • Support for module stop mode • Support for short address mode • Selectable among five bus right release timings • Selectable between two priorities at DTC startup Note: An on-chip peripheral module should be set as, at a minimum, either the transfer source or transfer destination. The DTC cannot be used for transfers among external memory, memory mapped external devices, and on-chip memory only. Item Transfer modes REJ06B0890-0100/Rev.1.00 July 2009 Page 5 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer DTC On-chip memory On-chip peripheral module Interrupt request MRA Internal bus (32 bits) Peripheral bus Register control MRB SAR Activation control CPU/DTC request determination DAR CRA CRB DTCERA to DTCERE INTC CPU interrupt request Interrupt source clear request Interrupt control DTCCR DTCVBR Bus interface External device (memory mapped) External bus External memory Bus state controller [Legend] MRA, MRB: SAR: DAR: CRA, CRB: DTCERA to DTCERE: DTCCR: DTCVBR: DTC mode registers A, B DTC source address register DTC destination address register DTC transfer count registers A, B DTC enable registers A to E DTC control register DTC vector base register Figure 3 DTC Block Diagram REJ06B0890-0100/Rev.1.00 July 2009 DTC internal bus Page 6 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer (1) Allocation of Transfer Information Figure 4 shows the allocation of DTC transfer information in normal mode. The DTC transfer information is assigned to a data area in a location such as on-chip RAM. Use address 4n as the start address for transfer information. If an address other than 4n is specified, the lowest two bits are ignored when access is performed (lowest 2 bits = B'00). Allocation of transfer information in normal mode Lower addresses Start address 0 MRA 1 2 MRB SAR DAR Chain transfer CRA MRA MRB SAR DAR CRA 4 bytes CRB CRB 3 Transfer information for one transfer round (4 longwords) Transfer information for 2nd transfer round in chain transfer (4 longwords) Figure 4 Allocation of Transfer Information in Data Area (2) Setting the DTC Vector Address For each activation source, the DTC reads the start address of the transfer information from a vector table, then reads the transfer information from this start address. Figure 5 shows the correspondence between the DTC vector table and the transfer information. For information on the correspondence between DTC activation sources and vector addresses, see the Data Transfer Controller (DTC) section in the SH7137 Group Hardware Manual (RJJ09B0392). Figure 5 Correspondence between DTC Vector Table and Transfer Information REJ06B0890-0100/Rev.1.00 July 2009 Page 7 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 2.2 2.2.1 Operation of the Sample Program The Sample Program Operation Specifications Table 3 lists the SCI communication function settings used in this application note. The SCI performs simultaneous transmit and receive in clock synchronous mode. The DTC transfer function is used to transfer SCI transmit and receive data. Table 3 SCI Communication Function Settings Description SCI channel 0 Clock synchronous mode • Transmit data empty interrupt (TXI) • Receive data full interrupt (RXI) • Receive error interrupt (ERI) 100 Kbytes 32 bytes 8-bit data (fixed) LSB-first Internal clock/synchronization clock output on SCK pin Item Module Communication mode Interrupts Communication speed Transmit/receive data count Data length Bit sequence Synchronization clock Table 4 lists the DTC transfer conditions for this application note. The DTC is set to two channels, one for SCI transmit and one for SCI receive. Table 4 DTC Transfer Conditions Description SCI transmit side DTC transfer conditions (TXI_0) Normal mode 32 times Byte transfer On-chip RAM (SCI transmit data storage area) SCI transmit data register (SCTDR_0) Transfer source address is incremented following transfer. Transfer source is fixed. DTC is activated at SCI channel 0 transmit data empty interrupt (TXI) request. Interrupt processing by the CPU (SCI TXI interrupt) is enabled following the completion of the specified data transfer count. SCI receive side DTC transfer conditions (RXI_0) Normal mode 32 times Byte transfer SCI receive data register (SCRDR_0) On-chip RAM (SCI receive data storage area) Transfer source is fixed. Transfer destination address is incremented following transfer. DTC is activated at SCI channel 0 receive data full interrupt (TXI) request. Interrupt processing by the CPU (SCI RXI interrupt) is enabled following the completion of the specified data transfer count. Item Transfer mode Transfer count Transfer size Transfer source Transfer destination Transfer source address Transfer destination address Activation source Interrupt handling REJ06B0890-0100/Rev.1.00 July 2009 Page 8 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 2.2.2 Allocation of DTC Transfer Information Figure 6 shows the allocation of DTC transfer information in memory. In this application note, the address H'FFFF8000 is set as the DTC vector base register (DTCVBR) and the vector table is allocated to an area in the on-chip RAM. The DTC transfer information is allocated to an area in the on-chip RAM. The SCI receive DTC transfer information is allocated to address H'FFF8800, and the SCI transmit DTC transfer information is allocated to address H'FFF8810. The DTC vector base is set in the on-chip RAM area. DTC vector base register (DTCVBR) = H'FFFF8000 SCI receive DTC · Activation source: RXI_0 of SCI_0 · Vector number: 217 · DTC vector address offset: H'764 Calculating the DTC vector address = DTCVBR + DTC vector address offset = H'FFFF8000 + H'764 = H'FFFF8764 RAM area [DTC vector table] H'FFFF8764 （RXI_0） H'FFFF8768 （TXI_0） Stores start address for transfer information (1) Stores start address for transfer information (2) [DTC transfer information] SCI transmit DTC · Activation source: TXI_0 of SCI_0 · Vector number: 218 · DTC vector address offset: H'768 Calculating the DTC vector address = DTCVBR + DTC vector address offset = H'FFFF8000 + H'768 = H'FFFF8768 H'FFFF8800 Transfer information (1) (for SCI receive) H'FFFF8810 Transfer information (2) (for SCI transmit) H'FFFF8820 Figure 6 Allocation of DTC Transfer Information in Memory 2.2.3 Operation Description Figure 7 provides an operation description. The transmit and receive operation setting bits (bits TE and RE) for SCI channel 0 are set to 1 simultaneously to start transmit and receive operation. In transmit operation, when 1 byte of data is ready to be transmitted, the TDRE flag is set to 1, a TXI interrupt request is generated, and the DTC is activated. The DTC transfers the transmit data from the on-chip RAM to the SCI, and the TDRE flag is automatically cleared to 0. During this time the CPU processes no interrupts. After the specified transfer count of 32 DTC data transfers is completed, the TDRE flag remains set to 1 and a TXI interrupt is issued to the CPU. The TDRE flag is cleared to 0 by the interrupt handling routine. In receive operation, when reception of 1 byte of data finishes, the RDRF flag is set to 1, an RXI interrupt request is generated, and the DTC is activated. The DTC transfers the receive data to the on-chip RAM, and the RDRF flag is automatically cleared to 0. During this time the CPU processes no interrupts. After the specified transfer count of 32 DTC data transfers is completed, the RDRF flag remains set to 1 and an RXI interrupt is issued to the CPU. The RDRF flag is cleared to 0 by the interrupt handling routine. REJ06B0890-0100/Rev.1.00 July 2009 Page 9 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer Figure 7 Operation Description REJ06B0890-0100/Rev.1.00 July 2009 Page 10 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 2.3 2.3.1 Configuration of the Sample Program Description of Functions Table 5 lists the modules used in the reference program. Table 5 Functions Used Label main () Description Makes initial settings for each module. Makes initial settings for the data transfer controller (DTC) and serial communication interface (SCI). Enables SCI simultaneous transmit and receive operation. Cancels module standby settings (SCI ch0, DTC). Makes DTC initial settings for SCI (ch0) transmit and SCI (ch0) receive. Makes pin function controller (PFC) initial settings. Sets SCI-related pins to function as serial pins. SCI (ch0) receive data full (RDRF) interrupt (RXI). Generated when DTC data transfer ends. SCI (ch0) transmit data empty (TDRE) interrupt (TXI). Generated when DTC data transfer ends. Receive error (ORER) interrupt (ERI). Processing when an overrun error occurs. Function Name Main Module standby setting DTC initial setting RFC initial setting RXI0 interrupt TXI0 interrupt ERI0 interrupt stbcr_init () dtc_init() pfc_init () int_sci_rxi() int_sci_txi() int_sci_eri() 2.3.2 Variables Usage Table 6 lists the variables used in the reference program. Table 6 Variables Usage Description Array for storing SCI receive data Array for storing SCI transmit data Structure variable for storing DTC transfer information settings for SCI receive. Allocated in on-chip RAM. Structure variable for storing DTC transfer information settings for SCI transmit. Allocated in on-chip RAM. Pointer variable for storing the start address of the DTC transfer information (structure variable DTC_RXI0). Allocated at the DTC vector table address (on-chip RAM) corresponding to DTC activation source RXI_0. Pointer variable for storing the start address of the DTC transfer information (structure variable DTC_TXI0). Allocated at the DTC vector table address (on-chip RAM) corresponding to DTC activation source TXI_0. Name of Employing Module main () dtc_init() dtc_init() Label Name Rxi_data[32] Txi_data[32] DTC_RXI0 DTC_TXI0 *Dtc_Vect_rxi0 dtc_init() *Dtc_vect_txi0 REJ06B0890-0100/Rev.1.00 July 2009 Page 11 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 2.4 2.4.1 Procedure for Setting Module Used Main Function The setting procedure for SCI clock synchronous mode using the DTC is described below. Figure 8 shows the processing sequence of the main function. Figure 8 Processing Sequence of Main Function 2.4.2 Cancel Module Standby Figure 9 shows the processing sequence of the function that cancels module standby. stbcr_init() Make setting in standby control register 3 (STBCR3) Make setting in standby control register 2 (STBCR2) END [1] [1] Enable clock supply to SCI_0. Clear MSTP11 bit to B'0. [2] Enable clock supply to DTC. Clear MSTP4 bit to B'0. [2] Figure 9 Setting sequence for canceling module standby. REJ06B0890-0100/Rev.1.00 July 2009 Page 12 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 2.4.3 Initialization of Data Transfer Controller (DTC) Figure 10 shows the initial setting sequence for the data transfer controller (DTC). dtc_init() Make settings in DTC control register (DTCCR) [1] [1] Operating mode selection · RRS bit = B'0: No not skip reading DTC transfer information. · RCHNE bit = B'0: Disable chain transfer after repeat transfer. · ERR bit = B'0: Clear transfer stop flag. DTC transfer information (DTC_RXI0) settings for SCI receive [2] Operating mode A selection · MD bit = B'00: Normal transfer mode · Sz bit = B'00: Byte size transfer · SM bit = B'00: SAR is fixed. [3] Operating mode B selection · CHNE bit = B'0: Disable chain transfer. · DISEL bit = B'0: Enable interrupt after end of specified transfer count. · DM bit = B'10: Increment DAR after transfer. [4] Transfer source address setting Specify SCI receive data register_0 (SCRDR_0). [5] Transfer destination address setting Specify SCI receive data storage area (start address) (on-chip RAM). [6] Data transfer count: 32 times [7] Specify block data transfer count (not used): 0 times DTC settings for SCI receive (DTC_RXI0) Make settings in DTC mode register A (MRA) Make settings in DTC mode register B (MRB) Make setting in DTC source address register (SAR) Make setting in DTC destination address register (DAR) Make setting in DTC transfer count register A (CRA) Make setting in DTC transfer count register B (CRB) [2] [3] [4] [5] [6] [7] DTC settings for SCI transmit (DTC_TXI0) Make settings in DTC mode register A (MRA) Make settings in DTC mode register B (MRB) Make setting in DTC source address register (SAR) Make setting in DTC destination address register (DAR) Make setting in DTC transfer count register A (CRA) Make setting in DTC transfer count register B (CRB) [8] [9] DTC transfer information (DTC_TXI0) settings for SCI transmit [8] Operating mode A selection · MD bit = B'00: Normal transfer mode · Sz bit = B'00: Byte size transfer · SM bit = B'10: Increment SAR after transfer. [9] Operating mode B selection · CHNE bit = B'0: Disable chain transfer. · DISEL bit = B'0: Enable interrupt after end of transfer. · DM bit = B'00: DAR is fixed. [10] Transfer source address setting Specify SCI transmit data storage area (start address) (on-chip RAM). [11] Transfer destination address setting Specify SCI transmit data register_0 (SCTDR_0). [12] Set data transfer count: 32 times [10] [11] [12] [13] Make setting in DTC vector base register Make vector table settings Make settings in DTC enable register E (DTCERE) END [14] [13] Specify block data transfer count (not used): 0 times [14] DTC vector base register setting Allocate DTC vector table in on-chip RAM. [15] [16] [15] · Set DTC transfer information (DTC_RXI0) for SCI receive in vector table. · Set DTC transfer information (DTC_TXI0) for SCI transmit in vector table. [16] DTC interrupt vector settings · Enable DTC activation by SCI_0 interrupt source RXI_0. · Enable DTC activation by SCI_0 interrupt source TXI_0. Figure 10 Initialization of Data Transfer Controller (DTC) REJ06B0890-0100/Rev.1.00 July 2009 Page 13 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 2.4.4 Initialization of Serial Communication Interface (SCI) Figure 11 shows the initial setting sequence for the serial communication interface (SCI). Figure 11 Initialization of Serial Communication Interface (SCI) 2.4.5 Initialization of Pin Function Controller (PFC) Figure 12 shows the initial setting sequence for the pin function controller (PFC). Figure 12 Initialization of Pin Function Controller (PFC) REJ06B0890-0100/Rev.1.00 July 2009 Page 14 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 2.4.6 Handling of SCI Receive Data Full Interrupt (RXI0) Figure 13 shows the processing sequence of the SCI receive data full interrupt (RXI0) handler. Figure 13 SCI Receive Data Full Interrupt (RXI0) Processing Sequence 2.4.7 Handling of SCI Transmit Data Empty Interrupt (TXI0) Figure 14 shows the processing sequence of the SCI transmit data empty interrupt (TXI0) handler. Figure 14 SCI Transmit Data Empty Interrupt (TXI0) Processing Sequence 2.4.8 Handling of SCI Receive Error Interrupt (ERI0) Figure 15 shows the processing sequence of the SCI receive error interrupt (ERI0) handler. int_sci_eri() Processing when overrun error is generated Clear ORER in serial status register_0 (SCSSR_0) Read serial status register_0 (SCSSR_0) END [1] [2] [1] Clear the overrun error bit to 0 (ORER = B'0). To clear the flag, write 0 after reading the bit as 1. [2] Do a dummy read of the serial status register. Figure 15 Receive Error Interrupt (ERI0) Processing Sequence REJ06B0890-0100/Rev.1.00 July 2009 Page 15 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 2.5 2.5.1 Settings of Registers in the Sample Program Clock Pulse Generator (CPG) The register setting values used in the reference program are listed below. Table 7 shows the register settings for the clock pulse generator (CPG). Table 7 Clock pulse generator (CPG) Address H'FFFFE800 Setting H'0241 Description Specifies the operating frequency multiplication ratios. • IFC2 to IFC0 = B'000: Internal clock (Iφ) × 1 • BFC2 to BFC0 = B'001: Bus clock (Bφ) × 1/2 • PFC2 to PFC0 = B'001: Peripheral clock (Pφ) × 1/2 • MIFC2 to MIFC0 = B'000: MTU2S clock (MIφ) × 1 • MPFC2 to MPFC0 = B'001: MTU2 clock (MPφ) × 1/2 Register Name Frequency control register (FRQCR) 2.5.2 Power-Down Mode Table 8 shows the register settings for low-power mode. Table 8 Power-Down Mode Address H'FFFFE804 Setting H'28 Description Specifies the operation settings for individual modules. • MSTP7 = B'0: Operate RAM. • MSTP6 = B'0: Operate ROM. • MSTP4 = B'0: Operate DTC. Specifies the operation settings for individual modules. • MSTP15 = B'1: Stop clock supply to I2C2. • MSTP13 = B'1: Stop clock supply to SCI_2. • MSTP12 = B'1: Stop clock supply to SCI_1. • MSTP11 = B'0: operate SCI_0. • MSTP10 = B'1: Stop clock supply to SSU. • MSTP8 = B'1: Stop clock supply to RCAN-ET_0. Register Name Standby control register_2 (STBCR_2) Standby control register_3 (STBCR_3) H'FFFFE806 H'F7 REJ06B0890-0100/Rev.1.00 July 2009 Page 16 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 2.5.3 Interrupt Controller (INTC) Table 9 shows the register settings for the interrupt controller (INTC). Table 9 Interrupt Controller (INTC) Address H'FFFFE992 Setting H'F000 Description Sets interrupt priority levels (level 0 to 15). • Bits 15 to 12 = B'1111: SCI_0 interrupt level = 15 • Bits 11 to 8 = B'0000: SCI_1 interrupt level = 0 • Bits 7 to 4 = B'0000: SCI_2 interrupt level = 0 • Bits 3 to 0: Reserved The SCI_0 interrupt is used by the reference program. Note: The SCI0 RXI and TXI interrupt priority is according to the offset address order of the interrupt vector addresses. For details on interrupt priority, see the Interrupt Exception Handling Vector Table item in the Interrupt Controller section of the SH7137 Group Hardware Manual. Register Name Interrupt priority register L (IPRL) 2.5.4 Pin Function Controller (PFC) Table 10 shows the register settings for the pin function controller (PFC). Table 10 Pin Function Controller (PFC) Register Name Port E control register L1 (PECRL1) Address H'FFFFD316 Setting H'6660 Description Sets port E multiplexed pin functions. • PE3MD2 to PE3MD0 = B'110: PE3 functions as SCK0 I/O (SCI). • PE2MD2 to PE2MD0 = B'110: PE2 functions as TXD0 output (SCI). • PE1MD2 to PE1MD0 = B'110: PE1 functions as RXD0 input (SCI). • PE0MD1 and PE0MD0 = B'00: PE0 functions as PE0 I/O (port). REJ06B0890-0100/Rev.1.00 July 2009 Page 17 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 2.5.5 Data Transfer Controller (DTC) Tables 11, 12, and 13 list the DTC settings for this application note. Table 11 Data Transfer Controller (DTC) Common Settings Register Name DTC control register (DTCCR) Address H'FFFFCC90 Setting H'00 Description • RRS = B'0: No not skip reading transfer information. • RCHNE = B'0: Disable chain transfer. • ERR = B'0: No interrupt requests. Specify the on-chip RAM area as the base address used to calculate vector table addresses. Select the interrupt source that activates the DTC. • DTCERE15 = B'1: Select RXI_0 as the activation source. • DTCERE14 = B'1: Select TXI_0 as the activation source. DTC vector base H'FFFFCC94 register (DTCVBR) H'FFFFCC88 DTC enable register E(DTCERE) H'FFFF8000 H'C000 Table 12 DTC Transfer Information (DTC_RXI0) for SCI Receive Register Name DTC mode register A(MRA) DTC mode register B(MRB) Address H'FFFF8800 *1 H'FFFF8801 (MRA +1) Setting H'00 Description • MD1 and MD0 = B'00: Normal transfer • Sz1 and Sz0 = B'00: Byte size transfer • SM1 and SM0 = B'00: SAR is fixed. • CHNE = B'0: Disable chain transfer. • CHNS = B'0: Continuous chain transfer. • DISEL = B'0: Generate CPU interrupt request at end of specified data transfer count. • DTS = B'0: Set destination as repeat area or block area. • DM1 and DM0 = B'10: Increment DAR. Specify transfer source address. Set SCI0 receive data register_0 (SCRDR_0). H'08 H'FFFF8804 SCRDR_0 DTC source address register (MRA +4) Register (SAR) Specify transfer destination address. DTC destination H'FFFF8808 On-chip RAM*2 address (MRA +8) Store start address of buffer array variable for receive register(DAR) (&rxi0_data[0]). H'FFFF880C H'0020 Specify DTC data transfer count. DTC transfer count register (MRA+12) 32 times A(CRA) H'FFFF880E H'0000 DTC transfer Specify DTC block data transfer count for block transfer mode (not used). count register (MRA+14) B(CRB) Notes: 1. The transfer information is allocated to on-chip RAM as a structure variable with no initial value. The allocation of variables in memory is dependent on the section allocation settings of the optimizing linkage editor used to create the executable object code. 2. The array variables are allocated to on-chip RAM as variables with no initial value. The allocation of variables in memory depends on the results of the compile process used to generate the executable object code. REJ06B0890-0100/Rev.1.00 July 2009 Page 18 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer Table 13 DTC Transfer Information (DTC_TXI0) for SCI Transmit Register Name DTC mode register A(MRA) DTC mode register B(MRB) Address H'FFFF8810 *1 H'FFFF8811 (MRA +1) Setting H'08 Description • MD1 and MD0 = B'00: Normal transfer • Sz1 and Sz0 = B'00: Byte size transfer • SM1 and SM0 = B'10: Increment SAR. • CHNE = B'0: Disable chain transfer. • CHNS = B'0: Continuous chain transfer. • DISEL = B'0: Generate CPU interrupt request at end of specified data transfer count. • DTS = B'0: Set destination as repeat area or block area. • DM1 and DM0 = B'00: DAR is fixed. Specify transfer source address. Store start address of buffer array variable for transmit (&txi0_data[0]). Specify transfer destination address. Set SCI0 transfer data register_0 (SCTDR_0). H'00 DTC source H'FFFF8814 On-chip address register (MRA +4) RAM*2 (SAR) DTC destination H'FFFF8818 SCTDR_0 Register address register (MRA +8) (DAR) Specify DTC data transfer count. DTC transfer H'FFFF881C H'0020 (MRA+12) count register 32 times A(CRA) DTC transfer H'FFFF881E H'0000 Specify DTC block data transfer count for block (MRA+14) transfer mode (not used). count register B(CRB) Notes: 1. The transfer information is allocated to on-chip RAM as a structure variable with no initial value. The allocation of variables in memory is dependent on the section allocation settings of the optimizing linkage editor used to create the executable object code. 2. The array variables are allocated to on-chip RAM as variables with no initial value. The allocation of variables in memory depends on the results of the compile process used to generate the executable object code. REJ06B0890-0100/Rev.1.00 July 2009 Page 19 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 2.5.6 Serial Communication Interface (SCI) Table 14 shows the SCI register settings for this application note. Table 14 SCI Register Settings Register Name Serial mode register_0 (SCSMR_0) Bit rate register_0 (SCBRR_0) Serial control register_0 (SCSCR_0) Address H'FFFEC000 Setting H'80 Description • C/A = B'1: Clock synchronous mode • • CHR = B'0: 8 data bits • • CKS1 and CKS0 = B'00: Pφ clock Clock synchronous mode Bit rate: 100 Kbit/s* Initial settings • TIE = B'0: Disable transmit data empty interrupt (TXI) requests. • RIE = B'0: Disable receive data full interrupt (RXI) requests. • TE = B'0: Disable transmit operation. • RE = B'0: Disable receive operation. • MPIE = B'0: Disable multiprocessor mode. • TEIE = B'0: Disable transmit end interrupt (TEI) requests. • CKE1 and CKE0 = B'00: Internal clock/SCK pin set as synchronization clock output (clock synchronous mode) When transmit and receive are enabled • TIE = B'1: Enable interrupt (TXI) requests. • RIE = B'1: Enable interrupt (RXI) requests. • TE = B'1: Enable transmit operation. • RE = B'1: Enable receive operation. • Set bits TE and RE to enable simultaneously. Status flags retain initial settings. • TDRE = B'1: Transmit data register empty flag • RDRF = B'0: Receive data register full flag • ORER = B'0: Overrun error flag • FER = B'0: Framing error flag • PER = B'0: Parity error flag • TEND = B'1: Transmit end flag LSB-first/MSB-first selection • DIR = B'0: LSB-first for transmit and receive H'FFFEC002 H'FFFEC004 H'63 (99) H'00 H'F0 Serial status register_0 (SCSSR_0) H'FFFEC008 H'84 (initial value) • EIO = B'0: When the RIE bit is set to 1, send RXI and ERI interrupts to the INTC. • SPB1IO = B'0: Do not output the value of the SPB1DT bit on the SCK pin. • PB0IO = PB0DT = B'1: Control the TXD pin according to the TE bit. TXD output is high-level when TE = 0. Note: * For details on the bit rate setting, see the Bit Rate Register (SCBRR) item in the Serial Communication Interface section of the SH7137 Group Hardware Manual. H'FFFFC00E H'03 Serial direction control register_0 (SCSDCR_0) Serial port register_0 (SCSPTR_0) H'FFFFC00C H'F2 REJ06B0890-0100/Rev.1.00 July 2009 Page 20 of 22 SH7136/SH7137 Group SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer 3. Documents for Reference • Hardware Manual SH7211 Group Hardware Manual [RJJ09B0338] (The latest version can be downloaded from the Renesas Technology Web site.) • Software Manual SH-2A/SH2A-FPU Software Manual [RJJ09B0086] (The latest version can be downloaded from the Renesas Technology Web site.) Website and Support Renesas Technology Website http://www.renesas.com/ Inquiries http://www.renesas.com/inquiry csc@renesas.com Revision Record Rev. 1.00 Date Jul.16.09 Description Page Summary — First edition issued All trademarks and registered trademarks are the property of their respective owners. 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