REJ09B0157-0200O
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
32
™
SH7615 Group
Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series SH7615 HD6417615
Rev. 2.00 Revision Date: Mar 17, 2005
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Rev. 2.00, 03/05, page ii of xxxviii
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed.
Rev. 2.00, 03/05, page iii of xxxviii
Configuration of This Manual
This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
Rev. 2.00, 03/05, page iv of xxxviii
Preface
The SH7615 RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas Technology original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users. Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the instruction set.
Notes on reading this manual: • Product names The following products are covered in this manual.
Product Classifications and Abbreviations Basic Classification SH7615 Product Code HD6417615
• In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions, and electrical characteristics. • In order to understand the details of the CPU's functions Read the SH-1/SH-2/SH-DSP Software Manual.
Rev. 2.00, 03/05, page v of xxxviii
Rules:
Register name:
The following notation is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. (http://www.renesas.com/)
xxxx
Related Manuals:
SH7615 manuals:
Document Title SH7615 Hardware Manual SH-1/SH-2/SH-DSP Software Manual Document No. This manual REJ09B0171
Users manuals for development tools:
Document Title Document No.
SuperH RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor REJ10B0152 User's Manual SuperH RISC engine High-performance Embedded Workshop User's Manual REJ10B0025 SuperH RISC engine High-performance Embedded Workshop, Tutorial SuperH RISC engine C/C++ Compiler Package Application Note REJ10B0023 REJ05B0463
Rev. 2.00, 03/05, page vi of xxxviii
Abbreviations ADC ALU ASE ASID AUD BCD bps BSC CCN CMT CPG CPU DMAC etu FIFO Hi-Z H-UDI INTC IrDA JTAG LQFP LRU LSB MMU MPX MSB PC PFC PLL PWM RAM RISC ROM RTC SCIF SDRAM Analog to Digital Converter Arithmetic Logic Unit Adaptive System Evaluator Address Space Identifier Advanced User Debugger Binary Coded Decimal bit per second Bus State Controller Cache memory Controller Compare Match Timer Clock Pulse Generator Central Processing Unit Direct Memory Access Controller Elementary Time Unit First-In First-Out High Impedance High-performance User Debugging Interface Interrupt Controller Infrared Data Association Joint Test Action Group Low Profile QFP Least Recently Used Least Significant Bit Memory Management Unit Multiplex Most Significant Bit Program Counter Pin Function Controller Phase Locked Loop Pulse Width Modulation Random Access Memory Reduced Instruction Set Computer Read Only Memory Real Time Clock Serial Communication Interface with FIFO Synchronous DRAM
Rev. 2.00, 03/05, page vii of xxxviii
TAP T.B.D TLB TMU TPU UART UBC USB WDT
Test Access Port To Be Determined Translation Lookaside Buffer Timer Unit Timer Pulse Unit Universal Asynchronous Receiver/Transmitter User Break Controller Universal Serial Bus Watchdog Timer
Rev. 2.00, 03/05, page viii of xxxviii
Main Revisions and Additions in this Edition
Item General 1.1 Features of SuperH Microcomputer with OnChip Ethernet Controller Table 1.1 Features 1.2 Block Diagram Figure 1.1 Block Diagram of SH7615 13 Page All 7 Revisions (See Manual for Details) BP-240A and BP-240AV packages added Description added to the features of direct memory access controller (DMAC) W hen synchronous DRAM is connected, single-address transfer is available in a single clock cycle at maximum 31.25 MHz Figure 1.1 amended
16-bit internal X data bus 16-bit internal Y data bus Internal X address bus Internal Y address bus
1.3.1 Pin Arrangement
14
Description modified Figure 1.2 shows the pin arrangement of the HD6417615ARF and HD6417615ARFV, and figure 1.3 shows the pin arrangement of the HD6417615ARBP and HD6417615ARBPV.
Rev. 2.00, 03/05, page ix of xxxviii
Item 1.3.1 Pin Arrangement Figure 1.2 HD6417615ARF and HD6417615ARFV Pin Arrangement (FP-208C, FP-208CV)
Page 14
Revisions (See Manual for Details) Figure 1.2 title amended, package name amended (Before) FP-208C (Top view) → (After) FP-208C, FP-208CV (Top view)
PVSS PB10/SRXD2/TIOCA1 PB9/STCK2/TIOCB1/TCLKC PB8/STS2/TIOCA2 PB7/STXD2/TIOCB2/TCLKD PB6/SRCK1/SCK2 PB5/SRS1/RXD2 PB4/SRXD1/TXD2 PB3/STCK1/TIOCA0 PB2/STS1/TIOCB0 PVCC PB1/STXD1/TIOCC0/TCLKA PVSS PB0/TIOCD0/TCLKB/WOL PA13/SRCK0 PA12/SRS0 PA11/SRXD0 PA10/STCK0 PA9/STS0 PA8/STXD0 PA7/WDTOVF PA6/FTCI PVCC PA5/FTI PVSS PA4/FTOA CKPO/FTOB PA2/LNKSTA PA1/EXOUT PA0 RX-ER RX-DV COL CRS PVSS RX-CLK PVCC ERXD0 ERXD1 ERXD2 ERXD3 MDIO MDC PVCC TX-CLK PVSS TX-EN ETXD0 ETXD1 ETXD2 ETXD3 TX-ER 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Figure 1.3 HD6417615ARBP and HD6417615ARBPV Pin Arrangement (BP-240A, BP-240AV) 1.3.2 Pin Functions Table 1.2 Pin Functions
15
Figure 1.3 added
18 to 20
Table 1.2 amended
Type Bus contro Symbol BUSHiZ I/O Input Name Bus high impedance Function Signal used in combination with WAIT signal to place bus and strobe signals in the high-impedance (HiZ) state without ending the bus cycle 4-bit transmit data
Ethernet controller (EtherC)
ETXD0 to ETXD3
Output
Transmit data 0 to 3 Receive data input channel 1, 2
Serial RXD1, RXD2 Input communication interface with FIFO (SCIF)
SCIF channel 1 and 2 receive data input pins
1.3.3 Pin Multiplexing Table 1.3 Pin Multiplexing
22 to 27
Table 1.3 amended The pin numbers for the BP-240A and BP-240AV packages are added.
Rev. 2.00, 03/05, page x of xxxviii
Item 1.4 Processing States
Page 29
Revisions (See Manual for Details) Bus-Released State Description added 1. In the bus-released state, the CPU releases the bus to a device that has requested it. 2. Bus-released state during manual reset signal assertion While the manual reset signal is being asserted ( = low and NMI = low), no arbitration request ( input) is accepted. If the signal continues to be asserted, this LSI remains in the bus-released state (asserts the signal). When the signal is negated in the bus-released state during manual reset signal assertion, this LSI starts using the bus (negates the signal).
2.2.5 DSP Type Instructions and Data Formats Table 2.5 Destination Register Data Formats for DSP Instructions
49
Table 2.5 amended
Register A0, A1 Instruction Data transfer MOVS.W MOVS.L X0, X1, Y0, Y1, M0, M1 Data transfer MOVX.W, MOVY.W, MOVS.W MOVS.L
Guard Bits 39 to 32 Sign extend
Register Bits 31 to 16 16-bit data 32-bit data 16-bit data 15 to 0
32-bit data
2.6 Usage Notes 3.2.3 Connecting a Crystal Resonator Figure 3.2 Example of Crystal Oscillator Connection 3.2.4 External Clock Input Figure 3.3 External Clock Input Method 3.2.7 Notes on Board Design
104 to 3. and 4. added 106 112 Note 1 amended Note: 1. The CKIO pin is an output or high impedance in clock modes 0,1, and 2, and is high impedance in clock mode 3. 113 Description amended The CKIO pin is an output or high impedance in clock modes 0, 1, and 2, and is high impedance in clock mode 3. 123 When Using an External Crystal Oscillator Description added Figure 3.5 shows an example of the oscillator circuit. This is a sample oscillator circuit and in the actual system, the values shown in the figure are affected by the environment such as noise, power supply characteristics, or wiring patterns. These values cannot be guaranteed and should be used as reference values. To determine the optimum oscillator circuit constants for the user system, please consult with the crystal resonator manufacturer.
Rev. 2.00, 03/05, page xi of xxxviii
RGB
SLRB SER
RGB
SLRB
SLRB
Item 3.2.7 Notes on Board Design Figure 3.5 Points for Attention when Using Crystal Resonator
Page 123
Revisions (See Manual for Details) Figure 3.5 amended Circuit constants added and crystal resonator information added
Bypass Capacitors Description amended 1. VSS/VCC pairs for FP-208C and FP-208CV 124 5.3.29 IRQ Control/Status Register (IRQCSR) 189 Description added 2. VSS/VCC pairs for BP-240A and BP-240AV Bits 15 to 8—IRQ Sense Select Bits (IRQ31S to IRQ00S) Bit table amended
Bits 15 to 8: IRQn1S 0 1 Bits 15 to 8: IRQn0S 0 1 0 1 Description Low-level detection Falling-edge detection Rising-edge detection Both-edge detection (Initial value)
7.2.1 Bus Control Register 1 (BCR1)
259
Bit 12—Endian Specification for Area 2 (A2ENDIAN) Note added Note: Data rearrangement into little-endian format requires no extra processing time.
260
Bit 3—Endian Specification for Area 4 (A4ENDIAN) Note: Data rearrangement into little-endian format requires no extra processing time.
7.2.7 Individual Memory Control Register (MCR)
271
• For DRAM interface Bit table added
Bit 1: TRP1 0 1 Bit 15: TRP0 0 1 0 1 Description 1 cycle 2 cycles Reserved (do not set) Reserved (do not set) (Initial value)
• For synchronous DRAM interface Bit table added
Bit 1: TRP1 0 1 Bit 15: TRP0 0 1 0 1 Description 1 cycle 2 cycles 3 cycles 4 cycles (Initial value)
274
• For synchronous DRAM interface Bit table replaced
Rev. 2.00, 03/05, page xii of xxxviii
Item 7.5.3 Burst Reads
Page 297,
Revisions (See Manual for Details) Figure title amended
299, Figure 7.19 (a) Basic Burst Read Timing (Auto- 302, Precharge) Except 305, tEcyc:tPcyc 1:1 308, Figure 7.20 (a) Burst Read Wait Specification Timing (Auto-Precharge) Except tEcyc:tPcyc 1:1 Figure 7.21 (a) Single Read Timing (AutoPrecharge) Except tEcyc:tPcyc 1:1 Figure 7.23 (a) Basic Burst Write Timing (AutoPrecharge) Except tEcyc:tPcyc 1:1 Figure 7.24 (a) Burst Read Timing (No Precharge) Except tEcyc:tPcyc 1:1 Figure 7.25 (a) Burst Read Timing (Bank Active, Same Row Address) Except tEcyc:tPcyc 1:1 Figure 7.26 (a) Burst Read Timing (Bank Active, Different Row Addresses) Except tEcyc:tPcyc 1:1 7.5.11 64-Mbit Synchronous DRAM (2 Mword × 32 Bit) Connection 323 Synchronous DRAM Mode Settings Description amended Synchronous DRAM Mode Settings: To make mode settings for the synchronous DRAM, write to address X + H'FFFF0000 or X + H'FFFF8000 from the CPU. (X represents the setting value.) Whether to use X + H'FFFF0000 or X + H'FFFF8000 determines on the synchronous DRAM used. 324 • 128-Mbit Synchronous DRAM (4 Mwords × 32 Bits) Connection Example Figure 7.35 added 310, 312
Figure 7.35 128-Mbit Synchronous DRAM (4 Mwords × 32 Bits) Connection Example
Rev. 2.00, 03/05, page xiii of xxxviii
Item 7.5.11 64-Mbit Synchronous DRAM (2 Mword × 32 Bit) Connection Figure 7.36 128-Mbit Synchronous DRAM (8 Mwords × 16 Bits) Connection Example Figure 7.37 256-Mbit Synchronous DRAM (8 Mwords × 32 Bits) Connection Example
Page 325
Revisions (See Manual for Details) • 128-Mbit Synchronous DRAM (8 Mwords × 16 Bits) Connection Example Figure 7.36 added
326
• 256-Mbit Synchronous DRAM (8 Mwords × 32 Bits) Connection Example Figure 7.37 added Section 7.11.3 added
7.11.3 Preventing Wrong 358 Data Output to Synchronous DRAM 8.2.1 Cache Control Register (CCR) Bit 4—Cache Purge Bit (CP) 9.2.1 EtherC Mode Register (ECMR) 384 361
Description added ... the CP bit reverts to 0. The CP bit always reads 0. Read the cache to check if initialization is completed. Bit 1—Duplex Mode (DM) Note added Note: When internal loopback mode is specified (ILB = 1), full-duplex transfer (DM = 1) must be used. The duplex mode information (half-duplex or full-duplex) detected by the PHY-LSI must be set to the DM bit. If this setting does not match the duplex mode in the PHY-LSI, the transfer rate may be degraded or a data collision may occur.
9.2.8 PHY Interface Status Register (PSR) 9.3.1 Transmission
391
Note added Note: The LMON bit is cleared to 0 when the LNKSTA pin is at a high level, and is set to 1 when the pin is at a low level.
405
Description amended 4. After waiting for the frame interval time (9.6 µs for 10Base or 0.96 µs for 100Base), the transmitter enters the idle state, and if there is more transmit data, continues transmitting.
9.5 Usage Notes
416
Section 9.5 added Note added For details on writing to the register, see section 10.4, Usage Notes. Note added For details on writing to the register, see section 10.4, Usage Notes.
10.2.2 E-DMAC Transmit 422 Request Register (EDTRR) 10.2.3 E-DMAC Receive 423 Request Register (EDRRR)
Rev. 2.00, 03/05, page xiv of xxxviii
Item 10.2.6 EtherC/E-DMAC Status Register (EESR)
Page 426, 427
Revisions (See Manual for Details) Bits 26 to 25 Description amended
Bit: Initial value: R/W: 31 — 0 R 30 — 0 R 29 — 0 R 28 — 0 R 27 — 0 R 26 TABT 0 R/W 25 RABT 0 R/W 24 RFCOF 0 R/W
Bits 31 to 27—Reserved: These bits are always read as 0. The write value should always read as 0. Bit 26—Transmit abort detection (TABT): Indicates whether or not a transmit abort was detected.
Bit 26: TABT 0 1 Description Transmit abort not detected Transmit abort detected (Initial value)
This bit will be set when any one or more of the following bits are set.
EESR bit 12: Illegal Transmit Frame (ITF) EESR bit 11: Carrier Not Detected (CND) EESR bit 10: Detect Loss of Carrier (DLC) EESR bit 9: Delayed Collision Detect (CD)
Bit 25— Receive abort detected (RABT): Indicates whether or not a receive abort was detected.
Bit 25: RABT 0 1 Description Receive abort not detected Receive abort detected (Initial value)
This bit will be set when any one or more of the following bits are set. EESR bit 4: Receive Residual-Bit Frame (RRF) EESR bit 3: Receive Too-Long Frame (RTLF) EESR bit 2: Receive Too-Short Frame (RTSF) EESR bit 1: PHY-LSI Receive Error (PRE) EESR bit 0: CRC Error on Received Frame (CERF)
430
Bit 9—Delayed Collision Detect (CD) Description amended
Bit 9—Delayed Collision Detect (CD): Indicates that a delayed collision has been detected during frame transmission.
Bit 9: CD 0 1 Description Delayed Collision not detected Delayed Collision detected (interrupt source) (Initial value)
10.2.8 Transmit/Receive 437 Status Copy Enable Register (TRSCER)
• • •
General description of register modified Bits 12 to 8, and 4 to 0 amended to reserved bits. Bit 7 Multicast Address Frame Receive (RMAF) Bit Copy Enable (RMAFCE) added.
10.2.10 Transmit FIFO Threshold Register (TFTR)
440, 441
Restriction added
Rev. 2.00, 03/05, page xv of xxxviii
Item 10.3.1 Descriptor List and Data Buffers
Page 449
Revisions (See Manual for Details) Transmit Descriptor Notes replaced Notes: 1. The descriptor start address must be specified to align with an address boundary corresponding to the descriptor length specified in the E-DMAC mode register (EDMR). 2. The transmit buffer start address must be specified to align with a longword boundary. Note, however, that it must be aligned with a 16-byte boundary when SDRAM is connected.
Transmit Descriptor 0 (TD0)
451
Bit 27—Transmit Frame Error (TFE) Description deleted Indicates that one or other bit of the transmit frame status indicated by bits 26 to 0 is set. ... Bits 26 to 0—Transmit Frame Status 26 to 0 (TFS26 to TFS0) • • Descriptions of TFS26 to TFS5 replaced Description of TFS1 amended Delayed Collision Detect in Transmission (corresponds to CD bit in EESR)
Transmit Descriptor 2 (TD2) Receive Descriptor
452
Note replaced Notes replaced
454
Bit 27—Receive Frame Error (RFE) Description amended ... indicated by bits 26 to 0 is set. Whether or not the multicast address frame receive information, which is part of the receive frame status, is copied into this bit is specified by the transmit/receive status copy enable register. Bits 26 to 0—Receive Frame Status 26 to 0 (RFS26 to RFS0) Description of RFS8 amended
Receive Descriptor 2 (RD2) 10.4 Usage Notes
455 461
Note replaced Newly added Description amended When 1 (burst mode) is set to bit TB, set 1 (edge detection) to the DREQ select bit (DS).
11.2.4 DMA Channel 473 Control Registers 0 and 1 (CHCR0, CHCR1) Bit 4—Transfer Bus Mode Bit (TB) 11.5 Usage Notes
520 to Notes 12, 13, 14, 15, and 16 added 524
Rev. 2.00, 03/05, page xvi of xxxviii
Item 13.2.3 Reset Control/Status Register (RSTCSR)
Page 553, 554
Revisions (See Manual for Details) Description amended RSTCR is initialized to H'1E by input of a reset signal from the pin, but is not initialized by the internal reset signal generated by overflow of the WDT. It is initialized to H'1E in standby mode, and in clock pause mode. Figure 13.9 amended
This LSI
Reset input RES
13.4.4 System Reset with Figure 13.9 Example of Circuit for System Reset with Signal
561
13.4.6 Internal Reset by Watchdog Timer (WDT) in Sleep Mode 14.2.6 Serial Control Register (SCSCR) 574
Bit 6—Receive Interrupt Enable (RIE) Description amended Bit 6—Receive Interrupt Enable (RIE): Enables or disables generation of receive-FIFO-data full interrupt (RXI), receiveerror interrupt (ERI), and break interrupt (BRI) requests when, after serial receive data is transferred from the receive shift register (SCRSR) to the receive FIFO data register (SCFRDR), the number of data bytes in SCFRDR reaches or exceeds the receive trigger set number, and the RDF flag is set to 1 in SC1SSR.
14.2.9 Bit Rate Register (SCBRR) Table 14.3 Examples of Bit Rates and SCBRR Settings in Asynchronous Mode
587, 588
Table 14.3 amended
Pφ (MHz) 12 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 0.00 –2.34 n 3 3 2 2 1 1 0 0 0 0 0 N 132 97 194 97 194 97 194 97 48 29 23 30 Error (%) 0.13 –0.35 0.16 –0.35 0.16 –0.35 0.16 –0.35 –0.35 0.00 1.73
SER
FVOTDW FVOTDW
Reset signal to entire system
WDTOVF
Section 13.4.6 added
Rev. 2.00, 03/05, page xvii of xxxviii
Item
Page
Revisions (See Manual for Details) Description amended SCFDR is initialized to H'0000 by a reset, by the module standby function, and in standby mode. Table 14.10 amended
SCSMR Settings CHR PE MP STOP
1 0 0 0
14.2.11 FIFO Data Count 594 Register (SCFDR) 14.3.2 Operation in Asynchronous Mode Transmit/Receive Format Table 14.10 Serial Transmit/Receive Formats (Asynchronous Mode) 601
Serial Transmit/Receive Format and Frame Length 1
S
2
3
4
5 7-bit data 7-bit data 7-bit data 7-bit data
6
7
8
9
STOP
10
11
12
1
S
STOP STOP
1
0
S
P
STOP
1
S
P
STOP STOP
14.3.3 Multiprocessor Communication Function Figure 14.12 Sample Multiprocessor Serial Transmission Flowchart
613
Figure 14.12 amended
Yes Read TEND bit in SC1SSR No
TEND = 1?
Figure 14.14 Sample Multiprocessor Serial Reception Flowchart (1)
616
Figure 14.14 (1) amended
BRK ∨ DR ∨ ER ∨ FER ∨ ORER = 1? No Read RDF flag in SC1SSR No RDF = 1? Yes Read receive data from SCFRDR, and clear RDF flag to 0 in SC1SSR No This station’s ID? Yes Read BRK, DR, ER, and FER bits in SC1SSR, and ORER bit in SC2SSR BRK ∨ DR ∨ ER ∨ FER ∨ ORER = 1? No
Yes
[3]
[4]
Yes
14.3.4 Operation in Synchronous Mode
619
Description amended In synchronous mode, the SCIF receives data in synchronization with the rising edge of the serial clock.
Rev. 2.00, 03/05, page xviii of xxxviii
Item 14.5 Usage Notes 17.1.2 H-UDI Block Diagram Figure 17.1 H-UDI Block Diagram
Page 640 732
Revisions (See Manual for Details) SCIF Initialization Flowchart and Receive-FIFO-Data-Full Interrupt (RXI) Requests added Figure 17.1 amended
SDIR
Shift register
SDSR
SDDRH
SDDRL
SDIDR
17.1.4 Register Configuration Table 17.2 Register Configuration
733
Table 17.2 amended
Register Instruction register Status register Data register H Data register L ID code register Abbreviation SDIR SDSR SDDRH SDDRL SDIDR
1 R/W*
Initial Value* H'E000 H'0401 Undefined Undefined H'0101000F
2
Address H'FFFFFCB0 H'FFFFFCB2 H'FFFFFCB4 H'FFFFFCB6 —
Access Size (Bits) 8/16/32 8/16 8/16/32 8/16 —
R R/W R/W R/W —
17.3.2 Status Register (SDSR)
737
Bit table amended
Bit: Initial value R/W: 15 — 0 R 14 — 0 R 13 — 0 R 12 — 0 R 11 — 0 R 10 — 1 R 9 — 0 R 8 — 0 R
17.3.6 ID Code Register 750 (SDIDR)
Description amended The ID code register (SDIDR) is a 32-bit register. In the IDCODE mode, SDIDR can output H'0101000F, which is a fixed code, from TDO. Description amended Figure 17.2 shows the internal states of TAP controller. State transitions basically conform with the IEEE1149.1 standard.
17.4.1 TAP Controller
751
Figure 17.2 TAP Controller State Transitions
Figure 17.2 amended
1 Test-logic-reset 0 0 Run-test/idle 1 Select-DR-scan 0 1 Select-IR-scan 1
Rev. 2.00, 03/05, page xix of xxxviii
Item 17.5.1 Supported Instructions
Page 756
Revisions (See Manual for Details) HIGHZ Description amended The instruction code is 0011. IDCODE Description amended The instruction code is 1110.
17.6 Usage Notes
757
Description amended • The registers are not initialized in standby mode. If TRST is set to 0 in standby mode, IDCODE mode will be entered.
18.1 Overview Table 18.1 Multiplex Pins
762
Table 18.1 amended
Function 1 [00]*
Signal Port Name B B B B PB3 PB2 PB1 PB0 I/O I/O I/O I/O I/O
Function 2 [01]*
I/O I I/O O —
Function 3 [10]*
I/O I/O I/O I/O I/O
Function 4 [11]*
I/O — — — O Related Module — — — EtherC
Related Signal Module Name Port Port Port Port STCK1 STS1 STXD1 —
Related Signal Module Name SIO1 SIO1 SIO1 — TIOCA0 TIOCB0 TIOCC0 TIOCD0
Related Signal Module Name TPU0 TPU0 TPU0 TPU0 — — — WOL
21.2 DC Characteristics Table 21.2 DC Characteristics
794
Table 21.2 amended
Item Three-state All I/O and output leakage pins (off status) current Output high Both 3.3 V and 5 V voltage Other output pins Output low Both 3.3 V and 5 V voltage Other output pins Symbol Min lTSI — Typ Max — 1.0 Unit Test Conditions µA V in = 0.5 to VCC – 0.5 V Vin = 0.5 to PVCC – 0.5 V VOH PVCC – 0.7 — VCC – 0.5 VCC – 1.0 VOL — — — — — — — — — 0.6 0.4 V V V V V IOH = –200 µA IOH = –200 µA IOH = –1 mA IOL = 1.6 mA IOL = 1.6 mA
21.3.1 Clock Timing Table 21.5 Clock Timing
797
Table 21.5 amended
Item CKPO clock output cycle time CKPO clock output low-level pulse width CKPO clock output high-level pulse width CKPO clock rise time CKPO clock fall time Power-on oscillation stabilization time Standby recovery oscillation stabilization time 1 Standby recovery oscillation stabilization time 2 PLL synchronization stabilization time Symbol tCKPCYC tCKPOL tCKPOH tCKPOr tCKPOf tOSC1 tOSC2 tOSC3 tPLL Min 32 11 11 — — 10 10 10 1 Max 1000 — — 5 5 — — — — Unit ns ns ns ns ns ms ms ms ms 21.5 21.6 21.7 21.8 Figure 21.4
Figure 21.3 CKIO Clock Output Timing
798
Figure 21.3 amended (Before) VIH → (After) VOH Figure 21.4 added
Figure 21.4 CKPO Clock 799 Output Timing
Rev. 2.00, 03/05, page xx of xxxviii
Item 21.3.3 Bus Timing Table 21.7 PLL-On Bus Timing [Modes 0 and 4] (2)
Page 805
Revisions (See Manual for Details) Conditions amended Conditions: VCC = PLLVCC = 3.3 V ± 5%, PVCC = 5.0 V ± 5%/3.3 V ± 5%, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –5 to +70°C, SDRAM bus cycle Figure 21.40 amended
CAS ⋅ OE CKE tOED1 tOED1 tOED2
Figure 21.40 EDO Read 834 Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait)
Rev. 2.00, 03/05, page xxi of xxxviii
Item 21.3.3 Bus Timing Figure 21.25 Synchronous DRAM Write Bus Cycle (Bank Active, Same Row Access, Except tEcyc:tPcyc 1:1) Figure 21.27 Synchronous DRAM Continuous Write Cycle (Bank Active, Same Row Access, Except tEcyc:tPcyc 1:1) Figure 21.45 Interrupt Vector Fetch Cycle (No Wait, Except tEcyc:tPcyc 1:1) Figure 21.46 Interrupt Vector Fetch Cycle (External Wait Input, Except tEcyc:tPcyc 1:1) Figure 21.50 FRT Input/Output Timing (Except tEcyc:tPcyc 1:1) Figure 21.52 FRT Clock Input Timing (Except tEcyc:tPcyc 1:1) Figure 21.57 TPU Input/Output Timing (Except tEcyc:tPcyc 1:1) Figure 21.60 Watchdog Timer Output Timing (Except tEcyc:tPcyc 1:1) Figure 21.69 I/O Port Input/Output Timing (Except tEcyc:tPcyc 1:1) Figure 21.70 MII Transmit Timing (Normal Operation) Figure 21.71 MII Transmit Timing (Case of Conflict) 21.3.6 Serial Communication Interface Timing Table 21.10 Serial Communication Interface Timing
Page 819, 821, 839, 840, 843, 846, 847, 852, 854
Revisions (See Manual for Details) Figure title amended
844
Table 21.10 amended (Before) tcscyc → (After) tscyc
Rev. 2.00, 03/05, page xxii of xxxviii
Item 21.3.8 Serial I/O Timing Table 21.13 Serial I/O Timing 21.3.11 Ethernet Controller Timing Table 21.16 Ethernet Controller Timing
Page 848
Revisions (See Manual for Details) Table 21.13 amended
Item SRCK, STCK clock input cycle time Symbol tsIcyc Min tPcyc or* 66.7 Max — Unit ns Figure 21.61
853
Table 21.16 amended
Item TX-CLK cycle time RX-CLK cycle time Symbol tTcyc tRcyc Min 40 40 Typ — — Max — — Unit ns ns 21.71 Figure
21.3.12 STATS, , and 856 Signal Timing
Table 21.17 amended
Item Symbol Min — Typ — Max 16 Unit ns Figure 21.78 STATS1 and STATS0 output delay time tSTATd
Figure 21.78 STATS Output Timing
A.1 Addresses
HB
Figure 21.79 Timing
Output 859 SICTR2 amended
Register Address H'FFFFFC24 H'FFFFFC25 Name SICTR2 Bit 7 — — Bit 6 — TM Bit 5 — SE Bit 4 — DL Bit Names Bit 3 — TIE Bit 2 — RIE Bit 1 — TE Bit 0 — RE Module SIO2
HB
Table 21.17 STATS, and Signal Timing
HB
ZiHSUB
ZiHSUB
,
856
Figure 21.78 and Figure 21.79 amended (Before) G-DMAC → (After) DMAC
862
SCSMR1 amended
Register Address Name Bit 7 C/A Bit 6 Bit 5 Bit 4 H'FFFF FCC0 SCSMR1 Bit Names Bit 3 Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module SCIF1 CHR/ICK3 PE/ICK2 O/E/ICK1 STOP/ ICK0
864
EESR amended
Register Address Name Bit 7 — — — RMAF Bit 6 — ECI — — Bit 5 — TC — — Bit Names Bit 4 — TDE ITF RRF Bit 3 — TFUF CND RTLF Bit 2 TABT FR DLC RTSF Bit 1 RABT RDE CD PRE Bit 0 RFCOF RFOF TRO CERF Module E-DMAC
H'FFFF FD14 EESR H'FFFF FD15 H'FFFF FD16 H'FFFF FD17
TRSCER amended
Register Address Name Bit 7 — — — Bit 6 — — — Bit 5 — — — — Bit 4 — — — — Bit Names Bit 3 — — — — Bit 2 — — — — Bit 1 — — — — Bit 0 — — — — Module E-DMAC
H'FFFF FD1C TRSCER H'FFFF FD1D H'FFFF FD1E H'FFFF FD1F
RMAFCE —
Rev. 2.00, 03/05, page xxiii of xxxviii
Item A.1 Addresses
Page 865
Revisions (See Manual for Details) EDOCR amended
Register Address H'FFFF FD30 H'FFFF FD31 H'FFFF FD32 H'FFFF FD33 Name EDOCR Bit 7 — — — — Bit 6 — — — — Bit 5 — — — — Bit 4 — — — — Bit Names Bit 3 — — — FEC Bit 2 — — — AEC Bit 1 — — — EDH Bit 0 — — — — Module E-DMAC
869
Register names amended H'FFFFFE71 (Before) DCDR0 → (After) DRCR0 H'FFFFFE72 (Before) DCDR1 → (After) DRCR1
872
BBRC amended
Register Address H'FFFFFF48 H'FFFFFF49 Name BBRC Bit 7 — CPC1 Bit 6 — CPC0 Bit 5 — IDC1 Bit 4 — IDC0 Bit Names Bit 3 — RWC1 Bit 2 — RWC0 Bit 1 XYEC SZC1 Bit 0 XYSC SZC0 Module UBC
876
MCR amended
Register Address H'FFFFFFEC H'FFFFFFED Name MCR Bit 7 TRP0 AMX2 Bit 6 RCD0 SZ Bit 5 TRWL0 AMX1 Bit 4 TRAS1 AMX0 Bit Names Bit 3 TRAS0 RFSH Bit 2 BE RMODE Bit 1 RASD TRP1 Bit 0 TRWL1 RCD1 Module BSC
B.1 Pin States in Reset, Power-Down State, and Bus-Released State
880
Table amended
Pin State Manual Reset Power-Down State BusReleased State O I
Pin Type EtherC
Pin Name ETXD3 to ETXD0 ERXD3 to ERXD0
Standby Standby PowerMode Sleep Mode On Bus Bus Reset Acquired Released (HIZ = 0) (HIZ = 1) Mode O I O I O I O I O I O I
Appendix C Product Lineup Table C.1 SH7615 Product Lineup
881
Table amended
Abbreviation SH7615 Voltage VCC = PLLVCC = 3.3 V PVCC = 5.0 V/3.3 V Operating Frequency 62.5 MHz Mark Code HD6417615ARF HD6417615ARFV HD6417615ARBP HD6417615ARBPV Package FP-208C FP-208CV BP-240A BP-240AV
Appendix D Package Dimensions
882
Description amended Figure D.1 shows the FP-208C and FP-208CV package dimensions, and figure D.2 shows the BP-240A and BP240AV package dimensions.
Figure D.1 Package Dimensions (FP-208C, FP-208CV) Figure D.2 Package Dimensions (BP-240A, BP-240AV)
882
Figure D.1 replaced
883
Figure D.2 added
Rev. 2.00, 03/05, page xxiv of xxxviii
Contents
Section 1 Overview.............................................................................................................
1.1 1.2 1.3 Features of SuperH Microcomputer with On-Chip Ethernet Controller ........................... Block Diagram.................................................................................................................. Pin Description ................................................................................................................. 1.3.1 Pin Arrangement.................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 1.3.3 Pin Multiplexing .................................................................................................. Processing States .............................................................................................................. 1 1 13 14 14 16 22 28
1.4
Section 2 CPU ...................................................................................................................... 33
2.1 Register Descriptions........................................................................................................ 2.1.1 General Registers................................................................................................. 2.1.2 Control Registers ................................................................................................. 2.1.3 System Registers.................................................................................................. 2.1.4 DSP Registers ...................................................................................................... 2.1.5 Notes on Guard Bits and Overflow Treatment .................................................... 2.1.6 Initial Values of Registers ................................................................................... Data Formats..................................................................................................................... 2.2.1 Data Format in Registers ..................................................................................... 2.2.2 Data Formats in Memory..................................................................................... 2.2.3 Immediate Data Format ....................................................................................... 2.2.4 DSP Type Data Formats ...................................................................................... 2.2.5 DSP Type Instructions and Data Formats............................................................ CPU Core Instruction Features ......................................................................................... Instruction Formats........................................................................................................... 2.4.1 CPU Instruction Addressing Modes .................................................................... 2.4.2 DSP Data Addressing .......................................................................................... 2.4.3 Instruction Formats for CPU Instructions............................................................ 2.4.4 Instruction Formats for DSP Instructions ............................................................ Instruction Set................................................................................................................... 2.5.1 CPU Instruction Set ............................................................................................. 2.5.2 DSP Data Transfer Instruction Set....................................................................... 2.5.3 DSP Operation Instruction Set............................................................................. 2.5.4 Various Operation Instructions............................................................................ Usage Notes ...................................................................................................................... 33 33 35 38 39 42 42 43 43 43 44 44 46 50 54 54 58 64 67 73 74 89 93 96 104
2.2
2.3 2.4
2.5
2.6
Section 3 Oscillator Circuits and Operating Modes .................................................. 107
3.1 3.2 Overview........................................................................................................................... 107 On-Chip Clock Pulse Generator and Operating Modes .................................................... 107
Rev. 2.00, 03/05, page xxv of xxxviii
3.3
3.2.1 Clock Pulse Generator ......................................................................................... 3.2.2 Clock Operating Mode Settings........................................................................... 3.2.3 Connecting a Crystal Resonator .......................................................................... 3.2.4 External Clock Input............................................................................................ 3.2.5 Operating Frequency Selection by Register......................................................... 3.2.6 Clock Modes and Frequency Ranges................................................................... 3.2.7 Notes on Board Design ........................................................................................ Bus Width of the CS0 Area ..............................................................................................
107 109 112 113 114 122 123 124
Section 4 Exception Handling ......................................................................................... 125
4.1 Overview........................................................................................................................... 4.1.1 Types of Exception Handling and Priority Order ................................................ 4.1.2 Exception Handling Operations........................................................................... 4.1.3 Exception Vector Table ....................................................................................... Resets................................................................................................................................ 4.2.1 Types of Resets.................................................................................................... 4.2.2 Power-On Reset................................................................................................... 4.2.3 Manual Reset ....................................................................................................... Address Errors .................................................................................................................. 4.3.1 Sources of Address Errors ................................................................................... 4.3.2 Address Error Exception Handling...................................................................... Interrupts........................................................................................................................... 4.4.1 Interrupt Sources.................................................................................................. 4.4.2 Interrupt Priority Levels....................................................................................... 4.4.3 Interrupt Exception Handling .............................................................................. Exceptions Triggered by Instructions ............................................................................... 4.5.1 Instruction-Triggered Exception Types ............................................................... 4.5.2 Trap Instructions.................................................................................................. 4.5.3 Illegal Slot Instructions........................................................................................ 4.5.4 General Illegal Instructions.................................................................................. When Exception Sources Are Not Accepted .................................................................... 4.6.1 Immediately after a Delayed Branch Instruction ................................................. 4.6.2 Immediately after an Interrupt-Disabled Instruction............................................ 4.6.3 Instructions in Repeat Loops ............................................................................... Stack Status after Exception Handling.............................................................................. Usage Notes ...................................................................................................................... 4.8.1 Value of Stack Pointer (SP) ................................................................................. 4.8.2 Value of Vector Base Register (VBR)................................................................. 4.8.3 Address Errors Caused by Stacking of Address Error Exception Handling ........ 4.8.4 Manual Reset during Register Access ................................................................. 125 125 127 128 131 131 131 132 132 132 134 135 135 136 136 137 137 137 138 138 139 139 139 140 141 142 142 142 142 142
4.2
4.3
4.4
4.5
4.6
4.7 4.8
Section 5 Interrupt Controller (INTC)........................................................................... 143
5.1 Overview........................................................................................................................... 143
Rev. 2.00, 03/05, page xxvi of xxxviii
5.2
5.3
5.4
5.1.1 Features................................................................................................................ 5.1.2 Block Diagram..................................................................................................... 5.1.3 Input/Output Pins................................................................................................. 5.1.4 Register Configuration......................................................................................... Interrupt Sources............................................................................................................... 5.2.1 NMI Interrupt ...................................................................................................... 5.2.2 User Break Interrupt ............................................................................................ 5.2.3 H-UDI Interrupt................................................................................................... 5.2.4 IRL Interrupts ...................................................................................................... 5.2.5 IRQ Interrupts...................................................................................................... 5.2.6 On-chip Peripheral Module Interrupts ................................................................. 5.2.7 Interrupt Exception Vectors and Priority Order................................................... Register Descriptions........................................................................................................ 5.3.1 Interrupt Priority Level Setting Register A (IPRA) ............................................. 5.3.2 Interrupt Priority Level Setting Register B (IPRB) ............................................. 5.3.3 Interrupt Priority Level Setting Register C (IPRC) ............................................. 5.3.4 Interrupt Priority Level Setting Register D (IPRD) ............................................. 5.3.5 Interrupt Priority Level Setting Register E (IPRE).............................................. 5.3.6 Vector Number Setting Register WDT (VCRWDT) ........................................... 5.3.7 Vector Number Setting Register A (VCRA) ....................................................... 5.3.8 Vector Number Setting Register B (VCRB)........................................................ 5.3.9 Vector Number Setting Register C (VCRC)........................................................ 5.3.10 Vector Number Setting Register D (VCRD) ....................................................... 5.3.11 Vector Number Setting Register E (VCRE) ........................................................ 5.3.12 Vector Number Setting Register F (VCRF)......................................................... 5.3.13 Vector Number Setting Register G (VCRG) ....................................................... 5.3.14 Vector Number Setting Register H (VCRH) ....................................................... 5.3.15 Vector Number Setting Register I (VCRI) .......................................................... 5.3.16 Vector Number Setting Register J (VCRJ).......................................................... 5.3.17 Vector Number Setting Register K (VCRK) ....................................................... 5.3.18 Vector Number Setting Register L (VCRL) ........................................................ 5.3.19 Vector Number Setting Register M (VCRM) ...................................................... 5.3.20 Vector Number Setting Register N (VCRN) ....................................................... 5.3.21 Vector Number Setting Register O (VCRO) ....................................................... 5.3.22 Vector Number Setting Register P (VCRP)......................................................... 5.3.23 Vector Number Setting Register Q (VCRQ) ....................................................... 5.3.24 Vector Number Setting Register R (VCRR)........................................................ 5.3.25 Vector Number Setting Register S (VCRS)......................................................... 5.3.26 Vector Number Setting Register T (VCRT) ........................................................ 5.3.27 Vector Number Setting Register U (VCRU) ....................................................... 5.3.28 Interrupt Control Register (ICR).......................................................................... 5.3.29 IRQ Control/Status Register (IRQCSR) .............................................................. Interrupt Operation ...........................................................................................................
143 144 145 145 146 147 147 147 147 148 152 152 159 159 160 161 162 163 164 165 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 187 188 191
Rev. 2.00, 03/05, page xxvii of xxxviii
Section 6 User Break Controller (UBC) ....................................................................... 201
6.1 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram..................................................................................................... 6.1.3 Register Configuration......................................................................................... Register Descriptions........................................................................................................ 6.2.1 Break Address Register A (BARA) ..................................................................... 6.2.2 Break Address Mask Register A (BAMRA)........................................................ 6.2.3 Break Bus Cycle Register A (BBRA).................................................................. 6.2.4 Break Address Register B (BARB) ..................................................................... 6.2.5 Break Address Mask Register B (BAMRB) ........................................................ 6.2.6 Break Bus Cycle Register B (BBRB) .................................................................. 6.2.7 Break Address Register C (BARC) ..................................................................... 6.2.8 Break Address Mask Register C (BAMRC) ........................................................ 6.2.9 Break Data Register C (BDRC)........................................................................... 6.2.10 Break Data Mask Register C (BDMRC) ............................................................. 6.2.11 Break Bus Cycle Register C (BBRC) .................................................................. 6.2.12 Break Execution Times Register C (BETRC) ..................................................... 6.2.13 Break Address Register D (BARD)..................................................................... 6.2.14 Break Address Mask Register D (BAMRD)........................................................ 6.2.15 Break Data Register D (BDRD) .......................................................................... 6.2.16 Break Data Mask Register D (BDMRD) ............................................................. 6.2.17 Break Bus Cycle Register D (BBRD).................................................................. 6.2.18 Break Execution Times Register D (BETRD)..................................................... 6.2.19 Break Control Register (BRCR) .......................................................................... 6.2.20 Branch Flag Registers (BRFR) ............................................................................ 6.2.21 Branch Source Registers (BRSR) ........................................................................ 6.2.22 Branch Destination Registers (BRDR) ................................................................ Operation .......................................................................................................................... 6.3.1 User Break Operation Sequence .......................................................................... 6.3.2 Instruction Fetch Cycle Break ............................................................................. 6.3.3 Data Access Cycle Break..................................................................................... 6.3.4 Saved Program Counter (PC) Value .................................................................... 6.3.5 X Memory Bus or Y Memory Bus Cycle Break.................................................. 6.3.6 Sequential Break.................................................................................................. 6.3.7 PC Traces............................................................................................................. 6.3.8 Examples of Use .................................................................................................. 201 201 202 203 205 205 206 207 209 210 211 213 214 216 217 219 220 221 222 224 225 227 228 229 234 235 236 237 237 238 239 240 240 241 242 244
6.2
6.3
Rev. 2.00, 03/05, page xxviii of xxxviii
0LRI
3LRI
5.5 5.6 5.7
5.4.1 Interrupt Sequence ............................................................................................... 5.4.2 Stack State after Interrupt Exception Handling ................................................... Interrupt Response Time................................................................................................... Sampling of Pins to ........................................................................................ Usage Notes ......................................................................................................................
191 193 193 195 196
6.3.9
Usage Notes......................................................................................................... 249
Section 7 Bus State Controller (BSC) ........................................................................... 251
7.1 Overview........................................................................................................................... 7.1.1 Features................................................................................................................ 7.1.2 Block Diagram..................................................................................................... 7.1.3 Input/Output Pins................................................................................................. 7.1.4 Register Configuration......................................................................................... 7.1.5 Address Map........................................................................................................ Register Descriptions........................................................................................................ 7.2.1 Bus Control Register 1 (BCR1) ........................................................................... 7.2.2 Bus Control Register 2 (BCR2) ........................................................................... 7.2.3 Bus Control Register 3 (BCR3) ........................................................................... 7.2.4 Wait Control Register 1 (WCR1) ........................................................................ 7.2.5 Wait Control Register 2 (WCR2) ........................................................................ 7.2.6 Wait Control Register 3 (WCR3) ........................................................................ 7.2.7 Individual Memory Control Register (MCR) ...................................................... 7.2.8 Refresh Timer Control/Status Register (RTCSR)................................................ 7.2.9 Refresh Timer Counter (RTCNT)........................................................................ 7.2.10 Refresh Time Constant Register (RTCOR) ......................................................... Access Size and Data Alignment ...................................................................................... 7.3.1 Connection to Ordinary Devices.......................................................................... 7.3.2 Connection to Little-Endian Devices................................................................... Accessing Ordinary Space ................................................................................................ 7.4.1 Basic Timing........................................................................................................ 7.4.2 Wait State Control ............................................................................................... 7.4.3 Assertion Period Extension............................................................................ Synchronous DRAM Interface ......................................................................................... 7.5.1 Synchronous DRAM Direct Connection ............................................................. 7.5.2 Address Multiplexing .......................................................................................... 7.5.3 Burst Reads.......................................................................................................... 7.5.4 Single Reads ........................................................................................................ 7.5.5 Single Writes ....................................................................................................... 7.5.6 Burst Write Mode ................................................................................................ 7.5.7 Bank Active Function .......................................................................................... 7.5.8 Refreshes ............................................................................................................. 7.5.9 Overlap Between Auto Precharge Cycle (Tap) and Next Access........................ 7.5.10 Power-On Sequence............................................................................................. 7.5.11 64-Mbit Synchronous DRAM (2 Mwords × 32 Bits) Connection....................... DRAM Interface ............................................................................................................... 7.6.1 DRAM Direct Connection ................................................................................... 7.6.2 Address Multiplexing .......................................................................................... 7.6.3 Basic Timing........................................................................................................
SC
7.2
7.3
7.4
7.5
7.6
251 251 253 254 256 257 259 259 262 263 265 267 269 270 276 277 278 279 279 280 282 282 287 291 292 292 294 296 301 303 304 307 317 320 321 323 327 327 328 329
Rev. 2.00, 03/05, page xxix of xxxviii
7.6.4 Wait State Control ............................................................................................... 7.6.5 Burst Access ........................................................................................................ 7.6.6 EDO Mode........................................................................................................... 7.6.7 DRAM Single Transfer........................................................................................ 7.6.8 Refreshing............................................................................................................ 7.6.9 Power-On Sequence............................................................................................. 7.7 Burst ROM Interface ........................................................................................................ 7.8 Idles between Cycles ........................................................................................................ 7.9 Bus Arbitration ................................................................................................................. 7.9.1 Master Mode........................................................................................................ 7.10 Additional Items ............................................................................................................... 7.10.1 Resets................................................................................................................... 7.10.2 Access as Viewed from CPU, DMAC or E-DMAC ............................................ 7.10.3 STATS1 and STATS0 Pins ................................................................................. 7.10.4 Specification ......................................................................................... 7.11 Usage Notes ...................................................................................................................... 7.11.1 Normal Space Access after Synchronous DRAM Write when Using DMAC .... 7.11.2 When Using Iφ:Eφ Clock Ratio of 1:1, 8-Bit Bus Width, and External Wait Input....................................................................................... 7.11.3 Preventing Wrong Data Output to Synchronous DRAM.....................................
ZiHSUB
330 332 335 339 340 342 342 346 348 352 353 353 353 355 355 356 356 358 358
Section 8 Cache.................................................................................................................... 359
8.1 8.2 8.3 8.4 Introduction ...................................................................................................................... 8.1.1 Register Configuration......................................................................................... Register Description ......................................................................................................... 8.2.1 Cache Control Register (CCR) ............................................................................ Address Space and the Cache ........................................................................................... Cache Operation ............................................................................................................... 8.4.1 Cache Reads ........................................................................................................ 8.4.2 Write Access........................................................................................................ 8.4.3 Cache-Through Access........................................................................................ 8.4.4 The TAS Instruction ............................................................................................ 8.4.5 Pseudo-LRU and Cache Replacement ................................................................. 8.4.6 Cache Initialization.............................................................................................. 8.4.7 Associative Purges............................................................................................... 8.4.8 Cache Flushing .................................................................................................... 8.4.9 Data Array Access ............................................................................................... 8.4.10 Address Array Access.......................................................................................... Cache Use ......................................................................................................................... 8.5.1 Initialization......................................................................................................... 8.5.2 Purge of Specific Lines........................................................................................ 8.5.3 Cache Data Coherency......................................................................................... 8.5.4 Two-Way Cache Mode........................................................................................ 359 360 360 360 362 363 363 365 368 368 368 370 370 371 371 372 373 373 374 374 375
8.5
Rev. 2.00, 03/05, page xxx of xxxviii
8.6
Usage Notes ...................................................................................................................... 376 8.6.1 Standby ................................................................................................................ 376 8.6.2 Cache Control Register........................................................................................ 376
Section 9 Ethernet Controller (EtherC) ......................................................................... 377
9.1 Overview........................................................................................................................... 9.1.1 Features................................................................................................................ 9.1.2 Configuration....................................................................................................... 9.1.3 Input/Output Pins................................................................................................. 9.1.4 Ethernet Controller Register Configuration......................................................... Register Descriptions........................................................................................................ 9.2.1 EtherC Mode Register (ECMR) .......................................................................... 9.2.2 EtherC Status Register (ECSR) ........................................................................... 9.2.3 EtherC Interrupt Permission Register (ECSIPR) ................................................. 9.2.4 PHY Interface Register (PIR) .............................................................................. 9.2.5 MAC Address High Register (MAHR) ............................................................... 9.2.6 MAC Address Low Register (MALR)................................................................. 9.2.7 Receive Frame Length Register (RFLR) ............................................................. 9.2.8 PHY Interface Status Register (PSR) .................................................................. 9.2.9 Transmit Retry Over Counter Register (TROCR) ............................................... 9.2.10 Collision Detect Counter Register (CDCR)......................................................... 9.2.11 Lost Carrier Counter Register (LCCR)................................................................ 9.2.12 Carrier Not Detect Counter Register (CNDCR) .................................................. 9.2.13 Illegal Frame Length Counter Register (IFLCR)................................................. 9.2.14 CRC Error Frame Counter Register (CEFCR) .................................................... 9.2.15 Frame Receive Error Counter Register (FRECR )............................................... 9.2.16 Too-Short Frame Receive Counter Register (TSFRCR) ..................................... 9.2.17 Too-Long Frame Receive Counter Register (TLFRCR ) .................................... 9.2.18 Residual-Bit Frame Counter Register (RFCR) .................................................... 9.2.19 Multicast Address Frame Counter Register (MAFCR) ....................................... Operation .......................................................................................................................... 9.3.1 Transmission........................................................................................................ 9.3.2 Reception ............................................................................................................. 9.3.3 MII Frame Timing ............................................................................................... 9.3.4 Accessing MII Registers...................................................................................... 9.3.5 Magic Packet Detection....................................................................................... 9.3.6 CPU Operating Mode and Ethernet Controller Operation................................... Connection to PHY-LSI.................................................................................................... Usage Notes ...................................................................................................................... 377 377 378 380 381 382 382 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 403 405 407 409 412 413 414 416
9.2
9.3
9.4 9.5
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) ....................................................................................................... 417
10.1 Overview........................................................................................................................... 417
Rev. 2.00, 03/05, page xxxi of xxxviii
10.1.1 Features................................................................................................................ 10.1.2 Configuration....................................................................................................... 10.1.3 Descriptor Management System.......................................................................... 10.1.4 Register Configuration......................................................................................... 10.2 Register Descriptions........................................................................................................ 10.2.1 E-DMAC Mode Register (EDMR)...................................................................... 10.2.2 E-DMAC Transmit Request Register (EDTRR) ................................................. 10.2.3 E-DMAC Receive Request Register (EDRRR)................................................... 10.2.4 Transmit Descriptor List Address Register (TDLAR)......................................... 10.2.5 Receive Descriptor List Address Register (RDLAR) .......................................... 10.2.6 EtherC/E-DMAC Status Register (EESR)........................................................... 10.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)...................... 10.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................ 10.2.9 Receive Missed-Frame Counter Register (RMFCR) ........................................... 10.2.10 Transmit FIFO Threshold Register (TFTR) ........................................................ 10.2.11 FIFO Depth Register (FDR) ................................................................................ 10.2.12 Receiver Control Register (RCR) ........................................................................ 10.2.13 E-DMAC Operation Control Register (EDOCR) ................................................ 10.2.14 Receiving-Buffer Write Address Register (RBWAR) ......................................... 10.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) .................................... 10.2.16 Transmission-Buffer Read Address Register (TBRAR)...................................... 10.2.17 Transmission-Descriptor Fetch Address Register (TDFAR) ............................... 10.3 Operation .......................................................................................................................... 10.3.1 Descriptor List and Data Buffers ......................................................................... 10.3.2 Transmission........................................................................................................ 10.3.3 Reception ............................................................................................................. 10.3.4 Multi-Buffer Frame Transmit/Receive Processing .............................................. 10.4 Usage Notes ...................................................................................................................... 10.4.1 E-DMAC Transmit Request Register (EDTRR) and E-DMAC Receive Request Register (EDRRR) Usage Notes ............................................................
417 418 419 419 421 421 422 423 424 425 426 432 437 438 439 440 443 444 445 446 447 448 449 449 455 457 459 461 461 463 463 463 465 466 467 468 468 468 469 470 474
Section 11 Direct Memory Access Controller (DMAC).......................................... 11.1 Overview........................................................................................................................... 11.1.1 Features................................................................................................................ 11.1.2 Block Diagram..................................................................................................... 11.1.3 Input/Output Pins................................................................................................. 11.1.4 Register Configuration......................................................................................... 11.2 Register Descriptions........................................................................................................ 11.2.1 DMA Source Address Registers 0 and 1 (SAR0, SAR1) .................................... 11.2.2 DMA Destination Address Registers 0 and 1 (DAR0, DAR1)............................ 11.2.3 DMA Transfer Count Registers 0 and 1 (TCR0, TCR1) ..................................... 11.2.4 DMA Channel Control Registers 0 and 1 (CHCR0, CHCR1)............................. 11.2.5 DMA Vector Number Registers 0 and 1 (VCRDMA0, VCRDMA1) .................
Rev. 2.00, 03/05, page xxxii of xxxviii
11.2.6 DMA Request/Response Selection Control Registers 0 and 1 (DRCR0, DRCR1)............................................................................................... 11.2.7 DMA Operation Register (DMAOR) .................................................................. 11.3 Operation .......................................................................................................................... 11.3.1 DMA Transfer Flow ............................................................................................ 11.3.2 DMA Transfer Requests ...................................................................................... 11.3.3 Channel Priorities ................................................................................................ 11.3.4 DMA Transfer Types........................................................................................... 11.3.5 Number of Bus Cycles......................................................................................... 11.3.6 DMA Transfer Request Acknowledge Signal Output Timing............................. 11.3.7 DREQn Pin Input Detection Timing.................................................................... 11.3.8 DMA Transfer End .............................................................................................. 11.3.9 Pin Output Timing......................................................................................... 11.4 Usage Examples................................................................................................................ 11.4.1 Example of DMA Data Transfer Between On-chip SCIF and External Memory 11.5 Usage Notes ......................................................................................................................
HB
475 477 479 479 481 485 488 498 498 509 515 516 517 517 518
Section 12 16-Bit Free-Running Timer (FRT) ........................................................... 525
12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram..................................................................................................... 12.1.3 Input/Output Pins................................................................................................. 12.1.4 Register Configuration......................................................................................... 12.2 Register Descriptions........................................................................................................ 12.2.1 Free-Running Counter (FRC) .............................................................................. 12.2.2 Output Compare Registers A and B (OCRA and OCRB) ................................... 12.2.3 Input Capture Register (FICR) ............................................................................ 12.2.4 Timer Interrupt Enable Register (TIER).............................................................. 12.2.5 Free-Running Timer Control/Status Register (FTCSR) ...................................... 12.2.6 Timer Control Register (TCR)............................................................................. 12.2.7 Timer Output Compare Control Register (TOCR) .............................................. 12.3 CPU Interface ................................................................................................................... 12.4 Operation .......................................................................................................................... 12.4.1 FRC Count Timing .............................................................................................. 12.4.2 Output Timing for Output Compare .................................................................... 12.4.3 FRC Clear Timing ............................................................................................... 12.4.4 Input Capture Input Timing ................................................................................. 12.4.5 Input Capture Flag (ICF) Setting Timing ............................................................ 12.4.6 Output Compare Flag (OCFA, OCFB) Setting Timing ....................................... 12.4.7 Timer Overflow Flag (OVF) Setting Timing....................................................... 12.5 Interrupt Sources............................................................................................................... 12.6 Example of FRT Use ........................................................................................................ 12.7 Usage Notes ...................................................................................................................... 525 525 526 527 527 528 528 528 529 529 530 532 533 534 537 537 538 538 539 540 540 541 542 542 543
Rev. 2.00, 03/05, page xxxiii of xxxviii
12.7.1 12.7.2 12.7.3 12.7.4 12.7.5
Contention between FRC Write and Clear .......................................................... Contention between FRC Write and Increment................................................... Contention between OCR Write and Compare Match......................................... Internal Clock Switching and Counter Operation................................................ Timer Output (FTOA, FTOB) .............................................................................
543 544 545 545 547 549 549 549 550 550 551 551 551 552 553 554 556 556 558 558 559 559 560 560 560 560 561 561 561 563 563 563 565 566 567 568 568 568 569 569 570
Section 13 Watchdog Timer (WDT).............................................................................. 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram..................................................................................................... 13.1.3 Input/Output Pin .................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions........................................................................................................ 13.2.1 Watchdog Timer Counter (WTCNT)................................................................... 13.2.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 13.2.3 Reset Control/Status Register (RSTCSR)............................................................ 13.2.4 Notes on Register Access .................................................................................... 13.3 Operation .......................................................................................................................... 13.3.1 Operation in Watchdog Timer Mode................................................................... 13.3.2 Operation in Interval Timer Mode....................................................................... 13.3.3 Operation when Standby Mode is Cleared .......................................................... 13.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 13.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting ............................. 13.4 Usage Notes ...................................................................................................................... 13.4.1 Contention between WTCNT Write and Increment ............................................ 13.4.2 Changing CKS2 to CKS0 Bit Values .................................................................. 13.4.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 13.4.4 System Reset with .............................................................................. 13.4.5 Internal Reset in Watchdog Timer Mode............................................................. 13.4.6 Internal Reset by Watchdog Timer (WDT) in Sleep Mode ................................. Section 14 Serial Communication Interface with FIFO (SCIF) ............................ 14.1 Overview........................................................................................................................... 14.1.1 Features................................................................................................................ 14.1.2 Block Diagrams ................................................................................................... 14.1.3 Input/Output Pins................................................................................................. 14.1.4 Register Configuration......................................................................................... 14.2 Register Descriptions........................................................................................................ 14.2.1 Receive Shift Register (SCRSR) ......................................................................... 14.2.2 Receive FIFO Data Register (SCFRDR) ............................................................. 14.2.3 Transmit Shift Register (SCTSR) ........................................................................ 14.2.4 Transmit FIFO Data Register (SCFTDR)............................................................ 14.2.5 Serial Mode Register (SCSMR)...........................................................................
Rev. 2.00, 03/05, page xxxiv of xxxviii
FVOTDW
14.2.6 Serial Control Register (SCSCR)......................................................................... 14.2.7 Serial Status 1 Register (SC1SSR) ...................................................................... 14.2.8 Serial Status 2 Register (SC2SSR) ...................................................................... 14.2.9 Bit Rate Register (SCBRR) ................................................................................. 14.2.10 FIFO Control Register (SCFCR) ......................................................................... 14.2.11 FIFO Data Count Register (SCFDR) ................................................................... 14.2.12 FIFO Error Register (SCFER) ............................................................................. 14.2.13 IrDA Mode Register (SCIMR) ............................................................................ 14.3 Operation .......................................................................................................................... 14.3.1 Overview.............................................................................................................. 14.3.2 Operation in Asynchronous Mode ....................................................................... 14.3.3 Multiprocessor Communication Function ........................................................... 14.3.4 Operation in Synchronous Mode ......................................................................... 14.3.5 Use of Transmit/Receive FIFO Buffers............................................................... 14.3.6 Operation in IrDA Mode ..................................................................................... 14.4 SCIF Interrupt Sources and the DMAC............................................................................ 14.5 Usage Notes ......................................................................................................................
573 577 582 584 592 594 595 595 597 597 600 611 619 629 632 635 636 643 643 643 646 647 647 648 648 649 651 653 653 654 657
Section 15 Serial I/O (SIO) .............................................................................................. 15.1 Overview........................................................................................................................... 15.1.1 Features................................................................................................................ 15.2 Register Configuration...................................................................................................... 15.2.1 Receive Shift Register (SIRSR)........................................................................... 15.2.2 Receive Data Register (SIRDR) .......................................................................... 15.2.3 Transmit Shift Register (SITSR) ......................................................................... 15.2.4 Transmit Data Register (SITDR)......................................................................... 15.2.5 Serial Control Register (SICTR).......................................................................... 15.2.6 Serial Status Register (SISTR) ............................................................................ 15.3 Operation .......................................................................................................................... 15.3.1 Input..................................................................................................................... 15.3.2 Output .................................................................................................................. 15.4 SIO Interrupt Sources and DMAC....................................................................................
16.1 Overview........................................................................................................................... 16.1.1 Features................................................................................................................ 16.1.2 Block Diagram..................................................................................................... 16.1.3 Input/Output Pins................................................................................................. 16.1.4 Register Configuration......................................................................................... 16.2 Register Descriptions........................................................................................................ 16.2.1 Timer Control Register (TCR)............................................................................. 16.2.2 Timer Mode Register (TMDR)............................................................................ 16.2.3 Timer I/O Control Register (TIOR).....................................................................
Section 16 16-Bit Timer Pulse Unit (TPU).................................................................. 659
659 659 662 663 664 665 665 669 671
Rev. 2.00, 03/05, page xxxv of xxxviii
16.3
16.4
16.5
16.6
16.7 16.8
16.2.4 Timer Interrupt Enable Register (TIER).............................................................. 16.2.5 Timer Status Register (TSR)................................................................................ 16.2.6 Timer Counter (TCNT)........................................................................................ 16.2.7 Timer General Register (TGR) ............................................................................ 16.2.8 Timer Start Register (TSTR) ............................................................................... 16.2.9 Timer Synchro Register (TSYR) ......................................................................... Interface to Bus Master..................................................................................................... 16.3.1 16-Bit Registers ................................................................................................... 16.3.2 8-Bit Registers ..................................................................................................... Operation .......................................................................................................................... 16.4.1 Overview.............................................................................................................. 16.4.2 Basic Functions.................................................................................................... 16.4.3 Synchronous Operation ....................................................................................... 16.4.4 Buffer Operation.................................................................................................. 16.4.5 PWM Modes........................................................................................................ 16.4.6 Phase Counting Mode.......................................................................................... Interrupts........................................................................................................................... 16.5.1 Interrupt Sources and Priorities ........................................................................... 16.5.2 DMAC Activation ............................................................................................... Operation Timing.............................................................................................................. 16.6.1 Input/Output Timing............................................................................................ 16.6.2 Interrupt Signal Timing ....................................................................................... Usage Notes ...................................................................................................................... Usage Notes ...................................................................................................................... 16.8.1 Clearing Flags in TSR0 to TSR2 ......................................................................... 16.8.2 DMA Transfer by TPU0......................................................................................
678 680 683 684 684 685 686 686 686 688 688 689 695 697 701 706 711 711 712 713 713 717 720 730 730 730 731 731 731 732 733 733 734 734 734 734 734 735 735 735 737 738
Section 17 High-Performance User Debugging Interface (H-UDI) ..................... 17.1 Overview........................................................................................................................... 17.1.1 Features................................................................................................................ 17.1.2 H-UDI Block Diagram......................................................................................... 17.1.3 Input/Output Pins................................................................................................. 17.1.4 Register Configuration......................................................................................... 17.2 External Signals ................................................................................................................ 17.2.1 Test Clock (TCK) ................................................................................................ 17.2.2 Test Mode Select (TMS)...................................................................................... 17.2.3 Test Data Input (TDI) .......................................................................................... 17.2.4 Test Data Output (TDO)...................................................................................... 17.2.5 Test Reset ( ) ............................................................................................... 17.3 Register Descriptions........................................................................................................ 17.3.1 Instruction Register (SDIR) ................................................................................. 17.3.2 Status Register (SDSR)........................................................................................ 17.3.3 Data Register (SDDR) .........................................................................................
Rev. 2.00, 03/05, page xxxvi of xxxviii
TSRT
17.3.4 Bypass Register (SDBPR) ................................................................................... 17.3.5 Boundary Scan Register (SDBSR) ...................................................................... 17.3.6 ID Code Register (SDIDR).................................................................................. 17.4 Operation .......................................................................................................................... 17.4.1 TAP Controller .................................................................................................... 17.4.2 H-UDI Interrupt and Serial Transfer.................................................................... 17.4.3 H-UDI Reset ........................................................................................................ 17.5 Boundary Scan.................................................................................................................. 17.5.1 Supported Instructions ......................................................................................... 17.5.2 Notes on Use........................................................................................................ 17.6 Usage Notes ......................................................................................................................
738 738 750 751 751 752 755 755 755 756 757
Section 18 Pin Function Controller (PFC) ................................................................... 761 18.1 Overview........................................................................................................................... 761 18.2 Register Configuration...................................................................................................... 763 18.3 Register Descriptions........................................................................................................ 763 18.3.1 Port A Control Register (PACR) ......................................................................... 763 18.3.2 Port A I/O Register (PAIOR)............................................................................... 766 18.3.3 Port B Control Registers (PBCR, PBCR2) .......................................................... 767 18.3.4 Port B I/O Register (PBIOR) ............................................................................... 772 Section 19 I/O Ports ............................................................................................................ 773
19.1 Overview........................................................................................................................... 773 19.2 Port A................................................................................................................................ 773 19.2.1 Register Configuration......................................................................................... 774 19.2.2 Port A Data Register (PADR).............................................................................. 774 19.3 Port B................................................................................................................................ 775 19.3.1 Register Configuration......................................................................................... 776 19.3.2 Port B Data Register (PBDR) .............................................................................. 776
Section 20 Power-Down Modes...................................................................................... 20.1 Overview........................................................................................................................... 20.1.1 Power-Down Modes ............................................................................................ 20.1.2 Register................................................................................................................ 20.2 Register Descriptions........................................................................................................ 20.2.1 Standby Control Register 1 (SBYCR1) ............................................................... 20.2.2 Standby Control Register 2 (SBYCR2) ............................................................... 20.3 Sleep Mode ....................................................................................................................... 20.3.1 Transition to Sleep Mode..................................................................................... 20.3.2 Canceling Sleep Mode......................................................................................... 20.4 Standby Mode................................................................................................................... 20.4.1 Transition to Standby Mode ................................................................................ 20.4.2 Canceling Standby Mode.....................................................................................
779 779 779 780 781 781 783 785 785 785 785 785 787
Rev. 2.00, 03/05, page xxxvii of xxxviii
20.4.3 Standby Mode Cancellation by NMI Interrupt .................................................... 20.4.4 Clock Pause Function .......................................................................................... 20.4.5 Notes on Standby Mode....................................................................................... 20.5 Module Standby Function................................................................................................. 20.5.1 Transition to Module Standby Function .............................................................. 20.5.2 Clearing the Module Standby Function ...............................................................
787 788 790 791 791 791 793 793 794 796 797 801 803 841 842 844 847 848 850 851 853 856 858
Section 21 Electrical Characteristics ............................................................................. 21.1 Absolute Maximum Ratings ............................................................................................. 21.2 DC Characteristics ............................................................................................................ 21.3 AC Characteristics ............................................................................................................ 21.3.1 Clock Timing ....................................................................................................... 21.3.2 Control Signal Timing ......................................................................................... 21.3.3 Bus Timing .......................................................................................................... 21.3.4 Direct Memory Access Controller Timing .......................................................... 21.3.5 Free-Running Timer Timing................................................................................ 21.3.6 Serial Communication Interface Timing.............................................................. 21.3.7 Watchdog Timer Timing ..................................................................................... 21.3.8 Serial I/O Timing................................................................................................. 21.3.9 High-Performance User Debugging Interface Timing......................................... 21.3.10 I/O Port Timing.................................................................................................... 21.3.11 Ethernet Controller Timing.................................................................................. 21.3.12 STATS, , and Signal Timing........................................................... 21.4 AC Characteristic Test Conditions ...................................................................................
A.1
ZiHSUB HB
Appendix A On-Chip Peripheral Module Registers .................................................. 859
Addresses.......................................................................................................................... 859
Appendix B Pin States ....................................................................................................... 877
B.1 Pin States in Reset, Power-Down State, and Bus-Released State ..................................... 877
Appendix C Product Lineup ............................................................................................. 881 Appendix D Package Dimensions .................................................................................. 882
Rev. 2.00, 03/05, page xxxviii of xxxviii
Section 1 Overview
1.1 Features of SuperH Microcomputer with On-Chip Ethernet Controller
The SH7615 is a CMOS single-chip microcomputer that integrates a high-speed CPU core using an original Renesas Technology architecture with supporting functions required for an Ethernet system. The CPU has a RISC (Reduced Instruction Set Computer) type instruction set. The CPU basically operates at a rate of one instruction per cycle, offering a great improvement in instruction execution speed. In addition, the 32-bit internal architecture provides improved data processing power, and DSP functions have also been enhanced with the implementation of extended Harvard architecture DSP data bus functions. With this CPU, it has become possible to assemble low-cost, high-performance/high-functionality systems even for applications such as realtime control, which could not previously be handled by microcomputers because of their high-speed processing requirements. The SH7615 also includes a maximum 4-kbyte cache, for greater CPU processing power when accessing external memory. The SH7615 is equipped with a media access controller (MAC) conforming to the IEEE802.3u standard, and an Ethernet controller that includes a media independent interface (MII) standard unit, enabling 10/100 Mbps LAN connection. Supporting functions necessary for system configuration are also provided, including RAM, timers, a serial communication interface with FIFO (SCIF), interrupt controller (INTC), and I/O ports.
Rev. 2.00, 03/05, page 1 of 884
Table 1.1
Item CPU
Features
Specifications • • • Original Renesas Technology architecture 32-bit internal architecture General register machine Sixteen 32-bit general registers Six 32-bit control registers (including 3 added for DSP use) Ten 32-bit system registers • RISC (Reduced Instruction Set Computer) type instruction set Fixed 16-bit instruction length for improved code efficiency Load-store architecture (basic operations are executed between registers) Delayed branch instructions reduce pipeline disruption during branches C-oriented instruction set • • • Instruction execution time: One instruction per cycle (16.0 ns/instruction at 62.5 MHz operation) Address space: Architecture supports 4 Gbytes On-chip multiplier: Multiply operations (32 bits × 32 bits → 64 bits) and multiply-and-accumulate operations (32 bits × 32 bits + 64 bits → 64 bits) executed in two to four cycles Five-stage pipeline
•
Rev. 2.00, 03/05, page 2 of 884
Item DSP
Specifications • DSP engine Multiplier Arithmetic logic unit (ALU) Shifter DSP registers • Multiplier 16 bits × 16 bits → 32 bits Single-cycle multiplier • DSP registers Two 40-bit data registers Six 32-bit data registers Modulo register (MOD, 32 bits) added to control registers Repeat counter (RC) added to status register (SR) Repeat start register (RS, 32 bits) and repeat end register (RE, 32 bits) added to control registers • DSP data bus Extended Harvard architecture Simultaneous access to two data buses and one instruction bus • Parallel processing Maximum of four parallel processes ALU operations, multiplication, and two loads or stores • Address processors Two address processors Address operations to access two memories • DSP data addressing modes Increment and index Each with or without modulo addressing • • Repeat control: Zero-overhead repeat (loop) control Instruction set 16-bit length (in case of load or store only) 32-bit length (including ALU operations and multiplication) Added SuperH microcomputer instructions for accessing DSP registers • Fifth and last pipeline stage is DSP stage
Rev. 2.00, 03/05, page 3 of 884
Item Cache
Specifications • • • • • • • • • • • Mixed instruction/data type cache Maximum of 4 kbytes 4-way set-associative type 16-byte line length 64 cache tag entries 16-byte write-back buffer Selection of write-through or write-back mode for data writes LRU replacement algorithm Can also be used as 2-kbyte cache and 2-kbyte RAM (2-way cache mode) Mixed instruction/data cache, instruction cache, or data cache mode can be set 1-cycle reads, 2-cycle writes (in write-back mode) 16 priority levels can be set On-chip supporting module interrupt vector numbers can be set 41 internal interrupt sources The E-DMAC interrupt (EINT) is input to the INTC as the OR of 22 EtherC and E-DMAC interrupt sources (max.). Thus, from the viewpoint of the INTC, there is one EtherC/E-DMAC interrupt source. 15 external interrupt sources (encoded input) can also be selected for pins to (IRL interrupts) • • IRL interrupt vector number setting can also be selected (selection of auto vector or external vector) Provision for IRQ interrupt setting (low-level, rising-edge, falling-edge, both-edge detection)
3LRI 0LRI 3LRI 0LRI
Interrupt controller (INTC)
• • • •
•
Five external interrupt pins (NMI,
to
)
Rev. 2.00, 03/05, page 4 of 884
Item User break controller (UBC), 4 channels (A, B, C, D)
Specifications • Interrupt generation based on independent or sequential conditions for channels A, B, C, D Three sequential setting patterns: A → B → C → D, B → C → D, C→D • Settable break conditions: Address, data (channels C and D only), bus master (CPU/DMAC), bus cycle (instruction fetch/data access), read/write, operand cycle (byte/word/longword) User break interrupt generated on occurrence of break condition Processing can be stopped before or after instruction execution in instruction fetch cycle Break with specification of number of executions (channels C and D only) Settable number of executions: max. 2 • PC trace function Branch source/branch destination can be traced in branch instruction fetch (max. 8 addresses (4 pairs))
12
• • •
– 1 (4095)
Rev. 2.00, 03/05, page 5 of 884
Item
Specifications Address space divided into five areas (CS0 to CS4, max. linear 32 Mbytes each) Memory types such as DRAM, synchronous DRAM, burst ROM, can be specified for each area Two synchronous DRAM spaces (CS2, CS3); CS3 also supports DRAM Bus width (8, 16, 32 bits) can be selected for each area W ait state insertion control for each area Control signal output for each area Endian can be set for CS2 and CS4 • Cache Cache area/cache-through area selection by access address Selection of write-through or write-back mode • Refresh functions CAS-before-RAS refreshing (auto refreshing) or self-refreshing Refresh interval settable by means of refresh counter and clock select setting Concentrated refreshing according to refresh count setting (1, 2, 4, 6, 8) Refresh request output possible (REFOUT) • Direct DRAM interface Multiplexed row address/column address output Fast page mode burst transfer and continuous access when reading EDO mode TP cycle generation to secure RAS precharge time • Direct synchronous DRAM interface Multiplexed row address/column address output Bank-active mode (valid for CS3 only) Selection of burst read/single write mode or burst read/burst write mode • Refresh counter can be used as interval timer Interrupt request generated on compare match (CMI interrupt request signal)
RGB SLRB
Bus state controller • (BSC)
•
Bus arbitration (
,
)
Rev. 2.00, 03/05, page 6 of 884
Item Direct memory access controller (DMAC), 2 channels
Specifications • • • • 4-Gbyte address space, maximum 16M (16,777,216) transfers Selection of 8-bit, 16-bit, 32-bit, or 16-byte transfer data length Parallel execution of CPU instruction processing and DMA operation possible in case of cache hit Selection of dual address or single address mode Single address (data transfer rate of one transfer unit in one bus cycle) Dual address (data transfer rate of one transfer unit in two bus cycles) W hen synchronous DRAM is connected, 16-byte continuous read → continuous write transfer is available (dual) W hen synchronous DRAM is connected, single-address transfer is available in a single clock cycle at maximum 31.25 MHz • • • Cycle stealing or burst transfer Relative channel priorities can be set (fixed mode/round robin mode) DMA transfer is possible for the following devices: External memory, on-chip memory, on-chip supporting modules (excluding DMAC, BSC, UBC, cache, E-DMAC, EtherC) • • • External requests, DMA transfer requests from on-chip supporting modules, auto requests Interrupt request (DEIn) can be issued to CPU at end of data transfer DACK used for DREQ sampling (however, there is always one overrun as there is one acceptance before first DACK) 4-kbyte X-RAM 4-kbyte Y-RAM Transfer possible between EtherC and external memory/on-chip memory 16-byte burst transfer possible Single address transfer Chain block transfer 32-bit transfer data width 4-Gbyte address space
On-chip RAM Ethernet controller direct memory access controller (E-DMAC), 2 channels
• • • • • • • •
Rev. 2.00, 03/05, page 7 of 884
Item Ethernet controller (EtherC)
Specifications • MAC (Media Access Control) functions Data frame assembly/disassembly (IEEE802.3-compliant frames) CSMA/CD link management (collision avoidance, processing in case of collision) CRC processing Built-in FIFOs (512 bytes each for transmission and reception) Supports full-duplex transmission/reception Transmitting and receiving short and long packets • Compatible with MII (Media Independent Interface) standard Converts 8-bit stream data from MAC level to MII nibble stream (4 bits) Station management (STA) functions 18 TTL-level signals • Variable transfer rate: 10/100 Mbps Magic Packet™* (with WOL (Wake On LAN) output) Asynchronous mode Data length: 7 or 8 bits Stop bit length: 1 or 2 Parity: Even, odd, or none Receive error detection: Parity errors, framing errors, overrun errors Break detection • Synchronous mode One serial communication format (8-bit data length) Receive error detection: Overrun errors • • • • • IrDA mode (conforming to IrDA 1.0) Simultaneous transmission/reception (full-duplex) capability Half-duplex communication used for IrDA communication Built-in dedicated baud rate generator allows selection of bit rate Built-in 16-stage transmit and receive FIFOs enable high-speed, continuous communication Internal or external (SCK) transmit/receive clock source
Serial communication interface with FIFO (SCIF), 2 channels
•
Note:
*
Magic Packet is a registered trademark of Advanced Micro Devices, Inc.
Rev. 2.00, 03/05, page 8 of 884
Item Serial communication interface with FIFO (SCIF), 2 channels
Specifications • Four interrupt sources Transmit FIFO data empty Break Receive FIFO data full Receive error • • Detection of transmit and receive FIFO register data quantity and number of receive FIFO register transmit data errors Timeout error (DR) can be detected during reception Full-duplex operation (independent transmit and receive registers, and independent transmit and receive clocks) Transmit/receive ports with double-buffer structure (enabling continuous transmission/reception) Interval transfer mode and continuous transfer mode Choice of 8- or 16-bit data length Data transfer communication by means of polling or interrupts MSB-first transfer between SIO and data I/O Conforms to IEEE1149.1 standard TAP controller Instruction register Data register Bypass register • Test mode that conforms to the IEEE1149.1 standard Standard instructions: BYPASS, SAMPLE/PRELOAD, and EXTEST Optional instructions: CLAMP, HIGHZ, and IDCODE • • H-UDI interrupt H-UDI interrupt request to INTC Reset hold
TSRT STC STR
•
Built-in modem control functions (
,
)
Serial I/O (SIO), 3 channels
• • • • • •
High-performance user debugging interface (H-UDI)
•
Five test signals (TCK, TDI, TDO, TMS,
)
Rev. 2.00, 03/05, page 9 of 884
Item Timer pulse unit (TPU), 3 channels
Specifications • • Maximum 8-pulse input/output Total of eight timer general registers (TGR) (four for channel 0, two each for channels 1 and 2) W aveform output by compare match: Selection of 0, 1, or toggle output Input capture function: Selection of rising-edge, falling-edge, or bothedge detection Counter clear operation: Counter clearing possible by compare match or input capture Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously; simultaneous clearing by compare match and input capture possible; simultaneous register input/output possible by counter synchronous operation PWM mode: Any PWM output duty can be set; maximum 7-phase PWM output possible by combination with synchronous operation • Buffer operation settable for channel 0 Input capture register double-buffering possible Automatic rewriting of output compare register possible • • Phase counting mode settable independently for channels 1 and 2 Two-phase encoder pulse up/down-count possible 13 interrupt sources For channel 0, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently For channels 1 and 2, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently
Rev. 2.00, 03/05, page 10 of 884
Item 16-bit free-running timer (FRT), 1 channel
Specifications • Choice of four counter input clocks Three internal clocks (Pφ/8, Pφ/32, Pφ/128) External clock (enabling external event counting) • • • • Two independent comparators (allowing generation of two waveform outputs) Input capture (choice of rising edge or falling edge) Counter clear specification Counter value can be cleared by compare match A Four interrupt sources Two compare match sources (OCIA, OCIB) One input capture source (ICI) One overflow source (OVI)
Watchdog timer (WDT), 1 channel
• • • •
Can be switched between watchdog timer mode and interval timer mode
FVOTDW
Internal reset, external signal ( overflow
), or interrupt generated on count
Used when standby mode is cleared or the clock frequency is changed, and in clock pause mode Selection of eight counter input clocks Built-in clock pulse generator Selection of crystal or external clock as clock source Built-in clock-multiplication PLL circuits Built-in PLL circuit for phase synchronization between external clock and internal clock CPU/DSP core clock (Iφ), peripheral module clock (Pφ), and external interface clock (Eφ) frequencies can be scaled independently
Clock pulse generator (CPG)
• • • • •
Rev. 2.00, 03/05, page 11 of 884
Item System controller (SYSC)
Specifications • • Selection of seven operating mode settings, three power-down modes Operating modes Control the method of clock generation (PLL ON/OFF) and clock division ratio • Power-down mode Sleep mode: CPU functions halted Standby mode: All functions halted Module standby function: Operation of FRT, SCIF, DMAC, UBC, DSP, TPU, and SIO on-chip supporting modules is halted selectively
I/O ports
•
29 input/output ports
Rev. 2.00, 03/05, page 12 of 884
1.2
Block Diagram
16-bit internal X data bus
CPU
Interrupt controller DSP Highperformance user debugging interface Serial I/O Y-RAM
X-RAM
16-bit internal Y data bus
32-bit cache data bus
Internal X address bus
Internal Y address bus
Cache address bus
Serial communication interface with FIFO
Timer pulse unit
Cache address array/data array
Cache controller User break controller
Free-running timer Watchdog timer Clock pulse generator
Bus state controller Direct memory access controller Ethernet controller Ethernet controller direct memory access controller
System controller
16-bit peripheral data bus
External bus interface
32-bit internal data bus
Figure 1.1 Block Diagram of SH7615
Rev. 2.00, 03/05, page 13 of 884
Peripheral address bus
I/O ports
Internal address bus
1.3
1.3.1
Pin Description
Pin Arrangement
Figure 1.2 shows the pin arrangement of the HD6417615ARF and HD6417615ARFV, and figure 1.3 shows the pin arrangement of the HD6417615ARBP and HD6417615ARBPV.
PB11/SRS2/CTS/STATS0 PVCC PB12/SRCK2/RTS/STATS1 PB13/TXD1 PB14/RXD1 PB15/SCK1 VSS VSS BGR VCC VCC BRLS DACK0 DACK1 DREQ0 DREQ1 BH BUSHiZ CS4 CS3 CS2 CS1 CS0 RD/WR VCC BS VSS REFOUT RD CKE CAS0 CAS1 CAS2 CAS3 DQMLL/WE0 DQMLU/WE1 DQMUL/WE2 DQMUU/WE3 CAS/OE RAS VCC WAIT VSS VSS VSS A24 VCC VCC A23 A22 A21 A20 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
PVSS PB10/SRXD2/TIOCA1 PB9/STCK2/TIOCB1/TCLKC PB8/STS2/TIOCA2 PB7/STXD2/TIOCB2/TCLKD PB6/SRCK1/SCK2 PB5/SRS1/RXD2 PB4/SRXD1/TXD2 PB3/STCK1/TIOCA0 PB2/STS1/TIOCB0 PVCC PB1/STXD1/TIOCC0/TCLKA PVSS PB0/TIOCD0/TCLKB/WOL PA13/SRCK0 PA12/SRS0 PA11/SRXD0 PA10/STCK0 PA9/STS0 PA8/STXD0 PA7/WDTOVF PA6/FTCI PVCC PA5/FTI PVSS PA4/FTOA CKPO/FTOB PA2/LNKSTA PA1/EXOUT PA0 RX-ER RX-DV COL CRS PVSS RX-CLK PVCC ERXD0 ERXD1 ERXD2 ERXD3 MDIO MDC PVCC TX-CLK PVSS TX-EN ETXD0 ETXD1 ETXD2 ETXD3 TX-ER
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
FP-208C, FP-208CV (Top view)
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
A19 A18 A17 VSS A16 VCC A15 A14 A13 A12 A11 A10 A9 VSS A8 VCC A7 A6 A5 A4 A3 A2 A1 VCC A0 VSS VSS D31 VCC D30 D29 D28 D27 D26 D25 VSS D24 VCC VCC D23 D22 D21 D20 VSS VSS D19 VCC D18 D17 D16 D15 D14
Note: * When doing debugging using the E10A emulator, this pin is used for mode switching. It should be connected to Vss when using the E10A emulator and connected to Vcc when using a normal user system.
Figure 1.2 HD6417615ARF and HD6417615ARFV Pin Arrangement (FP-208C, FP-208CV)
Rev. 2.00, 03/05, page 14 of 884
IRL3 IRL2 IRL1 IRL0 NMI ASEMODE* VSS RES PLLVSS PLLCAP2 PLLCAP1 PLLVCC MD4 MD3 MD2 MD1 MD0 VCC EXTAL VSS XTAL VCC CKIO CKPREQ/CKM CKPACK VSS IVECF TDO TDI TCK TMS TRST VCC D0 VSS D1 D2 D3 D4 D5 D6 VCC D7 D8 VSS D9 D10 D11 D12 VCC D13 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Body size Height Pin pitch
28 × 28 (mm) 1.7 (mm) 0.5 (mm)
X' 1 Y A NC ETXD3 ETXD1 TX-EN TX-CLK MDC ERXD1 RX-CLK RX-DV PA1/ EXOUT PVCC PA9/STS0 PA12/ SRS0 PB1/ STXD1/ TIOCC0/ TCLKA PVSS PB6/ SRCK1/ SCK2 PB10/ SRXD2/ TIOCA1 PB8/ STS2/ TIOCA2 PB3/ STCK1/ TIOCA0 PB5/ SRS1/ RXD2 PB7/ STXD2/ TIOCB2/ TCLKD 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PB9/ STCK2/ TIOCB1/ TCLKC PVSS
X 19 NC A
B ETXD2 TX-ER ETXD0 MDIO ERXD0 PVSS RX-ER CKPO/ FTOB PA5/FTI PA8/ STXD0 PA11/ SRXD0
IRL1
IRL3
PVCC PB13/ TXD1
B
C NMI NC PVSS PVCC ERXD3 PVCC CRS PA0 PA2/ LNKSTA PVCC
IRL0
PA4/FTOA WDTOVF/ PA10/ PA7 STCK0
PB0/ TIOCD0/ TCLKB/ WOL PA13/ SRCK0 NC NC
PB4/ SRXD1/ TXD2
PB2/ STS1/ TIOCB0
C PB15/ SCK1 NC
D Vss NC NC ERXD2 NC COL NC NC PVSS PA6/FTCI NC
IRL2
RES
PB12/ SRCK2/ RTS/ STATS1 PB11/ SRS2/ CTS/ STATS0 NC VSS PB14/ RXD1
D
E PLLVSS ASEMODE NC NC
VSS
E
F PLLCAP2 PLLCAP1 NC PLLVCC
NC
VCC
VCC
BGR
F
G MD4 MD3 MD2 MD1
DREQ0
DACK1
DACK0
BRLS
G
H MD0 VCC EXTAL VSS
CS4
BUSHiZ
BH
DREQ1
H
J XTAL VCC NC NC
CS1
CS0
CS2
CS3
J
K VSS CKIO
CKPREQ/ CKM
CKPACK
BP-240A, BP-240AV Bump No. (Top View)
NC
VCC
BS
RD/WR
K
L TCK TDI TDO
IVECF
REFOUT
VSS
RD
CKE
L
M D0 VCC TMS
TRST
CAS0
CAS1
CAS2
CAS3
M
N D3 D2 D1 VSS
DQMLL/ WE0 NC
DQMLU/ WE1 NC
DQMUL/ WE2 CAS/OE
DQMUU/ WE3 RAS
N
P VCC D6 D5 D4
P
R D8 D10 D7 NC
VCC
WAIT
VCC
VSS
R
T D9 D13 VSS NC NC
VCC
NC
D29
NC
A0
NC
A4
NC
A9
NC
NC
VSS
A21
A24
T
Figure 1.3 HD6417615ARBP and HD6417615ARBPV Pin Arrangement (BP-240A, BP-240AV)
U D11 D12 D20 VSS D21 VCC D25 D28 D31 VSS A1 A5 VCC A10 A13 A15 V VCC D14 D17 D15 VCC D23 VSS D27 VCC VSS A2 A6 A8 A11 A16 A19 W VSS D16 D18 Y' D19 VSS D22 D24 D26 D30 VCC A3 A7 VSS A12 A14 VCC
VSS
A23
VCC
U
A17
A20
A22
V
Rev. 2.00, 03/05, page 15 of 884
VSS
A18
NC
W
1.3.2 Table 1.2
Type Power
Pin Functions Pin Functions
Symbol VCC I/O Input Name Power Function For connection to the power supply. Connect all VCC pins to the system power supply. The chip will not operate if there are any open pins For connection to ground. Connect all VSS pins to the system ground. The chip will not operate if there are any open pins Power supply for the I/O circuits Ground for the I/O circuits For connection to a crystal resonator For connection to a crystal resonator, or used as external clock input pin Used as the external clock input or internal clock output pin Used as the clock pause request pin for changing the frequency of the clock input from the CKIO pin, or halting the clock Indicates that the chip is in the clock pause state (standby state) internally Outputs the on-chip peripheral clock (Pφ)
VSS
Input
Ground
PVCC PVSS Clock XTAL EXTAL CKIO
Input Input Output Input I/O
I/O circuit power I/O circuit ground Crystal input/ output pin System clock input/output pin Clock pause request input Clock pause acknowledge signal On-chip peripheral clock (Pφ) output
/
Input
Rev. 2.00, 03/05, page 16 of 884
QERPKC
CKM
Output
K CAPKC
CKPO
Output
PLLCAP1 PLLCAP2 PLLVCC PLLVSS
Input Input Input Input
PLL capacitance Connects capacitance for operation of connection pins PLL circuit 1 Connects capacitance for operation of PLL circuit 2 PLL power PLL ground PLL oscillator power supply PLL oscillator ground
Type System control
Symbol
SER
I/O Input
Name Reset
Function When = 0 and NMI = 1, the chip enters the power-on reset state. When = 0 and NMI = 0, the chip enters the manual reset state Counter overflow signal output in watchdog timer mode Indicates that the bus has been released to an external device. The device that output the signal recognizes that the bus has been acquired when it receives the signal Driven low when an external device requests release of the bus The operating mode is specified by the levels at these pins Inputs the nonmaskable interrupt request signal These pins input maskable interrupt request signals
RGB SLRB SER SER
Output Output
Watchdog timer overflow Bus grant
Operating mode Interrupts
NMI
0LRI
0SC
TIAW
SAR
4SC
DR
SB
Bus control
FVOTDW FCEVI SLRB RGB
Input
Bus release Mode setting Nonmaskable interrupt External interrupt request input 0 to 3 Interrupt vector fetch cycle Bus cycle start Chip select 0 to 4 Wait Read Row address strobe
MD0 to MD4 Input Input to Input
3LRI
Output
Indicates an external vector read cycle
Output
Signal indicating the start of a bus cycle Asserted every data cycle in burst transfer Chip select signals indicating the area being accessed Wait state request signal Strobe signal indicating a read cycle DRAM/synchronous DRAM RAS signal
to
Output Input Output Output
Rev. 2.00, 03/05, page 17 of 884
Type Bus control
Symbol
SAC ZiHSUB
I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Input
Name Column address strobe Output enable Highest byte access Second byte access Third byte access Lowest byte access Column address strobe 3 Column address strobe 2 Column address strobe 1 Column address strobe 0 Clock enable Refresh out Read/write Bus high impedance
Function Synchronous DRAM CAS signal EDO DRAM output enable signal Used in access in RAS down mode SRAM/synchronous DRAM highest byte select signal SRAM/synchronous DRAM second byte select signal SRAM/synchronous DRAM third byte select signal SRAM/synchronous DRAM lowest byte select signal DRAM highest byte select signal DRAM second byte select signal DRAM third byte select signal DRAM lowest byte select signal Synchronous DRAM clock enable signal Signal requesting refresh execution when the bus is released DRAM/synchronous DRAM write signal Signal used in combination with WAIT signal to place bus and strobe signals in the high-impedance (HiZ) state without ending the bus cycle Asserted at the start of a DMA burst, negated one bus cycle before the end of the burst CPU, DMAC, and E-DMAC status information
STATS0, STATS1
Rev. 2.00, 03/05, page 18 of 884
RW
3SAC
2SAC
1SAC
0SAC
3EW
2EW
1EW
0EW
EO
DQMUU/ DQMUL/ DQMLU/ DQMLL/
CKE REFOUT RD/
Output
Burst hint
HB
Output
Status
Type Bus control H-UDI
Symbol A24 to A0 D31 to D0 TCK TMS TDI TDO
TSRT
I/O Output I/O Input Input Input Output
Name Address bus Data bus Test clock Test mode select Test data input Test data output Test reset ASE mode input Transmitter clock Receive clock Transmit enable Transmit data 0 to 3 Transmit error Receive data enable Receive data 0 to 3 Receive error Carrier sense Collision Management data clock
Function Address output Data input/output Test clock input Test mode select input signal Serial data input Serial data output Test reset input signal ASE mode/user mode select signal TX-EN, ETXD0 to ETXD3, TX-ER timing reference signal RX-DV, ERXD0 to ERXD3, RX-ER timing reference signal Signal indicating that transmit data on ETXD0 to ETXD3 is ready 4-bit transmit data Signal sending error status to another port Indicates that enable receive data on ERXD0 to ERXD3 exist 4-bit receive data Reports error state that occurred during transfer of frame data Carrier detection notification signal Collision detection signal Reference clock signal for information transfer by MDIO
Input ASEMODE*1 Input Ethernet controller (EtherC) TX-CLK RX-CLK TX-EN ETXD0 to ETXD3 TX-ER RX-DV ERXD0 to ERXD3 RX-ER CRS COL MDC MDIO Input Input Output Output Output Input Input Input Input Input Output I/O
Management Bidirectional signal for exchanging data input/output management information between STA and PHY
Rev. 2.00, 03/05, page 19 of 884
Type Ethernet controller (EtherC)
Symbol LNKSTA EXOUT WOL
I/O Input Output Output Output
Name Link status
Function Link status input from PHY
General-purpose General-purpose external output pin external output Wake on LAN DMAC channel 0, 1 acknowledge DMAC channel 0, 1 request Transmit data output channel 1, 2 Receive data input channel 1, 2 Serial clock input/output channel 1, 2 Transmit request Transmit enable TPU timer clock input A, B, C, D Signal indicating detection of a Magic Packet These pins output receiving a DMA transfer request to an external device Pins that input DMA transfer requests from an external device SCIF channel 1 and 2 transmit data output pins SCIF channel 1 and 2 receive data input pins SCIF clock input/output pins
Direct memory access controller (DMAC)
DACK0, DACK1 DREQ0, DREQ1
Input
Serial TXD1, TXD2 Output communication interface with RXD1, RXD2 Input FIFO (SCIF) SCK1, SCK2 I/O
Output Input Input
SCIF channel 1 transmit request output pin SCIF channel 1 transmit enable input pin Pins that input an external clock to the TPU counter
Timer pulse unit (TPU)
Rev. 2.00, 03/05, page 20 of 884
STR STC
TCLKA TCLKB TCLKC TCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1
I/O
TPU input capture/output compare (channel 0) TPU input capture/output compare (channel 1)
Channel 0 input capture input/ output compare output/PWM output pins
I/O
Channel 1 input capture input/ output compare output/PWM output pins
Type Timer pulse unit (TPU)
Symbol TIOCA2 TIOCB2
I/O I/O
Name TPU input capture/output compare (channel 2) Counter clock input Output compare A output Output compare B output Input capture input Serial receive data input 0 to 2
Function Channel 2 input capture input/output compare output/PWM output pins
16-bit free-running timer (FRT)
FTCI FTOA FTOB FTI
Input Output Output Input Input Input Input
FRC counter clock input pin Output compare A output pin Output compare B output pin Input capture input pin Serial receive data input ports
Serial I/O (SIO)
SRXD0 to SRXD2 SRCK0 to SRCK2 SRS0 to SRS2 STXD0 to STXD2 STCK0 to STCK2 STS0 to STS2
Serial receive Serial receive clock ports clock input 0 to 2 Serial receive synchronization input 0 to 2 Serial transmit data 0 to 2 Serial receive synchronization input ports
Output Input I/O
Serial data output ports
Serial transmit Serial transmit clock ports clock input 0 to 2 Serial transmit Serial transmit synchronization synchronization input/output ports input/output 0 to 2 General port General port General input/output port pins Input or output can be specified bit by bit General input/output port pins Input or output can be specified bit by bit
I/O ports
PA0 to PA13*2
I/O
PB0 to PB15 I/O
Notes: 1. When carrying out debugging using the E10A emulator, this pin is used for mode switching. It should be connected to VSS when using the E10A emulator and connected to VCC when using a normal user system. When a boundary scan test is performed with the H-UDI, user mode must be used. A boundary scan test cannot be performed in ASE mode. 2. PA3 cannot be used; CKPO is valid instead.
Rev. 2.00, 03/05, page 21 of 884
1.3.3 Table 1.3
Pin Multiplexing Pin Multiplexing (1)
BPFP240A/ 208C/ AV CV Function 1 F4 E1 F2 F1 H3 J1 K2 K3 K4 D3 G1 G2 G3 G4 H1 C1 B2 D2 B1 C2 L3 12 9 11 10 19 21 23 24 25 8 13 14 15 16 17 5 1 2 3 4 27 PLLVCC PLLVSS PLLCAP1 PLLCAP2 EXTAL XTAL CKIO /CKM
QERPKC
Function 2
Function 3
Function 4
Type Clocks
9 pins System control
MD0 NMI
3LRI
Rev. 2.00, 03/05, page 22 of 884
K CAPKC FCEVI 2LRI 1LRI 0LRI SER
MD4 MD3 MD2 MD1
6 pins Interrupts
6 pins
BPFP240A/ 208C/ Function 1 AV CV
SB
Function 2
Function 3
Function 4
Type Bus control
K18 H16 J19 J18 J16 J17 F19 G19 R17 L18 P19 P18 N19 N18 N17 N16 M19 M18 M17 M16 L19 L16 K19 H17 H18
131 138 137 136 135 134 148 145 115 128 117 118 119 120 121 122 123 124 125 126 127 129 133 139 140
CKE REFOUT
RW
RD/
0EW
DQMLL/
3SAC
1EW
DQMLU/
2EW
DQMUL/
3EW
EO SAC
ZiHSUB
SLRB
2SAC
1SAC
0SAC
TIAW
RGB
SAR
4SC 3SC 2SC 1SC 0SC DR
/
DQMUU/
25 pins
HB
Rev. 2.00, 03/05, page 23 of 884
BPFP240A/ 208C/ Function 1 AV CV T19 U18 V19 T18 V18 V16 W18 V17 V15 U16 W15 U15 W14 V14 U14 T14 V13 W12 V12 U12 T12 W11 V11 U11 T10 111 108 107 106 105 104 103 102 100 98 97 96 95 94 93 92 90 88 87 86 85 84 83 82 80 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function 2
Function 3
Function 4
Type Address bus
25 pins
Rev. 2.00, 03/05, page 24 of 884
BPFP240A/ 208C/ Function 1 AV CV U9 W9 T8 U8 V8 W8 U7 W7 V6 W6 U5 U3 W4 W3 V3 W2 V4 V2 T2 U2 U1 R2 T1 R1 R3 P2 P3 P4 N1 N2 N3 M1 77 75 74 73 72 71 70 68 65 64 63 62 59 57 56 55 54 53 51 49 48 47 46 44 43 41 40 39 38 37 36 34 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function 2
Function 3
Function 4
Type Data bus
32 pins
Rev. 2.00, 03/05, page 25 of 884
BPFP240A/ 208C/ Function 1 AV CV L1 M4 L2 L4 M3 E2 A5 A8 A4 A2 B3 A3 B5 B4 A9 C6 D6 A7 B7 B9 C8 D8 A6 B6 G17 G18 H19 G16 Note: 30 31 29 28 32 6 201 192 203 207 206 205 204 208 188 197 196 195 194 187 190 189 199 198 143 144 141 142 * TCK TMS TDI TDO
TSRT
Function 2
Function 3
Function 4
Type H-UDI
ASEMODE* TX-CLK RX-CLK TX-EN ETXD3 ETXD2 ETXD1 ETXD0 TX-ER RX-DV ERXD3 ERXD2 ERXD1 ERXD0 RX-ER CRS COL MDC MDIO DACK1 DACK0 DREQ1 DREQ0
6 pins EtherC 5 V I/O compatibility
18 pins DMAC
4 pins
When carrying out debugging using the E10A emulator, this pin is used for mode switching. It should be connected to VSS when using the E10A emulator (ASE mode). When using the chip in the normal user system, and not using the E10A emulator (user mode), connect this pin to VCC. When a boundary scan test is performed with the HUDI, user mode must be used. A boundary scan test cannot be performed in ASE mode.
Rev. 2.00, 03/05, page 26 of 884
Table 1.3
Pin Multiplexing (2)
Function 2 [01]* Function 3 [10]* SCK1 RXD1 TXD1 SRS2 SRXD2 STCK2 STS2 STXD2 SRCK1 SRS1 SRXD1 STCK1 STS1 STXD1 SRCK0 SRS0 SRXD0 STCK0 STS0 STXD0 PA7 FTCI FTI FTOA FTOB LNKSTA EXOUT 14 pins 5 V I/O compatibility
STR
BPFP240A/ 208C/ Function 1 AV CV [00]* D19 E18 C19 C18 D18 B16 A18 B17 A17 B15 A16 C16 A15 C17 A14 C14 D14 A13 B13 C13 A12 B12 C12 D12 B11 C11 B10 C10 A10 C9 151 152 153 154 156 158 159 160 161 162 163 164 165 166 168 170 171 172 173 174 175 176 177 178 180 182 183 184 185 186 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA13 PA12 PA11 PA10 PA9 PA8
FVOTDW
Function 4 [11]*
Type Port B SCIF, SIO, TPU
SRCK2
STATS1 STATS0
5 V I/O compatibility
TIOCA1 TIOCB1/TCLKC TIOCA2 TIOCB2/TCLKD SCK2 RXD2 TXD2 TIOCA0 TIOCB0 TIOCC0/TCLKA TIOCD0/TCLKB WOL 16 pins Port A SIO, FRT
PA6 PA5 PA4 CKPO PA2 PA1 PA0
STC
Rev. 2.00, 03/05, page 27 of 884
Note:
*
Figures in square brackets indicate the settings of the mode bits (MD0, MD1) in the PFC in order to select the multiplex functions in port A [0:13] and port B [0:15]. : In a reset, this pin becomes an output pin. When used for general input/output, attention must be paid to the polarity of this pin.
FVOTDW
1.4
Processing States
State Transitions: The CPU has five processing states: the reset state, exception handling state, bus-released state, program execution state, and power-down state. Figure 1.4 shows the state transitions.
From any state when RES = 0 and NMI = 1 From any state when RES = 0 and NMI = 0 RST = 0, NMI = 0 Power-on reset state RST = 0, NMI = 1 RST = 1, NMI = 1 Interrupt or DMA address error RST = 1, NMI = 0 Reset states Manual reset state
Exception-handling state
NMI interrupt Bus request cleared
Bus request
Exception End of exception handling
Bus-released state
Bus request received
Bus request cleared
CKPREQ = 1*
Program execution state
Bus request received
Bus request cleared SLEEP instruction (SBY = 0) MSTP bit cleared MSTP bit set
SBY bit set and CKPREQ = 0*
SLEEP instruction (SBY = 1)
Sleep mode
Standby mode
Module standby Power-down state Note: * clock pause function
Figure 1.4 Processing State Transitions
Rev. 2.00, 03/05, page 28 of 884
• Reset State In this state, the CPU is reset. The reset state is entered when the pin goes low. The power-on reset state is entered if the NMI pin is high, and the manual reset state is entered if the NMI pin is low. • Exception Handling State The exception handling state is a transient state that occurs when the CPU alters the normal programming flow dues to a reset, interrupt, or other exception handling source. In the case of a reset, the CPU fetches the execution start address as the initial value of the program counter (PC) from the exception vector table, and the initial value of the stack pointer (SP), stores these values, branches to the start address, and begins program execution at that address. In the case of an interrupt, etc., the CPU references the SP and saves the PC and status register (SR) in the stack area. It fetches the start address of the exception service routine from the exception vector table, branches to that address, and begins program execution. Subsequently, the processing state is the program execution state. • Program Execution State In the program execution state the CPU executes program instructions in normal sequence. • Power-Down State In the power-down state the CPU stops operating to conserve power. The power-down state is entered by executing a SLEEP instruction. The power-down state includes two modes—sleep mode and standby mode—and a module standby function. • Bus-Released State 1. In the bus-released state, the CPU releases the bus to a device that has requested it. 2. Bus-released state during manual reset signal assertion While the manual reset signal is being asserted ( = low and NMI = low), no arbitration request ( input) is accepted. If the signal continues to be asserted, this LSI remains in the bus-released state (asserts the signal). When the signal is negated in the bus-released state during manual reset signal assertion, this LSI starts using the bus (negates the signal). Power-Down State: In addition to the normal program execution state, another CPU processing state called the power-down state is provided. In this state, CPU operation is halted and power consumption is reduced. The power-down state includes two modes—sleep mode and standby mode—and a module standby function.
Rev. 2.00, 03/05, page 29 of 884
SER
RGB
SER
RGB SLRB
SLRB
SLRB
• Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the standby bit (SBY) is cleared to 0 in standby control register 1 (SBYCR1). In sleep mode CPU operations stop but data in the CPU’s internal registers and in on-chip cache memory and on-chip RAM is retained. The functions of the on-chip supporting modules do not stop. • Standby Mode A transition to standby mode is made if the SLEEP instruction is executed while SBY is set to 1 in SBYCR1. In standby mode the CPU, the on-chip modules, and the oscillator all stop. When entering standby mode, the DMAC’s DMA master enable bit should be cleared to 0. Also, the cache should be turned off before entering this mode. The contents of the cache and on-chip RAM are not retained in this mode. Standby mode is exited by means of a reset or an external NMI interrupt. When standby mode is exited, the normal program execution state is entered via the exception handling state after the elapse of the oscillation settling time. If a transition is made to standby mode using the clock pause function, it is possible to change the frequency of the CKIO pin input clock, or to stop the clock itself. When SBY in SBYCR1 is set to 1 and a low level is applied to the /CKM pin, a transition is made to standby mode and a low level is output from the pin. The clock can then be stopped, or its frequency changed. On-chip supporting module states and pin states are the same as in the normal standby mode entered by means of the SLEEP instruction. A transition to the program execution state is made by applying a high level to the /CKM pin. In this mode the oscillator is halted, greatly reducing power consumption. • Module Standby Function A module standby function is provided for the following on-chip supporting modules: the direct memory access controller (DMAC), DSP, 16-bit free-running timer (FRT), serial communication interface with FIFO (SCIF), serial I/O (SIO), user break controller (UBC), and timer pulse unit (TPU). A module standby function is not supported for the Ethernet controller (EtherC) or the Ethernet direct memory access controller (E-DMAC). Setting one of module stop bits 11 to 3 and 1 (MSTP11 to MSTP3, MSTP1) to 1 in the standby control register (SBYCR1/2) stops the clock supply to the corresponding on-chip supporting module. Use of this function enables power consumption to be reduced. The module standby function is cleared by clearing the corresponding MSTP bit to 0. DSP instructions must not be used when the DSP has been placed in the module standby state. When using the DMAC module standby function, the direct memory access controller’s DMA master enable bit should be cleared to 0.
Rev. 2.00, 03/05, page 30 of 884
KCAPKC QERPKC
QERPKC
Table 1.4
Power-Down State
State On-chip Supporting Modules Operating On-Chip Cache or On-Chip RAM Held
Mode Sleep mode
Entering Conditions Executing SLEEP instruction while SBY bit is cleared in SBYCR1 Executing SLEEP instruction while SBY bit is set in SBYCR1
Clock Operating
CPU Halted
CPU Registers Held
Exiting Conditions 1. Interrupt 2. DMA address error 3. Power-on reset 4. Manual reset
Standby mode
Halted
Halted
Halted and initialized*1
Held
Undefined
1. NMI interrupt 2. Power-on reset 3. Manual reset
Module standby function
Operating Setting MSTP bit corresponding to individual module
Operating (DSP halted)
Clock supply Held to specified module halted, module initialized*2
Held
1. Clearing MSTP bit 2. Power-on reset 3. Manual reset
Notes: 1. Depends on individual supporting module or pin. 2. DMAC and DSP registers and specified module interrupt vectors retain their set values.
Rev. 2.00, 03/05, page 31 of 884
Rev. 2.00, 03/05, page 32 of 884
Section 2 CPU
2.1 Register Descriptions
The register set consists of sixteen 32-bit general registers, six 32-bit control registers, and ten 32bit system registers. This chip is upwardly compatible with the SH-1 and SH-2 on the object code level. For this reason, several registers have been added to the previous SuperH microcomputer registers. The added registers are the three control registers: repeat start register (RS), repeat end register (RE), and modulo register (MOD), and the six system registers: DSP status register (DSR), and A0, A1, X0, X1, Y0 and Y1 among the DSP data registers. The general registers are used in the same manner as the SH-1 or SH-2 with regard to SuperH microcomputer-type instructions. With regard to DSP type instructions, they are used as address and index registers for accessing memory. 2.1.1 General Registers
There are 16 general registers (Rn) numbered R0 to R15, which are 32 bits in length. General registers are used for data processing and address calculation. With SuperH microcomputer type instructions, R0 is also used as an index register. Several instructions are limited to use of R0 only. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15. With DSP type instructions, eight of the 16 general registers are used for the addressing of X and Y data memory and data memory (single data) using the I bus. R4 and R5 are used as an X address register (Ax) for X memory accesses, and R8 is used as an X index register (Ix). R6 and R7 are used as a Y address register (Ay) for Y memory accesses, and R9 is used as a Y index register (Iy). R2, R3, R4, and R5 are used as a single data address register (As) for accessing single data using the I bus, and R8 is used as a single data index register (Is). DSP type instructions can simultaneously access X and Y data memory. There are two groups of address pointers for designating X and Y data memory addresses. Figure 2.1 shows the general registers.
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31 R0*1 R1 R2, [As]*3 R3, [As]*3 R4, [As, Ax]*3 R5, [As, Ax]*3 R6, [Ay]*3 R7, [Ay]*3 R8, [Ix, Is]*3 R9, [Iy]*3 R10 R11 R12 R13 R14 R15, SP *2 Notes:
0
1. R0 also functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, only the R0 functions as a source register or destination register. 2. R15 functions as a hardware stack pointer (SP) during exception processing. 3. Used as memory address registers, memory index registers with DSP type instructions.
Figure 2.1 General Register Configuration With the assembler, symbol names are used for R2, R3 ... R9. If it is wished to use a name that makes clear the role of a register for DSP type instructions, a different register name (alias) can be used. This is written in the following manner for the assembler.
Ix: .REG (R8)
Rev. 2.00, 03/05, page 34 of 884
The name Ix is an alias for R8. The other aliases are assigned as follows:
Ax0: Ax1: Ix: Ay0: Ay1: Iy: As0: As1: As2: As3: Is: .REG (R4) .REG (R5) .REG (R8) .REG (R6) .REG (R7) .REG (R9) .REG (R4) defined when an alias is required for single data transfer .REG (R5) defined when an alias is required for single data transfer .REG (R2) defined when an alias is required for single data transfer .REG (R3) defined when an alias is required for single data transfer .REG (R8) defined when an alias is required for single data transfer
2.1.2
Control Registers
The six 32-bit control registers consist of the status register (SR), repeat start register (RS), repeat end register (RE), global base register (GBR), vector base register (VBR), and modulo register (MOD). The SR register indicates processing states. The GBR register functions as a base address for the indirect GBR addressing mode, and is used for such as on-chip peripheral module register data transfers. The VBR register functions as the base address of the exception processing vector area (including interrupts). The RS and RE registers are used for program repeat (loop) control. The repeat count is designated in the SR register repeat counter (RC), the repeat start address in the RS register, and the repeat end address in the RE register. However, note that the address values stored in the RS and RE registers are not necessarily always the same as the physical start and end address values of the repeat. The MOD register is used for modulo addressing to buffer the repeat data. The modulo addressing designation is made by DMX or DMY, the modulo end address (ME) is designated in the upper 16 bits of the MOD register, and the modulo start address (MS) is designated in the lower 16 bits. Note that the DMX and DMY bits cannot simultaneously designate modulo addressing. Modulo addressing is possible with X and Y data transfer instructions (MOVX, MOVY). It is not possible with single data transfer instructions (MOVS).
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Figure 2.2 shows the control registers. Table 2.1 indicates the SR register bits.
Status register (SR) 31 28 27 16 15 12 11 10 9 8 7 43 210 0000 RC 0000 DMY DMX M Q I3 I2 I1 I0 RF1 RF0 S T Repeat start register (RS) 31 RS Repeat end register (RE) 31 RE Global base register (GBR) 31 GBR Vector base register (VBR) 31 VBR Modulo register (MOD) 31 ME ME: Modulo end address MS: Modulo start address
0
0
0
0
16 15 MS
0
Figure 2.2 Control Register Configuration
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Table 2.1
Bit 27 to 16 11
SR Register Bits
Name (Abbreviation) Repeat counter (RC) Y pointer usage modulo addressing designation (DMY) X pointer usage modulo addressing designation (DMX) M bit Q bit Function Designate the repeat count (2 to 4095) for repeat (loop) control 1: modulo addressing mode becomes valid for Y memory address pointer, Ay (R6, R7) 1: modulo addressing mode becomes valid for X memory address pointer, Ax (R4, R5) Used by the DIV0S/U, DIV1 instructions Used by the DIV0S/U, DIV1 instructions
10
9 8 7 to 4 3 to 2
Interrupt request mask (I3 Indicate the receive level of an interrupt request (0 to to I0) 15) Repeat flags (RF1, RF0) Used in zero overhead repeat (loop) control. Set as below for an SETRC instruction For 1 step repeat 00 RE — RS = –4 For 2 step repeat 01 RE — RS = –2 For 3 step repeat 11 RE — RS = 0 For 4 steps or more 10 RE — RS > 0
1
Saturation arithmetic bit (S) T bit
Used with MAC instructions and DSP instructions 1: Designates saturation arithmetic (prevents overflows) For MOVT, CMP/cond, TAS, TST, BT, BT/S, BF, BF/S, SETT, CLRT and DT instructions, 0: represents false 1: represents true For ADDV/ADDC, SUBV/SUBC, DIV0U/DIV0S, DIV1, NEGC, SHAR/SHAL, SHLR/SHLL, ROTR/ROTL and ROTCR/ROTCL instructions, 1: represents occurrence of carry, borrow, overflow or underflow
0
31 to 28 15 to 12
0 bit
0: 0 is always read out; write a 0
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There are dedicated load/store instructions for accessing the RS, RE and MOD registers. For example, the RS register is accessed as follows.
LDC LDC.L STC STC.L Rm,RS; @Rm+,RS; RS,Rn; RS,@-Rn; Rm→RS (Rm)→RS,Rm+4→Rm RS→Rn Rn-4→Rn,RS→(Rn)
The following instructions set addresses in the RS, RE registers for zero overhead repeat control:
LDRS LDRE @(disp,PC); @(disp,PC); disp×2 + PC→RS disp×2 + PC→RE
The GBR register and VBR register are the same as the previous SuperH microprocessor registers. An RC counter and four control bits (DMX bit, DMY bit, RF1 bit, RF0 bit) have been added to the SR register. The RS, RE and MOD registers are new registers. 2.1.3 System Registers
System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The MACH and MACL store the results of multiplication or multiply and accumulate operations*. The PR stores the return address from the subroutine procedure. The PC indicates the address of the program in execution; it controls the flow of the processing. The PC indicates the fourth byte after the instruction currently being executed. These registers are the same as those in the SuperH microprocessor. Note: * These are used only when executing an instruction that was supported by SH-1 and SH-2. They are not used for newly added multiplication instructions (PMULS).
31 MACH MACL 0
Multiply and accumulate register high (MACH) Multiply and accumulate register low (MACL)
31 PR
0 Procedure register (PR)
31 PC
0 Program counter (PC)
Figure 2.3 System Register Configuration
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In addition, among the DSP unit usage registers (DSP registers) described in 2.1.4 DSP Registers, the DSP status register (DSR) and the five registers A0, X0, X1, Y0 and Y1 of the eight data registers are treated as system registers. Among these, the A0 is a 40-bit register, but when data is output from the A0 register, the guard bit section (A0G) is disregarded; when data is input to the A0 register, the MSB of the data is copied into the guard bit section (A0G). 2.1.4 DSP Registers
The DSP unit has eight data registers and one control register as its DSP registers. The DSP data registers are comprised of the two 40-bit registers A0 and A1, and the six 32-bit registers M0, M1, X0, X1, Y0 and Y1. The A0 and A1 registers have the 8-bit guard bits A0G and A1G, respectively. The DSP data registers are used for the transfer and processing of the DSP data of DSP instruction operands. There are three types of instructions that access DSP data registers: those for DSP data processing, and those for X or Y data transfer processing. The control register is the 32-bit DSP status register (DSR) that represents operation results. The DSR register has bits that represent operation results, a signed greater than bit (GT), a zero bit (Z), a negative value bit (N), an overflow bit (V), a DSP status bit (DC: DSP condition), and a status selection bit (CS: condition select) for controlling DC bit setting. The DC bit represents one status flag and is very similar to the SuperH microprocessor CPU core T bit. For conditional DSP type instructions, DSP data processing execution is controlled in accordance with the DC bit. This control is related to execution in the DSP unit only, and only DSP registers are updated. It bears no relation to address calculation or such SuperH microprocessor CPU core execution instructions as load/store instructions. The control bits CS (bits 2 to 0) designate the status for setting the DC bit. DSP type instructions are comprised of unconditional DSP type instructions and conditional DSP type instructions. The status and DC bits are updated in unconditional DSP type data processing, with the exception of the PMULS, MOVX, MOVY and MOVS instructions. Conditional DSP type instructions are executed according to the status of the DC bit, but regardless of whether or not they are executed, the DSR register is not updated. Figure 2.4 shows the DSP registers. The DSR register bit functions are shown in table 2.2.
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39 A0G A1G
32 31 A0 A1 M0 M1 X0 X1 Y0 Y1 31 87 6 5 4 321
0 DSP data registers
0 DSP status register (DSR)
GT Z N
V CS[2:0] DC
Figure 2.4 DSP Register Configuration
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Table 2.2
Bit 31 to 8 7
DSR Register Bits
Name (Abbreviation) Reserved Signed greater than bit (GT) Function 0: These bits are always read as 0. The write value should always be 0. Indicates that the operation result is positive (excepting 0), or that operand 1 is greater than operand 2 1: Operation result is positive, or operand 1 is greater Indicates that the operation result is zero (0), or that operand 1 is equal to operand 2 1: Operation result is zero (0), or equivalence Indicates that the operation result is negative, or that operand 1 is smaller than operand 2 1: Operation result is negative, or operand 1 is smaller
6
Zero bit (Z)
5
Negative bit (N)
4 3 to 1
Overflow bit (V)
Indicates that the operation result has overflowed 1: Operation result has overflowed
Status selection bits (CS) Designate the mode for selecting the operation result status set in the DC bit Do not set either 110 or 111 000: Carry/borrow mode 001: Negative value mode 010: Zero mode 011: Overflow mode 100: Signed greater mode 101: Signed above mode
0
DSP status bit (DC)
Sets the status of the operation result in the mode designated by the CS bits 0: Designated mode status not realized (unrealized) 1: Designated mode status realized
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2.1.5
Notes on Guard Bits and Overflow Treatment
DSP unit data operations are fundamentally performed in 32 bits, but these operations are always executed with a 40-bit length including the 8-bit guard section. When the guard bit section does not match the value of the 32-bit section MSB, the operation result is treated as an overflow. In this case, the N bit indicates the correct status of the operation result regardless of the existence or not of an overflow. This is so even if the destination operand is a 32-bit length register. The 8-bit section guard bits are always presupposed and each status flag is updated. When place overflows occur so that the correct result cannot be displayed even when the guard bits are used, the N flag cannot indicate the correct status. 2.1.6 Initial Values of Registers
Table 2.3 lists the values of the registers after reset. Table 2.3 Initial Values of Registers
Register R0 to R14 R15 (SP) Control registers SR RS RE GBR VBR MOD System registers MACH, MACL, PR PC DSP registers Undefined H'00000000 Undefined Undefined Value of the PC in the vector address table Initial Value Undefined Value of the SP in the vector address table Bits I3 to I0 are 1111 (H'F), the reserved bits, RC, DMY, and DMX are 0, and other bits are undefined Undefined
Classification General registers
A0, A0G, A1, A1G, M0, Undefined M1, X0, X1, Y0, Y1 DSR H'00000000
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2.2
2.2.1
Data Formats
Data Format in Registers
Register operand data size is always longword (32 bits). When loading data from memory into a register, if the memory operand is a byte (8 bits) or a word (16 bits), it is sign-extended into a longword, then loaded into the register.
31 Longword 0
Figure 2.5 Register Data Format 2.2.2 Data Formats in Memory
These formats are classified into bytes, words, and longwords. Place byte data in any address, word data from 2n addresses, and longword data from 4n addresses. An address error will occur if accesses are made from any other boundary. In such cases, the access results cannot be guaranteed. In particular, the stack area referred to by the hardware stack pointer (SP, R15) stores the program counter (PC) and status register (SR) as longwords, so establish the hardware stack pointer so that a 4n value will always result. To enable sharing of the processor accessing memory in little-endian mode and memory, the CS2, 4 space (area 2, 4) has a function that allows access in little-endian mode. The order of byte data differs between little-endian mode and normal big-endian mode.
Address m + 1 Address m 31 Byte Address 2n Address 4n Word Longword 23 Byte Address m + 3 Address m + 3 Address m + 1 Address m 7 Byte Word Longword Address 2n Address 4n 0
Address m + 2 15 Byte 7 Byte Word 0 31 Byte
Address m + 2 23 Byte Word 15 Byte
Big endian
Little endian
Figure 2.6 Data Formats in Memory
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2.2.3
Immediate Data Format
Byte immediate data is placed in an instruction code. With the MOV, ADD, and CMP/EQ instructions, immediate data is sign-extended and operated in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. Word or longword immediate data is not located in the instruction code; it should be placed in a memory table. Use an immediate data transfer instruction (MOV) to refer the memory table using the PC relative addressing mode with displacement. 2.2.4 DSP Type Data Formats
This chip has three different types of data format that correspond to various instructions. These are the fixed-point data format, the integer data format, and the logical data format. The DSP type fixed-point data format has a binary point fixed between bits 31 and 30. There are three types: with guard bits, without guard bits, and multiplication input; each with different valid bit lengths and value ranges. The DSP type integer data format has a binary point fixed between bits 16 and 15. There are three types: with guard bits, without guard bits, and shift amount; each with different valid bit lengths and value ranges. The shift amount of the arithmetic shift (PSHA) has a 7-bit range and can express values from –64 to +63, but the actual valid values are from –32 to +32. In the same manner, the shift amount of the logical shift has a 6-bit range, but the actual valid values are from –16 to +16. The DSP type logical data format does not have a decimal point. The data format and valid data length are determined by the instructions and DSP registers. Figure 2.7 shows the three DSP type data formats and binary point positions. The SuperH type data format is also shown for reference.
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DSP fixed decimal point data With guard bits 39 S 32 31 30 0 –28 to +28 – 2–31 31 30 No guard bits 39 Multiplication input S 31 30 S 16 15 0 –1 to +1 – 2–15 0 –1 to +1 – 2–31
DSP integer data 39 With guard bits S 31 No guard bits S 31 Arithmetic shift (PSHA) 31 Logical shift (PSHL) 22 S 21 16 15 S 0 –16 to +16 16 15 0 –32 to +32 16 15 0 –215 to +215 –1 32 31 16 15 0 –223 to +223 –1
39 DSP logical data
31
16 15
0 (16 bits)
31 SuperH integer (word) (Reference) S
0 –231 to +231 –1
S : Sign bit : Binary decimal point : Unrelated to processing (ignored)
Figure 2.7 DSP Type Data Formats
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2.2.5
DSP Type Instructions and Data Formats
The DSP data format and valid data length are determined by DSP type instructions and DSP registers. There are three types of instructions that access DSP data registers, DSP data processing, X, Y data transfer processing, and single data transfer processing instructions. DSP Data Processing: The guard bits (bits 39 to 32) are valid when the A0 and A1 registers are used as source registers in DSP fixed-point data processing. When any registers other than A0, A1 (i.e., M0, M1, X0, X1, Y0, Y1 registers) are used as source registers, the sign-extended part of that register data becomes the bits 39 to 32 data. When the A0 and A1 registers are used as destination registers, the guard bits (bits 39 to 32) are valid. When any registers other than A0, A1 are used as destination registers, bits 39 to 32 of the result data are disregarded. Processing for DSP integer data is the same as the DSP fixed-point data processing. However, the lower word (the lower 16 bits, bits 15 to 0) of the source register is disregarded. The lower word of the destination register is cleared to 0. In DSP logical data processing, the upper word (the upper 16 bits, bits 31 to 16) of the source register is valid. The lower word and the guard bits of the A0, A1 registers are disregarded. The upper word of the destination register is valid. The lower word and the guard bits of the A0, A1 registers are cleared to 0. X, Y Data Transfers: The MOVX.W and MOVY.W instructions access X, Y memory via the 16-bit X, Y data buses. The data loaded into registers and data stored from registers is always the upper word (the upper 16 bits, bits 31 to 16). When loading, the MOVX.W instruction loads X memory, with the X0 and X1 registers as the destination registers. The MOVY.W instruction loads Y memory, with the Y0 and Y1 registers as the destination registers. Data is stored in the upper word of the register; the lower word is cleared to 0. The upper word data of the A0, A1 registers can be stored in X or Y memory with these data transfer instructions, but storing is not possible from any other registers. The guard bits and the lower word of the A0, A1 registers are disregarded. Single Data Transfers: The MOVS.W and MOVS.L instructions can access any memory via the data bus (CDB). All DSP registers are connected to the CDB bus, and they can become source or destination registers during data transfers. The two data transfer modes are word and longword. In word mode, data is loaded to and stored in the upper word of the DSP register, with the exception of the A0G, A1G registers. In longword mode, data is loaded to and stored in the 32 bits of the DSP register, with the exception of the A0G, A1G registers. The A0G, A1G registers can be treated as independent registers during single data transfers. The load/store data length for the A0G, A1G registers is 8 bits.
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If DSP registers are used as source registers in word mode, when data is stored from any registers other than A0G, A1G, the data in the upper word of the register is transferred. In the case of the A0, A1 registers, the guard bits are disregarded. When the A0G, A1G registers are the source registers in word mode, only 8 bits of the data are stored from the registers; the upper bits are signextended. If the DSP registers are used as destination registers in word mode, the load is to the upper word of the register, with the exception of A0G, A1G. When data is loaded to any register other than A0G, A1G, the lower word of the register is cleared to 0. In the case of the A0, A1 registers, the data sign is extended and stored in the guard bits; the lower word is cleared to 0. When the A0G, A1G registers are the destination registers in word mode, the least significant 8 bits of the data are loaded into the registers; the A0, A1 registers are not zero cleared but retain their previous values. If the DSP registers are used as source registers in longword mode, when data is stored from any registers other than A0G, A1G, the 32 bits (data) of the register are transferred. When the A0, A1 registers are used as the source registers the guard bits are disregarded. When the A0G, A1G registers are the source registers in longword mode, only 8 bits of the data are stored from the registers; the upper bits are sign-extended. If the DSP registers are used as destination registers in longword mode, the load is to the 32 bits of the register, with the exception of A0G, A1G. In the case of the A0, A1 registers, the data sign is extended and stored in the guard bits. When the A0G, A1G registers are the destination registers in longword mode, the least significant 8 bits of the data are loaded into the registers; the A0, A1 registers are not zero cleared but retain their previous values. Tables 2.4 and 2.5 indicate the register data formats for DSP instructions. Some registers cannot be accessed by certain instructions. For example, the PMULS instruction can designate the A1 register as a source register but cannot designate A0 as such. Refer to the instruction explanations for details. Figure 2.8 shows the relationship between the buses and the DSP registers during transfers.
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Table 2.4
Source Register Data Formats for DSP Instructions
Guard Bits 39 to 32 40-bit data Register Bits 31 to 16 15 to 0
Register A0, A1 DSP operation
Instruction Fixed decimal, PDMSB, PSHA Integer Logic, PSHL, PMULS Data transfer MOVX.W, MOVY.W, MOVS.W MOVS.L
24-bit data — 16-bit data
—
32-bit data Data Sign* — 32-bit data —
A0G, A1G X0, X1, Y0, Y1, M0, M1
Data transfer DSP operation
MOVS.W MOVS.L Fixed decimal, PDMSB, PSHA Integer Logic, PSHL, PMULS
16-bit data —
—
Data transfer Note: *
MOVS.W MOVS.L 32-bit data
The sign is extended and stored in the ALU’s guard bits.
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Table 2.5
Destination Register Data Formats for DSP Instructions
Guard Bits 39 to 32 (Sign extend) Register Bits 31 to 16 40-bit result 15 to 0
Register A0, A1 DSP operation
Instruction Fixed decimal, PSHA, PMULS Integer, PDMSB Logic, PSHL Data transfer MOVS.W MOVS.L MOVS.W MOVS.L Fixed decimal, PSHA, PMULS Integer, logic, PDMSB, PSHL Data transfer MOVX.W, MOVY.W, MOVS.W MOVS.L
24-bit result Clear to 0 Sign extend Data — 16-bit result 16-bit data 32-bit data Not updated 32-bit result
Clear to 0
A0G, A1G X0, X1, Y0, Y1, M0, M1
Data transfer DSP operation
Not updated
16-bit result
Clear to 0
16-bit data
32-bit data
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32 bits 16 bits 16 bits [7:0] 8 bits 16 bits MOVX.W, MOVY.W 31 16 A0 32 A0G A1G DSR 7 0 A1 M0 M1 X0 X1 Y0 Y1
CDB XDB YDB 32 bits MOVS.W, MOVS.L 0
MOVS.W, MOVS.L 39
Figure 2.8 DSP Register-Bus Relationship during Data Transfers
2.3
CPU Core Instruction Features
The CPU core instructions are RISC type. The characteristics are as follows. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using the pipeline system. One state equals 16.0 ns when operating at 62.5 MHz. Data Length: Longword is the basic data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations. It also is handled as longword data.
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Table 2.6
Sign Extension of Word Data
Description Example of Conventional CPU #H'1234,R0
SH7615 CPU MOV.W ADD ........ .DATA.W H'1234 @(disp,PC),R1 R1,R0
ADD.W Data is sign-extended to 32 bits, and R1 becomes H'00001234. It is next operated upon by an ADD instruction
Note: @(disp, PC) accesses the immediate data.
Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). However, Instructions such as AND manipulating bits, are executed directly in memory. Delayed Branches: Such instructions as unconditional branches are delayed branch instructions. In the case of delayed branch instructions, the branch occurs after execution of the instruction immediately following the delayed branch instruction (slot instruction). This reduces pipeline disruption during branching. The branching operation of the delayed branch occurs after execution of the slot instruction. However, with the exception of such branch operations as register updating, execution of instructions is performed with the order of delayed branch instruction, then delayed slot instruction. For example, even if the contents of a register storing a branch destination address are modified by a delayed slot, the branch destination address will still be the contents of the register before the modification. Table 2.7 Delayed Branch Instructions
Description Executes an ADD before branching to TRGET Example of Conventional CPU ADD.W BRA R1,R0 TRGET
SH7615 CPU BRA ADD TRGET R1,R0
Multiplication/Multiply-Accumulate Operation: 16 × 16 → 32 multiplications execute in one to three cycles, and 16 × 16 + 64 → 64 multiply-accumulate operations execute in two to three cycles. 32 × 32 → 64 multiplications and 32 × 32 + 64 → 64 multiply-accumulate operations execute in two to four cycles.
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T Bit: The T bit in the status register (SR) changes according to the result of a comparison, and conditional branches occur in accordance with its true or false status. The number of instructions modifying the T bit is kept to a minimum to improve the processing speed. Table 2.8 T Bit
Description T bit is set when R0 ≥ R1. Example of Conventional CPU CMP.W R1,R0 TRGET0 TRGET1
SH7615 CPU CMP/GE BT BF ADD CMP/EQ BT R1,R0 TRGET0 TRGET1 #–1,R0 #0,R0 TRGET
The program branches to TRGET0 BGE when R0 ≥ R1. The program branches to TRGET1 BLT when R0 < R1 T bit is not changed by ADD. T bit is set when R0 = 0. The program branches when R0 = 0 BEQ
SUB.W #1,R0 TRGET
Immediate Data: Byte immediate data resides in instruction code. Word or longword immediate data is not input in instruction codes but is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. Table 2.9 Immediate Data Accessing
SH7615 CPU MOV MOV.W ........ .DATA.W H'1234 32-bit immediate MOV.L ........ .DATA.L H'12345678 Note: @(disp, PC) accesses the immediate data. @(disp,PC),R0 MOV.L #H'12345678,R0 #H'12,R0 @(disp,PC),R0 Example of Conventional CPU MOV.B MOV.W #H'12,R0 #H'1234,R0
Classification 8-bit immediate 16-bit immediate
Rev. 2.00, 03/05, page 52 of 884
Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect register addressing mode. Table 2.10 Absolute Address Accessing
Classification Absolute address SH7615 CPU MOV.L MOV.B ........ .DATA.L H'12345678 @(disp,PC),R1 @R1,R0 Example of Conventional CPU MOV.B @H'12345678,R0
16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the preexisting displacement value is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect indexed register addressing mode. Table 2.11 Displacement Accessing
Classification 16-bit displacement SH7615 CPU MOV.W MOV.W ........ .DATA.W H'1234 @(disp,PC),R0 @(R0,R1),R2 Example of Conventional CPU MOV.W @(H'1234,R1),R2
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2.4
2.4.1
Instruction Formats
CPU Instruction Addressing Modes
The addressing modes and effective address calculation for instructions executed by the CPU core are listed in table 2.12. Table 2.12 CPU Instruction Addressing Modes and Effective Addresses
Addressing Mode Direct register addressing Instruction Format Effective Addresses Calculation Rn The effective address is register Rn (The operand is the contents of register Rn) The effective address is the content of register Rn
Rn Rn
Equation — Rn
Indirect register @Rn addressing
Post-increment @Rn+ indirect register addressing
The effective address is the content of register Rn Rn. A constant is added to the content of Rn after (After the the instruction is executed. 1 is added for a byte instruction operation, 2 for a word operation, and 4 for a executes) longword operation Byte: Rn + 1 → Rn Rn Rn Word: Rn + 2 → Rn Rn + 1/2/4 Longword: Rn + 4 + → Rn
1/2/4
Pre-decrement @–Rn indirect register addressing
The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation
Rn Rn – 1/2/4 1/2/4 – Rn – 1/2/4
Byte: Rn – 1 → Rn Word: Rn – 2 → Rn Longword: Rn – 4 → Rn (Instruction executed with Rn after calculation)
Rev. 2.00, 03/05, page 54 of 884
Addressing Mode
Instruction Format Effective Addresses Calculation The effective address is Rn plus a 4-bit displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation
Rn disp (zero-extended) × 1/2/4 + Rn + disp × 1/2/4
Equation Byte: Rn + disp Word: Rn + disp × 2 Longword: Rn + disp × 4
Indirect register @(disp:4, addressing Rn) with displacement
Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0 register Rn addressing
+ R0 Rn + R0
Rn + R0
Indirect GBR @(disp:8, addressing with GBR) displacement
The effective address is the GBR value plus an 8-bit displacement (disp). The value of disp is zero-extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation
GBR disp (zero-extended) × 1/2/4 + GBR + disp × 1/2/4
Byte: GBR + disp Word: GBR + disp ×2 Longword: GBR + disp × 4
Rev. 2.00, 03/05, page 55 of 884
Addressing Mode Indirect indexed GBR addressing
Instruction Format Effective Addresses Calculation @(R0, GBR) The effective address is the GBR value plus the R0
GBR + R0 GBR + R0
Equation GBR + R0
PC relative addressing with displacement
@(disp:8, PC)
The effective address is the PC value plus an 8-bit displacement (disp). The value of disp is zeroextended, is doubled for a word operation, and is quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked
PC (for longword) & H'FFFFFFFC + disp (zero-extended) × 2/4 PC + disp × 2 or PC&H'FFFFFFFC + disp × 4
Word: PC + disp ×2 Longword: PC & H'FFFFFFFC + disp × 4
Rev. 2.00, 03/05, page 56 of 884
Addressing Mode PC relative addressing
Instruction Format Effective Addresses Calculation disp:8
Equation
The effective address is the PC value sign-extended PC + disp × 2 with an 8-bit displacement (disp), doubled, and added to the PC value
PC disp (sign-extended) × 2 + PC + disp × 2
disp:12
The effective address is the PC value sign-extended PC + disp × 2 with a 12-bit displacement (disp), doubled, and added to the PC value
PC disp (sign-extended) × 2 + PC + disp × 2
Rn
The effective address is the register PC value plus Rn
PC + Rn PC + Rn
PC + Rn
Immediate addressing
#imm:8 #imm:8 #imm:8
The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions are zero-extended The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions are sign-extended The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and is quadrupled
— — —
Rev. 2.00, 03/05, page 57 of 884
2.4.2
DSP Data Addressing
There are two different kinds of memory accesses with DSP instructions. One type is with the X, Y data transfer instructions (MOVX.W, MOVY.W), and the other is with the single data transfer instructions (MOVS.W, MOVS.L). The data addressing differs between these two types of instructions. Table 2.13 shows a summary of the data transfer instructions. Table 2.13 Overview of Data Transfer Instructions
Classification Address registers Index registers Addressing X, Y Data Transfer Processing (MOVX.W, MOVY.W) Ax: R4, R5; Ay: R6, R7 Ix: R8, Iy: R9 Nop/Inc(+2)/index addition: postupdate — Modulo addressing Data bus Data length Bus contention Memory Source registers Destination registers Possible XDB, YDB 16 bits (word) None X, Y data memory Dx, Dy: A0, A1 Dx: X0/X1; Dy: Y0/Y1 Single Data Transfer Processing (MOVS.W, MOVS.L) As: R2, R3, R4, R5 Is: R8 Nop/Inc(+2,+4)/index addition: postupdate Dec(–2,–4): pre-update Not possible CDB 16 bits/32 bits (word/longword) Yes All memory spaces Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G
X, Y Data Addressing: Among the DSP instructions, the MOVX.W and MOVY.W instructions can be used to simultaneously access X, Y data memory. The DSP instructions have two address pointers for simultaneous accessing of X, Y data memory. Only pointer addressing is possible with DSP instructions; there is no immediate addressing. The address registers are divided into two; the R4, R5 registers become the X memory address register (Ax), and the R6, R7 registers become the Y memory address register (Ay). The following three types of addressing exist with X, Y data transfer instructions. 1. Non-updated address registers: The Ax, Ay registers are address pointers. They are not updated. 2. Add index registers: The Ax, Ay registers are address pointers. The Ix, Iy register values are added to them, respectively, after the data transfer (post-update). 3. Increment address registers: The Ax, Ay registers are address pointers. The value +2 is added to each of them after the data transfer (post-update).
Rev. 2.00, 03/05, page 58 of 884
Each of the address pointers has an index register. The R8 register becomes the index register (Ix) of the X memory address register (Ax), and the R9 register becomes the index register (Iy) of the Y memory address register (Ay). The X, Y data transfer instructions are processed in word lengths. X, Y data memory is accessed in 16 bits. This is why the increment processing adds 2 to the address registers. In order to decrement, set –2 in the index register and designate add index register addressing. During X, Y data addressing, only bits 1 to 15 of the address pointer are valid. Always write a 0 to bit 0 of the address pointer and the index register during X, Y data addressing. Figure 2.9 shows the X, Y data transfer addressing. When X memory and Y memory are accessed using the X, Y bus, the upper word of Ax (R4 or R5) and Ay (R6 or R7) is ignored. The result of @Ay+ and @Ay+Iy is stored in the lower word of Ay, and the upper word retains its original value.
R8[Ix] +2 (INC) +0 (No update)
R4[Ax] R5[Ax]
R9[Iy] +2 (INC) +0 (No update)
R6[Ay] R7[Ay]
ALU
AU*1
Notes:
All three addressing methods (increment, index register addition (Ix, Iy), and no update) are post-updating methods. To decrement the address pointer, set the index register to –2 or –4. 1. Adder added for DSP addressing.
Figure 2.9 X, Y Data Transfer Addressing
Rev. 2.00, 03/05, page 59 of 884
Single Data Addressing: Among the DSP instructions, the single data transfer instructions (MOVS.W and MOVS.L) are used to either load data into DSP registers or to store it from them. With these instructions, the registers R2 to R5 are used as address registers (As) for the single data transfers. The four following data addressing instructions exist for single data transfer instructions. 1. Non-updated address registers: The As registers are address pointers. They are not updated. 2. Add index registers: The As registers are address pointers. The Is register values are added to them after the data transfer (post-update). 3. Increment address registers: The As registers are address pointers. The value +2 or +4 is added after the data transfer (post-update). 4. Decrement address registers: The As registers are address pointers. The value –2 or –4 is added (+2 or +4 is subtracted) before the data transfer (pre-update). The address pointer (As) uses the R8 register as an index register (Is). Figure 2.10 shows the single data transfer addressing.
31 R2[As] 31 R8[Is] –2/–4 (DEC) +2/+4 (INC) +0 (No update) 0 R3[As] R4[As] R5[As] 0
ALU 31 MAB CAB 0 Note: There are four addressing methods (no update, index register addition (Is), increment, and decrement). Index register addition and increment are post-updating methods. Decrement is a pre-updating method.
Figure 2.10 Single Data Transfer Addressing
Rev. 2.00, 03/05, page 60 of 884
Modulo Addressing: The chip has a modulo addressing mode, just as other DSPs do. Address registers are updated in the same manner as with other modes. When the address pointer value becomes the same as a previously established modulo end address, the address pointer becomes the modulo start address. Modulo addressing is valid only with X, Y data transfer instructions (MOVX.W, MOVY.W). When the DMX bit of the SR register is set, the X address register enters modulo addressing mode; when the DMY bit of the SR register is set, the Y address register does so. Modulo addressing is valid only for either the X or the Y address register; it is not possible to make them both modulo addressing mode at the same time. Therefore, do not simultaneously set the DMX and DMY. If they happen to be set at the same time, only the DMY side is valid. The MOD register is used to designate the start and end addresses of the modulo address area; it stores the MS (modulo start) and ME (modulo end). An example of MOD register (MS, ME) usage is indicated below.
MOV.L LDC ModAddr: .DATA.W .DATA.W ModAddr,Rn; Rn,MOD; mEnd; mStart; Rn=ModEnd, ModStart ME=ModEnd, MS=ModStart ModEnd ModStart
ModStart: .DATA : ModEnd: .DATA
Designate the start and end addresses in MS and ME, and then set the DMX or DMY bit to 1. The contents of the address register are compared with ME. If they match ME, the start address MS is stored in the address register. The lower 16 bits of the address register are compared with ME. The maximum modulo size is 64 kbytes. This is sufficient for X, Y data memory accesses. Figure 2.11 shows a block diagram of modulo addressing.
Rev. 2.00, 03/05, page 61 of 884
Instruction (MOVX/MOVY) 31 31 R8[Ix] +2 +0 0 16 15 R4[Ax] R5[Ax] 0 DMX DMY 31 16 15 R6[Ay] CONT 15 MS ALU CMP ABx 15 XAB 1 15 ME 1 15 YAB ABy 1 AU 1 R7[Ay] 0 31 R9[Iy] +2 +0 0
Figure 2.11 Modulo Addressing An example of modulo addressing is indicated below:
MS=H'E008; ME=H'E00C; R4=H'1000E008;
DMX=1; DMY=0; (sets modulo addressing for address register Ax (R4, R5)) The R4 register changes as follows due to the above settings. R4: H'1000E008
Inc. Inc. Inc. R4: H'1000E00A R4: H'1000E00C R4: H'1000E008
(becomes the modulo start address because the modulo end address occurred)
Data is placed so that the upper 16 bits of the modulo start and end addresses become identical. This is so because the modulo start address replaces only the lower 15 bits of the address register, excepting bit 0. Note: When using add index with DSP data addressing, there are cases where the value is exceeded without the address pointer matching the ME. In such cases, the address pointer does not return to the modulo start address. Bit 0 is disregarded not only for modulo addressing, but also during X, Y data addressing, so always write 0 to the 0 bits of the address pointer, index register, MS, and ME.
Rev. 2.00, 03/05, page 62 of 884
DSP Addressing Operation: The DSP addressing operation in the item stage (EX) of the pipeline, including modulo addressing, is indicated below.
if ( Operation is MOVX.W MOVY.W ) { ABx=Ax; ABy=Ay; /* memory access cycle uses ABx and ABy. The addresses to be used have not been updated */
/* Ax is one of R4,5 */ if ( DMX==0 || DMX==1 && DMY==1 )} Ax=Ax+(+2 or R8[Ix} or +0); /* Inc,Index,Not-Update */ else if (!not-update) Ax=modulo( Ax, (+2 or R8[Ix]) );
/* Ay is one of R6,7 */ if ( DMY==0 ) Ay=Ay+(+2 or R9[Iy] or +0; /* Inc,Index,Not-Update */ else if (! not-update) Ay=modulo( Ay, (+2 or R9[Iy]) ); } else if ( Operation is MOVS.W or MOVS.L ) { if ( Addressing is Nop, Inc, Add-index-reg ) { MAB=As; /* memory access cycle uses MAB. The address to be used has not been updated */ /* As is one of R2–5 */ As=As+(+2 or +4 or R8[Is] or +0); /* Inc.Index,Not-Update */ else { /* Decrement, Pre-update */ /* As is one of R2–5 */ As=As+(–2 or –4); MAB=As; /* memory access cycle uses MAB. The address to be used has been updated */ }
/* The value to be added to the address register depends on addressing operations. For example, (+2 or R8[Ix] or +0) means that +2: R8[Ix}: +0: */ Rev. 2.00, 03/05, page 63 of 884 if operation is increment if operation is add-index-reg if operation is not-update
function modulo ( AddrReg, Index ) { if ( AdrReg[15:0]==ME ) AdrReg[15:0]=MS; else AdrReg=AdrReg+Index; return AddrReg; }
2.4.3
Instruction Formats for CPU Instructions
The instruction format of instructions executed by the CPU core and the meanings of the source and destination operands are indicated below. The meaning of the operand depends on the instruction code. The symbols are used as follows: xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement Table 2.14 Instruction Formats for CPU Instructions
Instruction Formats 0 format
15 xxxx xxxx xxxx xxxx 0
Source Operand —
Destination Operand —
Example NOP
n format
15 xxxx nnnn xxxx xxxx 0
—
nnnn: Direct register
MOVT Rn STS MACH,Rn
Control register or nnnn: Direct system register register
Control register or nnnn: Indirect pre- STC.L SR,@-Rn system register decrement register m format
15 xxxx mmmm xxxx xxxx 0
mmmm: Direct register
Control register or LDC system register
Rm,SR
mmmm: Indirect post- Control register or LDC.L @Rm+,SR increment register system register mmmm: Indirect register mmmm: PC relative using Rm — — JMP @Rm BRAF Rm
Rev. 2.00, 03/05, page 64 of 884
Instruction Formats nm format
15 xxxx nnnn mmmm xxxx 0
Source Operand mmmm: Direct register mmmm: Direct register
Destination Operand nnnn: Direct register nnnn: Indirect register
Example ADD Rm,Rn
MOV.L Rm,@Rn MAC.W @Rm+,@Rn+
mmmm: Indirect post- MACH, MACL increment register (multiply/ accumulate) nnnn: Indirect postincrement register (multiply/ accumulate)* mmmm: Indirect post- nnnn: Direct increment register register mmmm: Direct register mmmm: Direct register md format
15 xxxx xxxx mmmm dddd 0
MOV.L @Rm+,Rn
nnnn: Indirect pre- MOV.L Rm,@-Rn decrement register nnnn: Indirect indexed register MOV.L Rm,@(R0,Rn)
mmmmdddd: indirect R0 (Direct register) MOV.B register with @(disp,Rm),R0 displacement R0 (Direct register) nnnndddd: Indirect MOV.B register with R0,@(disp,Rn) displacement mmmm: Direct register nnnndddd: Indirect MOV.L register with Rm,@(disp,Rn) displacement MOV.L @(disp,Rm),Rn
nd4 format
15 xxxx xxxx nnnn dddd 0
nmd format
15 xxxx nnnn mmmm dddd 0
mmmmdddd: Indirect nnnn: Direct register with register displacement
Rev. 2.00, 03/05, page 65 of 884
Instruction Formats d format
15 xxxx xxxx dddd dddd 0
Source Operand
Destination Operand
Example
dddddddd: Indirect R0 (Direct register) MOV.L GBR with @(disp,GBR),R0 displacement R0(Direct register) dddddddd: Indirect MOV.L GBR with R0,@(disp,GBR) displacement dddddddd: PC relative with displacement dddddddd: PC relative R0 (Direct register) MOVA @(disp,PC),R0 — — BF BRA label label
d12 format
15 xxxx dddd dddd dddd 0
dddddddddddd: PC relative
(label=disp+PC)
nd8 format
15 xxxx nnnn dddd dddd 0
dddddddd: PC relative with displacement iiiiiiii: Immediate
nnnn: Direct register
MOV.L @(disp,PC),Rn
i format
15 xxxx xxxx iiii iiii 0
Indirect indexed GBR
AND.B #imm,@(R0,GBR) #imm,R0
iiiiiiii: Immediate iiiiiiii: Immediate
R0 (Direct register) AND — nnnn: Direct register
TRAPA #imm ADD #imm,Rn
ni format
15 xxxx nnnn iiii iiii 0
iiiiiiii: Immediate
Note:
*
In multiply/accumulate instructions, nnnn is the source register.
Rev. 2.00, 03/05, page 66 of 884
2.4.4
Instruction Formats for DSP Instructions
New instructions have been added for digital signal processing. The new instructions are divided into the two following types. 1. Memory and DSP register double, single data transfer instructions (16-bit length) 2. Parallel processing instructions processed by the DSP unit (32-bit length) Figure 2.12 shows each of the instruction formats.
15 CPU core instructions 0000 to 1110 15 10 9 A field 0 A field 16 15 A field B field 0 0 0
Double data transfer instructions Single data transfer instructions Parallel processing instructions
111100 15 10 9
111101 31 26 25
111110
Figure 2.12 Instruction Formats for DSP Instructions Double, Single Data Transfer Instructions: Table 2.15 indicates the data formats for double data transfer instructions, and table 2.16 indicates the data formats for single data transfer instructions.
Rev. 2.00, 03/05, page 67 of 884
Table 2.15 Instruction Formats for Double Data Transfers
Category X memory data transfers NOPX MOVX.W MOVX.W MOVX.W MOVX.W MOVX.W MOVX.W Y memory data transfers NOPY MOVY.W MOVY.W MOVY.W MOVY.W MOVY.W MOVY.W @Ay,Dy @Ay+,Dy @Ay+Iy,Dy Da,@Ay Da,@Ay+ Da,@Ay+Iy @Ax,Dx @Ax+,Dx @Ax+Ix,Dx Da,@Ax Da,@Ax+ Da,@Ax+Ix 1 1 1 1 0 0 0 Ay Mnemonic 15 1 14 1 13 1 12 1 11 0 10 0 9 0 Ax 8
Category X memory data transfers NOPX MOVX.W MOVX.W MOVX.W MOVX.W MOVX.W MOVX.W Y memory data transfers NOPY MOVY.W MOVY.W MOVY.W MOVY.W MOVY.W MOVY.W
Mnemonic
7 0
6
5 0 0
4
3 0 0 1 1 0 1 1
2 0 1 0 1 1 0 1
1
0
@Ax,Dx @Ax+,Dx @Ax+Ix,Dx Da,@Ax Da,@Ax+ Da,@Ax+Ix
Dx
Da
1
0 @Ay,Dy @Ay+,Dy @Ay+Iy,Dy Da,@Ay Da,@Ay+ Da,@Ay+Iy Dy
0 0
0 0 1 1 0 1 1
0 1 0 1 1 0 1
Da
1
Ax: 0=R4, 1=R5 Ay: 0=R6, 1=R7 Dx: 0=X0, 1=X1 Dy: 0=Y0, 1=Y1 Da: 0=A0, 1=A1
Rev. 2.00, 03/05, page 68 of 884
Table 2.16 Instruction Formats for Single Data Transfers
Category Single data transfer MOVS.W MOVS.W MOVS.W MOVS.W MOVS.W MOVS.W MOVS.W MOVS.W MOVS.L MOVS.L MOVS.L MOVS.L MOVS.L MOVS.L MOVS.L MOVS.L Mnemonic @–As,Ds @As,Ds @As+,Ds @As+Is,Ds Ds,@-As Ds,@As Ds,@As+ Ds,@As+Is @–As,Ds @As,Ds @As+,Ds @As+Is,Ds Ds,@-As Ds,@As Ds,@As+ Ds,@As+Is 15 1 14 1 13 1 12 1 11 0 10 1 9 8
As 0: R4 1: R5 2: R2 3: R3
Category Single data transfer
Mnemonic MOVS.W MOVS.W MOVS.W MOVS.W MOVS.W MOVS.W MOVS.W MOVS.W MOVS.L MOVS.L MOVS.L MOVS.L MOVS.L MOVS.L MOVS.L MOVS.L @–As,Ds @As,Ds @As+,Ds @As+Is,Ds Ds,@-As Ds,@As Ds,@As+ Ds,@As+Is @–As,Ds @As,Ds @As+,Ds @As+Is,Ds Ds,@-As Ds,@As Ds,@As+ Ds,@As+Is
7 Ds
6
5 0: (*) 1: (*) 2: (*) 3: (*) 4: (*) 5: A1 6: (*) 7: A0 8: X0 9: X1 A: Y0 B: Y1 C: M0 D: A1G E: M1 F: A0G
4
3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 0
0 0
1
1
0
1
Note:
*
System reserved code
Rev. 2.00, 03/05, page 69 of 884
Parallel Processing Instructions: The parallel processing instructions allow for more efficient execution of digital signal processing using the DSP unit. They are 32 bits in length, allowing simultaneously in parallel four processes, ALU operations, multiplications or two data transfers. The parallel processing instructions are divided into A fields and B fields. The A field defines data transfer instructions; the B field defines ALU operation instructions and multiplication instructions. These instructions can be defined independently, the processes can be independent, and furthermore, they can be executed simultaneously in parallel. Table 2.17 indicates the A field parallel data transfer instructions, and table 2.18 indicates the B field ALU operation instructions and multiplication instructions. A fields instruction is the same as double data transfers in table 2.15. Table 2.17 A Field Parallel Data Transfer Instructions
Category X memory data transfers NOPX MOVX.W MOVX.W MOVX.W MOVX.W MOVX.W MOVX.W Y memory data transfers NOPY MOVY.W MOVY.W MOVY.W MOVY.W MOVY.W MOVY.W @Ay,Dy @Ay+,Dy @Ay+Iy,Dy Da,@Ay Da,@Ay+ Da,@Ay+Iy @Ax,Dx @Ax+,Dx @Ax+Ix,Dx Da,@Ax Da,@Ax+ Da,@Ax+Ix 0 Ay Mnemonic 31 1 30 1 29 1 28 1 27 1 26 0 25 0 Ax 24 23 0 Dx
Da
Rev. 2.00, 03/05, page 70 of 884
Category X memory data transfers
Mnemonic NOPX MOVX.W MOVX.W MOVX.W MOVX.W MOVX.W MOVX.W @Ax,Dx @Ax+,Dx @Ax+Ix,Dx Da,@Ax Da,@Ax+ Da,@Ax+Ix
22
21 0 0
20
19 0 0 1 1 0 1 1
18 0 1 0 1 1 0 1
17
16
15 to 0 B field
1
Y memory data transfers
NOPY MOVY.W MOVY.W MOVY.W MOVY.W MOVY.W MOVY.W @Ay,Dy @Ay+,Dy @Ay+Iy,Dy Da,@Ay Da,@Ay+ Da,@Ay+Iy
0 Dy
0 0
0 0 1 1 0 1 1
0 1 0 1 1 0 1
B field
Da
1
Ax: 0=R4, 1=R5 Ay: 0=R6, 1=R7 Dx: 0=X0, 1=X1 Dy: 0=Y0, 1=Y1 Da: 0=A0, 1=A1
Rev. 2.00, 03/05, page 71 of 884
Table 2.18 B Field ALU Operation Instructions, Multiplication Instructions
Category Imm. shift Mnemonic PSHL #lmm, Dz PSHA #lmm, Dz Reserved PMULS Se, Sf, Dg Reserved PSUB Sx, Sy, Du PMULS Se, Sf, Dg PADD Sx, Sy, Du PMULS Se, Sf, Dg Three operand instructions Reserved PSUBC Sx, Sy, Dz PADDC Sx, Sy, Dz PCMP Sx, Sy Reserved Reserved Reserved PABS Sx, Dz PRND Sx, Dz PABS Sy, Dz PRND Sy, Dz 31–27 1 26 0 25–16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A field 0 0 0 0 0 –16 ≤ lmm ≤ +16 Dz 00010 000 1 001 0100 Se Sf 0:Y0 1:Y1 2:X0 3:A1 Sx 0:X0 1:X1 2:A0 3:A1 Sy 0:Y0 1:Y1 2:M0 3:M1 Dg 0:M0 1:M1 2:A0 3:A1 Du 0:X0 1:Y0 2:A0 3:A1 – 32 ≤ lmm ≤ +32
Six operand parallel instruction
0 1 0 1 0:X0 1:X1 0 1 1 0 2:Y0 3:A1 0111 10 0000 01 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 001 1 0 1 010 1 0 1 011 1 0 1
0
0
Dz 0: (*1) 1: (*1) 2: (*1) 3: (*1) 4: (*1) 5: A1 6: (*1) 7: A0 8: X0 9: X1 A: Y0 B: Y1 C: M0 D: (*1) E: M1 F: (*1)
Reserved
Rev. 2.00, 03/05, page 72 of 884
Mnemonic 31–27 26 (if cc) PSHL Sx, Sy, Dz 1 0 Conditional (if cc) PSHA Sx, Sy, Dz three operand (if cc) PSUB Sx, Sy, Dz instructions (if cc) PADD Sx, Sy, Dz Reserved (if cc) PAND Sx, Sy, Dz (if cc) PXOR Sx, Sy, Dz (if cc) POR Sx, Sy, Dz (if cc) PDEC Sx, Dz (if cc) PINC Sx, Dz (if cc) PDEC Sy, Dz (if cc) PINC Sy, Dz (if cc) PCLR Dz (if cc) PDMSB Sx, Dz Reserved (if cc) PDMSB Sy, Dz (if cc) PNEG Sx, Dz (if cc) PCOPY Sx, Dz (if cc) PNEG Sy, Dz (if cc) PCOPY Sy, Dz Reserved (if cc) PSTS MACH, Dz (if cc) PSTS MACL, Dz (if cc) PLDS Dz, MACH (if cc) PLDS Dz, MACL Reserved*2 Reserved 1
Category
25–16 15 14 13 12 11 10 0000 A field 01 10 11 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 001 1 0 1 010 1 0 1 011 1 0 1 010 1 0 1
98 if cc
7 6 54 3210
01: Uncondition
10:DCT
11:DCF
11
0 0011 01 10 11 0 0*
0 if cc
0
Notes: 1. System reserved code 2. (if cc): DCT (DC bit true), DCF (DC bit false), or none (unconditional instruction)
2.5
Instruction Set
The instructions are divided into three groups: CPU instructions executed by the CPU core, DSP data transfer instructions executed by the DSP unit, and DSP operation instructions. There are a number of CPU instructions for supporting the DSP functions. The instruction set is explained below in terms of each of the three groups.
Rev. 2.00, 03/05, page 73 of 884
2.5.1
CPU Instruction Set
Table 2.19 lists the CPU instructions by classification. Table 2.19 Classification of CPU Instructions
Operation Classification Types Code Function Data transfer 5 MOV MOVA MOVT SWAP XTRCT Arithmetic operations 21 ADD ADDC ADDV DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULS MULU NEG NEGC SUB SUBC SUBV No. of Instructions
Data transfer, immediate data transfer, peripheral 39 module data transfer, structure data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of the middle of registers connected Binary addition Binary addition with carry Binary addition with overflow Division Initialization of signed division Initialization of unsigned division Signed double-length multiplication Unsigned double-length multiplication Decrement and test Sign extension Zero extension Multiply/accumulate, double-length multiply/accumulate operation Double-length multiply operation Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow 33
CMP/cond Comparison
Rev. 2.00, 03/05, page 74 of 884
Operation Classification Types Code Function Logic operations 6 AND NOT OR TAS TST XOR Shift 10 ROTCL ROTCR ROTL ROTR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch 9 BF BT BRA BRAF BSR BSRF JMP JSR RTS Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation with T bit One-bit right rotation with T bit One-bit left rotation One-bit right rotation One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift
No. of Instructions 14
14
Conditional branch, conditional branch with delay 11 (Branch when T = 0) Conditional branch, conditional branch with delay (Branch when T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure
Rev. 2.00, 03/05, page 75 of 884
Operation Classification Types Code Function System control 14 CLRMAC MAC register clear CLRT LDC LDRE LDRS LDS NOP RTE SETRC SETT SLEEP STC STS TRAPA Total:65 T bit clear Load to control register Load to repeat end register Load to repeat start register Load to system register No operation Return from exception processing Repeat count setting T bit set Shift into power-down mode Storing control register data Storing system register data Trap exception handling
No. of Instructions 71
182
Rev. 2.00, 03/05, page 76 of 884
The instruction codes, operation, and execution states of the CPU instructions are listed by classification with the formats listed in below.
Instruction Indicated by mnemonic Instruction Code Indicated in MSB ↔ LSB order Operation Indicates summary of operation Execution Cycles Value when no wait states are inserted*1 T Bit Value of T bit after instruction is executed
Explanation of Symbols OP.Sz SRC, DEST OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement *2
Explanation of Symbols mmmm: Source register
Explanation of Symbols →, ←: Transfer direction Explanation of Symbols —: No change
nnnn: Destination register (xx): Memory operand 0000: R0 M/Q/T: Flag bits in the SR 0001: R1 &: Logical AND of each bit ......... 1111: R15 iiii: Immediate data dddd: Displacement |: Logical OR of each bit ^: Exclusive OR of each bit ~: Logical NOT of each bit n: n-bit right shift
Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory → register) and the register used by the next instruction are the same. 2. Depending on the instruction’s operand size, scaling is ×1, ×2, or ×4. For details, see the SH-1/SH-2/SH-DSP Programming Manual.
Rev. 2.00, 03/05, page 77 of 884
Table 2.20 Data Transfer Instructions
Instruction MOV MOV.W MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W #imm,Rn @(disp,PC),Rn @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@–Rn Rm,@–Rn Rm,@–Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0 @(disp,Rm),R0 @(disp,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn Instruction Code Operation Cycles T Bit — — — — — — — — — — — — — — — — — — — — — — — — — — — 1110nnnniiiiiiii imm → Sign extension → Rn 1 1001nnnndddddddd (disp × 2 + PC) → Sign extension → Rn 1101nnnndddddddd (disp × 4 + PC) → Rn 0110nnnnmmmm0011 Rm → Rn 0010nnnnmmmm0000 Rm → (Rn) 0010nnnnmmmm0001 Rm → (Rn) 0010nnnnmmmm0010 Rm → (Rn) 0110nnnnmmmm0000 (Rm) → Sign extension → Rn 0110nnnnmmmm0001 (Rm) → Sign extension → Rn 0110nnnnmmmm0010 (Rm) → Rn 0010nnnnmmmm0100 Rn–1 → Rn, Rm → (Rn) 0010nnnnmmmm0101 Rn–2 → Rn, Rm → (Rn) 0010nnnnmmmm0110 Rn–4 → Rn, Rm → (Rn) 0110nnnnmmmm0100 (Rm) → Sign extension → Rn,Rm + 1 → Rm 0110nnnnmmmm0101 (Rm) → Sign extension → Rn,Rm + 2 → Rm 0110nnnnmmmm0110 (Rm) → Rn,Rm + 4 → Rm 10000000nnnndddd R0 → (disp + Rn) 10000001nnnndddd R0 → (disp × 2 + Rn) 0001nnnnmmmmdddd Rm → (disp × 4 + Rn) 10000100mmmmdddd (disp + Rm) → Sign extension → R0 10000101mmmmdddd (disp × 2 + Rm) → Sign extension → R0 0101nnnnmmmmdddd (disp × 4 + Rm) → Rn 0000nnnnmmmm0100 Rm → (R0 + Rn) 0000nnnnmmmm0101 Rm → (R0 + Rn) 0000nnnnmmmm0110 Rm → (R0 + Rn) 0000nnnnmmmm1100 (R0 + Rm) → Sign extension → Rn 0000nnnnmmmm1101 (R0 + Rm) → Sign extension → Rn 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Instruction MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT @(R0,Rm),Rn
Instruction Code
Operation
Cycles 1 1 1 1 1 1 1 1 1 1 1
T Bit — — — — — — — — — — — —
0000nnnnmmmm1110 (R0 + Rm) → Rn
R0,@(disp,GBR) 11000000dddddddd R0 → (disp + GBR) R0,@(disp,GBR) 11000001dddddddd R0 → (disp × 2 + GBR) R0,@(disp,GBR) 11000010dddddddd R0 → (disp × 4 + GBR) @(disp,GBR),R0 11000100dddddddd (disp + GBR) → Sign extension → R0 @(disp,GBR),R0 11000101dddddddd (disp × 2 + GBR) → Sign extension → R0 @(disp,GBR),R0 11000110dddddddd (disp × 4 + GBR) → R0 @(disp,PC),R0 Rn 11000111dddddddd disp × 4 + PC → R0 0000nnnn00101001 T → Rn 0110nnnnmmmm1000 Rm → Swap the bottom two bytes → Rn 0110nnnnmmmm1001 Rm → Swap upper and lower words → Rn
SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn
0010nnnnmmmm1101 Rm: Middle 32 bits of Rn → 1 Rn
Rev. 2.00, 03/05, page 79 of 884
Table 2.21 Arithmetic Instructions
Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS CMP/GE CMP/HI CMP/GT CMP/PL CMP/PZ Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010101 0100nnnn00010001 0010nnnnmmmm1100 Operation Rn + Rm → Rn Rn + imm → Rn Rn + Rm + T → Rn, Carry → T Rn + Rm → Rn, Overflow → T If R0 = imm, 1 → T If Rn = Rm, 1 → T Cycles 1 1 1 1 1 1 T Bit — — Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0 4* —
If Rn ≥ Rm with unsigned 1 data, 1 → T If Rn ≥ Rm with signed data, 1 → T 1
If Rn > Rm with unsigned 1 data, 1 → T If Rn > Rm with signed data, 1 → T If Rn > 0, 1 → T If Rn ≥ 0, 1 → T If Rn and Rm contain an identical byte, 1→T Single-step division (Rn/Rm) 1 1 1 1
CMP/STR Rm,Rn
DIV1 DIV0S DIV0U
Rm,Rn Rm,Rn
0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 0011nnnnmmmm1101
1
MSB of Rn → Q, MSB 1 of Rm → M, M ^ Q → T 0 → M/Q/T 1 Signed operation of Rn × 2 to Rm → MACH, MACL 32 × 32 → 64 bits Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits
DMULS.L Rm,Rn
DMULU.L Rm,Rn
0011nnnnmmmm0101
2 to 4*
—
Rev. 2.00, 03/05, page 80 of 884
Instruction DT Rn
Instruction Code 0100nnnn00010000
Operation
Cycles
T Bit Comparison result
Rn – 1 → Rn, when Rn 1 is 0, 1 → T When Rn is nonzero, 0→T A byte in Rm is signextended → Rn A word in Rm is signextended → Rn A byte in Rm is zeroextended → Rn A word in Rm is zeroextended → Rn Signed operation of (Rn) × (Rm) + MAC → MAC 32 × 32 + 64 → 64 bits Signed operation of (Rn) × (Rm) + MAC → MAC 16 × 16 + 64 → 64 bits Rn × Rm → MACL, 32 × 32 → 32 bits Signed operation of Rn × Rm → MAC 16 × 16 → 32 bits Unsigned operation of Rn × Rm → MAC 16 × 16 → 32 bits 0–Rm → Rn 0–Rm–T → Rn, Borrow → T Rn–Rm → Rn Rn–Rm–T → Rn, Borrow → T Rn–Rm → Rn, Underflow → T 1 1 1 1
EXTS.B Rm,Rn EXTS.W Rm,Rn EXTU.B Rm,Rn EXTU.W Rm,Rn MAC.L
0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101
— — — —
@Rm+,@Rn+ 0000nnnnmmmm1111
3/(2 to 4)* —
MAC.W
@Rm+,@Rn+ 0100nnnnmmmm1111
3/(2)*
—
MUL.L
Rm,Rn
0000nnnnmmmm0111 0010nnnnmmmm1111
2 to 4* 1 to 3*
— —
MULS.W Rm,Rn
MULU.W Rm,Rn
0010nnnnmmmm1110
1 to 3*
—
NEG NEGC SUB SUBC SUBV Note: *
Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn
0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011
1 1 1 1 1
— Borrow — Borrow Underflow
The normal number of execution cycles. The number in parentheses is the number of execution cycles in the case of contention with preceding or following instructions.
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Table 2.22 Logic Operation Instructions
Instruction AND AND AND.B NOT OR OR OR.B TAS.B TST TST TST.B XOR XOR XOR.B Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) @Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn #imm,R0 #imm,@(R0,GBR) Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 0010nnnnmmmm1000 11001000iiiiiiii 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii Operation Rn & Rm → Rn R0 & imm → R0 (R0 + GBR) & imm → (R0 + GBR) ~Rm → Rn Rn | Rm → Rn R0 | imm → R0 (R0 + GBR) | imm → (R0 + GBR) If (Rn) is 0, 1 → T, 1 → MSB of (Rn) Rn & Rm, if the result is 0, 1 → T R0 & imm, if the result is 0, 1 → T (R0 + GBR) & imm, if the result is 0, 1 → T Rn ^ Rm → Rn R0 ^ imm → R0 (R0 + GBR) ^ imm → (R0 + GBR) Cycles 1 1 3 1 1 1 3 4 1 1 3 1 1 3 T Bit — — — — — — — Test result Test result Test result Test result — — —
Rev. 2.00, 03/05, page 82 of 884
Table 2.23 Shift Instructions
Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 Operation T ← Rn ← MSB LSB → Rn → T T ← Rn ← T T → Rn → T T ← Rn ← 0 MSB → Rn → T T ← Rn ← 0 0 → Rn → T Rn2 → Rn Rn8 → Rn Rn16 → Rn Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit MSB LSB MSB LSB MSB LSB MSB LSB — — — — — —
SHLL16 Rn SHLR16 Rn
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Table 2.24 Branch Instructions
Instruction BF BF/S BT BT/S label label label label Instruction Code Operation Cycles 3/1* 2/1* 3/1* 2/1* T Bit — — — —
10001011dddddddd If T = 0, disp × 2 + PC → PC, if T = 1, nop 10001111dddddddd Delayed branch, if T = 0, disp × 2 + PC → PC, if T = 1, nop 10001001dddddddd If T = 1, disp × 2 + PC → PC, if T = 0, nop 10001101dddddddd Delayed branch, if T = 1, disp × 2 + PC → PC, if T = 0, nop 1010dddddddddddd Delayed branch, disp × 2 + PC → PC 0000mmmm00100011 Delayed branch, Rm + PC → PC 1011dddddddddddd Delayed branch, PC → PR, disp × 2 + PC → PC 0000mmmm00000011 Delayed branch, PC → PR, Rm + PC → PC 0100mmmm00101011 Delayed branch, Rm → PC 0100mmmm00001011 Delayed branch, PC → PR, Rm → PC 0000000000001011 Delayed branch, PR → PC
BRA BRAF BSR BSRF JMP JSR RTS Note:
label Rm label Rm @Rm @Rm
2 2 2 2 2 2 2
— — — — — — —
*
One state when it does not branch.
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Table 2.25 System Control Instructions
Instruction CLRMAC CLRT LDC LDC LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDRE LDRS LDS LDS LDS LDS LDS LDS LDS LDS LDS LDS.L LDS.L LDS.L LDS.L LDS.L LDS.L Rm,SR Rm,GBR Rm,VBR Rm,MOD Rm,RE Rm,RS @Rm+,SR @Rm+,GBR @Rm+,VBR @Rm+,MOD @Rm+,RE @Rm+,RS Instruction Code 0000000000101000 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm01011110 0100mmmm01111110 0100mmmm01101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm01010111 0100mmmm01110111 0100mmmm01100111 Operation 0 → MACH, MACL 0→T Rm → SR Rm → GBR Rm → VBR Rm → MOD Rm → RE Rm → RS (Rm) → SR, Rm + 4 → Rm (Rm) → GBR, Rm + 4 → Rm (Rm) → VBR, Rm + 4 → Rm (Rm) → MOD, Rm + 4 → Rm (Rm) → RE, Rm + 4 → Rm (Rm) → RS, Rm + 4 → Rm disp × 2 + PC → RE disp × 2 + PC → RS Rm → MACH Rm → MACL Rm → PR Rm → DSR Rm → A0 Rm → X0 Rm → X1 Rm → Y0 Rm → Y1 (Rm) → MACH, Rm + 4 → Rm (Rm) → MACL, Rm + 4 → Rm (Rm) → PR, Rm + 4 → Rm (Rm) → DSR, Rm + 4 → Rm (Rm) → A0, Rm + 4 → Rm (Rm) → X0, Rm + 4 → Rm Cycles 1 1 1 1 1 1 1 1 3 3 3 3 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit — 0 LSB — — — — — LSB — — — — — — — — — — — — — — — — — — — — — —
@(disp,PC) 10001110dddddddd @(disp,PC) 10001100dddddddd Rm,MACH Rm,MACL Rm,PR Rm,DSR Rm,A0 Rm,X0 Rm,X1 Rm,Y0 Rm,Y1 @Rm+,MACH @Rm+,MACL @Rm+,PR @Rm+,DSR @Rm+,A0 @Rm+,X0 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm01101010 0100mmmm01111010 0100mmmm10001010 0100mmmm10011010 0100mmmm10101010 0100mmmm10111010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0100mmmm01100110 0100mmmm01110110 0100mmmm10000110
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Instruction LDS.L LDS.L LDS.L NOP RTE SETRC Rm @Rm+,X1 @Rm+,Y0 @Rm+,Y1
Instruction Code 0100mmmm10010110 0100mmmm10100110 0100mmmm10110110 0000000000001001 0000000000101011 0100mmmm00010100
Operation (Rm) → X1, Rm + 4 → Rm (Rm) → Y0, Rm + 4 → Rm (Rm) → Y1, Rm + 4 → Rm No operation Delayed branch, stack area → PC/SR RE–RS operation result (repeat status) → RF1, RF0 Rm[11:0] → RC (SR[27:16]) RE–RS operation result (repeat status) → RF1, RF0 imm → RC (SR[23:16]), 0 → SR[27:24]
Cycles 1 1 1 1 4 1
T Bit — — — — LSB —
SETRC
#imm
10000010iiiiiiii
1
1
SETT SLEEP STC STC STC STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STS STS STS STS STS STS STS STS STS SR,Rn GBR,Rn VBR,Rn MOD,Rn RE,Rn RS,Rn SR,@–Rn GBR,@–Rn VBR,@–Rn MOD,@–Rn RE,@–Rn RS,@–Rn MACH,Rn MACL,Rn PR,Rn DSR,Rn A0,Rn X0,Rn X1,Rn Y0,Rn Y1,Rn
0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn01010010 0000nnnn01110010 0000nnnn01100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0100nnnn01010011 0100nnnn01110011 0100nnnn01100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0000nnnn01101010 0000nnnn01111010 0000nnnn10001010 0000nnnn10011010 0000nnnn10101010 0000nnnn10111010
1→T Sleep SR → Rn GBR → Rn VBR → Rn MOD → Rn RE → Rn RS → Rn Rn–4 → Rn, SR → (Rn) Rn–4 → Rn, GBR → (Rn) Rn–4 → Rn, VBR → (Rn) Rn–4 → Rn, MOD → (Rn) Rn–4 → Rn, RE → (Rn) Rn–4 → Rn, RS → (Rn) MACH → Rn MACL → Rn PR → Rn DSR → Rn A0 → Rn X0 → Rn X1 → Rn Y0 → Rn Y1 → Rn
1 3* 1 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1
1 — — — — — — — — — — — — — — — — — — — — — —
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Instruction STS.L STS.L STS.L STS.L STS.L STS.L STS.L STS.L STS.L TRAPA Note: MACH,@–Rn MACL,@–Rn PR,@–Rn DSR,@–Rn A0,@–Rn X0,@–Rn X1,@–Rn Y0,@–Rn Y1,@–Rn #imm *
Instruction Code 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 0100nnnn01100010 0100nnnn01110010 0100nnnn10000010 0100nnnn10010010 0100nnnn10100010 0100nnnn10110010 11000011iiiiiiii
Operation Rn–4 → Rn, MACH → (Rn) Rn–4 → Rn, MACL → (Rn) Rn–4 → Rn, PR → (Rn) Rn–4 → Rn, DSR → (Rn) Rn–4 → Rn, A0 → (Rn) Rn–4 → Rn, X0 → (Rn) Rn–4 → Rn, X1 → (Rn) Rn–4 → Rn, Y0 → (Rn) Rn–4 → Rn, Y1 → (Rn)
Cycles 1 1 1 1 1 1 1 1 1
T Bit — — — — — — — — — —
PC/SR → stack area, (imm × 4 8 + VBR) → PC
The number of execution cycles before the chip enters sleep mode.
Precautions Concerning the Number of Instruction Execution Cycles: The execution cycles listed in the tables are minimum values. In practice, the number of execution cycles increases under such conditions as 1) when the instruction fetch is in contention with a data access, 2) when the destination register of a load instruction (memory → register) is the same as the register used by the next instruction, 3) when the branch destination address of a branch instruction is a 4n + 2 address. CPU Instructions That Support DSP Functions: A number of system control instructions have been added to the CPU core instructions to support DSP functions. The RS, RE and MOD registers have been added to support repeat control and modulo addressing, and the repeat counter (RC) has been added to the status register (SR). The LDC and STC instructions have been added in order to access the aforementioned. The LDS and STS instructions have been added in order to access the DSP registers DSR, A0, X0, X1, Y0 and Y1. The SETRC instruction has been added to set the repeat counter (RC, bits 27 to 16) and repeat flags (RF1, RF0, bits 3 and 2) of the SR register. When the SETRC instruction operand is immediate, the 8-bit immediate data is stored in bits 23 to 16 of the SR register and bits 27 to 24 are cleared to 0. When the operand is a register, bits 11 to 0 (12 bits) of the register are stored in bits 27 to 16 of the SR register. Additionally, the status of 1 instruction repeat (00), 2 instruction repeat (01), 3 instruction repeat (11) or 4 instruction or greater repeat (10) is set from the RS and RE set values. In addition to the LDC instruction, the LDRS and LDRE instructions have been added for establishing the repeat start and repeat end addresses in the RS and RE registers. The added instructions are listed in table 2.26.
Rev. 2.00, 03/05, page 87 of 884
Table 2.26 Added CPU Instructions
Instruction LDC LDC LDC LDC.L LDC.L LDC.L STC STC STC STC.L STC.L STC.L LDS LDS.L LDS LDS.L LDS LDS.L LDS LDS.L LDS LDS.L LDS LDS.L STS STS.L STS STS.L STS STS.L STS Rm,MOD Rm,RE Rm,RS @Rm+,MOD @Rm+,RE @Rm+,RS MOD,Rn RE,Rn RS,Rn MOD,@-Rn RE,@-Rn RS,@-Rn Rm,DSR @Rm+,DSR Rm,A0 @Rm+,A0 Rm,X0 @Rm+,X0 Rm,X1 @Rm+,X1 Rm,Y0 @Rm+,Y0 Rm,Y1 @Rm+,Y1 DSR,Rn DSR,@-Rn A0,Rn A0,@-Rn X0,Rn X0,@-Rn X1,Rn Code 0100mmmm01011110 0100mmmm01111110 0100mmmm01101110 0100mmmm01010111 0100mmmm01110111 0100mmmm01100111 0000nnnn01010010 0000nnnn01110010 0000nnnn01100010 0100nnnn01010011 0100nnnn01110011 0100nnnn01100011 0100mmmm01101010 0100mmmm01100110 0100mmmm01111010 0100mmmm01110110 0100mmmm10001010 0100mmmm10000110 0100mmmm10011010 0100mmmm10010110 0100mmmm10101010 0100mmmm10100110 0100mmmm10111010 0100mmmm10110110 0000nnnn01101010 0100nnnn01100010 0000nnnn01111010 0100nnnn01110010 0000nnnn10001010 0100nnnn10000010 0000nnnn10011010 Operation Rm→MOD Rm→RE Rm→RS (Rm)→MOD,Rm+4→Rm (Rm)→RE,Rm+4→Rm (Rm)→RS,Rm+4→Rm MOD→Rn RE→Rn RS→Rn Rn–4→Rn,MOD→(Rn) Rn–4→Rn,RE→(Rn) Rn–4→Rn,RS→(Rn) Rm→DSR (Rm)→DSR,Rm+4→Rm Rm→A0 (Rm)→A0,Rm+4→Rm Rm→X0 (Rm)→X0,Rm+4→Rm Rm→X1 (Rm)→X1,Rm+4→Rm Rm→Y0 (Rm)→Y0,Rm+4→Rm Rm→Y1 (Rm)→Y1,Rm+4→Rm DSR→Rn Rn–4→Rn,DSR→(Rn) A0→Rn Rn–4→Rn,A0→(Rn) X0→Rn Rn–4→Rn,X0→(Rn) X1→Rn Cycles 1 1 1 3 3 3 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Rev. 2.00, 03/05, page 88 of 884
Instruction STS.L STS STS.L STS STS.L SETRC SETRC LDRS LDRE X1,@-Rn Y0,Rn Y0,@-Rn Y1,Rn Y1,@-Rn Rm #imm @(disp,PC) @(disp,PC)
Code 0100nnnn10010010 0000nnnn10101010 0100nnnn10100010 0000nnnn10111010 0100nnnn10110010 0100mmmm00010100 10000010iiiiiiii 10001100dddddddd 10001110dddddddd
Operation Rn–4→Rn,X1→(Rn) Y0→Rn Rn–4→Rn,Y0→(Rn) Y1→Rn Rn–4→Rn,Y1→(Rn) imm→RC(SR[23:16]), 0→SR[27:24] disp × 2+PC→RS disp × 2+PC→RE
Cycles 1 1 1 1 1 1 1 1
T Bit — — — — — — — — —
Rm[11:0]→RC (SR[27:16]) 1
2.5.2
DSP Data Transfer Instruction Set
Table 2.27 lists the DSP data transfer instructions by classification. Table 2.27 Classification of DSP Data Transfer Instructions
Classification Double data transfer instructions Types 4 Operation Code NOPX MOVX NOPY MOVY Single data transfer instructions 1 MOVS Function X memory no operation X memory data transfer Y memory no operation Y memory data transfer Single data transfer 16 No. of Instructions 14
Total: 5
Total: 30
The data transfer instructions are divided into two groups, double data transfers and single data transfers. Double data transfers can be combined with DSP operation instructions to perform DSP parallel processing. The parallel processing instructions are 32 bits in length, and the double data transfer instructions are incorporated into their A fields. Double data transfers that are not parallel processing instructions are 16 bits in length, as are the single data transfer instructions. The X memory and Y memory can be accessed simultaneously in parallel in double data transfers. One instruction each is designated from among the X and Y memory data accesses. The Ax pointer is used to access X memory; the Ay pointer is used to access Y memory. Double data transfers can only access X, Y memory.
Rev. 2.00, 03/05, page 89 of 884
Single data transfers can be accessed from any area. Single data transfers use the Ax pointer and two other pointers as an As pointer. Table 2.28 Double Data Transfer Instructions (X Memory Data)
Instruction NOPX MOVX.W @Ax,Dx MOVX.W @Ax+,Dx Operation No Operation Code 1111000*0*0*00** Cycles DC Bit 1 1 1 1 1 1 1 — — — — — — —
(Ax)→MSW of Dx,0→LSW of Dx 111100A*D*0*01** (Ax)→MSW of Dx,0→LSW of Dx, 111100A*D*0*10** Ax+2→Ax
MOVX.W @Ax+Ix,Dx (Ax)→MSW of Dx,0→LSW of Dx, 111100A*D*0*11** Ax+Ix→Ax MOVX.W Da,@Ax MOVX.W Da,@Ax+ MSW of Da→(Ax) MSW of Da→(Ax),Ax+2→Ax 111100A*D*1*01** 111100A*D*1*10** 111100A*D*1*11**
MOVX.W Da,@Ax+Ix MSW of Da→(Ax),Ax+Ix→Ax
Table 2.29 Double Data Transfer Instructions (Y Memory Data)
Instruction NOPY MOVY.W @Ay,Dy MOVY.W @Ay+,Dy Operation No Operation Code 111100*0*0*0**00 Cycles DC Bit 1 1 1 1 1 1 1 — — — — — — —
(Ay)→MSW of Dy,0→LSW of Dy 111100*A*D*0**01 (Ay)→MSW of Dy,0→LSW of Dy, 111100*A*D*0**10 Ay+2→Ay
MOVY.W @Ay+Iy,Dy (Ay)→MSW of Dy,0→LSW of Dy, 111100*A*D*0**11 Ay+Iy→Ay MOVY.W Da,@Ay MOVY.W Da,@Ay+ MSW of Da→(Ay) MSW of Da→(Ay),Ay+2→Ay 111100*A*D*1**01 111100*A*D*1**10 111100*A*D*1**11
MOVY.W Da,@Ay+Iy MSW of Da→(Ay),Ay+Iy→Ay
Rev. 2.00, 03/05, page 90 of 884
Table 2.30 Single Data Transfer Instructions
Instruction MOVS.W @-As,Ds MOVS.W @As,Ds MOVS.W @As+,Ds MOVS.W @As+Ix,Ds MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.W Ds,@As+Is MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L @As+Is,Ds MOVS.L Ds,@-As MOVS.L Ds,@As MOVS.L Ds,@As+ MOVS.L Ds,@As+Is Note: * Operation As–2→As,(As)→MSW of Ds,0→LSW of Ds (As)→MSW of Ds,0→LSW of Ds (As)→MSW of Ds,0→LSW of Ds, As+2→As (As)→MSW of Ds,0→LSW of Ds, As+Ix→As As–2→As,MSW of Ds→(As)* MSW of Ds→(As)* MSW of Ds→(As)*,As+2→As MSW of Ds→(As)*,As+Is→As As–4→As,(As)→Ds (As)→Ds (As)→Ds,As+4→As (As)→Ds,As+Is→As As–4→As,Ds→(As)* Ds→(As)* Ds→(As)*,As+4→As Ds→(As)*,As+Is→As Code 111101AADDDD0000 111101AADDDD0100 111101AADDDD1000 111101AADDDD1100 111101AADDDD0001 111101AADDDD0101 111101AADDDD1001 111101AADDDD1101 111101AADDDD0010 111101AADDDD0110 111101AADDDD1010 111101AADDDD1110 111101AADDDD0011 111101AADDDD0111 111101AADDDD1011 111101AADDDD1111 Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DC Bit — — — — — — — — — — — — — — — —
When guard bit registers A0G and A1G are specified for the source operand Ds, data is sign-extended before being transferred.
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Table 2.31 shows the correspondence between the DSP data transfer operands and registers. CPU core registers are used as pointer addresses indicating memory addresses. Table 2.31 Correspondence between DSP Data Transfer Operands and Registers
SH (CPU Core) Registers Operand Ax Ix (Is) Dx Ay Iy Dy Da As Ds R2 (As2) — — — — — — — Yes — R3 (As3) — — — — — — — Yes — R4 (Ax0) (As0) Yes — — — — — — Yes — R5 (Ax1) (As0) Yes — — — — — — Yes — R6 (Ay0) — — — Yes — — — — — R7 (Ay1) — — — Yes — — — — — R8 (Ix) (Is) — Yes — — — — — — — R9 (Iy) — — — — Yes — — — —
R0 — — — — — — — — —
R1 — — — — — — — — —
Operand Ax Ix (Is) Dx Ay Iy Dy Da As Ds
DSP Registers X0 — — Yes — — — — — Yes X1 — — Yes — — — — — Yes Y0 — — — — — Yes — — Yes Y1 — — — — — Yes — — Yes M0 — — — — — — — — Yes M1 — — — — — — — — Yes A0 — — — — — — Yes — Yes A1 — — — — — — Yes — Yes A0G — — — — — — — — Yes A1G — — — — — — — — Yes
Note: Yes indicates that the register can be set.
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2.5.3
DSP Operation Instruction Set
DSP operation instructions are digital signal processing instructions processed by the DSP unit. These instructions use 32-bit instruction codes, and multiple instructions are executed in parallel. The instruction codes are divided into an A field and a B field; parallel data transfer instructions are designated in the A field, and single or double data operation instructions are designated in the B field. Instructions can be independently designated and execution can also be carried out independently. A parallel data transfer instruction designated in the A field is exactly the same as a double data transfer instruction. The B field data operation instructions are divided into three groups: double data operation instructions, conditional single data operation instructions, and unconditional single data operation instructions. Table 2.32 lists the instruction formats of the DSP operation instructions. Each of the operands can be independently selected from the DSP registers. Table 2.33 shows the correspondence between the DSP operation instruction operands and registers. Table 2.32 DSP Operation Instruction Formats
Classification Double data operation instructions (6 operands) Conditional single data operation instructions 3 operands Instruction Forms ALUop. Sx, Sy, Du MLTop. Se, Sf, Dg ALUop. Sx, Sy, Dz DCT ALUop. Sx, Sy, Dz DCF ALUop. Sx, Sy, Dz 2 operands ALUop. Sx, Dz DCT ALUop. Sx, Dz DCF ALUop. Sx, Dz ALUop. Sy, Dz DCT ALUop. Sy, Dz DCF ALUop. Sy, Dz 1 operand ALUop. Dz DCT ALUop. Dz DCF ALUop. Dz Unconditional single data operation instructions 3 operands 2 operands ALUop. Sx, Sy, Du MLTop. Se, Sf, Dg ALUop. Sx, Dz ALUop. Sy, Dz ALUop. Sx, Sy 1 operand ALUop. Dz PSHA #imm, PSHL #imm Rev. 2.00, 03/05, page 93 of 884 PADDC, PSUBC, PMULS PCMP, PABS, PRND PCLR, PSHA #imm, PSHL #imm PCOPY, PDEC, PDMSB, PINC, PLDS, PSTS, PNEG Instruction PADD PMULS, PSUB PMULS PADD, PAND, POR, PSHA, PSHL, PSUB, PXOR
Table 2.33 Correspondence between DSP Instruction Operands and Registers
ALU and BPU Instructions Register A0 A1 M0 M1 X0 X1 Y0 Y1 Sx Yes Yes — — Yes Yes — — Sy — — Yes Yes — — Yes Yes Dz Yes Yes Yes Yes Yes Yes Yes Yes Du Yes Yes — — Yes — Yes — Se — Yes — — Yes Yes Yes — Multiplication Instructions Sf — Yes — — Yes — Yes Yes Dg Yes Yes Yes Yes — — — —
When writing parallel instructions, write the B field instructions first, then write the A field instructions:
PADD A0,M0,A0 PMULS X0,Y0,M0 DCF PINC X1,A1 PCMP X1,M0 MOVX.W @R4+,X0 MOVX.W A0,@R5+R8 MOVX.W @R4+R8 MOVY.W @R6+,Y0[;] MOVY.W @R7+,Y0[;] [NOPY][;]
Text in brackets ([]) can be omitted. The no operation instructions NOPX and NOPY can be omitted. Semicolons (;) are used to demarcate instruction lines, but can be omitted. If semicolons are used, the space after the semicolon can be used for comments. The individual status codes (DC, N, Z, V, GT) of the DSR register are always updated by unconditional ALU operation instructions and shift operation instructions. Conditional instructions do not update the status codes, even if the conditions have been met. Multiplication instructions also do not update the status codes. DC bit definitions are determined by the specifications of the CS bits in the DSR register. Table 2.34 lists the DSP operation instructions by classification.
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Table 2.34 Classification of DSP Instructions
Classification ALU arithmetic operation ALU fixed decimal point operation instructions Instruction Operation Types Code Function 11 PABS PADD PADD PMULS PADDC PCLR PCMP PCOPY PNEG PSUB PSUB PMULS PSUBC ALU integer operation instructions MSB detection instruction Rounding operation instruction ALU logical operation instructions 2 1 1 3 PDEC PINC PDMSB PRND PAND POR PXOR Fixed decimal point multiplication instruction Shift Arithmetic shift operation instruction Logical shift operation instruction System control instructions 1 1 1 2 PMULS PSHA PSHL PLDS PSTS Total 23 Absolute value operation Addition Addition and signed multiplication Addition with carry Clear Compare Copy Invert sign Subtraction Subtraction and signed multiplication Subtraction with borrow Decrement Increment MSB detection Rounding Logical AND Logical OR Logical exclusive OR Signed multiplication Arithmetic shift Logical shift System register load Store from system register Total 78 1 4 4 12 6 2 9 12 No. of Instructions 28
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2.5.4
Various Operation Instructions
ALU Arithmetic Operation Instructions: Tables 2.35 to 2.44 list various operation instructions. Table 2.35 ALU Fixed Point Operation Instructions
Instruction PABS Sx,Dz Operation If Sx≥0,Sx→Dz If Sx channel 1) (Initial value)
Round-robin (Top priority shifts to bottom after each transfer. The priority for the first DMA transfer after a reset is channel 1 > channel 0)
Bit 2—Address Error Flag Bit (AE): This flag indicates that an address error has occurred in the DMAC. When the AE bit is set to 1, DMA transfer cannot be enabled even if the DE bit in the DMA channel control register (CHCR) is set to 1. To clear the AE bit, read 1 from it and then write 0. Operation is performed up to the DMAC transfer being executed when the address error occurred. AE is initialized to 0 by a reset and in standby mode. It retains its value when the module standby function is used.
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Bit 2: AE 0 1
Description No DMAC address error To clear the AE bit, read 1 from it and then write 0 Address error by DMAC (Initial value)
Bit 1—NMI Flag Bit (NMIF): This flag indicates that an NMI interrupt has occurred. When the NMIF bit is set to 1, DMA transfer cannot be enabled even if the DE bit in the DMA channel control register (CHCR) and the DME bit are set to 1. To clear the NMIF bit, read 1 from it and then write 0. Operation is completed up to the end of the DMAC transfer being executed when NMI was input. When the NMI interrupt is input while the DMAC is not operating, the NMIF bit is set to 1. The NMIF bit is initialized to 0 by a reset or in the standby mode. It retains its value when the module standby function is used.
Bit 1: NMIF 0 1 Description No NMIF interrupt To clear the NMIF bit, read 1 from it and then write 0 NMIF interrupt has occurred (Initial value)
Bit 0—DMA Master Enable Bit (DME): Enables or disables DMA transfers on all channels. A DMA transfer becomes enabled when the DE bit in the CHCR and the DME bit are set to 1. For this to be effective, the TE bit in CHCR and the NMIF and AE bits must all be 0. When the DME bit is cleared, all channel DMA transfers are aborted. DME is initialized to 0 by a reset and in standby mode. It retains its value when the module standby function is used.
Bit 0: DME 0 1 Description DMA transfers disabled on all channels DMA transfers enabled on all channels (Initial value)
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11.3
Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority; when the transfer-end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip module request. A transfer can be in either single address mode or dual address mode. The bus mode can be either burst or cycle-steal. 11.3.1 DMA Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (TCR), DMA channel control registers (CHCR), DMA vector number registers (VCRDMA), DMA request/response selection control registers (DRCR), and DMA operation register (DMAOR) are initialized (initializing sets each register so that ultimately the condition (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0) is satisfied), the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0) 2. When a transfer request occurs and transfer is enabled, the DMAC transfers 1 transfer unit of data. (In auto-request mode, the transfer begins automatically after register initialization. The TCR value will be decremented by 1.) The actual transfer flows vary depending on the address mode and bus mode. 3. When the specified number of transfers have been completed (when TCR reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt request is sent to the CPU. 4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit in CHCR or the DME bit in DMAOR is changed to 0. Figure 11.2 shows a flowchart illustrating this procedure.
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Start Initial settings (SAR, DAR, TCR, CHCR, VCRDMA, DRCR, DMAOR)
DE, DME = 1 and NMIF, AE, TE = 0? Yes Has a transfer request been generated?*1 Yes
No
No *3
*2 Bus mode, transfer request mode, DREQ detection method?
Transfer TCR-1 → TCR, SAR, and DAR updated *4 No TCR = 0? Yes DEI interrupt request (when IE = 1) NMIF = 1, or AE = 1, or DE = 0, or DME = 0? Yes TE = 1 TE = 1 16-byte transfer in progress? *5
NMIF = 1, No or AE = 1, or DE = 0, or DME = 0? Yes No Transfer aborted
End transfer
End normally
Notes: 1. In auto-request mode, the transfer will start when the NMIF, AE, and TE bits are all 0 and the DE and DME bits are then set to 1. 2. Cycle-steal mode. 3. In burst mode, DREQ = edge detection (external request), or auto-request mode in burst mode. 4. 16-byte transfer cycle in progress. 5. End of a 16-byte transfer cycle.
Figure 11.2 DMA Transfer Flow
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11.3.2
DMA Transfer Requests
DMA transfer requests are usually generated in either the data transfer source or destination, but they can also be generated by devices that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. The request mode is selected with the AR bit in DMA channel control registers 0 and 1 (CHCR0, CHCR1) and the RS0, RS1, RS2, RS3 and RS4 bits in DMA request/response selection control registers 0 and 1 (DRCR0, DRCR1). Table 11.3 Selecting the DMA Transfer Request Using the AR and RS Bits
CHCR AR 0 RS4 0 RS3 0 DRCR RS2 0 1 1 0 1 RS1 0 0 1 0 1 0 1 1 1 0 0 1 1 1 Note: * * * Don’t care 0 * 0 1 0 1 0 1 * 0 1 0 1 0 * Auto-request mode 0 1 RS0 0 1 0 1 0 Request Mode Module request mode Resource Selection DREQ (external request) SCIF channel 1 RXI SCIF channel 1 TXI SCIF channel 2 RXI SCIF channel 2 TXI TPU TGI0A TPU TGI0B TPU TGI0C TPU TGI0D SIO channel 0 RDFI SIO channel 0 TDEI SIO channel 1 RDFI SIO channel 1 TDEI SIO channel 2 RDFI SIO channel 2 TDEI
Auto-Request Mode: When there is no transfer request signal from an external source (as in a memory-to-memory transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits in CHCR0 and CHCR1 and the DME bit in the DMA operation register (DMAOR) are set to 1, the transfer begins (so long as the TE bits in CHCR0 and CHCR1 and the NMIF and AE bits in DMAOR are all 0).
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External Request Mode: In this mode a transfer is started by a transfer request signal (DREQn) from an external device. Choose one of the modes shown in table 11.4 according to the application system. When DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon input of a DREQn signal. Table 11.4 Selecting External Request Modes with the TA and AM Bits
CHCR TA 0 AM 0 1 1 0 Transfer Address Mode Dual address mode Dual address mode Single address mode Single address mode
Acknowledge Mode DACKn output in read cycle DACKn output in write cycle Data transferred from memory to device Data transferred from device to memory
Source Any* Any*
Destination Any* Any*
External memory or External device memory-mapped with DACK external device External device with DACK External memory or memorymapped external device
1
Note:
*
External memory, memory-mapped external device, and on-chip peripheral module (excluding DMAC, BSC, UBC, cache memory, E-DMAC, and EtherC).
Choose to detect DREQn either by the falling edge or by level using the DS and DL bits in CHCR0 and CHCR1 (DS = 0 is level detection, DS = 1 is edge detection; DL = 0 is active-low, DL = 1 is active-high). The source of the transfer request does not have to be the data transfer source or destination. When 0 (level detection) is set to the DS bit of CHCR0 and CHCR1, set the TB bit to 0 (cyclesteal mode) and set the TS1 and TS0 bits of CHCR0 and CHCR1 to either 00 (byte unit), 01 (word unit), or 10 (long word unit). When 0 is set to the DS bit of CHCR0 and CHCR1, when 1 (burst mode) is set to the TB bit of CHCR0 and CHCR1, and when 11 (16 byte unit) is set to the TS1 and TS0 bits of CHCR1 and CHCR1, operation is not guaranteed.
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Table 11.5 Selecting the External Request Signal with the DS and DL Bits
CHCR DS 0 1 DL 0 1 0 1 External Request Low-level detection (can only be set in cycle-steal mode) High-level detection (can only be set in cycle-steal mode) Falling-edge detection Rising-edge detection
On-Chip Module Request Mode: In this mode, transfers are started by a transfer request signal (interrupt request signal) from an on-chip peripheral module. Transfer request signals include SCIF and SIO receive-data-full interrupts (RXI, RDFI), SCIF and SIO transmit-data-empty interrupts (TXI, TDEI), and TPU general registers (table 11.6). If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), DMA transfer starts upon input of a transfer request signal. When RXI or RDFI (transfer request due to an SCIF or SIO receive-data-full condition) is set as a transfer request, the transfer source must be the receive data register of the corresponding module (SCFRDR or SIRDR). When TXI or TDEI (transfer request due to an SCIF or SIO transmit-dataempty condition) is set as a transfer request, the transfer destination must be the transmit data register of the corresponding module (SCFTDR or SITDR). These restrictions do not apply to TPU transfer requests. When on-chip module request mode is used, an access size permitted by the peripheral module register used as the transfer source or transfer destination must be set in bits TS1 and TS0 of CHCR0 and CHCR1.
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Table 11.6 Selecting On-Chip Peripheral Module Request Mode with the AR and RS Bits
DMA DMA Transfer Transfer Request Request Signal RS4 RS3 RS2 RS1 RS0 Source 0 0 1 0 1 1 0 0 1 1 0 1 0 1 0 0 SCIF channel 1 RXI receiver SCIF channel 1 TXI transmitter SCIF channel 2 RXI receiver SCIF channel 2 TXI transmitter TPU channel 0A TGI0A Transfer* Transfer* Destination Source SCFRDR1 Any Any
AR 0
Bus Mode Cyclesteal
DREQ Setting Edge, active-low Edge, active-low Edge, active-low Edge, active-low Edge, active-low
SCFTDR1 Cyclesteal Cyclesteal
SCFRDR2 Any Any Any (excluding on-chip RAM) Any (excluding on-chip RAM) Any (excluding on-chip RAM) Any (excluding on-chip RAM) SIRDR0 Any SIRDR1 Any SIRDR2 Any
SCFTDR2 Cyclesteal CycleAny (excluding steal on-chip RAM) CycleAny (excluding steal on-chip RAM) CycleAny (excluding steal on-chip RAM) CycleAny (excluding steal on-chip RAM) Any SITDR0 Any SITDR1 Any SITDR2 Cyclesteal Cyclesteal Cyclesteal Cyclesteal Cyclesteal Cyclesteal
1
TPU channel 0B
TGI0B
Edge, active-low
1
0
TPU channel 0C
TGI0C
Edge, active-low
1
TPU channel 0D
TGI0D
Edge, active-low
1
0
0
0 1
1 0 1 0 1 0
SIO channel 0 receiver SIO channel 0 transmitter SIO channel 1 receiver SIO channel 1 transmitter SIO channel 2 receiver SIO channel 2 transmitter
RDFI TDEI RDFI TDEI RDFI TDEI
Edge, active-low Edge, active-low Edge, active-low Edge, active-low Edge, active-low Edge, active-low
1
0 1
1
0
0 1
Note:
*
Do not perform transfers between on-chip peripheral modules.
Rev. 2.00, 03/05, page 484 of 884
For outputting transfer request from the SCIF, SIO, and TPU, the corresponding interrupt enable bits must be set to output the interrupt signals. Note that transfer request signals from on-chip peripheral modules (interrupt request signals) are sent not just to the DMAC but to the CPU as well. When an on-chip peripheral module is specified as the transfer request source, set the priority level values in the interrupt priority level registers (IPRC to IPRE) of the interrupt controller (INTC) at or below the levels set in the I3 to I0 bits of the CPU’s status register so that the CPU does not accept the interrupt request signal. With the DMA transfer request signals in table 11.6, when DMA transfer is performed a DMA transfer request (interrupt request) from any module will be cleared at the first transfer. 11.3.3 Channel Priorities
When the DMAC receives simultaneous transfer requests on two channels, it selects a channel according to a predetermined priority order. There is a choice of two priority modes, fixed or round-robin. The mode is selected by the priority bit, PR, in the DMA operation register (DMAOR). Fixed Priority Mode: In this mode, the relative channel priority levels are fixed. When PR is set to 0, channel 0 has higher priority than channel 1. Figure 11.3 shows an example of a transfer in burst mode.
DREQ0 DREQ1 Channel 0 destination CPU CPU CPU Channel 0 source Channel 0 source Channel 1 source Channel 0 destination Channel 1 destination
Bus cycle
Figure 11.3 Fixed Mode DMA Transfer in Burst Mode (Dual Address, DREQn Falling-Edge Detection) In cycle-steal mode, once a channel 0 request is accepted, channel 1 requests are also accepted until the next request is accepted, which makes more effective use of the bus cycle. If requests come simultaneously for channel 0 and channel 1 when DMA operation is starting, the first is transmitted with channel 0, and thereafter channel 1 and channel 0 transfers are performed alternately.
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DREQ0 DREQ1 Channel 0 source CPU CPU CPU Channel 0 destination CPU Channel 1 destination Channel 1 source Channel 0 source CPU
Bus cycle
Figure 11.4 Fixed Mode DMA Transfer in Cycle-Steal Mode (Dual Address, DREQn Low-Level Detection) Round-Robin Mode: Switches the priority of channel 0 and channel 1, shifting their ability to receive transfer requests. Each time one transfer ends on one channel, the priority shifts to the other channel. The channel on which the transfer just finished is assigned low priority. After reset, channel 1 has higher priority than channel 0. Figure 11.5 shows how the priority changes when channel 0 and channel 1 transfers are requested simultaneously and another channel 0 transfer is requested after the first two transfers end. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 1 and 0. 2. Channel 1 has the higher priority, so the channel 1 transfer begins first (channel 0 waits for transfer). 3. When the channel 1 transfer ends, channel 1 becomes the lower-priority channel. 4. The channel 0 transfer begins. 5. When the channel 0 transfer ends, channel 0 becomes the lower-priority channel. 6. A channel 0 transfer is requested. 7. The channel 0 transfer begins. 8. When the channel 0 transfer ends, channel 0 is already the lower-priority channel, so the order remains the same.
Rev. 2.00, 03/05, page 486 of 884
Transfer requests 1. Requests occur in channels 0 and 1
Waiting channel
DMAC operation 2. Channel 1 transfer starts
Channel priority order
1>0 Priority changes
0 3. Channel 1 transfer ends
0>1
4. Channel 0 transfer starts None 5. Channel 0 transfer ends Priority changes
1>0
6. Request occurs in channel 0 None
7. Channel 0 transfer starts
Waiting for transfer request
8. Channel 0 transfer ends
Priority does not change
1>0
Figure 11.5 Channel Priority in Round-Robin Mode
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11.3.4
DMA Transfer Types
It can operate in single address mode or dual address mode, as defined by how many bus cycles the DMAC takes to access the transfer source and transfer destination. The actual transfer operation timing varies with the DMAC bus mode used: cycle-steal mode or burst mode. The DMAC supports all the transfers shown in table 11.7. Table 11.7 Supported DMA Transfers
Destination External Device with DACK Not available Single Single Not available Not available External Memory Single Dual Dual Dual* Dual On-Chip Memory-Mapped Peripheral External Device Module Single Dual Dual Dual* Dual On-Chip Memory
Source External device with DACK External memory Memory-mapped external device On-chip peripheral module On-chip memory
Not available Not available Dual* Dual* Dual* Dual* Dual Dual Dual* Dual
Single: Single address mode Dual: Dual address mode Note: * Access size permitted by peripheral module register used as transfer source or transfer destination (excluding DMAC, BSC, UBC, cache memory, E-DMAC, and EtherC).
Address Modes: • Single Address Mode In single address mode, both the transfer source and destination are external; one (selectable) is accessed by a DACKn signal while the other is accessed by address. In this mode, the DMAC performs the DMA transfer in one bus cycle by simultaneously outputting a transfer request acknowledge DACKn signal to one external device to access it, while outputting an address to the other end of the transfer. Figure 11.6 shows an example of a transfer between external memory and external device with DACK. That data is written in external memory in the same bus cycle while the external device outputs data to the data bus.
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External address bus External data bus This LSI DMAC External memory
External device with DACK
DACKn DREQn : Data flow
Figure 11.6 Data Flow in Single Address Mode Two types of transfers are possible in single address mode: 1) transfers between external devices with DACK and memory-mapped external devices; and 2) transfers between external devices with DACK and external memory. For both of them, transfer must be requested by the external request signal (DREQn). For the combination of the specifiable setting to perform data transfer using an external request (DREQn), see table 11.9. Figure 11.7 shows the DMA transfer timing for single address mode.
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CKIO A24–A0 CS WE D31–D0 DACKn BS a. External device with DACK to external memory space CKIO A24–A0 CS RD D31–D0 DACKn BS b. External memory space to external device with DACK Address output to external memory space Read strobe signal to external memory space Data output from external memory space DACK signal (active low) to external device with DACK Write strobe signal to external memory space Data output from external device with DACK DACK signal (active low) to external device with DACK Address output to external memory space
Figure 11.7 DMA Transfer Timing in Single Address Mode • Dual Address Mode In dual address mode, both the transfer source and destination are accessed (selectable) by address. The source and destination can be located externally or internally. The DMAC accesses the source in the read cycle and the destination in the write cycle, so the transfer is performed in two separate bus cycles. The transfer data is temporarily stored in the DMAC. Figure 11.8 shows an example of a transfer between two external memories in which data is read from one external memory in the read cycle and written to the other external memory in the following write cycle.
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External data bus This LSI DMAC 2 External memory
External memory 1
: Data flow 1: Read cycle 2: Write cycle
Figure 11.8 Data Flow in Dual Address Mode In dual address mode transfers, external memory and memory-mapped external devices can be mixed without restriction. Specifically, this enables transfers between the following: Transfer between external memory and external memory Transfer between external memory and memory-mapped external device Transfer between memory-mapped external device and memory-mapped external device Transfer between external memory and on-chip peripheral module (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC)*
Transfer between memory-mapped external device and on-chip peripheral module (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC)* Transfer between on-chip memory and on-chip memory Transfer between on-chip memory and memory-mapped external device Transfer between on-chip memory and on-chip peripheral module (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC)* Transfer between on-chip memory and external memory Transfer between on-chip peripheral module (excluding DMAC, BSC, UBC, cache, EDMAC, and EtherC) and on-chip peripheral module (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC)* Note: * Access size permitted by peripheral module register used as transfer source or transfer destination (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC).
Rev. 2.00, 03/05, page 491 of 884
Transfer requests can be auto-request, external requests, or on-chip peripheral module requests. If the transfer request source is the SCIF or SIO, an SCIF or SIO register, respectively, must be the transfer destination or transfer source (see table 11.6). For the combination of the specifiable setting to perform data transfer using an external request (DREQn), see table 11.9. Dual address mode outputs DACKn in either the read cycle or write cycle. The acknowledge/transfer mode bit (AM) of the DMA channel control registers 0 and 1 (CHCR0 and 1) specifies whether DACK is output in either the read cycle or the write cycle. Figure 11.9 shows the DMA transfer timing in dual address mode.
CKIO A24–A0 CS RD WE D31–D0 DACKn BS Read strobe signal to external memory space Write strobe signal to external memory space I/O data of external memory space DMAC acknowledge signal (active-low) Address output to external memory space
Figure 11.9 DMA Transfer Timing in Dual Address Mode (External Memory Space → External Memory Space, DACKn Output in Read Cycle)
Rev. 2.00, 03/05, page 492 of 884
Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode with the TB bits in CHCR0 and CHCR1. • Cycle-Steal Mode In cycle-steal mode, the bus right is given to another bus master each time the DMAC completes one transfer. When another transfer request occurs, the bus right is retrieved from the other bus master and another transfer is performed for one transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. (in the case of 16-byte transfer in dual address mode, the DMAC continues to hold the bus) Cycle-steal mode can be used with all categories of transfer destination, transfer source, and transfer request source. (with the exception of transfers between on-chip peripheral modules) The CPU may take the bus twice when an acknowledge signal is output during the write cycle or in single address mode. Figure 11.10 shows an example of DMA transfer timing in cyclesteal mode. The transfer conditions for the example in the figure are as shown below. When the transfer request source is an external request mode with level detection in the cyclesteal mode, set the TS1 and TS0 bits of CHCR0 and CHCR1 to either 00 (byte unit), 01 (word unit), or 01 (longword unit). If the TS1 and TS0 bits of CHCR0 and CHCR1 are set to 11 (16byte transfer), operation is not guaranteed.
• Dual address mode • DREQn level detection DREQn Bus right returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read Write CPU DMAC Read DMAC Write CPU
Figure 11.10 DMA Transfer Timing in Cycle-Steal Mode (Dual Address Mode, DREQn Low Level Detection)
Rev. 2.00, 03/05, page 493 of 884
• Burst Mode In burst mode, once the DMAC gets the bus, the transfer continues until the transfer end condition is satisfied. When external request mode is used with level detection of the DREQ pin, however, negating DREQ will pass the bus to the other bus master after completion of the bus cycle of the DMAC that currently has an acknowledged request, even if the transfer end conditions have not been satisfied. When the transfer request source is an on-chip peripheral module, however, cycle-steal mode is always used. Figure 11.11 shows an example of DMA transfer timing in burst mode. The transfer conditions for the example in the figure are as shown below.
• Single address mode • DREQn level detection DREQn
Bus cycle
CPU
CPU
CPU
DMAC DMAC DMAC DMAC
CPU
CPU
CPU
Figure 11.11 DMA Transfer Timing in Burst Mode (Single Address, DREQn Falling-Edge Detection) Refreshes cannot be performed during a burst transfer, so ensure that the number of transfers satisfies the refresh request period when a memory requiring refreshing is used. When the transfer request source is an external request (DREQn) in burst mode, set the DS bit of CHCR0 and CHCR1 to 1 (edge detection). If the DS bits of CHCR0 and CHCR1 are set to 0 (level detection), operation is not guaranteed.
Rev. 2.00, 03/05, page 494 of 884
Relationship of Request Modes and Bus Modes by DMA Transfer Category: Table 11.8 shows the relationship between request modes, bus modes, etc., by DMA transfer category. Table 11.8 Relationship of Request Modes and Bus Modes by DMA Transfer Category
Address Mode Transfer Range Single Between external memory and external device with DACK Between external device with DACK, and memory mapped external device Dual Between external memories Request Mode*3 External External Bus Transfer Mode*7 Size (Byte) B/C B/C 1/2/4/16*8 1/2/4/16*8
External Automatic
1 Internal peripheral module*
B/C B/C C B/C B/C C B/C B/C C B/C B/C C B/C B/C
2
1/2/4/16*8 1/2/4/16 1/2/4 1/2/4/16*8 1/2/4/16 1/2/4 1/2/4/16*8 1/2/4/16 1/2/4 1/2/4*4 1/2/4*4 1/2/4*4 1/2/4*4 1/2/4*4 1/2/4*4 1/2/4/16 1/2/4/16*8 1/2/4/16 1/2/4
Between external memory and memory mapped external device Between memory mapped external devices
External Automatic Internal peripheral module*1 External Automatic Internal peripheral module*1
Between external memory and internal peripheral module
External Automatic Internal peripheral module*2
Between memory mapped external device and internal peripheral module Between internal memories Between internal memory and memory mapped external 5 device*
External Automatic Internal peripheral module* Automatic External Automatic Internal peripheral module*1
C B/C B/C B/C C
Rev. 2.00, 03/05, page 495 of 884
Address Mode Transfer Range Dual Between internal memory and internal peripheral module
Request Mode*3 External Automatic Internal peripheral module*2
Bus Transfer Mode*7 Size (Byte) B/C B/C C B/C B/C C B/C B/C
2
1/2/4*4 1/2/4*4 1/2/4*4 1/2/4/16*8 1/2/4/16 1/2/4 1/2/4*4 1/2/4*4 1/2/4*4
Between internal memory and external memory*6
External Automatic Internal peripheral module*1
Between internal peripheral modules
External Automatic Internal peripheral module*
C
Notes: B: Burst mode C: Cycle steal mode 1. For on-chip peripheral module requests, do not specify SCIF and SIO as a transfer request source. 2. When the transfer request source is SCIF or SIO, the transfer source or transfer destination must be SCIF and SIO, respectively. 3. When the request mode is set to internal peripheral module request, set the DS bit and the DL bit of CHCR0 and CHCR1 to 1 and 0, respectively (detection at the falling edge of DREQn). In addition, the bus mode can only be set to cycle-steal mode. 4. Specify the access size that is allowed by the internal peripheral-module registers, which are a transfer source or a transfer destination. 5. When transferring data from internal memory to a memory mapped external device, set DACKn to write-time output. When transferring from a memory mapped external device to internal memory, set DACKn to read-time output. 6. When transferring data from internal memory to external memory, set DACKn to writetime output. When transferring from external memory to internal memory, set DACKn to read-time output. 7. When B (burst mode) is set in the external request mode, set the DS bits of CHCR0 and CHCR1 to 1 (edge detection). If they are set to 0 (level detection), operation cannot be guaranteed. 8. Transfer in units of 16 bytes is enabled only when edge detection has been specified. If transfer is attempted in units of 16 bytes when level detection has been specified, operation cannot be guaranteed.
Rev. 2.00, 03/05, page 496 of 884
Table 11.9 shows the combinations of request mode, bus mode, and address mode that can be specified in the external request mode. Table 11.9 Combinations of Request Mode, Bus Mode, and Address Mode Specifiable in the External Request Mode
Dual Address Mode Request Mode External request Level detection*1 Byte Word Longword 16-byte unit Edge detection*2 Byte Word Longword 16-byte unit Burst Mode — — — — O O O O Cycle-Steal Mode O O O — O O O O Single Address Mode Burst Mode — — — — O O O O Cycle-Steal Mode O O O — O O O O
Notes: O: Can be set —: Cannot be set 1. The same for high-level and low-level detection. 2. The same for rising-edge detection and falling-edge detection.
Bus Mode and Channel Priority: When a given channel (1) is transferring in burst mode and there is a transfer request to a channel (0) with a higher priority, the transfer of the channel with higher priority (0) will begin immediately. When channel 0 is also operating in the burst mode, the channel 1 transfer will continue as soon as the channel 0 transfer has completely finished. When channel 0 is in cycle-steal mode, channel 1 will begin operating again after channel 0 completes the transfer of one transfer unit, but the bus will then switch between the two in the order channel 1, channel 0, channel 1, channel 0. Since channel 1 is in burst mode, it will not give the bus to the CPU. This example is illustrated in figure 11.12.
Bus state
CPU
DMAC ch1 DMAC ch1 DMAC ch0 DMAC ch1 DMAC ch1 DMAC ch0 DMAC ch1 DMAC ch1 DMAC ch0 DMAC ch1 DMAC ch1 ch0 ch1 ch0 DMAC ch1/ch0 bus right transfers ch1 ch0
CPU
CPU
DMAC ch1 Burst mode
DMAC ch1 Burst mode
CPU
Figure 11.12 Bus Status when Multiple Channels are Operating (when priority order is ch0 > ch1, ch1 is set to burst mode, and ch0 to cycle-steal mode)
Rev. 2.00, 03/05, page 497 of 884
11.3.5
Number of Bus Cycles
The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus master. For details, see section 7, Bus State Controller (BSC). 11.3.6 DMA Transfer Request Acknowledge Signal Output Timing
DMA transfer request acknowledge signal DACKn is output synchronous to the DMA address output specified by the channel control register AM bit of the address bus. Normally, the acknowledge signal becomes valid when DMA address output begins, and becomes invalid 0.5 cycles before the address output ends. (See figure 11.13.) The output timing of the acknowledge signal varies with the settings of the connected memory space. The output timing of acknowledge signals in the memory spaces is shown in figure 11.13.
Clock
DACKn (Active high)
0.5 cycles CPU DMAC
Address bus
Figure 11.13 Example of DACKn Output Timing Acknowledge Signal Output when External Memory Is Set as Ordinary Memory Space: The timing at which the acknowledge signal is output is the same in the DMA read and write cycles specified by the AM bit (figures 11.14 and 11.15). When DMA address output begins, the acknowledge signal becomes valid; 0.5 cycles before address output ends, it becomes invalid. If a wait is inserted in this period and address output is extended, the acknowledge signal is also extended.
Rev. 2.00, 03/05, page 498 of 884
T1 Clock
TW
T2
DACKn (Active high) DMAC read CPU Basic timing
0.5 cycles Invalid write DMAC write CPU DMAC read 1 wait inserted
Address bus
Figure 11.14 DACKn Output in Ordinary Space Accesses (AM = 0)
Clock
DACKn (Active high) Address bus DMAC read Invalid DMAC write write CPU Basic timing DMAC read 1 wait inserted Invalid write DMAC write
Figure 11.15 DACKn Output in Ordinary Space Accesses (AM = 1) In a longword access of a 16-bit external device (figure 11.16) or an 8-bit external device (figure 11.17), or a word access of an 8-bit external device (figure 11.18), the lower and upper addresses are output 2 and 4 times in each DMAC access in order to align the data. For all of these addresses, the acknowledge signal becomes valid simultaneous with the start of output and the signal becomes invalid 0.5 cycles before the address output ends. When multiple addresses are output in a single access to align data for synchronous DRAM, DRAM, or burst ROM, an acknowledge signal is output to those addresses as well.
Rev. 2.00, 03/05, page 499 of 884
Clock
DACKn (Active high) Address bus
*1 *2
Invalid write DMAC write
CPU H
DMAC read H
DMAC read L
Basic timing Notes: 1. H: MSB side 2. L: LSB side
Figure 11.16 DACKn Output in Ordinary Space Accesses (AM = 0, Longword Access to 16-Bit External Device)
Clock
DACKn (Active high) Address bus DMAC read HH CPU Basic timing DMAC read HL DMAC read LH DMAC read LL
Figure 11.17 DACKn Output in Ordinary Space Accesses (AM = 0, Longword Access to 8-Bit External Device)
Clock
DACKn (Active high) Address bus
Invalid write CPU DMAC read H DMAC read L DMAC write
Basic timing
Figure 11.18 DACKn Output in Ordinary Space Accesses (AM = 0, Word Access to 8-Bit External Device)
Rev. 2.00, 03/05, page 500 of 884
Acknowledge Signal Output when External Memory Is Set as Synchronous DRAM: When external memory is set as synchronous DRAM, DACKn output becomes valid simultaneously with the start of the DMA address, and becomes invalid when the address output ends. When external memory is set as synchronous DRAM auto-precharge and AM = 0, the acknowledge signal is output across the row address, read command, wait and read address of the DMAC read (figure 11.19). Since the synchronous DRAM read has only burst mode, during a single read an invalid address is output; the acknowledge signal, however, is output on the same timing (figure 11.20). At this time, the acknowledge signal is extended until the write address is output after the invalid read. A synchronous DRAM burst read is performed in the case of 16-byte transfer. As 16-byte transfer is enabled only in auto-request mode and in external request mode with edge detection, when using on-chip peripheral module requests or external request mode with level detection, byte, word, or longword should be set as the transfer unit. Operation is not guaranteed if a 16-byte unit is set when using on-chip peripheral module requests or external request mode with level detection. When AM = 1, the acknowledge signal is output across the row address and column address of the DMAC write (figure 11.21).
Clock
DACKn (Active high)
Read command Row address
Address bus
CPU
Read 1
Read 2
Read 3
Read 4
DMAC read (basic timing)
Figure 11.19 DACKn Output in Synchronous DRAM Burst Read (Auto-Precharge, AM = 0)
Rev. 2.00, 03/05, page 501 of 884
Clock
DACKn (Active high)
Address bus
Read command Row address CPU Read Invalid read
Row Column address address
DMAC read (basic timing)
DMAC write (basic timing)
Figure 11.20 DACKn Output in Synchronous DRAM Single Read (Auto-Precharge, AM = 0)
Clock
DACKn (Active high) Row Column address address Address bus DMAC write (basic timing)
Figure 11.21 DACKn Output in Synchronous DRAM Write (Auto-Precharge, AM = 1)
Rev. 2.00, 03/05, page 502 of 884
When external memory is set as bank active synchronous DRAM, during a burst read the acknowledge signal is output across the read command, wait and read address when the row address is the same as the previous address output (figure 11.22). When the row address is different from the previous address, the acknowledge signal is output across the precharge, row address, read command, wait and read address (figure 11.23).
Clock
DACKn (Active high) Read command Address bus CPU Read 1 Read 2 Read 3 Read 4
DMAC read (basic timing)
Figure 11.22 DACKn Output in Synchronous DRAM Burst Read (Bank Active, Same Row Address, AM = 0)
Clock
DACKn (Active high) PreRead Row charge address command CPU DMAC read (basic timing) Read 1 Read 2 Read 3 Read 4
Address bus
Figure 11.23 DACKn Output in Synchronous DRAM Burst Read (Bank Active, Different Row Address, AM = 0)
Rev. 2.00, 03/05, page 503 of 884
When external memory is set as bank active synchronous DRAM, during a single read the acknowledge signal is output across the read command, wait and read address when the row address is the same as the previous address output (figure 11.24). When the row address is different from the previous address, the acknowledge signal is output across the precharge, row address, read command, wait and read address (figure 11.25). Since the synchronous DRAM read has only burst mode, during a single read an invalid address is output; the acknowledge signal is output on the same timing. At this time, the acknowledge signal is extended until the write address is output after the invalid read.
Clock
DACKn (Active high) Address bus
Read command CPU Read Invalid read
Row Column address address
DMAC read (basic timing)
DMAC write (basic timing)
Figure 11.24 DACKn Output in Synchronous DRAM Single Read (Bank Active, Same Row Address, AM = 0)
Clock
DACKn (Active high) Address bus
Row address PreRead charge command Read CPU DMAC read (basic timing) Invalid read
Row Column address address
DMAC write (basic timing)
Figure 11.25 DACKn Output in Synchronous DRAM Single Read (Bank Active, Different Row Address, AM = 0)
Rev. 2.00, 03/05, page 504 of 884
When external memory is set as bank active synchronous DRAM, during a write the acknowledge signal is output across the wait and column address when the row address is the same as the previous address output (figure 11.26). When the row address is different from the previous address, the acknowledge signal is output across the precharge, row address, wait and column address (figure 11.27).
Clock
DACKn (Active high) Column address
Address bus
DMAC write (basic timing)
Figure 11.26 DACKn Output in Synchronous DRAM Write (Bank Active, Same Row Address, AM = 1)
Clock
DACKn (Active high) Row Column Precharge address address Address bus DMAC write (basic timing)
Figure 11.27 DACKn Output in Synchronous DRAM Write (Bank Active, Different Row Address, AM = 1)
Rev. 2.00, 03/05, page 505 of 884
• Synchronous DRAM one-cycle write When a one-cycle write is performed to synchronous DRAM, the DACKn signal is synchronized with the rising edge of the clock. A request by the request signal is accepted while the clock is high during DACKn output.
Transfer Width Transfer bus mode Transfer address mode Byte/Word/Longword Transfer*1 Cycle-steal mode*2 Single mode DREQn Detection Method DACKn output timing Bus cycle Level Detection Write DACK Basic bus cycle
Notes: 1. Do not set a 16-byte unit; operation is not guaranteed if this setting is made. 2. Cycle-steal mode must be set when DREQ is level-detected.
Clock
Bus cycle
CPU
CPU
DMAC1
CPU
DMAC2
CPU
DMAC3 CPU
DREQn (Active high)
Blind zone
1st acceptance 2nd acceptance 3rd acceptance 4th acceptance
....
DACKn (Active high) RAS
DACK1
DACK2
DACK3
CAS
RD/WR
WEn/DQMxx
Figure 11.28 (a) Synchronous DRAM One-Cycle Write Timing
Transfer Width Transfer bus mode Transfer address mode Note: * Byte/Word/Longword Transfer Burst mode Single mode DREQn Detection Method DACKn output timing Bus cycle Edge Detection* Write DACK Basic bus cycle
Edge detection must be set when burst mode is selected as the transfer bus mode.
Rev. 2.00, 03/05, page 506 of 884
Clock
Bus cycle
CPU
CPU
DMAC1
DMAC2 DMAC3 DMAC4
CPU
CPU
DREQn (Active high) DACKn (Active high) RAS
Blind zone
Acceptance
....
DACK1
DACK2
DACK3
DACK4
CAS
RD/WR
WEn/DQMxx
Figure 11.28 (b) Synchronous DRAM One-Cycle Write Timing Acknowledge Signal Output when External Memory Is Set as DRAM: When external memory is set as DRAM and a row address is output during a read or write, the acknowledge signal is output across the row address and column address (figures 11.29 to 11.31).
Clock
DACKn (Active high) Address bus
Row Precharge address Column address DMAC read or write (basic timing)
Figure 11.29 DACKn Output in Normal DRAM Accesses (AM = 0 or 1)
Rev. 2.00, 03/05, page 507 of 884
Clock DACKn (Active high) Address bus Column address
DMAC read or write (basic timing)
Figure 11.30 DACKn Output in DRAM Burst Accesses (Same Row Address, AM = 0 or 1)
Clock
DACKn (Active high) PreRow charge address Address bus Column address DMAC read or write (basic timing)
Figure 11.31 DACKn Output in DRAM Burst Accesses (Different Row Address, AM = 0 or 1)
Rev. 2.00, 03/05, page 508 of 884
Acknowledge Signal Output When External Memory Is Set as Burst ROM: When external memory is set as burst ROM, the acknowledge signal is output synchronous to the DMA address (no dual writes allowed) (figure 11.32).
Clock
DACKn (Active high) Address bus DMAC cycle DMAC cycle
DMAC (1 wait state)
Figure 11.32 DACKn Output in Nibble Accesses of Burst ROM 11.3.7 DREQn Pin Input Detection Timing
In external request mode, DREQn pin signals are usually detected at the falling edge of the clock pulse (CKIO). When a request is detected, a DMAC bus cycle is produced four cycles later at the earliest and a DMA transfer performed. After the request is detected, the timing of the next input detection varies with the bus mode, address mode, DREQn input detection, and the memory connected. DREQn Pin Input Detection Timing in Cycle-Steal Mode: In cycle-steal mode, once a request is detected from the DREQn pin, the request signal is not detected until DACKn signal output in the next external bus cycle. In cycle-steal mode, request detection is performed from DACKn signal output until a request is detected. Once a request has been accepted, it cannot be canceled midway. The timing from the detection of a request until the next time requests are detectable is shown below. • Cycle-Steal Mode Edge Detection When transfer control is performed using edge detection, perform DREQn/DACKn handshaking as shown in figure 11.33, and perform DREQn input control so that there is a one-to-one relationship between DREQn and DACKn. Operation is not guaranteed if DREQn is input before the corresponding DACKn is output. If the DACKn signal is output a number of times, the first DACKn signal for the input DREQn signal indicates the request acceptance start timing, and subsequently each clock edge is sampled.
Rev. 2.00, 03/05, page 509 of 884
Clock
Bus cycle DREQn (Rising-edge detection) DACKn (Active high)
CPU 1st acceptance
CPU
DMAC 2nd acceptance
DMAC
CPU
CPU
DMAC 3rd acceptance
DMAC
Figure 11.33 DREQn/DACKn Handshaking • Edge Detection—1/2/4-Byte Transfer
Transfer Width Transfer bus mode Transfer address mode Byte/Word/Longword Cycle-steal mode Dual/single mode DREQn Detection Method DACKn output timing Bus cycle Edge Detection Read DACK/write DACK Basic bus cycle
Clock
Bus cycle
CPU
CPU
DMAC
CPU
DREQn (Active high) DACKn (Active high)
Blind zone 1st acceptance 2nd acceptance
Requests acceptable
Figure 11.34 DREQn Pin Input Detection Timing in Cycle-Steal Mode with Edge Detection
Rev. 2.00, 03/05, page 510 of 884
Clock
Bus cycle
CPU
CPU
DMAC H
DMAC L
DREQn (Active high)
Blind zone 1st 2nd acceptance acceptance
DACKn (Active high)
DACK H
DACK L
Figure 11.35 When a16-Bit External Device is Connected (Edge Detection)
Clock
Bus cycle
CPU
CPU
DMAC HH
DMAC HL
DMAC LH
DMAC LL
DREQn (Active high)
Blind zone 1st 2nd acceptance acceptance
DACK HH DACK HL DACK LH DACK LL
Blind zone
DACKn (Active high)
Figure 11.36 When an 8-Bit External Device is Connected (Edge Detection)
Rev. 2.00, 03/05, page 511 of 884
• Cycle-Steal Mode Edge Detection—16-Bit Transfer With 16-byte transfer, the first request signal is the first transfer request, and the second transfer request is accepted when the next request signal is accepted. The third and fourth requests are accepted in the same way.
Transfer Width Transfer bus mode Transfer address mode 16-Byte Transfer Cycle-steal mode Dual/single mode DREQn Detection Method DACKn output timing Bus cycle Edge Detection Read DACK/write DACK Basic bus cycle
Clock
Bus cycle
CPU
CPU
DMAC*1 DMAC*2 DMAC*3 DMAC*4
DMA
DREQn (Active high)
Blind zone 2nd 1st acceptance acceptance
DACKn (Active high) Note: * n is the nth 16-byte transfer.
DACK*1
DACK*2 DACK*3 DACK*4
Figure 11.37 DREQn Pin Input Detection Timing in Cycle-Steal Mode with Edge Detection (16-Byte Transfer Setting)
Rev. 2.00, 03/05, page 512 of 884
• Cycle-Steal Mode Level Detection In level detection mode, too, a request cannot be canceled once accepted.
Transfer Width Transfer bus mode Transfer address mode Note: * Byte/Word/Longword* Cycle-steal mode Dual/single mode DREQn Detection Method DACKn output timing Bus cycle Level Detection Read DACK/write DACK Basic bus cycle
Do not set a 16-byte unit; operation is not guaranteed if this setting is made.
Clock
Bus cycle
CPU
CPU
DMAC
CPU
DREQn (Active high) 1st acceptance DACKn (Active high)
Blind zone
Blind zone 2nd acceptance
Requests acceptable
Figure 11.38 DREQn Pin Input Detection Timing in Cycle-Steal Mode with Level Detection (Byte/Word/Longword Setting)
Clock
Bus cycle
CPU
CPU
DMAC H
DMAC L
DREQn (Active high)
Blind zone 1st acceptance
Blind zone 2nd acceptance
DACKn (Active high)
DACK H
DACK L
Figure 11.39 When a 16-Bit External Device is Connected (Level Detection)
Rev. 2.00, 03/05, page 513 of 884
Clock
Bus cycle
CPU
CPU
DMAC HH
DMAC HL
DMAC LH
DMAC LL
DREQn (Active high)
Blind zone 1st acceptance
Blind zone 2nd acceptance
DACKn (Active high)
DACK HH
DACK HL
DACK LH
DACK LL
Figure 11.40 When an 8-Bit External Device is Connected (Level Detection) DREQn Pin Input Detection Timing in Burst Mode: In burst mode, only edge detection is valid for DREQn input. Operation is not guaranteed if level detection is set. With edge detection of DREQn input, once a request is detected, DMA transfer continues until the transfer end condition is satisfied, regardless of the state of the DREQn pin. Request detection is not performed during this time. When the transfer start conditions are fulfilled after the end of transfer, request detection is performed again every cycle.
Clock
Bus cycle
CPU
CPU
DMAC1
DMAC2
DMAC3
DMAC4
CPU
Bus DREQn (Active high) DACKn (Active high)
Blind zone Acceptance
Figure 11.41 DREQn Pin Input Detection Timing in Burst Mode with Edge Detection
Rev. 2.00, 03/05, page 514 of 884
11.3.8
DMA Transfer End
The DMA transfer ending conditions vary when channels end individually and when both channels end together. Conditions for Channels Ending Individually: When either of the following conditions is met, the transfer will end in the relevant channel only: The DMA transfer count register (TCR) value becomes 0. The DMA enable bit (DE) of the DMA channel control register (CHCR) is cleared to 0. • Transfer end when TCR = 0 When the TCR value becomes 0, the DMA transfer for that channel ends and the transfer-end flag bit (TE) is set in CHCR. If the IE (interrupt enable) bit has already been set, a DMAC interrupt (DEI) request is sent to the CPU. For 16-byte transfer, set the number of transfers × 4. Operation is not guaranteed if an incorrect value is set. A 16-byte transfer is valid only in auto-request mode or in external request mode with edge detection. When using an external request with level detection or on-chip peripheral module request, do not specify a 16-byte transfer. • Transfer end when DE = 0 in CHCR When the DMA enable bit (DE) in CHCR is cleared, DMA transfers in the affected channel are halted. The TE bit is not set when this happens. Conditions for Both Channels Ending Simultaneously: Transfers on both channels end when either of the following conditions is met: The NMIF (NMI flag) bit or AE (address error flag) bit in DMAOR is set to 1. The DMA master enable (DME) bit is cleared to 0 in DMAOR. • Transfer end when NMIF = 1 or AE = 1 in DMAOR When an NMI interrupt or DMAC address error occurs and the NMIF or AE bit is set to 1 in DMAOR, all channels stop their transfers. The DMA source address register (SAR), destination address register (DAR), and transfer count register (TCR) are all updated by the transfer immediately preceding the halt. When this transfer is the final transfer, TE = 1 and the transfer ends. To resume transfer after NMI interrupt exception handling or address error exception handling, clear the appropriate flag bit. When the DE bit is then set to 1, the transfer on that channel will restart. To avoid this, keep its DE bit at 0. In dual address mode, DMA transfer will be halted after the completion of the following write cycle even when the address error occurs in the initial read cycle. SAR, DAR and TCR are updated by the final transfer. • Transfer end when DME = 0 in DMAOR Clearing the DME bit in DMAOR forcibly aborts the transfers on both channels at the end of the current bus cycle. When the transfer is the final transfer, TE = 1 and the transfer ends.
Rev. 2.00, 03/05, page 515 of 884
Purpose of New Specifications for : When the SH7615 is connected to the PCI bus as an external bus, Grew logic must be used externally because the SH7615 is not equipped with a PCI bus interface. The PCI bus uses burst transfer principally, and performance is poor if data is transferred in small increments. Due to these properties of the PCI bus, it is necessary to use Grew logic externally to compare the present address and the next address and determine whether burst transfer is possible. However, the size of the external Grew logic increases if address comparisons are required, and there is also the possibility that delays may interfere with timing requirements. have therefore been updated in order to solve these problems. Now if The specifications for burst transfer is possible using the present address this information is passed to the external Grew logic. This provides enhanced support for PCI bus connections. Pin: is output from only when the 16-byte transfer mode Register Settings When Using is selected using the DMAC built into the SH7615. However, it is not output when SDRAM or DRAM are accessed. When using the 16-byte transfer mode, specify auto-request mode or the external request mode with edge detection. If external request mode with level detection or onchip module request mode is specified, operation is not guaranteed. To use , the settings for the CHCR0 register or CHCR1 register in the on-chip DMAC of the SH7615 must be as shown in figure 11.43. is not output unless the settings for the CHCR0 register or CHCR1 register are as indicated in figure 11.42.
Bit 31 Bit name — Setting 0 Bit 15 Bit name DM1 Setting 0 30 — 0 14 DM0 1 29 28 27 26 25 — — — — — 0 0 0 0 0 13 12 11 10 9 SM1 SM0 TS1 TS0 AR 0 1 1 1 *
16-byte unit (four long words transferred) Source address is incremented Destination address is incremented
Rev. 2.00, 03/05, page 516 of 884
HB
Figure 11.42 Register Settings When Using
HB
HB
HB
HB
HB
HB
HB
11.3.9
Pin Output Timing
24 — 0 8 AM *
23 — 0 7 AL *
22 — 0 6 DS *
21 — 0 5 DL *
20 — 0 4 TB *
19 — 0 3 TA *
18 — 0 2 IE *
17 — 0 1 TE *
16 — 0 0 DE 1
DMA transfer allowed * Don't care
External bus cycle BH
CPU
DMAC read 0
DMAC read 1
DMAC read 2
DMAC read 3
DMAC write 0
11.4
11.4.1
Usage Examples
Example of DMA Data Transfer Between On-chip SCIF and External Memory
In this example data received by the serial communication interface (SCIF) with on-chip FIFO is sent to external memory using DMAC channel 1. Table 11.9 lists the transfer conditions and register setting values. Table 11.9 Transfer Conditions and Register Setting Values for Data Transfer Between On-chip SCIF and External Memory
Transfer Condition Transfer source: SCFRDR1 in on-chip SCIF Transfer destination: External memory (word space) Number of transfers: 64 Transfer destination address: Increment Transfer source address: Fixed Bus mode: Cycle-steal Transfer unit: Byte DEI interrupt request at end of transfer DE = 1 Channel priority: Fixed (0 > 1) DME = 1 DMAOR H'0001 H'05 Transfer request source (transfer request signal): SCIF DRCR1 (RXI) Register SAR1 DAR1 TCR1 CHCR1 Setting Value H'FFFFFCCC Transfer destination address H'0040 H'4045
Note: Make sure the SCIF settings have interrupts enabled and the appropriate CPU interrupt level.
HB
Figure 11.43 Summary of
Output Timing
HB
HB
Summary of
Timing: Figure 11.43 is a summary of the
output timing.
DMAC write 1
DMAC write 2
DMAC write 3
CPU
Rev. 2.00, 03/05, page 517 of 884
11.5
Usage Notes
1. DMA request/response selection control registers 0 and 1 (DRCR0 and DRCR1) should be accessed in bytes. All other registers should be accessed in longword units. 2. Before rewriting the registers in the DMAC (CHCR0, CHCR1, DRCR0, DRCR1), first clear the DE bit to 0 in the CHCR register for the specified channel, or clear the DME bit in DMAOR to 0. 3. When the DMAC is not operating, the NMIF bit in DMAOR is set even when an NMI interrupt is input. 4. The DMAC cannot access the cache memory. 5. Before changing the frequency or changing to standby mode, set the DME bit of DMAOR to 0 and stop operation of the DMAC. 6. Do not use the DMAC, BSC, UBC, E-DMAC, and EtherC for on-chip peripheral module transfers. 7. Do not access the cache (address array, data array, associative purge area). 8. Note that when level detection of the request signal is used in single address mode, the request signal may be detected before DACKn is output. 9. When Eφ exceeds 31.25 MHz, do not use transfer involving DACKn output on ordinary space for word or longword access with an 8-bit bus width, or longword access with a 16-bit bus width. 10. When DMA transfer is performed in response to a DMA transfer request signal from a peripheral module, if clearing of the DMA transfer request signal from the peripheral module by the DMA transfer is not completed before the next transfer request signal from that module, subsequent DMA transfers may not be possible.
Rev. 2.00, 03/05, page 518 of 884
11. The following restrictions apply when using dual address mode for 16-byte transfer in cyclesteal mode: a. When external request and level detection are set, do not input DREQn during cycles in which DACKn is not active after the start of DMA transfer.
Bus cycle DACKn (active high) DREQn (active high) * DACK output in read cycle CPU CPU DMA DMA DMA DMA DMA DMA DMA DMA CPU DMA DMA DMA DMA DMA DMA DMA DMA CPU (R) (R) (R) (R) (W) (W) (W) (W) (R) (R) (R) (R) (W) (W) (W) (W)
Bus cycle DACKn (active high) DREQn (active high)
CPU CPU DMA DMA DMA DMA DMA DMA DMA DMA CPU DMA DMA DMA DMA DMA DMA DMA DMA CPU (R) (R) (R) (R) (W) (W) (W) (W) (R) (R) (R) (R) (W) (W) (W) (W)
*
DACK output in write cycle Note: * In addition to CPU cycles, E-DMAC cycles may be inserted in some cases.
b. When external request DREQ edge detection is set, if DREQn is input continuously the DMAC continues to operate without insertion of a CPU cycle. (However, a CPU cycle will begin if there is no request from DREQn.)
Rev. 2.00, 03/05, page 519 of 884
12. DACKn output timing DACKn (n = 0 or 1) may be output with a wrong timing during 16-byte- or longword-unit DMA transfer to a 16-bit width ordinary space or during 16-byte-, longword-, or word-unit DMA transfer to an 8-bit width ordinary space. Correct timing:
T1 CKIO CSn RD Read D15 to 0 WEn Write D15 to 0 BS DACKn T2 T1 T2
Rev. 2.00, 03/05, page 520 of 884
Error timing 1:
T1 CKIO CSn RD Read D15 to 0/ D7 to 0 WEn Write D15 to 0/ D7 to 0 BS DACKn T2 T1 T2
Error timing 2:
T1 CKIO CSn RD Read D7 to 0 WEn Write D7 to 0 BS DACKn T2 T1 T2 T1 T2 T1 T2
Rev. 2.00, 03/05, page 521 of 884
DACKn (n = 0 or 1) assert timing and count:
Bus Width 16-bit bus width 8-bit bus width 16-Byte Unit Error timing 1 x 4 Error timing 2 x 4 Longword Unit Error timing 1 x 1 Error timing 2 x 1 Word Unit — Error timing 1 x 1
Conditions: When the following conditions are all satisfied, DACKn (n = 0 or 1) is output with a wrong timing. (1) Iφ:Eφ = 1:1 (2) DMA transfer to an ordinary space or burst ROM space (3) 16-byte or longword DMA transfer to a 16-bit width space or 16-byte, longword, or word DMA transfer to an 8-bit width space, which generates multiple bus cycles Countermeasures: This problem is avoided by any of the following countermeasures. (1) Specify a clock ratio except tEcyc:tPcyc 1:1. (2) Use 32-bit bus width. (3) When the bus width is 16 bits, perform word or byte DMA transfer. (4) When the bus width is 8 bits, perform byte DMA transfer. 13. DMAC does not perform DMA transfer on channel 1 by an on-chip peripheral module request Phenomenon: (1) DMAC does not perform DMA transfer on channel 1 by an on-chip peripheral module request. When channel 0 of the on-chip DMAC is set to cycle-steal mode and channel 1 is set to onchip peripheral module request mode, the DMAC may not perform DMA transfer on channel 1. Conditions: (1) Conditions for malfunction in DMA transfer on channel 1 by an on-chip peripheral module request When the following conditions are all satisfied, the DMAC does not perform DMA transfer on channel 1 by an on-chip peripheral module request. (a) DMAC channels 0 and 1 are both enabled. (b) DMAC channel 0 is set to cycle-steal mode. (c) DMAC channel 1 is set to cycle-steal mode, dual address mode, and on-chip peripheral module request mode. (d) Round-robin mode is specified as the DMAC priority mode.
Rev. 2.00, 03/05, page 522 of 884
Countermeasures: (1) Countermeasure against malfunction in DMA transfer on channel 1 by an on-chip peripheral module request This problem is avoided by the following countermeasure. (a) Set the DMAC priority mode to fixed priority mode. 14. DMAC does not perform DMA transfer between on-chip memory and on-chip peripheral module by an external request Phenomenon: (1) DMAC does not perform DMA transfer between on-chip memory and on-chip peripheral module by an external request. When the on-chip DMAC is set to external request (DREQ) mode and cycle-steal mode and DMA transfer is attempted between on-chip memory and on-chip peripheral module or between on-chip peripheral modules, the DMAC may not perform DMA transfer for the second and later DREQ inputs. Conditions: (1) Conditions for malfunction in DMA transfer between on-chip memory and on-chip peripheral module by an external request When the following conditions are all satisfied, the DMAC does not perform DMA transfer between on-chip memory and on-chip peripheral module or between on-chip peripheral modules by an external request. (a) The external request (DREQ) is selected for the transfer request source. (b) The DMA transfer between on-chip memory and on-chip peripheral module or between on-chip peripheral modules is selected. (c) Cycle-steal mode is used. Countermeasures: (1) Countermeasure against malfunction in DMA transfer between on-chip memory and onchip peripheral module by an external request This problem is avoided by the following counter measure. (a) Do not select the external request (DREQ) for the transfer request source. 15. Data bus collision during single-address DMAC transfer Phenomenon: (1) Data bus collision during DMA transfer in single address mode In the system which includes the SH7615, an external device with DACK, and synchronous DRAM (SDRAM), if single-address DMA transfer is performed from the external device with DACK to SDRAM immediately after the SH7615 writes data to SDRAM, the SH7615 may erroneously drive data bus during the single-address DMA transfer , and the erroneously driven data may collide with the DMA transfer data.
Rev. 2.00, 03/05, page 523 of 884
Conditions: (1) Conditions for data bus collision during single-address DMA transfer When the following conditions are all satisfied, a data bus collision occurs during singleaddress DMA transfer from the external device with DACK to SDRAM. (a) The clock ratio is set to external clock (Eφ):internal clock (Iφ) = 1:1. (b) SDRAM is used in single write mode. (c) Immediately after the SH7615 writes data to SDRAM, DMAC transfers data from the external device with DACK to SDRAM in single address mode. Countermeasures: (1) Countermeasure against data bus collision during single-address DMA transfer This problem is avoided by any of the following countermeasures. (a) Specify a clock ratio other than external clock (Eφ):internal clock (Iφ) = 1:1. (b) Do not write to SDRAM from CPU, Ethernet controller direct memory access controller (E-DMAC), or another channel of the DMAC during single-address DMA transfer from the external device with DACK to SDRAM. 16. DMAC DACK error output Phenomenon: (1) DACK error When DMAC channels 0 and 1 are both set to external request (DREQ0 and DREQ1) mode, the DMAC may execute DMA transfer with DACK1 output on channel 1 while the DREQ1 is not input. Conditions: (1) Conditions for DACK error When the following conditions are all satisfied, the DMAC executes DMA transfer with DACK1 output on channel 1 while the DREQ1 is not input. (a) DMAC channels 0 and 1 are both enabled. (b) DMAC channels 0 and 1 both select the external request (DREQ0 and DREQ1) for the transfer request source. (c) DMAC channels 0 and 1 are both set to cycle-steal mode. (d) Round-robin mode is specified as the DMAC priority mode. Countermeasures: (1) Countermeasure against DACK error This problem is avoided by any of the following countermeasures. (a) Set either DMAC channel 0 or 1 to burst mode. (b) Set the DMAC priority mode to fixed priority mode.
Rev. 2.00, 03/05, page 524 of 884
Section 12 16-Bit Free-Running Timer (FRT)
12.1 Overview
A single-channel, 16-bit free-running timer (FRT) is included on-chip. The FRT is based on a 16-bit free-running counter (FRC) and can output two types of independent waveforms. The FRT can also measure the width of input pulses and the cycle of external clocks. 12.1.1 Features
The FRT has the following features: • Choice of four counter input clocks The counter input clock can be selected from three internal clocks (Pφ/8, Pφ/32, Pφ/128) and an external clock (enabling external event counting). • Two independent comparators Two waveform outputs can be generated. • Input capture Choice of rising edge or falling edge • Counter clear specification The counter value can be cleared by compare match A. • Four interrupt sources Two compare match sources, one input capture source, and one overflow source can issue requests independently.
Rev. 2.00, 03/05, page 525 of 884
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the FRT.
Internal clock φ/8 φ/32 φ/128 Clock select Clock Compare match A FTOA FTOB FRC (H/L) Clear FTI Compare match B Comparator B
Bus interface
FTCI
OCRA (H/L)
Comparator A
Overflow
Internal data bus
Control logic
OCRB (H/L) Capture
FICR (H/L) FTCSR TIER TCR TOCR Module data bus
ICI OCIA OCIB OVI OCRA,B: FRC: FICR: FTCSR: TIER: TCR: TOCR:
Interrupt signals
Output compare registers A,B (16 bits) Free-running counter (16 bits) Input capture register (16 bits) Free-running timer control/status register (8 bits) Timer interrupt enable register (8 bits) Timer control register (8 bits) Timer output compare control register (8 bits)
Figure 12.1 FRT Block Diagram
Rev. 2.00, 03/05, page 526 of 884
12.1.3
Input/Output Pins
Table 12.1 lists FRT I/O pins and their functions. Table 12.1 Pin Configuration
Channel Counter clock input pin Output compare A output pin Output compare B output pin Input capture input pin Pin FTCI FTOA FTOB FTI I/O Input Output Output Input Function FRC counter clock input pin Output pin for output compare A Output pin for output compare B Input pin for input capture
12.1.4
Register Configuration
Table 12.2 shows the FRT register configuration. Table 12.2 Register Configuration
Register Timer interrupt enable register Free-running counter H Free-running counter L Output compare register A H Output compare register A L Output compare register B H Output compare register B L Timer control register Timer output compare control register Input capture register H Input capture register L Abbreviation TIER FRC H FRC L OCRA H OCRA L OCRB H OCRB L TCR TOCR FICR H FICR L R/W R/W R/(W)*1 R/W R/W R/W R/W R/W R/W R/W R/W R R Initial Value H'01 H'00 H'00 H'00 H'FF H'FF H'FF H'FF H'00 H'E0 H'00 H'00 Address HFFFFFE10 HFFFFFE11 HFFFFFE12 HFFFFFE13 HFFFFFE14*2 HFFFFFE15*2 HFFFFFE14*2 HFFFFFE15*2 HFFFFFE16 HFFFFFE17 HFFFFFE18 HFFFFFE19
Free-running timer control/status register FTCSR
Notes: Use byte-size access for all registers. 1. Bits 7 to 1 are read-only. The only value that can be written is a 0, which is used to clear flags. Bit 0 can be read or written. 2. OCRA and OCRB have the same address. The OCRS bit in TOCR is used to switch between them.
Rev. 2.00, 03/05, page 527 of 884
12.2
12.2.1
Register Descriptions
Free-Running Counter (FRC)
Bit: Initial value: R/W: 15 0 R/W 14 0 R/W 13 0 R/W … … … … 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0
FRC is a 16-bit read/write register. It increments upon input of a clock. The input clock can be selected using clock select bits 1 and 0 (CKS1, CKS0) in TCR. FRC can be cleared upon compare match A. When FRC overflows (H'FFFF → H'0000), the overflow flag (OVF) in FTCSR is set to 1. FRC can be read or written to by the CPU, but because it is 16 bits long, data transfers involving the CPU are performed via a temporary register (TEMP). See section 12.3, CPU Interface, for more detailed information. FRC is initialized to H'0000 by a reset, in standby mode, and when the module standby function is used. 12.2.2 Output Compare Registers A and B (OCRA and OCRB)
Bit: Initial value: R/W: 15 1 R/W 14 1 R/W 13 1 R/W … … … … 1 R/W 1 R/W 1 R/W 1 R/W 3 2 1 0
OCR is composed of two 16-bit read/write registers (OCRA and OCRB). The contents of OCR are always compared to the FRC value. When the two values are the same, the output compare flags in FTCSR (OCFA and OCFB) are set to 1. When the OCR and FRC values are the same (compare match), the output level values set in the output level bits (OLVLA and OLVLB) are output to the output compare pins (FTOA and FTOB). After a reset, FTOA and FTOB output 0 until the first compare match occurs. Because OCR is a 16-bit register, data transfers involving the CPU are performed via a temporary register (TEMP). See section 12.3, CPU Interface, for more detailed information. OCR is initialized to H'FFFF by a reset, in standby mode, and when the module standby function is used.
Rev. 2.00, 03/05, page 528 of 884
12.2.3
Input Capture Register (FICR)
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R … … … … 0 R 0 R 0 R 0 R 3 2 1 0
FICR is a 16-bit read-only register. When a rising edge or falling edge of the input capture signal (FTI pin) is detected, the current FRC value is transferred to FICR. At the same time, the input capture flag (ICF) in FTCSR is set to 1. The edge of the input signal can be selected using the input edge select bit (IEDG) in TCR. Because FICR is a 16-bit register, data transfers involving the CPU are performed via a temporary register (TEMP). See section 12.3, CPU Interface, for more detailed information. To ensure that the input capture operation is reliably performed, set the pulse width of the input capture input signal to six system clocks (Pφ) or more. FICR is initialized to H'0000 by a reset, in standby mode, and when the module standby function is used. 12.2.4 Timer Interrupt Enable Register (TIER)
Bit: Initial value: R/W: 7 ICIE 0 R/W 6 — 0 R 5 — 0 R 4 — 0 R 3 OCIAE 0 R/W 2 OCIBE 0 R/W 1 OVIE 0 R/W 0 — 1 R
TIER is an 8-bit read/write register that controls enabling of all interrupt requests. TIER is initialized to H'01 by a reset, in standby mode, and when the module standby function is used. Bit 7—Input Capture Interrupt Enable (ICIE): Selects enabling/disabling of the ICI interrupt request when the input capture flag (ICF) in FTCSR is set to 1.
Bit 7: ICIE 0 1 Description Interrupt request (ICI) caused by ICF disabled Interrupt request (ICI) caused by ICF enabled (Initial value)
Bits 6 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 529 of 884
Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects enabling/disabling of the OCIA interrupt request when the output compare flag A (OCFA) in FTCSR is set to 1.
Bit 3: OCIAE 0 1 Description Interrupt request (OCIA) caused by OCFA disabled Interrupt request (OCIA) caused by OCFA enabled (Initial value)
Bit 2—Output Compare Interrupt B Enable (OCIBE): Selects enabling/disabling of the OCIB interrupt request when the output compare flag B (OCFB) in FTCSR is set to 1.
Bit 2: OCIBE 0 1 Description Interrupt request (OCIB) caused by OCFB disabled Interrupt request (OCIB) caused by OCFB enabled (Initial value)
Bit 1—Timer Overflow Interrupt Enable (OVIE): Selects enabling/disabling of the OVI interrupt request when the overflow flag (OVF) in FTCSR is set to 1.
Bit 1: OVIE 0 1 Description Interrupt request (OVI) caused by OVF disabled Interrupt request (OVI) caused by OVF enabled (initial value)
Bit 0—Reserved: This bit is always read as 1. The write value should always be 1. 12.2.5 Free-Running Timer Control/Status Register (FTCSR)
Bit: Initial value: R/W: Note: * 7 ICF 0 R/(W)* 6 — 0 R 5 — 0 R 4 — 0 R 3 OCFA 0 R/(W)* 2 OCFB 0 R/(W)* 1 OVF 0 R/(W)* 0 CCLRA 0 R/W
For bits 7, and 3 to 1, the only value that can be written is 0 (to clear the flags).
FTCSR is an 8-bit register that selects counter clearing and controls interrupt request signals. FTCSR is initialized to H'00 by a reset, in standby mode, and when the module standby function is used. See section 12.4, Operation, for the timing. Bit 7—Input Capture Flag (ICF): Status flag that indicates that the FRC value has been sent to FICR by the input capture signal. This flag is cleared by software and set by hardware. It cannot be set by software.
Rev. 2.00, 03/05, page 530 of 884
Bit 7: ICF 0
Description [Clearing condition] When ICF is read while set to 1, and then 0 is written to it (Initial value)
1
[Setting condition] When the FRC value is sent to FICR by the input capture signal
Bits 6 to 4—Reserved: These bits always read 0. The write value should always be 0. Bit 3—Output Compare Flag A (OCFA): Status flag that indicates when the values of the FRC and OCRA match. This flag is cleared by software and set by hardware. It cannot be set by software.
Bit 3: OCFA 0 Description [Clearing condition] When OCFA is read while set to 1, and then 0 is written to it (Initial value) 1 [Setting condition] When the FRC value becomes equal to OCRA
Bit 2—Output Compare Flag B (OCFB): Status flag that indicates when the values of FRC and OCRB match. This flag is cleared by software and set by hardware. It cannot be set by software.
Bit 2: OCFB 0 Description [Clearing condition] When OCFB is read while set to 1, and then 0 is written to it (Initial value) 1 [Setting condition] When the FRC value becomes equal to OCRB
Bit 1—Timer Overflow Flag (OVF): Status flag that indicates when FRC overflows (from H'FFFF to H'0000). This flag is cleared by software and set by hardware. It cannot be set by software.
Bit 1: OVF 0 Description [Clearing condition] When OVF is read while set to 1, and then 0 is written to it (Initial value) 1 [Setting condition] When the FRC value changes from H'FFFF to H'0000
Rev. 2.00, 03/05, page 531 of 884
Bit 0—Counter Clear A (CCLRA): Selects whether or not to clear FRC on compare match A (signal indicating match of FRC and OCRA).
Bit 0: CCLRA 0 1 Description FRC clear disabled FRC cleared on compare match A (Initial value)
12.2.6
Timer Control Register (TCR)
Bit: Initial value: R/W: 7 IEDG 0 R/W 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 CKS1 0 R/W 0 CKS0 0 R/W
TCR is an 8-bit read/write register that selects the input edge for input capture and selects the input clock for FRC. TCR is initialized to H'00 by a reset, in standby mode, and when the module standby function is used. Bit 7—Input Edge Select (IEDG): Selects whether to capture the input capture input (FTI) on the falling edge or rising edge.
Bit 7: IEDG 0 1 Description Input captured on falling edge Input captured on rising edge (Initial value)
Bits 6 to 2—Reserved: These bits are always read as 0. The write value should always be 0. Bits 1 and 0—Clock Select (CKS1, CKS0): These bits select whether to use an external clock or one of three internal clocks for input to FRC. The external clock is counted at the rising edge.
Bit 1: CKS1 0 1 Bit 0: CKS0 0 1 0 1 Description Internal clock: count at φ/8 Internal clock: count at φ/32 Internal clock: count at φ/128 External clock: count at rising edge (Initial value)
Rev. 2.00, 03/05, page 532 of 884
12.2.7
Timer Output Compare Control Register (TOCR)
Bit: Initial value: R/W: 7 — 1 R 6 — 1 R 5 — 1 R 4 OCRS 0 R/W 3 — 0 R 2 — 0 R 1 OLVLA 0 R/W 0 OLVLB 0 R/W
TOCR is an 8-bit read/write register that selects the output level for output compare and controls switching between access of output compare registers A and B. TOCR is initialized to H'E0 by a reset, in standby mode, and when the module standby function is used. Bits 7 to 5—Reserved: These bits are always read as 1. The write value should always be 1. Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address. The OCRS bit controls which register is selected when reading/writing to this address. It does not affect the operation of OCRA and OCRB.
Bit 4: OCRS 0 1 Description OCRA register selected OCRB register selected (Initial value)
Bits 3 and 2—Reserved: These bits are always read as 0. The write value should always be 0. Bit 1—Output Level A (OLVLA): Selects the level output to the output compare A output pin upon compare match A (signal indicating match of FRC and OCRA).
Bit 1: OLVLA 0 1 Description 0 output on compare match A 1 output on compare match A (Initial value)
Bit 0—Output Level B (OLVLB): Selects the level output to the output compare B output pin upon compare match B (signal indicating match of FRC and OCRB).
Bit 0: OLVLB 0 1 Description 0 output on compare match B 1 output on compare match B (Initial value)
Rev. 2.00, 03/05, page 533 of 884
12.3
CPU Interface
FRC, OCRA, OCRB, and FICR are 16-bit registers. The data bus width between the CPU and FRT, however, is only 8 bits. Access of these three types of registers from the CPU therefore needs to be performed via an 8-bit temporary register called TEMP. The following describes how these registers are read from and written to: • Writing to 16-bit Registers The upper byte is written, which results in the upper byte of data being stored in TEMP. The lower byte is then written, which results in 16 bits of data being written to the register when combined with the upper byte value in TEMP. • Reading from 16-bit Registers The upper byte of data is read, which results in the upper byte value being transferred to the CPU. The lower byte value is transferred to TEMP. The lower byte is then read, which results in the lower byte value in TEMP being sent to the CPU. When registers of these three types are accessed, two byte accesses should always be performed, first to the upper byte, then the lower byte. If only the upper byte or lower byte is accessed, the data will not be transferred properly. Figure 12.2 and 12.3 show the flow of data when FRC is accessed. Other registers function in the same way. When reading OCRA and OCRB, however, both upper and lower-byte data is transferred directly to the CPU without passing through TEMP.
Rev. 2.00, 03/05, page 534 of 884
(Write to upper byte)
CPU (H'AA) upper byte
Data bus within module Bus interface
TEMP (H'AA)
FRC H ( ) (Write to lower byte) CPU (H'55) lower byte
FRC L ( )
Data bus within module Bus interface
TEMP (H'AA)
FRC H (H'AA)
FRC L (H'55)
Figure 12.2 FRC Access Operation (CPU Writes H'AA55 to FRC)
Rev. 2.00, 03/05, page 535 of 884
(Read from upper byte)
CPU (H'AA) upper byte
Data bus within module Bus interface
TEMP (H'55)
FRC H (H'AA) (Read from lower byte)
FRC L (H'55)
CPU (H'55) lower byte
Data bus within module Bus interface
TEMP (H'AA)
FRC H ( )
FRC L ( )
Figure 12.3 FRC Access Operation (CPU Reads H'AA55 from FRC)
Rev. 2.00, 03/05, page 536 of 884
12.4
12.4.1
Operation
FRC Count Timing
The FRC increments on clock input (internal or external). Internal Clock Operation: Set the CKS1 and CKS0 bits in TCR to select which of the three internal clocks created by dividing system clock φ (φ/8, φ/32, φ/128) is used. Figure 12.4 shows the timing.
Pφ Internal clock FRC input clock FRC N–1 N N+1
Figure 12.4 Count Timing (Internal Clock Operation) External Clock Operation: Set the CKS1 and CKS0 bits in TCR to select the external clock. External clock pulses are counted on the rising edge. The pulse width of the external clock must be at least 6 system clocks (φ). A smaller pulse width will result in inaccurate operation. Figures 12.5 shows the timing.
Pφ
External clock input pin FRC input clock FRC
N
N+1
Figure 12.5 Count Timing (External Clock Operation)
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12.4.2
Output Timing for Output Compare
When a compare match occurs, the output level set in the OLVL bit in TOCR is output from the output compare output pins (FTOA, FTOB). Figure 12.6 shows the timing for output of output compare A.
Pφ FRC N N N+1 N N N+1
OCRA Compare match A signal OLVLA Output compare A output pin FTOA
Clear*
Note: * ↓ Indicates instruction execution by software
Figure 12.6 Output Timing for Output Compare A 12.4.3 FRC Clear Timing
FRC can be cleared on compare match A. Figure 12.7 shows the timing.
Pφ Compare match A signal FRC N H'0000
Figure 12.7 Compare Match A Clear Timing
Rev. 2.00, 03/05, page 538 of 884
12.4.4
Input Capture Input Timing
Either the rising edge or falling edge can be selected for input capture input using the IEDG bit in TCR. Figure 12.8 shows the timing when the rising edge is selected (IEDG = 1).
Pφ
Input capture input pin Input capture signal
Figure 12.8 Input Capture Signal Timing (Normal) When the input capture signal is input when FICR is read (upper-byte read), the input capture signal is delayed by one cycle of Pφ. Figure 12.9 shows the timing.
FICR upper-byte read cycle Pφ
Input capture input pin Input capture signal
Figure 12.9 Input Capture Signal Timing (Input Capture Input when FICR is Read)
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12.4.5
Input Capture Flag (ICF) Setting Timing
Input capture input sets the input capture flag (ICF) to 1 and simultaneously transfers the FRC value to FICR. Figure 12.10 shows the timing.
Pφ
Input capture signal
ICF
FRC
N
FICR
N
Figure 12.10 ICF Setting Timing 12.4.6 Output Compare Flag (OCFA, OCFB) Setting Timing
The compare match signal output (when OCRA or OCRB matches the FRC value) sets output compare flag OCFA or OCFB to 1. The compare match signal is generated in the last state in which the values matched (at the timing for updating the count value that matched the FRC). After OCRA or OCRB matches the FRC, no compare match is generated until the next increment occurs. Figure 12.11 shows the timing for setting OCFA and OCFB.
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Pφ
FRC
N
N+1
OCRA, OCRB
N
Compare match signal
OCFA, OCFB
Figure 12.11 OCF Setting Timing 12.4.7 Timer Overflow Flag (OVF) Setting Timing
FRC overflow (from H'FFFF to H'0000) sets the timer overflow flag (OVF) to 1. Figure 12.12 shows the timing.
Pφ
FRC
H'FFFF
H'0000
Overflow signal
OVF
Figure 12.12 OVF Setting Timing
Rev. 2.00, 03/05, page 541 of 884
12.5
Interrupt Sources
There are four FRT interrupt sources of three types (ICI, OCIA/OCIB, and OVI). Table 12.3 lists the interrupt sources and their priorities after a reset is cleared. The interrupt enable bits in TIER are used to enable or disable the interrupt bits. Each interrupt request is sent to the interrupt controller independently. See section 5, Interrupt Controller (INTC), for more information about priorities and the relationship to interrupts other than those of the FRT. Table 12.3 FRT Interrupt Sources and Priorities
Interrupt Source ICI OCIA, OCIB OVI Description Interrupt by ICF Interrupt by OCFA or OCFB Interrupt by OVF Priority High ↑ ↓ Low
12.6
Example of FRT Use
Figure 12.13 shows an example in which pulses with a 50% duty factor and arbitrary phase relationship are output. The procedure is as follows: 1. Set the CCLRA bit in FTCSR to 1. 2. The OLVLA and OLVLB bits are inverted by software whenever a compare match occurs.
FRC H'FFFF OCRA OCRB H'0000 Counter clear
FTOA
FTOB
Figure 12.13 Example of Pulse Output
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12.7
Usage Notes
Note that the following contention and operations occur when the FRT is operating: 12.7.1 Contention between FRC Write and Clear
When a counter clear signal is generated with the timing shown in figure 12.14 during the write cycle for the lower byte of FRC, writing does not occur to the FRC, and the FRC clear takes priority.
FRC lower-byte write cycle Pφ
Address Internal write signal Counter clear signal
FRC address
FRC
N
H'0000
Figure 12.14 Contention between FRC Write and Clear
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12.7.2
Contention between FRC Write and Increment
When an increment occurs with the timing shown in figure 12.15 during the write cycle for the lower byte of FRC, no increment is performed and the counter write takes priority.
FRC lower-byte write cycle Pφ
Address
FRC address
Internal write signal FRC input clock
FRC
N Write data
M
Figure 12.15 Contention between FRC Write and Increment
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12.7.3
Contention between OCR Write and Compare Match
When a compare match occurs with the timing shown in figure 12.16, during the write cycle for the lower byte of OCRA or OCRB, the OCR write takes priority and the compare match signal is disabled.
FRC lower-byte write cycle Pφ
Address
OCR address
Internal write signal
FRC
N
N+1
OCR
N Write data
M
Compare match signal Disabled
Figure 12.16 Contention between OCR and Compare Match 12.7.4 Internal Clock Switching and Counter Operation
FRC will sometimes begin incrementing because of the timing of switching between internal clocks. Table 12.4 shows the relationship between internal clock switching timing (CKS1 and CKS0 bit rewrites) and FRC operation. When an internal clock is used, the FRC clock is generated when the falling edge of an internal clock (created by dividing the system clock (φ)) is detected. When a clock is switched to high before the switching and to low after switching, as shown in case 3 in table 12.4, the switchover is considered a falling edge and an FRC clock pulse is generated, causing FRC to increment. FRC may also increment when switching between an internal clock and an external clock.
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Table 12.4 Internal Clock Switching and FRC Operation
No. 1 Timing of Rewrite of CKS1 and CKS0 Bits Low-to-low switch
Clock before switching
FRC Operation
Clock after switching
FRC clock
FRC
N Rewrite of CKS bit
N+1
2
Low-to-high switch
Clock before switching
Clock after switching
FRC clock
FRC
N
N+1
N+2
Rewrite of CKS bit
Rev. 2.00, 03/05, page 546 of 884
No. 3
Timing of Rewrite of CKS1 and CKS0 Bits High-to-low switch
FRC Operation
Clock before switching
Clock after switching
FRC clock
FRC
N
N+1 Rewrite of CKS bit
N+2
4
High-to-high switch
Clock before switching
Clock after switching
FRC clock
FRC
N
N+1
N+2 Rewrite of CKS bit
Note: Because the switchover is considered a falling edge, FRC starts counting up.
12.7.5
Timer Output (FTOA, FTOB)
During a power-on reset, the timer outputs (FTOA, FTOB) will be unreliable until the oscillation stabilizes. The initial value is output after the oscillation settling time has elapsed.
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Section 13 Watchdog Timer (WDT)
13.1 Overview
A single-channel watchdog timer (WDT) is provided on-chip for monitoring system operations. If a system becomes uncontrolled and the timer counter overflows without being rewritten correctly ) is output externally. The WDT can simultaneously by the CPU, an overflow signal ( generate an internal reset signal for the entire chip. When this watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer operation, an interval timer interrupt is generated at each counter overflow. The WDT is also used when recovering from standby mode, in modifying a clock frequency, and in clock pause mode. 13.1.1 Features
The WDT includes the following features. • Can be switched between watchdog timer mode and interval timer mode. output in watchdog timer mode • The signal is output externally when the counter overflows, and a simultaneous internal reset of the chip can also be selected (either a power-on reset or manual reset can be specified). • Interrupt generation in interval timer mode An interval timer interrupt is generated when the counter overflows. • Used when standby mode is cleared or the clock frequency is changed, and in clock pause mode. • Choice of eight counter input clocks
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13.1.2
Block Diagram
Figure 13.1 shows a block diagram of the WDT.
ITI (Interrupt request signal)
Overflow Interrupt control Clock Clock select
WDTOVF Internal reset signal*
Reset control
φ/4 φ/128 φ/256 φ/512 φ/1024 φ/2048 φ/8192 φ/16384 Internal clock
RSTCSR
WTCNT
WTCSR
Module bus WDT φ: See figure 3.1, Block Diagram of Clock Pulse Generator Circuit. WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter RSTCSR: Reset control/status register
Bus interface
Note: The internal reset signal can be generated by a register setting. The type of reset can be selected (power-on or manual reset).
Figure 13.1 WDT Block Diagram 13.1.3 Input/Output Pin
Table 13.1 shows the pin configuration. Table 13.1 Pin Configuration
Pin Watchdog timer overflow Abbreviation I/O Output Function Outputs the counter overflow signal in watchdog timer mode
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Interna bus
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13.1.4
Register Configuration
Table 13.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 13.2 Register Configuration
Address Name Abbreviation R/W R/(W)*3 R/W R/(W)*3 Initial Value H'18 H'00 H'1E Write *1 Read*2 H'FFFFFE80 H'FFFFFE81 H'FFFFFE83
Watchdog timer WTCSR control/status register Watchdog timer counter Reset control/status register WTCNT RSTCSR
H'FFFFFE80 H'FFFFFE80 H'FFFFFE82
Notes: 1. Write by word access. It cannot be written by byte or longword access. 2. Read by byte access. The correct value cannot be read by word or longword access. 3. Only 0 can be written in bit 7 to clear the flag.
13.2
13.2.1
Register Descriptions
Watchdog Timer Counter (WTCNT)
Bit: Initial value: R/W: 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
WTCNT is an 8-bit read/write register. The method of writing to WTCNT differs from that of most other registers to prevent inadvertent rewriting. See section 13.2.4, Notes on Register Access, for details. When the timer enable bit (TME) in the watchdog timer control/status register (WTCSR) is set to 1, the watchdog timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in WTCSR. When the value of WTCNT overflows (changes from H'FF to H'00), a watchdog timer overflow signal ( ) or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/ bit in WTCSR. WTCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0. It is not initialized in standby mode, when the clock frequency is changed, or in clock pause mode.
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TI FVOTDW
13.2.2
Watchdog Timer Control/Status Register (WTCSR)
Bit: Initial value: R/W: 7 OVF 0 R/(W)* 6 0 5 TME 0 R/W 4 — 1 R 3 — 1 R 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
R/W
Note:
*
The method of writing to WTCSR differs from that of most other registers to prevent inadvertent rewriting. See section 13.2.4, Notes on Register Access, for details.
The watchdog timer control/status register (WTCSR) is an 8-bit read/write register. Its functions include selecting the timer mode and clock source. Bits 7 to 5 are initialized to 000 by a reset, in standby mode, when the clock frequency is changed, and in clock pause mode. Bits 2 to 0 are initialized to 000 by a reset, but are not initialized in standby mode, when the clock frequency is changed, or in clock pause mode. Bit 7—Overflow Flag (OVF): Indicates that WTCNT has overflowed from H'FF to H'00 in interval timer mode. It is not set in watchdog timer mode.
Bit 7: OVF 0 1 Description No overflow of WTCNT in interval timer mode Cleared by reading OVF, then writing 0 in OVF WTCNT overflow in interval timer mode (Initial value)
Bit 6—Timer Mode Select (WT/ ): Selects whether to use the WDT as a watchdog timer or interval timer. When WTCNT overflows, the WDT either generates an interval timer interrupt signal, depending on the mode selected. (ITI) or generates a
TI
Bit 6: WT/ 0 1
Description Interval timer mode: interval timer interrupt (ITI) request to the CPU when WTCNT overflows (Initial value) Watchdog timer mode: signal output externally when WTCNT overflows. Section 13.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when WTCNT overflows in watchdog timer mode
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WT/
TI
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Bit 5—Timer Enable (TME): Enables or disables the timer.
Bit 5: TME 0 1 Description Timer disabled: WTCNT is initialized to H'00 and count-up stops (Initial value)
Bits 4 and 3—Reserved: These bits are always read as 1. The write value should always be 1. Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources for input to WTCNT. The clock signals are obtained by dividing the frequency of the system clock (φ).
Description Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source 0 0 1 1 0 1 Note: * 0 1 0 1 0 1 0 1 φ/4 (Initial value) φ/128 φ/256 φ/512 φ/1024 φ/2048 φ/8192 φ/16384 Overflow Interval* (φ = 60 MHz) 17.0 µs 544 µs 1.1 ms 2.2 ms 4.4 ms 8.7 ms 34.8 ms 69.6 ms
The overflow interval listed is the time from when the WTCNT begins counting at H'00 until an overflow occurs.
13.2.3
Reset Control/Status Register (RSTCSR)
Bit: Initial value: R/W: 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 — 1 R 3 — 1 R 2 — 1 R 1 — 1 R 0 — 0 R
Note:
*
Only 0 can be written in bit 7, to clear the flag.
RSTCSR is an 8-bit read/write register that controls output of the reset signal generated by watchdog timer counter (WTCNT) overflow and selects the internal reset signal type. The method of writing to RSTCSR differs from that of most other registers to prevent inadvertent rewriting. See section 13.2.4, Notes on Register Access, for details. RSTCR is initialized to H'1E by input of
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Timer enabled: WTCNT starts counting. A is generated when WTCNT overflows
signal or interrupt
a reset signal from the pin, but is not initialized by the internal reset signal generated by overflow of the WDT. It is initialized to H'1E in standby mode, and in clock pause mode. Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed (from H'FF to H'00) in watchdog timer mode. It is not set in interval timer mode.
Bit 7: WOVF 0 1 Description No WTCNT overflow in watchdog timer mode Cleared by reading WOVF, then writing 0 in WOVF Set by WTCNT overflow in watchdog timer mode (Initial value)
Bit 6—Reset Enable (RSTE): Selects whether to reset the chip internally if WTCNT overflows in watchdog timer mode.
Bit 6: RSTE 0 1 Description Not reset when WTCNT overflows Reset when WTCNT overflows (Initial value)
Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if WTCNT overflows in watchdog timer mode.
Bit 5: RSTS 0 1 Description Power-on reset Manual reset (Initial value)
Bits 4 to 1—Reserved: These bits are always read as 1. The write value should always be 1. Bit 0— Reserved: This bit is always read as 0. The write value should always be 0. 13.2.4 Notes on Register Access
The watchdog timer’s WTCNT, WTCSR, and RSTCSR registers differ from other registers in that they are more difficult to write. The procedures for writing and reading these registers are given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by byte or longword transfer instructions. WTCNT and WTCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for WTCNT) or H'A5 (for WTCSR) (figure 13.2). This transfers the write data from the lower byte to WTCNT or WTCSR.
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SER
LSI not reset internally, but WTCNT and WTCSR reset within WDT
Writing to WTCNT 15 Address: Writing to WTCSR 15 Address: H'FFFFFE80 H'A5 87 Write data 0 H'FFFFFE80 H'5A 87 Write data 0
Figure 13.2 Writing to WTCNT and WTCSR Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFFFE82. It cannot be written by byte or longword transfer instructions. Procedures for writing 0 in WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 13.3. To write 0 in the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected.
Writing 0 to the WOVF bit 15 Address: H'FFFFFE82 H'A5 87 H'00 0
Writing to the RSTE and RSTS bits 15 Address: H'FFFFFE82 H'5A 87 Write data 0
Figure 13.3 Writing to RSTCSR Reading from WTCNT, WTCSR, and RSTCSR: WTCNT, WTCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFFFE80 for WTCSR, H'FFFFFE81 for WTCNT, and H'FFFFFE83 for RSTCSR.
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13.3
13.3.1
Operation
Operation in Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/ and TME bits in WTCSR to 1. Software must prevent WTCNT overflow by rewriting the WTCNT value (normally by writing H'00) before overflow occurs. Thus, WTCNT will not overflow while the system is operating normally, but if WTCNT fails to be rewritten and overflows occur due to a system crash or the like, a signal is output (figure 13.4). The signal can be used to reset the system. The signal is output for 512 φ clock cycles. If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally signal when WTCNT overflows. Either a power-on reset or a simultaneously with the manual reset can be selected by the RSTS bit. The internal reset signal is output for 2048 φ clock cycles. pin and a reset due to WDT overflow occur If a reset due to the input signal from the simultaneously, the reset takes priority and the WOVF bit in RSTCSR is cleared to 0.
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TI
SER
FVOTDW
FVOTDW
SER
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WTCNT value H'FF Overflow
H'00 WT/IT = 1 TME = 1 H'00 written in WTCNT WOVF = 1
Time WT/IT = 1 H'00 written TME = 1 in WTCNT
WDTOVF and internal reset generated
WDTOVF signal 512 φ clocks Internal reset signal* WT/IT: Timer mode select bit TME: Timer enable bit Note: * Internal reset signal is generated only when the RSTE bit is set to 1.
2048 φ clocks
Figure 13.4 Operation in Watchdog Timer Mode
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13.3.2
Operation in Interval Timer Mode
To use the WDT as an interval timer, clear WT/ to 0 and set TME to 1 in WTCSR. An interval timer interrupt (ITI) is generated each time the watchdog timer counter (WTCNT) overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 13.5).
WTCNT value H'FF Overflow Overflow Overflow Overflow
H'00 WT/IT = 0 TME = 1 ITI ITI ITI ITI
ITI: Interval timer interrupt request generation
Figure 13.5 Operation in Interval Timer Mode 13.3.3 Operation when Standby Mode is Cleared
The watchdog timer has a special function to clear standby mode with an NMI interrupt. When using standby mode, set the WDT as described below. Transition to Standby Mode: The TME bit in WTCSR must be cleared to 0 to stop the watchdog timer counter before it enters standby mode. The chip cannot enter standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 in WTCSR so that the counter overflow interval is equal to or longer than the oscillation settling time. See section 21, Electrical Characteristics, for the oscillation settling time. Recovery from Standby Mode: When an NMI request signal is received in standby mode the clock oscillator starts running and the watchdog timer starts counting at the rate selected by bits CKS2 to CKS0 before standby mode was entered. When WTCNT overflows (changes from H'FF to H'00) the system clock (φ) is presumed to be stable and usable; clock signals are supplied to the entire chip and standby mode ends. For details on standby mode, see section 20, Power Down Modes.
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Time
13.3.4
Timing of Overflow Flag (OVF) Setting
In interval timer mode, when WTCNT overflows, the OVF flag in WTCSR is set to 1 and an interval timer interrupt (ITI) is requested (figure 13.6).
WTCNT
H'FF
H'00
Overflow signal (internal signal)
OVF
Figure 13.6 Timing of OVF Setting 13.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting
signal is output. When WTCNT overflows the WOVF flag in RSTCSR is set to 1 and a When the RSTE bit is set to 1, WTCNT overflow enables an internal reset signal to be generated for the entire chip (figure 13.7).
WTCNT
H'FF
H'00
Overflow signal (internal signal)
WOVF
Figure 13.7 Timing of WOVF Setting
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13.4
13.4.1
Usage Notes
Contention between WTCNT Write and Increment
If a count-up pulse is generated at the timing shown in figure 13.8 during a watchdog timer counter (WTCNT) write cycle, the write takes priority and the timer counter is not incremented (figure 13.8).
Address
WTCNT address
Internal write signal WTCNT input clock
WTCNT
N
M Counter write data
Figure 13.8 Contention between WTCNT Write and Increment 13.4.2 Changing CKS2 to CKS0 Bit Values
If the values of bits CKS2 to CKS0 are altered while the WDT is running, the count may increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 13.4.3 Switching between Watchdog Timer Mode and Interval Timer Mode
The WDT may not operate correctly if it is switched between watchdog timer mode and interval timer mode while it is running. To ensure correct operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between watchdog timer mode and interval timer mode.
Rev. 2.00, 03/05, page 560 of 884
If a signal is input to the pin, the device cannot initialize correctly. Avoid logical input of the output signal to the input pin. To reset the entire system with the signal, use the circuit shown in figure 13.9.
Reset input
Reset signal to entire system
13.4.5
Internal Reset in Watchdog Timer Mode
If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not reset internally when a WTCNT overflow occurs, but WTCNT and WTCSR in the WDT will reset. 13.4.6 Internal Reset by Watchdog Timer (WDT) in Sleep Mode
When the watchdog time counter (WTCNT) overflows in watchdog timer mode, the SH7615 resets (power-on reset or manual reset) the chip internally. However, if WTCNT overflows in sleep mode, internal reset is not executed properly and exception handling by the reset cannot start. Conditions: • In sleep mode • WDT.WTCSR.WT/ bit = 1 (watchdog timer mode) • WDT.RSTCSR.RSTE bit = 1 (internal reset enabled) • WTCNT overflows Countermeasures: This problem can be avoided by the following countermeasures. • When sleep mode is not used, use this internal reset function in watchdog timer mode. • When sleep mode is used, reset by an external signal instead of the internal reset function. Note that the output signal must not be logically input to the pin of this LSI.
Rev. 2.00, 03/05, page 561 of 884
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Figure 13.9 Example of Circuit for System Reset with
SER
SER
SER
SER FVOTDW
13.4.4
System Reset with
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TI
FVOTDW FVOTDW FVOTDW
This LSI
RES
WDTOVF
Signal
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Section 14 Serial Communication Interface with FIFO (SCIF)
14.1 Overview
The SH7615 is equipped with a two-channel serial communication interface with built-in FIFO buffers (SCIF: SCI with FIFO). The SCIF can handle both asynchronous and synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). An on-chip Infrared Data Association (IrDA) interface based on the IrDA 1.0 system is also provided, enabling infrared communication. Sixteen-stage FIFO registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. 14.1.1 Features
The SCIF has the following features: • Choice of synchronous or asynchronous serial communication mode Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A multiprocessor communication function is also provided that enables serial data communication with a number of processors. There is a choice of 12 serial data communication formats. • Data length: 7 or 8 bits • Stop bit length: 1 or 2 bits • Parity: Even/odd/none • Multiprocessor bit: 1 or 0 • Receive error detection: Parity, overrun, and framing errors • Automatic break detection
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• •
• • •
• • • •
Synchronous mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other chips that have a synchronous communication function. There is a single serial data communication format. • Data length: 8 bits • Receive error detection: Overrun errors IrDA 1.0 compliance Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. In addition, the transmitter and receiver both have a 16-stage FIFO buffer structure, enabling continuous serial data transmission and reception. (However, IrDA communication is carried out in half-duplex mode.) Built-in baud rate generator allows a choice of bit rates. Choice of transmit/receive clock source: internal clock from baud rate generator or external clock from SCK pin Four interrupt sources There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error—that can issue requests independently. The transmit-FIFO-data-empty and receive-FIFO-data-full interrupts can activate the on-chip DMAC to execute data transfer. When not in use, the SCIF can be stopped by halting its clock supply to reduce power consumption. Choice of LSB-first or MSB-first mode In asynchronous mode, operation can be selected on a base clock of 4, 8, or 16 times the bit rate. Built-in modem control functions ( and )
Rev. 2.00, 03/05, page 564 of 884
STC
STR
14.1.2
Block Diagrams
A block diagram of the SCIF is shown in figure 14.1, and a diagram of the IrDA block in figure 14.2.
Module data bus
Bus interface
Internal data bus
SCFRDR (16-stage)
SCFTDR (16-stage)
SCFDR SCFCR SC1SSR SC2SSR SCSCR SCSMR SCFER SCIMR Transmission/ reception control
SCBRR Pφ Baud rate generator Pφ/4 Pφ/16 Pφ/64
RxD
SCRSR
SCTSR
TxD Parity generation Parity check SCK
Clock External clock BRI TxI RxI ERI
SCIF
IrDA/SCI switchover (to IrDA block)
SCRSR: SCFRDR: SCTSR: SCFTDR: SCSMR: SCSCR:
Receive shift register Receive FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register
SC1SSR: SC2SSR: SCBRR: SCFCR: SCFDR: SCFER: SCIMR:
Serial status 1 register Serial status 2 register Bit rate register FIFO control register FIFO data count register FIFO error register IrDA mode register
Figure 14.1 Block Diagram of SCIF
Rev. 2.00, 03/05, page 565 of 884
Clock input SCK
TxD Transmit clock SCIF Modulation unit TxD
RxD
Demodulation unit IrDA
RxD
IrDA/SCIF switchover
Figure 14.2 Diagram of IrDA Block 14.1.3 Input/Output Pins
The SCIF has the serial pins shown in table 14.1. Table 14.1 Pin Configuration
Channel 1 Name Serial clock pin Receive data pin Transmit data pin Transmit request pin Transmit enable pin 2 Serial clock pin Receive data pin Transmit data pin Abbreviation SCK1 RxD1 TxD1 I/O Input/ output Input Output Output Input Input/ output Input Output Function Clock input/output Receive data input Transmit data output Transmit request Transmit enable Clock input/output Receive data input Transmit data output
SCK2 RxD2 TxD2
Rev. 2.00, 03/05, page 566 of 884
STC STR
14.1.4
Register Configuration
The SCIF has the internal registers shown in table 14.2. These registers are used to specify asynchronous mode/synchronous mode and the IrDA communication mode, the data format and the bit rate, and to perform transmitter/receiver control. Table 14.2 SCIF Registers
Channel 1 Name Serial mode register Bit rate register Serial control register Transmit FIFO data register Serial status 1 register Serial status 2 register Receive FIFO data register FIFO control register FIFO data count register FIFO error register IrDA mode register 2 Serial mode register Bit rate register Serial control register Transmit FIFO data register Serial status 1 register Serial status 2 register Receive FIFO data register FIFO control register FIFO data count register FIFO error register IrDA mode register Note: * Abbreviation SCSMR1 SCBRR1 SCSCR1 SCFTDR1 SC1SSR1 SC2SSR1 SCFRDR1 SCFCR1 SCFDR1 SCFER1 SCIFMR1 SCSMR2 SCBRR2 SCSCR2 SCFTDR2 SC1SSR2 SC2SSR2 SCFRDR2 SCFCR2 SCFDR2 SCFER2 SCIMR2 R/W R/W R/W R/W W Initial Value H'00 H'FF H'00 Address Access Size
H'FFFFFCC0 8 H'FFFFFCC2 8 H'FFFFFCC4 8 H'FFFFFCC6 8 H'FFFFFCC8 16 H'FFFFFCCA 8 H'FFFFFCCE 8 H'FFFFFCD0 16 H'FFFFFCD2 16 H'FFFFFCD4 8 H'FFFFFCE0 8 H'FFFFFCE2 8 H'FFFFFCE4 8 H'FFFFFCE6 8 H'FFFFFCE8 16 H'FFFFFCEA 8 H'FFFFFCEE 8 H'FFFFFCF0 16 H'FFFFFCF2 16 H'FFFFFCF4 8
— * H'0060 R/(W) R/(W)* H'20 R R/W R R R/W R/W R/W R/W W H'00 H'0000 H'0000 H'00 H'00 H'FF H'00
Undefined H'FFFFFCCC 8
— * H'0060 R/(W) R/(W)* H'20 R R/W R R R/W H'00 H'0000 H'0000 H'00
Undefined H'FFFFFCEC 8
Only 0 can be written, to clear flags. Use byte access on registers with an access size of 8, and word access on registers with an access size of 16.
Rev. 2.00, 03/05, page 567 of 884
14.2
Register Descriptions
With the exception of the IrDA mode register (SCIMR) and bits 6 to 3 (ICK3 to ICK0) of the serial mode register (SCSMR), IrDA communication mode settings are the same as for asynchronous mode. 14.2.1 Receive Shift Register (SCRSR)
Bit: R/W: 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 —
The receive shift register (SCRSR) is the register used to receive serial data. The SCIF sets serial data input from the RxD pin in SCRSR in the order received, starting with the LSB (bit 0) or MSB (bit 7), and converts it to parallel data. When one byte of data has been received, it is transferred to the receive FIFO data register (SCFRDR) automatically. SCRSR cannot be read or written to directly. 14.2.2 Receive FIFO Data Register (SCFRDR)
Bit: R/W: 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 R
The receive FIFO data register (SCFRDR) is a 16-stage FIFO register (8 bits per stage) that stores received serial data. When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for reception, and consecutive receive operations can be performed until the receive FIFO data register is full (16 data bytes). SCFRDR is a read-only register, and cannot be written to. If a read is performed when there is no receive data in the receive FIFO data register, an undefined value will be returned. When the receive FIFO data register is full of receive data, subsequent serial data is lost.
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14.2.3
Transmit Shift Register (SCTSR)
Bit: R/W: 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 —
The transmit shift register (SCTSR) is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR to SCTSR, then sends the data to the TxD pin starting with the LSB (bit 0) or MSB (bit 7). When transmission of one byte is completed, the next transmit data is transferred from SCFTDR to SCTSR, and transmission started, automatically. SCTSR cannot be read or written to directly. 14.2.4 Transmit FIFO Data Register (SCFTDR)
Bit: R/W: 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 W
The transmit FIFO data register (SCFTDR) is a 16-stage FIFO register (8 bits per stage) that stores data for serial transmission. When the SCIF detects that SCTSR is empty, it transfers the transmit data written in SCFTDR to SCTSR and starts serial transmission. Serial transmission is performed continuously until there is no transmit data left in SCFTDR. SCFTDR is a write-only register, and cannot be read. The next data cannot be written when SCFTDR is filled with 16 bytes of transmit data. Data written in this case is ignored.
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14.2.5
Serial Mode Register (SCSMR)
Bit: 7 6 CHR/ ICK3 0 R/W 5 PE/ ICK2 0 R/W 4 O/ / ICK1 0 R/W 3 STOP/ ICK0 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Initial value: R/W:
0 R/W
The serial mode register (SCSMR) is an 8-bit register used to set the SCIF’s serial communication format and select the baud rate generator clock source. In IrDA communication mode, it is used to select the output pulse width. SCSMR can be read or written to by the CPU at all times. SCSMR is initialized to H'00 by a reset, by the module standby function, and in standby mode. Bit 7—Communication Mode (C/ ): Selects asynchronous mode or synchronous mode as the SCIF operating mode. In IrDA communication mode, this bit must be cleared to 0.
0 1
Bit 6—Character Length (CHR)/IrDA Clock Select 3 (ICK3): Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting,
Bit 6: CHR 0 1 Note: * Description 8-bit data 7-bit data* When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register (SCFTDR) is not transmitted. (Initial value)
In IrDA communication mode, bit 6 is the IrDA clock select 3 (ICK3) bit, enabling appropriate clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6, Operation in IrDA Mode, for details.
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A
Bit 7: C/
Description Asynchronous mode Synchronous mode (Initial value)
E
A
A
C/
Bit 5—Parity Enable (PE)/IrDA Clock Select 2 (ICK2): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit setting.
Bit 5: PE 0 1 Note: * Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (Initial value)
When the PE bit is set to 1, the parity (even or odd) specified by the O/ bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/ bit.
In IrDA communication mode, bit 5 is the IrDA clock select 2 (ICK2) bit, enabling appropriate clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6, Operation in IrDA Mode, for details. Bit 4—Parity Mode (O/ )/IrDA Clock Select 1 (ICK1): Selects either even or odd parity for use in parity addition and checking. The O/ bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/ bit setting is invalid in synchronous mode, and when parity addition and checking is disabled in asynchronous mode.
0 1
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd.
In IrDA communication mode, bit 4 is the IrDA clock select 1 (ICK1) bit, enabling appropriate clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6, Operation in IrDA Mode, for details.
E
Bit 4: O/
Description Even parity*1 Odd parity*2 (Initial value)
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E
E
E
E
E
Bit 3—Stop Bit Length (STOP)/IrDA Clock Select 0 (ICK0): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is set, the STOP bit setting is invalid since stop bits are not added.
Bit 3: STOP 0 1 Description 1 stop bit*1 2 stop bits*2 (Initial value)
Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. In IrDA communication mode, bit 3 is the IrDA clock select 0 (ICK0) bit, enabling appropriate clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6, Operation in IrDA Mode, for details. Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, the PE bit and O/ bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode and IrDA mode. For details of the multiprocessor communication function, see section 14.3.3, Multiprocessor Communication Function.
Bit 2: MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value)
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E
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the builtin baud rate generator. The clock source can be selected from Pφ, Pφ/4, Pφ/16, and Pφ/64, according to the setting of bits CKS1 and CKS0. For the relationship between the clock source, the bit rate register setting, and the baud rate, see section 14.2.9, Bit Rate Register (SCBRR).
Bit 1: CKS1 0 1 Bit 0: CKS0 0 1 0 1 Description Pφ clock Pφ/4 clock Pφ/16 clock Pφ/64 clock (Initial value)
Note: Pφ = peripheral clock
14.2.6
Serial Control Register (SCSCR)
Bit: 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 — 0 R 1 CKE1 0 R/W 0 CKE0 0 R/W
Initial value: R/W:
The serial control register (SCSCR) performs enabling or disabling of SCIF transmit/receive operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the transmit/receive clock source. SCSCR can be read or written to by the CPU at all times. SCSCR is initialized to H'00 by a reset, by the module standby function, and in standby mode.
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Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty interrupt (TXI) request generation when, after serial transmit data is transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the number of data bytes in SCFTDR falls to or below the transmit trigger set number, and the TDFE flag is set to 1 in the serial status 1 register (SC1SSR).
Bit 7: TIE 0 1 Note: * Description Transmit-FIFO-data-empty interrupt (TXI) request disabled* Transmit-FIFO-data-empty interrupt (TXI) request enabled TXI interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to SCFTDR, reading 1 from the TDFE flag, then clearing it to 0, or by clearing the TIE bit to 0. When transmit data is written to SCFTDR using the on-chip DMAC, the TDFE flag is cleared automatically. (Initial value)
Bit 6—Receive Interrupt Enable (RIE): Enables or disables generation of receive-FIFO-data full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests when, after serial receive data is transferred from the receive shift register (SCRSR) to the receive FIFO data register (SCFRDR), the number of data bytes in SCFRDR reaches or exceeds the receive trigger set number, and the RDF flag is set to 1 in SC1SSR.
Bit 6: RIE 0 1 Note: * Description Receive-FIFO-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request disabled* (Initial value) Receive-FIFO-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request enabled* RXI, ERI, and BRI interrupt requests can be cleared by reading 1 from the RDF or DR flag, the FER, PER, ORER, or ER flag, or the BRK flag, then clearing the flag to 0, or by clearing the RIE bit to 0. With the RDF flag, read receive data from SCFRDR until the number of receive data bytes is less than the receive trigger set number, then read 1 from the RDF flag and clear it to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCIF.
Bit 5: TE 0 1 Description Transmission disabled*1 Transmission enabled*2 (Initial value)
Notes: 1. The TDRE flag in SC1SSR is fixed at 1. 2. Serial transmission is started when transmit data is written to SCFTDR in this state. Serial mode register (SCSMR) and FIFO control register (SCFCR) settings must be made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set to 1.
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Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCIF.
Bit 4: RE 0 1 Description Reception disabled* Reception enabled*2
1
(Initial value)
Notes: 1. Clearing the RE bit to 0 does not affect the RDF, DR, FER, PER, ORER, ER, and BRK flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SCSMR settings must be made to decide the reception format before setting the RE bit to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR is set to 1. The MPIE bit setting is invalid in synchronous mode and IrDA mode, and when the MP bit is 0.
Bit 3: MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) (Initial value) [Clearing conditions] • • 1 W hen the MPIE bit is cleared to 0 W hen data with MPB = 1 is received Multiprocessor interrupts enabled* Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDF and FER in SC1SSR and ORER in SC2SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * Receive data transfer from SCRSR to SCFRDR, receive error detection, and setting of the RDF and FER in SC1SSR and ORER flags in SC2SSR, is not performed. When receive data with MPB = 1 is received, the MPB flag in SC2SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI (when the RIE bit in SCSCR is set to 1) and FER and ORER flag setting is enabled.
Bit 2—Reserved: This bit is always read as 0. The write value should always be 0.
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Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCIF clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as the serial clock output pin or the serial clock input pin. The function of the SCK pin should be selected with the pin function controller (PFC). The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in synchronous mode and in the case of external clock operation (CKE1 = 1). The CKE1 and CKE0 bits must be set before determining the SCIF’s operating mode with SCSMR. For details of clock source selection, see table 14.9 in section 14.3, Operation.
Bit 1: CKE1 0 Bit 0: CKE0 0 Description Asynchronous mode Synchronous mode 1 Asynchronous mode Synchronous mode 1 * Asynchronous mode Synchronous mode Internal clock/SCK pin functions as input pin (input signal ignored)*1 Internal clock/SCK pin functions as serial clock output*1 Internal clock/SCK pin functions as clock output*2 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*3 External clock/SCK pin functions as serial clock input *: Don’t care Notes: 1. Initial value 2. Outputs a clock with a frequency of 16/8/4 times the bit rate. 3. Inputs a clock with a frequency of 16/8/4 times the bit rate.
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14.2.7
Serial Status 1 Register (SC1SSR)
Bit: 15 PER3 0 R 7 ER 0 R/(W)* 14 PER2 0 R 6 TEND 1 R 13 PER1 0 R 5 TDFE 1 R/(W)* 12 PER0 0 R 4 BRK 0 R/(W)* 11 FER3 0 R 3 FER 0 R 10 FER2 0 R 2 PER 0 R 9 FER1 0 R 1 RDF 0 R/(W)* 8 FER0 0 R 0 DR 0 R/(W)*
Initial value: R/W: Bit: Initial value: R/W: Note: *
Only 0 can be written, to clear the flag.
The serial status 1 register (SC1SSR) is a 16-bit register in which the lower 8 bits consist of status flags that indicate the operating status of the SCIF, and the upper 8 bits indicate the number of receive errors in the data in the receive FIFO register. SC1SSR can be read or written to at all times. However, 1 cannot be written to the ER, TDFE, BRK, RDF, and DR status flags. Also note that in order to clear these flags to 0, they must first be read as 1. The TEND, FER, and PER flags are read-only and cannot be modified. SC1SSR is initialized to H'0084 by a reset, by the module standby function, and in standby mode. Bits 15 to 12—Parity Error Count 3 to 0 (PER3 to PER0): These bits indicate the number of data bytes in which a parity error occurred in the receive data in the receive FIFO data register. These bits are cleared by reading all the receive data in the receive FIFO data register, or by setting the RFRST bit to 1 in SCFCR and resetting the receive FIFO data register to the empty state. Bits 11 to 8—Framing Error Count 3 to 0 (FER3 to FER0): These bits indicate the number of data bytes in which a framing error occurred in the receive data in the receive FIFO data register. These bits are cleared by reading all the receive data in the receive FIFO data register, or by setting the RFRST bit to 1 in SCFCR and resetting the receive FIFO data register to the empty state.
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Bit 7—Receive Error (ER)
Bit 7: ER 0 Description Reception in progress, or reception has ended normally* [Clearing conditions] • • 1 In a reset or in standby mode W hen 0 is written to ER after reading ER = 1
1
(Initial value)
A framing error, parity error, or overrun error occurred during reception [Setting conditions] • • W hen the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0*2 W hen, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/ bit in the serial mode register (SCSMR) W hen the next serial receive operation is completed while there are 16 receive data bytes in SCFRDR
•
Notes: 1. The ER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. When a framing error or parity error occurs, the receive data is still transferred to SCFRDR, and reception is then halted or continued according to the setting of the EI bit. When an overrun error occurs, the receive data is not transferred to SCFRDR and reception cannot be continued. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked.
Bit 6—Transmit End (TEND): Indicates that there is no valid data in SCFTDR when the last bit of the transmit character is sent, and transmission has been ended.
Bit 6: TEND 0 Description Transmission is in progress [Clearing condition] When data is written to SCFTDR while TE = 1 1 Transmission has been ended [Setting conditions] • • • In a reset or in standby mode W hen the TE bit in SCSCR is 0 W hen there is no transmit data in SCFTDR on transmission of the last bit of a 1-byte serial transmit character (Initial value)
Rev. 2.00, 03/05, page 578 of 884
E
Bit 5—Transmit Data FIFO Empty (TDFE): Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the number of data bytes in SCFTDR has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR), and transmit data can be written to SCFTDR.
Bit 5: TDFE 0 Description A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR [Clearing conditions] • • 1 W hen transmit data exceeding the transmit trigger set number is written to SCFTDR, and 0 is written to TDFE after reading TDFE = 1 W hen transmit data exceeding the transmit trigger set number is written to SCFTDR by the on-chip DMAC
The number of transmit data bytes in SCFTDR does not exceed the transmit trigger set number (Initial value) [Setting conditions] • • In a reset or in standby mode W hen the number of SCFTDR transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation*
Note:
*
As SCFTDR is a 16-byte FIFO register, the maximum number of bytes that can be written when TDFE = 0 is {16 – (transmit trigger set number)}. Data written in excess of this will be ignored. The number of data bytes in SCFTDR is indicated by the upper 8 bits of SCFDR.
Bit 4—Break Detect (BRK): Indicates that a receive data break signal has been detected.
Bit 4: BRK 0 Description A break signal has not been received [Clearing conditions] • • 1 In a reset or in standby mode W hen 0 is written to BRK after reading BRK = 1 (Initial value)
A break signal has been received [Setting condition] When data with a framing error is received, and a framing error also occurs in the next receive data (all space “0”)
Note: When a break is detected, transfer to SCFRDR of the receive data (H'00) following detection is halted. When the break ends and the receive signal returns to mark “1”, receive data transfer is resumed.
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Bit 3—Framing Error (FER): Indicates a framing error in the data read from the receive FIFO data register (SCFRDR).
Bit 3: FER 0 Description There is no framing error in the receive data read from SCFRDR (Initial value) [Clearing conditions] • • 1 In a reset or in standby mode W hen there is no framing error in SCFRDR read data
There is a framing error in the receive data read from SCFRDR [Setting condition] When there is a framing error in SCFRDR read data
Bit 2—Parity Error (PER): In asynchronous mode, indicates a parity error in the data read from the receive FIFO data register (SCFRDR).
Bit 2: PER 0 Description There is no parity error in the receive data read from SCFRDR [Clearing conditions] • • 1 In a reset or in standby mode W hen there is no parity error in SCFRDR read data (Initial value)
There is a parity error in the receive data read from SCFRDR [Setting condition] When there is a parity error in SCFRDR read data
Bit 1—Receive Data Register Full (RDF): Indicates that the received data has been transferred to the receive FIFO data register (SCFRDR), and the number of receive data bytes in SCFRDR is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR).
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Bit 1: RDF 0
Description The number of receive data bytes in SCFRDR is less than the receive trigger set number (Initial value) [Clearing conditions] • • In a reset or in standby mode W hen SCFRDR is read until the number of receive data bytes in SCFRDR falls below the receive trigger set number, and 0 is written to RDF after reading RDF = 1 W hen SCFRDR is read by the on-chip DMAC until the number of receive data bytes in SCFRDR falls below the receive trigger set number
• 1
The number of receive data bytes in SCFRDR is equal to or greater than the receive trigger set number [Setting condition] When SCFRDR contains at least the receive trigger set number of receive data bytes
Note: SCFRDR is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set number of data bytes can be read. If all the data in SCFRDR is read and another read is performed, the data value will be undefined. The number of receive data bytes in SCFRDR is indicated by the lower 8 bits of SCFDR.
Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set number of data bytes in the receive FIFO data register (SCFRDR), and no further data has arrived for at least 16 etu after the stop bit of the last data received.
Bit 0: DR 0 Description Reception is in progress or has ended normally and there is no receive data left in SCFRDR (Initial value) [Clearing conditions] • • 1 In a reset or in standby mode W hen 0 is written to DR after all the remaining receive data has been read*1
No further receive data has arrived, and SCFRDR contains fewer than the receive trigger set number of data bytes [Setting condition] When SCFRDR contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 16 etu after the stop bit of the last data received*2
Notes: 1. All remaining receive data should be read before clearing the DR flag. 2. Equivalent to 1.6 frames when using an 8-bit, 1-stop-bit format. etu: Elementary time unit = sec/bit
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14.2.8
Serial Status 2 Register (SC2SSR)
Bit: 7 TLM 0 R/W 6 RLM 0 R/W 5 N1 1 R/W 4 N0 0 R/W 3 MPB 0 R 2 MPBT 0 R/W 1 EI 0 R/W 0 ORER 0 R/(W)*
Initial value: R/W: Note: *
Only 0 can be written, to clear the flag.
The serial status 2 register (SC2SSR) is an 8-bit register. SC2SSR can be read or written to at all times. However, 1 cannot be written to the ORER flag. Also note that in order to clear this flag to 0, they must first be read as 1. SC2SSR is initialized to H'20 by a reset, by the module standby function, and in standby mode. Bit 7—Transmit LSB/MSB-First Select (TLM): Selects LSB-first or MSB-first mode in data transmission.
Bit 7: TLM 0 1 Description LSB-first transmission MSB-first transmission (Initial value)
Bit 6—Receive LSB/MSB-First Select (RLM): Selects LSB-first or MSB-first mode in data reception.
Bit 6: RLM 0 1 Description LSB-first reception MSB-first reception (Initial value)
Bits 5 and 4—Clock Bit Rate Ratio (N1, N0): These bits select the ratio of the base clock to the bit rate.
Bit 5: N1 0 1 Bit 4: N0 0 1 0 1 Description SCIF operates on base clock of 4 times the bit rate SCIF operates on base clock of 8 times the bit rate SCIF operates on base clock of 16 times the bit rate Setting prohibited (Initial value)
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Bit 3—Multiprocessor bit (MPB): When reception is performed using a multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. The MPB flag is read-only and cannot be modified.
Bit 3: MPB 0 1 Note: * Description Data with a 0 multiprocessor bit has been received* Data with a 1 multiprocessor bit has been received Retains its previous state when the RE bit is cleared to 0 while using a multiprocessor format. (Initial value)
Bit 2—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid in synchronous mode and IrDA mode, when a multiprocessor format is not used, and when the operation is not transmission.
Bit 2: MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value)
Bit 1—Receive Data Error Ignore Enable (EI): Selects whether or not the receive operation is to be continued when a framing error or parity error occurs in receive data (ER = 1).
Bit 1: EI 0 1 Description Receive operation is halted when framing error or parity error occurs during reception (ER = 1) (Initial value) Receive operation is continued when framing error or parity error occurs during reception (ER = 1)
Note: When EI = 0, only the last data in SCFRDR is treated as data containing an error. When EI = 1, receive data is sent to SCFRDR even if it contains an error.
Rev. 2.00, 03/05, page 583 of 884
Bit 0—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination.
Bit 0: ORER 0 Description Reception in progress, or reception has ended normally* [Clearing conditions] • • 1 In a reset or in standby mode W hen 0 is written to ORER after reading ORER = 1 An overrun error occurred during reception*2
1
(Initial value)
[Setting condition] When the next serial receive operation is completed while there are 16 receive data bytes in SCFRDR Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. 2. The receive data prior to the overrun error is retained in SCFRDR, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. Also, serial transmission cannot be continued in synchronous mode.
14.2.9
Bit Rate Register (SCBRR)
Bit: 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W
Initial value: R/W:
The bit rate register (SCBRR) is an 8-bit register that sets the serial transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in the serial mode register (SCSMR). SCBRR can be read or written to by the CPU at all times. SCBRR is initialized to H'FF by a reset, by the module standby function, and in standby mode. The SCBRR setting is found from the following equations.
Rev. 2.00, 03/05, page 584 of 884
Asynchronous mode:
N= Pφ 64 × 22n–1 × B Pφ 32 × 22n–1 × B Pφ 16 × 22n–1 × B × 106 – 1 (When operating on a base clock of 16 times the bit rate)
N=
× 106 – 1 (When operating on a base clock of 8 times the bit rate)
N=
× 106 – 1 (When operating on a base clock of 4 times the bit rate)
Synchronous mode:
N= Pφ 8 × 22n–1 × B × 106 – 1
Where B: N: Pφ: n:
Bit rate (bits/s) SCBRR setting for baud rate generator (0 ≤ N ≤ 255) Peripheral module operating frequency (MHz) Baud rate generator input clock (n = 0, 1, 2, or 3) (See the table below for the relation between n and the clock.)
SCSMR Settings
n 0 1 2 3
Clock Pφ Pφ/4 Pφ/16 Pφ/64
CKS1 0 1
CKS0 0 1 0 1
The bit rate error in asynchronous mode is found from the following equations:
Pφ × 106 (N + 1) × B × 64 × 22n–1 – 1 × 100
Error (%) =
(When operating on a base clock of 16 times the bit rate) Pφ × 106 (N + 1) × B × 32 × 22n–1 – 1 × 100
Error (%) =
(When operating on a base clock of 8 times the bit rate) Pφ × 106 (N + 1) × B × 16 × 22n–1 – 1 × 100
Error (%) =
(When operating on a base clock of 4 times the bit rate)
Rev. 2.00, 03/05, page 585 of 884
Table 14.3 shows sample SCBRR settings in asynchronous mode, and table 14.4 shows sample SCBRR settings in synchronous mode. In both tables, the values are for operation on a base clock of 16 times the bit rate. Table 14.3 Examples of Bit Rates and SCBRR Settings in Asynchronous Mode
Pφ (MHz) 2 Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 –6.99 8.51 0.00 –18.62 n 1 1 0 0 0 0 0 0 0 0 0 2.097152 N 148 108 217 108 54 26 13 6 2 1 1 Error (%) –0.04 0.21 0.21 0.21 –0.70 1.14 –2.48 –2.48 13.78 4.86 –14.67 n 1 1 0 0 0 0 0 0 0 0 0 2.4576 N 174 127 255 127 63 31 15 7 3 1 1 Error (%) –0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 22.88 0.00 n 1 1 1 0 0 0 0 0 0 0 — N 212 155 77 155 77 38 19 9 4 2 — 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 –2.34 –2.34 –2.34 0.00 —
Pφ (MHz) 3.6864 Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 — 0 N 64 191 95 191 95 47 23 11 5 — 2 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 n 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –6.99 0.00 8.51 n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 1.73 0.00 1.73
Rev. 2.00, 03/05, page 586 of 884
Pφ (MHz) 6 Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) –0.44 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 –2.34 0.00 –2.34 n 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 6.144 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 7.37288 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) –0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 –6.99
Pφ (MHz) 9.8304 Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) –0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 0.00 –2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00
Rev. 2.00, 03/05, page 587 of 884
Pφ (MHz) 14.7456 Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 3 2 2 1 1 0 0 0 0 0 N 132 97 194 97 194 97 194 97 48 29 23 30 Error (%) 0.13 –0.35 0.16 –0.35 0.16 –0.35 0.16 –0.35 –0.35 0.00 1.73
Rev. 2.00, 03/05, page 588 of 884
Table 14.4 Examples of Bit Rates and SCBRR Settings in Synchronous Mode
Pφ (MHz) 4 Bit Rate (Bits/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2M n — 2 2 1 1 0 0 0 0 0 0 0 0 N — 249 124 249 99 199 99 39 19 9 3 1 0* n — 3 2 2 1 1 0 0 0 0 0 0 0 0 8 N — 124 249 124 199 99 199 79 39 19 7 3 1 0* n — 3 3 2 2 1 1 0 0 0 0 0 0 0 16 N — 249 124 249 99 199 99 159 79 39 15 7 3 1 n — — 3 3 2 2 1 1 0 0 0 0 0 0 32 N — — 249 124 199 99 199 79 159 79 31 15 7 3
Note: As far as possible, the setting should be made so that the error is within 1%. [Legend] Blank: No setting is available. —: A setting is available but error occurs. * Continuous transmission/reception is not possible.
Rev. 2.00, 03/05, page 589 of 884
Table 14.5 shows the maximum bit rate for various frequencies in asynchronous mode when using the baud rate generator. Tables 14.6 and 14.7 show the maximum bit rates when using external clock input. Table 14.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)
Settings Pφ (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.66080 20 24 24.57600 28 30 Maximum Bit Rate (Bits/s) 62500 65536 76800 93750 115200 125000 153600 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rev. 2.00, 03/05, page 590 of 884
Table 14.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
Pφ (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 30 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 2.0000 2.4576 3.0000 3.6864 4.0000 7.5000 Maximum Bit Rate (Bits/s) 31250 32768 38400 46875 57600 62500 76800 125000 153600 187500 230400 250000 468750
Table 14.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)
Pφ (MHz) 8 16 30 External Input Clock (MHz) 1.3333 2.6667 5.0 Maximum Bit Rate (Bits/s) 1333333.3 2666666.7 5000000.0
Rev. 2.00, 03/05, page 591 of 884
14.2.10 FIFO Control Register (SCFCR)
Bit: Initial value: R/W: 7 RTRG1 0 R/W 6 RTRG0 0 R/W 5 TTRG1 0 R/W 4 TTRG0 0 R/W 3 MCE 0 R/W 2 TFRST 0 R/W 1 RFRST 0 R/W 0 LOOP 0 R/W
The FIFO control register (SCFCR) performs data count resetting and trigger data number setting for the transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR can be read or written to at all times. SCFCR is initialized to H'00 by a reset, by the module standby function, and in standby mode. Bits 7 and 6—Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status 1 register (SC1SSR). The RDF flag is set when the number of receive data bytes in the receive FIFO data register (SCFRDR) is equal to or greater than the trigger set number shown in the following table.
Bit 7: RTRG1 0 1 Note: * Bit 6: RTRG0 0 1 0 1 Initial value Receive Trigger Number 1* 4 8 14
Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty (TDFE) flag in the serial status 1 register (SC1SSR). The TDFE flag is set when the number of transmit data bytes in the transmit FIFO data register (SCFTDR) is equal to or less than the trigger set number shown in the following table.
Bit 5: TTRG1 0 1 Note: * Bit 4: TTRG0 0 1 0 1 Transmit Trigger Number 8 (8)* 4 (12) 2 (14) 1 (15)
Initial value. Figures in parentheses are the number of empty bytes in SCFTDR when the flag is set.
Rev. 2.00, 03/05, page 592 of 884
Bit 3: MCE 0 1 Note: *
Description Modem signals disabled* Modem signals enabled is fixed at active-0 regardless of the input value, and (Initial value) output is also fixed at 0.
Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state.
Bit 2: TFRST 0 1 Description Reset operation disabled Reset operation enabled (Initial value)
Note: A reset operation is performed in the event of a reset, module standby, or in standby mode.
Bit 1—Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive FIFO data register and resets it to the empty state.
Bit 1: RFRST 0 1 Description Reset operation disabled Reset operation enabled (Initial value)
Note: A reset operation is performed in the event of a reset, module standby, or in standby mode.
Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD) and receive input pin (RxD), enabling loopback testing.
Bit 0: LOOP 0 1 Description Loopback test disabled Loopback test enabled (Initial value)
Rev. 2.00, 03/05, page 593 of 884
STR
STR
STC
Bit 3—Modem Control Enable (MCE): Enables or disables the signals.
and
modem control
STC
14.2.11 FIFO Data Count Register (SCFDR) The FIFO data count register (SCFDR) is a 16-bit register that indicates the number of data bytes stored in the transmit FIFO data register (SCFTDR) and receive FIFO data register (SCFRDR). The upper 8 bits show the number of transmit data bytes in SCFTDR, and the lower 8 bits show the number of receive data bytes in SCFRDR. SCFDR can be read by the CPU at all times. SCFDR is initialized to H'0000 by a reset, by the module standby function, and in standby mode. It is also initialized to H'00 by setting the TFRST and RFRST bits to 1 in SCFCR to reset SCFTDR and SCFRDR to the empty state.
Upper 8 bits: Initial value: R/W: 15 — 0 R 14 — 0 R 13 — 0 R 12 T4 0 R 11 T3 0 R 10 T2 0 R 9 T1 0 R 8 T0 0 R
Bits 15 to 13—Reserved: These bits are always read as 0. The write value should always be 0. Bits 12 to 8—Transmit FIFO Data Count 4 to 0 (T4 to T0): These bits show the number of untransmitted data bytes in SCFTDR. A value of H'00 indicates that there is no transmit data, and a value of H'10 indicates that SCFTDR is full of transmit data. The value is cleared to H'00 by transmitting all the data, as well as by the above initialization conditions.
Lower 8 bits: Initial value: R/W: 7 — 0 R 6 — 0 R 5 — 0 R 4 R4 0 R 3 R3 0 R 2 R2 0 R 1 R1 0 R 0 R0 0 R
Bits 7 to 5—Reserved: These bits are always read as 0. The write value should always be 0. Bits 4 to 0—Receive FIFO Data Count 4 to 0 (R4 to R0): These bits show the number of receive data bytes in SCFRDR. A value of H'00 indicates that there is no receive data, and a value of H'10 indicates that SCFRDR is full of receive data. The value is cleared to H'00 by reading all the receive data from SCFRDR, as well as by the above initialization conditions.
Rev. 2.00, 03/05, page 594 of 884
14.2.12 FIFO Error Register (SCFER) The FIFO error register (SCFER) indicates the data location at which a parity error or framing error occurred in receive data stored in the receive FIFO data register (SCFRDR). SCFER can be read at all times.
Upper 8 bits: Initial value: R/W: Lower 8 bits: Initial value: R/W: 15 ED15 0 R 7 ED7 0 R 14 ED14 0 R 6 ED6 0 R 13 ED13 0 R 5 ED5 0 R 12 ED12 0 R 4 ED4 0 R 11 ED11 0 R 3 ED3 0 R 10 ED10 0 R 2 ED2 0 R 9 ED9 0 R 1 ED1 0 R 8 ED8 0 R 0 ED0 0 R
Bits 15 to 0—Error Data Flags 15 to 0 (ED15 to ED0): These flags indicate the data location in the receive FIFO data register at which an error occurred. When data in the nth stage of the buffer contains an error, the nth bit is set to 1. Note that this register is not cleared by setting the RFRST bit to 1 in SCFCR.
Bits 15 to 0: ED15 to ED0 0 1 Description No parity or framing error in data in corresponding stage of register FIFO (Initial value) Parity or framing error present in data in corresponding stage of register FIFO
Note: A reset operation is performed in the event of a reset, when the module standby function is used, or in standby mode. These flags are also cleared by reading the data in which the parity error or framing error occurred from SCFRDR.
14.2.13 IrDA Mode Register (SCIMR) The IrDA mode register (SCIFMR) allows selection of the IrDA mode and the IrDA output pulse width, and inversion of the IrDA receive data polarity. SCIMR can be read and written to at all times. SCIMR is initialized to H'00 by a reset, by the module standby function, and in standby mode.
Rev. 2.00, 03/05, page 595 of 884
Bit: Initial value: R/W:
7 IRMOD 0 R/W
6 PSEL 0 R/W
5 RIVS 0 R/W
4 — 0 R
3 — 0 R
2 — 0 R
1 — 0 R
0 — 0 R
Bit 7—IrDA Mode (IRMOD): Selects operation as an IrDA serial communication interface.
Bit 7: IRMOD 0 1 Note: * Description Operation as SCIF is selected Operation as IrDA is selected* (Initial value)
When operation as an IrDA interface is selected, bit 7 (C/ ) of the serial mode register (SCSMR) must be cleared to 0.
Bit 6—Output Pulse Width Select (PSEL): Selects either 3/16 of the bit length set by bits ICK3 to ICK0 in the serial mode register (SCSMR), or 3/16 of the bit length corresponding to the selected baud rate, as the IrDA output pulse width. The setting is shown together with bits 6 to 3 (ICK3 to ICK0) of the serial mode register (SCSMR).
Serial Mode Register (SCSMR) Bit 6: ICK3 ICK3 Don’t care Bit 5: ICK2 ICK2 Don’t care Bit 4: ICK1 ICK1 Don’t care Bit 3: ICK0 ICK0 Don’t care SCIMR Bit 2: PSEL 1 0 Description Pulse width: 3/16 of bit length set in bits ICK3 to ICK0 Pulse width: 3/16 of bit length set in SCBRR (Initial value)
Note: A fixed clock pulse signal, IRCLK, must be generated by multiplying the Pφ clock by 1/2 N + 2 (where N is determined by the value set in ICK3 to ICK0). For details, see section 14.3.6 Pulse Width Selection.
Bit 5—IrDA Receive Data Inverse (RIVS): Allows inversion of the receive data polarity to be selected in IrDA communication.
Bit 5: RIVS 0 1 Description Receive data polarity inverted in reception Receive data polarity not inverted in reception (Initial value)
Note: Make the selection according to the characteristics of the IrDA modulation/demodulation module.
Bits 4 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 596 of 884
A
14.3
14.3.1
Operation
Overview
The SCIF can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. An IrDA block is also provided, enabling infrared communication conforming to IrDA 1.0 to be executed by connecting an infrared transmission/reception unit. Sixteen-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed. Selection of asynchronous, synchronous, or IrDA mode and the transmission format is made by means of the serial mode register (SCSMR) and IrDA mode register (SCIMR) as shown in table 14.8. The SCIF clock source is determined by a combination of the C/ bit in SCSMR, the IRMOD bit in SCIMR, and the CKE1 and CKE0 bits in the serial control register (SCSCR), as shown in table 14.9. • Asynchronous Mode Data length: Choice of 7 or 8 bits Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transmit/receive format and character length) Detection of framing, parity, and overrun errors, receive FIFO data full and receive data ready conditions, and breaks, during reception Detection of transmit FIFO data empty condition during transmission Choice of internal or external clock as SCIF clock source When internal clock is selected: The SCIF operates on a clock with a frequency of 16, 8, or 4 times the bit rate of the baud rate generator, and can output this operating clock. When external clock is selected: A clock with a frequency of 16, 8, or 4 times the bit rate must be input (the built-in baud rate generator is not used). • Synchronous Mode Transmit/receive format: Fixed 8-bit data Detection of overrun errors during reception Choice of internal or external clock as SCIF clock source When internal clock is selected: The SCIF operates on the baud rate generator clock and can output a serial clock to external devices. When external clock is selected: The on-chip baud rate generator is not used, and the SCIF operates on the input serial clock.
Rev. 2.00, 03/05, page 597 of 884
A
• IrDA Mode IrDA 1.0 compliance Data length: 8 bits Stop bit length: 1 bit Protection function to prevent receiver being affected during transmission Clock source: Internal clock Table 14.8 SCSMR and SCIMR Settings for Serial Transmit/Receive Format Selection
SCIMR SCSMR Settings Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: C/ CHR MP PE STOP Mode 0 SCIF Transmit/Receive Format Data Length MP Bit Absent Parity Bit Stop Bit Length
0
0 1
1 0 1
Note:
*
Don’t care
Rev. 2.00, 03/05, page 598 of 884
A
Bit 7: IRMOD
0
0
0 1
0 1 0 1 0 1 0 1 0 1 0 1 * ICK0 *
Asynchronous 8-bit mode data
Absent 1 bit 2 bits Present 1 bit 2 bits
1
0 1
7-bit data
Absent 1 bit 2 bits Present 1 bit 2 bits
0 1
1
* * * *
Asynchronous 8-bit mode (multi- data processor 7-bit format) data Synchronous mode IrDA mode Setting prohibited 8-bit data 8-bit data —
Present
Absent 1 bit 2 bits 1 bit 2 bits
* ICK3 *
* ICK2 *
* ICK1 *
Absent Absent —
Absent None Absent 1 bit — —
Table 14.9 SCSMR and SCSCR Settings for SCIF Clock Source Selection
SCSMR Bit 7: C/ 0 SCSCR Setting Bit 1: CKE1 0 Bit 0: CKE0 0 1 1 1 0 1 0 1 0 1 0 1 Synchronous mode Internal External Mode Asynchronous mode Clock Source Internal SCIF Transmit/Receive Clock SCK Pin Function SCIF does not use SCK pin Outputs clock with frequency of 16/8/4 times bit rate External Inputs clock with frequency of 16/8/4 times bit rate Outputs serial clock Inputs serial clock
A
Rev. 2.00, 03/05, page 599 of 884
14.3.2
Operation in Asynchronous Mode
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-bycharacter basis. Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a 16-stage FIFO buffer structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 14.3 shows the general format for asynchronous serial communication. In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCIF monitors the line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (LSB-first or MSB-first order selectable), a parity bit or multiprocessor bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCIF performs synchronization at the falling edge of the start bit in reception. The SCIF samples the data on the eighth (fourth, second) pulse of a clock with a frequency of 16 (8, 4) times the length of one bit, so that the transfer data is latched at the center of each bit.
Idle state (mark state) 1 0/1 Parity bit 1 bit, or none 1 Stop bit(s) 1 or 2 bits 1
1 Serial data 0 Start bit 1 bit
(LSB) D0 D1 D2 D3 D4 D5 D6
(MSB) D7
Transmit/receive data 7 or 8 bits
One unit of transfer data (character or frame)
Figure 14.3 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits, LSB-First Transfer)
Rev. 2.00, 03/05, page 600 of 884
Transmit/Receive Format: Table 14.10 shows the transmit/receive formats that can be used in asynchronous mode. Any of 12 transmit/receive formats can be selected by means of settings in the serial mode register (SCSMR). Table 14.10 Serial Transmit/Receive Formats (Asynchronous Mode)
SCSMR Settings CHR PE
0 0
Serial Transmit/Receive Format and Frame Length 1
S
MP STOP
0 0
2
3
4
5 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data
6
7
8
9
10
STOP
11
12
1
S
STOP STOP
1
0
S
P
STOP
1
S
P
STOP STOP
1
0
0
S
STOP
1
S
STOP STOP
1
0
S
P
STOP
1
S
P
STOP STOP
0
*
1
0
S
MPB STOP
*
1
S
MPB STOP STOP
1
*
0
S
MPB STOP
*
1
S
MPB STOP STOP
Note: * Don’t care [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit
Rev. 2.00, 03/05, page 601 of 884
When an external clock is input at the SCK pin, the input clock frequency should be 16, 8, or 4 times the bit rate used. When the SCIF is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is 16, 8, or 4 times the bit rate. Data Transmit/Receive Operations • SCIF Initialization (Asynchronous Mode) Before transmitting and receiving data, it is necessary to clear the TE and RE bits to 0 in SCSCR, then initialize the SCIF as described below. When the operating mode, communication format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the transmit shift register (SCTSR) is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of the serial status 1 register (SC1SSR), the transmit FIFO data register (SCFTDR), or the receive FIFO data register (SCFRDR). The TE bit should not be cleared to 0 until all transmit data has been transmitted and the TEND flag has been set in SC1SSR. It is possible to clear the TE bit to 0 during transmission, but the data being transmitted will go to the high-impedance state after TE is cleared. Also, before starting transmission by setting TE again, the TFRST bit should first be set to 1 in SCFCR to reset SCFTDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Figure 14.4 shows a sample SCIF initialization flowchart.
Rev. 2.00, 03/05, page 602 of 884
A
Clock: Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/ bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source selection, see table 14.9.
Initialization Clear TE and RE bits to 0 in SCSCR Set TFRST and RFRST bits to 1 in SCFCR Set CKE1 and CKE0 bits in SCSCR (leaving TE and RE bits cleared to 0) Set transmit/receive format in SCSMR Set value in SCBRR Wait 1-bit interval elapsed? Yes Set RTRG1–0 and TTRG1–0 bits in SCFCR, and clear TFRST and RFRST bits to 0 Set TE or RE bit to 1 in SCSCR, and set RIE, TIE, and MPIE bits End No
[1] Set the clock selection in SCSCR. Be sure to clear bits RIE, TIE, and MPIE, and bits TE and RE, to 0. When clock output is selected in asynchronous mode, it is output immediately after SCSCR settings are made. Select input or output for the SCK pin with the PFC. [2] Set the transmit/receive format in SCSMR. When using IrDA mode, also set SCIFMR. [3] Write a value corresponding to the bit rate into the bit rate register (SCBRR). (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE bit or RE bit in SCSCR to 1. Also set the RIE, TIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit.
[1]
[2]
[3]
[4]
Figure 14.4 Sample SCIF Initialization Flowchart • Serial Data Transmission (Asynchronous Mode) Figure 14.5 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Rev. 2.00, 03/05, page 603 of 884
Initialization Start of transmission
[1]
[1] PFC initialization: Set the TxD pin, and the SCK pin if necessary, with the PFC. [2] SCIF status check and transmit data write: Read the serial status 1 register (SC1SSR) and check that the TDFE bit is set to 1, then write transmit data to the transmit FIFO data register (SCFTDR) and clear the TDFE bit to 0 after reading TDFE = 1. The TEND bit is cleared automatically when transmission is started by writing transmit data. The number of data bytes that can be written is {16 – (transmit trigger set number)}. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE bit to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE bit to 0. (Checking and clearing of the TDFE bit is automatic when the DMAC is activated by a transmit-FIFOdata-empty interrupt (TXI) request, and data is written to SCFTDR.) [4] Break output at the end of serial transmission: To output a break in serial transmission, clear the port data register (DR) to 0, then clear the TE bit to 0 in SCSCR, and set the TxD pin as an output port with the PFC. In steps 2 and 3, the number of transmit data bytes that can be written can be ascertained from the number of transmit data bytes in SCFTDR indicated in the upper 8 bits of the FIFO data count register (SCFDR).
Read TDFE bit in SC1SSR
[2] No
TDFE = 1? Yes Write {16 – (transmit trigger set number)} bytes of transmit data to SCFTDR, and clear TDFE bit to 0 in SC1SSR after reading TDFE = 1 [3] All data transmitted? Yes Read TEND bit in SC1SSR TEND = 1? Yes Break output? Yes Clear DR to 0 Clear TE bit to 0 in SCSCR, and set TxD pin as output port with PFC [4]
No
No
No
End of transmission
Figure 14.5 Sample Serial Transmission Flowchart
Rev. 2.00, 03/05, page 604 of 884
In serial transmission, the SCIF operates as described below. 1. When data is written to the transmit FIFO data register (SCFTDR), the SCIF transfers the data to the transmit shift register (SCTSR), and starts transmitting. Check that the TDFE flag is set to 1 in the serial status 1 register (SC1SSR) before writing transmit data to SCFTDR. The number of data bytes that can be written is at least {16 – (transmit trigger set number)}. 2. When data is transferred from SCFTDR to SCTSR and transmission is started, transmit operations are performed continually until there is no transmit data left in SCFTDR. If the number of data bytes in SCFTDR falls to or below the transmit trigger number set in the FIFO control register (SCFCR) during transmission, the TDFE flag is set. If the TE bit setting in the serial control register (SCSCR) is 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) is requested. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first or MSB-first order according to the setting of the TLM bit in SC2SSR. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. (A format in which neither a parity bit nor a multiprocessor bit is output can also be selected.) d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks for transmit data in SCFTDR at the timing for sending the stop bit. If there is data in SCFTDR, it is transferred to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data in SCFTDR, the TEND flag is set to 1 in the serial status 1 register (SC1SSR), the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. Figure 14.6 shows an example of the operation for transmission in asynchronous mode.
Rev. 2.00, 03/05, page 605 of 884
1 Serial data
Start bit
Data
Parity Stop Start bit bit bit
Data
Parity Stop bit bit
1 Idle state (mark state)
0
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
1
TDFE
TEND TXI interrupt request TXI interrupt request
Data written to SCFTDR and TDFE flag cleared to 0 by TXI interrupt handler One frame
Figure 14.6 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit, LSB-First Transfer) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with input value. When is set to 1, if transmission is in progress, the line goes to the the mark state after transmission of one frame. When is set to 0, the next transmit data is output starting from the start bit. Figure 14.7 shows an example of the operation when modem control is used.
Start bit Parity Stop bit bit
Serial data
0
D0
D1
D7
0/1
CTS
Drive high at this point before stop bit
Rev. 2.00, 03/05, page 606 of 884
STC
Figure 14.7 Example of Operation Using Modem Control (
STC
STC
STC
Start bit
0
D0
D1
D7
0/1
)
• Serial Data Reception (Asynchronous Mode) Figure 14.8 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception.
Initialization [1] [1] PFC initialization: Set the RxD pin, and the SCK pin if necessary, with the PFC.
[2] Receive error handling and break detection: Read ER, BRK, FER, PER, and DR in SC1SSR, and ORER in SC2SSR, to check whether a receive error has occurred. If a receive error has occurred, read the Read ER, BRK, FER, PER, ER, BRK, FER, PER, and DR flags in and DR bits in SC1SSR, and [2] SC1SSR and the ORER flag in SC2SSR ORER bit in SC2SSR to identify the error. After performing the appropriate error handling, ensure that the ORER, BRK, DR, and ER bits are all ER ∨ BRK ∨ Yes cleared to 0. Reception cannot be FER ∨ PER ∨ DR ∨ resumed if the ORER bit is set to 1. The ORER = 1? setting of the EI bit in SC2SSR determines whether reception is Error handling No continued or halted when any of PER3–0 or FER3–0 is set to 1. In the case of a framing error, a break [3] Read RDF flag in SC1SSR can be detected by reading the value of the RxD pin. Start of reception No RDF = 1? Yes Read receive data from SCFRDR, and clear RDF flag to 0 in SC1SSR [3] SCIF status check and receive data read: Read the serial status 1 register (SC1SSR) and check that RDF = 1, then read receive data from the receive FIFO data register (SCFRDR) and clear the RDF bit to 0. Transition of the RDF bit from 0 to 1 can also be identified by means of an RXI interrupt. [4] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of data bytes from SCFRDR, and write 0 to the RDF flag after reading 1 from it. The number of receive data bytes in SCFRDR can be ascertained by reading the lower bits of the FIFO data count register (SCFDR). (The RDF bit is cleared automatically when the DMAC is activated by an RXI interrupt and the SCFRDR value is read.)
[4]
No
All data received? Yes Clear RE bit to 0 in SCSCR
End of reception
Figure 14.8 Sample Serial Reception Flowchart (1)
Rev. 2.00, 03/05, page 607 of 884
Error handling
No
ORER = 1? Yes Overrun error handling
[1] Whether a framing error or parity error has occurred in the receive data read from SCFRDR can be ascertained from the FER and PER bits in SC1SSR. [2] When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the H'00 break data in which a framing error occurred is stored as the last data in SCFRDR.
No
BRK = 1? Yes Clear RE bit to 0 in SCSCR
No
DR = 1? Yes Read receive data from SCFRDR [1]
No
FER = 1? Yes Framing error handling [2]
No
PER = 1? Yes Parity error handling
No
All data read? Yes Clear ORER, BRK, DR, and ER flags to 0
End
Figure 14.8 Sample Serial Reception Flowchart (2)
Rev. 2.00, 03/05, page 608 of 884
In serial reception, the SCIF operates as described below. 1. The SCIF monitors the communication line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order or MSB-to-LSB order according to the setting of the RLM bit in SC2SSR. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. a. Parity check: The SCIF checks whether the number of 1-bits in the receive data agrees with the parity (even or odd) set in the O/ bit in the serial mode register (SCSMR). b. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. c. Status check: The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR) to SCFRDR. d. Break check: The SCIF checks that the BRK flag is 0, indicating no break. If all the above checks are passed, the receive data is stored in SCFRDR. If a receive error is detected in the error check, the operation is as shown in table 14.11. Note: No further receive operations can be performed when an overrun error has occurred. The setting of the EI bit in SC2SSR determines whether reception is continued or halted when a framing error or parity error occurs. Also, as the RDF flag is not set to 1 when receiving, the error flags must be cleared to 0. 4. If the RIE bit setting in SCSCR is 1 when the RDF or DR flag is set to 1, a receive-FIFO-datafull interrupt (RXI) is requested. If the RIE bit setting in SCSCR is 1 when the ORER, PER, or FER flag is set to 1, a receiveerror interrupt (ERI) is requested. If the RIE bit setting in SCSCR is 1 when the BRK flag is set to 1, a break-receive interrupt (BRI) is requested.
E
Rev. 2.00, 03/05, page 609 of 884
Table 14.11 Receive Error Conditions
Receive Error Overrun error Abbreviation ORER Condition Data Transfer
Next serial receive operation is Receive data is not transferred from SCRSR to SCFRDR completed while there are 16 receive data bytes in SCFRDR Stop bit is 0 Received data parity differs from that (even or odd) set in SCSMR Receive data is transferred from SCRSR to SCFRDR Receive data is transferred from SCRSR to SCFRDR
Framing error Parity error
FER PER
Figure 14.9 shows an example of the operation for reception in asynchronous mode.
1 Serial data
Start bit Data Parity Stop Start bit bit bit Data Parity Stop bit bit
1
0
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
1
Idle state (mark state)
RDF
FER
RXI interrupt request One frame
Data read and RDF flag cleared to 0 by RXI interrupt handler
ERI interrupt request due to framing error
Figure 14.9 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit, LSB-First Transfer) signal is output when SCFRDR is empty. When 5. When modem control is enabled, the is 0, reception is possible. When is 1, this indicates that SCFRDR is full and reception is not possible. Figure 14.10 shows an example of the operation when modem control is used.
Rev. 2.00, 03/05, page 610 of 884
STR STR
STR
Start bit
Parity bit
Start bit
Serial data
0
D0
D1
D2
D7
0/1
1
0
RTS
14.3.3
Multiprocessor Communication Function
The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a serial communication line. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving stations skip the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, each receiving stations compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 14.11 shows an example of inter-processor communication using a multiprocessor format.
Rev. 2.00, 03/05, page 611 of 884
STR
Figure 14.10 Example of Operation Using Modem Control (
)
Transmitting station Serial communication line
Receiving station A (ID = 01)
Receiving station B (ID = 02)
Receiving station C (ID = 03)
Receiving station D (ID = 04)
Serial data
H'01 (MPB = 1) ID transmission cycle: Receiving station specification
H'AA (MPB = 0) Data transmission cycle: Data transmission to receiving station specified by ID
MPB: Multiprocessor bit
Figure 14.11 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Transmit/Receive Formats: There are four transmit/receive formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 14.10. Clock: See the section on asynchronous mode. Data Transmit/Receive Operations • SCI Initialization See the section on asynchronous mode. • Multiprocessor Serial Data Transmission Figure 14.12 shows a sample flowchart for multiprocessor serial data transmission. Use the following procedure for multiprocessor serial data transmission after enabling the SCIF for transmission.
Rev. 2.00, 03/05, page 612 of 884
Initialization Start of transmission
[1]
[1] PFC initialization: Set the TxD pin, and the SCK pin if necessary, with the PFC. [2] SCIF status check and transmit data write: Read the serial status 1 register (SC1SSR) and check that the TDFE bit is set to 1, then write transmit data to the transmit FIFO data register (SCFTDR). Set the MPBT bit to 0 or 1 in SC1SSR. Finally, clear the TDFE and TEND flags to 0 after reading 1 from them. The number of data bytes that can be written is {16 – (transmit trigger set number)}. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE bit to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE bit to 0. (Checking and clearing of the TDFE bit is automatic when the DMAC is activated by a transmit-FIFO-data-empty interrupt (TXI) request, and data is written to SCFTDR.) [4] Break output at the end of serial transmission: To output a break in serial transmission, clear the port data register (DR) to 0, then clear the TE bit to 0 in SCSCR, and set the TxD pin as an output port with the PFC. In steps 2 and 3, the number of transmit data bytes that can be written can be ascertained from the number of transmit data bytes in SCFTDR indicated in the upper 8 bits of the FIFO data count register (SCFDR).
Read TDFE bit in SC1SSR
[2] No
TDFE = 1? Yes Write {16 – (transmit trigger set number)} bytes of transmit data to SCFTDR, and set MPBT in SC2SSR Clear TDFE and TEND flags to 0
End of transmission? [3] Yes Read TEND bit in SC1SSR
No
TEND = 1? Yes Break output? Yes Clear DR to 0 Clear TE bit to 0 in SCSCR, and set TxD pin as output port with PFC [4]
No
No
End of transmission
Figure 14.12 Sample Multiprocessor Serial Transmission Flowchart
Rev. 2.00, 03/05, page 613 of 884
In serial transmission, the SCIF operates as described below. 1. When data is written to SCFTDR, the SCIF transfers the data to SCTSR and starts transmitting. Check that the TDFE flag is set to 1 in SC1SSR before writing transmit data to SCFTDR. The number of data bytes that can be written is at least {16 – (transmit trigger set number)}. 2. When data is transferred from SCFTDR to SCTSR and transmission is started, transmit operations are performed continually until there is no transmit data left in SCFTDR. If the number of data bytes in SCFTDR falls to or below the transmit trigger number set in SCFCR during transmission, the TDFE flag is set to 1. If the TIE bit setting in SCSCR is 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) is requested. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first or MSB-first order according to the setting of the TLM bit in SC2SSR. c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks for transmit data in SCFTDR at the timing for sending the stop bit. If there is data in SCFTDR, it is transferred to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data in SCFTDR, the TEND flag is set to 1 in SC1SSR, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. Figure 14.13 shows an example of SCIF operation for transmission using a multiprocessor format.
Rev. 2.00, 03/05, page 614 of 884
1 Serial data
Start bit
Data
Multiproces- Stop Start sor bit bit bit
Multiproces- Stop sor bit bit
1
0
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
1
Idle state (mark state)
TDFE
TEND TXI interrupt TXI interrupt request request Data written to SCFTDR and TDFE flag cleared to 0 by TXI interrupt handler
One frame
Figure 14.13 Example of SCIF Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit, LSB-First Transfer) • Multiprocessor Serial Data Reception Figure 14.14 shows a sample flowchart for multiprocessor serial reception. Use the following procedure for multiprocessor serial data reception after enabling the SCIF for reception.
Rev. 2.00, 03/05, page 615 of 884
Initialization Start of reception
[1]
[1] PFC initialization: Set the RxD pin, and the SCK pin if necessary, with the PFC. [2] ID reception cycle: Set the MPIE bit to 1 in SCSCR. [3] SCIF status check, ID reception and comparison: Read SC1SSR and check that the RDF bit is set to 1, then read the receive data in the receive FIFO data register (SCFRDR) and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDF bit to 0. If the data is this station’s ID, clear the RDF bit to 0. [4] Receive error handling and break detection: Read the ER, BRK, FER, and DR flags in SC1SSR and the ORER flag in SC2SSR to check whether a receive error has occurred. If a receive error has occurred, read the ER, BRK, FER, and DR flags in SC1SSR and the ORER flag in SC2SSR to identify the error. After performing the appropriate error handling, ensure that ER, BRK, DR, and ORER are all cleared to 0. The setting of the EI bit in SC2SSR determines whether reception is continued or halted when the ORER bit is set to 1. In the case of a framing error, a break can be detected by reading the value of the RxD pin. [5] SCIF status check and receive data read: Read the serial status 1 register (SC1SSR) and check that RDF = 1, then read receive data from the receive FIFO data register (SCFRDR).
Set MPIE bit to 1 in SCSCR Read ER, BRK, FER, and DR bits in SC1SSR, and ORER bit in SC2SSR BRK ∨ DR ∨ ER ∨ FER ∨ ORER = 1? No Read RDF flag in SC1SSR No RDF = 1? Yes Read receive data from SCFRDR, and clear RDF flag to 0 in SC1SSR No This station’s ID? Yes Read BRK, DR, ER, and FER bits in SC1SSR, and ORER bit in SC2SSR BRK ∨ DR ∨ ER ∨ FER ∨ ORER = 1? No Read RDF flag in SC1SSR RDF = 1? Yes Read receive data from SCFRDR No All data received? Yes Clear RE bit to 0 in SCSCR End of reception No [5] Yes [4] [3]
[2]
Yes
Error handling
Figure 14.14 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 2.00, 03/05, page 616 of 884
Error handling
No
[1] Whether a framing error has occurred in the receive data read from SCFRDR can be ascertained from the FER bit in SC1SSR. [2] When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00 and the break data in which a framing error occurred is stored. However, note that the H'00 break data in which a framing error occurred is stored as the last data in SCFRDR.
ORER = 1? Yes Overrun error handling
No
BRK = 1? Yes Clear RE bit to 0 in SCSCR
No
DR = 1? Yes Read receive data from SCFRDR [1]
No
FER = 1? Yes Framing error handling [2]
No
All data read? Yes Clear ORER, BRK, DR, and ER flags to 0
End
Figure 14.14 Sample Multiprocessor Serial Reception Flowchart (2)
Rev. 2.00, 03/05, page 617 of 884
Figure 14.15 shows an example of SCIF operation for multiprocessor format reception.
1 Serial data
Start bit Data (ID1) Stop Start bit Data (Data1) MPB bit Stop MPB bit
1 Idle state (mark state)
0
D0
D1
D7
1
1
0
D0
D1
D7
0
1
MPIE
RDF
SCFRDR value
ID1
RXI interrupt request (multiprocessor interrupt) MPIE = 0
SCFRDR data read and RDF flag cleared to 0 by RXI interrupt handler
As data is not this station’s ID, MPIE bit is set to 1 again
RXI interrupt request is not generated, and SCFRDR retains its state
(a) Data does not match station’s ID
1 Serial data
Start bit
Data (ID2)
Stop Start bit Data (Data2) MPB bit
Stop MPB bit
1 Idle state (mark state)
0
D0
D1
D7
1
1
0
D0
D1
D7
0
1
MPIE
RDF
SCFRDR value
ID1
ID2
Data2
RXI interrupt request (multiprocessor interrupt) MPIE = 0
SCFRDR data read and RDF flag cleared to 0 by RXI interrupt handler
As data matches this station’s ID, reception continues and data is received by RXI interrupt handler
MPIE bit set to 1 again
(b) Data matches station’s ID
Figure 14.15 Example of SCIF Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit, LSB-First Transfer)
Rev. 2.00, 03/05, page 618 of 884
14.3.4
Operation in Synchronous Mode
In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex communication using a common clock. Both the transmitter and the receiver also have a 16-stage FIFO buffer structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 14.16 shows the general format for synchronous serial communication.
One unit of transfer data (character or frame) * Serial clock *
LSB
MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don’t care
Serial data
Don’t care
Bit 0
Note: * High except in continuous transmission/reception
Figure 14.16 Data Format in Synchronous Communication (Example of LSB-First Transfer) In synchronous serial communication, data on the communication line is output from one fall of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In serial communication, each character is output starting with the LSB and ending with the MSB, or vice versa, according to the setting of the TLM bit in the serial status 2 register (SC2SSR). After the last data is output, the communication line remains in the state of the last data. In synchronous mode, the SCIF receives data in synchronization with the rising edge of the serial clock.
Rev. 2.00, 03/05, page 619 of 884
Transmit/Receive Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock: Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/ bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source selection, see table 14.9. When the SCIF is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transmission/reception is performed the clock is fixed high. In receive-only operation, however, the SCIF receives two characters as one unit, and so a 16-pulse serial clock is output. To perform single-character receive operations, an external clock should be selected as the clock source. Transmit/Receive Operations • SCIF Initialization (Synchronous Mode) Before transmitting and receiving data, it is necessary to clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF as described below. When the operating mode, communication format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDFE flag is set to 1 and the transmit shift register (SCTSR) is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDF, PER, FER, and ORER flags, or the receive FIFO data register (SCFRDR). Figure 14.17 shows a sample SCIF initialization flowchart.
Rev. 2.00, 03/05, page 620 of 884
A
Initialization Clear TE and RE bits to 0 in SCSCR Clear TFRST and RFRST bits to 1 in SCFCR Set RIE, TIE, MPIE, CKE1, and CKE0 bits in SCSCR (leaving TE and RE bits cleared to 0)
[1] Set the clock selection in SCSCR. Be sure to clear bits RIE, TIE, MPIE, TE, and RE to 0. [2] Set the transmit/receive format in the serial mode register (SCSMR). [3] Write a value corresponding to the bit rate into the bit rate register (SCBRR). (Not necessary if an external clock is used.)
[1]
Set data transmit/receive format [2] in SCSMR Set value in SCBRR Wait No
[4] Wait at least one bit interval, then set the TE bit or RE bit to 1 in SCSCR. Also set the RIE, TIE, and MPIE bits. Setting the TE and RE bits simultaneously enables the TxD and RxD pins to be used.
[3]
1-bit interval elapsed? Yes Set RTRG1–0 bits and TTRG1–0 bits in SCFCR, and clear TFRST and RFRST bits to 0
Set TE or RE bit to 1 in SCSCR, [4] and set RIE, TIE, and MPIE bits End
Figure 14.17 Sample SCIF Initialization Flowchart
Rev. 2.00, 03/05, page 621 of 884
• Serial Data Transmission (Synchronous Mode) Figure 14.18 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Initialization [1] [1] PFC initialization: Set the TxD pin, and the SCK pin if necessary, with the PFC. [2] SCIF status check and transmit data write: Read SC1SSR and check that TDFE =1, then write transmit data to the transmit FIFO data register (SCFTDR) and clear the TDFE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE flag to 0.
Start of transmission
Read TDFE flag in SC1SSR
[2] No
TDFE = 1? Yes Write transmit data to SCFTDR and clear TDFE flag to 0 in SC1SSR
All data transmitted? Yes Read TEND flag in SC1SSR
No [3]
TEND = 1? Yes Clear TE bit to 0 in SCSCR
No
End
Figure 14.18 Sample Serial Transmission Flowchart
Rev. 2.00, 03/05, page 622 of 884
In serial transmission, the SCIF operates as described below. 1. When data is written to the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR), and starts transmitting. Check that the TDFE flag is set to 1 in the serial status 1 register (SC1SSR) before writing transmit data to SCFTDR. The number of data bytes that can be written is at least {16 – (transmit trigger set number)}. 2. When data is transferred from SCFTDR to SCTSR and transmission is started, transmit operations are performed continually until there is no transmit data left in SCFTDR. If the number of data bytes in SCFTDR falls to or below the transmit trigger number set in the FIFO control register (SCFCR) during transmission, the TDFE flag is set. If the TIE bit setting in the serial control register (SCSCR) is 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) is requested. When clock output mode has been set, the SCIF outputs eight serial clock pulses for one unit of data. When use of an external clock has been specified, data is output in synchronization with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) or MSB (bit 7) according to the setting of the TLM bit in the serial status 2 register (SC2SSR). 3. The SCIF checks for transmit data in SCFTDR at the timing for sending the last bit. If there is transmit data in SCFTDR, it is transferred to SCTSR and then serial transmission of the next frame is started. If there is no transmit data in SCFTDR, the TEND flag is set to 1 in the serial status 1 register (SC1SSR), the last bit is sent, and then the transmit data pin (TxD) holds its state. 4. After completion of serial transmission, the SCK pin is fixed high. Figure 14.19 shows an example of SCIF operation in transmission.
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Transfer direction Serial clock LSB Serial data Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TDFE
TEND TXI interrupt request Data written to SCFTDR and TDFE flag cleared to 0 by TXI interrupt handler One frame TXI interrupt request
Figure 14.19 Example of SCIF Transmit Operation (Example of LSB-First Transfer) • Serial Data Reception (Synchronous Mode) Figure 14.20 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. When changing the operating mode from asynchronous to synchronous without resetting SCFRDR and SCFTDR by means of SCIF initialization, be sure to check that the ORER, PER3 to PER0, and FER3 to FER0 flags are all cleared to 0. The RDF flag will not be set if any of flags FER3 to FER0 or PER3 to PER0 are set to 1, and neither transmit nor receive operations will be possible.
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Initialization
[1]
[1] PFC initialization: Set the RxD pin, and the SCK pin if necessary, with the PFC. [2] Receive error handling: If a receive error occurs, read the ORER flag in SC2SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [2] [3] SCIF status check and receive data read: Read the serial status 1 register (SC1SSR) and check that RDF = 1, then read receive data from the receive FIFO data register (SCFRDR) and clear the RDF flag to 0. Transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [4] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of data bytes from SCFRDR, and write 0 to the RDF flag after reading 1 from it. The number of receive data bytes in SCFRDR can be ascertained by reading the lower 8 bits of the FIFO data count register (SCFDR). (The RDF bit is cleared automatically when the DMAC is activated by an RXI interrupt and the SCFRDR value is read.)
Start of reception
Read ORER flag in SC2SSR
ORER = 1? No
Yes
Error handling [3]
Read RDF flag in SC1SSR
No
RDF = 1? Yes Read receive data from SCFRDR, and clear RDF flag to 0 in SC1SSR [4]
No
All data received? Yes Clear RE bit to 0 in SCSCR
End of reception
Figure 14.20 Sample Serial Reception Flowchart (1)
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Error handling
No
ORER = 1? Yes Overrun error handling
Clear ORER flag to 0 in SC2SSR
End
Figure 14.20 Sample Serial Reception Flowchart (2) In serial reception, the SCIF operates as described below. 1. The SCIF performs internal initialization in synchronization with serial clock input or output. 2. The received data is stored in the receive shift register (SCRSR) in LSB-to-MSB order or MSB-to-LSB order according to the setting of the RLM bit in SC2SSR. After reception, the SCIF checks whether the receive data can be transferred from SCRSR to the receive FIFO data register (SCFRDR). If this check is passed, the receive data is stored in SCFRDR. If a receive error is detected in the error check, the operation is as shown in table 14.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. Also, as the RDF flag is not set to 1 when receiving, the flag must be cleared to 0. 3. If the RIE bit setting in the serial control register (SCSCR) is 1 when the RDF flag is set to 1, a receive-FIFO-data-full interrupt (RXI) is requested. If the RIE bit setting in SCRSR is 1 when the ORER flag is set to 1, a receive-error interrupt (ERI) is requested. Figure 14.21 shows an example of SCIF operation in reception.
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Transfer direction Serial clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDF
ORER RXI interrupt request Data read from SCFRDR and RDF flag cleared to 0 by RXI interrupt handler One frame RXI interrupt request ERI interrupt request due to overrun error
Figure 14.21 Example of SCIF Receive Operation (Example of LSB-First Transfer) • Simultaneous Serial Data Transmission and Reception (Synchronous Mode) Figure 14.22 shows a sample flowchart for simultaneous serial transmit and receive operations. Use the following procedure for simultaneous serial data transmit and receive operations after enabling the SCIF for transmission and reception.
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Initialization Start of transmission/ reception
[1]
[1] PFC initialization: Set the TxD and RxD pins, and the SCK pin if necessary, with the PFC. [2] SCIF status check and transmit data write: Read SC1SSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR and clear the TDFE flag to 0. Transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error handling: If a receive error occurs, read the ORER flag in SC2SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCIF status check and receive data read: Read SC1SSR and check that the RDF flag is set to 1, then read receive data from SCFRDR and clear the RDF flag to 0. Transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission/reception continuation procedure: To continue serial transmission/reception, finish reading the RDF flag, reading SCFRDR, and clearing the RDF flag to 0, before the MSB (bit 7) of the current frame is received. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR and clear the TDFE flag to 0. Note: When switching from transmitting or receiving to simultaneous transmitting and receiving, first clear the TE bit and RE bit to 0, then set the TE bit and RE bit to 1 simultaneously.
Read TDFE flag in SC1SSR No
[2]
TDFE = 1? Yes Write transmit data to SCFTDR and clear TDRE flag to 0 in SC1SSR
Read ORER flag in SC2SSR Yes [3] No Error handling
ORER = 1?
Read RDF flag in SC1SSR No
RDF = 1? Yes Read receive data from SCFRDR, and clear RDF flag to 0 in SC1SSR [4]
No
All data transferred? Yes Clear TE and RE bits to 0 in SCSCR
[5]
End of transmission/ reception
Figure 14.22 Sample Flowchart for Serial Data Transmission and Reception
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14.3.5
Use of Transmit/Receive FIFO Buffers
The SCIF has independent 16-stage FIFO buffers for transmission and reception. The configuration of these buffers is shown in figure 14.23.
TxD RxD
SCTSR
P P/G
SCRSR
PF
SCFTDR 1st stage 2nd stage 3rd stage
SCFRDR 1st stage 2nd stage 3rd stage
Error counter
SC1SSR PER3–PER0 FER3–FER0
16th stage
16th stage Data counter SCFDR T3–T0 R3–R0
SCFER ED15–ED0
Transmit data writes by CPU or DMAC
Receive data reads by CPU or DMAC
Figure 14.23 Transmit/Receive FIFO Configuration
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In Serial Data Transmit Operations: In transmission, when transmit data is written to the transmit FIFO by the CPU or DMAC and the TE bit is set to 1 in the serial control register (SCSCR), the data is first transferred to the transmit shift register (SCTSR) in the order of writing to the transmit FIFO, a parity bit is added by the parity generator (P/G), and then serial data is transmitted from the TxD pin. Each time data is written into the transmit FIFO, the value in bits T4 to T0 in the FIFO data count register (SCFDR) is incremented, and each time data is transferred to SCTSR the value in bits T4 to T0 is decremented. The current number of data bytes in the transmit FIFO can thus be found by reading bits T4 to T0 in SCFDR. A value of H'10 in bits T4 to T0 means that data has been written into all 16 stages of the transmit FIFO. If additional data is written to the FIFO in this state, bits T4 to T0 will not be incremented and the written data will be lost. When the transmit trigger number is set and transmit data is written to the FIFO by the DMAC, care must be taken not to write data exceeding the number of empty bytes in SCFTDR indicated by the FIFO control register (SCFCR) (see section 14.2.10). In Serial Data Receive Operations: In reception, serial data input from the RxD pin is first captured in the receive shift register (SCRSR) in the order specified by the RLM bit in the serial status 2 register (SC2SSR). A parity bit check is carried out, and if there is a parity error the P (parity error) flag for that data is set to 1. A stop bit check is also performed, and if a framing error is found the F (framing error) flag for that data is set to 1. The receive FIFO buffer has a 10-bit configuration, with the P and F flags for each 8-bit data unit stored together with that data. • Receive FIFO Control in Normal Operation Receive data held in the receive FIFO buffer is read by the CPU or DMAC. Each time data is transferred from SCRSR to the receive FIFO, the value in bits R4 to R0 in SCFDR is incremented, and each time the CPU or DMAC reads receive data from the receive FIFO, the value in bits R4 to R0 is decremented. The current number of data bytes in the receive FIFO can thus be found by reading bits R4 to R0 in SCFDR. A value of H'10 in bits R4 to R0 means that receive data has been transferred to all 16 stages of the receive FIFO. If the next serial receive operation is completed before the CPU or DMAC reads data from the receive FIFO, an overrun error will result and the serial data will be lost. If receive FIFO data is read when the value of bits R4 to R0 is H'00, an undefined value will be returned.
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• Receive FIFO Control in Error Data Reception When data is transferred from SCRSR to the receive FIFO, the P and F flags are also transferred. If either of these flags is set to 1, the error counter is incremented and the corresponding bit (PER3 to PER0, FER3 to FER0) is updated in the serial status 1 register (SC1SSR). The error counter is decremented if the P or F flag is 1 when data in the receive FIFO is read by the CPU or DMAC. The settings of the P and F flags for the read receive data are also reflected in the PER and FER flags in SC1SSR. PER and FER are set when data containing a parity error or framing error is read from the receive FIFO; they are not set when serial data containing a parity error or framing error is received from the RxD pin. PER and FER are cleared when data with no parity error or framing error is read from the receive FIFO. This data is transferred to the receive FIFO even if it contains a parity error or framing error. Whether or not the receive operation is to be continued at this point can be specified with the EI bit in SC2SSR. If the EI bit is set to 1, specifying continuation of the receive operation, receive data is still transferred sequentially to the receive FIFO after an error occurs. The stage of the 16-stage FIFO buffer in which the data with the error is located can be determined by reading bits ED15 to ED0 in the FIFO error register (SCFER). When the receive trigger number is set and receive data is read from the receive FIFO by the DMAC, care must be taken not to read data exceeding the receive trigger number indicated by the FIFO control register (SCFCR) (see section 14.2.10). • Receive FIFO Control by DR Flag When a number of data bytes equal to or exceeding the receive trigger number have been received, a receive data read request is issued to the CPU or DMAC by means of an RXI interrupt (RDF only). However, an RXI interrupt is not requested if all reception has been completed with fewer than the receive trigger number of data bytes having been received. In this case, the DR flag is set and an ERI interrupt is requested 16 etu after reception of the last data is completed. The CPU should therefore read bits R4 to R0 in SCFDR to find the number of data bytes left in the receive FIFO, and read all the data in the FIFO. Note: With an 8-bit, 1-stop-bit format, one etu is equivalent to 1.6 frames. etu: Elementary time unit = sec/bit
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14.3.6
Operation in IrDA Mode
In IrDA mode, the waveform of TxD/RxD transmit/receive data is modified to comply with the IrDA 1.0 infrared communication specification. This makes it possible to carry out infrared transmission and reception conforming to the IrDA 1.0 standard by connecting an infrared transmission/reception transceiver/receiver. In the IrDA 1.0 specification, communication is initially executed at 9600 bps, and then the transfer rate can be changed as required. However, the communication speed is not changed automatically in this module. When executing communication, therefore, it is necessary to check the communication speed and have the appropriate speed set in this module by software. Note: In IrDA mode, reception is not possible when the TE bit is set to 1 (enabling communication) in the serial control register (SCSCR). When performing reception, the TE bit in SCSCR must be cleared to 0. Transmission: In the case of a serial output signal (UART frame) from the SCIF, the waveform is corrected and the signal is converted to an IR frame serial output signal by the IrDA module as shown in figure 14.24. When the serial data is 0, if the PSEL bit is 0 in the IrDA mode register (SCIMR) a pulse of 3/16 the IR frame bit width is generated and output, and if the PSEL bit is 1 a pulse of 3/16 the bit width of the bit rate set in bits ICK3 to 0 in the serial mode register (SCSMR) is generated and output. When the serial data is 1, a pulse is not output. An infrared LED is driven by a signal demodulated to a 3/16 width. Reception: Pulses of 3/16 the received IR frame bit width are converted to UART frames after demodulation as shown in figure 14.24. Demodulation to 0 is executed for pulse output and demodulation to 1 when there is no pulse output.
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UART frame Start bit Data Stop bit
0
1
0
1
0
0
1
1
0
1
Transmission
Reception IR frame Start bit Data Stop bit
0
1
0
1
0
0
1
1
0
1
3/16 bit cycle pulse width Bit cycle
Figure 14.24 IrDA Mode Transmit/Receive Operations Pulse Width Selection: In transmission, the IR frame pulse width can be selected as either 3/16 of the transmission bit rate or a smaller pulse width by means of the PSEL bit in the IrDA mode register (SCIMR). The SCIF includes a baud rate generator that generates the transmit frame bit rate and a baud rate generator that generates the IRCLK signal for varying the pulse width. When the PSEL bit is cleared to 0 in SCIMR, a width of 3/16 the bit rate set in the bit rate register (SCBRR) is output as the IR frame pulse width. As the pulse width is the direct infrared emission time; if the user wishes to minimize the pulse width in order to reduce power consumption, the PSEL bit should be set to 1 in SCIMR and a setting should also be made in bits ICK3 to ICK0 in the serial mode register (SCSMR) to generate the IRCLK signal, resulting in output with the minimum settable pulse width.
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The minimum IR frame pulse width must be 3/16 of the 115.2 kbps bit rate (= 1.63 µs). With this minimum pulse width, IRCLK = 921.6 kHz, and so the setting for bits ICK3 to ICK0 to give the minimum settable pulse width is given by the following equation.
N≥ Pφ 2 × IRCLK –1
Pφ: Operating clock frequency IRCLK: 921.6 kHz (fixed) N: Set value of ICK3 to ICK0 (0 ≤ N ≤ 15)
For example, when Pφ = 20 MHz, N = 10. Table 14.12 shows the settings of bits ICK3 to ICK0 that can be used to obtain the minimum pulse width for various operating frequencies. Table 14.12 Bits ICK3 to ICK0 and Operating Frequencies in IrDA mode (When PSEL = 1)
Operating Frequency Pφ (MHz) 2 3 5 6 8 10 12 14 16 18 20 21 22 23 24 25 26 27 28 1 1 0 1 1 0 0 1 1 0 1 Setting of Bits ICK3 to ICK0 in SCSMR ICK3 0 ICK2 0 ICK1 0 ICK0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1
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14.4
SCIF Interrupt Sources and the DMAC
The SCIF has four interrupt sources: the break interrupt (BRI) request, receive-error interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and transmit-FIFO-data-empty interrupt (TXI) request. Table 14.13 shows the interrupt sources and their relative priorities. The interrupt sources can be enabled or disabled with the TIE or RIE bit in SCSCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDFE flag is set to 1 in the serial status 1 register (SC1SSR), a TXI interrupt is requested. A TXI interrupt request can activate the on-chip DMAC to perform data transfer. The TDFE bit is cleared to 0 automatically when all writes to the transmit FIFO data register (SCFTDR) by the DMAC are completed. When the RDF flag is set to 1 in SC1SSR, an RXI interrupt is requested. An RXI interrupt request can activate the on-chip DMAC to perform data transfer. The RDF bit is cleared to 0 automatically when all receive FIFO data register (SCFRDR) reads by the DMAC are completed. When the ER flag is set to 1, an ERI interrupt is requested. The on-chip DMAC cannot be activated by an ERI interrupt request. When the BRK flag is set to 1, a BRI interrupt is requested. The on-chip DMAC cannot be activated by a BRI interrupt request. A TXI interrupt indicates that transmit data can be written, and an RXI interrupt indicates that there is receive data in SCFRDR. Table 14.13 SCIF Interrupt Sources
Interrupt Source ERI RXI BRI TXI Description Receive error (ER) Receive data full (RDF) or data ready (DR) Break (BRK) Transmit data FIFO empty (TDFE) DMAC Activation Not possible Possible (RDF only) Not possible Possible Low Priority on Reset Release High
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14.5
Usage Notes
The following points should be noted when using the SCIF. SCFTDR Writing and the TDFE Flag: The TDFE flag in the serial status 1 register (SC1SSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO data count register (SCFDR). Simultaneous Multiple Receive Errors: If a number of receive errors occur at the same time, the state of the status flags in SC1SSR and SC2SSR is as shown in table 14.14. If there is an overrun error, data is not transferred from the receive shift register (SCRSR) to the receive FIFO data register (SCFRDR), and the receive data is lost. Table 14.14 SC1SSR/SC2SSR Status Flags and Transfer of Receive Data
SC1SSR/SC2SSR Status Flags Receive Errors Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error RDF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer SCRSR → SCFRDR × O O × × O ×
Note: O: Receive data is transferred from SCRSR to SCFRDR. ×: Receive data is not transferred from SCRSR to SCFRDR.
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Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that although the SCIF stops transferring receive data to SCFRDR after receiving a break, the receive operation continues, so if the FER and BRK flags are cleared to 0 they will be set to 1 again. Sending a Break Signal: The TxD pin is a general I/O pin whose input/output direction and level are determined by the I/O port data register (DR) and the control register (CR) of the pin function controller (PFC). This fact can be used to send a break signal. The DR value substitutes for the mark state until the PFC setting is made. The initial setting should therefore be as an output port outputting 1. To send a break signal during serial transmission, clear DR, then set the TxD pin as an output port with the PFC. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state. Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission cannot be started when any of the receive error flags (ORER, PER3 to PER0, FER3 to FER0) is set to 1, even if the TDFE flag is set to 1. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags are not cleared to 0 by clearing the RE bit to 0. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous mode, the SCIF operates on a base clock with a frequency of 16, 8, or 4 times the transfer rate. In reception, the SCIF synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth, fourth, or second base clock pulse. The timing is shown in figure 14.25.
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16 clocks 8 clocks
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
Base clock –7.5 clocks Receive data (RxD) Start bit +7.5 clocks
D0
D1
Synchronization sampling timing
Data sampling timing
Figure 14.25 Receive Data Sampling Timing in Asynchronous Mode (Using base clock with frequency of 16 times the transfer rate, sampled in 8th clock cycle) The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = 0.5 – 1 D – 0.5 (1 + F) × 100% – (L – 0.5) F – 2N N
................. ............ (1)
M: N: D: L: F:
Receive margin (%) Ratio of clock frequency to bit rate (N = 16, 8, or 4) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5, F = 0, and N = 16:
M = (0.5 – 1/(2 × 16)) × 100% = 46.875%...................................................................................................... (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. When Using Synchronous External Clock Mode • Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock SCK has changed from 0 to 1. • Only set both TE and RE to 1 when external clock SCK is 1. • In reception, note that if RE is cleared to 0 from 2.3 to 3.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK input, RDF will be set to 1 but copying to SCFRDR will not be possible.
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When Using Synchronous Internal Clock Mode: In reception, note that if RE is cleared to zero 1.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output, RDF will be set to 1 but copying to SCFRDR will not be possible. When Using the DMAC: When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 Pφ clock cycles after SCFTDR is updated by the DMAC. Incorrect operation may result if the transmit clock is input within 4 Pφ cycles after SCFTDR is updated. (See figure 14.26.) When performing SCFRDR reads by the DMAC, be sure to set the relevant SCIF receive-FIFOdata-full interrupt (RXI) as an activation source.
SCK t TDFE
TXD
D0
D1
D2
D3
D4
D5
D6
Figure 14.26 Example of Synchronous Transmission by DMAC SCFRDR Reading and the RDF Flag: The RDF flag in the serial status 1 register (SC1SSR) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR is equal to or greater than the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after receive data has been read to reduce the number of data bytes in SCFRDR to less than the trigger number. The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register (SCFDR).
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SCFRDR Reading when Overrun Occurs: If a receive operation is continued despite the fact that the receive FIFO data register (SCFRDR) contains 16 bytes of data, overrun will occur. If SCFRDR is read in this state, the data that caused the overrun is read in the 17th read. The value returned in the 18th and subsequent reads will be undefined. Also note that, from the first SCFRDR read onward, the number of receive data bytes in SCFRDR indicated by the lower 8 bits of the FIFO data count register (SCFDR) is one more than the actual number of receive data bytes. SCIF Initialization Flowchart and Receive-FIFO-Data-Full Interrupt (RXI) Requests Phenomenon: When the SCIF function is used and the operation in the SCIF initialization flowchart example in figure 14.4 is executed two or more times consecutively, the SCIF receive FIFO data full interrupt (RXI) request may be set in the second or later initialization operations, even if there is no received data. Condition: Figure 14.27 shows an example of SCIF initialization flowchart with 2nd initialization. RXI request may be set at the trigger (RTRG1, RTRG0) setting [2] of 2nd initialization when you try to reset the value of the Receive FIFO Data Number Trigger (RTRG1, RTRG0) setting [1] of 1st initialization. Countermeasures: Please apply any of the following countermeasures, if the write-access occurs at the Receive FIFO Data Number Trigger setting [2] of 2nd initialization. (1) Read out SCFCR and write the same value with the Receive FIFO Data Number Trigger (RTRG1, RTRG0). (2) Set Receive Interrupt Enable (RIE) bit to “0” in SCSCR before changing the value of the Receive FIFO Data Number Trigger (RTRG1, RTRG0). Mask the RXI request. After writing the SCFCR, clear the interrupt request to Receive Data Register Full (RDF). Set Receive Interrupt Enable (RIE) bit to “1” in SCSCR to terminate the mask-setting.
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Initialization
Clear TE and RE bits to 0 in SCSCR Set TFRST and RFRST bits to 1 in SCFCR Set CKE1 and CKE0 bits in SCSCR (leaving TE and RE bits cleared to 0) Set transmit/receive format in SCSMR 1st initialization Set value in SCBRR Wait No Reset the transmit/receive data resister
1-bit interval elapsed? Yes
Set RTRG1, RTRG0 and TTRG1, TTRG0 bits in SCFCR, and clear TFRST and RFRST bits to 0
[1] Trigger setting Set the transmit/receive FIFO data count
Set TE or RE bit to 1 in SCSCR, and set RIE, TIE and MPIE bits
Clear TE and RE bits to 0 in SCSCR Set TFRST and RFRST bits to 1 in SCFCR [2] Trigger setting RXI request may be set when the value of the receive FIFO data count has been changed from 1st initialization.
Set CKE1 and CKE0 bits in SCSCR (leaving TE and RE bits cleared to 0) Set transmit/receive format in SCSMR 2nd initialization Set value in SCBRR Wait No
1-bit interval elapsed? Yes
Set RTRG1, RTRG0 and TTRG1, TTRG0 bits in SCFCR, and clear TFRST and RFRST bits to 0 Set TE or RE bit to 1 in SCSCR, and set RIE, TIE and MPIE bits
Figure 14.27 Example of SCIF Initialization Flowchart
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Section 15 Serial I/O (SIO)
15.1 Overview
A three-channel simple synchronous serial I/O is provided on-chip. The serial I/O functions mainly as an interface between the chip and a codec or modem analog front-end. 15.1.1 Features
The serial I/O has the following features: • Full-duplex operation Independent transmit/receive registers and independent transmit/receive clocks • Double-buffered transmit/receive ports Continuous data transmission/reception possible • Interval transfer mode and continuous transfer mode • Memory-mapped receive register, transmit register, control register, and status register With the exception of SIRSR and SITSR, these registers are memory-mapped and can be accessed by a MOV instruction. • Choice of 8- or 16-bit data length • Data transfer communication by means of polling or interrupts Data transfer can be monitored by polling the receive data register full flag (RDRF) and transmit data register empty flag (TDRE) in the serial status register. Interrupt requests can be generated during data transfer by setting the receive interrupt request flag and transmit interrupt request flag. • MSB-first transfer between SIO and data I/O Figure 15.1 shows a block diagram of the serial I/O.
Rev. 2.00, 03/05, page 643 of 884
Peripheral bus
16
SIRDR
SISTR SICTR Bit counter I/O control unit
SITDR
SIRSR
MSB LSB
SITSR
MSB LSB
Serial I/O module (SIO) SRxD SIRDR: SIRSR: SISTR: SICTR: SITDR: SITSR: SRCK SRS STS STCK STxD
Receive data register Receive shift register Serial status register Serial control register Transmit data register Transmit shift register
Figure 15.1 SIO Block Diagram
Rev. 2.00, 03/05, page 644 of 884
Table 15.1 shows the functions of the external pins. As the channels are independent, the channel numbers are omitted from the signal names in the rest of this section. Table 15.1 Serial I/O (SIO) External Pins
Channel 0 Name Serial receive data input pin Serial receive clock input pin Serial reception synchronization input pin Serial transmit data output pin Serial transmit clock input pin Serial transmission synchronization input/output pin 1 Serial receive data input pin Serial receive clock input pin Serial reception synchronization input pin Serial transmit data output pin Serial transmit clock input pin Serial transmission synchronization input/output pin 2 Serial receive data input pin Serial receive clock input pin Serial reception synchronization input pin Serial transmit data output pin Serial transmit clock input pin Serial transmission synchronization input/output pin Pin SRxD0 SRCK0 SRS0 STxD0 STCK0 STS0 I/O Input Input Input Output Input I/O Function Serial data input port 0 Serial receive clock port 0 Serial reception synchronization input port 0 Serial data output port 0 Serial transmit clock port 0 Serial transmission synchronization input/output port 0 Serial data input port 1 Serial receive clock port 1 Serial reception synchronization input port 1 Serial data output port 1 Serial transmit clock port 1 Serial transmission synchronization input/output port 1 Serial data input port 2 Serial receive clock port 2 Serial reception synchronization input port 2 Serial data output port 2 Serial transmit clock port 2 Serial transmission synchronization input/output port 2
SRxD1 SRCK1 SRS1 STxD1 STCK1 STS1 SRxD2 SRCK2 SRS2 STxD2 STCK2 STS2
Input Input Input Output Input I/O Input Input Input Output Input I/O
Note: In a reset, all pins are initialized to the high-impedance state.
Rev. 2.00, 03/05, page 645 of 884
15.2
Register Configuration
Table 15.2 shows the SIO’s registers. As the channels are independent, the channel numbers are omitted from the signal names in the rest of this section. Table 15.2 Register Configuration
Channel 0 Register Receive shift register 0 Receive data register 0 Transmit shift register 0 Transmit data register 0 Serial control register 0 Serial status register 0 1 Receive shift register 1 Receive data register 1 Transmit shift register 1 Transmit data register 1 Serial control register 1 Serial status register 1 2 Receive shift register 2 Receive data register 2 Transmit shift register 2 Transmit data register 2 Serial control register 2 Serial status register 2 Note: * Abbreviation SIRSR0 SIRDR0 SITSR0 SITDR0 SICTR0 SISTR0 SIRSR1 SIRDR1 SITSR1 SITDR1 SICTR1 SISTR1 SIRSR2 SIRDR2 SITSR2 SITDR2 SICTR2 SISTR2 R/W — R — R/W R/W R/(W)* — R — R/W R/W R/(W)* — R — R/W R/W R/(W)* Initial Value — H'0000 — H'0000 H'0000 H'0002 — H'0000 — H'0000 H'0000 H'0002 — H'0000 — H'0000 H'0000 H'0002 Address — — Access Size (Bits) — —
H'FFFFFC00 8, 16, 32 H'FFFFFC02 8, 16, 32 H'FFFFFC04 8, 16, 32 H'FFFFFC06 8, 16, 32 — — — — H'FFFFFC10 8, 16, 32 H'FFFFFC12 8, 16, 32 H'FFFFFC14 8, 16, 32 H'FFFFFC16 8, 16, 32 — — — — H'FFFFFC20 8, 16, 32 H'FFFFFC22 8, 16, 32 H'FFFFFC24 8, 16, 32 H'FFFFFC26 8, 16, 32
Only 0 should be written, to clear flags (after reading 1 from the flag).
Rev. 2.00, 03/05, page 646 of 884
15.2.1
Receive Shift Register (SIRSR)
Bit: Initial value: R/W: 15 — — 14 — — 13 — — ... ... ... ... — — — — — — — — 3 2 1 0
SIRSR is a 16-bit register used to receive serial data. The data is fetched in MSB first from the SRxD pin in synchronization with the fall of the serial receive clock (SRCK), and is shifted into SIRSR. The data length is set by the transmit/receive data length select bit (DL) in the corresponding serial control register (SICTR). When data transfer to SIRSR is completed, the data contents are automatically transferred to the receive data register (SIRDR), and the receive data register full flag (RDRF) is set in the serial status register (SISTR). If the next data word input operation ends before the RDRF flag is cleared, an overrun error occurs, the receive overrun error flag (RERR) is set in SISTR, and an overrun error signal is sent to the interrupt controller (INTC). The data in SIRSR overwrites the data in SIRDR. 15.2.2 Receive Data Register (SIRDR)
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R ... ... ... ... 0 R 0 R 0 R 0 R 3 2 1 0
SIRDR is a 16-bit register that stores serial receive data. When data is transferred from SIRSR to SIRDR, the receive data register full flag (RDRF) is set in the serial status register (SISTR). If the receive interrupt enable flag (RIE) is set in SICTR, a receive-data-full interrupt (RDFI) request is sent to the interrupt controller (INTC) and the DMA controller (DMAC). When the flag is cleared, this interrupt request signal is not generated. When SIRDR is read by the DMAC, the RDRF flag is cleared automatically. SIRDR is initialized to H'0000 by a reset.
Rev. 2.00, 03/05, page 647 of 884
15.2.3
Transmit Shift Register (SITSR)
Bit: Initial value: R/W: 15 — — 14 — — 13 — — ... ... ... ... — — — — — — — — 3 2 1 0
SITSR is a 16-bit register used to transmit serial data. The contents of this register are shifted in MSB-first order in synchronization with the rising edge of the serial transmit clock (STCK), and output from the STxD pin. The transfer data length is set by the transmit/receive data length select bit (DL) in the serial control register (SICTR). When the DL bit is cleared to 0 (8-bit data length), the lower 8 bits of SITDR are output. When the serial transmission synchronization signal (STS) goes high, or the last data transmission ends without the synchronization enable (SE) bit being set in SICTR, the contents of the transmit data register (SITDR) are transferred to SITSR, and if TDRE is 0, TDRE is then set. If output of the next data begins before TDRE is cleared, an overrun error occurs, the transmit overrun error flag (TERR) is set in SISTR, and a transmit overrun error interrupt request is sent to the INTC. 15.2.4 Transmit Data Register (SITDR)
Bit: Initial value: R/W: 15 0 R/W 14 0 R/W 13 0 R/W ... ... ... ... 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0
SITDR is a 16-bit register that stores serial transmit data. Data should be written to SITDR when the transmit data register empty flag (TDRE) is set to 1 in SISTR. If data is written to SITDR when TDRE is 0, the previous data will be overwritten. When STS goes high or data output from transmit shift register SITSR ends with the SE bit cleared to 0 in SICTR, the data in SITDR is automatically transferred to SITSR, and if TDRE is 0, TDRE is then set. If the transmit interrupt enable flag (TIE) is set, a transmit-data-empty interrupt (TDEI) request is sent to the INTC and DMAC. When TIE is cleared, this interrupt request is not generated. When the DMAC writes to SITDR, the TDRE flag is cleared automatically. The TDRE flag is set only by hardware. SITDR is initialized to H'0000 by a reset.
Rev. 2.00, 03/05, page 648 of 884
15.2.5
Serial Control Register (SICTR)
Bit: Initial value: R/W: Bit: Initial value: R/W: 15 — 0 R 7 — 0 R 14 — 0 R 6 TM 0 R/W 13 — 0 R 5 SE 0 R/W 12 — 0 R 4 DL 0 R/W 11 — 0 R 3 TIE 0 R/W 10 — 0 R 2 RIE 0 R/W 9 — 0 R 1 TE 0 R/W 8 — 0 R 0 RE 0 R/W
SICTR is a 16-bit register used to set parameters for serial port control. SICTR is initialized to H'0000 by a reset. When modifying bit 4, 5, or 6 (TM, SE, or DL), TE and RE should be cleared to 0 beforehand. Bits 15 to 7—Reserved: These bits are always read as 0. The write value should always be 0. Bit 6—Transfer Mode Control (TM): Specifies whether the transmission synchronization signal is to be input from an external source or generated internally by the chip. When this flag is cleared, the transmission synchronization signal is STS pin input. When this flag is set, the transmission synchronization signal is generated by the chip, and is output to an external device from the STS pin. This bit does not affect reception.
Bit 6: TM 0 1 Description External signal input from STS pin is used as transmission start indication (Initial value) Internal signal output from STS pin is used as transmission start indication
Bit 5—Synchronization Signal Enable (SE): Specifies whether the synchronization signals are to be used for all serial data transfers, or only for the first transfer. When this bit is cleared to 0, the synchronization signals (SRS and STS) are necessary only for the first data transfer, and are not required for subsequent transfers. When this bit is set to 1, the synchronization signals are necessary for all data transfers.
Bit 5: SE 0 1 Description Continuous mode: SRS and STS are used only for the first data transfer (Initial value) Interval mode: SRS and STS are used for all data transfers Rev. 2.00, 03/05, page 649 of 884
Bit 4—Transmit/Receive Data Length Select (DL): Specifies the serial I/O module’s transfer data length. The initial value of this bit is 0, indicating an 8-bit data length. When an 8-bit data length is specified, the lower 8 bits of each I/O register are used.
Bit 4: DL 0 1 Description 8-bit transfer data length 16-bit transfer data length (Initial value)
Bit 3—Transmit Interrupt Enable (TIE): Enables the transmit-data-empty interrupt. The initial value of this bit is 0.
Bit 3: TIE 0 1 Description Transmit interrupt disabled Transmit interrupt enabled (Initial value)
Bit 2—Receive Interrupt Enable (RIE): Enables the receive-data-full interrupt. The initial value of this bit is 0.
Bit 2: RIE 0 1 Description Receive interrupt disabled Receive interrupt enabled (Initial value)
Bit 1—Transmit Enable (TE): Enables data transmission. When this flag is cleared, the STxD, STCK, and STS pins go to the high-impedance state.
Bit 1: TE 0 1 Description Transmission disabled: STxD, STCK, and STS pins go to high-impedance state (Initial value) Transmission enabled
Bit 0—Receive Enable (RE): Enables data reception. When this flag is cleared, the SRxD, SRCK, and SRS pins go to the high-impedance state.
Bit 0: RE 0 1 Description Reception disabled: SRxD, SRCK, and SRS pins go to high-impedance state (Initial value) Reception enabled
Rev. 2.00, 03/05, page 650 of 884
15.2.6
Serial Status Register (SISTR)
Bit: Initial value: R/W: 15 — 0 R 14 — 0 R ... ... ... ... 4 — 0 R 3 TERR 0 R/(W)* 2 RERR 0 R/(W)* 1 TDRE 1 R/(W)* 0 RDRF 0 R/(W)*
Note:
*
Only 0 should be written, to clear the flag.
SISTR is a 16-bit register that indicates the status of the serial I/O module. SISTR is initialized to H'0002 by a reset. Bits 15 to 4—Reserved: These bits are always read as 0. The write value should always be 0. Bit 3—Transmit Underrun Error (TERR): Flag that indicates the occurrence of a transmit underrun.
Bit 3: TERR 0 Description Transmission is in progress, or has ended normally [Clearing conditions] • • 1 W hen 0 is written to the TERR bit after reading TERR = 1 W hen the processor enters the reset state (Initial value)
A transmit underrun error has occurred TERR is set to 1 if data transmission is started while TDRE = 1
Bit 2—Receive Overrun Error (RERR): Flag that indicates the occurrence of a receive overrun.
Bit 2: RERR 0 Description Reception is in progress, or has ended normally [Clearing conditions] • • 1 W hen 0 is written to the RERR bit after reading RERR = 1 W hen the processor enters the reset state (Initial value)
A receive overrun error has occurred RERR is set to 1 if data reception ends while RDRE = 1
Rev. 2.00, 03/05, page 651 of 884
Bit 1—Transmit Data Register Empty (TDRE): Flag that indicates that the SITDR register is empty and the next data can be written.
Bit 1: TDRE 0 Description SITDR transmit data is valid [Clearing conditions] • • 1 W hen 0 is written to the TDRE bit after reading TDRE = 1 W hen the DMAC writes data to SITDR (Initial value)
SITDR transmit data is invalid TDRE is set to 1 in the following cases: • • • W hen data is transferred from SITDR to SITSR
W hen the TE bit is cleared to 0 in the serial control register (SICTR) W hen the processor enters the reset state
Bit 0—Receive Data Register Full (RDRF): Flag that indicates that SIRDR receive data is waiting.
Bit 0: RDRF 0 Description SIRDR receive data is invalid [Clearing conditions] • • • • 1 W hen the DMAC reads data from SIRDR W hen 1 is read from RDRF and 0 is written W hen the RE bit is cleared to 0 in the serial control register (SICTR) W hen the processor enters the reset state (Initial value)
SIRDR receive data is valid RDRF is set to 1 when serial data reception ends normally and the data is transferred from SIRSR to SIRDR
Rev. 2.00, 03/05, page 652 of 884
15.3
15.3.1
Operation
Input
Figure 15.2 shows interval transfer mode (SE set to 1 in SICTR), and figure 15.3 shows continuous transfer mode (SE cleared to 0 in SICTR).
RDRF
synchronous internal clock
SIRDR SIRSR SRCK SRS SRxD
A[7] A[6] A[5] A[1] A[0] Undefined A[7] A[7:6] A[7:1]
A[7:0]
A[7:0]
B[7]
Invalid
B[7]
Note: DL = 0: 8-bit data transfer SE = 1: Synchronous transfer in start signal mode
Figure 15.2 Reception: Interval Transfer Mode
RDRF
synchronous internal clock
SIRDR SIRSR SRCK SRS SRxD
A[7] A[6] A[5] A[1] A[0] Undefined A[7] A[7:6] A[7:1]
A[7:0] A[7:0] B[7] B[7:6] B[7:5]
B[7]
B[6]
B[5]
Note: DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer, no start signal mode
Figure 15.3 Reception: Continuous Transfer Mode
Rev. 2.00, 03/05, page 653 of 884
15.3.2
Output
Figure 15.4 shows interval transfer mode (SE set to 1 in SICTR) when TM is cleared to 0 in SICTR. Figure 15.5 shows continuous transfer mode (SE cleared to 0 in SICTR) when TM is cleared to 0 in SICTR. Figure 15.6 shows interval transfer mode (SE set to 1 in SICTR) when TM is set to 1 in SICTR. Figure 15.7 shows continuous transfer mode (SE cleared to 0 in SICTR) when TM is set to 1 in SICTR.
TDRE
synchronous internal clock
SITDR SITSR STCK STS STxD
Data C Undefined C[7:0] C[6:0] C[5:0] C[0] D[7:0] D[6:0]
C[7]
C[6]
C[5]
C[1]
C[0]
Invalid
D[7]
Note: TM = 0: STS is input DL = 0: 8-bit data transfer SE = 1: Synchronous transfer in start signal mode
Figure 15.4 Transmission: Interval Transfer Mode (TM = 0 Mode)
Rev. 2.00, 03/05, page 654 of 884
TDRE
synchronous internal clock
SITDR SITSR STCK STS STxD
Data C Undefined C[7:0] C[6:0] C[5:0] C[0] D[7:0] D[6:0] D[5:0] D[4:0]
C[7]
C[6]
C[5]
C[1]
C[0]
D[7]
D[6]
D[5]
Note: TM = 0: STS is input DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer, no start signal mode
Figure 15.5 Transmission: Continuous Transfer Mode (TM = 0 Mode)
TDRE
synchronous internal clock
SITDR SITSR STCK STS STxD
Undefined
Data C C[7:0] C[6:0] C[5:0] C[0]
Data D D[7:0] D[6:0]
C[7]
C[6]
C[5]
C[1]
C[0]
Invalid
D[7]
Note: TM = 1: STS is output DL = 0: 8-bit data transfer SE = 1: Synchronous transfer in start signal mode
Figure 15.6 Transmission: Interval Transfer Mode (TM = 1 Mode)
Rev. 2.00, 03/05, page 655 of 884
TDRE
synchronous internal clock
SITDR SITSR
Undefined
Data C C[7:0] C[6:0] C[5:0] C[0] D[7:0] D[6:0] D[5:0] D[4:0]
STCK STS STxD
C[7] C[6] C[5] C[1] C[0] D[7] D[6] D[5]
Note: TM = 1: STS is output DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer, no start signal mode
Figure 15.7 Transmission: Continuous Transfer Mode (TM = 1 Mode)
Rev. 2.00, 03/05, page 656 of 884
15.4
SIO Interrupt Sources and DMAC
Each SIO channel has four interrupt sources: the receive-overrun-error interrupt (RERI) request, transmit-underrun-error interrupt (TERI) request, receive-data-full interrupt (RDFI) request, and transmit-data-empty interrupt (TDEI) request. Table 15.3 shows the interrupt sources and their relative priorities. The RDFI and TDEI interrupts are enabled by the RIE and TIE bits, respectively, in SICTR. The RERI and TERI interrupts cannot be disabled. An RDFI interrupt request is generated when the RDRF bit is set to 1 in SISTR. RDFI can activate the DMA controller (DMAC) to read the data in SIRDR. RDRF is cleared to 0 automatically when the DMAC reads data from SIRDR. A TDEI interrupt request is generated when the TDRE bit is set to 1 in SISTR. TDEI can activate the DMAC to write the next data to SITDR. TDRE is cleared to 0 automatically when the DMAC writes data to SITDR. When TDEI and RDFI interrupt requests are handled by the DMAC, and not by the interrupt controller, a low priority level should be given to interrupts from the SIO to prevent the interrupt controller from operating. When the RERR bit is set to 1 in SISTR, an RERI interrupt request is generated. When the TERR bit is set to 1 in SISTR, a TERI interrupt request is generated. Channel interrupt priority levels are set by means of the IRPE register, as described in section 5, Interrupt Controller (INTC). Table 15.3 SIO Interrupt Sources
Interrupt Source RERI TERI RDFI TDEI Description Receive overrun error (RERR) Transmit underrun error (TERR) Receive data register full (RDRF) Transmit data register empty (TDRE) DMAC Activation Not possible Not possible Possible Possible Low Priority High
Rev. 2.00, 03/05, page 657 of 884
Rev. 2.00, 03/05, page 658 of 884
Section 16 16-Bit Timer Pulse Unit (TPU)
16.1 Overview
An on-chip 16-bit timer pulse unit (TPU) is provided that comprises three 16-bit timer channels. 16.1.1 Features
The TPU has the following features: • Maximum 8-pulse input/output • A total of eight timer general registers (TGRs) are provided (four for channel 0 and two each for channels 1, and 2). Each register can be set independently as an output compare/input capture register. TGRC and TGRD for channel 0 can be used as buffer registers • Choice of seven or eight counter input clocks for each channel • The following operations can be set for each channel: Waveform output by compare match: Selection of 0, 1, or toggle output Input capture function: Choice of rising edge, falling edge, or both edge detection Counter clear operation: Counter clearing possible by compare match or input capture Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously simultaneous clearing by compare match and input capture possible register simultaneous input/output possible by counter synchronous operation PWM mode: Any PWM output duty can be set maximum of 7-phase PWM output possible by combination with synchronous operation • Buffer operation settable for channel 0 Input capture register double-buffering possible Automatic rewriting of output compare register possible • Phase counting mode settable independently for each of channels 1, and 2 Two-phase encoder pulse up/down-count possible • Fast access via internal 16-bit bus Fast access is possible via a 16-bit bus interface • 13 interrupt sources For channel 0 four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently For channels 1, and 2, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently
Rev. 2.00, 03/05, page 659 of 884
• Automatic transfer of register data Block transfer, 1-word data transfer, and 1-byte data transfer possible by direct memory access controller (DMAC) activation Table 16.1 lists the functions of the TPU. Table 16.1 TPU Functions
Item Count clock Channel 0 Pφ/1 Pφ/4 Pφ/16 Pφ/64 TCLKA TCLKB TCLKC TCLKD TGR0A TGR0B TGR0C TGR0D TIOCA0 TIOCB0 TIOCC0 TIOCD0 TGR compare match or input capture O O O O O O — O Channel 1 Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKA TCLKB TGR1A TGR1B — TIOCA1 TIOCB1 Channel 2 Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKA TCLKB TCLKC TGR2A TGR2B — TIOCA2 TIOCB2
General registers General registers/ buffer registers I/O pins
Counter clear function Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation
TGR compare match or input capture O O O O O O O —
TGR compare match or input capture O O O O O O O —
Notes: O : Possible — : Not possible
Rev. 2.00, 03/05, page 660 of 884
Item DMAC activation Interrupt sources
Channel 0
Channel 1
Channel 2 — 4 sources • • Compare match or input capture 2A Compare match or input capture 2B
TGR compare match or — input capture 5 sources • • • • • Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow • • Overflow Underflow 4 sources • • Compare match or input capture 1A Compare match or input capture 1B
• •
Overflow Underflow
Note: — : Not possible
Rev. 2.00, 03/05, page 661 of 884
16.1.2
Block Diagram
Figure 16.1 shows a block diagram of the TPU.
Clock input Internal clock: Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 External clock: TCLKA TCLKB TCLKC TCLKD
TSTR TSYR
Bus interface
Common
TMDR
Control logic
Internal data bus
Channel 2
TSR
TGRA
Module data bus
TIOR
TIER
TCR
TGRB
TCNT
Channel 0:
Control logic for channels 0 to 2
Channel 2:
TCR
Channel 1:
TIORH TIORL
TMDR
I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2
Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U
TMDR
Channel 1
TSR
TGRA
TIOR
Channel 0
TSR
TIER
TGRB TGRC TGRD TGRB
TCNT TCNT
TCR: TMDR: TIOR: TIER: TSR: TCNT: TGR: TSTR: TSYR:
Timer Control Register Timer Mode Register Timer I/O Control Register Timer Interrupt Enable Register Timer Status Register Timer Counter Timer General Register Timer Start Register Timer Synchro Register
Figure 16.1 TPU Block Diagram
Rev. 2.00, 03/05, page 662 of 884
TIER
TCR
TGRA
16.1.3
Input/Output Pins
Table 16.2 shows the pin configuration of the TPU. Table 16.2 Pin Configuration
Channel All Name Clock input A Abbreviation TCLKA I/O Input Function External clock A input pin (Channel 1 phase counting mode A phase input) External clock B input pin (Channel 1 phase counting mode B phase input) External clock C input pin (Channel 2 phase counting mode A phase input) External clock D input pin (Channel 2 phase counting mode B phase input) TGR0A input capture input/output compare output/PWM output pin TGR0B input capture input/output compare output/PWM output pin TGR0C input capture input/output compare output/PWM output pin TGR0D input capture input/output compare output/PWM output pin TGR1A input capture input/output compare output/PWM output pin TGR1B input capture input/output compare output/PWM output pin TGR2A input capture input/output compare output/PWM output pin TGR2B input capture input/output compare output/PWM output pin
Clock input B
TCLKB
Input
Clock input C
TCLKC
Input
Clock input D
TCLKD
Input
0
Input capture/output compare match A0 Input capture/output compare match B0 Input capture/output compare match C0 Input capture/output compare match D0
TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2
I/O I/O I/O I/O I/O I/O I/O I/O
1
Input capture/output compare match A1 Input capture/output compare match B1
2
Input capture/output compare match A2 Input capture/output compare match B2
Rev. 2.00, 03/05, page 663 of 884
16.1.4
Register Configuration
Table 16.3 shows the register configuration of the TPU. Table 16.3 Register Configuration
Channel Name 0 Abbreviation R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W Initial Value H'00 H'C0 H'00 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF Address H'FFFFFC50 H'FFFFFC51 H'FFFFFC52 H'FFFFFC53 H'FFFFFC54 H'FFFFFC55 H'FFFFFC56 H'FFFFFC58 H'FFFFFC5A H'FFFFFC5C H'FFFFFC5E H'FFFFFC60 H'FFFFFC61 H'FFFFFC62 H'FFFFFC64 H'FFFFFC65 H'FFFFFC66 H'FFFFFC68 H'FFFFFC6A Access size (Bits) 8,16 8,16 8,16 8,16 8,16 8,16 16 16 16 16 16 8,16 8,16 8,16 8,16 8,16 16 16 16
Timer control register 0 TCR0 Timer mode register 0 TMDR0 Timer I/O control register 0H Timer I/O control register 0L TIOR0H TIOR0L
Timer interrupt enable TIER0 register 0 Timer status register 0 TSR0 Timer counter 0 TCNT0 Timer general register TGR0A 0A Timer general register TGR0B 0B Timer general register TGR0C 0C Timer general register TGR0D 0D 1 Timer control register 1 TCR1 Timer mode register 1 TMDR1 Timer I/O control register 1 TIOR1
Timer interrupt enable TIER1 register 1 Timer status register 1 TSR1 Timer counter 1 TCNT1 Timer general register TGR1A 1A Timer general register TGR1B 1B
Rev. 2.00, 03/05, page 664 of 884
Channel Name 2
Abbreviation R/W R/W R/W R/W R/W
Initial Value H'00 H'C0 H'00 H'40
Address H'FFFFFC70 H'FFFFFC71 H'FFFFFC72 H'FFFFFC74 H'FFFFFC75 H'FFFFFC76
Access size (Bits) 8, 16 8, 16 8, 16 8, 16 8, 16 16 16 16 8, 16 8, 16
Timer control register 2 TCR2 Timer mode register 2 Timer I/O control register 2 Timer interrupt enable register 2 Timer status register 2 Timer counter 2 Timer general register 2A Timer general register 2B TMDR2 TIOR2 TIER2 TSR2 TCNT2 TGR2A TGR2B TSTR TSYR
R/(W)* H'C0 R/W R/W R/W R/W R/W H'0000
H'FFFF H'FFFFFC78 H'FFFF H'FFFFFC7A H'00 H'00 H'FFFFFC40 H'FFFFFC41
All Note: *
Timer start register Timer synchro register
Only 0 can be written, to clear the flags.
16.2
16.2.1
Register Descriptions
Timer Control Register (TCR)
Channel 0: TCR0 Bit: Initial value: R/W: Channel 1: TCR1 Channel 2: TCR2 Bit: Initial value: R/W: 7 — 0 R 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W 7 CCLR2 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
The TCR registers are 8-bit registers that control the TCNT channels. The TPU has three TCR registers, one for each of channels 0 to 2. The TCR registers are initialized to H'00 by a reset. TCNT operation should be stopped when making TCR settings.
Rev. 2.00, 03/05, page 665 of 884
Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter clearing source.
Channel 0 Bit 7: CCLR2 0 Bit 6: CCLR1 0 Bit 5: CCLR0 0 1 1 0 1 Description TCNT clearing disabled (Initial value)
TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture *2 TCNT cleared by TGRD compare match/input 2 capture * TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1
1
0
0 1
1
0 1
Channel 1, 2
Bit 7: Bit 6: Reserved*3 CCLR1 0 0
Bit 5: CCLR0 0 1
Description TCNT clearing disabled (Initial value)
TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation *1
1
0 1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 3. Bit 7 is reserved in channels 1 and 2. It is always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 666 of 884
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When a both-edges count is selected, a clock divided by two from the input clock can be selected. (e.g. Pφ/4 both edges = Pφ/2 rising edge). If phase counting mode is used on channels 1, and 2, this setting is ignored and the phase counting mode setting has priority.
Bit 4: CKEG1 0 1 Bit 3: CKEG0 0 1 — Description Count at rising edge Count at falling edge Count at both edges (Initial value)
Note: Internal clock edge selection is valid when the input clock is Pφ/4 or slower. If Pφ/1 is selected for the input clock, this setting is ignored and a rising-edge count is selected.
Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter clock. The clock source can be selected independently for each channel. Table 16.4 shows the clock sources that can be set for each channel. Table 16.4 TPU Clock Sources
Internal Clock Channel
0 1 2
External Clock TCLKA TCLKB TCLKC TCLKD
O O O O O O O
Pφ/1
O O O
Pφ/4
O O O
Pφ/16 Pφ/64 Pφ/256 Pφ/1024
O O O O O O O O
O O
Notes: O: Setting Blank: No setting
Rev. 2.00, 03/05, page 667 of 884
Channel 0
Bit 2: TPSC2 0
Bit 1: TPSC1 0 1
Bit 0: TPSC0 0 1 0 1 0 1 0 1
Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input (Initial value)
1
0 1
Channel 1
Bit 2: TPSC2 0
Bit 1: TPSC1 0 1
Bit 0: TPSC0 0 1 0 1 0 1 0 1
Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on Pφ/256 Setting prohibited (Initial value)
1
0 1
Note: This setting is ignored when channel 1 is in phase counting mode. Bit 2: TPSC2 0 Bit 1: TPSC1 0 1 1 0 1 Bit 0: TPSC0 0 1 0 1 0 1 0 1
Channel 2
Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on Pφ/1024 (Initial value)
Note: This setting is ignored when channel 2 is in phase counting mode.
Rev. 2.00, 03/05, page 668 of 884
16.2.2
Timer Mode Register (TMDR)
Channel 0: TMDR0 Bit: Initial value: R/W: Channel 1: TMDR1 Channel 2: TMDR2 Bit: Initial value: R/W: 7 — 1 R 6 — 1 R 5 — 0 R 4 — 0 R 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W 7 — 1 R 6 — 1 R 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset. TCNT operation should be stopped when making TMDR settings. Bits 7 and 6—Reserved: These bits are always read as 1. The write value should always be 1. Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5: BFB 0 1 Description TGRB operates normally TGRB and TGRD used together for buffer operation (Initial value)
Rev. 2.00, 03/05, page 669 of 884
Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified.
Bit 4: BFA 0 1 Description TGRA operates normally TGRA and TGRC used together for buffer operation (Initial value)
Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.
Bit 3: 1 MD3* 0 Bit 2: 2 MD2* 0 Bit 1: MD1 0 1 1 0 1 1 Bit 0: MD0 0 1 0 1 0 1 0 1 * * * Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — (Initial value)
*: Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be written to MD2.
Rev. 2.00, 03/05, page 670 of 884
16.2.3
Timer I/O Control Register (TIOR)
Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Bit: Initial value: R/W: Channel 0: TIOR0L Bit: Initial value: R/W: 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W 7 IOB3 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
The TIOR registers are 8-bit registers that control the TGR registers. The TPU has four TIOR registers, two for channel 0 and one each for channels 1, and 2. The TIOR registers are initialized to H'00 by a reset. Note that TIOR is affected by the TMDR setting. The initial output specified by TIOR becomes valid when the counter is halted (i.e. when the CST bit is cleared to 0 in TSTR). In PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.
Rev. 2.00, 03/05, page 671 of 884
Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD.
TIOR0H Bit 7: Bit 6: Bit 5: Bit 4: IOB3 IOB2 IOB1 IOB0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR0B is Capture input Input capture at rising edge input source is TIOCB0 Input capture at falling edge capture pin Input capture at both edges register Setting prohibited *: Don’t care TGR0B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Channel 0
Rev. 2.00, 03/05, page 672 of 884
TIOR0L Bit 7: Bit 6: Bit 5: Bit 4: IOD3 IOD2 IOD1 IOD0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR0D is Capture input Input capture at rising edge input source is TIOCD0 Input capture at falling edge capture pin Input capture at both edges register*1 Setting prohibited TGR0D is Output disabled output Initial output is 0 compare output register*1 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Channel 0
*: Don’t care Note: 1. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
Rev. 2.00, 03/05, page 673 of 884
TIOR1 Bit 7: Bit 6: Bit 5: Bit 4: IOB3 IOB2 IOB1 IOB0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR1B is Capture input Input capture at rising edge input source is TIOCB1 Input capture at falling edge capture pin Input capture at both edges register Setting prohibited *: Don’t care TIOR2 Bit 7: Bit 6: Bit 5: Bit 4: IOB3 IOB2 IOB1 IOB0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 * 0 1 0 1 * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge TGR2B is Capture input input source is TIOCB2 Input capture at falling edge capture pin Input capture at both edges register *: Don’t care TGR2B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match TGR1B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Channel 1
Channel 2
Rev. 2.00, 03/05, page 674 of 884
Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC.
TIOR0H Bit 3: Bit 2: Bit 1: Bit 0: IOA3 IOA2 IOA1 IOA0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR0A is Capture input Input capture at rising edge input source is TIOCA0 Input capture at falling edge capture pin Input capture at both edges register Setting prohibited *: Don’t care TGR0A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Channel 0
Rev. 2.00, 03/05, page 675 of 884
TIOR0L Bit 3: Bit 2: Bit 1: Bit 0: IOC3 IOC2 IOC1 IOC0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge TGR0C is Capture input source is TIOCC0 Input capture at falling edge input pin capture 1 Input capture at both edges register* Setting prohibited TGR0C is Output disabled output Initial output is 0 compare output 1 register* (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Channel 0
*: Don’t care Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
Rev. 2.00, 03/05, page 676 of 884
TIOR1 Bit 3: Bit 2: Bit 1: Bit 0: IOA3 IOA2 IOA1 IOA0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 * 0 1 * * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge TGR1A is Capture input source is TIOCA1 Input capture at falling edge input pin capture Input capture at both edges register Setting prohibited *: Don’t care TIOR2 Bit 3: Bit 2: Bit 1: Bit 0: IOA3 IOA2 IOA1 IOA0 Description 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 * 0 1 0 1 * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR2A is Capture input Input capture at rising edge input source is TIOCA2 Input capture at falling edge pin capture Input capture at both edges register *: Don’t care TGR2A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match TGR1A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match
Channel 1
Channel 2
Rev. 2.00, 03/05, page 677 of 884
16.2.4
Timer Interrupt Enable Register (TIER)
Channel 0: TIER0 Bit: Initial value: R/W: Channel 1: TIER1 Channel 2: TIER2 Bit: Initial value: R/W: 7 — 0 R 6 — 1 R 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 R 2 — 0 R 1 TGIEB 0 R/W 0 TGIEA 0 R/W 7 — 0 R 6 — 1 R 5 — 0 R 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. The TIER registers are initialized to H'40 by a reset. Bit 7—Reserved: This bit is always read as 0. The write value should always be 0. Bit 6—Reserved: This bit is always read as 1. The write value should always be 1. Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5: TCIEU 0 1 Description Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled (Initial value)
Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1.
Bit 4: TCIEV 0 1 Description Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled (Initial value)
Rev. 2.00, 03/05, page 678 of 884
Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channel 0. In channels 1, and 2, bit 3 is reserved. It is always read as 0 and cannot be modified.
Bit 3: TGIED 0 1 Description Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled (Initial value)
Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified.
Bit 2: TGIEC 0 1 Description Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled (Initial value)
Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1.
Bit 1: TGIEB 0 1 Description Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled (Initial value)
Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1.
Bit 0: TGIEA 0 1 Description Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled (Initial value)
Rev. 2.00, 03/05, page 679 of 884
16.2.5
Timer Status Register (TSR)
Channel 0: TSR0 Bit: Initial value: R/W: Note: * 7 — 1 R 6 — 1 R 5 — 0 R 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
Only 0 can be written, to clear the flags.
Channel 1: TSR1 Channel 2: TSR2 Bit: Initial value: R/W: Note: * 7 TCFD 1 R 6 — 1 R 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 R 2 — 0 R 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
Only 0 can be written, to clear the flags.
The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has three TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset. Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, and 2. In channel 0, bit 7 is reserved. It is always read as 1 and cannot be modified.
Bit 7: TCFD 0 1 Description TCNT counts down TCNT counts up (Initial value)
Bit 6—Reserved: This bit is always read as 1. The write value should always be 1.
Rev. 2.00, 03/05, page 680 of 884
Bit 5—Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5: TCFU 0 1 Description [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) (Initial value)
Bit 4—Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred.
Bit 4: TCFV 0 1 Description [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) (Initial value)
Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified.
Bit 3: TGFD 0 Description [Clearing conditions] • • 1 • • (Initial value)
W hen DMAC is activated by TGID interrupt while DRCR setting in DMAC is TGI0D W hen 0 is written to TGFD after reading TGFD = 1 W hen TCNT = TGRD while TGRD is functioning as output compare register W hen TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register
[Setting conditions]
Rev. 2.00, 03/05, page 681 of 884
Bit 2—Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the occurrence of TGRC input capture or compare match in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified.
Bit 2: TGFC 0 Description [Clearing conditions] • • 1 • • (Initial value)
W hen DMAC is activated by TGIC interrupt while DRCR setting in DMAC is TGI0C W hen 0 is written to TGFC after reading TGFC = 1 W hen TCNT = TGRC while TGRC is functioning as output compare register W hen TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register
[Setting conditions]
Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match.
Bit 1: TGFB 0 Description [Clearing conditions] • • 1 • • (Initial value)
W hen DMAC is activated by TGIB interrupt while DRCR setting in DMAC is TGI0B W hen 0 is written to TGFB after reading TGFB = 1 W hen TCNT = TGRB while TGRB is functioning as output compare register W hen TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
[Setting conditions]
Rev. 2.00, 03/05, page 682 of 884
Bit 0—Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the occurrence of TGRA input capture or compare match.
Bit 0: TGFA 0 Description [Clearing conditions] • • 1 • • (Initial value)
W hen DMAC is activated by TGIA interrupt while DRCR setting in DMAC is TGI0A W hen 0 is written to TGFA after reading TGFA = 1 W hen TCNT = TGRA while TGRA is functioning as output compare register W hen TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
[Setting conditions]
16.2.6
Timer Counter (TCNT)
Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Bit: Initial value: R/W: Bit: Initial value: R/W: Note: * 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W
These counters can be used as up/down-counters only in phase counting mode. In other cases they function as up-counters.
The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
Rev. 2.00, 03/05, page 683 of 884
16.2.7
Timer General Register (TGR)
Bit: Initial value: R/W: Bit: Initial value: R/W: 15 1 R/W 7 1 R/W 14 1 R/W 6 1 R/W 13 1 R/W 5 1 R/W 12 1 R/W 4 1 R/W 11 1 R/W 3 1 R/W 10 1 R/W 2 1 R/W 9 1 R/W 1 1 R/W 8 1 R/W 0 1 R/W
The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 8 TGR registers, four for channel 0 and two each for channels 1, and 2. TGRC and TGRD for channel 0 can also be designated for operation as buffer registers*. The TGR registers are initialized to H'FFFF by a reset. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Note: * TGR buffer register combinations are TGRA–TGRC and TGRB–TGRD. 16.2.8 Timer Start Register (TSTR)
Bit: Initial value: R/W: 7 — 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 2. TSTR is initialized to H'00 by a reset. TCNT counter operation should be stopped when setting the operating mode in TMDR or the TCNT count clock in TCR. Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 684 of 884
Bits 2 to 0—Counter Start 2 to 0 (CST2 to CST0): These bits select operation or stoppage for TCNT.
Bit n: CSTn 0 1 Description TCNTn count operation is stopped TCNTn performs count operation (Initial value)
Notes: n = 2 to 0 1. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops, but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value.
16.2.9
Timer Synchro Register (TSYR)
Bit: Initial value: R/W: 7 — 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. TSYR is initialized to H'00 by a reset. Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0. Bits 2 to 0—Timer Synchro 2 to 0 (SYNC2 to SYNC0): These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels*1, and synchronous clearing through counter clearing on another channel*2 are possible.
Bit n: SYNCn 0 1 Description TCNTn operates independently TCNT presetting/clearing is unrelated to other channels TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible Notes: n = 2 to 0 1. To set synchronous operation, the SYNC bits for two channels at least must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. Rev. 2.00, 03/05, page 685 of 884 (Initial value)
16.3
16.3.1
Interface to Bus Master
16-Bit Registers
TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 16.2.
Internal data bus H Bus master Module data bus
L
Bus interface
TCNTH
TCNTL
Figure 16.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] 16.3.2 8-Bit Registers
Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. Examples of 8-bit register access operation are shown in figures 16.3, 16.4, and 16.5.
Internal data bus H Bus master Module data bus
L
Bus interface
TCR
Figure 16.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
Rev. 2.00, 03/05, page 686 of 884
Internal data bus H Bus master Module data bus
L
Bus interface
TMDR
Figure 16.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
Internal data bus H Bus master Module data bus
L
Bus interface
TCR
TMDR
Figure 16.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]
Rev. 2.00, 03/05, page 687 of 884
16.4
16.4.1
Operation
Overview
Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: The TCNT counter for a channel designated for synchronous operation by means of TSYR performs synchronous presetting. That is, when TCNT for a channel designated for synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at the same time. Synchronous clearing of the TCNT counters is also possible by setting the counter clear bits in TCR for channels designated for synchronous operation. Buffer Operation • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR. • When TGR is an input capture register When input capture occurs, the value in TCNT is transfer to TGR and the value previously held in TGR is transferred to the buffer register. PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the setting of each TGR register. Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, and 2. When phase counting mode is set, the corresponding TCLK pin functions as the clock input, and TCNT performs up- or down-counting. This can be used for two-phase encoder pulse input.
Rev. 2.00, 03/05, page 688 of 884
16.4.2
Basic Functions
Counter Operation: When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. • Example of count operation setting procedure Figure 16.6 shows an example of the count operation setting procedure.
1 Operation selection Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. Designate the TGR selected in [2] as an output compare register by means of TIOR. Set the periodic counter cycle in the TGR selected in (2). Set the CST bit in TSTR to 1 to start the count operation.
Select counter clock
1
Periodic counter
Free-running counter
2
Select counter clearing source
2
Select output compare register
3
3
Set period
4 4
Start count operation
5
Start count operation
5 5
Figure 16.6 Example of Counter Operation Setting Procedure
Rev. 2.00, 03/05, page 689 of 884
• Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 16.7 illustrates free-running counter operation.
TCNT value H'FFFF
H'0000
Time
CST bit
TCFV
Figure 16.7 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000.
Rev. 2.00, 03/05, page 690 of 884
Figure 16.8 illustrates periodic counter operation.
TCNT value TGR Counter cleared by TGR compare match
H'0000
Time
CST bit Flag cleared by software or DMAC activation TGF
Figure 16.8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. • Example of setting procedure for waveform output by compare match Figure 16.9 shows an example of the setting procedure for waveform output by compare match
1 Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. 1 2 Set the timing for compare match generation in TGR. 2 3 Set the CST bit in TSTR to 1 to start the count operation.
Output selection
Select waveform output mode
Set output timing
Start count operation
3
Figure 16.9 Example of Setting Procedure for Waveform Output by Compare Match
Rev. 2.00, 03/05, page 691 of 884
• Examples of waveform output operation Figure 16.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time
Figure 16.10 Example of 0 Output/1 Output Operation Figure 16.11 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B.
TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output
TIOCB TIOCA
Figure 16.11 Example of Toggle Output Operation
Rev. 2.00, 03/05, page 692 of 884
Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. • Example of input capture operation setting procedure Figure 16.12 shows an example of the input capture operation setting procedure.
1 Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. 1 2 Set the CST bit in TSTR to 1 to start the count operation.
Input selection
Select input capture input
Start count
2
Figure 16.12 Example of Input Capture Operation Setting Procedure
Rev. 2.00, 03/05, page 693 of 884
• Example of input capture operation Figure 16.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB input (falling edge)
TCNT value H'0180 H'0160
H'0010 H'0005 H'0000 Time
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB TGRB H'0180
Figure 16.13 Example of Input Capture Operation
Rev. 2.00, 03/05, page 694 of 884
16.4.3
Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 2 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 16.14 shows an example of the synchronous operation setting procedure.
Synchronous operation selection Set synchronous operation
1
Synchronous presetting
Synchronous clearing
Set TCNT
2
Clearing source generation channel? Yes Select counter clearing source Start count
No
3 5
Set synchronous counter clearing Start count
4 5
1 2 3 4 5
Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 16.14 Example of Synchronous Operation Setting Procedure
Rev. 2.00, 03/05, page 695 of 884
Example of Synchronous Operation: Figure 16.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle. For details of PWM modes, see section 16.4.5, PWM Modes.
Synchronous clearing by TGR0B compare match TCNT0 to TCNT2 values TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A H'0000 Time
TIOC0A TIOC1A TIOC2A
Figure 16.15 Example of Synchronous Operation
Rev. 2.00, 03/05, page 696 of 884
16.4.4
Buffer Operation
Buffer operation, provided for channel 0 enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 16.5 shows the register combinations used in buffer operation. Table 16.5 Register Combinations in Buffer Operation
Channel 0 Timer General Register TGR0A TGR0B Buffer Register TGR0C TGR0D
• When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 16.16.
Compare match signal
Buffer register
Timer general register
Comparator
TCNT
Figure 16.16 Compare Match Buffer Operation
Rev. 2.00, 03/05, page 697 of 884
• When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 16.17.
Input capture signal Timer general register
Buffer register
TCNT
Figure 16.17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 16.18 shows an example of the buffer operation setting procedure.
Buffer operation
1 Designate TGR as an input capture register or output compare register by means of TIOR. 1 2 Designate TGR for buffer operation with bits BFA and BFB in TMDR. 3 Set the CST bit in TSTR to 1 to start the count operation.
Select TGR function
Set buffer operation
2
Start count
3
Figure 16.18 Example of Buffer Operation Setting Procedure
Rev. 2.00, 03/05, page 698 of 884
Examples of Buffer Operation • When TGR is an output compare register Figure 16.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details of PWM modes, see section 16.4.5, PWM Modes.
TCNT value TGR0B H'0200 TGR0A H'0000 TGR0C H'0200 Transfer TGR0A H'0200 H'0450 H'0450 H'0520 Time H'0520
H'0450
TIOCA
Figure 16.19 Example of Buffer Operation (1)
Rev. 2.00, 03/05, page 699 of 884
• When TGR is an input capture register Figure 16.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value H'0F07 H'09FB H'0532 H'0000 Time
TIOCA
TGRA
H'0532
H'0F07
H'09FB
TGRC
H'0532
H'0F07
Figure 16.20 Example of Buffer Operation (2)
Rev. 2.00, 03/05, page 700 of 884
16.4.5
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. • PWM mode 1 PWM output is generated by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is performed in response to compare match A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR in response to compare match B and D, from pins TIOCA and TIOCC. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 4-phase PWM output is possible. • PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified by TIOR is performed in response to a compare match. Also, when the counter is cleared by a synchronization register compare match, pin output values are the initial values set in TIOR. If the set values of the period and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 7-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 16.6.
Rev. 2.00, 03/05, page 701 of 884
Table 16.6 PWM Output Registers and Output Pins
Output Pins Channel 0 Registers TGR0A TGR0B TGR0C TGR0D 1 2 TGR1A TGR1B TGR2A TGR2B TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
Example of PWM Mode Setting Procedure: Figure 16.21 shows an example of the PWM mode setting procedure.
1 Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. 2 Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. 3 Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. 4 Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. 5 Select the PWM mode with bits MD3 to MD0 in TMDR.
Set PWM mode
PWM mode
Select counter clock
1
Select counter clearing source
2
Select waveform output level
3
Set TGR
4
5
6 Set the CST bit in TSTR to 1 to start the count operation.
Start count
6
Figure 16.21 Example of PWM Mode Setting Procedure
Rev. 2.00, 03/05, page 702 of 884
Examples of PWM Mode Operation: Figure 16.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 output is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty.
TCNT value TGRA
Counter cleared by TGRA compare match
TGRB H'0000 Time
TIOCA
Figure 16.22 Example of PWM Mode Operation (1) Figure 16.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers, to output a 5-phase PWM waveform. In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as the duty.
Rev. 2.00, 03/05, page 703 of 884
TCNT value TGR1B TGR1A TGR0D TGR0C TGR0B TGR0A H'0000
Counter cleared by TGR1B compare match
TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1
Figure 16.23 Example of PWM Mode Operation (2)
Rev. 2.00, 03/05, page 704 of 884
Figure 16.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
TCNT value TGRA
TGRB rewritten
TGRB H'0000 0% duty
TGRB rewritten
TGRB rewritten Time
TIOCA
Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time
TIOCA
Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty 0% duty
TGRB rewritten Time
TIOCA
Figure 16.24 Example of PWM Mode Operation (3)
Rev. 2.00, 03/05, page 705 of 884
16.4.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 16.7 shows the correspondence between external clock pins and channels. Table 16.7 Phase Counting Mode Clock Input Pins
External Clock Pins Channels When channel 1 is set to phase counting mode When channel 2 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD
Example of Phase Counting Mode Setting Procedure: Figure 16.25 shows an example of the phase counting mode setting procedure.
1 Select phase counting mode with bits MD3 to MD0 in TMDR. 2 Set the CST bit in TSTR to 1 to start the count operation.
Phase counting mode
Select phase counting mode
1
Start count
2
Figure 16.25 Example of Phase Counting Mode Setting Procedure
Rev. 2.00, 03/05, page 706 of 884
Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. • Phase counting mode 1 Figure 16.26 shows an example of phase counting mode 1 operation, and table 16.8 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count
Time
Figure 16.26 Example of Phase Counting Mode 1 Operation Table 16.8 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Notes: : Rising edge : Falling edge Down-count TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count
Rev. 2.00, 03/05, page 707 of 884
• Phase counting mode 2 Figure 16.27 shows an example of phase counting mode 2 operation, and table 16.9 summarizes the TCNT up/down-count conditions.
TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) TCNT value Up-count Down-count
Time
Figure 16.27 Example of Phase Counting Mode 2 Operation Table 16.9 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Notes: : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don’t care Don’t care Don’t care Up-count Don’t care Don’t care Don’t care Down-count
Rev. 2.00, 03/05, page 708 of 884
• Phase counting mode 3 Figure 16.28 shows an example of phase counting mode 3 operation, and table 16.10 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value
Up-count
Down-count
Time
Figure 16.28 Example of Phase Counting Mode 3 Operation Table 16.10 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Notes: : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don’t care Don’t care Don’t care Up-count Down-count Don’t care Don’t care Don’t care
Rev. 2.00, 03/05, page 709 of 884
• Phase counting mode 4 Figure 16.29 shows an example of phase counting mode 4 operation, and table 16.11 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count
Up-count
Time
Figure 16.29 Example of Phase Counting Mode 4 Operation Table 16.11 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Notes: : Rising edge : Falling edge Don’t care Down-count Don’t care TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count
Rev. 2.00, 03/05, page 710 of 884
16.5
16.5.1
Interrupts
Interrupt Sources and Priorities
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller (INTC). Table 16.12 lists the TPU interrupt sources. Table 16.12 TPU Interrupts
Channel 0 Interrupt Source TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U Description TGR0A input capture/compare match TGR0B input capture/compare match TGR0C input capture/compare match TGR0D input capture/compare match TCNT0 overflow TGR1A input capture/compare match TGR1B input capture/compare match TCNT1 overflow TCNT1 underflow TGR2A input capture/compare match TGR2B input capture/compare match TCNT2 overflow TCNT2 underflow DMAC Activation Possible Possible Possible Possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible Low Priority High
Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.
Rev. 2.00, 03/05, page 711 of 884
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 8 input capture/compare match interrupts, four for channel 0, and two each for channels 1, and 2. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a particular channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has three overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has two underflow interrupts, one each for channels 1 and 2. 16.5.2 DMAC Activation
The DMAC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 11, Direct Memory Access Controller (DMAC). A total of four TPU input capture/compare match interrupts can be used as DMAC activation sources for channel 0.
Rev. 2.00, 03/05, page 712 of 884
16.6
16.6.1
Operation Timing
Input/Output Timing
TCNT Count Timing: Figure 16.30 shows TCNT count timing in internal clock operation, and figure 16.31 shows TCNT count timing in external clock operation.
Pφ
Internal clock
Falling edge
Rising edge
TCNT input clock TCNT N–1 N N+1 N+2
Figure 16.30 Count Timing in Internal Clock Operation
Pφ
External clock
Falling edge
Rising edge
Falling edge
TCNT input clock TCNT N–1 N N+1 N+2
Figure 16.31 Count Timing in External Clock Operation
Rev. 2.00, 03/05, page 713 of 884
Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 16.32 shows output compare output timing.
Pφ
TCNT input clock TCNT N N+1
TGR
N
Compare match signal TIOC pin
Figure 16.32 Output Compare Output Timing Input Capture Signal Timing: Figure 16.33 shows input capture signal timing.
Pφ Input capture input Input capture signal
TCNT
N
N+1
N+2
TGR
N
N+2
Figure 16.33 Input Capture Input Signal Timing
Rev. 2.00, 03/05, page 714 of 884
Timing for Counter Clearing by Compare Match/Input Capture: Figure 16.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 16.35 shows the timing when counter clearing by input capture occurrence is specified.
Pφ
Compare match signal Counter clear signal N H'0000
TCNT
TGR
N
Figure 16.34 Counter Clear Timing (Compare Match)
Pφ Input capture signal
Counter clear signal N H'0000
TCNT
TGR
N
Figure 16.35 Counter Clear Timing (Input Capture)
Rev. 2.00, 03/05, page 715 of 884
Buffer Operation Timing: Figures 16.36 and 16.37 show the timing in buffer operation.
Pφ
TCNT
n
n+1
Compare match signal TGRA, TGRB TGRC, TGRD
n
N
N
Figure 16.36 Buffer Operation Timing (Compare Match)
Pφ Input capture signal
TCNT TGRA, TGRB TGRC, TGRD
N
N+1
n
N
N+1
n
N
Figure 16.37 Buffer Operation Timing (Input Capture)
Rev. 2.00, 03/05, page 716 of 884
16.6.2
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 16.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing.
Pφ
TCNT input clock
TCNT
N
N+1
TGR
N
Compare match signal
TGF flag
TGI interrupt
Figure 16.38 TGI Interrupt Timing (Compare Match)
Rev. 2.00, 03/05, page 717 of 884
TGF Flag Setting Timing in Case of Input Capture: Figure 16.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing.
Pφ Input capture signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 16.39 TGI Interrupt Timing (Input Capture) TCFV Flag/TCFU Flag Setting Timing: Figure 16.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 16.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
Pφ
TCNT input clock TCNT (overflow) Overflow signal TCFV flag
H'FFFF
H'0000
TCIV interrupt
Figure 16.40 TCIV Interrupt Setting Timing
Rev. 2.00, 03/05, page 718 of 884
Pφ
TCNT input clock TCNT (underflow) Underflow signal
H'0000
H'FFFF
TCFU flag
TCIU interrupt
Figure 16.41 TCIU Interrupt Setting Timing Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is activated, the flag is cleared automatically. Figure 16.42 shows the timing for status flag clearing by the CPU, and figure 16.43 shows the timing for status flag clearing by the DMAC.
TSR write cycle T1 T2 Pφ
Address
TSR address
Write signal
Status flag
Interrupt request signal
Figure 16.42 Timing for Status Flag Clearing by CPU
Rev. 2.00, 03/05, page 719 of 884
DMAC read cycle T1 Pφ T2
DMAC write cycle T1 T2
Address
Source address
Destination address
Status flag
Interrupt request signal
Figure 16.43 Timing for Status Flag Clearing by DMAC Activation
16.7
Usage Notes
Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 16.44 shows the input clock conditions in phase counting mode.
Phase Phase differdifference Overlap ence
Overlap TCLKA (TCLKC) TCLKB (TCLKD)
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more
Figure 16.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Rev. 2.00, 03/05, page 720 of 884
Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula:
f= Pφ (N + 1)
Where
f : Counter frequency Pφ : Peripheral module clock N : TGR set value
Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 16.45 shows the timing in this case.
TCNT write cycle T2 T1 Pφ
Address
TCNT address
Write signal Counter clear signal
TCNT
N
H'0000
Figure 16.45 Contention between TCNT Write and Clear Operations
Rev. 2.00, 03/05, page 721 of 884
Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 16.46 shows the timing in this case.
TCNT write cycle T2 T1 Pφ
Address
TCNT address
Write signal TCNT input clock N TCNT write data M
TCNT
Figure 16.46 Contention between TCNT Write and Increment Operations
Rev. 2.00, 03/05, page 722 of 884
Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 16.47 shows the timing in this case.
TGR write cycle T2 T1 Pφ Address TGR address
Write signal Compare match signal TCNT N N+1
Inhibited
TGR
N TGR write data
M
Figure 16.47 Contention between TGR Write and Compare Match
Rev. 2.00, 03/05, page 723 of 884
Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the write data. Figure 16.48 shows the timing in this case.
TGR write cycle T2 T1 Pφ Address Buffer register address
Write signal Compare match signal Buffer register write data Buffer register TGR N M
M
Figure 16.48 Contention between Buffer Register Write and Compare Match
Rev. 2.00, 03/05, page 724 of 884
Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data before input capture transfer. Figure 16.49 shows the timing in this case.
TGR read cycle T2 T1 Pφ Address TGR address
Read signal Input capture signal TGR Internal data bus N M
N
Figure 16.49 Contention between TGR Read and Input Capture
Rev. 2.00, 03/05, page 725 of 884
Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 16.50 shows the timing in this case.
TGR write cycle T2 T1 Pφ Address TGR address
Write signal Input capture signal TCNT M
TGR
M
Figure 16.50 Contention between TGR Write and Input Capture
Rev. 2.00, 03/05, page 726 of 884
Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 16.51 shows the timing in this case.
Buffer register write cycle T1 T2 Pφ Address Buffer register address
Write signal Input capture signal TCNT N
TGR Buffer register
M
N
M
Figure 16.51 Contention between Buffer Register Write and Input Capture
Rev. 2.00, 03/05, page 727 of 884
Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 16.52 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
Pφ TCNT input clock TCNT Counter clear signal TGF Disabled TCFV H'FFFF H'0000
Figure 16.52 Contention between Overflow and Counter Clearing
Rev. 2.00, 03/05, page 728 of 884
Contention between TCNT Write and Overflow/Underflow: If there is an up-count or downcount in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set . Figure 16.53 shows the operation timing in the case of contention between a TCNT write and overflow.
TCNT write cycle T1 T2 Pφ
Address
TCNT address
Write signal
TCNT write data H'FFFF Disabled M
TCNT
TCFV flag
Figure 16.53 Contention between TCNT Write and Overflow Multiplexing of I/O Pins: In the Chip, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or DMAC activation source. Interrupts should therefore be disabled before entering module stop mode.
Rev. 2.00, 03/05, page 729 of 884
16.8
16.8.1
Usage Notes
Clearing Flags in TSR0 to TSR2
When bits TCFV, TGFD, TGFC, TGFB, and TGFA in TSR0, and bits TCFU, TCFV, TGFB, and TGFA in TSR1 and TSR2, are cleared, it may happen that the interrupt request in the internal logic cannot be cleared although the flag is cleared. In this case, if interrupt acceptance is enabled, another interrupt will be generated. Either of the following measures should therefore be taken when clearing flags in TSR0 to TSR2. 1. Execute clearing while the TPU timer is counting up. 2. If clearing when the TPU timer is stopped, write 0 to the flag again after executing clearing. 16.8.2 DMA Transfer by TPU0
When DMA transfer is performed by means of TPU channel 0 compare match or input capture, internal logic interrupt requests (transfer requests) may not be cleared correctly. Therefore, it may not be possible to execute DMA transfer when a subsequent transfer request is generated by TPU channel 0 compare match or input capture. Either of the following measures should therefore be taken when performing DMA transfer by means of TPU channel 0 compare match or input capture. 1. Do not set on-chip RAM as the DMA transfer source or destination. 2. When on-chip RAM has not been set as the DMA transfer source or destination, execute the transfer while the TPU channel 0 timer is counting up.
Rev. 2.00, 03/05, page 730 of 884
Section 17 High-Performance User Debugging Interface (H-UDI)
17.1 Overview
The high-performance user debugging interface (H-UDI) provides data transfer and interrupt request functions. The H-UDI performs serial transfer by means of external signal control. 17.1.1 Features
The H-UDI has the following features conforming to the IEEE 1149.1 standard.
The H-UDI has seven instructions. • Bypass mode Test mode conforming to IEEE 1149.1 • EXTEST mode Test mode corresponding to IEEE1149.1. • SAMPLE/PRELOAD mode Test mode corresponding to IEEE1149.1. • CLAMP mode Test mode corresponding to IEEE1149.1. • HIGHZ mode Test mode corresponding to IEEE1149.1. • IDCODE mode Test mode corresponding to IEEE1149.1. • H-UDI interrupt H-UDI interrupt request to INTC This chip does not support test modes other than bypass mode.
Rev. 2.00, 03/05, page 731 of 884
TSRT
• • • • • •
Five test signals (TCK, TDI, TDO, TMS, and TAP controller Instruction register Data register Bypass register Boundary scan register
)
17.1.2
H-UDI Block Diagram
Figure 17.1 shows a block diagram of the H-UDI.
TCK
TMS
TAP controller
Internal bus controller
H-UDI interrupt signal
TRST
TDI
Decoder
SDIR
Peripheral bus
Shift register
SDSR
SDBPR
SDBSR
SDDRH
16 SDDRL
SDIDR
TDO Mux
SDIR: SDSR: SDDRH: SDDRL: SDBPR: SDBSR:
Instruction register Status register Data register H Data register L Bypass register Boundary scan register
TCK: TMS: TRST: TDI: TDO: SDIDR:
Test clock Test mode select Test reset Test data input Test data output ID code register
Figure 17.1 H-UDI Block Diagram
Rev. 2.00, 03/05, page 732 of 884
17.1.3
Input/Output Pins
Table 17.1 shows the H-UDI pin configuration. Table 17.1 Pin Configuration
Pin Name Test clock Test mode select Test data input Test data output Test reset Abbreviation TCK TMS TDI TDO I/O Input Input Input Output Input Function Test clock input Test mode select input signal Serial data input Serial data output Test reset input signal
17.1.4
Register Configuration
Table 17.2 shows the H-UDI registers. Table 17.2 Register Configuration
Register Instruction register Status register Data register H Data register L Bypass register Boundary scan register ID code register Abbreviation SDIR SDSR SDDRH SDDRL SDBPR SDBSR SDIDR R/W*1 R R/W R/W R/W — — — Initial Value*2 H'E000 H'0401 Undefined Undefined — — H'0101000F Address H'FFFFFCB0 H'FFFFFCB2 H'FFFFFCB4 H'FFFFFCB6 — — — Access Size (Bits) 8/16/32 8/16 8/16/32 8/16 — — —
Notes: 1. Indicates whether the register can be read/written to by the CPU. 2. Initial value when the signal is input. Registers are not initialized by a reset (power-on or manual) or in standby mode.
Instructions and data can be input to the instruction register (SDIR) and data register (SDDR) by serial transfer from the test data input pin (TDI). Data from SDIR, the status register (SDSR), and SDDR can be output via the test data output pin (TDO). The bypass register (SDBPR) is a 1-bit register to which TDI and TDO are connected in bypass mode. The boundary scan register (SDBSR) is a 330-bit register, and is connected to TDI and TDO in the SAMPLE/PRELOAD or EXTEST mode. The ID code register (SDIDR) is a 32-bit register; a fixed code can be output via TDO in the IDCODE mode. All registers, except SDBPR, SDBSR, and SDIDR, can be accessed from the CPU.
Rev. 2.00, 03/05, page 733 of 884
TSRT
TSRT
Table 17.3 shows the kinds of serial transfer possible with each register. Table 17.3 H-UDI Register Serial Transfer
Register SDIR SDSR SDDRH SDDRL SDBPR SDBSR SDIDR Serial Input Possible Impossible Possible Possible Possible Possible Impossible Serial Output Possible Possible Possible Possible Possible Possible Possible
17.2
17.2.1
External Signals
Test Clock (TCK)
The test clock pin (TCK) provides an independent clock supply to the H-UDI. As the clock input to TCK is supplied directly to the H-UDI, a clock waveform with a duty cycle close to 50% should be input (for details, see section 21, Electrical Characteristics). If no clock is input, TCK is fixed at 1 by internal pull-up. 17.2.2 Test Mode Select (TMS)
The test mode select pin (TMS) is sampled on the rise of TCK. TMS controls the internal state of the TAP controller. If no signal is input, TMS is fixed at 1 by internal pull-up. 17.2.3 Test Data Input (TDI)
The test data input pin (TDI) performs serial input of instructions and data for H-UDI registers. TDI is sampled on the rise of TCK. If no signal is input, TDI is fixed at 1 by internal pull-up. 17.2.4 Test Data Output (TDO)
The test data output pin (TDO) performs serial output of instructions and data from H-UDI registers. Transfer is performed in synchronization with TCK. If there is no output, TDO goes to the high-impedance state.
Rev. 2.00, 03/05, page 734 of 884
17.3
17.3.1
Register Descriptions
Instruction Register (SDIR)
Bit: Initial value: R/W: Bit: Initial value: R/W: 15 TS3 1 R 7 — 0 R 14 TS2 1 R 6 — 0 R 13 TS1 1 R 5 — 0 R 12 TS0 0 R 4 — 0 R 11 — 0 R 3 — 0 R 10 — 0 R 2 — 0 R 9 — 0 R 1 — 0 R 8 — 0 R 0 — 0 R
The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. H-UDI instructions can be transferred to SDIR by serial input from TDI. SDIR can be initialized by the signal, but is not initialized by a reset or in standby mode. SDIR defines 4 valid bits for instruction. If an instruction exceeding 4 bits is input, the last 4 bits of the serial data will be stored in SDIR. Operation is not guaranteed if a reserved instruction is set in this register. Bits 15 to 12—Test Set Bits (TS3 to TS0): Table 17.4 shows the instruction configuration.
Rev. 2.00, 03/05, page 735 of 884
TSRT
The test reset pin ( ) initializes the H-UDI asynchronously. If no signal is input, fixed at 1 by internal pull-up.
TSRT
17.2.5
Test Reset (
) is
TSRT
TSRT
Table 17.4 Instruction Configuration
Bit 15: TS3 0 Bit 14: TS2 0 Bit 13: TS1 0 1 1 0 1 1 0 0 1 1 0 1 Bit 12: TS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description EXTEST mode Reserved CLAMP mode HIGHZ mode SAMPLE/PRELOAD mode Reserved Reserved Reserved Reserved Reserved H-UDI interrupt Reserved Reserved Reserved IDCODE mode BYPASS mode (Initial value)
Bits 11 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 736 of 884
17.3.2
Status Register (SDSR)
Bit: Initial value: R/W: Bit: Initial value: R/W: 15 — 0 R 7 — 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 — 0 R 12 — 0 R 4 — 0 R 11 — 0 R 3 — 0 R 10 — 1 R 2 — 0 R 9 — 0 R 1 — 0 R 8 — 0 R 0 SDTRF 1 R/W
The status register (SDSR) is a 16-bit register that can be read and written to by the CPU. Output from TDO is possible for SDSR, but serial data cannot be written to SDSR via TDI. The SDTRF bit is output by means of a 1-bit shift. In the case of a 2-bit shift, the SDTRF bit is first output, followed by a reserved bit.
Bits 15 to 1—Reserved: Bits 15 to 11 and 9 to 1 are always read as 0, and the write value should always be 0. Bit 10 is always read as 1, and the write value should always be 1. Bit 0—Serial Data Transfer Control Flag (SDTRF): Indicates whether H-UDI registers can be signal , but is not initialized by a reset accessed by the CPU. The SDTRF bit is reset by the or in standby mode.
Bit 0: SDTRF 0 1 Description Serial transfer to SDDR has ended, and SDDR can be accessed Serial transfer to SDDR in progress (Initial value)
TSRT
TSRT
SDSR is initialized by
signal input, but is not initialized by a reset or in standby mode.
Rev. 2.00, 03/05, page 737 of 884
17.3.3
Data Register (SDDR)
The data register (SDDR) comprises data register H (SDDRH) and data register L (SDDRL), each of which has the following configuration.
Bit: Initial value: R/W: Bit: Initial value: R/W: 15 — R/W 7 — R/W 14 — R/W 6 — R/W 13 — R/W 5 — R/W 12 — R/W 4 — R/W 11 — R/W 3 — R/W 10 — R/W 2 — R/W 9 — R/W 1 — R/W 8 — R/W 0 — R/W
SDDRH and SDDRL are 16-bit registers that can be read and written to by the CPU. SDDR is connected to TDO and TDI for serial data transfer to and from an external device. 32-bit data is input and output in serial data transfer. If data exceeding 32 bits is input, only the last 32 bits will be stored in SDDR. Serial data is input starting from the MSB of SDDR (bit 15 of SDDRH), and output starting from the LSB (bit 0 of SDDRL).
17.3.4
Bypass Register (SDBPR)
The bypass register (SDBPR) is a one-bit shift register. In bypass mode, CLAMP mode, and HIGHZ mode, SDBPR is connected to TDI and TDO, and the chip is excluded from the board test when a boundary scan test is conducted. SDBPR cannot be read or written to by the CPU. 17.3.5 Boundary Scan Register (SDBSR)
The boundary scan register (SDBSR), a shift register that controls the I/O terminals of this LSI, is provided on the PAD. Using the EXTEST mode or the SAMPLE/PRELOAD mode, a boundary scan test conforming to the IEEE1149.1 standard can be performed. For SDBSR, read/write by the CPU cannot be performed. Table 17.5 shows the relationship between the terminals of the LSI and the boundary scan register.
Rev. 2.00, 03/05, page 738 of 884
TSRT
This register is not initialized by a reset, in standby mode, or by the
signal.
Table 17.5 Correspondence between Pins and Boundary Scan Register Bits
Pin No. from TDI 34 D0 Input Output Output enable 36 D1 Input Output Output enable 37 D2 Input Output Output enable 38 D3 Input Output Output enable 39 D4 Input Output Output enable 40 D5 Input Output Output enable 41 D6 Input Output Output enable 43 D7 Input Output Output enable 44 D8 Input Output Output enable 46 D9 Input Output Output enable 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 Pin Name Input/Output Bit No.
Rev. 2.00, 03/05, page 739 of 884
Pin No. 47
Pin Name D10
Input/Output Input Output Output enable
Bit No. 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270
48
D11
Input Output Output enable
49
D12
Input Output Output enable
51
D13
Input Output Output enable
53
D14
Input Output Output enable
54
D15
Input Output Output enable
55
D16
Input Output Output enable
56
D17
Input Output Output enable
57
D18
Input Output Output enable
59
D19
Input Output Output enable
Rev. 2.00, 03/05, page 740 of 884
Pin No. 62
Pin Name D20
Input/Output Input Output Output enable
Bit No. 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240
63
D21
Input Output Output enable
64
D22
Input Output Output enable
65
D23
Input Output Output enable
68
D24
Input Output Output enable
70
D25
Input Output Output enable
71
D26
Input Output Output enable
72
D27
Input Output Output enable
73
D28
Input Output Output enable
74
D29
Input Output Output enable
Rev. 2.00, 03/05, page 741 of 884
Pin No. 75
Pin Name D30
Input/Output Input Output Output enable
Bit No. 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210
77
D31
Input Output Output enable
80 82 83 84 85 86 87 88 90 92 93 94
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable
Rev. 2.00, 03/05, page 742 of 884
Pin No. 95 96 97 98 100 102 103 104 105 106 107 108 111 115 117 118
Pin Name A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24
Input/Output Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Input Output Output enable Output Output enable
Bit No. 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179
SAR TIAW SAC
Rev. 2.00, 03/05, page 743 of 884
Pin No. 119 120 121 122 123 124 125 126 127 128 129 131 133 134 135
Pin Name
Input/Output Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable
Bit No. 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149
CKE
REFOUT
Rev. 2.00, 03/05, page 744 of 884
RW
RD/
0EW
DQMLL/
1EW
DQMLU/
2EW
DQMUL/
3EW
DQMUU/
3SAC 2SAC 1SAC 0SAC 0SC 1SC DR SB
Pin No. 136 137 138 139 140 141 142 143 144 145 148 151
Pin Name
Input/Output Output Output enable Output Output enable Output Output enable Input Output Output enable Input Input Output Output enable Output Output enable Input Output Output enable Input Output Output enable
Bit No. 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119
DREQ1 DREQ0 DACK1 DACK0
152
153
154
HB ZIHSUB
RGB SLRB
2SC 3SC 4SC
PB15 PB14 PB13 PB12
Input Output Output enable Input Output Output enable Input Output Output enable
Rev. 2.00, 03/05, page 745 of 884
Pin No. 156
Pin Name PB11
Input/Output Input Output Output enable
Bit No. 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
158
PB10
Input Output Output enable
159
PB9
Input Output Output enable
160
PB8
Input Output Output enable
161
PB7
Input Output Output enable
162
PB6
Input Output Output enable
163
PB5
Input Output Output enable
164
PB4
Input Output Output enable
165
PB3
Input Output Output enable
166
PB2
Input Output Output enable
Rev. 2.00, 03/05, page 746 of 884
Pin No. 168
Pin Name PB1
Input/Output Input Output Output enable
Bit No. 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59
170
PB0
Input Output Output enable
171
PA13
Input Output Output enable
172
PA12
Input Output Output enable
173
PA11
Input Output Output enable
174
PA10
Input Output Output enable
175
PA9
Input Output Output enable
176
PA8
Input Output Output enable
177
PA7
Input Output Output enable
178
PA6
Input Output Output enable
Rev. 2.00, 03/05, page 747 of 884
Pin No. 180
Pin Name PA5
Input/Output Input Output Output enable
Bit No. 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
182
PA4
Input Output Output enable
183 184
CKPO PA2
Output Output enable Input Output Output enable
185
PA1
Input Output Output enable
186
PA0
Input Output Output enable
187 188 189 190 192 194 195 196 197 198
RX–ER RX–DV COL CRS RX–CLK ERXD0 ERXD1 ERXD2 ERXD3 MDIO
Input Input Input Input Input Input Input Input Input Input Output Output enable
199
MDC
Output Output enable
Rev. 2.00, 03/05, page 748 of 884
Pin No. 201 203 204 205 206 207 208 1 2 3 4 5 13 14 15 16 17 24 25 27 to TDO
Pin Name TX–CLK TX–EN ETXD0 ETXD1 ETXD2 ETXD3 TX–ER
Input/Output Input Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Output Output enable Input Input Input Input Input Input Input Input Input Input
Bit No. 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Note: The output enable signals are active-low. When an output enable signal is driven low, the corresponding pin is driven. The exception is the output enable signal for the MDIO pin, which is active-high.
KCAPKC QERPKC
FCEVI
0LRI 1LRI 2LRI 3LRI
NMI MD4 MD3 MD2 MD1 MD0 /CKM
Input Output Output enable Output Output enable
Rev. 2.00, 03/05, page 749 of 884
17.3.6
ID Code Register (SDIDR)
The ID code register (SDIDR) is a 32-bit register. In the IDCODE mode, SDIDR can output H'0101000F, which is a fixed code, from TDO. However, no serial data can be written to SDIDR via TDI. For SDIDR, read/write by the CPU cannot be performed.
31 0000 Version (4 bits) 28 27 0001 0000 0001 12 0000 11 0000 0000 1 111 0 1 Fixed Code (1 bit)
Part Number (16 bits)
Manufacture Identify (11 bits)
Rev. 2.00, 03/05, page 750 of 884
17.4
17.4.1
Operation
TAP Controller
Figure 17.2 shows the internal states of TAP controller. State transitions basically conform with the IEEE1149.1 standard.
1
Test-logic-reset 0 1 Select-DR-scan 0 1 Select-IR-scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 1 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 0 1 1
0
Run-test/idle
0
0
Figure 17.2 TAP Controller State Transitions
Rev. 2.00, 03/05, page 751 of 884
17.4.2
H-UDI Interrupt and Serial Transfer
When an H-UDI interrupt instruction is transferred to SDIR via TDI, an interrupt is generated. Data transfer can be controlled by means of the H-UDI interrupt service routine. Transfer can be performed by means of SDDR. Control of data input/output between an external device and the H-UDI is performed by monitoring the SDTRF bit in SDSR externally and internally. Internal SDTRF bit monitoring is carried out by having SDSR read by the CPU. The H-UDI interrupt and serial transfer procedure is as follows. 1. An instruction is input to SDIR by serial transfer, and an H-UDI interrupt request is generated. 2. After the H-UDI interrupt request is issued, the SDTRF bit in SDSR is monitored externally. After output of SDTRF = 1 from TDO is observed, serial data is transferred to SDDR. 3. On completion of the serial transfer to SDDR, the SDTRF bit is cleared to 0, and SDDR can be accessed by the CPU. After SDDR has been accessed, SDDR serial transfer is enabled by setting the SDTRF bit to 1 in SDSR. 4. Serial data transfer between an external device and the H-UDI can be carried out by constantly monitoring the SDTRF bit in SDSR externally and internally. Figures 17.3, 17.4, and 17.5 show the timing of data transfer between an external device and the H-UDI.
Rev. 2.00, 03/05, page 752 of 884
Serial data
Instruction SDTRF 1
Input 0 1
Input/ output
H-UDI interrupt request Shift disabled SDTRF (in SDSR)*1 SDSR and SDDR MUX*2 SDDR access state Shift enabled SDSR SDDR Shift enabled SDSR SDDR
Shift
CPU
Shift
CPU
SDSR serial transfer (monitoring) Notes: 1. SDTRF flag (in SDSR): Indicates whether SDDR access by the CPU or serial transfer data input/output to SDDR is possible. 1 2 SDDR is shift-disabled. SDDR access by the CPU is enabled. SDDR is shift-enabled. Do not access SDDR until SDTRF = 0. Conditions: • SDTRF = 1 — When TRST = 0 — When the CPU writes 1 — In bypass mode • SDTRF = 0 — End of SDDR shift access in serial transfer 2. SDSR/SDDR (Update-DR state) internal MUX switchover timing • Switchover from SDSR to SDDR: On completion of serial transfer in which SDTRF = 1 is output from TDO • Switchover from SDDR to SDSR: On completion of serial transfer to SDDR
Figure 17.3 Data Input/Output Timing Chart (1)
Rev. 2.00, 03/05, page 753 of 884
TDI
Select-DR Capture-DR Shift-DR Exit1-DR Update-DR Select-DR Capture-DR
TDI
TCK
TCK
TDO
SDTRF
TMS
TDO
TMS
TRST
TRST
Test-Logic-Reset Run-Test/Idle Select-DR Select-IR Capture-IR
Rev. 2.00, 03/05, page 754 of 884
Bit 0 Bit 0
Shift-DR
Bit 31 Bit 31
TS0
Exit1-DR Update-DR Select-DR Capture-DR Shift-DR Exit1-DR Update-DR Select-DR Capture-DR
Shift-IR
TS3
Exit1-IR Update-IR Select-DR Capture-DR
SDTRF
SDTRF
Figure 17.5 Data Input/Output Timing Chart (3)
Bit 0 Bit 0 Bit 31 Bit 31
Figure 17.4 Data Input/Output Timing Chart (2)
Shift-DR Exit1-DR
Shift-DR Exit1-DR Update-DR
Update-DR Run-Test/Idle
Test-Logic-Reset
17.4.3
H-UDI Reset
The H-UDI can be reset in two ways. signal is held at 0. • The H-UDI is reset when the • When = 1, the H-UDI can be reset by inputting at least five TCK clock cycles while TMS = 1.
17.5
Boundary Scan
The H-UDI pins can be placed in the boundary scan mode stipulated by IEEE1149.1 by setting a command in SDIR. 17.5.1 Supported Instructions
The SH7615 supports the three essential instructions defined in IEEE1149.1 (BYPASS, SAMPLE/PRELOAD, and EXTEST) and optional instructions (CLAMP, HIGHZ, and IDCODE). BYPASS: The BYPASS instruction is an essential standard instruction that operates the bypass register. This instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. While this instruction is executing, the test circuit has no effect on the system circuits. The instruction code is 1111. SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction inputs values from the SH7615’s internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. When this instruction is executing, the SH7615’s input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. The SH7615’s system circuits are not affected by execution of this instruction. The instruction code is 0100. In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. Snapshot latching is performed in synchronization with the rise of TCK in the Capture-DR state. Snapshot latching does not affect normal operation of the SH7615. In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation, when the EXTEST instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST instruction, the parallel output latch value is constantly output to the output pin). EXTEST: This instruction is provided to test external circuitry when the SH7615 is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data
Rev. 2.00, 03/05, page 755 of 884
TSRT
TSRT
(previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. If testing is carried out by using the EXTEST instruction N times, the Nth test data is scanned-in when test data (N-1) is scanned out. Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). The instruction code is 0000. CLAMP: When the CLAMP instruction is enabled, the output pin outputs the value of the boundary scan register that has been set by the SAMPLE/PRELOAD instruction. While the CLAMP instruction is enabled, the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller. A bypass register is connected between TDI and TDO. The related circuit operates in the same way when the BYPASS instruction is enabled. The instruction code is 0010. HIGHZ: When the HIGHZ instruction is enabled, all output pins enter a high-impedance state. While the HIGHZ instruction is enabled, the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller. A bypass register is connected between TDI and TDO. The related circuit operates in the same way when the BYPASS instruction is enabled. The instruction code is 0011. IDCODE: When the IDCODE instruction is enabled, the value of the ID code register is output from TDO with LSB first when the TAP controller is in the Shift-DR state. While this instruction is being executed, the test circuit does not affect the system circuit. When the TAP controller is in the Test-Logic-Reset state, the instruction register is initialized to the IDCODE instruction. The instruction code is 1110. 17.5.2 Notes on Use
1. Boundary scan mode does not cover clock-related signals (EXTAL, XTAL, CKIO, CAP1, CAP2). , ASEMODE). 2. Boundary scan mode does not cover reset-related signals ( 3. Boundary scan mode does not cover H-UDI-related signals (TCK, TDI, TDO, TMS, ). 4. Fix the ASEMODE pin high.
Rev. 2.00, 03/05, page 756 of 884
TSRT
SER
17.6
Usage Notes
• A reset must always be executed by driving the signal to 0, regardless of whether or not the H-UDI is to be activated. must be held low for 20 TCK clock cycles. For details, see section 21, Electrical Characteristics. • The registers are not initialized in standby mode. If is set to 0 in standby mode, IDCODE mode will be entered. • The frequency of TCK must be lower than that of the peripheral module clock (Pφ). For details, see section 21, Electrical Characteristics. • In data transfer, data input/output starts with the LSB. Figure 17.6 shows serial data input/output. • When data that exceeds the number of bits of the register connected between TDI and TDO is serially transferred, the serial data that exceeds the number of register bits and output from TDO is the same as that input from TDI. • If the H-UDI serial transfer sequence is disrupted, a reset must be executed. Transfer should then be retried, regardless of the transfer operation. • TDO is output at the falling edge of TCK when one of six instructions defined in IEEE1149.1 is selected. Otherwise, it is output at the rising edge of TCK.
• SDIR and SDSR serial data input/output In Capture-IR, SDIR and SDSR are captured into the shift register, and in Shift-IR bits 0 to 15 of SDSR and bits 0 to 15 of SDIR are output in that order from TDO. In Update-IR, data input from TDI is written to SDIR, but not to SDSR. TDI Shift register SDIR Bit 16 Bit 15 SDSR Bit 0 Bit 31 Bit 15 TDI Shift register SDIR Bit 0 Bit 15 TDI input data SDSR Bit 0 Bit 0 Bit 16 Bit 15 SDSR Bit 31 Bit 15
. . .
. . .
TDO
Capture-IR
TDO
Figure 17.6 Serial Data Input/Output (1)
TSRT
TSRT
TSRT
TSRT
. . .
Bit 0
SDIR
Update-IR
Rev. 2.00, 03/05, page 757 of 884
• SDDRH and SDDRL serial data input/output (1) In H-UDI interrupt mode, before SDTRF = 1 is read from TDO when an H-UDI interrupt is generated, SDSR and SDIR are captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 15 of SDSR and bits 0 to 15 of SDIR are output in that order from TDO. In Update-DR, TDI input data is not written to any register. TDI Shift register SDIR Bit 16 Bit 15 SDSR Bit 0 Bit 31 Bit 15
. . .
Bit 0 Bit 15
SDIR
. . .
Bit 0
SDSR
TDO
Capture-DR
(2) In H-UDI interrupt mode, after SDTRF = 1 is read from TDO when an H-UDI interrupt is generated, SDDRH and SDDRL are captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 15 of SDDRL and bits 0 to 15 of SDDRH are output in that order from TDO. Data input from TDI is written to SDDRH and SDDRL in Update-DR. TDI Shift register SDDRH Bit 16 Bit 15 SDDRL Bit 0 Bit 31 Bit 15 TDI Shift register SDDRH Bit 0 Bit 15 TDI input data SDDRL Bit 0 Bit 0 Bit 16 Bit 15 Bit 31 Bit 15
. . .
. . .
Bit 0 Bit 15
SDDRH
. . .
. . .
Bit 0
SDDRL
TDO
Capture-DR
TDO
Update-DR
Figure 17.6 Serial Data Input/Output (2)
Rev. 2.00, 03/05, page 758 of 884
• SDIDR serial data input/output In IDCODE mode, SDIDR is captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 31 of SDIDR are output in that order from TDO. In Update-DR, data input from TDI is not written to any register. TDI Shift register Bit 31 Bit 15
SDIDR
. . . .
SDIDR
Bit 0
Bit 0
TDO
Capture-DR
Figure 17.6 Serial Data Input/Output (3)
Rev. 2.00, 03/05, page 759 of 884
Rev. 2.00, 03/05, page 760 of 884
Section 18 Pin Function Controller (PFC)
18.1 Overview
The pin function controller (PFC) consists of registers to select multiplexed pin functions and input/output direction. The pin function and input/output direction can be selected for individual pins regardless of the operating mode of the chip. Table 18.1 shows the chip’s multiplex pins.
Rev. 2.00, 03/05, page 761 of 884
Table 18.1 Multiplex Pins
Function 1 [00]*
Signal Port Name A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B PA13 PA12 PA11 PA10 PA9 PA8 I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Function 2 [01]*
I/O I I I I I/O O I/O I I O O I O — — — — I I I I I/O O I I I I I/O O —
Function 3 [10]*
I/O — — — — — — — — — — — — — — I/O I O O I I/O I/O I/O I/O I/O I O I/O I/O I/O I/O
Function 4 [11]*
I/O — — — — — — — — — — — — — — — — — O O — — — — — — — — — — O Related Module — — — — — — — — — — — — — — — — — BSC BSC — — — — — — — — — — EtherC
Related Signal Module Name Port Port Port Port Port Port WDT Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port SRCK0 SRS0 SRXD0 STCK0 STS0 STXD0 PA7 FTCI FTI FTOA FTOB LNKSTA EXOUT — — — — SRCK2 SRS2 SRXD2 STCK2 STS2 STXD2 SRCK1 SRS1 SRXD1 STCK1 STS1 STXD1 —
Related Signal Module Name SIO0 SIO0 SIO0 SIO0 SIO0 SIO0 Port FRT FRT FRT FRT EtherC EtherC — — — — SIO2 SIO2 SIO2 SIO2 SIO2 SIO2 SIO1 SIO1 SIO1 SIO1 SIO1 SIO1 — — — — — — — — — — — — — — — SCK1 RXD1 TXD1
Related Signal Module Name — — — — — — — — — — — — — — SCIF1 SCIF1 SCIF1 SCIF1 SCIF1 TPU1 TPU1 TPU2 TPU2 SCIF2 SCIF2 SCIF2 TPU0 TPU0 TPU0 TPU0 — — — — — — — — — — — — — — — — — STATS1 STATS0 — — — — — — — — — — WOL
PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
TIOCA2 TIOCB2 SCK2 RXD2 TXD2 TIOCA0 TIOCB0 TIOCC0 TIOCD0
Notes: In the initial state, function 1 is selected. * The initial value is "input." The figures in brackets indicate the settings of the mode bits (MD1, MD0) in the PFC to select multiplexed functions in port A[0:13] and port B[0:15].
Rev. 2.00, 03/05, page 762 of 884
STC STR
FVOTDW
PA6 PA5 PA4 CKPO PA2 PA1 PA0 PB15 PB14 PB13 PB12
TIOCA1
TIOCB1
18.2
Register Configuration
Table 18.2 shows the PFC registers. Table 18.2 Register Configuration
Name Port A control register Port A I/O register Port B control register Port B I/O register Port B control register 2 Abbreviation PACR PAIOR PBCR PBIOR PBCR2 R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 Address H'FFFFFC80 H'FFFFFC82 H'FFFFFC88 H'FFFFFC8A H'FFFFFC8E Access Size 8, 16 8, 16 8, 16 8, 16 8, 16
18.3
18.3.1
Register Descriptions
Port A Control Register (PACR)
Bit: Initial value: R/W: Bit: Initial value: R/W: 15 — 0 R 7 0 R/W 14 — 0 R 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W
PA13MD PA12MD PA11MD PA10MD PA9MD PA8MD
PA7MD PA6MD PA5MD PA4MD PA3MD PA2MD PA1MD PA0MD
The port A control register (PACR) is a 16-bit read/write register that selects the functions of the 14 multiplex pins in port A. PACR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in standby mode or sleep mode. Bits 15 and 14—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 763 of 884
Bit 13—PA13 Mode Bit (PA13MD): Selects the function of pin PA13/SRCK0.
Bit 13: PA13MD 0 1 Description General input/output (PA13) SIO0 serial receive clock input (SRCK0) (Initial value)
Bit 12—PA12 Mode Bit (PA12MD): Selects the function of pin PA12/SRS0.
Bit 12: PA12MD 0 1 Description General input/output (PA12) SIO0 serial receive synchronous input (SRS0) (Initial value)
Bit 11—PA11 Mode Bit (PA11MD): Selects the function of pin PA11/SRXD0.
Bit 11: PA11MD 0 1 Description General input/output (PA11) SIO0 serial receive data (SRXD0) (Initial value)
Bit 10—PA10 Mode Bit (PA10MD): Selects the function of pin PA10/STCK0.
Bit 10: PA10MD 0 1 Description General input/output (PA10) SIO0 serial transmit clock (STCK0) (Initial value)
Bit 9—PA9 Mode Bit (PA9MD): Selects the function of pin PA9/STS0.
Bit 9: PA9MD 0 1 Description General input/output (PA9) SIO0 serial transmit synchronous input/output (STS0) (Initial value)
Bit 8—PA8 Mode Bit (PA8MD): Selects the function of pin PA8/STXD0.
Bit 8: PA8MD 0 1 Description General input/output (PA8) SIO0 serial transmit data output (STXD0) (Initial value)
Rev. 2.00, 03/05, page 764 of 884
Bit 7: PA7MD 0 1
Description WDT overflow signal output ( General input/output (PA7)
Bit 6—PA6 Mode Bit (PA6MD): Selects the function of pin PA6/FTCI.
Bit 6: PA6MD 0 1 Description General input/output (PA6) FRT clock input (FTCI) (Initial value)
Bit 5—PA5 Mode Bit (PA5MD): Selects the function of pin PA5/FTI.
Bit 5: PA5MD 0 1 Description General input/output (PA5) FRT input capture input (FTI) (Initial value)
Bit 4—PA4 Mode Bit (PA4MD): Selects the function of pin PA4/FTO4.
Bit 4: PA4MD 0 1 Description General input/output (PA4) FRT output compare output (FTOA) (Initial value)
Bit 3—PA3 Mode Bit (PA3MD): Selects the function of pin CKPO/FTOB.
Bit 3: PA3MD 0 1 Description Peripheral module clock output (CKPO) FRT output compare output (FTOB) (Initial value)
Bit 2—PA2 Mode Bit (PA2MD): Selects the function of pin PA2/LNKSTA.
Bit 2: PA2MD 0 1 Description General input/output (PA2) EtherC rink status input (LNKSTA) (Initial value)
FVOTDW
Note:
*
is an output pin after a reset, so care is required when using this pin as a general input port (PA7).
FVOTDW
)*
Bit 7—PA7 Mode Bit (PA7MD): Selects the function of pin
/PA7.
(Initial value)
FVOTDW
Rev. 2.00, 03/05, page 765 of 884
Bit 1—PA1 Mode Bit (PA1MD): Selects the function of pin PA1/EXOUT.
Bit 1: PA1MD 0 1 Description General input/output (PA1) EtherC general external output (EXOUT) (Initial value)
Bit 0—PA0 Mode Bit (PA0MD): Selects the function of pin PA0.
Bit 0: PA0MD 0 1 Description General input/output (PA0) Reserved (Initial value)
18.3.2
Port A I/O Register (PAIOR)
Bit: Initial value: R/W: Bit: Initial value: R/W: 15 — 0 R 7 0 R/W 14 — 0 R 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 — 0 R 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W
PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR PA8IOR
PA7IOR PA6IOR PA5IOR PA4IOR
PA2IOR PA1IOR PA0IOR
The port A I/O register (PAIOR) is a 16-bit read/write register that selects the input/output direction of the 14 multiplex pins in port A. Bits PA13IOR to PA4IOR and PA2IOR to PA0IOR correspond to individual pins in port A. PAIOR is enabled when port A pins function as general input pins (PA13 to PA4 and PA2 to PA0), and disabled otherwise. When port A pins function as PA13 to PA0, a pin becomes an output when the corresponding bit in PAIOR is set to 1, and an input when the bit is cleared to 0. PAIOR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in standby mode or sleep mode.
Rev. 2.00, 03/05, page 766 of 884
18.3.3
Port B Control Registers (PBCR, PBCR2)
The port B control registers (PBCR and PBCR2) are 16-bit read/write registers that select the functions of the 16 multiplex pins in port B. PBCR selects the functions of the pins for the upper 8 bits in port B, and PBCR2 selects the functions of the pins for the lower 8 bits in port B. PBCR and PBCR2 are initialized to H'0000 by a power-on reset. They are not initialized by a manual reset or in standby mode or sleep mode. Port B Control Register (PBCR)
Bit: 15 PB15 MD1 Initial value: R/W: Bit: 0 R/W 7 PB11 MD1 Initial value: R/W: 0 R/W 14 PB15 MD0 0 R/W 6 PB11 MD0 0 R/W 13 PB14 MD1 0 R/W 5 PB10 MD1 0 R/W 12 PB14 MD0 0 R/W 4 PB10 MD0 0 R/W 11 PB13 MD1 0 R/W 3 PB9 MD1 0 R/W 10 PB13 MD0 0 R/W 2 PB9 MD0 0 R/W 9 PB12 MD1 0 R/W 1 PB8 MD1 0 R/W 8 PB12 MD0 0 R/W 0 PB8 MD0 0 R/W
Bits 15 and 14—PB15 Mode Bits 1 and 0 (PB15MD1, PB15MD0): These bits select the function of pin PB15/SCK1.
Bit 15: PB15MD1 0 1 Bit 14: PB15MD0 0 1 0 1 Description General input/output (PB15) Reserved SCIF1 serial clock input/output (SCK1) Reserved (Initial value)
Bits 13 and 12—PB14 Mode Bits 1 and 0 (PB14MD1, PB14MD0): These bits select the function of pin PB14/RXD1.
Bit 13: PB14MD1 0 1 Bit 12: PB14MD0 0 1 0 1 Description General input/output (PB14) Reserved SCIF1 serial data input (RXD1) Reserved (Initial value)
Rev. 2.00, 03/05, page 767 of 884
Bits 11 and 10—PB13 Mode Bits 1 and 0 (PB13MD1, PB13MD0): These bits select the function of pin PB13/TXD1.
Bit 11: PB13MD1 0 1 Bit 10: PB13MD0 0 1 0 1 Description General input/output (PB13) Reserved SCIF1 serial data output (TXD1) Reserved (Initial value)
Bits 9 and 8—PB12 Mode Bits 1 and 0 (PB12MD1, PB12MD0): These bits select the function of /STATS1. pin PB12/SRCK2/
Bit 9: PB12MD1 0 1
1
BSC status 1 output (STATS1)
Bits 7 and 6—PB11 Mode Bits 1 and 0 (PB11MD1, PB11MD0): These bits select the function of /STATS0. pin PB11/SRS2/
Bit 7: PB11MD1 0 1
Bit 6: PB11MD0 0 1 0 1
Description General input/output (PB11) SCIF1 transmit permission ( ) (Initial value)
SIO2 serial receive synchronous input (SRS2) BSC status 0 output (STATS0)
Bits 5 and 4—PB10 Mode Bits 1 and 0 (PB10MD1, PB10MD0): These bits select the function of pin PB10/SRXD2/TIOCA1.
Bit 5: PB10MD1 0 1 Bit 4: PB10MD0 0 1 0 1 Description General input/output (PB10) SIO2 serial receive data input (SRXD2) TPU1 input capture input/output compare output (TIOCA1) Reserved (Initial value)
Rev. 2.00, 03/05, page 768 of 884
STC
STR
STR
Bit 8: PB12MD0 0 1 0
Description General input/output (PB12) SIO2 serial receive clock input (SRCK2) SCIF1 transmit request ( ) (Initial value)
STC
Bits 3 and 2—PB9 Mode Bits 1 and 0 (PB9MD1, PB9MD0): These bits select the function of pin PB9/STCK2/TIOCB1, TCLKC.
Bit 3: PB9MD1 0 1 Bit 2: PB9MD0 0 1 0 1 Note: * Description General input/output (PB9) (Initial value)
SIO2 serial transmit clock input (STCK2) TPU1 input capture input/output compare output (TIOCB1)* Reserved
Timer clock input C (TCLKC) is selected when the TPU phase counting mode is set, or according to the setting of bits TPSC2 to TPSC0 in TCR.
Bits 1 and 0—PB8 Mode Bits 1 and 0 (PB8MD1, PB8MD0): These bits select the function of pin PB8/STS2/TIOCA2.
Bit 1: PB8MD1 0 1 Bit 0: PB8MD0 0 1 0 1 Description General input/output (PB8) (Initial value)
SIO2 serial transmit synchronous input/output (STS2) TPU2 input capture input/output compare output (TIOCA2) Reserved
Port B Control Register 2 (PBCR2)
Bit: 15 PB7 MD1 Initial value: R/W: Bit: 0 R/W 7 PB3 MD1 Initial value: R/W: 0 R/W 14 PB7 MD0 0 R/W 6 PB3 MD0 0 R/W 13 PB6 MD1 0 R/W 5 PB2 MD1 0 R/W 12 PB6 MD0 0 R/W 4 PB2 MD0 0 R/W 11 PB5 MD1 0 R/W 3 PB1 MD1 0 R/W 10 PB5 MD0 0 R/W 2 PB1 MD0 0 R/W 9 PB4 MD1 0 R/W 1 PB0 MD1 0 R/W 8 PB4 MD0 0 R/W 0 PB0 MD0 0 R/W
Rev. 2.00, 03/05, page 769 of 884
Bits 15 and 14—PB7 Mode Bits 1 and 0 (PB7MD1, PB7MD0): These bits select the function of pin PB7/STXD2/TIOCB2, TCLKD.
Bit 15: PB7MD1 0 1 Bit 14: PB7MD0 0 1 0 1 Note: * Description General input/output (PB7) (Initial value)
SIO2 serial transmit data output (STXD2) TPU2 input capture input/output compare output (TIOCB2)* Reserved
Timer clock input D (TCLKD) is selected when the TPU phase counting mode is set, or according to the setting of bits TPSC2 to TPSC0 in TCR.
Bits 13 and 12—PB6 Mode Bits 1 and 0 (PB6MD1, PB6MD0): These bits select the function of pin PB6/SRCK1/SCK2.
Bit 13: PB6MD1 0 1 Bit 12: PB6MD0 0 1 0 1 Description General input/output (PB6) SIO1 serial receive clock input (SRCK1) SCIF2 serial clock input/output (SCK2) Reserved (Initial value)
Bits 11 and 10—PB5 Mode Bits 1 and 0 (PB5MD1, PB5MD0): These bits select the function of pin PB5/SRS1/RXD2.
Bit 11: PB5MD1 0 1 Bit 10: PB5MD0 0 1 0 1 Description General input/output (PB5) SCIF2 serial data input (RXD2) Reserved (Initial value)
SIO1 serial receive synchronous input (SRS1)
Bits 9 and 8—PB4 Mode Bits 1 and 0 (PB4MD1, PB4MD0): These bits select the function of pin PB4/SRXD1/TXD2.
Bit 9: PB4MD1 0 1 Bit 8: PB4MD0 0 1 0 1 Description General input/output (PB4) SIO1 serial receive data input (SRXD1) SCIF2 serial data output (TXD2) Reserved (Initial value)
Rev. 2.00, 03/05, page 770 of 884
Bits 7 and 6—PB3 Mode Bits 1 and 0 (PB3MD1, PB3MD0): These bits select the function of pin PB3/STCK1/TIOCA0.
Bit 7: PB3MD1 0 1 Bit 6: PB3MD0 0 1 0 1 Description General input/output (PB3) (Initial value)
SIO1 serial transmit clock input (STCK1) TPU0 input capture input/output compare output (TIOCA0) Reserved
Bits 5 and 4—PB2 Mode Bits 1 and 0 (PB2MD1, PB2MD0): These bits select the function of pin PB2/STS1/TIOCB0.
Bit 5: PB2MD1 0 1 Bit 4: PB2MD0 0 1 0 1 Description General input/output (PB2) (Initial value)
SIO1 serial transmit synchronous input/output (STS1) TPU0 input capture input/output compare output (TIOCB0) Reserved
Bits 3 and 2—PB1 Mode Bits 1 and 0 (PB1MD1, PB1MD0): These bits select the function of pin PB1/STXD1/TIOCC0/TCLKA.
Bit 3: PB1MD1 0 1 Bit 2: PB1MD0 0 1 0 1 Note: * Description General input/output (PB1) (Initial value)
SIO1 serial transmit data output (STXD1) TPU0 input capture input/output compare output (TIOCC0)* Reserved
Timer clock input A (TCLKA) is selected when the TPU phase counting mode is set, or according to the setting of bits TPSC2 to TPSC0 in TCR.
Rev. 2.00, 03/05, page 771 of 884
Bits 1 and 0—PB0 Mode Bits 1 and 0 (PB0MD1, PB0MD0): These bits select the function of pin PB0/TIOCD0/TCLKB/WOL.
Bit 1: PB0MD1 0 1 Bit 0: PB0MD0 0 1 0 1 Note: * Description General input/output (PB0) Reserved TPU0 input capture input/output compare output (TIOCD0)* EtherC Wake-On-LAN output (WOL) (Initial value)
Timer clock input B (TCLKB) is selected when the TPU phase counting mode is set, or according to the setting of bits TPSC2 to TPSC0 in TCR.
18.3.4
Port B I/O Register (PBIOR)
Bit: 15 PB15 IOR Initial value: R/W: Bit: 0 R/W 7 PB7 IOR Initial value: R/W: 0 R/W 14 PB14 IOR 0 R/W 6 PB6 IOR 0 R/W 13 PB13 IOR 0 R/W 5 PB5 IOR 0 R/W 12 PB12 IOR 0 R/W 4 PB4 IOR 0 R/W 11 PB11 IOR 0 R/W 3 PB3 IOR 0 R/W 10 PB10 IOR 0 R/W 2 PB2 IOR 0 R/W 9 PB9 IOR 0 R/W 1 PB1 IOR 0 R/W 8 PB8 IOR 0 R/W 0 PB0 IOR 0 R/W
The port B I/O register (PBIOR) is a 16-bit read/write register that selects the input/output direction of the 16 multiplex pins in port B. Bits PB15IOR to PB0IOR correspond to individual pins in port B. PBIOR is enabled when port B pins function as general input pins (PB15 to PB0), and disabled otherwise. When port B pins function as PB15 to PB0, a pin becomes an output when the corresponding bit in PBIOR is set to 1, and an input when the bit is cleared to 0. PBIOR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in standby mode or sleep mode.
Rev. 2.00, 03/05, page 772 of 884
Section 19 I/O Ports
19.1 Overview
This chip has two ports, designated A and B. Port A is a 14-bit input/output port, and port B is a 16-bit input/output port. The port pins are multiplexed as general input/output and other functions. (The function of multiplexed multiplex pins is selected by means of the pin function controller (PFC).) Ports A and B are each provided with a data register for storing pin data.
19.2
Port A
Port A is an input/output port with the 14 pins shown in figure 19.1. Of the 14 pins, the CKPO pin has no port data register bit, and is multiplexed as an internal clock pin.
PA13 (input/output) / SRCK0 PA12 (input/output) / SRS0 PA11 (input/output) / SRXD0 PA10 (input/output) / STCK0 PA9 PA8 Port A PA6 PA5 PA4 PA2 PA1 PA0 (input/output) / STS0 (input/output) / STXD0 (input/output) / FTCI (input/output) / FTI (input/output) / FTOA / FTOB (input) (input) (input) (input) (input/output) (output) (input/output) (input) (input) (output) (output) (output)
WDTOVF* (output) / PA7
CKPO (output)
(input/output) / LNKSTA (input) (input/output) / EXOUT (input/output)
Note: * The fact that the WDTOVF pin is set to output mode after a reset must be noted when it is to be used as a general I/O port (PA7).
Figure 19.1 Port A
Rev. 2.00, 03/05, page 773 of 884
19.2.1
Register Configuration
The port A register is shown in table 19.1. Table 19.1 Register Configuration
Name Port A data register Abbreviation PADR R/W R/W Initial Value H'0000 Address H'FFFFFC84 Access Size 8, 16
19.2.2
Port A Data Register (PADR)
Bit: Initial value: R/W: Bit: Initial value: R/W: 15 — 0 R 7 PA7DR 0 R/W 14 — 0 R 6 PA6DR 0 R/W 13 0 R/W 5 PA5DR 0 R/W 12 0 R/W 4 PA4DR 0 R/W 11 0 R/W 3 — 0 R 10 0 R/W 2 PA2DR 0 R/W 9 0 R/W 1 PA1DR 0 R/W 8 PA8DR 0 R/W 0 PA0DR 0 R/W
PA13DR PA12DR PA11DR PA10DR PA9DR
The port A data register (PADR) is a 16-bit read/write register that stores port A data. Bits 15, 14, and 3 are reserved: they always read 0, and the write value should always be 0. Bits PA13DR to PA0DR correspond to pins PA13 to PA0. When a pin functions as a general output, if a value is written to PADR, that value is output directly from the pin, and if PADR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PADR is read the pin state, not the register value, is returned directly. If a value is written to PADR, although that value is written into PADR it does not affect the pin state. Table 19.2 summarizes port A data register read/write operations. PADR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in standby mode or sleep mode.
Rev. 2.00, 03/05, page 774 of 884
Table 19.2 Port A Data Register (PADR) Read/Write Operations
PAIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PADR value PADR value Write Value is written to PADR, but does not affect pin state Value is written to PADR, but does not affect pin state Write value is output from pin Value is written to PADR, but does not affect pin state
19.3
Port B
Port B is an input/output port with the 16 pins shown in figure 19.2.
PB15 (input/output) / Reserved PB14 (input/output) / Reserved PB13 (input/output) / Reserved PB12 (input/output) / SRCK2 (input) PB11 (input/output) / SRS2 (input) PB10 (input/output) / SRXD2 (input) PB9 (input/output) / STCK2 (input) Port B PB8 (input/output) / STS2 PB7 (input/output) / STXD2 (output) PB6 (input/output) / SRCK1 (input) PB5 (input/output) / SRS1 (input) PB4 (input/output) / SRXD1 (input) PB3 (input/output) / STCK1 (input) PB2 (input/output) / STS1 PB1 (input/output) / STXD1 (output) PB0 (input/output) / Reserved
/ SCK1 / RXD1 / TXD1 / RTS / CTS
(input/output) / Reserved (input) (output) (output) (input) / Reserved / Reserved / STATS1 (output) / STATS0 (output)
/ TIOCA1 (input/output) / Reserved / TIOCB1 (input/output) / Reserved / TIOCB2 (input/output) / Reserved / SCK2 / RXD2 / TXD2 (input/output) / Reserved (input) (output) / Reserved / Reserved
(input/output) / TIOCA2 (input/output) / Reserved
/ TIOCA0 (input/output) / Reserved / TIOCD0 (input/output) / Reserved / TIOCD0 (input/output) / WOL (output)
(input/output) / TIOCB0 (input/output) / Reserved
Figure 19.2 Port B
Rev. 2.00, 03/05, page 775 of 884
19.3.1
Register Configuration
Table 19.3 shows the port B register. Table 19.3 Register Configuration
Name Port B data register Abbreviation PBDR R/W R/W Initial Value H'0000 Address H'FFFFFC8C Access Size 8, 16
19.3.2
Port B Data Register (PBDR)
Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 R/W 7 PB7DR 0 R/W 14 0 R/W 6 PB6DR 0 R/W 13 0 R/W 5 PB5DR 0 R/W 12 0 R/W 4 PB4DR 0 R/W 11 0 R/W 3 PB3DR 0 R/W 10 0 R/W 2 PB2DR 0 R/W 9 0 R/W 1 PB1DR 0 R/W 8 PB8DR 0 R/W 0 PB0DR 0 R/W
PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR
The port B data register (PBDR) is a 16-bit read/write register that stores port B data. Bits PB15DR to PB0DR correspond to pins PB15 to PB0. When a pin functions as a general output, if a value is written to PBDR, that value is output directly from the pin, and if PBDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PBDR is read the pin state, not the register value, is returned directly. If a value is written to PBDR, although that value is written into PBDR it does not affect the pin state. Table 19.4 shows port B data register read/write operations. PBDR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset, in standby mode or sleep mode.
Rev. 2.00, 03/05, page 776 of 884
Table 19.4 Port B Data Register (PBDR) Read/Write Operations
PBIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PBDR value PBDR value Write Value is written to PBDR, but does not affect pin state Value is written to PBDR, but does not affect pin state Write value is output from pin Value is written to PBDR, but does not affect pin state
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Section 20 Power-Down Modes
20.1 Overview
This chip has a module standby function (which reduces power consumption by selectively halting operation of unnecessary modules among the on-chip peripheral modules and the DSP unit), a sleep mode (which halts CPU functions), and a standby mode (which halts all functions). 20.1.1 Power-Down Modes
The following modes and function are provided as power-down modes: 1. Sleep mode 2. Standby mode 3. Module standby function (UBC, DMAC, DSP, FRT, SCIF1 to SCIF2, TPU, SIO0 to SIO2) Table 20.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode.
Rev. 2.00, 03/05, page 779 of 884
Table 20.1 Power-Down Modes
State On-Chip Oscillation Circuit, Transition E-DMAC, CPU, Condition EtherC Cache DSP SLEEP Runs instruction executed with SBY bit set to 0 in SBYCR1 Halted Halted UBC, DMAC, FRT, SCIF1 to SCIF2, TPU, SIO2 to SIO0 Pins Runs Runs
Mode Sleep mode
BSC Runs
Canceling Procedure 1. Interrupt 2. DMA address error 3. Power-on reset 4. Manual reset
Standby SLEEP Halted mode instruction executed with SBY bit set to 1 in SBYCR1 Module MSTP bit Runs standby for relevant function module is set to 1
Halted Halted
Halted, and register values held
UBC: Halted, Held or 1. NMI interrupt and register high values held impedance 2. Power-on Other than reset UBC: Halted 3. Manual reset When an MSTP bit is 1, the clock supply to the relevant module is halted FRT, and 1. Clear SCIF1, 2 MSTP bit pins are to 0 initialized, 2. Power-on and others reset operate 3. Manual reset
Runs
When Runs MSTP is 1, the clock supply is halted
20.1.2
Register
Table 20.2 shows the register configuration. Table 20.2 Register Configuration
Name Standby control register 1 Standby control register 2 Abbreviation SBYCR1 SBYCR2 R/W R/W R/W Initial Value H'00 H'00 Address H'FFFFFE91 H'FFFFFE93 Access Size 8 8
Rev. 2.00, 03/05, page 780 of 884
20.2
20.2.1
Register Descriptions
Standby Control Register 1 (SBYCR1)
Bit: 7 SBY Initial value: R/W: 0 R/W 6 HIZ 0 R/W 5 MSTP5 (UBC) 0 R/W 4 MSTP4 (DMAC) 0 R/W 3 MSTP3 (DSP) 0 R/W 0 R 2 — 1 MSTP1 (FRT) 0 R/W 0 R 0 —
Standby control register 1 (SBYCR1) is an 8-bit read/write register that sets the power-down mode. SBYCR is initialized to H'00 by a reset. Bit 7—Standby (SBY): Specifies transition to standby mode. To enter the standby mode, halt the WDT (set the TME bit in WTCSR to 0) and set the SBY bit.
Bit 7: SBY 0 1 Description Executing a SLEEP instruction puts the chip into sleep mode Executing a SLEEP instruction puts the chip into standby mode (Initial value)
Bit 6—Port High Impedance (HIZ): Selects whether output pins are set to high impedance or retain the output state in standby mode. When HIZ = 0 (initial state), the specified pin retains its output state. When HIZ = 1, the pin goes to the high-impedance state. See appendix B.1, Pin States during Resets, Power-Down States and Bus Release State, for which pins are controlled.
Bit 6: HIZ 0 1 Description Pin state retained in standby mode Pin goes to high impedance in standby mode (Initial value)
Bit 5—Module Stop 5 (MSTP5): Specifies halting the clock supply to the user break controller (UBC). When the MSTP5 bit is set to 1, the supply of the clock to the UBC is halted. When the clock halts, the UBC registers retain their pre-halt state. Do not set this bit while the UBC is running.
Bit 5: MSTP5 0 1 Description UBC running Clock supply to UBC halted (Initial value)
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Bit 4—Module Stop 4 (MSTP4): Specifies halting the clock supply to the DMAC. When MSTP4 bit is set to 1, the supply of the clock to the DMAC is halted. When the clock halts, the DMAC retains its pre-halt state. When MSTP4 is cleared to 0 and the DMAC begins running again, its starts operating from its pre-halt state. Set this bit while the DMAC is halted; this bit cannot be set while the DMAC is operating (transferring data).
Bit 4: MSTP4 0 1 Description DMAC running Clock supply to DMAC halted (Initial value)
Bit 3—Module Stop 3 (MSTP3): Specifies halting the clock supply to the DSP unit. When the MSTP3 bit is set to 1, the supply of the clock to the DSP unit is halted. When the clock halts, the operation result prior to the halt is retained. This bit should be set when the DSP unit is halted. When the DSP unit is halted, no instructions with a DSP register, MACH, or MACL as an operand can be used.
Bit 3: MSTP3 0 1 Description DSP running Clock supply to DSP halted (Initial value)
Bit 2—Reserved: This bit is always read as 0. The write value should always be 0. Bit 1—Module Stop 1 (MSTP1): Specifies halting the clock supply to the 16-bit free-running timer (FRT). When the MSTP1 bit is set to 1, the supply of the clock to the FRT is halted. When the clock halts, all FRT registers are initialized except the FRT interrupt vector register in INTC, which holds its previous value. When MSTP1 is cleared to 0 and the FRT begins running again, its starts operating from its initial state.
Bit 1: MSTP1 0 1 Description FRT running Clock supply to FRT halted (Initial value)
Bit 0—Reserved: This bit is always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 782 of 884
20.2.2
Standby Control Register 2 (SBYCR2)
Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 4 3 2 1 0
MSTP11 MSTP10 MSTP9 (TPU) (SIO2) (SIO1) 0 R/W 0 R/W 0 R/W
MSTP8 MSTP7 MSTP6 (SIO0) (SCIF2) (SCIF1) 0 R/W 0 R/W 0 R/W
Standby control register 2 (SBYCR2) is an 8-bit read/write register that sets the power-down mode state. SBYCR2 is initialized to H'00 by a reset. Bits 7 and 6—Reserved: These bits are always read as 0. The write value should always be 0. Bit 5—Module Stop 11 (MSTP11): Specifies halting the clock supply to the 16-bit timer pulse unit (TPU). When the MSTP11 bit is set to 1, the supply of the clock to the TPU is halted. When the clock halts, the TPU retains its pre-halt state, and the TPU interrupt vector register in the INTC retains its pre-halt value. Therefore, when MSTP11 is cleared to 0 and the clock supply to the TPU is resumed, the TPU starts operating again.
Bit 5: MSTP11 0 1 Description TPU running Clock supply to TPU halted (Initial value)
Bit 4—Module Stop 10 (MSTP10): Specifies halting the clock supply to SIO channel 2. When the MSTP10 bit is set to 1, the supply of the clock to SIO channel 2 is halted. When the clock halts, SIO channel 2 retains its pre-halt state, and the SIO channel 2 interrupt vector register in the INTC retains its pre-halt value. Therefore, when MSTP10 is cleared to 0 and the clock supply to SIO channel 2 is restarted, operation starts again.
Bit 4: MSTP10 0 1 Description SIO channel 2 running Clock supply to SIO channel 2 halted (Initial value)
Rev. 2.00, 03/05, page 783 of 884
Bit 3—Module Stop 9 (MSTP9): Specifies halting the clock supply to SIO channel 1. When the MSTP9 bit is set to 1, the supply of the clock to SIO channel 1 is halted. When the clock halts, SIO channel 1 retains its pre-halt state, and the SIO channel 1 interrupt vector register in the INTC retains its pre-halt value. Therefore, when MSTP9 is cleared to 0 and the clock supply to SIO channel 1 is restarted, operation starts again.
Bit 3: MSTP9 0 1 Description SIO channel 1 running Clock supply to SIO channel 1 halted (Initial value)
Bit 2—Module Stop 8 (MSTP8): Specifies halting the clock supply to SIO channel 0. When the MSTP8 bit is set to 1, the supply of the clock to SIO channel 0 is halted. When the clock halts, SIO channel 0 retains its pre-halt state, and the SIO channel 0 interrupt vector register in the INTC retains its pre-halt value. Therefore, when MSTP8 is cleared to 0 and the clock supply to SIO channel 0 is restarted, operation starts again.
Bit 2: MSTP8 0 1 Description SIO channel 0 running Clock supply to SIO channel 0 halted (Initial value)
Bit 1—Module Stop 7 (MSTP7): Specifies halting the clock supply to SCIF2. When the MSTP7 bit is set to 1, the supply of the clock to SCIF2 is halted. When the clock halts, the SCIF2 registers are initialized, but the SCIF2 interrupt vector register in the INTC retains its pre-halt value. Therefore, when MSTP7 is cleared to 0 and SCIF2 begins running again, it starts operating from its initial state.
Bit 1: MSTP7 0 1 Description SCIF2 running Clock supply to SCIF2 halted (Initial value)
Bit 0—Module Stop 6 (MSTP6): Specifies halting the clock supply to SCIF1. When the MSTP6 bit is set to 1, the supply of the clock to SCIF1 is halted. When the clock halts, the SCIF1 registers are initialized, but the SCIF1 interrupt vector register in the INTC retains its pre-halt value. Therefore, when MSTP6 is cleared to 0 and SCIF1 begins running again, it starts operating from its initial state.
Bit 0: MSTP6 0 1 Description SCIF1 running Clock supply to SCIF1 halted (Initial value)
Rev. 2.00, 03/05, page 784 of 884
20.3
20.3.1
Sleep Mode
Transition to Sleep Mode
Executing the SLEEP instruction when the SBY bit in SBYCR1 is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run in sleep mode. 20.3.2 Canceling Sleep Mode
Sleep mode is canceled by an interrupt, DMA address error, power-on reset, or manual reset. Cancellation by an Interrupt: When an interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. Sleep mode is not canceled if the interrupt cannot be accepted because its priority level is equal to or less than the mask level set in the CPU’s status register (SR) or if an interrupt by an on-chip peripheral module is disabled at the peripheral module. Cancellation by a DMA Address Error: If a DMA address error occurs, sleep mode is canceled and DMA address error exception handling is executed. Cancellation by a Power-On Reset: A power-on reset cancels sleep mode. Cancellation by a Manual Reset: A manual reset cancels sleep mode.
20.4
20.4.1
Standby Mode
Transition to Standby Mode
To enter standby mode, set the SBY bit to 1 in SBYCR1, then execute the SLEEP instruction. The chip switches from the program execution state to standby mode. The NMI interrupt cannot be accepted when the SLEEP instruction is executed, or for the following five cycles. In standby mode, the clock supply to all on-chip peripheral modules is halted as well as the CPU. CPU register contents are held, and some on-chip peripheral modules are initialized.
Rev. 2.00, 03/05, page 785 of 884
Table 20.3 Register States in Standby Mode
Registers that Retain Data All registers All registers All registers • DMA source address registers 0 and 1 Registers with Undefined Contents — — — —
Module Interrupt controller (INTC) User break controller (UBC) Bus state controller (BSC) Direct memory access controller (DMAC)
Registers Initialized — — — DMA channel control register 0, 1
DMA operation register • DMA destination address registers 0 and 1 • DMA transfer count registers 0 and 1 • DMA request/ response selection control registers 0 and 1 • Vector number setting registers DMA0 and DMA1 Watchdog timer (WDT) Bits 7 to 5 of the timer control/status register Reset control/status register 16-bit free-running timer (FRT) All registers Serial communication interface All registers with FIFO (SCIF1 to SCIF2) Serial I/O (SIO0 to SIO2) High-performance user debugging interface (H-UDI) 16-bit timer pulse unit (TPU) Pin function controller (PFC) Ethernet controller direct memory access controller (E-DMAC) Ethernet controller (EtherC) Others — — — — All registers Bits 2 to 0 of the timer control/status register Timer counter — — All registers All registers All registers All registers — — — — — — — — —
All registers —
— Standby control registers 1 and 2 Frequency modification register
— —
Rev. 2.00, 03/05, page 786 of 884
20.4.2
Canceling Standby Mode
Standby mode is canceled by an NMI interrupt, a power-on reset, or a manual reset. Cancellation by an NMI Interrupt: When a rising edge or falling edge is detected in the NMI signal, after the elapse of the time set in the WDT timer control/status register, clocks are supplied to the entire chip, standby mode is canceled, and NMI exception handling begins. Insure that the interval set for the WDT is at least as long as the oscillation stabilization time. When standby mode is canceled by a falling edge in the NMI signal, insure that the NMI pin goes high when standby mode is entered (when the clock is halted), and goes low on recovering from standby mode (when the clock starts after oscillation has stabilized). The low level at the NMI pin should be held for at least 3 cycles after the start of clock signal output from the CKIO pin. When standby mode is canceled by a rising edge in the NMI signal, insure that the NMI pin goes low when standby mode is entered (when the clock is halted), and goes high on recovering from standby mode (when the clock starts after oscillation has stabilized). The high level at the NMI pin should be held for at least 3 cycles after the start of clock signal output from the CKIO pin. Cancellation by a Power-On Reset: A power-on reset cancels standby mode. Cancellation by a Manual Reset: A manual reset cancels standby mode. 20.4.3 Standby Mode Cancellation by NMI Interrupt
The following example describes moving to the standby mode upon the fall of the NMI signal and clearing the standby mode when the NMI signal rises. Figure 20.1 shows the timing. When the NMI pin level changes from high to low after the NMI edge select bit (NMIE) of the interrupt control register (ICR) has been set to 0 (detect falling edge), an NMI interrupt is accepted. When the NMIE bit is set to 1 (detect rising edge) by the NMI exception service routine, the standby bit (SBY) of the standby control register 1 (SBYCR1) is set to 1 and a SLEEP instruction is executed, the standby mode is entered. The standby mode is cleared the next time the NMI pin level changes from low level to high level. The high level at the NMI pin should be held for at least 3 cycles after the start of clock signal output from the CKIO pin.
Rev. 2.00, 03/05, page 787 of 884
Oscillator CKIO (output) NMI
NMIE
SBY NMI exception handling Exception service routine, SBY = 1, SLEEP instruction
Oscillation settling time Standby mode Start of oscillation WDT set time NMI exception handling
Figure 20.1 Standby Mode Cancellation by NMI Interrupt 20.4.4 Clock Pause Function
When the clock is input from the CKIO pin, the clock frequency can be modified or the clock stopped. The /CKM pin is provided for this purpose. Note that clock pauses are not accepted while the watchdog timer (WDT) is operating (i.e. when the timer enable bit (TME) in the WDT’s timer control/status register (WTCSR) is 1). When the clock pause request function is used, the standby bit (SBY) in the standby control register 1 (SBYCR1) must be set to 1 before inputting the request signal. The clock pause function is used as described below. 1. Set the TME bit in the watchdog timer’s WTCSR register to 0, and set the SBY bit in SBYCR1 to 1. 2. Apply a low level to the /CKM pin. pin. 3. When the chip enters the standby state internally, a low level is output from the 4. After confirming that the pin has gone low, perform clock halting or frequency modification. 5. To cancel the clock pause state (standby state), apply a high level to the /CKM pin. /CKM (Inside the chip , the standby state is canceled by detecting a rising edge at the pin.) 6. When PLL circuit 1 is operational, the WDT starts counting up inside the chip. When PLL circuit 1 is halted, the WDT is not activated.
Rev. 2.00, 03/05, page 788 of 884
KCAPKC
QERPKC QERPKC
KCAPKC
QERPKC
QERPKC
The standby state, all on-chip peripheral module states, and all pin states during clock pause are the same as in the normal standby mode. Figure 20.2 shows the timing chart for the clock pause function.
Frequency modification CKIO input CKPREQ/CKM input CKPACK output Clock pause request cancellation
Clock pause acceptance processing
Figure 20.2 Clock Pause Function Timing Chart (PLL Circuit 1 Operating) Figure 20.3 shows the clock pause function timing chart when the PLL circuit is halted.
Frequency modification
CKIO input CKPREQ/ CKM input Clock pause request cancellation
CKPACK output
Clock pause acceptance processing
Figure 20.3 Clock Pause Function Timing Chart (PLL Circuit 1 Halted)
Rev. 2.00, 03/05, page 789 of 884
KCAPKC
7. When the internal clock stabilizes, the that the chip can be operated.
pin goes high, giving external notification
WDT count-up Clock pause state
Normal state
Clock pause state
Normal state
The clock pause state can be canceled by means of NMI input, in the same way as the normal standby state. The clock pause request should be canceled within four CKIO clock cycles after NMI input. Figure 20.4 shows the timing chart for clock pause state cancellation by means of NMI input (in the case of rising edge detection).
Frequency modification Max. 4 cycles
CKIO input
CKPREQ/ CKM input NMI input Clock pause request cancellation
CKPACK output
NMI interrupt
Clock pause acceptance processing
Clock pause state
Normal state
Figure 20.4 Clock Pause Function Timing Chart (Cancellation by NMI Input) 20.4.5 Notes on Standby Mode
1. When the chip enters standby mode during use of the cache, disable the cache before making the mode transition. Initialize the cache beforehand when the cache is used after returning to standby mode. The contents of the on-chip RAM are not retained in standby mode when cache is used as on-chip RAM. 2. If an on-chip peripheral register is written in the 10 clock cycles before the chip transits to standby mode, read the register before executing the SLEEP instruction. 3. When using clock mode 0, 1, or 2, the CKIO pin is the clock output pin. Note the following when standby mode is used in these clock modes. When standby mode is canceled by NMI, an unstable clock is output from the CKIO pin during the oscillation settling time after NMI input. This also applies to clock output in the case of cancellation by a power-on reset or manual reset. Power-on reset and manual reset input should be continued for a period at least equal to for the oscillation settling time. 4. Before entering the standby mode, stop operation of the internal DMAC (E-DMAC or DMAC).
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20.5
20.5.1
Module Standby Function
Transition to Module Standby Function
By setting one of bits MSTP11 to MSTP3, MSTP1 to 1 in standby control register 1 or 2, the supply of the clock to the corresponding on-chip peripheral module or DSP unit can be halted. This function can be used to reduce the power consumption. Do not perform read/write operations for a module in module standby mode. With the module standby function, the external pins of the DMAC and SIO0 to SIO2 on-chip peripheral modules retain their states prior to halting, as do DMAC, DSP, and SIO0 to SIO2 registers. The external pins of the FRT, SCIF1 to SCIF2, and TPU are reset and all their registers are initialized. An on-chip peripheral module corresponding to a module standby bit must not be switched to the module standby state while it is running. Also, interrupts from a module placed in the module stop state should be disabled. 20.5.2 Clearing the Module Standby Function
Clear the module standby function by clearing the MSTP11 to MSTP3, MSTP1 bits, or by a power-on reset or manual reset.
Rev. 2.00, 03/05, page 791 of 884
Rev. 2.00, 03/05, page 792 of 884
Section 21 Electrical Characteristics
21.1 Absolute Maximum Ratings
Table 21.1 shows the absolute maximum ratings. Table 21.1 Absolute Maximum Ratings
Item Power supply voltage (internal) Power supply voltage (5 V I/O) Input voltage (excluding 5 V I/O) Input voltage (5 V I/O) Operating temperature Storage temperature Symbol VCC PVCC Vin Vin Topr Tstg Value –0.3 to +4.2 –0.3 to +7.0 –0.3 to VCC +0.3 –0.3 to PVCC +0.3 –20 to +75 –55 to +125 Unit V V V V °C °C
Notes: 1. Permanent damage to the chip may result if the maximum ratings are exceeded. 2. When powering on, turn on the 5 V I/O power supply (PVCC) after, or at the same time as, the internal power supply (VCC). When powering off, cut VCC after, or at the same time as, PVCC.
Rev. 2.00, 03/05, page 793 of 884
21.2
DC Characteristics
Tables 21.2 and 21.3 show the DC characteristics. Table 21.2 DC Characteristics Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item Symbol Min Typ Max — VCC + 0.3 Unit Test Conditions V
Both 3.3 V and 5 V EXTAL, CKIO Other input pins Input low voltage , NMI, MD4 to MD0, /CKM VIL ,
Other input pins Schmitt trigger input voltage PB14/RXD1, PB5/SRS1/RXD2 VT VT VT Input leakage current All input pins
–
Three-state All I/O and output pins (off status) leakage current Output high Both 3.3 V and 5 V voltage Other output pins Output low Both 3.3 V and 5 V voltage Other output pins
Rev. 2.00, 03/05, page 794 of 884
TSRT TSRT
QERPKC QERPKC SER
SER
Input high voltage
, NMI, MD4 to MD0, /CKM
VIH ,
VCC × 0.9
2.6 VCC × 0.9 VCC × 0.7 –0.3
— — — —
PVCC + 0.3 V VCC + 0.3 VCC + 0.3 VCC × 0.1 V V V
–0.3 — 4.0 2.6
–
— — — — — —
0.8 0.8 — — — 1.0
V V V V V µA Vin = 0.5 to VCC – 0.5 V Vin = 0.5 to PVCC – 0.5 V PVCC = 5 V ±0.5 V Other than above
+ + +
VT – VT 0.3 lin —
lTSI
—
—
1.0
µA
Vin = 0.5 to VCC – 0.5 V Vin = 0.5 to PVCC – 0.5 V
VOH
PVCC – 0.7 — VCC – 0.5 VCC – 1.0 — — — —
— — — 0.6 0.4
V V V V V
IOH = –200 µA IOH = –200 µA IOH = –1 mA IOL = 1.6 mA IOL = 1.6 mA
VOL
— —
Item Pin CAP1, CAP2 capacitance Other input pins Normal operation Current dissipation
Symbol Min Cin lcc — — —
Typ Max — — — 40 15 350
Unit Test Conditions pF pF mA 3.6 V, CPU operating clock = 62.5 MHz, DMAC used 3.6 V, CPU operating clock = 62.5 MHz, DMAC not used 3.6 V, CPU operating clock = 62.5 MHz, peripheral modules not used Ta = 25°C
—
—
300
mA
Sleep mode
—
—
250
mA
Standby mode
—
—
990
µA
Note: Do not leave the PLLVCC and PLLVSS pins open when the PLL circuit is not used. Connect the PLLVCC pin to VCC and the PLLVSS pin to VSS.
Table 21.3 Permissible Output Currents Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Symbol IOL IOL (–IOH) –IOH Min — — — — Typ — — — — Max 2.0 80 2.0 25 Unit mA mA mA mA
Note: To protect chip reliability, do not exceed the output current values in table 21.3.
∑ ∑
Rev. 2.00, 03/05, page 795 of 884
21.3
AC Characteristics
In principle, input is synchronous. Unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. Table 21.4 Maximum Operating Frequencies Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item Operating frequency CPU, DSP External bus (SDRAM not used) External bus (SDRAM used) Peripheral modules Symbol f Min 1 1 1 1 Typ — — — — Max 62.5 31.25 62.5 31.25 Unit MHz Notes tIcyc tEcyc tEcyc tPcyc
Rev. 2.00, 03/05, page 796 of 884
21.3.1
Clock Timing
Table 21.5 Clock Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock input frequency CKIO clock input cycle time CKIO clock input low-level pulse width CKIO clock input high-level pulse width CKIO clock input rise time CKIO clock input fall time CKIO clock output frequency CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock rise time CKIO clock fall time CKPO clock output cycle time CKPO clock output low-level pulse width CKPO clock output high-level pulse width CKPO clock rise time CKPO clock fall time Power-on oscillation stabilization time Standby recovery oscillation stabilization time 1 Standby recovery oscillation stabilization time 2 PLL synchronization stabilization time Notes: 1. When PLL circuit 2 is operating Rev. 2.00, 03/05, page 797 of 884 Symbol fEX tEXcyc tEXL tEXH tEXR tEXF fCKI tCKIcyc tCKIL tCKIH tCKIR tCKIF fOP tcyc tCKOL tCKOH tCKOR tCKOF tCKPCYC tCKPOL tCKPOH tCKPOr tCKPOf tOSC1 tOSC2 tOSC3 tPLL Min 1 32 8*1, 12*2 8*1, 12*2 — — 1 32 8*3, 12*4 8*3, 12*4 — — 1*5, 8*6 16 3 3 — — 32 11 11 — — 10 10 10 1 Max 31.25 1000 — — 4 4 31.25 1000 — — 4 4 62.5 1000*5, 125*6 — — 5 5 1000 — — 5 5 — — — — Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ms ms ms ms 21.5 21.6 21.7 21.8 21.4 21.3 21.2 Figure 21.1
2. 3. 4. 5. 6.
When PLL circuit 2 is not used When PLL circuit 1 is operating When PLL circuit 1 is not used When PLL circuit 1 and 2 are not used When PLL circuit 1 or 2 is operating
tEXcyc tEXH EXTAL* (input) tEXL VIH 1/2 VCC tEXR
1/2 VCC
VIH
VIH VIL tEXF VIL
Note: * When clock is input from EXTAL pin
Figure 21.1 EXTAL Clock Input Timing
tCKIcyc tCKIH CKIO (input) VIH VIH VIL tCKIF VIL tCKIL VIH 1/2 VCC tCKIR
1/2 VCC
Figure 21.2 CKIO Clock Input Timing
tcyc tCKOH CKIO (output) tCKOL VOH 1/2VCC tCKOR
1/2VCC
VOH
VOH VOL tCKOF VOL
Figure 21.3 CKIO Clock Output Timing
Rev. 2.00, 03/05, page 798 of 884
tCKPCYC tCKPOH CKPO (output) tCKPOL VOH 1/2VCC tCKPOr
1/2VCC
VOH
VOH VOL tCKPOf VOL
Figure 21.4 CKPO Clock Output Timing
Stable oscillation
CKIO, internal clock
VCC
VCC min tRESW tOSC1
RES
Note: Oscillation stabilization time when using on-chip crystal oscillator
Figure 21.5 Power-On Oscillation Stabilization Time at Power-On
Stable oscillation
Standby CKIO, internal clock
tRESW tOSC2
RES
Note: Oscillation stabilization time when using on-chip crystal oscillator
Rev. 2.00, 03/05, page 799 of 884
SER
Figure 21.6 Oscillation Stabilization Time after Standby Recovery (Recovery by
)
Standby CKIO, internal clock
Stable oscillation
tOSC3
NMI
Note: Oscillation stabilization time when using on-chip crystal oscillator
Figure 21.7 Oscillation Stabilization Time after Standby Recovery (Recovery by NMI)
Change of oscillation frequency
Stable oscillation
Stable oscillation
EXTAL or CKIO
PLL synchronization tPLL PLL synchronization
Internal clock
Figure 21.8 PLL Synchronization Stabilization Time
Rev. 2.00, 03/05, page 800 of 884
21.3.2
Control Signal Timing
Table 21.6 Control Signal Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item rise and fall time pulse width Symbol tRESr, tRESf tRESW tNMIRS tNMIRH tNMIr, tNMIf tRESS tNMIS tIRLS tNMIH tIRLH tBLSS tBLSH tBGRD tBOFF tBON Min — 20 tPcyc + 10 tPcyc + 10 — 3tEcyc + 40 40 30 20 20 10 5 — 0 0 Max 200 — — — 200 — — — — — — — 15 35 35 Unit ns tPcyc ns ns ns ns ns ns ns ns ns ns ns ns ns 21.11 21.10 Figure 21.9
RES tNMIr tNMIf NMI tNMIRS VIH VIL
VIH VIL tRESW VIL
0LRI 3LRI
SER
Note:
0LRI 3LRI
RGB SLRB SLRB 0LRI 3LRI
SER SER SER
NMI reset setup time NMI reset hold time NMI rise and fall time setup time* NMI setup time* to to setup time* hold time* NMI hold time setup time hold time
delay time
Bus tri-state delay time Bus buffer on time *
The , NMI, and to signals are asynchronous inputs. If the setup times shown here are observed, a transition is judged to have occurred at the fall of the clock; if the setup times cannot be observed, recognition may be delayed until the next fall of the clock.
tRESf
tRESr VIH tNMIRH VIH VIL
Figure 21.9 Reset Input Timing
Rev. 2.00, 03/05, page 801 of 884
CKIO
tRESS VIH
RES
tNMIH
VIL tNMIS VIH
NMI
tIRLH
IRL3–IRL0
VIL tIRLS VIH VIL
Figure 21.10 Interrupt Signal Input Timing
CKIO
tBLSS tBLSH tBLSS tBLSH tBGRD
BRLS (input)
tBGRD
BGR (output)
tBOFF
RD, RD/WR, RAS, CAS, CSn, WEn, BS, IVECF A24–A0, D31–D0
tBON
tBOFF
tBON
Figure 21.11 Bus Release Timing
Rev. 2.00, 03/05, page 802 of 884
21.3.3
Bus Timing
Table 21.7 PLL-On Bus Timing [Modes 0 and 4] (1) Conditions: VCC = PLLVCC = 3.3 V ± 0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ± 0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item Address delay time delay time delay time 1 delay time 2 Symbol Min tAD tBSD tCSD1 tCSD2 tRWD tRSD1 tRDS1 tRDS2 tRDH2 tRDH4 tRDH5 tRDH6 tRDH7 tRDH8 tWED1 tWDD1 tWDD2 tWDH1 tDON tDOF 1 — 1 — 1 — 8 8 6.5 0 2 0 3 1 2 — — — 2 — — Max Unit Figure 14 15 14 14 14 14 — — — — — — — — — 14 22 12 — 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 21.12, 13, 16, 17, 19, 21, 23, 25 to 29, 31 to 35, 38 to 41, 43 to 45 21.12, 13, 16, 17, 19, 21, 23, 25, 26, 29, 31, 32, 34, 35, 40, 43 to 45 21.12, 13, 16, 17, 19, 21, 23 to 26, 29, 31 to 35, 40, 42, 43 21.12, 13, 34, 35, 40, 43 21.12, 13, 16, 17, 19, 21 to 23, 25, 26, 29 to 35, 40, 43 to 45 21.12, 13, 16, 17, 23, 31, 34, 35, 38, 40, 41, 43 to 45 21.12, 34, 38, 43 to 45 21.40, 41 21.16, 17 21.12, 43 21.16, 17 21.34, 38 21.40, 41 21.40 21.44, 45 21.12, 13 21.13, 23, 25, 27, 35, 39 21.26, 28 21.13, 23, 25 to 28, 35, 39 21.13, 23, 25, 26, 35 21.13, 23, 25, 26, 35
SC SC
SB
Read/write delay time Read strobe delay time 1 Read data setup time 1 Read data setup time 2 (EDO) Read data hold time 2 Read data hold time 4 (SDRAM) Read data hold time 5 (DRAM) Read data hold time 6 (EDO) Read data hold time 7 (EDO) Read data hold time 8 (interrupt vector) Write enable delay time 1 Write data delay time 1 (except tEcyc:tPcyc = 1:1) Write data delay time 2 (tEcyc:tPcyc = 1:1) Write data hold time 1 Data buffer on time Data buffer off time
Read data setup time 3 (SDRAM) tRDS3
Rev. 2.00, 03/05, page 803 of 884
Item DACK delay time 1 DACK delay time 2 setup time hold time
Symbol Min tDACD1 tDACD2 tWTS tWTH tRASD1 tRASD2 tRASD3 tCASD1 tCASD2 tDQMD tCKED tOED1 tOED2 tIVD tASR tASC tDS tAS tREFOD — — 10 5 1 — — 1 — 1 1 — — — 0 0 0 0 —
Max 14 14 — — 14 14 14 14 14 14 14 14 14 15 — — — — 15
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Figure 21.12, 13, 16, 19, 21, 23, 25, 26, 29, 34, 35, 38 to 41, 43 21.12, 13, 34, 35, 38 to 41, 43 21.14, 15, 36, 37, 43 to 46 21.14, 15, 36, 37, 43 to 46 21.16 to 19, 21 to 26, 29 to 33 21.34, 35, 40, 42 21.40 21.16, 17, 18, 19, 23 to 29, 31 to 33, 43 21.34, 35, 38 to 42 21.16, 17, 19 to 21, 23, 25 to 30 21.33 21.40 21.40 21.44, 45 21.34, 35, 40 21.34, 35, 38, 39, 40 21.35, 39 21.12, 13 21.47
Rev. 2.00, 03/05, page 804 of 884
FCEVI EO EO
SAC SAR SAR SAR TIAW TIAW SAC
delay time 1 (SDRAM) delay time 2 (DRAM, EDO) delay time 3 (EDO) delay time 1 (SDRAM) delay time 2 (DRAM)
DQM delay time CKE delay time delay time 1 delay time 2 delay time
Row address setup time Column address setup time Data input setup time Read/write address setup time REFOUT delay time
Table 21.7 PLL-On Bus Timing [Modes 0 and 4] (2) Conditions: VCC = PLLVCC = 3.3 V ±5%, PVCC = 5.0 V ±5%/3.3 V ±5%, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –5 to +70°C, SDRAM bus cycle
Item Read data setup time 3 (SDRAM) Read data hold time 4 (SDRAM) Write data delay time 2 (Iφ:Eφ = 1:1) Write data hold time 1 Address delay time delay time 1 Symbol tRDS3 tRDH4 tWDD2 tWDH1 tAD tCSD1 tRWD tDQMD tRASD1 tCASD1 tCKED Min 6.5 1.5 — 2 4 2.5 2.5 2.5 2.5 2.5 2.5 Max — — 9.5 — 11 9.5 9.5 9.5 9.5 9.5 9.5 Unit ns ns ns ns ns ns ns ns ns ns ns Figure 21.16, 17 21.16, 17 21.26, 28 21.26, 28 21.16, 17, 19, 21, 23, 25, 26, 27, 28, 29, 31, 32, 33 21.16, 17, 19, 21, 23, 24, 25, 26, 29, 31, 32, 33 21.16, 17, 19, 21, 22, 23, 25, 26, 29, 30, 31, 32, 33 21.16, 17, 19, 20, 21, 23, 25, 26, 27, 28, 29, 30 21.16, 17, 18, 21, 22, 23, 24, 25, 26, 29, 30, 31, 32, 33 21.16, 17, 18, 19, 23, 24, 25, 26, 27, 28, 29, 31, 32, 33 21.33
SAR
SAC
SC
Read/write delay time DQM delay time delay time 1 (SDRAM) delay time 1 (SDRAM) CKE delay time
Rev. 2.00, 03/05, page 805 of 884
T1 CKIO
T2
tAD
A24–A0
tAD tAS
tBSD
BS
tBSD
tCSD1
CSn
tCSD2
tRWD
RD/WR
tRWD
tRSD1
RD
tRSD1
tWED1
WEn ⋅ DQMxx tRDH2
tWED1
tRDS1
D31–D0
tDACD1
DACKn
tDACD2
WAIT
RAS
CAS ⋅ OE
CKE
Notes: 1. tRDH2 is measured from the rise of CSn or RD, whichever comes first. 2. DACKn waveform when active-high is specified
Figure 21.12 Basic Read Cycle (No Wait)
Rev. 2.00, 03/05, page 806 of 884
T1 CKIO
T2
tAD
A24–A0
tAD
tBSD
BS
tAS
tBSD
tCSD1
CSn
tCSD2
tRWD
RD/WR
tRWD
tRSD1
RD
tRSD1
tWED1
WEn ⋅ DQMxx
tWED1
tWDD1 tDON
D31–D0
tDOF tWDH1
tDACD1
DACKn
tDACD2
WAIT
RAS
CAS ⋅ OE
CKE
Note: DACKn waveform when active-high is specified
Figure 21.13 Basic Write Cycle (No Wait)
Rev. 2.00, 03/05, page 807 of 884
T1
CKIO
Tw
T2
A24–A0
BS
CSn
RD/WR
RD
WEn ⋅ DQMxx
D31–D0
DACKn
tWTS tWTH
WAIT
RAS
CAS ⋅ OE
CKE
Note: DACKn waveform when active-high is specified
Figure 21.14 Basic Bus Cycle (1 Wait Cycle)
Rev. 2.00, 03/05, page 808 of 884
T1 CKIO
Tw
Twx
T2
A24–A0
BS
CSn
RD/WR
RD WEn ⋅ DQMxx
D31–D0
DACKn tWTS tWTH WAIT tWTS tWTH
RAS
CAS ⋅ OE
CKE
Note: DACKn waveform when active-high is specified
Figure 21.15 Basic Bus Cycle (External Wait Input)
Rev. 2.00, 03/05, page 809 of 884
Tr CKIO tAD Address upper bits
Tc
Td1
Td2
Td3
Td4
Tde tAD
tAD Address lower bits tBSD BS tCSD1 CSn tRWD RD/WR tRSD1 RD WEn ⋅ DQMxx tDQMD tDQMD tRWD tCSD1 tBSD
tRDS3 tRDH4 tRDS3 tRDH4 tRDS3 tRDH4 tRDS3 tRDH4 D31–D0 tDACD1 DACKn tDACD1
WAIT tRASD1 RAS tCASD1 CAS · OE tCASD1 tCASD1 tCASD1 tRASD1 tRASD1
CKE
Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed. 2. DACKn waveform when active-high is specified
Figure 21.16 Synchronous DRAM Read Bus Cycle (RCD = 1 Cycle, CAS Latency = 1 Cycle, Burst = 4)
Rev. 2.00, 03/05, page 810 of 884
Tr CKIO tAD Address upper bits tAD Address lower bits tBSD BS tCSD1 CSn tRWD RD/WR
Tc
Td1
Td2
Td3
Td4
Tde
tAD
tBSD
tCSD1
tRWD
tRSD1 RD tDQMD WEn ⋅ DQMxx tRDS3 tRDH4 D31–D0 tDQMD tDQMD
DACKn
WAIT tRASD1 RAS tCASD1 CAS · OE CKE tCASD1 tCASD1 tCASD1 tRASD1 tRASD1
Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed. 2. DACKn waveform when active-high is specified
Figure 21.17 Synchronous DRAM Single Read Bus Cycle (RCD = 1 Cycle, CAS Latency = 1 Cycle, Burst = 4)
Rev. 2.00, 03/05, page 811 of 884
Tr CKIO
Trw
Tc
Tw
Td1
Td2
Td3
Td4
Tde
Address upper bits Address lower bits
BS
CSn RD/WR
RD
WEn DQMxx D31–D0
⋅
DACKn WAIT tRASD1 RAS CAS OE CKE
tRASD1
⋅
tCASD1
tCASD1
Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed. 2. DACKn waveform when active-high is specified
Figure 21.18 Synchronous DRAM Read Bus Cycle (RCD = 2 Cycles, CAS Latency = 2 Cycles, Burst = 4)
Rev. 2.00, 03/05, page 812 of 884
Tnop CKIO tAD Address upper bits Address lower bits BS
Tc
Td1
Td2
Td3
Td4
Tde
tBSD
tCSD1 CSn tRWD RD/WR
RD tDQMD WEn ⋅ DQMxx D31–D0 tDACD1 DACKn WAIT tRASD1 RAS tCASD1 CAS tCASD1 tCASD1 tCASD1
CKE
Note: DACKn waveform when active-high is specified
Figure 21.19 Synchronous DRAM Read Bus Cycle (Bank Active, Same Row Access, CAS Latency = 1 Cycle)
Rev. 2.00, 03/05, page 813 of 884
TC CKIO Address upper bits Address lower bits BS
TW
Td1
Td2
Td3
Td4
Tde
CSn
RD/WR
RD tDQMD WEn ⋅ DQMxx D31–D0
DACKn
WAIT
RAS CAS ⋅ OE CKE
Note: DACKn waveform when active-high is specified
Figure 21.20 Synchronous DRAM Read Bus Cycle (Bank Active, Same Row Access, CAS Latency = 2 Cycles)
Rev. 2.00, 03/05, page 814 of 884
Tp CKIO tAD Address upper bits
Tr
Tc
Td1
Td2
Td3
Td4
Tde
tAD Address lower bits tBSD BS tCSD1 CSn tRWD RD/WR tRWD
RD tDQMD WEn ⋅ DQMxx D31–D0 tDACD1 DACKn
WAIT tRASD1 RAS CAS · OE CKE tRASD1
Note: DACKn waveform when active-high is specified
Figure 21.21 Synchronous DRAM Read Bus Cycle (Bank Active, Different Row Access, TRP = 1 Cycle, RCD = 1 Cycle, CAS Latency = 1 Cycle)
Rev. 2.00, 03/05, page 815 of 884
Tp CKIO Address upper bits Address lower bits BS
Tpw
Tr
Tc
Td1
Tde
CSn tRWD RD/WR
RD WEn ⋅ DQMxx D31–D0
DACKn
WAIT tRASD1 RAS CAS ⋅ OE CKE tRASD1
Note: DACKn waveform when active-high is specified
Figure 21.22 Synchronous DRAM Read Bus Cycle (Bank Active, Different Row Access, TRP = 2 Cycles, RCD = 1 Cycle, CAS Latency = 1 Cycle)
Rev. 2.00, 03/05, page 816 of 884
Tr CKIO tAD Address upper bits
Tc
Tap tAD
tAD Address lower bits tBSD BS tCSD1 CSn tRWD RD/WR tRSD1 RD tDQMD WEn ⋅ DQMxx tDQMD tRWD tRWD tCSD1 tCSD1 tBSD
tWDD1 tDON
tDOF tWDH1
D31–D0 tDACD1 DACKn tDACD1 tDACD1
WAIT tRASD1 RAS CAS ⋅ OE CKE tCASD1 tCASD1 tCASD1 tRASD1 tRASD1 tRASD1
Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed. 2. DACKn waveform when active-high is specified
Figure 21.23 Synchronous DRAM Write Bus Cycle (RASD = 0, RCD = 1 Cycle, TRWL = 1 Cycle)
Rev. 2.00, 03/05, page 817 of 884
Tr CKIO
Trw
Tc
Trwl
Tap
Address upper bits Address lower bits BS tCSD1 CSn
RD/WR
RD WEn ⋅ DQMxx
D31–D0
DACKn
WAIT tRASD1 RAS CAS ⋅ OE tCASD1 tRASD1
CKE
Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed. 2. DACKn waveform when active-high is specified
Figure 21.24 Synchronous DRAM Write Bus Cycle (RASD = 0, RCD = 2 Cycles, TRWL = 2 Cycles)
Rev. 2.00, 03/05, page 818 of 884
Tc CKIO tAD Address upper bits Address lower bits BS tCSD1 CSn tRWD RD/WR tRWD tCSD1 tAD
tBSD
tBSD
RD tDQMD WEn ⋅ DQMxx tDQMD
tWDD1 tDON
tDOF tWDH1
D31–D0
tDACD1
DACKn WAIT
tDACD1
tRASD1
RAS
tCASD1
CAS ⋅ OE CKE
tCASD1
Note: DACKn waveform when active-high is specified
Figure 21.25 Synchronous DRAM Write Bus Cycle (Bank Active, Same Row Access, Except tEcyc:tPcyc 1:1)
Rev. 2.00, 03/05, page 819 of 884
Tc CKIO tAD Address upper bits Address lower bits tBSD BS tCSD1 CSn tRWD RD/WR tRWD tCSD1 tBSD tAD
RD tDQMD WEn ⋅ DQMxx tDQMD
tWDD2 tDON
tDOF tWDH1
D31–D0
tDACD1 DACKn WAIT
tDACD1
tRASD1 RAS tCASD1 CAS ⋅ OE CKE tCASD1
Note: DACKn waveform when active-high is specified
Figure 21.26 Synchronous DRAM Write Cycle (Bank Active, Same Row Access, Iφ:Eφ = 1:1)
Rev. 2.00, 03/05, page 820 of 884
Tc
CKIO
Tc
tAD
Address upper bits Address lower bits
BS
CSn
RD/WR
RD
tDQMD
WEn ⋅ DQMxx
tWDD1 tWDH1
D31–D0
DACKn
WAIT
RAS
tCASD1
CAS ⋅ OE CKE
tCASD1
Note: DACKn waveform when active-high is specified
Figure 21.27 Synchronous DRAM Continuous Write Cycle (Bank Active, Same Row Access, Except tEcyc:tPcyc 1:1)
Rev. 2.00, 03/05, page 821 of 884
Tc
CKIO
Tc
tAD
Address upper bits Address lower bits
BS
CSn
RD/WR
RD
tDQMD
WEn ⋅ DQMxx
tWDD2 tWDH1
D31–D0
DACKn
WAIT
RAS CAS ⋅ OE CKE
tCASD1
tCASD1
Note: DACKn waveform when active-high is specified
Figure 21.28 Synchronous DRAM Continuous Write Cycle (Bank Active, Same Row Access, Iφ:Eφ = 1:1)
Rev. 2.00, 03/05, page 822 of 884
Tp CKIO tAD Address upper bits Address lower bits tBSD BS tCSD1 CSn tRWD RD/WR
Tr
Tc
tRWD
RD tDQMD WEn ⋅ DQMxx tDQMD
D31–D0 tDACD1 DACKn
WAIT tRASD1 RAS tCASD1 CAS ⋅ OE CKE
Note: DACKn waveform when active-high is specified
Figure 21.29 Synchronous DRAM Write Bus Cycle (Bank Active, Different Row Access, TRP = 1 Cycle, RCD = 1 Cycle)
Rev. 2.00, 03/05, page 823 of 884
Tp CKIO
Tpw
Tr
Trw
Tc
Address upper bits Address lower bits
BS
CSn tRWD RD/WR
RD tDQMD WEn ⋅ DQMxx
D31–D0
DACKn
WAIT tRASD1 RAS CAS ⋅ OE tRASD1
CKE
Note: DACKn waveform when active-high is specified
Figure 21.30 Synchronous DRAM Write Bus Cycle (Bank Active, Different Row Access, TRP = 2 Cycles, RCD = 2 Cycles)
Rev. 2.00, 03/05, page 824 of 884
Trr
Trc1
Trc2
Tre
CKIO
Address upper bits
tAD
Address lower bits
tAD
tBSD
BS
tCSD1
CSn
tCSD1
tRWD
RD/WR
tRWD
RD WEn ⋅ DQMxx
D31–D0
DACKn
WAIT
tRASD1
RAS
tRASD1
tRSD1
tCASD1
CAS ⋅ OE CKE
tCASD1
Note: An auto-refresh cycle is always preceded by a precharge cycle. The number of cycles between the two is determined by the number of cycles specified by TRP.
Figure 21.31 Synchronous DRAM Auto-Refresh Cycle (TRAS = 4 Cycles)
Rev. 2.00, 03/05, page 825 of 884
Tp CKIO Address upper bits tAD Address lower bits tBSD BS tCSD1 CSn tRWD RD/WR tRWD tAD
Trr
Trc1
Trc2
Tre
RD WEn ⋅ DQMxx
D31–D0
DACKn
WAIT tRASD1 RAS tCASD1 CAS ⋅ OE CKE
Figure 21.32 Synchronous DRAM Auto-Refresh Cycle (Shown from Precharge Cycle, TRP = 1 Cycle, TRAS = 4 Cycles)
Rev. 2.00, 03/05, page 826 of 884
Trr CKIO Address upper bits Address lower bits BS
Trc1
Trc2
Tre
Trc1
Tre
tAD
tAD
tCSD1 CSn tRWD RD/WR
tCSD1
RD WEn ⋅ DQMxx D31–D0 DACKn
WAIT tRASD1 RAS CAS ⋅ OE CKE tCASD1 tCASD1 tCKED tRASD1 tRASD1
tCKED
Note: A self-refresh cycle is always preceded by a precharge cycle. The number of cycles between the two is determined by the number of cycles specified by TRP.
Figure 21.33 Synchronous DRAM Self-Refresh Cycle (TRAS = 3)
Rev. 2.00, 03/05, page 827 of 884
Tp CKIO tAD Address upper bits
Tr
Tc1
Tc2
tAD
tASR Address lower bits tBSD BS tCSD2 CSn tRWD RD/WR tRSD1 RD tCASD2 CASxx
tAD
tCSD1
tRWD
tRSD1
tRSD1
tCASD2 tASC tRDS1
tCASD2 tRDH5
D31–D0 tDACD1 DACKn tDACD2
WAIT tRASD2 RAS CAS ⋅ OE CKE tRASD2 tRASD2
Notes: 1. tRDH5 is measured from the rise of RD or CASxx, whichever comes first. 2. DACKn waveform when active-high is specified
Figure 21.34 DRAM Read Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait)
Rev. 2.00, 03/05, page 828 of 884
Tp CKIO tAD Address upper bits
Tr
Tc1
Tc2
tAD
tASR Address lower bits tBSD BS tCSD2 CSn tRWD RD/WR tRSD1 RD tCASD2 CASxx
tAD
tCSD1
tRWD
tASC tCASD2 tWDD1 tDON tDS tCASD2 tDOF tWDH1
D31–D0 tDACD1 DACKn tDACD2
WAIT tRASD2 RAS CAS ⋅ OE CKE tRASD2 tRASD2
Note: DACKn waveform when active-high is specified
Figure 21.35 DRAM Write Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait)
Rev. 2.00, 03/05, page 829 of 884
Tp CKIO
Tpw
Tr
Trw
Tc1
Tw
Tc2
Address upper bits Address lower bits
BS
CSn
RD/WR
RD
CASxx
D31–D0
DACKn
tWTS tWTH
WAIT
RAS
CAS OE CKE
⋅
Note: DACKn waveform when active-high is specified
Figure 21.36 DRAM Bus Cycle (TRP = 2 Cycles, RCD = 2 Cycles, 1 Wait)
Rev. 2.00, 03/05, page 830 of 884
Tp CKIO Address upper bits Address lower bits
Tr
Tc1
Tw
Twx
Tc2
BS
CSn
RD/WR
RD
CASxx
D31–D0
DACKn tWTS tWTH WAIT tWTS tWTH
RAS CAS ⋅ OE
CKE
Note: DACKn waveform when active-high is specified
Figure 21.37 DRAM Bus Cycle (TRP = 1 Cycle, RCD = 1 Cycle, External Wait Input)
Rev. 2.00, 03/05, page 831 of 884
Tp CKIO Address upper bits
Tr
Tc1
Tc2
Tc1
Tc2
tAD Address lower bits
tAD
BS
CSn RD/WR tRSD1 RD tCASD2 CASxx tASC tRDS1 D31–D0 tDACD2 tDACD1 DACKn tRDH5 tASC tRDS1 tRDH5 tCASD2 tRSD1
WAIT
RAS CAS ⋅ OE CKE
Notes: 1. tRDH5 is measured from the rise of RD or CASxx, whichever comes first. 2. DACKn waveform when active-high is specified
Figure 21.38 DRAM Burst Read Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait)
Rev. 2.00, 03/05, page 832 of 884
Tp CKIO Address upper bits
Tr
Tc1
Tc2
Tc1
Tc2
tAD Address lower bits
BS
CSn
RD/WR
RD tCASD2 CASxx tWDD1 tDS D31–D0 tDACD2 DACKn tWDH1
tASC tCASD2
tDS
tDACD1
WAIT
RAS CAS ⋅ OE CKE
Note: DACKn waveform when active-high is specified
Figure 21.39 DRAM Burst Write Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait)
Rev. 2.00, 03/05, page 833 of 884
Tp CKIO
Tr
Tc1
Tc2
tAD
Address upper bits
tAD
tASR
Address lower bits tBSD BS
tAD
tCSD2
CSn
tCSD1
tRWD
RD/WR
tRWD
tRSD1
RD
tRSD1
tRSD1
tCASD2
CASxx
tCASD2
tCASD2
tASC
D31–D0
tRDS2 tRDH6
tDACD1
DACKn
tDACD2
tRDH7*
WAIT
tRASD2
RAS CAS ⋅ OE CKE
tRASD2
tRASD3
tOED1
tOED1
tOED2
Notes: DACKn waveform when active-high is specified * tRDH7 is measured from the rise of RAS or CAS · OE, whichever comes first.
Figure 21.40 EDO Read Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait)
Rev. 2.00, 03/05, page 834 of 884
Tp CKIO Address upper bits
Tr
Tc1
Tc2
Tc1
Tc2
tAD Address lower bits
BS
CSn
RD/WR tRSD1 RD tCASD2 CASxx tASC tRDS2 D31–D0 tDACD2 tDACD1 DACKn tRDH6 tRDS2 tRDH6 tCASD2 tRSD1
WAIT
RAS CAS ⋅ OE CKE
Note: DACKn waveform when active-high is specified
Figure 21.41 EDO Burst Read Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait)
Rev. 2.00, 03/05, page 835 of 884
Tp CKIO
Trr
Trc1
Trc2
Tre
Address upper bits Address lower bits
BS tCSD1 CSn tCSD1
RD/WR
RD tCASD2 CASxx tCASD2 tCASD2
D31–D0
DACKn
WAIT tRASD2 RAS CAS ⋅ OE CKE tRASD2 tRASD2
Figure 21.42 DRAM -BeforeRefresh Cycle (TRP = 1 Cycle, TRAS = 2 Cycles)
Rev. 2.00, 03/05, page 836 of 884
SAR
SAC
T1 CKIO tAD A24–A0 tBSD BS tCSD1 CSn tRWD RD/WR tRSD1 RD tCASD1 CASxx tBSD
TW
T2
TW
T2
tAD
tAD
tBSD
tBSD
tCSD2
tRWD
tRSD1
tRSD1
tRSD1
tCASD1 tRDH2 tRDS1 tRDS1 tRDH2
D31–D0 tDACD1 DACKn tWTS tWTH WAIT tWTS tWTH tDACD2 tDACD1 tDACD2
RAS CAS ⋅ OE
CKE
Note: DACKn waveform when active-high is specified
Figure 21.43 Burst ROM Read Cycle (Wait = 1)
Rev. 2.00, 03/05, page 837 of 884
T1 CKIO tAD A3–A0
T2
T3
T4
tAD
tBSD BS tIVD IVECF tRWD RD/WR
tBSD
tIVD
tRWD
tRSD1 RD
tRSD1
tRDH8 tRDS1
D7–D0 tWTS WAIT tWTH
Figure 21.44 Interrupt Vector Fetch Cycle (No Wait, Iφ:Eφ = 1:1)
Rev. 2.00, 03/05, page 838 of 884
T1 CKIO tAD A3–A0
T2
tAD
tBSD BS tIVD IVECF tRWD RD/WR tRSD1
tBSD
tIVD
tRSD1
RD tRDS1 tRDH8 D7–D0 tWTS WAIT tWTH
Figure 21.45 Interrupt Vector Fetch Cycle (No Wait, Except tEcyc:tPcyc 1:1)
Rev. 2.00, 03/05, page 839 of 884
T1 CKIO
TW
T2
A3–A0
BS
IVECF
RD/WR
RD
D7–D0 tWTS WAIT tWTH tWTS tWTH
Figure 21.46 Interrupt Vector Fetch Cycle (External Wait Input, Except tEcyc:tPcyc 1:1)
CKIO
tREFOD
REFOUT
Figure 21.47 REFOUT Delay Time
Rev. 2.00, 03/05, page 840 of 884
21.3.4
Direct Memory Access Controller Timing
Table 21.8 Direct Memory Access Controller Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item DREQ0, DREQ1 setup time DREQ0, DREQ1 hold time Symbol tDRQS tDRQH Min 10 5 Max — — Unit ns ns Figure 21.48
CKIO
tDRQS
DREQ0, DREQ1
tDRQH
Figure 21.48 DREQ0, DREQ1 Input Timing
Rev. 2.00, 03/05, page 841 of 884
21.3.5
Free-Running Timer Timing
Table 21.9 Free-Running Timer Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item Output compare output delay time Input capture input setup time (tEcyc:tPcyc = 1:1) Input capture input setup time (tEcyc:tPcyc = 1:2) Input capture input setup time (tEcyc:tPcyc = 1:4) Input capture input hold time Timer clock input setup time (tEcyc:tPcyc = 1:1) Timer clock input setup time (tEcyc:tPcyc = 1:2) Timer clock input setup time (tEcyc:tPcyc = 1:4) Timer clock pulse width (single edge specified) Timer clock pulse width (both edges specified) Symbol tFOCD tFICS tFICS tFICS tFICH tFCKS tFCKS tFCKS tFCKWH tFCKWL Min — 50 tcyc + 50 3tcyc + 50 50 50 tcyc + 50 3tcyc + 50 4.5 8.5 Max 100 — — — — — — — — — Unit ns ns ns ns ns ns ns ns tPcyc tPcyc Figure 21.49, 21.50 21.49 21.50 21.50 21.49, 21.50 21.51 21.52 21.52 21.51, 21.52
CKIO tFOCD FTOA, FTOB tFICS FTI tFICH
Figure 21.49 FRT Input/Output Timing (tEcyc:tPcyc = 1:1)
Rev. 2.00, 03/05, page 842 of 884
CKIO tFOCD FTOA, FTOB tFICS FTI tFICH
Figure 21.50 FRT Input/Output Timing (Except tEcyc:tPcyc 1:1)
CKIO tFCKS FTCI tFCKWL tFCKWH
Figure 21.51 FRT Clock Input Timing (tEcyc:tPcyc = 1:1)
CKIO tFCKS FTCI tFCKWL tFCKWH
Figure 21.52 FRT Clock Input Timing (Except tEcyc:tPcyc 1:1)
Rev. 2.00, 03/05, page 843 of 884
21.3.6
Serial Communication Interface Timing
Table 21.10 Serial Communication Interface Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item Input clock cycle Input clock cycle (synchronous mode) Input clock pulse width Transmit data delay time (synchronous mode) Receive data setup time (synchronous mode) Receive data hold time (synchronous mode) delay time setup time (synchronous mode) hold time (synchronous mode) Symbol tscyc tscyc tSCKW tTXD tRXS tRXH tRTSD tCTSS tCTSH Min 4 6 0.4 — 100 100 — 100 100 Max — — 0.6 100 — — 100 — — Unit tPcyc tPcyc tscyc ns ns ns ns ns ns 21.55 Figure 21.53 21.54 21.53 21.54
Rev. 2.00, 03/05, page 844 of 884
STC STC STR
tSCKW SCK SCK1 SCK2
tscyc
Figure 21.53 Input Clock Input/Output Timing
tscyc SCK tTXD TxD (transmit data) tRXS RxD (receive data) tRXH
Figure 21.54 SCI Input/Output Timing (Synchronous Mode)
tscyc SCK1 tRTSD RTS tCTSS CTS tCTSH
Table 21.11 16-Bit Timer-Pulse Unit Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item Timer output delay time Timer input setup time (tEcyc:tPcyc = 1:1) Timer input setup time (tEcyc:tPcyc = 1:2) Timer input setup time (tEcyc:tPcyc = 1:4) Timer clock input setup time (tEcyc:tPcyc = 1:1) Timer clock input setup time (tEcyc:tPcyc = 1:2) Timer clock input setup time (tEcyc:tPcyc = 1:4) Timer clock pulse width Single edge specified Both edges specified Symbol tTOCD tTICS tTICS tTICS tTCKS tTCKS tTCKS tTCKWH tTCKWL Min — 50 tcyc + 50 3tcyc + 50 50 tcyc + 50 3tcyc + 50 1.5 2.5 Max 100 — — — — — — — — Unit ns ns ns ns ns ns ns tcyc 21.58 21.56, 21.57 Figure 21.56, 21.57
STC
STR
Figure 21.55
and
Input/Output Timing
Rev. 2.00, 03/05, page 845 of 884
CKIO tTOCD Output compare output*
tTICS
Input capture input* Note: * TIOCA0–TIOCA2, TIOCB0–TIOCB2, TIOCC0, TIOCD0
Figure 21.56 TPU Input/Output Timing (tEcyc:tPcyc = 1:1)
CKIO tTOCD Output compare output*
tTICS
Input capture input* Note: * TIOCA0–TIOCA2, TIOCB0–TIOCB2, TIOCC0, TIOCD0
Figure 21.57 TPU Input/Output Timing (Except tEcyc:tPcyc 1:1)
CKIO tTCKS TCLKA–TCLKD tTCKWL tTCKWH tTCKS
Figure 21.58 TPU Clock Input Timing
Rev. 2.00, 03/05, page 846 of 884
21.3.7
Watchdog Timer Timing
Table 21.12 Watchdog Timer Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item delay time Symbol tWOVD Min — Max 70 Unit ns Figure 21.59, 21.60
FVOTDW
CKIO
tWOVD
tWOVD
WDTOVF
Figure 21.59 Watchdog Timer Output Timing (tEcyc:tPcyc = 1:1)
CKIO tWOVD WDTOVF tWOVD
Figure 21.60 Watchdog Timer Output Timing (Except tEcyc:tPcyc 1:1)
Rev. 2.00, 03/05, page 847 of 884
21.3.8
Serial I/O Timing
Table 21.13 Serial I/O Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item SRCK, STCK clock input cycle time SRCK, STCK clock input low-level width SRCK, STCK clock input high-level width SRS input setup time SRS input hold time SRXD input setup time SRXD input hold time STS input setup time STS input hold time STS output delay time STXD output delay time Note: * Symbol tsIcyc tWL tWH tRSS tRSH tSRDS tSRDH tTSS tTSH tTSD tTDD Min tPcyc or* 66.7 0.4 × tsIcyc 0.4 × tsIcyc 15 10 15 10 15 10 0 0 Max — — — — — — — — — 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns 21.64 21.63, 21.64 21.63 21.62 Figure 21.61
Specified as tPcyc or 66.7, whichever is greater.
tsIcyc tWL STCKn, SRCKn tWH n = 0, 1, or 2
Figure 21.61 SIO Input Clock Timing
Rev. 2.00, 03/05, page 848 of 884
SRCKn (input) tRSS SRSn (input) SRXDn (input) n = 0, 1, or 2 tRSH tSRDS tSRDH
Figure 21.62 SIO Receive Timing
STCKn (input) tTSS STSn (input) tTDD STXDn (output) n = 0, 1, or 2 tTDD tTSH
Figure 21.63 SIO Transmit Timing (TMn = 0 Mode)
STCKn (input) tTSD STSn (output) tTDD STXDn (output) n = 0, 1, or 2 tTDD tTSD
Figure 21.64 SIO Transmit Timing (TMn = 1 Mode)
Rev. 2.00, 03/05, page 849 of 884
21.3.9
High-Performance User Debugging Interface Timing
Table 21.14 High-Performance User Debugging Interface Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item TCK clock input cycle time TCK clock input high-level width TCK clock input low-level width pulse width setup time Symbol ttcyc tTCKH tTCKL tTRSW tTRSS tTMSS tTMSH tTDIS tTDIH tTDOD Min tPcyc or* 66.7 ns 0.4 0.4 20 40 30 10 30 10 0 Max — 0.6 0.6 — — — — — — 30 Unit ns ttcyc ttcyc ttcyc ns ns ns ns ns ns 21.67 21.66 Figure 21.65
Note:
Rev. 2.00, 03/05, page 850 of 884
TSRT
TSRT TSRT
TMS setup time TMS hold time TDI setup time TDI hold time TDO delay time *
Specified as tPcyc or 66.7, whichever is greater.
ttcyc tTCKH TCK tTCKL
Figure 21.65 H-UDI Clock Timing
TCK
tTRSS TRST tTRSW
tTRSS
Figure 21.66 H-UDI
Timing
TCK tTMSS TMS tTDIS TDI tTDOD TDO tTDOD tTDIH tTMSH
Figure 21.67 H-UDI Input/Output Timing 21.3.10 I/O Port Timing Table 21.15 I/O Port Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item Port output data delay time Port input data setup time (tEcyc:tPcyc = 1:1) Port input data setup time (tEcyc:tPcyc = 1:2) Port input data setup time (tEcyc:tPcyc = 1:4) Port input data hold time Symbol tPWD tPRS tPRS tPRS tPRH Min — 50 tcyc + 50 3tcyc + 50 50 Max 50 — — — — Unit ns ns ns ns ns 21.68, 21.69 Figure 21.68, 21.69 21.68 21.69
Rev. 2.00, 03/05, page 851 of 884
CKIO tPRS PA0–PA13 PB0–PB15 (read) PA0–PA13 PB0–PB15 (write) tPRH
tPWD
Figure 21.68 I/O Port Input/Output Timing (tEcyc:tPcyc = 1:1)
CKIO tPRS PA0–PA13 PB0–PB15 (read) PA0–PA13 PB0–PB15 (write) tPRH
tPWD
Figure 21.69 I/O Port Input/Output Timing (Except tEcyc:tPcyc 1:1)
Rev. 2.00, 03/05, page 852 of 884
21.3.11 Ethernet Controller Timing Table 21.16 Ethernet Controller Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item TX-CLK cycle time TX-EN output delay time ETXD[3:0] output delay time CRS setup time CRS hold time COL setup time COL hold time RX-CLK cycle time RX-DV setup time RX-DV hold time ERXD[3:0] setup time ERXD[3:0] hold time RX-ER setup time RX-ER hold time MDIO setup time MDIO hold time MDIO output data hold time* WOL output delay time EXOUT output delay time Note: * Symbol tTcyc tTENd tETDd tCRSs tCRSh tCOLs tCOLh tRcyc tRDVs tRDVh tERDs tERDh tRERs tRERh tMDIOs tMDIOh tMDIOdh tWOLd tEXOUTd Min 40 3 3 10 10 10 10 40 10 3 10 3 10 3 10 10 5 1 1 Typ — — — — — — — — — — — — — — — — — — — Max — 20 20 — — — — — — — — — — — — — 18 14 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 21.75 21.76 21.77 21.74 21.73 21.72 21.71 Figure 21.70
The user must ensure that the code satisfies this condition.
Rev. 2.00, 03/05, page 853 of 884
TX-CLK tTENd TX-EN tETDd ETXD[3:0] Preamble SFD DATA CRC
TX-ER tCRSs CRS tCRSh
COL
Figure 21.70 MII Transmit Timing (Normal Operation)
TX-CLK
TX-EN
ETXD[3:0]
Preamble
JAM
TX-ER
CRS tCOLs COL tCOLh
Figure 21.71 MII Transmit Timing (Case of Conflict)
RX-CLK tRDVs RX-DV tERDh tERDs ERXD[3:0] Preamble SFD DATA CRC tRDVh
RX-ER
Figure 21.72 MII Receive Timing (Normal Operation)
Rev. 2.00, 03/05, page 854 of 884
RX-CLK
RX-DV Preamble SFD DATA tRERs RX-ER tRERh XXXX
ERXD[3:0]
Figure 21.73 MII Receive Timing (Case of Error)
MDC tMDIOs MDIO tMDIOh
Figure 21.74 MDIO Input Timing
MDC tMDIOdh MDIO
Figure 21.75 MDIO Output Timing
RX-CLK tWOLd WOL
Figure 21.76 WOL Output Timing
CKIO tEXOUTd EXOUT
Figure 21.77 EXOUT Output Timing
Rev. 2.00, 03/05, page 855 of 884
Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C
Item Symbol Min — — — 7 8 — Typ — — — — — — Max 16 16 16 — — 16 Unit ns ns ns ns ns ns 21.80 Figure 21.78 21.79
STATS1 and STATS0 output delay time tSTATd output rising edge delay time output falling edge delay time setup time hold time tBHNrd tBHNfd tBHIZs tBHIZh tBHIZd
Output delay time of target pins
CKIO
Address
CPU
CPU
E-DMAC E-DMAC E-DMAC
CSn tSTATd STATS1, 0
Figure 21.78 STATS Output Timing
CKIO Read 0 Address CPU DMAC tBHNfd BH Read 1 DMAC Read 2 DMAC tBHNrd Read 3 DMAC Write 0 DMAC Write 1 DMAC Write 2 DMAC Write 3 DMAC CPU
Rev. 2.00, 03/05, page 856 of 884
HB
Figure 21.79
ZiHSUB
HB
Table 21.17 STATS,
, and
ZiHSUB
HB
21.3.12 STATS,
, and
Signal Timing Signal Timing
ZiHSUB ZiHSUB HB HB
E-DMAC
DMAC
DMAC
DMAC
DMAC
Output Timing
CKIO
WAIT tBHIZs BUSHiZ tBHIZd Target Pins tBHIZh
ZiHSUB
Figure 21.80
Bus Timing
Rev. 2.00, 03/05, page 857 of 884
21.4
AC Characteristic Test Conditions
The AC characteristic test conditions are as follows: • Input/output signal reference level: 1.5 V (VCC = 3.3 to 3.6 V) • Input pulse level: VSS to 3.0 V (VSS to VCC for , , EXTAL, CKIO, MD0 to MD4, and NMI) • Input rise/fall time: 1 ns The output load circuit is shown in figure 21.80.
IOL
SH7615 output pin CL V
IOH CL is the total value, including the capacitance of the test jig, etc. The capacitance of each pin is as follows: 30 pF: CKIO, A24–A0, D31–D0, BS, RD, CS4–CS0, DQMUU/WE3–DQMLL/WE0, CAS3–CAS0, RAS, CAS/OE, DACK1, DACK0 50 pF: All other pins IOL and IOH values are as shown in table 21.3, Permissible Output Currents.
Figure 21.81 Output Load Circuit
Rev. 2.00, 03/05, page 858 of 884
TSRT SER
DUT output VREF
Appendix A On-Chip Peripheral Module Registers
A.1 Addresses
On-chip peripheral module register addresses and bit names are shown in the following table. 16bit registers and 32-bit registers are shown, respectively, in two and four lines of 8 bits.
Register Address H'FFFFFC00 H'FFFFFC01 H'FFFFFC02 H'FFFFFC03 H'FFFFFC04 H'FFFFFC05 H'FFFFFC06 H'FFFFFC07 H'FFFFFC08 to H'FFFFFC0F H'FFFFFC10 H'FFFFFC11 H'FFFFFC12 H'FFFFFC13 H'FFFFFC14 H'FFFFFC15 H'FFFFFC16 H'FFFFFC17 H'FFFFFC18 to H'FFFFFC1F H'FFFFFC20 H'FFFFFC21 H'FFFFFC22 H'FFFFFC23 H'FFFFFC24 H'FFFFFC25 H'FFFFFC26 H'FFFFFC27 SISTR2 SICTR2 — — — — — TM — — — SE — — — DL — — — TIE — TERR — RIE — RERR — TE — TDRE — RE — RDRF SITDR2 — SISTR1 SICTR1 — — — — — — TM — — — — SE — — — — DL — — — — TIE — TERR — — RIE — RERR — — TE — TDRE — — RE — RDRF — — SITDR1 — SISTR0 SICTR0 — — — — — — TM — — — — SE — — — — DL — — — — TIE — TERR — — RIE — RERR — — TE — TDRE — — RE — RDRF — — SITDR0 Name SIRDR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit Names Bit 3 Bit 2 Bit 1 Bit 0 Module SIO0
SIRDR1
SIO1
SIRDR2
SIO2
Rev. 2.00, 03/05, page 859 of 884
Register Address H'FFFFFC28 to H'FFFFFC3F H'FFFFFC40 H'FFFFFC41 H'FFFFFC42 to H'FFFFFC4F H'FFFFFC50 H'FFFFFC51 H'FFFFFC52 H'FFFFFC53 H'FFFFFC54 H'FFFFFC55 H'FFFFFC56 H'FFFFFC57 H'FFFFFC58 H'FFFFFC59 H'FFFFFC5A H'FFFFFC5B H'FFFFFC5C H'FFFFFC5D H'FFFFFC5E H'FFFFFC5F H'FFFFFC60 H'FFFFFC61 H'FFFFFC62 H'FFFFFC63 H'FFFFFC64 H'FFFFFC65 H'FFFFFC66 H'FFFFFC67 H'FFFFFC68 H'FFFFFC69 H'FFFFFC6A H'FFFFFC6B H'FFFFFC6C to H'FFFFFC6F — — — — — TGR1B TGR1A TCR1 TMDR1 TIOR1 — TIER1 TSR1 TCNT1 — — IOB3 — — TCFD CCLR1 — IOB2 — — — CCLR0 — IOB1 — TCIEU TCFU TGR0D TGR0C TGR0B TGR0A Name — Bit 7 — Bit 6 — Bit 5 — Bit 4 —
Bit Names Bit 3 — Bit 2 — Bit 1 — Bit 0 — Module —
TSTR TSYR —
— — —
— — —
— — —
— — —
— — —
CST2 SYNC2 —
CST1 SYNC1 —
CST0 SYNC0 —
TPU
—
TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TCNT0
CCLR2 — IOB3 IOD3 — —
CCLR1 — IOB2 IOD2 — —
CCLR0 BFB IOB1 IOD1 — —
CKEG1 BFA IOB0 IOD0 TCIEV TCFV
CKEG0 MD3 IOA3 IOC3 TGIED TGFD
TPSC2 MD2 IOA2 IOC2 TGIEC TGFC
TPSC1 MD1 IOA1 IOC1 TGIEB TGFB
TPSC0 MD0 IOA0 IOC0 TGIEA TGFA
TPU
CKEG1 — IOB0 — TCIEV TCFV
CKEG0 MD3 IOA3 — — —
TPSC2 MD2 IOA2 — — —
TPSC1 MD1 IOA1 — TGIEB TGFB
TPSC0 MD0 IOA0 — TGIEA TGFA
—
—
—
—
—
Rev. 2.00, 03/05, page 860 of 884
Register Address H'FFFFFC70 H'FFFFFC71 H'FFFFFC72 H'FFFFFC73 H'FFFFFC74 H'FFFFFC75 H'FFFFFC76 H'FFFFFC77 H'FFFFFC78 H'FFFFFC79 H'FFFFFC7A H'FFFFFC7B H'FFFFFC7C to H'FFFFFC7F H'FFFFFC80 H'FFFFFC81 H'FFFFFC82 H'FFFFFC83 H'FFFFFC84 H'FFFFFC85 H'FFFFFC86 to H'FFFFFC87 H'FFFFFC88 H'FFFFFC89 H'FFFFFC8A H'FFFFFC8B H'FFFFFC8C H'FFFFFC8D H'FFFFFC8E H'FFFFFC8F H'FFFFFC90 to H'FFFFFCAF H'FFFFFCB0 H'FFFFFCB1 H'FFFFFCB2 H'FFFFFCB3 SDSR — PBCR2 PBDR PBIOR — PADR PAIOR — — — — — TGR2B TGR2A Name TCR2 TMDR2 TIOR2 — TIER2 TSR2 TCNT2 Bit 7 — — IOB3 — — TCFD Bit 6 CCLR1 — IOB2 — — — Bit 5 CCLR0 — IOB1 — TCIEU TCFU Bit 4
Bit Names Bit 3 CKEG0 MD3 IOA3 — — — Bit 2 TPSC2 MD2 IOA2 — — — Bit 1 TPSC1 MD1 IOA1 — TGIEB TGFB Bit 0 TPSC0 MD0 IOA0 — TGIEA TGFA Module TPU
CKEG1 — IOB0 — TCIEV TCFV
—
—
—
—
—
PACR
— PA7MD — PA7IOR — PA7DR —
— PA6MD — PA6IOR — PA6DR —
PA13MD PA12MD PA11MD PA10MD PA9MD PA5MD PA4MD PA3MD PA2MD PA1MD
PA8MD PA0MD PA8IOR PA0IOR PA8DR PA0DR —
PFC
PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR PA5IOR PA4IOR — PA2IOR PA1IOR
PA13DR PA12DR PA11DR PA10DR PA9DR PA5DR — PA4DR — — — PA2DR — PA1DR —
I/O port
—
PBCR
PB15MD1 PB15MD0 PB14MD1 PB14MD0 PB13MD1 PB13MD0 PB12MD1 PB12MD0 PFC PB11MD1 PB11MD0 PB10MD1 PB10MD0 PB9MD1 PB9MD0 PB8MD1 PB8MD0 PB15IOR PB14IOR PB13IOR PB12IOR PB11IOR PB10IOR PB9IOR PB7IOR PB6IOR PB5IOR PB4IOR PB3IOR PB2IOR PB1IOR PB8IOR PB0IOR PB8DR PB0DR I/O port
PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR
PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 PFC PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 — — — — — — — — —
SDIR
TS3 — — —
TS2 — — —
TS1 — — —
TS0 — — —
— — — —
— — — —
— — — —
— — — SDTRF
H-UDI
Rev. 2.00, 03/05, page 861 of 884
Register Address H'FFFFFCB4 H'FFFFFCB5 H'FFFFFCB6 H'FFFFFCB7 H'FFFFFCB8 to H'FFFFFCBF H'FFFFFCC0 H'FFFFFCC1 H'FFFFFCC2 H'FFFFFCC3 H'FFFFFCC4 H'FFFFFCC5 H'FFFFFCC6 H'FFFFFCC7 H'FFFFFCC8 H'FFFFFCC9 H'FFFFFCCA H'FFFFFCCB — — — — — SDDRL Name SDDRH Bit 7 Bit 6 Bit 5
Bit Names Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H-UDI
—
—
—
—
—
— SCBRR1 — SCSCR1 — SCFTDR1 —
—
—
—
—
— TIE —
— RIE —
— TE —
— RE —
—
— PER2 TEND RLM —
— PER1 TDFE N1 —
— PER0 BRK N0 —
SC1SSR1 PER3 ER SC2SSR1 TLM — —
H'FFFFFCCC SCFRDR1 H'FFFFFCCD — H'FFFFFCCE H'FFFFFCCF H'FFFFFCD0 H'FFFFFCD1 H'FFFFFCD2 H'FFFFFCD3 H'FFFFFCD4 H'FFFFFCD5 to H'FFFFFCDF SCIMR1 — SCFER1 SCFCR1 — SCFDR1 — RTRG1 — — — ED15 ED7 IRMOD — — RTRG0 — — — ED14 ED6 PSEL — — TTRG1 — — — ED13 ED5 RIVS — — TTRG0 — T4 R4 ED12 ED4 — — — MCE — T3 R3 ED11 ED3 — — — TFRST — T2 R2 ED10 ED2 — — — RFRST — T1 R1 ED9 ED1 — — — LOOP — T0 R0 ED8 ED0 — — —
H'FFFFFCE1 H'FFFFFCE2 H'FFFFFCE3
— SCBRR2 —
—
—
—
—
—
—
—
—
Rev. 2.00, 03/05, page 862 of 884
E
A
H'FFFFFCE0
SCSMR2
C/
CHR/ICK3 PE/ICK2 O/ /ICK1 STOP/ ICK0 —
E
A
SCSMR1
C/
CHR/ICK3 PE/ICK2 O/ /ICK1 STOP/ ICK0 —
MP —
CKS1 —
CKS0 —
SCIF1
— MPIE —
— — —
— CKE1 —
— CKE0 —
— FER3 FER MPB —
— FER2 PER MPBT —
— FER1 RDF EI —
— FER0 DR ORER —
MP
CKS1
CKS0
SCIF2
—
—
—
—
—
—
—
Register Address H'FFFFFCE4 H'FFFFFCE5 H'FFFFFCE6 H'FFFFFCE7 H'FFFFFCE8 H'FFFFFCE9 H'FFFFFCEA H'FFFFFCEB Name SCSCR2 — SCFTDR2 — — — PER2 TEND RLM — — PER1 TDFE N1 — — Bit 7 TIE — Bit 6 RIE — Bit 5 TE — Bit 4 RE —
Bit Names Bit 3 MPIE — Bit 2 — — Bit 1 CKE1 — Bit 0 CKE0 — Module SCIF2
— FER3 FER MPB —
— FER2 PER MPBT —
— FER1 RDF EI —
— FER0 DR ORER —
SC1SSR2 PER3 ER SC2SSR2 TLM — —
PER0 BRK N0 —
H'FFFFFCEC SCFRDR2 H'FFFFFCED — H'FFFFFCEE H'FFFFFCEF H'FFFFFCF0 H'FFFFFCF1 H'FFFFFCF2 H'FFFFFCF3 H'FFFFFCF4 H'FFFFFCF5 to H'FFFFFCFF H'FFFFFD00 H'FFFFFD01 H'FFFFFD02 H'FFFFFD03 H'FFFFFD04 H'FFFFFD05 H'FFFFFD06 H'FFFFFD07 H'FFFFFD08 H'FFFFFD09 H'FFFFFD0A H'FFFFFD0B EDRRR EDTRR EDMR — — — — — — — — — — — — — — — — — — — — — — — — — — — DL1 — — — — — — — — — — — DL0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SWR — — — TR — — — RR E-DMAC SCIMR2 — SCFER2 SCFCR2 — SCFDR2 — RTRG1 — — — ED15 ED7 IRMOD — — RTRG0 — — — ED14 ED6 PSEL — — TTRG1 — — — ED13 ED5 RIVS — — TTRG0 — T4 R4 ED12 ED4 — — — MCE — T3 R3 ED11 ED3 — — — TFRST — T2 R2 ED10 ED2 — — — RFRST — T1 R1 ED9 ED1 — — — LOOP — T0 R0 ED8 ED0 — — —
Rev. 2.00, 03/05, page 863 of 884
Register Address H'FFFFFD0C H'FFFFFD0D H'FFFFFD0E H'FFFFFD0F H'FFFFFD10 H'FFFFFD11 H'FFFFFD12 H'FFFFFD13 H'FFFFFD14 H'FFFFFD15 H'FFFFFD16 H'FFFFFD17 H'FFFFFD18 H'FFFFFD19 H'FFFFFD1A H'FFFFFD1B H'FFFFFD1C H'FFFFFD1D H'FFFFFD1E H'FFFFFD1F H'FFFFFD20 H'FFFFFD21 H'FFFFFD22 H'FFFFFD23 H'FFFFFD24 H'FFFFFD25 H'FFFFFD26 H'FFFFFD27 H'FFFFFD28 H'FFFFFD29 H'FFFFFD2A H'FFFFFD2B FDR TFTR RMFCR TRSCER EESIPR EESR RDLAR Name TDLAR Bit 7 TDLA31 TDLA23 TDLA15 TDLA7 RDLA31 RDLA23 RDLA15 RDLA7 — — — RMAF — — — RMAFIP — — — Bit 6 TDLA30 TDLA22 TDLA14 TDLA6 RDLA30 RDLA22 RDLA14 RDLA6 — ECI — — — ECIIP — — — — — Bit 5 TDLA29 TDLA21 TDLA13 TDLA5 RDLA29 RDLA21 RDLA13 RDLA5 — TC — — — TCIP — — — — — — — — MFC13 MFC5 — — — TFT5 — — — — Bit 4
Bit Names Bit 3 TDLA27 TDLA19 TDLA11 TDLA3 RDLA27 RDLA19 RDLA11 RDLA3 — TFUF CND RTLF — TFUFIP CNDIP RTLFIP — — — — — — MFC11 MFC3 — — — TFT3 — — — — Bit 2 TDLA26 TDLA18 TDLA10 TDLA2 RDLA26 RDLA18 RDLA10 RDLA2 TABT FR DLC RTSF — FRIP DLCIP RTSFIP — — — — — — MFC10 MFC2 — — TFT10 TFT2 — — — — Bit 1 TDLA25 TDLA17 TDLA9 TDLA1 RDLA25 RDLA17 RDLA9 RDLA1 RABT RDE CD PRE — RDEIP CDIP PREIP — — — — — — MFC9 MFC1 — — TFT9 TFT1 — — — — Bit 0 TDLA24 TDLA16 TDLA8 TDLA0 RDLA24 RDLA16 RDLA8 RDLA0 RFCOF RFOF TRO CERF RFCOFIP RFOFIP TROIP CERFIP — — — — — — MFC8 MFC0 — — TFT8 TFT0 — — TFD RFD Module E-DMAC
TDLA28 TDLA20 TDLA12 TDLA4 RDLA28 RDLA20 RDLA12 RDLA4 — TDE ITF RRF — TDEIP ITFIP RRFIP — — — — — — MFC12 MFC4 — — — TFT4 — — — —
RMAFCE — — — MFC15 MFC7 — — — TFT7 — — — — — — MFC14 MFC6 — — — TFT6 — — — —
Rev. 2.00, 03/05, page 864 of 884
Register Address H'FFFFFD2C H'FFFFFD2D H'FFFFFD2E H'FFFFFD2F H'FFFFFD30 H'FFFFFD31 H'FFFFFD32 H'FFFFFD33 H'FFFFFD34 to H'FFFFFD3F H'FFFFFD40 H'FFFFFD41 H'FFFFFD42 H'FFFFFD43 H'FFFFFD44 H'FFFFFD45 H'FFFFFD46 H'FFFFFD47 H'FFFFFD48 to H'FFFFFD4B H'FFFFFD4C H'FFFFFD4D H'FFFFFD4E H'FFFFFD4F H'FFFFFD50 H'FFFFFD51 H'FFFFFD52 H'FFFFFD53 H'FFFFFD54 to H'FFFFFD5F — TDFAR TBRAR TBRA31 TBRA23 TBRA15 TBRA7 TDFA31 TDFA23 TDFA15 TDFA7 — TBRA30 TBRA22 TBRA14 TBRA6 TDFA30 TDFA22 TDFA14 TDFA6 — TBRA29 TBRA21 TBRA13 TBRA5 TDFA29 TDFA21 TDFA13 TDFA5 — — RDFAR RBWAR — EDOCR Name RCR Bit 7 — — — — — — — — — Bit 6 — — — — — — — — — Bit 5 — — — — — — — — — Bit 4 — — — — — — — — —
Bit Names Bit 3 — — — — — — — FEC — Bit 2 — — — — — — — AEC — Bit 1 — — — — — — — EDH — Bit 0 — — — RNC — — — — — Module E-DMAC
RBWA31 RBWA30 RBWA29 RBWA28 RBWA27 RBWA26 RBWA23 RBWA22 RBWA21 RBWA20 RBWA19 RBWA18 RBWA15 RBWA14 RBWA13 RBWA12 RBWA11 RBWA10 RBWA7 RBWA6 RBWA5 RBWA4 RBWA3 RBWA2
RBWA25 RBWA24 RBWA17 RBWA16 RBWA9 RBWA1 RBWA8 RBWA0
RDFA31 RDFA30 RDFA29 RDFA28 RDFA27 RDFA26 RDFA23 RDFA22 RDFA21 RDFA20 RDFA19 RDFA18 RDFA15 RDFA14 RDFA13 RDFA12 RDFA11 RDFA10 RDFA7 — RDFA6 — RDFA5 — RDFA4 — RDFA3 — RDFA2 —
RDFA25 RDFA24 RDFA17 RDFA16 RDFA9 RDFA1 — RDFA8 RDFA0 —
TBRA28 TBRA20 TBRA12 TBRA4 TDFA28 TDFA20 TDFA12 TDFA4 —
TBRA27 TBRA19 TBRA11 TBRA3 TDFA27 TDFA19 TDFA11 TDFA3 —
TBRA26 TBRA18 TBRA10 TBRA2 TDFA26 TDFA18 TDFA10 TDFA2 —
TBRA25 TBRA24 TBRA17 TBRA16 TBRA9 TBRA1 TDFA25 TDFA17 TDFA9 TDFA1 — TBRA8 TBRA0 TDFA24 TDFA16 TDFA8 TDFA0 —
Rev. 2.00, 03/05, page 865 of 884
Register Address H'FFFFFD60 H'FFFFFD61 H'FFFFFD62 H'FFFFFD63 H'FFFFFD64 H'FFFFFD65 H'FFFFFD66 H'FFFFFD67 H'FFFFFD68 H'FFFFFD69 H'FFFFFD6A H'FFFFFD6B H'FFFFFD6C H'FFFFFD6D H'FFFFFD6E H'FFFFFD6F H'FFFFFD70 H'FFFFFD71 H'FFFFFD72 H'FFFFFD73 H'FFFFFD74 H'FFFFFD75 H'FFFFFD76 H'FFFFFD77 H'FFFFFD78 H'FFFFFD79 H'FFFFFD7A H'FFFFFD7B H'FFFFFD7C H'FFFFFD7D H'FFFFFD7E H'FFFFFD7F PSR RFLR MALR MAHR PIR ECSIPR ECSR Name ECMR Bit 7 — — — — — — — — — — — — — — — — MA47 MA39 MA31 MA23 — — MA15 MA7 — — — RFL7 — — — — Bit 6 — — — RE — — — — — — — — — — — — MA46 MA38 MA30 MA22 — — MA14 MA6 — — — RFL6 — — — — Bit 5 — — — TE — — — — — — — — — — — — MA45 MA37 MA29 MA21 — — MA13 MA5 — — — RFL5 — — — — Bit 4 — —
Bit Names Bit 3 — — — ILB — — — — — — — — — — — MDI MA43 MA35 MA27 MA19 — — MA11 MA3 — — RFL11 RFL3 — — — — Bit 2 — — — ELB — — — LCHNG — — — Bit 1 — — MPDE DM — — — MPD — — — Bit 0 — — — PRM — — — ICD — — — ICDIP — — — MDC MA40 MA32 MA24 MA16 — — MA8 MA0 — — RFL8 RFL0 — — — LMON Module EtherC
PRCEF — — — — — — — — — — — — — MA44 MA36 MA28 MA20 — — MA12 MA4 — — — RFL4 — — — —
LCHNGIP MPDIP — — — MDO MA42 MA34 MA26 MA18 — — MA10 MA2 — — RFL10 RFL2 — — — — — — — MMD MA41 MA33 MA25 MA17 — — MA9 MA1 — — RFL9 RFL1 — — — —
Rev. 2.00, 03/05, page 866 of 884
Register Address H'FFFFFD80 H'FFFFFD81 H'FFFFFD82 H'FFFFFD83 H'FFFFFD84 H'FFFFFD85 H'FFFFFD86 CDCR Name TROCR Bit 7 — — Bit 6 — — Bit 5 — — Bit 4 — —
Bit Names Bit 3 — — Bit 2 — — Bit 1 — — Bit 0 — — TROC8 TROC0 — — Module EtherC
TROC15 TROC14 TROC13 TROC12 TROC11 TROC10 TROC9 TROC7 — — TROC6 — — TROC5 — — TROC4 — — TROC3 — — TROC2 — — TROC1 — —
COLDC1 COLDC1 COLDC1 COLDC1 COLDC1 COLDC1 COLDC9 COLDC8 5 4 3 2 1 0
H'FFFFFD87 H'FFFFFD88 H'FFFFFD89 H'FFFFFD8A H'FFFFFD8B H'FFFFFD8C H'FFFFFD8D H'FFFFFD8E H'FFFFFD8F H'FFFFFD90 H'FFFFFD91 H'FFFFFD92 H'FFFFFD93 H'FFFFFD94 H'FFFFFD95 H'FFFFFD96 H'FFFFFD97 H'FFFFFD98 H'FFFFFD99 H'FFFFFD9A H'FFFFFD9B H'FFFFFD9C H'FFFFFD9D H'FFFFFD9E H'FFFFFD9F TSFRCR FRECR CEFCR IFLCR CNDCR LCCR
COLDC7 COLDC6 COLDC5 COLDC4 COLDC3 COLDC2 COLDC1 COLDC0 — — LCC15 LCC7 — — — — LCC14 LCC6 — — — — LCC13 LCC5 — — — — LCC12 LCC4 — — — — LCC11 LCC3 — — — — LCC10 LCC2 — — — — LCC9 LCC1 — — — — LCC8 LCC0 — — CNDC8 CNDC0 — — IFLC8 IFLC0 — — CEFC8 CEFC0 — — FREC8 FREC0 — — TSFC8 TSFC0
CNDC15 CNDC14 CNDC13 CNDC12 CNDC11 CNDC10 CNDC9 CNDC7 — — IFLC15 IFLC7 — — CNDC6 — — IFLC14 IFLC6 — — CNDC5 — — IFLC13 IFLC5 — — CNDC4 — — IFLC12 IFLC4 — — CNDC3 — — IFLC11 IFLC3 — — CNDC2 — — IFLC10 IFLC2 — — CNDC1 — — IFLC9 IFLC1 — —
CEFC15 CEFC14 CEFC13 CEFC12 CEFC11 CEFC10 CEFC9 CEFC7 — — CEFC6 — — CEFC5 — — CEFC4 — — CEFC3 — — CEFC2 — — CEFC1 — —
FREC15 FREC14 FREC13 FREC12 FREC11 FREC10 FREC9 FREC7 — — TSFC15 TSFC7 FREC6 — — TSFC14 TSFC6 FREC5 — — TSFC13 TSFC5 FREC4 — — TSFC12 TSFC4 FREC3 — — TSFC11 TSFC3 FREC2 — — TSFC10 TSFC2 FREC1 — — TSFC9 TSFC1
Rev. 2.00, 03/05, page 867 of 884
Register Address H'FFFFFDA0 H'FFFFFDA1 H'FFFFFDA2 H'FFFFFDA3 H'FFFFFDA4 H'FFFFFDA5 H'FFFFFDA6 H'FFFFFDA7 H'FFFFFDA8 H'FFFFFDA9 H'FFFFFDAA H'FFFFFDAB H'FFFFFDAC — to H'FFFFFE0F H'FFFFFE10 H'FFFFFE11 H'FFFFFE12 H'FFFFFE13 H'FFFFFE14 TIER FTCSR FRCH FRCL OCRAH OCRBH H'FFFFFE15 OCRAL OCRBL H'FFFFFE16 H'FFFFFE17 H'FFFFFE18 H'FFFFFE19 H'FFFFFE1A to H'FFFFFE3F H'FFFFFE40 H'FFFFFE41 H'FFFFFE42 H'FFFFFE43 H'FFFFFE44 H'FFFFFE45 VCRF VCRE TCR TOCR FICRH FICRL — — — — — IEDG — — — — — — ICIE ICF — — — — — — MAFCR RFCR Name TLFRCR Bit 7 — — TLFC15 TLFC7 — — RFC15 RFC7 — — Bit 6 — — TLFC14 TLFC6 — — RFC14 RFC6 — — Bit 5 — — TLFC13 TLFC5 — — RFC13 RFC5 — —
Bit Names Bit 4 — — TLFC12 TLFC4 — — RFC12 RFC4 — — Bit 3 — — TLFC11 TLFC3 — — RFC11 RFC3 — — Bit 2 — — TLFC10 TLFC2 — — RFC10 RFC2 — — Bit 1 — — TLFC9 TLFC1 — — RFC9 RFC1 — — Bit 0 — — TLFC8 TLFC0 — — RFC8 RFC0 — — MAFC8 MAFC0 — — Module EtherC
MAFC15 MAFC14 MAFC13 MAFC12 MAFC11 MAFC10 MAFC9 MAFC7 — MAFC6 — MAFC5 — MAFC4 — MAFC3 — MAFC2 — MAFC1 —
OCIAE OCFA
OCIBE OCFB
OVIE OVF
— CCLRA
FRT
— —
— —
CKS1 OLVLA
CKS0 OLVLB
OCRS
—
—
—
—
—
IPRD
TPU0IP3 TPU0IP2 TPU0IP1 TPU0IP0 TPU1IP3 TPU1IP2 TPU1IP1 TPU1IP0 INTC TPU2IP3 TPU2IP2 TPU2IP1 TPU2IP0 SCF1IP3 SCF1IP2 SCF1IP1 SCF1IP0 — — — — TG0AV6 TG0BV6 TG0AV5 TG0BV5 TG0AV4 TG0BV4 TG0AV3 TG0BV3 TG0AV2 TG0BV2 TG0AV1 TG0BV1 TG0AV0 TG0BV0
TG0CV6 TG0CV5 TG0CV4 TG0CV3 TG0CV2 TG0CV1 TG0CV0 TG0DV6 TG0DV5 TG0DV4 TG0DV3 TG0DV2 TG0DV1 TG0DV0
Rev. 2.00, 03/05, page 868 of 884
Register Address H'FFFFFE46 H'FFFFFE47 H'FFFFFE48 H'FFFFFE49 H'FFFFFE4A H'FFFFFE4B H'FFFFFE4C H'FFFFFE4D H'FFFFFE4E H'FFFFFE4F H'FFFFFE50 H'FFFFFE51 H'FFFFFE52 H'FFFFFE53 H'FFFFFE54 H'FFFFFE55 H'FFFFFE56 H'FFFFFE57 H'FFFFFE58 to H'FFFFFE5F H'FFFFFE60 H'FFFFFE61 H'FFFFFE62 H'FFFFFE63 H'FFFFFE64 H'FFFFFE65 H'FFFFFE66 H'FFFFFE67 H'FFFFFE68 H'FFFFFE69 H'FFFFFE6A to H'FFFFFE70 H'FFFFFE71 H'FFFFFE72 — VCRD VCRC VCRB VCRA — VCRO VCRN VCRM VCRL VCRK VCRJ VCRI VCRH Name VCRG Bit 7 — — — — — — — — — — — — — — — — — — — Bit 6 TC0VV6 — TG1AV6 TG1BV6 TC1VV6 TC1UV6 TG2AV6 TG2BV6 TC2VV6 TC2UV6 SER1V6 SRX1V6 SBR1V6 STX1V6 SER2V6 SRX2V6 SBR2V6 STX2V6 — Bit 5 TC0VV5 — TG1AV5 TG1BV5 TC1VV5 TC1UV5 TG2AV5 TG2BV5 TC2VV5 Bit 4
Bit Names Bit 3 TC0VV3 — TG1AV3 TG1BV3 TC1VV3 TC1UV3 TG2AV3 TG2BV3 TC2VV3 TC2UV3 Bit 2 TC0VV2 — TG1AV2 TG1BV2 TC1VV2 TC1UV2 TG2AV2 TG2BV2 TC2VV2 TC2UV2 SER1V2 SRX1V2 SBR1V2 STX1V2 SER2V2 SRX2V2 SBR2V2 STX2V2 — Bit 1 TC0VV1 — TG1AV1 TG1BV1 TC1VV1 TC1UV1 TG2AV1 TG2BV1 TC2VV1 TC2UV1 SER1V1 SRX1V1 SBR1V1 STX1V1 SER2V1 SRX2V1 SBR2V1 STX2V1 — Bit 0 TC0VV0 — TG1AV0 TG1BV0 TC1VV0 TC1UV0 TG2AV0 TG2BV0 TC2VV0 TC2UV0 SER1V0 SER1V0 SBR1V0 STX1V0 SER2V0 SRX2V0 SBR2V0 STX2V0 — — Module INTC
TC0VV4 — TG1AV4 TG1BV4 TC1VV4 TC1UV4 TG2AV4 TG2BV4 TC2VV4
TC2UV 5 TC2UV4 SER1V5 SRX1V5 SBR1V5 STX1V5 SER2V5 SRX2V5 SBR2V5 STX2V5 —
SER1V4 SER1V3 SRX1V4 SRX1V3
SBR1V4 SBR1V3 STX1V4 STX1V3
SER2V4 SER2V3 SRX2V4 SRX2V3
SBR2V4 SBR2V3 STX2V4 — STX2V3 —
IPRB
FRTIP3 EEEEDMACIP3 DMACIP2 DMACIP1 DMACIP0 — — — — — — — — — — — EINV6 — — — FICV6 FOCV6 FOVV6 — — — EINV5 — — — FICV5 FOCV5 FOVV5 — — — EINV4 — — — FICV4 FOCV4 FOVV4 — — — EINV3 — — — FICV3 FOCV3 FOVV3 — —
FRTIP2 — EINV2 — — — FICV2 FOCV2 FOVV2 — —
FRTIP1 — EINV1 — — — FICV1 FOCV1 FOVV1 — —
FRTIP0 — EINV0 — — — FICV0 FOCV0 FOVV0 — —
INTC
—
DRCR0 DRCR1
— —
— —
— —
RS4 RS4
RS3 RS3
RS2 RS2
RS1 RS1
RS0 RS0
DMAC
Rev. 2.00, 03/05, page 869 of 884
Register Address H'FFFFFE73 to H'FFFFFE7F H'FFFFFE80 H'FFFFFE81 H'FFFFFE82 H'FFFFFE83 H'FFFFFE84 to H'FFFFFE8F H'FFFFFE90 Name — Bit 7 — Bit 6 — Bit 5 — Bit 4 —
Bit Names Bit 3 — Bit 2 — Bit 1 — Bit 0 — Module —
WTCNT — RSTCSR — — WOVF — —
RSTE —
FMR
PLL2ST
PLL1ST
H'FFFFFE91 H'FFFFFE92 H'FFFFFE93 H'FFFFFE94 to H'FFFFFEBF H'FFFFFEC0 H'FFFFFEC1 H'FFFFFEC2 H'FFFFFEC3 H'FFFFFEC4 H'FFFFFEC5 H'FFFFFEC6 H'FFFFFEC7 H'FFFFFEC8 H'FFFFFEC9 H'FFFFFECA H'FFFFFECB H'FFFFFECC H'FFFFFECD H'FFFFFECE to H'FFFFFEDF H'FFFFFEE0 H'FFFFFEE1 H'FFFFFEE2 H'FFFFFEE3
SBYCR1 CCR SBYCR2 —
SBY W1 — —
HIZ W0 — —
IPRE
SCF2IP3 SCF2IP2 SCF2IP1 SCF2IP0 SIO0IP3 SIO1IP3 SIO1P2 SIO2P1 SIO1IP0 SIO2IP3
VCRP
— —
RER0V6 RER0V5 RER0V4 RER0V3 RER0V2 RER0V1 RER0V0 TER0V6 RDF0V6 TDE0V6 TER0V5 RDF0V5 TDE0V5 TER0V4 RDF0V4 TDE0V4 TER0V3 RDF0V3 TDE0V3 TER0V2 RDF0V2 TDE0V2 TER0V1 RDF0V1 TDE0V1 TER0V0 RDF0V0 TDE0V0
VCRQ
— —
VCRR
— —
RER1V6 RER1V5 RER1V4 RER1V3 RER1V2 RER1V1 RER1V0 TER1V6 RDF1V6 TDE1V6 TER1V5 RDF1V5 TDE1V5 TER1V4 RDF1V4 TDE1V4 TER1V3 RDF1V3 TDE1V3 TER1V2 RDF1V2 TDE1V2 TER1V1 RDF1V1 TDE1V1 TER1V0 RDF1V0 TDE1V0
VCRS
— —
VCRT
— —
RER2V6 RER2V5 RER2V4 RER2V3 RER2V2 RER2V1 RER2V0 TER2V6 RDF2V6 TDE2V6 — TER2V5 RDF2V5 TDE2V5 — TER2V4 RDF2V4 TDE2V4 — TER2V3 RDF2V3 TDE2V3 — TER2V2 RDF2V2 TDE2V2 — TER2V1 RDF2V1 TDE2V1 — TER2V0 RDF2V0 TDE2V0 — —
VCRU
— —
—
—
ICR
NMIL —
— — — WDTIP2
IPRA
— WDTIP3
Rev. 2.00, 03/05, page 870 of 884
TI
WTCSR
OVF
WT/
TME
—
—
CKS2
CKS1
CKS0
WDT
— RSTS —
— — —
— — —
— — —
— — —
— — — —
CKIOST
—
FR3
FR2
FR1
FR0
On-chip oscillation circuit Power-down state CACHE Power-down state —
MSTP5 WB
MSTP4 CP
MSTP3 TW
— OD MSTP8 —
MSTP1 ID MSTP7 —
— CE MSTP6 —
MSTP11 MSTP10 MSTP9 — — —
SIO0IP2 SIO2IP2
SIO0IP1 SIO2IP1
SIO0IP0 SIO2IP0
INTC
— — — WDTIP1
— — — WDTIP0
— —
— —
— EXIMD
NMIE VECMD
INTC
DMACIP3 DMACIP2 DMACIP1 DMACIP0 — — — —
Register Address H'FFFFFEE4 H'FFFFFEE5 H'FFFFFEE6 H'FFFFFEE7 H'FFFFFEE8 H'FFFFFEE9 H'FFFFFEEA to H'FFFFFEFF H'FFFFFF00 H'FFFFFF01 H'FFFFFF02 H'FFFFFF03 H'FFFFFF04 H'FFFFFF05 H'FFFFFF06 H'FFFFFF07 H'FFFFFF08 H'FFFFFF09 H'FFFFFF0A to H'FFFFFF0F H'FFFFFF10 H'FFFFFF11 H'FFFFFF12 to H'FFFFFF13 H'FFFFFF14 H'FFFFFF15 H'FFFFFF16 H'FFFFFF17 H'FFFFFF18 H'FFFFFF19 H'FFFFFF1A H'FFFFFF1B BRDRL BRDRH BRSRL BRSRH BSA31 BSA23 BSA15 BSA7 BDA31 BDA23 BDA15 BDA7 BSA30 BSA22 BSA14 BSA6 BDA30 BDA22 BDA14 BDA6 BSA29 BSA21 BSA13 BSA5 BDA29 BDA21 BDA13 BDA5 — BRFR SVF DVF — PID2 — — PID1 — — — BBRA BAMRAL BAMRAH BARAL — IRQCSR IPRC Name VCRWDT Bit 7 — — Bit 6 WITV6 BCMV6 Bit 5 WITV5 BCMV5 Bit 4
Bit Names Bit 3 WITV3 BCMV3 Bit 2 WITV2 BCMV2 Bit 1 WITV1 BCMV1 IRQ1IP1 IRQ3IP1 IRQ01S IRQ1F — Bit 0 WITV0 BCMV0 IRQ1IP0 IRQ3IP0 IRQ00S IRQ0F — — Module INTC
WITV4 BCMV4
IRQ0IP3 IRQ0IP2 IRQ0IP1 IRQ2IP3 IRQ2IP2 IRQ2IP1 IRQ31S IRL3PS — IRQ30S IRL2PS — IRQ21S IRL1PS —
IRQ0IP0 IRQ1IP3 IRQ1IP2 IRQ2IP0 IRQ3IP3 IRQ3IP2 IRQ20S IRL0PS — IRQ11S IRQ3F — IRQ10S IRQ2F —
BARAH
BAA31 BAA23 BAA15 BAA7
BAA30 BAA22 BAA14 BAA6
BAA29 BAA21 BAA13 BAA5
BAA28 BAA20 BAA12 BAA4
BAA27 BAA19 BAA11 BAA3
BAA26 BAA18 BAA10 BAA2
BAA25 BAA17 BAA9 BAA1
BAA24 BAA16 BAA8 BAA0
UBC
BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA7 — CPA1 — BAMA6 — CPA0 — BAMA5 — IDA1 — BAMA4 — IDA0 — BAMA3 — RWA1 — BAMA2 — RWA0 — BAMA1 — SZA1 — BAMA8 BAMA0 — SZA0 — —
PID0 — —
— — —
— — —
— — —
— — —
UBC
—
BSA28 BSA20 BSA12 BSA4 DA28 BDA20 BDA12 BDA4
BSA27 BSA19 BSA11 BSA3 BDA27 BDA19 BDA11 BDA3
BSA26 BSA18 BSA10 BSA2 BDA26 BDA18 BDA10 BDA2
BSA25 BSA17 BSA9 BSA1 BDA25 BDA17 BDA9 BDA1
BSA24 BSA16 BSA8 BSA0 BDA24 BDA16 BDA8 BDA0
UBC
Rev. 2.00, 03/05, page 871 of 884
Register Address H'FFFFFF1C to H'FFFFFF1F H'FFFFFF20 H'FFFFFF21 H'FFFFFF22 H'FFFFFF23 H'FFFFFF24 H'FFFFFF25 H'FFFFFF26 H'FFFFFF27 H'FFFFFF28 H'FFFFFF29 H'FFFFFF2A to H'FFFFFF2F H'FFFFFF30 H'FFFFFF31 H'FFFFFF32 H'FFFFFF33 H'FFFFFF34 to H'FFFFFF3F H'FFFFFF40 H'FFFFFF41 H'FFFFFF42 H'FFFFFF43 H'FFFFFF44 H'FFFFFF45 H'FFFFFF46 H'FFFFFF47 H'FFFFFF48 H'FFFFFF49 H'FFFFFF4A to H'FFFFFF4F — BBRC BAMRCL BAMRCH BARCL BARCH BAC31 BAC23 BAC15 BAC7 BAC30 BAC22 BAC14 BAC6 BAC29 BAC21 BAC13 BAC5 — BRCRL BRCRH CMFCA CMFCB CMFCC CMFCD — CMFPA CMFPB CMFPC CMFPD — — — ETBEC ETBED — — — BBRB BAMRBL BAMRBH BARBL BARBH BAB31 BAB23 BAB15 BAB7 BAB30 BAB22 BAB14 BAB6 BAB29 BAB21 BAB13 BAB5 Name — Bit 7 — Bit 6 — Bit 5 — Bit 4 —
Bit Names Bit 3 — Bit 2 — Bit 1 — Bit 0 — Module —
BAB28 BAB20 BAB12 BAB4
BAB27 BAB19 BAB11 BAB3
BAB26 BAB18 BAB10 BAB2
BAB25 BAB17 BAB9 BAB1
BAB24 BAB16 BAB8 BAB0
UBC
BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB7 — CPB1 — BAMB6 — CPB0 — BAMB5 — IDB1 — BAMB4 — IDB0 — BAMB3 — RWB1 — BAMB2 — RWB0 — BAMB1 — SZB1 — BAMB8 BAMB0 — SZB0 — —
PCTE SEQ0 DBEC DBED —
PCBA PCBB PCBC PCBD —
— — — — —
— — — — —
UBC
SEQ1 — — —
—
BAC28 BAC20 BAC12 BAC4
BAC27 BAC19 BAC11 BAC3
BAC26 BAC18 BAC10 BAC2
BAC25 BAC17 BAC9 BAC1
BAC24 BAC16 BAC8 BAC0
UBC
BAMC31 BAMC30 BAMC29 BAMC28 BAMC27 BAMC26 BAMC25 BAMC24 BAMC23 BAMC22 BAMC21 BAMC20 BAMC19 BAMC18 BAMC17 BAMC16 BAMC15 BAMC14 BAMC13 BAMC12 BAMC11 BAMC10 BAMC9 BAMC7 — CPC1 — BAMC6 — CPC0 — BAMC5 — IDC1 — BAMC4 — IDC0 — BAMC3 — RWC1 — BAMC2 — RWC0 — BAMC1 XYEC SZC1 — BAMC8 BAMC0 XYSC SZC0 — —
Rev. 2.00, 03/05, page 872 of 884
Register Address H'FFFFFF50 H'FFFFFF51 H'FFFFFF52 H'FFFFFF53 H'FFFFFF54 H'FFFFFF55 H'FFFFFF56 H'FFFFFF57 H'FFFFFF58 H'FFFFFF59 H'FFFFFF5A to H'FFFFFF5F H'FFFFFF60 H'FFFFFF61 H'FFFFFF62 H'FFFFFF63 H'FFFFFF64 H'FFFFFF65 H'FFFFFF66 H'FFFFFF67 H'FFFFFF68 H'FFFFFF69 H'FFFFFF6A to H'FFFFFF6F H'FFFFFF70 H'FFFFFF71 H'FFFFFF72 H'FFFFFF73 H'FFFFFF74 H'FFFFFF75 BDMRDH BDRDL BDRDH BDD31 BDD23 BDD15 BDD7 BDD30 BDD22 BDD14 BDD6 BDD29 BDD21 BDD13 BDD5 — BBRD BAMRDL BAMRDH BARDL BARDH BAD31 BAD23 BAD15 BAD7 BAD30 BAD22 BAD14 BAD6 BAD29 BAD21 BAD13 BAD5 — BETRC BDMRCL BDMRCH BDRCL Name BDRCH Bit 7 BDC31 BDC23 BDC15 BDC7 Bit 6 BDC30 BDC22 BDC14 BDC6 Bit 5 BDC29 BDC21 BDC13 BDC5 Bit 4
Bit Names Bit 3 BDC27 BDC19 BDC11 BDC3 Bit 2 BDC26 BDC18 BDC10 BDC2 Bit 1 BDC25 BDC17 BDC9 BDC1 Bit 0 BDC24 BDC16 BDC8 BDC0 Module UBC
BDC28 BDC20 BDC12 BDC4
BDMC31 BDMC30 BDMC29 BDMC28 BDMC27 BDMC26 BDMC25 BDMC24 BDMC23 BDMC22 BDMC21 BDMC20 BDMC19 BDMC18 BDMC17 BDMC16 BDMC15 BDMC14 BDMC13 BDMC12 BDMC11 BDMC10 BDMC9 BDMC7 — ETRC7 — BDMC6 — ETRC6 — BDMC5 — ETRC5 — BDMC4 — ETRC4 — BDMC3 BDMC2 BDMC1 ETRC9 ETRC1 — BDMC8 BDMC0 ETRC8 ETRC0 — —
ETRC11 ETRC10 ETRC3 — ETRC2 —
BAD28 BAD20 BAD12 BAD4
BAD27 BAD19 BAD11 BAD3
BAD26 BAD18 BAD10 BAD2
BAD25 BAD17 BAD9 BAD1
BAD24 BAD16 BAD8 BAD0
UBC
BAMD31 BAMD30 BAMD29 BAMD28 BAMD27 BAMD26 BAMD25 BAMD24 BAMD23 BAMD22 BAMD21 BAMD20 BAMD19 BAMD18 BAMD17 BAMD16 BAMD15 BAMD14 BAMD13 BAMD12 BAMD11 BAMD10 BAMD9 BAMD7 — CPD1 — BAMD6 — CPD0 — BAMD5 — IDD1 — BAMD4 — IDD0 — BAMD3 — RWD1 — BAMD2 — RWD0 — BAMD1 XYED SZD1 — BAMD8 BAMD0 XYSD SZD0 — —
BDD28 BDD20 BDD12 BDD4
BDD27 BDD19 BDD11 BDD3
BDD26 BDD18 BDD10 BDD2
BDD25 BDD17 BDD9 BDD1
BDD24 BDD16 BDD8 BDD0
UBC
BDMD31 BDMD30 BDMD29 BDMD28 BDMD27 BDMD26 BDMD25 BDMD24 BDMD23 BDMD22 BDMD21 BDMD20 BDMD19 BDMD18 BDMD17 BDMD16
Rev. 2.00, 03/05, page 873 of 884
Register Address H'FFFFFF76 H'FFFFFF77 H'FFFFFF78 H'FFFFFF79 H'FFFFFF7A to H'FFFFFF7F H'FFFFFF80 H'FFFFFF81 H'FFFFFF82 H'FFFFFF83 H'FFFFFF84 H'FFFFFF85 H'FFFFFF86 H'FFFFFF87 H'FFFFFF88 H'FFFFFF89 H'FFFFFF8A H'FFFFFF8B H'FFFFFF8C H'FFFFFF8D H'FFFFFF8E H'FFFFFF8F H'FFFFFF90 H'FFFFFF91 H'FFFFFF92 H'FFFFFF93 H'FFFFFF94 H'FFFFFF95 H'FFFFFF96 H'FFFFFF97 H'FFFFFF98 H'FFFFFF99 H'FFFFFF9A H'FFFFFF9B TCR1 — — — — DAR1 SAR1 CHCR0 — — DM1 AL — — DM0 DS — — SM1 DL — — SM0 TB TCR0 — — — — DAR0 SAR0 — BETRD Name BDMRDL Bit 7 Bit 6 Bit 5
Bit Names Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BDMD8 BDMD0 ETRD8 ETRD0 — — Module USB
BDMD15 BDMD14 BDMD13 BDMD12 BDMD11 BDMD10 BDMD9 BDMD7 — ETRD7 — BDMD6 — ETRD6 — BDMD5 — ETRD5 — BDMD4 — ETRD4 — BDMD3 ETRD11 ETRD3 — BDMD2 ETRD10 ETRD2 — BDMD1 ETRD9 ETRD1 —
DMAC
—
—
—
—
— — TS1 TA
— — TS0 IE
— — AR TE
— — AM DE
—
—
—
—
Rev. 2.00, 03/05, page 874 of 884
Register Address H'FFFFFF9C H'FFFFFF9D H'FFFFFF9E H'FFFFFF9F H'FFFFFFA0 H'FFFFFFA1 H'FFFFFFA2 H'FFFFFFA3 H'FFFFFFA4 to H'FFFFFFA7 H'FFFFFFA8 H'FFFFFFA9 H'FFFFFFAA H'FFFFFFAB H'FFFFFFAC to H'FFFFFFAF H'FFFFFFB0 H'FFFFFFB1 H'FFFFFFB2 H'FFFFFFB3 H'FFFFFFB4 to H'FFFFFFBF H'FFFFFFC0 H'FFFFFFC1 H'FFFFFFC2 to H'FFFFFFC3 H'FFFFFFC4 H'FFFFFFC5 H'FFFFFFC6 to H'FFFFFFDF H'FFFFFFE0 H'FFFFFFE1 H'FFFFFFE2 to H'FFFFFFE3 — — — — — — Name CHCR1 Bit 7 — — DM1 AL VCRDMA0 — — — VC7 — Bit 6 — — DM0 DS — — — VC6 — Bit 5 — — SM1 DL — — — VC5 — Bit 4 — — SM0 TB — — — VC4 —
Bit Names Bit 3 — — TS1 TA — — — VC3 — Bit 2 — — TS0 IE — — — VC2 — Bit 1 — — AR TE — — — VC1 — Bit 0 — — AM DE — — — VC0 — — Module DMAC
VCRDMA1 — — — VC7 —
— — — VC6 —
— — — VC5 —
— — — VC4 —
— — — VC3 —
— — — VC2 —
— — — VC1 —
— — — VC0 —
DMAC
—
DMAOR
— — — — —
— — — — —
— — — — —
— — — — —
— — — PR —
— — — AE —
— — — NMIF —
— — — DME —
DMAC
—
WCR2
A4WD1 — —
A4WD0 — —
— — —
A4WM — —
A3WM IW41 —
A2WM IW40 —
A1WM W41 —
A0WM W40 —
BSC
—
WCR3
—
—
A4SW2
A4SW1
A4SW0
—
A4HW1
A4HW0
BSC
A3SHW1 A3SHW0 A2SHW1 A2SHW0 A1SHW1 A1SHW0 A0SHW1 A0SHW0 — — — — — — — — —
BCR1
— A1LW1 —
A4LW1 A1LW0 —
A4LW0 A0LW1 —
A2ENDIA BSTROM — N A0LW0 — A4ENDIA DRAM2 N — —
AHLW1 DRAM1 —
AHLW0 DRAM0 —
BSC
—
Rev. 2.00, 03/05, page 875 of 884
Register Address H'FFFFFFE4 H'FFFFFFE5 H'FFFFFFE6 to H'FFFFFFE7 H'FFFFFFE8 H'FFFFFFE9 H'FFFFFFEA to H'FFFFFFEB H'FFFFFFEC H'FFFFFFED H'FFFFFFEE to H'FFFFFFEF H'FFFFFFF0 H'FFFFFFF1 H'FFFFFFF2 to H'FFFFFFF3 H'FFFFFFF4 H'FFFFFFF5 H'FFFFFFF6 to H'FFFFFFF7 H'FFFFFFF8 H'FFFFFFF9 H'FFFFFFFA to H'FFFFFFFB H'FFFFFFFC H'FFFFFFFD H'FFFFFFFE to H'FFFFFFFF — — — — — — — — — — — — — — — Name BCR2 Bit 7 — A3SZ1 — Bit 6 — A3SZ0 — Bit 5 — A2SZ1 — Bit 4 —
Bit Names Bit 3 — A1SZ1 — Bit 2 — A1SZ0 — Bit 1 A4SZ1 — — Bit 0 A4SZ0 — — — Module BSC
A2SZ0 —
WCR1
IW31 W31 —
IW30 W30 —
IW21 W21 —
IW20 W20 —
IW11 W11 —
IW10 W10 —
IW01 W01 —
IW00 W00 —
BSC
—
MCR
TRP0 AMX2 —
RCD0 SZ —
TRWL0 AMX1 —
TRAS1 AMX0 —
TRAS0 RFSH —
BE RMODE —
RASD TRP1 —
TRWL1 RCD1 —
BSC
—
RTCSR
— CMF —
— CMIE —
— CKS2 —
— CKS1 —
— CKS0 —
— RRC2 —
— RRC1 —
— RRC0 —
BSC
—
RTCNT
—
—
—
—
—
—
—
—
BSC
—
—
—
—
—
RTCOR
—
—
—
—
—
—
—
—
BSC
—
—
—
—
—
BCR3
— DSWW1 —
— DSWW0 —
— — —
— — —
A4LW2 — —
AHLW2 BASEL —
A1LW2 EDO —
A0LW2 BWE —
BSC
—
Rev. 2.00, 03/05, page 876 of 884
Appendix B Pin States
B.1 Pin States in Reset, Power-Down State, and Bus-Released State
Pin State Manual Reset Power-Down State BusReleased State Z Z Z Z Z Z Ignored Z Z O I H Z Z Z Z O Z Z Ignored I I H
Pin Type
Pin Name
PowerStandby Standby On Bus Bus Mode Mode Sleep Reset Acquired Released (HIZ = 0) (HIZ = 1) Mode O Z H H H H Z H H H Z H H H H H L H H Z I Z H O IO O O O O I O O O I O O O O O O O O I I Z H Z Z Z Z Z Z Z Z Z O I H Z Z Z Z O Z Z Z I Z H Z Z H H H H Z H H H Z O H H H H L H H Z I I H Z Z H H H H Z H H H Z O H H H H Z H H Z I I Z O IO H H H H I H H O I O H H H H O H H I I I H
Bus control A24 to A0 D31 to D0
DQMUL/
DQMLU/ DQMLL/
REFOUT to
Interrupt
NMI
ZiHSUB HB 0SAC 3SAC
FCEVI 0LRI 3LRI
to
0EW 1EW 2EW 3EW
SLRB RGB DR SB TIAW EO SAC SAR RW 0SC 4SC
RD/ / CKE DQMUU/
to
Rev. 2.00, 03/05, page 877 of 884
Pin State Manual Reset Power-Down State BusReleased State O* I* IO* H I IO I O I I IO IO/I IO/O IO/I/O/O IO/I/I/O IO/I/IO IO/I/IO IO/IO/IO IO/O/IO IO/I/IO IO/I/I IO/I/O IO/I/IO IO/IO/IO IO/O/IO
Pin Type Clock
Pin Name XTAL EXTAL CKIO
PowerStandby Standby On Bus Bus Mode Mode Sleep Reset Acquired Released (HIZ = 0) (HIZ = 1) Mode O* I* IO* H I IO Z H I I Z Z Z / Z Z O* I* IO* H I IO Z H I I IO/Z IO/Z IO/Z O* I* IO* H I IO Z H I I IO/Z IO/Z IO/Z O* I* IO* H I IO Z K I I K K K K/K/K/O K/K/K/O K/K/K K/K/K K/K/K K/K/K K/K/K K/K/K K/K/K K/K/K K/K/K K/K/K O* I* IO* H I IO Z Z I I Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z O* I* IO* H I IO I O I I IO IO/I IO/O IO/I/O/O IO/I/I/O IO/I/IO IO/I/IO IO/IO/IO IO/O/IO IO/I/IO IO/I/I IO/I/O IO/I/IO IO/IO/IO IO/O/IO
DMAC
DREQ1, DREQ0 DACK1, DACK0
MD4 to MD0
Port, PB15/SCK1 Internal PB14/RXD1 peripheral PB13/TXD1 module
PB10/SRXD2/TIOCA1 Z PB9/STCK2/TIOCB1, TCLKC PB8/STS2/TIOCA2 PB7/STXD2/TIOCB2, TCLKD PB6/SRCK1/SCK2 PB5/SRS1/RXD2 PB4/SRXD1/TXD2 PB3/STCK1/TIOCA0 PB2/STS1/TIOCB0 PB1/STXD1/TIOCC0, TCLKA Z Z Z Z Z Z Z Z Z
Rev. 2.00, 03/05, page 878 of 884
STC
PB11/SRS2/ STATS0
STR
PB12/SRCK2/ STATS1
SER
System control
QERPKC KCAPKC
/CKM
PLLCAP2, PLLCAP1
IO/Z/Z/O IO/Z/Z/O IO/Z/Z/O IO/Z/Z/O IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z IO/Z/Z
/
Pin State Manual Reset Power-Down State BusReleased State IO/IO/O IO/I IO/I IO/I IO/I IO/IO IO/O O/IO IO/I IO/I IO/O O/O IO/I IO/O IO I I I I O I
Pin Type
Pin Name
PowerStandby Standby On Bus Bus Mode Mode Sleep Reset Acquired Released (HIZ = 0) (HIZ = 1) Mode Z Z Z Z Z Z Z H Z Z Z H Z Z Z I I I I O I IO/Z/O IO/Z IO/Z IO/Z IO/Z IO/Z IO/Z H/IO IO/Z IO/Z IO/L H/L IO/I IO/O IO I I I I O I IO/Z/O IO/Z IO/Z IO/Z IO/Z IO/Z IO/Z H/IO IO/Z IO/Z IO/L H/L IO/I IO/O IO I I I I O I K/K/O K/K K/K K/K K/K K/K K/K O/K K K K K K K K I I I I O I Z Z Z Z Z Z Z O/Z Z Z Z Z Z Z Z I I I I O I IO/IO/O IO/I IO/I IO/I IO/I IO/IO IO/O O/IO IO/I IO/I IO/O O/O IO/I IO/O IO I I I I O I
Port, PB0/TIOCD0, Internal TCLKB/WOL peripheral PA13/SRCK0 module PA12/SRS0 PA11/SRXD0 PA10/STCK0 PA9/STS0 PA8/STXD0 /PA7
TSRT
H-UDI
FVOTDW
PA5/FTI PA0 TCK TMS TDI TDO
PA6/FTCI
PA4/FTOA CKPO/FTOB PA2/LNKSTA PA1/EXOUT
ASEMODE
Rev. 2.00, 03/05, page 879 of 884
Pin State Manual Reset Power-Down State BusReleased State I O O O I I O IO I I I I
Pin Type EtherC
Pin Name TX-CLK TX-EN TX-ER ETXD3 to ETXD0 CRS COL MDC MDIO RX-CLK RX-DV RX-ER ERXD3 to ERXD0
PowerStandby Standby On Bus Bus Mode Mode Sleep Reset Acquired Released (HIZ = 0) (HIZ = 1) Mode I O O O I I O IO I I I I I O O O I I O IO I I I I I O O O I I O IO I I I I I O O O I I O IO I I I I I O O O I I O IO I I I I I O O O I I O IO I I I I
I: O: H: L: Z: K:
Input Output High-level output Low-level output High-impedance state Input pins are in the high-impedance state; output pins maintain their previous state.
Notes: In sleep mode, if the DMAC is operating the address/data bus and bus control signals vary according to the operation of the DMAC. (The same applies when refreshing is performed.) * Depends on the clock mode ( , MD2 to MD0 setting).
Rev. 2.00, 03/05, page 880 of 884
NQERPKC
Appendix C Product Lineup
Table C.1 SH7615 Product Lineup
Voltage VCC = PLLVCC = 3.3 V PVCC = 5.0 V/3.3 V Operating Frequency 62.5 MHz Mark Code HD6417615ARF HD6417615ARFV HD6417615ARBP HD6417615ARBPV Package FP-208C FP-208CV BP-240A BP-240AV
Abbreviation SH7615
Rev. 2.00, 03/05, page 881 of 884
Appendix D Package Dimensions
Figure D.1 shows the FP-208C and FP-208CV package dimensions, and figure D.2 shows the BP240A and BP-240AV package dimensions.
JEITA Package Code P-LQFP208-28x28-0.50 RENESAS Code PLQP0208KA-A Previous Code FP-208C/FP-208CV MASS[Typ.] 2.7g
HD
*1
D 105 104 bp b1
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
156 157
Reference Symbol
Dimension in Millimeters Min Nom 28 28 1.40 29.8 29.8 30.0 30.0 30.2 30.2 1.70 0.05 0.17 0.10 0.22 0.20 0.12 0.17 0.15 0˚ 8˚ 0.5 0.08 0.08 1.25 1.25 0.4 0.5 1.0 0.6 0.22 0.15 0.27 Max
c1
HE
E
c
D E A2
*2
Terminal cross section
ZE
HD HE A A1 bp b1
208 1 ZD Index mark 52
53
c
A2
F
A1
c
c1
A
L L1
e x y ZD ZE L L1
e
*3
y
bp
x
M
Detail F
Figure D.1 Package Dimensions (FP-208C, FP-208CV)
Rev. 2.00, 03/05, page 882 of 884
JEITA Package Code P-LFBGA240-13x13-0.65
RENESAS Code PLBG0240JA-A
Previous Code BP-240A/BP-240AV
MASS[Typ.] 0.4g
wSA
D
wSB
×4
v
y1 S S
A
y
S
e
ZD A
V U T R P N M L K J H G F E D
e
W
A1
E
Reference Symbol
Dimension in Millimeters Min Nom 13.00 13.00 0.15 0.20 1.40 0.28 0.33 0.65 0.35 0.40 0.45 0.08 0.10 0.2 0.38 Max
B D E v w A A1
ZE
C B A
e b
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
x y y1 SD SE ZD ZE 0.65 0.65
φb
×M S A B
Figure D.2 Package Dimensions (BP-240A, BP-240AV)
Rev. 2.00, 03/05, page 883 of 884
Rev. 2.00, 03/05, page 884 of 884
Renesas 32-Bit RISC Microcomputer Hardware Manual SH7615 Group
Publication Date: 1st Edition, September 2000 Rev.2.00, March 17, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd.
© 2005. Renesas Technology Corp. All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: (21) 6472-1001, Fax: (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001
http://www.renesas.com
Colophon 2.0
SH7615 Group Hardware Manual
