SH7619

REJ09B0237-0500 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SuperH TM SH7619 Group Hardware Manual Renesas 32-Bit RISC Microcomputer RISC engine Family / SH7619 Series SH7619 R4S76190 Rev.5.00 Revision Date: Mar. 15, 2007 Rev. 5.00 Mar. 15, 2007 Page ii of xxxviii Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 5.00 Mar. 15, 2007 Page iii of xxxviii General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 5.00 Mar. 15, 2007 Page iv of xxxviii Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 5.00 Mar. 15, 2007 Page v of xxxviii Preface The SH7619 Group RISC (Reduced Instruction Set Computer) microcomputers include a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using the SH/7619 in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the SH/7619 to the target users. Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the instruction set. Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. • In order to understand the details of the CPU's functions Read the SH-1/SH-2/SH-DSP Software Manual. • In order to understand the details of a register when its name is known The addresses, bits, and initial values of the registers are summarized in section 23, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal: xxxx Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ Rev. 5.00 Mar. 15, 2007 Page vi of xxxviii SH/7619 Group manuals: Document Title SH/7619 Group Hardware Manual SH-1/SH-2/SH-DSP Software Manual Document No. This manual REJ09B0171 User's manuals for development tools: Document Title SuperH RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual TM Document No. REJ10B0152 SuperH RISC engine High-performance Embedded Workshop 3 User's REJ10B0025 Manual SuperH RISC engine High-performance Embedded Workshop 3 Tutorial REJ10B0023 Application note: Document Title SuperH RISC engine C/C++ Compiler Document No. REJ05B0463 Rev. 5.00 Mar. 15, 2007 Page vii of xxxviii Rev. 5.00 Mar. 15, 2007 Page viii of xxxviii Contents Section 1 Overview..................................................................................................1 1.1 1.2 1.3 1.4 Features................................................................................................................................. 2 Block Diagram...................................................................................................................... 7 Pin Assignments ................................................................................................................... 8 Pin Functions ........................................................................................................................ 9 Section 2 CPU........................................................................................................23 2.1 2.2 Features............................................................................................................................... 23 Register Configuration........................................................................................................ 23 2.2.1 General Registers (Rn)........................................................................................ 25 2.2.2 Control Registers ................................................................................................ 25 2.2.3 System Registers................................................................................................. 26 2.2.4 Initial Values of Registers................................................................................... 27 Data Formats....................................................................................................................... 28 2.3.1 Register Data Format .......................................................................................... 28 2.3.2 Memory Data Formats ........................................................................................ 28 2.3.3 Immediate Data Formats..................................................................................... 29 Features of Instructions....................................................................................................... 29 2.4.1 RISC Type .......................................................................................................... 29 2.4.2 Addressing Modes .............................................................................................. 32 2.4.3 Instruction Formats ............................................................................................. 35 Instruction Set ..................................................................................................................... 39 2.5.1 Instruction Set by Type....................................................................................... 39 Processing States................................................................................................................. 51 2.6.1 State Transition ................................................................................................... 51 2.3 2.4 2.5 2.6 Section 3 Cache .....................................................................................................53 3.1 Features............................................................................................................................... 53 3.1.1 Cache Structure................................................................................................... 53 3.1.2 Divided Areas and Cache.................................................................................... 55 Register Descriptions.......................................................................................................... 56 3.2.1 Cache Control Register 1 (CCR1) ...................................................................... 56 Operation ............................................................................................................................ 57 3.3.1 Searching Cache ................................................................................................. 57 3.3.2 Read Access........................................................................................................ 58 3.3.3 Write Access ....................................................................................................... 59 3.2 3.3 Rev. 5.00 Mar. 15, 2007 Page ix of xxxviii 3.4 3.3.4 Write-Back Buffer .............................................................................................. 59 3.3.5 Coherency of Cache and External Memory........................................................ 59 Memory-Mapped Cache ..................................................................................................... 60 3.4.1 Address Array..................................................................................................... 60 3.4.2 Data Array .......................................................................................................... 61 3.4.3 Usage Examples.................................................................................................. 63 Section 4 U Memory ............................................................................................. 65 4.1 4.2 Features............................................................................................................................... 65 Usage Notes ........................................................................................................................ 65 Section 5 Exception Handling ............................................................................... 67 5.1 Overview ............................................................................................................................ 67 5.1.1 Types of Exception Handling and Priority ......................................................... 67 5.1.2 Exception Handling Operations.......................................................................... 68 5.1.3 Exception Handling Vector Table ...................................................................... 69 Resets.................................................................................................................................. 71 5.2.1 Types of Resets................................................................................................... 71 5.2.2 Power-On Reset .................................................................................................. 71 5.2.3 H-UDI Reset ....................................................................................................... 72 Address Errors .................................................................................................................... 73 5.3.1 Address Error Sources ........................................................................................ 73 5.3.2 Address Error Exception Source......................................................................... 73 Interrupts............................................................................................................................. 74 5.4.1 Interrupt Sources................................................................................................. 74 5.4.2 Interrupt Priority ................................................................................................. 75 5.4.3 Interrupt Exception Handling ............................................................................. 75 Exceptions Triggered by Instructions ................................................................................. 76 5.5.1 Types of Exceptions Triggered by Instructions .................................................. 76 5.5.2 Trap Instructions................................................................................................. 76 5.5.3 Illegal Slot Instructions....................................................................................... 77 5.5.4 General Illegal Instructions................................................................................. 77 Cases when Exceptions are Accepted................................................................................. 78 Stack States after Exception Handling Ends....................................................................... 79 Usage Notes ........................................................................................................................ 81 5.8.1 Value of Stack Pointer (SP) ................................................................................ 81 5.8.2 Value of Vector Base Register (VBR)................................................................ 81 5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling...... 81 5.8.4 Notes on Slot Illegal Instruction Exception Handling ........................................ 81 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Rev. 5.00 Mar. 15, 2007 Page x of xxxviii Section 6 Interrupt Controller (INTC) ...................................................................83 6.1 6.2 6.3 Features............................................................................................................................... 83 Input/Output Pins................................................................................................................ 85 Register Descriptions.......................................................................................................... 85 6.3.1 Interrupt Control Register 0 (ICR0).................................................................... 86 6.3.2 IRQ Control Register (IRQCR) .......................................................................... 87 6.3.3 IRQ Status register (IRQSR) .............................................................................. 90 6.3.4 Interrupt Priority Registers A to G (IPRA to IPRG)........................................... 95 Interrupt Sources................................................................................................................. 97 6.4.1 External Interrupts .............................................................................................. 97 6.4.2 On-Chip Peripheral Module Interrupts ............................................................... 99 6.4.3 User Break Interrupt ........................................................................................... 99 6.4.4 H-UDI Interrupt .................................................................................................. 99 Interrupt Exception Handling Vector Table...................................................................... 100 Interrupt Operation ........................................................................................................... 102 6.6.1 Interrupt Sequence ............................................................................................ 102 6.6.2 Stack after Interrupt Exception Handling ......................................................... 104 Interrupt Response Time................................................................................................... 104 6.4 6.5 6.6 6.7 Section 7 Bus State Controller (BSC)..................................................................107 7.1 7.2 7.3 Features............................................................................................................................. 107 Input/Output Pins.............................................................................................................. 110 Area Overview.................................................................................................................. 111 7.3.1 Area Division.................................................................................................... 111 7.3.2 Shadow Area..................................................................................................... 112 7.3.3 Address Map ..................................................................................................... 112 7.3.4 Area 0 Memory Type and Memory Bus Width ................................................ 114 7.3.5 Data Alignment................................................................................................. 114 Register Descriptions........................................................................................................ 115 7.4.1 Common Control Register (CMNCR) .............................................................. 116 7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5B, 6B) ............... 117 7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 3, 4, 5B, 6B) ................ 122 7.4.4 SDRAM Control Register (SDCR)................................................................... 138 7.4.5 Refresh Timer Control/Status Register (RTCSR)............................................. 139 7.4.6 Refresh Timer Counter (RTCNT)..................................................................... 141 7.4.7 Refresh Time Constant Register (RTCOR) ...................................................... 142 Operation .......................................................................................................................... 143 7.5.1 Endian/Access Size and Data Alignment.......................................................... 143 7.5.2 Normal Space Interface..................................................................................... 149 7.5.3 Access Wait Control ......................................................................................... 154 Rev. 5.00 Mar. 15, 2007 Page xi of xxxviii 7.4 7.5 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 Extension of Chip Select (CSn) Assertion Period............................................. 156 SDRAM Interface ............................................................................................. 157 Byte-Selection SRAM Interface ....................................................................... 186 PCMCIA Interface............................................................................................ 191 Wait between Access Cycles ............................................................................ 198 Others................................................................................................................ 198 Section 8 Clock Pulse Generator (CPG) ............................................................. 201 8.1 8.2 8.3 8.4 Features............................................................................................................................. 201 Input/Output Pins.............................................................................................................. 204 Clock Operating Modes .................................................................................................... 204 Register Descriptions........................................................................................................ 206 8.4.1 Frequency Control Register (FRQCR) ............................................................. 206 8.4.2 PHY Clock Frequency Control Register (MCLKCR) ...................................... 208 8.4.3 Usage Notes ...................................................................................................... 209 Changing Frequency ......................................................................................................... 210 8.5.1 Changing Multiplication Ratio ......................................................................... 210 8.5.2 Changing Division Ratio .................................................................................. 211 8.5.3 Changing Clock Operating Mode ..................................................................... 211 Notes on Board Design ..................................................................................................... 213 8.5 8.6 Section 9 Watchdog Timer (WDT) ..................................................................... 215 9.1 9.2 Features............................................................................................................................. 215 Register Descriptions........................................................................................................ 217 9.2.1 Watchdog Timer Counter (WTCNT)................................................................ 217 9.2.2 Watchdog Timer Control/Status Register (WTCSR)........................................ 217 9.2.3 Notes on Register Access ................................................................................. 219 WDT Operation ................................................................................................................ 220 9.3.1 Canceling Software Standbys ........................................................................... 220 9.3.2 Changing Frequency ......................................................................................... 221 9.3.3 Using Watchdog Timer Mode .......................................................................... 221 9.3.4 Using Interval Timer Mode .............................................................................. 222 Usage Notes ...................................................................................................................... 222 9.3 9.4 Section 10 Power-Down Modes.......................................................................... 223 10.1 10.2 10.3 Features............................................................................................................................. 223 10.1.1 Types of Power-Down Modes .......................................................................... 223 Input/Output Pins.............................................................................................................. 224 Register Descriptions........................................................................................................ 224 10.3.1 Standby Control Register (STBCR).................................................................. 225 Rev. 5.00 Mar. 15, 2007 Page xii of xxxviii 10.4 10.5 10.6 10.3.2 Standby Control Register 2 (STBCR2)............................................................. 226 10.3.3 Standby Control Register 3 (STBCR3)............................................................. 227 10.3.4 Standby Control Register 4 (STBCR4)............................................................. 228 Sleep Mode ....................................................................................................................... 229 10.4.1 Transition to Sleep Mode.................................................................................. 229 10.4.2 Canceling Sleep Mode ...................................................................................... 229 Software Standby Mode.................................................................................................... 230 10.5.1 Transition to Software Standby Mode .............................................................. 230 10.5.2 Canceling Software Standby Mode................................................................... 231 Module Standby Mode...................................................................................................... 232 10.6.1 Transition to Module Standby Mode ................................................................ 232 10.6.2 Canceling Module Standby Function................................................................ 232 Section 11 Ethernet Controller (EtherC)..............................................................233 11.1 11.2 11.3 Features............................................................................................................................. 233 Input/Output Pins.............................................................................................................. 235 Register Description ......................................................................................................... 237 11.3.1 EtherC Mode Register (ECMR)........................................................................ 238 11.3.2 EtherC Status Register (ECSR)......................................................................... 241 11.3.3 EtherC Interrupt Permission Register (ECSIPR) .............................................. 243 11.3.4 PHY Interface Register (PIR) ........................................................................... 244 11.3.5 MAC Address High Register (MAHR)............................................................. 245 11.3.6 MAC Address Low Register (MALR).............................................................. 245 11.3.7 Receive Frame Length Register (RFLR) .......................................................... 246 11.3.8 PHY Status Register (PSR)............................................................................... 247 11.3.9 Transmit Retry Over Counter Register (TROCR) ............................................ 247 11.3.10 Delayed Collision Detect Counter Register (CDCR)........................................ 248 11.3.11 Lost Carrier Counter Register (LCCR) ............................................................. 248 11.3.12 Carrier Not Detect Counter Register (CNDCR) ............................................... 248 11.3.13 CRC Error Frame Counter Register (CEFCR).................................................. 249 11.3.14 Frame Receive Error Counter Register (FRECR)............................................. 249 11.3.15 Too-Short Frame Receive Counter Register (TSFRCR)................................... 249 11.3.16 Too-Long Frame Receive Counter Register (TLFRCR)................................... 250 11.3.17 Residual-Bit Frame Counter Register (RFCR) ................................................. 250 11.3.18 Multicast Address Frame Counter Register (MAFCR)..................................... 250 11.3.19 IPG Register (IPGR) ......................................................................................... 251 11.3.20 Automatic PAUSE Frame Set Register (APR) ................................................. 251 11.3.21 Manual PAUSE Frame Set Register (MPR) ..................................................... 252 11.3.22 PAUSE Frame Retransfer Count Set Register (TPAUSER)............................. 252 Operation .......................................................................................................................... 253 Rev. 5.00 Mar. 15, 2007 Page xiii of xxxviii 11.4 11.5 11.6 11.4.1 Transmission..................................................................................................... 253 11.4.2 Reception .......................................................................................................... 255 11.4.3 MII Frame Timing ............................................................................................ 256 11.4.4 Accessing MII Registers................................................................................... 258 11.4.5 Magic Packet Detection .................................................................................... 261 11.4.6 Operation by IPG Setting.................................................................................. 262 11.4.7 Flow Control..................................................................................................... 262 Connection to PHY-LSI.................................................................................................... 263 Usage Notes ...................................................................................................................... 264 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)........................................................................................ 265 12.1 12.2 Features............................................................................................................................. 265 Register Descriptions........................................................................................................ 266 12.2.1 E-DMAC Mode Register (EDMR) ................................................................... 267 12.2.2 E-DMAC Transmit Request Register (EDTRR) .............................................. 268 12.2.3 E-DMAC Receive Request Register (EDRRR)................................................ 269 12.2.4 Transmit Descriptor List Address Register (TDLAR)...................................... 270 12.2.5 Receive Descriptor List Address Register (RDLAR) ....................................... 270 12.2.6 EtherC/E-DMAC Status Register (EESR)........................................................ 271 12.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)................... 276 12.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)............................. 279 12.2.9 Receive Missed-Frame Counter Register (RMFCR) ........................................ 281 12.2.10 Transmit FIFO Threshold Register (TFTR)...................................................... 282 12.2.11 FIFO Depth Register (FDR) ............................................................................. 283 12.2.12 Receiving Method Control Register (RMCR) .................................................. 284 12.2.13 E-DMAC Operation Control Register (EDOCR) ............................................. 285 12.2.14 Receiving-Buffer Write Address Register (RBWAR) ...................................... 286 12.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) ................................. 286 12.2.16 Transmission-Buffer Read Address Register (TBRAR)................................... 286 12.2.17 Transmission-Descriptor Fetch Address Register (TDFAR) ............................ 287 12.2.18 Flow Control FIFO Threshold Register (FCFTR) ............................................ 287 12.2.19 Transmit Interrupt Register (TRIMD) .............................................................. 288 Operation .......................................................................................................................... 289 12.3.1 Descriptor List and Data Buffers ...................................................................... 289 12.3.2 Transmission..................................................................................................... 298 12.3.3 Reception .......................................................................................................... 300 12.3.4 Multi-Buffer Frame Transmit/Receive Processing ........................................... 302 12.3 Rev. 5.00 Mar. 15, 2007 Page xiv of xxxviii 12.4 Usage Notes ...................................................................................................................... 304 12.4.1 Usage Notes on SH-Ether EtherC/E-DMAC Status Register (EESR).............. 304 12.4.2 Usage Notes on SH-Ether Transmit-FIFO Underflow...................................... 313 Section 13 Direct Memory Access Controller (DMAC) .....................................323 13.1 13.2 13.3 Features............................................................................................................................. 323 Input/Output Pins.............................................................................................................. 325 Register Descriptions........................................................................................................ 326 13.3.1 DMA Source Address Registers 0 to 3 (SAR_0 to SAR_3) ............................. 327 13.3.2 DMA Destination Address Registers 0 to 3 (DAR_0 to DAR_3) .................... 327 13.3.3 DMA Transfer Count Registers 0 to 3 (DMATCR_0 to DMATCR_3) ........... 327 13.3.4 DMA Channel Control Registers 0 to 3 (CHCR_0 to CHCR_3)...................... 328 13.3.5 DMA Operation Register (DMAOR) ............................................................... 333 13.3.6 DMA Extended Resource Selectors 0 and 1 (DMARS0 and DMARS1) ......... 335 Operation .......................................................................................................................... 337 13.4.1 DMA Transfer Flow ......................................................................................... 337 13.4.2 DMA Transfer Requests ................................................................................... 339 13.4.3 Channel Priority................................................................................................ 341 13.4.4 DMA Transfer Types........................................................................................ 344 13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ....................... 353 Usage Notes ...................................................................................................................... 357 13.5.1 Notes on DACK Pin Output ............................................................................. 357 13.5.2 Notes On DREQ Sampling When DACK is Divided in External Access ........ 358 13.5.3 Other Notes ....................................................................................................... 361 13.4 13.5 Section 14 Compare Match Timer (CMT) ..........................................................363 14.1 14.2 Features............................................................................................................................. 363 Register Descriptions........................................................................................................ 364 14.2.1 Compare Match Timer Start Register (CMSTR) .............................................. 364 14.2.2 Compare Match Timer Control/Status Register (CMCSR) .............................. 365 14.2.3 Compare Match Counter (CMCNT) ................................................................. 366 14.2.4 Compare Match Constant Register (CMCOR) ................................................. 366 Operation .......................................................................................................................... 367 14.3.1 Interval Count Operation .................................................................................. 367 14.3.2 CMCNT Count Timing..................................................................................... 367 Interrupts........................................................................................................................... 368 14.4.1 Interrupt Sources............................................................................................... 368 14.4.2 Timing of Setting Compare Match Flag ........................................................... 368 14.4.3 Timing of Clearing Compare Match Flag......................................................... 368 Usage Notes ...................................................................................................................... 369 Rev. 5.00 Mar. 15, 2007 Page xv of xxxviii 14.3 14.4 14.5 14.5.1 14.5.2 14.5.3 14.5.4 Conflict between Write and Compare-Match Processes of CMCNT ............... 369 Conflict between Word-Write and Count-Up Processes of CMCNT ............... 370 Conflict between Byte-Write and Count-Up Processes of CMCNT................. 371 Conflict between Write Processes to CMCNT with the Counting Stopped and CMCOR ..................................................................................................... 371 Section 15 Serial Communication Interface with FIFO (SCIF).......................... 373 15.1 15.2 15.3 Overview .......................................................................................................................... 373 15.1.1 Features............................................................................................................. 373 Pin Configuration.............................................................................................................. 376 Register Description ......................................................................................................... 377 15.3.1 Receive Shift Register (SCRSR) ...................................................................... 378 15.3.2 Receive FIFO Data Register (SCFRDR) .......................................................... 378 15.3.3 Transmit Shift Register (SCTSR) ..................................................................... 378 15.3.4 Transmit FIFO Data Register (SCFTDR)......................................................... 379 15.3.5 Serial Mode Register (SCSMR)........................................................................ 379 15.3.6 Serial Control Register (SCSCR)...................................................................... 382 15.3.7 Serial Status Register (SCFSR) ........................................................................ 386 15.3.8 Bit Rate Register (SCBRR) .............................................................................. 394 15.3.9 FIFO Control Register (SCFCR) ...................................................................... 401 15.3.10 FIFO Data Count Register (SCFDR)................................................................ 404 15.3.11 Serial Port Register (SCSPTR) ......................................................................... 405 15.3.12 Line Status Register (SCLSR) .......................................................................... 409 Operation .......................................................................................................................... 410 15.4.1 Overview .......................................................................................................... 410 15.4.2 Operation in Asynchronous Mode .................................................................... 412 15.4.3 Synchronous Mode ........................................................................................... 423 SCIF Interrupts ................................................................................................................. 431 Serial Port Register (SCSPTR) and SCIF Pins ................................................................. 432 Usage Notes ...................................................................................................................... 436 15.4 15.5 15.6 15.7 Section 16 Serial I/O with FIFO (SIOF) ............................................................. 441 16.1 16.2 16.3 Features............................................................................................................................. 441 Input/Output Pins.............................................................................................................. 443 Register Descriptions........................................................................................................ 444 16.3.1 Mode Register (SIMDR) .................................................................................. 445 16.3.2 Control Register (SICTR)................................................................................. 448 16.3.3 Transmit Data Register (SITDR) ...................................................................... 451 16.3.4 Receive Data Register (SIRDR) ....................................................................... 452 16.3.5 Transmit Control Data Register (SITCR) ......................................................... 453 Rev. 5.00 Mar. 15, 2007 Page xvi of xxxviii 16.4 16.3.6 Receive Control Data Register (SIRCR)........................................................... 454 16.3.7 Status Register (SISTR).................................................................................... 455 16.3.8 Interrupt Enable Register (SIIER)..................................................................... 461 16.3.9 FIFO Control Register (SIFCTR) ..................................................................... 463 16.3.10 Clock Select Register (SISCR) ......................................................................... 465 16.3.11 Transmit Data Assign Register (SITDAR) ....................................................... 466 16.3.12 Receive Data Assign Register (SIRDAR)......................................................... 468 16.3.13 Control Data Assign Register (SICDAR) ......................................................... 469 16.3.14 SPI Control Register (SPICR) .......................................................................... 470 Operation .......................................................................................................................... 473 16.4.1 Serial Clocks ..................................................................................................... 473 16.4.2 Serial Timing .................................................................................................... 474 16.4.3 Transfer Data Format........................................................................................ 475 16.4.4 Register Allocation of Transfer Data ................................................................ 477 16.4.5 Control Data Interface....................................................................................... 479 16.4.6 FIFO.................................................................................................................. 481 16.4.7 Transmit and Receive Procedures..................................................................... 483 16.4.8 Interrupts........................................................................................................... 488 16.4.9 Transmit and Receive Timing........................................................................... 490 16.4.10 SPI Mode .......................................................................................................... 494 Section 17 Host Interface (HIF)...........................................................................503 17.1 17.2 17.3 Features............................................................................................................................. 503 Input/Output Pins.............................................................................................................. 505 Parallel Access.................................................................................................................. 506 17.3.1 Operation .......................................................................................................... 506 17.3.2 Connection Method........................................................................................... 506 Register Descriptions........................................................................................................ 507 17.4.1 HIF Index Register (HIFIDX)........................................................................... 507 17.4.2 HIF General Status Register (HIFGSR)............................................................ 510 17.4.3 HIF Status/Control Register (HIFSCR) ............................................................ 510 17.4.4 HIF Memory Control Register (HIFMCR) ....................................................... 513 17.4.5 HIF Internal Interrupt Control Register (HIFIICR) .......................................... 515 17.4.6 HIF External Interrupt Control Register (HIFEICR) ........................................ 515 17.4.7 HIF Address Register (HIFADR) ..................................................................... 516 17.4.8 HIF Data Register (HIFDATA) ........................................................................ 517 17.4.9 HIF Boot Control Register (HIFBCR).............................................................. 517 17.4.10 HIFDREQ Trigger Register (HIFDTR) ............................................................ 518 17.4.11 HIF Bank Interrupt Control Register (HIFBICR) ............................................. 519 Memory Map .................................................................................................................... 521 Rev. 5.00 Mar. 15, 2007 Page xvii of xxxviii 17.4 17.5 17.6 17.7 Interface (Basic)................................................................................................................ 522 Interface (Details) ............................................................................................................. 523 17.7.1 HIFIDX Write/HIFGSR Read .......................................................................... 523 17.7.2 Reading/Writing of HIF Registers other than HIFIDX and HIFGSR............... 523 17.7.3 Consecutive Data Writing to HIFRAM by External Device............................. 524 17.7.4 Consecutive Data Reading from HIFRAM to External Device ........................ 524 17.8 External DMAC Interface................................................................................................. 525 17.9 Alignment Control ............................................................................................................ 531 17.10 Interface When External Device Power is Cut Off........................................................... 532 Section 18 Pin Function Controller (PFC) .......................................................... 535 18.1 Register Descriptions........................................................................................................ 545 18.1.1 Port A IO Register H (PAIORH) ...................................................................... 546 18.1.2 Port A Control Register H1 and H2 (PACRH1 and PACRH2) ........................ 546 18.1.3 Port B IO Register L (PBIORL) ....................................................................... 549 18.1.4 Port B Control Register L1 and L2 (PBCRL1 and PBCRL2)........................... 549 18.1.5 Port C IO Register H and L (PCIORH and PCIORL) ...................................... 553 18.1.6 Port C Control Register H2, L1, and L2 (PCCRH2, PCCRL1, and PCCRL2). 553 18.1.7 Port D IO Register L (PDIORL)....................................................................... 558 18.1.8 Port D Control Register L2 (PDCRL2)............................................................. 559 18.1.9 Port E IO Register H and L (PEIORH and PEIORL) ....................................... 561 18.1.10 Port E Control Register H1, H2, L1, and L2 (PECRH1, PECRH2, PECRL1, and PECRL2) .................................................................................................... 561 Section 19 I/O Ports............................................................................................. 569 19.1 Port A................................................................................................................................ 569 19.1.1 Register Description ......................................................................................... 569 19.1.2 Port A Data Register H (PADRH) .................................................................... 569 Port B................................................................................................................................ 571 19.2.1 Register Description ......................................................................................... 571 19.2.2 Port B Data Register L (PBDRL) ..................................................................... 571 Port C................................................................................................................................ 573 19.3.1 Register Description ......................................................................................... 574 19.3.2 Port C Data Registers H and L (PCDRH and PCDRL) .................................... 574 Port D................................................................................................................................ 576 19.4.1 Register Description ......................................................................................... 576 19.4.2 Port D Data Register L (PDDRL)..................................................................... 576 19.2 19.3 19.4 Rev. 5.00 Mar. 15, 2007 Page xviii of xxxviii 19.5 19.6 Port E ................................................................................................................................ 578 19.5.1 Register Description ......................................................................................... 579 19.5.2 Port E Data Registers H and L (PEDRH and PEDRL) ..................................... 579 Usage Notes ...................................................................................................................... 581 Section 20 User Break Controller (UBC) ............................................................583 20.1 20.2 Features............................................................................................................................. 583 Register Descriptions........................................................................................................ 585 20.2.1 Break Address Register A (BARA) .................................................................. 585 20.2.2 Break Address Mask Register A (BAMRA)..................................................... 586 20.2.3 Break Bus Cycle Register A (BBRA)............................................................... 586 20.2.4 Break Address Register B (BARB) .................................................................. 587 20.2.5 Break Address Mask Register B (BAMRB) ..................................................... 588 20.2.6 Break Data Register B (BDRB) ........................................................................ 588 20.2.7 Break Data Mask Register B (BDMRB)........................................................... 589 20.2.8 Break Bus Cycle Register B (BBRB) ............................................................... 589 20.2.9 Break Control Register (BRCR) ....................................................................... 591 20.2.10 Execution Times Break Register (BETR)......................................................... 594 20.2.11 Branch Source Register (BRSR)....................................................................... 594 20.2.12 Branch Destination Register (BRDR)............................................................... 595 Operation .......................................................................................................................... 596 20.3.1 Flow of User Break Operation .......................................................................... 596 20.3.2 Break on Instruction Fetch Cycle...................................................................... 597 20.3.3 Break on Data Access Cycle............................................................................. 597 20.3.4 Sequential Break ............................................................................................... 598 20.3.5 Value of Saved Program Counter (PC)............................................................. 598 20.3.6 PC Trace ........................................................................................................... 599 20.3.7 Usage Examples................................................................................................ 600 20.3.8 Notes ................................................................................................................. 604 20.3 Section 21 User Debugging Interface (H-UDI) ...................................................605 21.1 21.2 21.3 Features............................................................................................................................. 605 Input/Output Pins.............................................................................................................. 606 Register Descriptions........................................................................................................ 607 21.3.1 Bypass Register (SDBPR) ................................................................................ 607 21.3.2 Instruction Register (SDIR) .............................................................................. 607 21.3.3 Boundary Scan Register (SDBSR) ................................................................... 608 21.3.4 ID Register (SDID)........................................................................................... 615 Operation .......................................................................................................................... 616 21.4.1 TAP Controller ................................................................................................. 616 Rev. 5.00 Mar. 15, 2007 Page xix of xxxviii 21.4 21.5 21.6 21.4.2 Reset Configuration .......................................................................................... 617 21.4.3 TDO Output Timing ......................................................................................... 617 21.4.4 H-UDI Reset ..................................................................................................... 618 21.4.5 H-UDI Interrupt ................................................................................................ 618 Boundary Scan.................................................................................................................. 619 21.5.1 Supported Instructions ...................................................................................... 619 21.5.2 Points for Attention........................................................................................... 620 Usage Notes ...................................................................................................................... 620 Section 22 Ethernet Physical Layer Transceiver (PHY) ..................................... 621 22.1 22.2 22.3 22.4 Features............................................................................................................................. 621 Pin Configuration.............................................................................................................. 623 Top Level Functional Architecture................................................................................... 624 PHY Management Control ............................................................................................... 625 22.4.1 Serial Management Interface (SMI) ................................................................. 625 22.4.2 SMI Register Mapping...................................................................................... 632 100Base-TX Transmit....................................................................................................... 638 100Base-TX Receive ........................................................................................................ 641 10Base-T Transmit ........................................................................................................... 644 10Base-T Receive............................................................................................................. 646 MAC Interface .................................................................................................................. 647 Miscellaneous Functions................................................................................................... 651 Internal I/O Signals........................................................................................................... 655 Signals Relevant to PHY-IF ............................................................................................. 657 Usage Notes ...................................................................................................................... 658 Guidelines for Layout ....................................................................................................... 662 22.14.1 General Guidelines ........................................................................................... 662 22.14.2 Guidelines for Layout ....................................................................................... 663 22.5 22.6 22.7 22.8 22.9 22.10 22.11 22.12 22.13 22.14 Section 23 PHY Interface (PHY-IF) ................................................................... 667 23.1 23.2 Features............................................................................................................................. 667 Register Descriptions........................................................................................................ 669 23.2.1 PHY-IF Control Register (PHYIFCR).............................................................. 669 23.2.2 PHY-IF SMI Register 2 (PHYIFSMIR2) ......................................................... 670 23.2.3 PHY-IF SMI Register 3 (PHYIFSMIR3) ......................................................... 671 23.2.4 PHY-IF Address Register (PHYIFADDRR) .................................................... 671 23.2.5 PHY-IF status Register (PHYIFSR) ................................................................. 672 PHY-IF Operation ............................................................................................................ 673 23.3.1 The Procedures of Setting Up the On-Chip PHY ............................................. 673 23.3.2 The Procedures of Set Up the External PHY LSI ............................................. 674 23.3 Rev. 5.00 Mar. 15, 2007 Page xx of xxxviii Section 24 List of Registers .................................................................................675 24.1 24.2 24.3 Register Addresses (Address Order)................................................................................. 676 Register Bits...................................................................................................................... 684 Register States in Each Processing State .......................................................................... 706 Section 25 Electrical Characteristics ...................................................................713 25.1 25.2 25.3 25.4 Absolute Maximum Ratings ............................................................................................. 713 Power-On and Power-Off Order ....................................................................................... 714 DC Characteristics ............................................................................................................ 716 AC Characteristics ............................................................................................................ 718 25.4.1 Clock Timing .................................................................................................... 719 25.4.2 Control Signal Timing ...................................................................................... 723 25.4.3 AC Bus Timing................................................................................................. 725 25.4.4 Basic Timing..................................................................................................... 727 25.4.5 Synchronous DRAM Timing ............................................................................ 733 25.4.6 PCMCIA Timing .............................................................................................. 750 25.4.7 DMAC Signal Timing....................................................................................... 754 25.4.8 SCIF Timing ..................................................................................................... 755 25.4.9 SIOF Module Signal Timing ............................................................................ 756 25.4.10 Port Timing ....................................................................................................... 760 25.4.11 HIF Timing ....................................................................................................... 761 25.4.12 EtherC Timing .................................................................................................. 764 25.4.13 H-UDI Related Pin Timing............................................................................... 767 25.4.14 AC Characteristic Test Conditions ................................................................... 769 Physical Layer Ttransceiver (PHY) Characteristics (Reference Values).......................... 770 25.5 Appendix..............................................................................................................771 A. B. C. Port States in Each Pin State............................................................................................. 771 Product Code Lineup ........................................................................................................ 776 Package Dimensions ......................................................................................................... 777 Main Revisions and Additions in this Edition .....................................................779 Index ....................................................................................................................787 Rev. 5.00 Mar. 15, 2007 Page xxi of xxxviii Rev. 5.00 Mar. 15, 2007 Page xxii of xxxviii Figures Section 1 Overview Figure 1.1 Block Diagram .............................................................................................................. 7 Figure 1.2 Pin Assignments ............................................................................................................ 8 Section 2 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Section 3 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Section 7 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 CPU CPU Internal Register Configuration .......................................................................... 24 Register Data Format................................................................................................... 28 Memory Data Format .................................................................................................. 28 CPU State Transition................................................................................................... 51 Cache Cache Structure ........................................................................................................... 53 Cache Search Scheme ................................................................................................. 58 Write-Back Buffer Configuration................................................................................ 59 Specifying Address and Data for Memory-Mapped Cache Access............................. 62 Interrupt Controller (INTC) INTC Block Diagram .................................................................................................. 84 Block Diagram of IRQ7 to IRQ0 Interrupts Control................................................... 98 Interrupt Sequence Flowchart.................................................................................... 103 Stack after Interrupt Exception Handling .................................................................. 104 Bus State Controller (BSC) Block Diagram of BSC.............................................................................................. 109 Address Space ........................................................................................................... 112 Normal Space Basic Access Timing (No-Wait Access)............................................ 149 Consecutive Access to Normal Space (1): Bus Width = 16 bits, Longword Access, CSnWCR.WM = 0 (Access Wait = 0, Cycle Wait = 0) ............................................ 150 Figure 7.5 Consecutive Access to Normal Space (2): Bus Width = 16 bits, Longword Access, CSnWCR.WM = 1 (Access Wait = 0, Cycle Wait = 0) ............................................ 151 Figure 7.6 Example of 32-Bit Data-Width SRAM Connection .................................................. 152 Figure 7.7 Example of 16-Bit Data-Width SRAM Connection .................................................. 153 Figure 7.8 Example of 8-Bit Data-Width SRAM Connection.................................................... 153 Figure 7.9 Wait Timing for Normal Space Access (Software Wait Only) ................................. 154 Figure 7.10 Wait Cycle Timing for Normal Space Access | (Wait cycle Insertion using WAIT)........................................................................ 155 Figure 7.11 Example of Timing when CSn Assertion Period is Extended ................................. 156 Figure 7.12 Example of 32-Bit Data-Width SDRAM Connection ............................................. 158 Figure 7.13 Example of 16-Bit Data-Width SDRAM Connection ............................................. 159 Rev. 5.00 Mar. 15, 2007 Page xxiii of xxxviii Figure 7.14 Figure 7.15 Figure 7.16 Figure 7.17 Figure 7.18 Figure 7.19 Figure 7.20 Figure 7.21 Figure 7.22 Figure 7.23 Figure 7.24 Figure 7.25 Figure 7.26 Figure 7.27 Figure 7.28 Figure 7.29 Figure 7.30 Figure 7.31 Figure 7.32 Figure 7.33 Figure 7.34 Figure 7.35 Figure 7.36 Figure 7.37 Figure 7.38 Figure 7.39 Burst Read Basic Timing (Auto Precharge) ............................................................ 170 Burst Read Wait Specification Timing (Auto Precharge) ....................................... 171 Basic Timing for Single Read (Auto Precharge)..................................................... 172 Basic Timing for Burst Write (Auto Precharge) ..................................................... 173 Basic Timing for Single Write (Auto-Precharge).................................................... 174 Burst Read Timing (No Auto Precharge) ................................................................ 176 Burst Read Timing (Bank Active, Same Row Address) ......................................... 177 Burst Read Timing (Bank Active, Different Row Addresses) ................................ 178 Single Write Timing (No Auto Precharge).............................................................. 179 Single Write Timing (Bank Active, Same Row Address)....................................... 180 Single Write Timing (Bank Active, Different Row Addresses).............................. 181 Auto-Refreshing Timing ......................................................................................... 182 Self-Refreshing Timing........................................................................................... 184 Write Timing for SDRAM Mode Register (Based on JEDEC)............................... 186 Basic Access Timing for Byte-Selection SRAM (BAS = 0)................................... 187 Basic Access Timing for Byte-Selection SRAM (BAS = 1)................................... 188 Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only)............. 189 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM ............... 190 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM ............... 190 Example of PCMCIA Interface Connection............................................................ 192 Basic Access Timing for PCMCIA Memory Card Interface................................... 193 Wait Timing for PCMCIA Memory Card Interface (TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1)................................................................................................ 194 Example of PCMCIA Space Assignment (CS5BWCR.SA[1:0] = B'10, CS6BWCR.SA[1:0] = B'10) .................................................................................. 195 Basic Timing for PCMCIA I/O Card Interface ....................................................... 196 Wait Timing for PCMCIA I/O Card Interface (TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1) ............................... 197 Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface (TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Waits = 3) ............................ 197 Section 8 Clock Pulse Generator (CPG) Figure 8.1 Block Diagram of CPG ............................................................................................. 202 Figure 8.2 Note on Using a Crystal Resonator ........................................................................... 213 Figure 8.3 Note on Using a PLL Oscillator Circuit .................................................................... 214 Section 9 Watchdog Timer (WDT) Figure 9.1 Block Diagram of WDT ............................................................................................ 216 Figure 9.2 Writing to WTCNT and WTCSR.............................................................................. 220 Rev. 5.00 Mar. 15, 2007 Page xxiv of xxxviii Section 10 Power-Down Modes Figure 10.1 Canceling Standby Mode with STBY Bit in STBCR.............................................. 232 Section 11 Ethernet Controller (EtherC) Figure 11.1 Configuration of EtherC.......................................................................................... 234 Figure 11.2 EtherC Transmitter State Transitions ...................................................................... 254 Figure 11.3 EtherC Receiver State Transmissions...................................................................... 255 Figure 11.4 (1) MII Frame Transmit Timing (Normal Transmission)........................................ 256 Figure 11.4 (2) MII Frame Transmit Timing (Collision)............................................................ 256 Figure 11.4 (3) MII Frame Transmit Timing (Transmit Error)................................................... 257 Figure 11.4 (4) MII Frame Receive Timing (Normal Reception)............................................... 257 Figure 11.4 (5) MII Frame Receive Timing (Reception Error (1))............................................. 257 Figure 11.4 (6) MII Fame Receive Timing (Reception Error (2)) .............................................. 257 Figure 11.5 MII Management Frame Format ............................................................................. 258 Figure 11.6 (1) 1-Bit Data Write Flowchart ............................................................................... 259 Figure 11.6 (2) Bus Release Flowchart (TA in Read in Figure 11.5) ......................................... 260 Figure 11.6 (3) 1-Bit Data Read Flowchart ................................................................................ 260 Figure 11.6 (4) Independent Bus Release Flowchart (IDLE in Write in Figure 11.5)................ 261 Figure 11.7 Changing IPG and Transmission Efficiency ........................................................... 262 Figure 11.8 Example of Connection to DP83846AVHG............................................................ 263 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Figure 12.1 Configuration of E-DMAC, and Descriptors and Buffers....................................... 265 Figure 12.2 Relationship between Transmit Descriptor and Transmit Buffer ............................ 290 Figure 12.3 Relationship between Receive Descriptor and Receive Buffer ............................... 294 Figure 12.4 Sample Transmission Flowchart ............................................................................. 299 Figure 12.5 Sample Reception Flowchart................................................................................... 301 Figure 12.6 E-DMAC Operation after Transmit Error ............................................................... 302 Figure 12.7 E-DMAC Operation after Receive Error................................................................. 303 Figure 12.8 Timing of the Case where Setting of the Interrupt Source Bit in EESR by the E-DMAC Fails ............................................................................................ 304 Figure 12.9 Countermeasure by Monitoring the Transmit Descriptor in Processing of Interrupts Other than the Frame Transmit Complete (TC) Interrupt...................... 310 Figure 12.10 Method of Adding Timeout Processing................................................................. 312 Figure 12.11 Operation when E-DMAC Stops and the Transmit FIFO ..................................... 314 Figure 12.12 Processing Transmission without Handling of the TC Interrupt ........................... 317 Figure 12.13 Countermeasure for the Case with TC Interrupt-Driven Software: Addition of Timeout Processing within the Limit Imposed by the Maximum Specified Time. 320 Rev. 5.00 Mar. 15, 2007 Page xxv of xxxviii Section 13 Direct Memory Access Controller (DMAC) Figure 13.1 Block Diagram of DMAC ....................................................................................... 324 Figure 13.2 DMA Transfer Flowchart........................................................................................ 338 Figure 13.3 Round-Robin Mode................................................................................................. 342 Figure 13.4 Changes in Channel Priority in Round-Robin Mode............................................... 343 Figure 13.5 Data Flow of Dual Address Mode........................................................................... 345 Figure 13.6 Example of DMA Transfer Timing in Dual Mode (Source: Ordinary Memory, Destination: Ordinary Memory) ............................... 346 Figure 13.7 Data Flow in Single Address Mode......................................................................... 347 Figure 13.8 Example of DMA Transfer Timing in Single Address Mode ................................. 348 Figure 13.9 DMA Transfer Example in Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection)........................................................ 349 Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode (Dual Address, DREQ Low Level Detection)..................................................... 350 Figure 13.11 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection)..................................................... 350 Figure 13.12 Bus State when Multiple Channels are Operating................................................. 352 Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 353 Figure 13.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 353 Figure 13.15 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 354 Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection .................... 354 Figure 13.17 Example of DMA Transfer End in Cycle Steal Mode Level Detection ................ 355 Figure 13.18 Example of BSC Ordinary Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)............................. 356 Figure 13.19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection When DACK is Divided to 4 by Idle Cycles ........................................................ 358 Figure 13.20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection When DACK is Divided to 2 by Idle Cycles........................................................ 359 Figure 13.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When DACK is Divided to 4 by Idle Cycles ........................................................ 359 Figure 13.22 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When DACK is Divided to 2 by Idle Cycles ........................................................ 360 Section 14 Compare Match Timer (CMT) Figure 14.1 Block Diagram of Compare Match Timer............................................................... 363 Figure 14.2 Counter Operation ................................................................................................... 367 Figure 14.3 Count Timing .......................................................................................................... 367 Figure 14.4 Timing of CMF Setting ........................................................................................... 368 Figure 14.5 Conflict between Write and Compare-Match Processes of CMCNT...................... 369 Figure 14.6 Conflict between Word-Write and Count-Up Processes of CMCNT...................... 370 Rev. 5.00 Mar. 15, 2007 Page xxvi of xxxviii Figure 14.7 Conflict between Byte-Write and Count-Up Processes of CMCNT ....................... 371 Section 15 Serial Communication Interface with FIFO (SCIF) Figure 15.1 Block Diagram of SCIF........................................................................................... 375 Figure 15.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) ........................................................... 412 Figure 15.3 Sample Flowchart for SCIF Initialization ............................................................... 415 Figure 15.4 Sample Flowchart for Transmitting Serial Data ...................................................... 416 Figure 15.5 Example of Transmit Operation (8-Bit Data, Parity, One Stop Bit)........................ 418 Figure 15.6 Example of Operation Using Modem Control (CTS).............................................. 418 Figure 15.7 Sample Flowchart for Receiving Serial Data (1)..................................................... 419 Figure 15.8 Sample Flowchart for Receiving Serial Data (2)..................................................... 420 Figure 15.9 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit)................ 422 Figure 15.10 Example of Operation Using Modem Control (RTS)............................................ 422 Figure 15.11 Data Format in Synchronous Communication ...................................................... 423 Figure 15.12 Sample Flowchart for SCIF Initialization.............................................................. 425 Figure 15.13 Sample Flowchart for Transmitting Serial Data .................................................... 426 Figure 15.14 Example of SCIF Transmit Operation................................................................... 427 Figure 15.15 Sample Flowchart for Receiving Serial Data (1)................................................... 428 Figure 15.16 Sample Flowchart for Receiving Serial Data (2)................................................... 428 Figure 15.17 Example of SCIF Receive Operation .................................................................... 429 Figure 15.18 Sample Flowchart for Transmitting/Receiving Serial Data................................... 430 Figure 15.19 RTSIO Bit, RTSDT Bit, and RTS Pin................................................................... 432 Figure 15.20 CTSIO Bit, CTSDT Bit, and CTS Pin................................................................... 433 Figure 15.21 SCKIO Bit, SCKDT Bit, and SCK Pin ................................................................. 434 Figure 15.22 SPBIO Bit, SPBDT Bit, and TxD Pin ................................................................... 434 Figure 15.23 SPBDT Bit and RxD Pin ....................................................................................... 435 Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode ...................................... 437 Section 16 Serial I/O with FIFO (SIOF) Figure 16.1 Block Diagram of SIOF .......................................................................................... 442 Figure 16.2 Serial Clock Supply................................................................................................. 473 Figure 16.3 Serial Data Synchronization Timing ....................................................................... 474 Figure 16.4 SIOF Transmit/Receive Timing .............................................................................. 475 Figure 16.5 Transmit/Receive Data Bit Alignment .................................................................... 477 Figure 16.6 Control Data Bit Alignment .................................................................................... 478 Figure 16.7 Control Data Interface (Slot Position) ..................................................................... 479 Figure 16.8 Control Data Interface (Secondary FS) ................................................................... 480 Figure 16.9 Example of Transmit Operation in Master Mode.................................................... 483 Figure 16.10 Example of Receive Operation in Master Mode ................................................... 484 Figure 16.11 Example of Transmit Operation in Slave Mode .................................................... 485 Rev. 5.00 Mar. 15, 2007 Page xxvii of xxxviii Figure 16.12 Figure 16.13 Figure 16.14 Figure 16.15 Figure 16.16 Figure 16.17 Figure 16.18 Figure 16.19 Figure 16.20 Figure 16.21 Figure 16.22 Figure 16.23 Figure 16.24 Example of Receive Operation in Slave Mode ..................................................... 486 Transmit and Receive Timing (8-Bit Monaural Data (1))..................................... 490 Transmit and Receive Timing (8-Bit Monaural Data (2))..................................... 490 Transmit and Receive Timing (16-Bit Monaural Data (1))................................... 491 Transmit and Receive Timing (16-Bit Stereo Data (1)) ........................................ 491 Transmit and Receive Timing (16-Bit Stereo Data (2)) ........................................ 492 Transmit and Receive Timing (16-Bit Stereo Data (3)) ........................................ 492 Transmit and Receive Timing (16-Bit Stereo Data (4)) ........................................ 493 Transmit and Receive Timing (16-Bit Stereo Data).............................................. 493 Example of Configuration in SPI Mode ................................................................ 494 SPI Data/Clock Timing 1 (CPHA = 0).................................................................. 496 SPI Data/Clock Timing 2 (CPHA = 1).................................................................. 497 SPI Transmission/Reception Operation (Example of Full-Duplex Transmission/Reception by the CPU with TDMAE = 0) ........................................................................................................ 498 Figure 16.25 SPI Transmission Operation (Example of Half-Duplex Transmission by the CPU with TDMAE = 0)............. 499 Figure 16.26 SPI Transmission Operation (Example of Half-Duplex Transmission by DMA with TDMAE = 1) ................. 500 Figure 16.27 SPI Reception Operation (Example of Half-Duplex Reception by DMA with RDMAE = 1)...................... 501 Section 17 Host Interface (HIF) Figure 17.1 Block Diagram of HIF............................................................................................. 504 Figure 17.2 HIF Connection Example........................................................................................ 506 Figure 17.3 Basic Timing for HIF Interface ............................................................................... 522 Figure 17.4 HIFIDX Write and HIFGSR Read .......................................................................... 523 Figure 17.5 HIF Register Settings .............................................................................................. 523 Figure 17.6 Consecutive Data Writing to HIFRAM................................................................... 524 Figure 17.7 Consecutive Data Reading from HIFRAM ............................................................. 525 Figure 17.8 HIFDREQ Timing (When DMD = 0 and DPOL = 0)............................................. 526 Figure 17.9 HIFDREQ Timing (When DMD = 0 and DPOL = 1)............................................. 526 Figure 17.10 HIFDREQ Timing (When DMD = 1 and DPOL = 0) ........................................... 527 Figure 17.11 HIFDREQ Timing (When DMD = 1 and DPOL = 1) ........................................... 527 Figure 17.12 Image of High-Impedance Control of HIF Pins by HIFEBL Pin .......................... 532 Section 19 I/O Ports Figure 19.1 Port A ...................................................................................................................... 569 Figure 19.2 Port B ...................................................................................................................... 571 Figure 19.3 Port C ...................................................................................................................... 573 Figure 19.4 Port D ...................................................................................................................... 576 Rev. 5.00 Mar. 15, 2007 Page xxviii of xxxviii Figure 19.5 Port E....................................................................................................................... 578 Section 20 User Break Controller (UBC) Figure 20.1 Block Diagram of UBC........................................................................................... 584 Section 21 User Debugging Interface (H-UDI) Figure 21.1 Block Diagram of H-UDI........................................................................................ 605 Figure 21.2 TAP Controller State Transitions ............................................................................ 616 Figure 21.3 H-UDI Data Transfer Timing.................................................................................. 618 Figure 21.4 H-UDI Reset............................................................................................................ 618 Section 22 Ethernet Physical Layer Transceiver (PHY) Figure 22.1 The block Diagram around PHY Module................................................................ 622 Figure 22.2 Architectural Overview ........................................................................................... 624 Figure 22.3 How to Derive MDIO Signal from Core Signals .................................................... 625 Figure 22.4 MDIO Timing and Frame Structure (READ Cycle) ............................................... 626 Figure 22.5 MDIO Timing and Frame Structure (WRITE Cycle).............................................. 626 Figure 22.6 100Base-TX Data Path ............................................................................................ 638 Figure 22.7 Receive Data Path ................................................................................................... 641 Figure 22.8 Relationship between Received Data and Some MII Signals.................................. 643 Figure 22.9 Manchester Encoded Output ................................................................................... 645 Figure 22.10 Role of Each Bit Field (Example of Rising Waveform) Slope is Controlled in Four Segments................................................................... 661 Figure 22.11 Example of Connection with a Pulse Transformer (RJ45) .................................... 663 Section 23 PHY Interface (PHY-IF) Figure 23.1 Block Diagram of PHY-IF ...................................................................................... 668 Section 25 Electrical Characteristics Figure 25.1 External Clock Input Timing................................................................................... 720 Figure 25.2 CKIO Clock Output Timing and CK_PHY Clock Input Timing ............................ 720 Figure 25.3 Oscillation Settling Timing after Power-On............................................................ 721 Figure 25.4 Oscillation Settling Timing after Standby Mode (By Reset)................................... 721 Figure 25.5 Oscillation Settling Timing after Standby Mode (By NMI or IRQ)........................ 721 Figure 25.6 PLL Synchronize Settling Timing By Reset or NMI .............................................. 722 Figure 25.7 Reset Input Timing.................................................................................................. 723 Figure 25.8 Interrupt Input Timing............................................................................................. 724 Figure 25.9 Pin Drive Timing in Standby Mode ........................................................................ 724 Figure 25.10 Basic Bus Timing: No Wait Cycle ........................................................................ 727 Figure 25.11 Basic Bus Timing: One Software Wait Cycle ....................................................... 728 Figure 25.12 Basic Bus Timing: One External Wait Cycle ........................................................ 729 Figure 25.13 Basic Bus Timing: One Software Wait Cycle, External Wait Enabled (WM Bit = 0), No Idle Cycle............................................ 730 Rev. 5.00 Mar. 15, 2007 Page xxix of xxxviii Figure 25.14 Byte Control SRAM Timing: SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, CSnWCR.BAS = 0 (UB-/LB-Controlled Write Cycle) ...... 731 Figure 25.15 Byte Control SRAM Timing: SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, CSnWCR.BAS = 1 (WE-Controlled Write Cycle)............. 732 Figure 25.16 Synchronous DRAM Single Read Bus Cycle (Auto-Precharge, CAS Latency = 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)...... 733 Figure 25.17 Synchronous DRAM Single Read Bus Cycle (Auto-Precharge, CAS Latency = 2, WTRCD = 1 Cycle, WTRP = 1 Cycle)...... 734 Figure 25.18 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4) (Auto-Precharge, CAS Latency = 2, WTRCD = 0 Cycle, WTRP = 1 Cycle)....... 735 Figure 25.19 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4) (Auto-Precharge, CAS Latency = 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)....... 736 Figure 25.20 Synchronous DRAM Single Write Bus Cycle (Auto-Precharge, TRWL = 1 Cycle)..................................................................... 737 Figure 25.21 Synchronous DRAM Single Write Bus Cycle (Auto-Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle)................................... 738 Figure 25.22 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4) (Auto-Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle) .................................... 739 Figure 25.23 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4) (Auto-Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle) .................................... 740 Figure 25.24 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4) (Bank Active Mode: ACT + READ Commands, CAS Latency = 2, WTRCD = 0 Cycle) .............................................................................................. 741 Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4) (Bank Active Mode: READ Command, Same Row Address, CAS Latency = 2, WTRCD = 0 Cycle) .............................................................................................. 742 Figure 25.26 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4) (Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses, CAS Latency = 2, WTRCD = 0 Cycle)................................................................. 743 Figure 25.27 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4) (Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle, TRWL = 0 Cycle) ................................................................................................. 744 Figure 25.28 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4) (Bank Active Mode: WRITE Command, Same Row Address, WTRCD = 0 Cycle, TRWL = 0 Cycle) ................................................................................................. 745 Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4) (Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses, WTRCD = 0 Cycle, TRWL = 0 Cycle)................................................................. 746 Figure 25.30 Synchronous DRAM Auto-Refreshing Timing (WTRP = 1 Cycle, WTRC = 3 Cycles)................................................................. 747 Rev. 5.00 Mar. 15, 2007 Page xxx of xxxviii Figure 25.31 Figure 25.32 Figure 25.33 Figure 25.34 Figure 25.35 Figure 25.36 Figure 25.37 Figure 25.38 Figure 25.39 Figure 25.40 Figure 25.41 Figure 25.42 Figure 25.43 Figure 25.44 Figure 25.45 Figure 25.46 Figure 25.47 Figure 25.48 Figure 25.49 Figure 25.50 Figure 25.51 Figure 25.52 Figure 25.53 Figure 25.54 Figure 25.55 Figure 25.56 Figure 25.57 Figure 25.58 Figure 25.59 Figure 25.60 Figure 25.61 Figure 25.62 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle) ....................... 748 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle)............... 749 PCMCIA Memory Card Interface Bus Timing ..................................................... 750 PCMCIA Memory Card Interface Bus Timing (TED = 2.5 Cycles, TEH = 1.5 Cycles, One Software Wait Cycle, One External Wait Cycle) ..................................................................................... 751 PCMCIA I/O Card Interface Bus Timing.............................................................. 752 PCMCIA I/O Card Interface Bus Timing (TED = 2.5 Cycles, TEH = 1.5 Cycles, One Software Wait Cycle, One External Wait Cycle) ..................................................................................... 753 DREQ Input Timing.............................................................................................. 754 TENDn, DACKn Output Timing .......................................................................... 754 SCK Input Clock Timing....................................................................................... 755 SCI Input/Output Timing in Clocked Synchronous Mode .................................... 756 SIOMCLK Input Timing....................................................................................... 757 SIOF Transmit/Receive Timing (Master Mode 1/Falling Edge Sampling).......... 757 SIOF Transmit/Receive Timing (Master Mode 1/Rising Edge Sampling)........... 758 SIOF Transmit/Receive Timing (Master Mode 2/Falling Edge Sampling).......... 758 SIOF Transmit/Receive Timing (Master Mode 2/Rising Edge Sampling)........... 759 SIOF Transmit/Receive Timing (Slave Mode 1/ Slave Mode 2) ......................... 759 I/O Port Timing ..................................................................................................... 760 HIF Access Timing ............................................................................................... 762 HIFINT and HIFDREQ Timing ............................................................................ 762 HIFRDY and HIF Pin Enable/Disable Timing...................................................... 763 MII Transmission Timing (Normal Operation)..................................................... 765 MII Transmission Timing (Collision Occurred).................................................... 765 MII Reception Timing (Normal Operation) .......................................................... 766 MII Reception Timing (Error Occurred) ............................................................... 766 MDIO Input Timing .............................................................................................. 766 MDIO Output Timing ........................................................................................... 766 WOL Output Timing ............................................................................................. 767 EXOUT Output Timing......................................................................................... 767 TCK Input Timing................................................................................................. 768 TCK Input Timing in Reset Hold State ................................................................. 768 H-UDI Data Transmission Timing ........................................................................ 768 Output Load Circuit............................................................................................... 769 Appendix Figure C.1 Package Dimensions (BP-176) ................................................................................. 777 Rev. 5.00 Mar. 15, 2007 Page xxxi of xxxviii Rev. 5.00 Mar. 15, 2007 Page xxxii of xxxviii Tables Section 1 Overview Table 1.1 Features of SH7619 .................................................................................................. 2 Table 1.2 Pin Functions ............................................................................................................ 9 Table 1.3 Pin Features ............................................................................................................ 17 Section 2 CPU Table 2.1 Initial Values of Registers....................................................................................... 27 Table 2.2 Word Data Sign Extension...................................................................................... 29 Table 2.3 Delayed Branch Instructions................................................................................... 30 Table 2.4 T Bit ........................................................................................................................ 30 Table 2.5 Access to Immediate Data ...................................................................................... 31 Table 2.6 Access to Absolute Address.................................................................................... 31 Table 2.7 Access with Displacement ...................................................................................... 32 Table 2.8 Addressing Modes and Effective Addresses........................................................... 32 Table 2.9 Instruction Formats ................................................................................................. 36 Table 2.10 Instruction Types .................................................................................................... 39 Section 3 Cache Table 3.1 LRU and Way to be Replaced ................................................................................ 54 Table 3.2 Correspondence between Divided Areas and Cache............................................... 55 Section 5 Exception Handling Table 5.1 Types of Exceptions and Priority............................................................................ 67 Table 5.2 Timing for Exception Detection and Start of Exception Handling ......................... 68 Table 5.3 Vector Numbers and Vector Table Address Offsets............................................... 69 Table 5.4 Calculating Exception Handling Vector Table Addresses ...................................... 70 Table 5.5 Reset Status............................................................................................................. 71 Table 5.6 Bus Cycles and Address Errors............................................................................... 73 Table 5.7 Interrupt Sources..................................................................................................... 74 Table 5.8 Interrupt Priority ..................................................................................................... 75 Table 5.9 Types of Exceptions Triggered by Instructions ...................................................... 76 Table 5.10 Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions............... 78 Table 5.11 Stack Status after Exception Handling Ends........................................................... 79 Section 6 Interrupt Controller (INTC) Table 6.1 Pin Configuration.................................................................................................... 85 Table 6.2 Interrupt Exception Handling Vectors and Priorities............................................ 100 Table 6.3 Interrupt Response Time....................................................................................... 105 Rev. 5.00 Mar. 15, 2007 Page xxxiii of xxxviii Section 7 Bus State Controller (BSC) Table 7.1 Pin Configuration.................................................................................................. 110 Table 7.2 Address Map 1 (CMNCR.MAP = 0) .................................................................... 113 Table 7.3 Address Map 2 (CMNCR.MAP = 1) .................................................................... 113 Table 7.4 Correspondence between External Pin (MD3), Memory Type, and Bus Width for CS0......................................................................................... 114 Table 7.5 Correspondence between External Pin (MD5) and Endians................................. 114 Table 7.6 32-Bit External Device/Big Endian Access and Data Alignment......................... 143 Table 7.7 16-Bit External Device/Big Endian Access and Data Alignment......................... 144 Table 7.8 8-Bit External Device/Big Endian Access and Data Alignment........................... 145 Table 7.9 32-Bit External Device/Big Endian Access and Data Alignment......................... 146 Table 7.10 16-Bit External Device/Little Endian Access and Data Alignment ...................... 147 Table 7.11 8-Bit External Device/Little Endian Access and Data Alignment ........................ 148 Table 7.12 Relationship between Register Settings (A3BSZ[1:0], A3ROW[1:0], and A3COL[1:0]) and Address Multiplex Output (1)........................................... 160 Table 7.13 Relationship between Register Settings (A3BSZ[1:0], A3ROW[1:0], and A3COL[1:0]) and Address Multiplex Output (2)........................................... 161 Table 7.14 Relationship between Register Settings (A3BSZ[1:0], A3ROW[1:0], and A3COL[1:0]) and Address Multiplex Output (3)........................................... 163 Table 7.15 Relationship between Register Settings (A3BSZ[1:0], A3ROW[1:0], and A3COL[1:0]) and Address Multiplex Output (4)........................................... 164 Table 7.16 Relationship between Register Settings (A3BSZ[1:0], A3ROW[1:0], and A3COL[1:0]) and Address Multiplex Output (5)........................................... 165 Table 7.17 Relationship between Register Settings (A3BSZ[1:0], A3ROW[1:0], and A3COL[1:0]) and Address Multiplex Output (6)........................................... 167 Table 7.18 Relationship between Access Size and Number of Bursts.................................... 169 Table 7.19 Access Address for SDRAM Mode Register Write.............................................. 185 Section 8 Clock Pulse Generator (CPG) Table 8.1 Pin Configuration.................................................................................................. 204 Table 8.2 Mode Control Pins and Clock Operating Modes .................................................. 204 Table 8.3 Possible Combination of Clock Modes and FRQCR Values................................ 205 Section 10 Power-Down Modes Table 10.1 States of Power-Down Modes .............................................................................. 223 Table 10.2 Pin Configuration.................................................................................................. 224 Table 10.3 Register States in Software Standby Mode........................................................... 230 Section 11 Ethernet Controller (EtherC) Table 11.1 Pin Configuration.................................................................................................. 235 Rev. 5.00 Mar. 15, 2007 Page xxxiv of xxxviii Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Table 12.1 EESR Bits for which This Problem can Occur and Reflection of Interrupt Sources in the Descriptor................................................................... 305 Table 12.2 Reference Values for Maximum Specified Time.................................................. 321 Section 13 Direct Memory Access Controller (DMAC) Table 13.1 Pin Configuration.................................................................................................. 325 Table 13.2 Transfer Request Sources ..................................................................................... 336 Table 13.3 Selecting External Request Modes with RS Bits .................................................. 339 Table 13.4 Selecting External Request Detection with DL, DS Bits ...................................... 340 Table 13.5 Selecting External Request Detection with DO Bit .............................................. 340 Table 13.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits ..... 341 Table 13.7 Supported DMA Transfers.................................................................................... 344 Table 13.8 Relationship between Request Modes and Bus Modes by DMA Transfer Category .................................................................................. 351 Section 15 Serial Communication Interface with FIFO (SCIF) Table 15.1 SCIF Pins .............................................................................................................. 376 Table 15.2 SCSMR Settings ................................................................................................... 395 Table 15.3 Bit Rates and SCBRR Settings in Asynchronous Mode ....................................... 395 Table 15.4 Bit Rates and SCBRR Settings in Synchronous Mode ......................................... 398 Table 15.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) .......................................................................................... 399 Table 15.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)............... 400 Table 15.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) ................. 400 Table 15.8 SCSMR Settings and SCIF Communication Formats........................................... 411 Table 15.9 SCSMR and SCSCR Settings and SCIF Clock Source Selection......................... 411 Table 15.10 Serial Communication Formats (Asynchronous Mode).................................... 413 Table 15.11 SCIF Interrupt Sources ..................................................................................... 431 Section 16 Serial I/O with FIFO (SIOF) Table 16.1 Pin Configuration.................................................................................................. 443 Table 16.2 Operation in Each Transfer Mode......................................................................... 447 Table 16.3 SIOF Serial Clock Frequency ............................................................................... 473 Table 16.4 Serial Transfer Modes........................................................................................... 475 Table 16.5 Frame Length........................................................................................................ 476 Table 16.6 Audio Mode Specification for Transmit Data....................................................... 478 Table 16.7 Audio Mode Specification for Receive Data ........................................................ 478 Table 16.8 Setting Number of Channels in Control Data ....................................................... 479 Table 16.9 Conditions to Issue Transmit Request .................................................................. 481 Table 16.10 Conditions to Issue Receive Request ................................................................ 481 Rev. 5.00 Mar. 15, 2007 Page xxxv of xxxviii Table 16.11 Table 16.12 Table 16.13 Transmit and Receive Reset ............................................................................. 487 SIOF Interrupt Sources ..................................................................................... 488 States of Transmit and Receive Operations in SPI Mode ................................. 495 Section 17 Host Interface (HIF) Table 17.1 Pin Configuration.................................................................................................. 505 Table 17.2 HIF Operations ..................................................................................................... 506 Table 17.3 Memory Map ........................................................................................................ 521 Table 17.4 Consecutive Write Procedure to HIFRAM by External DMAC........................... 528 Table 17.5 Consecutive Read Procedure from HIFRAM by External DMAC....................... 529 Table 17.6 HIFDATA Register Alignment for Access by an External Device ...................... 531 Table 17.7 HIF Registers (other than HIFDATA) Alignment for Access by an External Device........................................................................................... 531 Table 17.8 Input/Output Control for HIF Pins........................................................................ 533 Section 18 Pin Function Controller (PFC) Table 18.1 List of Multiplexed Pins (Port A) ......................................................................... 535 Table 18.2 List of Multiplexed Pins (Port B).......................................................................... 535 Table 18.3 List of Multiplexed Pins (Port C).......................................................................... 537 Table 18.4 List of Multiplexed Pins (Port D) ......................................................................... 538 Table 18.5 List of Multiplexed Pins (Port E).......................................................................... 538 Table 18.6 Pin Functions in Each Operating Mode ................................................................ 540 Section 19 I/O Ports Table 19.1 Port A Data Register H (PADRH) Read/Write Operation.................................... 570 Table 19.2 Port B Data Register L (PBDRL) Read/Write Operation ..................................... 572 Table 19.3 Port C Data Registers H and L (PCDRH and PCDRL) Read/Write Operation .... 575 Table 19.4 Port D Data Register L (PDDRL) Read/Write Operation..................................... 577 Table 19.5 Port E Data Registers H, L (PEDRH, PEDRL) Read/Write Operation ................ 580 Section 20 User Break Controller (UBC) Table 20.1 Data Access Cycle Addresses and Operand Size Comparison Conditions........... 597 Section 21 User Debugging Interface (H-UDI) Table 21.1 Pin Configuration.................................................................................................. 606 Table 21.2 H-UDI Commands................................................................................................ 608 Table 21.3 External pins and Boundary Scan Register Bits ................................................... 609 Table 21.4 Reset Configuration .............................................................................................. 617 Section 22 Ethernet Physical Layer Transceiver (PHY) Table 22.1 Pin Configuration.................................................................................................. 623 Table 22.2 4B/5B Code Table ................................................................................................ 639 Rev. 5.00 Mar. 15, 2007 Page xxxvi of xxxviii Section 25 Electrical Characteristics Table 25.1 Absolute Maximum Ratings ................................................................................. 713 Table 25.2 Recommended Timing at Power-On..................................................................... 714 Table 25.3 Recommended Timing in Power-Off.................................................................... 715 Table 25.4 DC Characteristics (1)........................................................................................... 716 Table 25.4 DC Characteristics (2)........................................................................................... 717 Table 25.5 Permissible Output Currents ................................................................................. 718 Table 25.6 Maximum Operating Frequency ........................................................................... 718 Table 25.7 Clock Timing ........................................................................................................ 719 Table 25.8 Control Signal Timing .......................................................................................... 723 Table 25.9 Bus Timing ........................................................................................................... 725 Table 25.10 DMAC Signal Timing....................................................................................... 754 Table 25.11 SCIF Timing ..................................................................................................... 755 Table 25.12 SCIF Timing ..................................................................................................... 756 Table 25.13 Port Timing ....................................................................................................... 760 Table 25.14 HIF Timing ....................................................................................................... 761 Table 25.15 EtherC Timing .................................................................................................. 764 Table 25.16 H-UDI Related Pin Timing............................................................................... 767 Table 25.17 PHY Characteristics.......................................................................................... 770 Appendix Table A.1 Port States in Each Pin State................................................................................. 771 Rev. 5.00 Mar. 15, 2007 Page xxxvii of xxxviii Rev. 5.00 Mar. 15, 2007 Page xxxviii of xxxviii Section 1 Overview Section 1 Overview This LSI is a CMOS single-chip microcontroller that integrates a Renesas Technology original RISC (Reduced Instruction Set Computer) CPU core with peripheral functions required for an Ethernet system. The CPU of this LSI has a RISC (Reduced Instruction Set Computer) type instruction set. The CPU basically operates at a rate of one instruction per cycle, offering a great improvement in instruction execution speed. In addition, the 32-bit internal architecture provides improved data processing power. With this CPU, it has become possible to assemble low-cost and highperformance/high-functionality systems even for applications such as realtime control, which could not previously be handled by microcontrollers because of their high-speed processing requirements. This LSI is equipped with an Ethernet controller that includes a media access controller (MAC) conforming to the IEEE802.3u standard and a physical layer transceiver (PHY), enabling 10/100 Mbps LAN connection. As the equipped Ethernet controller also includes a media independent interface (MII) standard unit, a PHY LSI can be externally connected. In addition, this LSI provides on-chip peripheral functions necessary for system configuration, such as cache memory, RAM, a direct memory access controller (DMAC), timers, a serial communication interface with FIFO (SCIF), a serial IO with FIFO (SIOF), a host interface (HFI), an interrupt controller (INTC), and I/O ports. The external memory access support function of this LSI enables direct connection to various types of memory, such as standard memory, SDRAM, and PCMCIA. This greatly reduces system cost. Rev. 5.00 Mar. 15, 2007 Page 1 of 794 REJ09B0237-0500 Section 1 Overview 1.1 Features The features of this LSI are listed in table 1.1. Table 1.1 Items CPU Features of SH7619 Specification • • • • • • • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture (basic operations are executed between registers) Sixteen 32-bit general registers Five-stage pipeline On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits) executed in two to five cycles C language-oriented 62 basic instructions Some specifications on the slot illegal instruction differ from the conventional SH2 core. For details, see section 5.8, Usage Notes in section 5, Exception Handling. Note: User break controller (UBC) • • • Address, data value, access type, and data size are available for setting as break conditions Supports the sequential break function Two break channels 16 kbytes Unified cache, mixture of instructions and data 4-way set associative type Selection of write-back or write-through mode 16 kbytes U memory Cache memory • • • • • Rev. 5.00 Mar. 15, 2007 Page 2 of 794 REJ09B0237-0500 Section 1 Overview Items Bus state controller (BSC) Specification • Address space is divided into five areas: three areas 0, 3, and 4; each a maximum of 64 Mbytes, and two areas 5B and 6B; each a maximum of 32 Mbytes (address map 1 mode). Address space is divided into five areas, 0, 3, 4, 5, and 6; each a maximum of 64 Mbytes (address map 2 mode). 32-bit external bus (max.) The following features are settable for each area.  Bus size (8, 16, or 32 bits) (Area 0 does not support the bus size of 32 bits.)  Number of access wait cycles  Setting of idle wait cycles  Specifying the memory to be connected to each area enables direct connection to SRAM, SDRAM, and PCMCIA.  Outputs chip select signals (CS0, CS3, CS4, CS5B, and CS6B) for corresponding area • • • • SDRAM refresh function  Supports auto-refresh and self-refresh modes SDRAM burst access function PCMCIA access function  Conforms to the JEIDA Ver. 4.2 standard, two slots Selection of big or little endian mode (The mode of all the areas is switched collectively by a mode pin.) Four channels; external request available for two of them Burst mode and cycle steal mode Outputs a transfer end signal of the channel handling an external request Intermittent mode available (16 and 64 cycles supported) Supports nine external interrupt pins (NMI, IRQ7 to IRQ0) On-chip peripheral interrupt: Priority level is independently selected for each module Vector address: Specified vector address for each interrupt source Supports the JTAG interface emulator JTAG standard pins arranged • • • Direct memory access • controller (DMAC) • • • Interrupt controller (INTC) • • • User debugging interface (H-UDI) • • Rev. 5.00 Mar. 15, 2007 Page 3 of 794 REJ09B0237-0500 Section 1 Overview Items Specification Clock mode: Input clock can be selected from external input or crystal resonator Three types of clocks generated:  CPU clock: 125 MHz (max.)  Bus clock: 62.5 MHz (max.)  Peripheral clock: 31.25 MHz (max.) • Supports power-down modes:  Sleep mode  Software standby mode • Selection of four types of clock modes (PLL2 ×2/×4 and clock/crystal resonator are selectable) MAC (Media Access Control) function  Data frame assembly/disassembly (frame format conforming to IEEE802.3u)  CSMA/CD link management (collision prevention and collision processing)  CRC processing  512 bytes each for transmit/receive FIFO  Full-duplex transmit/receive support  Short frame/long frame detectable • Conforms to the MII (Media Independent Interface) standard  Conversion from 8-bit stream data in MAC layer to MII nibble (4-bit) stream  Station management (STA function)  18 TTL-level signals  10/100 Mbps transfer rate adjustable • TM Magic Packet * (WOL (Wake-On-LAN) output) Clock pulse generator • (CPG) • Ethernet controller (EtherC) • Ethernet controller DMAC (EDMAC) • • • • • CPU load reduced with the descriptor management method For transferring from EtherC receive FIFO to receive buffer × 1 channel For transferring from transmit buffer to EtherC transmit FIFO × 1 channel 16-byte burst transfer improves the efficiency of system bus Supports single frame and multiple buffer Rev. 5.00 Mar. 15, 2007 Page 4 of 794 REJ09B0237-0500 Section 1 Overview Items Specification Conforms to the IEEE802.3u standard. 10Base-T and 100Base-TX supported Supports Auto-negotiation and manual-negotiation modes Supports power-down modes Outputs the status of Link, Activity, Duplex, and Speed Selection of either on-chip clock oscillator output or dedicated clock externally input 1 kbyte × 2 banks: in total 2-kbyte buffer RAM The buffer RAM and the external device are connected in parallel via 16 data pins The buffer RAM and the CPU of this LSI are connected in parallel via internal bus The external device can access the desired register after the register index has been specified. (However, when the buffer RAM is accessed successively, the address is updated automatically.) Selection of endian mode Interrupt requested to the external device Internal interrupt requested to the CPU of this LSI Booting from the buffer RAM is enabled if the external device has stored the instruction code in the buffer RAM 16-bit counter Generates compare match interrupts Two channels Synchronous and asynchronous modes 16 bytes each for transmit/receive FIFO High-speed UART The UART supports FIFO stop and FIFO trigger Flow control enabled (channel 0 and channel 1 only) Three channels Ethernet physical layer • transceiver (PHY) • • • • Host interface (HIF) • • • • • • • • Compare match timer • (CMT) • • Serial communication interface with FIFO (SCIF) • • • • • • Rev. 5.00 Mar. 15, 2007 Page 5 of 794 REJ09B0237-0500 Section 1 Overview Items Serial IO with FIFO (SIOF) Specification • • • • • 64 bytes each for transmit/receive FIFO Supports 8-/16-/16-bit stereo sound input/output Can operate together with the DMAC Supports frame synchronous signals One channel 78 general input/output pins Input or output can be set per bit within the input/output common port BP1313-176 (0.8 pitch) I/O: 3.0 to 3.6 V Internal: 1.8±0.09 V (Two power sources are externally provided.) is the registered trademark of Advance Micro Devices, Inc. I/O ports Package Power supply voltage Note: * • • • • TM Magic Packet Rev. 5.00 Mar. 15, 2007 Page 6 of 794 REJ09B0237-0500 Section 1 Overview 1.2 Block Diagram Figure 1.1 is a block diagram of this LSI. SuperH CPU core User break controller (UBC) CPU bus (I clock) Cache access controller (CCN) Internal bus (B clock) Cache memory 16 kbytes U memory 16 kbytes Bus state controller (BSC) Peripheral bus controller Direct memory access controller (DMAC) External bus Direct memory access controller for Ethernet controller (E-DMAC) Transmit FIFO (512 bytes) Receive FIFO (512 bytes) Ethernet controller (EtherC) Ethernet physical layer transceiver (PHY) Peripheral bus (P clock) I/O port, Pin function controller (PFC) 1-kbyte SRAM Host interface (HIF) Serial communication interface with FIFO (SCIF)*1 Serial IO with FIFO (SIOF) Compare match timer (CMT)*2 User debugging interface (H-UDI) Interrupt controller (INTC) Powerdown mode control Watchdog timer (WDT) Clock pulse generator (CPG) Notes: 1. SCIF includes three channels. 2. CMT includes two channels. Figure 1.1 Block Diagram Rev. 5.00 Mar. 15, 2007 Page 7 of 794 REJ09B0237-0500 Section 1 Overview 1.3 Pin Assignments 1 A 2 3 4 5 6 7 8 RD 9 10 11 12 13 14 15 A VccQ PA25 PA22 PA18 PA16 PB09 Vcc VccQ A13 A11 A07 A03 A01 PB12 B VssQ PD7 PA24 PA20 PA17 PB07 Vss PB00 VssQ A15 A09 A05 A02 VssQ VccQ B C PD4 PD5 PD6 PA21 PB08 PB10 PB06 PB11 PB13 A12 A08 A04 A00 PB04 PB02 C D PD0 PD2 PD3 PA23 PA19 PB01 PB05 CS0 A14 A10 A06 PB03 RD/(WR) WE1/ DQMLU/ WE WE0/ DQMLL D E Vss Vcc PE08 PD1 Vss Vcc D09 D08 E F PE22 PE20 PE23 PE24 D13 D11 D10 D12 F G PE18 PE17 PE19 PE21 D06 D15 D14 D07 G H PE16 PE15 Vss Vcc BP1313-176 (Top view) D03 D05 VccQ VssQ H J PE13 PE11 PE12 PE14 MD2 D01 D04 D02 J K VccQ VssQ PE09 PE10 Vcc Vss D00 CKIO K L PE06 PE05 PE07 PE03 NMI ASEMD TESTMD MD1 L M PE04 PE02 PE01 PC17 TSTBUSA PC09 PC01 PC13 PC05 Vcc MD5 TDI TMS TRST RES M N PE00 PC16 Vss1A Vcc1A EXRES1 PC08 PC03 PC11 PC07 Vss PC19 TDO MD0 Vss(PLL1) Vcc(PLL1) N P PC15 PC18 Vss1A Vcc2A Vss2A PC02 VssQ PC04 PC12 PC20 CK_PHY TCK VccQ VssQ Vss(PLL2) P R TxM TxP RxM RxP Vcc3A PC00 VccQ PC10 PC06 PC14 TESTOUT MD3 EXTAL XTAL Vcc(PLL2) R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 1.2 Pin Assignments Rev. 5.00 Mar. 15, 2007 Page 8 of 794 REJ09B0237-0500 Section 1 Overview 1.4 Table 1.2 Classification Power supply Pin Functions Pin Functions Abbr. Vcc I/O Input Pin Name Description Power Supply Power supply for the internal logic of this LSI. All the Vcc pins must be connected to the system power supply. This LSI does not operate correctly if there is a pin left open. Ground Ground pins. All the Vss pins must be connected to the system power supply (0 V). This LSI does not operate correctly if there is a pin left open. Vss Input VccQ Input Power Supply Power supply for input/output pins. All the VccQ pins must be connected to the system power supply. This LSI does not operate correctly if there is a pin left open. Ground Ground pins. All the VssQ pins must be connected to the system power supply (0 V). This LSI does not operate correctly if there is a pin left open. VssQ Input Clock Vcc (PLL1) Vss (PLL1) Vcc (PLL2) Vss (PLL2) EXTAL Input Input Input Input Input Power Supply Power supply pin for the on-chip PLL1 oscillator for PLL1 Ground for PLL1 Ground pin for the on-chip PLL1 oscillator Power Supply Power supply pin for the on-chip PLL2 oscillator for PLL2 Ground for PLL2 Ground pin for the on-chip PLL2 oscillator External Clock Connects to a crystal resonator. An external clock is also input on this pin. For details on connection of an external clock, see section 8, Clock Pulse Generator (CPG). Connects to a crystal resonator. XTAL CKIO Output Crystal Output System Clock Supplies the system clock to external devices. Mode Setting These pins set operating mode. The signal levels of these pins must not be changed during operation. Pins MD2 to MD0 are used for setting clock mode, pin MD3 is for setting bus width mode for area 0, and pin MD5 is for setting endian. Power-On Reset This LSI enters the power-on reset state when this signal goes low. Input Operating MD5, MD3 to MD0 mode control System control RES Input Rev. 5.00 Mar. 15, 2007 Page 9 of 794 REJ09B0237-0500 Section 1 Overview Classification Interrupt Abbr. NMI IRQ7 to IRQ0 I/O Input Input Pin Name Description Non-Maskable Non-maskable interrupt request pin. This pin must be fixed Interrupt high when not in use. Interrupt Maskable interrupt request pins. Request 7 to 0 Level-input or edge-input detection can be selected. When the edge-input detection is selected, the rising or falling edge can also be selected. These pins output addresses. 32-bit bidirectional bus Address bus Data bus Bus control A25 to A0 D31 to D0 Output Address Bus Input/ Data Bus output CS0, CS3, Output Chip Select 0, Chip select signals for external memory and devices. 3, 4, 5B, 6B CS4, CS5B, CS6B RD RD/WR BS WE3 Output Read Output Read/Write Output Bus Cycle Start Output Most Significant Byte Write Output Second Byte Write Output Third Byte Write Output Least Significant Byte Write Input Wait Indicates that data is read from an external device. Read/write signal Indicates start of a bus cycle. Indicates that bits 31 to 24 of data of external memory or devices are written to. Indicates that bits 23 to 16 of data of external memory or devices are written to. Indicates that bits 15 to 8 of data of external memory or devices are written to. Indicates that bits 7 to 0 of data of external memory or devices are written to. Input pin used to insert wait cycles into the bus cycle when accessing the external space Connects to the RAS pin of SDRAM. Connects to the CAS pin of SDRAM. Connects to the CKE pin of SDRAM. Selects bits 31 to 24 of SDRAM data bus. WE2 WE1 WE0 WAIT RAS CAS CKE DQMUU Output RAS Output CAS Output Clock Enable Output Most Significant Byte Select Rev. 5.00 Mar. 15, 2007 Page 10 of 794 REJ09B0237-0500 Section 1 Overview Classification Bus control Abbr. DQMUL DQMLU DQMLL I/O Pin Name Description Selects bits 23 to 16 of SDRAM data bus. Selects bits 15 to 8 of SDRAM data bus. Selects bits 7 to 0 of SDRAM data bus. Output Second Byte Select Output Third Byte Select Output Least Significant Byte Select CE1A Output PCMCIA Card Chip enable for PCMCIA allocated to area 5 Select Lower Side Output PCMCIA Card Chip enable for PCMCIA allocated to area 6 Select Lower Side Output PCMCIA Card Chip enable for PCMCIA allocated to area 5 Select Upper Side Output PCMCIA Card Chip enable for PCMCIA allocated to area 6 Select Upper Side Output PCMCIA I/O Write Strobe Output PCMCIA I/O Read Strobe Connects to the PCMCIA I/O write strobe pin. Connects to the PCMCIA I/O read strobe pin. CE1B CE2A CE2B ICIOWR ICIORD WE Output PCMCIA Connects to the PCMCIA memory write strobe. Memory Write Strobe Input PCMCIA Dynamic Bus Sizing In little endian mode, this signal indicates 16-bit bus width of PCMCIA. In big endian mode, fix this pin low. IOIS16 Ethernet controller CRS COL Input Input Carrier Sense Carrier sense pin Collision Collision detect pin MII_TXD3 to Output Transmit Data 4-bit transmit data pins MII_TXD0 TX_EN Output Transmit Enable Indicates that transmit data is on pins MII_TXD3 to MII_TXD0. Rev. 5.00 Mar. 15, 2007 Page 11 of 794 REJ09B0237-0500 Section 1 Overview Classification Ethernet controller Abbr. TX_CLK TX_ER MII_RXD3 to MII_RXD0 RX_DV RX_CLK RX_ER MDC MDIO WOL I/O Input Pin Name Transmit Clock Description Timing reference input for the TX_EN, TX_ER, and MII_TXD3 to MII_TXD0 pins Output Transmit Error Informs PHY LSI of an error during transmission. Input Receive Data 4-bit receive data pins Input Input Input Receive Data Indicates that valid receive data is on pins MII_RXD3 to Valid MII_RXD0. Receive Clock Timing reference input for the RX_DV, RX_ER, and MII_RXD3 to MII_RXD0 pins Receive Error Pin for detection of an error during reception Timing reference input for transfer information on the MDIO pin Bidirectional pin for management information transfer Indicates that a Magic Packet* has received. Output Management Clock Input/ Management output Data I/O Output MAGIC Packet Receive Input Link Status LNKSTA EXOUT Direct memory access controller DREQ1, DREQ0 DACK1, DACK0 TEND1, TEND0 Serial communication interface with FIFO TXD2 to TXD0 RXD2 to RXD0 SCK2 to SCK0 RTS1 and RTS0 Input pin for a link state from a PHY LSI. Output pin to external devices Input pins for external DMA transfer request Request receive output pins for external DMA transfer request Output pins for DMA transfer end signal Output General Output Input DMA transfer request Output DMA transfer request receive Output DMA transfer end Output Transmit Data Transmit data pins Input Receive Data Receive data pins Clock input pins Modem control pins. Supported only by SCIF0 and SCIF1. Input/ Serial Clock output Output Transmit Request Rev. 5.00 Mar. 15, 2007 Page 12 of 794 REJ09B0237-0500 Section 1 Overview Classification Abbr. I/O Input Pin Name Transmit Enable Description Modem control pins. Supported only by SCIF0 and SCIF1. CTS1 and Serial Communi- CTS0 cation interface with FIFO Serial I/O SIOMCLK0 with FIFO SCK_SIO0 Input SIOF0 clock input Master clock input pin Input/output pin for communication clock common to transmit/receive Input/output pin for frame synchronization signal common to transmit/receive Transmit data Input/ SIOF0 output communication clock SIOFSYNC0 Input/ SIOF0 frame output sync Output SIOF0 transmit data Input TXD_SIO0 RXD_SIO0 Host interface HIFD15 to HIFD00 HIFCS HIFRS HIFWR HIFRD HIFINT HIFMD HIFDREQ SIOF0 receive Receive data data Input/ HIF Data Bus Address, data, and command input/output pins for the HIF. output Input Input Input Input HIF Chip Select HIF Register Select HIF Write HIF Read Chip select input for the HIF. Controls the access type switching for the HIF. Write strobe signal Read strobe signal Interrupt request to external devices by the HIF. Specifies HIF boot mode. Requests DMAC transfer for the HIFRAM to external devices. Output HIF Interrupt Input HIF Mode Output HIF DMAC Transfer Request Output HIF Boot Ready Input HIF Pin Enable HIFRDY HIFEBL Indicates that a reset of the HIF has been cleared in this LSI and the HIF is ready for accesses to it. HIF pins other than this pin are enabled by driving this pin high. Rev. 5.00 Mar. 15, 2007 Page 13 of 794 REJ09B0237-0500 Section 1 Overview Classification Abbr. I/O Input Input Input Pin Name Test Clock Test Mode Select Test Data Input Description Test clock input pin Input pin for test mode select signal Serial input pin for an instruction and data Serial output pin for an instruction and data Input pin for initialization Pins for 10-bit general input/output port Pins for 14-bit general input/output port Pins for 21-bit general input/output port Pins for 8-bit general input/output port Pins for 25-bit general input/output port Specifies ASE mode. This LSI enters ASE mode when this signal goes low and normal mode when this pin goes high. In ASE mode, functions for the emulator are available. TCK User debugging TMS interface (H-UDI) TDI TDO TRST I/O ports PA25 to PA16 PB13 to PB00 PC20 to PC00 PD07 to PD00 PE24 to PE00 Emulator interface ASEMD Output Test Data Output Input Test Reset Input/ General Port output Input/ General Port output Input/ General Port output Input/ General Port output Input/ General Port output Input ASE Mode Test mode TESTMD Input Test Mode Specifies test mode. This LSI enters test mode when this signal goes low. Fix this signal high. TESTOUT Physical layer transceiver (PHY) Vcc1A Output Test Output Input Output pin for testing. This pin should be open. Analog Power Analog power supply pin for the PHY Supply 1 for PHY Analog Power Analog power supply pin for the PHY Supply 2 for PHY Vcc2A Input Rev. 5.00 Mar. 15, 2007 Page 14 of 794 REJ09B0237-0500 Section 1 Overview Classification Physical layer transceiver (PHY) Abbr. Vcc3A I/O Input Pin Name Description Analog Power Analog power supply pin for the PHY Supply 3 for PHY Analog Ground 1 for PHY Analog Ground 2 for PHY PHY Clock Analog ground pin for the PHY Vss1A Input Vss2A Input Analog ground pin for the PHY CK_PHY Input This pins is used to externally supply clocks to the PHY. When clocks are supplied to the on-chip PHY from the onchip clock pulse generator (CPG), this pins should be pulled up to VccQ or pulled down to VssQ. TxP Differential transmit output (+) for the Ethernet circuit by the Output Differential Transmit Data PHY. (+) Differential transmit output (-) for the Ethernet circuit by the Output Differential Transmit Data PHY. (-) Input Differential receive input (+) for the PHY by the Ethernet Differential Receive Data circuit. (+) Differential receive input (-) for the PHY by the Ethernet Differential Receive Data circuit. (-) TxM RxP RxM Input Rev. 5.00 Mar. 15, 2007 Page 15 of 794 REJ09B0237-0500 Section 1 Overview Classification Physical layer transceiver (PHY) Abbr. SPEED100 LINK CRS DUPLEX EXRES1 TSTBUSA I/O Pin Name Description Monitor output pins indicating communication status Output SPEED100 signal Output LINK signal Output CRS signal Output DUPLEX signal Input Reference resistor Connect to the PHY analog ground through a 12.4-kΩ (accuracy: 1%) resistor. Input/output pin for testing the on-chip IEEE802.3u PHY. This pin should be open. Input/ Test I/O output Notes Fix all unused pins that have no weak keeper circuit to high or low level. Unused pins that internally have weak keeper circuit need not to be fixed to high or low level. The weak keeper is a circuit that is included in I/O pins and fixes the input pins to high or low when I/O pins are not driven from outside. * Magic Packet is the trademark of Advanced Micro Devices, Inc. Rev. 5.00 Mar. 15, 2007 Page 16 of 794 REJ09B0237-0500 Section 1 Overview Table 1.3 Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 Pin Features Pin Name VccQ PA25/A25/SIOFSYNC0 PA22/A22/SIOMCLK0 PA18/A18 PA16/A16 PB09/CE2A Vcc RD VccQ A13 A11 A07 A03 A01 PB12/CS3 VssQ PD7/IRQ7/SCK2 PA24/A24/TXD_SIO0 PA20/A20 PA17/A17 PB07/CE2B Vss PB00/WAIT VssQ A15 A09 A05 A02 VssQ VccQ I/O Features Power IO/O/IO IO/O/I IO/O IO/O IO/O Power O Power O O O O O IO/O Power IO/I/IO IO/O/O IO/O IO/O IO/O Power IO/I Power O O O O Power Power Rev. 5.00 Mar. 15, 2007 Page 17 of 794 REJ09B0237-0500 Section 1 Overview Pin No. C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E1 E2 Pin Name PD4/IRQ4/SCK1 PD5/IRQ5/TxD2/DREQ1 PD6/IRQ6/RxD2/DACK1 PA21/A21/SCK_SIO0 PB08/CS6B/CE1B PB10/CS5B/CE1A PB06/WE3 (BE3)/DQMUU/ICIOWR PB11/CS4 PB13/BS A12 A08 A04 A00 PB04/RAS PB02/CKE PD0/IRQ0/-/TEND0 PD2/IRQ2/TxD1/DREQ0 PD3/IRQ3/RxD1/DACK0 PA23/A23/RXD_SIO0 PA19/A19 PB01/IOIS16 PB05/WE2 (BE2)/DQMUL/ICIORD CS0 A14 A10 A06 PB03/CAS RD/WR WE1/DQMLU/WE WE0/DQMLL Vss Vcc I/O Features IO/I/IO IO/I/O/I IO/I/I/O IO/O/IO IO/O/O IO/O/O IO/O/O/O IO/O IO/O O O O O IO/O IO/O IO/I/-/O IO/I/O/I IO/I/I/O IO/O/I IO/O IO/I IO/O/O/O O O O O IO/O O O/O/O O/O Power Power Rev. 5.00 Mar. 15, 2007 Page 18 of 794 REJ09B0237-0500 Section 1 Overview Pin No. E3 E4 E12 E13 E14 E15 F1 F2 F3 F4 F12 F13 F14 F15 G1 G2 G3 G4 G12 G13 G14 G15 H1 H2 H3 H4 H12 H13 H14 H15 J1 J2 Pin Name PE08/HIFCS PD1/IRQ1/-/TEND1 Vss Vcc D09 D08 PE22/HIFD13/CTS0/D29 PE20/HIFD11/SCK1/D27 PE23/HIFD14/RTS1/D30 PE24/HIFD15/CTS1/D31 D13 D11 D10 D12 PE18/HIFD09/TxD1/D25 PE17/HIFD08/SCK0/D24 PE19/HIFD10/RxD1/D26 PE21/HIFD12/RTS0/D28 D06 D15 D14 D07 PE16/HIFD07/RxD0/D23 PE15/HIFD06/TxD0/D22 Vss Vcc D03 D05 VccQ VssQ PE13/HIFD04/-/D20 PE11/HIFD02/-/D18 I/O Features IO/I IO/I/-/O Power Power IO IO IO/IO/I/IO IO/IO/IO/IO IO/IO/O/IO IO/IO/I/IO IO IO IO IO IO/IO/O/IO IO/IO/IO/IO IO/IO/I/IO IO/IO/O/IO IO IO IO IO IO/IO/I/IO IO/IO/O/IO Power Power IO IO Power Power IO/IO/-/IO IO/IO/-/IO Rev. 5.00 Mar. 15, 2007 Page 19 of 794 REJ09B0237-0500 Section 1 Overview Pin No. J3 J4 J12 J13 J14 J15 K1 K2 K3 K4 K12 K13 K14 K15 L1 L2 L3 L4 L12 L13 L14 L15 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 Pin Name PE12/HIFD03/-/D19 PE14/HIFD05/-/D21 MD2 D01 D04 D02 VccQ VssQ PE09/HIFD00/-/D16 PE10/HIFD01/-/D17 Vcc Vss D00 CKIO PE06/HIFWR/SIOFSYNC0 PE05/HIFRD PE07/HIFRS PE03/HIFMD NMI ASEMD TESTMD MD1 PE04/HIFINT/TXD_SIO0 PE02/HIFDREQ/RXD_SIO0 PE01/HIFRDY/SIOMCLK0 PC17/MDC TSTBUSA PC09/RX_ER PC01/MII_RXD1 PC13/TX_CLK PC05/MII_TXD1/-/LINK Vcc I/O Features IO/IO/-/IO IO/IO/-/IO I IO IO IO Power Power IO/IO/-/IO IO/IO/-/IO Power Power IO O IO/I/IO IO/I IO/I IO/I I I I I IO/O/O IO/O/I IO/O/I IO/O IO IO/I IO/I IO/I IO/O/-/O Power Rev. 5.00 Mar. 15, 2007 Page 20 of 794 REJ09B0237-0500 Section 1 Overview Pin No. M11 M12 M13 M14 M15 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 Pin Name MD5 TDI TMS TRST RES PE00/HIFEBL/SCK_SIO0 PC16/MDIO Vss1A Vcc1A EXRES1 PC08/RX_DV PC03/MII_RXD3 PC11/TX_ER PC07/MII_TXD3/-/DUPLEX Vss PC19/EXOUT TDO MD0 Vss (PLL1) Vcc (PLL1) PC15/CRS PC18/LNKSTA Vss1A Vcc2A Vss2A PC02/MII_RXD2 VssQ PC04/MII_TXD0/-/SPEED100 PC12/TX_EN PC20/WOL CK_PHY TCK I/O Features I I I I I IO/I/IO IO/IO Power Power I IO/I IO/I IO/O IO/O/-/O Power IO/O O I Power Power IO/I IO/I Power Power Power IO/I Power IO/O/-/O IO/O IO/O I I Rev. 5.00 Mar. 15, 2007 Page 21 of 794 REJ09B0237-0500 Section 1 Overview Pin No. P13 P14 P15 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Pin Name VccQ VssQ Vss (PLL2) TxM TxP RxM RxP Vcc3A PC00/MII_RXD0 VccQ PC10/RX_CLK PC06/MII_TXD2/-/CRS PC14/COL TESTOUT MD3 EXTAL XTAL Vcc (PLL2) I/O Features Power Power Power O O I I Power IO/I Power IO/I IO/O/-/O IO/I O I I O Power Rev. 5.00 Mar. 15, 2007 Page 22 of 794 REJ09B0237-0500 Section 2 CPU Section 2 CPU 2.1 Features • General registers: 32-bit register × 16 • Basic instructions: 62 • Addressing modes: 11 Register direct (Rn) Register indirect (@Rn) Post-increment register indirect (@Rn+) Pre-decrement register indirect (@-Rn) Register indirect with displacement (@disp:4, Rn) Index register indirect (@R0, Rn) GBR indirect with displacement (@disp:8, GBR) Index GBR indirect (@R0, GBR) PC relative with displacement (@disp:8, PC) PC relative (disp:8/disp:12/Rn) Immediate (#imm:8) 2.2 Register Configuration There are three types of registers: general registers (32-bit × 16), control registers (32-bit × 3), and system registers (32-bit × 4). Rev. 5.00 Mar. 15, 2007 Page 23 of 794 REJ09B0237-0500 Section 2 CPU General register (Rn) 31 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)0*2 0 Status register (SR) 31 9 8765 43 210 M Q I3 I2 I1 I0 ST Global base register (GBR) 31 GBR 0 Vector base register (VBR) 31 VBR 0 Multiply and accumulate register (MAC) 31 MACH MACL 0 Procedure register (PR) 31 PR 0 Program counter (PC) 31 PC 0 Notes: 1. R0 can be used as an index register in index register indirect or index GBR indirect addressing mode. For some instructions, only R0 is used as the source or destination register. 2. R15 is used as a hardware stack pointer during exception handling. Figure 2.1 CPU Internal Register Configuration Rev. 5.00 Mar. 15, 2007 Page 24 of 794 REJ09B0237-0500 Section 2 CPU 2.2.1 General Registers (Rn) There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are used for data processing and address calculation. R0 is also used as an index register. With a number of instructions, R0 is the only register that can be used. R15 is used as a hardware stack pointer (SP). In exception handling, R15 is used for accessing the stack to save or restore the status register (SR) and program counter (PC) values. 2.2.2 Control Registers There are three 32-bit control registers, designated status register (SR), global base register (GBR), and vector base register (VBR). SR indicates a processing state. GBR is used as a base address in GBR indirect addressing mode for data transfer of on-chip peripheral module registers. VBR is used as a base address of the exception handling (including interrupts) vector table. • Status register (SR) Bit 31 to 10 Bit name  Default All 0 Read/ Write R/W Description Reserved These bits are always read as 0. The write value should always be 0. 9 8 7 6 5 4 3, 2 M Q I3 I2 I1 I0  Undefined Undefined 1 1 1 1 All 0 R/W R/W R/W R/W R/W R/W R/W Reserved These bits are always read as 0. The write value should always be 0. 1 S Undefined R/W S Used by the multiply and accumulate instruction. Used by the DIV0U, DIV0S, and DIV1 instructions. Used by the DIV0U, DIV0S, and DIV1 instructions. Interrupt Mask Rev. 5.00 Mar. 15, 2007 Page 25 of 794 REJ09B0237-0500 Section 2 CPU Bit 0 Bit name T Default Undefined Read/ Write R/W Description T Indicates true (1) or false (0) in the following instructions: MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, CLRT Indicates carry, borrow, overflow, or underflow in the following instructions: ADDV, ADDC, SUBV, SUBC, NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, ROTCL • Global-base register (GBR) This register indicates a base address in GBR indirect addressing mode. The GBR indirect addressing mode is used for data transfer of the on-chip peripheral module registers and logic operations. • Vector-base register (VBR) This register indicates the base address of the exception handling vector table. 2.2.3 System Registers There are four 32-bit system registers, designated two multiply and accumulate registers (MACH and MACL), a procedure register (PR), and program counter (PC). • Multiply and accumulate registers (MAC) This register stores the results of multiplication and multiply-and-accumulate operation. • Procedure register (PR) This register stores the return-destination address from subroutine procedures. • Program counter (PC) The PC indicates the point which is four bytes (two instructions) after the current execution instruction. Rev. 5.00 Mar. 15, 2007 Page 26 of 794 REJ09B0237-0500 Section 2 CPU 2.2.4 Initial Values of Registers Table 2.1 lists the initial values of registers after a reset. Table 2.1 Initial Values of Registers Register R0 to R14 R15 (SP) Control register SR Default Undefined SP value set in the exception handling vector table I3 to I0: 1111 (H'F) Reserved bits: 0 Other bits: Undefined GBR VBR System register MACH, MACL, PR PC Undefined H'00000000 Undefined PC value set in the exception handling vector table Type of register General register Rev. 5.00 Mar. 15, 2007 Page 27 of 794 REJ09B0237-0500 Section 2 CPU 2.3 2.3.1 Data Formats Register Data Format The size of register operands is always longwords (32 bits). When loading byte (8 bits) or word (16 bits) data in memory into a register, the data is sign-extended to longword and stored in the register. 31 Longword 0 Figure 2.2 Register Data Format 2.3.2 Memory Data Formats Memory data formats are classified into byte, word, and longword. Byte data can be accessed from any address. If word data starting from boundary other than 2n or longword data starting from a boundary other than 4n is accessed, an address error will occur. In such cases, the data accessed cannot be guaranteed. See figure 2.3. Address A + 1 Address A 31 Address A Address A + 4 Address A + 8 Byte 0 23 Byte 1 Address A + 3 31 Byte 3 Address A + 10 Address A + 11 0 Byte 3 23 Byte 2 Address A + 8 Address A + 2 15 Byte 2 7 Address A + 9 15 Byte 1 7 Byte 0 0 Address A + 8 Address A + 4 Address A Word 0 Longword Big endian Word 1 Word 1 Longword Little endian Word 0 Figure 2.3 Memory Data Format Either big endian and little endian formats can be selected according to the mode pin setting at a reset. For details on mode pin settings, see section 7, Bus State Controller (BSC). Rev. 5.00 Mar. 15, 2007 Page 28 of 794 REJ09B0237-0500 Section 2 CPU 2.3.3 Immediate Data Formats Immediate data of eight bits is placed in the instruction code. For the MOV, ADD, and CMP/EQ instructions, the immediate data is sign-extended to longword and then calculated. For the TST, AND, OR, and XOR instructions, the immediate data is zeroextended to longword and then calculated. Thus, if the immediate data is used for the AND instruction, the upper 24 bits in the destination register are always cleared. The immediate data of word or longword is not placed in the instruction code. It is placed in a table in memory. The table in memory is accessed by the MOV immediate data instruction in PC relative addressing mode with displacement. 2.4 2.4.1 Features of Instructions RISC Type The instructions are RISC-type instructions with the following features: Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code efficiency. One Instruction per Cycle: Since pipelining is used, basic instructions can be executed in one cycle. One cycle is 25ns with 40 MHz operation. Data Size: The basic data size for operations is longword. Byte, word, or longword can be selected as the memory access size. Byte or word data in memory is sign-extended to longword and then calculated. Immediate data is sign-extended to longword for arithmetic operations or zero-extended to longword size for logical operations. Table 2.2 Word Data Sign Extension Description Sign-extended to 32 bits, R1 becomes H'00001234, and is then operated on by the ADD instruction. Example of Other CPUs ADD.W #H'1234,R0 CPU in this LSI MOV.W ADD @(disp,PC),R1 R1,R0 ........ .DATA.W H'1234 Note: * Immediate data is accessed by @(disp,PC). Rev. 5.00 Mar. 15, 2007 Page 29 of 794 REJ09B0237-0500 Section 2 CPU Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a register (load/store architecture). However, bit manipulation instructions such as AND are executed directly in memory. Delayed Branching: Unconditional branch instructions mean the delayed branch instructions. With a delayed branch instruction, the branch is made after execution of the instruction immediately following the delayed branch instruction. This minimizes disruption of the pipeline when a branch is made. The conditional branch instructions have two types of instructions: conditional branch instructions and delayed branch instructions. Table 2.3 Delayed Branch Instructions Description ADD is executed before branch to TRGET. Example of Other CPUs ADD.W R1,R0 BRA TRGET CPU in this LSI BRA ADD TRGET R1,R0 Multiply/Multiply-and-Accumulate Operations: A 16 × 16 → 32 multiply operation is executed in one to two cycles, and a 16 × 16 + 64 → 64 multiply-and-accumulate operation in two to three cycles. A 32 × 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply-andaccumulate operation are each executed in two to four cycles. T Bit: The result of a comparison is indicated by the T bit in SR, and a conditional branch is performed according to whether the result is True or False. Processing speed has been improved by keeping the number of instructions that modify the T bit to a minimum. Table 2.4 T Bit Description When R0 ≥ R1, the T bit is set. Example of Other CPUs CMP.W R1,R0 TRGET0 TRGET1 TRGET CPU in this LSI CMP/GE BT BF ADD CMP/EQ BT R1,R0 TRGET0 TRGET1 #−1,R0 #0,R0 TRGET When R0 ≥ R1, a branch is made to TRGET0. BGE When R0 < R1, a branch is made to TRGET1. BLT The T bit is not changed by ADD. When R0 = 0, the T bit is set. A branch is made when R0 = 0. BEQ SUB.W #1,R0 Rev. 5.00 Mar. 15, 2007 Page 30 of 794 REJ09B0237-0500 Section 2 CPU Immediate Data: 8-bit immediate data is placed in the instruction code. Word and longword immediate data is not placed in the instruction code. It is placed in a table in memory. The table in memory is accessed with the MOV immediate data instruction using PC relative addressing mode with displacement. Table 2.5 Type 8-bit immediate 16-bit immediate Access to Immediate Data This LSI's CPU MOV #H'12,R0 ........ .DATA.W H'1234 Example of Other CPU MOV.B #H'12,R0 MOV.W @(disp,PC),R0 MOV.W #H'1234,R0 32-bit immediate MOV.L @(disp,PC),R0 ........ MOV.L #H'12345678,R 0 .DATA.L H'12345678 Note: * Immediate data is accessed by @(disp,PC). Absolute Addresses: When data is accessed by absolute address, place the absolute address value in a table in memory beforehand. The absolute address value is transferred to a register using the method whereby immediate data is loaded when an instruction is executed, and the data is accessed using the register indirect addressing mode. Table 2.6 Type Absolute address Access to Absolute Address CPU in this LSI MOV.L MOV.B @(disp,PC),R1 @R1,R0 ........ .DATA.L H'12345678 Example of Other CPUs MOV.B @H'12345678,R0 Note: * Immediate data is referenced by @(disp,PC). 16-Bit/32-Bit Displacement: When data is accessed using the 16- or 32-bit displacement addressing mode, the displacement value is placed in a table in memory beforehand. Using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is accessed using index register indirect addressing mode. Rev. 5.00 Mar. 15, 2007 Page 31 of 794 REJ09B0237-0500 Section 2 CPU Table 2.7 Type Access with Displacement CPU in this LSI MOV.W @(disp,PC),R0 MOV.W @(R0,R1),R2 ........ .DATA.W H'1234 Example of Other CPUs MOV.W @(H'1234,R1),R 2 16-bit displacement Note: * Immediate data is referenced by @(disp,PC). 2.4.2 Addressing Modes Table 2.8 lists addressing modes and effective address calculation methods. Table 2.8 Addressing Mode Register direct Register indirect Addressing Modes and Effective Addresses Instruction Format Effective Address Calculation Method Rn @Rn Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents. Rn Rn Calculation Formula  Rn Rn After instruction execution Byte: Rn + 1 → Rn Word: Rn + 2 → Rn Longword: Rn + 4 → Rn Register @Rn+ indirect with post-increment Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, and 4 for a longword operand. Rn Rn + 1/2/4 + 1/2/4 Rn Register indirect with pre-decrement @–Rn Byte: Rn – 1 → Rn Effective address is register Rn contents, decremented by a constant beforehand: 1 for a Word: Rn – 2 → Rn byte operand, 2 for a word operand, 4 for a Longword: Rn – 4 longword operand. → Rn Rn Rn - 1/2/4 1/2/4 Rn - 1/2/4 (Instruction executed with Rn after calculation) Rev. 5.00 Mar. 15, 2007 Page 32 of 794 REJ09B0237-0500 Section 2 CPU Addressing Mode Register indirect with displacement Instruction Format Effective Address Calculation Method @(disp:4, Rn) Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. Rn disp (zero-extended) × 1/2/4 Calculation Formula Byte: Rn + disp Word: Rn + disp × 2 Longword: Rn + disp × 4 + Rn + disp × 1/2/4 Index @(R0, Rn) Effective address is sum of register Rn and R0 register indirect contents. Rn Rn + R0 + R0 Rn + R0 GBR indirect with displacement @(disp:8, GBR) Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. GBR disp (zero-extended) × 1/2/4 Byte: GBR + disp Word: GBR + disp ×2 Longword: GBR + disp × 4 + GBR + disp × 1/2/4 Index GBR indirect @(R0, GBR) Effective address is sum of register GBR and R0 contents. GBR GBR + R0 + R0 GBR + R0 Rev. 5.00 Mar. 15, 2007 Page 33 of 794 REJ09B0237-0500 Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation Method Effective address is PC with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. PC & H'FFFFFFFC disp (zero-extended) * PC + disp × 2 or PC& H'FFFFFFFC + disp × 4 *With longword operand Calculation Formula Word: PC + disp ×2 Longword: PC&H'FFFFFFFC + disp × 4 PC relative with @(disp:8, displacement PC) + × 2/4 PC relative disp:8 Effective address is PC with 8-bit displacement PC + disp × 2 disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) × 2 + PC + disp × 2 disp:12 Effective address is PC with 12-bit displacement disp added after being signextended and multiplied by 2. PC disp (sign-extended) × 2 PC + disp × 2 + PC + disp × 2 Rev. 5.00 Mar. 15, 2007 Page 34 of 794 REJ09B0237-0500 Section 2 CPU Addressing Mode PC relative Instruction Format Effective Address Calculation Method Rn Effective address is sum of PC and Rn. PC Calculation Formula PC + Rn + Rn PC + Rn Immediate #imm:8 #imm:8 #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended.   8-bit immediate data imm of TRAPA instruction  is zero-extended and multiplied by 4. 2.4.3 Instruction Formats This section describes the instruction formats, and the meaning of the source and destination operands. The meaning of the operands depends on the instruction code. The following symbols are used in the table. xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement Rev. 5.00 Mar. 15, 2007 Page 35 of 794 REJ09B0237-0500 Section 2 CPU Table 2.9 Instruction Formats Source Operand  Destination Operand  Sample Instruction NOP Instruction Format 0 type 15 0 xxxx xxxx xxxx xxxx n type 15 0 xxxx nnnn xxxx xxxx  nnnn: register direct MOVT Rn STS MACH,Rn Control register or nnnn: register system register direct Control register or nnnn: preSTC.L SR,@-Rn system register decrement register indirect m type 15 0 xxxx mmmm xxxx xxxx mmmm: register direct Control register or LDC Rm,SR system register mmmm: postControl register or LDC.L @Rm+,SR increment register system register indirect mmmm: register indirect PC relative using Rm   JMP @Rm BRAF Rm Rev. 5.00 Mar. 15, 2007 Page 36 of 794 REJ09B0237-0500 Section 2 CPU Instruction Format nm type 15 0 xxxx nnnn mmmm xxxx Source Operand mmmm: register direct mmmm: register direct Destination Operand nnnn: register direct nnnn: register indirect Sample Instruction ADD Rm,Rn MOV.L Rm,@Rn MAC.W @Rm+,@Rn+ mmmm: postMACH, MACL increment register indirect (multiplyand-accumulate operation) nnnn: * postincrement register indirect (multiplyand-accumulate operation) mmmm: postnnnn: register increment register direct indirect mmmm: register direct mmmm: register direct md type 15 0 xxxx xxxx mmmm dddd MOV.L @Rm+,Rn nnnn: preMOV.L Rm,@-Rn decrement register indirect nnnn: index register indirect MOV.L Rm,@(R0,Rn) mmmmdddd: R0 (register direct) MOV.B @(disp,Rm),R0 register indirect with displacement R0 (register direct) nnnndddd: MOV.B R0,@(disp,Rn) register indirect with displacement mmmm: register direct nnnndddd: MOV.L Rm,@(disp,Rn) register indirect with displacement MOV.L @(disp,Rm),Rn nd4 type 15 0 xxxx xxxx nnnn dddd nmd type 15 0 xxxx nnnn mmmm dddd mmmmdddd: nnnn: register register indirect direct with displacement Rev. 5.00 Mar. 15, 2007 Page 37 of 794 REJ09B0237-0500 Section 2 CPU Instruction Format d type 15 0 xxxx xxxx dddd dddd Source Operand dddddddd: GBR indirect with displacement Destination Operand Sample Instruction R0 (register direct) MOV.L @(disp,GBR),R0 R0 (register direct) dddddddd: GBR indirect with displacement dddddddd: PC relative with displacement  d12 type 15 0 xxxx dddd dddd dddd MOV.L R0,@(disp,GBR) R0 (register direct) MOVA @(disp,PC),R0 dddddddd: PC relative dddddddddddd: PC relative nnnn: register direct BF label BRA label (label=disp+PC) MOV.L @(disp,PC),Rn  nd8 type 15 0 xxxx nnnn dddd dddd dddddddd: PC relative with displacement iiiiiiii: immediate iiiiiiii: immediate iiiiiiii: immediate i type 15 0 xxxx xxxx iiii iiii Index GBR indirect AND.B #imm,@(R0,GBR) R0 (register direct) AND #imm,R0  nnnn: register direct TRAPA #imm ADD #imm,Rn ni type 15 0 xxxx nnnn iiii iiii iiiiiiii: immediate Note: * In multiply and accumulate instructions, nnnn is the source register. Rev. 5.00 Mar. 15, 2007 Page 38 of 794 REJ09B0237-0500 Section 2 CPU 2.5 2.5.1 Instruction Set Instruction Set by Type Table 2.10 lists the instructions classified by type. Table 2.10 Instruction Types Type Data transfer instructions Kinds of Instruction 5 Op Code MOV Function Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer MOVA MOVT SWAP XTRCT Arithmetic operation instructions 21 ADD ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL Effective address transfer T bit transfer Upper/lower swap Extraction of middle of linked registers Binary addition Binary addition with carry Binary addition with overflow Comparison Division Signed division initialization Unsigned division initialization Signed double-precision multiplication Unsigned double-precision multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate, doubleprecision multiply-and-accumulate Double-precision multiplication 33 Number of Instructions 39 Rev. 5.00 Mar. 15, 2007 Page 39 of 794 REJ09B0237-0500 Section 2 CPU Type Arithmetic operation instructions Kinds of Instruction 21 Op Code MULS MULU NEG NEGC SUB SUBC SUBV Function Signed multiplication Unsigned multiplication Sign inversion Sign inversion with borrow Binary subtraction Binary subtraction with carry Binary subtraction with underflow Logical AND Bit inversion Logical OR Memory test and bit setting T bit setting for logical AND Exclusive logical OR 1-bit left shift 1-bit right shift 1-bit left shift with T bit 1-bit right shift with T bit Arithmetic 1-bit left shift Arithmetic 1-bit right shift Logical 1-bit left shift Logical n-bit left shift Logical 1-bit right shift Logical n-bit right shift Number of Instructions 33 Logic operation instructions 6 AND NOT OR TAS TST XOR 14 Shift instructions 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn 14 Rev. 5.00 Mar. 15, 2007 Page 40 of 794 REJ09B0237-0500 Section 2 CPU Type Branch instructions Kinds of Instruction 9 Op Code BF BT BRA BRAF BSR BSRF JMP JSR RTS Function Number of Instructions Conditional branch, delayed conditional 11 branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure T bit clear MAC register clear Load into control register Load into system register No operation Return from exception handling T bit setting Transition to power-down mode Store from control register Store from system register Trap exception handling 142 31 System control instructions 11 CLRT CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total: 62 Rev. 5.00 Mar. 15, 2007 Page 41 of 794 REJ09B0237-0500 Section 2 CPU The instruction code, operation, and execution cycles of the instructions are listed in the following tables, classified by type. Instruction Instruction Code Summary of Operation Indicates summary of operation. Execution Cycles T Bit Value when no Value of T bit after wait cycles are instruction is executed 1 inserted* Explanation of Symbols Indicated by mnemonic. Indicated in MSB ↔ LSB order. Explanation of Symbols Explanation of Symbols Explanation of Symbols OP.Sz SRC, DEST OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement* 2 : No change mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ......... 1111: R15 iiii: Immediate data →, ←: (xx): Transfer direction Memory operand M/Q/T: Flag bits in SR &: |: ^: Logical AND of each bit Logical OR of each bit Exclusive logical OR of each bit –: Logical NOT of each bit dddd: Displacement n: n-bit right shift Notes: 1. The table shows the minimum number of execution states. In practice, the number of instruction execution states will be increased in cases such as the following: • When there is contention between an instruction fetch and a data access • When the destination register of a load instruction (memory → register) is also used by the following instruction 2. Scaled (×1, ×2, or ×4) according to the instruction operand size, etc. For details, see SH-1/SH-2/SH-DSP Software Manual. Rev. 5.00 Mar. 15, 2007 Page 42 of 794 REJ09B0237-0500 Section 2 CPU • Data Transfer Instructions Instruction MOV #imm,Rn Operation imm → Sign extension → Rn extension → Rn Code 1110nnnniiiiiiii Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit                         MOV.W @(disp,PC),Rn (disp × 2 + PC) → Sign MOV.L @(disp,PC),Rn (disp × 4 + PC) → Rn MOV Rm,Rn R m → Rn Rm → (Rn) Rm → (Rn) Rm → (Rn) (Rm) → Sign extension → Rn (Rm) → Sign extension → Rn (Rm) → Rn Rn–1 → Rn, Rm → (Rn) Rn–2 → Rn, Rm → (Rn) Rn–4 → Rn, Rm → (Rn) (Rm) → Sign extension → Rn, Rm + 1 → Rm (Rm) → Sign extension → Rn, Rm + 2 → Rm 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@–Rn MOV.W Rm,@–Rn MOV.L Rm,@–Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 (Rm) → Rn,Rm + 4 → Rm 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd MOV.B R0,@(disp,Rn) R0 → (disp + Rn) MOV.W R0,@(disp,Rn) R0 → (disp × 2 + Rn) MOV.L Rm,@(disp,Rn) Rm → (disp × 4 + Rn) MOV.B @(disp,Rm),R0 (disp + Rm) → Sign extension → R0 MOV.W @(disp,Rm),R0 (disp × 2 + Rm) → Sign extension → R0 10000101mmmmdddd MOV.L @(disp,Rm),Rn (disp × 4 + Rm) → Rn MOV.B Rm,@(R0,Rn) MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) Rm → (R0 + Rn) 0101nnnnmmmmdddd 0000nnnnmmmm0100 0000nnnnmmmm0101 Rev. 5.00 Mar. 15, 2007 Page 43 of 794 REJ09B0237-0500 Section 2 CPU Instruction MOV.L Rm,@(R0,Rn) MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.B MOV.W MOV.L MOV.B R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) @(disp,GBR),R0 Operation Rm → (R0 + Rn) (R0 + Rm) → Sign extension → Rn (R0 + Rm) → Sign extension → Rn (R0 + Rm) → Rn R0 → (disp + GBR) R0 → (disp × 2 + GBR) R0 → (disp × 4 + GBR) (disp + GBR) → Sign extension → R0 (disp × 2 + GBR) → Sign extension → R0 (disp × 4 + GBR) → R0 Code 0000nnnnmmmm0110 0000nnnnmmmm1100 Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit                0000nnnnmmmm1101 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd MOV.W @(disp,GBR),R0 11000101dddddddd MOV.L @(disp,GBR),R0 11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 MOVA MOVT @(disp,PC),R0 disp × 4 + PC → R0 Rn T → Rn Rm → Swap lowest two bytes → Rn Rm → Swap two consecutive words → Rn Rm: Middle 32 bits of Rn → Rn SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn 0110nnnnmmmm1001 0010nnnnmmmm1101 Rev. 5.00 Mar. 15, 2007 Page 44 of 794 REJ09B0237-0500 Section 2 CPU • Arithmetic Operation Instructions Instruction ADD ADD ADDC ADDV Rm,Rn #imm,Rn Rm,Rn Rm,Rn Operation Rn + Rm → Rn Rn + imm → Rn Rn + Rm + T → Rn, Carry → T Rn + Rm → Rn, Overflow → T If R0 = imm, 1 → T If Rn = Rm, 1 → T If Rn ≥ Rm with unsigned data, 1 → T If Rn ≥ Rm with signed data, 1 → T If Rn > Rm with unsigned data, 1 → T If Rn > Rm with signed data, 1 → T If Rn ≥ 0, 1 → T If Rn > 0, 1 → T If Rn and Rm have an equivalent byte, 1 → T Single-step division (Rn/Rm) MSB of Rn → Q, MSB of Rm → M, M^ Q → T 0 → M/Q/T Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 to 5* T Bit   Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0011nnnnmmmm1111 CMP/EQ #imm,R0 CMP/EQ Rm,Rn CMP/HS Rm,Rn CMP/GE Rm,Rn CMP/HI Rm,Rn CMP/GT Rm,Rn CMP/PZ Rn CMP/PL Rn CMP/STRRm,Rn DIV1 DIV0S DIV0U DMULS.L Rm,Rn Rm,Rn 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010001 0100nnnn00010101 0010nnnnmmmm1100 0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 0011nnnnmmmm1101 0  Rm,Rn Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits Rev. 5.00 Mar. 15, 2007 Page 45 of 794 REJ09B0237-0500 Section 2 CPU Instruction DMULU.L Operation Rm,Rn Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits Code 0011nnnnmmmm0101 Execution Cycles T Bit 2 to 5*  DT Rn Rn - 1 → Rn, if Rn = 0, 1 → T, else 0 → T A byte in Rm is signextended → Rn A word in Rm is signextended → Rn A byte in Rm is zeroextended → Rn A word in Rm is zeroextended → Rn Signed operation of (Rn) × (Rm) + MAC → MAC, 32 × 32 + 64 → 64 bits Signed operation of (Rn) × (Rm) + MAC → MAC, 16 × 16 + 64 → 64 bits Rn × Rm → MACL 32 × 32 → 32 bits Signed operation of Rn × Rm → MAC 16 × 16 → 32 bits Unsigned operation of Rn × Rm → MAC 16 × 16 → 32 bits 0-Rm → Rn 0-Rm-T → Rn, Borrow → T Rn-Rm → Rn Rn-Rm–T → Rn, Borrow → T 0100nnnn00010000 1 1 1 1 1 2 to 5* Comparison result EXTS.B Rm,Rn EXTS.W Rm,Rn EXTU.B Rm,Rn EXTU.W Rm,Rn MAC.L @Rm+,@Rn+ 0110nnnnmmmm1110      0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 2 to 4*  MUL.L Rm,Rn MULS.W Rm,Rn 0000nnnnmmmm0111 2 to 5* 1 (3)*   0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 1 (3)*  NEG Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 1 1 1 1  Borrow  Borrow NEGC Rm,Rn SUB Rm,Rn 0011nnnnmmmm1000 0011nnnnmmmm1010 SUBC Rm,Rn Rev. 5.00 Mar. 15, 2007 Page 46 of 794 REJ09B0237-0500 Section 2 CPU Instruction Operation Rn-Rm → Rn, Underflow → T Code 0011nnnnmmmm1011 Execution Cycles T Bit 1 Overflow SUBV Rm,Rn Note: * Indicates the number of execution cycles for normal operation. The values in parentheses indicate the number of execution cycles when conflicts occur with the previous or next instruction. • Logic Operation Instructions Instruction AND AND Rm,Rn #imm,R0 Operation Rn & Rm → Rn R0 & imm → R0 (R0 + GBR) Code Execution Cycles T Bit        Test result Test result Test result Test result 0010nnnnmmmm1001 1 11001001iiiiiiii 1 11001101iiiiiiii 3 0110nnnnmmmm0111 1 0010nnnnmmmm1011 1 11001011iiiiiiii 1 11001111iiiiiiii 3 0100nnnn00011011 4 0010nnnnmmmm1000 1 11001000iiiiiiii 1 11001100iiiiiiii 3 0010nnnnmmmm1010 1 11001010iiiiiiii 1 11001110iiiiiiii 3 AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → NOT OR OR Rm,Rn Rm,Rn #imm,R0 ~Rm → Rn Rn | Rm → Rn R0 | imm → R0 (R0 + GBR) OR.B #imm,@(R0,GBR) (R0 + GBR) | imm → TAS.B @Rn TST TST Rm,Rn #imm,R0 If (Rn) is 0, 1 → T; 1 → MSB of (Rn) Rn & Rm; if the result is 0, 1 → T R0 & imm; if the result is 0, 1 → T if the result is 0, 1 → T TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; XOR XOR Rm,Rn #imm,R0 Rn ^ Rm → Rn R0 ^ imm → R0 (R0 + GBR)    XOR.B #imm,@(R0,GBR) (R0 + GBR) ^ imm → Rev. 5.00 Mar. 15, 2007 Page 47 of 794 REJ09B0237-0500 Section 2 CPU • Shift Instructions Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Operation T ← Rn ← MSB LSB → Rn → T T ← Rn ← T T → Rn → T T ← Rn ← 0 MSB → Rn → T T ← Rn ← 0 0 → Rn → T Rn > 2 → Rn Rn > 8 → Rn Rn > 16 → Rn Code Execution Cycles T Bit MSB LSB MSB LSB MSB LSB MSB LSB       0100nnnn00000100 1 0100nnnn00000101 1 0100nnnn00100100 1 0100nnnn00100101 1 0100nnnn00100000 1 0100nnnn00100001 1 0100nnnn00000000 1 0100nnnn00000001 1 0100nnnn00001000 1 0100nnnn00001001 1 0100nnnn00011000 1 0100nnnn00011001 1 0100nnnn00101000 1 0100nnnn00101001 1 SHLL16 Rn SHLR16 Rn • Branch Instructions Instruction BF label Operation If T = 0, disp × 2 + PC → PC; if T = 1, nop Delayed branch, if T = 0, disp × 2 + PC → PC; if T = 1, nop If T = 1, disp × 2 + PC → PC; if T = 0, nop Delayed branch, if T = 1, disp × 2 + PC → PC; if T = 0, nop Code Execution Cycles T Bit  10001011dddddddd 3/1* BF/S label 10001111dddddddd 2/1*  BT label 10001001dddddddd 3/1*  BT/S label 10001101dddddddd 2/1*  Rev. 5.00 Mar. 15, 2007 Page 48 of 794 REJ09B0237-0500 Section 2 CPU Instruction BRA label Operation Delayed branch, disp × 2 + PC → PC Delayed branch, Rm + PC → PC Code Execution Cycles T Bit        1010dddddddddddd 2 0000mmmm00100011 2 BRAF Rm BSR label Delayed branch, PC → PR, 1011dddddddddddd 2 disp × 2 + PC → PC Delayed branch, PC → PR, 0000mmmm00000011 2 Rm + PC → PC Delayed branch, Rm → PC 0100mmmm00101011 2 BSRF Rm JMP JSR RTS Note: * @Rm @Rm Delayed branch, PC → PR, 0100mmmm00001011 2 Rm → PC Delayed branch, PR → PC 0000000000001011 2 One cycle when the branch is not executed. • System Control Instructions Instruction CLRT CLRMAC LDC LDC LDC Rm,SR Rm,GBR Rm,VBR Operation 0→T 0 → MACH, MACL Rm → SR Rm → GBR Rm → VBR (Rm) → SR, Rm + 4 → Rm (Rm) → GBR, Rm + 4 → Rm Code 0000000000001000 0000000000101000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 Execution Cycles 1 1 6 4 4 8 4 4 1 1 1 1 1 T Bit 0  LSB   LSB        LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDS LDS LDS Rm,MACH Rm,MACL Rm,PR (Rm) → VBR, Rm + 4 → Rm 0100mmmm00100111 Rm → MACH Rm → MACL Rm → PR (Rm) → MACH, Rm + 4 → Rm (Rm) → MACL, Rm + 4 → Rm 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 LDS.L @Rm+,MACH LDS.L @Rm+,MACL 0100mmmm00010110 Rev. 5.00 Mar. 15, 2007 Page 49 of 794 REJ09B0237-0500 Section 2 CPU Instruction LDS.L @Rm+,PR NOP RTE SETT SLEEP STC STC STC SR,Rn GBR,Rn VBR,Rn Operation (Rm) → PR, Rm + 4 → Rm No operation Delayed branch, Stack area → PC/SR 1→T Sleep S R → Rn GBR → Rn VBR → Rn Rn–4 → Rn, SR → (Rn) Rn–4 → Rn, GBR → (Rn) Rn–4 → Rn, VBR → (Rn) MACH → Rn MACL → Rn P R → Rn Rn–4 → Rn, MACH → (Rn) Rn–4 → Rn, MACL → (Rn) Rn–4 → Rn, PR → (Rn) PC/SR → Stack area, (imm × 4 + VBR) → PC Code 0100mmmm00100110 0000000000001001 0000000000101011 Execution Cycles 1 1 5 1 4* 1 1 1 1 1 1 1 1 1 1 1 1 8 T Bit    1               0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii STC.L SR,@–Rn STC.L GBR,@–Rn STC.L VBR,@–Rn STS STS STS MACH,Rn MACL,Rn PR,Rn STS.L MACH,@–Rn STS.L MACL,@–Rn STS.L PR,@–Rn TRAPA #imm Note: * Number of execution cycles until this LSI enters sleep mode. About the number of execution cycles: The table lists the minimum number of execution cycles. In practice, the number of execution cycles will be increased depending on the conditions such as: • When there is a conflict between instruction fetch and data access • When the destination register of a load instruction (memory → register) is also used by the instruction immediately after the load instruction. Rev. 5.00 Mar. 15, 2007 Page 50 of 794 REJ09B0237-0500 Section 2 CPU 2.6 2.6.1 Processing States State Transition The CPU has the four processing states: reset, exception handling, program execution, and powerdown. Figure 2.4 shows the CPU state transition. Note that some products do not support the manual reset function and the MRES pin. RES = 0 in any state RES = 1 and MRES = 0 in any state Power-on reset state Manual reset state Reset state Exception handling state Request for internal power-on reset Request for NMI or internal manual reset by the WDT or IRQ interrupt Request for End of exception handling exception handling Program execution state SLEEP instruction by clearing SSBY bit SLEEP instruction by setting SSBY bit Sleep mode Software standby mode Power-down mode Figure 2.4 CPU State Transition Rev. 5.00 Mar. 15, 2007 Page 51 of 794 REJ09B0237-0500 Section 2 CPU • Reset state The CPU is reset. When the RES pin is driven low, the CPU enters the power-on reset state. When the RES pin is high and MRES pin is low, the CPU enters the manual reset state. • Exception handling state This state is a transitional state in which the CPU processing state changes due to a request for exception handling such as a reset or an interrupt. When a reset occurs, the execution start address as the initial value of the program counter (PC) and the initial value of the stack pointer (SP) are fetched from the exception handling vector table. Then, a branch is made for the start address to execute a program. When an interrupt occurs, the PC and status register (SR) are saved in the stack area pointed to by SP. The start address of an exception handling routine is fetched from the exception handling vector table and a branch to the address is made to execute a program. Then the processing state enters the program execution state. • Program execution state The CPU executes programs sequentially. • Power-down state The CPU stops to reduce power consumption. The SLEEP instruction makes the CPU enter sleep mode or software standby mode. Rev. 5.00 Mar. 15, 2007 Page 52 of 794 REJ09B0237-0500 Section 3 Cache Section 3 Cache 3.1 • • • • • • Features Capacity: 16 kbytes Structure: Instructions/data unified, 4-way set associative Line size: 16 bytes Number of entries: 256 entries/way in 16-kbyte mode Write method: Write-back/write-through is selectable Replacement method: Least-recently-used (LRU) algorithm Cache Structure 3.1.1 The cache holds both instructions and data and employs a 4-way set associative system. It is composed of four ways (banks), and each of which is divided into an address section and a data section. Each of the address and data sections is divided into 256 entries. The data of an entry is called a line. Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 4 kbytes (16 bytes × 256 entries), with a total of 16 kbytes in the cache (4 ways). Figure 3.1 shows the cache structure. Address array (ways 0 to 3) Data array (ways 0 to 3) LRU Entry 0 V U Tag address Entry 1 . . . . . . 0 1 . . . . . . LW0 LW1 LW2 LW3 0 1 . . . . . . Entry 255 24 (1 + 1 + 22) bits 255 128 (32 × 4) bits LW0 to LW3: Longword data 0 to 3 255 6 bits Figure 3.1 Cache Structure Rev. 5.00 Mar. 15, 2007 Page 53 of 794 REJ09B0237-0500 Section 3 Cache Address Array: The V bit indicates whether or not the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit indicates whether or not the entry has been written to in write-back mode. When the U bit is 1, the entry has been written to; when 0, it has not. The tag address is composed of 22 bits (address bits 31 to 10) used for comparison during cache searches. In this LSI, the upper three bits of 32 address bits are used as shadow bits (see section 7, Bus State Controller (BSC)), therefore, the upper three bits of the tag address are cleared to 0. The V and U bits are initialized to 0 by a power-on reset. The tag address is not initialized by a power-on reset. Data Array: Holds 16-byte instruction and data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on reset. LRU: With the 4-way set associative system, up to four instructions or data with the same entry address can be registered in the cache. When an entry is registered, LRU shows which of the four ways it is registered in. There are six LRU bits, controlled by hardware. The least-recently-used (LRU) algorithm is used to select the way. When a cache miss occurs, six LRU bits indicate the way to be replaced. If a bit pattern other than those listed in table 3.1 is set in the LRU bits by software, the cache will not function correctly. When changing the LRU bits by software, set one of the patterns listed in table 3.1. The LRU bits are initialized to 000000 by a power-on reset. Table 3.1 LRU and Way to be Replaced Way to be Replaced 3 2 1 0 LRU (Bits 5 to 0) 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111 Rev. 5.00 Mar. 15, 2007 Page 54 of 794 REJ09B0237-0500 Section 3 Cache 3.1.2 Divided Areas and Cache A 4-G byte address space is divided into five areas with the architecture of this LSI. The cache access methods can be specified for each area. Table 3.2 lists the correspondence between the divided areas and cache. Table 3.2 Address H'00000000 to H'7FFFFFFF H'80000000 to H'9FFFFFFF H'A0000000 to H'BFFFFFFF H'C0000000 to H'DFFFFFFF H'E0000000 to H'FFFFFFFF Correspondence between Divided Areas and Cache Area P0 P1 P2 P3 P4 Cacheable Cacheable Cacheable Non cacheable Cacheable Non cacheable (internal I/O) Cache Operating Control WT bit in CCR1 CB bit in CCR1  WT bit in CCR1  Rev. 5.00 Mar. 15, 2007 Page 55 of 794 REJ09B0237-0500 Section 3 Cache 3.2 Register Descriptions The cache has the following registers. For details on register addresses and register states during each process, refer to section 24, List of Registers. • Cache control register 1 (CCR1) 3.2.1 Cache Control Register 1 (CCR1) The cache is enabled or disabled by the CE bit in CCR1. CCR1 also has the CF bit (which invalidates all cache entries), and the WT and CB bits (which select either write-through mode or write-back mode). Programs that change the contents of CCR1 should be placed in the address space that is not cached. Bit 31 to 4 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 CF 0 R/W Cache Flush Writing 1 flushes all cache entries meaning that it clears the V, U, and LRU bits of all cache entries to 0. This bit is always read as 0. Write-back to external memory is not performed when the cache is flushed. 2 CB 0 R/W Write-Back Indicates the cache operating mode for H'80000000 to H'9FFFFFFF. 0: Write-through mode 1: Write-back mode 1 WT 0 R/W Write-Through Indicates the cache operating mode for H'00000000 to H'7FFFFFFF and H'C0000000 to H'DFFFFFFF. 0: Write-back mode 1: Write-through mode Rev. 5.00 Mar. 15, 2007 Page 56 of 794 REJ09B0237-0500 Section 3 Cache Bit 0 Bit Name CE Initial Value 0 R/W R/W Description Cache Enable Indicates whether or not the cache function is used. 0: Cache function is not used. 1: Cache function is used. 3.3 3.3.1 Operation Searching Cache If the cache is enabled (the CE bit in CCR1 is set to 1), whenever an instruction or data in H'00000000 to H'7FFFFFFF, H'8000000 to H'9FFFFFFF, and H'C0000000 to H'DFFFFFFF is accessed, the cache will be searched to see if the desired instruction or data is in the cache. Figure 3.2 illustrates the method by which the cache is searched. Entries are selected using bits 11 to 4 of the memory access address and the tag address of that entry is read. The address comparison is performed on all four ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a cache miss occurs. Figure 3.2 shows a hit on way 1. Rev. 5.00 Mar. 15, 2007 Page 57 of 794 REJ09B0237-0500 Section 3 Cache Address 31 12 11 4 3 2 10 Entry selection Longword (LW) selection Ways 0 to 3 Ways 0 to 3 0 1 V U Tag address LW0 LW1 LW2 LW3 255 CMP0 CMP1 CMP2 CMP3 Hit signal 1 CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 Figure 3.2 Cache Search Scheme 3.3.2 Read Access Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The LRU bits are updated so that they point to the most recently hit way. Read Miss: An external bus cycle starts and the entry is updated. The way to be replaced is shown in table 3.1. Data is updated in units of 16 bytes by updating the entry. When the desired instruction or data is loaded from external memory to the cache, the instruction or data is transferred to the CPU in parallel. When it is loaded to the cache, the U bit is cleared to 0, the V bit is set to 1, the LRU bits are updated so that they point to the most recently hit way. When the U bit of the entry which is to be replaced by entry updating in write-back mode is 1, the cacheupdate cycle starts after the entry is transferred to the write-back buffer. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte units. Rev. 5.00 Mar. 15, 2007 Page 58 of 794 REJ09B0237-0500 Section 3 Cache 3.3.3 Write Access Write Hit: In a write access in write-back mode, the data is written to the cache and no external memory write cycle is generated. The U bit of the entry that has been written to is set to 1, and the LRU bits are updated to indicate that the hit way is the most recently hit way. In write-through mode, the data is written to the cache and an external memory write cycle is generated. The U bit of the entry that has been written to is not updated, and the LRU bits are updated to indicate that the hit way is the most recently hit way. Write Miss: In write-back mode, an external write cycle starts when a write miss occurs, and the entry is updated. The way to be replaced is shown in table 3.1. When the U bit of the entry which is to be replaced by entry updating is 1, the cache-update cycle starts after the entry has been transferred to the write-back buffer. Data is written to the cache and the U bit and the V bit are set to 1. The LRU bits are updated to indicate that the replaced way is the most recently updated way. After the cache has completed its update cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte units. In write-through mode, no write to cache occurs in a write miss; the write is only to the external memory. 3.3.4 Write-Back Buffer When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. After the fetching of new entries to the cache completes, the write-back buffer writes the entry back to the external memory. During the write-back cycles, the cache can be accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 3.3 shows the configuration of the write-back buffer. PA (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3 PA (31 to 4): Physical address to be written to external memory Longword 0 to 3: One line of cache data to be written to external memory Figure 3.3 Write-Back Buffer Configuration 3.3.5 Coherency of Cache and External Memory Coherency between the cache and the external memory must be ensured by software. When memory shared by this LSI and another device is allocated to a cacheable address space, invalidate and write back the cache by accessing the memory-mapped cache, as required. Memory that is shared by the CPU, DMAC, and E-DMAC of this LSI should also be handled in this way. Rev. 5.00 Mar. 15, 2007 Page 59 of 794 REJ09B0237-0500 Section 3 Cache 3.4 Memory-Mapped Cache To allow software management of the cache, cache contents can be read from or written to by the MOV instructions. The address array is allocated to addresses H'F0000000 to H'F0FFFFFF, and the data array to addresses H'F1000000 to H'F1FFFFFF. The address array and data array must be accessed in longwords, and instruction fetches cannot be performed. 3.4.1 Address Array The address array is allocated to H'F0000000 to H'F0FFFFFF. To access an address array, the 32bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the tag address, V bit, U bit, and LRU bits to be written to the address array. In the address field, specify the entry address for selecting the entry, W for selecting the way, A for enabling or disabling the associative operation, and H'F0 for indicating address array access. As for W, 00 indicates way 0, 01 indicates way 1, 10 indicates way 2, and 11 indicates way 3. In the data field, specify the tag address, LRU bits, U bit, and V bit. Always clear the upper three bits (bits 31 to 29) of the tag address to 0. Figure 3.4 shows the address and data formats. The following three operations are available in the address array. Address-Array Read: Read the tag address, LRU bits, U bit, and V bit for the entry that corresponds to the entry address and way specified by the address field of the read instruction. In reading, the associative operation is not performed, regardless of whether the associative bit (A bit) specified in the address is 1 or 0. Address-Array Write (Non-Associative Operation): Write the tag address, LRU bits, U bit, and V bit, specified by the data field of the write instruction, to the entry that corresponds to the entry address and way as specified by the address field of the write instruction. Ensure that the associative bit (A bit) in the address field is set to 0. When writing to a cache line for which the U bit = 1 and the V bit =1, write the contents of the cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the data field of the write instruction. When 0 is written to the V bit, 0 must also be written to the U bit for that entry. Rev. 5.00 Mar. 15, 2007 Page 60 of 794 REJ09B0237-0500 Section 3 Cache Address-Array Write (Associative Operation): When writing with the associative bit (A bit) of the address field set to 1, the addresses in the four ways for the entry specified by the address field of the write instruction are compared with the tag address that is specified by the data field of the write instruction. Write the U bit and the V bit specified by the data field of the write instruction to the entry of the way that has a hit. However, the tag address and LRU bits remain unchanged. When there is no way that has a hit, nothing is written and there is no operation. This function is used to invalidate a specific entry in the cache. When the U bit of the entry that has had a hit is 1 at this time, writing back should be performed. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. 3.4.2 Data Array The data array is allocated to H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. In the address field, specify the entry address for selecting the entry, L for indicating the longword position within the (16-byte) line, W for selecting the way, and H'F1 for indicating data array access. As for L, 00 indicates longword 0, 01 indicates longword 1, 10 indicates longword 2, and 11 indicates longword 3. As for W, 00 indicates way 0, 01 indicates way 1, 10 indicates way 2, and 11 indicates way 3. Since access size of the data array is fixed at longword, bits 1 and 0 of the address field should be set to 00. Figure 3.4 shows the address and data formats. The following two operations on the data array are available. The information in the address array is not affected by these operations. Data-Array Read: Read the data specified by L of the address field, from the entry that corresponds to the entry address and the way that is specified by the address field. Data-Array Write: Write the longword data specified by the data field, to the position specified by L of the address field, in the entry that corresponds to the entry address and the way specified by the address field. Rev. 5.00 Mar. 15, 2007 Page 61 of 794 REJ09B0237-0500 Section 3 Cache (1) Address array access (a) Address specification Read access 31 1111 0000 Write access 31 1111 0000 24 23 *--------* 14 13 12 11 W Entry address 43210 0*00 24 23 *--------* 14 13 12 11 W Entry address 43210 A*00 (b) Data specification (both read and write accesses) 31 30 29 28 00 0 Tag address (28 to 10) 10 9 LRU 43210 X XU V (2) Data array access (both read and write accesses) (a) Address specification 31 1111 0001 (b) Data specification 31 Longword [Legend] *: Don't care X: 0 for read, don't care for write 0 24 23 *--------* 14 13 12 11 W Entry address 43210 L 00 Figure 3.4 Specifying Address and Data for Memory-Mapped Cache Access Rev. 5.00 Mar. 15, 2007 Page 62 of 794 REJ09B0237-0500 Section 3 Cache 3.4.3 Usage Examples Invalidating Specific Entries: Specific cache entries can be invalidated by writing 0 to the entry's V bit in the memory-mapped cache access. When the A bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address, and the V bit and U bit specified by the write data are written when a match is found. If no match is found, there is no operation. When the V bit of an entry in the address array is set to 0, the entry is written back if the entry's U bit is 1. In the example shown below, R0 specifies the write data and R1 specifies the address. ; R0=H'01100010; VPN=B'0000 0001 0001 0000 0000 00, U=0, V=0 ; R1=H'F0000088; address array access, entry=B'00001000, A=1 ; MOV.L R0,@R1 Reading Data of Specific Entry: The data section of a specific entry can be read from by the memory-mapped cache access. The longword indicated in the data field of the data array in figure 3.4 is read into the register. In the example shown below, R0 specifies the address and R1 shows what is read. ; R0=H'F100004C; data array access, entry=B'00000100 ; Way = 0, longword address = 3 ; MOV.L @R0,R1 ; Longword 3 is read. Rev. 5.00 Mar. 15, 2007 Page 63 of 794 REJ09B0237-0500 Section 3 Cache Rev. 5.00 Mar. 15, 2007 Page 64 of 794 REJ09B0237-0500 Section 4 U Memory Section 4 U Memory This LSI has on-chip U memory which can be used to store instructions and data. 4.1 Features Features of the U Memory are shown below. • Size 16 kbytes • Address H'E55F_C000 to H'E55F_FFFF • Priority The U memory can be accessed from the I bus by the DMAC and E-DMAC and from the L bus by the CPU. In the event of simultaneous accesses from different buses, the accesses are processed according to the priority. The priority is: I bus > L bus. 4.2 Usage Notes In sleep mode, the U memory cannot be accessed by the DMAC and E-DMAC. Rev. 5.00 Mar. 15, 2007 Page 65 of 794 REJ09B0237-0500 Section 4 U Memory Rev. 5.00 Mar. 15, 2007 Page 66 of 794 REJ09B0237-0500 Section 5 Exception Handling Section 5 Exception Handling 5.1 5.1.1 Overview Types of Exception Handling and Priority Exception handling is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. When several exceptions are detected at once, they are processed according to the priority. Table 5.1 Exception Reset Types of Exceptions and Priority Exception Source Power-on reset H-UDI reset Priority High Interrupt Address error Instruction User break (break before instruction execution) CPU address error (instruction fetch) General illegal instructions (undefined code) Illegal slot instruction (undefined code placed immediately after a delayed branch instruction*1 or instruction that changes the PC value*2) Trap instruction (TRAPA instruction) Address error Interrupt CPU address error (data access) User break (break after instruction execution or operand break) NMI H-UDI IRQ On-chip peripheral modules Watchdog timer (WDT) Ether controller (EtherC and E-DMAC) Compare match timer 0 and 1 (CMT0 and CMT1) Serial communication interface with FIFO (SCIF0, SCIF1, and SCIF2) Host interface (HIF) Low Rev. 5.00 Mar. 15, 2007 Page 67 of 794 REJ09B0237-0500 Section 5 Exception Handling Exception Interrupt Exception Source On-chip peripheral modules Direct memory access controller (DMAC0, DMAC1 DMAC2, and DMAC3) Serial I/O with FIFO (SIOF) Priority High Low Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and BRAF. 2. Instructions that change the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR. 5.1.2 Exception Handling Operations The exceptions are detected and the exception handling starts according to the timing shown in table 5.2. Table 5.2 Exception Reset Power-on reset H-UDI reset Address error Interrupt Instruction Timing for Exception Detection and Start of Exception Handling Timing of Source Detection and Start of Exception Handling Started when the RES pin changes from low to high or when the WDT overflows. Started when the reset assert command and the reset negate command are input to the H-UDI in this order. Detected during the instruction decode stage and started after the execution of the current instruction is completed. Trap instruction Started by the execution of the TRAPA instruction. General illegal instructions Illegal slot instructions Started when an undefined code placed at other than a delay slot (immediately after a delayed branch instruction) is decoded. Started when an undefined code placed at a delay slot (immediately after a delayed branch instruction) or an instruction that changes the PC value is detected. When exception handling starts, the CPU operates Exception Handling Triggered by Reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception handling vector table (PC from the address H'A0000000 and SP from the address H'A0000004). For details, see section 5.1.3, Exception Handling Vector Table. H'00000000 is then written to the vector base register (VBR), and H'F (B'1111) is written to the interrupt mask bits (I3 to I0) in the status register (SR). The program starts from the PC address fetched from the exception handling vector table. Rev. 5.00 Mar. 15, 2007 Page 68 of 794 REJ09B0237-0500 Section 5 Exception Handling Exception Handling Triggered by Address Error, Interrupt, and Instruction: SR and PC are saved to the stack indicated by R15. For interrupt exception handling, the interrupt priority level is written to the interrupt mask bits (I3 to I0) in SR. For address error and instruction exception handling, bits I3 to I0 are not affected. The start address is then fetched from the exception handling vector table and the program starts from that address. 5.1.3 Exception Handling Vector Table Before exception handling starts, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception handling routines. (The reset exception handling table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets. The vector table addresses are calculated from these vector numbers and vector table address offsets. During exception handling, the start addresses of the exception handling routines are fetched from the exception handling vector table that is indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Vector Numbers and Vector Table Address Offsets Vector Number 0 1 2 3 General illegal instruction (Reserved by system) Illegal slot instruction (Reserved by system) 4 5 6 7 8 CPU address error (Reserved by system) Interrupt NMI User break H-UDI 9 10 11 12 13 Vector Table Address Offset H'00000000 to H'00000003 H'00000004 to H'00000007 H'00000008 to H'0000000B H'0000000C to H'0000000F H'00000010 to H'00000013 H'00000014 to H'00000017 H'00000018 to H'0000001B H'0000001C to H'0000001F H'00000020 to H'00000023 H'00000024 to H'00000027 H'00000028 to H'0000002B H'0000002C to H'0000002F H'00000030 to H'00000033 H'00000034 to H'00000037 Exception Handling Source Power-on reset H-UDI reset (Reserved by system) PC SP Rev. 5.00 Mar. 15, 2007 Page 69 of 794 REJ09B0237-0500 Section 5 Exception Handling Exception Handling Source (Reserved by system) Vector Number 14 : 31 Vector Table Address Offset H'00000038 to H'0000003B : H'0000007C to H'0000007F H'00000080 to H'00000083 : H'000000FC to H'000000FF H'00000100 to H'00000103 H'00000104 to H'00000107 H'00000108 to H'0000010B H'0000010C to H'0000010F H'00000110 to H'00000113 : H'0000013C to H'0000013F H'00000140 to H'00000143 H'00000144 to H'00000147 H'00000148 to H'0000014B H'0000014C to H'0000014F H'00000120 to H'00000124 : H'000003FC to H'000003FF Trap instruction (user vector) 32 : 63 Interrupt IRQ0 IRQ1 IRQ2 IRQ3 (Reserved by system) 64 65 66 67 68 : 79 IRQ4 IRQ5 IRQ6 IRQ7 On-chip peripheral module* 80 81 82 83 84 : 255 Note: * For details on the vector numbers and vector table address offsets of on-chip peripheral module interrupts, see table 6.2, Interrupt Exception Handling Sources, Vector Addresses and Priorities in section 6, Interrupt Controller (INTC). Table 5.4 Calculating Exception Handling Vector Table Addresses Vector Table Address Calculation Vector table address = H'A0000000 + (vector table address offset) = H'A0000000 + (vector number) × 4 Vector table address = VBR + (vector table address offset) = VBR + (vector number) × 4 Exception Source Resets Address errors, interrupts, instructions Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 5.3. 3. Vector number: See table 5.3. Rev. 5.00 Mar. 15, 2007 Page 70 of 794 REJ09B0237-0500 Section 5 Exception Handling 5.2 5.2.1 Resets Types of Resets Resets have priority over any exception source. As table 5.5 shows, a power-on reset initializes all modules in this LSI. Table 5.5 Reset Status Conditions for Transition to Reset State WDT Overflow  Overflow Not overflowed H-UDI Command   Internal State On-Chip Peripheral Module Initialized Initialized Initialized Type Power-on reset RES Low High CPU, INTC Initialized Initialized PFC, I/O Port Initialized Initialized Initialized H-UDI reset High Reset assert Initialized command 5.2.2 Power-On Reset Power-On Reset by RES Pin: When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this LSI, the RES pin should be kept low for at least the oscillation settling time when applying the power or when in standby mode (when the clock is halted) or at least 20 tcyc when the clock is operating. During the power-on reset state, CPU internal states and all registers of on-chip peripheral modules are initialized. In the power-on reset state, power-on reset exception handling starts when driving the RES pin high after driving the pin low for the given time. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception handling vector table are set in PC and SP, then the program starts. Be certain to always perform power-on reset exception handling when turning the system power on. Rev. 5.00 Mar. 15, 2007 Page 71 of 794 REJ09B0237-0500 Section 5 Exception Handling Power-On Reset by WDT: When TCNT of the WDT overflows while a setting is made so that a power-on reset can be generated in watchdog timer mode of the WDT, this LSI enters the poweron reset state. If a reset caused by the signal input on the RES pin and a reset caused by a WDT overflow occur simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0. When the power-on reset exception handling caused by the WDT is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception handling vector table are set in the PC and SP, then the program starts. 5.2.3 H-UDI Reset The H-UDI reset is generated by issuing the H-UDI reset assert command. The CPU operation is described below. For details, see section 21, User Debugging Interface (H-UDI). 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) in the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception handling vector table are set in PC and SP, then the program starts. Rev. 5.00 Mar. 15, 2007 Page 72 of 794 REJ09B0237-0500 Section 5 Exception Handling 5.3 5.3.1 Address Errors Address Error Sources Address errors occur when instructions are fetched or data is read from or written to, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Instruction fetch Data read/write Bus Master CPU Bus Cycle Description Instruction fetched from even address Instruction fetched from odd address CPU Word data accessed from even address Word data accessed from odd address Longword data accessed from a longword boundary Longword data accessed from other than a long-word boundary Address Errors None (normal) Address error occurs None (normal) Address error occurs None (normal) Address error occurs 5.3.2 Address Error Exception Source When an address error exception is generated, the bus cycle which caused the address error ends, the current instruction finishes, and then the address error exception handling starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value to be saved is the start address of the instruction which caused an address error exception. When the instruction that caused the exception is placed in the delay slot, the address of the delayed branch instruction which is placed immediately before the delay slot. 3. The start address of the exception handling routine is fetched from the exception handling vector table that corresponds to the generated address error, and the program starts executing from that address. This branch is not a delayed branch. Rev. 5.00 Mar. 15, 2007 Page 73 of 794 REJ09B0237-0500 Section 5 Exception Handling 5.4 5.4.1 Interrupts Interrupt Sources Table 5.7 shows the sources that start the interrupt exception handling. They are NMI, user break, H-UDI, IRQ, and on-chip peripheral modules. Table 5.7 Type NMI User break H-UDI IRQ On-chip peripheral module Interrupt Sources Request Source NMI pin (external input) User break controller (UBC) User debug interface (H-UDI) IRQ0 to IRQ7 pins (external input) Watchdog timer (WDT) Ether controller (EtherC and E-DMAC) Compare match timer (CMT0 and CMT1) Serial communication interface with FIFO (SCIF0, SCIF1, and SCIF2) Host interface (HIF) Direct memory access controller (DMAC0, DMAC1, DMAC2, and DMAC3) Serial I/O with FIFO (SIOF) Number of Sources 1 1 1 8 1 1 2 12 2 4 1 All interrupt sources are given different vector numbers and vector table address offsets. For details on vector numbers and vector table address offsets, see table 6.2, Interrupt Exception Sources, Vector Addresses and Priorities in section 6, Interrupt Controller (INTC). Rev. 5.00 Mar. 15, 2007 Page 74 of 794 REJ09B0237-0500 Section 5 Exception Handling 5.4.2 Interrupt Priority The interrupt priority is predetermined. When multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and starts the exception handling according to the results. The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The priority level of the user break interrupt and H-UDI is 15. IRQ interrupt and on-chip peripheral module interrupt priority levels can be set freely using the interrupt priority level setting registers A to G (IPRA to IPRG) of the INTC as shown in table 5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. For details on IPRA to IPRG, see section 6.3.4, Interrupt Priority Registers A to G (IPRA to IPRG). Table 5.8 Type NMI User break H-UDI IRQ On-chip peripheral module Interrupt Priority Priority Level 16 15 15 0 to 15 Comment Fixed priority level. Cannot be masked. Fixed priority level. Can be masked. Fixed priority level. Set with interrupt priority level setting registers A through G (IPRA to IPRG). 5.4.3 Interrupt Exception Handling When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR). When an interrupt is accepted, exception handling begins. In interrupt exception handling, the CPU saves SR and the program counter (PC) to the stack. The priority level of the accepted interrupt is written to bits I3 to I0 in SR. Although the priority level of the NMI is 16, the value set in bits I3 to I0 is H'F (level 15). Next, the start address of the exception handling routine is fetched from the exception handling vector table for the accepted interrupt, and program execution branches to that address and the program starts. For details on the interrupt exception handling, see section 6.6, Interrupt Operation. Rev. 5.00 Mar. 15, 2007 Page 75 of 794 REJ09B0237-0500 Section 5 Exception Handling 5.5 5.5.1 Exceptions Triggered by Instructions Types of Exceptions Triggered by Instructions Exception handling can be triggered by the trap instruction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. Table 5.9 Type Trap instruction Illegal slot instructions* Types of Exceptions Triggered by Instructions Source Instruction TRAPA Undefined code placed immediately after a delayed branch instruction (delay slot) or instructions that changes the PC value Undefined code anywhere besides in a delay slot Comment  Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that changes the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR  General illegal instructions* Note: * The operation is not guaranteed when undefined instructions other than H'FC00 to H'FFFF are decoded. 5.5.2 Trap Instructions When a TRAPA instruction is executed, the trap instruction exception handling starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The CPU reads the start address of the exception handling routine from the exception handling vector table that corresponds to the vector number specified in the TRAPA instruction, program execution branches to that address, and then the program starts. This branch is not a delayed branch. Rev. 5.00 Mar. 15, 2007 Page 76 of 794 REJ09B0237-0500 Section 5 Exception Handling 5.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is called “instruction placed in a delay slot”. When the instruction placed in the delay slot is an undefined code, illegal slot exception handling starts after the undefined code is decoded. Illegal slot exception handling also starts when an instruction that changes the program counter (PC) value is placed in a delay slot and the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The start address of the exception handling routine is fetched from the exception handling vector table that corresponds to the exception that occurred. Program execution branches to that address and the program starts. This branch is not a delayed branch. 5.5.4 General Illegal Instructions When an undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. The CPU handles the general illegal instructions in the same procedures as in the illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value that is stacked is the start address of the undefined code. Rev. 5.00 Mar. 15, 2007 Page 77 of 794 REJ09B0237-0500 Section 5 Exception Handling 5.6 Cases when Exceptions are Accepted When an exception other than resets occurs during decoding the instruction placed in a delay slot or immediately after an interrupt disabled instruction, it may not be accepted and be held shown in table 5.10. In this case, when an instruction which accepts an interrupt request is decoded, the exception is accepted. Table 5.10 Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions Exception Address Error ×* 2 Occurrence Timing Instruction in delay slot General Illegal Instruction  √ Slot Illegal Instruction ×* √ 2 Trap Instruction  √ Interrupt × *3 ×*4 Immediately after interrupt √ disabled instruction*1 [Legend] √: Accepted ×: Not accepted : Does not occur Notes: 1. Interrupt disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L 2. An exception is accepted before the execution of a delayed branch instruction. However, when an address error or a slot illegal instruction exception occurs in the delay slot of the RTE instruction, correct operation is not guaranteed. 3. An exception is accepted after a delayed branch (between instructions in the delay slot and the branch destination). 4. An exception is accepted after the execution of the next instruction of an interrupt disabled instruction (before the execution two instructions after an interrupt disabled instruction). Rev. 5.00 Mar. 15, 2007 Page 78 of 794 REJ09B0237-0500 Section 5 Exception Handling 5.7 Stack States after Exception Handling Ends The stack states after exception handling ends are shown in table 5.11. Table 5.11 Stack Status after Exception Handling Ends Types Address error (when the instruction that caused an exception is placed in the delay slot) Stack State SP → Address of delayed branch instruction SR 32 bits 32 bits Address error (other than above) SP → Address of instruction that caused exception SR 32 bits 32 bits Interrupt SP → Address of instruction after executed instruction SR 32 bits 32 bits Trap instruction SP → Address of instruction after TRAPA instruction SR 32 bits 32 bits Rev. 5.00 Mar. 15, 2007 Page 79 of 794 REJ09B0237-0500 Section 5 Exception Handling Types Illegal slot instruction Stack State SP → Address of delayed branch instruction SR 32 bits 32 bits General illegal instruction SP → Address of general illegal instruction SR 32 bits 32 bits Rev. 5.00 Mar. 15, 2007 Page 80 of 794 REJ09B0237-0500 Section 5 Exception Handling 5.8 5.8.1 Usage Notes Value of Stack Pointer (SP) The SP value must always be a multiple of 4. If it is not, an address error will occur when the stack is accessed during exception handling. 5.8.2 Value of Vector Base Register (VBR) The VBR value must always be a multiple of 4. If it is not, an address error will occur when the stack is accessed during exception handling. 5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling When the SP value is not a multiple of 4, an address error will occur when stacking for exception handling (interrupts, etc.) and address error exception handling will start after the first exception handling is ended. Address errors will also occur in the stacking for this address error exception handling. To ensure that address error exception handling does not go into an endless loop, no address errors are accepted at that point. This allows program control to be passed to the handling routine for address error exception and enables error processing. When an address error occurs during exception handling stacking, the stacking bus cycle (write) is executed. When stacking the SR and PC values, the SP values for both are subtracted by 4, therefore, the SP value is still not a multiple of 4 after the stacking. The address value output during stacking is the SP value whose lower two bits are cleared to 0. So the write data stacked is undefined. 5.8.4 Notes on Slot Illegal Instruction Exception Handling Some specifications on slot illegal instruction exception handling in this LSI differ from those of the conventional SH2. • Conventional SH2: Instructions LDC Rm,SR and LDC.L @Rm+,SR are not subject to the slot illegal instructions. • This LSI: Instructions LDC Rm,SR and LDC.L @Rm+,SR are subject to the slot illegal instructions. The supporting status on our software products regarding this note is as follows: Rev. 5.00 Mar. 15, 2007 Page 81 of 794 REJ09B0237-0500 Section 5 Exception Handling Compiler This instruction is not allocated in the delay slot in the compiler V.4 and its subsequent versions. Real-time OS for µITRON specifications 1. HI7000/4, HI-SH7 This instruction does not exist in the delay slot within the OS. 2. HI7000 This instruction is in part allocated to the delay slot within the OS, which may cause the slot illegal instruction exception handling in this LSI. 3. Others The slot illegal instruction exception handling may be generated in this LSI in a case where the instruction is described in assembler or when the middleware of the object is introduced. Note that a check-up program (checker) to pick up this instruction is available on our website. Download and utilize this checker as needed. Rev. 5.00 Mar. 15, 2007 Page 82 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. 6.1 Features • 16 levels of interrupt priority Figure 6.1 shows a block diagram of the INTC. Rev. 5.00 Mar. 15, 2007 Page 83 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) NMI IRQ0 . . . . . . Input control Comparator IRQ7 UBC H-UDI WDT E-DMAC CMT0 CMT1 SCIF0 SCIF1 SCIF2 HIF DMAC SIOF (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) Priority determination Interrupt request SR I3 I2 I1 I0 CPU DTER ICR0 IRQCR IRQSR IPRA to IPRE IPR DTC Module bus Bus interface INTC [Legend] UBC: H-UDI: WDT: E-DMAC: CMT: SCIF: User break controller User debugging interface Watchdog timer DMAC for Ethernet controller Compare match timer Serial communications interface with FIFO HIF: DMAC: ICR0: IRQCR: IRQSR: IPRA to IPRG: SR: Host interface Direct memory access controller Interrupt control register 0 IRQ control register IRQ status register Interrupt priority registers A to G Status register Figure 6.1 INTC Block Diagram Rev. 5.00 Mar. 15, 2007 Page 84 of 794 REJ09B0237-0500 Internal bus Section 6 Interrupt Controller (INTC) 6.2 Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Name Non-maskable interrupt input pin Interrupt request input pins Pin Configuration Abbr. NMI IRQ0 to IRQ7 I/O Input Input Function Input of non-maskable interrupt request signal Input of maskable interrupt request signals 6.3 Register Descriptions The interrupt controller has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 24, List of Registers. • • • • • • • • • • Interrupt control register 0 (ICR0) IRQ control register (IRQCR) IRQ status register (IRQSR) Interrupt priority register A (IPRA) Interrupt priority register B (IPRB) Interrupt priority register C (IPRC) Interrupt priority register D (IPRD) Interrupt priority register E (IPRE) Interrupt priority register F (IPRF) Interrupt priority register G (IPRG) Rev. 5.00 Mar. 15, 2007 Page 85 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) 6.3.1 Interrupt Control Register 0 (ICR0) ICR0 is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level on the NMI pin. Bit 15 Initial Bit Name Value NMIL 1/0 R/W R Description NMI Input Level Indicates the state of the signal input to the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. 0: State of the NMI input is low 1: State of the NMI input is high 14 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 NMIE 0 R/W NMI Edge Select 0: Interrupt request is detected on the falling edge of the NMI input 1: Interrupt request is detected on the rising edge of the NMI input 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 86 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) 6.3.2 IRQ Control Register (IRQCR) IRQCR is a 16-bit register that sets the input signal detection mode of the external interrupt input pins IRQ0 to IRQ7. Bit 15 14 Bit Name IRQ71S IRQ70S Initial Value 0 0 R/W R/W R/W Description IRQ7 Sense Select Set the interrupt request detection mode for pin IRQ7. 00: Interrupt request is detected at the low level of pin IRQ7 01: Interrupt request is detected at the falling edge of pin IRQ7 10: Interrupt request is detected at the rising edge of pin IRQ7 11: Interrupt request is detected at both the falling and rising edges of pin IRQ7 13 12 IRQ61S IRQ60S 0 0 R/W R/W IRQ6 Sense Select Set the interrupt request detection mode for pin IRQ6. 00: Interrupt request is detected at the low level of pin IRQ6 01: Interrupt request is detected at the falling edge of pin IRQ6 10: Interrupt request is detected at the rising edge of pin IRQ6 11: Interrupt request is detected at both the falling and rising edges of pin IRQ6 Rev. 5.00 Mar. 15, 2007 Page 87 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) Bit 11 10 Bit Name IRQ51S IRQ50S Initial Value 0 0 R/W R/W R/W Description IRQ5 Sense Select Set the interrupt request detection mode for pin IRQ5. 00: Interrupt request is detected at the low level of pin IRQ5 01: Interrupt request is detected at the falling edge of pin IRQ5 10: Interrupt request is detected at the rising edge of pin IRQ5 11: Interrupt request is detected at both the falling and rising edges of pin IRQ5 9 8 IRQ41S IRQ40S 0 0 R/W R/W IRQ4 Sense Select Set the interrupt request detection mode for pin IRQ4. 00: Interrupt request is detected at the low level of pin IRQ4 01: Interrupt request is detected at the falling edge of pin IRQ4 10: Interrupt request is detected at the rising edge of pin IRQ4 11: Interrupt request is detected at both the falling and rising edges of pin IRQ4 7 6 IRQ31S IRQ30S 0 0 R/W R/W IRQ3 Sense Select Set the interrupt request detection mode for pin IRQ3. 00: Interrupt request is detected at the low level of pin IRQ3 01: Interrupt request is detected at the falling edge of pin IRQ3 10: Interrupt request is detected at the rising edge of pin IRQ3 11: Interrupt request is detected at both the falling and rising edges of pin IRQ3 Rev. 5.00 Mar. 15, 2007 Page 88 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) Bit 5 4 Bit Name IRQ21S IRQ20S Initial Value 0 0 R/W R/W R/W Description IRQ2 Sense Select Set the interrupt request detection mode for pin IRQ2. 00: Interrupt request is detected at the low level of pin IRQ2 01: Interrupt request is detected at the falling edge of pin IRQ2 10: Interrupt request is detected at the rising edge of pin IRQ2 11: Interrupt request is detected at both the falling and rising edges of pin IRQ2 3 2 IRQ11S IRQ10S 0 0 R/W R/W IRQ1 Sense Select Set the interrupt request detection mode for pin IRQ1. 00: Interrupt request is detected at the low level of pin IRQ1 01: Interrupt request is detected at the falling edge of pin IRQ1 10: Interrupt request is detected at the rising edge of pin IRQ1 11: Interrupt request is detected at both the falling and rising edges of pin IRQ1 1 0 IRQ01S IRQ00S 0 0 R/W R/W IRQ0 Sense Select Set the interrupt request detection mode for pin IRQ0. 00: Interrupt request is detected at the low level of pin IRQ0 01: Interrupt request is detected at the falling edge of pin IRQ0 10: Interrupt request is detected at the rising edge of pin IRQ0 11: Interrupt request is detected at both the falling and rising edges of pin IRQ0 Rev. 5.00 Mar. 15, 2007 Page 89 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) 6.3.3 IRQ Status register (IRQSR) IRQSR is a 16-bit register that indicates the states of the external interrupt input pins IRQ0 to IRQ7 and the status of interrupt request. Bit 15 Bit Name IRQ7L Initial Value 0/1 R/W R Description Indicates the state of pin IRQ7. 0: State of pin IRQ7 is low 1: State of pin IRQ7 is high 14 IRQ6L 0/1 R Indicates the state of pin IRQ6. 0: State of pin IRQ6 is low 1: State of pin IRQ6 is high 13 IRQ5L 0/1 R Indicates the state of pin IRQ5. 0: State of pin IRQ5 is low 1: State of pin IRQ5 is high 12 IRQ4L 0 or 1 R Indicates the state of pin IRQ4. 0: State of pin IRQ4 is low 1: State of pin IRQ4 is high 11 IRQ3L 0 or 1 R Indicates the state of pin IRQ3. 0: State of pin IRQ3 is low 1: State of pin IRQ3 is high 10 IRQ2L 0 or 1 R Indicates the state of pin IRQ2. 0: State of pin IRQ2 is low 1: State of pin IRQ2 is high 9 IRQ1L 0 or 1 R Indicates the state of pin IRQ1. 0: State of pin IRQ1 is low 1: State of pin IRQ1 is high 8 IRQ0L 0 or 1 R Indicates the state of pin IRQ0. 0: State of pin IRQ0 is low 1: State of pin IRQ0 is high Rev. 5.00 Mar. 15, 2007 Page 90 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) Bit 7 Bit Name IRQ7F Initial Value 0 R/W R/W Description Indicates the status of an IRQ7 interrupt request. • When level detection mode is selected [Clearing condition] Driving pin IRQ7 high 1: An IRQ7 interrupt has been detected [Setting condition] Driving pin IRQ7 low • When edge detection mode is selected [Clearing conditions]  Writing 0 after reading IRQ7F = 1  Accepting an IRQ7 interrupt 1: An IRQ7 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ7 0: An IRQ7 interrupt has not been detected 0: An IRQ7 interrupt has not been detected 6 IRQ6F 0 R/W Indicates the status of an IRQ6 interrupt request. • When level detection mode is selected [Clearing condition] Driving pin IRQ6 high 1: An IRQ6 interrupt has been detected [Setting condition] Driving pin IRQ6 low • When edge detection mode is selected [Clearing conditions]  Writing 0 after reading IRQ6F = 1  Accepting an IRQ6 interrupt 1: An IRQ6 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ6 0: An IRQ6 interrupt has not been detected 0: An IRQ6 interrupt has not been detected Rev. 5.00 Mar. 15, 2007 Page 91 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) Bit 5 Bit Name IRQ5F Initial Value 0 R/W R/W Description Indicates the status of an IRQ5 interrupt request. • When level detection mode is selected [Clearing condition] Driving pin IRQ5 high 1: An IRQ5 interrupt has been detected [Setting condition] Driving pin IRQ5 low • When edge detection mode is selected [Clearing conditions]  Writing 0 after reading IRQ5F = 1  Accepting an IRQ5 interrupt 1: An IRQ5 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ5 0: An IRQ5 interrupt has not been detected 0: An IRQ5 interrupt has not been detected 4 IRQ4F 0 R/W Indicates the status of an IRQ4 interrupt request. • When level detection mode is selected [Clearing condition] Driving pin IRQ4 high 1: An IRQ4 interrupt has been detected [Setting condition] Driving pin IRQ4 low • When edge detection mode is selected [Clearing conditions]  Writing 0 after reading IRQ4F = 1  Accepting an IRQ4 interrupt 1: An IRQ4 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ4 0: An IRQ4 interrupt has not been detected 0: An IRQ4 interrupt has not been detected Rev. 5.00 Mar. 15, 2007 Page 92 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) Bit 3 Bit Name IRQ3F Initial Value 0 R/W R/W Description Indicates the status of an IRQ3 interrupt request. • When level detection mode is selected [Clearing condition] Driving pin IRQ3 high 1: An IRQ3 interrupt has been detected [Setting condition] Driving pin IRQ3 low • When edge detection mode is selected [Clearing conditions]  Writing 0 after reading IRQ3F = 1  Accepting an IRQ3 interrupt 1: An IRQ3 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ3 0: An IRQ3 interrupt has not been detected 0: An IRQ3 interrupt has not been detected 2 IRQ2F 0 R/W Indicates the status of an IRQ2 interrupt request. • When level detection mode is selected [Clearing condition] Driving pin IRQ2 high 1: An IRQ2 interrupt has been detected [Setting condition] Driving pin IRQ2 low • When edge detection mode is selected [Clearing conditions]  Writing 0 after reading IRQ2F = 1  Accepting an IRQ2 interrupt 1: An IRQ2 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ2 0: An IRQ2 interrupt has not been detected 0: An IRQ2 interrupt has not been detected Rev. 5.00 Mar. 15, 2007 Page 93 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) Bit 1 Bit Name IRQ1F Initial Value 0 R/W R/W Description Indicates the status of an IRQ1 interrupt request. • When level detection mode is selected [Clearing condition] Driving pin IRQ1 high 1: An IRQ1 interrupt has been detected [Setting condition] Driving pin IRQ1 low • When edge detection mode is selected [Clearing conditions]  Writing 0 after reading IRQ1F = 1  Accepting an IRQ1 interrupt 1: An IRQ1 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ1 0: An IRQ1 interrupt has not been detected 0: An IRQ1 interrupt has not been detected 0 IRQ0F 0 R/W Indicates the status of an IRQ0 interrupt request. • When level detection mode is selected [Clearing condition] Driving pin IRQ0 high 1: An IRQ0 interrupt has been detected [Setting condition] Driving pin IRQ0 low • When edge detection mode is selected [Clearing conditions]  Writing 0 after reading IRQ0F = 1  Accepting an IRQ0 interrupt 1: An IRQ0 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ0 0: An IRQ0 interrupt has not been detected 0: An IRQ0 interrupt has not been detected Rev. 5.00 Mar. 15, 2007 Page 94 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) 6.3.4 Interrupt Priority Registers A to G (IPRA to IPRG) Interrupt priority registers are seven 16-bit readable/writable registers that set priority levels from 0 to 15 for interrupts except NMI. For the correspondence between interrupt request sources and IPR, refer to table 6.2 Interrupt Request Sources, Vector Address, and Interrupt Priority Level. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 to H'F in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved bits that are not assigned should be set H'0 (B'0000). Bit 15 14 13 12 Bit Name IPR15 IPR14 IPR13 IPR12 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) Rev. 5.00 Mar. 15, 2007 Page 95 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) Bit 11 10 9 8 Bit Name IPR11 IPR10 IPR9 IPR8 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) 7 6 5 4 IPR7 IPR6 IPR5 IPR4 0 0 0 0 R/W R/W R/W R/W Set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) Rev. 5.00 Mar. 15, 2007 Page 96 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) Bit 3 2 1 0 Bit Name IPR3 IPR2 IPR1 IPR0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) Note: Name in the tables above is represented by a general name. Name in the list of register is, on the other hand, represented by a module name. 6.4 6.4.1 Interrupt Sources External Interrupts There are five types of interrupt sources: User break, NMI, H-UDI, IRQ, and on-chip peripheral modules. Individual interrupts are given priority levels (0 to 16, with 0 the lowest and 15 the highest). Giving an interrupt a priority level of 0 masks it. NMI Interrupt: The NMI interrupt is given a priority level of 16 and is always accepted. An NMI interrupt is detected at the edge of the pins. Use the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0) to select either the rising or falling edge. In the NMI interrupt exception handler, the interrupt mask level bits (I3 to I0) in the status register (SR) are set to level 15. Rev. 5.00 Mar. 15, 2007 Page 97 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) IRQ7 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ7. Use the IRQ sense select bits (IRQ71S to IRQ 01S and IRQ70S to IRQ00S) in the IRQ control register (IRQCR) to select the detection mode from low level detection, falling edge detection, rising edge detection, and both edge detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt priority registers A and B (IPRA and IPRB). In the case that the low level detection is selected, an interrupt request signal is sent to the INTC while the IRQ pin is driven low. The interrupt request signal stops to be sent to the INTC when the IRQ pin becomes high. It is possible to confirm that an interrupt is requested by reading the IRQ flags (IRQ7F to IRQ0F) in the IRQ status register (IRQSR). In the case that the edge detection is selected, an interrupt request signal is sent to the INTC when the following change on the IRQ pin is detected: from high to low in falling edge detection mode, from low to high in rising edge detection mode, and from low to high or from high to low in both edge detection mode. The IRQ interrupt request by detecting the change on the pin is held until the interrupt request is accepted. It is possible to confirm that an IRQ interrupt request has been detected by reading the IRQ flags (IRQ7F to IRQ0F) in the IRQ status register (IRQSR). An IRQ interrupt request by detecting the change on the pin can be withdrawn by writing 0 to an IRQ flag after reading 1. In the IRQ interrupt exception handling, the interrupt mask bits (I3 to I0) in the status register (SR) are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block diagram of the IRQ7 to IRQ0 interrupts. IRQSR.IRQnL IRQCR.IRQn1S IRQCR.IRQn0S IRQSR.IRQnF Selection IRQn pins Level detection Edge detection S Q CPU interrupt request RESIRQn (Acceptance of IRQn interrupt/ writing 0 after reading IRQnF = 1) R n = 7 to 0 Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control Rev. 5.00 Mar. 15, 2007 Page 98 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) 6.4.2 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules. Since a different interrupt vector is allocated to each interrupt source, the exception handling routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be allocated to individual on-chip peripheral modules in interrupt priority registers C to G (IPRC to IPRG). On-chip peripheral module interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.4.3 User Break Interrupt A user break interrupt has a priority level of 15, and occurs when the break condition set in the user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are held until accepted. User break interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. For more details on the user break interrupt, see section 20, User Break Controller (UBC). 6.4.4 H-UDI Interrupt User debugging interface (H-UDI) interrupt has a priority level of 15, and occurs when an H-UDI interrupt instruction is serially input. H-UDI interrupt requests are detected by edge and are held until accepted. H-UDI exception handling sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. For more details on the H-UDI interrupt, see section 21, User Debugging Interface (H-UDI). Rev. 5.00 Mar. 15, 2007 Page 99 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) 6.5 Interrupt Exception Handling Vector Table Table 6.2 lists interrupt sources, their vector numbers, vector table address offsets, and interrupt priorities. Individual interrupt sources are allocated to different vector numbers and vector table address offsets. Vector table addresses are calculated from the vector numbers and vector table address offsets. For interrupt exception handling, the start address of the exception handling routine is fetched from the vector table address in the vector table. For the details on calculation of vector table addresses, see table 5.4, Calculating Exception Handling Vector Table Addresses in section 5, Exception Handling. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A to G (IPRA to IPRG). However, when interrupt sources whose priority levels are allocated with the same IPR are requested, the interrupt of the smaller vector number has priority. This priority cannot be changed. Priority levels of IRQ interrupts and on-chip peripheral module interrupts are initialized to level 0 at a power-on reset. If the same priority level is allocated to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priority order shown in table 6.2. Table 6.2 Interrupt Source User break External pin H-UDI External pin IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 NMI Interrupt Exception Handling Vectors and Priorities Name Vector No. 12 11 13 64 65 66 67 80 81 82 83 Vector Table Starting Address H'00000030 H'0000002C H'00000034 H'00000100 H'00000104 H'00000108 H'0000010C H'00000140 H'00000144 H'00000148 H'0000014C IPR    IPRA15 to IPRA12 IPRA11 to IPRA8 IPRA7 to IPRA4 IPRA3 to IPRA0 IPRB15 to IPRB12 IPRB11 to IPRB8 IPRB7 to IPRB4 IPRB3 to IPRB0 Low Default Priority High Rev. 5.00 Mar. 15, 2007 Page 100 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) Interrupt Source WDT E-DMAC CMT channel 0 CMT channel 1 SCIF channel 0 Name ITI EINT0 CMI0 CMI1 ERI_0 RXI_0 BRI_0 TXI_0 Vector No. 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 104 105 106 107 108 Vector Table Starting Address H'00000150 H'00000154 H'00000158 H'0000015C H'00000160 H'00000164 H'00000168 H'0000016C H'00000170 H'00000174 H'00000178 H'0000017C H'00000180 H'00000184 H'00000188 H'0000018C H'00000190 H'00000194 H'000001A0 H'000001A4 H'000001A8 H'000001AC H'000001B0 IPR IPRC15 to IPRC12 IPRC11 to IPRC8 IPRC7 to IPRC4 IPRC3 to IPRC0 IPRD15 to IPRD12 Default Priority Hight SCIF channel 1 ERI_1 RXI_1 BRI_1 TXI_1 IPRD11 to IPRD8 SCIF channel 2 ERI_2 RXI_2 BRI_2 TXI_2 IPRD7 to IPRD4 HIF HIFI HIFBI IPRE15 to IPRE12 IPRE11 to IPRE8 IPRF15 to IPRF12 IPRF11 to IPRF8 IPRF7 to IPRF4 IPRF3 to IPRF0 IPRG15 to IPRG12 Low DMAC DEI0 DEI1 DEI2 DEI3 SIOF SIOFI Rev. 5.00 Mar. 15, 2007 Page 101 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) 6.6 6.6.1 Interrupt Operation Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt from interrupt requests sent, according to the priority levels set in interrupt priority level setting registers A to G (IPRA to IPRG). Interrupts that have lower-priority than that of the selected interrupt are ignored*. If interrupts that have the same priority level or interrupts within a same module occur simultaneously, the interrupt with the highest priority is selected according to the priority shown in table 6.2. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the priority level of the selected request is equal to or less than the level set in bits I3 to I0, the request is ignored. If the priority level of the selected request is higher than the level in bits I3 to I0, the interrupt controller accepts the request and sends an interrupt request signal to the CPU. 4. The CPU detects the interrupt request sent from the interrupt controller in the decode stage of an instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception handling (see figure 6.5). 5. SR and PC are saved onto the stack. 6. The priority level of the accepted interrupt is copied to bits (I3 to I0) in SR. 7. The CPU reads the start address of the exception handling routine from the exception vector table for the accepted interrupt, branches to that address, and starts executing the program. This branch is not a delayed branch. Note: * Interrupt requests that are designated as edge-detect type are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ status register (IRQSR). Interrupts held pending due to edge detection are cleared by a power-on reset or an H-UDI reset. Rev. 5.00 Mar. 15, 2007 Page 102 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) Program execution state Interrupt? Yes User break? Yes No No NMI? Yes No H-UDI interrupt? Yes No Level 15 interrupt? Yes No I3 to I0 ≤ level 14? Yes Yes No I3 to I0 ≤ level 14? No Yes Level 14 interrupt? Yes I3 to I0 ≤ level 13? No Yes No Level 1 interrupt? Yes I3 to I0 = level 0? No No Save SR to stack Save PC to stack Copy interrupt level to I3 to I0 Read exception vector table Branch to exception handling routine Note: I3 to I0 are Interrupt mask bits in the status register (SR) of the CPU Figure 6.3 Interrupt Sequence Flowchart Rev. 5.00 Mar. 15, 2007 Page 103 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) 6.6.2 Stack after Interrupt Exception Handling Figure 6.4 shows the stack after interrupt exception handling. Address 4n – 8 4n – 4 4n PC*1 SR 32 bits 32 bits SP*2 Notes: 1. PC is the start address of the next instruction (instruction at the return address) after the executed instruction. 2. Always make sure that SP is a multiple of 4 Figure 6.4 Stack after Interrupt Exception Handling 6.7 Interrupt Response Time Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction of the interrupt handling routine begins. Figure 6.5 shows an example of the pipeline operation when an IRQ interrupt is accepted. Rev. 5.00 Mar. 15, 2007 Page 104 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) Table 6.3 Interrupt Response Time Number of Cycles Item Interrupt priority decision and comparison with mask bits in SR Wait for completion of sequence currently being executed by CPU NMI, H-UDI 1 × Icyc + 2 × Pcyc IRQ, Peripheral Modules 1 × Icyc + 3 × Pcyc Remarks X (≥ 0) X (≥ 0) The longest sequence is for interrupt or addresserror exception handling (X = 7 × Icyc + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Performs the saving PC and SR, and vector address fetch. Time from start of interrupt exception handling until fetch of first instruction of exception handling routine starts Interrupt response time Total: 8 × Icyc + m1 + m2 8 × Icyc + m1 + m2 + m3 + m3 9 × Icyc + 2 × Pcyc + m1 + m2 + m3 +X 12 × Icyc + 2 × Pcyc 9 × Icyc + 3 × Pcyc + m1 + m2 + m3 +X 12 × Icyc + 3 × Pcyc SR, PC, and vector table are all in on-chip RAM, or cache hit occurs (in write back mode). Minimum*: Maximum: 16 × Icyc + 2 × Pcyc + 2 × (m1 + m2 + m3) + m4 16 × Icyc + 3 × Pcyc + 2 × (m1 + m2 + m3) + m4 Notes: * In the case that m1 = m2 = m3 = m4 = 1 × Icyc. m1 to m4 are the number of cycles needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine Rev. 5.00 Mar. 15, 2007 Page 105 of 794 REJ09B0237-0500 Section 6 Interrupt Controller (INTC) Rev. 5.00 Mar. 15, 2007 Page 106 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Section 7 Bus State Controller (BSC) The bus state controller (BSC) outputs control signals for various types of memory that is connected to the external address space and external devices. The BSC functions enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices. 7.1 Features The BSC has the following features. • External address space  A maximum 32 or 64 Mbytes for each of the areas, CS0, CS3, CS4, CS5B, and CS6B, totally 256 Mbytes (divided into five areas)  A maximum 64 Mbytes for each of the six areas, CS0, CS3, CS4, CS5, and CS6, totally 320 Mbytes (divided into five areas)  Can specify the normal space interface, byte-selection SRAM, SDRAM, PCMCIA for each address space  Can select the data bus width (8, 16, or 32 bits) for each address space. (The CS0 data bus width can only be selected from 8 or 16 bits.)  Can control the insertion of wait cycles for each address space  Can control the insertion of wait cycles for each read access and write access  Can control the insertion of idle cycles in the consecutive access for five cases independently: read-write (in same space/different space), read-read (in same space/different space), or the first cycle is a write access • Normal space interface  Supports the interface that can directly connect to the SRAM • SDRAM interface  Can connect directly to SDRAM in area 3  Multiplex output for row address/column address  Efficient access by single read/single write  High-speed access by bank-active mode  Supports auto-refreshing and self-refreshing Rev. 5.00 Mar. 15, 2007 Page 107 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) • Byte-selection SRAM interface  Can connect directly to byte-selection SRAM • PCMCIA direct interface  Supports IC memory cards and I/O card interfaces defined in the JEIDA specifications Ver 4.2 (PCMCIA2.1 Rev 2.1)  Controls the insertion of wait cycles by software  Supports the bus sizing function of the I/O bus width (only in little endian mode) • Refresh function  Supports the auto-refreshing and self-refreshing functions  Specifies the refresh interval by setting the refresh counter and clock selection  Can execute consecutive refresh cycles by specifying the refresh counts (1, 2, 4, 6, or 8) Rev. 5.00 Mar. 15, 2007 Page 108 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) The block diagram of the BSC is shown in figure 7.1. Bus mastership controller CMNCR Internal bus Internal master module Internal slave module CS0WCR WAIT Wait controller ... ... CS6BWCR RWTCNT CS0, CS3, CS4, CS5B (CE1A), CS6B (CE1B) MD5 A25 to A0, D31 to D0, BS, RD/WR, RD, WE3 (BE3, DQMUU), WE2 (BE2, DQMUU), WE1 (BE1, DQMUU,WE), WE0 (BE0, DQMLL), ICIOWR, ICIORD, RAS, CAS, CKE, CE2A, CE2B IOIS16 CS6BBCR Memory controller SDCR RTCSR RTCNT Refresh controller Comparator RTCOR BSC Common control register CSn space wait control register (n = 0, 3, 4, 5B, 6B) Reset wait counter CSn space bus control register (n = 0, 3, 4, 5B, 6B) SDRAM control register Refresh timer control/status register Refresh timer counter Refresh time constant register [Legend] CMNCR: CSnWCR: RWTCNT: CSnBCR: SDCR: RTCSR: RTCNT: RTCOR: Figure 7.1 Block Diagram of BSC Rev. 5.00 Mar. 15, 2007 Page 109 of 794 REJ09B0237-0500 Module bus Area controller CS0BCR ... ... ... Section 7 Bus State Controller (BSC) 7.2 Input/Output Pins table 7.1 lists the pin configuration of the BSC. Table 7.1 Pin Configuration I/O Function Abbreviation A25 to A0 D31 to D0 BS Output Address Bus* I/O Data Bus Asserted when a normal space, burst ROM (clock synchronous /asynchronous), or PCMCIA is accessed. Asserted at the same timing as CAS assertion in SDRAM access. Output Bus Cycle Start CS0, CS3, CS4 Output Chip Select CS5B/CE1A CE2A CS6B/CE1B CE2B RD/WR RD ICIOWR ICIORD WE3(BE3) WE2(BE2) WE1(BE1)/WE Output Chip Select Chip enable for PCMCIA allocated to area 5 when PCMCIA is in use Output Chip enable for PCMCIA allocated to area 5 when PCMCIA is in use Output Chip Select Chip enable for PCMCIA allocated to area 6 when PCMCIA is in use Output Chip enable for PCMCIA allocated to area 6 when PCMCIA is in use Output Read/Write Connects to WE pins when SDRAM or byte-selection SRAM is used. Output Read Pulse Signal (read data output enable signal) Strobe signal to indicate a memory read cycle when PCMCIA is in use. Output Strobe signal to indicate I/O write when PCMCIA is in use. Output Strobe signal to indicate I/O read when PCMCIA is in use. Output Indicates that D31 to D24 are being written to. Connected to the byte select signal when byte-selection SRAM is in use. Output Indicates that D23 to D16 are being written to. Connected to the byte select signal when byte-selection SRAM is in use. Output Indicates that D15 to D8 are being written to. Connected to the byte select signal when byte-selection SRAM is in use. Strove signal to indicate a memory write cycle when PCMCIA is in use. Rev. 5.00 Mar. 15, 2007 Page 110 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Abbreviation WE0(BE0) I/O Function Output Indicates that D7 to D0 are being written to. Connected to the byte select signal when a byte-selection SRAM is in use. RAS CAS CKE IOIS16 Output Connected to RAS pin when SDRAM is in use. Output Connected to CAS pin when SDRAM is in use. Output Connected to CKE pin when SDRAM is in use. Input PCMCIA 16-bit I/O Signal Enabled only in little endian mode. Drive this signal low in big endian mode. DQMUU, DQMUL, DQMLU, DQMLL Output Connected to the DQMxx pin when SDRAM is in use. DQMUU: Select signal for D31 to D24 DQMUL: Select signal for D23 to D16 DQMLU: Select signal for D15 to D8 DQMLL: Select signal for D7 to D0 WAIT MD5, MD3 Note: * Input Input External wait input MD5: Selects data alignment (big endian or little endian) MD3: Specifies area 0 bus width (8/16 bits) As pins A25 to A16 act as general I/O ports immediately after a power-on reset, pull-up or pull-down these pins outside the LSI as needed. 7.3 7.3.1 Area Overview Area Division The architecture of this LSI has 32-bit address space. The upper three address bits divide the space into areas P0 to P4, and the cache access methods can be specified for each area. For details, see section 3, Cache. Each area indicated by the remaining 29 bits is divided into ten areas (five areas are reserved) when address map 1 is selected or eight areas (three areas are reserved) when address map 2 is selected. The address map is selected by the MAP bit in CMNCR. The BSC controls the areas indicated by the 29 bits. As listed in tables 7.2 and 7.3, memory can be connected directly to five physical areas of this LSI, and the chip select signals (CS0, CS3, CS4, CS5B, and CS6B) are output for each area. CS0 is asserted during area 0 access. Rev. 5.00 Mar. 15, 2007 Page 111 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) 7.3.2 Shadow Area Areas 0, 3, 4, 5B, and 6B are divided by decoding physical address bits A28 to A25, which correspond to areas 000 to 111. Address bits 31 to 29 are ignored. This means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address space in P1 to P3 areas obtained by adding to it H'20000000 × n (n = 1 to 6). The address range for area 7 is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 + H'20000000 × n to H'1FFFFFFF + H'20000000 × n (n = 0 to 6) corresponding to the area 7 shadow spaces are reserved, so do not use it. Area P4 (H'E0000000 to H'EFFFFFFF) is an I/O area and is allocated to internal register addresses. Therefore, area P4 does not become shadow space. H'00000000 H'20000000 H'40000000 H'60000000 H'80000000 P1 H'A0000000 P2 H'C0000000 P3 H'E0000000 P4 Address Space P0 Area 0 (CS0) Area 1 (reserved) Area 2 (reserved) Area 3 (CS3) Area 4 (CS4) Area 5A (reserved) Area 5B (CS5B) Area 6A (reserved) Area 6B (CS6B) Area 7 (reserved) Physical address space Figure 7.2 Address Space 7.3.3 Address Map The external address space has a capacity of 256 Mbytes and is divided into five areas. Types of memory to be connected and the data bus width are specified for individual areas. The address map for the external address space is shown in table 7.2. Rev. 5.00 Mar. 15, 2007 Page 112 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Table 7.2 Address Map 1 (CMNCR.MAP = 0) Area Area 0 Area 1 Area 2 Area 3 Memory to be Connected Normal memory Reserved area* Reserved area* Normal memory Byte-selection SRAM SDRAM Capacity 64 Mbytes 64 Mbytes 64 Mbytes 64 Mbytes Physical Address H'00000000 to H'03FFFFFF H'04000000 to H'07FFFFFF H'08000000 to H'0BFFFFFF H'0C000000 to H'0FFFFFFF H'10000000 to H'13FFFFFF H'14000000 to H'15FFFFFF H'16000000 to H'17FFFFFF H'18000000 to H'19FFFFFF H'1A000000 to H'1BFFFFFF H'1C000000 to H'1FFFFFFF Note: * Area 4 Area 5A Area 5B Area 6A Area 6B Area 7 Normal memory Byte-selection SRAM Reserved area* Normal memory Byte-selection SRAM Reserved area* Normal memory Byte-selection SRAM Reserved area* 64 Mbytes 32 Mbytes 32 Mbytes 32 Mbytes 32 Mbytes 64 Mbytes Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. Table 7.3 Address Map 2 (CMNCR.MAP = 1) Area Area 0 Area 1 Area 2 Area 3 Memory to be Connected Normal memory Reserved area* Reserved area* 1 1 Physical Address H'00000000 to H'03FFFFFF H'04000000 to H'07FFFFFF H'08000000 to H'0BFFFFFF H'0C000000 to H'0FFFFFFF Capacity 64 Mbytes 64 Mbytes 64 Mbytes 64 Mbytes Normal memory Byte-selection SRAM SDRAM H'10000000 to H'13FFFFFF H'14000000 to H'17FFFFFF Area 4 Area 5* 2 Normal memory Byte-selection SRAM Normal memory Byte-selection SRAM PCMCIA 64 Mbytes 64 Mbytes Rev. 5.00 Mar. 15, 2007 Page 113 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Physical Address H'18000000 to H'1BFFFFFF Area Area 6* 2 Memory to be Connected Normal memory Byte-selection SRAM PCMCIA Capacity 64 Mbytes H'1C000000 to H'1FFFFFFF Area 7 Reserved area*1 64 Mbytes Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 2. For area 5, CS5BBCR and CS5BWCR are enabled. For area 6, CS6BBCR and CS6BWCR are enabled. 7.3.4 Area 0 Memory Type and Memory Bus Width The memory bus width in this LSI can be set for each area. In area 0, the bus width is selected from 8 bits and 16 bits at a power-on reset by the external pin setting. The bus width of other areas is set by the register. The correspondence between the memory type, external pin (MD3), and bus width is listed in table 7.4. Table 7.4 MD3 1 0 Correspondence between External Pin (MD3), Memory Type, and Bus Width for CS0 Memory Type Normal memory Bus Width 8 bits 16 bits 7.3.5 Data Alignment This LSI supports the big endian and little endian methods of data alignment. The data alignment is specified using the external pin (MD5) at a power-on reset as shown in table 7.5. Table 7.5 MD5 0 1 Correspondence between External Pin (MD5) and Endians Endian Big endian Little endian Rev. 5.00 Mar. 15, 2007 Page 114 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) 7.4 Register Descriptions The BSC has the following registers. For the addresses and access size for these registers, see section 24, List of Registers. Do not access spaces other than CS0 until setting the memory interfaces is complete. • • • • • • • • • • • • • • • Common control register (CMNCR) CS0 space bus control register for area 0 (CS0BCR) CS3 space bus control register for area 3 (CS3BCR) CS4 space bus control register for area 4 (CS4BCR) CS5B space bus control register for area 5B (CS5BBCR) CS6B space bus control register for area 6B (CS6BBCR) CS0 space wait control register for area 0 (CS0WCR) CS3 space wait control register for area 3 (CS3WCR) CS4 space wait control register for area 4 (CS4WCR) CS5B space wait control register for area 5B (CS5BWCR) CS6B space wait control register for area 6B (CS6BWCR) SDRAM control register (SDCR) Refresh timer control/status register (RTCSR) Refresh timer counter (RTCNT) Refresh time constant register (RTCOR) Rev. 5.00 Mar. 15, 2007 Page 115 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) 7.4.1 Common Control Register (CMNCR) CMNCR is a 32-bit register that controls the common items for each area. Do not access external memory other than area 0 until setting CMNCR is complete. Bit 31 to 13 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 MAP 0 R/W Space Specification Selects the address map for the external address space. The address maps to be selected are shown in tables 7.2 and 7.3. 0: Selects address map 1 1: Selects address map 2 11 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4  1 R Reserved This bit is always read as 1. The write value should always be 1. 3 ENDIAN 0/1* R Endian Flag Fetches the external pin (MD5) state for specifying endian at a power-on reset. The endian setting for all the address spaces are set by this bit. This is a read-only bit. 0: External pin (MD5) for specifying endian was driven low at a power-on reset. This LSI is operated as big endian. 1: External pin (MD5) for specifying endian was driven high at a power-on reset. This LSI is being operated as little endian. 2  1 R Reserved This bit is always read as 1. The write value should always be 1. Rev. 5.00 Mar. 15, 2007 Page 116 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 1 Bit Name HIZMEM Initial Value 0 R/W R/W Description Hi-Z Memory Control Specifies the pin state in standby mode for pins A25 to A0, BS, CSn, RD/WR, WEn (BEn)/DQMxx, and RD. 0: High impedance in standby mode 1: Driven in standby mode 0 HIZCNT 0 R/W Hi-Z Control Specifies the pin state in standby mode for the CKIO, CKE, RAS, and CAS pins. 0: High impedance in standby mode 1: Driven in standby mode Note: * The external pin (MD5) state for specifying endian is sampled at a power-on reset. When big endian is specified, this bit is read as 0 and when little endian is specified, this bit is read as 1. 7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5B, 6B) CSnBCR specifies the type of memory connected to each space, data-bus width of each space, and the number of wait cycles between access cycles. Do not access external memory other than area 0 until setting CSnBCR is completed. Bit 31, 30 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 29 28 IWW1 IWW0 1 1 R/W R/W Idle Cycles between Write-Read Cycles and Write-Write Cycles Specify the number of idle cycles to be inserted after the access to a memory that is connected to the area. The write and read cycles or write and write cycles performed consecutively are the target cycle. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted Rev. 5.00 Mar. 15, 2007 Page 117 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 27 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 26 25 IWRWD1 IWRWD0 1 1 R/W R/W Idle Cycles for Another Space Read-Write Specify the number of idle cycles to be inserted after the access to a memory that is connected to the area. The read and write cycles which are performed consecutively and are accessed to different areas are the target cycle. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 24  0 R Reserved This bit is always read as 0. The write value should always be 0. 23 22 IWRWS1 IWRWS0 1 1 R/W R/W Idle Cycles for Read-Write in Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the area. The read and write cycles which are performed consecutively and are accessed to the same area are the target cycle. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 21  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 118 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 20 19 Bit Name IWRRD1 IWRRD0 Initial Value 1 1 R/W R/W R/W Description Idle Cycles for Read-Read in Another Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the area. The read and read cycles which are performed consecutively and are accessed to different areas are the target cycle. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 18  0 R Reserved This bit is always read as 0. The write value should always be 0. 17 16 IWRRS1 IWRRS0 1 1 R/W R/W Idle Cycles for Read-Read in Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the area. The read and read cycles which are performed consecutively and are accessed to the same area are the target cycle. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted Rev. 5.00 Mar. 15, 2007 Page 119 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 15 14 13 12 Bit Name TYPE3 TYPE2 TYPE1 TYPE0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Memory Type Specify the type of memory connected to the area. 0000: Normal space 0001: Reserved (setting prohibited) 0010: Reserved (setting prohibited) 0011: Byte-selection SRAM 0100: SDRAM 0101: PCMCIA 0110: Reserved (setting prohibited) 0111: Reserved (setting prohibited) 1000: Reserved (setting prohibited) 1001: Reserved (setting prohibited) 1010: Reserved (setting prohibited) 1011: Reserved (setting prohibited) 1100: Reserved (setting prohibited) 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) For details on memory type in each area, see tables 7.2 and 7.3. Reserved This bit is always read as 0. The write value should always be 0. 11  0 R Rev. 5.00 Mar. 15, 2007 Page 120 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 10 9 Bit Name BSZ1 BSZ0 Initial Value 1* 1* R/W R/W R/W Description Data Bus Size Specify the data bus width of each area. 00: Reserved (setting prohibited) 01: 8 bits 10: 16 bits 11: 32 bits Notes: 1. The data bus width for area 0 is specified by the external pin. These bits are ignored. 2. When area 5 or 6 is specified as PCMCIA space, the bus width can be specified as either 8 bits or 16 bits. 3. If area 3 is specified as SDRAM space, the bus width cannot be specified as 8 bits. 4. These bits must be specified to either 01 or 11 before accessing to memory in other than area 0. 8 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * CS0BCR fetches the external pin state (MD3) that specify the bus width at a power-on reset. Rev. 5.00 Mar. 15, 2007 Page 121 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) 7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 3, 4, 5B, 6B) CSnWCR specifies various wait cycles for memory accesses. The bit configuration of this register varies as shown below according to the memory type (TYPE3, TYPE2, TYPE1, or TYPE0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. Specify CSnBCR first, then specify CSnWCR. Normal Space, Byte-Selection SRAM: • CS0WCR Bit 31 to 13 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn (BEn) Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn (BEn) assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 5.00 Mar. 15, 2007 Page 122 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 10 9 8 7 Bit Name WR3 WR2 WR1 WR0 Initial Value 1 0 1 0 R/W R/W R/W R/W R/W Description Number of Access Wait Cycles Specify the number of wait cycles that are necessary for read or write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored 6 WM 0 R/W 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Number of Delay Cycles from RD, WEn (BEn) negation to Address, CSn negation Specify the number of delay cycles from RD and WEn (BEn) negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 5.00 Mar. 15, 2007 Page 123 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) • CS3WCR Bit 31 to 21 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W Byte Access Selection for Byte-Selection SRAM Specifies the WEn (BEn) and RD/WR signal timing when the byte-selection SRAM interface is used. 0: Asserts the WEn (BEn) signal at the read/write timing (signal used as strobe) and asserts the RD/WR signal during the write access cycle (signal used as status) 1: Asserts the WEn (BEn) signal during the read/write access cycle (used as status) and asserts the RD/WR signal at the write timing (used as strobe) 19 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 9 8 7 WR3 WR2 WR1 WR0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of wait cycles that are necessary for read access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Rev. 5.00 Mar. 15, 2007 Page 124 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 6 Bit Name WM Initial Value 0 R/W R/W Description External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. • CS4WCR Bit 31 to 21 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W Byte Access Selection for Byte-Selection SRAM Specifies the WEn (BEn) and RD/WR signal timing when the byte-selection SRAM interface is used. 0: Asserts the WEn (BEn) signal at the read/write timing (signal used as strobe) and asserts the RD/WR signal during the write access cycle (signal used as status) 1: Asserts the WEn (BEn) signal during the read/write access cycle (signal used as status)and asserts the RD/WR signal at the write timing (signal used as strobe) 19  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 125 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 18 17 16 Bit Name WW2 WW1 WW0 Initial Value 0 0 0 R/W R/W R/W R/W Description Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: Same number of cycles as WR3 to WR0 setting (read access wait) 001: 0 cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn (BEn) Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn (BEn) assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 5.00 Mar. 15, 2007 Page 126 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 10 9 8 7 Bit Name WR3 WR2 WR1 WR0 Initial Value 1 0 1 0 R/W R/W R/W R/W R/W Description Number of Access Wait Cycles Specify the number of wait cycles that are necessary for read access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait is valid 1: External wait is ignored 6 WM 0 R/W 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Number of Delay Cycles from RD, WEn (BEn) negation to Address, CSn negation Specify the number of delay cycles from RD and WEn (BEn) negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 5.00 Mar. 15, 2007 Page 127 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) • CS5BWCR Bit 31 to 19 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 18 17 16 WW2 WW1 WW0 0 0 0 R/W R/W R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: Same number of cycles as WR3 to WR0 setting (read access wait) 001: 0 cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn (BEn) Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn (BEn) assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 5.00 Mar. 15, 2007 Page 128 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 10 9 8 7 Bit Name WR3 WR2 WR1 WR0 Initial Value 1 0 1 0 R/W R/W R/W R/W R/W Description Number of Access Wait Cycles Specify the number of wait cycles that are necessary for read access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored 6 WM 0 R/W 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Number of Delay Cycles from RD, WEn (BEn) negation to Address, CSn negation Specify the number of delay cycles from RD and WEn (BEn) negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 5.00 Mar. 15, 2007 Page 129 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) • CS6BWCR Bit 31 to 21 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W Byte Access Selection for Byte-Selection SRAM Specifies the WEn (BEn) and RD/WR signal timing when the byte-selection SRAM interface is used. 0: Asserts the WEn (BEn) signal at the read/write timing (signal used as strobe) and asserts the RD/WR signal during the write access cycle (signal used as status) 1: Asserts the WEn (BEn) signal during the read/write access cycle (used as status) and asserts the RD/WR signal at the write timing (used as strobe) 19 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn (BEn) Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn (BEn) assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 5.00 Mar. 15, 2007 Page 130 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 10 9 8 7 Bit Name WR3 WR2 WR1 WR0 Initial Value 1 0 1 0 R/W R/W R/W R/W R/W Description Number of Access Wait Cycles Specify the number of wait cycles that are necessary for read or write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored 6 WM 0 R/W 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Number of Delay Cycles from RD, WEn (BEn) negation to Address, CSn negation Specify the number of delay cycles from RD and WEn (BEn) negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 5.00 Mar. 15, 2007 Page 131 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) SDRAM: • CS3WCR Bit 31 to 15 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 14 13 WTRP1 WTRP0 0 0 R/W R/W Wait Cycle Number for Precharge Completion Specify the number of minimum wait cycles inserted to wait for the completion of precharge in the following cases. • • • • From the start of auto-precharge to the issuing of the ACTV command for the same bank. From the issuing of the PRE/PALL command to the issuing of the ACTV command for the same bank. From the issuing of the PALL command during autorefreshing to the issuing of the REF command. From the issuing of the PALL command during selfrefreshing to the issuing of the SELF command. 00: 0 cycle (no wait cycle) 01: 1 cycle 10: 2 cycles 11: 3 cycles 12  0 R Reserved This bit is always read as 0. The write value should always be 0. 11 10 WTRCD1 WTRCD0 0 1 R/W R/W Wait Cycle Number from ACTV Command to READ(A)/WRIT(A) Command Specify the number of minimum wait cycles from issuing the ACTV command to issuing the READ(A)/WRIT(A) command. 00: 0 cycle (no wait cycle) 01: 1 cycle 10: 2 cycles 11: 3 cycles Rev. 5.00 Mar. 15, 2007 Page 132 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 9 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 8 7 A3CL1 A3CL0 1 0 R/W R/W CAS Latency for Area 3. Specify the CAS latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: Reserved (setting prohibited) 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 3 TRWL1 TRWL0 0 0 R/W R/W Wait Cycle Number for Precharge Start Wait Specify the number of minimum wait cycles inserted to wait for the start of precharge in the following cases. • From the issuing of the WRITA command by this LSI to the start of the auto-precharge in the SDRAM. The ACTV command for the same bank is issued after issuing the WRITA command in non-bank active mode. To confirm how many cycles should be needed in the SDRAM between receiving the WRITA command and the auto-precharge start, refer to the data sheets for each SDRAM. Set this bit so that the cycle number in that data sheets should not exceed the cycle number set by this bit. • From the issuing of the WRIT command by this LSI to the issuing of the PRE command. A different row address in the same bank is accessed in bank active mode. 00: 0 cycle (no wait cycle) 01: 1 cycle 10: 2 cycles 11: 3 cycles Rev. 5.00 Mar. 15, 2007 Page 133 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 2 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 1 0 WTRC1 WTRC0 0 0 R/W R/W Idle Cycle Number from REF Command/Self-Refreshing Release to ACTV/REF/MRS Command Specify the number of minimum idle cycles in the following cases. • • From the issuing of the REF command to the issuing of the ACTV/REF/MRS command. From the self-refreshing release to the issuing of the ACTV/REF/MRS command. 00: 2 cycles 01: 3 cycles 10: 5 cycles 11: 8 cycles PCMCIA: • CS5BWCR, CS6BWCR Bit 31 to 22 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21 20 SA1 SA0 0 0 R/W R/W Space Attribute Specification Specify memory card interface or I/O card interface when the PCMCIA interface is selected. • SA1 0: Specifies memory card interface when A25 = 1 1: Specifies I/O card interface when A25 = 1 • SA0 0: Specifies memory card interface when A25 = 0 1: Specifies I/O card interface when A25 = 0 Rev. 5.00 Mar. 15, 2007 Page 134 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 19 to 15 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 14 13 12 11 TED3 TED2 TED1 TED0 0 0 0 0 R/W R/W R/W R/W Delay from Address to RD or WE Assert Specify the delay time from address output to RD or WE assertion in PCMCIA interface. 0000: 0.5 cycles 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: Reserved (setting prohibited) 1001: Reserved (setting prohibited) 1010: Reserved (setting prohibited) 1011: Reserved (setting prohibited) 1100: Reserved (setting prohibited) 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Rev. 5.00 Mar. 15, 2007 Page 135 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 10 9 8 7 Bit Name PCW3 PCW2 PCW1 PCW0 Initial Value 1 0 1 0 R/W R/W R/W R/W R/W Description Number of Access Wait Cycles Specify the number of wait cycles to be inserted. 0000: 3 cycles 0001: 6 cycles 0010: 9 cycles 0011: 12 cycles 0100: 15 cycles 0101: 18 cycles 0110: 22 cycles 0111: 26 cycles 1000: 30 cycles 1001: 33 cycles 1010: 36 cycles 1011: 38 cycles 1100: 52 cycles 1101: 60 cycles 1110: 64 cycles 1111: 80 cycles External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored 6 WM 0 R/W 5, 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 136 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 3 2 1 0 Bit Name TEH3 TEH2 TEH1 TEH0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Delay from RD or WE Negate to Address Specify the address hold time from RD or WE negation in the PCMCIA interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles Rev. 5.00 Mar. 15, 2007 Page 137 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) 7.4.4 SDRAM Control Register (SDCR) SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be connected. Bit 31 to 12 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 RFSH 0 R/W Refresh Control Specifies whether or not the refreshing SDRAM is performed. 0: Refreshing is not performed 1: Refreshing is performed 10 RMODE 0 R/W Refresh Control Specifies whether to perform auto-refreshing or selfrefreshing when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 1, self-refreshing starts immediately. When the RFSH bit is 1 and this bit is 0, auto-refreshing starts according to the contents that are set in RTCSR, RTCNT, and RTCOR. 0: Auto-refreshing is performed 1: Self-refreshing is performed 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8 BACTV 0 R/W Bank Active Mode Specifies whether to access in auto-precharge mode (using READA and WRITA commands) or in bank active mode (using READ and WRIT commands). 0: Auto-precharge mode (using READA and WRITA commands) 1: Bank active mode (using READ and WRIT commands) 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 138 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 4 3 Bit Name A3ROW1 A3ROW0 Initial Value 0 0 R/W R/W R/W Description Number of Bits of Row Address for Area 3 Specify the number of bits of the row address for area 3. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1 0 A3COL1 A3COL0 0 0 R/W R/W Number of Bits of Column Address for Area 3 Specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited) 7.4.5 Refresh Timer Control/Status Register (RTCSR) RTCSR specifies various items about refresh for SDRAM. When RTCSR is written to, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit 31 to 8 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 139 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 7 Bit Name CMF Initial Value 0 R/W R/W Description Compare Match Flag Indicates that a compare match occurs between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR). [Clearing condition] When 0 is written to this bit after reading RTCSR with CMF = 1. [Setting condition] When RTCNT value matches RTCOR value 6  0 R Reserved This bit is always read as 0. The write value should always be 0. 5 4 3 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select Select the clock input to count-up the refresh timer counter (RTCNT). 000: Stop the counting-up 001: Bφ/4 010: Bφ/16 011: Bφ/64 100: Bφ/256 101: Bφ/1024 110: Bφ/2048 111: Bφ/4096 Rev. 5.00 Mar. 15, 2007 Page 140 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Bit 2 1 0 Bit Name RRC2 RRC1 RRC0 Initial Value 0 0 0 R/W R/W R/W R/W Description Refresh Count Specify the number of consecutive refresh cycles, when the refresh request occurs after the coincidence of the values of the refresh timer counter (RTCNT) and the refresh time constant register (RTCOR). Using consecutive refresh cycles can prolong cycles between refreshing. 000: Once 001: Twice 010: 4 times 011: 6 times 100: 8 times 101: Reserved (setting prohibited) 110: Reserved (setting prohibited) 111: Reserved (setting prohibited) 7.4.6 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit counter that increments using the clock selected by bits CKS2 to CKS0 in RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When RTCNT is written to, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit 31 to 8 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 to 0  All 0 R/W 8-bit Counter Rev. 5.00 Mar. 15, 2007 Page 141 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) 7.4.7 Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1 and RTCNT is cleared to 0. When the RFSH bit in SDCR is 1, a memory refresh request is issued. The request is maintained until the refresh operation is performed. If the request is not processed when the next matching occurs, the previous request is ignored. When the RTCOR is written to, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit 31 to 8 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 to 0  All 0 R/W 8-bit Counter Rev. 5.00 Mar. 15, 2007 Page 142 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) 7.5 7.5.1 Operation Endian/Access Size and Data Alignment This LSI supports big endian, in which the most significant byte (MSByte) of multiple byte data is stored in the lower address, and little endian, in which the least significant byte (LSByte) of multiple byte data is stored in the lower address. Endian is specified at a power-on reset by the external pin (MD5). When pin MD5 is driven low at a power-on reset, the endian will become big endian and when pin MD5 is driven high at a power-on reset, the endian will become little endian. Three data bus widths (8, 16, and 32 bits) are available for normal memory and byte-selection SRAM. Two data bus widths (16 and 32 bits) are available for SDRAM. Two data bus widths (8 and 16 bits) are available for PCMCIA interface. Data alignment is performed in accordance with the data bus width of the device and endian. This also means that when longword data is read from a byte-width device, the read operation must be done four times. In this LSI, data alignment and conversion of data length is performed automatically between the respective interfaces. Tables 7.6 to 7.11 show the relationship between endian, device data width, and access unit. Table 7.6 32-Bit External Device/Big Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword access at 0 Strobe Signals WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0), D31 to D24 D23 to D16 D15 to D8 D7 to D0 DQMUU DQMUL DQMLU DQMLL Data 7 to 0    Data 15 to 8  Data 31 to 24  Data 7 to 0   Data 7 to 0  Data 23 to 16   Data 7 to 0   Data 15 to 8 Data 15 to 8    Data 7 to 0  Data 7 to 0 Data 7 to 0 Assert    Assert  Assert  Assert   Assert  Assert   Assert   Assert Assert    Assert  Assert Assert Rev. 5.00 Mar. 15, 2007 Page 143 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Table 7.7 16-Bit External Device/Big Endian Access and Data Alignment Data Bus Strobe Signals WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0), Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword access at 0 D31 to D24 D23 to D16 D15 to D8 D7 to D0 DQMUU DQMUL DQMLU DQMLL               Data 7 to 0  Data 7 to 0  Data 15 to 8 Data 15 to 8 Data 31 to 24 Data 15 to 8  Data 7 to 0  Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 23 to 16 Data 7 to 0                 Assert  Assert  Assert Assert Assert Assert  Assert  Assert Assert Assert Assert Assert 1st time  at 0 2nd time  at 2 Rev. 5.00 Mar. 15, 2007 Page 144 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Table 7.8 8-Bit External Device/Big Endian Access and Data Alignment Data Bus Strobe Signals WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0), Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 D31 to D24 D23 to D16 D15 to D8 D7 to D0 DQMUU DQMUL DQMLU DQMLL                             Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0                                     Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert 1st time  at 0 2nd time  at 1 Word access at 2 1st time  at 2 2nd time  at 3 Longword access at 0 1st time  at 0 2nd time  at 1 3rd time  at 2 4th time  at 3 Rev. 5.00 Mar. 15, 2007 Page 145 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Table 7.9 32-Bit External Device/Big Endian Access and Data Alignment Data Bus Strobe Signals WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0), Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword access at 0 D31 to D24 D23 to D16 D15 to D8 D7 to D0 DQMUU DQMUL DQMLU DQMLL    Data 7 to 0  Data 15 to 8 Data 31 to 24   Data 7 to 0   Data 7 to 0 Data 23 to 16  Data 7 to 0   Data 15 to 8  Data 15 to 8 Data 7 to 0    Data 7 to 0  Data 7 to 0    Assert  Assert Assert   Assert   Assert Assert  Assert   Assert  Assert Assert    Assert  Assert Rev. 5.00 Mar. 15, 2007 Page 146 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Table 7.10 16-Bit External Device/Little Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword access at 0 Strobe Signals WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0), D31 to D24 D23 to D16 D15 to D8 D7 to D0 DQMUU DQMUL DQMLU DQMLL                Data 7 to 0  Data 7 to 0 Data 15 to 8 Data 15 to 8 Data 15 to 8 Data 31 to 24 Data 7 to 0  Data 7 to 0  Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 23 to 16                  Assert  Assert Assert Assert Assert Assert Assert  Assert  Assert Assert Assert Assert 1st time  at 0 2nd time  at 2 Rev. 5.00 Mar. 15, 2007 Page 147 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Table 7.11 8-Bit External Device/Little Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Strobe Signals WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0), D31 to D24 D23 to D16 D15 to D8 D7 to D0 DQMUU DQMUL DQMLU DQMLL                             Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 23 to 16 Data 31 to 24                                     Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert 1st time  at 0 2nd time  at 1 Word access at 2 1st time  at 2 2nd time  at 3 Longword access at 0 1st time  at 0 2nd time  at 1 3rd time  at 2 4th time  at 3 Rev. 5.00 Mar. 15, 2007 Page 148 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) 7.5.2 Normal Space Interface Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byteselection pin, see section 7.5.6, Byte-Selection SRAM Interface. Figure 7.3 shows the basic timings of normal space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. T1 CKIO T2 A CSn RD/WR Read RD D RD/WR WEn(BEn) Write D BS Figure 7.3 Normal Space Basic Access Timing (No-Wait Access) There is no output signal which informs external devices of the access size when reading. Although the least significant bit of the address indicates the correct address when the access starts, 16-bit data is always read from a 16-bit device. When writing, only the WEn (BEn) signal for the byte to be written to is asserted. When buffers are placed on the data bus, the RD signal should be used to control the buffers. The RD/WR signal indicates the same state as a read cycle (driven high) when no access has been Rev. 5.00 Mar. 15, 2007 Page 149 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) carried out. Therefore, care must be taken when controlling the buffers with the RD/WR signal, to avoid data conflict. Figures 7.4 and 7.5 show the basic timings of normal space consecutive access. If the WM bit in CSnWCR is cleared to 0, a Tnop cycle is inserted to check the external wait (figure 7.4). If the WM bit in CSnWCR is set to 1, an external wait request is ignored and no Tnop cycle is inserted (figure 7.5). T1 CKIO T2 Tnop T1 T2 A25 to A0 CSn RD/WR RD Read D WEn(BEn) Write D BS WAIT Figure 7.4 Consecutive Access to Normal Space (1): Bus Width = 16 bits, Longword Access, CSnWCR.WM = 0 (Access Wait = 0, Cycle Wait = 0) Rev. 5.00 Mar. 15, 2007 Page 150 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) T1 T2 T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D WEn(BEn) Write D BS WAIT Figure 7.5 Consecutive Access to Normal Space (2): Bus Width = 16 bits, Longword Access, CSnWCR.WM = 1 (Access Wait = 0, Cycle Wait = 0) Rev. 5.00 Mar. 15, 2007 Page 151 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) This LSI A18 .... 128 kwords × 8 bits SRAM A16 .... A2 CSn RD D31 .... A0 CS OE I/O7 .... D24 WE3(BE3) D23 D16 WE2(BE2) D15 D8 WE1(BE1) D7 .... .... .... I/O0 WE A16 .... A0 CS OE I/O7 .... D0 WE0(BE0) I/O0 WE A16 .... A0 CS OE I/O7 .... I/O0 WE A16 .... A0 CS OE I/O7 .... I/O0 WE Figure 7.6 Example of 32-Bit Data-Width SRAM Connection Rev. 5.00 Mar. 15, 2007 Page 152 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) This LSI •••• •••• 128 kwords × 8 bits SRAM •••• •••• •••• •••• A17 A1 CSn RD D15 •••• A16 A0 CS OE I/O7 I/O0 WE •••• •••• D0 WE0(BE0) •••• D8 WE1(BE1) D7 •••• •••• •••• A16 A0 CS OE I/O7 I/O0 WE Figure 7.7 Example of 16-Bit Data-Width SRAM Connection 128 kwords x 8 bits SRAM A16 This LSI A16 ... ... •••• A0 CSn RD D7 D0 WE0(BE0) A0 CS OE I/O7 ... ... I/O0 WE Figure 7.8 Example of 8-Bit Data-Width SRAM Connection Rev. 5.00 Mar. 15, 2007 Page 153 of 794 REJ09B0237-0500 ... ... Section 7 Bus State Controller (BSC) 7.5.3 Access Wait Control Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in read access and in write access. The areas other than 4, 5A, and 5B have the same access wait for read cycle and write cycle. The specified number of Tw cycles is inserted as wait cycles in a normal space access shown in figure 7.9. T1 Tw T2 CKIO A25 to A0 CSn RD/WR RD Read D WEn(BEn) Write D BS Figure 7.9 Wait Timing for Normal Space Access (Software Wait Only) When the WM bit in CSnWCR is cleared to 0, the external wait signal (WAIT) is also sampled. The WAIT pin sampling is shown in figure 7.10. In this example, two wait cycles are inserted as software wait. The WAIT signal is sampled at the falling edge of the CKIO signal in the cycle immediately before the T2 cycle (T1 or Tw cycle). Rev. 5.00 Mar. 15, 2007 Page 154 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) T1 CKIO A25 to A0 CSn RD/WR RD Read D WEn(BEn) Write D WAIT BS Tw Tw Wait cycles inserted by WAIT signal Twx T2 Figure 7.10 Wait Cycle Timing for Normal Space Access (Wait cycle Insertion using WAIT) Rev. 5.00 Mar. 15, 2007 Page 155 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) 7.5.4 Extension of Chip Select (CSn) Assertion Period The number of cycles from CSn assertion to RD and WEn (BEn) assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD and WEn (BEn) negation to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device can be obtained. Figure 7.11 shows an example. A Th cycle and a Tf cycle are added before and after a normal cycle, respectively. In these cycles, RD and WEn (BEn) are not asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful for devices with slow writing operations. Th T1 T2 Tf CKIO A25 to A0 CSn RD/WR RD Read D WEn(BEn) Write D BS Figure 7.11 Example of Timing when CSn Assertion Period is Extended Rev. 5.00 Mar. 15, 2007 Page 156 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) 7.5.5 SDRAM Interface SDRAM Direct Connection: The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in read and write command cycles. The control signals for direct connection of SDRAM are RAS, CAS, RD/WR, DQMUU, DQMUL, DQMLU, DQMLL, CKE, and CS3. Signals other than CKE are valid when CS3 is asserted. SDRAM can be connected to area 2. The data bus width of the area that is connected to SDRAM can be set to 16 bits or 32 bits. Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as the SDRAM operating mode. Commands for SDRAM can be specified by RAS, CAS, RD/WR, and specific address signals. These commands are shown below. • • • • • • • • • • • NOP Auto-refreshing (REF) Self-refreshing (SELF) All banks precharge (PALL) Specified bank precharge (PRE) Bank active (ACTV) Read (READ) Read with precharge (READA) Write (WRIT) Write with precharge (WRITA) Write mode register (MRS) The byte to be accessed is specified by DQMUU, DQMUL, DQMLU and DQMLL. Reading or writing is performed for a byte whose corresponding DQMxx is low. For details on the relationship between DQMxx and the byte to be accessed, refer to section 7.5.1, Endian/Access Size and Data Alignment. Rev. 5.00 Mar. 15, 2007 Page 157 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Figures 7.12 and 7.13 show an example of the connection of the SDRAM with the LSI. 64-Mbit SDRAM (1 Mword x 16 bits x 4 banks) A15 A13 This LSI .... A2 CKE CKIO CSn RAS CAS RD/WR D31 .... D16 DQMUU DQMUL D15 .... D0 DQMLU DQMLL Figure 7.12 Example of 32-Bit Data-Width SDRAM Connection Rev. 5.00 Mar. 15, 2007 Page 158 of 794 REJ09B0237-0500 .... I/O0 DQMU DQML .... A0 CKE CLK CS RAS CAS WE I/O15 .... I/O0 DQMU DQML A13 .... A0 CKE CLK CS RAS CAS WE I/O15 Section 7 Bus State Controller (BSC) This LSI A14 64-Mbit SDRAM (1 Mword x 16 bits x 4 banks) A13 A0 CKE CLK CS A1 CKE CKIO CSn ... RAS CAS RD/WR D15 RAS CAS WE I/O15 I/O0 DQMU DQML D0 DQMLU DQMLL Figure 7.13 Example of 16-Bit Data-Width SDRAM Connection Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ1 and BSZ0 in CSnBCR, AnROW1 and AnROW0 and AnCOL1 AnCOL0 in SDCR. Tables 7.12 to 7.17 show the relationship between those settings and the bits output on the address pins. Do not specify those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not multiplexed and the original values of address are always output on these pins. When the data bus width is 16 bits (BSZ[1:0] = B'10), pin A0 of SDRAM specifies a word address. Therefore, connect this A0 pin of SDRAM to pin A1 of this LSI; pin A1 pin of SDRAM to pin A2 of this LSI, and so on. When the data bus width is 32 bits (BSZ[1:0] = B'11), pin A0 of SDRAM specifies a long word address. Therefore, connect this A0 pin of SDRAM to pin A2 of this LSI; pin A1 pin of SDRAM to pin A3 of this LSI, and so on. ... Rev. 5.00 Mar. 15, 2007 Page 159 of 794 REJ09B0237-0500 ... ... Section 7 Bus State Controller (BSC) Table 7.12 Relationship between Register Settings (A3BSZ[1:0], A3ROW[1:0], and A3COL[1:0]) and Address Multiplex Output (1) Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 00 (11 bits) A2/3 COL [1:0] 00 (8 bits) Output Column Address A17 A16 A15 23 Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 01 (12 bits) A2/3 COL [1:0] 00 (8 bits) Output Column Address A17 A16 2 Output Pins of Output Row This LSI Address A17 A16 A15 A14 A13 A12 A25 A24 A23 A22* * A21* A20 2 Pins of SDRAM Function Unused Output Pins of Output Row This LSI Address A17 A16 A15 A24 A23 A23* A22* A21 A20 Pins of SDRAM Function Unused A23* A22* A13 L/H* 2 A22* * A21* L/H* 2 23 A12 (BA1) Specifies bank A11 (BA0) A10/AP Specifies address/ precharge Address A14 A13 A12 2 2 A13 (BA1) Specifies bank A12 (BA0) A11 Address Specifies address/ precharge Address 1 1 A10/AP A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Rev. 5.00 Mar. 15, 2007 Page 160 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 00 (11 bits) A2/3 COL [1:0] 00 (8 bits) Output Column Address A1 A0 Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 01 (12 bits) A2/3 COL [1:0] 00 (8 bits) Output Column Address A1 A0 Output Pins of Output Row This Address LSI A1 A0 A9 A8 Pins of SDRAM Function Unused Output Pins of Output Row This Address LSI A1 A0 A9 A8 Pins of SDRAM Function Unused Example of memory connection One 64-Mbit product (512 kwords x 32 bits x 4 banks, 8bit column product) Two 16-Mbit products (512 kwords x 16 bits x 2 banks, 8bit column product) Example of memory connection One 128-Mbit product (1 Mword x 32 bits x 4 banks, 8-bit column product) Two 64-Mbit product (1 Mword x 16 bits x 4 banks, 8-bit column product) Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the access mode. 2. Bank address specification 3. Applicable only to a 64-Mbit product Table 7.13 Relationship between Register Settings (A3BSZ[1:0], A3ROW[1:0], and A3COL[1:0]) and Address Multiplex Output (2) Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 01 (12 bits) A2/3 COL [1:0] 01 (9 bits) Output Column Address A17 A16 2 Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 01 (12 bits) A2/3 COL [1:0] 10 (10 bits) Output Column Address A17 A16 2 Output Pins of Output Row This Address LSI A17 A16 A15 A14 A26 A25 A24* A23* Pins of SDRAM Function Unused Output Pins of Output Row This Address LSI A17 A16 A27 A26 A25* A24* Pins of SDRAM Function Unused A24* A23* 2 2 2 A13 (BA1) Specifies bank A12 (BA0) A15 A14 A25* A24* 2 2 2 A13 (BA1) Specifies bank A12 (BA0) Rev. 5.00 Mar. 15, 2007 Page 161 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 01 (12 bits) A2/3 COL [1:0] 01 (9 bits) Output Column Address A13 L/H* 1 Setting A2/3 BSZ [1:0] 11 (32 bits) A2/3 ROW [1:0] 01 (12 bits) A2/3 COL [1:0] 10 (10 bits) Output Column Address A13 L/H* 1 Output Pins of Output Row This Address LSI A13 A12 A22 A21 Pins of SDRAM A11 A10/AP Function Address Specifies address/ precharge Address Output Pins of Output Row This Address LSI A13 A12 A23 A22 Pins of SDRAM A11 A10/AP Function Address Specifies address/ precharge Address A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Unused A1 A0 Unused Example of memory connection One 256-Mbit product (2 Mwords x 32 bits x 4 banks, 9bit column product) Two 128-Mbit products (2 Mwords x 16 bits x 4 banks, 9bit column product) Example of memory connection One 512-Mbit product (4 Mwords x 32 bits x 4 banks, 10bit column product) Two 256-Mbit product (4 Mwords x 16 bits x 4 banks, 10bit column product) Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the access mode. 2. Bank address specification Rev. 5.00 Mar. 15, 2007 Page 162 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Table 7.14 Relationship between Register Settings (A3BSZ[1:0], A3ROW[1:0], and A3COL[1:0]) and Address Multiplex Output (3) Setting A2/3 BSZ [1:0] 11 (32 bits) Output Pins of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A2/3 ROW [1:0] 10 (13 bits) Output Row Address A26 A25* A24* A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 2 A2/3 COL [1:0] 01 (9 bits) Output Column Address A17 A25* A24* A14 A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 Pins of SDRAM Function Unused A14 (BA1) A13 (BA0) A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank 2 2 Address Specifies address/precharge Address Unused Example of memory connection One 512-Mbit product (4 Mwords x 32 bits x 4 banks, 9-bit column product) Two 256-Mbit products (4 Mwords x 16 bits x 4 banks, 9-bit column product) Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the access mode. 2. Bank address specification Rev. 5.00 Mar. 15, 2007 Page 163 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Table 7.15 Relationship between Register Settings (A3BSZ[1:0], A3ROW[1:0], and A3COL[1:0]) and Address Multiplex Output (4) Setting A3 BSZ [1:0] 10 (16 bits) A3 ROW [1:0] 00 (11 bits) A3 COL [1:0] Setting A3 BSZ [1:0] 10 (16 bits) A3 ROW [1:0] 01 (12 bits) A3 COL [1:0] 00 (8 bits) 00 (8 bits) Output Pins of Output This Row Address LSI A17 A16 A15 A14 A13 A12 A25 A24 A23 A22 A21 A20* 2 Output Column Address A17 A16 A15 A14 A21 A20* 2 Pins of SDRAM Function Unused Output Pins of Output This Row Address LSI A17 A16 A15 A14 A13 A25 A24 A23 A22* A21* A20 2 Output Column Address A17 A16 A15 A22* A21* A12 1 2 Pins of SDRAM Function Unused 2 2 A13 (BA1) Specifies bank A12 (BA0) A11 Address A11 (BA0) Specifies bank A10/AP Specifies address/ precharge Address A12 A11 A19 L/H* 1 A11 A19 L/H* A10/AP Specifies address/ precharge Address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Unused A0 Unused Rev. 5.00 Mar. 15, 2007 Page 164 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Setting A3 BSZ [1:0] 10 (16 bits) A3 ROW [1:0] 00 (11 bits) A3 COL [1:0] Setting A3 BSZ [1:0] 10 (16 bits) A3 ROW [1:0] 01 (12 bits) A3 COL [1:0] 00 (8 bits) 00 (8 bits) Output Pins of Output Row This LSI Address Output Column Address Pins of SDRAM Function Output Pins of Output Row This LSI Address Output Column Address Pins of SDRAM Function Example of memory connection One 16-Mbit product (512 kwords x 16 bits x 2 banks, 8bit column product) Example of memory connection One 64-Mbit products (1 Mword x 16 bits x 4 banks, 8-bit column product) Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the access mode. 2. Bank address specification Table 7.16 Relationship between Register Settings (A3BSZ[1:0], A3ROW[1:0], and A3COL[1:0]) and Address Multiplex Output (5) Setting A3 BSZ [1:0] 10 (16 bits) A3 ROW [1:0] 01 (12 bits) A3 COL [1:0] Setting A3 BSZ [1:0] 10 (16 bits) A3 ROW [1:0] 01 (12 bits) A3 COL [1:0] 01 (9 bits) 10 (10 bits) Output Pins of Output This Row Address LSI A17 A16 A15 A14 A13 A12 A26 A25 A24 A23* A22* A21 2 Output Column Address A17 A16 A15 A23* A22* A12 2 Pins of SDRAM Function Unused Output Pins of Output This Row Address LSI A17 A16 A15 A27 A26 A25 A24* A23* A22 2 Output Column Address A17 A16 A15 A24* A23* A12 2 Pins of SDRAM Function Unused 2 2 A13 (BA1) Specifies bank A12 (BA0) A11 Address A14 A13 A12 2 2 A13 (BA1) Specifies bank A12 (BA0) A11 Address Rev. 5.00 Mar. 15, 2007 Page 165 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Setting A3 BSZ [1:0] 10 (16 bits) A3 ROW [1:0] 01 (12 bits) A3 COL [1:0] Setting A3 BSZ [1:0] 10 (16 bits) A3 ROW [1:0] 01 (12 bits) A3 COL [1:0] 01 (9 bits) 10 (10 bits) Output Pins of Output Row This LSI Address A11 A20 Output Column Address L/H* 1 Pins of SDRAM A10/AP Function Specifies address/ precharge Address Output Pins of Output Row This LSI Address A11 A21 Output Column Address L/H* 1 Pins of SDRAM A10/AP Function Specifies address/ precharge Address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Unused A0 Unused Example of memory connection One 128-Mbit product (2 Mwords x 16 bits x 4 banks, 9bit column product) Example of memory connection One 256-Mbit product (4 Mwords x 16 bits x 4 banks, 10bit column product) Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the access mode. 2. Bank address specification Rev. 5.00 Mar. 15, 2007 Page 166 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Table 7.17 Relationship between Register Settings (A3BSZ[1:0], A3ROW[1:0], and A3COL[1:0]) and Address Multiplex Output (6) Setting A3 BSZ [1:0] 10 (16 bits) A3 ROW [1:0] 10 (13 bits) A3 COL [1:0] Setting A3 BSZ [1:0] 10 (16 bits) A3 ROW [1:0] 10 (13 bits) A3 COL [1:0] 01 (9 bits) 10 (10 bits) Output Pins of Output This Row Address LSI A17 A16 A15 A14 A13 A12 A11 A26 A25 A24* A23* A22 A21 A20 2 Output Column Address A17 A16 A24* A23* A13 A12 L/H* 1 2 Pins of SDRAM Function Unused Output Pins of Output This Row Address LSI A17 A16 A27 A26 A25* A24* A23 A22 A21 2 Output Column Address A17 A16 A25* A24* A13 A12 L/H* 1 2 Pins of SDRAM Function Unused 2 2 A14 (BA1) Specifies bank A13 (BA0) A12 A11 A10/AP Specifies address/ precharge Address Address A15 A14 A13 A12 A11 2 2 A14 (BA1) Specifies bank A13 (BA0) A12 A11 A10/AP Specifies address/ precharge Address Address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Unused A0 Unused Rev. 5.00 Mar. 15, 2007 Page 167 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Setting A3 BSZ [1:0] 10 (16 bits) A3 ROW [1:0] 10 (13 bits) A3 COL [1:0] Setting A3 BSZ [1:0] 10 (16 bits) A3 ROW [1:0] 10 (13 bits) A3 COL [1:0] 01 (9 bits) 10 (10 bits) Output Pins of Output Row This LSI Address Output Column Address Pins of SDRAM Function Output Pins of Output Row This LSI Address Output Column Address Pins of SDRAM Function Example of memory connection One 256-Mbit product (4 Mwords x 16 bits x 4 banks, 9bit column product) Example of memory connection One 512-Mbit product (8 Mwords x 16 bits x 4 banks, 10bit column product) Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the access mode. 2. Bank address specification Burst Read: A burst read occurs in the following cases with this LSI. 1. Access size in reading is larger than data bus width. 2. 16-byte transfer in cache miss. 3. 16-byte transfer by DMAC and E-DMAC (access to non-cacheable area) This LSI always accesses the SDRAM with burst length 1. For example, read access of burst length 1 is performed consecutively four times to read 16-byte consecutive data from the SDRAM that is connected to a 32-bit data bus. The number of bursts in this access is four. Rev. 5.00 Mar. 15, 2007 Page 168 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Table 7.18 shows the relationship between the access size and the number of bursts. Table 7.18 Relationship between Access Size and Number of Bursts Bus Width 16 bits Access Size 8 bits 16 bits 32 bits 16 bytes 32 bits 8 bits 16 bits 32 bits 16 bytes Number of Bursts 1 1 2 8 1 1 1 4 Figures 7.14 and 7.15 show timing charts in burst read. In burst read, the ACTV command is output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA command is issued in the Tc4 cycle, and the read data is latched at the rising edge of the external clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an auto-precharge induced by the READ command in the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, other banks can be accessed. The number of Tap cycles is specified by bits WTRP1 and WTRP0 in CS3WCR. In this LSI, wait cycles can be inserted by specifying bits in CSnWCR to connect the SDRAM with variable frequencies. Figure 7.15 shows an example in which wait cycles are inserted. The number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where the READA command is output can be specified using bits WTRCD1 and WTRCD0 in CS3WCR. When bits WTRCD1 and WTRCD0 is set to one cycle or more, a Trw cycle where the NOP command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the Tc1 cycle where the READA command is output to the Td1 cycle where the read data is latched can be specified by bits A3CL1 and A3CL0 bits in CS3WCR in CS3WCR. This number of cycles corresponds to the synchronous DRAM CAS latency. The CAS latency for the synchronous DRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can be specified as one to four cycles. This CAS latency can be achieved by connecting a latch circuit between this LSI and the synchronous DRAM. Rev. 5.00 Mar. 15, 2007 Page 169 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Tr CKIO A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde Tap Note: * Address pin to be connected to pin A10 of SDRAM. Figure 7.14 Burst Read Basic Timing (Auto Precharge) Rev. 5.00 Mar. 15, 2007 Page 170 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Tr CKIO A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Trw Tc1 Tw Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde Tap Note: * Address pin to be connected to pin A10 of SDRAM. Figure 7.15 Burst Read Wait Specification Timing (Auto Precharge) Rev. 5.00 Mar. 15, 2007 Page 171 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Single Read: A read access ends in one cycle when data exists in non-cacheable area and the data bus width is larger than or equal to access size. Since the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. Figure 7.16 shows the single read basic timing. Tr CKIO A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Note: * Address pin to be connected to pin A10 of SDRAM. Tc1 Td1 Tde Tap Figure 7.16 Basic Timing for Single Read (Auto Precharge) Burst Write: A burst write occurs in the following cases in this LSI. 1. Access size in writing is larger than data bus width. 2. Write-back of the cache 3. 16-byte transfer by DMAC and E-DMAC (access to non-cacheable area) This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1 is performed consecutively four times to write 16-byte consecutive data to the SDRAM that is connected to a 32-bit data bus. The relationship between the access size and the number of bursts is shown in table 7.18. Rev. 5.00 Mar. 15, 2007 Page 172 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Figure 7.17 shows a timing chart for burst writes. In burst write, the ACTV command is output in the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data is output simultaneously with the write command. After the write command with the autoprecharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, other CS areas and other banks can be accessed. The number of Trw1 cycles is specified by bits TRWL1 and TRWL0 in CS3WCR. The number of Tap cycles is specified by bits WTRP1 and WTRP0 in CS3WCR. Tr CKIO A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Tc1 Tc2 Tc3 Tc4 Trwl Tap Note: * Address pin to be connected to pin A10 of SDRAM. Figure 7.17 Basic Timing for Burst Write (Auto Precharge) Rev. 5.00 Mar. 15, 2007 Page 173 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Single Write: A write access ends in one cycle when data is written in non-cacheable area and the data bus width is larger than or equal to access size. Figure 7.18 shows the single write basic timing. Tr CKIO A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Tc1 Trwl Tap Note: * Address pin to be connected to pin A10 of SDRAM. Figure 7.18 Basic Timing for Single Write (Auto-Precharge) Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the BACTV bit in SDCR is 1, accesses are performed using commands without auto-precharge (READ or WRIT). This function is called bank-active function. When a bank-active function is used, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command. Since synchronous DRAM is internally divided into several banks, it is possible to keep one row address in each bank activated. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. The number of cycles between issuance of the PRE command and the ACTV command is determined by bits WTRP1 and WTRP0 in CSnWCR. Rev. 5.00 Mar. 15, 2007 Page 174 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) In a write access, when an auto-precharge is performed, a command cannot be issued to the same bank for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode is used, READ or WRIT command can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tap cycles for each write. There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee that another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refreshing and set the refresh cycle to no more than the maximum value of tRAS. A burst read cycle without auto-precharge is shown in figure 7.19, a burst read cycle for the same row address in figure 7.20, and a burst read cycle for different row addresses in figure 7.21. Likewise, a single write cycle without auto-precharge is shown in figure 7.22, a single write cycle for the same row address in figure 7.23, and a single write cycle for different row addresses in figure 7.24. In figure 7.20, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that issues the READ command. The Tnop cycle is inserted to secure two cycles of CAS latency for the DQMxx signal that specifies which byte data is read from SDRAM. If the CAS latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of latency can be secured even if the DQMxx signal is asserted after the Tc cycle. When bank active mode is set, if only accesses to the respective banks in the area 3 are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 7.19 or 7.22, followed by repetition of the cycle in figure 7.20 or 7.23. An access to a different area during this time has no effect. When a different row address is accessed in the bank active state, the bus cycle shown in figure 7.21 or 7.24 is executed instead of that in figure 7.20 or 7.23. In bank active mode, too, all banks become inactive after a refresh cycle. Rev. 5.00 Mar. 15, 2007 Page 175 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Tr CKIO A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde Note: * Address pin to be connected to pin A10 of SDRAM. Figure 7.19 Burst Read Timing (No Auto Precharge) Rev. 5.00 Mar. 15, 2007 Page 176 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Tnop CKIO A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde Note: * Address pin to be connected to pin A10 of SDRAM. Figure 7.20 Burst Read Timing (Bank Active, Same Row Address) Rev. 5.00 Mar. 15, 2007 Page 177 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Tp CKIO A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Tpw Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde Note: * Address pin to be connected to pin A10 of SDRAM. Figure 7.21 Burst Read Timing (Bank Active, Different Row Addresses) Rev. 5.00 Mar. 15, 2007 Page 178 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Tr CKIO A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Tc1 Note: * Address pin to be connected to pin A10 of SDRAM. Figure 7.22 Single Write Timing (No Auto Precharge) Rev. 5.00 Mar. 15, 2007 Page 179 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Tnop CKIO A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Tc1 Note: * Address pin to be connected to pin A10 of SDRAM. Figure 7.23 Single Write Timing (Bank Active, Same Row Address) Rev. 5.00 Mar. 15, 2007 Page 180 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Tp CKIO A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Tpw Tr Tc1 Note: * Address pin to be connected to pin A10 of SDRAM. Figure 7.24 Single Write Timing (Bank Active, Different Row Addresses) Refreshing: This LSI has a function for controlling synchronous DRAM refreshing. Autorefreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A consecutive refreshing can be performed by setting bits RRC2 to RRC0 in RTCSR. If synchronous DRAM is not accessed for a long period, self-refreshing mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. 1. Auto-refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0 in RTCSR, and the value set by in RTCOR. The value of bits CKS[2:0] in RTCOR should be set so as to satisfy the given refresh interval for the synchronous DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE, then make the CKS[2:0] and RRC[2:0] settings. When the clock is selected by bits CKS[2:0], RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto-refreshing is performed for the number of times specified by the RRC[2:0]. At the same time, RTCNT is cleared to 0 and the count-up is restarted. Rev. 5.00 Mar. 15, 2007 Page 181 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Figure 7.25 shows the auto-refreshing cycle timing. After starting the auto-refreshing, PALL command is issued in the Tp cycle to make all the banks to precharged state from active state when some bank is being precharged. Then the REF command is issued in the Trr cycle after inserting idle cycles of which number is specified by bits WTRP1 and WTRP0 in CSnWCR. A new command is not issued for the duration of the number of cycles specified by bits WTRC1 and WTRC0 in CSnWCR after the Trr cycle. Bits WTRC1 and WTRC0 in CSnWCR must be set so as to satisfy the SDRAM refreshing cycle time (tRC). A Tpw cycle is inserted between the Tp cycle and Trr cycle when the setting of bits WTRP1 and WTRP0 in CSnWCR is longer than or equal to two cycles. Tp CKIO A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Hi-z Tpw Trr Trc Trc Trc Note: * Address pin to be connected to pin A10 of SDRAM. Figure 7.25 Auto-Refreshing Timing Rev. 5.00 Mar. 15, 2007 Page 182 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) 2. Self-refreshing When self-refreshing mode is selected, the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR to 1. After starting the self-refreshing, the PALL command is issued in the Tp cycle after the completion of pre-charging the bank. The SELF command is then issued after inserting idle cycles of which the number is specified by bits WTRP1 and WTRP0 in CSnWSR. Synchronous DRAM cannot be accessed while self-refreshing. Selfrefreshing mode is cleared by clearing the RMODE bit to 0. After self-refreshing mode has been cleared, command issuance is disabled for the number of cycles specified by bits WTRC1 and WTRC0 in CSnWCR. Self-refreshing timing is shown in figure 7.26. Settings must be made immediately after clearing self-refreshing mode so that auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the auto-refreshing mode, only clearing the RMODE bit to 1 resumes auto-refreshing mode. If it takes long time to start the auto-refreshing, setting RTCNT to the value of RTCOR − 1 starts the auto-refreshing immediately. After self-refreshing has been set, the self-refreshing mode continues even in standby mode, and is maintained even after recovery from standby mode by an interrupt. Since the BSC registers are initialized at a power-on reset, the self-refreshing mode is cleared. Rev. 5.00 Mar. 15, 2007 Page 183 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Tp CKIO CKE A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Tpw Trr Trc Trc Trc Trc Trc Hi-z Note: * Address pin to be connected to pin A10 of SDRAM. Figure 7.26 Self-Refreshing Timing Relationship between Refresh Requests and Bus Cycles: If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a new refresh request occurs while the previous refresh request is not performed, the previous refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus busy must be prevented. Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after turning the power on. To perform synchronous DRAM initialization correctly, the BSC registers must first be set, followed by writing to the synchronous DRAM mode register. When writing to the synchronous DRAM mode register, the address signal value at that time is latched by a combination of the CSn, RAS, CAS, and RD/WR signals. If the value to be set is X, write to the address of H'F8FD5000 + X in words. In this operation, the data is ignored. To set burst read/single write, burst read/burst write, CAS latency 2 to 3, wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is written to the addresses shown in table 7.19 in bytes. In this case, 0s are output at the external address pins of A12 or later. Rev. 5.00 Mar. 15, 2007 Page 184 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Table 7.19 Access Address for SDRAM Mode Register Write • Burst read/single write (burst length 1) Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address H'F8FD5440 H'F8FD5460 H'F8FD50880 H'F8FD58C0 External Address Pin H'0000440 H'0000460 H'0000880 H'00008C0 • Burst read/burst write (burst length 1) Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address H'F8FD5040 H'F8FD5060 H'F8FD5080 H'F8FD50C0 External Address Pin H'0000040 H'0000060 H'0000080 H'00000C0 Mode register setting timing is shown in figure 7.27. The PALL command (all bank precharge command) is firstly issued. The REF command (auto-refreshing command) is then issued eight times. The MRS command (mode register write command) is finally issued. Idle cycles, of which number is specified by bits WTRP1 and WTRP0 in CSnWCR, are inserted between the PALL and the first REF commands. Idle cycles, of which number is specified by bits WTRC1 and WTRC0 in CSnWCR, are inserted between the REF and REF commands, and between the 8th REF and MRS commands. In addition, one or more idle cycles are inserted between the MRS and the next command. It is necessary to keep idle time of certain cycles for SDRAM before issuing the PALL command after turning the power on. Refer the manual of the SDRAM for the idle time to be needed. When the pulse width of the reset signal is longer then the idle time, mode register setting can be started immediately after the reset, but care should be taken when the pulse width of the reset signal is shorter than the idle time. Rev. 5.00 Mar. 15, 2007 Page 185 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Tp PALL CKIO Tpw Trr REF Trc Trc Trr REF Trc Trc Tmw MRS Tnop A25 to A0 A11* CSn RAS CAS RD/WR DQMxx D BS Note: * Address pin to be connected to pin A10 of SDRAM. Hi-Z Figure 7.27 Write Timing for SDRAM Mode Register (Based on JEDEC) 7.5.6 Byte-Selection SRAM Interface The byte-selection SRAM interface is for access to SRAM which has a byte-selection pin (WEn (BEn)). This interface is used to access to SRAM which has 16-bit data pins and upper and lower byte selection pins, such as UB and LB. When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the byteselection SRAM interface is the same as that for the normal space interface. While in read access of a byte-selection SRAM interface, the byte-selection signal is output from the WEn (BEn) pin, which is different from that for the normal space interface. The basic access timing is shown in figure 7.28. In write access, data is written to the memory according to the timing of the byteselection pin (WEn (BEn)). For details, refer to the data sheet for the corresponding memory. If the BAS bit in CSnWCR is set to 1, the WEn (BEn) pin and RD/WR pin timings change. The basic access timing is shown in figure 7.29. In write access, data is written to the memory according to the timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write must be secured by setting bits HW1 to HW0 in CSnWCR. Figure 7.30 shows the access timing when a software wait is specified. Rev. 5.00 Mar. 15, 2007 Page 186 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) T1 T2 CKIO A25 to A0 CSn WEn(BEn) RD/WR RD Read D RD/WR High Write RD D BS Figure 7.28 Basic Access Timing for Byte-Selection SRAM (BAS = 0) Rev. 5.00 Mar. 15, 2007 Page 187 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) T1 CKIO T2 A25 to A0 CSn WEn(BEn) RD/WR Read RD D RD/WR Write High RD D BS Figure 7.29 Basic Access Timing for Byte-Selection SRAM (BAS = 1) Rev. 5.00 Mar. 15, 2007 Page 188 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Th T1 Tw T2 Th CKIO A25 to A0 CSn WEn(BEn) RD/WR Read RD D RD/WR RD High Write D BS Figure 7.30 Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only) Rev. 5.00 Mar. 15, 2007 Page 189 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) This LSI A17 64 kwords x 16 bits SRAM A15 .... A2 CSn RD RD/WR D31 D16 WE3(BE3) WE2(BE2) D15 .... .... D0 WE1(BE1) WE0(BE0) Figure 7.31 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM 64 kwords x 16 bits SRAM This LSI ... A1 CSn RD RD/WR D15 ... D0 WE1(BE1) WE0(BE0) Figure 7.32 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM Rev. 5.00 Mar. 15, 2007 Page 190 of 794 REJ09B0237-0500 ... ... A16 A16 A1 CS OE WE I/O 15 I/O 0 UB LB .... I/O0 UB LB .... A0 CS OE WE I/O15 .... I/O0 UB LB A15 .... A0 CS OE WE I/O15 Section 7 Bus State Controller (BSC) 7.5.7 PCMCIA Interface With this LSI, if address map 2 is selected using the MAP bit in CMNCR, the PCMCIA interface can be specified in areas 5 and 6. Areas 5 and 6 in the physical space can be used for the IC memory card and I/O card interface defined in the JEIDA specifications version 4.2 (PCMCIA2.1 Rev. 2.1) by specifying bits TYPE3 to TYPE0 in CSnBCR (n = 5B and 6B) to B'0101. In addition, bits SA1 and SA0 in CSnWCR (n = 5B and 6B) assign the upper or lower 32 Mbytes of each area to an IC memory card or I/O card interface. For example, if bits SA1 and SA0 in CS5BWCR are set to 1 and cleared to 0, respectively, the upper 32 Mbytes and the lower 32 Mbytes of area 5B are used as an IC memory card interface and I/O card interface, respectively. When the PCMCIA interface is used, the bus size must be specified as 8 bits or 16 bits using bits BSZ1 and BSZ0 in CS5BBCR or CS6BBCR. Figure 7.33 shows an example of a connection between this LSI and the PCMCIA card. To enable insertion and removal of the PCMCIA card with the system power turned on, tri-state buffers must be connected between the LSI and the PCMCIA card. In the JEIDA and PCMCIA standards, operation in big endian mode is not clearly defined. Consequently, the provided PCMCIA interface in big endian mode is available only for this LSI. Rev. 5.00 Mar. 15, 2007 Page 191 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) This LSI A25 to A0 D7 to D0 D15 to D8 RD/WR CE1A CE2A G DIR G PC card (memory or I/O) A25 to A0 D7 to D0 D15 to D8 G DIR CE1 CE2 RD WE ICIORD ICIOWR I/O Port G OE WE/PGM IORD IOWR REG WAIT IOIS16 Card detection circuit WAIT IOIS16 CD1, CD2 Figure 7.33 Example of PCMCIA Interface Connection Rev. 5.00 Mar. 15, 2007 Page 192 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Basic Timing for Memory Card Interface: Figure 7.34 shows the basic timing of the PCMCIA IC memory card interface. If areas 5 and 6 in the physical space are specified as the PCMCIA interface, accessing the common memory areas in areas 5 and 6 automatically accesses with the IC memory card interface. If the external bus frequency (CKIO) increases, the setup times and hold times for the address pins (A25 to A0), card enable signals (CE1A, CE2A, CE1B, CE2B), and write data (D15 to D0) to the RD and WE signals become insufficient. To prevent this error, this LSI can specify the setup times and hold times for areas 5 and 6 in the physical space independently, using CS5BWCR and CS6BWCR. In the PCMCIA interface, as in the normal space interface, a software wait or hardware wait can be inserted using the WAIT pin. Figure 7.35 shows the PCMCIA memory bus wait timing. Tpcm1 CKIO Tpcm1w Tpcm1w Tpcm1w Tpcm2 A25 to A0 CExx RD/WR RD Read D WE Write D BS Figure 7.34 Basic Access Timing for PCMCIA Memory Card Interface Rev. 5.00 Mar. 15, 2007 Page 193 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Tpcm0 CKIO A25 to A0 CExx RD/WR RD Read D WE Write D BS WAIT Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm2w Figure 7.35 Wait Timing for PCMCIA Memory Card Interface (TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1) When 32 Mbytes of the memory space are used as an IC memory card interface, a port is used to generate the REG signal that switches between the common memory and attribute memory. When the memory space used for the IC memory card interface is 16 Mbytes or less, pin A24 can be used as the REG signal by allocating 16-Mbyte memory space to each the common memory space and the attribute memory space. Rev. 5.00 Mar. 15, 2007 Page 194 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) PCMCIA interface area is 32 Mbytes (An I/O port pin is used as the REG) Area 5 : H'14000000 Attribute memory/common memory Area 5 : H'16000000 I/O space Area 6 : H'18000000 Attribute memory/common memory Area 6 : H'1A000000 I/O space PCMCIA interface area is 16 Mbytes (A24 is used as the REG) Area 5 : H'14000000 Area 5 : H'15000000 Area 5 : H'16000000 H'17000000 Area 6 : H'18000000 Area 6 : H'19000000 Area 6 : H'1A000000 H'1B000000 Attribute memory Common memory I/O space Attribute memory Common memory I/O space Figure 7.36 Example of PCMCIA Space Assignment (CS5BWCR.SA[1:0] = B'10, CS6BWCR.SA[1:0] = B'10) Basic Timing for I/O Card Interface: Figures 7.37 and 7.38 show the basic timings for the PCMCIA I/O card interface. The I/O card and IC memory card interfaces are specified by an address to be accessed. When area 5 of the physical space is specified as the PCMCIA and both bits SA1 and SA0 in CS5BWCR are set to 1, the I/O card interface can automatically be specified by accessing the physical addresses from H'16000000 to H'17FFFFFF and from H'14000000 to H'15FFFFFF. When area 6 of the physical space is specified as the PCMCIA and both bits SA1 and SA0 in CS6BWCR are set to 1, the I/O card interface can automatically be specified by accessing the physical addresses from H'1A000000 to H'1BFFFFFF and from H'18000000 to H'19FFFFFF. Note that areas to be accessed as the PCMCIA I/O card must be non-cached (space P2). If the PCMCIA card is accessed as an I/O card in little endian mode, dynamic bus sizing for the I/O bus can be achieved using the IOIS16 signal. If the IOIS16 signal is driven high in a word-size I/O bus cycle while the bus width of area 6 is specified as 16 bits, the bus width is recognized as 8 bits and data is accessed twice in units of eight bits in the I/O bus cycle to be executed. Rev. 5.00 Mar. 15, 2007 Page 195 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) The IOIS16 signal is sampled at the falling edge of the CKIO signal in the Tpci0, Tpci0w, and Tpci1 cycles when bits TED3 to TED0 are specified as 1.5 cycles or more, and is reflected in the CE2 signal 1.5 cycles after the CKIO sampling point. Bits TED3 to TED0 must be specified appropriately to satisfy the setup time of the PC card from ICIORD and ICIOWR to CEn. Figure 7.39 shows the dynamic bus sizing basic timing. Note that the IOIS16 signal is not supported in big endian mode. In the big endian mode, the IOIS16 signal must be fixed low. Tpci1 Tpci1w Tpci1w Tpci1w Tpci2 CKIO A25 to A0 CExx RD/WR ICIORD Read D ICIOWR Write D BS Figure 7.37 Basic Timing for PCMCIA I/O Card Interface Rev. 5.00 Mar. 15, 2007 Page 196 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Tpci0 CKIO A25 to A0 CExx RD/WR ICIORD Read D ICIOWR Write D BS WAIT IOIS16 Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w Figure 7.38 Wait Timing for PCMCIA I/O Card Interface (TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1) Tpci0 CKIO A25 to A0 CE1x CE2x RD/WR ICIORD Read D ICIOWR Write D BS WAIT IOIS16 Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w Figure 7.39 Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface (TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Waits = 3) Rev. 5.00 Mar. 15, 2007 Page 197 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) 7.5.8 Wait between Access Cycles Data output in the previous cycle may conflict with that in the next cycle because the buffer-off timing of devices with slow access speed cannot be operated to satisfy the higher operating frequency of LSIs. As a result of these conflict, the reliability of the device is low and malfunctions may occur. This LSI has a function that avoids data conflicts by inserting wait cycles between consecutive access cycles. The number of wait cycles between access cycles can be set by bits IWW1 and IWW0, bits IWRWD1 and IWRWD0, bits IWRWS1 and IWRWS0, bits IWRRD1 and IWRRD0, and bits IWRRS1 and IWRRS0 in CSnBCR. The conditions for setting the wait cycles between access cycles (idle cycles) are shown below. 1. 2. 3. 4. 5. Consecutive accesses are write-read or write-write Consecutive accesses are read-write for different areas Consecutive accesses are read-write for the same area Consecutive accesses are read-read for different areas Consecutive accesses are read-read for the same area Others 7.5.9 Reset: The bus state controller (BSC) can be initialized completely only by a power-on reset. At power-on reset, all signals are negated and output buffers are turned off regardless of the bus cycle state. All control registers are initialized. In standby mode and sleep mode, control registers of the BSC are not initialized. Some flash memories may stipulate a minimum time from reset release to the first access. To ensure this minimum time, the BSC supports a 7-bit counter (RWTCNT). At a power-on reset, the RWTCNT contents are cleared to 0. After a power-on reset, RWTCNT is counted up in synchronization with the CKIO signal and an external access will not be generated until RWTCNT is counted up to H'007F. Access from the Site of the LSI Internal Bus Master: There are three types of LSI internal buses: a cache bus, internal bus, and peripheral bus. The CPU and cache memory are connected to the cache bus. Internal bus masters other than the CPU and BSC are connected to the internal bus. Low-speed peripheral modules are connected to the peripheral bus. Internal memory other than the cache memory and debugging modules such as the UBC are connected to both the cache bus and internal bus. Access from the cache bus to the internal bus is enabled but access from the internal bus to the cache bus is disabled. This gives rise to the following problems. Rev. 5.00 Mar. 15, 2007 Page 198 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) Internal bus masters other than the CPU such as the DMAC and E-DMAC can access on-chip memory other than the cache memory but cannot access the cache memory. If an on-chip bus master other than the CPU writes data to an external memory other than the cache, the contents of the external memory may differ from that of the cache memory. To prevent this problem, if the external memory whose contents is cached is written by an on-chip bus master other than the CPU, the corresponding cache memory should be purged by software. If the CPU initiates read access for the cache, the cache is searched. If the cache stores data, the CPU latches the data and completes the read access. If the cache does not store data, the CPU performs four consecutive longword read cycles to perform cache fill operations via the internal bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary (4n + 2), the CPU performs four consecutive longword accesses to perform a cache fill operation on the external interface. For a cache-through area, the CPU performs access according to the actual access addresses. For an instruction fetch to an even word boundary (4n), the CPU performs longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU performs word access. For a read cycle of a cache-through area or an on-chip peripheral module, the read cycle is first accepted and then read cycle is initiated. The read data is sent to the CPU via the cache bus. In a write cycle for the cache area, the write cycle operation differs according to the cache write methods. In write-back mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is then re-written to the cache. In the actual memory, data will not be re-written until data in the corresponding address is re-written. If data is not detected at the address corresponding to the cache, the cache is updated. In this case, data to be updated is first saved to the internal buffer, 16-byte data including the data corresponding to the address is then read, and data in the corresponding access of the cache is finally updated. Following these operations, a write-back cycle for the saved 16-byte data is executed. In write-through mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is re-written to the cache simultaneously with the actual write via the internal bus. If data is not detected at the address corresponding to the cache, the cache is not updated but an actual write is performed via the internal bus. Since the BSC incorporates a 1-stage write buffer, the BSC can execute an access via the internal bus before the previous external bus cycle is completed in a write cycle. If the on-chip module is read or written after the external low-speed memory is written, the on-chip module can be accessed before the completion of the external low-speed memory write cycle. Rev. 5.00 Mar. 15, 2007 Page 199 of 794 REJ09B0237-0500 Section 7 Bus State Controller (BSC) In read cycles, the CPU is placed in the wait cycle until read operation has been completed. To continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed. The write buffer of the BSC functions in the same way for an access by a bus master other than the CPU such as the DMAC or E-DMAC. Accordingly, to perform dual address DMA transfers, the next read cycle is initiated before the previous write cycle is completed. Note, however, that if both the DMA source and destination addresses exist in external memory space, the next write cycle will not be initiated until the previous write cycle is completed. On-Chip Peripheral Module Access: To access an on-chip module register, two or more peripheral module clock (Pφ) cycles are required. Care must be taken in system design. Rev. 5.00 Mar. 15, 2007 Page 200 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) Section 8 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock (Pφ), a bus clock (Bφ), and a clock (Mφ) for the on-chip IEEE802.3-PHY (physical layer device, hereinafter called PHY). The CPG consists of an oscillator, PLL circuits, and divider circuits. 8.1 Features • Four clock modes Selection of four clock modes depending on the frequency of a clock source and whether a crystal resonator or external clock input is in use. • Four clocks generated independently An internal clock (Iφ) for the CPU and cache; a peripheral clock (Pφ) for the on-chip peripheral modules; a bus clock (Bφ = CKIO) for the external bus interface; and a clock (Mφ) for the on-chip PHY. • Frequency change function Frequencies of the internal clock, peripheral clock, and clock for the PHY can be changed independently using the PLL circuit and divider circuit within the CPG. Frequencies are changed by software using the frequency control register (FRQCR) and PHY clock frequency control register (MCLKCR) settings. • Power-down mode control The clock can be stopped in sleep mode and software standby mode and specific modules can be stopped using the module standby function. Rev. 5.00 Mar. 15, 2007 Page 201 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) A block diagram of the CPG is shown in figure 8.1. Oscillator unit Divider 2 ×1 ×1/2 ×1/4 ×1/5 Divider 1 ×1 PLL circuit 1 (×1, ×2) CKIO XTAL EXTAL Crystal oscillator Bus clock (Bφ = CKIO) ×1/2 ×1/4 Internal clock (Iφ) PHY clock (Mφ) PLL circuit 2 (×2, ×4) Peripheral clock (Pφ) CPG control unit MD2 MD1 MD0 FRQCR Clock frequency control circuit Standby control circuit MCLKCR STBCR STBCR2 STBCR3 STBCR4 Bus interface [Legend] FRQCR: STBCR: STBCR2: STBCR3: STBCR4: MCLKCR: Internal bus Frequency control register Standby control register Standby control register 2 Standby control register 3 Standby control register 4 PHY clock frequency control register Figure 8.1 Block Diagram of CPG Rev. 5.00 Mar. 15, 2007 Page 202 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) The clock pulse generator blocks function as follows: PLL Circuit 1: PLL circuit 1 leaves the input clock frequency from the PLL circuit 2 unchanged or doubles it. The multiplication ratio is set by the frequency control register. The phase of the rising edge of the internal clock is controlled so that it will match the phase of the rising edge of the CKIO pin. PLL Circuit 2: PLL circuit 2 doubles or quadruples the clock frequency input from the crystal oscillator or the EXTAL pin. The multiplication ratio is fixed for each clock operating mode. The clock operating mode is set with pins MD0, MD1, or MD2. Crystal Oscillator: The crystal oscillator is an oscillator circuit when a crystal resonator is connected to the XTAL and EXTAL pins. The crystal oscillator can be used by setting the clock operating mode. Divider 1: Divider 1 generates clocks with the frequencies used by the internal clock, peripheral clock, and bus clock. The frequency output as the internal clock is always the same as that of the devider1 output. The frequency output as the bus clock is automatically selected so that it is the same as the frequency of the CKIO signal according to the multiplication ratio of PLL circuit 1. The frequencies can be 1, 1/2, or 1/4 times the output frequency of PLL circuit 1, as long as it stays at or above the frequency of the CKIO pin. The division ratio is set in the frequency control register. Divider 2: Divider 2 generates a clock that is supplied to the on-chip PHY. Divider 2 must output 25-MHz frequency for the on-chip PHY that requires 25-MHz clock. The output clock of divider 2 can be 1, 1/2, 1/4, or 1/5 times the output frequency of PLL circuit 1. The division ratio is set in the PHY clock frequency control register. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency using pins MD0, MD1, and MD2, the frequency control register, and PHY clock frequency control register. Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillator circuit and other modules during clock switching and in software standby mode. Frequency Control Register: The frequency control register has control bits assigned for the following functions: clock output/non-output from the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the peripheral clock. Standby Control Register: The standby control register has bits for controlling the power-down modes. For details, see section 10, Power-Down Modes. Rev. 5.00 Mar. 15, 2007 Page 203 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) PHY Clock Frequency Control Register: The PHY clock frequency control register sets the frequency division ratio of the PHY clock. 8.2 Input/Output Pins Table 8.1 shows the CPG pin configuration. Table 8.1 Pin Name Pin Configuration Abbr. I/O Input Input Input Output Input Output Description Set the clock operating mode. Set the clock operating mode. Set the clock operating mode. Connects a crystal resonator. Connects a crystal resonator or an external clock. Outputs an external clock. Mode control pins* MD0 MD1 MD2 Clock input pins XTAL EXTAL Clock output pin Note: * CKIO The values of these mode control pins are sampled only at a power-on reset or in a software standby with the MDCHG bit in STBCR to 1. This can prevent the erroneous operation of this LSI. 8.3 Clock Operating Modes Table 8.2 shows the relationship between the mode control pins (MD2 to MD0) combinations and the clock operating modes. Table 8.3 shows the usable frequency ranges in the clock operating modes and the frequency range of the input clock. Table 8.2 Mode Control Pins and Clock Operating Modes Clock I/O Source EXTAL Crystal resonator EXTAL Crystal resonator Output CKIO CKIO CKIO CKIO PLL2 ON (×4) ON (×4) ON (×2) ON (×2) PLL1 CKIO Frequency Clock Pin Values Operating Mode MD2 MD1 MD0 1 2 5 6 0 0 1 1 0 1 0 1 1 0 1 0 ON (×1, ×2) (EXTAL) × 4 ON (×1, ×2) (Crystal resonator) × 4 ON (×1, ×2) (EXTAL) × 2 ON (×1, ×2) (Crystal resonator) × 2 Rev. 5.00 Mar. 15, 2007 Page 204 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) Mode 1: The frequency of the external clock input from the EXTAL pin is quadrupled by PLL circuit 2, and then the clock is supplied to this LSI. Since the input clock frequency ranging 10 MHz to 15.625 MHz can be used, the CKIO frequency ranges from 40 MHz to 62.5 MHz. Mode 2: The frequency of the on-chip crystal oscillator output is quadrupled by PLL circuit 2, and then the clock is supplied to this LSI. Since the crystal resonator frequency ranging 10 MHz to 15.625 MHz can be used, the CKIO frequency ranges from 40 MHz to 62.5 MHz. Mode 5: The frequency of the external clock from the EXTAL pin is doubled by PLL circuit 2, and then the clock is supplied to this LSI. Since the input clock frequency ranging 10 MHz to 25 MHz, the CKIO frequency ranges from 20 MHz to 50 MHz. Mode 6: The frequency of the on-chip crystal oscillator output is doubled by PLL circuit 2, and then the clock is supplied to the LSI. Since the crystal oscillation frequency ranging 10 MHz to 25 MHz can be used, the CKIO frequency ranges from 20 MHz to 50 MHz. Table 8.3 Possible Combination of Clock Modes and FRQCR Values Input Clock Frequency Range (Pφ must be equal CKIO Pin to or lower than Frequency 31.25 MHz) Range 10 MHz to 15.625 MHz 40 MHz to 62.5 MHz Mode 1 or 2 FRQCR Register Value H'1000 H'1001 H'1003 H'1101 H'1103 PLL Circuit 1 ON (×1) ON (×1) ON (×1) ON (×2) ON (×2) ON (×1) ON (×1) ON (×1) ON (×2) ON (×2) PLL Circuit 2 ON (×4) ON (×4) ON (×4) ON (×4) ON (×4) ON (×2) ON (×2) ON (×2) ON (×2) ON (×2) Clock Ratio* (I:B:P) 4:4:4 4:4:2 4:4:1 8:4:4 8:4:2 2:2:2 2:2:1 2:2:1/2 4:2:2 4:2:1 5 or 6 H'1000 H'1001 H'1003 H'1101 H'1103 10 MHz to 25 MHz 20 MHz to 50 MHz Note: * Input clock is assumed to be 1. Rev. 5.00 Mar. 15, 2007 Page 205 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) Cautions: 1. The internal clock frequency is the product of the frequency of the CKIO pin and the frequency multiplication ratio of PLL circuit 1. 2. The peripheral clock frequency is the product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1. Do not set the peripheral clock frequency lower than the CKIO pin frequency. 3. The PHY clock frequency is the product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 2. 4. ×1, ×1/2, or ×1/4 can be used as the division ratio of divider 1. This is set by the frequency control register. 5. The division ratio of divider 2 is selected from ×1, ×1/2, ×1/4, or ×1/5. This is set by the PHY clock frequency control register. 6. The output frequency of PLL circuit 1 is the product of the frequency of the CKIO pin and the multiplication ratio of PLL circuit 1. It is set by the frequency control register. 7. The bus clock frequency is always set to be equal to the frequency of the CKIO pin. 8. The clock mode, the FRQCR register value, and the frequency of the input clock should be decided to satisfy the range of operating frequency specified in section 25, Electrical Characteristics, with referring to table 8.3. 8.4 Register Descriptions The CPG has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 24, List of Registers. • Frequency control register (FRQCR) • PHY clock frequency control register (MCLKCR) 8.4.1 Frequency Control Register (FRQCR) FRQCR is a 16-bit readable/writable register that specifies whether a clock is output from the CKIO pin in standby mode, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the peripheral clock. Only word access can be used on FRQCR. FRQCR is initialized by a power-on reset due to the external input signal. However, it is not initialized by a power-on reset due to a WDT overflow. Rev. 5.00 Mar. 15, 2007 Page 206 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) Bit 15 to 13 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 CKOEN 1 R/W Clock Output Enable Specifies whether a clock continues to be output from the CKIO pin or the output level of the CKIO signal is fixed when leaving software standby mode. The CKIO output is fixed low when this bit is set to 0. Therefore, the malfunction of external circuits because of an unstable CKIO clock when leaving software standby mode can be prevented. 0: Output level of the CKIO signal is fixed low in software standby mode. 1: Clock input to the EXTAL pin is output to the CKIO pin during software standby mode in clock mode 1 or 5. However, the output level of the CKIO pin is fixed low for two cycles of Pφ when changing from the normal mode to the standby mode. This prevents hazard which occurs when the source of the CKIO signal is changed from the PLL2 output to the EXTAL signal. 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 9 8 7 to 3 STC2 STC1 STC0  0 0 0 All 0 R/W R/W R/W R PLL Circuit 1 Frequency Multiplication Ratio 000: ×1 001: ×2 Other values: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 207 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) Bit 2 1 0 Bit Name PFC2 PFC1 PFC0 Initial Value 0 1 1 R/W R/W R/W R/W Description Peripheral Clock Frequency Division Ratio Specify the division ratio of the peripheral clock frequency with respect to the output frequency of PLL circuit 1. 000: ×1 001: ×1/2 011: ×1/4 Other values: Setting prohibited 8.4.2 PHY Clock Frequency Control Register (MCLKCR) MCLKCR is an 8-bit readable/writable register. This register must be written to in words. The upper byte of the word data must be H'5A and the lower byte is the write data. Bit 7 6 Bit Name FLSCS1 FLSCS0 Initial Value 0 1 R/W R/W R/W Description Source Clock Select Select the source clock. 00: PLL1 output clock 01: PLL1 output clock 10: Setting prohibited 11: Setting prohibited 5 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 1 0 FLDIVS2 FLDIVS1 FLDIVS0 0 1 1 R/W R/W R/W Divider Select Set the division ratio of PLL1 output. 000: ×1 001: ×1/2 011: ×1/4 100: ×1/5 Other values: Setting prohibited Rev. 5.00 Mar. 15, 2007 Page 208 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) 8.4.3 Usage Notes • MCLKCR is used only to generate clocks for the on-chip PHY. However, dedicated clocks input from the CK_PHY pin can be used instead of Mφ, which is set by MCLKCR as clocks for the on-chip PHY. • When changing the contents of MCLKCR or FRQCR, make sure that the on-chip PHY is in the reset state. Otherwise, a hazard may be temporarily generated on Mφ output. To use Mφ as clocks for the on-chip PHY, assert the module reset of the on-chip PHY after the contents of MCLKCR or FRQCR have been changed. Rev. 5.00 Mar. 15, 2007 Page 209 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) 8.5 Changing Frequency The internal clock frequency can be changed by changing the multiplication ratio of PLL circuit 1. The peripheral clock frequency can be changed either by changing the multiplication ratio of PLL circuit 1 or by changing the division ratio of divider 1. All of these are controlled by software through the frequency control register. The methods are described below. 8.5.1 Changing Multiplication Ratio The PLL lock time must be preserved when the multiplication ratio of PLL circuit 1 is changed. The on-chip WDT counts for preserving the PLL lock time. 1. In the initial state, the multiplication ratio of PLL circuit 1 is 1. 2. Set a value that satisfies the given PLL lock time in the WDT and stop the WDT. The following must be set.  TME bit in WTCSR = 0: WDT stops  Bits CKS2 to CKS0 in WTCSR: Division ratio of WDT count clock  WTCNT: Initial counter value 3. Set the desired value in bits STC2 to STC0 while the MDCHG bit in STBCR is 0. The division ratio can also be set in bits PFC2 to PFC0. 4. This LSI pauses internally and the WDT starts incrementing. The internal and peripheral clocks both stop and only the WDT is supplied with the clock. The clock will continue to be output on the CKIO pin. 5. Supply of the specified clock starts at a WDT count overflow, and this LSI starts operating again. The WDT stops after it overflows. Notes: 1. When the MDCHG bit in STBCR is set to 1, changing the FRQCR value has no effect on the operation immediately. For details, see section 8.5.3, Changing Clock Operating Mode. 2. The multiplication ratio should be changed after completion of the operation, if the onchip peripheral module is operating. The internal and peripheral clocks are stopped during the multiplication ratio is changed. The communication error may occur by the peripheral module communicating to the external IC, and the time error may occur by the timer unit (except the WDT). The edge detection of external interrupts (NMI and IRQ7 to IRQ0) cannot be performed. Rev. 5.00 Mar. 15, 2007 Page 210 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) 8.5.2 Changing Division Ratio The WDT will not count unless the multiplication ratio is changed simultaneously. 1. In the initial state, PFC2 to PFC0 = 011. 2. Set the desired values in bits PFC2 to PFC0 while the MDCHG bit in STBCR is 0. The values that can be set are limited by the clock mode and the multiplication ratio of PLL circuit 1. Note that if the wrong value is set, this LSI will malfunction. 3. The clock is immediately changed to the new division ratio. Note: When the MDCHG bit in STBCR is set to 1, changing the FRQCR value has no effect on the operation immediately. For details, see section 8.5.3, Changing Clock Operating Mode. 8.5.3 Changing Clock Operating Mode The values of the mode control pins (MD2 to MD0) that define a clock operating mode are fetched at a power-on reset and software standby while the MDCHG bit in STBCR is set to 1 register. Even if changing the FRQCR with the MDCHG bit set to 1, the clock mode cannot immediately be changed to the specified clock mode. This change can be reflected as a multiplication ratio or a division ratio after leaving software standby mode to change operating modes. Reducing the PLL settling time without changing again the multiplication ratio after the operating mode changing is possible by the use of this. The procedures for the mode change using software standby mode are described below. 1. Set bits MD2 to MD0 to the desired clock operating mode. 2. Set both the STBY and MDCHG bits in STBCR to 1. 3. Set the adequate value to the WDT so that the given oscillation settling time can be satisfied. Then stop the WDT. 4. Set FRQCR to the desired mode. Set bits STC2 to STC0 to the desired multiplication ratio. At this time, a division ratio can be set in bits PFC2 to PFC0. During the operation before the mode change, the clock cannot be changed to the specified clock. 5. Enter software standby mode using the SLEEP instruction. 6. Leave software standby mode using an interrupt. 7. After leaving software standby mode, this LSI starts the operation with the value of FRQCR that has been set before the mode change. Rev. 5.00 Mar. 15, 2007 Page 211 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) Notes: 1. Pins MD2 to MD0 should be set during the operation before the mode change or during software standby mode before requesting an interrupt. 2. Clear the STBY bit in STBCR in the exception handling routine for the interrupt in step 6. Otherwise, software standby mode is entered again. For details, see section 10.5.2, Canceling Software Standby Mode. 3. Once bits STC2 to STC0 are changed, the clock is not switched to the specified clock even if only bits PFC2 to PFC0 are changed. When bits STC2 to STC0 are changed after the MDCHG bit has been set to 1, the FRQCR setting must not be made until the clock mode is changed. Rev. 5.00 Mar. 15, 2007 Page 212 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) 8.6 Notes on Board Design Note on Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and CL2, and feedback resistor R1 as close to the XTAL and EXTAL pins as possible. In addition, to minimize induction and thus obtain oscillation at the correct frequency, the capacitors to be attached to the resonator must be grounded to the same ground. Do not bring wiring patterns close to these components. Signal lines prohibited CL1 CL2 Reference value CL1 = 10 to 33 pF CL2 = 10 to 33 pF Rl = 1MΩ Note: The values for CL1, CL2, and the damping resistance RI should be determined after consultation with the crystal resonator manufacturer. Rl EXTAL XTAL This LSI Figure 8.2 Note on Using a Crystal Resonator Notes on Using External Clocks: When external clocks are input from the EXTAL pin, leave the XTAL pin open. In order to prevent a malfunction due to the reflection noise caused in a signal line which connected to XTAL pin, cut this signal line as short as possible. Notes on Bypass Capacitor: A multilayer ceramic capacitor must be inserted for each pair of Vss and Vcc as a bypass capacitor. The bypass capacitor must be inserted as close as possible to the power supply pins of the LSI. Note that the capacitance and frequency characteristics of the bypass capacitor must be appropriate for the operating frequency of the LSI. • Digital power supply pairs for internal logic A7-B7, E2-E1, E13-E12, H4-H3, K12-K13, M10-N10 • Power supply pairs for input and output A1-B1, A9-B9, B15-B14, H14-H15, K1-K2, R7-P7, P13-P14 • Power supply pairs for PLL N15-N14, R15-P15 • Analog power supply pairs for PHY N4-(N3, AP3), P4-P5 • No ground available that can be paired with R5 (Vcc3A) Rev. 5.00 Mar. 15, 2007 Page 213 of 794 REJ09B0237-0500 Section 8 Clock Pulse Generator (CPG) Notes on Using a PLL Oscillator Circuit: In the Vcc and Vss connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interference. Since the analog power supply pins of the PLL are sensitive to the noise, the system may malfunction due to inductive interference at the other power supply pins. To prevent such malfunction, the analog power supply pin Vcc and digital power supply pin VccQ should not supply the same resources on the board if at all possible. Signal lines prohibited Vcc(PLL2) Power supply Vcc Vss(PLL2) Vcc(PLL1) Vss Vss(PLL1) Figure 8.3 Note on Using a PLL Oscillator Circuit Rev. 5.00 Mar. 15, 2007 Page 214 of 794 REJ09B0237-0500 Section 9 Watchdog Timer (WDT) Section 9 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT) that can reset this LSI by the overflow of the counter when the value of the counter has not been updated because of a system runaway. The WDT is a single-channel timer that uses a peripheral clock as an input and counts the clock settling time when leaving software standby mode and temporary standby state, such as frequency changes. It can also be used as an interval timer. 9.1 Features The WDT has the following features: • Can be used to ensure the clock settling time. The WDT can be used when leaving software standby mode and the temporary standby state which occur when the clock frequency is changed. • Can switch between watchdog timer mode and interval timer mode. • Internal resets in watchdog timer mode Internal resets are generated when the counter overflows. • Interrupts are generated in interval timer mode Interval timer interrupts are generated when the counter overflows. • Choice of eight counter input clocks Eight clocks (×1 to ×1/4096) that are obtained by dividing the peripheral clock can be chosen. Rev. 5.00 Mar. 15, 2007 Page 215 of 794 REJ09B0237-0500 Section 9 Watchdog Timer (WDT) Figures 9.1 is a block diagram of the WDT. WDT Standby cancellation Standby mode Peripheral clock (Pφ) Internal reset request Reset control Clock selection Clock selector Interrupt request Interrupt control WTCSR Overflow Clock Divider Standby control WTCNT Bus interface [Legend] WTCSR: WTCNT: Watchdog timer control/status register Watchdog timer counter Figure 9.1 Block Diagram of WDT Rev. 5.00 Mar. 15, 2007 Page 216 of 794 REJ09B0237-0500 Section 9 Watchdog Timer (WDT) 9.2 Register Descriptions The WDT has the following two registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 24, List of Registers. • Watchdog timer counter (WTCNT) • Watchdog timer control/status register (WTCSR) 9.2.1 Watchdog Timer Counter (WTCNT) WTCNT is an 8-bit readable/writable register that increments on the selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. WTCNT is not initialized by an internal power-on reset due to the WDT overflow. WTCNT is initialized to H'00 by a power-on reset input to the pin and an H-UDI reset. Use a word access to write to WTCNT, with H'5A in the upper byte. Use a byte access to read WTCNT. Note: The writing method for WTCNT differs from other registers so that the WTCNT value cannot be changed accidentally. For details, see section 9.2.3, Notes on Register Access. 9.2.2 Watchdog Timer Control/Status Register (WTCSR) WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the counting, bits to select the timer mode and overflow flags, and enable bits. WTCSR holds its value in the internal reset state due to the WDT overflow. WTCSR is initialized to H'00 by a power-on reset input to the pin and an H-UDI reset. To use it for counting the clock settling time when leaving software standby mode, WTCSR holds its value after a counter overflow. Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a byte access to read WTCSR. Note: The writing method for WTCNT differs from other registers so that the WTCNT value cannot be changed accidentally. For details, see section 9.2.3, Notes on Register Access. Rev. 5.00 Mar. 15, 2007 Page 217 of 794 REJ09B0237-0500 Section 9 Watchdog Timer (WDT) Bit 7 Initial Bit Name Value TME 0 R/W R/W Description Timer Enable Starts and stops timer operation. Clear this bit to 0 when using the WDT in software standby mode or when changing the clock frequency. 0: Timer disabled: Count-up stops and WTCNT value is retained 1: Timer enabled 6 WT/IT 0 R/W Timer Mode Select Selects whether to use the WDT as a watchdog timer or an interval timer. 0: Interval timer mode 1: Watchdog timer mode Note: If WT/IT is modified when the WDT is operating, the up-count may not be performed correctly. 5  0 R Reserved This bit is always red as 0. The write value should always be 0. 4 WOVF 0 R/W Watchdog Timer Overflow Indicates that WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode 3 IOVF 0 R/W Interval Timer Overflow Indicates that WTCNT has overflowed in interval timer mode. This bit is not set in watchdog timer mode. 0: No overflow 1: WTCNT has overflowed in interval timer mode Rev. 5.00 Mar. 15, 2007 Page 218 of 794 REJ09B0237-0500 Section 9 Watchdog Timer (WDT) Bit 2 1 0 Initial Bit Name Value CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W R/W Description Clock Select 2 to 0 These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock (Pφ). The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (Pφ) is 25 MHz. 000: Pφ (10 µs) 001: Pφ /4 (41 µs) 010: Pφ /16 (164 µs) 011: Pφ /32 (328 µs) 100: Pφ /64 (655 µs) 101: Pφ /256 (2.62 ms) 110: Pφ /1024 (10.49 ms) 111: Pφ /4096 (41.94 ms) Note: If bits CKS2 to CKS0 are modified when the WDT is operating, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not operating. 9.2.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 9.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. Rev. 5.00 Mar. 15, 2007 Page 219 of 794 REJ09B0237-0500 Section 9 Watchdog Timer (WDT) WTCNT write 15 8 H'5A 7 Write data 0 Address: H'F815FF84 WTCSR write 15 Address: H'F815FF86 H'A5 8 7 Write data 0 Figure 9.2 Writing to WTCNT and WTCSR 9.3 9.3.1 WDT Operation Canceling Software Standbys The WDT can be used to cancel software standby mode with an NMI interrupt or external interrupt (IRQ). The procedure is described below. (The WDT does not run when resets are used for canceling, so keep the RES pin low until the clock stabilizes.) 1. Before transition to software standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. Move to software standby mode by executing a SLEEP instruction to stop the clock. 4. The WDT starts counting by detecting the change of input levels of the NMI or IRQ pin. 5. When the WDT count overflows, the CPG starts supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 6. Since the WDT continues counting from H'00, set the STBY bit in STBCR to 0 in the interrupt processing program and this will stop the WDT to count. When the STBY bit remains 1, the LSI again enters software standby mode when the WDT has counted up to H'80. This software standby mode can be canceled by a power-on reset. Rev. 5.00 Mar. 15, 2007 Page 220 of 794 REJ09B0237-0500 Section 9 Watchdog Timer (WDT) 9.3.2 Changing Frequency To change the multiplication ratio of PLL circuit 1, use the WDT. When changing the frequency only by switching the divider, do not use the WDT. 1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. When bits STC2 to STC0 in the frequency control register (FRQCR) is written, the processor stops temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG resumes supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 5. WTCNT stops at the value of H'00. 6. Before changing WTCNT after the execution of the frequency change instruction, always confirm that the value of WTCNT is H'00 by reading WTCNT. 9.3.3 Using Watchdog Timer Mode 1. Set the WT/IT bit in WTCSR to 1, set the type of count clock in bits CKS2 to CKS0, and set the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates a power-on reset. WTCNT then resumes counting. Rev. 5.00 Mar. 15, 2007 Page 221 of 794 REJ09B0237-0500 Section 9 Watchdog Timer (WDT) 9.3.4 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the WTCNT overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval timer interrupt request is sent to the INTC. The WTCNT then resumes counting. 9.4 Usage Notes Pay attention to the following points when using the WDT. While using the WDT in interval mode, no overflow occurs by the H'00 immediately after writing H'FF to WDTCNT. (IOVF in WTCSR is not set.) The overflow occurs at the point when the count reaches H'00 after one cycle. This phenomenon does not occur when the WDT is used in watchdog timer mode. Rev. 5.00 Mar. 15, 2007 Page 222 of 794 REJ09B0237-0500 Section 10 Power-Down Modes Section 10 Power-Down Modes This LSI supports the following power-down modes: sleep mode, software standby mode, module standby mode. 10.1 Features • Supports sleep mode, software standby mode, and module standby 10.1.1 Types of Power-Down Modes This LSI has the following power-down modes. • Sleep mode • Software standby mode • Module standby mode (cache, U-memory, UBC, H-UDI, and on-chip peripheral modules) Table 10.1 shows the methods to make a transition from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode. Table 10.1 States of Power-Down Modes State CPU Register Held On-Chip Memory Halts (contents remained) On-Chip Peripheral Modules Run Canceling Procedure • Interrupt other than user break • Halts Held Halts (contents remained) Specified module halts (contents remained) Halt Held • • Reset NMI, IRQ Reset Mode Sleep Transition Method CPG Execute SLEEP Runs instruction with STBY bit in STBCR cleared to 0. CPU Halts Pins Held Software Execute SLEEP Halts standby instruction with STBY bit in STBCR set to 1. Module standby Set MSTP bits in STBCR2 to STBCR4 to 1. Runs Runs Held Specified module halts Held • • Clear MSTP bit to 0 Power-on reset Rev. 5.00 Mar. 15, 2007 Page 223 of 794 REJ09B0237-0500 Section 10 Power-Down Modes 10.2 Input/Output Pins Table 10.2 lists the pins used for the power-down modes. Table 10.2 Pin Configuration Pin Name Reset input pin Abbr. RES I/O Input Description Reset input signal. Reset by low level. 10.3 Register Descriptions There are following registers used for the power-down modes. For details on the addresses of these registers and the states of these registers in each processing state, see section 24, List of Registers. • • • • Standby control register (STBCR) Standby control register 2 (STBCR2) Standby control register 3 (STBCR3) Standby control register 4 (STBCR4) Rev. 5.00 Mar. 15, 2007 Page 224 of 794 REJ09B0237-0500 Section 10 Power-Down Modes 10.3.1 Standby Control Register (STBCR) STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode. Bit 7 Bit Name STBY Initial Value 0 R/W R/W Description Standby Specifies transition to software standby mode. 0: Executing SLEEP instruction makes this LSI sleep mode 1: Executing SLEEP instruction makes this LSI software standby mode 6 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 MDCHG 0 R/W MD2 to MD0 Pin Control Specifies whether or not the values of pins MD2 to MD0 are reflected in software standby mode. The values of pins MD2 to MD0 are reflected at returning from software standby mode by an interrupt when the MDCHG bit has been set to 1. 0: The values of pins MD2 to MO0 are not reflected in software standby mode. 1: The values of pins MD2 to MD0 are reflected in software standby mode. 2 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 225 of 794 REJ09B0237-0500 Section 10 Power-Down Modes 10.3.2 Standby Control Register 2 (STBCR2) STBCR2 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode. Bit 7 Bit Name MSTP10 Initial Value 0 R/W R/W Description Module Stop Bit 10 When this bit is set to 1, the supply of the clock to the H-UDI is halted. 0: H-UDI operates 1: Clock supply to H-UDI halted 6 MSTP9 0 R/W Module Stop Bit 9 When this bit is set to 1, the supply of the clock to the UBC is halted. 0: UBC operates 1: Clock supply to UBC halted 5 MSTP8 0 R/W Module Stop Bit 8 When this bit is set to 1, the supply of the clock to the DMAC is halted. 0: DMAC operates 1: Clock supply to DMAC halted 4, 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 MSTP5 0 R/W Module Stop Bit 5 When this bit is set to 1, the supply of the clock to the cache memory is halted. 0: Cache memory operates 1: Clock supply to cache memory halted 1 MSTP4 0 R/W Module Stop Bit 4 When this bit is set to 1, the supply of the clock to the U memory is halted. 0: U memory operates 1: Clock supply to the U memory halted Rev. 5.00 Mar. 15, 2007 Page 226 of 794 REJ09B0237-0500 Section 10 Power-Down Modes Bit 0 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 10.3.3 Standby Control Register 3 (STBCR3) STBCR3 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode. Bit 7 to 5 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 MSTP15 0 R/W Module Stop Bit 15 When this bit is set to 1, the supply of the clock to the CMT is halted. 0: CMT operates 1: Clock supply to CMT halted 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 MSTP13 0 R/W Module Stop Bit 13 When this bit is set to 1, the supply of the clock to the SCIF2 is halted. 0: SCIF2 operates 1: Clock supply to SCIF2 halted 1 MSTP12 0 R/W Module Stop Bit 12 When this bit is set to 1, the supply of the clock to the SCIF1 is halted. 0: SCIF1 operates 1: Clock supply to SCIF1 halted Rev. 5.00 Mar. 15, 2007 Page 227 of 794 REJ09B0237-0500 Section 10 Power-Down Modes Bit 0 Bit Name MSTP11 Initial Value 0 R/W R/W Description Module Stop Bit 11 When this bit is set to 1, the supply of the clock to the SCIF0 is halted. 0: SCIF0 operates 1: Clock supply to SCIF0 halted 10.3.4 Standby Control Register 4 (STBCR4) STBCR4 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode. Bit 7 to 5 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 MSTP23 0 R/W Module Stop Bit 23 When this bit is set to 1, the supply of the clock to the HIF is halted. 0: HIF operates 1: Clock supply to HIF halted 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 MSTP21 0 R/W Module Stop Bit 21 When this bit is set to 1, the supply of the clock to the SIOF is halted. 0: SIOF operates 1: Clock supply to SIOF halted 1 MSTP20 0 R/W Module Stop Bit 20 When this bit is set to 1, the supply of the clock to the PHY is halted. 0: PHY-IF operates 1: Clock supply to PHY-IF halted Rev. 5.00 Mar. 15, 2007 Page 228 of 794 REJ09B0237-0500 Section 10 Power-Down Modes Bit 0 Bit Name MSTP19 Initial Value 0 R/W R/W Description Module Stop Bit 19 When this bit is set to 1, the supply of the clock to the EtherC and E-DMAC is halted. 0: EtherC and E-DMAC operate 1: Clock supply to EtherC and E-DMAC halted 10.4 10.4.1 Sleep Mode Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to operate in sleep mode and the clock continues to be output to the CKIO pin. 10.4.2 Canceling Sleep Mode Sleep mode is canceled by an interrupt other than a user break (NMI, H-UDI, IRQ, and on-chip peripheral module) or a reset. Canceling with Interrupt: When a user-break, NMI, H-UDI, IRQ, or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. When the priority level of an IRQ or on-chip peripheral module interrupt is lower than the interrupt mask level set in the status register (SR) of the CPU, an interrupt request is not accepted preventing sleep mode from being canceled. Canceling with Reset: Sleep mode is canceled by a power-on reset or an H-UDI reset. Rev. 5.00 Mar. 15, 2007 Page 229 of 794 REJ09B0237-0500 Section 10 Power-Down Modes 10.5 10.5.1 Software Standby Mode Transition to Software Standby Mode This LSI switches from a program execution state to software standby mode by executing the SLEEP instruction when the STBY bit in STBCR is 1. In software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin also halts. The contents of the CPU and cache registers remain unchanged. Some registers of on-chip peripheral modules are, however, initialized. Table 10.3 lists the states of on-chip peripheral modules registers in software standby mode. Table 10.3 Register States in Software Standby Mode Module Interrupt controller (INTC) Clock pulse generator (CPG) User break controller (UBC) Bus state controller (BSC) Direct memory access controller (DMAC) Ethernet controller (EtherC) Direct memory access controller for Ethernet controller (E-DMAC) I/O port User debugging interface (H-UDI) Serial communication interface with FIFO (SCIF0 to SCIF2) Compare match timer (CMT0 and CMT1) Host interface (HIF) Serial IO with FIFO (SIOF) Ethernet physical layer transceiver (PHY) Note: * Registers Initialized           All registers   Some registers* Registers Retaining Data All registers All registers All registers All registers All registers All registers All registers All registers All registers All registers  All registers All registers Some registers* For details, see section 22, Ethernet Physical Layer Transceiver (PHY). Rev. 5.00 Mar. 15, 2007 Page 230 of 794 REJ09B0237-0500 Section 10 Power-Down Modes The procedure for switching to software standby mode is as follows: 1. Clear the TME bit in the timer control register (WTCSR) of the WDT to 0 to stop the WDT. 2. Set the timer counter (WTCNT) of the WDT to 0 and bits CKS2 to CKS0 in WTCSR to appropriate values to secure the specified oscillation settling time. 3. After setting the STBY bit in STBCR to 1, execute the SLEEP instruction. 4. Software standby mode is entered and the clocks within this LSI are halted. 10.5.2 Canceling Software Standby Mode Software standby mode is canceled by interrupts (NMI, IRQ) or a reset. Canceling with Interrupt: The WDT can be used for hot starts. When an NMI or IRQ interrupt is detected, the clock will be supplied to the entire LSI and software standby mode will be canceled after the time set in the timer control/status register of the WDT has elapsed. Interrupt exception handling is then executed. After the branch to the interrupt handling routine, clear the STBY bit in STBCR. WTCNT stops automatically. If the STBY bit is not cleared, WTCNT continues operation and a transition is made to software standby mode* when it reaches H'80. This function prevents data destruction due to the voltage rise by an unstable power supply voltage. IRQ cancels the software standby mode when the input condition matches the specified detect condition while the IRQn1S and IRQn0S bits in IRQCR are not B'00 (settings other than the low level detection). When the priority level of an IRQ interrupt is lower than the interrupt mask level set in the status register (SR) of the CPU, the execution of the instruction following the SLEEP instruction starts again after the cancellation of software standby mode. When the priority level of an IRQ interrupt is higher than the interrupt mask level set in the status register (SR) of the CPU, IRQ interrupt exception handling is executed after the cancellation of software standby mode. Note: * This software standby mode can be canceled only by a power-on reset. Rev. 5.00 Mar. 15, 2007 Page 231 of 794 REJ09B0237-0500 Section 10 Power-Down Modes Interrupt request Crystal oscillator settling time and PLL synchronization time WTCNT value WDT overflow and branch to interrupt handling routine Clear bit STBCR.STBY before WTCNT reaches H'80. When STBCR.STBY is cleared, WTCNT halts automatically. H'FF H'80 Time Figure 10.1 Canceling Standby Mode with STBY Bit in STBCR Canceling with Reset: Software standby mode is canceled by a power-on reset. Keep the RES pin low until the clock oscillation settles. The internal clock will continue to be output to the CKIO pin. 10.6 10.6.1 Module Standby Mode Transition to Module Standby Mode Setting the MSTP bits in the standby control registers (STBCR2 to STBCR4) to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal mode. In module standby mode, the states of the external pins of the on-chip peripheral modules change depending on the on-chip peripheral module and port settings. Almost all of the registers retain its previous state. 10.6.2 Canceling Module Standby Function The module standby function can be canceled by clearing the MSTP bits in STBCR2 to STBCR4 to 0, or by a power-on reset. Rev. 5.00 Mar. 15, 2007 Page 232 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) Section 11 Ethernet Controller (EtherC) This LSI has an on-chip Ethernet controller (EtherC) conforming to the Ethernet or the IEEE802.3 MAC (Media Access Control) layer standard. Connecting a physical-layer LSI (PHY-LSI) complying with this standard enables the Ethernet controller (EtherC) to perform transmission and reception of Ethernet/IEEE802.3 frames. This LSI has one MAC layer interface. The Ethernet controller is connected to the direct memory access controller for Ethernet controller (E-DMAC) inside this LSI, and carries out high-speed data transfer to and from the memory. Figure 11.1 shows a configuration of the EtherC. 11.1 • • • • • • Features Transmission and reception of Ethernet/IEEE802.3 frames Supports 10/100 Mbps receive/transfer Supports full-duplex and half-duplex modes Conforms to IEEE802.3u standard MII (Media Independent Interface) Magic Packet detection and Wake-On-LAN (WOL) signal output Conforms to IEEE802.3x flow control Rev. 5.00 Mar. 15, 2007 Page 233 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) E-DMAC EtherC E-DMAC interface MAC Transmit controller Receive controller Command status interface MII PHY Figure 11.1 Configuration of EtherC Rev. 5.00 Mar. 15, 2007 Page 234 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.2 Input/Output Pins Table 11.1 lists the pin configuration of the EtherC. Table 11.1 Pin Configuration Port 0 Abbreviation I/O TX-CLK* Input Function Transmit Clock Timing reference signal for the TX-EN, MII_TXD3 to MII_TXD0, TX-ER signals 0 RX-CLK* Input Receive Clock Timing reference signal for the RX-DV, MII_RXD3 to MII_RXD0, RX-ER signals 0 TX-EN* Output Transmit Enable Indicates that transmit data is ready on pins MII_TXD3 to MII_TXD0. 0 0 0 MII_TXD3 to MII_TXD0* TX-ER* RX-DV* Output Output Input Transmit Data 4-bit transmit data Transmit Error Notifies the PHY-LSI of error during transmission Receive Data Valid Indicates that valid receive data is on pins MII_RXD3 to MII_RXD0. 0 0 0 0 0 0 MII_RXD3 to MII_RXD0* RX-ER* CRS COL MDC MDIO Input Input Input Input Output Input/ Output Receive Data 4-bit receive data Receive Error Identifies error state occurred during data reception. Carrier Detection Carrier detection signal Collision Detection Collision detection signal Management Data Clock Reference clock signal for information transfer via MDIO Management Data I/O Bidirectional signal for exchange of management information between this LSI and PHY Rev. 5.00 Mar. 15, 2007 Page 235 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) Port 0 0 0 Note: Abbreviation I/O LNKSTA EXOUT WOL * Input Output Output Function Link Status Inputs link status from PHY General-Purpose External Output Signal indicating value of register-bit (ECMR0-ELB) Wake-On-LAN Signal indicating reception of Magic Packet MII signal conforming to IEEE802.3u Rev. 5.00 Mar. 15, 2007 Page 236 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.3 Register Description The EtherC has the following registers. For details on addresses and access sizes of registers, see section 24, List of Registers. MAC Layer Interface Control Registers: • EtherC mode register (ECMR) • EtherC status register (ECSR) • EtherC interrupt permission register (ECSIPR) • PHY interface register (PIR) • MAC address high register (MAHR) • MAC address low register (MALR) • Receive frame length register (RFLR) • PHY status register (PSR) • Transmit retry over counter register (TROCR) • Delayed collision detect counter register (CDCR) • Lost carrier counter register (LCCR) • Carrier not detect counter register (CNDCR) • CRC error frame counter register (CEFCR) • Frame receive error counter register (FRECR) • Too-short frame receive counter register (TSFRCR) • Too-long frame receive counter register (TLFRCR) • Residual-bit frame counter register (RFCR) • Multicast address frame counter register (MAFCR) • IPG register (IPGR) • Automatic PAUSE frame set register (APR) • Manual PAUSE frame set register (MPR) • PAUSE frame retransfer count set register (TPAUSER) Rev. 5.00 Mar. 15, 2007 Page 237 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.3.1 EtherC Mode Register (ECMR) ECMR is a 32-bit readable/writable register and specifies the operating mode of the Ethernet controller. The settings in this register are normally made in the initialization process following a reset. The operating mode setting must not be changed while the transmitting and receiving functions are enabled. To switch the operating mode, return the EtherC and E-DMAC to their initial states by means of the SWR bit in EDMR before making settings again. Bit 31 to 20 Initial Bit Name Value  All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 19 ZPF 0 R/W 0 time parameter PAUSE Frame Use Enable 0: Disables PAUSE frame control in which the TIME parameter is 0. The next frame is transmitted after the time indicated by the Timer value has elapsed. When the EtherC receives a PAUSE frame with the time indicated by the Timer value set to 0, the PAUSE frame is discarded. 1: Enables PAUSE frame control in which the TIME parameter is 0. A PAUSE frame with the Timer value set to 0 is transmitted when the number of data in the receive FIFO is less than the FCFTR value before the time indicated by the Timer value has not elapsed. When the EtherC receives a PAUSE frame with the time indicated by the Timer value set to 0, the transmit wait state is canceled. 18 PFR 0 R/W PAUSE Frame Receive Mode 0: PAUSE frame is not transferred to the E-DMAC 1: PAUSE frame is transferred to the E-DMAC 17 RXF 0 R/W Receive Flow Control Operating Mode 0: PAUSE frame detection function is disabled 1: Receive flow control function is enabled Rev. 5.00 Mar. 15, 2007 Page 238 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) Bit 16 Initial Bit Name Value TXF 0 R/W R/W Description Transmit Flow Control Operating mode 0: Transmit flow control function is disabled 1: Transmit flow control function is enabled 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 PRCEF 0 R/W Permit Receive CRC Error Frame 0: A frame with a CRC error is received as a frame with an error. 1: A frame with a CRC error is received as a frame without an error. For a frame with an error, a CRC error is reflected in the ECSR of the E-DMAC and the status of the receive descriptor. For a frame without an error, the frame is received as normal frame. 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 MPDE 0 R/W Magic Packet Detection Enable Enables or disables Magic Packet detection by hardware to allow activation from the Ethernet. 0: Magic Packet detection is not enabled 1: Magic Packet detection is enabled 8, 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6 RE 0 R/W Reception Enable If a frame is being received when this bit is switched from receive function enabled (RE = 1) to disabled (RE = 0), the receive function will be enabled until reception of the corresponding frame is completed. 0: Receive function is disabled 1: Receive function is enabled Rev. 5.00 Mar. 15, 2007 Page 239 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) Bit 5 Initial Bit Name Value TE 0 R/W R/W Description Transmission Enable If a frame is being transmitted when this bit is switched from transmit function enabled (TE = 1) to disabled (TE = 0), the transmit function will be enabled until transmission of the corresponding frame is completed. 0: Transmit function is disabled 1: Transmit function is enabled 4  0 R Reserved This bit is always read as 0. The write value should always be 0. 3 ILB 0 R/W Internal Loop Back Mode Specifies loopback mode in the EtherC. 0: Normal data transmission/reception is performed. 1: When DM = 1, data loopback is performed inside the MAC in the EtherC. 2 ELB 0 R/W External Loop Back Mode This bit value is output directly to this LSI’s generalpurpose external output pin (EXOUT). This bit is used for loopback mode directives, etc., in the LSI, using the EXOUT pin. In order for LSI loopback to be implemented using this function, the LSI must have a pin corresponding to the EXOUT pin. 0: Low-level output from the EXOUT pin 1: High-level output from the EXOUT pin 1 DM 0 R/W Duplex Mode Specifies the EtherC transfer method. 0: Half-duplex transfer is specified 1: Full-duplex transfer is specified Rev. 5.00 Mar. 15, 2007 Page 240 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) Bit 0 Initial Bit Name Value PRM 0 R/W R/W Description Promiscuous Mode Setting this bit enables all Ethernet frames to be received. All Ethernet frames means all receivable frames, irrespective of differences or enabled/disabled status (destination address, broadcast address, multicast bit, etc.). 0: EtherC performs normal operation 1: EtherC performs promiscuous mode operation 11.3.2 EtherC Status Register (ECSR) ECSR is a 32-bit readable/writable register and indicates the status in the EtherC. This status can be notified to the CPU by interrupts. When 1 is written to the PSRTO, LCHNG, MPD, and ICD, the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that generate interrupt, the interrupt can be enabled or disabled according to the corresponding bit in ECSIPR. The interrupts generated due to this status register are indicated in the ECI bit in EESR. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 PSRTO 0 R/W PAUSE Frame Retransfer Retry Over Indicates that during the retransfer of PAUSE frames when the flow control is enabled, the number of retries has exceeded the upper limit set in the automatic PAUSE frame retransfer count set register (TPAUSER). 0: Number of PAUSE frame retransfers has not exceeded the upper limit 1: Number of PAUSE frame retransfers has exceeded the upper limit 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 31 to 5  Rev. 5.00 Mar. 15, 2007 Page 241 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) Bit 2 Bit Name LCHNG Initial Value 0 R/W R/W Description Link Signal Change Indicates that the LNKSTA signal input from the PHY has changed from high to low or low to high. To check the current Link state, refer to the LMON bit in the PHY status register (PSR). 0: Changes in the LNKSTA signal are not detected 1: Changes in the LNKSTA signal are detected (high to low or low to high) 1 MPD 0 R/W Magic Packet Detection Indicates that a Magic Packet has been detected on the line. 0: Magic Packet has not been detected 1: Magic Packet has been detected 0 ICD 0 R/W Illegal Carrier Detection Indicates that the PHY has detected an illegal carrier on the line. If a change in the signal input from the PHY occurs before the software recognition period, the correct information may not be obtained. Refer to the timing specification for the PHY used. 0: LSI has not detected an illegal carrier on the line 1: LSI has detected an illegal carrier on the line Rev. 5.00 Mar. 15, 2007 Page 242 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.3.3 EtherC Interrupt Permission Register (ECSIPR) ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 PSRTOIP 0 R/W PAUSE Frame Retransfer Retry Over Interrupt Enable 0: Interrupt notification by the PSRTO bit is disabled 1: Interrupt notification by the PSRTO bit is enabled 3 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 LCHNGIP 0 R/W LINK Signal Changed Interrupt Enable 0: Interrupt notification by the LCHNG bit is disabled 1: Interrupt notification by the LCHNG bit is enabled 1 MPDIP 0 R/W Magic Packet Detection Interrupt Enable 0: Interrupt notification by the MPD bit is disabled 1: Interrupt notification by the MPD bit is enabled 0 ICDIP 0 R/W Illegal Carrier Detection Interrupt Enable 0: Interrupt notification by the ICD bit is disabled 1: Interrupt notification by the ICD bit is enabled 31 to 5  Rev. 5.00 Mar. 15, 2007 Page 243 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.3.4 PHY Interface Register (PIR) PIR is a 32-bit readable/writable register that provides a means of accessing the PHY registers via the MII. Bit Bit Name Initial Value All 0 R/W Description R Reserved These bits are always read as 0. The write value should always be 0. 3 2 MDI MDO Undefined R 0 MII Management Data-In Indicates the level of the MDIO pin. R/W MII Management Data-Out Outputs the value set to this bit from the MDIO pin, when the MMD bit is 1. 1 MMD 0 R/W MII Management Mode Specifies the data read/write direction with respect to the MII. 0: Read direction is indicated 1: Write direction is indicated 0 MDC 0 R/W MII Management Data Clock Outputs the value set to this bit from the MDC pin and supplies the MII with the management data clock. For the method of accessing the MII registers, see section 11.4.4, Accessing MII Registers. 31 to 4  Rev. 5.00 Mar. 15, 2007 Page 244 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.3.5 MAC Address High Register (MAHR) MAHR is a 32 -bit readable/writable register that specifies the upper 32 bits of the 48-bit MAC address. The settings in this register are normally made in the initialization process after a reset. The MAC address setting must not be changed while the transmitting and receiving functions are enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states by means of the SWR bit in EDMR before making settings again. Bit Bit Name Initial Value All 0 R/W R/W Description MAC Address Bits These bits are used to set the upper 32 bits of the MAC address. If the MAC address is 01-23-45-67-89-AB (hexadecimal), the value set in this register is H'01234567. 31 to 0 MA47 to MA16 11.3.6 MAC Address Low Register (MALR) MALR is a 32-bit readable/writable register that specifies the lower 16 bits of the 48-bit MAC address. The settings in this register are normally made in the initialization process after a reset. The MAC address setting must not be changed while the transmitting and receiving functions are enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states by means of the SWR bit in EDMR before making settings again. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 MA15 to MA0 All 0 R/W MAC Address Bits 15 to 0 These bits are used to set the lower 16 bits of the MAC address. If the MAC address is 01-23-45-67-89-AB (hexadecimal), the value set in this register is H'000089AB. 31 to 16  Rev. 5.00 Mar. 15, 2007 Page 245 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.3.7 Receive Frame Length Register (RFLR) RFLR is a 32-bit readable/writable register and it specifies the maximum frame length (in bytes) that can be received by this LSI. The settings in this register must not be changed while the receiving function is enabled. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 RFL11 to RFL0 All 0 R/W Receive Frame Length 11 to 0 The frame length described here refers to all fields from the destination address up to and including the CRC data. Frame contents from the destination address up to and including the data are actually transferred to memory. CRC data is not included in the transfer. When data that exceeds the specified value is received, the part of the data that exceeds the specified value is discarded. H'000 to H'5EE: 1,518 bytes H'5EF: 1,519 bytes H'5F0: 1,520 bytes : : H'7FF: 2,047 bytes H'800 to H'FFF: 2,048 bytes 31 to 12  Rev. 5.00 Mar. 15, 2007 Page 246 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.3.8 PHY Status Register (PSR) PSR is a read-only register that can read interface signals from the PHY. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 LMON 0 R LNKSTA Pin Status The Link status can be read by connecting the Link signal output from the PHY to the LNKSTA pin. For the polarity, refer to the PHY specifications to be connected. 31 to 1  11.3.9 Transmit Retry Over Counter Register (TROCR) TROCR is a 32-bit counter that indicates the number of frames that were unable to be transmitted in 16 transmission attempts including the retransfer. When 16 transmission attempts have failed, TROCR is incremented by 1. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value All 0 R/W R/W Description Transmit Retry Over Count These bits indicate the number of frames that were unable to be transmitted in 16 transmission attempts including the retransfer. 31 to 0 TROC31 to TROC0 Rev. 5.00 Mar. 15, 2007 Page 247 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.3.10 Delayed Collision Detect Counter Register (CDCR) CDCR is a 32-bit counter that indicates the number of delayed collisions on all lines from a start of transmission. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value All 0 R/W R/W Description Delayed Collision Detect Count These bits indicate the number of delayed collisions on all lines from a start of transmission. 31 to 0 COSDC31 to COSDC0 11.3.11 Lost Carrier Counter Register (LCCR) LCCR is a 32-bit counter that indicates the number of times the carrier was lost during data transmission. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by writing to this register with any value. Bit Bit Name Initial Value All 0 R/W R/W Description Lost Carrier Count These bits indicate the number of times the carrier was lost during data transmission. 31 to 0 LCC31 to LCC0 11.3.12 Carrier Not Detect Counter Register (CNDCR) CNDCR is a 32-bit counter that indicates the number of times the carrier could not be detected while the preamble was being sent. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value All 0 R/W R/W Description Carrier Not Detect Count These bits indicate the number of times the carrier was not detected. 31 to 0 CNDC31 to CNDC0 Rev. 5.00 Mar. 15, 2007 Page 248 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.3.13 CRC Error Frame Counter Register (CEFCR) CEFCR is a 32-bit counter that indicates the number of times a frame with a CRC error was received. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value All 0 R/W R/W Description CRC Error Frame Count These bits indicate the count of CRC error frames received. 31 to 0 CEFC31 to CEFC0 11.3.14 Frame Receive Error Counter Register (FRECR) FRECR is a 32-bit counter that indicates the number of frames input from the PHY for which a receive error was indicated by the RX-ER pin. FRECR is incremented each time the RX-ER pin becomes active. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value All 0 R/W R/W Description Frame Receive Error Count These bits indicate the count of errors during frame reception. 31 to 0 FREC31 to FREC0 11.3.15 Too-Short Frame Receive Counter Register (TSFRCR) TSFRCR is a 32-bit counter that indicates the number of frames of fewer than 64 bytes that have been received. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value All 0 R/W R/W Description Too-Short Frame Receive Count These bits indicate the count of frames received with a length of less than 64 bytes. 31 to 0 TSFC31 to TSFC0 Rev. 5.00 Mar. 15, 2007 Page 249 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.3.16 Too-Long Frame Receive Counter Register (TLFRCR) TLFRCR is a 32-bit counter that indicates the number of frames received with a length exceeding the value specified by the receive frame length register (RFLR). When the value in this register reaches H'FFFFFFFF, the count is halted. TLFRCR is not incremented when a frame containing residual bits is received. In this case, the reception of the frame is indicated in the residual-bit frame counter register (RFCR). The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value All 0 R/W R/W Description Too-Long Frame Receive Count These bits indicate the count of frames received with a length exceeding the value in RFLR. 31 to 0 TLFC31 to TLFC0 11.3.17 Residual-Bit Frame Counter Register (RFCR) RFCR is a 32-bit counter that indicates the number of frames received containing residual bits (less than an 8-bit unit). When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value All 0 R/W R/W Description Residual-Bit Frame Count These bits indicate the count of frames received containing residual bits. 31 to 0 RFC31 to RFC0 11.3.18 Multicast Address Frame Counter Register (MAFCR) MAFCR is a 32-bit counter that indicates the number of frames received with a specified multicast address. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit Bit Name Initial Value All 0 R/W R/W Description Multicast Address Frame Count These bits indicate the count of multicast frames received. 31 to 0 MAFC31 to MAFC0 Rev. 5.00 Mar. 15, 2007 Page 250 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.3.19 IPG Register (IPGR) IPGR sets the IPG (Inter Packet Gap). This register must not be changed while the transmitting and receiving functions of the EtherC mode register (ECMR) are enabled. (For details, refer to section 11.4.6, Operation by IPG Setting.) Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 to 0 IPG4 to IPG0 H'13 R/W Inter Packet Gap Sets the IPG value every 4-bit time. H'00: 20-bit time H'01: 24-bit time : : : : H'13: 96-bit time (Initial value) H'1F: 144-bit time 31 to 5  11.3.20 Automatic PAUSE Frame Set Register (APR) APR sets the TIME parameter value of the automatic PAUSE frame. When transmitting the automatic PAUSE frame, the value set in this register is used as the TIME parameter of the PAUSE frame. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 AP15 to AP0 All 0 R/W Automatic PAUSE Sets the TIME parameter value of the automatic PAUSE frame. At this time, 1 bit means 512-bit time. 31 to 16  Rev. 5.00 Mar. 15, 2007 Page 251 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.3.21 Manual PAUSE Frame Set Register (MPR) MPR sets the TIME parameter value of the manual PAUSE frame. When transmitting the manual PAUSE frame, the value set to this register is used as the TIME parameter of the PAUSE frame. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 MP15 to MP0 All 0 R/W Manual PAUSE Sets the TIME parameter value of the manual PAUSE frame. At this time, 1 bit means 512-bit time. Read values are undefined. 31 to 16  11.3.22 PAUSE Frame Retransfer Count Set Register (TPAUSER) TPAUSER sets the upper limit of the number of times of the PAUSE frame retransfer. TPAUSER must not be changed while the transmitting function is enabled. Bit 31 to 16 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 TPAUSE15 All 0 to TPAUSE0 R/W Upper Limit of the Number of Times of PAUSE Frame Retransfer H'0000: Unlimited number of times of retransfer H'0001: Retransfer once : : H'FFFF: Number of times of retransfer is 65535 Rev. 5.00 Mar. 15, 2007 Page 252 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.4 Operation The overview of the Ethernet controller (EtherC) are shown below. The EtherC transmits and receives PAUSE frames conforming to the Ethernet/IEEE802.3 frames. 11.4.1 Transmission The EtherC transmitter assembles the transmit data on the frame and outputs to MII when there is a transmit request from the E-DMAC. The data transmitted via the MII is transmitted to the lines by PHY-LSI. Figure 11.3 shows the state transition of the EtherC transmitter. Rev. 5.00 Mar. 15, 2007 Page 253 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) TE set Idle FDPX Start of transmission (preamble transmission) Carrier non-detection Retransfer initiation Collision Carrier detection HDPX FDPX Transmission halted HDPX TE reset Carrier detection Carrier detection Reset Retransfer processing*1 Failure of 15 retransfer attempts or collision after 512-bit time Carrier non-detection Collision SFD transmission Error Collision*2 Error detection Error notification Error Data transmission Collision*2 Error [Legend] FDPX: Full Duplex CRC Normal transmission HDPX: Half Duplex transmission SFD: Start Frame Delimiter Notes: 1. Transmission retry processing includes both jam transmission that depends on collision detection and the adjustment of transmission intervals based on the back-off algorithm. 2. Transmission is retried only when data of 512 bits or less (including the preamble and SFD) is transmitted. When a collision is detected during the transmission of data greater than 512 bits, only jam is transmitted and transmission based on the back-off algorithm is not retried. Figure 11.2 EtherC Transmitter State Transitions 1. When the transmit enable (TE) bit is set, the transmitter enters the transmit idle state. 2. When a transmit request is issued by the transmit E-DMAC, the EtherC sends the preamble after a transmission delay equivalent to the frame interval time. If full-duplex transfer is selected, which does not require carrier detection, the preamble is sent as soon as a transmit request is issued by the E-DMAC. Rev. 5.00 Mar. 15, 2007 Page 254 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 3. The transmitter sends the SFD, data, and CRC sequentially. At the end of transmission, the transmit E-DMAC generates a transmission complete interrupt (TC). If a collision or the carrier-not-detected state occurs during data transmission, these are reported as interrupt sources. 4. After waiting for the frame interval time, the transmitter enters the idle state, and if there is more transmit data, continues transmitting. 11.4.2 Reception The EtherC receiver separates the frame data (MII into preamble, SFD, DA (destination address), SA (Source address), type/length, Data, and CRC data) and outputs DA, SA, type/length, Data to the E-DMAC. Figure 11.3 shows the state transitions of the EtherC receiver. Illegal carrier detection RX-DV negation Idle RE set Preamble detection Start of frame reception Wait for SFD reception SFD reception Destination address reception Own destination address or broadcast or multicast or promiscuous Data reception End of reception CRC reception Reception halted RE reset Promiscuous and other station destination address Reset Error notification* Error detection Receive error detection Receive error detection Normal reception [Legend] SFD: Start frame delimiter Note: * The error frame also transmits data to the buffer. Figure 11.3 EtherC Receiver State Transmissions Rev. 5.00 Mar. 15, 2007 Page 255 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 1. When the receive enable (RE) bit is set, the receiver enters the receive idle state. 2. When an SFD (start frame delimiter) is detected after a receive packet preamble, the receiver starts receive processing. Discards a frame with an invalid pattern. 3. In normal mode, if the destination address matches the receiver’s own address, or if broadcast or multicast transmission or promiscuous mode is specified, the receiver starts data reception. 4. Following data reception from the MII, the receiver carries out a CRC check. The result is indicated as a status bit in the descriptor after the frame data has been written to memory. Reports an error status in the case of an abnormality. 5. After one frame has been received, if the receive enable bit is set (RE = 1) in the EtherC mode register, the receiver prepares to receive the next frame. 11.4.3 MII Frame Timing Each MII Frame timing is shown in figure 11.4. TX-CLK TX-EN TXD3 to TXD0 TX-ER CRS COL Preamble SFD Data CRC Figure 11.4 (1) MII Frame Transmit Timing (Normal Transmission) TX-CLK TX-EN MII_TXD3 to MII_TXD0 TX-ER CRS COL Preamble JAM Figure 11.4 (2) MII Frame Transmit Timing (Collision) Rev. 5.00 Mar. 15, 2007 Page 256 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) TX-CLK TX-EN MII_TXD3 to MII_TXD0 TX-ER CRS COL Preamble SFD Data Figure 11.4 (3) MII Frame Transmit Timing (Transmit Error) RX-CLK RX-DV MII_RXD3 to MII_RXD0 RX-ER Preamble SFD Data CRC Figure 11.4 (4) MII Frame Receive Timing (Normal Reception) RX-CLK RX-DV MII_RXD3 to MII_RXD0 RX-ER Preamble SFD Data XXXX Figure 11.4 (5) MII Frame Receive Timing (Reception Error (1)) RX-CLK RX-DV MII_RXD3 to MII_RXD0 RX-ER XXXX 1110 XXXX Figure 11.4 (6) MII Fame Receive Timing (Reception Error (2)) Rev. 5.00 Mar. 15, 2007 Page 257 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.4.4 Accessing MII Registers MII registers in the PHY are accessed via this LSI’s PHY interface register (PIR). Connection is made as a serial interface in accordance with the MII frame format specified in IEEE802.3u. MII Management Frame Format: The format of an MII management frame is shown in figure 11.8. To access an MII register, a management frame is implemented by the program in accordance with the procedures shown in MII Register Access Procedure. Access Type Item Number of bits Read Write [Legend] PRE: ST: OP: PHYAD: PRE 32 1..1 1..1 ST 2 01 01 OP 2 10 01 MII Management Frame PHYAD 5 00001 00001 REGAD 5 RRRRR RRRRR TA 2 Z0 10 DATA 16 D..D D..D X IDLE 32 consecutive 1s Write of 01 indicating start of frame Write of code indicating access type Write of 0001 if the PHY address is 1 (sequential write starting with the MSB). This bit changes depending on the PHY address. REGAD: Write of 0001 if the register address is 1 (sequential write starting with the MSB). This bit changes depending on the PHY register address. TA: Time for switching data transmission source on MII interface (a) Write: 10 written (b) Read: Bus release (notation: Z0) performed DATA: 16-bit data. Sequential write or read from MSB (a) Write: 16-bit data write (b) Read: 16-bit data read IDLE: Wait time until next MII management format input (a) Write: Independent bus release (notation: X) performed (b) Read: Bus already released in TA; control unnecessary Figure 11.5 MII Management Frame Format Rev. 5.00 Mar. 15, 2007 Page 258 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) MII Register Access Procedure: The program accesses MII registers via the PHY interface register (PIR). Access is implemented by a combination of 1-bit-unit data write, 1-bit-unit data read, bus release, and independent bus release. Figure 11.9 shows the MII register access timing. The timing will differ depending on the PHY type. (1) Write to PHY interface register MMD = 1 MDO = write data MDC = 0 MDC MDO (2) Write to PHY interface register MMD = 1 MDO = write data MDC = 1 (1) (2) (3) 1-bit data write timing relationship (3) Write to PHY interface register MMD = 1 MDO = write data MDC = 0 Figure 11.6 (1) 1-Bit Data Write Flowchart Rev. 5.00 Mar. 15, 2007 Page 259 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) (1) Write to PHY interface register MMD = 0 MDC = 0 MDC MDO (2) Write to PHY interface register (1) (2) MMD = 0 MDC = 1 (3) Bus release timing relationship (3) Write to PHY interface register MMD = 0 MDC = 0 Figure 11.6 (2) Bus Release Flowchart (TA in Read in Figure 11.5) (1) Write to PHY interface register MMD = 0 MDC = 1 MDC MDI (2) Read from PHY interface register read MMD = 0 MMC = 1 MDI is read data (1) (2) (3) 1-bit data read timing relationship (3) Write to PHY interface register MMD = 0 MDC = 0 Figure 11.6 (3) 1-Bit Data Read Flowchart Rev. 5.00 Mar. 15, 2007 Page 260 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) (1) Write to PHY interface register MMD = 0 MDC = 0 MDC MDO (1) Independent bus release timing relationship Figure 11.6 (4) Independent Bus Release Flowchart (IDLE in Write in Figure 11.5) 11.4.5 Magic Packet Detection The EtherC has a Magic Packet detection function. This function provides a Wake-On-LAN (WOL) facility that activates various peripheral devices connected to a LAN from the host device or other source. This makes it possible to construct a system in which a peripheral device receives a Magic Packet sent from the host device or other source, and activates itself. When the Magic Packet is detected, data is stored in the FIFO of the E-DMAC by the broadcast packet that has received data previously and the EtherC is notified of the receiving status. To return to normal operation from the interrupt processing, initialize the EtherC and E-DMAC by using the SWR bit in the E-DMAC mode register (EDMR). With a Magic Packet, reception is performed regardless of the destination address. As a result, this function is valid, and the WOL pin enabled, only in the case of a match with the destination address specified by the format in the Magic Packet. Further information on Magic Packets can be found in the technical documentation published by AMD Corporation. The procedure for using the WOL function with this LSI is as follows. 1. Disable interrupt source output by means of the various interrupt enable/mask registers. 2. Set the Magic Packet detection enable bit (MPDE) in the EtherC mode register (ECMR). 3. Set the Magic Packet detection interrupt enable bit (MPDIP) in the EtherC interrupt enable register (ECSIPR) to the enable setting. 4. If necessary, set the CPU operating mode to sleep mode or set supporting functions to module standby mode. 5. When a Magic Packet is detected, an interrupt is sent to the CPU. The WOL pin notifies peripheral LSIs that the Magic Packet has been detected. Rev. 5.00 Mar. 15, 2007 Page 261 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.4.6 Operation by IPG Setting The EtherC has a function to change the non-transmission period IPG (Inter Packet Gap) between transmit frames. By changing the set values of the IPG setting register (IPGR), the transmission efficiency can be raised and lowered from the standard value. IPG settings are prescribed in IEEE802.3 standards. When changing settings, adequately check that the respective devices can operate smoothly on the same network. Case A (short IPG) [1] [2] [3] [4] [5] ...... Packet Case B (long IPG) IPG* [1] [2] [3] [4] ...... Note: * IPG may be longer than the set value, depending on the state of the circuit and the system bus. Figure 11.7 Changing IPG and Transmission Efficiency 11.4.7 Flow Control The EtherC supports flow control functions conforming to IEEE802.3x in full-duplex operations. Flow control can be applied to both receive and transmit operations. The methods for transmitting PAUSE frames when controlling flow are as follows: Automatic PAUSE Frame Transmission: For receive frames, PAUSE frames are automatically transmitted when the number of data in the receive FIFO (included in E-DMAC) reaches the value set in the flow control FIFO threshold register (FCFTR) of the E-DMAC. The TIME parameter included in the PAUSE frame at this time is set by the automatic PAUSE frame setting register (APR). The automatic PAUSE frame transmission is repeated until the number of data in the receive FIFO becomes less than the FCFTR setting as the receive data is read from the FIFO. The upper limit of the number of retransfers of the PAUSE frame can also be set by the automatic PAUSE frame retransfer count set register (TPAUSER). In this case, PAUSE frame transmission is repeated until the number of data becomes FCFTR value set or below, or the number of transmits reaches the value set by TPAUSER. The automatic PAUSE frame transmission is enabled when the TXF bit in the EtherC mode register (ECMR) is 1. Rev. 5.00 Mar. 15, 2007 Page 262 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) Manual PAUSE Frame Transmission: PAUSE frames are transmitted by directives from the software. When writing the Timer value to the manual PAUSE frame set register (MPR), manual PAUSE frame transmission is started. With this method, PAUSE frame transmission is carried out only once. PAUSE Frame Reception: The next frame is not transmitted until the time indicated by the Timer value elapses after receiving a PAUSE frame. However, the transmission of the current frame is continued. A received PAUSE frame is valid only when the RXF bit in the EtherC mode register (ECMR) is set to 1. 11.5 Connection to PHY-LSI Figure 11.8 shows the example of connection to a DP83846AVHG by National Semiconductor Corporation. MII (Media Independent Interface) DP83846AVHG TXER TXD3 TXD2 TXD1 TXD0 TXEN TXCLK MDC MDIO RXD3 RXD2 RXD1 RXD0 RXCLK CRS COL RXDV RXER This LSI TX-ER MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0 TX-EN TX-CLK MDC MDIO MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0 RX-CLK CRS COL RX-DV RX-ER Figure 11.8 Example of Connection to DP83846AVHG Rev. 5.00 Mar. 15, 2007 Page 263 of 794 REJ09B0237-0500 Section 11 Ethernet Controller (EtherC) 11.6 Usage Notes • Conditions for Setting LCHNG Bit Even if the level of the signal input to the LNKSTA pin is not changed, the LCHNG bit in ECSR may be set. It may happen when the pin function is changed from port to LNKSTA by PCCRH2 of the PFC or when a software reset caused by the SWR bit in EDMR is cleared while the LNKSTA pin is being driven high. This is because the LNKSTA signal is internally fixed low when the pin functions as a port or during the software reset state regardless of the external pin level. Clear the LCHNG bit before setting the LCHNGIP bit in ECSIPR not to request a LINK signal changed interrupt accidentally. • Flow Control Defect 1 Once a PAUSE frame is received while the receiving flow control is enabled in full-duplex mode (the RXF bit in ECMR = 1), each time when the local station receives a normal unicast frame (non-PAUSE frame without a CRC error), the TIME parameter specified by the PAUSE frame that has been previously received is incorrectly applied. As a result, unnecessary waiting time is generated to slow down the transmission throughput. The TIME parameter value is maintained until another PAUSE frame is received. This defect can be prevented if the destination station supports the function to transmit the 0 time PAUSE frame as the same as this LSI does. Enable the use of 0 time PAUSE frame in this LSI (the ZPF bit in ECMR = 1) before the 0 time PAUSE frame is received from the destination station. This clears the TIME parameter incorrectly maintained in the EtherC and prevents the unnecessary waiting time for transmission to be generated. • Flow Control Defect 2 When a PAUSE period is generated while the transmitting/receiving flow control is enabled in full-duplex mode (the TXF/RXF bit in ECMR = 1), non-PAUSE frames are waited for transmission (this is a normal operation) whereas PAUSE frames are incorrectly waited for transmission. The transmission of non-PAUSE frames in a PAUSE period is prohibited, though the transmission of PAUSE frames is enabled in IEEE802.3. When a PAUSE period is generated by the request from the destination station (that is, a PAUSE frame is received from the destination station), the load of the destination station is high and that of the local station is not so high. Therefore, the transmission of PAUSE frames during this period is less likely to happen. The ratio that this defect actually affects the operation in this LSI is rather low. Rev. 5.00 Mar. 15, 2007 Page 264 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) This LSI includes a direct memory access controller (E-DMAC) directly connected to the Ethernet controller (EtherC). A large proportion of buffer management is controlled by the E-DMAC itself using descriptors. This lightens the load on the CPU and enables efficient control of data transfer. Figure 12.1 shows the configuration of the E-DMAC, and the descriptors and transmit/receive buffers in memory. 12.1 Features The E-DMAC has the following features: • • • • The load on the CPU is reduced by means of a descriptor management system Transmit/receive frame status information is indicated in descriptors Achieves efficient system bus utilization through the use of block transfer (16-byte units) Supports single-frame/multi-buffer operation This LSI Internal bus Transmit buffer Transmit descriptor External bus interface E-DMAC Receive buffer Receive descriptor Internal bus interface Descriptor information Transmit DMAC Descriptor information Receive DMAC Transmit FIFO Receive FIFO EtherC External memory Figure 12.1 Configuration of E-DMAC, and Descriptors and Buffers Rev. 5.00 Mar. 15, 2007 Page 265 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2 Register Descriptions The E-DMAC has the following registers. For addresses and access sizes of these registers, see section 24, List of Registers. • • • • • • • • • • • • • • • • • • • E-DMAC mode register (EDMR) E-DMAC transmit request register (EDTRR) E-DMAC receive request register (EDRRR) Transmit descriptor list address register (TDLAR) Receive descriptor list address register (RDLAR) EtherC/E-DMAC status register (EESR) EtherC/E-DMAC status interrupt permission register (EESIPR) Transmit/receive status copy enable register (TRSCER) Receive missed-frame counter register (RMFCR) Transmit FIFO threshold register (TFTR) FIFO depth register (FDR) Receiving method control register (RMCR) E-DMAC operation control register (EDOCR) Receive buffer write address register (RBWAR) Receive descriptor fetch address register (RDFAR) Transmit buffer read address register (TBRAR) Transmit descriptor fetch address register (TDFAR) Flow control FIFO threshold register (FCFTR) Transmit interrupt register (TRIMD) Rev. 5.00 Mar. 15, 2007 Page 266 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2.1 E-DMAC Mode Register (EDMR) EDMR is a 32-bit readable/writable register that specifies the operating mode of the E-DMAC. The settings in this register are normally made in the initialization process following a reset. If the EtherC and E-DMAC are initialized by means of this register during data transmission, abnormal data may be sent onto the line. Operating mode settings must not be changed while the transmit and receive functions are enabled. To change the operating mode, the EtherC and E-DMAC modules are got into at their initial state by means of the software reset bit (SWR) in this register, then make new settings. It takes 64 cycles of the internal bus clock Bφ to initialize the EtherC and E-DMAC. Therefore, registers of the EtherC and E-DMAC should be accessed after 64 cycles of the internal bus clock Bφ has elapsed. Bit 31 to 7 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 6 DE 0 R/W E-DMAC Data Endian Convert Selects whether or not the endian format is converted on data transfer by the E-DMAC. However, the endian format of the descriptors and E-DMAC register values are not converted regardless of this bit setting. 0: Endian format not converted (big endian) 1: Endian format converted (little endian) 5 4 DL1 DL0 0 0 R/W R/W Descriptor Length These bits specify the descriptor length. 00: 16 bytes 01: 32 bytes 10: 64 bytes 11: Reserved (setting prohibited) 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 267 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 0 Bit Name SWR Initial value 0 R/W R/W Description Software Reset Writing 1 in this bit initializes registers of the E-DMAC other than TDLAR, RDLAR, and RMFCR and registers of the EtherC. While a software reset is being executed (64 cycles of the internal bus clock Bφ), accesses to the all Ethernet-related registers are prohibited. Software reset period (example): When Bφ = 62.5 MHz: 1.03 µS When Bφ = 33 MHz: 1.94 µS This bit is always read as 0. 0: Writing 0 is ignored (E-DMAC operation is not affected) 1: Writing 1 resets the EtherC and E-DMAC and then automatically cleared 12.2.2 E-DMAC Transmit Request Register (EDTRR) The EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC. When transmission of one frame is completed, the next descriptor is read. If the transmit descriptor active bit in this descriptor has the "active" setting, transmission is continued. If the transmit descriptor active bit has the "inactive" setting, the TR bit is cleared and operation of the transmit DMAC is halted. Bit 31 to 1 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 TR 0 R/W Transmit Request 0: Transmission-halted state. Writing 0 does not stop transmission. Termination of transmission is controlled by the active bit in the transmit descriptor 1: Start of transmission. The relevant descriptor is read and a frame is sent with the transmit active bit set to 1 Rev. 5.00 Mar. 15, 2007 Page 268 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2.3 E-DMAC Receive Request Register (EDRRR) EDRRR is a 32-bit readable/writable register that issues receive directives to the E-DMAC. When the receive request bit is set, the E-DMAC reads the relevant receive descriptor. If the receive descriptor active bit in the descriptor has the "active" setting, the E-DMAC prepares for a receive request from the EtherC. When one receive buffer of data has been received, the E-DMAC reads the next descriptor and prepares to receive the next frame. If the receive descriptor active bit in the descriptor has the "inactive" setting, the RR bit is cleared and operation of the receive DMAC is halted. Bit 31 to 1 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 RR 0 R/W Receive Request 0: The receive function is disabled* 1: A receive descriptor is read and the E-DMAC is ready to receive Note: * If the receive function is disabled during frame reception, write-back is not performed successfully to the receive descriptor. Following pointers to read a receive descriptor become abnormal and the E-DMAC cannot operate successfully. In this case, to make the E-DMAC reception enabled again, execute a software reset by the SWR bit in EDMR. To make the E-DMAC reception disabled without executing a software reset, set the RE bit in ECMR. Next, after the E_DMAC has completed the reception and write-back to the receive descriptor has been confirmed, disable the receive function of this register. Rev. 5.00 Mar. 15, 2007 Page 269 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2.4 Transmit Descriptor List Address Register (TDLAR) TDLAR is a 32-bit readable/writable register that specifies the start address of the transmit descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bit in EDMR. This register must not be written to during transmission. Modifications to this register should only be made while transmission is disabled by the TR bit (= 0) in the E-DMAC transmit request register (EDTRR). Bit 31 to 0 Bit Name TDLA31 to TDLA0 Initial value All 0 R/W R/W Description Transmit Descriptor Start Address The lower bits are set as follows according to the specified descriptor length. 16-byte boundary: TDLA3 to TDLA0 = 0000 32-byte boundary: TDLA4 to TDLA0 = 00000 64-byte boundary: TDLA5 to TDLA0 = 000000 12.2.5 Receive Descriptor List Address Register (RDLAR) RDLAR is a 32-bit readable/writable register that specifies the start address of the receive descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bit in EDMR. This register must not be written to during reception. Modifications to this register should only be made while reception is disabled by the RR bit (= 0) in the E-DMAC Receive Request Register (EDRRR). Bit 31 to 0 Bit Name RDLA31 to RDLA0 Initial value All 0 R/W R/W Description Receive Descriptor Start Address The lower bits are set as follows according to the specified descriptor length. 16-byte boundary: RDLA3 to RDLA0 = 0000 32-byte boundary: RDLA4 to RDLA0 = 00000 64-byte boundary: RDLA5 to RDLA0 = 000000 Rev. 5.00 Mar. 15, 2007 Page 270 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2.6 EtherC/E-DMAC Status Register (EESR) EESR is a 32-bit readable/writable register that shows communications status information on the E-DMAC in combination with the EtherC. The information in this register is reported in the form of interrupts. Individual bits are cleared by writing 1 (however, bit 22 (ECI) is a read-only bit and not to be cleared by writing 1) and are not affected by writing 0. Each interrupt source can also be masked by means of the corresponding bit in the EtherC/E-DMAC status interrupt permission register (EESIPR). The interrupts generated by this register are EINT0. For interrupt priority, see section 6.5, Interrupt Exception Handling Vector Table. Bit 31 Bit Name  Initial value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 30 TWB 0 R/W Write-Back Complete Indicates that write-back from the E-DMAC to the corresponding descriptor has completed. This operation is enabled when the TIS bit in TRIMD is set to 1. 0: Write-back has not completed, or no transmission directive 1: Write-back has completed 29 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 TABT 0 R/W Transmit Abort Detection Indicates that frame transmission by the EtherC has been aborted because of an error during transmission. 0: Frame transmission has not been aborted or no transmit directive 1: Frame transmit has been aborted Rev. 5.00 Mar. 15, 2007 Page 271 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 25 Bit Name RABT Initial value 0 R/W R/W Description Receive Abort Detection Indicates that frame reception by the EtherC has been aborted because of an error during reception. 0: Frame reception has not been aborted or no receive directive 1: Frame receive has been aborted 24 RFCOF 0 R/W Receive Frame Counter Overflow Indicates that the receive FIFO frame counter has overflowed. 0: Receive frame counter has not overflowed 1: Receive frame counter overflows 23 ADE 0 R/W Address Error Indicates that the memory address that the E-DMAC tried to transfer is found illegal. 0: Illegal memory address not detected (normal operation) 1: Illegal memory address detected Note: When an address error is detected, the E-DMAC halts transmitting/receiving. To resume the operation, set the E-DMAC again after software reset by means of the SWR bit in EDMR. 22 ECI 0 R EtherC Status Register Interrupt Source This bit is a read-only bit. When the source of an ECSR interrupt in the EtherC is cleared, this bit is also cleared. 0: EtherC status interrupt source has not been detected 1: EtherC status interrupt source has been detected Rev. 5.00 Mar. 15, 2007 Page 272 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 21 Bit Name TC Initial value 0 R/W R/W Description Frame Transmit Complete Indicates that all the data specified by the transmit descriptor has been transmitted to the EtherC. The transfer status is written back to the relevant descriptor. When 1-frame transmission is completed for 1-frame/1-buffer processing, or when the last data in the frame is transmitted and the transmission descriptor valid bit (TACT) in the next descriptor is not set for multiple-frame buffer processing, transmission is completed and this bit is set to 1. After frame transmission, the E-DMAC writes the transmission status back to the descriptor. 0: Transfer not complete, or no transfer directive 1: Transfer complete 20 TDE 0 R/W Transmit Descriptor Empty Indicates that the transmission descriptor valid bit (TACT) in the descriptor is not set when the E-DMAC reads the transmission descriptor when the previous descriptor is not the last one of the frame for multiplebuffer frame processing. As a result, an incomplete frame may be transmitted. 0: Transmit descriptor active bit TACT = 1 detected 1: Transmit descriptor active bit TACT = 0 detected When transmission descriptor empty (TDE = 1) occurs, execute a software reset and initiate transmission. In this case, the address that is stored in the transmit descriptor list address register (TDLAR) is transmitted first. 19 TFUF 0 R/W Transmit FIFO Underflow Indicates that underflow has occurred in the transmit FIFO during frame transmission. Incomplete data is sent onto the line. 0: Underflow has not occurred 1: Underflow has occurred Rev. 5.00 Mar. 15, 2007 Page 273 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 18 Bit Name FR Initial value 0 R/W R/W Description Frame Reception Indicates that a frame has been received and the receive descriptor has been updated. This bit is set to 1 each time a frame is received. 0: Frame not received 1: Frame received 17 RDE 0 R/W Receive Descriptor Empty When receive descriptor empty (RDE = 1) occurs, receiving can be restarted by setting RACT = 1 in the receive descriptor and initiating receiving. 0: Receive descriptor active bit RACT = 1 not detected 1: Receive descriptor active bit RACT = 0 detected 16 RFOF 0 R/W Receive FIFO Overflow Indicates that the receive FIFO has overflowed during frame reception. 0: Overflow has not occurred 1: Overflow has occurred 15 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 CND 0 R/W Carrier Not Detect Indicates the carrier detection status. 0: A carrier is detected when transmission starts 1: A carrier is not detected when transmission starts 10 DLC 0 R/W Detect Loss of Carrier Indicates that loss of the carrier has been detected during frame transmission. 0: Loss of carrier not detected 1: Loss of carrier detected 9 CD 0 R/W Delayed Collision Detect Indicates that a delayed collision has been detected during frame transmission. 0: Delayed collision not detected 1: Delayed collision detected Rev. 5.00 Mar. 15, 2007 Page 274 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 8 Bit Name TRO Initial value 0 R/W R/W Description Transmit Retry Over Indicates that a retry-over condition has occurred during frame transmission. Total 16 transmission retries including 15 retries based on the back-off algorithm are failed after the EtherC transmission starts. 0: Transmit retry-over condition not detected 1: Transmit retry-over condition detected 7 RMAF 0 R/W Receive Multicast Address Frame 0: Multicast address frame has not been received 1: Multicast address frame has been received 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 RRF 0 R/W Receive Residual-Bit Frame 0: Residual-bit frame has not been received 1: Residual-bit frame has been received 3 RTLF 0 R/W Receive Too-Long Frame Indicates that the frame more than the number of receive frame length upper limit set by RFLR of the EtherC has been received. 0: Too-long frame has not been received 1: Too-long frame has been received 2 RTSF 0 R/W Receive Too-Short Frame Indicates that a frame of fewer than 64 bytes has been received. 0: Too-short frame has not been received 1: Too-short frame has been received 1 PRE 0 R/W PHY Receive Error 0: PHY receive error not detected 1: PHY receive error detected 0 CERF 0 R/W CRC Error on Received Frame 0: CRC error not detected 1: CRC error detected Rev. 5.00 Mar. 15, 2007 Page 275 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR) EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual bits in the EtherC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the corresponding bit. In the initial state, interrupts are not enabled. Bit 31 Bit Name  Initial value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 30 TWBIP 0 R/W Write-Back Complete Interrupt Permission 0: Write-back complete interrupt is disabled 1: Write-back complete interrupt is enabled 29 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 TABTIP 0 R/W Transmit Abort Detection Interrupt Permission 0: Transmit abort detection interrupt is disabled 1: Transmit abort detection interrupt is enabled 25 RABTIP 0 R/W Receive Abort Detection Interrupt Permission 0: Receive abort detection interrupt is disabled 1: Receive abort detection interrupt is enabled 24 RFCOFIP 0 R/W Receive Frame Counter Overflow Interrupt Permission 0: Receive frame counter overflow interrupt is disabled 1: Receive frame counter overflow interrupt is enabled 23 ADEIP 0 R/W Address Error Interrupt Permission 0: Address error interrupt is disabled 1: Address error interrupt is enabled 22 ECIIP 0 R/W EtherC Status Register Interrupt Permission 0: EtherC status interrupt is disabled 1: EtherC status interrupt is enabled 21 TCIP 0 R/W Frame Transmit Complete Interrupt Permission 0: Frame transmit complete interrupt is disabled 1: Frame transmit complete interrupt is enabled Rev. 5.00 Mar. 15, 2007 Page 276 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 20 Bit Name TDEIP Initial value 0 R/W R/W Description Transmit Descriptor Empty Interrupt Permission 0: Transmit descriptor empty interrupt is disabled 1: Transmit descriptor empty interrupt is enabled 19 TFUFIP 0 R/W Transmit FIFO Underflow Interrupt Permission 0: Underflow interrupt is disabled 1: Underflow interrupt is enabled 18 FRIP 0 R/W Frame Received Interrupt Permission 0: Frame received interrupt is disabled 1: Frame received interrupt is enabled 17 RDEIP 0 R/W Receive Descriptor Empty Interrupt Permission 0: Receive descriptor empty interrupt is disabled 1: Receive descriptor empty interrupt is enabled 16 RFOFIP 0 R/W Receive FIFO Overflow Interrupt Permission 0: Receive FIFO overflow interrupt is disabled 1: Receive FIFO overflow interrupt is enabled 15 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 CNDIP 0 R/W Carrier Not Detect Interrupt Permission 0: Carrier not detect interrupt is disabled 1: Carrier not detect interrupt is enabled 10 DLCIP 0 R/W Detect Loss of Carrier Interrupt Permission 0: Detect loss of carrier interrupt is disabled 1: Detect loss of carrier interrupt is enabled 9 CDIP 0 R/W Delayed Collision Detect Interrupt Permission 0: Delayed collision detect interrupt is disabled 1: Delayed collision detect interrupt is enabled 8 TROIP 0 R/W Transmit Retry Over Interrupt Permission 0: Transmit retry over interrupt is disabled 1: Transmit retry over interrupt is enabled Rev. 5.00 Mar. 15, 2007 Page 277 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 7 Bit Name RMAFIP Initial value 0 R/W R/W Description Receive Multicast Address Frame Interrupt Permission 0: Receive multicast address frame interrupt is disabled 1: Receive multicast address frame interrupt is enabled 6, 5  All 0 R Reserved This bit is always read as 0. The write value should always be 0. 4 RRFIP 0 R/W Receive Residual-Bit Frame Interrupt Permission 0: Receive residual-bit frame interrupt is disabled 1: Receive residual-bit frame interrupt is enabled 3 RTLFIP 0 R/W Receive Too-Long Frame Interrupt Permission 0: Receive too-long frame interrupt is disabled 1: Receive too-long frame interrupt is enabled 2 RTSFIP 0 R/W Receive Too-Short Frame Interrupt Permission 0: Receive too-short frame interrupt is disabled 1: Receive too-short frame interrupt is enabled 1 PREIP 0 R/W PHY-LSI Receive Error Interrupt Permission 0: PHY-LSI receive error interrupt is disabled 1: PHY-LSI receive error interrupt is enabled 0 CERFIP 0 R/W CRC Error on Received Frame 0: CRC error on received frame interrupt is disabled 1: CRC error on received frame interrupt is enabled Rev. 5.00 Mar. 15, 2007 Page 278 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2.8 Transmit/Receive Status Copy Enable Register (TRSCER) TRSCER specifies whether or not transmit and receive status information reported by bits in the EtherC/E-DMAC status register is to be indicated in bits TFS26 to TFS0 and RFS26 to RFS0 in the corresponding descriptor. Bits in this register correspond to bits 11 to 0 in the EtherC/EDMAC status register (EESR). When a bit is cleared to 0, the transmit status (bits 11 to 8 in EESR) is indicated in bits TFS3 to TFS0 in the transmit descriptor, and the receive status (bits 7 to 0 in EESR) is indicated in bits RFS7 to RFS0 of the receive descriptor. When a bit is set to 1, the occurrence of the corresponding interrupt is not indicated in the descriptor. After this LSI is reset, all bits are cleared to 0. Bit 31 to 12 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 CNDCE 0 R/W CND Bit Copy Directive 0: Indicates the CND bit state in bit TFS3 in the transmit descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit TFS3 of the transmit descriptor 10 DLCCE 0 R/W DLC Bit Copy Directive 0: Indicates the DLC bit state in bit TFS2 of the transmit descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit TFS2 of the transmit descriptor 9 CDCE 0 R/W CD Bit Copy Directive 0: Indicates the CD bit state in bit TFS1 of the transmit descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit TFS1 of the transmit descriptor 8 TROCE 0 R/W TRO Bit Copy Directive 0: Indicates the TRO bit state in bit TFS0 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit TFS0 of the receive descriptor Rev. 5.00 Mar. 15, 2007 Page 279 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 7 Bit Name RMAFCE Initial value 0 R/W R/W Description RMAF Bit Copy Directive 0: Indicates the RMAF bit state in bit RFS7 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFS7 of the receive descriptor 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 RRFCE 0 R/W RRF Bit Copy Directive 0: Indicates the RRF bit state in bit RFS4 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFS4 of the receive descriptor 3 RTLFCE 0 R/W RTLF Bit Copy Directive 0: Indicates the RTLF bit state in bit RFS3 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFS3 of the receive descriptor 2 RTSFCE 0 R/W RTSF Bit Copy Directive 0: Indicates the RTSF bit state in bit RFS2 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFS2 of the receive descriptor 1 PRECE 0 R/W PRE Bit Copy Directive 0: Indicates the PRF bit state in bit RFS1 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFS1 of the receive descriptor 0 CERFCE 0 R/W CERF Bit Copy Directive 0: Indicates the CERF bit state in bit RFS0 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFS0 of the receive descriptor Rev. 5.00 Mar. 15, 2007 Page 280 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2.9 Receive Missed-Frame Counter Register (RMFCR) RMFCR is a 16-bit counter that indicates the number of frames missed (discarded, and not transferred to the receive buffer) during reception. When the receive FIFO overflows, the receive frames in the FIFO are discarded. The number of frames discarded at this time is counted. When the value in this register reaches H'FFFF, counting-up is halted. When this register is read, the counter value is cleared to 0. Write operations to this register have no effect. Bit 31 to 16 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 MFC15 to MFC0 All 0 R Missed-Frame Counter Indicate the number of frames that are discarded and not transferred to the receive buffer during reception. Rev. 5.00 Mar. 15, 2007 Page 281 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2.10 Transmit FIFO Threshold Register (TFTR) TFTR is a 32-bit readable/writable register that specifies the transmit FIFO threshold at which the first transmission is started. The actual threshold is 4 times the set value. The EtherC starts transmission when the amount of data in the transmit FIFO exceeds the number of bytes specified by this register, when the transmit FIFO is full, or when 1-frame write is executed. When setting this register, do so in the transmission-halt state. Bit 31 to 11 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 TFT10 to TFT0 All 0 R/W Transmit FIFO threshold When setting a transmit FIFO, the FIFO must be set to a smaller value than the specified value of the FIFO capacity by FDR. H'00: Store and forward modes H'01 to H'0C: Setting prohibited H'0D: 52 bytes H'0E: 56 bytes : : H'1F: 124 bytes H'20: 128 bytes : : H'3F: 252 bytes H'40: 256 bytes : : H'7F: 508 bytes H'80: 512 bytes H'81 to H'200: Setting prohibited Note: When starting transmission before one frame of data write has completed, take care the generation of the underflow. Rev. 5.00 Mar. 15, 2007 Page 282 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2.11 FIFO Depth Register (FDR) FDR is a 32-bit readable/writable register that specifies the depth of the transmit and receive FIFOs. Bit 31 to 11 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 TFD2 to TFD0 B'001 R/W Transmit FIFO Depth These bits specify the depth of the transmit FIFO. After the start of the transmission and reception, the setting cannot be changed. 000: 256 bytes 001: 512 bytes Other than above: Setting prohibited 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 RFD2 to RFD0 B'001 R/W Receive FIFO Depth These bits specify the depth of the receive FIFO. After the start of the transmission and reception, the setting cannot be changed. 000: 256 bytes 001: 512 bytes Other than above: Setting prohibited Rev. 5.00 Mar. 15, 2007 Page 283 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2.12 Receiving Method Control Register (RMCR) RMCR is a 32-bit readable/writable register that specifies the control method for the RR bit in EDRRR when a frame is received. This register must be set during the receiving-halt state. Bit 31 to 1 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 RNC 0 R/W Receive Enable Control 0: When reception of one frame is completed, the EDMAC writes the receive status into the descriptor and clears the RR bit in EDRRR 1: When reception of one frame is completed, the EDMAC writes the receive status into the descriptor, reads the next descriptor, and prepares to receive the next frame Rev. 5.00 Mar. 15, 2007 Page 284 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2.13 E-DMAC Operation Control Register (EDOCR) EDOCR is a 32-bit readable/writable register that specifies the control methods used in E-DMAC operation. Bit 31 to 4 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 FEC 0 R/W FIFO Error Control Specifies E-DMAC operation when transmit FIFO underflow or receive FIFO overflow occurs. 0: E-DMAC operation continues when underflow or overflow occurs 1: E-DMAC operation halts when underflow or overflow occurs 2 AEC 0 R/W Address Error Control Indicates detection of an illegal memory address in an attempted E-DMAC transfer. 0: Illegal memory address not detected (normal operation) 1: E-DMAC stops its operation due to illegal memory address detection Note: To resume the operation, set the E-DMAC again after software reset by means of the SWR bit in EDMR. 1 EDH 0 R/W E-DMAC Halted 0: The E-DMAC is operating normally 1: The E-DMAC has been halted by NMI pin assertion. E-DMAC operation is restarted by writing 0 0  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 285 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2.14 Receiving-Buffer Write Address Register (RBWAR) RBWAR stores the address of data to be written in the receiving buffer when the E-DMAC writes data to the receiving buffer. Which addresses in the receiving buffer are processed by the EDMAC can be recognized by monitoring addresses displayed in this register. The address that the E-DMAC is actually processing may be different from the value read from this register. Bit 31 to 0 Bit Name RBWA31 to RBWA0 Initial value All 0 R/W R Description Receiving-Buffer Write Address These bits can only be read. Writing is prohibited. 12.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) RDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor information from the receiving descriptor. Which receiving descriptor information is used for processing by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually fetching a descriptor may be different from the value read from this register. Bit 31 to 0 Bit Name RDFA31 to RDFA0 Initial value All 0 R/W R Description Receiving-Descriptor Fetch Address These bits can only be read. Writing is prohibited. 12.2.16 Transmission-Buffer Read Address Register (TBRAR) TBRAR stores the address of the transmission buffer when the E-DMAC reads data from the transmission buffer. Which addresses in the transmission buffer are processed by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually reading in the buffer may be different from the value read from this register. Bit 31 to 0 Bit Name TBRA31 to TBRA0 Initial value All 0 R/W R Description Transmission-Buffer Read Address These bits can only be read. Writing is prohibited. Rev. 5.00 Mar. 15, 2007 Page 286 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.2.17 Transmission-Descriptor Fetch Address Register (TDFAR) TDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor information from the transmission descriptor. Which transmission descriptor information is used for processing by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually fetching a descriptor may be different from the value read from this register. Bit 31 to 0 Bit Name TDFA31 to TDFA0 Initial value All 0 R/W R Description Transmission-Descriptor Fetch Address These bits can only be read. Writing is prohibited. 12.2.18 Flow Control FIFO Threshold Register (FCFTR) FCFTR is a 32-bit readable/writable register that sets the flow control of the EtherC (setting the threshold on automatic PAUSE transmission). The threshold can be specified by the depth of the receive FIFO data (RFD2 to RFD0) and the number of receive frames (RFF2 to RFF0). The condition to start the flow control is decided by taking OR operation on the two thresholds. Therefore, the flow control by the two thresholds is independently started. When flow control is performed according to the RFD bits setting, if the setting is the same as the depth of the receive FIFO specified by the FIFO depth register (FDR), flow control is started when the remaining FIFO is (FIFO data − 64) bytes. For instance, when RFD in FDR = 1 and RFD in FCFTR = 1, flow control is started when (512 − 64) bytes of data is stored in the receive FIFO. The value set in the RFD bits in this register should be equal to or less than those in FDR. Bit 31 to 19 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 287 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 18 17 16 Bit Name RFF2 RFF1 RFF0 Initial value 1 1 1 R/W R/W R/W R/W Description Receive Frame Number Flow Control Threshold 000: When one receive frame has been stored in the receive FIFO 001: When two receive frames have been stored in the receive FIFO : : 110: When seven receive frames have been stored in the receive FIFO 111: When eight receive frames have been stored in the receive FIFO 15 to 3  All 0  Reserved These bits are always read as 0. The write value should always be 0. 2 1 0 RFD2 RFD1 RFD0 0 0 0 R/W R/W R/W Receive Byte Flow Control Threshold 000: When (256 − 64) bytes of data is stored in the receive FIFO 001: When (512 − 64) bytes of data is stored in the receive FIFO Other than above: Setting prohibited 12.2.19 Transmit Interrupt Register (TRIMD) TRIMD is a 32-bit readable/writable register that specifies whether or not to notify write-back completion for each frame using the TWB bit in EESR and an interrupt on transmit operations. Bit 31 to 1 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 TIS 0 R/W Transmit Interrupt Setting 0: Write-back completion for each frame is not notified 1: Write-backed completion for each frame using the TWB bit in EESR is notified Rev. 5.00 Mar. 15, 2007 Page 288 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.3 Operation The E-DMAC is connected to the EtherC, and performs efficient transfer of transmit/receive data between the EtherC and memory (buffers) without the intervention of the CPU. The E-DMAC itself reads control information, including buffer pointers called descriptors, relating to the buffers. The E-DMAC reads transmit data from the transmit buffer and writes receive data to the receive buffer in accordance with this control information. By setting up a number of consecutive descriptors (a descriptor list), it is possible to execute transmission and reception continuously. 12.3.1 Descriptor List and Data Buffers Before starting transmission/reception, the communication program creates transmit and receive descriptor lists in memory. The start addresses of these lists are then set in the transmit and receive descriptor list start address registers. The descriptor start address must be aligned so that it matches the address boundary according to the descriptor length set by the E-DMAC mode register (EDMR). The transmit buffer start address can be aligned with a byte, a word, and a longword boundary. (1) Transmit Descriptor Figure 12.2 shows the relationship between a transmit descriptor and the transmit buffer. According to the specification in this descriptor, the relationship between the transmit frame and transmit buffer can be defined as one frame/one buffer or one frame/multi-buffer. Rev. 5.00 Mar. 15, 2007 Page 289 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Transmit descriptor 31 30 29 28 27 26 TTTTT ADFFF CLPPE TE10 31 TD1 31 TD2 TBA Padding (4 bytes) TDL 0 0 TFS26 to TFS0 Transmit buffer TD0 16 Valid transmit data Figure 12.2 Relationship between Transmit Descriptor and Transmit Buffer Rev. 5.00 Mar. 15, 2007 Page 290 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) (a) Transmit Descriptor 0 (TD0) TD0 indicates the transmit frame status. The CPU and E-DMAC use TD0 to report the frame transmission status. Bit 31 Bit Name TACT Initial value 0 R/W R/W Description Transmit Descriptor Active Indicates that this descriptor is active. The CPU sets this bit after transmit data has been transferred to the transmit buffer. The E-DMAC resets this bit on completion of a frame transfer or when transmission is suspended. 0: The transmit descriptor is invalid. Indicates that valid data has not been written to this bit by the CPU, or this bit has been reset by a writeback operation on termination of E-DMAC frame transfer processing (completion or suspension of transmission) If this state is recognized in an E-DMAC descriptor read, the E-DMAC terminates transmit processing and transmit operations cannot be continued (a restart is necessary) 1: The transmit descriptor is valid. Indicates that valid data has been written to the transmit buffer by the CPU and frame transfer processing has not yet been executed, or that frame transfer is in progress When this state is recognized in an E-DMAC descriptor read, the E-DMAC continues with the transmit operation 30 TDLE 0 R/W Transmit Descriptor List End After completion of the corresponding buffer transfer, the E-DMAC references the first descriptor. This specification is used to set a ring configuration for the transmit descriptors. 0: This is not the last transmit descriptor list 1: This is the last transmit descriptor list Rev. 5.00 Mar. 15, 2007 Page 291 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 29 28 Bit Name TFP1 TFP0 Initial value 0 0 R/W R/W R/W Description Transmit Frame Position 1, 0 These two bits specify the relationship between the transmit buffer and transmit frame. In the preceding and following descriptors, a logically positive relationship must be maintained between the settings of this bit and the TDLE bit. 00: Frame transmission for transmit buffer indicated by this descriptor continues (frame is not concluded) 01: Transmit buffer indicated by this descriptor contains end of frame (frame is concluded) 10: Transmit buffer indicated by this descriptor is start of frame (frame is not concluded) 11: Contents of transmit buffer indicated by this descriptor are equivalent to one frame (one frame/one buffer) 27 TFE 0 R/W Transmit Frame Error Indicates that one or other bit of the transmit frame status indicated by bits 26 to 0 is set. Whether or not the transmit frame status information is copied into this bit is specified by the transmit/receive status copy enable register. 0: No error during transmission 1: An error occurred during transmission 26 to 0 TFS26 to TFS0 All 0 R/W Transmit Frame Status TFS26 to TFS4: Reserved (The write value should always be 0.) TFS3: Carrier Not Detect (corresponds to CND bit in EESR) TFS2: Detect Loss of Carrier (corresponds to DLC bit in EESR) TFS1: Delayed Collision Detect (corresponds to CD bit in EESR) TFS0: Transmit Retry Over (corresponds to TRO bit in EESR) Rev. 5.00 Mar. 15, 2007 Page 292 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) (b) Transmit Descriptor 1 (TD1) TD1 specifies the transmit buffer length (maximum 64 kbytes). Bit 31 to 16 Bit Name TDL Initial value All 0 R/W R/W Description Transmit Buffer Data Length These bits specify the valid transfer byte length in the corresponding transmit buffer. When the one frame/multi-buffer system is specified (TD0 and TFP = 10 or 00), the transfer byte length specified in the descriptors at the start and midway can be set in byte units. 15 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. (c) Transmit Descriptor 2 (TD2) TD2 specifies the 32-bit transmit buffer start address. The transmit buffer start address setting can be aligned with a byte, a word, or a longword boundary. Rev. 5.00 Mar. 15, 2007 Page 293 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) (2) Receive Descriptor Figure 12.3 shows the relationship between a receive descriptor and the receive buffer. In frame reception, the E-DMAC performs data rewriting up to a receive buffer 16-byte boundary, regardless of the receive frame length. Finally, the actual receive frame length is reported in the lower 16 bits of RD1 in the descriptor. Data transfer to the receive buffer is performed automatically by the E-DMAC to give a one frame/one buffer or one frame/multi-buffer configuration according to the size of one received frame. Receive descriptor 31 30 29 28 27 26 RRRRR ADF FF CLPPE TE1 0 RBL 31 31 16 RBA Padding (4 bytes) 0 RFS26 to RFS0 Valid receive data Receive buffer RD0 15 RDL 0 0 RD1 RD2 Figure 12.3 Relationship between Receive Descriptor and Receive Buffer Rev. 5.00 Mar. 15, 2007 Page 294 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) (a) Receive Descriptor 0 (RD0) RD0 indicates the receive frame status. The CPU and E-DMAC use RD0 to report the frame receive status. Bit 31 Bit Name RACT Initial value 0 R/W R/W Description Receive Descriptor Active Indicates that this descriptor is active. The E-DMAC resets this bit after receive data has been transferred to the receive buffer. On completion of receive frame processing, the CPU sets this bit to prepare for reception. 0: The receive descriptor is invalid. Indicates that the receive buffer is not ready (access disabled by E-DMAC), or this bit has been reset by a write-back operation on termination of EDMAC frame transfer processing (completion or suspension of reception). If this state is recognized in an E-DMAC descriptor read, the E-DMAC terminates receive processing and receive operations cannot be continued. Reception can be restarted by setting RACT to 1 and executing receive initiation. 1: The receive descriptor is valid Indicates that the receive buffer is ready (access enabled) and processing for frame transfer from the FIFO has not been executed, or that frame transfer is in progress. When this state is recognized in an E-DMAC descriptor read, the E-DMAC continues with the receive operation. 30 RDLE 0 R/W Receive Descriptor List Last After completion of the corresponding buffer transfer, the E-DMAC references the first receive descriptor. This specification is used to set a ring configuration for the receive descriptors. 0: This is not the last receive descriptor list 1: This is the last receive descriptor list Rev. 5.00 Mar. 15, 2007 Page 295 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 29 28 Bit Name RFP1 RFP0 Initial value 0 0 R/W R/W R/W Description Receive Frame Position These two bits specify the relationship between the receive buffer and receive frame. 00: Frame reception for receive buffer indicated by this descriptor continues (frame is not concluded) 01: Receive buffer indicated by this descriptor contains end of frame (frame is concluded) 10: Receive buffer indicated by this descriptor is start of frame (frame is not concluded) 11: Contents of receive buffer indicated by this descriptor are equivalent to one frame (one frame/one buffer) 27 RFE 0 R/W Receive Frame Error Indicates that one or other bit of the receive frame status indicated by bits 26 to 0 is set. Whether or not the receive frame status information is copied into this bit is specified by the transmit/receive status copy enable register. 0: No error during reception 1: A certain kind of error occurred during reception Rev. 5.00 Mar. 15, 2007 Page 296 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 26 to 0 Bit Name RFS26 to RFS0 Initial value All 0 R/W R/W Description Receive Frame Status These bits indicate the error status during frame reception. RFS26 to RFS10: Reserved (The write value should always be 0.) RFS9: Receive FIFO overflow (corresponds to RFOF bit in EESR) RFS8: Reserved (The write value should always be 0.) RFS7: Multicast address frame received (corresponds to RMAF bit in EESR) RFS6: CAM entry unregistered frame received (corresponds to the RUAF bit in EESR) RSF5: Reserved (The write value should always be 0.) RFS4: Receive residual-bit frame error (corresponds to RRF bit in EESR) RFS3: Receive too-long frame error (corresponds to RTLF bit in EESR) RFS2: Receive too-short frame error (corresponds to RTSF bit in EESR) RFS1: PHY-LSI receive error (corresponds to PRE bit in EESR) RFS0: CRC error on received frame (corresponds to CERF bit in EESR) Rev. 5.00 Mar. 15, 2007 Page 297 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) (b) Receive Descriptor 1 (RD1) RD1 specifies the receive buffer length (maximum 64 kbytes). Bit 31 to 16 Bit Name RBL Initial value All 0 R/W R/W Description Receive Buffer Length These bits specify the maximum reception byte length in the corresponding receive buffer. The transfer byte length must align with a 16-byte boundary (bits 19 to 16 cleared to 0). The maximum receive frame length with one frame per buffer is 1,514 bytes, excluding the CRC data. Therefore, for the receive buffer length specification, a value of 1,520 bytes (H'05F0) that takes account of a 16-byte boundary is set as the maximum receive frame length. 15 to 0 RDL All 0 R/W Receive Data Length These bits specify the data length of a receive frame stored in the receive buffer. The receive data transferred to the receive buffer does not include the 4-byte CRC data at the end of the frame. The receive frame length is reported as the number of words (valid data bytes) not including this CRC data. (c) Receive Descriptor 2 (RD2) RD2 specifies the 32-bit receive buffer start address. The receive buffer start address must be aligned with a longword boundary. However, when SDRAM is connected, it must be aligned with a 16-byte boundary. 12.3.2 Transmission When the transmit function is enabled and the transmit request bit (TR) is set in the E-DMAC transmit request register (EDTRR), the E-DMAC reads the descriptor used last time from the transmit descriptor list (in the initial state, the descriptor indicated by the transmission descriptor start address register (TDLAR)). If the setting of the TACT bit in the read descriptor is active, the E-DMAC reads transmit frame data sequentially from the transmit buffer start address specified by TD2, and transfers it to the EtherC. The EtherC creates a transmit frame and starts transmission to the MII. After DMA transfer of data equivalent to the buffer length specified in the descriptor, the following processing is carried out according to the TFP value. Rev. 5.00 Mar. 15, 2007 Page 298 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 1. TFP = 00 or 01 (frame continuation): Descriptor write-back is performed after DMA transfer. 2. TFP = 01 or 11 (frame end): Descriptor write-back is performed after completion of frame transmission. The E-DMAC continues reading descriptors and transmitting frames as long as the setting of the TACT bit in the read descriptors is "active." When a descriptor with an "inactive" TACT bit is read, the E-DMAC resets the transmit request bit (TR) in the transmit register and ends transmit processing (EDTRR). Transmission flowchart This LSI + memory E-DMAC Transmit FIFO EtherC PHY EtherC/E-DMAC initialization Descriptor and transmit buffer setting Transmit directive Descriptor read Transmit data transfer Descriptor write-back Descriptor read Transmit data transfer Frame transmission Descriptor write-back Transmission completed Figure 12.4 Sample Transmission Flowchart Rev. 5.00 Mar. 15, 2007 Page 299 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.3.3 Reception When the receive function is enabled and the CPU sets the receive request bit (RR) in the EDMAC receive request register (EDRRR), the E-DMAC reads the descriptor following the previously used one from the receive descriptor list (in the initial state, the descriptor indicated by the transmission descriptor start address register (TDLAR)), and then enters the receive-standby state. If the setting of the RACT bit is "active" and an own-address frame is received, the EDMAC transfers the frame to the receive buffer specified by RD2. If the data length of the received frame is greater than the buffer length given by RD1, the E-DMAC performs write-back to the descriptor when the buffer is full (RFP = 10 or 00), then reads the next descriptor. The EDMAC then continues to transfer data to the receive buffer specified by the new RD2. When frame reception is completed, or if frame reception is suspended because of a certain kind of error, the E-DMAC performs write-back to the relevant descriptor (RFP = 11 or 01), and then ends the receive processing. The E-DMAC then reads the next descriptor and enters the receive-standby state again. To receive frames continuously, the receive enable control bit (RNC) must be set to 1 in the receive control register (RCR). After initialization, this bit is cleared to 0. Rev. 5.00 Mar. 15, 2007 Page 300 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Reception flowchart This LSI + memory E-DMAC Receive FIFO EtherC PHY EtherC/E-DMAC initialization Descriptor and receive buffer setting Start of reception Descriptor read Frame reception Receive data transfer Descriptor write-back Descriptor read Receive data transfer Descriptor write-back Descriptor read (receive ready for the next frame) Reception completed Figure 12.5 Sample Reception Flowchart Rev. 5.00 Mar. 15, 2007 Page 301 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.3.4 Multi-Buffer Frame Transmit/Receive Processing Multi-Buffer Frame Transmit Processing If an error occurs during multi-buffer frame transmission, the processing shown in figure 12.6 is carried out by the E-DMAC. Where the transmit descriptor is shown as inactive (TACT bit = 0) in the figure, buffer data has already been transmitted normally, and where the transmit descriptor is shown as active (TACT bit = 1), buffer data has not been transmitted. If a frame transmit error occurs in the first descriptor part where the transmit descriptor is active (TACT bit = 1), transmission is halted, and the TACT bit cleared to 0, immediately. The next descriptor is then read, and the position within the transmit frame is determined on the basis of bits TFP1 and TFP0 (continuing [B'00] or end [B'01]). In the case of a continuing descriptor, the TACT bit is cleared to 0, only, and the next descriptor is read immediately. If the descriptor is the final descriptor, not only is the TACT bit cleared to 0, but write-back is also performed to the TFE and TFS bits at the same time. Data in the buffer is not transmitted between the occurrence of an error and write-back to the final descriptor. If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register (EESIPR), an interrupt is generated immediately after the final descriptor write-back. Descriptors T A C T T D L E T F P 1 T F P 0 00 00 00 Inactivates TACT (change 1 to 0) E-DMAC Descriptor read Inactivates TACT Descriptor read Inactivates TACT Descriptor read Inactivates TACT Descriptor read Inactivates TACT and writes TFE, TFS 10 10 10 10 10 11 10 00 00 00 00 00 00 01 10 Buffer Untransmitted data is not transmitted after error occurrence Descriptor is only processed. Transmit error occurrence One frame Transmitted data Untransmitted data Figure 12.6 E-DMAC Operation after Transmit Error Rev. 5.00 Mar. 15, 2007 Page 302 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Multi-Buffer Frame Receive Processing If an error occurs during multi-buffer frame reception, the processing shown in figure 12.7 is carried out by the E-DMAC. Where the receive descriptor is shown as inactive (RACT bit = 0) in the figure, buffer data has already been received normally, and where the receive descriptor is shown as active (RACT bit = 1), this indicates a buffer for which reception has not yet been performed. If a frame receive error occurs in the first descriptor part where the RACT bit = 1 in the figure, reception is halted immediately and a status write-back to the descriptor is performed. If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register (EESIPR), an interrupt is generated immediately after the write-back. If there is a new frame receive request, reception is continued from the buffer after that in which the error occurred. Descriptors R A C T 0 0 0 Inactivates RACT and writes RFE, RFS E-DMAC 1 Descriptor read Write-back 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Buffer New frame reception continues from buffer 0 0 1 R D L E 0 0 0 R F P 1 1 0 0 R F P 0 0 0 0 Receive error occurrence Start of frame Figure 12.7 E-DMAC Operation after Receive Error ......... Received data Unreceived data Rev. 5.00 Mar. 15, 2007 Page 303 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.4 12.4.1 Usage Notes Usage Notes on SH-Ether EtherC/E-DMAC Status Register (EESR) When the status bits in EESR of the on-chip E-DMAC of the SH-Ether chip are used as interrupt sources, setting of the interrupt source may fail if software writes a 1 to the corresponding status bit in EESR to clear the bit and this coincides with setting of the status interrupt source in EESR by the EtherC or E-DMAC. Figure 12.8 shows an example of timing in the case where setting of the interrupt source in EESR has failed. (a) In this example, both the reception interrupt and transmission interrupt sources of EESR are used. Firstly, reception interrupt source A from the EtherC or E-DMAC sets bit A in EESR and an interrupt is generated. (b) The interrupt handler writes 1 to bit A to clear it. (c) If clearing of bit A by writing of a 1 and generation of the transmission-interrupt source B signal by the EtherC or E-DMAC take place simultaneously, bit A will be cleared but the status bit for transmission-interrupt source B in EESR might not be set. (a) (b), (c) (c) Internal clock (Iφ) Reception interrupt source A generated by EtherC/E-DMAC Transmission interrupt source B generated by EtherC/E-DMAC Simultaneous clearing of the bit by writing of a 1 and generation of interrupt source B. Bit A in EESR Bit B in EESR Write access to EESR by software Data to be written to EESR H'00000001 Reception interrupt source A is set in bit A of EESR. Only bit A of EESR is cleared by software. Failure to generate transmission interrupt source B due to non-setting of bit B. Bit clearing by writing a 1 : Expected operation Figure 12.8 Timing of the Case where Setting of the Interrupt Source Bit in EESR by the EDMAC Fails Rev. 5.00 Mar. 15, 2007 Page 304 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) (1) Countermeasure This problem does not occur with all of the bits in EESR. The description applies to some bits but not others. Table 12.1 shows whether the problem can occur with the individual bits and whether the state of the individual interrupt source is reflected in the descriptor. Table 12.1 EESR Bits for which This Problem can Occur and Reflection of Interrupt Sources in the Descriptor Bit 31 30 29 28 27 26 Bit Name Status  TWB    TABT Reserved Write-back complete Reserved Reserved Reserved Transmit abort detected Possibility of Problem  Yes    Yes Reflection in Descriptor      Reflected in TD0 bit8 (TFS8) Reflected in RD0 bit8 (RFS8)    Reflected in TD0 bit31 (TACT)   Reflected in RD0 bit31 (RACT)  Reflected in RD0 bit9 (RFS9) Interrupt Source  Transmit    Transmit 25 RABT Receive abort detected No Reception 24 23 22 21 RFCOF ADE ECI TC Receive frame counter overflow Address error EtherC status register interrupt source Frame transmission complete Yes No No Yes Reception Others Others Transmit 20 19 18 TDE TFUF FR Transmit descriptor empty Transmit FIFO underflow Frame received No Yes No Transmit Transmit Reception 17 16 RDE RFOF Receive descriptor empty Receive FIFO overflow No Yes Reception Reception Rev. 5.00 Mar. 15, 2007 Page 305 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 15 14 13 12 Bit Name Status     Reserved Reserved Reserved Transmit frame length error Possibility of Problem    Yes Reflection in Descriptor    Reflected in TD0 bit4 (TFS4) Reflected in TD0 bit3 (TFS3) Reflected in TD0 bit2 (TFS2) Reflected in TD0 bit1 (TFS1) Reflected in TD0 bit0 (TFS0) Reflected in RD0 bit7 (RFS7)  Reflected in RD0 bit5 (RFS5) Reflected in RD0 bit4 (RFS4) Reflected in RD0 bit3 (RFS3) Reflected in RD0 bit2 (RFS2) Reflected in RD0 bit1 (RFS1) Interrupt Source    Transmit 11 CND Carrier not detected Yes Transmit 10 DLC Loss of carrier detected Yes Transmit 9 CD Delayed collision detected Yes Transmit 8 TRO Transmit retry over Yes Transmit 7 RMAF Multicast address frame received No Reception 6 5   Reserved Receive frame discard request asserted Residual-bit frame received  No  Reception 4 RRF No Reception 3 RTLF Overly long frame received No Reception 2 RTSF Overly short frame received No Reception 1 PRE PHY receive error No Reception Rev. 5.00 Mar. 15, 2007 Page 306 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 0 Bit Name Status CERF CRC error in received frame Possibility of Problem No Reflection in Descriptor Reflected in RD0 bit0 (RFS0) Interrupt Source Reception "Yes": Setting of this interrupt source bit can fail. "No": Setting of this interrupt source bit does not fail. Take the following countermeasures for bits where the problem can arise. • Bit 30 (TWB): Write-back complete interrupt source bit in EESR may not be set. Check the TACT bit in the transmit descriptor. TACT = 0 indicates that the transmission is complete. • Bit 26 (TABT): Transmit abort detection interrupt source bit in EESR may not be set. Since the state of the interrupt source is written back to the relevant descriptor, check the transmit descriptor (TD0) to confirm the error status. • Bit 24 (RFCOF): Receive frame counter overflow interrupt source bit in EESR may not be set. However, even if the software is not notified of the interrupt despite the frame counter having overflowed, the upper layer (e.g. TCP/IP) can recognize the error because this LSI discards the frame. After departure from the overflow state, storage in the receive FIFO proceeds normally from the head of the next frame. Therefore, no problem with the system arises. • Bit 21 (TC): Frame transmission complete interrupt source bit in EESR may not be set. For transmission-related processing, either procedure (a) or (b) given below is effective. (a) Transmission processing without interrupt handling of the frame transmission complete interrupt 1. Prepare multiple transmit descriptors so that multiple frames can be transmitted. 2. After setting the transmit descriptors, set bit 0 (TR) in the E-DMAC transmit request register (EDTRR) to start transmission. 3. Before setting the next frame for transmission in the descriptor (when a transmission task arises), check the TACT bit of the corresponding transmit descriptor. 4. If the TACT bit is clear, set the frame for transmission in the corresponding transmit descriptor and set the TR bit in EDTRR to start transmission. If the TACT bit is set to 1, do not set the transmit descriptor until the next timing. (b) For systems where completion of the transmission of each frame must be confirmed (that is, set frame for transmission → initiate transmission → complete frame transmission → set the next frame for transmission → …) 1. Check the TACT bit in the last descriptor of the frame for transmission and confirm that TACT = 0, which means that the transmission was completed. Rev. 5.00 Mar. 15, 2007 Page 307 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) • Bit 19 (TFUF): Transmit FIFO underflow interrupt source bit in EESR may not be set. When this bit is used as an interrupt source but is not set when it should be, the software is not notified of the interrupt. However, the upper layer will recognize the error in the form of an underflow of the transmit FIFO. • Bit 16 (RFOF): Receive FIFO overflow interrupt source bit in EESR may not be set. Since the state of the interrupt source is written back to the relevant descriptor, check the receive descriptor (RD0) to confirm the error status. • Bit 11 (CND), bit 10 (DLC), bit 9 (CD), bit 8 (TRO): The interrupt source bits in EESR for the carrier not detected, loss of carrier detected, delayed collision detected, and transmit retry over interrupts may not be set. However, since the states of the interrupt sources are written back to the relevant descriptor, check the transmit descriptor (TD0) to confirm the error status. (2) Example of a countermeasure when the software configuration is based on the frame transmit complete interrupt The following descriptions are of sample countermeasures for cases when software processing is based on the frame transmit complete interrupt (bit 21 (TC) in EESR). If the TC interrupt source bit (bit 21) in EESR is not set on completion of transmission, the system will continue to wait for the TC interrupt, leading to stoppage of transmission. This situation arises when the interrupt handler writes a 1 to clear the bit. The sample method given as case (a) below takes the above possibility into account and avoids the problem by monitoring the transmit descriptor in interrupt processing for interrupts other than the TC interrupt. The sample method given as case (b) below avoids the above problem by setting a timeout limit for retry processing when multiple transmit descriptors are in use. Note: The countermeasure should be the one that best suits the structure of your driver and other software. Rev. 5.00 Mar. 15, 2007 Page 308 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) (a) Countermeasure by monitoring of the transmit descriptor in the processing of interrupts other than the frame transmit complete (TC) interrupt 1. Prepare multiple transmit descriptors so that multiple frames can be transmitted. 2. Provide a "condition flag" for use in step 5 and by interrupt handlers, and then turn off this flag. This flag serves as a condition flag into which the TACT bits of transmit descriptors are read out. 3. After setting the frame for transmission in the first descriptor, start transmission by setting bit 0 (TR) in the E-DMAC transmit request register (EDTRR). 4. Before setting the next frame for transmission in the transmit descriptor (when another transmission task arises), check the TACT bit in the corresponding transmit descriptor. 5. If the TACT bit is clear, set the frame for transmission in the corresponding transmit descriptor and start transmission by setting the TR bit in EDTRR. If the TACT bit is set to 1, turn on the condition flag and make an OS service call (e.g. to acquire the semaphore) to place the transmission task in the waiting state. Note: Before setting the TR bit in EDTRR, always read the TR bit and make sure that TR = 0. 6. Wait until the transmission task leaves the waiting state. There are two conditions for making the OS service call (e.g. returning the semaphore) from the interrupt handler to take the task out of the waiting state.  Generation of a TC interrupt  Generation of an interrupt other than the TC interrupt while the condition flag is on and TACT = 0. Elimination of unwanted processing by checking the TACT bit is only possible when the condition flag is on. The condition flag should be turned off after the task has left the waiting state. 7. When the transmission task has left the waiting state and entered execution, set the transmit frame in the corresponding transmit descriptor and then set the TR bit in EDTRR to start transmission. Rev. 5.00 Mar. 15, 2007 Page 309 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Transmission task 1. 2. Prepare multiple transmit descriptors. Prepare the condition flag and turn it off. Transmission starts After setting the transmit 3. descriptor, set the TR bit in EDTRR to 1. Interrupt handler Generation of EtherC/E-DMAC interrupt Save EESR and clear the bit by writing a 1. No TC interrupt? Yes No End Interrupt other than TC? Yes Interrupt processing for interrupts other than TC No Is the condition flag on? Next transmission task generated? Yes Read the TACT bit of the corresponding transmit descriptor. Make an OS service call to bring the transmission task out of the waiting state. No 4. TACT = 0? Yes 5. Turn the condition flag on. Make an OS service call to place the transmission task in a waiting state. No Yes Read the TACT bit of the corresponding transmit descriptor. No TACT = 0? 5. After setting the corresponding transmit 7. descriptor, set the TR bit in EDTRR to 1. 6. Has the transmission task been brought out of the waiting state by the interrupt handler? Yes No Yes Make an OS service call to bring the transmission task out of the waiting state. Turn off the condition flag. TC: EESR frame transmission complete : Processing added as the countermeasure for the problem End Figure 12.9 Countermeasure by Monitoring the Transmit Descriptor in Processing of Interrupts Other than the Frame Transmit Complete (TC) Interrupt Rev. 5.00 Mar. 15, 2007 Page 310 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) (b) Countermeasure by adding timeout processing 1. Prepare multiple transmit descriptors so that multiple frames can be transmitted. 2. After setting the descriptors, set bit 0 (TR) in the E-DMAC transmit request register (EDTRR) to start transmission. 3. Before setting the next frame for transmission in the transmit descriptor (when a transmission task arises), check the TACT bit in the corresponding transmit descriptor. 4. If the TACT bit is clear, set the frame for transmission in the corresponding transmit descriptor and set the TR bit in EDTRR to start transmission. If the TACT bit is set to 1, place the transmission task in a waiting state by making an OS service call of a routine with a timeout function (e.g. acquire a semaphore that has a timeout). Note: Before setting the TR bit in EDTRR, always read the TR bit and make sure that TR = 0. 5. When the transmission task has left the waiting state and entered the execution state within the time limit, set the frame for transmission in the corresponding transmit descriptor and then set the TR bit in EDTRR to start transmission. Taking the transmission task out of the waiting state should be done by the interrupt handler when the TC interrupt is generated. 6. When the timeout limit is reached, check the TACT bit in the corresponding transmit descriptor. If the TACT bit is clear, set the frame for transmission in the corresponding transmit descriptor and set the TR bit in EDTRR to start transmission. If the TACT bit is set to 1, place the transmission task in a waiting state by making an OS service call of a routine with a timeout function, or execute a software reset to initialize all of the modules associated with Ethernet functionality. Rev. 5.00 Mar. 15, 2007 Page 311 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Transmission task 1. Interrupt handler Generation of EtherC/E-DMAC interrupt Save EESR and clear the bit by writing a 1. No Prepare multiple transmit descriptors. Transmission starts. 2. After setting the transmit descriptor, set the TR bit in EDTRR to 1. TC interrupt? Next transmission task generated? Yes No Yes End Make an OS service call to bring the transmission task out of the waiting state. Read the TACT bit of the corresponding transmit descriptor. Interrupt other than TC? Yes No 3. No TACT = 0? Yes Interrupt processing for interrupts other than TC End 4. After setting the corresponding transmit 5. descriptor, set the TR bit in EDTRR to 1. 4. Place the transmission task in a waiting state by calling an OS service routine with a timeout function. Has the transmission task left the waiting state within the specified time? Yes No Timeout 6. Read the TACT bit of the corresponding transmit descriptor. No TACT = 0? Yes TC: EESR frame transmission complete : Processing added as the countermeasure for the problem Figure 12.10 Method of Adding Timeout Processing Rev. 5.00 Mar. 15, 2007 Page 312 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 12.4.2 Usage Notes on SH-Ether Transmit-FIFO Underflow In the transmission operation of the on-chip E-DMAC of the SH-Ether, if the E-DMAC cannot acquire bus-mastership due to occupancy of the bus by a bus master other than the E-DMAC, data are not writable to the transmit FIFO and an underflow occurs. The expected operation from that point is as follows: on obtaining the bus mastership, the E-DMAC resumes transmission of the remaining data for transmission; on completion of the DMA transfer, it writes back to the corresponding descriptor, and then fetches the next transmit descriptor. However, if the size of the transmit FIFO set by the FIFO depth register (FDR) ≤ maximum frame length for transmission (1518 bytes), the E-DMAC may stop operating even if the transmit request bit (TR) in the EDMAC transmit request register (EDTRR) is set to 1, according to the relationship between the length of the remaining frame data and the value of the transmit FIFO pointer. The relationship between the stoppage of E-DMAC operation and the state of the transmit FIFO is shown below. The data for transmission, which are placed in external memory (transmit buffer), are DMAtransferred by the E-DMAC to the transmit FIFO and output from the MII pin via the EtherC module. The transmit FIFO write pointer (WP) is used when the E-DMAC writes the data for transmission to the transmit FIFO, and the transmit FIFO read pointer (RP) is used when the EtherC module reads the data for transmission from the transmit FIFO. 1. After a software reset, the transmit FIFO will have been initialized, and WP and RP will hold the minimum and maximum values, respectively, of the transmit FIFO capacity. 2. When the E-DMAC starts DMA transfer, WP is incremented when the data for transmission are written to the transmit FIFO. On the other hand, RP is incremented when the data written to the transmit FIFO are read out by the EtherC module. Note: The transmit FIFO only stores the data of a single frame that is being processed. It does not store data extending over multiple frames. This means that the E-DMAC does not transfer the next frame to the transmit FIFO until the data of the frame being processed are read from the transmit FIFO. 3. If the E-DMAC fails to get the bus mastership for a system-related reason, the DMA transfer does not proceed and a transmit underflow occurs (WP = RP < frame length). Read access to the transmit FIFO by the EtherC is then terminated and RP is initialized (to the maximum value of the size of the transmit FIFO). 4. On again acquiring the bus mastership, the E-DMAC resumes DMA transfer of the remaining data of the frame. However, if the transmit FIFO becomes full despite a failure to write all of the remaining frame data from the point when the transmit FIFO underflowed, the E-DMAC waits for the transmit FIFO to become empty before transferring further remaining data. Rev. 5.00 Mar. 15, 2007 Page 313 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) However, as stated in step 3, the read access to the transmit FIFO by the EtherC module will have been terminated, and the E-DMAC thus stops operating with the transmit FIFO full. In short, this problem arises when [initial value of RP – WP value < length of remaining frame data] at the point of the transmit underflow. Data for transmission is written by the E-DMAC. Transmit FIFO Maximum transmit FIFO capacity RP Transmit FIFO WP Increment Minimum WP transmit FIFO capacity Increment RP Data for transmission is read by EtherC 1. Initial state after software reset 2. Writing and reading of the data for transmission Data for transmission is written by the E-DMAC. Transmit FIFO Maximum transmit FIFO capacity WP RP Initial state RP WP Transmit FIFO Transmit FIFO is full RP Minimum transmit FIFO capacity Data for transmission is read by EtherC Reading of data for transmission by EtherC is terminated. 4. Point where the problem makes the E-DMAC stop WP: Transmit FIFO write pointer RP: Transmit FIFO read pointer 3. Transmit-FIFO underflow has occurred Figure 12.11 Operation when E-DMAC Stops and the Transmit FIFO Rev. 5.00 Mar. 15, 2007 Page 314 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) (1) Countermeasure This problem occurs under this condition: size of transmit FIFO set in the FIFO depth register (FDR) ≤ maximum length of frame for transmission (1518bytes). To release the E-DMAC from the stopped state due to this problem, execute a software reset to initialize both the E-DMAC and EtherC modules. Specific countermeasures are given below. An example for the case where the software does not use TC interrupts in transmission processing is given as (2), and an example for the case with TC interrupt-driven software is given as (3). Both methods require the addition of timeout processing with a maximum specified time as the timeout limit, and are based on the countermeasures explained in section 12.4.1, Usage Notes on the SH-Ether EtherC/E-DMAC Status Register (EESR). The constant specified time corresponds to the timeout limit stated in section 12.4.1, Usage Notes on the SH-Ether EtherC/E-DMAC Status Register (EESR). The maximum specified time should be set with reference to the maximum times taking retry processing into consideration, as given in table 12.2. Derive n, the number of repetitions of the constant specified time, from this maximum specified time. If transfer takes more than the maximum specified time, this indicates that the EDMAC has stopped due to a transmission underflow. In this case, execute a software reset to initialize the EtherC and E-DMAC modules. Since the receiving side will also be initialized by the software reset, the receiving side may require processing in a higher-level layer (e.g. TCP/IP). Note: The countermeasure should be the one that best suits the structure of your driver and other software. (2) Countermeasure for the case where the software handles transmission without the aid of TC interrupts The countermeasure described under (a), Processing transmission without handling of the frame transmission complete (TC) interrupt, below, is based on the method explained in the description of bit 21 in (1) of section 12.4.1, Usage Notes on SH-Ether EtherC/E-DMAC Status Register (EESR). Rev. 5.00 Mar. 15, 2007 Page 315 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) (a) Processing transmission without handling of the frame transmission complete (TC) interrupt 1. Make initial settings for the timer. 2. Prepare multiple transmit descriptors so that multiple frames can be transmitted. 3. After setting the transmit descriptors, start transmission by setting bit 0 (TR) in the E-DMAC transmit request register (EDTRR). 4. Before setting the next frame for transmission in the transmit descriptor (when a transmission task arises), check the TACT bit in the corresponding transmit descriptor. 5. If the TACT bit is clear, set the frame for transmission in the corresponding transmit descriptor and start transmission by setting the TR bit in EDTRR. If the TACT bit is set to 1, set counter i to 0 (counter i is the variable that indicates the number of repetitions of the timer operation to measure the specified constant period). 6. Start counting by the timer. 7. When the specified constant period has elapsed, stop the timer counter and check the TACT bit in the corresponding transmit descriptor. 8. If the TACT bit is clear, set the frame for transmission in the corresponding transmit descriptor and set the TR bit in EDTRR to start transmission. If the TACT bit is set to 1, increment counter i. 9. While the TACT bit is found to be 1 in step 8 and the value of counter i is less than n, repeat steps 6 to 8 until the maximum specified time is reached (the maximum specified time should be set with reference to the maximum times in consideration of retry processing given in table 12.2, and from this maximum specified time, determine n, the number of repetitions of the specified constant period; n is determined by the user with reference to table 12.2). If counter i reaches or exceeds n, the maximum specified time has elapsed and we can judge that the E-DMAC has stopped due to a transmit underflow. Initialize the EtherC and E-DMAC modules by setting the software-reset bit SWR in the E-DMAC mode register (EDMR). After re-making initial settings for the Ethernet module, initialize the transmit/receive descriptors and transmit/receive buffers. Rev. 5.00 Mar. 15, 2007 Page 316 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Transmission task 1. 2. Make initial settings for the timer. Prepare multiple transmit descriptors. Transmission starts. 3. After setting the transmit descriptor, set the TR bit in EDTRR to 1. Next transmission task generated? Yes No End Read the TACT bit of the corresponding transmit descriptor. 4. No TACT = 0? Yes 5. i = 0; 5. After setting the corresponding transmit 8. descriptor, set the TR bit in EDTRR to 1. 6. Start the timer. Specified constant 1 period elapsed? * Yes 7. No Stop the timer. Read the TACT bit of the corresponding transmit descriptor. No TACT = 0? Yes i++; 8. 9. i >= n? * Yes 2 No Issue a software reset to initialize the EtherC and E-DMAC modules. Make initial settings of the EtherC and E-DMAC modules. Initialize the transmit/receive descriptors and transmit/receive buffers. Notes: 1. The specified constant period is the timeout period mentioned in section 12.4.1, Usage Notes on SH-Ether EtherC/E-DMAC Status Register (EESR). 2. Set n with reference to the maximum specified time values in table 12.2. : Processing added as the countermeasure for the problem Figure 12.12 Processing Transmission without Handling of the TC Interrupt Rev. 5.00 Mar. 15, 2007 Page 317 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) (3) Countermeasure for the case of TC interrupt-driven software The sample countermeasure for the case of TC interrupt-driven software shown below is the addition of timeout processing within the limit imposed by the maximum specified time. This is based on the method explained in (b) Countermeasure by adding timeout processing in section 12.4.1, Usage Notes on the SH-Ether EtherC/E-DMAC Status Register (EESR). The maximum specified time should be set with reference to the maximum times in consideration of retry processing (table 12.2). From this maximum specified time, determine n, the number of calls of the OS service routine with a timeout function. (b) Countermeasure as the addition of timeout processing within the limit imposed by the maximum specified time 1. Prepare multiple transmit descriptors so that multiple frames can be transmitted. 2. After setting the transmit descriptors, start transmission by setting bit 0 (TR) in the E-DMAC transmit request register (EDTRR). 3. Before setting the next frame for transmission in the transmit descriptor (when a transmission task arises), check the TACT bit in the transmit descriptor. 4. If the TACT bit is clear, set the frame for transmission in the corresponding transmit descriptor and start transmission by setting the TR bit in EDTRR. If the TACT bit is set to 1, set counter i to 0 (counter i is the variable that indicates the number of calls of the OS service routine with a timeout function). Then, place the transmission task in a waiting state by calling the OS routine (e.g. acquire a semaphore that has a timeout limit). Note: Before setting the TR bit in EDTRR, always read the TR bit and make sure that TR = 0. 5. When the transmission task has left the waiting state and entered the execution state within the specified constant period, set the frame for transmission in the corresponding transmit descriptor and then set the TR bit in EDTRR to start transmission. The transmission task should be taken out of the waiting state by the interrupt handler initiated by generation of the TC interrupt. 6. If the transmission task has not left the waiting state within the specified constant period, increment counter i. Then, if i < n, check the TACT bit in the corresponding transmit descriptor. The value for counting, n, is determined by the user with reference to table 12.2. 7. If the TACT bit is clear, set the frame for transmission in the corresponding transmit descriptor and set the TR bit in EDTRR to start transmission. If the TACT bit is set to 1, return the transmission task to the waiting state by calling an OS service routine that has a timeout function, and then repeat steps 5 and 6. Rev. 5.00 Mar. 15, 2007 Page 318 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) 8. If counter i reaches or exceeds n, the maximum specified time has elapsed and we can judge that the E-DMAC has stopped due to a transmit underflow. Initialize the EtherC and E-DMAC modules by setting the software-reset bit SWR in the E-DMAC mode register (EDMR). After re-making initial settings for the Ethernet module, initialize the transmit/receive descriptors and transmit/receive buffers. Rev. 5.00 Mar. 15, 2007 Page 319 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Transmission task 1. Interrupt handler Generation of EtherC/E-DMAC interrupt Save EESR and clear the bit by writing 1. No Prepare multiple transmit descriptors. Transmission starts. 2. After setting the transmit descriptor, set the TR bit in EDTRR to 1. TC interrupt? No Yes Next transmission task generated? Yes Make an OS service call to bring the transmission task out of the waiting state. End Interrupt other than TC? Yes No Read the TACT bit of the corresponding transmit descriptor. 3. No TACT = 0? Yes Interrupt processing for interrupts other than TC End 4. After setting the corresponding transmit 5. descriptor, set the TR bit in EDTRR to 1. i = 0; 4. Call an OS service routine with a timeout function to place the transmission task in a waiting state. Has the transmission task 1 left the waiting state within * he constant specified time? Yes No 5. 6. Timeout i++; i < n? * Yes 2 No 8. Read the TACT bit of the corresponding transmit descriptor. Issue a software reset to initialize the EtherC and E-DMAC modules. Make initial settings of the EtherC and E-DMAC modules. Initialize the transmit/receive descriptors and transmit/receive buffers. 7. TACT = 0? Yes No Notes: 1. The specified constant period is the timeout period mentioned in section 12.4.1, Usage Notes on SH-Ether EtherC/E-DMAC Status Register (EESR). 2. Set n with reference to the maximum specified time values in table 12.2. : Processing added as the countermeasure for the problem Figure 12.13 Countermeasure for the Case with TC Interrupt-Driven Software: Addition of Timeout Processing within the Limit Imposed by the Maximum Specified Time Rev. 5.00 Mar. 15, 2007 Page 320 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Table 12.2 Reference Values for Maximum Specified Time Communication Rate Maximum Full-duplex with no flow specified time control Half-duplex with no flow control With flow control 10 Mbps 1.3 ms or longer 183 ms or longer (max. 366 ms) 336 ms or longer 100 Mbps 130 µs or longer 18.3 ms or longer (max. 36.6 ms) 33.6 ms or longer Note: The maximum specified time refers to the maximum time taken to transmit a single frame or the maximum time for flow control for a single frame. Rev. 5.00 Mar. 15, 2007 Page 321 of 794 REJ09B0237-0500 Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Rev. 5.00 Mar. 15, 2007 Page 322 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Section 13 Direct Memory Access Controller (DMAC) This LSI includes the direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules. 13.1 Features • Four channels (two channels can receive an external request) • 4-Gbyte physical address space • Data transfer unit is selectable: Byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword × 4) • Maximum transfer count: 16,777,216 transfers • Address mode: Dual address mode or single address mode can be selected. • Transfer requests: External request, on-chip peripheral module request, or auto request can be selected. The following modules can issue an on-chip peripheral module request.  SCIF0, SCIF1, SCIF2, and SIOF0 • Selectable bus modes: Cycle steal mode (normal mode and intermittent mode) or burst mode can be selected. • Selectable channel priority levels: The channel priority levels are selectable between fixed mode and round-robin mode. • Interrupt request: An interrupt request can be generated to the CPU after transfers end by the specified counts. • External request detection: There are following four types of DREQ input detection.  Low level detection  High level detection  Rising edge detection  Falling edge detection • Transfer request acknowledge signal: Active levels for DACK and TEND can be set independently. Rev. 5.00 Mar. 15, 2007 Page 323 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Figure 13.1 shows the block diagram of the DMAC. DMAC module On-chip memory On-chip peripheral module Iteration control SARn DARn Peripheral bus Internal bus Register control DMATCRn Start-up control CHCRn DMA transfer request signal DMA transfer acknowledge signal Interrupt controller DEIn Request priority control DMAOR DMASR0, DMASR1 External ROM External RAM External I/O (memory mapped) External I/O (with acknowledgement) DACK0, DACK1 TEND0, TEND1 DREQ0, DREQ1 Bus state controller Bus interface [Legend] SARn: DARn: DMATCRn: CHCRn: DMAOR: DMASR0, DMASR1: DEIn: n: DMA source address register DMA destination address register DMA transfer count register DMA channel control register DMA operation register DMA extended resource selectors DMA transfer-end interrupt request to the CPU 0, 1, 2, 3 Figure 13.1 Block Diagram of DMAC Rev. 5.00 Mar. 15, 2007 Page 324 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) 13.2 Input/Output Pins The external pins for the DMAC are described below. Table 13.1 lists the configuration of the pins that are connected to external bus. The DMAC has pins for 2 channels (channels 0 and 1) for external bus use. Table 13.1 Pin Configuration Channel Name 0 DMA transfer request DMA transfer request acknowledge DMA transfer end 1 DMA transfer request DMA transfer request acknowledge DMA transfer end Pin Name DREQ0 DACK0 I/O Input Function DMA transfer request input from external device to channel 0 Output DMA transfer request acknowledge output from channel 0 to external device Output DMA transfer end of DMAC channel 0 output of Input DMA transfer request input from external device to channel 1 TEND0 DREQ1 DACK1 Output DMA transfer request acknowledge output from channel 1 to external device Output DMA transfer end of DMAC channel 1 output TEND1 Rev. 5.00 Mar. 15, 2007 Page 325 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) 13.3 Register Descriptions The DMAC has the following registers. See section 24, List of Registers, for the addresses of these registers and the state of them in each processing status. The SAR for channel 0 is expressed such as SAR_0. Channel 0: • • • • DMA source address register_0 (SAR_0) DMA destination address register_0 (DAR_0) DMA transfer count register_0 (DMATCR_0) DMA channel control register_0 (CHCR_0) Channel 1: • • • • DMA source address register_1 (SAR_1) DMA destination address register_1 (DAR_1) DMA transfer count register_1 (DMATCR_1) DMA channel control register _1 (CHCR_1) Channel 2: • • • • DMA source address register_2 (SAR_2) DMA destination address register_2 (DAR_2) DMA transfer count register_2 (DMATCR_2) DMA channel control register_2 (CHCR_2) Channel 3: • • • • DMA source address register_3 (SAR_3) DMA destination address register_3 (DAR_3) DMA transfer count register_3 (DMATCR_3) DMA channel control register_3 (CHCR_3) Common: • DMA operation register (DMAOR) • DMA extended resource selector 0 (DMARS0) • DMA extended resource selector 1 (DMARS1) Rev. 5.00 Mar. 15, 2007 Page 326 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) 13.3.1 DMA Source Address Registers 0 to 3 (SAR_0 to SAR_3) SAR are 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. When the data is transferred from an external device with the DACK in single address mode, the SAR is ignored. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. When transferring data in 16-byte units, a 16-byte boundary must be set for the source address value. The initial value is undefined. 13.3.2 DMA Destination Address Registers 0 to 3 (DAR_0 to DAR_3) DAR are 32-bit readable/writable registers that specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the next destination address. When the data is transferred from an external device with the DACK in single address mode, the DAR is ignored. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. When transferring data in 16-byte units, a 16-byte boundary must be set for the destination address value. The initial value is undefined. 13.3.3 DMA Transfer Count Registers 0 to 3 (DMATCR_0 to DMATCR_3) DMATCR are 32-bit readable/writable registers that specify the DMA transfer count. The number of transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers indicate the remaining transfer count. The upper eight bits of DMATCR are always read as 0, and the write value should always be 0. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. The initial value is undefined. Rev. 5.00 Mar. 15, 2007 Page 327 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) 13.3.4 DMA Channel Control Registers 0 to 3 (CHCR_0 to CHCR_3) CHCR are 32-bit readable/writable registers that control the DMA transfer mode. Bit 31 to 24 Bit Name  Initial Value All 0 R/W R Descriptions Reserved These bits are always read as 0. The write value should always be 0. 23 DO 0 R/W DMA Overrun Selects whether DREQ is detected by overrun 0 or by overrun 1. This bit is valid only in CHCR_0 and CHCR_1. This bit is always reserved and read as 0 in CHCR_2 and CHCR_3. The write value should always be 0. 0: Detects DREQ by overrun 0 1: Detects DREQ by overrun 1 22 TL 0 R/W Transfer End Level Specifies whether the TEND signal output is high active or low active. This bit is valid only in CHCR_0 and CHCR_1. This bit is always reserved and read as 0 in CHCR2 and CHCR_3. The write value should always be 0. 0: Low-active output of TEND 1: High-active output of TEND 21 to 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17 AM 0 R/W Acknowledge Mode Selects whether DACK is output in data read cycle or in data write cycle in dual address mode. In single address mode, DACK is always output regardless of the specification by this bit. This bit is valid only in CHCR_0 and CHCR_1. This bit is always reserved and read as 0 in CHCR_2 and CHCR_3. The write value should always be 0. 0: DACK output in read cycle (dual address mode) 1: DACK output in write cycle (dual address mode) Rev. 5.00 Mar. 15, 2007 Page 328 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Bit 16 Bit Name AL Initial Value 0 R/W R/W Descriptions Acknowledge Level Specifies whether the DACK signal output is high active or low active. This bit is valid only in CHCR_0 and CHCR_1. This bit is always reserved and read as 0 in CHCR_2 and CHCR_3. The write value should always be 0. 0: Low-active output of DACK 1: High-active output of DACK 15 14 DM1 DM0 0 0 R/W R/W Destination Address Mode 1, 0 Specify whether the DMA destination address is incremented, decremented, or left fixed. (In single address mode, the DM1 and DM0 bits are ignored when data is transferred to an external device with DACK.) 00: Fixed destination address (setting prohibited in 16byte transfer) 01: Destination address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longwordunit transfer, +16 in 16-byte transfer) 10: Destination address is decremented (–1 in byte-unit transfer, –2 in word-unit transfer, –4 in longwordunit transfer; setting prohibited in 16-byte transfer) 11: Setting prohibited 13 12 SM1 SM0 0 0 R/W R/W Source Address Mode 1, 0 Specify whether the DMA source address is incremented, decremented, or left fixed. (In single address mode, SM1 and SM0 bits are ignored when data is transferred from an external device with DACK.) 00: Fixed source address (setting prohibited in 16-byte transfer) 01: Source address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longwordunit transfer, +16 in 16-byte transfer) 10: Source address is decremented (–1 in byte-unit transfer, –2 in word-unit transfer, –4 in longwordunit transfer; setting prohibited in 16-byte transfer) 11: Setting prohibited Rev. 5.00 Mar. 15, 2007 Page 329 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Bit 11 10 9 8 Bit Name RS3 RS2 RS1 RS0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Descriptions Resource Select 3 to 0 Specify which transfer requests will be sent to the DMAC. The changing of transfer request source should be done in the state that the DMA enable bit (DE) is set to 0. 0 0 0 0 0 0 0 0 1 0 1 0 External request, dual address mode Setting prohibited External request, single address mode External address space → External device with DACK 0 0 1 1 External request, single address mode External device with DACK → External address space 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Auto request Setting prohibited Setting prohibited Setting prohibited Selected by DMA extended resource selector Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Note: External request specification is valid only in CHCR_0 and CHCR_1. None of the external request can be selected in CHCR_2 and CHCR_3. Rev. 5.00 Mar. 15, 2007 Page 330 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Bit 7 6 Bit Name DL DS Initial Value 0 0 R/W R/W R/W Descriptions DREQ Level and DREQ Edge Select Specify the detecting method of the DREQ pin input and the detecting level. These bits are valid only in CHCR_0 and CHCR_1. These bits are always reserved and read as 0 in CHCR_2 and CHCR_3. The write value should always be 0. In channels 0 and 1, also, if the transfer request source is specified as an on-chip peripheral module or if an autorequest is specified, these bits are invalid. 00: DREQ detected in low level 01: DREQ detected at falling edge 10: DREQ detected in high level 11: DREQ detected at rising edge 5 TB 0 R/W Transfer Bus Mode Specifies the bus mode when DMA transfers data. 0: Cycle steal mode 1: Burst mode 4 3 TS1 TS0 0 0 R/W R/W Transfer Size 1, 0 Specify the size of data to be transferred. Select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: Byte size 01: Word size (2 bytes) 10: Longword size (4 bytes) 11: 16-byte unit (four longword transfers) 2 IE 0 R/W Interrupt Enable Specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interrupt request (DEI) to the CPU when the TE bit is set to 1. 0: Interrupt request is disabled. 1: Interrupt request is enabled. Rev. 5.00 Mar. 15, 2007 Page 331 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Bit 1 Bit Name TE Initial Value 0 R/W Descriptions R/(W)* Transfer End Flag Shows that DMA transfer ends. The TE bit is set to 1 when data transfer ends when DMATCR becomes to 0. The TE bit is not set to 1 in the following cases. • • DMA transfer ends due to an NMI interrupt or DMA address error before DMATCR is cleared to 0. DMA transfer is ended by clearing the DE bit and DME bit in the DMA operation register (DMAOR). To clear the TE bit, the TE bit should be written to 0 after reading 1. Even if the DE bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: During the DMA transfer or DMA transfer has been interrupted [Clearing condition] Writing 0 after TE = 1 read 1: DMA transfer ends by the specified count (DMATCR = 0) 0 DE 0 R/W DMA Enable Enables or disables the DMA transfer. In auto request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this time, all of the bits TE, NMIF, and AE in DMAOR must be 0. In an external request or peripheral module request, DMA transfer starts if DMA transfer request is generated by the devices or peripheral modules after setting the bits DE and DME to 1. In this case, however, all of the bits TE, NMIF, and AE must be 0, which is the same as in the case of auto request mode. Clearing the DE bit to 0 can terminate the DMA transfer. 0: DMA transfer disabled 1: DMA transfer enabled Note: * Writing 0 is possible to clear the flag. Rev. 5.00 Mar. 15, 2007 Page 332 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) 13.3.5 DMA Operation Register (DMAOR) DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the DMA transfer. This register shows the DMA transfer status. Bit 15, 14 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13 12 CMS1 CMS0 0 0 R/W R/W Cycle Steal Mode Select 1, 0 Select either normal mode or intermittent mode in cycle steal mode. It is necessary that all channel's bus modes are set to cycle steal mode to make valid intermittent mode. 00: Normal mode 01: Setting prohibited 10: Intermittent mode 16 Executes one DMA transfer in each of 16 clocks of an external bus clock. 11: Intermittent mode 64 Executes one DMA transfer in each of 64 clocks of an external bus clock. 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 8 PR1 PR0 0 0 R/W R/W Priority Mode 1, 0 Select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: CH0 > CH1 > CH2 > CH3 01: CH0 > CH2 > CH3 > CH1 10: Setting prohibited 11: Round-robin mode 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 333 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Bit 2 Bit Name AE Initial Value 0 R/W Description R/(W)* Address Error Flag Indicates that an address error occurred during DMA transfer. If this bit is set, DMA transfer is disabled even if the DE bit in CHCR and the DME bit in DMAOR are set to 1. This bit can only be cleared by writing 0 after reading 1. 0: No DMAC address error [Clearing condition] Writing AE = 0 after AE = 1 read 1: DMAC address error occurs 1 NMIF 0 R/(W)* NMI Flag Indicates that an NMI interrupt occurred. If this bit is set, DMA transfer is disabled even if the DE bit in CHCR and the DME bit in DMAOR are set to 1. This bit can only be cleared by writing 0 after reading 1. When the NMI is input, the DMA transfer in progress can be done in one transfer unit. When the DMAC is not in operational, the NMIF bit is set to 1 even if the NMI interrupt was input. 0: No NMI interrupt [Clearing condition] Writing NMIF = 0 after NMIF = 1 read 1: NMI interrupt occurs 0 DME 0 R/W DMA Master Enable Enables or disables DMA transfers on all channels. If the DME bit and the DE bit in CHCR are set to 1, transfer is enabled. In this time, all of the bits TE in CHCR, NMIF, and AE in DMAOR must be 0. If this bit is cleared during transfer, transfers in all channels are terminated. 0: Disables DMA transfers on all channels 1: Enables DMA transfers on all channels Note: * Writing 0 is possible to clear the flag. Rev. 5.00 Mar. 15, 2007 Page 334 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) 13.3.6 DMA Extended Resource Selectors 0 and 1 (DMARS0 and DMARS1) DMARS are 16-bit readable/writable registers that specify the DMA transfer request sources from peripheral modules in each channel. DMARS0 specifies the sources for channels 0 and 1, and DMARS1 specifies the sources for channels 2 and 3. This register can set the transfer request of SCIF0, SCIF1, SCIF2, and SIOF0. When MID/RID other than the values listed in table 13.2 is set, the operation of this LSI is not guaranteed. The transfer request from DMARS is valid only when the resource select bits (RS3 to RS0) has been set to B'1000 for CHCR_0 to CHCR_3 registers. Otherwise, even if DMARS has been set, transfer request source is not accepted. • DMARS0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name C1MID5 C1MID4 C1MID3 C1MID2 C1MID1 C1MID0 C1RID1 C1RID0 C0MID5 C0MID4 C0MID3 C0MID2 C0MID1 C0MID0 C0RID1 C0RID0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer request register ID1 and ID0 for DMA channel 0 (RID) See table 13.2. Transfer request register ID1 and ID0 for DMA channel 1 (RID) See table 13.2. Transfer request module ID5 to ID0 for DMA channel 0 (MID) See table 13.2. Description Transfer request module ID5 to ID0 for DMA channel 1 (MID) See table 13.2. Rev. 5.00 Mar. 15, 2007 Page 335 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) • DMARS1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name C3MID5 C3MID4 C3MID3 C3MID2 C3MID1 C3MID0 C3RID1 C3RID0 C2MID5 C2MID4 C2MID3 C2MID2 C2MID1 C2MID0 C2RID1 C2RID0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer request register ID1 and ID0 for DMA channel 2 (RID) See table 13.2. Transfer request register ID1 and ID0 for DMA channel 3 (RID) See table 13.2. Transfer request module ID5 to ID0 for DMA channel 2 (MID) See table 13.2. Description Transfer request module ID5 to ID0 for DMA channel 3 (MID) See table 13.2. Table 13.2 Transfer Request Sources Peripheral Module SCIF0 Setting Value for One Channel (MID + RID) H'21 H'22 SCIF1 H'25 H'26 SCIF2 H'29 H'2A SIOF0 H'51 H'52 010100 001010 001001 MID 001000 RID 01 10 01 10 01 10 01 10 Function Transmit Receive Transmit Receive Transmit Receive Transmit Receive Rev. 5.00 Mar. 15, 2007 Page 336 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) 13.4 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. In bus mode, burst mode or cycle steal mode can be selected. 13.4.1 DMA Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation register (DMAOR), and DMA extended resource selectors (DMARS) are set, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0) 2. When a transfer request occurs while transfer is enabled, the DMAC transfers one transfer unit of data (depending on the TS0 and TS1 settings). In auto request mode, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented for each transfer. The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfer have been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error or an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit in CHCR or the DME bit in DMAOR is changed to 0. Rev. 5.00 Mar. 15, 2007 Page 337 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Figure 13.2 shows a flowchart of this procedure. Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR, DMARS) DE, DME = 1 and NMIF, AE, TE = 0? Yes Transfer request occurs?*1 Yes No No *2 *3 Bus mode, transfer request mode, DREQ detection selection system Transfer (1 transfer unit); DMATCR – 1 → DMATCR, SAR and DAR updated DMATCR = 0? No NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Yes Transfer aborted No Yes TE = 1 DEI interrupt request (when IE = 1) NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Yes Transfer end No Normal end Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0 and the DE and DME bits are set to 1. 2. DREQ = level detection in burst mode (external request) or cycle-steal mode. 3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode. Figure 13.2 DMA Transfer Flowchart Rev. 5.00 Mar. 15, 2007 Page 338 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) 13.4.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by external devices or on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. The request mode is selected in the RS3 to RS0 bits in DMARS0 and DMARS 1. Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits in CHCR and the DME bit in DMAOR are set to 1, the transfer begins so long as the AE and NMIF bits in DMAOR are all 0. External Request Mode: In this mode, a transfer is performed at the request signals (DREQ0 and DREQ1) of an external device. This mode is valid only in channel 0 and channel 1. Choose one of the modes shown in table 13.3 according to the application system. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at the DREQ input. Table 13.3 Selecting External Request Modes with RS Bits RS3 0 RS2 0 RS1 0 1 RS0 0 0 Address Mode Dual address mode Single address mode Source Any External memory, memory-mapped external device External device with DACK Destination Any External device with DACK External memory, memory-mapped external device 1 Choose to detect DREQ by either the edge or level of the signal input with the DL bit and DS bit in CHCR_0 and CHCR_1 as shown in table 13.4. The source of the transfer request does not have to be the data transfer source or destination. Rev. 5.00 Mar. 15, 2007 Page 339 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Table 13.4 Selecting External Request Detection with DL, DS Bits CHCR_0 or CHCR_1 DL 0 DS 0 1 1 0 1 Detection of External Request Low level detection Falling edge detection High level detection Rising edge detection When DREQ is accepted, the DREQ pin becomes request accept disabled state. After issuing acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept enabled state. When DREQ is used by level detection, there are following two cases by the timing to detect the next DREQ after outputting DACK. • Overrun 0: Transfer is aborted after the same number of transfer has been performed as requests. • Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests plus 1) times. The DO bit in CHCR selects this overrun 0 or overrun 1. Table 13.5 Selecting External Request Detection with DO Bit CHCR_0 or CHCR_1 DO 0 1 External Request Overrun 0 Overrun 1 On-Chip Peripheral Module Request Mode: In this mode, a transfer is performed at the transfer request signal of an on-chip peripheral module. Transfer request signals comprise the transmit data empty transfer request and receive data full transfer request from the SCIF0, SCIF1, SCIF2, and SIOF0 set by DMARS0 and DMARS 1. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon the input of a transfer request signal. Rev. 5.00 Mar. 15, 2007 Page 340 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) When a transmit data empty transfer request of the SCIF0 is set as the transfer request, the transfer destination must be the SCIF0's transmit data register. Likewise, when receive data full transfer request of the SCIF0 is set as the transfer request, the transfer source must be the SCIF0's receive data register. These conditions also apply to the SCIF1, SCIF2, and SIOF0. The number of the receive FIFO triggers can be set as a transfer request depending on an on-chip peripheral module. Data needs to be read after the DMA transfer is ended, because data may be remained in the receive FIFO when the receive FIFO trigger condition is not satisfied. Table 13.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits CHCR RS[3:0] 1000 DMARS MID 001000 RID 01 10 001001 01 10 001010 01 10 010100 01 10 DMA Transfer DMA Transfer Request Source Request Signal SCIF0 transmitter SCIF0 receiver SCIF1 transmitter SCIF1 receiver SCIF2 transmitter SCIF2 receiver SIOF0 transmitter SIOF0 receiver TXI0 (transmit FIFO data empty interrupt) RXI0 (receive FIFO data full interrupt) TXI1 (transmit FIFO data empty interrupt) RXI1 (receive FIFO data full interrupt) TXI2 (transmit FIFO data empty interrupt) RXI2 (receive FIFO data full interrupt) TXI0 (transmit FIFO data empty interrupt) RXI0 (receive FIFO data full interrupt) Bus Mode Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Source Any SCFRDR0 Any SCFRDR1 Any SCFRDR2 Any SIRDR0 Destination SCFTDR0 Any SCFTDR0 Any SCFTDR2 Any SITDR0 Any 13.4.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it transfers data according to a predetermined priority. Two modes (fixed mode and round-robin mode) are selected by the PR1 and PR0 bits in DMAOR. Fixed Mode: In this mode, the priority levels among the channels remain fixed. There are two kinds of fixed modes as follows: • CH0 > CH1 > CH2 > CH3 • CH0 > CH2 > CH3 > CH1 These are selected by the PR1 and the PR0 bits in DMAOR. Rev. 5.00 Mar. 15, 2007 Page 341 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Round-Robin Mode: In round-robin mode each time data of one transfer unit (word, byte, longword, or 16-byte unit) is transferred on one channel, the priority is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority. The round-robin mode operation is shown in figure 13.3. The priority of round-robin mode is CH0 > CH1 > CH2 > CH3 immediately after a reset. When round-robin mode is specified, the same bus mode, either cycle steal mode or burst mode, must be specified for all of the channels. (1) When channel 0 is transferred Initial priority order CH0 > CH1 > CH2 > CH3 CH1 > CH2 > CH3 > CH0 Channel 0 becomes bottom priority Priority order after transfer (2) When channel 1 is transferred Channel 1 becomes bottom priority. The priority of channel 0, which was higher than channel 1, is also shifted. Initial priority order CH0 > CH1 > CH2 > CH3 Priority order after transfer CH2 > CH3 > CH0 > CH1 (3) When channel 2 is transferred CH0 > CH1 > CH2 > CH3 Channel 2 becomes bottom priority. The priority of channels 0 and 1, which were higher than channel 2, are also shifted. If immediately after there is a request to transfer channel 1 only, channel 1 becomes bottom priority and the priority of channels 0 and 3, which were higher than channel 1, are also shifted. Initial priority order Priority order after transfer CH3 > CH0 > CH1 > CH2 Post-transfer priority order when there is an CH2 > CH3 > CH0 > CH1 immediate transfer request to channel 1 only (4) When a channel 3 is transferred Initial priority order Priority order after transfer CH0 > CH1 > CH2 > CH3 CH0 > CH1 > CH2 > CH3 Priority order does not change. Figure 13.3 Round-Robin Mode Rev. 5.00 Mar. 15, 2007 Page 342 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Figure 13.4 shows how the priority changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 0 and 3. 2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. When the channel 0 transfer ends, channel 0 becomes lowest priority. 5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. When the channel 1 transfer ends, channel 1 becomes lowest priority. 7. The channel 3 transfer begins. 8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority. Transfer request Waiting channel(s) DMAC operation Channel priority (1) Channels 0 and 3 (3) Channel 1 3 (2) Channel 0 transfer starts Priority order changes 0>1>2>3 1,3 (4) Channel 0 transfer ends (5) Channel 1 transfer starts 1>2>3>0 3 (6) Channel 1 transfer ends Priority order changes 2>3 >0>1 (7) Channel 3 transfer starts None (8) Channel 3 transfer ends Priority order changes 0>1>2>3 Figure 13.4 Changes in Channel Priority in Round-Robin Mode Rev. 5.00 Mar. 15, 2007 Page 343 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) 13.4.4 DMA Transfer Types DMA transfer has two types; single address mode transfer and dual address mode transfer. They depend on the number of bus cycles of access to source and destination. A data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. The DMAC supports the transfers shown in table 13.7. Table 13.7 Supported DMA Transfers Destination External Device with External DACK Memory Not available Dual, single MemoryMapped External Device Dual, single Dual Dual Dual On-Chip Peripheral Module Not available Dual Dual Dual Source External device with DACK External memory Memory-mapped external device On-chip peripheral module X/Y Memory U Memory Not available Dual Dual Dual Dual, single Dual Dual, single Dual Not available Dual Notes: 1. Dual: Dual address mode 2. Single: Single address mode 3. For on-chip peripheral modules, 16-byte transfer is available only by registers which can be accessed in longword units. Rev. 5.00 Mar. 15, 2007 Page 344 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Address Modes: • Dual Address Mode In dual address mode, both the transfer source and destination are accessed by an address. The source and destination can be located externally or internally. DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 13.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle. DMAC SAR DAR Memory Address bus Data bus Transfer source module Transfer destination module Data buffer The SAR value is an address, data is read from the transfer source module, and the data is temporarily stored in the DMAC. First bus cycle DMAC SAR Memory Address bus DAR Data bus Transfer source module Transfer destination module Data buffer The DAR value is an address and the value stored in the data buffer in the DMAC is written to the transfer destination module. Second bus cycle Figure 13.5 Data Flow of Dual Address Mode Auto request, external request, and on-chip peripheral module request are available for the transfer request. DACK can be output in read cycle or write cycle in dual address mode. The channel control register (CHCR) can specify whether the DACK is output in read cycle or write cycle. Rev. 5.00 Mar. 15, 2007 Page 345 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Figure 13.6 shows an example of DMA transfer timing in dual address mode. CKIO A25 to A0 Transfer source address Transfer destination address CSn D31 to D0 RD WEn DACKn (Active-low) Data read cycle (1st cycle) Data write cycle (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 13.6 Example of DMA Transfer Timing in Dual Mode (Source: Ordinary Memory, Destination: Ordinary Memory) Rev. 5.00 Mar. 15, 2007 Page 346 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) • Single Address Mode In single address mode, either the transfer source or transfer destination peripheral device is accessed (selected) by means of the DACK signal, and the other device is accessed by an address. In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. For example, in the case of transfer between external memory and an external device with DACK shown in figure 13.7, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. External address bus This LSI DMAC External memory External data bus External device with DACK DACK DREQ Data flow Figure 13.7 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. In both cases, only the external request signal (DREQ) is used for transfer requests. Rev. 5.00 Mar. 15, 2007 Page 347 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Figure 13.8 shows an example of DMA transfer timing in single address mode. CKIO A25 to A0 CSn WE D31 to D0 DACKn Address output to external memory space Select signal to external memory space Write strobe signal to external memory space Data output from external device with DACK DACK signal (active-low) to external device with DACK (a) External device with DACK → external memory space (ordinary memory) CKIO A25 to A0 CSn RD D31 to D0 DACKn Address output to external memory space Select signal to external memory space Read strobe signal to external memory space Data output from external memory space DACK signal (active-low) to external device with DACK (b) External memory space (ordinary memory) → external device with DACK Figure 13.8 Example of DMA Transfer Timing in Single Address Mode Bus Modes: There are two bus modes: cycle steal mode and burst mode. Select the mode in the TB bits in the channel control register (CHCR). • Cycle-Steal Mode  Normal mode In cycle-steal normal mode, the bus mastership is given to another bus master after a onetransfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer request occurs, the bus mastership is obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus mastership is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. In cycle-steal normal mode, transfer areas are not affected regardless of settings of the transfer request source, transfer source, and transfer destination. Figure 13.9 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer conditions shown in the figure are:  Dual address mode  DREQ low level detection Rev. 5.00 Mar. 15, 2007 Page 348 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) DREQ Bus mastership returned to CPU once Bus cycle CPU CPU CPU DMAC DMAC Read/Write CPU DMAC DMAC CPU Read/Write Figure 13.9 DMA Transfer Example in Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection)  Intermittent mode 16 and intermittent mode 64 In intermittent mode of cycle steal, the DMAC returns the bus mastership to other bus master whenever a unit of transfer (byte, word, longword, or 16-byte unit) is complete. If the next transfer request occurs after that, the DMAC gets the bus mastership from other bus master after waiting for 16 or 64 clocks in Bφ count. The DMAC then transfers data of one unit and returns the bus mastership to other bus master. These operations are repeated until the transfer end condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA transfer than cycle-steal normal mode. When the DMAC gets again the bus mastership, DMA transfer can be postponed in case of entry updating due to cache miss. This intermittent mode can be used for all transfer section; transfer request source, transfer source, and transfer destination. The bus modes, however, must be cycle steal mode in all channels. Rev. 5.00 Mar. 15, 2007 Page 349 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Figure 13.10 shows an example of DMA transfer timing in cycle steal intermittent mode. Transfer conditions shown in the figure are:  Dual address mode  DREQ low level detection DREQ More than 16 or 64 Bφ (change by the CPU, LCDC, and USBH states of using bus) Bus cycle CPU CPU CPU DMAC DMAC Read/Write CPU CPU DMAC DMAC Read/Write CPU Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode (Dual Address, DREQ Low Level Detection) • Burst Mode In burst mode, once the DMAC obtains the bus mastership, the transfer is performed continuously without releasing the bus mastership until the transfer end condition is satisfied. In external request mode with level detection of the DREQ pin, however, when the DREQ pin is not active, the bus mastership passes to the other bus master after the DMAC transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. Burst mode cannot be used when the on-chip peripheral module is the transfer request source. Figure 13.11 shows DMA transfer timing in burst mode. DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC Read Write Read Write Read Write CPU Figure 13.11 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection) Rev. 5.00 Mar. 15, 2007 Page 350 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 13.8 shows the relationship between request modes and bus modes by DMA transfer category. Table 13.8 Relationship between Request Modes and Bus Modes by DMA Transfer Category Address Mode Transfer Category Dual External device with DACK and external memory Request Bus Mode Mode External B/C B/C B/C B/C B/C C C C B/C B/C Transfer Size (Bits) 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 Usable Channels 0,1 0, 1 0 to 5*4 0 to 5*4 0 to 5*4 External device with DACK and memory- External mapped external device External memory and external memory External memory and memory-mapped external device Memory-mapped external device and memory-mapped external device External memory and on-chip peripheral module Memory-mapped external device and on-chip peripheral module On-chip peripheral module and on-chip peripheral module Single External device with DACK and external memory All*1 All*1 All*1 All*2 All*2 All*2 External 8/16/32/128*3 0 to 5*4 8/16/32/128*3 0 to 5*4 8/16/32/128*3 0 to 5*4 8/16/32 8/16/32 0, 1 0, 1 External device with DACK and memory- External mapped external device B: Burst mode, C: Cycle steal mode Notes: 1. External requests and auto requests are all available. 2. External requests, auto requests, and on-chip peripheral module requests are all available. However, for on-chip peripheral module requests, the request source register must be designated as the transfer source or the transfer destination. 3. Access size permitted for the on-chip peripheral module register functioning as the transfer source or transfer destination. 4. If the transfer request is an external request, channels 0 and 1 are only available. Rev. 5.00 Mar. 15, 2007 Page 351 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Bus Mode and Channel Priority: When the priority is set in fixed mode (CH0 > CH1), even though channel 1 is transferring in burst mode, if there is a transfer request to channel 0 which has a higher priority, the transfer of channel 0 will begin immediately. At this time, if channel 0 is also operating in burst mode, the channel 1 transfer will continue when the channel 0 transfer with a higher priority has completely finished. If channel 0 is operating in cycle steal mode, immediately after channel 0 with a higher priority completes the transfer of one transfer unit, the channel 1 transfer will begin again without releasing the bus mastership. Transfer will then switch between the two in the order of channel 0, channel 1, channel 0, and channel 1. For the bus state, the CPU cycle after cycle steal mode transfer finishes is replaced with a burst mode transfer cycle (hereafter referred to as burst mode high-priority execution). This example is illustrated in figure 13.12. If there are channels with conflicting burst transfers, transfer for the channel with the highest priority is performed first. In DMA transfer for more than one channel, the DMAC does not give the bus mastership to the bus master until all conflicting burst transfers have finished. CPU DMA CH1 DMA CH1 DMA CH0 CH0 DMA CH1 CH1 DMA CH0 CH0 DMA CH1 DMA CH1 CPU CPU DMAC CH1 Burst mode DMAC CH0 and CH1 Cycle-steal mode DMAC CH1 Burst mode CPU Priority: CH0 > CH1 CH0: Cycle-steal mode CH1: Burst mode Figure 13.12 Bus State when Multiple Channels are Operating In round-robin mode, the priority changes according to the specifications shown in figure 13.3. Note that a channel operating in cycle steal mode cannot be handled together with a channel operating in burst mode. Rev. 5.00 Mar. 15, 2007 Page 352 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) 13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. For details, see section 7, Bus State Controller (BSC). DREQ Pin Sampling Timing: Figures 13.13, 13.14, 13.15, and 13.16 show the sample timing of the DREQ input in each bus mode, respectively. CKIO Bus cycle DREQ (Rising edge) DACK (High-active) CPU CPU 1st acceptance Non-sensitive period DMAC CPU 2nd acceptance Acceptance started Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection CKIO Bus cycle DREQ (Overrun 0, high-level) DACK (High-active) CPU 1st acceptance CPU DMAC CPU 2nd acceptance Non-sensitive period Acceptance started CKIO Bus cycle DREQ (Overrun 1, high-level) DACKn (High-active) CPU 1st acceptance CPU DMAC CPU 2nd acceptance Non-sensitive period Non-sensitive period Acceptance started Figure 13.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection Rev. 5.00 Mar. 15, 2007 Page 353 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) CKIO Bus cycle DREQ (Rising edge) DACK (High-active) CPU CPU Burst acceptance DMAC DMAC Non-sensitive period Figure 13.15 Example of DREQ Input Detection in Burst Mode Edge Detection CKIO Bus cycle DREQ (Overrun 0, high-level) DACK (High-active) CPU 1st acceptance CPU DMAC 2nd acceptance Non-sensitive period Acceptance started CKIO Bus cycle DREQ (Overrun 1, high-level) DACK (High-active) Acceptance started Acceptance started CPU 1st acceptance CPU DMAC 2nd acceptance DMAC 3rd acceptance Non-sensitive period Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection Rev. 5.00 Mar. 15, 2007 Page 354 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) CKIO Last DMA transfer Bus cycle DREQ DMAC CPU DMAC CPU CPU DACK TEND Figure 13.17 Example of DMA Transfer End in Cycle Steal Mode Level Detection When an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external device is accessed in word units, the DACK output is divided because of the data alignment. This example is illustrated in figure 13.18. Rev. 5.00 Mar. 15, 2007 Page 355 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) T1 CKIO T2 Taw T1 T2 Address CS RD Data WEn DACKn (Active-low) WAIT Note: The DACK is asserted for the last transfer unit of the DMA transfer. When the transfer unit is divided into several bus cycles and the CS is negated between bus cycles, the DACK is also divided. Figure 13.18 Example of BSC Ordinary Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) Rev. 5.00 Mar. 15, 2007 Page 356 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) 13.5 Usage Notes Pay attentions to the following notes when the DMAC is used. 13.5.1 Notes on DACK Pin Output When burst mode and cycle steal mode are simultaneously set in two or more channels, an additional DACK may be asserted at the end of burst transfer. This phenomenon will occur when all of the conditions described below are satisfied. 1. When the DMA transfer is simultaneously performed in two or more channels support both burst mode and cycle steal mode 2. When the channel to be used in burst mode is set to dual address mode, and DACK is output in data write cycle 3. When the DMAC cannot obtain the bus mastership consecutively even though a transfer demand of cycle steal has been received after the completion of burst transfer This phenomenon is avoided by taking either of three measures shown below. • Measure 1 After confirming the completion of burst transfer (TE bit = 1), perform the DMA transfer of other cycle steal mode • Measure 2 The channel to be used in burst mode should not be set to output DACK in data write cycle • Measure 3 When the DMA transfer is simultaneously performed in two or more channels, set all of the channels to burst mode or cycle steal mode Rev. 5.00 Mar. 15, 2007 Page 357 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) 13.5.2 (1) Notes On DREQ Sampling When DACK is Divided in External Access Error Phenomenon When the DACK output is divided in an external access, DREQ may be sampled twice at maximum in the external access. (2) Error Conditions and Phenomenon Conditions: The DACK output is divided in an external access when: • 16-byte access, • 32-bit access to the 8-bit space, • 16-bit access to the 8-bit space, or • 32-bit access to the 16-bit space is performed with either of the following idle cycle settings made: • Idle cycles between write-write cycles (IWW = 01 or more) • Idle cycles between read-read cycles in the same spaces (IWRRS = 01 or more) • External wait mask specification (WM = 0). In addition to the above conditions, the following conditions are included depending on the detection method of DREQ. • For DREQ level detection: only write access • For DREQ edge detection: both write access and read access Phenomenon: The detection timings of the DREQ pin in the above access are shown in figures 13.19 to 13.22. CKIO Bus cycle CPU 1st acceptance 2nd acceptance DMAC write or read DREQ (Rising edge) Non-sensitive period DACK (High-active) Non-sensitive period 3rd acceptance possible Figure 13.19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection When DACK is Divided to 4 by Idle Cycles Rev. 5.00 Mar. 15, 2007 Page 358 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) CKIO Bus cycle DREQ (Rising edge) DACK (High-active) CPU 1st acceptance Non-sensitive period DMAC write or read 2nd acceptance 3rd acceptance is after the Non-sensitive period next DACK assertion Figure 13.20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection When DACK is Divided to 2 by Idle Cycles CKIO CPU 1st acceptance Non-sensitive period 2nd acceptance DMAC write 3rd acceptance possible Bus cycle DREQ (Overrun 0, high-level) DACK (High-active) Non-sensitive period CKIO CPU 1st acceptance 2nd acceptance DMAC write 3rd acceptance possible Bus cycle DREQ (Overrun 1, high-level) DACK (High-active) Non-sensitive period Non-sensitive period Figure 13.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When DACK is Divided to 4 by Idle Cycles Rev. 5.00 Mar. 15, 2007 Page 359 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) CKIO CPU 1st acceptance Non-sensitive period DMAC write 2nd acceptance 3rd acceptance possible Non-sensitive period Bus cycle DREQ (Overrun 0, high-level) DACK (High-active) CKIO Bus cycle DREQ (Overrun 1, high-level) DACK (High-active) CPU 1st acceptance DMAC write 2nd acceptance 3rd acceptance possible Non-sensitive period Non-sensitive period Figure 13.22 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When DACK is Divided to 2 by Idle Cycles (3) Notes For the external access described in (2) above, note the following. 1. When the DREQ edge is detected, input one DREQ edge at maximum in the bus cycle. 2. When the DREQ level is detected in overrun 0, negate the DREQ input in the bus cycle after the detection of the first DACK output negation and before the second DACK output negation. 3. When the DREQ level is detected in overrun 1, negate DREQ input after the detection of the first DACK output assertion and before the second DACK output assertion. Rev. 5.00 Mar. 15, 2007 Page 360 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) 13.5.3 Other Notes 1. Before making a transition to standby mode, either wait until DMA transfer finishes or suspend DMA transfer. 2. If an on-chip peripheral module whose clock supply is to be stopped by the module standby function is performing DMA transfer, either wait until DMA transfer finishes or suspend DMA transfer before making a transition to module standby mode. 3. Do not write to SAR, DAR, DMATCR, or DMARS during DMA transfer. Concerning Above Notes 1 and 2: DMA transfer end can be confirmed by checking whether the TE bit in CHCR is set to 1. To suspend DMA transfer, clear the DE bit in CHCR to 0. Rev. 5.00 Mar. 15, 2007 Page 361 of 794 REJ09B0237-0500 Section 13 Direct Memory Access Controller (DMAC) Rev. 5.00 Mar. 15, 2007 Page 362 of 794 REJ09B0237-0500 Section 14 Compare Match Timer (CMT) Section 14 Compare Match Timer (CMT) This LSI has an on-chip compare match timer (CMT) consisting of a 2-channel 16-bit timer. The CMT has a16-bit counter, and can generate interrupts at set intervals. 14.1 Features CMT has the following features. • Selection of four counter input clocks Any of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected independently for each channel. • Interrupt request on compare match • When not in use, CMT can be stopped by halting its clock supply to reduce power consumption. Figure 14.1 shows a block diagram of CMT. Pφ/32 Pφ/512 Pφ/128 Pφ/32 Pφ/512 Pφ/128 CMI0 Pφ/8 CMI1 Pφ/8 Control circuit Clock selection Control circuit Clock selection Comparator Comparator CMCOR0 CMCOR1 CMCSR0 CMCSR1 CMCNT0 Channel 0 Module bus CMT [Legend] CMSTR: CMCSR: CMCOR: CMCNT: CMI: CMCNT1 CMSTR0 Channel 1 Bus interface Internal bus Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match counter Compare match interrupt Figure 14.1 Block Diagram of Compare Match Timer Rev. 5.00 Mar. 15, 2007 Page 363 of 794 REJ09B0237-0500 Section 14 Compare Match Timer (CMT) 14.2 Register Descriptions The CMT has the following registers. • • • • • • • • Compare match timer start register (CMSTR) Compare match timer control/status register_0 (CMCSR_0) Compare match counter_0 (CMCNT_0) Compare match constant register_0 (CMCOR_0) Compare match timer start register_1 (CMSTR_1) Compare match timer control/status register_1 (CMCSR_1) Compare match counter_1 (CMCNT_1) Compare match constant register_1 (CMCOR_1) Compare Match Timer Start Register (CMSTR) 14.2.1 CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is stopped. CMSTR is initialized to H'0000 by a power-on reset and a transition to standby mode. Bit 15 to 2 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 STR1 0 R/W Count Start 1 Specifies whether compare match counter 1 operates or is stopped. 0: CMCNT_1 count is stopped 1: CMCNT_1 count is started 0 STR0 0 R/W Count Start 0 Specifies whether compare match counter 0 operates or is stopped. 0: CMCNT_0 count is stopped 1: CMCNT_0 count is started Rev. 5.00 Mar. 15, 2007 Page 364 of 794 REJ09B0237-0500 Section 14 Compare Match Timer (CMT) 14.2.2 Compare Match Timer Control/Status Register (CMCSR) CMCSR is a 16-bit register that indicates compare match generation, enables interrupts and selects the counter input clock. CMCSR is initialized to H'0000 by a power-on reset and a transition to standby mode. Bit 15 to 8 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 CMF 0 R/(W)* Compare Match Flag Indicates whether or not the values of CMCNT and CMCOR match. 0: CMCNT and CMCOR values do not match [Clearing condition] When 0 is written to this bit 1: CMCNT and CMCOR values match 6 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables compare match interrupt (CMI) generation when CMCNT and CMCOR values match (CMF=1). 0: Compare match interrupt (CMI) disabled 1: Compare match interrupt (CMI) enabled 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 365 of 794 REJ09B0237-0500 Section 14 Compare Match Timer (CMT) Bit 1 0 Bit Name CKS1 CKS0 Initial value 0 0 R/W R/W R/W Description Clock Select 1 and 0 Select the clock to be input to CMCNT from four internal clocks obtained by dividing the peripheral operating clock (Pφ). When the STR bit in CMSTR is set to 1, CMCNT starts counting on the clock selected with bits CKS1 and CKS0. 00: Pφ/8 01: Pφ/32 10: Pφ/128 11: Pφ/512 Note: * Only 0 can be written, to clear the flag. 14.2.3 Compare Match Counter (CMCNT) CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts counting using the selected clock. When the value in CMCNT and the value in compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. CMCNT is initialized to H'0000 by a power-on reset and a transition to standby mode. 14.2.4 Compare Match Constant Register (CMCOR) CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT. CMCOR is initialized to H'FFFF by a power-on reset and is initialized to H'FFFF in standby mode. Rev. 5.00 Mar. 15, 2007 Page 366 of 794 REJ09B0237-0500 Section 14 Compare Match Timer (CMT) 14.3 14.3.1 Operation Interval Count Operation When an internal clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CMIE bit in CMCSR is set to 1, a compare match interrupt (CMI) is requested. CMCNT then starts counting up again from H'0000. Figure 14.2 shows the operation of the compare match counter. CMCNT1 value Counter cleared by compare match with CMCOR1 CMCOR1 H'0000 Time Figure 14.2 Counter Operation 14.3.2 CMCNT Count Timing One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the Pφ clock can be selected with bits CKS1 and CKS0 in CMCSR. Figure 14.3 shows the timing. Peripheral operating clock (Pφ) Nth clock N (N + 1)th clock N+1 Count clock CMCNT1 Figure 14.3 Count Timing Rev. 5.00 Mar. 15, 2007 Page 367 of 794 REJ09B0237-0500 Section 14 Compare Match Timer (CMT) 14.4 14.4.1 Interrupts Interrupt Sources The CMT has channels and each of them to which a different vector address is allocated has compare match interrupt. When both the interrupt request flag (CMF) and interrupt enable bit (CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to activate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings. For details, see section 6, Interrupt Controller (INTC). 14.4.2 Timing of Setting Compare Match Flag When CMCOR and CMCNT match, a compare match signal is generated and the CMF bit in CMCSR is set to 1. The compare match signal is generated in the last cycle in which the values match (when the CMCNT value is updated to H'0000). That is, after a match between CMCOR and CMCNT, the compare match signal is not generated until the next CMCNT counter clock input. Figure 14.4 shows the timing of CMF bit setting. Peripheral operating clock (Pφ) Counter clock (N + 1)th clock CMCNT1 N 0 CMCOR1 N Compare match signal Figure 14.4 Timing of CMF Setting 14.4.3 Timing of Clearing Compare Match Flag The CMF bit in CMCSR is cleared by reading 1 from this bit, then writing 0. Rev. 5.00 Mar. 15, 2007 Page 368 of 794 REJ09B0237-0500 Section 14 Compare Match Timer (CMT) 14.5 14.5.1 Usage Notes Conflict between Write and Compare-Match Processes of CMCNT When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 14.5 shows the timing to clear the CMCNT counter. CMCSR write cycle T1 Peripheral operating clock (Pφ) T2 Address CMCNT Internal write Counter clear CMCNT N H'0000 Figure 14.5 Conflict between Write and Compare-Match Processes of CMCNT Rev. 5.00 Mar. 15, 2007 Page 369 of 794 REJ09B0237-0500 Section 14 Compare Match Timer (CMT) 14.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has priority over the count-up. In this case, the count-up is not performed. Figure 14.6 shows the timing to write to CMCNT in words. CMCSR write cycle T1 Peripheral operating clock (Pφ) T2 Address CMCNT Internal write CMCNT count-up enable CMCNT N M Figure 14.6 Conflict between Word-Write and Count-Up Processes of CMCNT Rev. 5.00 Mar. 15, 2007 Page 370 of 794 REJ09B0237-0500 Section 14 Compare Match Timer (CMT) 14.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the byte-writing has priority over the count-up. In this case, the count-up is not performed. The byte data on another side, which is not written to, is also not counted and the previous contents remain. Figure 14.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNT in bytes. CMCSR write cycle T1 Peripheral operating clock (Pφ) T2 Address CMCNTH Internal write CMCNT count-up enable CMCNTH N M CMCNTL X X Figure 14.7 Conflict between Byte-Write and Count-Up Processes of CMCNT 14.5.4 Conflict between Write Processes to CMCNT with the Counting Stopped and CMCOR Writing the same value to CMCNT with the counting stopped and CMCOR is prohibited. If written, the CMF flag in CMCSR is set to 1 and CMCNT is cleared to H'0000. Rev. 5.00 Mar. 15, 2007 Page 371 of 794 REJ09B0237-0500 Section 14 Compare Match Timer (CMT) Rev. 5.00 Mar. 15, 2007 Page 372 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Section 15 Serial Communication Interface with FIFO (SCIF) 15.1 Overview This LSI has a three-channel serial communication interface with FIFO (SCIF) that supports both asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception independently for each channel that enable this LSI to perform efficient high-speed continuous communication. 15.1.1 Features • Asynchronous serial communication:  Serial data communication is performed by start-stop in character units. The SCIF can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are eight selectable serial data communication formats.  Data length: 7 or 8 bits  Stop bit length: 1 or 2 bits  Parity: Even, odd, or none  Receive error detection: Parity, framing, and overrun errors  Break detection: Break is detected when a framing error is followed by at least one frame at the space 0 level (low level). It is also detected by reading the RxD level directly from the port data register when a framing error occurs. • Synchronous mode:  Serial data communication is synchronized with a clock signal. The SCIF can communicate with other chips having a synchronous communication function. There is one serial data communication format.  Data length: 8 bits  Receive error detection: Overrun errors • Full duplex communication: The transmitting and receiving sections are independent, so the SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions. • On-chip baud rate generator with selectable bit rates Rev. 5.00 Mar. 15, 2007 Page 373 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) • Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) • Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error interrupts are requested independently. • When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving power. • In asynchronous, on-chip modem control functions (RTS and CTS) (only for channel 1 and channel 0). • The number of data in the transmit and receive FIFO registers and the number of receive errors of the receive data in the receive FIFO register can be ascertained. • A time-out error (DR) can be detected when receiving in asynchronous mode. Rev. 5.00 Mar. 15, 2007 Page 374 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Figure 15.1 shows a block diagram of the SCIF for each channel. Bus interface Module data bus Internal data bus SCSMR SCFRDR (16 stage) SCFTDR (16 stage) SCLSR SCFDR SCFCR RxD SCRSR SCTSR SCFSR SCSCR SCSPTR Transmission/ reception control TxD Parity generation Parity check SCK CTS RTS Clock SCBRRn Pφ Baud rate generator Pφ/4 Pφ/16 Pφ/64 External clock TXI RXI ERI BRI SCIF [Legend] SCRSR: Receive shift register SCFRDR: Receive FIFO data register SCTSR: Transmit shift register SCFTDR: Transmit FIFO data register SCSMR: Serial mode register SCSCR: Serial control register SCFSR: Serial status register SCBRR: Bit rate register SCSPTR: Serial port register SCFCR: FIFO control register SCFDR: FIFO data count register SCLSR: Line status register Figure 15.1 Block Diagram of SCIF Rev. 5.00 Mar. 15, 2007 Page 375 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.2 Pin Configuration The SCIF has the serial pins summarized in table 15.1. Table 15.1 SCIF Pins Channel 0 Pin Name Serial clock pin Receive data pin Transmit data pin Request to send pin Clear to send pin 1 Serial clock pin Receive data pin Transmit data pin Request to send Clear to send pin 2 Serial clock pin Receive data pin Transmit data pin Abbreviation SCK0 RxD0 TxD0 RTS0 CTS0 SCK1 RxD1 TxD1 RTS1 CTS1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O I/O I/O Input Output Output Input I/O Input Output Function Clock I/O Receive data input Transmit data output Request to send Clear to send Clock I/O Receive data input Transmit data output Request to send Clear to send Clock I/O Receive data input Transmit data output Rev. 5.00 Mar. 15, 2007 Page 376 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3 Register Description The SCIF has the following registers. These registers specify the data format and bit rate, and control the transmitter and receiver sections. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Receive FIFO data register_0 (SCFRDR_0) Transmit FIFO data register_0 (SCFTDR_0) Serial mode register_0 (SCSMR_0) Serial control register_0 (SCSCR_0) Serial status register_0 (SCFSR_0) Bit rate register_0 (SCBRR_0) FIFO control register_0 (SCFCR_0) FIFO data count register_0 (SCFDR_0) Serial port register_0 (SCSPTR_0) Line status register_0 (SCLSR_0) Receive FIFO data register_1 (SCFRDR_1) Transmit FIFO data register_1 (SCFTDR_1) Serial mode register_1 (SCSMR_1) Serial control register_1 (SCSCR_1) Serial status register_1 (SCFSR_1) Bit rate register_1 (SCBRR_1) FIFO control register_1 (SCFCR_1) FIFO data count register_1 (SCFDR_1) Serial port register_1 (SCSPTR_1) Line status register_1 (SCLSR_1) Receive FIFO data register_2 (SCFRDR_2) Transmit FIFO data register_2 (SCFTDR_2) Serial mode register_2 (SCSMR_2) Serial control register_2 (SCSCR_2) Serial status register_2 (SCFSR_2) Bit rate register_2 (SCBRR_2) FIFO control register_2 (SCFCR_2) FIFO data count register_2 (SCFDR_2) Serial port register_2 (SCSPTR_2) Line status register_2 (SCLSR_2) Rev. 5.00 Mar. 15, 2007 Page 377 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.1 Receive Shift Register (SCRSR) SCRSR receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCFRDR, the receive FIFO data register. The CPU cannot read or write to SCRSR directly. 15.3.2 Receive FIFO Data Register (SCFRDR) SCFRDR is a 16-stage 8-bit FIFO register that stores serial receive data. The SCIF completes the reception of one byte of serial data by moving the received data from the receive shift register (SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored. The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the value is undefined. When this register is full of receive data, subsequent serial data is lost. SCFRDR is initialized to undefined value by a power-on reset. Bit 7 to 0 Bit Name  Initial value R/W Description FIFO for transmits serial data Undefined R 15.3.3 Transmit Shift Register (SCTSR) SCTSR transmits serial data. The SCIF loads transmit data from the transmit FIFO data register (SCFTDR) into SCTSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCIF automatically loads the next transmit data from SCFTDR into SCTSR and starts transmitting again. The CPU cannot read or write to SCTSR directly. Rev. 5.00 Mar. 15, 2007 Page 378 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.4 Transmit FIFO Data Register (SCFTDR) SCFTDR is a 16-stage 8-bit FIFO register that stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed until there is no transmit data left in SCFTDR. SCFTDR can always be written to by the CPU. When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new data is attempted, the data is ignored. SCFTDR is initialized to undefined value by a power-on reset. Bit 7 to 0 Bit Name  Initial value R/W Description FIFO for transmits serial data Undefined W 15.3.5 Serial Mode Register (SCSMR) SCSMR is a 16-bit register that specifies the SCIF serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. SCSMR is initialized to H'0000 by a power-on reset. Bit 15 to 8 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 C/A 0 R/W Communication Mode Selects whether the SCIF operates in asynchronous or synchronous mode. 0: Asynchronous mode 1: Synchronous mode Rev. 5.00 Mar. 15, 2007 Page 379 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 6 Bit Name CHR Initial value 0 R/W R/W Description Character Length Selects 7-bit or 8-bit data in asynchronous mode. In the synchronous mode, the data length is always eight bits, regardless of the CHR setting. 0: 8-bit data 1: 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register is not transmitted. 5 PE 0 R/W Parity Enable Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added or checked 1: Parity bit added and checked* Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. 4 O/E 0 R/W Parity mode Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 0: Even parity*1 1: Odd parity*2 Note: 1. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. Rev. 5.00 Mar. 15, 2007 Page 380 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 3 Bit Name STOP Initial value 0 R/W R/W Description Stop Bit Length Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because no stop bits are added. When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. 0: One stop bit When transmitting, a single 1-bit is added at the end of each transmitted character. 1: Two stop bits When transmitting, two 1 bits are added at the end of each transmitted character. 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 Select the internal clock source of the on-chip baud rate generator. Four clock sources are available. Pφ, Pφ/4, Pφ/16 and Pφ/64. For further information on the clock source, bit rate register settings, and baud rate, see section 15.3.8, Bit Rate Register (SCBRR). 00: Pφ 01: Pφ/4 10: Pφ/16 11: Pφ/64 Note: Pφ: Peripheral clock Rev. 5.00 Mar. 15, 2007 Page 381 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.6 Serial Control Register (SCSCR) SCSCR is a 16-bit register that operates the SCIF transmitter/receiver, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'0000 by a power-on reset. Bit 15 to 8 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 TIE 0 R/W Transmit Interrupt Enable Enables or disables the transmit-FIFO-data-empty interrupt (TXI). Serial transmit data in the transmit FIFO data register (SCFTDR) is send to the transmit shift register (SCTSR). Then, the TDFE flag in the serial status register (SCFSR) is set to1 when the number of data in SCFTDR becomes less than the number of transmission triggers. At this time, a TXI is requested. 0: Transmit-FIFO-data-empty interrupt request (TXI) is disabled* 1: Transmit-FIFO-data-empty interrupt request (TXI) is enabled Note: * The TXI interrupt request can be cleared by writing a greater number of transmit data than the specified transmission trigger number to SCFTDR and by clearing the TDFE bit to 0 after reading 1 from the TDFE bit, or can be cleared by clearing this bit to 0. Rev. 5.00 Mar. 15, 2007 Page 382 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 6 Bit Name RIE Initial value 0 R/W R/W Description Receive Interrupt Enable Enables or disables the receive-data-full (RXI) interrupts requested when the RDF flag or DR flag in serial status register (SCFSR) is set to1, receive-error (ERI) interrupts requested when the ER flag in SCFSR is set to1, and break (BRI) interrupts requested when the BRK flag in SCFSR or the ORER flag in line status register (SCLSR) is set to1. 0: Receive-data-full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are disabled* 1: Receive-data-full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are enabled Note: * RXI interrupt requests can be cleared by reading the DR or RDF flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. ERI or BRI interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. 5 TE 0 R/W Transmit Enable Enables or disables the SCIF serial transmitter. 0: Transmitter disabled 1: Transmitter enabled* Note: * Serial transmission starts after writing of transmit data into SCFTDR. Select the transmit format in SCSMR and SCFCR and reset the transmit FIFO before setting TE to 1. Rev. 5.00 Mar. 15, 2007 Page 383 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 4 Bit Name RE Initial value 0 R/W R/W Description Receive Enable Enables or disables the SCIF serial receiver. 0:Receiver disabled* 1 2 1: Receiver enabled* Note: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, RDF, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in synchronous mode. Select the receive format in SCSMR and SCFCR and reset the receive FIFO before setting RE to 1. 3 REIE 0 R Receive Error Interrupt Enable Enables or disables the receive-error (ERI) interrupts and break (BRI) interrupts. The setting of REIE bit is valid only when RIE bit is set to 0. 0: Receive-error interrupt (ERI) and break interrupt (BRI) requests are disabled* 1: Receive-error interrupt (ERI) and break interrupt (BRI) requests are enabled Note: * ERI or BRI interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. Even if RIE is set to 0, when REIE is set to 1, ERI or BRI interrupt requests are enabled. 2  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 384 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 1 0 Bit Name CKE1 CKE0 Initial value 0 0 R/W R/W R/W Description Clock Enable 1 and 0 Select the SCIF clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. The CKE0 setting is valid only when the SCIF is operating on the internal clock (CKE1 = 0). The CKE0 setting is ignored when an external clock source is selected (CKE1 = 1). In synchronous mode, select the SCIF operating mode in the serial mode register (SCSMR), then set CKE1 and CKE0. • Asynchronous mode 00: Internal clock, SCK pin used for input pin (The input signal is ignored. The state of the SCK pin depends on both the SCKIO and SCKDT bits.) 01: Internal clock, SCK pin used for clock output (The output clock frequency is 16 times the bit rate.) 10: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate.) 11: Setting prohibited • Synchronous mode 00: Internal clock, SCK pin used for serial clock output 01: Internal clock, SCK pin used for serial clock output 10: External clock, SCK pin used for serial clock input 11: Setting prohibited Rev. 5.00 Mar. 15, 2007 Page 385 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.7 Serial Status Register (SCFSR) SCFSR is a 16-bit register. The upper 8 bits indicate the number of receives errors in the SCFRDR data, and the lower 8 bits indicate the status flag indicating SCIF operating state. The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. SCFSR is initialized to H'0060 by a power-on reset. Bit 15 14 13 12 Bit Name PER3 PER2 PER1 PER0 Initial value 0 0 0 0 R/W R R R R Description Number of Parity Errors Indicate the number of data including a parity error in the receive data stored in the receive FIFO data register (SCFRDR). The value indicated by bits 15 to 12 represents the number of parity errors in SCFRDR. When parity errors have occurred in all 16-byte receive data in SCFRDR, PER3 to PER0 show 0. Number of Framing Errors Indicate the number of data including a framing error in the receive data stored in SCFRDR. The value indicated by bits 11 to 8 represents the number of framing errors in SCFRDR. When framing errors have occurred in all 16-byte receive data in SCFRDR, FER3 to FER0 show 0. 11 10 9 8 FER3 FER2 FER1 FER0 0 0 0 0 R R R R Rev. 5.00 Mar. 15, 2007 Page 386 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 7 Bit Name ER Initial value 0 R/W Description R/(W)* Receive Error Indicates the occurrence of a framing error, or of a 1 parity error when receiving data that includes parity. * 0: Receiving is in progress or has ended normally [Clearing conditions] • • ER is cleared to 0 a power-on reset ER is cleared to 0 when the chip is when 0 is written after 1 is read from ER 1: A framing error or parity error has occurred. [Setting conditions] • ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit of the received data 2 is 1 at the end of one data receive operation* • ER is set to 1 when the total number of 1s in the receive data plus parity bit does not match the even/odd parity specified by the O/E bit in SCSMR Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ER bit, which retains its previous value. Even if a receive error occurs, the receive data is transferred to SCFRDR and the receive operation is continued. Whether or not the data read from SCRDR includes a receive error can be detected by the FER and PER bits in SCFSR. 2. In two stop bits mode, only the first stop bit is checked; the second stop bit is not checked. Rev. 5.00 Mar. 15, 2007 Page 387 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 6 Bit Name TEND Initial value 0 R/W Description R/(W)* Transmit End Indicates that when the last bit of a serial character was transmitted, SCFTDR did not contain valid data, so transmission has ended. 0: Transmission is in progress [Clearing conditions] • TEND is cleared to 0 when 0 is written after 1 is read from TEND after transmit data is written in SCFTDR 1: End of transmission [Setting conditions] • • • TEND is set to 1 when the chip is a power-on reset TEND is set to 1 when TE is cleared to 0 in the serial control register (SCSCR) TEND is set to 1 when SCFTDR does not contain receive data when the last bit of a one-byte serial character is transmitted Rev. 5.00 Mar. 15, 2007 Page 388 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 5 Bit Name TDFE Initial value 0 R/W Description R/(W)* Transmit FIFO Data Empty Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the number of data in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and TTRG0 bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled. 0: The number of transmit data written to SCFTDR is greater than the specified transmission trigger number [Clearing conditions] • TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR after 1 is read from the TDFE bit and then 0 is written TDFE is cleared to 0 when DMAC write data exceeding the specified transmission trigger number to SCFTDR • 1: The number of transmit data in SCFTDR is equal to or less than the specified transmission trigger number* [Setting conditions] • • TDFE is set to 1 by a power-on reset TDFE is set to 1 when the number of transmit data in SCFTDR has become equal to or less than the specified transmission trigger number as a result of transmission Note: * Since SCFTDR is a 16-byte FIFO register, the maximum number of data that can be written when TDFE is 1 is "16 minus the specified transmission trigger number". If an attempt is made to write additional data, the data is ignored. The number of data in SCFTDR is indicated by the upper 8 bits of SCFDR. Rev. 5.00 Mar. 15, 2007 Page 389 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 4 Bit Name BRK Initial value 0 R/W Description R/(W)* Break Detection Indicates that a break signal has been detected in receive data. 0: No break signal received [Clearing conditions] • • BRK is cleared to 0 when the chip is a power-on reset BRK is cleared to 0 when software reads BRK after it has been set to 1, then writes 0 to BRK 1: Break signal received* [Setting condition] • BRK is set to 1 when data including a framing error is received, and a framing error occurs with space 0 in the subsequent receive data Note: * When a break is detected, transfer of the receive data (H'00) to SCFRDR stops after detection. When the break ends and the receive signal becomes mark 1, the transfer of receive data resumes. 3 FER 0 R Framing Error Indicates a framing error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive framing error occurred in the next data read from SCFRDR [Clearing conditions] • • FER is cleared to 0 when the chip undergoes a power-on reset FER is cleared to 0 when no framing error is present in the next data read from SCFRDR 1: A receive framing error occurred in the next data read from SCFRDR. [Setting condition] • FER is set to 1 when a framing error is present in the next data read from SCFRDR Rev. 5.00 Mar. 15, 2007 Page 390 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 2 Bit Name PER Initial value 0 R/W R Description Parity Error Indicates a parity error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive parity error occurred in the next data read from SCFRDR [Clearing conditions] • • PER is cleared to 0 when the chip undergoes a power-on reset PER is cleared to 0 when no parity error is present in the next data read from SCFRDR 1: A receive parity error occurred in the data read from SCFRDR [Setting condition] • PER is set to 1 when a parity error is present in the next data read from SCFRDR Rev. 5.00 Mar. 15, 2007 Page 391 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 1 Bit Name RDF Initial value 0 R/W Description R/(W)* Receive FIFO Data Full Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the number of data in SCFRDR has become more than the receive trigger number specified by the RTRG1 and RTRG0 bits in the FIFO control register (SCFCR). 0: The number of transmit data written to SCFRDR is less than the specified receive trigger number [Clearing conditions] • • RDF is cleared to 0 by a power-on reset RDF is cleared to 0 when the SCFRDR is read until the number of receive data in SCFRDR becomes less than the specified receive trigger number after 1 is read from RDF and then 0 is written 1: The number of receive data in SCFRDR is more than the specified receive trigger number [Setting condition] • RDF is set to 1 when a number of receive data more than the specified receive trigger number is stored in SCFRDR* Note: * SCFTDR is a 16-byte FIFO register. When RDF is 1, the specified receive trigger number of data can be read at the maximum. If an attempt is made to read after all the data in SCFRDR has been read, the data is undefined. The number of receive data in SCFRDR is indicated by the lower 8 bits of SCFDR. Rev. 5.00 Mar. 15, 2007 Page 392 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 0 Bit Name DR Initial value 0 R/W Description R/(W)* Receive Data Ready Indicates that the number of data in the receive FIFO data register (SCFRDR) is less than the specified receive trigger number, and that the next data has not yet been received after the elapse of 15 ETU from the last stop bit in asynchronous mode. In clock synchronous mode, this bit is not set to 1. 0: Receiving is in progress, or no receive data remains in SCFRDR after receiving ended normally [Clearing conditions] • • DR is cleared to 0 when the chip undergoes a power-on reset DR is cleared to 0 when all receive data are read after 1 is read from DR and then 0 is written 1: Next receive data has not been received [Setting conditions] • DR is set to 1 when SCFRDR contains less data than the specified receive trigger number, and the next data has not yet been received after the elapse of 15 ETU from the last stop bit.* Note: * This is equivalent to 1.5 frames with the 8-bit, 1-stop-bit format. (ETU: elementary time unit) Note: * The only value that can be written is 0 to clear the flag. Rev. 5.00 Mar. 15, 2007 Page 393 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.8 Bit Rate Register (SCBRR) SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset. Each channel has independent baud rate generator control, so different values can be set in three channels. The SCBRR setting is calculated as follows: • Asynchronous mode: N= Pφ × 106 - 1 64 × 22n-1 × B • Synchronous mode: N= Pφ × 106 - 1 8 × 22n-1 × B B: N: Bit rate (bits/s) SCBRR setting for baud rate generator (0 ≤ N ≤ 255) (The setting value should satisfy the electrical characteristics.) Pφ: Operating frequency for peripheral modules (MHz) n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 15.2.) Rev. 5.00 Mar. 15, 2007 Page 394 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Table 15.2 SCSMR Settings SCSMR Settings n 0 1 2 3 Clock Source Pφ Pφ/4 Pφ/16 Pφ/64 Pφ × 106 -1 (N + 1) × B × 642n-1 × 2 CKS1 0 0 1 1 CKS0 0 1 0 1 Note: The bit rate error in asynchronous is given by the following formula: Error (%) = × 100 Table 15.3 lists examples of SCBRR settings in asynchronous mode, and table 15.4 lists examples of SCBRR settings in synchronous mode. Table 15.3 Bit Rates and SCBRR Settings in Asynchronous Mode Pφ (MHz) 5 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 Error (%) n –0.25 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 1.73 0.00 1.73 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 6 Error (%) n –0.44 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 –2.34 0.00 –2.34 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 6.144 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 Rev. 5.00 Mar. 15, 2007 Page 395 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Pφ (MHz) 7.3728 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 1 1 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) n –0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 Pφ (MHz) 10 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 Error (% ) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (% ) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 –2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (% ) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (% ) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 8 Error (%) n 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 –6.99 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 9.8304 Error (%) –0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 Rev. 5.00 Mar. 15, 2007 Page 396 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Pφ (MHz) 16 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 Error (% ) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (% ) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (% ) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –1.36 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 24 Error (% ) –0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 –2.34 24.576 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 N 108 79 159 79 159 79 159 79 39 24 19 Error (% ) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 28.7 N 126 92 186 92 186 92 186 92 46 28 22 Error (% ) 0.31 0.46 –0.08 0.46 –0.08 0.46 –0.08 0.46 –0.61 –1.03 1.55 n 3 3 2 2 1 1 0 0 0 0 0 N 30 Error (% ) 0.13 –0.35 0.16 –0.35 0.16 –0.35 –1.36 –0.35 –0.35 0.00 1.73 132 97 194 97 194 97 194 97 48 29 23 Note: Settings with an error of 1% or less are recommended. Rev. 5.00 Mar. 15, 2007 Page 397 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Table 15.4 Bit Rates and SCBRR Settings in Synchronous Mode Bit Rate (bits/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M 5 n  3 3 2 1 0 0 0 0  0   N  77 38 77 124 249 124 49 24  4   n  3 2 2 1 1 0 0 0 0 0 0 0 0 8 N  124 249 124 199 99 199 79 39 19 7 3 1 0* n  3 3 2 2 1 1 0 0 0 0 0 0 0 16 N  249 124 249 99 199 99 159 79 39 15 7 3 1 n   3 3 2 2 1 1 0 0     28.7 N   223 111 178 89 178 71 143 71     n   3 3 2 2 1 1 0 0 0 0   30 N   233 116 187 93 187 74 149 74 29 14   [Legend] Blank: No setting possible : Setting possible, but error occurs *: Continuous transmission/reception is disabled. Note: Settings with an error of 1% or less are recommended. Rev. 5.00 Mar. 15, 2007 Page 398 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Table 15.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 15.6 and 15.7 list the maximum rates for external clock input. Table 15.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ (MHz) 5 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 Maximum Bit Rate (bits/s) 156250 153600 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 n 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 5.00 Mar. 15, 2007 Page 399 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Table 15.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ (MHz) 5 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 External Input Clock (MHz) 1.2500 1.2288 2.0000 2.4576 3.0000 3.6864 4.0000 4.9152 5.0000 6.0000 6.1440 7.1750 7.5000 Maximum Bit Rate (bits/s) 78125 76800 125000 153600 187500 230400 250000 307200 312500 375000 384000 448436 468750 Table 15.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) Pφ (MHz) 5 8 16 24 28.7 30 External Input Clock (MHz) 0.8333 1.3333 2.6667 4.0000 4.7833 5.0000 Maximum Bit Rate (bits/s) 833333.3 1333333.3 2666666.7 4000000.0 4783333.3 5000000.0 Rev. 5.00 Mar. 15, 2007 Page 400 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.9 FIFO Control Register (SCFCR) SCFCR is a 16-bit register that resets the number of data in the transmit and receive FIFO registers, sets the trigger data number, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU. It is initialized to H'0000 by a power-on reset. Bit 15 to 11 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 9 8 RSTRG2 RSTRG1 RSTRG0 0 0 0 R/W R/W R/W RTS Output Active Trigger When the number of receive data in the receive FIFO register (SCFRDR) becomes more than the number shown below, the RTS signal is set to high. These bits are available only in SCFCR_0 and SCFCR_1. In SCFCR_2, these bits are reserved. The initial value is 0 and the write value should always be 0. 000: 15 001: 1 010: 4 011: 6 100: 8 101: 10 110: 12 111: 14 Rev. 5.00 Mar. 15, 2007 Page 401 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 7 6 Bit Name RTRG1 RTRG0 Initial value 0 0 R/W R/W R/W Description Receive FIFO Data Trigger Set the specified receive trigger number. The receive data full (RDF) flag in the serial status register (SCFSR) is set when the number of receive data stored in the receive FIFO register (SCFRDR) exceeds the specified trigger number shown below. • Asynchronous mode 00: 1 01: 4 10: 8 11: 14 • Synchronous mode 00: 1 01: 2 10: 8 11: 14 5 4 TTRG1 TTRG0 0 0 R/W R/W Transmit FIFO Data Trigger 1 and 0 Set the specified transmit trigger number. The transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR) is set when the number of transmit data in the transmit FIFO data register (SCFTDR) becomes less than the specified trigger number shown below. 00: 8 (8)* 01: 4 (12)* 10: 2 (14)* 11: 0 (16)* Note: * Values in parentheses mean the number of remaining bytes in SCFTDR when the TDFE flag is set to 1. Rev. 5.00 Mar. 15, 2007 Page 402 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 3 Bit Name MCE Initial value 0 R/W R/W Description Modem Control Enable Enables modem control signals CTS and RTS. In synchronous mode, clear this bit to 0. This bit is available only in SCFCR_0 and SCFCR_1. In SCFCR_2, this bit is reserved. The initial value is 0 and the write value should always be 0. 0: Modem signal disabled* 1: Modem signal enabled Note: * The CTS signal is fixed active 0 regardless of the input value, and the RTS signal is also fixed 0. 2 TFRST 0 R/W Transmit FIFO Data Register Reset Disables the transmit data in the transmit FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset. 1 RFRST 0 R/W Receive FIFO Data Register Reset Disables the receive data in the receive FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset. 0 LOOP 0 R/W Loop-Back Test Internally connects the transmit output pin (TxD) and receive input pin (RxD) and enables loop-back testing. 0: Loop back test disabled 1: Loop back test enabled Rev. 5.00 Mar. 15, 2007 Page 403 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.10 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit register which indicates the number of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the number of transmit data in SCFTDR with the upper eight bits, and the number of receive data in SCFRDR with the lower eight bits. SCFDR can always be read from by the CPU. SCFDR is initialized to H'0000 by a power on reset. Bit 15 to 13 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 11 10 9 8 7 to 5 T4 T3 T2 T1 T0  0 0 0 0 0 All 0 R R R R R R Reserved These bits are always read as 0. The write value should always be 0. 4 3 2 1 0 R4 R3 R2 R1 R0 0 0 0 0 0 R R R R R Indicate the number of receive data stored in SCFRDR. H'00 means no receive data, and H'10 means that SCFRDR full of receive data. Indicate the number of non-transmitted data stored in SCFTDR. H'00 means no transmit data, and H'10 means that SCFTDR is full of transmit data. Rev. 5.00 Mar. 15, 2007 Page 404 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.11 Serial Port Register (SCSPTR) SCSPTR is a 16-bit register that controls input/output and data for the pins multiplexed to the SCIF function. Bits 7 and 6 can control the RTS pin, bits 5 and 4 can control the CTS pin, and bits 3 and 2 can control the SCK pin. Bits 1 and 0 can be used to read the input data from the RxD pin and to output data to the TxD pin, so they control break of serial transfer. In addition to descriptions of individual bits shown below, see section 15.6, Serial Port Register (SCSPTR) and SCIF Pins. SCSPTR can always be read from or written to by the CPU. Bits 7, 5, 3, and 1 in SCSPTR are initialized by a power-on reset. Bit 15 to 8 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 RTSIO 0 R/W RTS Port Input/Output Control Controls the RTS pin in combination with the RTSDT bit in this register and the MCE bit in SCFCR. This bit is reserved in SCPTR_2 of SCIF channel 2 since SCIF channel 2 does not support the flow control. 6 RTSDT * R/W RTS Port Data Controls the RTS pin in combination with the RTSIO bit in this register and the MCE bit in SCFCR. Select the RTS pin function in the PFC (pin function controller) beforehand. MCE RTSIO RTSDT: RTS pin state 0 0 0 1 0 1 1 × ×: 0: 1: ×: Input (initial state) Low level output High level output Sequence output according to modem control logic ×: Don't care The RTS pin state is read from this bit instead of the set value. This bit is reserved in SCPTR_2 of SCIF channel 2 since SCIF channel 2 does not support the flow control. Rev. 5.00 Mar. 15, 2007 Page 405 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 5 Bit Name CTSIO Initial value 0 R/W R/W Description CTS Port Input/Output Control Controls the CTS pin in combination with the CTSDT bit in this register and the MCE bit in SCFCR. This bit is reserved in SCPTR_2 of SCIF channel 2 since SCIF channel 2 does not support the flow control. 4 CTSDT * R/W CTS Port Data Controls the CTS pin in combination with the CTSIO bit in this register and the MCE bit in SCFCR. Select the CTS pin function in the PFC (pin function controller) beforehand. MCE CTSIO CTSDT: CTS pin state 0 0 0 1 0 1 1 × ×: 0: 1: ×: Input (initial state) Low level output High level output Input to modem control logic ×: Don't care The CTS pin state is read from this bit instead of the set value. This bit is reserved in SCPTR_2 of SCIF channel 2 since SCIF channel 2 does not support the flow control. 3 SCKIO 0 R/W SCK Port Input/Output Control Controls the SCK pin in combination with the SCKDT bit in this register, the C/A bit in SCSMR, and bits CKE1 and CKE0 in SCSCR. Rev. 5.00 Mar. 15, 2007 Page 406 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 2 Bit Name SCKDT Initial value * R/W R/W Description SCK Port Data Controls the SCK pin in combination with the SCKIO bit in this register, the C/A bit in SCSMR, and bits CKE1 and CKE0 in SCSCR. Select the SCK pin function in the PFC (pin function controller) beforehand. C/A 0 0 0 0 CKE1 0 0 0 0 CKE0 0 0 0 1 SCKIO 0 0 1 × SCKDT: ×: 0: 1: ×: SCK pin state Input (initial state) Low level output High level output Internal clock output according to serial core logic External clock input to serial core logic Setting prohibited Internal clock output according to serial core logic Internal clock output according to serial core logic External clock input to serial core logic Setting prohibited 0 0 1 1 1 0 0 1 0 × × × ×: ×: ×: 1 0 1 × ×: 1 1 1 1 0 1 × × ×: ×: ×: Don't care The SCK pin state is read from this bit instead of the set value. 1 SPBIO 0 R/W Serial Port Break Input/Output Control Controls the TxD pin in combination with the SPBDT bit in this register and the TE bit in SCSCR. Rev. 5.00 Mar. 15, 2007 Page 407 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Bit 0 Bit Name SPBDT Initial value * R/W R/W Description Serial Port Break Data Controls the TxD pin in combination with the SPBIO bit in this register and the TE bit in SCSCR. The RxD pin state can also be monitored. Select the TxD or RxD pin function in the PFC (pin function controller) beforehand. TE 0 0 0 0 SPBIO 0 1 1 × SPBDT: ×: 0: 1: ×: TxD pin state Input (initial state) Low level output High level output Transmit data output according to serial core logic ×: Don't care The RxD pin state is read from this bit instead of the set value. Note: * This bit is read as an undefined value and the setting value is 0. Rev. 5.00 Mar. 15, 2007 Page 408 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.3.12 Line Status Register (SCLSR) SCLSR is a 16-bit readable/writable register which can always be read from and written to by the CPU. However, a 1 cannot be written to the ORER flag. This flag can be cleared to 0 only if it has first been read (after being set to 1). SCLSR is initialized to H'0000 by a power-on reset. Bit 15 to 1 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 ORER 0 R/(W)* Overrun Error Indicates the occurrence of an overrun error. 0: Receiving is in progress or has ended normally * [Clearing conditions] • • ORER is cleared to 0 when the chip is a power-on reset ORER is cleared to 0 when 0 is written after 1 is read from ORER. 2 1 1: An overrun error has occurred * [Setting condition] • ORER is set to 1 when the next serial receiving is finished while receive FIFO data are full. Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ORER bit, which retains its previous value. 2. The receive FIFO data register (SCFRDR) hold the data before an overrun error is occurred, and the next receive data is extinguished. When ORER is set to 1, SCIF can not continue the next serial receiving. Note: * The only value that can be written is 0 to clear the flag. Rev. 5.00 Mar. 15, 2007 Page 409 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.4 15.4.1 Operation Overview For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. The SCIF has a 16-byte FIFO buffer for both transmit and receive operations, reducing the overhead of the CPU, and enabling continuous high-speed communication. Moreover, it has RTS and CTS signals as modem control signals (for channels 0 and 1). The transmission format is selected in the serial mode register (SCSMR), which is shown in table 15.8. The SCIF clock source is selected by the combination of the CKE1 and CKE0 bits in the serial control register (SCSCR), which is shown in table 15.9. Asynchronous Mode: • Data length is selectable: 7 or 8 bits. • Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length. • In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full, overrun errors, receive data ready, and breaks. • The number of stored data bytes is indicated for both the transmit and receive FIFO registers. • An internal or external clock can be selected as the SCIF clock source.  When an internal clock is selected, the SCIF operates using the on-chip baud rate generator.  When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode: • The transmission/reception format has a fixed 8-bit data length. • In receiving, it is possible to detect overrun errors (ORER). • An internal or external clock can be selected as the SCIF clock source.  When an internal clock is selected, the SCIF operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices.  When an external clock is selected, the SCIF operates on the input serial clock. The onchip baud rate generator is not used. Rev. 5.00 Mar. 15, 2007 Page 410 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Table 15.8 SCSMR Settings and SCIF Communication Formats SCSMR Settings Bit 7 C/A 0 Bit 6 CHR 0 Bit 5 PE 0 Bit 3 STOP Mode 0 1 1 0 1 1 0 0 1 1 0 1 1 Note: * * * * Synchronous 8 bits Not set : Don't care Set 7 bits Not set Set Asynchronous SCIF Communication Format Data Length 8 bits Parity Bit Not set Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None Table 15.9 SCSMR and SCSCR Settings and SCIF Clock Source Selection SCSMR Bit 7 C/A 0 SCSCR Settings Bit 1 CKE1 0 Bit 0 CKE0 0 Mode Asynchronous Clock Source Internal SCIF Transmit/Receive Clock SCK Pin Function SCIF does not use the SCK pin. The state of the SCK pin depends on both the SCKIO and SCKDT bits. Clock with a frequency 16 times the bit rate is output. External  Synchronous Internal External  Input a clock with frequency 16 times the bit rate. Setting prohibited. Serial clock is output. Input the serial clock. Setting prohibited. 1 1 0 1 1 0 1 Note: * * 0 1 : Don't care Rev. 5.00 Mar. 15, 2007 Page 411 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.4.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCIF are independent, so full duplex communication is possible. The transmitter and receiver are 16-byte FIFO buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 15.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCIF monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCIF synchronizes at the falling edge of the start bit. The SCIF samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Idle state (mark state) 1 0/1 Parity bit 1 bit or none 1 1 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 Stop bit Transmit/receive data 7 or 8 bits One unit of transfer data (character or frame) 1 or 2 bits Figure 15.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) Rev. 5.00 Mar. 15, 2007 Page 412 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Transmit/Receive Formats: Table 15.10 lists the eight communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 15.10 Serial Communication Formats (Asynchronous Mode) SCSMR Bits CHR 0 0 0 0 1 1 1 1 PE STOP 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 START START START START START START START START 2 Serial Transmit/Receive Format and Frame Length 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP STOP STOP STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data [Legend] START: Start bit STOP: Stop bit P: Parity bit Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR) (table 15.9). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCIF operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to 16 times the desired bit rate. Rev. 5.00 Mar. 15, 2007 Page 413 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Transmitting and Receiving Data: SCIF Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing TE and RE to 0, however, does not initialize the serial status register (SCFSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the TEND flag in the SCFSR is set. The TE bit can be cleared to 0 during transmission, but the transmit data goes to the Mark state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1 and reset SCFTDR before TE is set again to start transmission. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCIF operation becomes unreliable if the clock is stopped. Rev. 5.00 Mar. 15, 2007 Page 414 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Figure 15.3 shows a sample flowchart for initializing the SCIF. Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 After reading BRK, DR, and ER flags in SCFSR, and each flag in SCLSR, write 0 to clear them Set CKE1 and CKE0 bits in SCSCR (leaving TE, RE, TIE, and RIE bits cleared to 0) Set data transfer format in SCSMR Set value in SCBRR Wait 1-bit interval elapsed? Yes Set RTRG1-0 and TTRG1-0 bits in SCFCR, and clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits End of initialization [4] No [1] [1] Set the clock selection in SCSCR. Be sure to clear bits TIE, RIE, TE, and RE to 0. [2] Set the data transfer format in SCSMR. [3] Write a value corresponding to the bit rate into SCBRR. (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE bit or RE bit in SCSCR to 1. Also set the RIE, REIE, and TIE bits. Setting the TE bit enables the TxD and RxD pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. [2] [3] Figure 15.3 Sample Flowchart for SCIF Initialization Rev. 5.00 Mar. 15, 2007 Page 415 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Transmitting Serial Data (Asynchronous Mode) Figure 15.4 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start of transmission [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and read 1 from the TDFE and TEND flags, then clear to 0. [1] The number of transmit data bytes that can be written is 16 - (transmit trigger set number). [2] Serial transmission continuation procedure: No [2] To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE flag to 0. [3] Break output at the end of serial transmission: No To output a break in serial transmission, clear the SPBDT bit to 0 and set the SPBIO bit to 1 in SCSPTR, then clear the TE bit in SCSCR to 0. In [1] and [2], it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR indicated by the upper 8 bits of SCFDR. Read TDFE flag in SCFSR No TDFE = 1? Yes Write transmit data in SCFTDR, and read 1 from TDFE flag and TEND flag in SCFSR, then clear to 0 All data transmitted? Yes Read TEND flag in SCFSR TEND = 1? Yes Break output? Yes Clear SPBDT to 0 and set SPBIO to 1 Clear TE bit in SCSCR to 0 No [3] End of transmission Figure 15.4 Sample Flowchart for Transmitting Serial Data Rev. 5.00 Mar. 15, 2007 Page 416 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register (SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD pin in the following order. A. Start bit: One-bit 0 is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) D. Stop bit(s): One or two 1 bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. Rev. 5.00 Mar. 15, 2007 Page 417 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Figure 15.5 shows an example of the operation for transmission. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Serial data 1 Idle state (mark state) TDFE TEND TXI interrupt request Data written to SCFTDR and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame TXI interrupt request Figure 15.5 Example of Transmit Operation (8-Bit Data, Parity, One Stop Bit) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with the CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When CTS is set to 0, the next transmit data is output starting from the start bit. Figure 15.6 shows an example of the operation when modem control is used (only for channel 0). Start bit Serial data TxD 0 D0 D1 Parity Stop bit bit D7 0/1 1 Start bit 0 D0 D1 D7 0/1 CTS Drive high before stop bit Figure 15.6 Example of Operation Using Modem Control (CTS) Rev. 5.00 Mar. 15, 2007 Page 418 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Receiving Serial Data (Asynchronous Mode): Figures 15.7 and 15.8 show a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. [1] Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR, and the ORER flag in SCLSR, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD pin. [2] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [3] Serial reception continuation procedure: All data received? Yes Clear RE bit in SCSCR to 0 End of reception [3] To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading from SCRFDR. Start of reception Read ER, DR, BRK flags in SCFSR and ORER flag in SCLSR [1] ER, DR, BRK or ORER = 1? No Read RDF flag in SCFSR No Yes Error handling [2] RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 No Figure 15.7 Sample Flowchart for Receiving Serial Data (1) Rev. 5.00 Mar. 15, 2007 Page 419 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Error handling No ORER = 1? Yes Overrun error handling [1] Whether a framing error or parity error has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER bits in SCFSR. [2] When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00, and the break data in which a framing error occurred is stored. No ER = 1? Yes Receive error handling No BRK = 1? Yes Break handling No DR = 1? Yes Read receive data in SCFRDR Clear DR, ER, BRK flags in SCFSR, and ORER flag in SCLSR, to 0 End Figure 15.8 Sample Flowchart for Receiving Serial Data (2) Rev. 5.00 Mar. 15, 2007 Page 420 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. B. The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR) to SCFRDR. C. Overrun check: The SCIF checks that the ORER flag is 0, indicating that the overrun error has not occurred. D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If all the above checks are passed, the receive data is stored in SCFRDR. Note: When a parity error or a framing error occurs, reception is not suspended. 4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated. Rev. 5.00 Mar. 15, 2007 Page 421 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Figure 15.9 shows an example of the operation for reception. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 0/1 1 Serial data RDF FER RXI interrupt request One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler ERI interrupt request generated by receive error Figure 15.9 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit) 5. When modem control is enabled, the RTS signal is output depending on the empty status of SCFRDR. When RTS is 0, reception is possible. When RTS is 1, this indicates that the SCFRDR is full and no extra data can be received. (Only for channel 0 and channel 1) Figure 15.10 shows an example of the operation when modem control is used. Start bit Serial data RxD 0 D0 D1 D2 Parity Stop bit bit D7 0/1 1 Start bit 0 D0 D1 D7 0/1 RTS Figure 15.10 Example of Operation Using Modem Control (RTS) Rev. 5.00 Mar. 15, 2007 Page 422 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.4.3 Synchronous Mode In synchronous mode, the SCIF transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCIF transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 15.11 shows the general format in synchronous serial communication. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don’t care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don’t care * Figure 15.11 Data Format in Synchronous Communication In synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode, the SCIF transmits data by synchronizing with the falling edge of the serial clock, and receives data by synchronizing with the rising edge of the serial clock. Rev. 5.00 Mar. 15, 2007 Page 423 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Communication Format: The data length is fixed at eight bits. No parity bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCIF is not transmitting or receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs while the RE bit of SCSCR is 1 and the number of data in receive FIFO is less than the receive FIFO data trigger number. In this case, 8 × (16 + 1) = 136 pulses of synchronous clock are output. To perform reception of n characters of data, select an external clock as the clock source. If an internal clock should be used, set RE = 1 and TE = 1 and receive n characters of data simultaneously with the transmission of n characters of dummy data. Transmitting and Receiving Data SCIF Initialization (Synchronous Mode): Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents. Figure 15.12 shows a sample flowchart for initializing the SCIF. Rev. 5.00 Mar. 15, 2007 Page 424 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 to clear the FIFO buffer After reading BRK, DR, and ER flags in SCFSR and a flag in SCLSR, write 0 to clear them Set CKE1 and CKE0 bits in SCSCR (leaving TE, RE, TIE, and RIE bits cleared to 0) Set data transfer format in SCSMR Set value in SCBRR Wait 1-bit interval elapsed? Yes Set RTRG1-0 and TTRG1-0 bits in SCFCR, and clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits End of initialization [1] [1] Leave the TE and RE bits cleared to 0 until the initialization almost ends. Be sure to clear the TIE, RIE, TE, and RE bits to 0. [2] Set the CKE1 and CKE0 bits. [3] Set the data transfer format in SCSMR. [4] Write a value corresponding to the bit rate into SCBRR. This is not necessary if an external clock is used. Wait at least one bit interval after this write before moving to the next step. [2] [3] [4] No [5] Set the TE or RE bit in SCSCR to 1. Also set the TEI, RIE, and REIE bits to enable the TxD, RxD, and SCK pins to be used. When transmitting, the TxD pin will go to the mark state. When receiving in clocked synchronous mode with the synchronization clock output (clock master) selected, a clock starts to be output from the SCIF_CLK pin at this point. [5] Figure 15.12 Sample Flowchart for SCIF Initialization Rev. 5.00 Mar. 15, 2007 Page 425 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Transmitting Serial Data (Synchronous Mode): Figure 15.13 shows a sample flowchart for transmitting serial data. Start of transmission [1] SCIF status check and transmit data write: No Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR. Read the TDFE and TEND flags while they are 1, then clear them to 0. [1] Read TDFE flag in SCFSR TDFE = 1? Yes Write transmit data to SCFTDR Read TDFE and TEND flags in SCFSR while they are 1, then clear them to 0 [2] Serial transmission continuation procedeure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, them write data to SCFTDR, and then clear the TDFE flag to 0. All data transmitted? [2] Yes Read TEND flag in SCFSR No TEND = 1? Yes Clear TE bit in SCSCR to 0 No End of transmission Figure 15.13 Sample Flowchart for Transmitting Serial Data Rev. 5.00 Mar. 15, 2007 Page 426 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) In transmitting serial data, the SCIF operates as follows: 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register (SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. If clock output mode is selected, the SCIF outputs eight synchronous clock pulses. If an external clock source is selected, the SCIF outputs data in synchronization with the input clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCIF checks the SCFTDR transmit data at the timing for sending the MSB (bit 7). If data is present, the data is transferred from SCFTDR to SCTSR, the MSB (bit 7) is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR is set to 1, the MSB (bit 7) is sent, and then the TxD pin holds the states. 4. After the end of serial transmission, the SCK pin is held in the high state. Figure 15.14 shows an example of SCIF transmit operation. Synchronization clock Serial data LSB Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDFE TEND TXI interrupt request Data written to SCFTDR TXI and TDFE flag cleared interrupt to 0 by TXI interrupt request handler One frame Figure 15.14 Example of SCIF Transmit Operation Rev. 5.00 Mar. 15, 2007 Page 427 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Receiving Serial Data (Synchronous Mode): Figure 15.15 and 15.16 show a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode without SCIF initialization, make sure that ORER, PER, and FER are cleared to 0. [1] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Transmission/reception cannot be resumed while the ORER flag is set to 1. Yes [1] No Read RDF flag in SCFSR No Error handling [2] [2] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [3] Serial reception continuation procedure: RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End of reception [3] To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading SCFRDR. Start of reception Read ORER flag in SCLSR ORER = 1? Figure 15.15 Sample Flowchart for Receiving Serial Data (1) Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag in SCLSR to 0 End Figure 15.16 Sample Flowchart for Receiving Serial Data (2) Rev. 5.00 Mar. 15, 2007 Page 428 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) In receiving, the SCIF operates as follows: 1. The SCIF synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this check is passed, the SCIF stores the received data in SCFRDR. If the check is not passed (overrun error is detected), further reception is prevented. 3. After setting RDF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the RIE bit or REIE bit in SCSCR is also set to 1, the SCIF requests a break interrupt (BRI). Figure 15.17 shows an example of SCIF receive operation. Synchronization clock Serial data Bit 7 LSB Bit 0 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDF ORER Data read from RXI RXI SCFRDR and interrupt interrupt request RDF flag cleared request to 0 by RXI interrupt handler BRI interrupt request by overrun error One frame Figure 15.17 Example of SCIF Receive Operation Rev. 5.00 Mar. 15, 2007 Page 429 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 15.18 shows a sample flowchart for transmitting and receiving serial data simultaneously. Initialization [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR. Read the TDFE and TEND flags while they are 1, then clear them to 0. The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt. [2] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. [3] SCIF status check and receive data read: Start of transmission and reception Read TDFE flag in SCFSR No TDFE = 1? Yes Write transmit data to SCFTDR Read TDFE and TEND flags in SCFSR while they are 1, then clear them to 0 [1] Read ORER flag in SCLSR Yes [2] No Read RDF flag in SCFSR Error handling ORER = 1? Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [4] Serial transmission and reception continuation procedure: To continue serial transmission and reception, read 1 from the RDF flag and the receive data in SCFRDR, and clear the RDF flag to 0 before receiving the MSB in the current frame. Similarly, read 1 from the TDFE flag to confirm that writing is possible before transmitting the MSB in the current frame. Then write data to SCFTDR and clear the TDFE flag to 0. No RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 [3] No All data received? Yes Clear TE and RE bits in SCSCR to 0 [4] Note: When switching from a transmit operation or receive operation to simultaneous transmission and reception operations, clear the TE and RE bits to 0, and then set them simultaneously to 1. End of transmission and reception Figure 15.18 Sample Flowchart for Transmitting/Receiving Serial Data Rev. 5.00 Mar. 15, 2007 Page 430 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.5 SCIF Interrupts The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive-data-full (RXI), and break (BRI). Table 15.11 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When TXI request is enabled by TIE bit and the TDFE flag in the serial status register (SCFSR) is set to 1, a TXI interrupt request is generated. When RXI request is enabled by RIE bit and the RDF or DR flag in SCFSR is set to 1, an RXI interrupt request is generated. The RXI interrupt request caused by DR flag is generated only in asynchronous mode. When BRI request is enabled by RIE bit or REIE bit and the BRK flag in SCFSR or ORER flag in SCLSR is set to 1, a BRI interrupt request is generated. When ERI request is enabled by RIE bit or REIE bit and the ER flag in SCFCR is set to 1, an ERI interrupt request is generated. When the RIE bit is set to 0 and the REIE bit is set to 1, SCIF request ERI interrupt and BRI interrupt without requesting RXI interrupt. The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that there is receive data in SCFRDR. Table 15.11 SCIF Interrupt Sources Interrupt Source ERI RXI BRI TXI Description Interrupt initiated by receive error (ER) Interrupt Enable Bit RIE or REIE Priority on Reset Release High Interrupt initiated by receive data FIFO full (RDF) or RIE data ready (DR) Interrupt initiated by break (BRK) or overrun error (ORER) Interrupt initiated by transmit FIFO data empty (TDFE) RIE or REIE TIE Low Rev. 5.00 Mar. 15, 2007 Page 431 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.6 Serial Port Register (SCSPTR) and SCIF Pins The relationship between SCSPTR and the SCIF pins is shown in figures 15.19 to 15.23. Reset R Q D RTSIO C SPTRW Reset RTS R Q D RTSDT C SPTRW Modem control enable signal* RTS signal Bit 6 Bit 7 Internal data bus SPTRR SPTRW: SPTRR: Note: SCSPTR write SCSPTR read * The modem control function is specified for the RTS pin by setting the MCE bit in SCFCR. Figure 15.19 RTSIO Bit, RTSDT Bit, and RTS Pin Rev. 5.00 Mar. 15, 2007 Page 432 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Reset R Q D CTSIO C SPTRW Reset R Q D CTSDT C SPTRW Bit 4 Bit 5 Internal data bus CTS Modem control enable signal* CTS signal SPTRR SPTRW: SPTRR: Note: SCSPTR write SCSPTR read * The modem control function is specified for the CTS pin by setting the MCE bit in SCFCR. Figure 15.20 CTSIO Bit, CTSDT Bit, and CTS Pin Rev. 5.00 Mar. 15, 2007 Page 433 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Reset R Q D SCKIO C SPTRW Reset SCK2 R Q D SCKDT C SPTRW Clock output enable signal* Sirial clock output signal* Serial clock input signal* Serial input enable signal* Bit 2 Internal data bus Bit 3 SPTRR SPTRW: SPTRR: Note: SCSPTR write SCSPTR read * These signals control the SCK pin according to the settings of the C/A bit in SCSMR and bits CKE1 and CKE0 in SCSCR. Figure 15.21 SCKIO Bit, SCKDT Bit, and SCK Pin Reset R Q D SPBIO C SPTRW Reset TxD R Q D SPBDT C SPTRW Transmit enable signal Serial transmit data Bit 0 Bit 1 Internal data bus SPTRW: SCSPTR write Figure 15.22 SPBIO Bit, SPBDT Bit, and TxD Pin Rev. 5.00 Mar. 15, 2007 Page 434 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) RxD Serial receive data Internal data bus Bit 0 SPTRR SPTRR: SCSPTR read Figure 15.23 SPBDT Bit and RxD Pin Rev. 5.00 Mar. 15, 2007 Page 435 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 15.7 Usage Notes Note the following when using the SCIF. 1. SCFTDR Writing and TDFE Flag The TDFE flag in the serial status register (SCFSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO data count register (SCFDR). 2. SCFRDR Reading and RDF Flag The RDF flag in the serial status register (SCFSR) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR is equal to or greater than the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after all the receive data has been read. The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register (SCFDR). 3. Break Detection and Processing Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of receive data to SCFRDR is halted in the break state, the SCIF receiver continues to operate. Rev. 5.00 Mar. 15, 2007 Page 436 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 4. Sending a Break Signal The I/O condition and level of the TxD pin are determined by the SPBIO and SPBDT bits in the serial port register (SCSPTR). This feature can be used to send a break signal. Until TE bit is set to 1 (enabling transmission) after initializing, TxD pin does not work. During the period, mark status is performed by SPBDT bit. Therefore, the SPBIO and SPBDT bits should be set to 1 (high level output). To send a break signal during serial transmission, clear the SPBDT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD pin. 5. Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 15.24. 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 Base clock –7.5 clocks +7.5 clocks Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit D0 D1 Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode Rev. 5.00 Mar. 15, 2007 Page 437 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: M = (0.5 D - 0.5 1 ) = (L - 0.5) F (1+F) × 100 % 2N N Where: M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Equation 2: When D = 0.5 and F = 0: M = (0.5 – 1/(2 × 16)) × 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. 6. Prohibited Multiple Pin Allocation for Channel 1 Although signals SCK1, RxD1, and TxD1 can be respectively assigned to multiple pins of PD4 or PE20, PD3 or PE19, and PD2 or PE18, either of them must be selected. For example, if signal SCK1 is assigned to both pins PD4 and PE20, correct operation of the SCIF is not guaranteed. 7. Status of the TxD and RTS Pins When the TE Bit is Cleared The TxDi (i = 0, 1, 2) and RTSj (j = 0, 1) pins usually function as output pins during serial communication. However, even if these functions are selected by the pin function controller (PFC), the internal weak keeper drives the pins to unstable levels as long as the TE bit in SCSCRi (i = 0, 1, 2) is cleared. To make these pins always function as output pins (regardless of the value of the TE bit), set SCSPTRi (i = 0, 1, 2) and PFC in the following order. a. Set the SPBIO and SPBDT bits in SCSPTRi (i = 0, 1, 2). Set the RTSIO and RTSDT bits in SCSPTRj (j = 0, 1). b. Select the TxDi (i = 0, 1, 2) and RTSj (j = 0, 1) pins with the PFC. 8. Interval from when the TE bit in SCSCR is Set to 1 until a Start Bit is Transmitted in Asynchronous Mode In the SCIF included in former products, a start bit is transmitted after the internal equivalent to one frame. In the SCIF included in this product, however, a start bit is transmitted directly after the TE bit is set to 1. Rev. 5.00 Mar. 15, 2007 Page 438 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) 9. Clear Timing of the FER or PER Bits when the DMAC Saves the Receive Data in Asynchronous Mode The FER or PER bits in SCFSR are set when data including a framing error or parity error is received in asynchronous mode, whereas cleared when the corresponding data is read from SCFRDR. Therefore, when data with an error is received while the DMAC is set to save the receive data automatically, the receive-error interrupt is accepted after the DMAC reads the corresponding data. As a result, the CPU cannot check the FER or PER bits. To prevent this defect, the RTRG[1:0] bits in SCFCR should be set to the higher number to delay the DMAC call timing. This enables the CPU to check the FER or PER bits in the receive-error interrupt routine, prior to the DMAC to read the error data. Rev. 5.00 Mar. 15, 2007 Page 439 of 794 REJ09B0237-0500 Section 15 Serial Communication Interface with FIFO (SCIF) Rev. 5.00 Mar. 15, 2007 Page 440 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Section 16 Serial I/O with FIFO (SIOF) This LSI includes a clock-synchronized serial I/O module with FIFO (SIOF) that comprises one channel. The SIOF can perform serial communication with a serial peripheral interface bus (SPI). 16.1 Features • Serial transfer  16-stage 32-bit FIFOs (independent transmission and reception)  Supports 8-bit data/16-bit data/16-bit stereo audio input and output  MSB first for data transmission  Supports a maximum of 48-kHz sampling rate  Synchronization by either frame synchronization pulse or left/right channel switch  Supports CODEC control data interface  Connectable to linear, audio, or A-Law or µ-Law CODEC chip  Supports both master and slave modes • Serial clock  An external pin input or internal clock (Pφ) can be selected as the clock source. • Interrupts: One type • DMA transfer  Supports DMA transmission and reception by a transfer request for transmission and reception • SPI mode  Fixed master mode can perform the full-duplex communication with the SPI slave devices continuously.  Selects the falling/rising edge of the SCK as data sampling.  Selects the clock phase of the SCK as a transmit timing.  Selects one slave device.  The length of transmit/receive data is fixed to 8 bits. Rev. 5.00 Mar. 15, 2007 Page 441 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Figure 16.1 shows a block diagram of the SIOF. SIOF interrupt request Bus interface Peripheral bus Control registers Transmit FIFO (32 bits x16 stages) Receive FIFO (32 bits x16 stages) Pφ Transmit control data Receive control data Baud rate generator 1/nMCLK Timing control P/S S/P SIOFMCLK SIOFSCK SIOFSYNC SIOFTxD SIOFRxD Figure 16.1 Block Diagram of SIOF Rev. 5.00 Mar. 15, 2007 Page 442 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.2 Input/Output Pins The pin configuration in this module is shown in table 16.1. Table 16.1 Pin Configuration Channel 0 Pin Name SIOF0_MCLK SIOF0_SCK (SCK0) SIOF0_SYNC (SS00) Abbreviation* SIOFMCLK SIOFSCK (SCK) I/O Input I/O Function Master clock input Serial clock (common to transmission/reception) In SPI mode, fixed to output. SIOFSYNC (SS0) I/O Frame synchronous signal (common to transmission/reception) In SPI mode, fixed to output, and selects slave device 0. SIOF0_TxD (MOSI0) SIOF0_RxD (MISO0) Note: * SIOFTxD (MOSI) Output SIOFRxD (MISO) Input Transmit data Receive data The pins are abbreviated as SIOFMCLK, SIOFSCK, SIOFSYNC, SIOFTxD, and SIOFRxD in the following descriptions. In SPI mode, the pins are called SCK, SS0, MOSI, and MISO. Rev. 5.00 Mar. 15, 2007 Page 443 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.3 Register Descriptions The SIOF has the following registers. For the addresses of these registers and the register states in each operating state, refer to section 24, List of Registers. In the register descriptions following this section, channel numbers are omitted. Channel 0: • • • • • • • • • • • • • • Mode register_0 (SIMDR_0) Control register_0 (SICTR_0) Transmit data register_0 (SITDR_0) Receive data register_0 (SIRDR_0) Transmit control data register_0 (SITCR_0) Receive control data register_0 (SIRCR_0) Status register_0 (SISTR_0) Interrupt enable register_0 (SIIER_0) FIFO control register_0 (SIFCTR_0) Clock select register_0 (SISCR_0) Transmit data assign register_0 (SITDAR_0) Receive data assign register_0 (SIRDAR_0) Control data assign register_0 (SICDAR_0) SPI control register_0 (SPICR_0) Rev. 5.00 Mar. 15, 2007 Page 444 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.3.1 Mode Register (SIMDR) SIMDR is a 16-bit readable/writable register that sets the SIOF operating mode. Bit 15 14 Bit Name TRMD1 TRMD0 Initial Value 1 0 R/W R/W R/W Description Transfer Mode 1, 0 Select transfer mode. For details, see table 16.2. 00: Slave mode 1 01: Slave mode 2 10: Master mode 1 11: Master mode 2 13 SYNCAT 0 R/W SIOFSYNC Pin Valid Timing Indicates the position of the SIOFSYNC signal to be output as a synchronization pulse. 0: At the start-bit data of frame 1: At the last-bit data of slot 12 REDG 0 R/W Receive Data Sampling Edge 0: The SIOFRxD signal is sampled at the falling edge of SIOFSCK (The SIOFTxD signal is transmitted at the rising edge of SIOFSCK.) 1: The SIOFRxD signal is sampled at the rising edge of SIOFSCK (The SIOFTxD signal is transmitted at the falling edge of SIOFSCK.) Note: This bit is valid only in master mode. Rev. 5.00 Mar. 15, 2007 Page 445 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 11 10 9 8 Bit Name FL3 FL2 FL1 FL0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Frame Length 3 to 0 00xx: Data length is 8 bits and frame length is 8 bits. 0100: Data length is 8 bits and frame length is 16 bits. 0101: Data length is 8 bits and frame length is 32 bits. 0110: Data length is 8 bits and frame length is 64 bits. 0111: Data length is 8 bits and frame length is 128 bits. 10xx: Data length is 16 bits and frame length is 16 bits. 1100: Data length is 16 bits and frame length is 32 bits. 1101: Data length is 16 bits and frame length is 64 bits. 1110: Data length is 16 bits and frame length is 128 bits. 1111: Data length is 16 bits and frame length is 256 bits. Note: When data length is specified as 8 bits, control data cannot be transmitted or received. x: Don't care 7 TXDIZ 0 R/W SIOFTxD Pin Output when Transmission is Invalid* 0: High output (1 output) when invalid 1: High-impedance state when invalid Note: Invalid means when disabled, and when a slot that is not assigned as transmit data or control data is being transmitted. 6 RCIM 0 R/W Receive Control Data Interrupt Mode 0: Sets the RCRDY bit in SISTR when the contents of SIRCR change. 1: Sets the RCRDY bit in SISTR each time when the SIRCR receives the control data. 5 SYNCAC 0 R/W SIOFSYNC Pin Polarity Valid when the SIOFSYNC signal is output as synchronous pulse in master mode. 0: Active-high 1: Active-low Rev. 5.00 Mar. 15, 2007 Page 446 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 4 Bit Name SYNCDL Initial Value 0 R/W R/W Description Data Pin Bit Delay for SIOFSYNC Pin Valid when the SIOFSYNC signal is output as synchronous pulse. Only one-bit delay is valid for transmission in slave mode. 0: No bit delay 1: 1-bit delay 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Table 16.2 Operation in Each Transfer Mode Transfer Mode Slave mode 1 Slave mode 2 Master mode 1 Master mode 2 Note: * Master/Slave Slave Slave Master Master SIOFSYNC Synchronous pulse Synchronous pulse Synchronous pulse L/R No Bit Delay SYNCDL bit Control Data Method* Slot position Secondary FS Slot position Not supported The control data method is valid only when the FL3 to FL0 bits are specified as 1xxx. (x: Don’t care.) Rev. 5.00 Mar. 15, 2007 Page 447 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.3.2 Control Register (SICTR) SICTR is a 16-bit readable/writable register that sets the SIOF operating state. Bit 15 Bit Name SCKE Initial Value 0 R/W R/W Description Serial Clock Output Enable This bit is valid in master mode. 0: Disables the SIOFSCK output (outputs 0) 1: Enables the SIOFSCK output • If this bit is set to 1, the SIOF initializes the baud rate generator and initiates the operation. At the same time, the SIOF outputs the clock generated by the baud rate generator to the SIOFSCK pin. This bit is initialized in module stop mode. 14 FSE 0 R/W Frame Synchronous Signal Output Enable This bit is valid in master mode. 0: Disables the SIOFSYNC output (outputs 0) 1: Enables the SIOFSYNC output • If this bit is set to 1, the SIOF initializes the frame counter and initiates the operation. This bit is initialized in module stop mode. 13 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 448 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 9 Bit Name TXE Initial Value 0 R/W R/W Description Transmit Enable 0: Disables data transmission from the SIOFTxD pin 1: Enables data transmission from the SIOFTxD pin • • This bit setting becomes valid at the start of the next frame (at the rising edge of the SIOFSYNC signal). When the 1 setting for this bit becomes valid, the SIOF issues a transmit transfer request according to the setting of the TFWM bit in SIFCTR. When transmit data is stored in the transmit FIFO, transmission of data from the SIOFTxD pin begins. This bit is initialized upon a transmit reset. • 8 RXE 0 R/W This bit is initialized in module stop mode. Receive Enable 0: Disables data reception from SIOFRxD 1: Enables data reception from SIOFRxD • • This bit setting becomes valid at the start of the next frame (at the rising edge of the SIOFSYNC signal). When the 1 setting for this bit becomes valid, the SIOF begins the reception of data from the SIOFRxD pin. When receive data is stored in the receive FIFO, the SIOF issues a reception transfer request according to the setting of the RFWM bit in SIFCTR. This bit is initialized upon receive reset. • 7 to 2  All 0 R This bit is initialized in module stop mode. Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 449 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 1 Bit Name TXRST Initial Value 0 R/W R/W Description Transmit Reset 0: Does not reset transmit operation 1: Resets transmit operation • This bit setting becomes valid immediately. This bit should be cleared to 0 before setting the register to be initialized. When the 1 setting for this bit becomes valid, the SIOF immediately sets transmit data from the SIOFTxD pin to 1, and initializes the transmit data register and transmit-related status. The following are initialized.  SITDR  SITCR  Transmit FIFO write pointer and read pointer  TCRDY, TFEMP, and TDREQ bits in SISTR  TXE bit • 0 RXRST 0 R/W Receive Reset 0: Does not reset receive operation 1: Resets receive operation • This bit setting becomes valid immediately. This bit should be cleared to 0 before setting the register to be initialized. When the 1 setting for this bit becomes valid, the SIOF immediately disables reception from the SIOFRxD pin, and initializes the receive data register and receive-related status. The following are initialized.  SIRDR  SIRCR  Receive FIFO write pointer and read pointer  RCRDY, RFFUL, and RDREQ bits in SISTR  RXE bit • Rev. 5.00 Mar. 15, 2007 Page 450 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.3.3 Transmit Data Register (SITDR) SITDR is a 32-bit write-only register that specifies the SIOF transmit data. SITDR is initialized by the conditions specified in section 23, List of Registers, or by a transmit reset caused by the TXRST bit in SICTR. SITDR is initialized in module stop mode. Bit 31 to 16 Bit Name SITDL 15 to 0 Initial Value All 0 R/W W Description Left-Channel Transmit Data Specify data to be output from the SIOFTxD pin as leftchannel data. The position of the left-channel data in the transmit frame is specified by the TDLA bit in SITDAR. • 15 to 0 SITDR 15 to 0 All 0 W These bits are valid only when the TDLE bit in SITDAR is set to 1. Right-Channel Transmit Data Specify data to be output from the SIOFTxD pin as right-channel data. The position of the right-channel data in the transmit frame is specified by the TDRA bit in SITDAR. • These bits are valid only when the TDRE bit and TLREP bit in SITDAR are set to 1 and cleared to 0, respectively. Rev. 5.00 Mar. 15, 2007 Page 451 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.3.4 Receive Data Register (SIRDR) SIRDR is a 32-bit read-only register that reads receive data of the SIOF. SIRDR stores data in the receive FIFO and is initialized by the conditions specified in section 23, List of Registers, or by a receive reset caused by the RXRST bit in SICTR. Bit 31 to 16 Bit Name SIRDL 15 to 0 Initial Value All 0 R/W R Description Left-Channel Receive Data Store data received from the SIOFRxD pin as leftchannel data. The position of the left-channel data in the receive frame is specified by the RDLA bit in SIRDAR. • 15 to 0 SIRDR 15 to 0 All 0 R These bits are valid only when the RDLE bit in SIRDAR is set to 1. Right-Channel Receive Data Store data received from the SIOFRxD pin as rightchannel data. The position of the right-channel data in the receive frame is specified by the RDRA bit in SIRDAR. • These bits are valid only when the RDRE bit in SIRDAR is set to 1. Rev. 5.00 Mar. 15, 2007 Page 452 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.3.5 Transmit Control Data Register (SITCR) SITCR is a 32-bit readable/writable register that specifies transmit control data of the SIOF. SITCR can be specified only when the FL3 to FL0 bits in SIMDR are specified as 1xxx (x: Don't care.). SITCR is initialized in module stop mode. Bit 31 to 16 Bit Name SITC0 15 to 0 Initial Value All 0 R/W R/W Description Control Channel 0 Transmit Data Specify data to be output from the SIOFTxD pin as control channel 0 transmit data. The position of the control channel 0 data in the transmit or receive frame is specified by the CD0A bit in SICDAR. • 15 to 0 SITC1 15 to 0 All 0 R/W These bits are valid only when the CD0E bit in SICDAR is set to 1. Control Channel 1 Transmit Data Specify data to be output from the SIOFTxD pin as control channel 1 transmit data. The position of the control channel 1 data in the transmit or receive frame is specified by the CD1A bit in SICDAR. • These bits are valid only when the CD1E bit in SICDAR is set to 1. Rev. 5.00 Mar. 15, 2007 Page 453 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.3.6 Receive Control Data Register (SIRCR) SIRCR is a 32-bit readable/writable register that stores receive control data of the SIOF. SIRCR can be specified only when the FL3 to FL0 bits in SIMDR are specified as 1xxx (x: Don't care.). Bit 31 to 16 Bit Name SIRC0 15 to 0 Initial Value All 0 R/W R Description Control Channel 0 Receive Data Store data received from the SIOFRxD pin as control channel 0 receive data. The position of the control channel 0 data in the transmit or receive frame is specified by the CD0A bit in SICDAR. • 15 to 0 SIRC1 15 to 0 All 0 R These bits are valid only when the CD0E bit in SICDAR is set to 1. Control Channel 1 Receive Data Store data received from the SIOFRxD pin as control channel 1 receive data. The position of the control channel 1 data in the transmit or receive frame is specified by the CD1A bit in SICDAR. • These bits are valid only when the CD1E bit in SICDAR is set to 1. Rev. 5.00 Mar. 15, 2007 Page 454 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.3.7 Status Register (SISTR) SISTR is a 16-bit read-only register that shows the SIOF state. Each bit in this register becomes an SIOF interrupt source when the corresponding bit in SIIER is set to 1. SISTR is initialized in module stop mode. Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 TCRDY 0 R Transmit Control Data Ready 0: Indicates that a write to SITCR is disabled 1: Indicates that a write to SITCR is enabled • If SITCR is written when this bit is cleared to 0, SITCR is over-written and the previous contents of SITCR are not output from the SIOFTxD pin. This bit is valid when the TXE bit in SITCR is set to 1. This bit indicates a state of the SIOF. If SITCR is written, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. • • • 13 TFEMP 0 R Transmit FIFO Empty 0: Indicates that transmit FIFO is not empty 1: Indicates that transmit FIFO is empty • • • This bit is valid when the TXE bit in SICTR is 1. This bit indicates a state; if SITDR is written, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. Rev. 5.00 Mar. 15, 2007 Page 455 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 12 Bit Name TDREQ Initial Value 0 R/W R Description Transmit Data Transfer Request 0: Indicates that the size of empty space in the transmit FIFO does not exceed the size specified by the TFWM bit in SIFCTR. 1: Indicates that the size of empty space in the transmit FIFO exceeds the size specified by the TFWM bit in SIFCTR. A transmit data transfer request is issued when the empty space in the transmit FIFO exceeds the size specified by the TFWM bit in SIFCTR. When using transmit data transfer through the DMAC, this bit is always cleared by one DMAC access. After DMAC access, when conditions for setting this bit are satisfied, the SIOF again indicates 1 for this bit. • • This bit is valid when the TXE bit in SICTR is 1. This bit indicates a state; if the size of empty space in the transmit FIFO is less than the size specified by the TFWM bit in SIFCTR, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. • 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 RCRDY 0 R Receive Control Data Ready 0: Indicates that the SIRCR stores no valid data. 1: Indicates that the SIRCR stores valid data. • • • • If SIRCR is written when this bit is set to 1, SIRCR is modified by the latest data. This bit is valid when the RXE bit in SICTR is set to 1. This bit indicates a state of the SIOF. If SIRCR is read, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. Rev. 5.00 Mar. 15, 2007 Page 456 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 9 Bit Name RFFUL Initial Value 0 R/W R Description Receive FIFO Full 0: Receive FIFO not full 1: Receive FIFO full • • • This bit is valid when the RXE bit in SICTR is 1. This bit indicates a state; if SIRDR is read, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. 8 RDREQ 0 R Receive Data Transfer Request 0: Indicates that the size of valid space in the receive FIFO does not exceed the size specified by the RFWM bit in SIFCTR. 1: Indicates that the size of valid space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR. A receive data transfer request is issued when the valid space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR. When using receive data transfer through the DMAC, this bit is always cleared by one DMAC access. After DMAC access, when conditions for setting this bit are satisfied, the SIOF again indicates 1 for this bit. • • This bit is valid when the RXE bit in SICTR is 1. This bit indicates a state; if the size of valid space in the receive FIFO is less than the size specified by the RFWM bit in SIFCTR, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. • 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 457 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 5 Bit Name SAERR Initial Value 0 R/W R/W Description Slot Assign Error 0: Indicates that no slot assign error occurs 1: Indicates that a slot assign error occurs A slot assign error occurs when the specifications in SITDAR, SIRDAR, and SICDAR overlap. If a slot assign error occurs, the SIOF does not transmit data to the SIOFTxD pin and does not receive data from the SIOFRxD pin. Note that the SIOF does not clear the TXE bit or RXE bit in SICTR at a slot assign error. • • • This bit is valid when the TXE bit or RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. 4 FSERR 0 R/W Frame Synchronization Error 0: Indicates that no frame synchronization error occurs 1: Indicates that a frame synchronization error occurs A frame synchronization error occurs when the next frame synchronization timing appears before the previous data or control data transfers have been completed. If a frame synchronization error occurs, the SIOF performs transmission or reception for slots that can be transferred. • • • This bit is valid when the TXE or RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. Rev. 5.00 Mar. 15, 2007 Page 458 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 3 Bit Name TFOVF Initial Value 0 R/W R/W Description Transmit FIFO Overflow 0: No transmit FIFO overflow 1: Transmit FIFO overflow A transmit FIFO overflow means that there has been an attempt to write to SITDR when the transmit FIFO is full. When a transmit FIFO overflow occurs, the SIOF indicates overflow, and writing is invalid. • • • This bit is valid when the TXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. 2 TFUDF 0 R/W Transmit FIFO Underflow 0: No transmit FIFO underflow 1: Transmit FIFO underflow A transmit FIFO underflow means that loading for transmission has occurred when the transmit FIFO is empty. When a transmit FIFO underflow occurs, the SIOF repeatedly sends the previous transmit data. • • • This bit is valid when the TXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. Rev. 5.00 Mar. 15, 2007 Page 459 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 1 Bit Name RFUDF Initial Value 0 R/W R/W Description Receive FIFO Underflow 0: No receive FIFO underflow 1: Receive FIFO underflow A receive FIFO underflow means that reading of SIRDR has occurred when the receive FIFO is empty. When a receive FIFO underflow occurs, the value of data read from SIRDR is not guaranteed. • • • This bit is valid when the RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. 0 RFOVF 0 R/W Receive FIFO Overflow 0: No receive FIFO overflow 1: Receive FIFO overflow A receive FIFO overflow means that writing has occurred when the receive FIFO is full. When a receive FIFO overflow occurs, the SIOF indicates overflow, and receive data is lost. • • • This bit is valid when the RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. Rev. 5.00 Mar. 15, 2007 Page 460 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.3.8 Interrupt Enable Register (SIIER) SIIER is a 16-bit readable/writable register that enables the issue of SIOF interrupts. When each bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, the SIOF issues an interrupt. Bit 15 Bit Name TDMAE Initial Value 0 R/W R/W Description Transmit Data DMA Transfer Request Enable Transmits an interrupt as an interrupt to the CPU/DMA transfer request. The TDREQE bit can be set as transmit interrupts. 0: Used as a CPU interrupt 1: Used as a DMA transfer request to the DMAC 14 TCRDYE 0 R/W Transmit Control Data Ready Enable 0: Disables interrupts due to transmit control data ready 1: Enables interrupts due to transmit control data ready 13 TFEMPE 0 R/W Transmit FIFO Empty Enable 0: Disables interrupts due to transmit FIFO empty 1: Enables interrupts due to transmit FIFO empty 12 TDREQE 0 R/W Transmit Data Transfer Request Enable 0: Disables interrupts due to transmit data transfer requests 1: Enables interrupts due to transmit data transfer requests 11 RDMAE 0 R/W Receive Data DMA Transfer Request Enable Transmits an interrupt as an interrupt to the CPU/DMA transfer request. The RDREQE bit can be set as receive interrupts. 0: Used as a CPU interrupt 1: Used as a DMA transfer request to the DMAC 10 RCRDYE 0 R/W Receive Control Data Ready Enable 0: Disables interrupts due to receive control data ready 1: Enables interrupts due to receive control data ready Rev. 5.00 Mar. 15, 2007 Page 461 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 9 Bit Name RFFULE Initial Value 0 R/W R/W Description Receive FIFO Full Enable 0: Disables interrupts due to receive FIFO full 1: Enables interrupts due to receive FIFO full 8 RDREQE 0 R/W Receive Data Transfer Request Enable 0: Disables interrupts due to receive data transfer requests 1: Enables interrupts due to receive data transfer requests 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 SAERRE 0 R/W Slot Assign Error Enable 0: Disables interrupts due to slot assign error 1: Enables interrupts due to slot assign error 4 FSERRE 0 R/W Frame Synchronization Error Enable 0: Disables interrupts due to frame synchronization error 1: Enables interrupts due to frame synchronization error 3 TFOVFE 0 R/W Transmit FIFO Overflow Enable 0: Disables interrupts due to transmit FIFO overflow 1: Enables interrupts due to transmit FIFO overflow 2 TFUDFE 0 R/W Transmit FIFO Underflow Enable 0: Disables interrupts due to transmit FIFO underflow 1: Enables interrupts due to transmit FIFO underflow 1 RFUDFE 0 R/W Receive FIFO Underflow Enable 0: Disables interrupts due to receive FIFO underflow 1: Enables interrupts due to receive FIFO underflow 0 RFOVFE 0 R/W Receive FIFO Overflow Enable 0: Disables interrupts due to receive FIFO overflow 1: Enables interrupts due to receive FIFO overflow Rev. 5.00 Mar. 15, 2007 Page 462 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.3.9 FIFO Control Register (SIFCTR) SIFCTR is a 16-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer. Bit 15 14 13 Bit Name TFWM2 TFWM1 TFWM0 Initial Value 0 0 0 R/W R/W R/W R/W Description Transmit FIFO Watermark 000: Issue a transfer request when 16 stages of the transmit FIFO are empty. 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Issue a transfer request when 12 or more stages of the transmit FIFO are empty. 101: Issue a transfer request when 8 or more stages of the transmit FIFO are empty. 110: Issue a transfer request when 4 or more stages of the transmit FIFO are empty. 111: Issue a transfer request when 1 or more stages of transmit FIFO are empty. • • 12 11 10 9 8 TFUA4 TFUA3 TFUA2 TFUA1 TFUA0 1 0 0 0 0 R R R R R A transfer request to the transmit FIFO is issued by the TDREQE bit in SISTR. The transmit FIFO is always used as 16 stages of the FIFO regardless of these bit settings. Transmit FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'00000 (full) to B'10000 (empty). Rev. 5.00 Mar. 15, 2007 Page 463 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 7 6 5 Bit Name RFWM2 RFWM1 RFWM0 Initial Value 0 0 0 R/W R/W R/W R/W Description Receive FIFO Watermark 000: Issue a transfer request when 1 stage or more of the receive FIFO are valid. 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Issue a transfer request when 4 or more stages of the receive FIFO are valid. 101: Issue a transfer request when 8 or more stages of the receive FIFO are valid. 110: Issue a transfer request when 12 or more stages of the receive FIFO are valid. 111: Issue a transfer request when 16 stages of the receive FIFO are valid. • • A transfer request to the receive FIFO is issued by the RDREQE bit in SISTR. The receive FIFO is always used as 16 stages of the FIFO regardless of these bit settings. 4 3 2 1 0 RFUA4 RFUA3 RFUA2 RFUA1 RFUA0 0 0 0 0 0 R R R R R Receive FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'00000 (empty) to B'10000 (full). Rev. 5.00 Mar. 15, 2007 Page 464 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.3.10 Clock Select Register (SISCR) SISCR is a 16-bit readable/writable register that sets the serial clock generation conditions for the master clock. SISCR can be specified when the TRMD1 and TRMD0 bits in SIMDR are specified as B'10 or B'11. Bit 15 Bit Name MSSEL Initial Value 1 R/W R/W Description Master Clock Source Selection 0: Uses the input signal of the SIOFMCLK pin as the master clock 1: Uses Pφ as the master clock The master clock is the clock input to the baud rate generator. 14 MSIMM 1 R/W Master Clock Direct Selection 0: Uses the output clock of the baud rate generator as the serial clock 1: Uses the master clock itself as the serial clock 13  0 R Reserved This bit is always read as 0. The write value should always be 0. 12 11 10 9 8 7 to 3 BRPS4 BRPS3 BRPS2 BRPS1 BRPS0  0 0 0 0 0 All 0 R/W R/W R/W R/W R/W R Prescalar Setting Set the master clock division ratio according to the count value of the prescalar of the baud rate generator. The range of settings is from B'00000 (× 1/1) to B'11111 (× 1/32). Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 465 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 2 1 0 Bit Name BRDV2 BRDV1 BRDV0 Initial Value 0 0 0 R/W R/W R/W R/W Description Baud rate generator’s Division Ratio Setting Set the frequency division ratio for the output stage of the baud rate generator. 000: Prescalar output × 1/2 001: Prescalar output × 1/4 010: Prescalar output × 1/8 011: Prescalar output × 1/16 100: Prescalar output × 1/32 101: Setting prohibited 110: Setting prohibited 111: Prescalar output × 1/1* The final frequency division ratio of the baud rate generator is determined by BRPS × BRDV (maximum 1/1024). Note: * This setting is valid only when the BRPS4 to BRPS0 bits are set to B'00000. 16.3.11 Transmit Data Assign Register (SITDAR) SITDAR is a 16-bit readable/writable register that specifies the position of the transmit data in a frame (slot number). Bit 15 Bit Name TDLE Initial Value 0 R/W R/W Description Transmit Left-Channel Data Enable 0: Disables left-channel data transmission 1: Enables left-channel data transmission 14 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 466 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 11 10 9 8 Bit Name TDLA3 TDLA2 TDLA1 TDLA0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Transmit Left-Channel Data Assigns 3 to 0 Specify the position of left-channel data in a transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited • Transmit data for the left channel is specified in the SITDL bit in SITDR. 7 TDRE 0 R/W Transmit Right-Channel Data Enable 0: Disables right-channel data transmission 1: Enables right-channel data transmission 6 TLREP 0 R/W Transmit Left-Channel Repeat 0: Transmits data specified in the SITDR bit in SITDR as right-channel data 1: Repeatedly transmits data specified in the SITDL bit in SITDR as right-channel data • • This bit setting is valid when the TDRE bit is set to 1. When this bit is set to 1, the SITDR settings are ignored. 5, 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 2 1 0 TDRA3 TDRA2 TDRA1 TDRA0 0 0 0 0 R/W R/W R/W R/W Transmit Right-Channel Data Assigns 3 to 0 Specify the position of right-channel data in a transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited • Transmit data for the right channel is specified in the SITDR bit in SITDR. Rev. 5.00 Mar. 15, 2007 Page 467 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.3.12 Receive Data Assign Register (SIRDAR) SIRDAR is a 16-bit readable/writable register that specifies the position of the receive data in a frame (slot number). Bit 15 Bit Name RDLE Initial Value 0 R/W R/W Description Receive Left-Channel Data Enable 0: Disables left-channel data reception 1: Enables left-channel data reception 14 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 10 9 8 RDLA3 RDLA2 RDLA1 RDLA0 0 0 0 0 R/W R/W R/W R/W Receive Left-Channel Data Assigns 3 to 0 Specify the position of left-channel data in a receive frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited • 7 RDRE 0 R/W Receive data for the left channel is stored in the SIRDL bit in SIRDR. Receive Right-Channel Data Enable 0: Disables right-channel data reception 1: Enables right-channel data reception 6 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 2 1 0 RDRA3 RDRA2 RDRA1 RDRA0 0 0 0 0 R/W R/W R/W R/W Receive Right-Channel Data Assigns 3 to 0 Specify the position of right-channel data in a receive frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited • Receive data for the right channel is stored in the SIRDR bit in SIRDR. Rev. 5.00 Mar. 15, 2007 Page 468 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.3.13 Control Data Assign Register (SICDAR) SICDAR is a 16-bit readable/writable register that specifies the position of the control data in a frame (slot number). SICDAR can be specified only when the FL bit in SIMDR is specified as 1xxx (x: Don't care.). Bit 15 Bit Name CD0E Initial Value 0 R/W R/W Description Control Channel 0 Data Enable 0: Disables transmission and reception of control channel 0 data 1: Enables transmission and reception of control channel 0 data 14 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 10 9 8 CD0A3 CD0A2 CD0A1 CD0A0 0 0 0 0 R/W R/W R/W R/W Control Channel 0 Data Assigns 3 to 0 Specify the position of control channel 0 data in a receive or transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited • • 7 CD1E 0 R/W Transmit data for the control channel 0 data is specified in the SITD0 bit in SITCR. Receive data for the control channel 0 data is stored in the SIRD0 bit in SIRCR. Control Channel 1 Data Enable 0: Disables transmission and reception of control channel 1 data 1: Enables transmission and reception of control channel 1 data 6 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 469 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 3 2 1 0 Bit Name CD1A3 CD1A2 CD1A1 CD1A0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Control Channel 1 Data Assigns 3 to 0 Specify the position of control channel 1 data in a receive or transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited • • Transmit data for the control channel 1 data is specified in the SITD1 bit in SITCR. Receive data for the control channel 1 data is stored in the SIRD1 bit in SIRCR. 16.3.14 SPI Control Register (SPICR) SPICR is a 16-bit readable/writable register that specifies the operating mode of the SPI. Bit 15 Bit Name SPIM Initial Value 0 R/W R/W Description SPI Mode Selects the SIOF operating mode. 0: Operates as the SIOF. 1: The SIOF operates in master mode of the SPI. 14  0 R Reserved This bit is always read as 0. The write value should always be 0. 13 CPHA 0 R/W SPI Clock Phase Selects the SPI clock phase. 0: Samples data at the first edge of the SCK. 1: Samples data at the second edge of the SCK. 12 CPOL 0 R/W SPI Clock Polarity Selects the SPI clock polarity. 0: The SCK is high-active, and goes low in the idle state. 1: The SCK is low-active, and goes high in the idle state. Rev. 5.00 Mar. 15, 2007 Page 470 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 9  8 SS0E 0 R/W Slave Device 0 (SS0) Enable 0: Not select slave device 0. 1: Selects slave device 0. 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 4 SSAST1 SSAST0 0 0 R/W R/W Setting of SS Assert Set the setup timing of the SS for the SCK. • CPHA = 0 SSAST[1:0] 00 01 10 11 • CPHA = 1 SSAST[1:0] 00 01 10 11 SS Setup 0 clock 0.5 clock 1 clock 1.5 clock SS Hold 0.5 clock 1 clock 1.5 clock 2 clock SS Setup 0.5 clock 1 clock 1.5 clock 2 clock SS Hold 0 clock 0.5 clock 1 clock 1.5 clock (Unit: SCK clock) (Unit: SCK clock) 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 471 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Bit 1 0 Bit Name FLD1 FLD0 Initial Value 0 0 R/W R/W R/W Description Frame Delay Specify the minimum time of the idle state between frames in terms of the clock number of the SCK. 00: Not delay. The continuous communication of the SPI is performed when the SS pin asserts low continuously. 01: Delay for 1 clock of the SCK. 10: Delay for 2 clocks of the SCK. 11: Delay for 3 clocks of the SCK. Rev. 5.00 Mar. 15, 2007 Page 472 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.4 16.4.1 Operation Serial Clocks Master/Slave Modes: The following two modes are available as the SIOF clock mode. • Slave mode: SIOFSCK, SIOFSYNC input • Master mode: SIOFSCK, SIOFSYNC output Baud Rate Generator: In SIOF master mode, the baud rate generator (BRG) is used to generate the serial clock. The division ratio is from 1/1 to 1/1024. Figure 16.2 shows connections for supply of the serial clock. MCLK BRG 1/1 to 1/1024 MCLK SIOFMCLK Pφ Timing control SCKE Master SIOFSCK Figure 16.2 Serial Clock Supply Table 16.3 shows an example of serial clock frequency. Table 16.3 SIOF Serial Clock Frequency Sampling Rate Frame Length 32 bits 64 bits 128 bits 256 bits 8 kHz 256 kHz 512 kHz 1.024 MHz 2.048 MHz 44.1 kHz 1.4112 MHz 2.8224 MHz 5.6448 MHz 11.289 MHz 48 kHz 1.536 MHz 3.072 MHz 6.144 MHz 12.289 MHz Rev. 5.00 Mar. 15, 2007 Page 473 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.4.2 Serial Timing SIOFSYNC: The SIOFSYNC is a frame synchronous signal. Depending on the transfer mode, it has the following functions. • Synchronous pulse: 1-bit-width pulse indicating the start of the frame • L/R: 1/2-frame-width pulse indicating the left-channel stereo data (L) in high level and the right-channel stereo data (R) in low level Figure 16.3 shows the SIOFSYNC synchronization timing. (a) Synchronous pulse 1 frame SIOFSCK SIOFSYNC SIOFTxD SIOFRxD Start bit data 1-bit delay (b) L/R 1 frame SIOFSCK SIOFSYNC SIOFTxD SIOFRxD Start bit of left channel data (1/2 frame length) No delay Start bit of right channel data (1/2 frame length) Figure 16.3 Serial Data Synchronization Timing Rev. 5.00 Mar. 15, 2007 Page 474 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Transmit/Receive Timing: The SIOFTxD transmit timing and SIOFRxD receive timing relative to the SIOFSCK can be set as the sampling timing in the following ways. The transmit/receive timing is set using the REDG bit in SIMDR. • Falling-edge sampling • Rising-edge sampling Figure 16.4 shows the transmit/receive timing. (a) Falling-edge sampling SIOFSCK SIOFSYNC SIOFTxD SIOFRxD Receive timing Transmit timing (a) Rising-edge sampling SIOFSCK SIOFSYNC SIOFTxD SIOFRxD Receive timing Transmit timing Figure 16.4 SIOF Transmit/Receive Timing 16.4.3 Transfer Data Format The SIOF performs the following transfer. • Transmit/receive data: Transfer of 8-bit data/16-bit data/16-bit stereo data • Control data: Transfer of 16-bit data (uses the specific register as interface) Transfer Mode: The SIOF supports the following four transfer modes as listed in table 16.4. The transfer mode can be specified by the TRMD1 and TRMD0 bits in SIMDR. Table 16.4 Serial Transfer Modes Transfer Mode Slave mode 1 Slave mode 2 Master mode 1 Master mode 2 SIOFSYNC Synchronous pulse Synchronous pulse Synchronous pulse L/R No Bit Delay SYNCDL bit Control Data Slot position Secondary FS Slot position Not supported Rev. 5.00 Mar. 15, 2007 Page 475 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Frame Length: The length of the frame to be transferred by the SIOF is specified by the FL3 to FL0 bits in SIMDR. Table 16.5 shows the relationship between the FL3 to FL0 bit settings and frame length. Table 16.5 Frame Length FL3 to FL0 00xx 0100 0101 0110 0111 10xx 1100 1101 1110 1111 Slot Length 8 8 8 8 8 16 16 16 16 16 Number of Bits in a Frame 8 16 32 64 128 16 32 64 128 256 Transfer Data 8-bit monaural data 8-bit monaural data 8-bit monaural data 8-bit monaural data 8-bit monaural data 16-bit monaural data 16-bit monaural/stereo data 16-bit monaural/stereo data 16-bit monaural/stereo data 16-bit monaural/stereo data Note: x: Don't care. Slot Position: The SIOF can specify the position of transmit data, receive data, and control data in a frame (common to transmission and reception) by slot numbers. The slot number of each data is specified by the following registers. • Transmit data: SITDAR • Receive data: SIRDAR • Control data: SICDAR Only 16-bit data is valid for control data. In addition, control data is always assigned to the same slot number both in transmission and reception. Rev. 5.00 Mar. 15, 2007 Page 476 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.4.4 Register Allocation of Transfer Data Transmit/Receive Data: Writing and reading of transmit/receive data is performed for the following registers. • Transmit data writing: SITDR (32-bit access) • Receive data reading: SIRDR (32-bit access) Figure 16.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment. (a) 16-bit stereo data 31 24 23 L-channel data 16 15 87 R-channel data 0 (b) 16-bit monaural data 31 24 23 Data 16 15 87 0 (c) 8-bit monaural data 31 24 23 Data 16 15 87 0 (d) 16-bit stereo data (left and right same audio output) data 31 24 23 16 15 87 Data 0 Figure 16.5 Transmit/Receive Data Bit Alignment Note: In the figure, only the shaded areas are transmitted or received as valid data. Data in unshaded areas is not transmitted or received. Monaural or stereo can be specified for transmit data by the TDLE bit and TDRE bit in SITDAR. Monaural or stereo can be specified for receive data by the RDLE bit and RDRE bit in SIRDAR. To achieve left and right same audio output while stereo is specified for transmit data, specify the TLREP bit in SITDAR. Tables 16.6 and 16.7 show the audio mode specification for transmit data and that for receive data, respectively. Rev. 5.00 Mar. 15, 2007 Page 477 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Table 16.6 Audio Mode Specification for Transmit Data Bit Mode Monaural Stereo Left and right same audio output Note: x: Don't care TDLE 1 1 1 TDRE 0 1 1 TLREP x 0 1 Table 16.7 Audio Mode Specification for Receive Data Bit Mode Monaural Stereo RDLE 1 1 RDRE 0 1 Note: Left and right same audio mode is not supported in receive data. To execute 8-bit monaural transmission or reception, use the left channel. Control Data: Control data is written to or read from by the following registers. • Transmit control data write: SITCR (32-bit access) • Receive control data read: SIRCR (32-bit access) Figure 16.6 shows the control data and bit alignment in SITCR and SIRCR. (a) Control data: One channel 31 24 23 Control data (channel 0) 16 15 87 0 (b) Control data: Two channels 31 24 23 Control data (channel 0) 16 15 87 Control data (channel 1) 0 Figure 16.6 Control Data Bit Alignment Rev. 5.00 Mar. 15, 2007 Page 478 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) The number of channels in control data is specified by the CD0E and CD1E bits in SICDAR. Table 16.8 shows the relationship between the number of channels in control data and bit settings. Table 16.8 Setting Number of Channels in Control Data Bit Number of Channels 1 2 CD0E 1 1 CD1E 0 1 Note: To use only one channel in control data, use channel 0. 16.4.5 Control Data Interface Control data performs control command output to the CODEC and status input from the CODEC. The SIOF supports the following two control data interface methods. • Control by slot position • Control by secondary FS Control data is valid only when data length is specified as 16 bits. Control by Slot Position (Master Mode 1, Slave Mode 1): Control data is transferred for all frames transmitted or received by the SIOF by specifying the slot position of control data. This method can be used in both SIOF master and slave modes. Figure 16.7 shows an example of the control data interface timing by slot position control. 1 frame SIOFSCK SIOFSYNC SIOFTxD SIOFRxD L-channel data Control channel 0 R-channel data Control channel 1 Slot No.0 Slot No.1 Slot No.2 Slot No.3 REDG=0, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0001, FL[3:0]=1110 (Frame length: 128 bits), TDRA[3:0]=0010, TDRE=1, RDRA[3:0]=0010, RDRE=1, CD1A[3:0]=0011 CD1E=1, Specifications: TRMD[1:0]=00 or 10, TDLE=1, RDLE=1, CD0E=1, Figure 16.7 Control Data Interface (Slot Position) Rev. 5.00 Mar. 15, 2007 Page 479 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Control by Secondary FS (Slave Mode 2): The CODEC normally outputs the SIOFSYNC signal as synchronization pulse (FS). In this method, the CODEC outputs the secondary FS specific to the control data transfer after 1/2 frame time has been passed (not the normal FS output timing) to transmit or receive control data. This method is valid for SIOF slave mode. The following summarizes the control data interface procedure by the secondary FS. • Transmit normal transmit data of LSB = 0 (the SIOF forcibly clears 0). • To execute control data transmission, send transmit data of LSB = 1 (the SIOF forcibly set to 1 by writing SITCDR). • The CODEC outputs the secondary FS. • The SIOF transmits or receives (stores in SIRCDR) control data (data specified by SITCDR) synchronously with the secondary FS. Figure 16.8 shows an example of the control data interface timing by the secondary FS. 1 frame 1/2 frame 1/2 frame SIOFSCK SIOFSYNC SIOFTxD SIOFRxD L-channel data Normal FS Secondary FS Normal FS Slot No.0 LSB=1 (Secondary FS request) REDG=0, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0000, Control channel 0 Slot No.0 FL[3:0]=1110 (Frame length: 128 bits), TDRA[3:0]=0000, TDRE=0, RDRA[3:0]=0000, RDRE=0, CD1A[3:0]=0000 CD1E=0, Specifications: TRMD[1:0]=01, TDLE=1, RDLE=1, CD0E=1, Figure 16.8 Control Data Interface (Secondary FS) Rev. 5.00 Mar. 15, 2007 Page 480 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.4.6 FIFO Overview: The transmit and receive FIFOs of the SIOF have the following features. • 16-stage 32-bit FIFOs for transmission and reception • The FIFO pointer can be updated in one read or write cycle regardless of access size of the CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.) Transfer Request: The transfer request of the FIFO can be issued to the CPU or DMAC as the following interrupt sources. • FIFO transmit request: TDREQ (transmit interrupt source) • FIFO receive request: RDREQ (receive interrupt source) The request conditions for FIFO transmit or receive can be specified individually. The request conditions for the FIFO transmit and receive are specified by the TFWM2 to TFWM0 bits and RFWM2 to RFWM0 bits in SIFCTR, respectively. Tables 16.9 and 16.10 summarize the conditions specified by SIFCTR. Table 16.9 Conditions to Issue Transmit Request TFWM2 to TFWM0 000 100 101 110 111 Number of Requested Stages 1 4 8 12 16 Transmit Request Empty area is 16 stages Empty area is 12 stages or more Empty area is 8 stages or more Empty area is 4 stages or more Empty area is 1 stage or more Largest Used Areas Smallest Table 16.10 Conditions to Issue Receive Request RFWM2 to RFWM0 000 100 101 110 111 Number of Requested Stages 1 4 8 12 16 Receive Request Valid data is 1 stage or more Valid data is 4 stages or more Valid data is 8 stages or more Valid data is 12 stages or more Valid data is 16 stages Largest Used Areas Smallest Rev. 5.00 Mar. 15, 2007 Page 481 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) The number of stages of the FIFO is always sixteen even if the data area or empty area exceeds the FIFO size (the number of FIFOs). Accordingly, an overflow error or underflow error occurs if data area or empty area exceeds sixteen FIFO stages. The FIFO transmit or receive request is canceled when the above condition is not satisfied even if the FIFO is not empty or full. Number of FIFOs: The number of FIFO stages used in transmission and reception is indicated by the following register. • Transmit FIFO: The number of empty FIFO stages is indicated by the TFUA4 to TFUA0 bits in SIFCTR. • Receive FIFO: The number of valid data stages is indicated by the RFUA4 to RFUA0 bits in SIFCTR. The above indicate possible data numbers that can be transferred by the CPU or DMAC. Rev. 5.00 Mar. 15, 2007 Page 482 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.4.7 Transmit and Receive Procedures Transmission in Master Mode: Figure 16.9 shows an example of settings and operation for master mode transmission. No. Flow Chart Start SIOF Settings SIOF Operation 1 Set SIMDR, SISCR, SITDAR, SIRDAR, SICDAR, and SIFCTR Set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and FIFO request threshold value 2 Set the SCKE bit in SICTR to 1 Set operation start for baud rate generator 3 Start SIOFSCK output Output serial clock 4 Set the FSE and TXE bits in SICTR to 1 frame synchronous Set the start for frame synchronous Outputand issue transmit signal signal output and enable transfer request* transmission 5 TDREQ = 1? Yes No 6 Set SITDR Set transmit data 7 Transmit SITDR from SIOFTXD synchronously with SIOFSYNC Transmit Transfer ended? 8 Yes No Set to disable transmission End transmission Clear the TXE bit in SICTR to 0 End Note: * When interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the TXE bit should be set to 1. Figure 16.9 Example of Transmit Operation in Master Mode Rev. 5.00 Mar. 15, 2007 Page 483 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Reception in Master Mode: Figure 16.10 shows an example of settings and operation for master mode reception. No. Flow Chart Start 1 SIOF Settings SIOF Operation Set SIMDR, SISCR, SITDAR, SIRDAR, SICDAR, and SIFCTR Set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and FIFO request threshold value Set operation start for baud rate generator 2 Set the SCKE bit in SICTR to 1 3 Start SIOFSCK output Output serial clock 4 Set the FSE and RXE bits in SICTR to 1 Set the start for frame synchronous Output frame synchronous signal output and enable signal reception 5 Store SIOFRXD receive data in SIRDR synchronously with SIOFSYNC Issue receive transfer request according to the receive FIFO threshold value 6 RDREQ = 1? Yes No Reception 7 Read SIRDR Read receive data Transfer ended? 8 Yes No Set to disable reception End reception Clear the RXE bit in SICTR to 0 End Figure 16.10 Example of Receive Operation in Master Mode Rev. 5.00 Mar. 15, 2007 Page 484 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Transmission in Slave Mode: Figure 16.11 shows an example of settings and operation for slave mode transmission. No. Flow Chart Start 1 Set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and FIFO request threshold value SIOF Settings SIOF Operation Set SIMDR, SISCR, SITDAR, SIRDAR, SICDAR, and SIFCTR 2 Set the TXE bit in SICTR to 1 Set to enable transmission Issue transmit transfer request to enable transmission when frame synchronous signal is input 3 TDREQ = 1? Yes No 4 Set SITDR Set transmit data 5 Transmit SITDR from SIOFTXD synchronously with SIOFSYNC Transmit Transfer ended? Yes 6 No Set to disable transmission End transmission Clear the TXE bit in SICTR to 0 End Figure 16.11 Example of Transmit Operation in Slave Mode Rev. 5.00 Mar. 15, 2007 Page 485 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Reception in Slave Mode: Figure 16.12 shows an example of settings and operation for slave mode reception. No. Flow Chart Start 1 Set SIMDR, SISCR, SITDAR, SIRDAR, SICDAR, and SIFCTR SIOF Settings SIOF Operation Set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and FIFO request threshold value Set to enable reception Enable reception when the frame synchronous signal is input Issue receive transfer request according to the receive FIFO threshold value 2 Set the RXE bit in SICTR to 1 3 Store SIOFRXD receive data in SIRDR synchronously with SIOFSYNC 4 RDREQ = 1? Yes No Reception 5 Read SIRDR Read receive data Transfer ended? 6 Yes No Set to disable reception End reception Clear the RXE bit in SICTR to 0 End Figure 16.12 Example of Receive Operation in Slave Mode Rev. 5.00 Mar. 15, 2007 Page 486 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Transmit/Receive Reset: The SIOF can separately reset the transmit and receive units by setting the following bits to 1. • Transmit reset: TXRST bit in SICTR • Receive reset: RXRST bit in SICTR Table 16.11 shows the details of initialization upon transmit or receive reset. Table 16.11 Transmit and Receive Reset Type Transmit reset Objects Initialized SITDR Transmit FIFO write pointer and read pointer TCRDY, TFEMP, and TDREQ bits in SISTR TXE bit in SICTR Receive reset SIRDR Receive FIFO write pointer and read pointer RCRDY, RFFUL, and RDREQ bits in SISTR RXE bit in SICTR Module Stop Mode: The SIOF stops the transmit/receive operation in module stop mode. And all the registers in SIOF are retained. Rev. 5.00 Mar. 15, 2007 Page 487 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.4.8 Interrupts The SIOF has one type of interrupt. Interrupt Sources: Interrupts can be issued by several sources. Each source is shown as an SIOF status in SISTR. Table 16.12 lists the SIOF interrupt sources. Table 16.12 SIOF Interrupt Sources No. Classification 1 2 3 4 5 6 7 8 Error Control Reception Transmission Bit Name TDREQ TFEMP RDREQ RFFUL TCRDY RCRDY TFUDF TFOVF Function Name Description Transmit FIFO transfer The transmit FIFO stores data of request specified size or more. Transmit FIFO empty Receive FIFO transfer request Receive FIFO full Transmit control data ready Receive control data ready Transmit FIFO underflow The transmit FIFO is empty. The receive FIFO stores data of specified size or more. The receive FIFO is full. The transmit control register is ready to be written. The receive control data register stores valid data. Serial data transmit timing has arrived while the transmit FIFO is empty. Transmit FIFO overflow Write to the transmit FIFO is performed while the transmit FIFO is full. Receive FIFO overflow Serial data is received while the receive FIFO is full. Receive FIFO underflow FS error The receive FIFO is read while the receive FIFO is empty. A synchronous signal is input before the specified bit number has been passed (in slave mode). The same slot is specified in both serial data and control data. 9 10 11 RFOVF RFUDF FSERR 12 SAERR Assign error Whether an interrupt is issued or not as the result of an interrupt source is determined by the SIIER settings. If an interrupt source is set to 1 and the corresponding bit in SIIER is set to 1, an SIOF interrupt is issued. Rev. 5.00 Mar. 15, 2007 Page 488 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Regarding Transmit and Receive Classification: The transmit sources and receive sources are signals indicating the state; after being set, if the state changes, they are automatically cleared by the SIOF. When the DMA transfer is used, a DMA transfer request is pulled low (0 level) for one cycle at the end of DMA transfer. Processing when Errors Occur: On occurrence of each of the errors indicated as a status in SISTR, the SIOF performs the following operations. • Transmit FIFO underflow (TFUDF) The immediately preceding transmit data is again transmitted. • Transmit FIFO overflow (TFOVF) The contents of the transmit FIFO are protected, and the write operation causing the overflow is ignored. • Receive FIFO overflow (RFOVF) Data causing the overflow is discarded and lost. • Receive FIFO underflow (RFUDF) An undefined value is output on the bus. • FS error (FSERR) The internal counter is reset according to the FSYN signal in which an error occurs. • Assign error (SAERR)  If the same slot is assigned to both serial data and control data, the slot is assigned to serial data.  If the same slot is assigned to two control data items, data cannot be transferred correctly. Rev. 5.00 Mar. 15, 2007 Page 489 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.4.9 Transmit and Receive Timing Examples of the SIOF serial transmission and reception are shown in figures 16.13 to 16.19. 8-bit Monaural Data (1): Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, an frame length = 8 bits 1 frame SIOFSCK SIOFSYNC SIOFTxD L-channel data SIOFRxD Slot No.0 1-bit delay Specifications: TRMD[1:0]=00 or 10, TDLE=1, RDLE=1, CD0E=0, REDG=0, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0000, FL[3:0]=0000 (frame length: 8 bits) TDRE=0, TDRA[3:0]=0000, RDRE=0, RDRA[3:0]=0000, CD1E=0, CD1A[3:0]=0000 Figure 16.13 Transmit and Receive Timing (8-Bit Monaural Data (1)) 8-bit Monaural Data (2): Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, and frame length = 16 bits 1 frame SIOFSCK SIOFSYNC SIOFTxD L-channel data SIOFRxD Slot No.0 1-bit delay Specifications: TRMD[1:0]=00 or 10, TDLE=1, RDLE=1, CD0E=0, REDG=0, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0000, FL[3:0]=0100 (frame length: 16 bits) TDRE=0, TDRA[3:0]=0000, RDRE=0, RDRA[3:0]=0000, CD1E=0, CD1A[3:0]=0000 Slot No.1 Figure 16.14 Transmit and Receive Timing (8-Bit Monaural Data (2)) Rev. 5.00 Mar. 15, 2007 Page 490 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16-bit Monaural Data (1): Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, and frame length = 64 bits 1 frame SIOFSCK SIOFSYNC SIOFTxD SIOFRxD L-channel data Slot No.0 1-bit delay Specifications: TRMD[1:0]=00 or 10, TDLE=1, RDLE=1, CD0E=0, REDG=0, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0000, FL[3:0]=1101 (frame length: 64 bits) TDRA[3:0]=0000, TDRE=0, RDRA[3:0]=0000, RDRE=0, CD1A[3:0]=0000 CD1E=0, Slot No.1 Slot No.2 Slot No.3 Figure 16.15 Transmit and Receive Timing (16-Bit Monaural Data (1)) 16-bit Stereo Data (1): L/R method, rising edge sampling, slot No.0 used for left channel data, slot No.1 used for right channel data, and frame length = 32 bits 1 frame SIOFSCK SIOFSYNC SIOFTxD L-channel data SIOFRxD No bit delay Specifications: TRMD[1:0]=11, TDLE=1, RDLE=1, CD0E=0, REDG=1, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0000, FL[3:0]=1100 (frame length: 32 bits) TDRA[3:0]=0001, TDRE=1, RDRA[3:0]=0001, RDRE=1, CD1A[3:0]=0000 CD1E=0, Slot No.0 R-channel data Slot No.1 Figure 16.16 Transmit and Receive Timing (16-Bit Stereo Data (1)) Rev. 5.00 Mar. 15, 2007 Page 491 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16-bit Stereo Data (2): L/R method, rising edge sampling, slot No.0 used for left-channel transmit data, slot No.1 used for left-channel receive data, slot No.2 used for right-channel transmit data, slot No.3 used for right-channel receive data, and frame length = 64 bits 1 frame SIOFSCK SIOFSYNC SIOFTxD L-channel data R-channel data SIOFRxD Slot No.0 No bit delay L-channel data Slot No.1 Slot No.2 R-channel data Slot No.3 Specifications: TRMD[1:0]=01, TDLE=1, RDLE=1, CD0E=0, REDG=1, TDLA[3:0]=0000, RDLA[3:0]=0001, CD0A[3:0]=0000, FL[3:0]=1101 (frame length: 64 bits), TDRA[3:0]=0010, TDRE=1, RDRA[3:0]=0011, RDRE=1, CD1A[3:0]=0000 CD1E=0, Figure 16.17 Transmit and Receive Timing (16-Bit Stereo Data (2)) 16-bit Stereo Data (3): Synchronous pulse method, falling edge sampling, slot No.0 used for leftchannel data, slot No.1 used for right-channel data, slot No.2 used for control channel 0 data, slot No.3 used for control channel 1 data, and frame length = 128 bits 1 frame SIOFSCK SIOFSYNC SIOFTxD SIOFRxD L-channel data R-channel data Slot No.0 Slot No.1 Control Control channel 0 channel 1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7 1 bit delay Specifications: TRMD[1:0]=00 or 10,REDG=0, TDLA[3:0]=0000, TDLE=1, RDLA[3:0]=0000, RDLE=1, CD0A[3:0]=0010, CD0E=1, FL[3:0]=1110 (frame length: 128 bits), TDRA[3:0]=0001, TDRE=1, RDRA[3:0]=0001, RDRE=1, CD1A[3:0]=0011 CD1E=1, Figure 16.18 Transmit and Receive Timing (16-Bit Stereo Data (3)) Rev. 5.00 Mar. 15, 2007 Page 492 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16-bit Stereo Data (4): Synchronous pulse method, falling edge sampling, slot No.0 used for leftchannel data, slot No.2 used for right-channel data, slot No.1 used for control channel 0 data, slot No.3 used for control channel 1 data, and frame length = 128 bits 1 frame SIOFSCK SIOFSYNC SIOFTxD SIOFRxD L-channel data R-channel Control Control data channel 0 channel 1 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.0 Slot No.5 Slot No.6 Slot No.7 1 bit delay Specifications: TRMD[1:0]=00 or 10, TDLE=1, RDLE=1, CD0E=1, REDG=1, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0001, FL[3:0]=1110 (frame length: 128 bits) TDRA[3:0]=0010, TDRE=1, RDRA[3:0]=0010, RDRE=1, CD1A[3:0]=0011 CD1E=1, Figure 16.19 Transmit and Receive Timing (16-Bit Stereo Data (4)) Synchronization-Pulse Output Mode at End of Each Slot (SYNCAT Bit = 1): Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.1 used for rightchannel data, slot No.2 used for control channel 0 data, slot No.3 used for control channel 1 data, and frame length = 128 bits In this mode, valid data must be set to slot No. 0. 1 frame SIOFSCK SIOFSYNC SIOFTxD SIOFRxD L-channel data R-channel data Slot No.0 Slot No.1 Control channel 0 Slot No.2 Control channel 1 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7 Specifications: TRMD[1:0]=00 or 10,REDG=0, TDLA[3:0]=0000, TDLE=1, RDLA[3:0]=0000, RDLE=1, CD0A[3:0]=0010, CD0E=1, FL[3:0]=1110 (frame length: 128 bits), TDRA[3:0]=0001, TDRE=1, RDRA[3:0]=0001, RDRE=1, CD1A[3:0]=0011 CD1E=1, Figure 16.20 Transmit and Receive Timing (16-Bit Stereo Data) Rev. 5.00 Mar. 15, 2007 Page 493 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) 16.4.10 SPI Mode SPI-mode operation is selected for the SIOF by the setting in SPICR. Example of Configuration: Figure 16.21 shows an example of the configuration for SPI-mode communications. Master SPI Transmit FIFO P/S MOSI Slave 0 SPI Receive FIFO S/P MISO SS0 SS Baud rate generator SCK Figure 16.21 Example of Configuration in SPI Mode SPI Operation: The states of operation in SPI mode are described in terms of transmission and reception in table 16.13. In SPI mode, the data length is fixed to 8 bits and the values of the upper 8 bits of SITDR and SIRDR are the valid data for transmission and reception, respectively. Fixed master mode can perform the full-duplex communication with the SPI slave devices continuously. That is, 8-bit data is continuously transmitted/received, and resetting of transmit/receive operation by the TXRST or RXRST bit with SCK = Pφ controls the respective frames. 31 SITDR/SIRDR Data 24 23 0 The shaded part is the data which is transmitted or received. Rev. 5.00 Mar. 15, 2007 Page 494 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) The only sources of interrupts that should be enabled in SPI-mode transfer are transmit data transfer request (TDREQ), transmit FIFO empty (TFEMP), receive-data transfer request (RDREQ), receive-FIFO full (RFFUL), and receive-FIFO overflow (RFOVF). Enabled or disabled states are selectable by the interrupt enable register (SIIER). Interrupts from other sources must be disabled at all times. For the DMA transfer requests, the enabled sources are transmit-data DMA transfer request (TDMA) and receive-data DMA transfer request (RDMA). Enabled or disabled states are selectable by the interrupt enable register (SIIER). In SPI mode, the baud rate is set by SISCR. Table 16.13 States of Transmit and Receive Operations in SPI Mode TXE 0 0 RXE 0 1 TDMAE Don’t care 0 RDMAE Don’t care 1 SPI Transmit/Receive Operation Transmission/reception is disabled Half-Duplex Reception The transmit FIFO does not operate and dummy data is transmitted from the MOSI. Data received at the MISO is stored in the receive FIFO and is transferred by using the DMA. Receive operation continues as long as RE bit = 1; the receive-FIFO overflow (RFOVF) status is set after the receive FIFO has become full and further receive data is ignored. 1 0 0 0 Half-Duplex Transmission The data in the transmit FIFO is transmitted from the MOSI. The receive FIFO does not operate, and data on the MISO is ignored. When the transmit FIFO becomes empty, the transmit operation is completed. 1 0 Half-Duplex Transmission The data which has been transferred by using the DMA to the transmit FIFO is transmitted from the MOSI. The receive FIFO does not operate and data on the MISO is ignored. When the transmit FIFO becomes empty, the transmit operation is completed. Rev. 5.00 Mar. 15, 2007 Page 495 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) TXE 1 RXE 1 TDMAE 0 RDMAE 0 SPI Transmit/Receive Operation Full-Duplex Communication The transmit and receive FIFOs operate at the same time. Data in the transmit FIFO are transmitted or received. When there is no data left in the transmit FIFO, the transmit and receive operations end. Note that even if only reception is to be done, dummy transmission is necessary because only master mode is allowed in the SPI mode. Note: In SPI mode, settings other than the above are prohibited. In half-duplex reception (transmission is disabled), the value output from the MOSI can be controlled by the TXDIZ bit in SIMDR as follows. TXDIZ = 0: Transmission is disabled, 1 is output on the MOSI. TXDIZ = 1: Transmission is disabled, the MOSI is in the high-impedance state. Serial Clock Timing: Timing on the data and clock lines in SPI mode is shown in figures 16.22 and 16.23. The user can select from four serial transfer formats, which differ according to the phase and polarity of the serial clock. SCK (CPOL = 0) (CPOL = 1) Sampling MISO/MOSI SS0 Ts Th Td MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Ts: The setup time for the SCK edge. The minimum value is 1/2 of the period of the SCK. The setting is made by the SSAST1 and SSAST0 bits in SPICR. Th: The hold time for the SCK edge. The minimum value is 0. Td: The idle time. A number of SCK-clock cycles from 0 to 3 is set by the FLD1 and FLD0 bits in SPICR. Figure 16.22 SPI Data/Clock Timing 1 (CPHA = 0) Rev. 5.00 Mar. 15, 2007 Page 496 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) SCK (CPOL = 0) (CPOL = 1) Sampling MISO/MOSI SS0 Ts Th Td MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Ts: The setup time for the SCK edge. The minimum value is 0. The setting is made by the SSAST1 and SSAST0 bits in SPICR. Th: The hold time for the SCK edge. The minimum value is 1/2 of the period of the SCK. Td: The idle time. A number of SCK-clock cycles from 0 to 3 is set by the FLD1 and FLD0 bits in SPICR. Figure 16.23 SPI Data/Clock Timing 2 (CPHA = 1) Rev. 5.00 Mar. 15, 2007 Page 497 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Procedures for Transmission/Reception: Shown in figures 16.24 to 16.27 are examples of settings for SPI transmission/reception along with the corresponding operations. No. Time chart Start SIOF Setting SIOF Operation 1 Set SISCR, SIFCTR, and SPICR. Set the serial clock and threshold values for FIFO. [Note] In SPI mode, registers SIMDR, SITDAR, SIRDAR, and SICDAR should be set to their initial values. 2 3 Set the SCKE bit in SICTR to 1. Start baud rate generator operation. [Note] Serial clock will not be output form the pin until communication is actually started. [Note] Communication is actually started after SITDR has been written. Set the FSE bit in SICTR to 1. Set the TXE and RXE bits in SICTR to 1.* Initialize the frame in the SIOF (ie, initialize the state of signal SS0), and enable transmission and reception. 4 TDREQ=1? Yes No 5 6 Set the SITDR register. Synchronously to SS0, output the contents of SITDR from MOSI and receive data from MISO. Set the data for transmission. Executes transmission and reception simultaneously. (Even when transmission is not necessary, dummy transmission must be performed. The output of dummy transmission can be masked by setting the pin function.) 7 RDREQ=1? Yes No 8 9 Read the SIRDR register. No Read the received data. Check SISTR.TFEMP (transmit FIFO empty) and ensure completion of communication by using a wait loop or other means. (Checking SISTR.TFEMP is enough to confirm the completion of simultaneous transmission and reception.) Disable transmission and reception. To be prepared for the transmission/reception that is resumed later, set FSE = 0 to synchronize the frame in this LSI. Transmission/reception end. Transfer complete? Yes 10 11 Clear the TXE and RXE bits in SICTR to 0. Clear the FSE bit in SICTR to 0. Set BPRS = 00000 and BRDV = 111 in the SISCR register. 12 Apply a pulse to bits TxRST and RxRST in the SICTR register (0->1->0 input). Set the SISCR register to set the baud rate again. Change communication mode? To be prepared for the transmission/reception that is resumed later, initialize inside the baud rate generator. No End 13 Yes If communication is not to be resumed (branching to No), no further setting is needed. To return to the same communication mode, go back to setting of FSE at step 3 of this flowchart. Go on to 'Start' of the corresponding flowchart. 14 With FSE=0, TXE=0, and RXE=0 held, start setting other bits. Note: * For the case when interrupt generation on transmit FIFO underflow is enabled, set the TXE bit to 1 after setting data for transmission at step No.5. Figure 16.24 SPI Transmission/Reception Operation (Example of Full-Duplex Transmission/Reception by the CPU with TDMAE = 0) Rev. 5.00 Mar. 15, 2007 Page 498 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) No. Time chart Start SIOF Setting SIOF Operation [Note] In SPI mode, registers SIMDR, SITDAR, SIRDAR, and SICDAR should be set to their initial values. 1 Set SISCR, SIFCTR, and SPICR. Set the serial clock and threshold values for FIFO. 2 3 4 5 6 7 Set the SCKE bit in SICTR to 1. Set the FSE bit in SICTR to 1. Set the TXE bit in SICTR to 1.* No Start baud rate generator operation. [Note] Serial clock will not be output form the pin until communication is actually started. [Note] Communication is actually started after SITDR has been written. Initialize the frame in the SIOF (ie, initialize the state of signal SS0), and enable transmission. TDREQ=1? Yes Set the SITDR register. Synchronously to SS0, output the contents of SITDR from MOSI. Transfer complete? Yes Set the data for transmission. Executes transmission. No Check SISTR.TFEMP (transmit FIFO empty) and ensure completion of communication by using a wait loop or other means. 8 9 Clear the TXE bit in SICTR to 0. Disable transmission. To be prepared for the transmission/reception that is resumed later, set FSE = 0 to synchronize the frame in this LSI. Transmission ends. Clear the FSE bit in SICTR to 0. Set BPRS = 00000 and BRDV = 111 in the SISCR register. 10 Apply a pulse to bit TxRST in the SICTR register (0->1->0 input). Set the SISCR register to set the baud rate again. Change communication mode? To be prepared for the transmission/reception that is resumed later, initialize inside the baud rate generator. 11 No End Yes If communication is not to be resumed (branching to No), no further setting is needed. To return to the same communication mode, go back to setting of FSE at step 3 of this flowchart. Go on to 'Start' of the corresponding flowchart. 12 With FSE=0, TXE=0, and RXE=0 held, start setting other bits. Note: * For the case when interrupt generation on transmit FIFO underflow is enabled, set the TXE bit to 1 after setting data for transmission at step No.5. Figure 16.25 SPI Transmission Operation (Example of Half-Duplex Transmission by the CPU with TDMAE = 0) Rev. 5.00 Mar. 15, 2007 Page 499 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) No. Time Chart Start SIOF/DMA Setting SIOF/DMA Operation 1 Make settings for DMA. Complete setting for DMA before making settings for the SIOF. 2 3 4 Set SISCR, SIFCTR, SPICR, and SIIER. Set the serial clock, threshold values for FIFO, and TDMAE = 1 [Note] In SPI mode, registers SIMDR, SITDAR, SIRDAR, and SICDAR should be set to their initial values. [Note] Serial clock will not be output form the pin until communication is actually started. [Note] Communication is actually started after SITDR has been written. Set the SCKE bit in SICTR to 1. Set the FSE bit in SICTR to 1. Set the TXE bit in SICTR to 1. No Start baud rate generator operation. Initialize the frame in the SIOF (ie, initialize the state of signal SS0), and enable transmission. 5 6 7 8 9 10 TDREQ=1? Yes DMA transfer (Set the SITDR register.) Synchronously to SS0, output the contents of SITDR from MOSI. Transfer complete? Yes Clear the TXE bit in SICTR to 0. No Set the data for transmission. Executes transmission. For example, in the DMA transfer end interrupt service routine, check SISTR.TFEMP (transmit FIFO empty) and ensure completion of communication by using a wait loop. Disable transmission. To be prepared for the transmission/reception that is resumed later, set FSE = 0 to synchronize the frame in this LSI. When the DMA transfr end interrupt is used, clear the IE bit in DMA.CHCRn before the execution returns from the interrupt service routine. Transmission ends. Clear the FSE bit in SICTR to 0. Set BPRS = 00000 and BRDV = 111 in the SISCR register. 11 Apply a pulse to bit TxRST in the SICTR register (0->1->0 input). Set the SISCR register to set the baud rate again. Change communication mode? To be prepared for the transmission/reception that is resumed later, initialize inside the baud rate generator. No End 12 13 Yes With FSE=0, TXE=0, and RXE=0 held, start setting other bits. If communication is not to be resumed (branching to No), no further setting is needed. To return to the same communication mode, go back to setting of FSE at step 4 of this flowchart. Go on to 'Start' of the corresponding flowchart. Figure 16.26 SPI Transmission Operation (Example of Half-Duplex Transmission by DMA with TDMAE = 1) Rev. 5.00 Mar. 15, 2007 Page 500 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) No. Time Chart Start SIOF/DMA Setting SIOF/DMA Operation 1 Make settings for DMA. Complete setting for DMA before making settings for the SIOF. 2 3 4 Set SISCR, SIFCTR, SPICR, and SIIER. Set the serial clock, threshold values for FIFO, and RDMAE = 1 [Note] In SPI mode, registers SIMDR, SITDAR, SIRDAR, and SICDAR should be set to their initial values. Set the SCKE bit in SICTR to 1. Set the FSE bit in SICTR to 1. Set the RXE bit in SICTR to 1. RDREQ=1? Yes No Start baud rate generator operation. [Note] Serial clock will not be output form the pin until communication is actually started. [Note] Communication is actually started after RXE = 1 has been set. Initialize the frame in the SIOF (ie, initialize the state of signal SS0), and enable reception. 5 6 7 8 9 10 DMA transfer (Read from the SIRDR register.) Synchronously to SS0, receive data from MISO. Transfer complete? Yes No Read data from the SIRDR register. Executes reception. At the point when a DEI interrupt is generated, reception has already proceeded excessively. Therefore, read the necessary amount of data from FIFO and skip the remainder, or cancel by RxRST. Disable reception. To be prepared for the transmission/reception that is resumed later, set FSE = 0 to synchronize the frame in this LSI. When the DMA transfr end interrupt is used, clear the IE bit in DMA.CHCRn before the execution returns from the interrupt service routine. Reception ends. Clear the RXE bit in SICTR to 0. Clear the FSE bit in SICTR to 0. Set BPRS = 00000 and BRDV = 111 in the SISCR register. 11 Apply a pulse to bit RxRST in the SICTR register (0->1->0 input). Set the SISCR register to set the baud rate again. Change communication mode? To be prepared for the transmission/reception that is resumed later, initialize inside the baud rate generator. No End 12 13 Yes With FSE=0, TXE=0, and RXE=0 held, start setting other bits. If communication is not to be resumed (branching to No), no further setting is needed. To return to the same communication mode, go back to setting of FSE at step 4 of this flowchart. Go on to 'Start' of the corresponding flowchart. Figure 16.27 SPI Reception Operation (Example of Half-Duplex Reception by DMA with RDMAE = 1) Rev. 5.00 Mar. 15, 2007 Page 501 of 794 REJ09B0237-0500 Section 16 Serial I/O with FIFO (SIOF) Rev. 5.00 Mar. 15, 2007 Page 502 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Section 17 Host Interface (HIF) This LSI incorporates a host interface (HIF) for use in high-speed transfer of data between external devices which cannot utilize the system bus. The HIF allows external devices to read from and write to 2 kbytes (1 kbyte × 2 banks) of the onchip RAM exclusively for HIF use (HIFRAM) within this LSI, in 32-bit units. Interrupts issued to this LSI by an external device, interrupts sent from this LSI to the external device, and DMA transfer requests sent from this LSI to the external device are also supported. By using HIFRAM and these interrupt functions, software-based data transfer between external devices and this LSI becomes possible, and connection to external devices not releasing bus mastership is enabled. Using HIFRAM, the HIF also supports HIF boot mode allowing this LSI to be booted. 17.1 Features The HIF has the following features. • An external device can read from or write to HIFRAM in 32-bit units via the HIF pins (access in 8-bit or 16-bit units not allowed). The on-chip CPU can read from or write to HIFRAM in 8bit, 16-bit, or 32-bit units, via the internal peripheral bus. The HIFRAM access mode can be specified as bank mode or non-bank mode. • When an external device accesses HIFRAM via the HIF pins, automatic increment of addresses and the endian can be specified with the HIF internal registers. • By writing to specific bits in the HIF internal registers from an external device, or by accessing the end address of HIFRAM from the external device, interrupts (internal interrupts) can be issued to the on-chip CPU. Conversely, by writing to specific bits in the HIF internal registers from the on-chip CPU, interrupts (external interrupts) or DMAC transfer requests can be sent from the on-chip CPU to the external device. • There are seven interrupt source bits each for internal interrupts and external interrupts. Accordingly, software control of 128 different interrupts is possible, enabling high-speed data transfer using interrupts. • In HIF boot mode, this LSI can be booted from HIFRAM by an external device storing the instruction code in HIFRAM. Rev. 5.00 Mar. 15, 2007 Page 503 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Figure 17.1 shows a block diagram of the HIF. HIF HIFDATA HIFSCR HIFRAM HIFRAM HIFD15 to HIFD00 HIFEICR HIFBCR HIFADR HIFMCR HIFIICR Select HIFCS HIFRS HIFWR HIFRD HIFMD HIFINT HIFDREQ HIFRDY HIFEBL Control circuit HIFI HIFBI [Legend] HIFIDX: HIFGSR: HIFSCR: HIFMCR: HIFIICR: HIFEICR: HIF index register HIF general status register HIF status/control register HIF memory control register HIF internal interrupt control register HIF external interrupt control register HIFBICR HIFGSR HIFDTR HIFIDX HIFADR: HIFDATA: HIFBCR: HIFDTR: HIFBICR: HIFI: HIFIB: HIF address register HIF data register HIF boot control register HIFDREQ trigger register HIF bank interrupt control register HIF interrupt (internal interrupt) HIF bank interrupt (internal interrupt) Figure 17.1 Block Diagram of HIF Rev. 5.00 Mar. 15, 2007 Page 504 of 794 REJ09B0237-0500 Internal bus Section 17 Host Interface (HIF) 17.2 Input/Output Pins Table 17.1 shows the HIF pin configuration. Table 17.1 Pin Configuration Name HIF data pins HIF chip select HIF register select Abbreviation HIFD15 to HIFD00 HIFCS HIFRS I/O I/O Input Input Description Address, data, or command input/output to the HIF Chip select input to the HIF Switching between HIF access types 0: Normal access (other than below) 1: Index register write or status register read HIF write HIF read HIF interrupt HIF mode HIFWR HIFRD HIFINT HIFMD Input Input Write strobe signal. Low level is input when an external device writes data to the HIF. Read strobe signal. Low level is input when an external device reads data from the HIF. Output Interrupt request to an external device from the HIF Input Selects whether or not this LSI is started up in HIF boot mode. If a power-on reset is canceled when high level is input, this LSI is started up in HIF boot mode. HIFDMAC transfer request HIF boot ready HIFDREQ HIFRDY Output To an external device, DMAC transfer request with HIFRAM as the destination Output Indicates that the HIF reset is canceled in this LSI and access from an external device to the HIF can be accepted. After 10 clock cycles (max.) of the peripheral clock following negate of the reset input pin of this LSI, this pin is asserted. HIF pin enable HIFEBL Input All HIF pins other than this pin are asserted by high-level input. Rev. 5.00 Mar. 15, 2007 Page 505 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) 17.3 17.3.1 Parallel Access Operation The HIF can be accessed by combining the HIFCS, HIFRS, HIFWR, and HIFRD pins. Table 17.2 shows the correspondence between combinations of these signals and HIF operations. Table 17.2 HIF Operations HIFCS 1 0 0 0 0 0 0 [Legend] *: Don't care HIFRS * 0 0 1 1 * * HIFWR * 1 0 1 0 1 0 HIFRD * 0 1 0 1 1 0 Operation No operation (NOP) Read from register specified by HIFIDX[7:0] Write to register specified by HIFIDX[7:0] Read from status register (HIFGSR[7:0]) Write to index register (HIFIDX[7:0]) No operation (NOP) Setting prohibited 17.3.2 Connection Method When connecting the HIF to an external device, a method like that shown in figure 17.2 should be used. External device CS A02 WR RD D15 to D00 HIFCS HIFRS HIFWR HIFRD HIFD15 to HIFD00 HIF Figure 17.2 HIF Connection Example Rev. 5.00 Mar. 15, 2007 Page 506 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) 17.4 Register Descriptions The HIF has the following registers. • • • • • • • • • • • HIF index register (HIFIDX) HIF general status register (HIFGSR) HIF status/control register (HIFSCR) HIF memory control register (HIFMCR) HIF internal interrupt control register (HIFIICR) HIF external interrupt control register (HIFEICR) HIF address register (HIFADR) HIF data register (HIFDATA) HIF boot control register (HIFBCR) HIFDREQ trigger register (HIFDTR) HIF bank interrupt control register (HIFBICR) HIF Index Register (HIFIDX) 17.4.1 HIFIDX is a 32-bit register used to specify the register read from or written to by an external device when the HIFRS pin is held low. HIFIDX can be only read by the on-chip CPU. HIFIDX can be only written to by an external device while the HIFRS pin is driven high. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 8 — Rev. 5.00 Mar. 15, 2007 Page 507 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Bit 7 6 5 4 3 2 Bit Name REG5 REG4 REG3 REG2 REG1 REG0 Initial Value 0 0 0 0 0 0 R/W R/W* R/W* R/W* R/W* R/W* R/W* Description HIF Internal Register Select These bits specify which register among HIFGSR, HIFSCR, HIFMCR, HIFIICR, HIFEICR, HIFADR, HIFDATA, and HIFBCR is accessed by an external device. 000000: HIFGSR 000001: HIFSCR 000010: HIFMCR 000011: HIFIICR 000100: HIFEICR 000101: HIFADR 000110: HIFDATA 001111: HIFBCR Other than above: Setting prohibited Rev. 5.00 Mar. 15, 2007 Page 508 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Bit 1 0 Bit Name BYTE1 BYTE0 Initial Value 0 0 R/W R/W* R/W* Description Internal Register Byte Specification These bits specify in advance the target word location before the external device accesses a register among HIFGSR, HIFSCR, HIFMCR, HIFIICR, HIFEICR, HIFADR, HIFDATA, and HIFBCR. See also section 17.9, Alignment Control. • When HIFSCR.BO = 0 00: Bits 31 to 16 in register 01: Setting prohibited 10: Bits 15 to 0 in register 11: Setting prohibited • When HIFSCR.BO = 1 00: Bits 15 to 0 in register 01: Setting prohibited 10: Bits 31 to 16 in register 11: Setting prohibited However, when HIFDATA is selected using bits REG5 to REG0, each time reading or writing of HIFDATA occurs, these bits change according to the following rule. 00 → 10 → 00 → 10... repeated Note: * This bit can be only written to by an external device while the HIFRS pin is held high. It cannot be written to by the on-chip CPU. Rev. 5.00 Mar. 15, 2007 Page 509 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) 17.4.2 HIF General Status Register (HIFGSR) HIFGSR is a 32-bit register, which can be freely used for handshaking between an external device connected to the HIF and the software of this LSI. HIFGSR can be read from and written to by the on-chip CPU. Reading from HIFGSR by an external device should be performed with the HIFRS pin high, or HIFGSR specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low. Writing to HIFGSR by an external device should be performed with HIFGSR specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low. Bit 31 to 16 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 STATUS15 to All 0 STATUS0 R/W General Status This register can be read from and written to by an external device connected to the HIF, and by the onchip CPU. These bits are initialized only at a poweron reset. 17.4.3 HIF Status/Control Register (HIFSCR) HIFSCR is a 32-bit register used to control the HIFRAM access mode and endian setting. HIFSCR can be read from and written to by the on-chip CPU. Access to HIFSCR by an external device should be performed with HIFSCR specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low. Bit 31 to 12 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 510 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Bit 11 10 Bit Name DMD DPOL Initial Value 0 0 R/W R/W R/W Description DREQ Mode DREQ Polarity Controls the assert mode for the HIFDREQ pin. For details on the negate timing, see section 17.8, External DMAC Interface. 00: For a DMAC transfer request to an external device, low level is generated at the HIFDREQ pin. The default for the HIFDREQ pin is high-level output. 01: For a DMAC transfer request to an external device, high level is generated at the HIFDREQ pin. The default for the HIFDREQ pin is low-level output. 10: For a DMAC transfer request to an external device, falling edge is generated at the HIFDREQ pin. The default for the HIFDREQ pin is high-level output. 11: For a DMAC transfer request to an external device, rising edge is generated at the HIFDREQ pin. The default for the HIFDREQ pin is low-level output. 9 8 BMD BSEL 0 0 R/W R/W HIFRAM Bank Mode HIFRAM Bank Select Controls the HIFRAM access mode. 00: Both an external device and the on-chip CPU can access bank 0. When access by both of these conflict, even though the access addresses differ, access by the external device is processed before access by the on-chip CPU. Bank 1 cannot be accessed. 01: Both an external device and the on-chip CPU can access bank 1. When access by both of these conflict, even though the access addresses differ, access by the external device is processed before access by the on-chip CPU. Bank 0 cannot be accessed. 10: An external device can access only bank 0 while the on-chip CPU can access only bank 1. 11: An external device can access only bank 1 while the on-chip CPU can access only bank 0. Rev. 5.00 Mar. 15, 2007 Page 511 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Bit 7 Bit Name — Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 — 1 R Reserved This bit is always read as 1. The write value should always be 1. 5 MD1 0/1 R HIF Mode 1 Indicates whether this LSI was started up in HIF boot mode or non-HIF boot mode. This bit stores the value of the HIFMD pin sampled at a power-on reset 0: Started up in non-HIF boot mode (booted from the memory connected to area 0) 1: Started up in HIF boot mode (booted from HIFRAM) 4, 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 WBSWP 0 R/W Byte Order for Access of HIFDATA Specifies the byte order when an external device accesses HIFDATA. See also section 17.9, Alignment Control. 0: Aligned according to the BO bit. 1: Swapped in word units from the big endian order and then swapped in byte units within each word. The setting of the BO bit is ignored. 1 EDN 0 R/W Endian for HIFRAM Access Specifies the byte order when HIFRAM is accessed by the on-chip CPU. 0: Big endian (MSB first) 1: Little endian (LSB first) Rev. 5.00 Mar. 15, 2007 Page 512 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Bit 0 Bit Name BO Initial Value 0 R/W R/W Description Byte Order for Access of All HIF Registers Including HIFDATA Specifies the byte order when an external device accesses all HIF registers including HIFDATA. However, for the HIFDATA alignment, this bit is referred to only when WBSWP = 0 and ignored when WBSWP = 1. See also section 17.9, Alignment Control. 0: Big endian (MSB first) 1: Little endian (LSB first) 17.4.4 HIF Memory Control Register (HIFMCR) HIFMCR is a 32-bit register used to control HIFRAM. HIFMCR can be only read by the on-chip CPU. Access to HIFMCR by an external device should be performed with HIFMCR specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 LOCK 0 R/W* Lock This bit is used to lock the access direction (read or write) for consecutive access of HIFRAM by an external device via HIFDATA. When this bit is set to 1, the values of the RD and WT bits set at the same time are held until this bit is next cleared to 0. When the RD bit and this bit are simultaneously set to 1, consecutive read mode is entered. When the WT bit and this bit are simultaneously set to 1, consecutive write mode is entered. Both the RD and WT bits should not be set to 1 simultaneously. 6 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 31 to 8 — Rev. 5.00 Mar. 15, 2007 Page 513 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Bit 5 Bit Name WT Initial Value 0 R/W R/W* Description Write When this bit is set to 1, the HIFDATA value is written to the HIFRAM position corresponding to HIFADR. If this bit and the LOCK bit are set to 1 simultaneously, HIFRAM consecutive write mode is entered, and highspeed data transfer becomes possible. This mode is maintained until this bit is next cleared to 0, or until the LOCK bit is cleared to 0. If the LOCK bit is not simultaneously set to 1 with this bit, writing to HIFRAM is performed only once. Thereafter, the value of this bit is automatically cleared to 0. 4 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 3 RD 0 R/W* Read When this bit is set to 1, the HIFRAM data corresponding to HIFADR is fetched to HIFDATA. If this bit and the LOCK bit are set to 1 simultaneously, HIFRAM consecutive read mode is entered, and highspeed data transfer becomes possible. This mode is maintained until this bit is next cleared to 0, or until the LOCK bit is cleared to 0. If the LOCK bit is not simultaneously set to 1 with this bit, reading of HIFRAM is performed only once. Thereafter, the value of this bit is automatically cleared to 0. 2, 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 AI/AD 0 R/W* Address Auto-Increment/Decrement This bit is valid only when the LOCK bit is 1. The value of HIFADR is automatically incremented by 4 or decremented by 4 according to the setting of this bit each time reading or writing of HIFRAM is performed. 0: Auto-increment mode (+4) 1: Auto-decrement mode (−4) Note: * This bit can be only written to by an external device when the HIFRS pin is low. It cannot be written to by the on-chip CPU. Changing the HIFRAM banks accessible from an external device by setting the BMD and BSEL bits in HIFSCR does not affect the setting of this bit. Rev. 5.00 Mar. 15, 2007 Page 514 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) 17.4.5 HIF Internal Interrupt Control Register (HIFIICR) HIFIICR is a 32-bit register used to issue interrupts from an external device connected to the HIF to the on-chip CPU. Access to HIFIICR by an external device should be performed with HIFIICR specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 5 4 3 2 1 0 IIC6 IIC5 IIC4 IIC3 IIC2 IIC1 IIC0 IIR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Internal Interrupt Request While this bit is 1, an interrupt request (HIFI) is issued to the on-chip CPU. Internal Interrupt Source These bits specify the source for interrupts generated by the IIR bit. These bits can be written to from both an external device and the on-chip CPU. By using these bits, fast execution of interrupt exception handling is possible. These bits are completely under software control, and their values have no effect on the operation of this LSI. 31 to 8 — 17.4.6 HIF External Interrupt Control Register (HIFEICR) HIFEICR is a 32-bit register used to issue interrupts to an external device connected to the HIF from this LSI. Access to HIFEICR by an external device should be performed with HIFEICR specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 8 — Rev. 5.00 Mar. 15, 2007 Page 515 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Bit 7 6 5 4 3 2 1 0 Bit Name EIC6 EIC5 EIC4 EIC3 EIC2 EIC1 EIC0 EIR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description External Interrupt Source These bits specify the source for interrupts generated by the EIR bit. These bits can be written to from both an external device and the on-chip CPU. By using these bits, fast execution of interrupt exception handling is possible. These bits are completely under software control, and their values have no effect on the operation of this LSI. External Interrupt Request While this bit is 1, the HIFINT pin is asserted to issue an interrupt request to an external device from this LSI. 17.4.7 HIF Address Register (HIFADR) HIFADR is a 32-bit register which indicates the address in HIFRAM to be accessed by an external device. When using the LOCK bit setting in HIFMCR to specify consecutive access of HIFRAM, auto-increment (+4) or auto-decrement (-4) of the address, according to the AI/AD bit setting in HIFMCR, is performed automatically, and HIFADR is updated. HIFADR can be only read by the on-chip CPU. Access to HIFADR by an external device should be performed with HIFADR specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low. Bit 31 to 10 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 9 to 2 A9 to A2 All 0 R/W* HIFRAM Address Specification These bits specify the address of HIFRAM to be accessed by an external device, with 32-bit boundary. 1, 0 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * This bit can be only written to by an external device when the HIFRS pin is low. It cannot be written to by the on-chip CPU. Rev. 5.00 Mar. 15, 2007 Page 516 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) 17.4.8 HIF Data Register (HIFDATA) HIFDATA is a 32-bit register used to hold data to be written to HIFRAM and data read from HIFRAM for external device accesses. If HIFDATA is not used when accessing HIFRAM, it can be used for data transfer between an external device connected to the HIF and the on-chip CPU. HIFDATA can be read from and written to by the on-chip CPU. Access to HIFDATA by an external device should be performed with HIFDATA specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low. Bit 31 to 0 Bit Name Initial Value R/W R/W Description 32-bit Data D31 to D0 All 0 17.4.9 HIF Boot Control Register (HIFBCR) HIFBCR is a 32-bit register for exclusive control of an external device and the on-chip CPU regarding access of HIFRAM. HIFBCR can be only read by the on-chip CPU. Access to HIFBCR by an external device should be performed with HIFBCR specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low. Bit 31 to 8 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 to 1 — All 0 R/W AC-Bit Writing Assistance These bits should be used to write the bit pattern (H'A5) needed to set the AC bit to 1. These bits are always read as 0. Rev. 5.00 Mar. 15, 2007 Page 517 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Bit 0 Bit Name AC Initial Value 0/1 R/W R/W Description HIFRAM Access Exclusive Control Controls accessing of HIFRAM by the on-chip CPU for the HIFRAM bank selected by the BMD and BSEL bits in HIFSCR as the bank allowed to be accessed by this LSI. 0: The on-chip CPU can perform reading/writing of HIFRAM. 1: When an HIFRAM read/write operation by the on-chip CPU occurs, the CPU enters the wait state, and execution of the instruction is halted until this bit is cleared to 0. When booted in non-HIF boot mode, the initial value of this bit is 0. When booted in HIF boot mode, the initial value of this bit is 1. After an external device writes a boot program to HIFRAM via the HIF, clearing this bit to 0 boots the onchip CPU from HIFRAM. When 1 is written to this bit by an external device, H'A5 should be written to bits 7 to 0 to prevent erroneous writing. 17.4.10 HIFDREQ Trigger Register (HIFDTR) HIFDTR is a 32-bit register. Writing to HIFDTR by the on-chip CPU asserts the HIFDREQ pin. HIFDTR cannot be accessed by an external device. Bit 31 to 1 Bit Name — Initial Value All 0 R/W R* 1 Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 518 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Bit 0 Bit Name DTRG Initial Value 0 R/W R/W* * 1 2 Description HIFDREQ Trigger When 1 is written to this bit, the HIFDREQ pin is asserted according to the setting of the DMD and DPOL bits in HIFSCR. This bit is automatically cleared to 0 in synchronization with negate of the HIFDREQ pin. Though this bit can be set to 1 by the on-chip CPU, it cannot be cleared to 0. To avoid conflict between clearing of this bit by negate of the HIFDREQ pin and setting of this bit by the onchip CPU, make sure this bit is cleared to 0 before setting this bit to 1 by the on-chip CPU. Notes: 1. This bit cannot be accessed by an external device. It can be accessed only by the onchip CPU. 2. Writing 0 to this bit by the on-chip CPU is ignored. 17.4.11 HIF Bank Interrupt Control Register (HIFBICR) HIFBICR is a 32-bit register that controls HIF bank interrupts. HIFBICR cannot be accessed by an external device. Bit 31 to 2 Bit Name — Initial Value All 0 R/W R* 1 Description Reserved These bits are always read as 0. The write value should always be 0. 1 BIE 0 R/W*1 Bank Interrupt Enable Enables or disables a bank interrupt request (HIFBI) issued to the on-chip CPU. 0: HIFBI disabled 1: HIFBI enabled Rev. 5.00 Mar. 15, 2007 Page 519 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Bit 0 Bit Name BIF Initial Value 0 R/W R/W* * 1 2 Description Bank Interrupt Request Flag While this bit is 1, a bank interrupt request (HIFBI) is issued to the on-chip CPU according to the setting of the BIE bit. In auto-increment mode (AI/AD bit in HIFMCR is 0), this bit is automatically set to 1 when an external device has completed access to the 32-bit data in the end address of HIFRAM and the HIFCS pin has been negated. In auto-decrement mode (AI/AD bit in HIFMCR is 1), this bit is automatically set to 1 when an external device has completed access to the 32-bit data in the start address of HIFRAM and the HIFCS pin has been negated. Though this bit can be cleared to 0 by the on-chip CPU, it cannot be set to 1. Make sure setting of this bit by HIFRAM access from an external device and clearing of this bit by the onchip CPU do not conflict using software. Notes: 1. This bit cannot be accessed by an external device. It can only be accessed by the onchip CPU. 2. Writing 1 to this bit by the on-chip CPU is ignored. Rev. 5.00 Mar. 15, 2007 Page 520 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) 17.5 Memory Map Table 17.3 shows the memory map of HIFRAM. Table 17.3 Memory Map Classification Map from external device* Map from on-chip CPU* * 1 1 2 Start Address H'0000 H'F84E0000 End Address H'03FF H'F84E03FF Memory Size 1 kbyte 1 kbyte Notes: 1. Map for a single HIFRAM bank. Which bank is to be accessed by an external device or the on-chip CPU depends on the BMD and BSEL bits in HIFSCR. The mapping addresses are common between the banks. 2. Note that in HIF boot mode, bank 0 is selected, and the first 1 kbyte in each of the following address ranges are also mapped: H'00000000 to H'01FFFFFF (first-half 32 Mbytes of area 0 in the P0 area), H'20000000 to H'21FFFFFF (first-half 32 Mbytes of area 0 in the P0 area), H'40000000 to H'41FFFFFF (first-half 32 Mbytes of area 0 in the P0 area), H'60000000 to H'61FFFFFF (first-half 32 Mbytes of area 0 in the P0 area), H'80000000 to H'81FFFFFF (first-half 32 Mbytes of area 0 in the P1 area), H'A0000000 to H'A1FFFFFF (first-half 32 Mbytes of area 0 in the P2 area), and H'C0000000 to H'C1FFFFFF (first-half 32 Mbytes of area 0 in the P3 area). If an external device modifies HIFRAM when HIFRAM is accessed from the P0, P1, or P3 area with the cache enabled, coherency may not be ensured. When the cache is enabled, accessing HIFRAM from the P2 area is recommended. In HIF boot mode, among the first-half 32 Mbytes of each area 0, access to the areas to which HIFRAM is not mapped is inhibited. Even in HIF boot mode, the second-half 32 Mbytes of area 0, area 3, area 4, area 5B, area 5, area 6B, and area 6 are mapped to the external memory as normally. Rev. 5.00 Mar. 15, 2007 Page 521 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) 17.6 Interface (Basic) Figure 17.3 shows the basic read/write sequence. HIF read is defined by the overlap period of the HIFRD low-level period and HIFCS low-level period, and HIF write is defined by the overlap period of the HIFWR low-level period and HIFCS low-level period. The HIFRS signal indicates whether this is normal access or index/status register access; low level indicates normal access and high level indicates index/status register access. Write cycle HIFCS HIFRS HIFRD HIFWR HIFD15 to HIFD00 WT_D RD_D Read cycle Figure 17.3 Basic Timing for HIF Interface Rev. 5.00 Mar. 15, 2007 Page 522 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) 17.7 17.7.1 Interface (Details) HIFIDX Write/HIFGSR Read Writing of HIFIDX and reading of HIFGSR are shown in figure 17.4. HIFIDX write cycle HIFGSR read cycle HIFCS HIFRS HIFRD HIFWR HIFD15 to HIFD00 WT_D RD_D Figure 17.4 HIFIDX Write and HIFGSR Read 17.7.2 Reading/Writing of HIF Registers other than HIFIDX and HIFGSR As shown in figure 17.5, in reading and writing of HIF internal registers other than HIFIDX and HIFGSR, first HIFRS is held high and HIFIDX is written to in order to select the register to be accessed and the byte location. Then HIFRS is held low, and reading or writing of the register selected by HIFIDX is performed. Index write Register write Register read HIFCS HIFRS HIFRD HIFWR HIFD15 to HIFD00 HIFIDX WT_D RD_D Register selection Figure 17.5 HIF Register Settings Rev. 5.00 Mar. 15, 2007 Page 523 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) 17.7.3 Consecutive Data Writing to HIFRAM by External Device Figure 17.6 shows the timing chart for consecutive data transfer from an external device to HIFRAM. As shown in this timing chart, by setting the start address and the data to be written first, consecutive data transfer can subsequently be performed. HIFCS HIFRS HIFRD HIFWR HIFD15 to HIFD00 0016 AHAL 0018 D0D1 001A D2D3 000A 00A0 0018 D4D5 D6D7 D8D9 High level HIFADR setting [15:8] = AH [7:0] = AL Data for first write operation set in HIFDATA [31:24] = D0, [23:16] = D1, [15:8] = D2, [7:0] = D3 HIFMCR setting HIFDATA Consecutive data writing Consecutive write selection Auto-increment Figure 17.6 Consecutive Data Writing to HIFRAM 17.7.4 Consecutive Data Reading from HIFRAM to External Device Figure 17.7 shows the timing chart for consecutive data reading from HIFRAM to an external device. As this timing chart indicates, by setting the start address, data can subsequently be read out consecutively. Rev. 5.00 Mar. 15, 2007 Page 524 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) HIFCS HIFRS HIFRD HIFWR HIFD15 to HIFD00 0016 AHAL 000A 0088 0018 D0D1 D2D3 D4D5 D6D7 D8D9 DADB DCDD HIFADR setting HIFMCR setting HIFDATA [15:8] = AH Consecutive read selection [7:0] = AL Auto-increment Consecutive data reading Figure 17.7 Consecutive Data Reading from HIFRAM 17.8 External DMAC Interface Figures 17.8 to 17.11 show the HIFDREQ output timing. The start of the HIFDREQ assert synchronizes with the DTRG bit in HIFDTR being set to 1. The HIFDREQ negate timing and assert level are determined by the DMD and DPOL bits in HIFSCR, respectively. When the external DMAC is specified to detect low level of the HIFDREQ signal, set DMD = 0 and DPOL = 0. After writing 1 to the DTRG bit, the HIFDREQ signal remains low until low level is detected for both the HIFCS and HIFRS signals. In this case, when the HIFDREQ signal is used, make sure that the setup time (HIFCS assertion to HIFRS settling) and the hold time (HIFRS hold to HIFCS negate) are satisfied. If tHIFAS and tHIFAH stipulated in section 25.4.11, HIF Timing, are not satisfied, the HIFDREQ signal may be negated unintentionally. Rev. 5.00 Mar. 15, 2007 Page 525 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) DTRG bit DPOL bit Asserted in synchronization with the DTRG bit being set by the on-chip CPU. HIFDREQ The DTRG bit is cleared simultaneously with HIFDREQ negate. Negated when HIFCS = HIFRS = low level. Latency is tPCYC (peripheral clock cycle) × 3 cyc or less. HIFCS HIFRS Figure 17.8 HIFDREQ Timing (When DMD = 0 and DPOL = 0) When the external DMAC is specified to detect high level of the HIFDREQ signal, set DMD = 0 and DPOL = 1. At the time the DPOL bit is set to 1, HIFDREQ becomes low. Then after writing 1 to the DTRG bit, HIFDREQ remains high until low level is detected for both the HIFCS and HIFRS signals. In this case, when the HIFDREQ signal is used, make sure that the setup time (HIFCS assertion to HIFRS settling) and the hold time (HIFRS hold to HIFCS negate) are satisfied. If tHIFAS and tHIFAH stipulated in section 25.4.11, HIF Timing, are not satisfied, the HIFDREQ signal may be negated unintentionally. DTRG bit DPOL bit Negated in synchronization with the DPOL bit being set by the on-chip CPU. Asserted in synchronization with the DTRG bit being set by the on-chip CPU. The DTRG bit is cleared simultaneously with HIFDREQ negate. HIFDREQ Negated when HIFCS = HIFRS = low level. Latency is tPCYC (peripheral clock cycle) × 3 cyc or less. HIFCS HIFRS Figure 17.9 HIFDREQ Timing (When DMD = 0 and DPOL = 1) Rev. 5.00 Mar. 15, 2007 Page 526 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) When the external DMAC is specified to detect the falling edge of the HIFDREQ signal, set DMD = 1 and DPOL = 0. After writing 1 to the DTRG bit, a low pulse of 32 peripheral clock cycles is generated at the HIFDREQ pin. DTRG bit DPOL bit Asserted in synchronization with the DTRG bit being set by the on-chip CPU. The DTRG bit is cleared simultaneously with HIFDREQ negate. After assert, negated when tPCYC (peripheral clock cycle) × 32 cyc have elapsed. HIFDREQ Figure 17.10 HIFDREQ Timing (When DMD = 1 and DPOL = 0) When the external DMAC is specified to detect the rising edge of the HIFDREQ signal, set DMD = 1 and DPOL = 1. At the time the DPOL bit is set to 1, HIFDREQ becomes low. Then after writing 1 to the DTRG bit, a low pulse of 32 peripheral clock cycles is generated at the HIFDREQ pin. DTRG bit DPOL bit Negated in synchronization with the DPOL bit being set by the on-chip CPU. Asserted in synchronization with the DTRG bit being set by the on-chip CPU. The DTRG bit is cleared simultaneously with HIFDREQ negate. HIFDREQ After assert, negated when tPCYC (peripheral clock cycle) × 32 cyc have elapsed. Figure 17.11 HIFDREQ Timing (When DMD = 1 and DPOL = 1) When the external DMAC supports intermittent operating mode (block transfer mode), efficient data transfer can be implemented by using the HIFRAM consecutive access and bank functions. Rev. 5.00 Mar. 15, 2007 Page 527 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Table 17.4 Consecutive Write Procedure to HIFRAM by External DMAC External Device No. 1 2 3 CPU HIF initial setting DMAC initial setting Set HIFADR to HIFRAM end address −8 Select HIFDATA and write dummy data (4 bytes) to HIFDATA Set HIFRAM consecutive write with address increment in HIFMCR Select HIFDATA and → write dummy data (4 bytes) to HIFDATA → HIF bank interrupt occurs → HIFRAM bank switching by HIF bank interrupt handler (external device accesses bank 1 and onchip CPU accesses bank 0) ← Set DTRG bit to 1 DMAC HIF This LSI CPU HIF initial setting 4 5 6 7 8 Activate DMAC Consecutive data write to bank 1 in HIFRAM ← Assert HIFDREQ 9 Write to end → HIF bank address of bank interrupt 1 in HIFRAM occurs completes and operation halts Re-activate DMAC Consecutive data write to bank 0 in HIFRAM ← Assert HIFDREQ → HIFRAM bank switching by HIF bank interrupt handler (external device accesses bank 0 and onchip CPU accesses bank 1) ← Set DTRG bit to 1 Read data from bank 1 in HIFRAM 10 11 Rev. 5.00 Mar. 15, 2007 Page 528 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) External Device No. 12 CPU DMAC HIF Write to end → HIF bank address of bank interrupt 0 in HIFRAM occurs completes and operation halts Re-activate DMAC ← Assert HIFDREQ This LSI CPU → HIFRAM bank switching by HIF bank interrupt handler (external device accesses bank 1 and onchip CPU accesses bank 0) ← Set DTRG bit to 1 13 Hereafter No. 11 to 13 are repeated. When a register other than HIFDATA is accessed (except that HIFGSR read with HIFRS = low), HIFRAM consecutive write is interrupted, and No. 3 to 6 need to be done again. Table 17.5 Consecutive Read Procedure from HIFRAM by External DMAC External Device No. 1 2 3 CPU HIF initial setting DMAC initial setting Set HIFADR to HIFRAM start address Set HIFRAM consecutive read with address increment in HIFMCR Select HIFDATA Write data to bank 1 in HIFRAM After writing data to end address of bank 1 in HIFRAM, perform HIFRAM bank switching (external device accesses bank 1 and onchip CPU accesses bank 0) Activate DMAC ← Assert HIFDREQ ← Set DTRG bit to 1 DMAC HIF This LSI CPU HIF initial setting 4 5 6 7 8 Rev. 5.00 Mar. 15, 2007 Page 529 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) External Device No. 9 CPU DMAC Consecutive data read from bank 1 in HIFRAM Read from end → HIF bank address of bank interrupt 1 in HIFRAM occurs completes and operation halts Re-activate DMAC Consecutive data read from bank 0 in HIFRAM Read from end → HIF bank address of bank interrupt 0 in HIFRAM occurs completes and operation halts Re-activate DMAC ← Assert HIFDREQ ← Assert HIFDREQ HIF This LSI CPU Write data to bank 0 in HIFRAM 10 → HIFRAM bank switching by HIF bank interrupt handler (external device accesses bank 0 and onchip CPU accesses bank 1) ← Set DTRG bit to 1 Write data to bank 1 in HIFRAM 11 12 13 → HIFRAM bank switching by HIF bank interrupt handler (external device accesses bank 1 and onchip CPU accesses bank 0) ← Set DTRG bit to 1 14 Hereafter No. 12 to 14 are repeated. When a register other than HIFDATA is accessed (except that HIFGSR read with HIFRS = low), HIFRAM consecutive read is interrupted, and No. 3 to 5 need to be done again. Rev. 5.00 Mar. 15, 2007 Page 530 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) 17.9 Alignment Control Tables 17.6 and 17.7 show the alignment control when an external device accesses the HIFDATA register, and the HIF registers other than the HIFDATA register, respectively. Table 17.6 HIFDATA Register Alignment for Access by an External Device Data in HIFDATA WBSWP Bit H'76543210 0 BO Bit 0 BYTE[1:0] Bits B'00 B'10 1 B'00 B'10 1 0 B'00 B'10 1 B'00 B'10 Alignment in HIFD[15:0] Pins H'7654 H'3210 H'3210 H'7654 H'1032 H'5476 H'5476 H'1032 Table 17.7 HIF Registers (other than HIFDATA) Alignment for Access by an External Device Data in HIFDATA WBSWP Bit H'76543210 Don't care BO Bit 0 BYTE[1:0] Bits B'00 B'10 1 B'00 B'10 Alignment in HIFD[15:0] Pins H'7654 H'3210 H'3210 H'7654 Rev. 5.00 Mar. 15, 2007 Page 531 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) 17.10 Interface When External Device Power is Cut Off When the power supply of an external device interfacing with the HIF is cut off, intermediate levels may be applied to the HIF input pins or the HIF output pins may drive an external device not powered, thus causing the device to be damaged. The HIFEBL pin is provided to prevent this from happening. The system power monitor block controls the HIFEBL pin in synchronization with the cutoff of the external device power so that all HIF pins can be set to the high-impedance state. Figure 17.12 shows an image of high-impedance control of the HIF pins. Table 17.8 lists the input/output control for the HIF pins. HIFD15 to HIFD00 HIFCS HIFRS HIFWR HIFRD HIFMD HIFINT HIFDREQ HIFRDY HIFEBL Figure 17.12 Image of High-Impedance Control of HIF Pins by HIFEBL Pin Rev. 5.00 Mar. 15, 2007 Page 532 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) Table 17.8 Input/Output Control for HIF Pins LSI Status HIFMD input level Reset State by RES Pin Low (Non-boot setting) The HIFEBL pin is a general input port and the HIF is not controlled by the signal input on this pin. General input port Reset Canceled by RES Pin High (After the reset canceled by boot setting) Low (After the reset canceled by non-boot setting) High (Boot setting) HIFEBL input level HIFRDY output control Low Output buffer: On (Low output) Output buffer: Off High Output buffer: On (Low output) Output buffer: Off Output buffer: Off I/O buffer: Off Low Output buffer: Off High Output buffer: On (Sequence output) Output buffer: On (Sequence output) Output buffer: On (Sequence output) General input port at the 1 initial state * General input port at the 2 initial state* HIFINT output control General input port Output buffer: Off Output buffer: Off I/O buffer: Off General input port at the 2 initial state* HIFDREQ Output buffer: output Off control HIFD 15 to HIFD0 I/O control I/O buffer: Off General input port General input port at the 2 initial state* General input port General input port at the I/O buffer 2 initial state* controlled according to states of HIFCS, HIFWR, and HIFRD HIFCS input control HIFRS input control Input buffer: Off Input buffer: Off Input buffer: Off Input buffer: Off General input port Input buffer: Input buffer: General input port at the 2 Off On initial state* Input buffer: Input buffer: General input port at the 2 Off On initial state* General input port Rev. 5.00 Mar. 15, 2007 Page 533 of 794 REJ09B0237-0500 Section 17 Host Interface (HIF) LSI Status HIFMD input level Reset State by RES Pin Reset Canceled by RES Pin High (After the reset canceled by boot setting) Low (After the reset canceled by non-boot setting) High (Boot setting) Low (Non-boot setting) The HIFEBL pin is a general input port and the HIF is not controlled by the signal input on this pin. General input port HIFEBL input level HIFWR input control HIFRD input control Low Input buffer: Off Input buffer: Off High Input buffer: Off Input buffer: Off Low Input buffer: Off Input buffer: Off High Input buffer: On Input buffer: On General input port at the initial 1 state * General input port at the initial 2 state* General input port General input port at the initial 2 state* Notes: 1. The pin also functions as an HIFEBL pin by setting the PFC registers. 2. The pin also functions as an HIF pin by setting the PFC registers. When the HIF pin function is selected for the HIFEBL pin and this pin by setting the PFC registers, the input and/or output buffers are controlled according to the HIFEBL pin state. When the HIF pin function is not selected for the HIFEBL pin and is selected for this pin by setting the PFC registers, the input and/or output buffers are always turned off. This setting is prohibited. Rev. 5.00 Mar. 15, 2007 Page 534 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Section 18 Pin Function Controller (PFC) The pin function controller (PFC) consists of registers that select multiplexed pin functions and input/output directions. Tables 18.1 to 18.5 show the multiplexed pins in this LSI. Table 18.6 shows the pin functions in each operating mode. Table 18.1 List of Multiplexed Pins (Port A) Port A Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module)      SCK_SIO0 input/output (SIOF) Function 4 (Related Module)       PA16 input/output (port) A16 output (BSC) PA17 input/output (port) A17 output (BSC) PA18 input/output (port) A18 output (BSC) PA19 input/output (port) A19 output (BSC) PA20 input/output (port) A20 output (BSC) PA21 input/output (port) A21 output (BSC) PA22 input/output (port) A22 output (BSC) PA23 input/output (port) A23 output (BSC) PA24 input/output (port) A24 output (BSC) PA25 input/output (port) A25 output (BSC) SIOMCLK0 input (SIOF)  RXD_SIO0 input (SIOF)  TXD_SIO0 output (SIOF) SIOFSYNC0 input/output (SIOF)   Table 18.2 List of Multiplexed Pins (Port B) Function 1 (Related Module) PB00 input/output (port) PB01 input/output (port) PB02 input/output (port) CKE output (BSC) Function 2 (Related Module) WAIT input (BSC) IOIS16 input (BSC) Function 3 (Related Module)  Function 4 (Related Module)  Port B     Rev. 5.00 Mar. 15, 2007 Page 535 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Port B Function 1 (Related Module) PB03 input/output (port) PB04 input/output (port) PB05 input/output (port) PB06 input/output (port) PB07 input/output (port) PB08 input/output (port) PB09 input/output (port) PB10 input/output (port) PB11 input/output (port) PB12 input/output (port) PB13 input/output (port) Function 2 (Related Module) CAS output (BSC) RAS output (BSC) WE2(BE2) output (BSC) WE3(BE3) output (BSC) DQMUL output (BSC) ICIORD output (BSC) Function 3 (Related Module)  Function 4 (Related Module)      DQMUU output ICIOWR output  (BSC) (BSC) CE2B output (BSC)    CS6B output (BSC) CE1B output (BSC) CE2A output (BSC)     CS5B output (BSC) CS4 output (BSC) CS3 output (BSC) BS output (BSC) CE1A output (BSC)         Rev. 5.00 Mar. 15, 2007 Page 536 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Table 18.3 List of Multiplexed Pins (Port C) Port C Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) Function 4 (Related Module)     SPEED100 output (PHY) LINK output (PHY) CRS output (PHY) DUPLEX output (PHY)              PC00 input/output (port) MII_RXD0 input (EtherC)  PC01 input/output (port) MII_RXD1 input (EtherC)  PC02 input/output (port) MII_RXD2 input (EtherC)  PC03 input/output (port) MII_RXD3 input (EtherC)  PC04 input/output (port) MII_TXD0 output (EtherC) PC05 input/output (port) MII_TXD1 output (EtherC) PC06 input/output (port) MII_TXD2 output (EtherC) PC07 input/output (port) MII_TXD3 output (EtherC) PC08 input/output (port) RX_DV input (EtherC) PC09 input/output (port) RX_ER input (EtherC) PC10 input/output (port) RX_CLK input (EtherC) PC11 input/output (port) TX_ER output (EtherC) PC12 input/output (port) TX_EN output (EtherC) PC13 input/output (port) TX_CLK input (EtherC) PC14 input/output (port) COL input (EtherC) PC15 input/output (port) CRS input (EtherC) PC16 input/output (port) MDIO input/output (EtherC) PC17 input/output (port) MDC output (EtherC) PC18 input/output (port) LNKSTA input (EtherC) PC19 input/output (port) EXOUT output (EtherC) PC20 input/output (port) WOL output (EtherC)                  Rev. 5.00 Mar. 15, 2007 Page 537 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Table 18.4 List of Multiplexed Pins (Port D) Port D Function 1 (Related Module) PD0 input/output (port) PD1 input/output (port) PD2 input/output (port) PD3 input/output (port) PD4 input/output (port) PD5 input/output (port) PD6 input/output (port) PD7 input/output (port) Function 2 (Related Module) IRQ0 input (INTC) IRQ1 input (INTC) IRQ2 input (INTC) IRQ3 input (INTC) IRQ4 input (INTC) IRQ5 input (INTC) IRQ6 input (INTC) IRQ7 input (INTC) Function 3 (Related Module)   TxD1 output (SCIF) RxD1 input (SCIF) Function 4 (Related Module) TEND0 output (DMAC) TEND1 output (DMAC) DREQ0 input (DMAC) DACK0 output (DMAC) SCK1 input/output (SCIF)  TxD2 output (SCIF) RxD2 input (SCIF) DREQ1 input (DMAC) DACK1 output (DMAC) SCK2 input/output (SCIF)  Table 18.5 List of Multiplexed Pins (Port E) Port E Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) SCK_SIO0 input/output (SIOF) SIOMCLK0 input (SIOF) RXD_SIO0 input (SIOF)  Function 4 (Related Module)     PE00 input/output (port) HIFEBL input (HIF) PE01 input/output (port) HIFRDY output (HIF) PE02 input/output (port) HIFDREQ output (HIF) PE03 input/output (port) HIFMD input (HIF) PE04 input/output (port) HIFINT output (HIF) PE05 input/output (port) HIFRD input (HIF) PE06 input/output (port) HIFWR input (HIF) PE07 input/output (port) HIFRS input (HIF) PE08 input/output (port) HIFCS input (HIF) TXD_SIO0 output (SIOF)   SIOSYNC0 input/output (SIOF)       D16 input/output (BSC) D17 input/output (BSC) D18 input/output (BSC) D19 input/output (BSC) PE09 input/output (port) HIFD00 input/output (HIF)  PE10 input/output (port) HIFD01 input/output (HIF)  PE11 input/output (port) HIFD02 input/output (HIF)  PE12 input/output (port) HIFD03 input/output (HIF)  Rev. 5.00 Mar. 15, 2007 Page 538 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Port E Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) Function 4 (Related Module) D20 input/output (BSC) D21 input/output (BSC) D22 input/output (BSC) D23 input/output (BSC) PE13 input/output (port) HIFD04 input/output (HIF)  PE14 input/output (port) HIFD05 input/output (HIF)  PE15 input/output (port) HIFD06 input/output (HIF) TxD0 output (SCIF) PE16 input/output (port) HIFD07 input/output (HIF) RxD0 input (SCIF) PE17 input/output (port) HIFD08 input/output (HIF) SCK0 input/output (SCIF) D24 input/output (BSC) PE18 input/output (port) HIFD09 input/output (HIF) TxD1 output (SCIF) PE19 input/output (port) HIFD10 input/output (HIF) RxD1 input (SCIF) D25 input/output (BSC) D26 input/output (BSC) PE20 input/output (port) HIFD11 input/output (HIF) SCK1 input/output (SCIF) D27 input/output (BSC) PE21 input/output (port) HIFD12 input/output (HIF) RTS0 output (SCIF) PE22 input/output (port) HIFD13 input/output (HIF) CTS0 input (SCIF) PE23 input/output (port) HIFD14 input/output (HIF) RTS1 output (SCIF) PE24 input/output (port) HIFD15 input/output (HIF) CTS1 input (SCIF) D28 input/output (BSC) D29 input/output (BSC) D30 input/output (BSC) D31 input/output (BSC) Rev. 5.00 Mar. 15, 2007 Page 539 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Table 18.6 Pin Functions in Each Operating Mode Pin No. C13 A14 B13 A13 C12 B12 D11 A12 C11 B11 D10 A11 C10 A10 D9 B10 A5 B5 A4 D5 B4 C4 A3 D4 B3 A2 B8 D6 C15 Not HIF Boot Mode Initial Function A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PB00 PB01 PB02 HIF Boot Mode Function Settable by PFC Initial Function                 PA16/A16 PA17/A17 PA18/A18 PA19/A19 PA20/A20 PA21/A21/SCK_SIO0 PA22/A22/SIOMCLK0 PA23/A23/RXD_SIO0 PA24/A24/TXD_SIO0 PA25/A25/SIOFSYNC0 PB00/WAIT PB01/IOIS16 PB02/CKE A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PB00 PB01 PB02 Function Settable by PFC                 PA16/A16 PA17/A17 PA18/A18 PA19/A19 PA20/A20 PA21/A21/SCK_SIO0 PA22/A22/SIOMCLK0 PA23/A23/RXD_SIO0 PA24/A24/TXD_SIO0 PA25/A25/SIOFSYNC0 PB00/WAIT PB01/IOIS16 PB02/CKE Rev. 5.00 Mar. 15, 2007 Page 540 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Pin No. D12 C14 D15 D14 D7 C7 A8 D13 B6 C5 A6 C6 C8 A15 D8 C9 R6 M7 P6 N7 P8 M9 R9 N9 N6 M6 R8 N8 Not HIF Boot Mode Initial Function PB03 PB04 (WE0/DQMLL) (WE1/DQMLU/WE) PB05 PB06 RD RDWR PB07 PB08 PB09 PB10 PB11 PB12 CS0 PB13 PC00 PC01 PC02 PC03 PC04 PC05 PC06 PC07 PC08 PC09 PC10 PC11 HIF Boot Mode Function Settable by PFC Initial Function PB03/CAS PB04/RAS   PB05/WE2(BE2)/DQMUL/ ICIORD PB03 PB04 (WE0/DQMLL) (WE1/DQMLU/WE) PB05 Function Settable by PFC PB03/CAS PB04/RAS   PB05/WE2(BE2)/DQMUL/ ICIORD PB06/WE3(BE3)/DQMUU/ ICIOWR   PB07/CE2B PB08/(CS6B/CE1B) PB09/CE2A PB10/(CS5B/CE1A) PB11/CS4 PB12/CS3  PB13/BS PC00/MII_RXD0 PC01/MII_RXD1 PC02/MII_RXD2 PC03/MII_RXD3 PC04/MII_TXD0/ SPEED100 PC05/MII_TXD1/LINK PC06/MII_TXD2/CRS PC07/MII_TXD3/DUPLEX PC08/RX_DV PC09/RX_ER PC10/RX_CLK PC11/TX_ER PB06/WE3(BE3)/DQMUU/ PB06 ICIOWR   PB07/CE2B PB08/(CS6B/CE1B) PB09/CE2A PB10/(CS5B/CE1A) PB11/CS4 PB12/CS3  PB13/BS PC00/MII_RXD0 PC01/MII_RXD1 PC02/MII_RXD2 PC03/MII_RXD3 PC04/MII_TXD0/ SPEED100 PC05/MII_TXD1/LINK PC06/MII_TXD2/CRS PC07/MII_TXD3/DUPLEX PC08/RX_DV PC09/RX_ER PC10/RX_CLK PC11/TX_ER RD RDWR PB07 PB08 PB09 PB10 PB11 PB12 CS0 PB13 PC00 PC01 PC02 PC03 PC04 PC05 PC06 PC07 PC08 PC09 PC10 PC11 Rev. 5.00 Mar. 15, 2007 Page 541 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Pin No. P9 M8 R10 P1 N2 M4 P2 N11 P10 D1 E4 D2 D3 C1 C2 C3 B2 N1 M3 M2 L4 M1 L2 L1 L3 E3 K3 K4 J2 J3 Not HIF Boot Mode Initial Function PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE00 PE01 PE02 HIFMD PE04 PE05 PE06 PE07 PE08 PE09 PE10 PE11 PE12 HIF Boot Mode Function Settable by PFC Initial Function PC12/TX_EN PC13/TX_CLK PC14/COL PC15/CRS PC16/MDIO PC17/MDC PC18/LNKSTA PC19/EXOUT PC20/WOL PD0/IRQ0/TEND0 PD1/IRQ1/TEND1 PD2/IRQ2/TxD1/DREQ0 PD3/IRQ3/RxD1/DACK0 PD4/IRQ4/SCK1 PD5/IRQ5/TxD2/DREQ1 PD6/IRQ6/RxD2/DACK1 PD7/IRQ7/SCK2 PE00/HIFEBL/SCK_SIO0 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 HIFEBL Function Settable by PFC PC12/TX_EN PC13/TX_CLK PC14/COL PC15/CRS PC16/MDIO PC17/MDC PC18/LNKSTA PC19/EXOUT PC20/WOL PD0/IRQ0/TEND0 PD1/IRQ1/TEND1 PD2/IRQ2/TxD1/DREQ0 PD3/IRQ3/RxD1DACK0 PD4/IRQ4/SCK1 PD5/IRQ5/TxD2/DREQ1 PD6/IRQ6/RxD2/DACK1 PD7/IRQ7/SCK2 PE00/HIFEBL/SCK_SIO0 PE01/HIFRDY/SIOMCLK0 PE02/HIFDREQ/ RXD_SIO0 PE03/HIFMD PE04/HIFINT/TXD_SIO0 PE05/HIFRD PE06/HIFWR/SIOFSYNC0 PE07/HIFRS PE08/HIFCS PE09/HIFD00/D16 PE10/HIFD01/D17 PE11/HIFD02/D18 PE12/HIFD03/D19 PE01/HIFRDY/SIOMCLK0 HIFRDY PE02/HIFDREQ/ RXD_SIO0 PE03/HIFMD PE04/HIFINT/TXD_SIO0 PE05/HIFRD HIFDREQ HIFMD HIFINT HIFRD PE06/HIFWR/SIOFSYNC0 HIFWR PE07/HIFRS PE08/HIFCS PE09/HIFD00/D16 PE10/HIFD01/D17 PE11/HIFD02/D18 PE12/HIFD03/D19 HIFRS HIFCS HIFD00 HIFD01 HIFD02 HIFD03 Rev. 5.00 Mar. 15, 2007 Page 542 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Pin No. J1 J4 H2 H1 G2 G1 G3 F2 G4 F1 F3 F4 K14 J13 J15 H12 J14 H13 G12 G15 E15 E14 F14 F13 F15 F12 G14 G13 M14 N12 Not HIF Boot Mode Initial Function PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 TRST input TDO output HIF Boot Mode Function Settable by PFC Initial Function PE13/HIFD04/D20 PE14/HIFD05/D21 PE15/HIFD06/TxD0/D22 PE16/HIFD07/RxD0/D23 PE17/HIFD08/SCK0/D24 PE18/HIFD09/TxD1/D25 PE19/HIFD10/RxD1/D26 PE20/HIFD11/SCK1/D27 PE21/HIFD12/RTS0/D28 PE22/HIFD13/CTS0/D29 PE23/HIFD14/RTS1/D30 PE24/HIFD15/CTS1/D31                   HIFD04 HIFD05 HIFD06 HIFD07 HIFD08 HIFD09 HIFD10 HIFD11 HIFD12 HIFD13 HIFD14 HIFD15 D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 TRST input TDO output Function Settable by PFC PE13/HIFD04//D20 PE14/HIFD05/D21 PE15/HIFD06/TxD0/D22 PE16/HIFD07/RxD0/D23 PE17/HIFD08/SCK0/D24 PE18/HIFD09/TxD1/D25 PE19/HIFD10/RxD1/D26 PE20/HIFD11/SCK1/D27 PE21/HIFD12/RTS0/D28 PE22/HIFD13/CTS0/D29 PE23/HIFD14/RTS1/D30 PE24/HIFD15/CTS1/D31                   Rev. 5.00 Mar. 15, 2007 Page 543 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Pin No. M12 M13 P12 R13 R14 K15 P11 L13 L14 R12 J12 L15 N13 M15 L12 M11 R11 Not HIF Boot Mode Initial Function TDI input TMS input TCK input EXTAL input XTAL output CKIO output CK_PHY input ASEMD input TESTMD input MD3 input MD2 input MD1 input MD0 input RES input NMI input MD5 input TESTOUT output HIF Boot Mode Function Settable by PFC Initial Function                  TDI input TMS input TCK input EXTAL input XTAL output CKIO output CK_PHY input ASEMD input TESTMD input MD3 input MD2 input MD1 input MD0 input RES input NMI input MD5 input TESTOUT output Function Settable by PFC                  Rev. 5.00 Mar. 15, 2007 Page 544 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) 18.1 Register Descriptions The PFC has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 24, List of Registers. • • • • • • • • • • • • • • • • • • • Port A IO register H (PAIORH) Port A control register H1 (PACRH1) Port A control register H2 (PACRH2) Port B IO register L (PBIORL) Port B control register L1 (PBCRL1) Port B control register L2 (PBCRL2) Port C IO register H (PCIORH) Port C IO register L (PCIORL) Port C control register H2 (PCCRH2) Port C control register L1 (PCCRL1) Port C control register L2 (PCCRL2) Port D IO register L (PDIORL) Port D control register L2 (PDCRL2) Port E IO register H (PEIORH) Port E IO register L (PEIORL) Port E control register H1 (PECRH1) Port E control register H2 (PECRH2) Port E control register L1 (PECRL1) Port E control register L2 (PECRL2) Rev. 5.00 Mar. 15, 2007 Page 545 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) 18.1.1 Port A IO Register H (PAIORH) PAIORH is a 16-bit readable/writable register that selects the input/output directions of the port A pins. Bits PA25IOR to PA16IOR correspond to pins PA25 to PA16 (the pin name abbreviations for multiplexed functions are omitted). PAIORH is enabled when a port A pin functions as a general input/output (PA25 to PA16), otherwise, disabled. Setting a bit in PAIORH to 1 makes the corresponding pin function as an output and clearing a bit in PAIORH to 0 makes the pin function as an input. Bits 15 to 10 in PAIORH are reserved. These bits are always read as 0. The write value should always be 0. The initial value of PAIORH is H'0000. 18.1.2 Port A Control Register H1 and H2 (PACRH1 and PACRH2) PACRH1 and PACRH2 are 16-bit readable/writable registers that select the pin functions for the multiplexed port A pins. • PACRH1 Bit 15 to 4 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 2 PA25MD1 PA25MD0 0 0 R/W R/W PA25 Mode Select the function of pin PA25/A25/SIOFSYNC0. 00: PA25 input/output (port) 01: A25 output (BSC) 10: SIOFSYNC0 input/output (SIOF) 11: Setting prohibited Rev. 5.00 Mar. 15, 2007 Page 546 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 1 0 Bit Name PA24MD1 PA24MD0 Initial Value 0 0 R/W R/W R/W Description PA24 Mode Select the function of pin PA24/A24/TXD_SIO0. 00: PA24 input/output (port) 01: A24 output (BSC) 10: TXD_SIO0 output (BSC) 11: Setting prohibited • PACRH2 Bit 15 14 Bit Name PA23MD1 PA23MD0 Initial Value 0 0 R/W R/W R/W Description PA23 Mode Select the function of pin PA23/A23/RXD_SIO0. 00: PA23 input/output (port) 01: A23 output (BSC) 10: RXD_SIO0 input (SIOF) 11: Setting prohibited 13 12 PA22MD1 PA22MD0 0 0 R/W R/W PA22 Mode Select the function of pin PA22/A22/SIOMCLK0. 00: PA22 input/output (port) 01: A22 output (BSC) 10: SIOMCLK0 input (SIOF) 11: Setting prohibited 11 10 PA21MD1 PA21MD0 0 0 R/W R/W PA21 Mode Select the function of pin PA21/A21/SCK_SIO0. 00: PA21 input/output (port) 01: A21 output (BSC) 10: SCK_SIO0 input/output (SIOF) 11: Setting prohibited 9  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 547 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 8 Bit Name PA20MD0 Initial Value 0 R/W R/W Description PA20 Mode Selects the function of pin PA20/A20. 0: PA20 input/output (port) 1: A20 output (BSC) 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PA19MD0 0 R/W PA19 Mode Selects the function of pin PA19/A19. 0: PA19 input/output (port) 1: A19 output (BSC) 5  0 R Reserved This bit is always read as 0. The write value should always be 0. 4 PA18MD0 0 R/W PA18 Mode Selects the function of pin PA18/A18. 0: PA18 input/output (port) 1: A18 output (BSC) 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PA17MD0 0 R/W PA17 Mode Selects the function of pin PA17/A17. 0: PA17 input/output (port) 1: A17 output (BSC) 1  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 PA16MD0 0 R/W PA16 Mode Selects the function of pin PA16/A16. 0: PA16 input/output (port) 1: A16 output (BSC) Rev. 5.00 Mar. 15, 2007 Page 548 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) 18.1.3 Port B IO Register L (PBIORL) PBIORL is a 16-bit readable/writable register that selects the input/output directions of the port B pins. Bits PB13IOR to PB0IOR correspond to pins PB13 to PB00 (the pin name abbreviations for multiplexed functions are omitted). PBIORL is enabled when a port B pin functions as a general input/output (PB13 to PB00), otherwise, disabled. Setting a bit in PBIORL to 1 makes the corresponding pin function as an output and clearing a bit in PBIORL to 0 makes the pin function as an input. Bits 15 and 14 in PBIORL are reserved. These bits are always read as 0. The write value should always be 0. The initial value of PAIBRL is H'0000. 18.1.4 Port B Control Register L1 and L2 (PBCRL1 and PBCRL2) PBCRL1 and PBCRL2 are 16-bit readable/writable registers that select the pin functions for the multiplexed port B pins. • PBCRL1 Bit 15 to 11 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 PB13MD0 0 R/W PB13 Mode Selects the function of pin PB13/BS. 0: PB13 input/output (port) 1: BS output (BSC) 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8 PB12MD0 0 R/W PB12 Mode Selects the function of pin PB12/CS3. 0: PB12 input/output (port) 1: CS3 output (BSC) Rev. 5.00 Mar. 15, 2007 Page 549 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 7 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 PB11MD0 0 R/W PB11 Mode Selects the function of pin PB11/CS4. 0: PB11 input/output (port) 1: CS4 output (BSC) 5  0 R Reserved This bit is always read as 0. The write value should always be 0. 4 PB10MD0 0 R/W PB10 Mode Selects the function of pin PB10/CS5B/CE1A. 0: PB10 input/output (port) 1: CS5B/CE1A output (BSC) 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PB9MD0 0 R/W PB9 Mode Selects the function of pin PB09/CE2A. 0: PB09 input/output (port) 1: CE2A output (BSC) 1  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 PB8MD0 0 R/W PB8 Mode Selects the function of pin PB08/CS6B/CE1B. 0: PB08 input/output (port) 1: CS6B/CE1B output (BSC) Rev. 5.00 Mar. 15, 2007 Page 550 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) • PBCRL2 Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 PB7MD0 0 R/W PB7 Mode Selects the function of pin PB07/CE2B. 0: PB07 input/output (port) 1: CE2B output (BSC) 13  0 R Reserved This bit is always read as 0. The write value should always be 0. 12 PB6MD0 0 R/W PB6 Mode Selects the function of pin PB06/WE3(BE3)/DQMUU/ICIOWR. 0: PB06 input/output (port) 1: WE3(BE3)/DQMUU/ICIOWR output (BSC) 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PB5MD0 0 R/W PB5 Mode Selects the function of pin PB05/WE2(BE2)/DQMUL/ICIORD. 0: PB05 input/output (port) 1: WE2(BE2)/DQMUL/ICIORD output (BSC) 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8 PB4MD0 0 R/W PB4 Mode Selects the function of pin PB04/RAS. 0: PB04 input/output (port) 1: RAS output (BSC) Rev. 5.00 Mar. 15, 2007 Page 551 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 7 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 PB3MD0 0 R/W PB3 Mode Selects the function of pin PB03/CAS. 0: PB03 input/output (port) 1: CAS output (BSC) 5  0 R Reserved This bit is always read as 0. The write value should always be 0. 4 PB2MD0 0 R/W PB2 Mode Selects the function of pin PB02/CKE. 0: PB02 input/output (port) 1: CKE output (BSC) 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PB1MD0 0 R/W PB1 Mode Selects the function of pin PB01/IOIS16. 0: PB01 input/output (port) 1: IOIS16 input (BSC) 1  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 PB0MD0 0 R/W PB0 Mode Selects the function of pin PB00/WAIT. 0: PB00 input/output (port) 1: WAIT input (BSC) Rev. 5.00 Mar. 15, 2007 Page 552 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) 18.1.5 Port C IO Register H and L (PCIORH and PCIORL) PCIORH and PCIORL are 16-bit readable/writable registers that select the input/output directions of the port C pins. Bits PC20IOR to PC0IOR correspond to pins PC20 to PC00 (the pin name abbreviations for multiplexed functions are omitted). PCIORH is enabled when a port C pin functions as a general input/output (PC20 to PC16), otherwise, disabled. PCIORL is enabled when a port C pin functions as a general input/output (PC15 to PC00), otherwise, disabled. Setting a bit in PCIORH and PCIORL to 1 makes the corresponding pin function as an output and clearing a bit in PCIORH and PCIORL to 0 makes the pin function as an input. Bits 15 to 5 in PCIORH are reserved. These bits are always read as 0. The write value should always be 0. The initial values of PCIORH and PCIORL are H'0000. 18.1.6 Port C Control Register H2, L1, and L2 (PCCRH2, PCCRL1, and PCCRL2) PCCRH2, PCCRL1, and PCCRL2 are 16-bit readable/writable registers that select the pin functions for the multiplexed port C pins. • PCCRH2 Bit 15 to 9 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 8 PC20MD0 0 R/W PC20 Mode Selects the function of pin PC20/WOL. 0: PC20 input/output (port) 1: WOL output (EtherC) 7  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 553 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 6 Bit Name PC19MD0 Initial Value 0 R/W R/W Description PC19 Mode Selects the function of pin PC19/EXOUT. 0: PC19 input/output (port) 1: EXOUT output (EtherC) 5  0 R Reserved This bit is always read as 0. The write value should always be 0. 4 PC18MD0 0 R/W PC18 Mode Selects the function of pin PC18/LNKSTA. 0: PC18 input/output (port) 1: LNKSTA input (EtherC) 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PC17MD0 0 R/W PC17 Mode Selects the function of pin PC17/MDC. 0: PC17 input/output (port) 1: MDC output (EtherC) 1  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 PC16MD0 0 R/W PC16 Mode Selects the function of pin PC16/MDIO. 0: PC16 input/output (port) 1: MDIO input/output (EtherC) Rev. 5.00 Mar. 15, 2007 Page 554 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) • PCCRL1 Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 PC15MD0 0 R/W PC15 Mode Selects the function of pin PC15/CRS. 0: PC15 input/output (port) 1: CRS input (EtherC) 13  0 R Reserved This bit is always read as 0. The write value should always be 0. 12 PC14MD0 0 R/W PC14 Mode Selects the function of pin PC14/COL. 0: PC14 input/output (port) 1: COL input (EtherC) 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PC13MD0 0 R/W PC13 Mode Selects the function of pin PC13/TX_CLK. 0: PC13 input/output (port) 1: TX_CLK input (EtherC) 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8 PC12MD0 0 R/W PC12 Mode Selects the function of pin PC12/TX_EN. 0: PC12 input/output (port) 1: TX_EN output (EtherC) Rev. 5.00 Mar. 15, 2007 Page 555 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 7 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 PC11MD0 0 R/W PC11 Mode Selects the function of pin PC11/TX_ER. 0: PC11 input/output (port) 1: TX_ER output (EtherC) 5  0 R Reserved This bit is always read as 0. The write value should always be 0. 4 PC10MD0 0 R/W PC10 Mode Selects the function of pin PC10/RX_CLK. 0: PC10 input/output (port) 1: RX_CLK input (EtherC) 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PC9MD0 0 R/W PC9 Mode Selects the function of pin PC09/RX_ER. 0: PC09 input/output (port) 1: RX_ER input (EtherC) 1  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 PC8MD0 0 R/W PC8 Mode Selects the function of pin PC08/RX_DV. 0: PC08 input/output (port) 1: RX_DV input (EtherC) Rev. 5.00 Mar. 15, 2007 Page 556 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) • PCCRL2 Bit 15 14 Bit Name PC7MD1 PC7MD0 Initial Value 0 0 R/W R/W R/W Description PC7 Mode Select the function of pin PC7/MII_TXD3/DUPLEX. 00: PC07 input/output (port) 01: MII_TXD3 output (EtherC) 10: Setting prohibited 11: DUPLEX output (PHY) 13 12 PC6MD1 PC6MD0 0 0 R/W R/W PC6 Mode Select the function of pin PC6/MII_TXD2/CRS. 00: PC06 input/output (port) 01: MII_TXD2 output (EtherC) 10: Setting prohibited 11: CRS output (PHY) 11 10 PC5MD1 PC5MD0 0 0 R/W R/W PC5 Mode Select the function of pin PC5/MII_TXD1/LINK. 00: PC05 input/output (port) 01: MII_TXD1 output (EtherC) 10: Setting prohibited 11: LINK output (PHY) 9 8 PC4MD1 PC4MD0 0 0 R/W R/W PC4 Mode Select the function of pin PC4/MII_TXD0/SPEED100. 00: PC04 input/output (port) 01: MII_TXD0 output (EtherC) 10: Setting prohibited 11: SPEED100 output (PHY) 7  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 557 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 6 Bit Name PC3MD0 Initial Value 0 R/W R/W Description PC3 Mode Selects the function of pin PC03/MII_RXD3. 0: PC03 input/output (port) 1: MII_RXD3 input (EtherC) 5  0 R Reserved This bit is always read as 0. The write value should always be 0. 4 PC2MD0 0 R/W PC2 Mode Selects the function of pin PC02/MII_RXD2. 0: PC02 input/output (port) 1: MII_RXD2 input (EtherC) 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PC1MD0 0 R/W PC1 Mode Selects the function of pin PC01/MII_RXD1. 0: PC01 input/output (port) 1: MII_RXD1 input (EtherC) 1  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 PC0MD0 0 R/W PC0 Mode Selects the function of pin PC00/MII_RXD0. 0: PC00 input/output (port) 1: MII_RXD0 input (EtherC) 18.1.7 Port D IO Register L (PDIORL) PDIORL is a 16-bit readable/writable register that selects the input/output directions of the port D pins. Bits PD7IOR to PD0IOR correspond to pins PD7 to PD0 (the pin name abbreviations for multiplexed functions are omitted). PDIORL is enabled when a port C pin functions as a general input/output (PD7 to PD0), otherwise, disabled. Rev. 5.00 Mar. 15, 2007 Page 558 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Setting a bit in PDIORL to 1 makes the corresponding pin function as an output and clearing a bit in PDIORL to 0 makes the pin function as an input. Bits 15 to 8 in PDIORL are reserved. These bits are always read as 0. The write value should always be 0. The initial value of PDIORL is H'0000. 18.1.8 Port D Control Register L2 (PDCRL2) PDCRL2 is a 16-bit readable/writable register that selects the pin functions for the multiplexed port B pins. • PDCRL2 Bit 15 14 Bit Name PD7MD1 PD7MD0 Initial Value 0 0 R/W R/W R/W Description PD7 Mode Select the function of pin PD7/IRQ7/SCK2. 00: PD7 input/output (port) 01: IRQ7 input (INTC) 10: SCK2 input/output (SCIF) 11: Setting prohibited 13 12 PD6MD1 PD6MD0 0 0 R/W R/W PD6 Mode Select the function of pin PD6/IRQ6/RxD2/DACK1. 00: PD6 input/output (port) 01: IRQ6 input (INTC) 10: RxD2 input (SCIF) 11: DACK1 output (DMAC) 11 10 PD5MD1 PD5MD0 0 0 R/W R/W PD5 Mode Select the function of pin PD5/IRQ5/TxD2/DREQ1. 00: PD5 input/output (port) 01: IRQ5 input (INTC) 10: TxD2 output (SCIF) 11: DREQ1 input (DMAC) Rev. 5.00 Mar. 15, 2007 Page 559 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 9 8 Bit Name PD4MD1 PD4MD0 Initial Value 0 0 R/W R/W R/W Description PD4 Mode Select the function of pin PD4/IRQ4/SCK1. 00: PD4 input/output (port) 01: IRQ4 input (INTC) 10: SCK1 input/output (SCIF) 11: Setting prohibited 7 6 PD3MD1 PD3MD0 0 0 R/W R/W PD3 Mode Select the function of pin PD3/IRQ3/RxD1/DACK0. 00: PD3 input/output (port) 01: IRQ3 input (INTC) 10: RxD1 input (SCIF) 11: DACK0 output (DMAC) 5 4 PD2MD1 PD2MD0 0 0 R/W R/W PD2 Mode Select the function of pin PD2/IRQ2/TxD1/DREQ0. 00: PD2 input/output (port) 01: IRQ2 input (INTC) 10: TxD1 output (SCIF) 11: DREQ0 input (DMAC) 3 2 PD1MD1 PD1MD0 0 0 R/W R/W PD1 Mode Select the function of pin PD1/IRQ1/TEND1. 00: PD1 input/output (port) 01: IRQ1 input (INTC) 10: Setting prohibited 11: TEND1 output (DMAC) 1 0 PD0MD1 PD0MD0 0 0 R/W R/W PD0 Mode Select the function of pin PD0/IRQ0/TEND0. 00: PD0 input/output (port) 01: IRQ0 input (INTC) 10: Setting prohibited 11: TEND0 output (DMAC) Rev. 5.00 Mar. 15, 2007 Page 560 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) 18.1.9 Port E IO Register H and L (PEIORH and PEIORL) PEIORH and PEIORL are 16-bit readable/writable registers that select the input/output directions of the port E pins. Bits PE24IOR to PE0IOR correspond to pins PE24 to PE00 (the pin name abbreviations for multiplexed functions are omitted). PEIORH is enabled when a port E pin functions as a general input/output (PE24 to PE16), otherwise, disabled. PEIORL is enabled when a port E pin functions as a general input/output (PE15 to PE00), otherwise, disabled. Setting a bit in PEIORH and PEIORL to 1 makes the corresponding pin function as an output and clearing a bit in PEIORH and PEIORL to 0 makes the pin function as an input. Bits 15 to 9 in PAIORH are reserved. These bits are always read as 0. The write value should always be 0. The initial values of PEIORH and PEIORL are H'0000. 18.1.10 Port E Control Register H1, H2, L1, and L2 (PECRH1, PECRH2, PECRL1, and PECRL2) PECRH1, PECRH2, PECRL1, and PECRL2 are 16-bit readable/writable registers that select the pin functions for the multiplexed port E pins. • PECRH1 Bit 15 to 2 Bit Name  Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 1 0 PE24MD1 PE24MD0 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W PE24 Mode Select the function of pin PE24/HIFD15/CTS1/D31. 00: PE24 input/output (port) 01: HIFD15 input/output (HIF) 10: CTS1 input (SCIF) 11: D31 input/output (BSC) Rev. 5.00 Mar. 15, 2007 Page 561 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) • PECRH2 Bit 15 14 Bit Name PE23MD1 PE23MD0 Initial Value 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) 13 12 PE22MD1 PE22MD0 0 0 (When in nonHIF boot mode) 0 1 (When in HIF boot mode) 11 10 PE21MD1 PE21MD0 0 0 (When in nonHIF boot mode) 0 1 (When in HIF boot mode) R/W R/W PE21 Mode Select the function of pin PE21/HIFD12/RTS0/D28. 00: PE21 input/output (port) 01: HIFD12 input/output (HIF) 10: RTS0 output (SCIF) 11: D28 input/output (BSC) R/W R/W PE22 Mode Select the function of pin PE22/HIFD13/CTS0/D29. 00: PE22 input/output (port) 01: HIFD13 input/output (HIF) 10: CTS0 input (SCIF) 11: D29 input/output (BSC) R/W R/W R/W Description PE23 Mode Select the function of pin PE23/HIFD14/RTS1/D30. 00: PE23 input/output (port) 01: HIFD14 input/output (HIF) 10: RTS1 input (SCIF) 11: D30 input/output (BSC) Rev. 5.00 Mar. 15, 2007 Page 562 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 9 8 Bit Name PE20MD1 PE20MD0 Initial Value R/W 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W Description PE20 Mode Select the function of pin PE20/HIFD11/SCK1/D27. 00: PE20 input/output (port) 01: HIFD11 input/output (HIF) 10: SCK1 input/output (SCIF) 11: D27 input/output (BSC) 7 6 PE19MD1 PE19MD0 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W PE19 Mode Select the function of pin PE19/HIFD10/RxD1/D26. 00: PE19 input/output (port) 01: HIFD10 input/output (HIF) 10: RxD1 output (SCIF) 11: D26 input/output (BSC) 5 4 PE18MD1 PE18MD0 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W PE18 Mode Select the function of pin PE18/HIFD09/TxD1/D25. 00: PE18 input/output (port) 01: HIFD09 input/output (HIF) 10: TxD1 output (SCIF) 11: D25 input/output (BSC) 3 2 PE17MD1 PE17MD0 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W PE17 Mode Select the function of pin PE17/HIFD08/SCK0/D24. 00: PE17 input/output (port) 01: HIFD08 input/output (HIF) 10: SCK0 input/output (SCIF) 11: D24 input/output (BSC) Rev. 5.00 Mar. 15, 2007 Page 563 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 1 0 Bit Name PE16MD1 PE16MD0 Initial Value 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W R/W Description PE16 Mode Select the function of pin PE16/HIFD07/RxD0/D23. 00: PE16 input/output (port) 01: HIFD07 input/output (HIF) 10: RxD0 input (SCIF) 11: D23 input/output (BSC) • PECRL1 Bit 15 14 Bit Name PE15MD1 PE15MD0 Initial Value 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) 13 12 PE14MD1 PE14MD0 0 0 (When in nonHIF boot mode) 0 1 (When in HIF boot mode) R/W R/W PE14 Mode Select the function of pin PE14/HIFD05/D21. 00: PE14 input/output (port) 01: HIFD05 input/output (HIF) 10: Setting prohibited 11: D21 input/output (BSC) R/W R/W R/W Description PE15 Mode Select the function of pin PE15/HIFD06/TxD0/D22. 00: PE15 input/output (port) 01: HIFD06 input/output (HIF) 10: TxD0 output (SCIF) 11: D22 input/output (BSC) Rev. 5.00 Mar. 15, 2007 Page 564 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 11 10 Bit Name PE13MD1 PE13MD0 Initial Value R/W 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W Description PE13 Mode Select the function of pin PE13/HIFD04/D20. 00: PE13 input/output (port) 01: HIFD04 input/output (HIF) 10: Setting prohibited 11: D20 input/output (BSC) 9 8 PE12MD1 PE12MD0 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W PE12 Mode Select the function of pin PE12/HIFD03/D19. 00: PE12 input/output (port) 01: HIFD03 input/output (HIF) 10: Setting prohibited 11: D19 input/output (BSC) 7 6 PE11MD1 PE11MD0 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W PE11 Mode Select the function of pin PE11/HIFD02/D18. 00: PE11 input/output (port) 01: HIFD02 input/output (HIF) 10: Setting prohibited 11: D18 input/output (BSC) 5 4 PE10MD1 PE10MD0 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W PE10 Mode Select the function of pin PE10/HIFD01/D17. 00: PE10 input/output (port) 01: HIFD01 input/output (HIF) 10: Setting prohibited 11: D17 input/output (BSC) Rev. 5.00 Mar. 15, 2007 Page 565 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 3 2 Bit Name PE9MD1 PE9MD0 Initial Value 0 0 (When in nonHIF boot mode) 0 1 (When in HIF boot mode) R/W Description R/W PE9 Mode R/W Select the function of pin PE09/HIFD00/D16. 00: PE09 input/output (port) 01: HIFD00 input/output (HIF) 10: Setting prohibited 11: D16 input/output (BSC) 1  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 PE8MD0 0 (When in nonHIF boot mode) 1 (When in HIF boot mode) R/W PE8 Mode Selects the function of pin PE08/HIFCS. 0: PE08 input/output (port) 1: HIFCS input (HIF) • PECRL2 Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 PE7MD0 0 (When in non-HIF boot mode) 1 (When in HIF boot mode) R/W PE7 Mode Selects the function of pin PE07/HIFRS. 0: PE07 input/output (port) 1: HIFRS input (HIF) Rev. 5.00 Mar. 15, 2007 Page 566 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 13 12 Bit Name PE6MD1 PE6MD0 Initial Value 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W R/W Description PE6 Mode Select the function of pin PE06/HIFWR/SIOFSYNC0. 00: PE06 input/output (port) 01: HIFWR input (HIF) 10: SIOFSYNC0 input/output (SIOF) 11: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PE5MD0 0 (When in non-HIF boot mode) 1 (When in HIF boot mode) R/W PE5 Mode Selects the function of pin PE05/HIFRD. 0: PE05 input/output (port) 1: HIFRD input (HIF) 9 8 PE4MD1 PE4MD0 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W PE4 Mode Select the function of pin PE04/HIFINT/TXD_SIO0. 00: PE04 input/output (port) 01: HIFINT input (HIF) 10: TXD_SIO0 output (SIOF) 11: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 567 of 794 REJ09B0237-0500 Section 18 Pin Function Controller (PFC) Bit 6 Bit Name PE3MD0 Initial Value R/W 1 R/W Description PE3 Mode Selects the function of pin PE03/HIFMD. 0: PE03 input/output (port) 1: HIFMD input (HIF) 5 4 PE2MD1 PE2MD0 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W PE2 Mode Select the function of pin PE02/HIFDREQ/RXD_SIO0. 00: PE02 input/output (port) 01: HIFDREQ output (HIF) 10: RXD_SIO0 input (SIOF) 11: Setting prohibited 3 2 PE1MD0 PE1MD0 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W PE1 Mode Select the function of pin PE01/HIFRDY/SIOMCLK0. 00: PE01 input/output (port) 01: HIFRDY output (HIF) 10: SIOMCLK0 input (SIOF) 11: Setting prohibited 1 0 PE0MD1 PE0MD0 0 0 (When in non-HIF boot mode) 0 1 (When in HIF boot mode) R/W R/W PE0 Mode Select the function of pin PE00/HIFEBL/SCK_SIO0. 00: PE00 input/output (port) 01: HIFEBL input (HIF) 10: SCK_SIO0 input/output (SIOF) 11: Setting prohibited Rev. 5.00 Mar. 15, 2007 Page 568 of 794 REJ09B0237-0500 Section 19 I/O Ports Section 19 I/O Ports This LSI has 26 ports (ports A, B, C, D, and E). Port A, port B, port C, port D, and port E are 10bit, 14-bit, 21-bit, 8-bit, and 25-bit I/O port, respectively. The pins of each port are multiplexed with other functions. The pin function controller (PFC) handles the selection of multiplex pin functions. Each port has a data register to store data of pin. 19.1 Port A Port A of this LSI is an I/O port with ten pins as shown in figure 19.1. PA16 (input/output)/A16 (output) PA17 (input/output)/A17 (output) PA18 (input/output)/A18 (output) PA19 (input/output)/A19 (output) Port A PA20 (input/output)/A20 (output) PA21 (input/output)/A21 (output)/SCK_SIO0 (input/output) PA22 (input/output)/A22 (output)/SIOMCLK0 (input) PA23 (input/output)/A23 (output)/RXD_SIO0 (input) PA24 (input/output)/A24 (output)/TXD_SIO0 (output) PA25 (input/output)/A25 (output)/SIOFSYNC0 (input/output) Figure 19.1 Port A 19.1.1 Register Description Port A is a 10-bit I/O port that has a following register. For details on the address of this register and the states of this register in each processing state, see section 24, List of Registers. • Port A data register H (PADRH) 19.1.2 Port A Data Register H (PADRH) PADRH is a 16-bit readable/writable register which stores data for port A. Bits PA25DR to PA16DR correspond to pins PA25 to PA16. (Description of multiplexed functions is omitted.) Rev. 5.00 Mar. 15, 2007 Page 569 of 794 REJ09B0237-0500 Section 19 I/O Ports When the pin function is general output port, if the value is written to PADRH, the value is output from the pin; if PADRH is read, the value written to the register is directly read regardless of the pin state. When the pin function is general input port, not the value of register but pin state is directly read if PADRH is read. Data can be written to PADRH but no effect on the pin state. Table 19.1 shows the reading/writing function of the port A data register H. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 9 8 7 6 5 4 3 2 1 0 PA25DR PA24DR PA23DR PA22DR PA21DR PA20DR PA19DR PA18DR PA17DR PA16DR 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W See table 19.1. 15 to 10  Table 19.1 Port A Data Register H (PADRH) Read/Write Operation • Bits 9 to 0 in PADRH Pin Function General input General output Other functions PAIORH 0 1 * Read Pin state PADRH value PADRH value Write Data can be written to PADRH but no effect on the pin state. Written value is output from the pin. Data can be written to PADRH but no effect on the pin state. Rev. 5.00 Mar. 15, 2007 Page 570 of 794 REJ09B0237-0500 Section 19 I/O Ports 19.2 Port B Port B of this LSI is an I/O port with 14 pins as shown in figure 19.2. PB00 (input/output)/WAIT (input) PB01 (input/output)/IOIS16 (input) PB02 (input/output)/CKE (output) PB03 (input/output)/CAS (output) PB04 (input/output)/RAS (output) PB05 (input/output)/WE2(BE2)/DQMUL/ICIORD (output) PB06 (input/output)/WE3(BE3)/DQMUU/ICIOWR (output) Port B PB07 (input/output)/CE2B (output) PB08 (input/output)/CS6B (output)/CE1B (output) PB09 (input/output)/CE2A (output) PB10 (input/output)/CS5B (output)/CE1A (output) PB11 (input/output)/CS4 (output) PB12 (input/output)/CS3 (output) PB13 (input/output)/BS (output) Figure 19.2 Port B 19.2.1 Register Description Port B is a 14-bit I/O port that has a following register. For details on the address of this register and the states of this register in each processing state, see section 24, List of Registers. • Port B data register L (PBDRL) 19.2.2 Port B Data Register L (PBDRL) PBDRL is a 16-bit readable/writable register which stores data for port B. Bits PB13DR to PB0DR correspond to pins PB13 to PB00. (Description of multiplexed functions is omitted.) When the pin function is general output port, if the value is written to PBDRL, the value is output from the pin; if PBDRL is read, the value written to the register is directly read regardless of the pin state. Rev. 5.00 Mar. 15, 2007 Page 571 of 794 REJ09B0237-0500 Section 19 I/O Ports When the pin function is general input port, not the value of register but pin state is directly read if PBDRL is read. Data can be written to PBDRL but no effect on the pin state. Table 19.2 shows the reading/writing function of the port B data register L. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name   PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. See table 19.2. Table 19.2 Port B Data Register L (PBDRL) Read/Write Operation • Bits 13 to 0 in PBDRL Pin Function General input General output Other functions PBIORL 0 1 * Read Pin state PBDRL value PBDRL value Write Data can be written to PBDRL but no effect on the pin state. Written value is output from the pin. Data can be written to PBDRL but no effect on the pin state. Rev. 5.00 Mar. 15, 2007 Page 572 of 794 REJ09B0237-0500 Section 19 I/O Ports 19.3 Port C Port C of this LSI is an I/O port with 21 pins as shown in figure 19.3. PC00 (input/output)/MII_RXD0 (input) PC01 (input/output)/MII_RXD1 (input) PC02 (input/output)/MII_RXD2 (input) PC03 (input/output)/MII_RXD3 (input) PC04 (input/output)/MII_TXD0 (output)/SPEED100 (output) PC05 (input/output)/MII_TXD1 (output)/LINK (output) PC06 (input/output)/MII_TXD2 (output)/CRS (output) PC07 (input/output)/MII_TXD3 (output)/DUPLEX (output) PC08 (input/output)/RX_DV (input) PC09 (input/output)/RX_ER (input) Port C PC10 (input/output)/RX_CLK (input) PC11 (input/output)/TX_ER (output) PC12 (input/output)/TX_EN (output) PC13 (input/output)/TX_CLK (input) PC14 (input/output)/COL (input) PC15 (input/output)/CRS (input) PC16 (input/output)/MDIO (input/output) PC17 (input/output)/MDC (output) PC18 (input/output)/LNKSTA (input) PC19 (input/output)/EXOUT (output) PC20 (input/output)/WOL (output) Figure 19.3 Port C Rev. 5.00 Mar. 15, 2007 Page 573 of 794 REJ09B0237-0500 Section 19 I/O Ports 19.3.1 Register Description Port C is a 21-bit I/O port that has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 24, List of Registers. • Port C data register H (PCDRH) • Port C data register L (PCDRL) 19.3.2 Port C Data Registers H and L (PCDRH and PCDRL) PCDRH and PCDRL are 16-bit readable/writable registers that stores data for port C. Bits PC20DR to PC0DR correspond to pins PC20 to PC00. (Description of multiplexed functions is omitted.) When the pin function is general output port, if the value is written to PCDRH or PCDRL, the value is output from the pin; if PCDRH or PCDRL is read, the value written to the register is directly read regardless of the pin state. When the pin function is general input port, not the value of register but pin state is directly read if PCDRH or PCDRL is read. Data can be written to PCDRH or PCDRL but no effect on the pin state. Table 19.3 shows the reading/writing function of the port C data registers H and L. • PCDRH Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 3 2 1 0 PC20DR PC19DR PC18DR PC17DR PC16DR 0 0 0 0 0 R/W R/W R/W R/W R/W See table 19.3. 15 to 5  Rev. 5.00 Mar. 15, 2007 Page 574 of 794 REJ09B0237-0500 Section 19 I/O Ports • PCDRL Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PC15DR PC14DR PC13DR PC12DR PC11DR PC10DR PC9DR PC8DR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description See table 19.3. Table 19.3 Port C Data Registers H and L (PCDRH and PCDRL) Read/Write Operation • Bits 4 to 0 in PCDRH and Bits 15 to 0 in PCDRL Pin Function General input General output Other functions PBIORL 0 1 * Read Pin state PCDRH or PCDRL value PCDRH or PCDRL value Write Data can be written to PCDRH or PCDRL but no effect on the pin state. Written value is output from the pin. Data can be written to PCDRH or PCDRL but no effect on the pin state. Rev. 5.00 Mar. 15, 2007 Page 575 of 794 REJ09B0237-0500 Section 19 I/O Ports 19.4 Port D Port D of this LSI is an I/O port with eight pins as shown in figure 19.4. PD0 (input/output)/IRQ0 (input)/TEND0 (output) PD1 (input/output)/IRQ1 (input)/TEND1 (output) PD2 (input/output)/IRQ2 (input)/TxD1 (output)/DREQ0 (input) PD3 (input/output)/IRQ3 (input)/RxD1 (input)/DACK0(output) Port D PD4 (input/output)/IRQ4 (input)/SCK1 (input/output) PD5 (input/output)/IRQ5 (input)/TxD2 (output)/DREQ1 (input) PD6 (input/output)/IRQ6 (input)/RxD2 (input)/DACK0(output) PD7 (input/output)/IRQ7 (input)/SCK2 (input/output) Figure 19.4 Port D 19.4.1 Register Description Port D is an 8-bit I/O port that has a following register. For details on the address of this register and the states of this register in each processing state, see section 24, List of Registers. • Port D data register L (PDDRL) 19.4.2 Port D Data Register L (PDDRL) PDDRL is a 16-bit readable/writable register which stores data for port D. Bits PD7DR to PD0DR correspond to pins PD7 to PD0. (Description of multiplexed functions is omitted.) When the pin function is general output port, if the value is written to PDDRL, the value is output from the pin; if PDDRL is read, the value written to the register is directly read regardless of the pin state. When the pin function is general input port, not the value of register but pin state is directly read if PDDRL is read. Data can be written to PDDRL but no effect on the pin state. Table 19.4 shows the reading/writing function of the port D data register L. Rev. 5.00 Mar. 15, 2007 Page 576 of 794 REJ09B0237-0500 Section 19 I/O Ports Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 8  7 6 5 4 3 2 1 0 PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W See table 19.4. Table 19.4 Port D Data Register L (PDDRL) Read/Write Operation • Bits 7 to 0 in PDDRL Pin Function General input General output Other functions PBIORL 0 1 * Read Pin state PDDRL value PDDRL value Write Data can be written to PDDRL but no effect on the pin state. Written value is output from the pin. Data can be written to PDDRL but no effect on the pin state. Rev. 5.00 Mar. 15, 2007 Page 577 of 794 REJ09B0237-0500 Section 19 I/O Ports 19.5 Port E Port E of this LSI is an I/O port with 25 pins as shown in figure 19.5. PE00 (input/output)/HIFEBL (input)/SCK_SIO0 (input/output) PE01 (input/output)/HIFRDY (output)/SIOMCLK0 (input) PE02 (input/output)/HIFDREQ (output)/RXD_SIO0 (input) PE03 (input/output)/HIFMD (input) PE04 (input/output)/HIFINT (output)/TXD_SIO0 (output) PE05 (input/output)/HIFRD (input) PE06 (input/output)/HIFWR (input)/SIOFSYNC (input/output) PE07 (input/output)/HIFRS (input) PE08 (input/output)/HIFCS (input) PE09 (input/output)/HIFD00 (input/output)/D16 (input/output) PE10 (input/output)/HIFD01 (input/output)/D17 (input/output) PE11 (input/output)/HIFD02 (input/output)/D18 (input/output) Port E PE12 (input/output)/HIFD03 (input/output)/D19 (input/output) PE13 (input/output)/HIFD04 (input/output)/D20 (input/output) PE14 (input/output)/HIFD05 (input/output)/D21 (input/output) PE15 (input/output)/HIFD06 (input/output)/TxD0 (output)/D22 (input/output) PE16 (input/output)/HIFD07 (input/output)/RxD0 (input)/D23 (input/output) PE17 (input/output)/HIFD08 (input/output)/SCK0 (input/output)/D24 (input/output) PE18 (input/output)/HIFD09 (input/output)/TxD1 (output)/D25 (input/output) PE19 (input/output)/HIFD10 (input/output)/RxD1 (input)/D26 (input/output) PE20 (input/output)/HIFD11 (input/output)/SCK1 (input/output)/D27 (input/output) PE21 (input/output)/HIFD12 (input/output)/RTS0 (output)/D28 (input/output) PE22 (input/output)/HIFD13 (input/output)/CTS0 (input)/D29 (input/output) PE23 (input/output)/HIFD14 (input/output)/RTS1 (output)/D30 (input/output) PE24 (input/output)/HIFD15 (input/output)/CTS1 (input)/D31 (input/output) Figure 19.5 Port E Rev. 5.00 Mar. 15, 2007 Page 578 of 794 REJ09B0237-0500 Section 19 I/O Ports 19.5.1 Register Description Port E is a 25-bit I/O port that has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 24, List of Registers. • Port E data register H (PEDRH) • Port E data register L (PEDRL) 19.5.2 Port E Data Registers H and L (PEDRH and PEDRL) PEDRH and PEDRL are 16-bit readable/writable registers that store data for port E. Bits PE24DR to PE0DR correspond to pins PE24 to PE00. (Description of multiplexed functions is omitted.) When the pin function is general output port, if the value is written to PEDRH or PEDRL, the value is output from the pin; if PEDRH or PEDRL is read, the value written to the register is directly read regardless of the pin state. When the pin function is general input port, not the value of register but pin state is directly read if PEDRH or PEDRL is read. Data can be written to PEDRH or PEDRL but no effect on the pin state. Table 19.5 shows the reading/writing function of the port E data registers H and L. • PEDRH Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 8 7 6 5 4 3 2 1 0 PE24DR PE23DR PE22DR PE21DR PE20DR PE19DR PE18DR PE17DR PE16DR 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W See table 19.5. 15 to 9  Rev. 5.00 Mar. 15, 2007 Page 579 of 794 REJ09B0237-0500 Section 19 I/O Ports • PEDRL Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description See table 19.5. Table 19.5 Port E Data Registers H, L (PEDRH, PEDRL) Read/Write Operation • Bits 8 to 0 in PEDRH and Bits 15 to 0 in PEDRL Pin Function General input General output Other functions PBIORL 0 1 * Read Pin state PEDRH or PEDRL value PEDRH or PEDRL value Write Data can be written to PEDRH or PEDRL but no effect on the pin state. Written value is output from the pin. Data can be written to PEDRH or PEDRL but no effect on the pin state. Rev. 5.00 Mar. 15, 2007 Page 580 of 794 REJ09B0237-0500 Section 19 I/O Ports 19.6 Usage Notes 1. When pins that are multiplexed with general I/O is used as output pins for other functions, these pins work as general output pins for the period of 1 × tPCYC synchronized with internal power-on reset by WDT overflow. For example, when the pin PB12/CS3 works as CS3 and the PB12DR bit in PBDRL is set to 0, the pin is driven low for the period of 1 × tPCYC and may lead to memory malfunction. To prevent this, port registers that correspond to pins used for the strobe output must be set to strobe non-active level. This case does not apply to the power-on reset from the RES pin. 2. The weak keeper circuit is included in all pins except MD5, MD3, MD2, MD1, MD0, ASEMD, TESTMD, EXTAL, and XTAL. The weak keeper is a circuit that fixes the input in I/O pins to low or high when the pins are not driven from outside. Notes on processing the input pins are as follows:  When using pins having the weak keeper circuit as input pins and driving these pins to a certain level from outside, adjust the resistance of pull-up/pull-down resistors to let the weak keeper circuit keep the intended levels. (2 kΩ and 8 kΩ are recommended respectively.) A large resistance may fail to let the weak keeper circuit to keep the intended levels.  While using the pins having the weak keeper circuit as input pins, if their levels do not matter, there is no need to deal with pins from outside.  MD5, MD3, MD2, MD1, MD0, ASEMD, and TESTMD. Drive these to intended levels from outside. Since the weak keeper circuit is not included in those pins, comparatively large resistance in pull-up/pull-down resistors can be used.  EXTAL, and XTAL See section 8.6, Notes on Board Design in section 8, Clock Pulse Generator (CPG). 3. Since the HIFMD pin is not initially set to function as a general port pin, it must be pulled up or down externally to fix its state. 4. When using a multiplexed pin with a function not selected with its initial value (for example, using the PB12/CS3 pin, the initial function of which is PB12, as the CS3 pin), the pin must be pulled up or down externally at least after a reset until its pin function is selected by software to fix its state. Rev. 5.00 Mar. 15, 2007 Page 581 of 794 REJ09B0237-0500 Section 19 I/O Ports Rev. 5.00 Mar. 15, 2007 Page 582 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) Section 20 User Break Controller (UBC) The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write access, data size, data contents, address value, and stop timing in the case of instruction fetch. 20.1 Features The UBC has the following features: • The following break comparison conditions can be set. Number of break channels: two channels (channels A and B) User break can be requested as either the independent or sequential condition on channels A and B (sequential break: when channel A and channel B match with break conditions in the different bus cycles in that order, a break condition is satisfied).  Address (Compares addresses 32 bits): Comparison bits are maskable in 1-bit units; user can mask addresses at lower 12 bits (4-k page), lower 10 bits (1-k page), or any size of page, etc. One of the two address buses (L-bus address (LAB) and I-bus address (IAB)) can be selected.  Data (only on channel B, 32-bit maskable) One of the two data buses (logic data bus (LDB) and internal data bus (IDB)) can be selected.  Bus cycle: Instruction fetch or data access  Read/write  Operand size: Byte, word, or longword • User break interrupt is generated upon satisfying break conditions. A user-designed user-break condition interrupt exception processing routine can be run. • In an instruction fetch cycle, it can be selected that a break is set before or after an instruction is executed. • Maximum repeat times for the break condition (only for channel B): 212 – 1 times. • Four pairs of branch source/destination buffers. Rev. 5.00 Mar. 15, 2007 Page 583 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) Figure 20.1 shows a block diagram of the UBC. Access control IAB LAB Access comparator MDB BBRA BARA Address comparator BAMRA Channel A Access comparator BBRB BARB Address comparator BAMRB Data comparator Channel B BBRB BDMRB BETR BRSR PC trace BRDR Control BRCR LDB/IDB CPU state signal User break request UBC location [Legend] BBRA: BARA: BAMRA: BBRB: BARB: BAMRB: Break bus cycle register A Break address register A Break address mask register A Break bus cycle register B Break address register B Break address mask register B BDRB: BDMRB: BETR: BRSR: BRDR: BRCR: Break data register B Break data mask register B Execution times break register Branch source register Branch destination register Break control register Figure 20.1 Block Diagram of UBC Rev. 5.00 Mar. 15, 2007 Page 584 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) 20.2 Register Descriptions The user break controller has the following registers. For details on register addresses and access sizes, refer to section 24, List of Registers. • • • • • • • • • • • • Break address register A (BARA) Break address mask register A (BAMRA) Break bus cycle register A (BBRA) Break address register B (BARB) Break address mask register B (BAMRB) Break bus cycle register B (BBRB) Break data register B (BDRB) Break data mask register B (BDMRB) Break control register (BRCR) Execution times break register (BETR) Branch source register (BRSR) Branch destination register (BRDR) Break Address Register A (BARA) 20.2.1 BARA is a 32-bit readable/writable register. BARA specifies the address used for a break condition in channel A. Bit 31 to 0 Bit Name BAA31 to BAA 0 Initial Value All 0 R/W R/W Description Break Address A Store the address on the LAB or IAB specifying break conditions of channel A. Rev. 5.00 Mar. 15, 2007 Page 585 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) 20.2.2 Break Address Mask Register A (BAMRA) BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address specified by BARA. Bit 31 to 0 Bit Name BAMA31 to BAMA 0 Initial Value All 0 R/W R/W Description Break Address Mask A Specify bits masked in the channel A break address bits specified by BARA (BAA31 to BAA0). 0: Break address bit BAAn of channel A is included in the break condition 1: Break address bit BAAn of channel A is masked and is not included in the break condition Note: n = 31 to 0 20.2.3 Break Bus Cycle Register A (BBRA) Break bus cycle register A (BBRA) is a 16-bit readable/writable register, which specifies (1) L bus cycle or I bus cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel A. Bit 15 to 8 Initial Bit Name Value — All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 CDA1 CDA0 0 0 R/W R/W L Bus Cycle/I Bus Cycle Select A Select the L bus cycle or I bus cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle Rev. 5.00 Mar. 15, 2007 Page 586 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) Bit 5 4 Initial Bit Name Value IDA1 IDA0 0 0 R/W R/W R/W Description Instruction Fetch/Data Access Select A Select the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3 2 RWA1 RWA0 0 0 R/W R/W Read/Write Select A Select the read cycle or write cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1 0 SZA1 SZA0 0 0 R/W R/W Operand Size Select A Select the operand size of the bus cycle for the channel A break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access 20.2.4 Break Address Register B (BARB) BARB is a 32-bit readable/writable register. BARB specifies the address used for a break condition in channel B. Bit 31 to 0 Initial Bit Name Value BAB31 to All 0 BAB 0 R/W R/W Description Break Address B Store an address of LAB or IAB which specifies a break condition in channel B. Rev. 5.00 Mar. 15, 2007 Page 587 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) 20.2.5 Break Address Mask Register B (BAMRB) BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB. Bit 31 to 0 Bit Name BAMB31 to BAMB 0 Initial Value All 0 R/W R/W Description Break Address Mask B Specify bits masked in the break address of channel B specified by BARB (BAB31 to BAB0). 0: Break address BABn of channel B is included in the break condition 1: Break address BABn of channel B is masked and is not included in the break condition Note: n = 31 to 0 20.2.6 Break Data Register B (BDRB) BDRB is a 32-bit readable/writable register. BDBR selects data used for a break condition in channel B. Bit 31 to 0 Bit Name BDB31 to BDB 0 Initial Value All 0 R/W R/W Description Break Data Bit B Store data which specifies a break condition in channel B. BDRB specifies the break data on LDB or IDB. Notes: 1. Specify an operated size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte must be set in bits 15 to 8 and 7 to 0 in BDRB as the break data. Rev. 5.00 Mar. 15, 2007 Page 588 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) 20.2.7 Break Data Mask Register B (BDMRB) BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data specified by BDRB. Bit 31 to 0 Bit Name BDMB31 to BDMB 0 Initial Value All 0 R/W R/W Description Break Data Mask B Specify bits masked in the break data of channel B specified by BDRB (BDB31 to BDB0). 0: Break data BDBn of channel B is included in the break condition 1: Break data BDBn of channel B is masked and is not included in the break condition Note: n = 31 to 0 Notes: 1. Specify an operated size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break mask data. 20.2.8 Break Bus Cycle Register B (BBRB) Break bus cycle register B (BBRB) is a 16-bit readable/writable register, which specifies (1) L bus cycle or I bus cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel B. Bit 15 to 8 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 5.00 Mar. 15, 2007 Page 589 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) Bit 7 6 Bit Name CDB1 CDB0 Initial Value 0 0 R/W R/W R/W Description L Bus Cycle/I Bus Cycle Select B Select the L bus cycle or I bus cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle 5 4 IDB1 IDB0 0 0 R/W R/W Instruction Fetch/Data Access Select B Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3 2 RWB1 RWB0 0 0 R/W R/W Read/Write Select B Select the read cycle or write cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1 0 SZB1 SZB0 0 0 R/W R/W Operand Size Select B Select the operand size of the bus cycle for the channel B break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Rev. 5.00 Mar. 15, 2007 Page 590 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) 20.2.9 Break Control Register (BRCR) BRCR sets the following conditions: • Channels A and B are used in two independent channel conditions or under the sequential condition. • A break is set before or after instruction execution. • Specify whether to include the number of execution times on channel B in comparison conditions. • Specify whether to include data bus on channel B in comparison conditions. • Enable PC trace. The break control register (BRCR) is a 32-bit readable/writable register that has break conditions match flags and bits for setting a variety of break conditions. Bit 31 to 16 Initial Bit Name Value — All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 SCMFCA 0 R/W L Bus Cycle Condition Match Flag A When the L bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel A does not match 1: The L bus cycle condition for channel A matches 14 SCMFCB 0 R/W L Bus Cycle Condition Match Flag B When the L bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel B does not match 1: The L bus cycle condition for channel B matches Rev. 5.00 Mar. 15, 2007 Page 591 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) Bit 13 Initial Bit Name Value SCMFDA R/W R/W Description I Bus Cycle Condition Match Flag A When the I bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel A does not match 1: The I bus cycle condition for channel A matches 0 12 SCMFDB 0 R/W I Bus Cycle Condition Match Flag B When the I bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel B does not match 1: The I bus cycle condition for channel B matches 11 PCTE 0 R/W PC Trace Enable 0: Disables PC trace 1: Enables PC trace 10 PCBA 0 R/W PC Break Select A Selects the break timing of the instruction fetch cycle for channel A as before or after instruction execution. 0: PC break of channel A is set before instruction execution 1: PC break of channel A is set after instruction execution 9, 8 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 DBEB 0 R/W Data Break Enable B Selects whether or not the data bus condition is included in the break condition of channel B. 0: No data bus condition is included in the condition of channel B 1: The data bus condition is included in the condition of channel B Rev. 5.00 Mar. 15, 2007 Page 592 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) Bit 6 Initial Bit Name Value PCBB 0 R/W R/W Description PC Break Select B Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. 0: PC break of channel B is set before instruction execution 1: PC break of channel B is set after instruction execution 5, 4 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 SEQ 0 R/W Sequence Condition Select Selects two conditions of channels A and B as independent or sequential conditions. 0: Channels A and B are compared under independent conditions 1: Channels A and B are compared under sequential conditions (channel A, then channel B) 2, 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 ETBE 0 R/W Number of Execution Times Break Enable Enables the execution-times break condition only on channel B. If this bit is 1 (break enable), a user break is issued when the number of break conditions matches with the number of execution times that is specified by BETR. 0: The execution-times break condition is disabled on channel B 1: The execution-times break condition is enabled on channel B Rev. 5.00 Mar. 15, 2007 Page 593 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) 20.2.10 Execution Times Break Register (BETR) BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 212 – 1 times. Every time the break condition is satisfied, BETR is decremented by 1. A break is issued when the break condition is satisfied after BETR becomes H'0001. Bit 15 to 12 Initial Bit Name Value — All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 BET11 to BET0 All 0 R/W Number of Execution Times 20.2.11 Branch Source Register (BRSR) BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on reset. Other bits are not initialized by a power-on reset. The four BRSR registers have a queue structure and a stored register is shifted at every branch. Bit 31 Bit Name SVF Initial Value 0 R/W R Description BRSR Valid Flag Indicates whether or not the branch source address is stored. When a branch is made, this flag is set to 1. This flag is cleared to 0 by one of the following conditions: when this flag is read from this register, when PC trace is enabled, and when a power-on reset is generated. 0: The value of BRSR register is invalid 1: The value of BRSR register is valid Rev. 5.00 Mar. 15, 2007 Page 594 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) Bit 30 to 28 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BSA27 to BSA0 Undefined R Branch Source Address Store bits 27 to 0 of the branch source address. 20.2.12 Branch Destination Register (BRDR) BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by a power-on reset. Other bits are not initialized by a power-on reset. The four BRDR registers have a queue structure and a stored register is shifted at every branch. Bit 31 Bit Name DVF Initial Value 0 R/W R Description BRDR Valid Flag Indicates whether or not the branch source address is stored. When a branch is made, this flag is set to 1. This flag is cleared to 0 by one of the following conditions: when this flag is read from this register, when PC trace is enabled, and when a power-on reset is generated. 0: The value of BRDR register is invalid 1: The value of BRDR register is valid 30 to 28 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BDA27 to BDA0 Undefined R Branch Destination Address Store bits 27 to 0 of the branch destination address. Rev. 5.00 Mar. 15, 2007 Page 595 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) 20.3 20.3.1 Operation Flow of User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses are set in the break address registers (BARA and BARB). The masked addresses are set in the break address mask registers (BAMRA and BAMRB). The break data is set in the break data register (BDRB). The masked data is set in the break data mask register (BDMRB). The bus break conditions are set in the break bus cycle registers (BBRA and BBRB). There are three control bit combinations in both BBRA and BBRB: bits to select Lbus cycle or I-bus cycle, bits to select instruction fetch or data access, and bits to select read or write. No user break will be generated if one of these combinations is set to B'00. The respective conditions are set in the bits of the break control register (BRCR). Make sure to set all registers related to breaks before setting BBRA/BBRB. 2. When the break conditions are satisfied, the UBC sends a user break request to the CPU and sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition match flag (SCMFDA or SCMFDB) for the appropriate channel. 3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can be used to check if the set conditions match or not. The matching of the conditions sets flags. Reset the flags by writing 0 before they are used again. 4. There is a chance that the data access break and its following instruction fetch break occur around the same time, there will be only one break request to the CPU, but these two break channel match flags could be both set. Rev. 5.00 Mar. 15, 2007 Page 596 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) 20.3.2 Break on Instruction Fetch Cycle 1. When L bus/instruction fetch/read/word or longword is set in the break bus cycle register (BBRA/BBRB), the break condition becomes the L bus instruction fetch cycle. Whether it breaks before or after the execution of the instruction can then be selected with the PCBA/PCBB bit of the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is set as a break condition, clear LSB in the break address register (BARA/BARB) to 0. A break cannot be generated as long as this bit is set to 1. 2. If the condition is matched while a break before execution is selected, a break is generated when it is confirmed that the instruction has been fetched and it will be executed. This means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set in the delay slot of a delayed branch instruction, the break is generated immediately before the execution of the instruction that first accepts the break. Meanwhile, a break before the execution of the instruction in a delay slot and a break after the execution of the SLEEP instruction are also prohibited. 3. When a break after execution is selected, the instruction that matches the break condition is executed and then the break is generated prior to the execution of the next instruction. As with a break before execution, this cannot be used with overrun fetch instructions. When this kind of break is set for a delayed branch instruction, a break is not generated until the first instruction at which breaks are accepted. 4. When an instruction fetch cycle is set for channel B, the break data register B (BDRB) is ignored. There is thus no need to set break data for the break of the instruction fetch cycle. 20.3.3 Break on Data Access Cycle • The bus cycles in which L bus data access breaks occur are from instructions. • The relationship between the data access cycle address and the comparison condition for each operand size is listed in table 20.1. Table 20.1 Data Access Cycle Addresses and Operand Size Comparison Conditions Access Size Longword Word Byte Address Compared Compares break address register bits 31 to 2 to address bus bits 31 to 2 Compares break address register bits 31 to 1 to address bus bits 31 to 1 Compares break address register bits 31 to 0 to address bus bits 31 to 0 Rev. 5.00 Mar. 15, 2007 Page 597 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) This means that when address H'00001003 is set in the break address register (BARA or BARB), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met).  Longword access at H'00001000  Word access at H'00001002  Byte access at H'00001003 • When the data value is included in the break conditions on channel B: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle registers (BBRA and BBRB). In this case, a break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register B (BDRB) and break data mask register B (BDMRB). When word or byte is set, bits 31 to 16 of BDRB and BDMRB are ignored. 20.3.4 Sequential Break • By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break condition matches after a channel A break condition matches. A user break is not generated even if a channel B break condition matches before a channel A break condition matches. When channels A and B break conditions match at the same time, the sequential break is not issued. To clear the channel A condition match when a channel A condition match has occurred but a channel B condition match has not yet occurred in a sequential break specification, clear the SEQ bit in BRCR to 0. • In sequential break specification, the L- or I-bus can be selected and the execution times break condition can be also specified. For example, when the execution times break condition is specified, the break is generated when a channel B condition matches with BETR = H'0001 after a channel A condition has matched. 20.3.5 Value of Saved Program Counter (PC) When a break occurs, PC is saved onto the stack. The PC value saved is as follows depending on the type of break. • When a break before execution is selected: The value of the program counter (PC) saved is the address of the instruction that matches the break condition. The fetched instruction is not executed, and a break occurs before it. Rev. 5.00 Mar. 15, 2007 Page 598 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) • When a break after execution is selected: The PC value saved is the address of the instruction to be executed following the instruction in which the break condition matches. The fetched instruction is executed, and a break occurs before the execution of the next instruction. • When an address in a data access cycle is specified as a break condition: The PC value is the address of the instruction to be executed following the instruction that matched the break condition. The instruction that matched the condition is executed and the break occurs before the next instruction is executed. • When an address and data in a data access cycle are specified as a break condition: The PC value is the start address of the instruction that follows the instruction already executed when break processing started. When a data value is added to the break conditions, the break will occur before the execution of an instruction that is within two instructions of the instruction that matched the break condition. Therefore, where the break will occur cannot be specified exactly. 20.3.6 PC Trace • Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt) is generated, the branch source address and branch destination address are stored in BRSR and BRDR, respectively. • The branch source address has different values due to the kind of branch.  Branch instruction The branch instruction address.  Interrupt and exception The address of the instruction in which the interrupt or exception was accepted. This address is equal to the return address saved onto the stack. The start address of the interrupt or exception handling routine is stored in BRDR. The TRAPA instruction belongs to interrupt and exception above. • BRSR and BRDR have four pairs of queue structures. The top of queues is read first when the address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the PCTE bit (in BRCR) off and on, the values in the queues are invalid. Rev. 5.00 Mar. 15, 2007 Page 599 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) 20.3.7 Usage Examples Break Condition Specified for L Bus Instruction Fetch Cycle: • Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300400 Specified conditions: Channel A/channel B independent mode  Channel A Address: H'00000404, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition)  Channel B Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction of address H'00000404 is executed or before instructions of addresses H'00008010 to H'00008016 are executed. • Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode  Channel A Address: H'00037226, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word  Channel B Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word After address H'00037226 is executed, a user break occurs before an instruction of address H'0003722E is executed. Rev. 5.00 Mar. 15, 2007 Page 600 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) • Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300000 Specified conditions: Channel A/channel B independent mode  Channel A Address: H'00027128, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word The ASID check is not included.  Channel B Address: H'00031415, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B, no user break occurs since instruction fetch is performed for an even address. • Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode  Channel A Address: H'00037226, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word  Channel B Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word Since instruction fetch is not a write cycle on channel A, a sequential condition does not match. Therefore, no user break occurs. Rev. 5.00 Mar. 15, 2007 Page 601 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) • Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode  Channel A Address: H'00000500, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword The ASID check is not included.  Channel B Address: H'00001000, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword The number of execution-times break enable (5 times) On channel A, a user break occurs before an instruction of address H'00000500 is executed. On channel B, a user break occurs after the instruction of address H'00001000 are executed four times and before the fifth time. • Register specifications BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode  Channel A Address: H'00008404, Address mask: H'00000FFF Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition)  Channel B Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction of addresses H'00008000 to H'00008FFE is executed or before an instruction of addresses H'00008010 to H'00008016 is executed. Rev. 5.00 Mar. 15, 2007 Page 602 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) Break Condition Specified for L Bus Data Access Cycle: • Register specifications BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode  Channel A Address: H'00123456, Address mask: H'00000000, ASID = H'80 Bus cycle: L bus/data access/read (operand size is not included in the condition)  Channel B Address: H'000ABCDE, Address mask: H'000000FF Data: H'0000A512, Data mask: H'00000000 Bus cycle: L bus/data access/write/word On channel A, a user break occurs with longword read from address H'00123454, word read from address H'00123456, or byte read from address H'00123456. On channel B, a user break occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE. Break Condition Specified for I Bus Data Access Cycle: • Register specifications: BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00007878, BDMRB = H'00000F0F, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode  Channel A Address: H'00314156, Address mask: H'00000000, ASID = H'80 Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition)  Channel B Address: H'00055555, Address mask: H'00000000, ASID = H'70 Data: H'00000078, Data mask: H'0000000F Bus cycle: I bus/data access/write/byte On channel A, a user break occurs when instruction fetch is performed for address H'00314156 in the memory space. On channel B, a user break occurs when the I bus writes byte data H'7* in address H'00055555. Rev. 5.00 Mar. 15, 2007 Page 603 of 794 REJ09B0237-0500 Section 20 User Break Controller (UBC) 20.3.8 Notes 1. The CPU reads from or writes to the UBC registers via the I bus. A desired break may not occur until the instruction to rewrite the UBC registers are executed and the actual values are reflected. In order to know the timing the UBC register is changed, read the last written register. Instructions after then are valid for the newly written register value. 2. UBC cannot monitor access to the L bus and I bus in the same channel. 3. Note on specification of sequential break: A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel match occurs in another bus cycle in sequential break setting. Therefore, no break occurs even if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is set. 4. When user breaks and other exceptions occur by the same instruction, they are handled according to the priority listed in table 5.1 of section 5, Exception Handling. When an exception with a higher priority is generated, no user break occurs.  A break before the execution of an instruction is accepted with a priority over other exceptions.  When a break after the execution of an instruction or a data access break occurs simultaneously with a re-execution-type exception with a higher priority (including a break before the execution of an instruction), the re-execution-type exception is accepted and the condition match flag is not set (however, there is an exception as explained in 5. of section 20.3.8, Notes). When the exception source of the re-execution type is cleared by exception handling and the same instruction is executed again and completed, the break is generated again and the flag is set.  When a break after the execution of an instruction or a data access break occurs simultaneously with a completion-type exception with a higher priority (TRAPA), no break occurs but the condition match flag is set. 5. Note on exception of 4. of section 20.3.8, Notes When a break after the execution of an instruction or a data access break occurs during the execution of the instruction in which a CPU address error is generated by data access, the CPU address error has a priority over the break and occurs before the break. The condition match flag is also set at this time. 6. Note when a break occurs in the delay slot When a break before the execution of an instruction is set to the delay slot instruction of the RTE instruction, the break does not occur before executing the branch destination of the RTE instruction. 7. User breaks are disabled during USB module standby mode. Do not read from or write to the UBC registers during USB module standby mode; the values are not guaranteed. Rev. 5.00 Mar. 15, 2007 Page 604 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) Section 21 User Debugging Interface (H-UDI) This LSI incorporates a user debugging interface (H-UDI) to provide a boundary scan function and emulator support. This section describes the boundary scan function of the H-UDI. For details on emulator functions of the H-UDI, refer to the user's manual of the relevant emulator. 21.1 Features The H-UDI is a serial I/O interface which conforms to JTAG (Joint Test Action Group, IEEE Standard 1149.1 and IEEE Standard Test Access Port and Boundary-Scan Architecture) specifications. The H-UDI in this LSI supports a boundary scan function, and is also used for emulator connection. When using an emulator, H-UDI functions should not be used. Refer to the emulator manual for the method of connecting the emulator. Figure 21.1 shows a block diagram of the H-UDI. TDI Shift register SDBPR SDBSR SDIR SDID TDO MUX TCK TMS TRST TAP controller Decoder Local bus [Legend] SDBPR: SDBSR: SDIR: SDID: Bypass register Boundary scan register Instruction register ID register Figure 21.1 Block Diagram of H-UDI Rev. 5.00 Mar. 15, 2007 Page 605 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) 21.2 Input/Output Pins Table 21.1 shows the pin configuration of the H-UDI. Table 21.1 Pin Configuration Abbr. TCK Input/Output Input Description Serial Data Input/Output Clock Pin Data is serially supplied to the H-UDI from the data input pin (TDI) and output from the data output pin (TDO) in synchronization with this clock. TMS Input Mode Select Input Pin The state of the TAP control circuit is determined by changing this signal in synchronization with TCK. The protocol conforms to the JTAG standard (IEEE Std.1149.1). TRST Input Reset Input Pin Input is accepted asynchronously with respect to TCK, and when low, the H-UDI is reset. TRST must be low for the given period when the power is turned on regardless of using the HUDI function. This is different from the JTAG standard. For details on resets, see section 21.4.2, Reset Configuration. TDI Input Serial Data Input Pin Data transfer to the H-UDI is executed by changing this signal in synchronization with TCK. TDO Output Serial Data Output Pin Data read from the H-UDI is executed by reading this pin in synchronization with TCK. The data output timing depends on the command type set in SDIR. For details, see section 21.3.2, Instruction Register (SDIR). ASEMD Input ASE Mode Select Pin When a low level is input to the ASEMD pin, ASE mode is entered; if a high level is input, normal mode is entered. In ASE mode, the emulator functions can be used. The input level on the ASEMD pin should be held except during the RES pin assertion period. Rev. 5.00 Mar. 15, 2007 Page 606 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) 21.3 Register Descriptions The H-UDI has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 24, List of Registers. • • • • Bypass register (SDBPR) Instruction register (SDIR) Boundary scan register (SDBSR) ID register (SDID) Bypass Register (SDBPR) 21.3.1 SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to the bypass mode, SDBPR is connected between H-UDI pins (TDI and TDO). The initial value is undefined. 21.3.2 Instruction Register (SDIR) SDIR is a 16-bit read-only register. This register is in JTAG IDCODE in its initial state. It is initialized by TRST assertion or in the TAP test-logic-reset state, and can be written to by the HUDI irrespective of the CPU mode. Operation is not guaranteed if a reserved command is set in this register. Bit 15 to 13 12 11 to 8 7 to 2 1 0 Bit Name TI7 to TI5 TI4 TI3 to TI0    Initial Value All 1 0 All 1 All 1 0 1 R/W R R R R R R Description Test Instruction 7 to 0 The H-UDI instruction is transferred to SDIR by a serial input from TDI. For commands, see table 21.2. Reserved These bits are always read as 1. Reserved This bit is always read as 0. Reserved This bit is always read as 1. Rev. 5.00 Mar. 15, 2007 Page 607 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) Table 21.2 H-UDI Commands Bits 15 to 8 TI7 0 0 0 0 0 0 1 1 1 TI6 0 0 0 1 1 1 0 1 1 TI5 0 1 1 0 1 1 1 1 1 TI4 0 0 1 0 0 1  0 1 TI3          TI2          TI1          TI0          Description JTAG EXTEST JTAG CLAMP JTAG HIGHZ JTAG SAMPLE/PRELOAD H-UDI reset, negate H-UDI reset, assert H-UDI interrupt JTAG IDCODE (Initial value) JTAG BYPASS Reserved Other than above 21.3.3 Boundary Scan Register (SDBSR) SDBSR is a 333-bit shift register, located on the PAD, for controlling the input/output pins of this LSI. The initial value is undefined. This register cannot be accessed by the CPU. Using the EXTEST, SAMPLE/PRELOAD, CLAMP, and HIGHZ commands, a boundary scan test conforming to the JTAG standard can be carried out. Table 21.3 shows the correspondence between this LSI's pins and boundary scan register bits. Rev. 5.00 Mar. 15, 2007 Page 608 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) Table 21.3 External pins and Boundary Scan Register Bits Bit Pin Name from TDI 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 PD06/IRQ6/RxD2/DACK1 PD05/IRQ5/TxD2/DREQ1 PD04/IRQ4/SCK1/PD03/IRQ3/RxD1/DACK0 PD02/IRQ2/TxD1/DREQ0 PD01/IRQ1/-/TEND1 PD00/IRQ0/-/TEND0 PE08/HIFCS PE24/HIFD15/CTS1/D31 PE23/HIFD14/RTS1/D30 PE22/HIFD13/CTS0/D29 PE21/HIFD12/RTS0/D28 PE20/HIFD11/SCK1/D27 PE19/HIFD10/RxD1/D26 PE18/HIFD09/TxD1/D25 PE17/HIFD08/SCK0/D24 PE16/HIFD07/RxD0/D23 PE15/HIFD06/TxD0/D22 PE14/HIFD05/-/D21 PE13/HIFD04/-/D20 PE12/HIFD03/-/D19 PE11/HIFD02/-/D18 PE10/HIFD01/-/D17 PE09/HIFD00/-/D16 PE07/HIFRS PE06/HIFWR/SIOFSYNC0/PE05/HIFRD PE04/HIFINT/TXD_SIO0/PE03/HIFMD IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN I/O Bit 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 Pin Name I/O PE02/HIFDREQ/RXD_SIO0/- IN PE01/HIFRDY/SIOMCLK0/PE00/HIFEBL/SCK_SIO0/PC17/MDC/-/PC16/MDIO/-/PC15/CRS/-/PC18/LNKSTA PD06/IRQ6/RxD2/DACK1 PD05/IRQ5/TxD2/DREQ1 PD04/IRQ4/SCK1/PD03/IRQ3/RxD1/DACK0 PD02/IRQ2/TxD1/DREQ0 PD01/IRQ1/-/TEND1 PD00/IRQ0/-/TEND0 PE08/HIFCS PE24/HIFD15/CTS1/D31 PE23/HIFD14/RTS1/D30 PE22/HIFD13/CTS0/D29 PE21/HIFD12/RTS0/D28 PE20/HIFD11/SCK1/D27 PE19/HIFD10/RxD1/D26 PE18/HIFD09/TxD1/D25 PE17/HIFD08/SCK0/D24 PE16/HIFD07/RxD0/D23 PE15/HIFD06/TxD0/D22 PE14/HIFD05/-/D21 PE13/HIFD04/-/D20 PE12/HIFD03/-/D19 PE11/HIFD02/-/D18 PE10/HIFD01/-/D17 IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Rev. 5.00 Mar. 15, 2007 Page 609 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) Bit 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 Pin Name PE09/HIFD00/-/D16 PE07/HIFRS PE06/HIFWR/SIOFSYNC0/PE05/HIFRD PE04/HIFINT/TXD_SIO0/PE03/HIFMD I/O OUT OUT OUT OUT OUT OUT Bit 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 Pin Name PE13/HIFD04/-/D20 PE12/HIFD03/-/D19 PE11/HIFD02/-/D18 PE10/HIFD01/-/D17 PE09/HIFD00/-/D16 PE07/HIFRS PE06/HIFWR/SIOFSYNC0/PE05/HIFRD PE04/HIFINT/TXD_SIO0/PE03/HIFMD I/O Control Control Control Control Control Control Control Control Control Control PE02/HIFDREQ/RXD_SIO0/- OUT PE01/HIFRDY/SIOMCLK0/PE00/HIFEBL/SCK_SIO0/PC17/MDC/-/PC16/MDIO/-/PC15/CRS/-/PC18/LNKSTA PD06/IRQ6/RxD2/DACK1 PD05/IRQ5/TxD2/DREQ1 PD04/IRQ4/SCK1/PD03/IRQ3/RxD1/DACK0 PD02/IRQ2/TxD1/DREQ0 PD01/IRQ1/-/TEND1 PD00/IRQ0/-/TEND0 PE08/HIFCS PE24/HIFD15/CTS1/D31 PE23/HIFD14/RTS1/D30 PE22/HIFD13/CTS0/D29 PE21/HIFD12/RTS0/D28 PE20/HIFD11/SCK1/D27 PE19/HIFD10/RxD1/D26 PE18/HIFD09/TxD1/D25 PE17/HIFD08/SCK0/D24 PE16/HIFD07/RxD0/D23 PE15/HIFD06/TxD0/D22 PE14/HIFD05/-/D21 OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control PE02/HIFDREQ/RXD_SIO0/- Control PE01/HIFRDY/SIOMCLK0/PE00/HIFEBL/SCK_SIO0/PC17/MDC/-/PC16/MDIO/-/PC15/CRS/ PC18/LNKSTA PC09/RX_ER/-/PC08/RX_DV/-/PC00/MIIRXD0/-/PC01/MIIRXD1/-/PC02/MIIRXD2/-/PC03/MIIRXD3/-/PC10/RX_CLK/-/PC11/TX_ER/-/PC13/TX_CLK/-/PC04/MIITXD0/-/SPEED100 PC05/MIITXD1/-/LINK PC06/MIITXD2/-/CRS PC07/MIITXD3/-/DUPLEX PC12/TX_EN/-/PC14/COL/-/Control Control Control Control Control Control IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN Rev. 5.00 Mar. 15, 2007 Page 610 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) Bit 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 Pin Name PC20/WOL PC19/EXOUT MD3 MD5 TESTMD PC09/RX_ER/-/PC08/RX_DV/-/PC00/MIIRXD0/-/PC01/MIIRXD1/-/PC02/MIIRXD2/-/PC03/MIIRXD3/-/PC10/RX_CLK/-/PC11/TX_ER/-/PC13/TX_CLK/-/PC04/MIITXD0/-/SPEED100 PC05/MIITXD1/-/LINK PC06/MIITXD2/-/CRS PC07/MIITXD3/-/DUPLEX PC12/TX_EN/-/PC14/COL/-/PC20/WOL PC19/EXOUT TESTOUT PC09/RX_ER/-/PC08/RX_DV/-/PC00/MIIRXD0/-/PC01/MIIRXD1/-/PC02/MIIRXD2/-/PC03/MIIRXD3/-/PC10/RX_CLK/-/PC11/TX_ER/-/PC13/TX_CLK/-/- I/O IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Bit 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 Pin Name PC04/MIITXD0/-/SPEED100 PC05/MIITXD1/-/LINK PC06/MIITXD2/-/CRS PC07/MIITXD3/-/DUPLEX PC12/TX_EN/-/PC14/COL/-/PC20/WOL PC19/EXOUT TESTOUT MD0 NMI MD1 MD2 D00 D01 D02 D03 D04 D05 D06 D07 D15 D14 D13 D12 D11 D10 D09 D08 PB02/CKE PB03/CAS PB04/RAS I/O Control Control Control Control Control Control Control Control Control IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN Rev. 5.00 Mar. 15, 2007 Page 611 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) Bit 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 Pin Name D00 D01 D02 D03 D04 D05 D06 D07 D15 D14 D13 D12 D11 D10 D09 D08 WE0, DQMLL WE1, DQMLU, WE RDWR PB02/CKE PB03/CAS PB04/RAS D00 D01 D02 D03 D04 D05 D06 D07 I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Bit 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 Pin Name D15 D14 D13 D12 D11 D10 D09 D08 WE0, DQMLL WE1, DQMLU, WE RDWR PB02/CKE PB03/CAS PB04/RAS PB12/CS3 PB13/BS PB11/CS4 PB00/WAIT PB05/WE2(BE2)/DQMUL/ ICIORD PB06/WE3(BE3)/DQMUU/ ICIOWR PB01/IOIS16 PB09/CE2A PB10/CS5B, CE1A PB07/CE2B PB08/CS6B, CE1B PA16/A16 PA17/A17 PA18/A18 PA19/A19 PA20/A20 I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN Rev. 5.00 Mar. 15, 2007 Page 612 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) Bit 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 Pin Name PA21/A21/SCK_SIO0/PA22/A22/SIOMCLK0/PA23/A23/RXD_SIO0/PA24/A24/TXD_SIO0/PA25/A25/SIOFSYNC0/PD07/IRQ7/SCK2/PB12/CS3 A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 PB13/BS CS0 PB11/CS4 RD PB00/WAIT PB05/WE2(BE2)/DQMUL/ ICIORD I/O IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Bit 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Pin Name PB06/WE3(BE3)/DQMUU/ ICIOWR PB01/IOIS16 PB09/CE2A PB10/CS5B, CE1A PB07/CE2B PB08/CS6B, CE1B PA16/A16 PA17/A17 PA18/A18 PA19/A19 PA20/A20 PA21/A21/SCK_SIO0/PA22/A22/SIOMCLK0/PA23/A23/RXD_SIO0/PA24/A24/TXD_SIO0/PA25/A25/SIOFSYNC0/PD07/IRQ7/SCK2/PB12/CS3 A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Rev. 5.00 Mar. 15, 2007 Page 613 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) Bit 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 Note: Pin Name A11 A12 A13 A14 A15 PB13/BS CS0 PB11/CS4 RD PB00/WAIT PB05/WE2(BE2)/ DQMUL/ICIORD PB06/WE3(BE3)/ DQMUU/ICIOWR PB01/IOIS16 PB09/CE2A PB10/CS5B, CE1A * I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Bit 12 11 10 9 8 7 6 5 4 3 2 1 0 Pin Name PB07/CE2B PB08/CS6B, CE1B PA16/A16 PA17/A17 PA18/A18 PA19/A19 PA20/A20 PA21/A21/SCK_SIO0/PA22/A22/SIOMCLK0/PA23/A23/RXD_SIO0/PA24/A24/TXD_SIO0/PA25/A25/SIOFSYNC0/PD07/IRQ7/SCK2/to TDO I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control means a low active signal. The corresponding pin is driven with an OUT value when the Control is driven low. Rev. 5.00 Mar. 15, 2007 Page 614 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) 21.3.4 ID Register (SDID) SDID is a 32-bit read-only register in which SDIDH and SDIDL are connected. Each register is a 16-bit that can be read by the CPU. To read this register by the H-UDI side, the contents can be read via the TDO pin when the IDCODE command is set and the TAP state is Shift-DR. Writing is disabled. Bit 31 to 0 Bit Name DID31 to DID0 Initial Value R/W Description Device ID 31 to Device ID 0 ID register that is stipulated by JTAG. H'0800C447 (initial value) for this LSI. Upper four bits may be changed according to the LSI version. SDIDH corresponds to bits 31 to 16. SDIDL corresponds to bits 15 to 0. Refer to R description Rev. 5.00 Mar. 15, 2007 Page 615 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) 21.4 21.4.1 Operation TAP Controller Figure 21.2 shows the internal states of the TAP controller. State transitions basically conform to the JTAG standard. 1 Test-logic-reset 0 1 1 Select-DR-scan 0 0 1 Capture-DR 0 Shift-DR 1 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 Exit2-IR 1 Update-IR 1 0 Exit1-IR 0 Pause-IR 1 0 0 1 Capture-IR 0 Shift-IR 1 1 0 Select-IR-scan 1 0 Run-test/idle Figure 21.2 TAP Controller State Transitions Note: The transition condition is the TMS value at the rising edge of the TCK signal. The TDI value is sampled at the rising edge of the TCK signal and is shifted at the falling edge of the TCK signal. For details on change timing of the TDO value, see section 21.4.3, TDO Output Timing. The TDO pin is high impedance, except in the shift-DR and shift-IR states. A transition to the Test-Logic-Reset state is made asynchronously with TCK by driving the TRST signal 0. Rev. 5.00 Mar. 15, 2007 Page 616 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) 21.4.2 Reset Configuration Table 21.4 Reset Configuration ASEMD*1 High RES Low TRST Low High High Low High Low Low Low High High Low High LSI State Normal reset and H-UDI reset Normal reset H-UDI reset only Normal operation Reset hold*2 Normal reset H-UDI reset only Normal operation Notes: 1. Selects to normal mode or ASE mode. ASEMD0 = high: normal mode ASEMD0 = low: ASE mode 2. In ASE mode, the reset hold state is entered by driving the RES and TRST pins low for the given time. In this state, the CPU does not start up, even if the RES pin is driven high. After that, when the TRST pin is driven high, H-UDI operation is enabled, but the CPU does not start up. The reset hold state is canceled by the following: another RES assert (power-on reset) or TRST reassert. 21.4.3 TDO Output Timing The timing of data output from the TDO differs according to the command type set in SDIR. The timing changes at the TCK falling edge when JTAG commands (EXTEST, CLAMP, HIGHZ, SAMPLE/PRELOAD, IDCODE, and BYPASS) are set. This is a timing of the JTAG standard. When the H-UDI commands (H-UDI reset negate, H-UDI reset assert, and H-UDI interrupt) are set, the TDO signal is output at the TCK rising edge earlier than the JTAG standard by a half cycle. Rev. 5.00 Mar. 15, 2007 Page 617 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) TCK TDO (when the H-UDI command is set) TDO (when the JTAG command is set) tTDO tTDO Figure 21.3 H-UDI Data Transfer Timing 21.4.4 H-UDI Reset An H-UDI reset is generated by setting the H-UDI reset assert command in SDIR. An H-UDI reset is of the same kind as a power-on reset. An H-UDI reset is released by inputting the H-UDI reset negate command. The required time between the H-UDI reset assert command and H-UDI reset negate command is the same as time for keeping the RESETP pin low to apply a power-on reset. SDIR H-UDI reset assert H-UDI reset negate LSI internal reset CPU state Branch to H'A0000000 Figure 21.4 H-UDI Reset 21.4.5 H-UDI Interrupt The H-UDI interrupt function generates an interrupt by setting an H-UDI command in SDIR. An H-UDI interrupt is an interrupt of general exceptions, resulting in a branch to an address based on the VBR value plus offset, and with return by the RTE instruction. This interrupt request has a fixed priority level of 15. H-UDI interrupts are accepted in sleep mode, but not in standby mode. Rev. 5.00 Mar. 15, 2007 Page 618 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) 21.5 Boundary Scan A command can be set in SDIR by the H-UDI to place the H-UDI pins in boundary scan mode stipulated by JTAG. 21.5.1 Supported Instructions This LSI supports the three mandatory instructions defined in the JTAG standard (BYPASS, SAMPLE/PRELOAD, and EXTEST) and three option instructions (IDCODE, CLAMP, and HIGHZ). BYPASS: The BYPASS instruction is a mandatory instruction that operates the bypass register. This instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. While this instruction is executing, the test circuit has no effect on the system circuits. The upper four bits of the instruction code are 1111. SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction inputs data from this LSI's internal circuitry to the boundary scan register, outputs data from the scan path, and loads data onto the scan path. While this instruction is executed, signals input to this LSI pins are transmitted directly to the internal circuitry, and internal circuit outputs are directly output externally from the output pins. This LSI's system circuits are not affected by execution of this instruction. The upper four bits of the instruction code are 0100. In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. Snapshot latching is performed in synchronization with the rising edge of the TCK signal in the Capture-DR state. Snapshot latching does not affect normal operation of this LSI. In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation, when the EXTEST instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST instruction, the parallel output latch value is constantly output to the output pin). EXTEST: This instruction is provided to test external circuitry when this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. If testing is carried out by using the EXTEST instruction N times, the Nth test data is scanned-in when test data (N-1) is scanned out. Rev. 5.00 Mar. 15, 2007 Page 619 of 794 REJ09B0237-0500 Section 21 User Debugging Interface (H-UDI) Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). The upper four bits of the instruction code are 0000. IDCODE: A command can be set in SDIR by the H-UDI pins to place the H-UDI pins in the IDCODE mode stipulated by JTAG. When the H-UDI is initialized (TRST is asserted or TAP is in the Test-Logic-Reset state), the IDCODE mode is entered. CLAMP, HIGHZ: A command can be set in SDIR by the H-UDI pins to place the H-UDI pins in the CLAMP or HIGHZ mode stipulated by JTAG. 21.5.2 Points for Attention • Boundary scan mode does not cover clock-related system signals (EXTAL, XTAL, CKIO, and CK_PHY), E10A-related signals (RES and ASEMD), and H-UDI-related signals (TCK, TDI, TDO, TMS, and TRST). • When the EXTEST, CLAMP, and HIGHZ commands are set, fix the RES pin low. • When a boundary scan test for other than BYPASS and IDCODE is carried out, fix the ASEMD pin high. 21.6 Usage Notes • An H-UDI command, once set, will not be modified as long as another command is not reissued from the H-UDI. If the same command is given continuously, the command must be set after a command (BYPASS, etc.) that does not affect LSI operations is once set. • Because LSI operations are suspended in standby mode, H-UDI commands are not accepted. To hold the state of the TAP before and after standby mode, the TCK signal must be high during standby mode transition. • The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when using an emulator. Rev. 5.00 Mar. 15, 2007 Page 620 of 794 REJ09B0237-0500 Section 22 Ethernet Physical Layer Transceiver (PHY) Section 22 Ethernet Physical Layer Transceiver (PHY) This LSI has an on-chip PHY module. 22.1 Features • Fully-integrated IEEE 802.3/802.3u compliant 10/100Mbps Ethernet PHY • PHY clock = 25 MHz, 3.3 V Analog power supply. • Integrated DSP with adaptive-equalizer and Baseline Wander (BLW) correction High immunity to crosstalk • Link-configuration automatically determined by Auto-negotiation / parallel detection; manual configuration also available • Low power consumption • Half- and Full-duplex capable for both 10 and 100 Mbps links • Automatic Polarity Correction in 10Base-T • Extended cable length option in 10Base-T • MII interface to the CPU core of this LSI. • Serial Management Interface (SMI) • Link, Activity, Duplex and Speed LED outputs Rev. 5.00 Mar. 15, 2007 Page 621 of 794 REJ09B0237-0500 Section 22 Ethernet Physical Layer Transceiver (PHY) Figure 22.1 shows the block diagram around the PHY module. CPU This LSI Outside LSI Internal bus PHY-IF MII ETC (Ether C) TX-ER MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0 TX-EN TX-CLK MDC MDIO MDI_DIR MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0 RX-CLK CRS COL RX-DV RX-ER PHY Tx/Rx CO_TX_ER CO_MII_TXD3 CO_MII_TXD2 CO_MII_TXD1 CO_MII_TXD0 CO_TX_EN CO_TX_CLK CO_MDCLK CO_MDI CO_MDO CO_MDIO_DIR CO_MII_RXD3 CO_MII_RXD2 CO_MII_RXD1 CO_MII_RXD0 CO_RX_CLK CO_CRS CO_COL CO_RX_DV CO_RX_ER LED (_CRS) LED (_LINK) LED (_SPEED100) LED (_FULL-DUPLEX) Magnetics CAT5 Figure 22.1 The block Diagram around PHY Module. Rev. 5.00 Mar. 15, 2007 Page 622 of 794 REJ09B0237-0500 Section 22 Ethernet Physical Layer Transceiver (PHY) 22.2 Pin Configuration PHY module has below pins. Table 22.1 Pin Configuration Pin Name Analog power supply 1 for PHY Analog power supply 2 for PHY Analog power supply 3 for PHY Abbreviation Vcc1A Vcc2A Vcc3A I/O Input Input Input Input Input Input Function Analog power supply for PHY Analog power supply for PHY Analog power supply for PHY Analog ground for PHY Analog ground for PHY For providing the external clock for PHY. Of course you can provide a clock from internal clock pulse generator (CPG), but you have to pull up or down this pin in that case. The differential transmit output (+) from PHY to Ethernet network The differential transmit output (-) from PHY to Ethernet network The differential receive input (+) from Ethernet network to PHY The differential receive input (-) from Ethernet network to PHY SPEED100 Output Low shows that the operating speed is 100 Mbit/s or during Auto negotiation LINK Output (Low indicates that link is on.) CRS Output (Low indicates that there is CRS (carrier sense), keeps low after inactivation of CRS about 128 ms.) DUPLEX Output (Low indicates FULL DUPLEX) Analog ground 1 for PHY Vss1A Analog ground 2 for PHY Vss2A PHY clock CK_PHY Differential transmit output (+) Differential transmit output (-) TxP TxM Output Output Input Input Output Differential receive input RxP (+) Differential receive input RxM (-) SPEED100 signal SPEED100 LINK signal CRS signal LINK CRS Output Output DUPLEX signal DUPLEX Output Rev. 5.00 Mar. 15, 2007 Page 623 of 794 REJ09B0237-0500 Section 22 Ethernet Physical Layer Transceiver (PHY) Pin Name Reference resistor Test input/output Abbreviation EXRES1 TSTBUSA I/O Input I/O Function Connect to the ground through a resistor of value 12.4Kohm, 1%. I/O for test. Do not connect anything to this pin. 22.3 Top Level Functional Architecture Functionally, this PHY module can be divided into the following sections: • • • • • 100Base-TX transmit and receive 10Base-T transmit and receive MII interface to the on-chip EtherC of this LSI Auto-negotiation to automatically determine the best speed and duplex possible Management Control to read status registers and write control register. 10M Tx logic 10M Transmitter 100M Transmitter To magnetics 100M Tx Logic MII logic Transmit MII bus 100M Rx Logic DSP system: clock data recovery Equalizer A/D 100M PLL 10M Rx Logic Squelch and Filters From magnetics Receive Auto-negotiation Central Bias 10M PLL SMI Management control = Analog blocks Figure 22.2 Architectural Overview Rev. 5.00 Mar. 15, 2007 Page 624 of 794 REJ09B0237-0500 Section 22 Ethernet Physical Layer Transceiver (PHY) 22.4 PHY Management Control The Management Control module includes 2 blocks: • Serial Management Interface (SMI) • Management Registers Set 22.4.1 Serial Management Interface (SMI) The Serial Management Interface is used to control this PHY core and obtain its status. This interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard. Nonsupported registers (7 to 15) will be read as hexadecimal "FFFF". At the system level there are 2 signals, MDIO and MDC where MDIO is bi-directional open-drain and MDC is the clock. In the core there is no notion of bi-directional signals so the MDIO signal is implemented as 3 signals: CO_MDIO_DIR, CO_MDO and CO_MDI. The relationship among these signals is made clear in Figure 22.3. CO_MDIO_DIR ENB CO_MDIO CO_MDI PHY module side MDIO EtherC side Inside of this LSI Note: Drivers are in open-drain state Figure 22.3 How to Derive MDIO Signal from Core Signals The CO_MDC signal is an a-periodic clock provided by the station management controller (SMC). The CO_MDI signal receives serial data (commands) from the controller SMC. The CO_MDO sends serial data (status) to the SMC. The minimum time between edges of the CO_MDC is 160 ns. There is no maximum time between edges. The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400 ns. These modest timing requirements allow this interface to be easily driven by the CPU. Rev. 5.00 Mar. 15, 2007 Page 625 of 794 REJ09B0237-0500 Section 22 Ethernet Physical Layer Transceiver (PHY) The data on the CO_MDO and CO_MDI lines is latched on the rising edge of the CO_MDC. The frame structure and timing of the data is shown in Figure 22.4 and Figure 22.5. Output on the rising edge Latch on the rising edge CO_MDC CO_MDI CO_MDIO_DIR CO_MDO Preamble Start of Frame OP Code PHY Address Register Address Turn Around D15 D14 ... 32 1's 0 1 1 0 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 ... Data D1 D0 Figure 22.4 MDIO Timing and Frame Structure (READ Cycle) Output on the rising edge Latch on the rising edge CO_MDC CO_MDI CO_MDIO_DIR CO_MDO Preamble Start of Frame OP Code PHY Address Register Address Turn Around 32 1's 0 1 0 1 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 D15 D14 ... ... Data D1 D0 Figure 22.5 MDIO Timing and Frame Structure (WRITE Cycle) Shown below is an example of coding for MDC cycles implemented by software loops. Note: CO_MDIO_DIR in figures 22.4 and 22.5 above has a reverse polarity in relation to the MMD bit in the PIR register. Rev. 5.00 Mar. 15, 2007 Page 626 of 794 REJ09B0237-0500 Section 22 Ethernet Physical Layer Transceiver (PHY) /* SMI register read */ unsigned short { unsigned short data; ether_reg_read( unsigned short reg_addr ) phy_preamble(); phy_reg_set( reg_addr, PHY_READ ); phy_ta_z0(); phy_reg_read( &data ); mii_idle(); return( data ); } /* SMI register write */ void { phy_preamble(); phy_reg_set( reg_addr, PHY_WRITE ); phy_ta_10(); phy_reg_write( data ); mii_idle(); } ether_reg_write( unsigned short reg_addr, unsigned short data ) /* Subroutines */ void { long i; phy_preamble( void ) i = 32; while( i > 0 ) { mii_write_1(); i--; } Rev. 5.00 Mar. 15, 2007 Page 627 of 794 REJ09B0237-0500 Section 22 Ethernet Physical Layer Transceiver (PHY) } void { long phy_reg_set( unsigned short reg_addr, long option ) i; data; unsigned short data = 0; data = (PHY_ST