SH7750S

REJ09B0366-0700 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7750, SH7750S, SH7750R Group 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7750 Series Rev.7.00 Revision Date: Oct. 10, 2008 Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.7.00 Oct. 10, 2008 Page ii of lxxxiv REJ09B0366-0700 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. ⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. ⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. ⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. ⎯ When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ⎯ The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.7.00 Oct. 10, 2008 Page iii of lxxxiv REJ09B0366-0700 Rev.7.00 Oct. 10, 2008 Page iv of lxxxiv REJ09B0366-0700 Preface The SH-4 (SH7750 Group: SH7750, SH7750S, SH7750R) microprocessor incorporates the 32-bit SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7750 Group is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, timers, two serial communication interfaces (SCI, SCIF), real-tim1e clock (RTC), user break controller (UBC), bus state controller (BSC) and smart card interface. This LSI can be used in a wide range of multimedia equipment. The bus controller is compatible with ROM, SRAM, DRAM, synchronous DRAM and PCMCIA, as well as 64-bit synchronous DRAM 4-bank system and 64-bit data bus. Target Readers: This manual is designed for use by people who design application systems using the SH7750, SH7750S, or SH7750R. To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. Purpose: This manual provides the information of the hardware functions and electrical characteristics of the SH7750, SH7750S, and SH7750R. The SH-4 Software Manual contains detailed information of executable instructions. Please read the Software Manual together with this manual. How to Use the Book: • To understand general functions → Read the manual from the beginning. The manual explains the CPU, system control functions, peripheral functions and electrical characteristics in that order. • To understanding CPU functions → Refer to the separate SH-4 Software Manual. Explanatory Note: Bit sequence: upper bit at left, and lower bit at right List of Related Documents: The latest documents are available on our Web site. Please make sure that you have the latest version. (http://www.renesas.com/) • User manuals for SH7750, SH7750S, and SH7750R Name of Document SH7750, SH7750S, SH7750R Group Hardware Manual SH-4 Software Manual Document No. This manual REJ09B0318-0600 Rev.7.00 Oct. 10, 2008 Page v of lxxxiv REJ09B0366-0700 • User manuals for development tools Name of Document SuperH™ RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual SuperH™ RISC engine Simulator/Debugger User's Manual High-performance Embedded Workshop User's Manual Document No. REJ10J1571-0100 REJ10B0210-0400 REJ10J1737-0100 Rev.7.00 Oct. 10, 2008 Page vi of lxxxiv REJ09B0366-0700 Main Revisions for This Edition Item All Page ⎯ Revision (See Manual for Details) • Notification of change in company name amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. Description amended Iφ → Ick Bφ → Bck Pφ → Pck 1.1 SH7750, SH7750S, 1 SH7750R Groups Features Description amended This LSI (SH7750, SH7750S, and SH7750R Groups) is a 32-bit RISC (reduced instruction set computer) microprocessor with a SH-4 CPU core and features upward compatibility with SH-1, SH-2, and SH-3 microcomputers at the instruction set level. Item LSI Features Table 1.1 LSI Features 1 to 3, 8 Table amended • • Superscalar architecture: Parallel execution of two instructions External buses ⎯ Separate 26-bit address and 64-bit data buses ⎯ External bus frequency of 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus frequency CPU FPU • • RISC-type instruction set (upward-compatible with SH-1, SH-2, and SH-3) Floating-point registers: 32 bits × 16 × 2 banks (single-precision 32 bits × 16 or double-precision 64 bits × 8 ) × 2 banks Voltage (Internal) 1.95 V 1.8 V 1.5 V Operating Frequency 200 MHz 167 MHz 128 MHz 200 MHz Product lineup Abbreviation SH7750 Model No. HD6417750BP200M HD6417750F167 HD6417750VF128 HD6417750SBP200 HD6417750SF200 Package 256-pin BGA 208-pin QFP SH7750S 1.95 V 256-pin BGA 208-pin QFP 1.8 V 1.5 V 167 MHz 133 MHz HD6417750SF167 HD6417750SVF133 HD6417750SVBT133 264-pin CSP 292-pin BGA 256-pin BGA 208-pin QFP 292-pin BGA 256-pin BGA 208-pin QFP SH7750R 1.5 V 240 MHz HD6417750RBG240 HD6417750RBP240 HD6417750RF240 200 MHz HD6417750RBG200 HD6417750RBP200 HD6417750RF200 Rev.7.00 Oct. 10, 2008 Page vii of lxxxiv REJ09B0366-0700 Item 1.2 Block Diagram Figure 1.1 Block Diagram of SH7750/ SH7750S/SH7750R Group Functions Page 9 Revision (See Manual for Details) Figure amended CPU 32-bit address (instructions) UBC FPU 32-bit data (instructions) 32-bit address (data) 32-bit data (store) 64-bit data (store) Lower 32-bit data Upper 32-bit data 32-bit data (load) SH-4 Core Lower 32-bit data I cache ITLB Cache and TLB controller UTLB O cache 29-bit address 32-bit data CPG INTC 16-bit peripheral data bus Peripheral address bus SCI (SCIF) BSC 32-bit data DMAC 64-bit data TMU External bus interface 26-bit address 64-bit data Rev.7.00 Oct. 10, 2008 Page viii of lxxxiv REJ09B0366-0700 64-bit data RTC Address Item 1.3 Pin Arrangement Figure 1.4 Pin Arrangement (264-Pin CSP) Page 12 Revision (See Manual for Details) Figure amended 1 A VSS-CPG XTAL EXTAL VDD-CPG TRST TDO MD6/IOIS16 A0 VDDQ VDDQ A20 VDD TCLK VSS-RTC XTAL2 EXTAL2 IRL2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 B RESET CS4 VDD-PLL2 VSS STATUS0 DACK0 A24 VDDQ MD7/TXD CA IRL3 C RDY VSS-PLL2 VSS-PLL1 VDD-PLL1 TCK VSSQ VSSQ MD3/CE2A A22 A18 VDDQ VDDQ VDD-RTC MD1/TXD2 NMI D CS0 VSSQ CKIO2ENB TDI VDD A1 MD5/RAS2 A23 VSS MD8/RTS2 CTS2 VSSQ IRL0 IRL1 E BS CS1 CS5 CS6 TMS ASEBRK/ BRKACK VDDQ VDDQ MD4/CE2B VSSQ VSSQ SCK2/ MRESET D48 RD/WR2 MD2/RXD2 VSSQ F VDD D47 VDDQ RD2 D32 D33 STATUS1 DACK1 VSSQ A25 A21 A19 D49 VDDQ D63 MD0/SCK D62 G D45 VDDQ D46 VSS VSSQ D34 D50 VDDQ VDD VSSQ VSS D61 H VDDQ D43 D44 D35 VSSQ D36 CSP264 (Top view) D52 VDDQ D51 VSSQ D60 D59 J VDDQ D38 D42 D41 D37 VSSQ VSSQ D57 D53 D54 D58 VDDQ K D39 D0 VSSQ D15 VDDQ D40 D56 VSSQ D31 D16 D55 VDDQ L D1 VSS VSSQ VDD VDDQ D14 D30 VSSQ VSS D18 VDDQ D17 M D2 D4 D3 VDDQ D13 A14 A9 VDDQ A6 A2 D29 D28 D27 VDDQ D19 VDD N VSSQ D5 D11 D12 A16 VDDQ VDDQ A7 A4 DRAK0 VSSQ VSS D26 D21 VDDQ D20 P VSSQ VDDQ VDDQ WE4/CAS4/ WE0/CAS0/ DQM4 DQM0 CKE WE5/CAS5/ DQM5 VDD A11 VSSQ VSSQ CS2 RD/CASS/ VSSQ FRAME RAS VSSQ D25 DREQ1 R D6 BREQ/ BSACK D10 A17 VSS A12 A8 VDDQ VDDQ WE3/CAS3/ WE6/CAS6/ WE2/CAS2/ RXD DQM3/ICIOWR DQM6 DQM2/ICIORD T BACK/ BSREQ VSSQ D8 VDDQ VSSQ A13 VSSQ CKIO2 A3 VDD RD/WR D24 D22 VSSQ DREQ0 U D9 D7 WE1/CAS1/ DQM1 A15 VSSQ A10 CKIO A5 DRAK1 CS3 VDDQ VDDQ WE7/CAS7/ DQM7/REG D23 VSSQ Figure 1.5 Pin Arrangement (292-Pin BGA) 1.4.1 Pin Functions (256-Pin BGA) Table 1.2 Pin Functions 13 Newly added 17, 20, 23 Table and notes amended No. 92 93 94 95 Pin No. Y11 V10 U10 W11 Memory Interface Pin Name CKIO VDDQ VSSQ CKIO2 RD/WR RD/WR2 I/O O Function Clock output Reset SRAM CKIO DRAM SDRAM PCMCIA MPX CKIO CKIO Power IO VDD (3.3 V) Power IO GND (0 V) O O O CKIO*1 Read/write RD/WR CKIO CKIO RD/WR RD/WR CKIO RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR 115 W16 178 E18 Notes: ... VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package. NC pins must be left completely open, and not connected to a power supply, GND, etc. Rev.7.00 Oct. 10, 2008 Page ix of lxxxiv REJ09B0366-0700 Item 1.4.2 Pin Functions (208-Pin QFP) Table 1.3 Pin Functions Page 26, 27, 31 Revision (See Manual for Details) Table and notes amended Memory Interface Pin No. 77 95 Pin Name CKIO RD/WR I/O O O Function Clock output Read/write Reset SRAM CKIO DRAM SDRAM PCMCIA MPX CKIO RD/WR CKIO RD/WR RD/WR RD/WR RD/WR Notes: ... VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package. The RD2, RD/WR2, CKIO2, and CKIO2ENB pins are not provided on the QFP package. 1.4.3 Pin Functions (264-Pin CSP) Table 1.4 Pin Functions 35, 38, 41 Table and notes amended Pin No. No. 90 91 92 93 U9 M9 P9 T9 Memory Interface Pin Name CKIO VDDQ VSSQ CKIO2 RD/WR RD/WR2 I/O O Function Clock output Reset SRAM CKIO DRAM SDRAM PCMCIA MPX CKIO CKIO Power IO VDD (3.3 V) Power IO GND (0 V) O O O CKIO* Read/write RD/WR CKIO CKIO RD/WR RD/WR CKIO RD/WR RD/WR 113 T12 175 E14 RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR Notes: ... Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-chip RTC is used. NC pins must be left completely open, and not connected to a power supply, GND, etc. 1.4.4 Pin Functions (292-Pin BGA) 42 to 52 Newly added Table amended Type Control registers Registers SR Initial Value* MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, IMASK = 1111 (H'F), reserved bits = 0, others undefined 2.2.1 Privileged Mode 55 and Banks Table 2.1 Initial Register Values 2.6 Processor States Figure 2.6 Processor State Transitions 68 Figure amended From any state when RESET = 0 and MRESET = 1 RESET = 0 and MRESET = 0 Power-on reset state RESET = 0, MRESET = 1 Manual reset state Reset state 3.8 Usage Notes 4.3.1 Configuration • LRU (SH7750R only) 109 119 Newly added Description amended Rev.7.00 Oct. 10, 2008 Page x of lxxxiv REJ09B0366-0700 Item Page Revision (See Manual for Details) Newly added 4.3.10 Notes on Using 125 to Cache Enhanced Mode 127 (SH7750R Only) 4.4.1 Configuration • LRU (SH7750R only) 130 Description amended • LRU (SH7750R only) In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each entry address. When an entry is registered, the LRU bit indicates which of the 2 ways it is to be registered in. The LRU bit is a single bit of each entry, and its value is controlled by hardware. 5.3.2 Exception Handling Vector Addresses 151 Description amended The reset vector address is fixed at H'A000 0000. General exception and interrupt vector addresses are determined by adding the offset for the specific event to the vector base address, which is set by software in the vector base register (VBR). 5.5.3 Exception Requests and BL Bit 158 Description amended When the BL bit in SR is 0, general exception and interrupts are accepted. When the BL bit in SR is 1 and a general exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A000 0000). 5.6.1 Resets (1) Power-On Reset 159 Description amended In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. ... SR.IMASK = B'1111; (2) Manual Reset 160 Description amended In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. ... SR.IMASK = B'1111; Rev.7.00 Oct. 10, 2008 Page xi of lxxxiv REJ09B0366-0700 Item 5.6.1 Resets (3) H-UDI Reset Page 161 Revision (See Manual for Details) Description amended In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. ... SR.IMASK = B'1111; (4) Instruction TLB Multiple-Hit Exception 162 Description amended In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. ... SR.IMASK = B'1111; (5) Operand TLB Multiple-Hit Exception 163 Description amended In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. ... SR.IMASK = B'1111; 5.6.2 General Exceptions (11) General FPU Disable Exception 5.6.3 Interrupts (3) Peripheral Module Interrupts 174 Note amended Note: * FPU instructions are instructions in which the first 4 bits of the instruction code are H'F (but excluding undefined instruction H'FFFD), and the LDS, STS, LDS.L, and STS.L instructions corresponding to FPUL and FPSCR. 180 Description amended INTEVT = H'00000400 ~ H'00000B80; Rev.7.00 Oct. 10, 2008 Page xii of lxxxiv REJ09B0366-0700 Item 5.7 Usage Notes Page 182 Revision (See Manual for Details) Description amended 2. If a general exception or interrupt occurs when SR.BL = 1 a. General exception When a general exception other than a user break occurs, a manual reset is executed. The value in EXPEVT at this time is H'0000 0020; the value of the SPC and SSR registers is undefined. ... 3. SPC when an exception occurs a. Re-execution type general exception The PC value for the instruction in which the general exception occurred is set in SPC, and the instruction is reexecuted after returning from exception handling. If an exception occurs in a delay slot instruction, however, the PC value for the delay slot instruction is saved in SPC regardless of whether or not the preceding delayed branch instruction condition is satisfied. b. Completion type general exception or interrupt The PC value for the instruction following that in which the general exception occurred is set in SPC. If an exception occurs in a branch instruction with delay slot, however, the PC value for the branch destination is saved in SPC. 6.5 Floating-Point Exceptions • Enable/disable exception handling 194 Description amended For information on these possibilities, see the individual instruction descriptions in chapter 9 of the SH-4 Software Manual. The particulars differ demanding on the instruction. All exception events that originate in the FPU are assigned as the same exception event. The meaning of an exception is determined by software by reading system register FPSCR and interpreting the information it contains. Description amended In addition to the geometric operation instructions, the FPU also supports high-speed data transfer instructions. When FPSCR.SZ = 1, the FPU can perform data transfer by means of pair single-precision data transfer instructions. 6.6.2 Pair Single196 Precision Data Transfer 6.7 Usage Notes 197 to 207 Newly added Rev.7.00 Oct. 10, 2008 Page xiii of lxxxiv REJ09B0366-0700 Item 7.3 Instruction Set Table 7.12 FloatingPoint Graphics Acceleration Instructions Page 227 Revision (See Manual for Details) Table amended Instruction FRCHG FSCHG Operation ~FPSCR.FR → FPSCR.FR ~FPSCR.SZ → FPSCR.SZ 7.4 Usage Notes 8.4 Usage Notes 227 to 229 258 Newly added Newly added Description amended • Module standby function (TMU, RTC, SCI/SCIF, DMAC, SQ*, and UBC* ) 9.1.1 Types of Power- 259 Down Modes 9.2.4 Standby Control 266 Register 2 (STBCR2) Description amended Bit 6 —STATUS Pin High-Impedance Control (STHZ): This bit selects whether the STATUS0 and STATUS1 pins are set to high-impedance when in hardware standby mode. Bit 6: STHZ 0 1 Description Sets STATUS0, 1 pins to high-impedance when in hardware standby mode (Initial value) Drives STATUS0, 1 pins to LH when in hardware standby mode 9.5.2 Exit from Standby 271 Mode Notes amended Notes: 1. Only when the RTC clock (32.768 kHz) is operating (see section 19.2.2, IRL Interrupts), standby mode can be exited by means of IRL3–IRL0 (when the IRL3–IRL0 level is higher than the SR register IMASK mask level). 2. GPIO can be used to cancel standby mode when the RTC clock (32.768 kHz) is operating (when the GPIO level is higher than the SR register IMASK mask level). 9.7.1 Transition to Hardware Standby Mode 274 Description amended 3. On the SH7750S, the RTC continues to operate even when no power is supplied to power pins other than the RTC power supply pin. The state of the STATUS pin reflects the setting of the STHZ bit. Refer to appendix E, Pin Functions, for details on output pin states. Rev.7.00 Oct. 10, 2008 Page xiv of lxxxiv REJ09B0366-0700 Item 9.7.2 Exit from Hardware Standby Mode Page 274 Revision (See Manual for Details) Description amended Setting the CA pin level high after the RESET pin level has been set low and the SCK2 pin high starts the clock to oscillate. The RESET pin level should be kept low until the clock has stabilized, then set high so that the CPU starts the power-on reset exiting procedure. 9.7.3 Usage Notes 275 Description amended 1. The CA pin level must be kept high when the RTC power supply is started (figure 9.15). 2. On the SH7750R, power must be supplied to the other power supply pins (VDD, VDDQ, VDD−CPG, VDD−PLL1, and VDD−PLL2), in addition to the RTC power supply pin, in hardware standby mode. 9.8.1 In Reset Figure 9.2 STATUS Output in Manual Reset 276 Figure amended CKIO Must be asserted for tRESW or longer RESET* SCK2 STATUS Normal Reset 0–30 Bcyc ≥ 0 Bcyc Normal Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting until the end of the currently executing bus cycle. 9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only) Figure 9.15 Timing When VDD-RTC Power is Off → On 285 Figure amended VDD-RTC Power-on oscillation setting time CA VDD, VDDQ* Min 0s RESET SCK2 Note: * VDD, VDD-PLL1/2, VDDQ, VDD-CPG 9.9 Usage Notes 286 Newly added Rev.7.00 Oct. 10, 2008 Page xv of lxxxiv REJ09B0366-0700 Item 10.1.1 Features Page 287 Revision (See Manual for Details) Description amended • Three clocks The CPG can generate the CPU clock (Ick) used by the CPU, FPU, caches, and TLB, the peripheral module clock (Pck) used by the peripheral modules, and the bus clock (Bck) used by the external bus interface. 10.3 Clock Operating Modes Table 10.4 FRQCR Settings and Internal Clock Frequencies 10.11 Usage Notes 11.1 Overview 294 Table amended Frequency Division Ratio of Frequency Divider 2 309 311 Newly added Description amended This LSI includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillation circuit for use by the RTC. 11.2.16 RTC Control Register 2 (RCR2) Bit 3— Oscillation Circuit Enable (RTCEN): 326 Description amended Controls the operation of the RTC crystal oscillation circuit. Bit 3: RTCEN 0 1 Description RTC crystal oscillation circuit halted RTC crystal oscillation circuit operating (Initial value) 11.5.4 RTC Register 334 to Settings (SH7750 only) 336 12.1.2 Block Diagram 338 Figure 12.1 Block Diagram of TMU Newly added Figure amended Pck/4,16, 64*1 Prescaler To each channel 12.2.7 Input Capture Register 2 (TCPR2) 350 Title amended Newly added Description amended Ensure that the external clock frequency for any channel does not exceed Pck/8. 12.5.2 Underflow Flag 356 Writes (SH7750 only) 12.5.5 External Clock Frequency Rev.7.00 Oct. 10, 2008 Page xvi of lxxxiv REJ09B0366-0700 Item Page Revision (See Manual for Details) Figure amended BS RD/FRAME RD/WR WE7–WE0 RAS CAS7–CAS0, CASS CKE ICIORD, ICIOWR REG IOIS16 13.1.2 Block Diagram 359 Figure 13.1 Block Diagram of BSC Memory control unit 13.1.3 Pin Configuration Table 13.1 BSC Pins 360 Table amended Name Data bus Signals D63−D52, D31−D0 I/O I/O Description Data input/output When port functions are used and DDT mode is selected, input the DTR format. Otherwise, when port functions are used, D63−D52 cannot be used and should be left open. 13.1.6 PCMCIA Support Table 13.5 PCMCIA Support Interfaces 371 Table and notes amended IC Memory Card Interface Signal Pin Name 59 WAIT I/O Function O Wait request Signal Name WAIT I/O Card Interface I/O Function O Wait request Corresponding LSI Pin 2 RDY* Note: 1. WP is not supported. 2. Input an external wait request with correct polarity. 13.2.1 Bus Control Register 1 (BCR1) 372 Bit table amended Bit: Initial value: R/W: 31 ENDIAN 30 MASTER 1 29 A0MPX 1 28 — 0 R 1 27 — 0 R 26 2 DPUP* 0/1* R 0/1* R 0/1* R 0 R/W 13.2.7 Wait Control Register 3 (WCR3) 400 Description amended Bits 4n+3⎯Area n (4 or 1) Read-Strobe Negate Timing (AnRDH) (Setting Only Possible in the SH7750R): When reading, these bits specify the timing for the negation of read strobe. These bits should be cleared to 0 when a byte control SRAM setting is made. Valid only for the SRAM interface. Bit 4n + 3: AnRDH 0 1 Read-Strobe Negate Timing Read strobe negated after hold wait cycles specified by WCR3.AnH bits (Initial value) Read strobe negated according to data sampling timing Rev.7.00 Oct. 10, 2008 Page xvii of lxxxiv REJ09B0366-0700 Item Page Revision (See Manual for Details) Description and table amended Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3 are both designated as synchronous DRAM interface. See Connecting a 128-Mbit/256Mbit Synchronous DRAM with 64-bit Bus Width (SH7750R Only): in section 13.3.5, Synchronous DRAM Interface. Bit 31: RASD 0 Description Auto-precharge mode (Initial value) 13.2.8 Memory Control 402 Register (MCR) Bit 31—RAS Down (RASD): Bits 29 to 27—RAS 402 Precharge Time at End of Refresh (TRC2– TRC0) Bits 21 to 19—RAS Precharge Period (TPC2–TPC0): 403 Note added Note: For setting values and the period during which no command is issued, see 22.3.3, Bus Timing. Description amended and note added When the DRAM interface is selected, these bits specify the minimum number of cycles until RAS is asserted again after being negated. When the synchronous DRAM interface is selected, these bits specify the minimum number of cycles until the next bank active command after precharging. Note: For setting values and the period during which no command is issued, see 22.3.3, Bus Timing. Bits 15 to 13—Write Precharge Delay (TRWL2–TRWL0): 404 Description amended and note added After a write cycle, the next active command is not issued for a period equivalent to the setting values of the TPC[2:0] and TRWL[2:0] bits.* ... Note: * For setting values and the period during which no command is issued, see 22.3.3, Bus Timing. Bits 12 to 10—CASBefore-RAS Refresh RAS Assertion Period (TRAS2–TRAS0): 405 Description amended and note added When the DRAM interface is set, these bits set the RAS assertion period in CAS-before-RAS refreshing. When the synchronous DRAM interface is set, the bank active command is not issued for the period set by the TRC[2:0]* and TRAS[2:0] bits after an auto-refresh command is issued. Note: For setting values and the period during which no command is issued, see 22.3.3, Bus Timing. Rev.7.00 Oct. 10, 2008 Page xviii of lxxxiv REJ09B0366-0700 Item Page Revision (See Manual for Details) Description deleted After the self-refresh is cleared, the refresh controller immediately generates a refresh request. The RAS precharge time immediately after the end of the self-refreshing can be set by bits TRC2–TRC0 in MCR. CAS-before-RAS refreshing is performed in normal operation, in sleep mode, and in the case of a manual reset. 13.3.4 DRAM Interface 463 Refresh Timing: • Self-Refresh 13.3.5 Synchronous DRAM Interface 465 Description amended With this LSI, burst read/burst write mode is supported as the synchronous DRAM operating mode. The data bus width is 32 or 64 bits, and the SZ size bits in MCR must be set to 00 or 11. The burst enable bit (BE) in MCR is ignored, a 32-byte burst transfer is performed in a cache fill/copy-back cycle, and in a write-through area write or a non-cacheable area read/write, 32-byte data is read even in a single read in order to access synchronous DRAM with a burst read/write access. 32-byte data transfer is also performed in a single write, but DQMn is not asserted when unnecessary data is transferred. For details on the burst length, see section 13.2.10, Synchronous DRAM Mode Register (SDMR), and Power-On Sequence in section 13.3.5, Synchronous DRAM Interface. The SH7750R Group supports burst read and burst write operations with a burst length of 4 as a synchronous DRAM operating mode when using a 32-bit data bus. The burst enable (BE) bit in MCR is ignored, and a 32-byte burst transfer is performed in a cache fill or copy-back cycle. In write-through area write operations and non-cacheable area read or write operations, 16 bytes of data is read even in a single read because burst read or write accesses to synchronous DRAM use a burst length of 4. Sixteen bytes of data is transferred in the case of a single write also, but DQMn is not asserted when unnecessary data is transferred. For changing the burst length (a function only available in the SH7750R) for a 32-bit bus, see Notes on Changing the Burst Length (SH7750R Only) in section 13.3.5, Synchronous DRAM Interface. Rev.7.00 Oct. 10, 2008 Page xix of lxxxiv REJ09B0366-0700 Item 13.3.5 Synchronous DRAM Interface Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3) Page 466 Revision (See Manual for Details) Figure amended SH7750, SH7750S, SH7750R A12–A3 CKIO CKE CS3 RAS CASS RD/WR D63–D48 DQM7 DQM6 Figure 13.27 Example 467 of 32-Bit Data Width Synchronous DRAM Connection (Area 3) Figure amended SH7750, SH7750S, SH7750R A11–A2 CKIO CKE CS3 RAS CASS RD/WR D31–D16 DQM3 DQM2 Figure 13.37 Burst Write Timing (Different Row Addresses) 481 Figure amended Tpr CKIO Bank Tpc Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Trwl Row Row Precharge-sel H/L Row Row H/L Address CSn RD/WR c1 Power-On Sequence: Figure 13.42 (1) Synchronous DRAM Mode Write Timing (PALL) 490 Figure amended CASS D63–D0 CKE (High) Rev.7.00 Oct. 10, 2008 Page xx of lxxxiv REJ09B0366-0700 Item 13.3.5 Synchronous DRAM Interface Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set) Connecting a 128Mbit/256-Mbit Synchronous DRAM with 64-bit Bus Width (SH7750R Only): Page 491 Revision (See Manual for Details) Figure amended CASS D63–D0 CKE (High) 494, 495 Description amended • In the auto-refresh operation, the REF command is issued twice continuously in response to a single refresh request. The interval cycle number between the first and second REF commands issuance is specified by the setting of the TRAS2−TRAS0 bits in MCR, which is 4 to 11 CKIO cycles. The interval cycle number between the second REF command and the next ACTV command issuance is specified by the settings of both the TRAS2−TRAS0 bits and the TRC2−TRC0 bits in MCR in the sum total, which is 4 to 32 CKIO cycles. Set RTCOR and bits CKS2−CKS0, and MCR so as to satisfy the refresh-interval rating of the synchronous DRAM which you are using. The synchronous DRAM autorefresh timing with 64-bit bus width is shown below figure. Figure newly added Figure 13.46 496 Synchronous DRAM Auto-Refresh Timing with 64-Bit Bus Width (TRAS [2:0] = 001, TRC [2:0] = 001)) 13.3.7 PCMCIA Interface Figure 13.51 Basic Timing for PCMCIA Memory Card Interface 505 Figure amended WE1 (write) D15–D0 (write) Figure 13.52 Wait 506 Timing for PCMCIA Memory Card Interface Figure amended WE1 (write) D15–D0 (write) Rev.7.00 Oct. 10, 2008 Page xxi of lxxxiv REJ09B0366-0700 Item 13.3.7 PCMCIA Interface Figure 13.54 Basic Timing for PCMCIA I/O Card Interface Page 508 Revision (See Manual for Details) Figure amended ICIOWR (write) D15–D0 (write) Figure 13.55 Wait 509 Timing for PCMCIA I/O Card Interface Figure amended ICIOWR (write) D15–D0 (write) 13.3.8 MPX Interface Figure 13.57 Example of 64-Bit Data Width MPX Connection 512 Figure amended SH7750, SH7750S, SH7750R CKIO CSn BS RD/FRAME RD/WR D63–D0 RDY Figure 13.66 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Figure 13.67 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) 521 Title amended 522 Title amended Rev.7.00 Oct. 10, 2008 Page xxii of lxxxiv REJ09B0366-0700 Item 13.3.8 MPX Interface Figure 13.68 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Figure 13.69 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) 13.3.16 Notes on Usage Synchronous DRAM Mode Register Setting (SH7750, SH7750S Only): Page 523 Revision (See Manual for Details) Title amended 524 Title amended 543 Notes amended 3. If synchronous DRAM mode register setting is performed immediately following write access to the on-chip peripheral 2 modules* , the values written to the on-chip peripheral modules cannot be guaranteed. Note that following power-on, synchronous DRAM mode register settings should be performed before accessing synchronous DRAM. After making mode register settings, do not change them. BSREQ Output in Partial-Sharing Master Mode 543, 544 Newly added 14.2.1 DMA Source 552 Address Registers 0–3 (SAR0–SAR3) Description deleted When transfer is performed from memory to an external device with DACK in DDT mode, DTR format [31:0] is set in SAR0 [31:0]. For details, see Data Transfer Request Format in section 14.5.2, Pin in DDT Mode. Description amended These bits specify incrementing/decrementing of the DMA transfer source address. The specification of these bits is ignored when data is transferred from an external device to external memory in single address mode. For channel 0, in DDT mode these bits are set to SM1 = 0 and SM0 = 1 with the DTR format. 14.2.4 DMA Channel Control Registers 0−3 (CHCR0−CHCR3) Bits 13 and 12⎯Source Address Mode 1 and 0 (SM1, SM0): 560 Rev.7.00 Oct. 10, 2008 Page xxiii of lxxxiv REJ09B0366-0700 Item 14.3.2 DMA Transfer Requests Page 569 Revision (See Manual for Details) Description amended The DS bit in CHCR0/CHCR1 is used to select either falling edge detection or low level detection for the DREQ signal (level detection when DS = 0, edge detection when DS = 1). DREQ is accepted after a power-on reset if TE = 0, NMIF = 0, and AE = 0, but transfer is not executed if DMA transfer is not enabled (DE = 0 or DME = 0). 14.3.4 Types of DMA Transfer Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode Table 14.8 External Request Transfer Sources and Destinations in Normal DMA Mode 582 Notes amended Notes: 2. Auto-request, or on-chip peripheral module request possible. If the transfer request source is the SCI (SCIF), either the transfer source must be SCRDR1 (SCFRDR2) or the transfer destination must be SCTDR1 (SCFTDR2). 583 Title ameded 14.3.5 Number of Bus 585 Cycle States and DREQ Pin Sampling Timing Description added DREQ Pin Sampling Timing: In external request mode, the DREQ pin is sampled at the rising edge of CKIO clock pulses. When DREQ input is detected, a DMAC bus cycle is generated and DMA transfer executed after four CKIO cycles at the earliest. When falling edge detection is selected for DREQ, the DMAC will recognize DREQ two cycles (CKIO) later because the signal must pass through the asynchronous input synchronization circuit. (There is a 1-cycle (CKIO) delay when low-level detection is selected.) The second and subsequent DREQ sampling operations are performed one cycle after the start of the first DMAC transfer bus cycle (in the case of single address mode). Rev.7.00 Oct. 10, 2008 Page xxiv of lxxxiv REJ09B0366-0700 Item 14.5.2 Pins in DDT Mode Figure 14.24 System Configuration in OnDemand Data Transfer Mode Page 605 Revision (See Manual for Details) Figure amended DBREQ/DREQ0 BAVL/DRAK0 TR/DREQ1 TDACK/DACK0 SH7750, SH7750S, SH7750R ID1, ID0/DRAK1, DACK1 CKIO D63–D0=DTR External device A25–A0, RAS, CAS, WE, DQMn, CKE Synchronous DRAM • TR: Transfer request signal Description amended Assertion of TR has the following different meanings. ⎯ In normal data transfer mode (channel 0, except channel 0), TR is asserted, and at the same time the DTR format is output, two cycles after BAVL is asserted. 608 Notes amended 7. For DTR format transfer when ID[1:0] = 00, input MD[1:0] and SZ ≠ 101, 110. 14.8.3 Transfer Channel Notification in DDT Mode 648 Description amended When the DMAC is set up for eight-channel external request acceptance in DDT mode (DMAOR.DBL = 1), the ID [1:0] bits and the simultaneous (on the timing of TDACK assertion) assertion of ID2 from the BAVL (data bus available) pin are used to notify the external device of the DMAC channel that is to be used (see table 14.15). Table amended Function of BAVL TDACK = High Bus available Table 14.16 Function of BAVL 14.9 Usage Notes 10. [SH7750 Only] 15.1 Overview 653 655 Newly added Description amended The SCI supports a smart card interface. This is a serial communication function supporting a subset of the ISO/IEC 7816-3 (identification cards) standard. For details, see section 17, Smart Card Interface. Rev.7.00 Oct. 10, 2008 Page xxv of lxxxiv REJ09B0366-0700 Item Page Revision (See Manual for Details) Description of 1. and 2. added, and figure replaced 15.3.3 Multiprocessor 702 to Communication 704 Function Multiprocessor Serial Data Reception: Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1) Figure 15.16 Example 706 of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Figure amended 1 Serial data Start Data (ID1) bit 0 D0 D1 D7 Stop Start MPB bit bit 1 1 0 Data (Data1) D0 D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF SCRDR1 value RXI interrupt request (multiprocessor interrupt) MPIE = 0 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler ID1 As data is not this RXI interrupt station's ID, MPIE request bit is set to 1 again MPIE = 1 The RDRF flag is cleared to 0 by the RXI interrupt handler. (a) Data does not match station's ID Start Data (ID2) bit 0 D0 D1 D7 Stop Start MPB bit bit 1 1 0 Data (Data2) D0 D1 D7 Stop MPB bit 0 1 1 Serial data 1 Idle state (mark state) MPIE RDRF SCRDR1 value ID1 ID2 Data2 RXI interrupt request (multiprocessor interrupt) MPIE = 0 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler As data matches this station's ID, reception continues and data is received by RXI interrupt handler MPIE bit set to 1 again (b) Data matches station's ID 15.5 Usage Notes Handling of TEND Flag and TE Bit SH7750 Only 720 Newly added 722 to 724 Newly added Rev.7.00 Oct. 10, 2008 Page xxvi of lxxxiv REJ09B0366-0700 Item 16.1.3 Pin Configuration Table 16.1 SCIF Pins Page 728 Revision (See Manual for Details) Note amended Note: After a power-on reset, these pins function as mode input pins MD1, MD2 and MD8. These pins can function as serial pins by setting the SCIF operation with the TE, RE, and CKE1 bits in SCSCR2 and the MCE bit in SCFCR2. These pins are made to function as serial pins by performing SCIF operation settings with the TE, RE, and CKE1 bits in SCSCR2 and the MCE bit in SCFCR2. Break state transmission and detection can be set in the SCIF's SCSPTR2 register. 16.2.9 FIFO Control Register (SCFCR2) Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): 747 Description amended • SH7750 Bit 5: TTRG1 0 Bit 4: TTRG0 0 1 1 0 1 Transmit Trigger Number 7 (9) 3 (13) 1 (15) 0 (16) (Initial value) Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set. • SH7750S/SH7750R Bit 5: TTRG1 0 Bit 4: TTRG0 0 1 1 0 1 Transmit Trigger Number 8 (8) 4 (12) 2 (14) 1 (15) (Initial value) Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set. 16.2.11 Serial Port Register (SCSPTR2) 750, 751 Description amended Bit: 7 RTSIO Initial value: R/W: 0 R/W 6 RTSDT — R/W 5 CTSIO 0 R/W 4 CTSDT — R/W 3 — 0 R 2 — — R 1 0 SPB2IO SPB2DT 0 R/W — R/W Bit 3—Reserved: This bit is always read as 0, and should only be written with 0. Bit 2—Reserved: The value of this bit is undefined when read. The write value should always be 0. 17.1 Overview 775 Description amended The serial communication interface (SCI) supports a subset of the ISO/IEC 7816-3 (identification cards) standard as an extended function. 17.1.3 Pin Configuration Table 17.1 Smart Card Interface Pins 777 Note added Note: The serial clock pin and transmit data pin function as mode input pins MD0 and MD7 after a power-on reset Rev.7.00 Oct. 10, 2008 Page xxvii of lxxxiv REJ09B0366-0700 Item Page Revision (See Manual for Details) Figure amended 19.1.2 Block Diagram 826 Figure 19.1 Block Diagram of INTC Interrupt request SR IMASK CPU 19.1.3 Pin Configuration Table 19.1 INTC Pins 827 Table amended Pin Name Nonmaskable interrupt input pin Interrupt input pins Abbreviation NMI IRL3–IRL0 I/O Input Input Function Input of nonmaskable interrupt request signal Input of interrupt request signals (maskable by IMASK in SR) 19.2.1 NMI Interrupt 828 Description amended NMI interrupt exception handling does not affect the interrupt mask level bits (IMASK) in the status register (SR). 19.2.2 IRL Interrupts 830 Description amended The interrupt mask bits (IMASK) in the status register (SR) are not affected by IRL interrupt handling. 19.2.3 On-Chip Peripheral Module Interrupts 831 Description amended The interrupt mask bits (IMASK) in the status register (SR) are not affected by on-chip peripheral module interrupt handling. Rev.7.00 Oct. 10, 2008 Page xxviii of lxxxiv REJ09B0366-0700 Item 19.4.1 Interrupt Operation Sequence Page 843 Revision (See Manual for Details) Description and notes amended 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (IMASK) in the status register (SR) of the CPU. If the request priority level is higher that the level in bits IMASK, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. ... Notes: 1. The interrupt mask bits (IMASK) in the status register (SR) are not changed by acceptance of an interrupt in this LSI. 2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, then wait for the interval shown in table 19.9 (Time for priority decision and SR mask bit comparison) before clearing the BL bit or executing an RTE instruction. Figure 19.3 Interrupt Operation Flowchart 844 Figure amended Level 15 interrupt? Yes Yes IMASK* = level 14 or lower? No Set interrupt source in INTEVT Save SR to SSR; save PC to SPC Set BL, MD, RB bits in SR to 1 Branch to exception handler Yes No Level 14 interrupt? Yes IMASK = level 13 or lower? No Yes No Level 1 interrupt? Yes IMASK = level 0? No No Note: * IMASK: Interrupt mask bits in status register (SR) 19.6 Usage Notes 847 to 849 Newly added Rev.7.00 Oct. 10, 2008 Page xxix of lxxxiv REJ09B0366-0700 Item Page Revision (See Manual for Details) Description amended 2. Execute instructions requiring 5 states for execution after the memory store instruction that updated the register. As the CPU executes two instructions in parallel and a minimum of 0.5 state is required for execution of one instruction, 11 instructions must be inserted. The updated value will be valid from the 6th state onward. Description amended The high-performance user debug interface (H-UDI) is a serial input/output interface supporting a subset of the JTAG, IEEE 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. 20.2.1 Access to UBC 854 Control Registers 21.1.1 Features 879 21.1.3 Pin Configuration Table 21.1 H-UDI Pins 881, 882 Note amended 3. Fixed to the ground or connected to the same signal line as RESET, or to a signal line that behaves in the same way. However, there is a problem when this pin is fixed to the ground. TRST is pulled up in the chip so, when this pin is fixed to the ground via external connection, a minute current will flow. The size of this current is determined by the rating of the pull-up resistor . Although this current has no effect on the chip's operation, unnecessary current will be dissipated. Rev.7.00 Oct. 10, 2008 Page xxx of lxxxiv REJ09B0366-0700 Item Page Revision (See Manual for Details) Description amended The boundary scan register (SDBSR) is a shift register that is placed on the pads to control the chip's I/O pins. This register can perform a boundary scan test equivalent to the JTAG (IEEE Std 1149.1) standard using EXTEST, SAMPLE, and PRELOAD commands. Table amended No. to TDO 345 344 Pin Name CKIO2ENB MD6/IOIS16 Type IN IN 21.2.5 Boundary Scan 887 Register (SDBSR) (SH7750R Only) Table 21.3 888 Configuration of the Boundary Scan Register 890 Table amended No. Pin Name 2 CS0 1 RDY from TDI Type OUT IN 21.3.4 Boundary Scan 893 (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only) Description amended In the SH7750R, setting a command from the H-UDI in SDIR can place the H-UDI pins in the boundary scan mode . However, the following limitations apply. ... 4. With EXTEST, assert the MRESET pin (low), the RESET pin (low), and the CA pin (high). With SAMPLE/PRELOAD, assert the CA pin (high). 6. Deleted 21.4 Usage Notes 894 Description added 6. In BYPASS mode on the SH7750 or SH7750S, the contents of the bypass register (SDBPR) are undefined in the Capture-DR state. On the SH7750R, SDBPR has a value of 0. Rev.7.00 Oct. 10, 2008 Page xxxi of lxxxiv REJ09B0366-0700 Item Section 22 Electrical Characteristics Page 895 to 1016 Revision (See Manual for Details) Description of lead-free products added HD6417750RBP240 (V) HD6417750RF240 (V) HD6417750RBG240 (V) HD6417750RBP200 (V) HD6417750RF200 (V) HD6417750RBG200 (V) HD6417750SBP200 (V) HD6417750SF200 (V) HD6417750BP200M (V) HD6417750SF167 (V) HD6417750F167 (V) HD6417750SVF133 (V) HD6417750SVBF133 (V) HD6417750VF128 (V) 22.1 Absolute Maximum Ratings Table 22.1 Absolute Maximum Ratings 895 Table and notes amended Item I/O, PLL, RTC, CPG power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-RTC VDD-CPG VDD Topr Value –0.3 to 4.2, –0.3 to 4.6* Unit V Internal power supply voltage Operating temperature –0.3 to 2.5, –0.3 to 2.1* –20 to 75 V °C Notes: * HD6417750R only 22.2 DC Characteristics Table 22.2 DC Characteristics (HD6417750RBP240 (V), HD6417750RBG240 (V)) Table 22.3 DC 899 Characteristics (HD6417750RF240 (V)) 896, 897 Title and table amended Item Current dissipation Normal operation Sleep mode Output voltage All output pins VOH VOL IOH = –2 mA IOL = 2 mA Symbol IDD Test Conditions Ick = 240 MHz Table amended Item Output voltage All output pins Symbol VOH VOL Test Conditions IOH = –2 mA IOL = 2 mA Rev.7.00 Oct. 10, 2008 Page xxxii of lxxxiv REJ09B0366-0700 Item 22.2 DC Characteristics Table 22.4 DC Characteristics (HD6417750RBP200 (V), HD6417750RBG200 (V)) Page Revision (See Manual for Details) 900, 901 Title and table amended Item Output voltage All output pins Symbol VOH VOL Test Conditions IOH = –2 mA IOL = 2 mA Table 22.5 DC 903 Characteristics (HD6417750RF200 (V)) Table amended Item Output voltage All output pins Symbol VOH VOL Test Conditions IOH = –2 mA IOL = 2 mA Table 22.6 DC Characteristics (HD6417750SBP200 (V)) 904 Table amended Item Output voltage All output pins Symbol VOH VOL Test Conditions IOH = –2 mA IOL = 2 mA Table 22.7 DC 906 Characteristics (HD6417750SF200 (V)) Table amended Item Output voltage All output pins Symbol VOH VOL Test Conditions IOH = –2 mA IOL = 2 mA Table 22.8 DC Characteristics (HD6417750BP200M (V)) 908 Table amended Item Output voltage All output pins Symbol VOH VOL Test Conditions IOH = –2 mA IOL = 2 mA Table 22.9 DC 910 Characteristics (HD6417750SF167 (V)) Table amended Item Output voltage All output pins Symbol VOH VOL Test Conditions IOH = –2 mA IOL = 2 mA Table 22.10 DC — Characteristics (HD6417750SF167I (V)) Deleted Rev.7.00 Oct. 10, 2008 Page xxxiii of lxxxiv REJ09B0366-0700 Item 22.2 DC Characteristics Table 22.10 DC Characteristics (HD6417750F167 (V)) Page 912 Revision (See Manual for Details) Table amended Item Output voltage All output pins Symbol VOH VOL Test Conditions IOH = –2 mA IOL = 2 mA Table 22.12 DC — Characteristics (HD6417750F167I (V)) Table 22.11 DC Characteristics (HD6417750SVF133 (V)) 914 Deleted Table amended Item Current dissipation Output voltage Normal operation All output pins Symbol IDD VOH VOL Test Conditions Ick = 133 MHz, Bck = 67 MHz IOH = –2 mA IOL = 2 mA Table 22.12 DC Characteristics (HD6417750SVBT133 (V)) 916 Table amended Item Output voltage All output pins Symbol VOH VOL Test Conditions IOH = –2 mA IOL = 2 mA Table 22.13 DC 918 Characteristics (HD6417750VF128 (V)) Table amended Item Output voltage All output pins Symbol VOH VOL Test Conditions IOH = –2 mA IOL = 2 mA 22.3 AC Characteristics Table 22.15 Clock Timing (HD6417750RBP240 (V), HD6417750RBG240 (V)) 920 Title amended Rev.7.00 Oct. 10, 2008 Page xxxiv of lxxxiv REJ09B0366-0700 Item 22.3 AC Characteristics Table 22.17 Clock Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750RBP200 (V), HD6417750RBG200 (V)) Table 22.20 Clock Timing (HD6417750F167 (V), HD6417750SF167 (V) ) 22.3.1 Clock and Control Signal Timing Table 22.23 Clock and Control Signal Timing (HD6417750RBP240 (V), HD6417750RBG240 (V)) Page 920 Revision (See Manual for Details) Title amended 921 Title amended 922 Title amended Table 22.25 Clock and 926 Control Signal Timing (HD6417750RBP200 (V), HD6417750RBG200 (V)) Table 22.27 Clock and 930 Control Signal Timing (HD6417750BP200M (V), HD6417750SBP200 (V)) Title amended Description amended VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF Table 22.29 Clock and 934, 935 Title, description, notes amended Control Signal Timing HD6417750SF167 (V), HD6417750F167 (V): (HD6417750F167 (V), VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF HD6417750SF167 (V) ) Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. Rev.7.00 Oct. 10, 2008 Page xxxv of lxxxiv REJ09B0366-0700 Item 22.3.1 Clock and Control Signal Timing Table 22.30 Clock and Control Signal Timing (HD6417750SVF133, HD6417750SVBT133 (V)) Page Revision (See Manual for Details) 936, 937 Description and notes amended HD6417750SVBT133 (V): VDDQ = 3.0 to 3.6 V, VDD = 1.5 V , Ta = –30 to +70°C, CL = 30 pF HD6417750SVF133 (V): VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. Notes amended Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. Figure amended Bus idle CKIO tRESW RESET tSCK2RS tSCK2RH Table 22.31 Clock and 939 Control Signal Timing (HD6417750VF128) Figure 22.11 Manual Reset Input Timing 945 SCK2 22.3.2 Control Signal Timing Table 22.32 Control Signal Timing (1) 946 Table and note amended HD6417750 RBP240 (V) HD6417750 RBG240 (V) * Item Bus tri-state delay time to standby mode Bus buffer on time Bus buffer on time from standby STATUS0/1 delay time Symbol Min tBOFF2 — Max 2 Min — HD6417750 RBP200 (V) HD6417750 RBG200 (V) * Max 2 Min — HD6417750 RF240 (V) * Max 2 Min — HD6417750 RF200 (V) * Max 2 Unit Figure tcyc 22.14 (2) Notes tBON1 tBON2 — — 12 2 — — 12 2 — — 12 2 — — 12 2 ns tcyc 22.13 22.14 (2) 22.14 (1) 22.14 (1), (2) 22.14 (2) tSTD1 tSTD2 tSTD3 — — — 6 2 2 — — — 6 2 2 — — — 6 2 2 — — — 6 2 2 ns tcyc tcyc Note: * VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on Rev.7.00 Oct. 10, 2008 Page xxxvi of lxxxiv REJ09B0366-0700 1.5 V, Ta = –20 to +75°C, Item 22.3.2 Control Signal Timing Table 22.32 Control Signal Timing (2) Page 947 Revision (See Manual for Details) Table and notes amended HD6417750 F167 (V) HD6417750 SVF133 (V) HD6417750 VF128 (V) *1 Item Bus tri-state delay time to standby mode Bus buffer on time Bus buffer on time from standby STATUS0/1 delay time Symbol Min tBOFF2 — Max 2 Min — HD6417750 SVBT133 (V) *1 Max 2 Min — HD6417750 SF167 (V) HD6417750 SF200 (V) *2 Max 2 Min — HD6417750 BP200M (V) HD6417750 SBP200 (V) *3 Max 2 Unit Figure tcyc 22.14 (2) Notes tBON1 tBON2 — — 12 2 — — 12 2 — — 12 2 — — 12 2 ns tcyc 22.13 22.14 (2) 22.14 (1) 22.14 (1), (2) 22.14 (2) tSTD1 tSTD2 tSTD3 — — — 6 2 2 — — — 6 2 2 — — — 6 2 2 — — — 6 2 2 ns tcyc tcyc Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 2. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on Figure 22.14 (1) Pin Drive Timing for Reset or Sleep Mode 948 Title amended and figure replaced 1.5 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, Figure 22.14 (2) Pin 949 Drive Timing for Software Standby Mode 22.3.3 Bus Timing Table 22.33 Bus Timing (1) Figure replaced 950, 951 Table and note amended HD6417750 RBP240 (V) HD6417750 RBG240 (V) * Item Symbol Min Max Min HD6417750 RBP200 (V) HD6417750 RBG200 (V) * Max Note: * VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 1.5 V, Ta = –20 to +75°C, Rev.7.00 Oct. 10, 2008 Page xxxvii of lxxxiv REJ09B0366-0700 Item 22.3.3 Bus Timing Table 22.33 Bus Timing (2) Page Revision (See Manual for Details) 952, 953 Table and notes amended HD6417750S VF133 (V) HD6417750S VBT133 (V) *1 Item Symbol Min Max Min HD6417750S F167 (V) HD6417750S F200 (V) *2 Max Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 2. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on Table 22.33 Bus Timing (3) 954, 955 Table and notes amended 1.5 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, HD6417750 F167 (V) HD6417750 VF 128 (V) *1 Item Symbol Min Max Min *2 Max Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 2. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 1.5 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, Rev.7.00 Oct. 10, 2008 Page xxxviii of lxxxiv REJ09B0366-0700 Item 22.3.3 Bus Timing Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RASD = 1, RCD[1:0] = 01, CAS Latency = 3) Page 966 Revision (See Manual for Details) Title amended Figure 22.26 967 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst (RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, CAS Latency = 3) Figure 22.27 968 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (RASD = 1, CAS Latency = 3) Figure 22.30 971 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RASD = 1, RCD[1:0] = 01, TRWL[2:0] = 010) Figure 22.31 972 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) Title amended Title amended Title amended Title amended Rev.7.00 Oct. 10, 2008 Page xxxix of lxxxiv REJ09B0366-0700 Item 22.3.3 Bus Timing Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (RASD = 1, TRWL[2:0] = 010) Page 973 Revision (See Manual for Details) Title amended Figure 22.52 PCMCIA 994 Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait 22.3.4 Peripheral Module Signal Timing Table 22.34 Peripheral Module Signal Timing (1) 1003, 1004 Notes amended Note: *: SH7750S and SH7750R only Table amended HD6417750 RBP240 (V) HD6417750 RBG240 (V) *2 Module Item Symbol Min Max Min HD6417750 RBP200 (V) HD6417750 RBG200 (V) *2 Max Table 22.34 Peripheral 1005, Module Signal Timing 1006 (2) Table and notes amended HD6417750 SF167 (V) HD6417750S VF133 (V) HD6417750S VBT133 (V) *2 Module Item Symbol Min Max Min HD6417750 SF200 (V) *3 Max Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 4. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 1.5 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, Rev.7.00 Oct. 10, 2008 Page xl of lxxxiv REJ09B0366-0700 Item 22.3.4 Peripheral Module Signal Timing Table 22.34 Peripheral Module Signal Timing (3) Page 1007 Revision (See Manual for Details) Table and notes amended HD6417750 SF167 (V) HD6417750S VF133 (V) HD6417750S VBT133 (V) *2 Module Item Symbol Min Max Min HD6417750 SF200 (V) *3 Max Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 4. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on Table 22.34 Peripheral 1008, Module Signal Timing 1009 (4) Table and notes amended 1.5 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, HD6417750 F167 (V) HD6417750 VF128 (V) *2 Module Item Symbol Min Max Min *3 Max Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 4. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 1.5 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, Rev.7.00 Oct. 10, 2008 Page xli of lxxxiv REJ09B0366-0700 Item 22.3.4 Peripheral Module Signal Timing Table 22.34 Peripheral Module Signal Timing (5) Page 1010 Revision (See Manual for Details) Table and notes amended HD6417750 F167 (V) HD6417750 VF128 (V) *2 Module Item Symbol Min Max Min *3 Max Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on 4. VDDQ = 3.0 to 3.6 V, VDD = CL = 30 pF, PLL2 on Appendix A Address List Table A.1 Address List 1017 to 1022 Table amended Synchronization Clock lclk → lck Bclk → Bck Pclk → Pck Appendix B Package Dimensions Figure B.2 Package Dimensions (256-Pin BGA) Figure B.4 Package Dimensions (292-Pin BGA) 1026 Newly added ⎯ Package Dimensions deleted (Combined with figure B.1) 1.5 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, 1.8 V, Ta = –20 to +75°C, Rev.7.00 Oct. 10, 2008 Page xlii of lxxxiv REJ09B0366-0700 Item E.1 Pin States Table E.1 Pin States in Reset, Power-Down State, and BusReleased State Page 1033 Revision (See Manual for Details) Table and notes amended Reset (Power-On) Signal Name D0–D7 D8–D15 D16–D23 D24–D31 D32–D51 D52–D55 D56–D63 A0, A1, A18–A25 A2–A17 RESET BACK/BSREQ BREQ/BSACK BS CKE CS6–CS0 RAS RD/CASS/FRAME RD/WR RDY WE7/CAS7/DQM7 WE6/CAS6/DQM6 WE5/CAS5/DQM5 WE4/CAS4/DQM4 WE3/CAS3/DQM3 WE2/CAS2/DQM2 I/O I/O I/O I/O I/O I/O I/O I/O O O I O I O Master Z Z Z Z Z Z Z P P I H P H H H H H H PI H H H H H H Slave Z Z Z Z Z Z Z P P I H P PZ H PZ PZ PZ PZ PI PZ PZ PZ PZ PZ PZ Reset (Manual) Master Z*19 Z*19 Z*19 Z*19 Z*19K*18 Z*19 Z*19 Slave Z*19 Z*19 Z*19 Z*19 Z*19K*18 Z*19 Z*19 Standby Z*19 Z*19 Z*19 Z*19 Z*19K*18 Z*19 Z*19 Z*13O*6 Z*13O*6 I H I*12 Z*13H*6 L Z*13H*6 Z*13O*4 Z*13O*4 Z*13H*6 Z*12 Z*13O*4 Z*13O*4 Z*13O*4 Z*13O*4 Z*13O*4 Z*13O*4 Bus Hardware Released Standby Z*19 Z*19 Z*19 Z*19 Z*19K*18 Z*19 Z*19 Z*13 Z*13 I O I*12 Z*13 O Z*13 Z*13O*4 Z*13O*4 Z*13 I*12 Z*13O*4 Z*13O*4 Z*13O*4 Z*13O*4 Z*13O*4 Z*13O*4 Z Z Z Z Z Z Z Z Z I Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z*13O*15 Z*13 Z*13O*8 I H I*12 H O H O O H I*12 O O O O O O Z*13 I H I*12 Z*13 O Z*13 Z*13 Z*13 Z*13 I*12 Z*13 Z*13 Z*13 Z*13 Z*13 Z*13 O O O O O I O O O O O O Rev.7.00 Oct. 10, 2008 Page xliii of lxxxiv REJ09B0366-0700 Item E.1 Pin States Table E.1 Pin States in Reset, Power-Down State, and BusReleased State Page 1034 Revision (See Manual for Details) Reset (Power-On) Signal Name WE1/CAS1/DQM1 WE0/CAS0/DQM0 DACK1–DACK0 MD7/TXD MD6/IOIS16 MD5/RAS2I/O MD4/CE2BI/O MD3/CE2AI/O CKIO STATUS1–STATUS0 IRL3–IRL0 NMI DREQ1–DREQ0 DRAK1–DRAK0 MD0/SCK RXD SCK2/MRESET MD1/TXD2 MD2/RXD2 CTS2 MD8/RTS2 TCLK TDO TMS TCK TDI TRST CKIO2*21 I/O O O O I/O I I/O *1 I/O *3 I/O *2 O O I I I O I/O I I I/O I I/O I/O I/O O I I I I O Master H H L PI*14 PI*14 PI*14 PI*14 PI*14 O O PI PI PI L PI*14 PI PI PI*14 PI*14 PI PI*14 PI O PI PI PI PI Slave PZ PZ L PI*14 PI*14 PI*14 PI*14 PI*14 O O PI PI PI L PI*14 PI PI PI*14 PI*14 PI PI*14 PI O PI PI PI PI Reset (Manual) Master O O L Z*11 I*12 Z*13O*5 Z*13H*6 Z*13H*6 Slave Z* 13 Standby Z* O* 13 4 Bus Hardware Released Standby Z*13O*4 Z*13O*4 O Z Z Z Z*13 L Z*11 I*12 Z*13 Z*13 Z*13 Z*13O*4 Z*11O*7 Z*11K*18O*7 Z*11K*18O*7 Z Z*12 Z*13O*4 Z*13H*6 Z*13H*6 I*12 Z*13O*4 Z*13 Z*13 O*10Z*10 O I*12 I*12 I*11 O Z Z Z Z Z ZO*16 I I I Z Z Z Z Z Z Z Z Z Z Z Z Z Z O*10Z*10 O*10Z*10 PZ O I*12 I*12 I*11 L I*11 I*11 I*11 Z*11 I*11 I*11 I*11 I*11 O PI PI PI PI PZ*20 O*9 * 20 O I*12 I*12 I*11 L I*11 I*11 I*11 Z*11 I*11 I*11 I*11 I*11 O PI PI PI PI PZ*20 O*9 * 20 O I*12 I*12 Z*11 Z*11O*7 11 18 Z*11K*18O*7 I* OK* Z*11 I*11 Z*11 K*18 O*7 Z*11 Z*11K*18 Z*11K*18 K*11O*17 O PZ PZ PZ PZ PZ I*11 I*11 Z*11 K*18 O*7 I*11 I*11K*18 I*11K*18 I*11O*17 O PI PI PI PI PZ*20O*9 PZ*20O*9 PZ *20O*9 *20 Z 1035 Signal Name RD2* 21 Reset (Power-On) I/O O O I I I/O Master Z*20 20 H*9 * Z*20 20 H*9 * PI I Slave Z* PZ* 20 9 Reset (Manual) Master Z* * O*9 13 20 Slave Z* * 9 13 Standby Z* * O* 9 13 4 Bus Hardware Released Standby Z*9*13 O*4 Z*9*13 PI I PI*22O*22 Z Z Z I Z RD/WR2*21 CKIO2ENB CA ASEBRK/BRKACK Z*20PZ*9 PI I Z*13 *20 H*9 PI I I Z*9*13 PI Z*9*13 H*4 PI I PI*22O*22 PI*22O*22 PI*22O*22 PI*22O*22 PI*22O*22 Legend: I: Input (not Pulled Up) O: Output Z: High-impedance (not Pulled Up) H: High-level output L: Low-level output K: Output state held Rev.7.00 Oct. 10, 2008 Page xliv of lxxxiv REJ09B0366-0700 Item E.1 Pin States Page Revision (See Manual for Details) PI: Input (Pulled Up) PZ: High-impedance (Pulled Up) Notes: 1. Output when area 2 is used as DRAM. 2. Output when area 5 is used as PCMCIA. 3. Output when area 6 is used as PCMCIA. 4. Z (I) or O on refresh operations, depending on register setting (BCR1.HIZCNT). 5. Depends on refresh operations. 6. Z (I) or H (state held), depending on register setting (BCR1.HIZMEM). 7. Z or O, depending on register setting (STBCR.PHZ). 8. Output when refreshing is set. 9. Operation in respective state when CKIO2ENB = 0 (SH7750/SH7750S) (High-level outputs as SH7750R). 10. PZ or O, depending on register setting (FRQCR.CKOEN). 11. Pulled up or not pulled up, depending on register setting (STBCR.PPU). 12. Pulled up or not pulled up, depending on register setting (BCR1.IPUP). 13. Pulled up or not pulled up, depending on register setting (BCR1.OPUP). 14. Pulled up with a built-in pull-up resistance. However it, cannot use for fixation of an input MD pin at the time of power-on reset. Pull up or down outside this LSI. 15. Output when refreshing is set (SH7750R only). 16. Z or O, depending on register setting (STBCR2.STHZ) (SH7750R only). 17. Z or O, depending on register setting (TOCR, TCOE) 18. Output state held when used as port. 19. Pulled up or not pulled up, depending on register setting (BCR1.DPUP) (SH7750R only). 20. Z when CKIO2ENB = 1 21. BGA Package only. 22. Depends on Emulator operations. Rev.7.00 Oct. 10, 2008 Page xlv of lxxxiv REJ09B0366-0700 1035, Table E.1 Pin States in 1036 Reset, Power-Down State, and BusReleased State Item E.2 Handling of Unused Pins Page 1036 Revision (See Manual for Details) Note added Note: To prevent unwanted effects on other pins when using external pull-up or pull-down resistors, use independent pull-up or pull-down resistors for individual pins. Appendix F Synchronous DRAM Address Multiplexing Tables (17) BUS 64 (128 M: 4 M × 8 b × 4) × 8* (SH7750R only) 1053 Title amended Appendix H Power-On 1061 to and Power-Off 1063 Procedures Appendix I Product Lineup Table I.1 SH7750/ SH7750S/SH7750R Product Lineup Appendix J Version Registers 1067 1065 Replaced Table amended and note added Newly added All trademarks and registered trademarks are the property of their respective owners. Rev.7.00 Oct. 10, 2008 Page xlvi of lxxxiv REJ09B0366-0700 Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 1.4 SH7750, SH7750S, SH7750R Groups Features ............................................................... Block Diagram .................................................................................................................. Pin Arrangement ............................................................................................................... Pin Functions .................................................................................................................... 1.4.1 Pin Functions (256-Pin BGA).............................................................................. 1.4.2 Pin Functions (208-Pin QFP)............................................................................... 1.4.3 Pin Functions (264-Pin CSP) ............................................................................... 1.4.4 Pin Functions (292-Pin BGA).............................................................................. 1 1 9 10 14 14 24 32 42 Section 2 Programming Model ........................................................................................ 53 2.1 2.2 Data Formats ..................................................................................................................... Register Configuration ...................................................................................................... 2.2.1 Privileged Mode and Banks ................................................................................. 2.2.2 General Registers ................................................................................................. 2.2.3 Floating-Point Registers....................................................................................... 2.2.4 Control Registers ................................................................................................. 2.2.5 System Registers.................................................................................................. Memory-Mapped Registers............................................................................................... Data Format in Registers................................................................................................... Data Formats in Memory .................................................................................................. Processor States................................................................................................................. Processor Modes ............................................................................................................... 53 54 54 57 59 62 63 65 66 66 67 69 2.3 2.4 2.5 2.6 2.7 Section 3 Memory Management Unit (MMU) ........................................................... 71 3.1 Overview........................................................................................................................... 3.1.1 Features................................................................................................................ 3.1.2 Role of the MMU................................................................................................. 3.1.3 Register Configuration......................................................................................... 3.1.4 Caution................................................................................................................. Register Descriptions ........................................................................................................ Address Space ................................................................................................................... 3.3.1 Physical Address Space ....................................................................................... 3.3.2 External Memory Space....................................................................................... 3.3.3 Virtual Address Space.......................................................................................... 3.3.4 On-Chip RAM Space........................................................................................... 3.3.5 Address Translation ............................................................................................. 71 71 71 74 74 75 79 79 82 83 84 85 3.2 3.3 Rev.7.00 Oct. 10, 2008 Page xlvii of lxxxiv REJ09B0366-0700 3.4 3.5 3.6 3.7 3.8 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode ................... 3.3.7 Address Space Identifier (ASID) ......................................................................... TLB Functions .................................................................................................................. 3.4.1 Unified TLB (UTLB) Configuration ................................................................... 3.4.2 Instruction TLB (ITLB) Configuration................................................................ 3.4.3 Address Translation Method................................................................................ MMU Functions................................................................................................................ 3.5.1 MMU Hardware Management ............................................................................. 3.5.2 MMU Software Management .............................................................................. 3.5.3 MMU Instruction (LDTLB)................................................................................. 3.5.4 Hardware ITLB Miss Handling ........................................................................... 3.5.5 Avoiding Synonym Problems .............................................................................. MMU Exceptions.............................................................................................................. 3.6.1 Instruction TLB Multiple Hit Exception.............................................................. 3.6.2 Instruction TLB Miss Exception.......................................................................... 3.6.3 Instruction TLB Protection Violation Exception ................................................. 3.6.4 Data TLB Multiple Hit Exception ....................................................................... 3.6.5 Data TLB Miss Exception ................................................................................... 3.6.6 Data TLB Protection Violation Exception........................................................... 3.6.7 Initial Page Write Exception ................................................................................ Memory-Mapped TLB Configuration............................................................................... 3.7.1 ITLB Address Array ............................................................................................ 3.7.2 ITLB Data Array 1............................................................................................... 3.7.3 ITLB Data Array 2............................................................................................... 3.7.4 UTLB Address Array........................................................................................... 3.7.5 UTLB Data Array 1 ............................................................................................. 3.7.6 UTLB Data Array 2 ............................................................................................. Usage Notes ...................................................................................................................... 85 85 86 86 90 90 93 93 93 93 94 95 96 96 96 98 98 99 100 101 102 103 104 105 106 107 108 109 Section 4 Caches .................................................................................................................. 111 4.1 Overview........................................................................................................................... 4.1.1 Features................................................................................................................ 4.1.2 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ Operand Cache (OC)......................................................................................................... 4.3.1 Configuration ....................................................................................................... 4.3.2 Read Operation .................................................................................................... 4.3.3 Write Operation ................................................................................................... 4.3.4 Write-Back Buffer ............................................................................................... 4.3.5 Write-Through Buffer.......................................................................................... 111 111 113 114 116 116 120 121 122 122 4.2 4.3 Rev.7.00 Oct. 10, 2008 Page xlviii of lxxxiv REJ09B0366-0700 4.4 4.5 4.6 4.7 4.3.6 RAM Mode .......................................................................................................... 4.3.7 OC Index Mode.................................................................................................... 4.3.8 Coherency between Cache and External Memory ............................................... 4.3.9 Prefetch Operation ............................................................................................... 4.3.10 Notes on Using Cache Enhanced Mode (SH7750R Only)................................... Instruction Cache (IC)....................................................................................................... 4.4.1 Configuration ....................................................................................................... 4.4.2 Read Operation .................................................................................................... 4.4.3 IC Index Mode ..................................................................................................... Memory-Mapped Cache Configuration (SH7750, SH7750S) .......................................... 4.5.1 IC Address Array ................................................................................................. 4.5.2 IC Data Array....................................................................................................... 4.5.3 OC Address Array................................................................................................ 4.5.4 OC Data Array ..................................................................................................... Memory-Mapped Cache Configuration (SH7750R) ......................................................... 4.6.1 IC Address Array ................................................................................................. 4.6.2 IC Data Array....................................................................................................... 4.6.3 OC Address Array................................................................................................ 4.6.4 OC Data Array ..................................................................................................... 4.6.5 Summary of the Memory-Mapping of the OC..................................................... Store Queues ..................................................................................................................... 4.7.1 SQ Configuration ................................................................................................. 4.7.2 SQ Writes............................................................................................................. 4.7.3 Transfer to External Memory............................................................................... 4.7.4 SQ Protection ....................................................................................................... 4.7.5 Reading the SQs (SH7750R Only) ...................................................................... 4.7.6 SQ Usage Notes ................................................................................................... 123 124 125 125 125 128 128 130 131 131 131 132 133 135 136 137 138 139 141 142 142 142 143 143 145 145 146 Section 5 Exceptions........................................................................................................... 149 5.1 Overview........................................................................................................................... 5.1.1 Features................................................................................................................ 5.1.2 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ Exception Handling Functions .......................................................................................... 5.3.1 Exception Handling Flow .................................................................................... 5.3.2 Exception Handling Vector Addresses ................................................................ Exception Types and Priorities ......................................................................................... Exception Flow ................................................................................................................. 5.5.1 Exception Flow .................................................................................................... 5.5.2 Exception Source Acceptance.............................................................................. 149 149 149 150 151 151 151 152 155 155 156 5.2 5.3 5.4 5.5 Rev.7.00 Oct. 10, 2008 Page xlix of lxxxiv REJ09B0366-0700 5.6 5.7 5.8 5.5.3 Exception Requests and BL Bit ........................................................................... 5.5.4 Return from Exception Handling......................................................................... Description of Exceptions................................................................................................. 5.6.1 Resets................................................................................................................... 5.6.2 General Exceptions .............................................................................................. 5.6.3 Interrupts.............................................................................................................. 5.6.4 Priority Order with Multiple Exceptions.............................................................. Usage Notes ...................................................................................................................... Restrictions ....................................................................................................................... 158 158 158 159 164 178 181 182 183 Section 6 Floating-Point Unit (FPU) ............................................................................. 185 6.1 6.2 Overview........................................................................................................................... Data Formats..................................................................................................................... 6.2.1 Floating-Point Format.......................................................................................... 6.2.2 Non-Numbers (NaN) ........................................................................................... 6.2.3 Denormalized Numbers ....................................................................................... Registers............................................................................................................................ 6.3.1 Floating-Point Registers....................................................................................... 6.3.2 Floating-Point Status/Control Register (FPSCR)................................................. 6.3.3 Floating-Point Communication Register (FPUL) ................................................ Rounding........................................................................................................................... Floating-Point Exceptions................................................................................................. Graphics Support Functions.............................................................................................. 6.6.1 Geometric Operation Instructions........................................................................ 6.6.2 Pair Single-Precision Data Transfer..................................................................... Usage Notes ...................................................................................................................... 6.7.1 Rounding Mode and Underflow Flag .................................................................. 6.7.2 Setting of Overflow Flag by FIPR or FTRV Instruction ..................................... 6.7.3 Sign of Operation Result when Using FIPR or FTRV Instruction....................... 6.7.4 Notes on Double-Precision FADD and FSUB Instructions ................................. 6.7.5 Notes on FPU Double-Precision Operation Instructions (SH7750 Only)............ 185 185 185 187 188 189 189 191 192 193 193 195 195 196 197 197 198 199 199 200 6.3 6.4 6.5 6.6 6.7 Section 7 Instruction Set .................................................................................................... 209 7.1 7.2 7.3 7.4 Execution Environment..................................................................................................... Addressing Modes ............................................................................................................ Instruction Set ................................................................................................................... Usage Notes ...................................................................................................................... 7.4.1 Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction (H'FFFD).............................................................................................................. 209 211 215 227 227 Rev.7.00 Oct. 10, 2008 Page l of lxxxiv REJ09B0366-0700 Section 8 Pipelining ............................................................................................................ 231 8.1 8.2 8.3 8.4 Pipelines............................................................................................................................ Parallel-Executability........................................................................................................ Execution Cycles and Pipeline Stalling ............................................................................ Usage Notes ...................................................................................................................... 231 238 242 258 Section 9 Power-Down Modes ........................................................................................ 259 9.1 Overview........................................................................................................................... 9.1.1 Types of Power-Down Modes ............................................................................. 9.1.2 Register Configuration......................................................................................... 9.1.3 Pin Configuration................................................................................................. Register Descriptions ........................................................................................................ 9.2.1 Standby Control Register (STBCR)..................................................................... 9.2.2 Peripheral Module Pin High Impedance Control ................................................. 9.2.3 Peripheral Module Pin Pull-Up Control............................................................... 9.2.4 Standby Control Register 2 (STBCR2)................................................................ 9.2.5 Clock-Stop Register 00 (CLKSTP00) (SH7750R Only) ..................................... 9.2.6 Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only) .................... Sleep Mode ....................................................................................................................... 9.3.1 Transition to Sleep Mode..................................................................................... 9.3.2 Exit from Sleep Mode .......................................................................................... Deep Sleep Mode .............................................................................................................. 9.4.1 Transition to Deep Sleep Mode............................................................................ 9.4.2 Exit from Deep Sleep Mode................................................................................. Standby Mode ................................................................................................................... 9.5.1 Transition to Standby Mode................................................................................. 9.5.2 Exit from Standby Mode...................................................................................... 9.5.3 Clock Pause Function .......................................................................................... Module Standby Function ................................................................................................. 9.6.1 Transition to Module Standby Function .............................................................. 9.6.2 Exit from Module Standby Function.................................................................... Hardware Standby Mode (SH7750S, SH7750R Only) ..................................................... 9.7.1 Transition to Hardware Standby Mode ................................................................ 9.7.2 Exit from Hardware Standby Mode ..................................................................... 9.7.3 Usage Notes ......................................................................................................... STATUS Pin Change Timing ........................................................................................... 9.8.1 In Reset ................................................................................................................ 9.8.2 In Exit from Standby Mode ................................................................................. 9.8.3 In Exit from Sleep Mode...................................................................................... 9.8.4 In Exit from Deep Sleep Mode ............................................................................ 259 259 261 261 262 262 264 265 265 267 268 268 268 269 269 269 269 270 270 271 271 272 272 273 274 274 274 275 275 276 277 279 281 9.2 9.3 9.4 9.5 9.6 9.7 9.8 Rev.7.00 Oct. 10, 2008 Page li of lxxxiv REJ09B0366-0700 9.9 9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only) ........................... 283 Usage Notes ...................................................................................................................... 286 9.9.1 Note on Current Consumption ............................................................................. 286 Section 10 Clock Oscillation Circuits ........................................................................... 287 10.1 Overview........................................................................................................................... 10.1.1 Features................................................................................................................ 10.2 Overview of CPG.............................................................................................................. 10.2.1 Block Diagram of CPG........................................................................................ 10.2.2 CPG Pin Configuration ........................................................................................ 10.2.3 CPG Register Configuration ................................................................................ 10.3 Clock Operating Modes .................................................................................................... 10.4 CPG Register Description................................................................................................. 10.4.1 Frequency Control Register (FRQCR)................................................................. 10.5 Changing the Frequency ................................................................................................... 10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off) ........... 10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)............ 10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On) ...................... 10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off) ..................... 10.5.5 Changing CPU or Peripheral Module Clock Division Ratio ............................... 10.6 Output Clock Control........................................................................................................ 10.7 Overview of Watchdog Timer .......................................................................................... 10.7.1 Block Diagram..................................................................................................... 10.7.2 Register Configuration......................................................................................... 10.8 WDT Register Descriptions .............................................................................................. 10.8.1 Watchdog Timer Counter (WTCNT)................................................................... 10.8.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 10.8.3 Notes on Register Access..................................................................................... 10.9 Using the WDT ................................................................................................................. 10.9.1 Standby Clearing Procedure ................................................................................ 10.9.2 Frequency Changing Procedure ........................................................................... 10.9.3 Using Watchdog Timer Mode.............................................................................. 10.9.4 Using Interval Timer Mode ................................................................................. 10.10 Notes on Board Design ..................................................................................................... 10.11 Usage Notes ...................................................................................................................... 10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7750 and SH7750S).. 287 287 289 289 292 292 293 295 295 298 298 298 299 299 299 299 300 300 301 301 301 302 305 305 305 306 306 307 307 309 309 Section 11 Realtime Clock (RTC) .................................................................................. 311 11.1 Overview........................................................................................................................... 311 11.1.1 Features................................................................................................................ 311 Rev.7.00 Oct. 10, 2008 Page lii of lxxxiv REJ09B0366-0700 11.2 11.3 11.4 11.5 11.1.2 Block Diagram ..................................................................................................... 11.1.3 Pin Configuration................................................................................................. 11.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 11.2.1 64 Hz Counter (R64CNT).................................................................................... 11.2.2 Second Counter (RSECCNT) .............................................................................. 11.2.3 Minute Counter (RMINCNT) .............................................................................. 11.2.4 Hour Counter (RHRCNT).................................................................................... 11.2.5 Day-of-Week Counter (RWKCNT)..................................................................... 11.2.6 Day Counter (RDAYCNT) .................................................................................. 11.2.7 Month Counter (RMONCNT) ............................................................................. 11.2.8 Year Counter (RYRCNT) .................................................................................... 11.2.9 Second Alarm Register (RSECAR) ..................................................................... 11.2.10 Minute Alarm Register (RMINAR) ..................................................................... 11.2.11 Hour Alarm Register (RHRAR)........................................................................... 11.2.12 Day-of-Week Alarm Register (RWKAR)............................................................ 11.2.13 Day Alarm Register (RDAYAR) ......................................................................... 11.2.14 Month Alarm Register (RMONAR) .................................................................... 11.2.15 RTC Control Register 1 (RCR1).......................................................................... 11.2.16 RTC Control Register 2 (RCR2).......................................................................... 11.2.17 RTC Control Register 3 (RCR3) and Year-Alarm Register (RYRAR) (SH7750R Only) .................................................................................................. Operation........................................................................................................................... 11.3.1 Time Setting Procedures ...................................................................................... 11.3.2 Time Reading Procedures .................................................................................... 11.3.3 Alarm Function .................................................................................................... Interrupts ........................................................................................................................... Usage Notes ...................................................................................................................... 11.5.1 Register Initialization........................................................................................... 11.5.2 Carry Flag and Interrupt Flag in Standby Mode .................................................. 11.5.3 Crystal Oscillator Circuit ..................................................................................... 11.5.4 RTC Register Settings (SH7750 only)................................................................. 312 313 313 315 315 316 316 317 317 318 318 319 320 320 321 321 322 323 323 325 327 329 329 330 332 333 333 333 333 333 334 Section 12 Timer Unit (TMU) ......................................................................................... 337 12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram ..................................................................................................... 12.1.3 Pin Configuration................................................................................................. 12.1.4 Register Configuration......................................................................................... 12.2 Register Descriptions ........................................................................................................ 337 337 338 338 339 341 Rev.7.00 Oct. 10, 2008 Page liii of lxxxiv REJ09B0366-0700 12.2.1 Timer Output Control Register (TOCR) .............................................................. 12.2.2 Timer Start Register (TSTR) ............................................................................... 12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only) .............................................. 12.2.4 Timer Constant Registers (TCOR) ...................................................................... 12.2.5 Timer Counters (TCNT) ...................................................................................... 12.2.6 Timer Control Registers (TCR) ........................................................................... 12.2.7 Input Capture Register 2 (TCPR2)....................................................................... 12.3 Operation .......................................................................................................................... 12.3.1 Counter Operation................................................................................................ 12.3.2 Input Capture Function ........................................................................................ 12.4 Interrupts........................................................................................................................... 12.5 Usage Notes ...................................................................................................................... 12.5.1 Register Writes .................................................................................................... 12.5.2 Underflow Flag Writes (SH7750 only)................................................................ 12.5.3 TCNT Register Reads .......................................................................................... 12.5.4 Resetting the RTC Frequency Divider................................................................. 12.5.5 External Clock Frequency.................................................................................... 341 342 343 344 344 345 350 350 350 353 355 355 355 356 356 356 356 357 357 357 359 360 364 365 368 372 372 381 383 384 388 391 399 401 409 413 415 418 419 Section 13 Bus State Controller (BSC) ......................................................................... 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram..................................................................................................... 13.1.3 Pin Configuration................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.1.5 Overview of Areas ............................................................................................... 13.1.6 PCMCIA Support ................................................................................................ 13.2 Register Descriptions ........................................................................................................ 13.2.1 Bus Control Register 1 (BCR1) ........................................................................... 13.2.2 Bus Control Register 2 (BCR2) ........................................................................... 13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only) ............................................... 13.2.4 Bus Control Register 4 (BCR4) (SH7750R Only) ............................................... 13.2.5 Wait Control Register 1 (WCR1)......................................................................... 13.2.6 Wait Control Register 2 (WCR2)......................................................................... 13.2.7 Wait Control Register 3 (WCR3)......................................................................... 13.2.8 Memory Control Register (MCR)........................................................................ 13.2.9 PCMCIA Control Register (PCR)........................................................................ 13.2.10 Synchronous DRAM Mode Register (SDMR) .................................................... 13.2.11 Refresh Timer Control/Status Register (RTCSR)................................................ 13.2.12 Refresh Timer Counter (RTCNT)........................................................................ 13.2.13 Refresh Time Constant Register (RTCOR) ......................................................... Rev.7.00 Oct. 10, 2008 Page liv of lxxxiv REJ09B0366-0700 13.2.14 Refresh Count Register (RFCR) .......................................................................... 13.2.15 Notes on Accessing Refresh Control Registers.................................................... 13.3 Operation........................................................................................................................... 13.3.1 Endian/Access Size and Data Alignment............................................................. 13.3.2 Areas .................................................................................................................... 13.3.3 SRAM Interface ................................................................................................... 13.3.4 DRAM Interface .................................................................................................. 13.3.5 Synchronous DRAM Interface............................................................................. 13.3.6 Burst ROM Interface............................................................................................ 13.3.7 PCMCIA Interface ............................................................................................... 13.3.8 MPX Interface...................................................................................................... 13.3.9 Byte Control SRAM Interface ............................................................................. 13.3.10 Waits between Access Cycles.............................................................................. 13.3.11 Bus Arbitration..................................................................................................... 13.3.12 Master Mode ........................................................................................................ 13.3.13 Slave Mode .......................................................................................................... 13.3.14 Partial-Sharing Master Mode ............................................................................... 13.3.15 Cooperation between Master and Slave ............................................................... 13.3.16 Notes on Usage .................................................................................................... 420 420 421 421 433 438 447 465 497 500 511 529 534 536 539 540 541 542 543 Section 14 Direct Memory Access Controller (DMAC) .......................................... 545 14.1 Overview........................................................................................................................... 14.1.1 Features................................................................................................................ 14.1.2 Block Diagram (SH7750, SH7750S) ................................................................... 14.1.3 Pin Configuration (SH7750, SH7750S) ............................................................... 14.1.4 Register Configuration (SH7750, SH7750S) ....................................................... 14.2 Register Descriptions (SH7750, SH7750S) ...................................................................... 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......................... 14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 14.2.5 DMA Operation Register (DMAOR)................................................................... 14.3 Operation........................................................................................................................... 14.3.1 DMA Transfer Procedure..................................................................................... 14.3.2 DMA Transfer Requests ...................................................................................... 14.3.3 Channel Priorities................................................................................................. 14.3.4 Types of DMA Transfer....................................................................................... 14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 14.3.6 Ending DMA Transfer ......................................................................................... 14.4 Examples of Use ............................................................................................................... 545 545 547 549 550 552 552 553 554 555 564 567 567 569 573 576 585 599 602 Rev.7.00 Oct. 10, 2008 Page lv of lxxxiv REJ09B0366-0700 14.5 14.6 14.7 14.8 14.9 14.4.1 Examples of Transfer between External Memory and an External Device with DACK .................................................................................................................. On-Demand Data Transfer Mode (DDT Mode)................................................................ 14.5.1 Operation ............................................................................................................. 14.5.2 Pins in DDT Mode............................................................................................... 14.5.3 Transfer Request Acceptance on Each Channel .................................................. 14.5.4 Notes on Use of DDT Module ............................................................................. Configuration of the DMAC (SH7750R).......................................................................... 14.6.1 Block Diagram of the DMAC.............................................................................. 14.6.2 Pin Configuration (SH7750R) ............................................................................. 14.6.3 Register Configuration (SH7750R) ..................................................................... Register Descriptions (SH7750R)..................................................................................... 14.7.1 DMA Source Address Registers 0–7 (SAR0–SAR7) .......................................... 14.7.2 DMA Destination Address Registers 0–7 (DAR0–DAR7).................................. 14.7.3 DMA Transfer Count Registers 0–7 (DMATCR0–DMATCR7)......................... 14.7.4 DMA Channel Control Registers 0–7 (CHCR0–CHCR7)................................... 14.7.5 DMA Operation Register (DMAOR) .................................................................. Operation (SH7750R) ....................................................................................................... 14.8.1 Channel Specification for a Normal DMA Transfer............................................ 14.8.2 Channel Specification for DDT-Mode DMA Transfer ........................................ 14.8.3 Transfer Channel Notification in DDT Mode ...................................................... 14.8.4 Clearing Request Queues by DTR Format........................................................... 14.8.5 Interrupt-Request Codes ...................................................................................... Usage Notes ...................................................................................................................... 602 603 603 605 608 631 634 634 636 637 640 640 640 641 641 645 647 647 647 648 649 649 652 655 655 655 657 658 658 659 659 660 660 661 661 664 667 671 Section 15 Serial Communication Interface (SCI) .................................................... 15.1 Overview........................................................................................................................... 15.1.1 Features................................................................................................................ 15.1.2 Block Diagram..................................................................................................... 15.1.3 Pin Configuration................................................................................................. 15.1.4 Register Configuration......................................................................................... 15.2 Register Descriptions ........................................................................................................ 15.2.1 Receive Shift Register (SCRSR1)........................................................................ 15.2.2 Receive Data Register (SCRDR1) ....................................................................... 15.2.3 Transmit Shift Register (SCTSR1) ...................................................................... 15.2.4 Transmit Data Register (SCTDR1)...................................................................... 15.2.5 Serial Mode Register (SCSMR1)......................................................................... 15.2.6 Serial Control Register (SCSCR1)....................................................................... 15.2.7 Serial Status Register (SCSSR1).......................................................................... 15.2.8 Serial Port Register (SCSPTR1) .......................................................................... Rev.7.00 Oct. 10, 2008 Page lvi of lxxxiv REJ09B0366-0700 15.2.9 Bit Rate Register (SCBRR1)................................................................................ 15.3 Operation........................................................................................................................... 15.3.1 Overview.............................................................................................................. 15.3.2 Operation in Asynchronous Mode ....................................................................... 15.3.3 Multiprocessor Communication Function............................................................ 15.3.4 Operation in Synchronous Mode ......................................................................... 15.4 SCI Interrupt Sources and DMAC .................................................................................... 15.5 Usage Notes ...................................................................................................................... 676 684 684 686 698 707 717 718 725 725 725 727 728 729 729 729 730 730 731 731 734 737 744 745 749 750 756 757 757 758 769 770 775 775 775 776 777 777 Section 16 Serial Communication Interface with FIFO (SCIF)............................. 16.1 Overview........................................................................................................................... 16.1.1 Features................................................................................................................ 16.1.2 Block Diagram ..................................................................................................... 16.1.3 Pin Configuration................................................................................................. 16.1.4 Register Configuration......................................................................................... 16.2 Register Descriptions ........................................................................................................ 16.2.1 Receive Shift Register (SCRSR2)........................................................................ 16.2.2 Receive FIFO Data Register (SCFRDR2) ........................................................... 16.2.3 Transmit Shift Register (SCTSR2) ...................................................................... 16.2.4 Transmit FIFO Data Register (SCFTDR2) .......................................................... 16.2.5 Serial Mode Register (SCSMR2)......................................................................... 16.2.6 Serial Control Register (SCSCR2)....................................................................... 16.2.7 Serial Status Register (SCFSR2).......................................................................... 16.2.8 Bit Rate Register (SCBRR2)................................................................................ 16.2.9 FIFO Control Register (SCFCR2) ....................................................................... 16.2.10 FIFO Data Count Register (SCFDR2) ................................................................. 16.2.11 Serial Port Register (SCSPTR2) .......................................................................... 16.2.12 Line Status Register (SCLSR2) ........................................................................... 16.3 Operation........................................................................................................................... 16.3.1 Overview.............................................................................................................. 16.3.2 Serial Operation ................................................................................................... 16.4 SCIF Interrupt Sources and the DMAC ............................................................................ 16.5 Usage Notes ...................................................................................................................... Section 17 Smart Card Interface ..................................................................................... 17.1 Overview........................................................................................................................... 17.1.1 Features................................................................................................................ 17.1.2 Block Diagram ..................................................................................................... 17.1.3 Pin Configuration................................................................................................. 17.1.4 Register Configuration......................................................................................... Rev.7.00 Oct. 10, 2008 Page lvii of lxxxiv REJ09B0366-0700 17.2 Register Descriptions ........................................................................................................ 17.2.1 Smart Card Mode Register (SCSCMR1) ............................................................. 17.2.2 Serial Mode Register (SCSMR1)......................................................................... 17.2.3 Serial Control Register (SCSCR1)....................................................................... 17.2.4 Serial Status Register (SCSSR1).......................................................................... 17.3 Operation .......................................................................................................................... 17.3.1 Overview.............................................................................................................. 17.3.2 Pin Connections ................................................................................................... 17.3.3 Data Format ......................................................................................................... 17.3.4 Register Settings .................................................................................................. 17.3.5 Clock.................................................................................................................... 17.3.6 Data Transmit/Receive Operations ...................................................................... 17.4 Usage Notes ...................................................................................................................... 778 778 779 780 781 782 782 783 784 785 787 790 797 803 803 803 804 811 813 814 814 815 816 817 818 819 821 Section 18 I/O Ports ............................................................................................................ 18.1 Overview........................................................................................................................... 18.1.1 Features................................................................................................................ 18.1.2 Block Diagrams ................................................................................................... 18.1.3 Pin Configuration................................................................................................. 18.1.4 Register Configuration......................................................................................... 18.2 Register Descriptions ........................................................................................................ 18.2.1 Port Control Register A (PCTRA) ....................................................................... 18.2.2 Port Data Register A (PDTRA) ........................................................................... 18.2.3 Port Control Register B (PCTRB) ....................................................................... 18.2.4 Port Data Register B (PDTRB)............................................................................ 18.2.5 GPIO Interrupt Control Register (GPIOIC)......................................................... 18.2.6 Serial Port Register (SCSPTR1) .......................................................................... 18.2.7 Serial Port Register (SCSPTR2) .......................................................................... 19.1 Overview........................................................................................................................... 19.1.1 Features................................................................................................................ 19.1.2 Block Diagram..................................................................................................... 19.1.3 Pin Configuration................................................................................................. 19.1.4 Register Configuration......................................................................................... 19.2 Interrupt Sources............................................................................................................... 19.2.1 NMI Interrupt....................................................................................................... 19.2.2 IRL Interrupts ...................................................................................................... 19.2.3 On-Chip Peripheral Module Interrupts ................................................................ 19.2.4 Interrupt Exception Handling and Priority........................................................... Rev.7.00 Oct. 10, 2008 Page lviii of lxxxiv REJ09B0366-0700 Section 19 Interrupt Controller (INTC) ........................................................................ 825 825 825 825 827 827 828 828 829 831 832 19.3 Register Descriptions ........................................................................................................ 19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) ............................................... 19.3.2 Interrupt Control Register (ICR).......................................................................... 19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)........ 19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only).............................. 19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only) ............................... 19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only) .............. 19.3.7 Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only) .................................................................................................. 19.4 INTC Operation ................................................................................................................ 19.4.1 Interrupt Operation Sequence .............................................................................. 19.4.2 Multiple Interrupts ............................................................................................... 19.4.3 Interrupt Masking with MAI Bit .......................................................................... 19.5 Interrupt Response Time ................................................................................................... 19.6 Usage Notes ...................................................................................................................... 19.6.1 NMI Interrupts (SH7750 and SH7750S Only)..................................................... 835 835 837 839 840 841 842 842 843 843 845 845 846 847 847 851 851 851 852 854 854 855 856 856 857 859 859 859 859 860 861 861 864 864 864 865 866 867 Section 20 User Break Controller (UBC) ..................................................................... 20.1 Overview........................................................................................................................... 20.1.1 Features................................................................................................................ 20.1.2 Block Diagram ..................................................................................................... 20.2 Register Descriptions ........................................................................................................ 20.2.1 Access to UBC Control Registers ........................................................................ 20.2.2 Break Address Register A (BARA) ..................................................................... 20.2.3 Break ASID Register A (BASRA)....................................................................... 20.2.4 Break Address Mask Register A (BAMRA)........................................................ 20.2.5 Break Bus Cycle Register A (BBRA).................................................................. 20.2.6 Break Address Register B (BARB)...................................................................... 20.2.7 Break ASID Register B (BASRB) ....................................................................... 20.2.8 Break Address Mask Register B (BAMRB) ........................................................ 20.2.9 Break Data Register B (BDRB) ........................................................................... 20.2.10 Break Data Mask Register B (BDMRB).............................................................. 20.2.11 Break Bus Cycle Register B (BBRB) .................................................................. 20.2.12 Break Control Register (BRCR) .......................................................................... 20.3 Operation........................................................................................................................... 20.3.1 Explanation of Terms Relating to Accesses......................................................... 20.3.2 Explanation of Terms Relating to Instruction Intervals ....................................... 20.3.3 User Break Operation Sequence .......................................................................... 20.3.4 Instruction Access Cycle Break ........................................................................... 20.3.5 Operand Access Cycle Break............................................................................... Rev.7.00 Oct. 10, 2008 Page lix of lxxxiv REJ09B0366-0700 20.3.6 Condition Match Flag Setting .............................................................................. 20.3.7 Program Counter (PC) Value Saved .................................................................... 20.3.8 Contiguous A and B Settings for Sequential Conditions ..................................... 20.3.9 Usage Notes ......................................................................................................... 20.4 User Break Debug Support Function ................................................................................ 20.5 Examples of Use ............................................................................................................... 20.6 User Break Controller Stop Function................................................................................ 20.6.1 Transition to User Break Controller Stopped State.............................................. 20.6.2 Cancelling the User Break Controller Stopped State ........................................... 20.6.3 Examples of Stopping and Restarting the User Break Controller........................ 868 868 869 870 872 874 876 876 876 877 879 879 879 879 881 882 883 883 885 885 886 887 891 891 892 892 893 893 Section 21 High-performance User Debug Interface (H-UDI) .............................. 21.1 Overview........................................................................................................................... 21.1.1 Features................................................................................................................ 21.1.2 Block Diagram..................................................................................................... 21.1.3 Pin Configuration................................................................................................. 21.1.4 Register Configuration......................................................................................... 21.2 Register Descriptions ........................................................................................................ 21.2.1 Instruction Register (SDIR) ................................................................................. 21.2.2 Data Register (SDDR) ......................................................................................... 21.2.3 Bypass Register (SDBPR) ................................................................................... 21.2.4 Interrupt Source Register (SDINT) (SH7750R Only).......................................... 21.2.5 Boundary Scan Register (SDBSR) (SH7750R Only) .......................................... 21.3 Operation .......................................................................................................................... 21.3.1 TAP Control......................................................................................................... 21.3.2 H-UDI Reset ........................................................................................................ 21.3.3 H-UDI Interrupt ................................................................................................... 21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only) .................................................................................................. 21.4 Usage Notes ...................................................................................................................... Section 22 Electrical Characteristics ............................................................................. 895 22.1 Absolute Maximum Ratings ............................................................................................. 895 22.2 DC Characteristics ............................................................................................................ 896 22.3 AC Characteristics ............................................................................................................ 920 22.3.1 Clock and Control Signal Timing ........................................................................ 922 22.3.2 Control Signal Timing ......................................................................................... 946 22.3.3 Bus Timing .......................................................................................................... 950 22.3.4 Peripheral Module Signal Timing...................................................................... 1003 22.3.5 AC Characteristic Test Conditions .................................................................... 1015 Rev.7.00 Oct. 10, 2008 Page lx of lxxxiv REJ09B0366-0700 22.3.6 Delay Time Variation Due to Load Capacitance ............................................... 1016 Appendix A Address List ................................................................................................ 1017 Appendix B Package Dimensions................................................................................. 1023 Appendix C Mode Pin Settings ..................................................................................... 1027 Appendix D CKIO2ENB Pin Configuration ............................................................. 1031 Appendix E Pin Functions .............................................................................................. 1033 E.1 E.2 Pin States......................................................................................................................... 1033 Handling of Unused Pins ................................................................................................ 1036 Appendix F Synchronous DRAM Address Multiplexing Tables....................... 1037 Appendix G Prefetching of Instructions and its Side Effects ............................... 1059 Appendix H Power-On and Power-Off Procedures................................................. 1061 H.1 H.2 H.3 Power-On Stipulations .................................................................................................... 1061 Power-Off Stipulations ................................................................................................... 1061 Common Stipulations for Power-On and Power-Off ...................................................... 1062 Appendix I Product Lineup............................................................................................. 1065 Appendix J Version Registers ........................................................................................ 1067 Index ........................................................................................................................... 1069 Rev.7.00 Oct. 10, 2008 Page lxi of lxxxiv REJ09B0366-0700 Rev.7.00 Oct. 10, 2008 Page lxii of lxxxiv REJ09B0366-0700 Figures Section 1 Overview Figure 1.1 Block Diagram of SH7750/SH7750S/SH7750R Group Functions ........................ Figure 1.2 Pin Arrangement (256-Pin BGA)........................................................................... Figure 1.3 Pin Arrangement (208-Pin QFP) ............................................................................ Figure 1.4 Pin Arrangement (264-Pin CSP) ............................................................................ Figure 1.5 Pin Arrangement (292-Pin BGA)........................................................................... 9 10 11 12 13 Section 2 Programming Model Figure 2.1 Data Formats .......................................................................................................... 53 Figure 2.2 CPU Register Configuration in Each Processor Mode........................................... 56 Figure 2.3 General Registers ................................................................................................... 58 Figure 2.4 Floating-Point Registers ......................................................................................... 61 Figure 2.5 Data Formats In Memory ....................................................................................... 67 Figure 2.6 Processor State Transitions .................................................................................... 68 Section 3 Memory Management Unit (MMU) Figure 3.1 Role of the MMU ................................................................................................... Figure 3.2 MMU-Related Registers......................................................................................... Figure 3.3 Physical Address Space (MMUCR.AT = 0) .......................................................... Figure 3.4 P4 Area................................................................................................................... Figure 3.5 External Memory Space ......................................................................................... Figure 3.6 Virtual Address Space (MMUCR.AT = 1)............................................................. Figure 3.7 UTLB Configuration .............................................................................................. Figure 3.8 Relationship between Page Size and Address Format............................................ Figure 3.9 ITLB Configuration................................................................................................ Figure 3.10 Flowchart of Memory Access Using UTLB........................................................... Figure 3.11 Flowchart of Memory Access Using ITLB ............................................................ Figure 3.12 Operation of LDTLB Instruction............................................................................ Figure 3.13 Memory-Mapped ITLB Address Array.................................................................. Figure 3.14 Memory-Mapped ITLB Data Array 1 .................................................................... Figure 3.15 Memory-Mapped ITLB Data Array 2 .................................................................... Figure 3.16 Memory-Mapped UTLB Address Array ................................................................ Figure 3.17 Memory-Mapped UTLB Data Array 1................................................................... Figure 3.18 Memory-Mapped UTLB Data Array 2................................................................... 73 75 79 81 82 83 86 87 90 91 92 94 103 104 105 107 108 109 Section 4 Caches Figure 4.1 Cache and Store Queue Control Registers ............................................................. 114 Rev.7.00 Oct. 10, 2008 Page lxiii of lxxxiv REJ09B0366-0700 Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 Figure 4.6 Figure 4.7 Figure 4.8 Figure 4.9 Figure 4.10 Figure 4.11 Figure 4.12 Figure 4.13 Figure 4.14 Figure 4.15 Figure 4.16 Configuration of Operand Cache (SH7750, SH7750S).......................................... Configuration of Operand Cache (SH7750R) ........................................................ Configuration of Write-Back Buffer ...................................................................... Configuration of Write-Through Buffer................................................................. Configuration of Instruction Cache (SH7750, SH7750S) ...................................... Configuration of Instruction Cache (SH7750R)..................................................... Memory-Mapped IC Address Array ...................................................................... Memory-Mapped IC Data Array ............................................................................ Memory-Mapped OC Address Array..................................................................... Memory-Mapped OC Data Array .......................................................................... Memory-Mapped IC Address Array ...................................................................... Memory-Mapped IC Data Array ............................................................................ Memory-Mapped OC Address Array..................................................................... Memory-Mapped OC Data Array .......................................................................... Store Queue Configuration..................................................................................... 117 118 122 122 128 129 132 133 135 136 138 139 140 141 143 Section 5 Exceptions Figure 5.1 Register Bit Configurations.................................................................................... 150 Figure 5.2 Instruction Execution and Exception Handling...................................................... 155 Figure 5.3 Example of General Exception Acceptance Order................................................. 157 Section 6 Floating-Point Unit (FPU) Figure 6.1 Format of Single-Precision Floating-Point Number............................................... Figure 6.2 Format of Double-Precision Floating-Point Number ............................................. Figure 6.3 Single-Precision NaN Bit Pattern........................................................................... Figure 6.4 Floating-Point Registers......................................................................................... 185 186 188 190 Section 8 Pipelining Figure 8.1 Basic Pipelines ....................................................................................................... 232 Figure 8.2 Instruction Execution Patterns................................................................................ 233 Figure 8.3 Examples of Pipelined Execution........................................................................... 245 Section 9 Power-Down Modes Figure 9.1 STATUS Output in Power-On Reset ..................................................................... Figure 9.2 STATUS Output in Manual Reset.......................................................................... Figure 9.3 STATUS Output in Standby → Interrupt Sequence............................................... Figure 9.4 STATUS Output in Standby → Power-On Reset Sequence .................................. Figure 9.5 STATUS Output in Standby → Manual Reset Sequence ...................................... Figure 9.6 STATUS Output in Sleep → Interrupt Sequence................................................... Figure 9.7 STATUS Output in Sleep → Power-On Reset Sequence ...................................... Rev.7.00 Oct. 10, 2008 Page lxiv of lxxxiv REJ09B0366-0700 276 276 277 277 278 279 279 Figure 9.8 Figure 9.9 Figure 9.10 Figure 9.11 Figure 9.12 Figure 9.13 Figure 9.14 Figure 9.15 STATUS Output in Sleep → Manual Reset Sequence........................................... STATUS Output in Deep Sleep → Interrupt Sequence ......................................... STATUS Output in Deep Sleep → Power-On Reset Sequence ............................. STATUS Output in Deep Sleep → Manual Reset Sequence ................................. Hardware Standby Mode Timing (When CA = Low in Normal Operation) .......... Hardware Standby Mode Timing (When CA = Low in WDT Operation) ............. Timing When Power Other than VDD-RTC Is Off................................................ Timing When VDD-RTC Power Is Off → On....................................................... 280 281 281 282 283 284 285 285 Section 10 Clock Oscillation Circuits Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S) ................................................... Figure 10.1 (2) Block Diagram of CPG (SH7750R).................................................................. Figure 10.2 Block Diagram of WDT ......................................................................................... Figure 10.3 Writing to WTCNT and WTCSR........................................................................... Figure 10.4 Points for Attention when Using Crystal Resonator............................................... Figure 10.5 Points for Attention when Using PLL Oscillator Circuit ....................................... Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Realtime Clock (RTC) Block Diagram of RTC .......................................................................................... Examples of Time Setting Procedures.................................................................... Examples of Time Reading Procedures.................................................................. Example of Use of Alarm Function........................................................................ Example of Crystal Oscillator Circuit Connection................................................. Timer Unit (TMU) Block Diagram of TMU ......................................................................................... Example of Count Operation Setting Procedure .................................................... TCNT Auto-Reload Operation ............................................................................... Count Timing when Operating on Internal Clock .................................................. Count Timing when Operating on External Clock ................................................. Count Timing when Operating on On-Chip RTC Output Clock............................ Operation Timing when Using Input Capture Function ......................................... 289 290 300 305 307 308 312 329 331 332 334 338 351 352 352 353 353 354 Bus State Controller (BSC) Block Diagram of BSC........................................................................................... Correspondence between Virtual Address Space and External Memory Space..... External Memory Space Allocation ....................................................................... Example of RDY Sampling Timing at which BCR4 Is Set (Two Wait Cycles Are Inserted by WCR2)............................................................ Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR................................................. 359 365 367 385 421 Rev.7.00 Oct. 10, 2008 Page lxv of lxxxiv REJ09B0366-0700 Figure 13.6 Basic Timing of SRAM Interface........................................................................... Figure 13.7 Example of 64-Bit Data Width SRAM Connection ............................................... Figure 13.8 Example of 32-Bit Data Width SRAM Connection ............................................... Figure 13.9 Example of 16-Bit Data Width SRAM Connection ............................................... Figure 13.10 Example of 8-Bit Data Width SRAM Connection ................................................. Figure 13.11 SRAM Interface Wait Timing (Software Wait Only) ............................................ Figure 13.12 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal) .......... Figure 13.13 SRAM Interface Read-Strobe Negate Timing (AnS = 1, AnW = 4, AnH = 2) ...... Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3) ............................... Figure 13.15 Example of DRAM Connection (32-Bit Data Width, Area 3) ............................... Figure 13.16 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3) .................... Figure 13.17 Basic DRAM Access Timing ................................................................................. Figure 13.18 DRAM Wait State Timing ..................................................................................... Figure 13.19 DRAM Burst Access Timing ................................................................................. Figure 13.20 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)............................ Figure 13.21 Burst Access Timing in DRAM EDO Mode.......................................................... Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, AnW = 0) .......................................................... Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, AnW = 0) .......................................................... Figure 13.22 (3) DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, AnW = 0).................................................................. Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, AnW = 0).................................................................. Figure 13.23 CAS-Before-RAS Refresh Operation..................................................................... Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1).............. Figure 13.25 DRAM Self-Refresh Cycle Timing........................................................................ Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3) .......... Figure 13.27 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) .......... Figure 13.28 Basic Timing for Synchronous DRAM Burst Read ............................................... Figure 13.29 Basic Timing for Synchronous DRAM Single Read.............................................. Figure 13.30 Basic Timing for Synchronous DRAM Burst Write .............................................. Figure 13.31 Basic Timing for Synchronous DRAM Single Write............................................. Figure 13.32 Burst Read Timing ................................................................................................. Figure 13.33 Burst Read Timing (RAS Down, Same Row Address).......................................... Figure 13.34 Burst Read Timing (RAS Down, Different Row Addresses)................................. Figure 13.35 Burst Write Timing ................................................................................................ Figure 13.36 Burst Write Timing (Same Row Address) ............................................................. Figure 13.37 Burst Write Timing (Different Row Addresses) .................................................... 439 440 441 442 443 444 445 446 448 449 450 452 453 454 455 456 457 458 459 460 461 462 464 466 467 469 471 473 474 476 477 478 479 480 481 Rev.7.00 Oct. 10, 2008 Page lxvi of lxxxiv REJ09B0366-0700 Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle.................................................................................................... Figure 13.39 Auto-Refresh Operation ......................................................................................... Figure 13.40 Synchronous DRAM Auto-Refresh Timing........................................................... Figure 13.41 Synchronous DRAM Self-Refresh Timing ............................................................ Figure 13.42 (1) Synchronous DRAM Mode Write Timing (PALL) ........................................ Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set)..................... Figure 13.43 Basic Timing of Synchronous DRAM Burst Read (Burst Length = 4).................. Figure 13.44 Basic Timing of a Burst Write to Synchronous DRAM......................................... Figure 13.45 Example of the Connection of Synchronous DRAM with 64-bit Bus Width (256 Mbits)............................................................................................................. Figure 13.46 Synchronous DRAM Auto-Refresh Timing with 64-Bit Bus Width (TRAS[2:0] = 001, TRC[2:0] = 001)...................................................................... Figure 13.47 Burst ROM Basic Access Timing .......................................................................... Figure 13.48 Burst ROM Wait Access Timing ........................................................................... Figure 13.49 Burst ROM Wait Access Timing ........................................................................... Figure 13.50 Example of PCMCIA Interface .............................................................................. Figure 13.51 Basic Timing for PCMCIA Memory Card Interface .............................................. Figure 13.52 Wait Timing for PCMCIA Memory Card Interface ............................................... Figure 13.53 PCMCIA Space Allocation .................................................................................... Figure 13.54 Basic Timing for PCMCIA I/O Card Interface ...................................................... Figure 13.55 Wait Timing for PCMCIA I/O Card Interface ....................................................... Figure 13.56 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface .............................. Figure 13.57 Example of 64-Bit Data Width MPX Connection.................................................. Figure 13.58 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits)................................................................................................ Figure 13.59 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted, Bus Width: 64 Bits)................................................................................................ Figure 13.60 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No Wait, Bus Width: 64 Bits)................................................................................................ Figure 13.61 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted, Bus Width: 64 Bits)................................................................................................ Figure 13.62 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) ............................................... Figure 13.63 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) ............................................... Figure 13.64 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) ............................................... Figure 13.65 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) ............................................... 483 485 486 487 490 491 492 494 495 496 498 499 500 504 505 506 507 508 509 510 512 513 514 515 516 517 518 519 520 Rev.7.00 Oct. 10, 2008 Page lxvii of lxxxiv REJ09B0366-0700 Figure 13.66 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits).................................................. 521 Figure 13.67 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................................... 522 Figure 13.68 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits).................................................. 523 Figure 13.69 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)................................... 524 Figure 13.70 MPX Interface Timing 13 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)................................................ 525 Figure 13.71 MPX Interface Timing 14 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)............................................... 526 Figure 13.72 MPX Interface Timing 15 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)............................................... 527 Figure 13.73 MPX Interface Timing 16 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)............................................... 528 Figure 13.74 Example of 64-Bit Data Width Byte Control SRAM............................................. 530 Figure 13.75 Byte Control SRAM Basic Read Cycle (No Wait) ................................................ 531 Figure 13.76 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) ....................... 532 Figure 13.77 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) .............................................................. 533 Figure 13.78 Waits between Access Cycles ................................................................................ 535 Figure 13.79 Arbitration Sequence.............................................................................................. 538 Section 14 Direct Memory Access Controller (DMAC) Figure 14.1 Block Diagram of DMAC ...................................................................................... Figure 14.2 DMAC Transfer Flowchart .................................................................................... Figure 14.3 Round Robin Mode ................................................................................................ Figure 14.4 Example of Changes in Priority Order in Round Robin Mode............................... Figure 14.5 Data Flow in Single Address Mode ....................................................................... Figure 14.6 DMA Transfer Timing in Single Address Mode.................................................... Figure 14.7 Operation in Dual Address Mode........................................................................... Figure 14.8 Example of Transfer Timing in Dual Address Mode ............................................. Figure 14.9 Example of DMA Transfer in Cycle Steal Mode ................................................... Figure 14.10 Example of DMA Transfer in Burst Mode............................................................. Figure 14.11 Bus Handling with Two DMAC Channels Operating............................................ Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle) ................................................................ Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) ................................................................. Rev.7.00 Oct. 10, 2008 Page lxviii of lxxxiv REJ09B0366-0700 548 568 574 575 577 578 579 580 581 581 585 588 589 Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle) ................................................................ Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) ................................................................. Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) → External Bus ........................................................................................................... Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI (Level Detection).................................................................................................... Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection).................................................................................................... Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection) .................................................................................................... Figure 14.20 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection).................................................................................................... Figure 14.21 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection) .................................................................................................... Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection)/32-Byte Block Transfer (Bus Width: 64 Bits, SDRAM: Row Hit Write)....................................................................................................... Figure 14.23 On-Demand Transfer Mode Block Diagram .......................................................... Figure 14.24 System Configuration in On-Demand Data Transfer Mode................................... Figure 14.25 Data Transfer Request Format................................................................................ Figure 14.26 Single Address Mode: Synchronous DRAM → External Device Longword Transfer SDRAM auto-precharge Read bus cycle, burst (RCD[1:0] = 01, CAS latency = 3, TPC[2:0] = 001)....................................................................................................... Figure 14.27 Single Address Mode: External Device → Synchronous DRAM Longword Transfer SDRAM auto-precharge Write bus cycle, burst (RCD[1:0] = 01, TRWL[2:0] = 101, TPC[2:0] = 001)....................................................................................................... Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer ............ Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer ........................................... Figure 14.30 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer ........................................... Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer ..................................................... Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer ..................................................... Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) ..... Figure 14.34 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data Transfer) ................................................................................................................. 590 591 592 593 594 595 596 597 598 603 605 606 609 610 611 612 613 614 615 616 617 Rev.7.00 Oct. 10, 2008 Page lxix of lxxxiv REJ09B0366-0700 Figure 14.35 Read from Synchronous DRAM Precharge Bank.................................................. Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) ...................... Figure 14.37 Read from Synchronous DRAM (Row Hit) ........................................................... Figure 14.38 Write to Synchronous DRAM Precharge Bank...................................................... Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss).......................... Figure 14.40 Write to Synchronous DRAM (Row Hit)............................................................... Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer........................................... Figure 14.42 DDT Mode Setting ................................................................................................. Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device → External Bus Data Transfer ............................................................................... Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus → External Device Data Transfer .......................................................................... Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Bus → External Device Data Transfer................................... Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device → External Bus Data Transfer................................... Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer Request to Channels 1–3 Using Data Bus.............................................................. Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus → External Device Data Transfer/ Direct Data Transfer Request to Channel 2 without Using Data Bus ......................................................................................... Figure 14.49 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer/Direct Data Transfer Request to Channel 2 ............................................. Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer/Direct Data Transfer Request to Channel 2 ............................................. Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2........ Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2........ Figure 14.53 Block Diagram of the DMAC ................................................................................ Figure 14.54 DTR Format (Transfer Request Format) (SH7750R)............................................. Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer........................................... Figure 14.56 Single Address Mode/Burst Mode/External Bus → External Device/32-Byte Block Transfer/On-Demand Data Transfer on Channel 4...................................... 618 618 619 619 620 620 621 622 622 623 624 625 626 627 628 629 630 631 635 646 650 651 Rev.7.00 Oct. 10, 2008 Page lxx of lxxxiv REJ09B0366-0700 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Serial Communication Interface (SCI) Block Diagram of SCI............................................................................................ MD0/SCK Pin ........................................................................................................ MD7/TxD Pin......................................................................................................... RxD Pin.................................................................................................................. Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) ............................................................................................ Figure 15.6 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode)............................................................................................ Figure 15.7 Sample SCI Initialization Flowchart ...................................................................... Figure 15.8 Sample Serial Transmission Flowchart .................................................................. Figure 15.9 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) ................................................... Figure 15.10 Sample Serial Reception Flowchart (1).................................................................. Figure 15.10 Sample Serial Reception Flowchart (2).................................................................. Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit).......................................................................................................... Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ........................................... Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart ......................................... Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)................................................................................................... Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1)......................................... Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2)......................................... Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)................................................................................................... Figure 15.17 Data Format in Synchronous Communication ....................................................... Figure 15.18 Sample SCI Initialization Flowchart ...................................................................... Figure 15.19 Sample Serial Transmission Flowchart .................................................................. Figure 15.20 Example of SCI Transmit Operation ...................................................................... Figure 15.21 Sample Serial Reception Flowchart (1).................................................................. Figure 15.21 Sample Serial Reception Flowchart (2).................................................................. Figure 15.22 Example of SCI Receive Operation........................................................................ Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception ............................ Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode ....................................... Figure 15.25 Example of Synchronous Transmission by DMAC ............................................... Figure 15.26 Example Countermeasure on SH7750.................................................................... Figure 15.27 Clock Input Timing of SCK Pin............................................................................. 657 674 675 675 687 689 690 691 693 694 695 697 699 700 702 704 705 706 707 709 710 712 713 714 715 716 720 721 723 723 Rev.7.00 Oct. 10, 2008 Page lxxi of lxxxiv REJ09B0366-0700 Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Figure 16.7 Figure 16.8 Serial Communication Interface with FIFO (SCIF) Block Diagram of SCIF.......................................................................................... MD8/RTS2 Pin....................................................................................................... CTS2 Pin ................................................................................................................ MD1/TxD2 Pin....................................................................................................... MD2/RxD2 Pin ...................................................................................................... Sample SCIF Initialization Flowchart .................................................................... Sample Serial Transmission Flowchart .................................................................. Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit).......................................................................................................... Figure 16.9 Example of Operation Using Modem Control (CTS2)........................................... Figure 16.10 Sample Serial Reception Flowchart (1).................................................................. Figure 16.10 Sample Serial Reception Flowchart (2).................................................................. Figure 16.11 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit).......................................................................................................... Figure 16.12 Example of Operation Using Modem Control (RTS2)........................................... Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode ....................................... Figure 16.14 Overrun Error Flag ................................................................................................. Section 17 Smart Card Interface Figure 17.1 Block Diagram of Smart Card Interface................................................................. Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections............................... Figure 17.3 Smart Card Interface Data Format ......................................................................... Figure 17.4 TEND Generation Timing...................................................................................... Figure 17.5 Sample Start Character Waveforms ....................................................................... Figure 17.6 Difference in Clock Output According to GM Bit Setting..................................... Figure 17.7 Sample Initialization Flowchart ............................................................................. Figure 17.8 Sample Transmission Processing Flowchart .......................................................... Figure 17.9 Sample Reception Processing Flowchart ............................................................... Figure 17.10 Receive Data Sampling Timing in Smart Card Mode ............................................ Figure 17.11 Retransfer Operation in SCI Receive Mode ........................................................... Figure 17.12 Retransfer Operation in SCI Transmit Mode ......................................................... Figure 17.13 Procedure for Stopping and Restarting the Clock .................................................. Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 I/O Ports 16-Bit Port.............................................................................................................. 4-Bit Port................................................................................................................ MD0/SCK Pin ........................................................................................................ MD7/TxD Pin......................................................................................................... RxD Pin.................................................................................................................. 727 753 754 755 755 761 762 764 764 765 766 768 769 772 774 776 783 784 786 787 790 791 793 795 797 799 799 800 804 805 806 807 807 Rev.7.00 Oct. 10, 2008 Page lxxii of lxxxiv REJ09B0366-0700 Figure 18.6 Figure 18.7 Figure 18.8 Figure 18.9 Section 19 Figure 19.1 Figure 19.2 Figure 19.3 MD1/TxD2 Pin....................................................................................................... MD2/RxD2 Pin ...................................................................................................... CTS2 Pin ................................................................................................................ MD8/RTS2 Pin....................................................................................................... 808 808 809 810 Interrupt Controller (INTC) Block Diagram of INTC......................................................................................... 826 Example of IRL Interrupt Connection.................................................................... 829 Interrupt Operation Flowchart................................................................................ 844 Section 20 User Break Controller (UBC) Figure 20.1 Block Diagram of User Break Controller............................................................... 852 Figure 20.2 User Break Debug Support Function Flowchart .................................................... 873 Section 21 Figure 21.1 Figure 21.2 Figure 21.3 High-performance User Debug Interface (H-UDI) Block Diagram of H-UDI Circuit........................................................................... 880 TAP Control State Transition Diagram .................................................................. 891 H-UDI Reset........................................................................................................... 892 Section 22 Electrical Characteristics Figure 22.1 EXTAL Clock Input Timing .................................................................................. Figure 22.2 (1) CKIO Clock Output Timing ............................................................................. Figure 22.2 (2) CKIO Clock Output Timing ............................................................................. Figure 22.3 Power-On Oscillation Settling Time ...................................................................... Figure 22.4 Standby Return Oscillation Settling Time (Return by RESET) ............................. Figure 22.5 Power-On Oscillation Settling Time ...................................................................... Figure 22.6 Standby Return Oscillation Settling Time (Return by RESET) ............................. Figure 22.7 Standby Return Oscillation Settling Time (Return by NMI).................................. Figure 22.8 Standby Return Oscillation Settling Time (Return by IRL3 to IRL0).................... Figure 22.9 PLL Synchronization Settling Time in Case of RESET or NMI Interrupt............. Figure 22.10 PLL Synchronization Settling Time in Case of IRL Interrupt................................ Figure 22.11 Manual Reset Input Timing.................................................................................... Figure 22.12 Mode Input Timing ................................................................................................ Figure 22.13 Control Signal Timing............................................................................................ Figure 22.14 (1) Pin Drive Timing for Reset or Sleep Mode .................................................... Figure 22.14 (2) Pin Drive Timing for Software Standby Mode ............................................... Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait)...................................................... Figure 22.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) ...................................... Figure 22.17 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) .... 940 940 940 941 941 942 942 943 943 944 944 945 945 948 948 949 956 957 958 Rev.7.00 Oct. 10, 2008 Page lxxiii of lxxxiv REJ09B0366-0700 Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) ................................................................................. 959 Figure 22.19 Burst ROM Bus Cycle (No Wait) .......................................................................... 960 Figure 22.20 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait)..................................................................... 961 Figure 22.21 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) ................................................................................................................ 962 Figure 22.22 Burst ROM Bus Cycle (One Internal Wait + One External Wait) ......................... 963 Figure 22.23 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) ....................................................................... 964 Figure 22.24 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) ....................................................................... 965 Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RASD = 1, RCD[1:0] = 01, CAS Latency = 3)........................................... 966 Figure 22.26 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst ((RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, CAS Latency = 3) .............. 967 Figure 22.27 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst ((RASD = 1, CAS Latency = 3) ............................................................................. 968 Figure 22.28 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) ...................................................................... 969 Figure 22.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) ...................................................................... 970 Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RASD = 1, RCD[1:0] = 01, TRWL[2:0] = 010) ......................................... 971 Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) .............. 972 Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (RASD = 1, TRWL[2:0] = 010) ............................................................................. 973 Figure 22.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command (RASD = 1, TPC[2:0] = 001) ................................................................................. 974 Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh (TRAS = 1, TRC[2:0] = 001) ................................................................................. 975 Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh (TRC[2:0] = 001) ................................................................................................... 976 Figure 22.36 (a) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (PALL)....................................................................................................... 977 Figure 22.36 (b) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (SET).......................................................................................................... 978 Figure 22.37 DRAM Bus Cycles (1) RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001 (2) RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 010 .......................................... 979 Rev.7.00 Oct. 10, 2008 Page lxxiv of lxxxiv REJ09B0366-0700 Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) ..................................................................................................... Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) ..................................................................................................... Figure 22.40 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001) ..................................................................................................... Figure 22.41 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width) ............................................. Figure 22.42 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000).................................................................................................... Figure 22.43 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000).......................................................................... Figure 22.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) ..................................................................................................... Figure 22.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001) ..................................................................................................... Figure 22.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width) ............................................. Figure 22.47 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000).......................................................................... Figure 22.48 DRAM Burst Bus Cycle: RAS Down Mode Continuation (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000).......................................................................... Figure 22.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 000, TRC[2:0] = 001)..................................................................................................... Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 001, TRC[2:0] = 001)..................................................................................................... Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001) .................................. Figure 22.52 PCMCIA Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait .... Figure 22.53 PCMCIA I/O Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait .... Figure 22.54 PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait, Bus Sizing) ............................................................................................................. Figure 22.55 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data (One Internal Wait + One External Wait) .............................................................. Figure 22.56 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data (One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait)................................. Figure 22.57 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait) (2) 1st Data (One Internal Wait), 2nd to 4th Data (One Internal Wait + One External Wait) .............................................................. 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 Rev.7.00 Oct. 10, 2008 Page lxxv of lxxxiv REJ09B0366-0700 Figure 22.58 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait), 2nd to 4th Data (No Internal Wait + External Wait Control) ................................ 1000 Figure 22.59 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait).................................................................................... 1001 Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, AnS[0] = 1, AnH[1:0] =0 1) ..................................... 1002 Figure 22.61 TCLK Input Timing .............................................................................................. 1011 Figure 22.62 RTC Oscillation Settling Time at Power-On......................................................... 1011 Figure 22.63 SCK Input Clock Timing ...................................................................................... 1011 Figure 22.64 SCI I/O Synchronous Mode Clock Timing ........................................................... 1012 Figure 22.65 I/O Port Input/Output Timing................................................................................ 1012 Figure 22.66 (a) DREQ/DRAK Timing.................................................................................... 1012 Figure 22.66 (b) DBREQ/TR Input Timing and BAVL Output Timing .................................. 1013 Figure 22.67 TCK Input Timing................................................................................................. 1013 Figure 22.68 RESET Hold Timing............................................................................................. 1014 Figure 22.69 H-UDI Data Transfer Timing................................................................................ 1014 Figure 22.70 Pin Break Timing .................................................................................................. 1014 Figure 22.71 NMI Input Timing................................................................................................. 1014 Figure 22.72 Output Load Circuit .............................................................................................. 1015 Figure 22.73 Load Capacitance vs. Delay Time......................................................................... 1016 Appendix B Figure B.1 Figure B.2 Figure B.3 Figure B.4 Package Dimensions Package Dimensions (256-Pin BGA).................................................................... 1023 Package Dimensions (208-Pin QFP) ..................................................................... 1024 Package Dimensions (264-Pin CSP) ..................................................................... 1025 Package Dimensions (292-Pin BGA).................................................................... 1026 Appendix D CKIO2ENB Pin Configuration Figure D.1 CKIO2ENB Pin Configuration ............................................................................. 1031 Appendix G Prefetching of Instructions and its Side Effects Figure G.1 Instruction Prefetch ............................................................................................... 1059 Appendix H Power-On and Power-Off Procedures Figure H.1 Power-On Procedure 1 .......................................................................................... 1062 Figure H.2 Power-On Procedure 2 .......................................................................................... 1063 Rev.7.00 Oct. 10, 2008 Page lxxvi of lxxxiv REJ09B0366-0700 Tables Section 1 Overview Table 1.1 LSI Features ........................................................................................................... Table 1.2 Pin Functions.......................................................................................................... Table 1.3 Pin Functions.......................................................................................................... Table 1.4 Pin Functions.......................................................................................................... Table 1.5 Pin Functions.......................................................................................................... 1 14 24 32 42 Section 2 Programming Model Table 2.1 Initial Register Values ............................................................................................ 55 Section 3 Memory Management Unit (MMU) Table 3.1 MMU Registers ...................................................................................................... 74 Section 4 Caches Table 4.1 Cache Features (SH7750, SH7750S)...................................................................... Table 4.2 Cache Features (SH7750R) .................................................................................... Table 4.3 Features of Store Queues........................................................................................ Table 4.4 Cache Control Registers......................................................................................... 111 112 112 113 Section 5 Exceptions Table 5.1 Exception-Related Registers .................................................................................. 149 Table 5.2 Exceptions .............................................................................................................. 152 Table 5.3 Types of Reset........................................................................................................ 161 Section 6 Floating-Point Unit (FPU) Table 6.1 Floating-Point Number Formats and Parameters ................................................... Table 6.2 Floating-Point Ranges ............................................................................................ Table 6.3 Incorrect Operation Result ..................................................................................... Table 6.4 FDIV DRm, DRn (DRn/DRm → DRn) ................................................................ Table 6.5 FADD DRm, DRn (DRn + DRm → DRn) FSUB DRm, DRn (DRn − DRm → DRn) ........................................................................................... Table 6.6 FMUL DRm, DRn (DRn*DRm → DRn).............................................................. Table 6.7 TRAP Routine Processing...................................................................................... 186 187 203 204 205 205 207 Section 7 Instruction Set Table 7.1 Addressing Modes and Effective Addresses .......................................................... 211 Table 7.2 Notation Used in Instruction List ........................................................................... 215 Rev.7.00 Oct. 10, 2008 Page lxxvii of lxxxiv REJ09B0366-0700 Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 Table 7.8 Table 7.9 Table 7.10 Table 7.11 Table 7.12 Fixed-Point Transfer Instructions........................................................................... Arithmetic Operation Instructions.......................................................................... Logic Operation Instructions.................................................................................. Shift Instructions .................................................................................................... Branch Instructions ................................................................................................ System Control Instructions ................................................................................... Floating-Point Single-Precision Instructions.......................................................... Floating-Point Double-Precision Instructions ........................................................ Floating-Point Control Instructions........................................................................ Floating-Point Graphics Acceleration Instructions ................................................ 216 218 220 221 222 223 225 226 226 227 Section 8 Pipelining Table 8.1 Instruction Groups.................................................................................................. 238 Table 8.2 Parallel-Executability ............................................................................................. 242 Table 8.3 Execution Cycles.................................................................................................... 249 Section 9 Power-Down Modes Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes ............................ Table 9.2 Power-Down Mode Registers ................................................................................ Table 9.3 Power-Down Mode Pins ........................................................................................ Table 9.4 State of Registers in Standby Mode ....................................................................... Section 10 Clock Oscillation Circuits Table 10.1 CPG Pins ................................................................................................................ Table 10.2 CPG Register.......................................................................................................... Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S).................................................... Table 10.3 (2) Clock Operating Modes (SH7750R) .................................................................. Table 10.4 FRQCR Settings and Internal Clock Frequencies .................................................. Table 10.5 WDT Registers....................................................................................................... 260 261 261 270 292 292 293 293 294 301 Section 11 Realtime Clock (RTC) Table 11.1 RTC Pins ................................................................................................................ 313 Table 11.2 RTC Registers ........................................................................................................ 313 Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values) ............................... 333 Section 12 Timer Unit (TMU) Table 12.1 TMU Pins ............................................................................................................... 338 Table 12.2 TMU Registers ....................................................................................................... 339 Table 12.3 TMU Interrupt Sources .......................................................................................... 355 Rev.7.00 Oct. 10, 2008 Page lxxviii of lxxxiv REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.1 BSC Pins ................................................................................................................ Table 13.2 BSC Registers ........................................................................................................ Table 13.3 External Memory Space Map................................................................................. Table 13.4 PCMCIA Interface Features ................................................................................... Table 13.5 PCMCIA Support Interfaces .................................................................................. Table 13.6 MPX Interface is Selected (Areas 0 to 6) ............................................................... Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment ...................... Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment ...................... Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment .......................... Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment .......................... Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment ............................ Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment ................. Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment ................. Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment ....................... Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment ....................... Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment ......................... Table 13.15 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing... Table 13.16 Example of Correspondence between this LSI and Synchronous DRAM Address Pins (64-Bit Bus Width, AMX2–AMX0 = 011, AMXEXT = 0) ........................... Table 13.17 Cycles for which Pipeline Access is Possible......................................................... Table 13.18 Relationship between Address and CE when Using PCMCIA Interface ............... Section 14 Table 14.1 Table 14.2 Table 14.3 Table 14.4 Table 14.5 Table 14.6 Table 14.7 Table 14.8 Table 14.9 Table 14.10 Table 14.11 Table 14.12 Table 14.13 Table 14.14 Table 14.15 Direct Memory Access Controller (DMAC) DMAC Pins ............................................................................................................ DMAC Pins in DDT Mode .................................................................................... DMAC Registers .................................................................................................... Selecting External Request Mode with RS Bits ..................................................... Selecting On-Chip Peripheral Module Request Mode with RS Bits ...................... Supported DMA Transfers ..................................................................................... Relationship between DMA Transfer Type, Request Mode, and Bus Mode ......... External Request Transfer Sources and Destinations in Normal DMA Mode ....... External Request Transfer Sources and Destinations in DDT Mode ..................... Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings ........................................................ DMAC Pins ............................................................................................................ DMAC Pins in DDT Mode .................................................................................... Register Configuration ........................................................................................... Channel Selection by DTR Format (DMAOR.DBL = 1)....................................... Notification of Transfer Channel in Eight-Channel DDT Mode ............................ 360 364 366 368 369 398 423 424 425 426 427 428 429 430 431 432 451 468 484 502 549 550 550 570 572 576 582 583 584 602 636 637 638 646 648 Rev.7.00 Oct. 10, 2008 Page lxxix of lxxxiv REJ09B0366-0700 Table 14.16 Function of BAVL ................................................................................................. 648 Table 14.17 DTR Format for Clearing Request Queues ............................................................ 649 Table 14.18 DMAC Interrupt-Request Codes............................................................................ 650 Section 15 Serial Communication Interface (SCI) Table 15.1 SCI Pins.................................................................................................................. Table 15.2 SCI Registers.......................................................................................................... Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ................. Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode.................... Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)............................................................................................ Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) .................... Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection ........................................ Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection.......................... Table 15.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... Table 15.11 Receive Error Conditions ....................................................................................... Table 15.12 SCI Interrupt Sources ............................................................................................. Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data.............................................. Table 15.14 Peripheral Module Signal Timing .......................................................................... Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.1 SCIF Pins ............................................................................................................... Table 16.2 SCIF Registers ....................................................................................................... Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection ........................................ Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection .............................................. Table 16.5 Serial Transmit/Receive Formats ........................................................................... Table 16.6 SCIF Interrupt Sources........................................................................................... Section 17 Smart Card Interface Table 17.1 Smart Card Interface Pins ...................................................................................... Table 17.2 Smart Card Interface Registers............................................................................... Table 17.3 Smart Card Interface Register Settings .................................................................. Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings .................................... Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0)....... Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) .................... Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) ............ Table 17.8 Register Settings and SCK Pin State ...................................................................... Table 17.9 Smart Card Mode Operating States and Interrupt Sources..................................... 658 659 677 681 682 683 683 685 686 688 696 718 719 724 728 729 758 758 759 770 777 777 785 788 788 788 789 789 796 Rev.7.00 Oct. 10, 2008 Page lxxx of lxxxiv REJ09B0366-0700 Section 18 I/O Ports Table 18.1 20-Bit General-Purpose I/O Port Pins .................................................................... Table 18.2 SCI I/O Port Pins.................................................................................................... Table 18.3 SCIF I/O Port Pins.................................................................................................. Table 18.4 I/O Port Registers ................................................................................................... Section 19 Interrupt Controller (INTC) Table 19.1 INTC Pins............................................................................................................... Table 19.2 INTC Registers....................................................................................................... Table 19.3 IRL3–IRL0 Pins and Interrupt Levels .................................................................... Table 19.4 SH7750 IRL3–IRL0 Pins and Interrupt Levels (When IRLM = 1)........................ Table 19.5 Interrupt Exception Handling Sources and Priority Order ..................................... Table 19.6 Interrupt Request Sources and IPRA–IPRD Registers ........................................... Table 19.7 Interrupt Request Sources and the Bits of the INTPRI00 Register ........................ Table 19.8 Bit Assignments ..................................................................................................... Table 19.9 Interrupt Response Time ........................................................................................ 811 812 812 813 827 827 830 831 833 836 839 842 846 Section 20 User Break Controller (UBC) Table 20.1 UBC Registers........................................................................................................ 853 Section 21 High-performance User Debug Interface (H-UDI) Table 21.1 H-UDI Pins............................................................................................................. 881 Table 21.2 H-UDI Registers..................................................................................................... 882 Table 21.3 Configuration of the Boundary Scan Register........................................................ 888 Section 22 Table 22.1 Table 22.2 Table 22.3 Table 22.4 Table 22.5 Table 22.6 Table 22.7 Table 22.8 Table 22.9 Table 22.10 Table 22.11 Table 22.12 Table 22.13 Table 22.14 Electrical Characteristics Absolute Maximum Ratings................................................................................... DC Characteristics (HD6417750RBP240 (V), HD6417750RBG240 (V)) ............ DC Characteristics (HD6417750RF240 (V)) ......................................................... DC Characteristics (HD6417750RBP200 (V), HD6417750RBG200 (V)) ............ DC Characteristics (HD6417750RF200 (V)) ......................................................... DC Characteristics (HD6417750SBP200 (V))....................................................... DC Characteristics (HD6417750SF200 (V)).......................................................... DC Characteristics (HD6417750BP200M (V))...................................................... DC Characteristics (HD6417750SF167 (V)).......................................................... DC Characteristics (HD6417750F167 (V))............................................................ DC Characteristics (HD6417750SVF133 (V))....................................................... DC Characteristics (HD6417750SVBT133 (V)).................................................... DC Characteristics (HD6417750VF128 (V))......................................................... Permissible Output Currents................................................................................... 895 896 898 900 902 904 906 908 910 912 914 916 918 919 Rev.7.00 Oct. 10, 2008 Page lxxxi of lxxxiv REJ09B0366-0700 Table 22.15 Clock Timing (HD6417750RBP240 (V), HD6417750RBG240 (V)) .................... 920 Table 22.16 Clock Timing (HD6417750RF240 (V))................................................................. 920 Table 22.17 Clock Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750RBP200 (V), HD6417750RBG200 (V))............................................. 920 Table 22.18 Clock Timing (HD6417750RF200 (V))................................................................. 920 Table 22.19 Clock Timing (HD6417750SF200 (V)) ................................................................. 921 Table 22.20 Clock Timing (HD6417750F167 (V), HD6417750SF167 (V)) ............................. 921 Table 22.21 Clock Timing (HD6417750SVF133 (V), HD6417750SVBT133 (V)) .................. 921 Table 22.22 Clock Timing (HD6417750VF128 (V))................................................................. 921 Table 22.23 Clock and Control Signal Timing (HD6417750RBP240 (V), HD6417750RBG240 (V)) ...................................................................................... 922 Table 22.24 Clock and Control Signal Timing (HD6417750RF240 (V)).................................. 924 Table 22.25 Clock and Control Signal Timing (HD6417750RBP200 (V), HD6417750RBG200 (V)) ...................................................................................... 926 Table 22.26 Clock and Control Signal Timing (HD6417750RF200 (V)).................................. 928 Table 22.27 Clock and Control Signal Timing (HD6417750BP200M (V), HD6417750SBP200 (V)) ....................................................................................... 930 Table 22.28 Clock and Control Signal Timing (HD6417750SF200 (V)) .................................. 932 Table 22.29 Clock and Control Signal Timing (HD6417750F167 (V), HD6417750SF167 (V)).......................................................................................... 934 Table 22.30 Clock and Control Signal Timing (HD6417750SVF133 (V), HD6417750SVBT133 (V)) .................................................................................... 936 Table 22.31 Clock and Control Signal Timing (HD6417750VF128 (V)).................................. 938 Table 22.32 Control Signal Timing (1) ...................................................................................... 946 Table 22.32 Control Signal Timing (2) ...................................................................................... 947 Table 22.33 Bus Timing (1) ....................................................................................................... 950 Table 22.33 Bus Timing (2) ....................................................................................................... 952 Table 22.33 Bus Timing (3) ....................................................................................................... 954 Table 22.34 Peripheral Module Signal Timing (1)................................................................... 1003 Table 22.34 Peripheral Module Signal Timing (2)................................................................... 1005 Table 22.34 Peripheral Module Signal Timing (3)................................................................... 1007 Table 22.34 Peripheral Module Signal Timing (4)................................................................... 1008 Table 22.34 Peripheral Module Signal Timing (5)................................................................... 1010 Appendix A Address List Table A.1 Address List ......................................................................................................... 1017 Appendix E Pin Functions Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State ........................ 1033 Rev.7.00 Oct. 10, 2008 Page lxxxii of lxxxiv REJ09B0366-0700 Appendix I Product Lineup Table I.1 SH7750/SH7750S/SH7750R Product Lineup ...................................................... 1065 Appendix J Version Registers Table J.1 Register Configuration ......................................................................................... 1067 Rev.7.00 Oct. 10, 2008 Page lxxxiii of lxxxiv REJ09B0366-0700 Rev.7.00 Oct. 10, 2008 Page lxxxiv of lxxxiv REJ09B0366-0700 Section 1 Overview Section 1 Overview 1.1 SH7750, SH7750S, SH7750R Groups Features This LSI (SH7750, SH7750S, and SH7750R Groups) is a 32-bit RISC (reduced instruction set computer) microprocessor with a SH-4 CPU core and features upward compatibility with SH-1, SH-2, and SH-3 microcomputers at the instruction set level. It includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation lookaside buffer). The SH7750 and SH7750S have an 8-Kbyte instruction cache and a 16-Kbyte data cache. The SH7750R has a 16-Kbyte instruction cache and a 32-Kbyte data cache. This LSI has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions. The features of this LSI are summarized in table 1.1. Table 1.1 Item LSI LSI Features Features • • Superscalar architecture: Parallel execution of two instructions External buses ⎯ Separate 26-bit address and 64-bit data buses ⎯ External bus frequency of 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus frequency Rev.7.00 Oct. 10, 2008 Page 1 of 1074 REJ09B0366-0700 Section 1 Overview Item CPU Features • • • Renesas Technology original SuperH architecture 32-bit internal data bus General register file: ⎯ Sixteen 32-bit general registers (and eight 32-bit shadow registers) ⎯ Seven 32-bit control registers ⎯ Four 32-bit system registers • RISC-type instruction set (upward-compatible with SH-1, SH-2, and SH-3) ⎯ Fixed 16-bit instruction length for improved code efficiency ⎯ Load-store architecture ⎯ Delayed branch instructions ⎯ Conditional execution ⎯ C-based instruction set • • • • • • Superscalar architecture (providing simultaneous execution of two instructions) including FPU Instruction execution time: Maximum 2 instructions/cycle Virtual address space: 4 Gbytes (448-Mbyte external memory space) Space identifier ASIDs: 8 bits, 256 virtual address spaces On-chip multiplier Five-stage pipeline Rev.7.00 Oct. 10, 2008 Page 2 of 1074 REJ09B0366-0700 Section 1 Overview Item FPU Features • • • • • • • • • • • On-chip floating-point coprocessor Supports single-precision (32 bits) and double-precision (64 bits) Supports IEEE754-compliant data types and exceptions Two rounding modes: Round to Nearest and Round to Zero Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754 Floating-point registers: 32 bits × 16 × 2 banks (single-precision 32 bits × 16 or double-precision 64 bits × 8) × 2 banks 32-bit CPU-FPU floating-point communication register (FPUL) Supports FMAC (multiply-and-accumulate) instruction Supports FDIV (divide) and FSQRT (square root) instructions Supports FLDI0/FLDI1 (load constant 0/1) instructions Instruction execution times ⎯ Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8 cycles (double-precision) ⎯ Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles (double-precision) Note: FMAC is supported for single-precision only. • 3-D graphics instructions (single-precision only): ⎯ 4-dimensional vector conversion and matrix operations (FTRV): 4 cycles (pitch), 7 cycles (latency) ⎯ 4-dimensional vector inner product (FIPR): 1 cycle (pitch), 4 cycles (latency) Rev.7.00 Oct. 10, 2008 Page 3 of 1074 REJ09B0366-0700 Section 1 Overview Item Clock pulse generator (CPG) Features • Choice of main clock: ⎯ SH7750, SH7750S: 1/2, 1, 3, or 6 times EXTAL ⎯ SH7750R: 1, 6, or 12 times EXTAL • Clock modes: ⎯ CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ⎯ Bus frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ⎯ Peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock Note: Maximum frequency varies with models. • Power-down modes ⎯ Sleep mode ⎯ Standby mode ⎯ Module standby function • Memory management unit (MMU) • • • • • • • Single-channel watchdog timer 4-Gbyte address space, 256 address space identifiers (8-bit ASIDs) Single virtual mode and multiple virtual memory mode Supports multiple page sizes: 1 Kbyte, 4 Kbytes, 64 Kbytes, 1 Mbyte 4-entry fully-associative TLB for instructions 64-entry fully-associative TLB for instructions and operands Supports software-controlled replacement and random-counter replacement algorithm TLB contents can be accessed directly by address mapping Rev.7.00 Oct. 10, 2008 Page 4 of 1074 REJ09B0366-0700 Section 1 Overview Item Features Instruction cache (IC) ⎯ 8 Kbytes, direct mapping ⎯ 256 entries, 32-byte block length ⎯ Normal mode (8-Kbyte cache) ⎯ Index mode • Operand cache (OC) ⎯ 16 Kbytes, direct mapping ⎯ 512 entries, 32-byte block length ⎯ Normal mode (16-Kbyte cache) ⎯ Index mode ⎯ RAM mode (8-Kbyte cache + 8-Kbyte RAM) ⎯ Choice of write method (copy-back or write-through) • • • Cache memory [SH7750R] • Single-stage copy-back buffer, single-stage write-through buffer Cache memory contents can be accessed directly by address mapping (usable as on-chip memory) Store queue (32 bytes × 2 entries) Instruction cache (IC) ⎯ 16 Kbytes, 2-way set associative ⎯ 256 entries/way, 32-byte block length ⎯ Cache-double-mode (16-Kbyte cache) ⎯ Index mode ⎯ SH7750/SH7750S-compatible mode (8 Kbytes, direct mapping) • Operand cache (OC) ⎯ 32 Kbytes, 2-way set associative ⎯ 512 entries/way, 32-byte block length ⎯ Cache-double-mode (32-Kbyte cache) ⎯ Index mode ⎯ RAM mode (16-Kbyte cache + 16-Kbyte RAM) ⎯ SH7750/SH7750S-compatible mode (16 Kbytes, direct mapping) • • • Single-stage copy-back buffer, single-stage write-through buffer Cache memory contents can be accessed directly by address mapping (usable as on-chip memory) Store queue (32 bytes × 2 entries) Rev.7.00 Oct. 10, 2008 Page 5 of 1074 REJ09B0366-0700 Cache memory • [SH7750, SH7750S] Section 1 Overview Item Interrupt controller (INTC) Features • • • Five independent external interrupts: NMI, IRL3 to IRL0 15-level encoded external interrupts: IRL3 to IRL0 On-chip peripheral module interrupts: Priority level can be set for each module Supports debugging by means of user break interrupts Two break channels Address, data value, access type, and data size can all be set as break conditions Supports sequential break function Supports external memory access ⎯ 64/32/16/8-bit external data bus • External memory space divided into seven areas, each of up to 64 Mbytes, with the following parameters settable for each area: ⎯ Bus size (8, 16, 32, or 64 bits) ⎯ Number of wait cycles (hardware wait function also supported) ⎯ Connection of DRAM, synchronous DRAM, and burst ROM possible by setting space type ⎯ Supports fast page mode and DRAM EDO ⎯ Supports PCMCIA interface ⎯ Chip select signals (CS0 to CS6) output for relevant areas • DRAM/synchronous DRAM refresh functions ⎯ Programmable refresh interval ⎯ Supports CAS-before-RAS refresh mode and self-refresh mode • • DRAM/synchronous DRAM burst access function Big endian or little endian mode can be set User break controller (UBC) • • • • Bus state controller (BSC) • Rev.7.00 Oct. 10, 2008 Page 6 of 1074 REJ09B0366-0700 Section 1 Overview Item Direct memory access controller (DMAC) Features • Physical address DMA controller: ⎯ SH7750, SH7750S: 4-channel ⎯ SH7750R: 8-channel • • Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes Address modes: ⎯ Single address mode ⎯ Dual address mode • • • Timer unit (TMU) • Transfer requests: External, on-chip module, or auto-requests Bus modes: Cycle-steal or burst mode Supports on-demand data transfer Auto-reload 32-bit timer: ⎯ SH7750, SH7750S: 3-channel ⎯ SH7750R: 5-channel • • Realtime clock (RTC) • • Input capture function Choice of seven counter input clocks On-chip clock and calendar functions Built-in 32 kHz crystal oscillator with maximum 1/256 second resolution (cycle interrupts) Two full-duplex communication channels (SCI, SCIF) Channel 1 (SCI): ⎯ Choice of asynchronous mode or synchronous mode ⎯ Supports smart card interface • Channel 2 (SCIF): ⎯ Supports asynchronous mode ⎯ Separate 16-byte FIFOs provided for transmitter and receiver Serial communication interface (SCI, SCIF) • • Rev.7.00 Oct. 10, 2008 Page 7 of 1074 REJ09B0366-0700 Section 1 Overview Item Product lineup Features Abbreviation SH7750 Voltage (Internal) 1.95 V 1.8 V 1.5 V SH7750S 1.95 V Operating Frequency 200 MHz 167 MHz 128 MHz 200 MHz Model No. HD6417750BP200M HD6417750F167 HD6417750VF128 HD6417750SBP200 HD6417750SF200 1.8 V 1.5 V 167 MHz 133 MHz HD6417750SF167 HD6417750SVF133 HD6417750SVBT133 SH7750R 1.5 V 240 MHz HD6417750RBG240 HD6417750RBP240 HD6417750RF240 200 MHz HD6417750RBG200 HD6417750RBP200 HD6417750RF200 264-pin CSP 292-pin BGA 256-pin BGA 208-pin QFP 292-pin BGA 256-pin BGA 208-pin QFP 256-pin BGA 208-pin QFP Package 256-pin BGA 208-pin QFP Rev.7.00 Oct. 10, 2008 Page 8 of 1074 REJ09B0366-0700 Section 1 Overview 1.2 Block Diagram Figure 1.1 shows an internal block diagram of this LSI. CPU 32-bit address (instructions) UBC FPU 32-bit data (instructions) 32-bit address (data) 32-bit data (store) 64-bit data (store) Lower 32-bit data Upper 32-bit data 32-bit data (load) SH-4 Core Lower 32-bit data I cache ITLB Cache and TLB controller UTLB O cache 29-bit address 32-bit data CPG INTC 16-bit peripheral data bus Peripheral address bus SCI (SCIF) BSC 32-bit data DMAC 64-bit data TMU External bus interface 26-bit address 64-bit data Legend: BSC: CPG: DMAC: FPU: INTC: ITLB: Bus state controller Clock pulse generator Direct memory access controller Floating-point unit Interrupt controller Instruction TLB (translation lookaside buffer) UTLB: RTC: SCI: SCIF: TMU: UBC: Figure 1.1 Block Diagram of SH7750/SH7750S/SH7750R Group Functions Rev.7.00 Oct. 10, 2008 Page 9 of 1074 REJ09B0366-0700 64-bit data RTC Address Unified TLB (translation lookaside buffer) Realtime clock Serial communication interface Serial communication interface with FIFO Timer unit User break controller Section 1 Overview 1.3 Pin Arrangement EXTAL CKIO2ENB XTAL VSS-CPG VDD-CPG(3.3V) VDD-PLL1(3.3V) VDD-PLL2(3.3V) TDI TCK TMS TDO ASEBRK/BRKACK MD6/IOIS16 STATUS1 STATUS0 DACK1 DACK0 MD5/RAS2 MD4/CE2B VDD-RTC(3.3V) VSS-RTC EXTAL2 XTAL2 18 19 20 1 2 3 4 5 6 7 8 9 10 MD3/CE2A A25 A24 A23 A22 A21 A20 A19 A18 MD7/TXD SCK2/MRESET MD8/RTS2 TCLK 11 12 13 14 15 16 17 VSS-PLL1 D VSS-PLL2 RDY RESET CS0 CS1 CS6 BS D47 D32 D46 D33 D45 D34 D44 D35 D43 D36 D42 D37 D41 D38 D40 D39 D15 D0 D14 D1 D13 D2 D12 D3 D11 D4 D10 D5 D9 D6 A B C NMI IRL3 IRL2 IRL1 IRL0 MD1/TXD2 MD0/SCK D63 TRST CTS2 E F CS4 CS5 RD2 D48 D62 CA* D49 D61 D50 D60 D51 D59 D52 D58 D53 D57 D54 D56 D55 D31 D16 D30 D17 D29 D18 D28 D19 D27 D20 D26 D21 D25 A1 A0 G MD2/RXD2 RD/WR2 H J K BGA256 (Top view) L M N P DRAK1 DRAK0 R BACK/BSREQ BREQ/BSACK DREQ1 DREQ0 RXD T U V W Y Notes: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used. * Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Figure 1.2 Pin Arrangement (256-Pin BGA) Rev.7.00 Oct. 10, 2008 Page 10 of 1074 REJ09B0366-0700 CKIO CKIO2 A6 A5 A4 A3 A2 CS3 CS2 RAS RD/CASS/FRAME RD/WR WE2/CAS2/DQM2/ICIORD WE3/CAS3/DQM3/ICIOWR WE6/CAS6/DQM6 WE7/CAS7/DQM7/REG D23 D24 D22 D8 D7 CKE WE5/CAS5/DQM5 WE4/CAS4/DQM4 WE1/CAS1/DQM1 WE0/CAS0/DQM0 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 VDDQ (IO) VSSQ (IO) VDD (internal) VSS (internal) NC Section 1 Overview TDO ASEBRK/BRKACK MD6/IOIS16 STATUS1 STATUS0 A1 EXTAL XTAL VSS-CPG VDD-CPG(3.3V) VSS-PLL1 VDD-PLL1(3.3V) VSS-PLL2 VDD-PLL2(3.3V) TRST TDI TCK TMS RDY RESET CS0 CS1 CS4 CS5 CS6 BS D47 D32 D46 D33 D45 D34 D44 D35 D43 D36 D42 D37 D41 D38 D40 D39 D15 D0 D14 D1 D13 D2 D12 D3 D11 D4 D10 D5 D9 D6 BACK/BSREQ BREQ/BSACK D8 D7 CKE A12 A11 A10 A9 A8 A7 CKIO A6 A5 A4 A3 A2 DRAK1 DRAK0 CS3 CS2 RAS RD/CASS/FRAME RD/WR WE2/CAS2/DQM2/IOICRD WE3/CAS3/DQM3/IOICWR WE6/CAS6/DQM6 Notes: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used. * Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Figure 1.3 Pin Arrangement (208-Pin QFP) Rev.7.00 Oct. 10, 2008 Page 11 of 1074 REJ09B0366-0700 WE7/CAS7/DQM7/REG D23 D24 D22 WE5/CAS5/DQM5 WE4/CAS4/DQM4 WE1/CAS1/DQM1 WE0/CAS0/DQM0 A17 A16 A15 A14 A13 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 CA* VDD-RTC(3.3V) VSS-RTC EXTAL2 XTAL2 SCK2/MRESET MD7/TXD MD8/RTS2 TCLK CTS2 A0 DACK1 DACK0 MD5/RAS2 MD4/CE2B MD3/CE2A A25 A24 A23 A22 A21 A20 A19 A18 QFP208 Top view VDD (internal) VSS (internal) VDDQ (IO) VSSQ (IO) 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 NMI IRL3 IRL2 IRL1 IRL0 MD2/RXD2 MD1/TXD2 MD0/SCK D63 D48 D62 D49 D61 D50 D60 D51 D59 D52 D58 D53 D57 D54 D56 D55 D31 D16 D30 D17 D29 D18 D28 D19 D27 D20 D26 D21 D25 DREQ1 DREQ0 RXD Section 1 Overview 1 A VSS-CPG 2 3 4 5 TRST 6 7 8 9 10 11 12 13 14 15 16 17 IRL2 XTAL EXTAL VDD-CPG TDO MD6/IOIS16 A0 VDDQ VDDQ A20 VDD TCLK VSS-RTC XTAL2 EXTAL2 B RESET CS4 VDD-PLL2 VSS STATUS0 DACK0 A24 VDDQ MD7/TXD CA IRL3 C RDY VSS-PLL2 VSS-PLL1 VDD-PLL1 TCK VSSQ VSSQ MD3/CE2A A22 A18 VDDQ VDDQ VDD-RTC MD1/TXD2 NMI D CS0 VSSQ CKIO2ENB TDI VDD A1 MD5/RAS2 A23 VSS MD8/RTS2 CTS2 VSSQ IRL0 IRL1 E BS CS1 CS5 CS6 TMS ASEBRK/ BRKACK VDDQ VDDQ MD4/CE2B VSSQ VSSQ SCK2/ MRESET D48 RD/WR2 MD2/RXD2 VSSQ F VDD D47 VDDQ RD2 D32 D33 STATUS1 DACK1 VSSQ A25 A21 A19 D49 VDDQ D63 MD0/SCK D62 G D45 VDDQ D46 VSS VSSQ D34 D50 VDDQ VDD VSSQ VSS D61 H VDDQ D43 D44 D35 VSSQ D36 J VDDQ D38 D42 D41 D37 VSSQ CSP264 (Top view) D52 VDDQ D51 VSSQ D60 D59 VSSQ D57 D53 D54 D58 VDDQ K D39 D0 VSSQ D15 VDDQ D40 D56 VSSQ D31 D16 D55 VDDQ L D1 VSS VSSQ VDD VDDQ D14 D30 VSSQ VSS D18 VDDQ D17 M D2 D4 D3 VDDQ D13 A14 A9 VDDQ A6 A2 D29 D28 D27 VDDQ D19 VDD N VSSQ D5 D11 D12 A16 VDDQ VDDQ A7 A4 DRAK0 VSSQ VSS D26 D21 VDDQ D20 P VSSQ VDDQ VDDQ WE4/CAS4/ WE0/CAS0/ DQM4 DQM0 CKE WE5/CAS5/ DQM5 VDD A11 VSSQ VSSQ CS2 RD/CASS/ VSSQ FRAME RAS VSSQ D25 DREQ1 R D6 BREQ/ BSACK D10 A17 VSS A12 A8 VDDQ VDDQ WE3/CAS3/ WE6/CAS6/ WE2/CAS2/ RXD DQM3/ICIOWR DQM6 DQM2/ICIORD T BACK/ BSREQ VSSQ D8 VDDQ VSSQ A13 VSSQ CKIO2 A3 VDD RD/WR D24 D22 VSSQ DREQ0 U D9 D7 WE1/CAS1/ DQM1 A15 VSSQ A10 CKIO A5 DRAK1 CS3 VDDQ VDDQ WE7/CAS7/ DQM7/REG D23 VSSQ VDDQ (IO) VSSQ (IO) VDD (internal) VSS (internal) NC Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used. Figure 1.4 Pin Arrangement (264-Pin CSP) Rev.7.00 Oct. 10, 2008 Page 12 of 1074 REJ09B0366-0700 Section 1 Overview EXTAL VSS-PLL1 XTAL VDD-CPG(3.3V) VSS-CPG VSS-PLL2 VDD-PLL1(3.3V) TRST VDD-PLL2(3.3V) TMS TCK MD6/IOIS16 ASEBRK/BRKACK STATUS0 STATUS1 A0 A1 DACK0 DACK1 MD5/RAS2 MD4/CE2B MD3/CE2A A25 A24 A23 A22 A21 A20 A19 A18 SCK2/MRESET MD7/TXD TCLK CTS2 VDD-RTC(3.3V) VSS-RTC EXTAL2 IRL3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 RDY RESET CS0 CS1 CS5 CS6 RD2 D47 D32 D46 D33 D45 D34 D44 D35 D43 D36 D42 D38 D41 D39 D40 D0 D15 D1 D14 D2 D13 D3 D12 D10 D4 D9 D5 BACK/ BSREQ BREQ/ BSACK A XTAL2 VSS-RTC NMI IRL1 IRL2 MD2/RXD2 IRL0 RD/WR2 B C D CKIO2ENB TDI E F CS4 BS BGA292 (Top view) MD8/ RTS2 TDO MD0/SCK D62 CA D48 D61 D49 D60 D50 D59 D53 D51 D58 D52 D57 D54 D56 D55 D31 D16 D30 D17 D29 D18 D28 D19 D27 D20 D21 D25 DREQ1 WE7/CAS7/DQM7/ REG G MD1/TXD2 D63 H J K D37 L M N CKIO2 P D11 R D7 WE4/CAS4/DQM4 D26 WE2/CAS2/ DQM2/ICIORD T U V W Y Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used. Figure 1.5 Pin Arrangement (292-Pin BGA) A5 A6 A3 A4 DRAK1 A2 CS3 DRAK0 RAS CS2 RD/WR RD/CASS/FRAME WE6/CAS6/DQM6 WE3/CAS3/DQM3/ICIOWR D24 D23 D22 DREQ0 RXD D6 D8 CKE WE5/CAS5/DQM5 WE1/CAS1/DQM1 WE0/CAS0/DQM0 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 CKIO VDDQ (IO) VDD (internal) VSS Rev.7.00 Oct. 10, 2008 Page 13 of 1074 REJ09B0366-0700 Section 1 Overview 1.4 1.4.1 Table 1.2 Pin No. B2 B1 C2 C1 D4 D3 D2 D1 E4 E3 F3 F4 E2 E1 G3 G4 F2 F1 H3 H4 G2 G1 H2 H1 J3 J4 Pin Functions Pin Functions (256-Pin BGA) Pin Functions Memory Interface Pin Name RDY RESET CS0 CS1 CS4 CS5 CS6 BS VSSQ RD2 VDDQ VSSQ D47 D32 VDD VSS D46 D33 VDDQ VSSQ D45 D34 D44 D35 VDDQ VSSQ I/O I I O O O O O O Function Bus ready Reset Chip select 0 Chip select 1 Chip select 4 Chip select 5 Chip select 6 Bust start RD/CASS/ FRAME CS0 CS1 CS4 CS5 CS6 (BS) OE (BS) (BS) CAS CE1A CE1B (BS) OE Reset SRAM RDY DRAM SDRAM PCMCIA MPX RDY RESET CS0 CS1 CS4 CS5 CS6 (BS) FRAME RDY No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Power IO GND (0 V) O Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power Internal VDD (1.8 V) Power Internal GND (0 V) I/O I/O Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data/port Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) Rev.7.00 Oct. 10, 2008 Page 14 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin Name D43 D36 D42 D37 VDDQ VSSQ D41 D38 D40 D39 VDDQ VSSQ D15 D0 D14 D1 VDDQ VSSQ D13 D2 VDD VSS D12 D3 VDDQ VSSQ D11 D4 D10 D5 VDDQ VSSQ D9 I/O I/O I/O I/O I/O Function Data/port Data/port Data/port Data/port Reset SRAM (Port) (Port) (Port) (Port) DRAM (Port) (Port) (Port) (Port) SDRAM PCMCIA MPX (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Pin No. J2 J1 K2 K1 K3 K4 L1 L2 M1 M2 L3 L4 N1 N2 P1 P2 M3 M4 R1 R2 P3 P4 T1 T2 R3 R4 U1 U2 V1 V2 T3 T4 W1 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data/port Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A15 A0 A14 A1 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data Data A13 A2 Power Internal VDD Power Internal GND (0 V) I/O I/O Data Data A12 A3 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A11 A4 A10 A5 Power IO VDD (3.3 V) Power IO GND (0 V) I/O Data A9 Rev.7.00 Oct. 10, 2008 Page 15 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin Name D6 BACK/ BSREQ BREQ/ BSACK D8 D7 CKE VDDQ VSSQ I/O I/O O Function Data Bus acknowledge/ bus request Bus request/bus acknowledge Data Data Clock output enable CKE A8 A7 Reset SRAM DRAM SDRAM PCMCIA MPX A6 No. 60 61 Pin No. Y1 U3 62 V3 I 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 W2 Y2 W3 V5 U5 Y3 W4 Y4 W5 Y5 V6 U6 W6 Y6 V7 U7 W7 Y7 V8 U8 V4 W8 Y8 I/O I/O O Power IO VDD (3.3 V) Power IO GND (0 V) D47–D40 select signal D39–D32 select signal D15–D8 select signal D7–D0 select signal Address WE5 WE4 WE1 WE0 CAS5 CAS4 CAS1 CAS0 DQM5 DQM4 DQM1 DQM0 WE1 WE5/CAS5/ O DQM5 WE4/CAS4/ O DQM4 WE1/CAS1/ O DQM1 WE0/CAS0/ O DQM0 A17 VDDQ VSSQ A16 A15 VDD VSS A14 A13 VDDQ VSSQ NC A12 A11 O O O Power IO VDD (3.3 V) Power IO GND (0 V) O O Address Address Power Internal VDD Power Internal GND (0 V) O O Address Address Power IO VDD (3.3 V) Power IO GND (0 V) Address Address Rev.7.00 Oct. 10, 2008 Page 16 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin Name A10 VDDQ VSSQ A9 A8 A7 CKIO VDDQ VSSQ CKIO2 A6 A5 A4 VDDQ VSSQ A3 A2 DRAK1 DRAK0 VDDQ VSSQ CS3 CS2 VDD VSS RAS RD/CASS/ FRAME VDDQ VSSQ RD/WR I/O O Function Address Reset SRAM DRAM SDRAM PCMCIA MPX No. 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Pin No. W9 V9 U9 Y9 W10 Y10 Y11 V10 U10 W11 Y12 W12 Y13 V11 Power IO VDD (3.3 V) Power IO GND (0 V) O O O O Address Address Address Clock output CKIO CKIO CKIO Power IO VDD (3.3 V) Power IO GND (0 V) O O O O CKIO* 1 CKIO CKIO CKIO Address Address Address Power IO VDD (3.3 V) Power IO GND (0 V) O O O O Address Address DMAC1 request acknowledge DMAC0 request acknowledge 100 U11 101 W13 102 Y14 103 V12 104 U13 105 V13 106 U12 107 W14 108 Y15 109 V14 110 U14 111 W15 112 Y16 113 V15 114 U15 115 W16 Power IO VDD (3.3 V) Power IO GND (0 V) O O Chip select 3 Chip select 2 CS3 CS2 (CS3) (CS2) CS3 CS2 CS3 CS2 Power Internal VDD Power Internal GND (0 V) O O RAS Read/CAS/ FRAME OE RAS RAS CAS OE FRAME Power IO VDD (3.3 V) Power IO GND (0 V) O Read/write RD/WR RD/WR RD/WR RD/WR RD/WR Rev.7.00 Oct. 10, 2008 Page 17 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin Name I/O Function D23–D16 select signal D31–D24 select signal D55–D48 select signal Reset SRAM WE2 DRAM CAS2 SDRAM PCMCIA MPX DQM2 ICIORD WE2/CAS2/ O DQM2/ ICIORD WE3/CAS3/ O DQM3/ ICIOWR WE6/CAS6/ O DQM6 VDDQ VSSQ No. Pin No. 116 Y17 117 W17 WE3 CAS3 DQM3 ICIOWR 118 Y18 119 V16 120 U16 121 W18 122 Y19 123 W19 124 Y20 125 V17 126 U17 127 U18 128 W20 129 T18 130 T17 131 V19 132 V20 133 U19 134 U20 135 R18 136 R17 137 T19 138 T20 139 P18 140 P17 141 R19 142 R20 WE6 CAS6 DQM6 Power IO VDD (3.3 V) Power IO GND (0 V) D63–D56 select signal Data Data Data SCI data input Request from DMAC0 Request from DMAC1 Data A25 WE7 CAS7 DQM7 REG A23 A24 A22 WE7/CAS7/ O DQM7/REG D23 D24 D22 RXD DREQ0 DREQ1 D25 VDDQ VSSQ D21 D26 D20 D27 VDDQ VSSQ D19 D28 VDD VSS D18 D29 I/O I/O I/O I I I I/O Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A20 A21 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data Data A19 Power Internal VDD Power Internal GND (0 V) I/O I/O Data Data A18 Rev.7.00 Oct. 10, 2008 Page 18 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin Name VDDQ VSSQ D17 D30 D16 D31 VDDQ VSSQ D55 D56 D54 D57 VDDQ VSSQ D53 D58 D52 D59 VDDQ VSSQ D51 D60 D50 D61 VDDQ VSSQ D49 D62 VDD VSS D48 D63 VDDQ I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX No. Pin No. 143 N18 144 N17 145 P19 146 P20 147 N19 148 N20 149 M18 150 M17 151 M19 152 M20 153 L19 154 L20 155 L18 156 L17 157 K20 158 K19 159 J20 160 J19 161 K18 162 K17 163 H20 164 H19 165 G20 166 G19 167 J18 168 J17 169 F20 170 F19 171 G18 172 G17 173 E20 174 E19 175 F18 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A16 A17 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data/port Data Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE0 (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE1 Power Internal VDD Power Internal GND (0 V) I/O I/O Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE2 Power IO VDD (3.3 V) Rev.7.00 Oct. 10, 2008 Page 19 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin Name VSSQ VSSQ RD/WR2 MD0/SCK I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX No. Pin No. 176 F17 177 E17 178 E18 179 D20 180 D19 181 D18 182 C20 183 C19 184 B20 185 C18 186 A20 187 B19 188 A19 189 B18 190 A18 191 D17 192 C17 193 B17 194 C16 195 A17 196 B16 Power IO GND (0 V) Power IO GND (0 V) O I/O RD/WR Mode/SCI clock Mode SCIF data output Mode/SCIF data input Interrupt 0 Interrupt 1 Interrupt 2 Interrupt 3 Nonmaskable interrupt RTC crystal resonator pin RTC crystal resonator pin MD0 MD1 MD2 RD/WR RD/WR RD/WR RD/WR SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 RD/WR SCK TXD2 RXD2 MD1/TXD2 I/O MD2/RXD2 I IRL0 IRL1 IRL2 IRL3 NMI XTAL2 EXTAL2 VSS-RTC VDD-RTC CA VSS VDDQ CTS2 TCLK I I I I I O I Power RTC GND (0 V) Power RTC VDD (3.3 V) I *2 Power Internal GND (0 V) Power IO VDD (3.3 V) I/O I/O SCIF data control (CTS) RTC/TMU clock Mode/SCIF data control (RTS) MD8 RTS2 RTS2 RTS2 RTS2 RTS2 MD8/RTS2 I/O 197 C15 198 D15 199 B15 VDDQ VSSQ MD7/TXD Power IO VDD (3.3 V) Power IO GND (0 V) I/O Mode/SCI data output MD7 TXD TXD TXD TXD TXD Rev.7.00 Oct. 10, 2008 Page 20 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin Name SCK2/ MRESET VDD VSS A18 A19 VDDQ VSSQ A20 A21 A22 A23 VDDQ VSSQ A24 A25 I/O I Function SCIF clock/ manual reset Reset SRAM DRAM SCK2 SDRAM PCMCIA MPX SCK2 SCK2 SCK2 MRESET SCK2 No. Pin No. 200 A16 201 C14 202 D14 203 A15 204 B14 205 C13 206 D13 207 A14 208 B13 209 A13 210 B12 211 C12 212 D12 213 A12 214 B11 215 A11 216 A10 217 C11 218 D11 219 B10 220 A9 221 B9 222 C8 223 C10 224 D10 225 D8 226 A8 227 B8 Power Internal VDD Power Internal GND (0 V) O O Address Address Power IO VDD (3.3 V) Power IO GND (0 V) O O O O Address Address Address Address Power IO VDD (3.3 V) Power IO GND (0 V) O O Address Address Mode/ PCMCIA-CE Mode/ PCMCIA-CE MD3 MD4 CE2A CE2B MD3/CE2A I/O MD4/CE2B I/O VDDQ VSSQ Power IO VDD (3.3 V) Power IO GND (0 V) Mode/RAS (DRAM) DMAC0 bus acknowledge DMAC1 bus acknowledge Address MD5 RAS2 MD5/RAS2 I/O DACK0 DACK1 A0 VDDQ VSSQ A1 STATUS0 STATUS1 O O O Power IO VDD (3.3 V) Power IO GND (0 V) O O O Address Status Status Rev.7.00 Oct. 10, 2008 Page 21 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin Name MD6/ IOIS16 VDDQ VSSQ ASEBRK/ BRKACK TDO VDD VSS TMS TCK TDI TRST I/O I Function Mode/IOIS16 (PCMCIA) Reset MD6 SRAM DRAM SDRAM PCMCIA MPX IOIS16 No. Pin No. 228 A7 229 C9 230 D9 231 B7 Power IO VDD (3.3 V) Power IO GND (0 V) I/O Pin break/ acknowledge (H-UDI) Data out (H-UDI) 232 A6 233 C7 234 D7 235 B6 236 A5 237 B5 238 C4 239 C3 O Power Internal VDD Power Internal GND (0 V) I I I I Mode (H-UDI) Clock (H-UDI) Data in (H-UDI) Reset (H-UDI) CKIO2, RD2, RD/WR2 enable CKIO2ENB I 240 C6 241 A4 242 D6 243 B4 244 D5 245 A3 246 B3 247 A2 248 A1 NC VDD-PLL2 VSS-PLL2 VDD-PLL1 VSS-PLL1 VDD-CPG VSS-CPG XTAL EXTAL Power PLL2 VDD (3.3V) Power PLL2 GND (0V) Power PLL1 VDD (3.3V) Power PLL1 GND (0V) Power CPG VDD (3.3V) Power CPG GND (0V) O I Crystal resonator External input clock/crystal resonator 249 C5 NC Rev.7.00 Oct. 10, 2008 Page 22 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin Name NC NC NC NC NC NC NC I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX No. Pin No. 250 D16 251 H17 252 H18 253 N3 254 N4 255 U4 256 V18 Legend: I: Input O: Output I/O: Input/output Power: Power supply Notes: Supply power to all power pins. For the SH7750S, supply power to RTC at a minimum in hardware standby mode. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the onchip crystal oscillation circuit is used. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the onchip RTC is used. VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package. NC pins must be left completely open, and not connected to a power supply, GND, etc. 1. CKIO2 is not connected to PLL2. 2. Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Rev.7.00 Oct. 10, 2008 Page 23 of 1074 REJ09B0366-0700 Section 1 Overview 1.4.2 Table 1.3 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Pin Functions (208-Pin QFP) Pin Functions Memory Interface Pin Name RDY RESET CS0 CS1 CS4 CS5 CS6 BS VDDQ VSSQ D47 D32 VDD VSS D46 D33 D45 D34 D44 D35 VDDQ VSSQ D43 D36 D42 D37 D41 D38 D40 I/O I I O O O O O O Power Power I/O I/O Power Power I/O I/O I/O I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/O I/O Function Bus ready Reset Chip select 0 Chip select 1 Chip select 4 Chip select 5 Chip select 6 Bust start IO VDD (3.3 V) IO GND (0 V) Data/port Data/port Internal VDD Internal GND (0 V) Data/port Data/port Data/port Data/port Data/port Data/port IO VDD (3.3 V) IO GND (0 V) Data/port Data/port Data/port Data/port Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) CS0 CS1 CS4 CS5 CS6 (BS) (BS) (BS) CE1A CE1B (BS) Reset SRAM RDY DRAM SDRAM PCMCIA MPX RDY RESET CS0 CS1 CS4 CS5 CS6 (BS) RDY Rev.7.00 Oct. 10, 2008 Page 24 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Pin Name D39 VDDQ VSSQ D15 D0 D14 D1 D13 D2 VDD VSS D12 D3 VDDQ VSSQ D11 D4 D10 D5 D9 D6 BACK/ BSREQ BREQ/ BSACK D8 D7 CKE VDDQ VSSQ I/O I/O Power Power I/O I/O I/O I/O I/O I/O Power Power I/O I/O Power Power I/O I/O I/O I/O I/O I/O O Function Data/port IO VDD (3.3 V) IO GND (0 V) Data Data Data Data Data Data Internal VDD (1.8 V) Internal GND (0 V) Data Data IO VDD (3.3 V) IO GND (0 V) Data Data Data Data Data Data Bus acknowledge/ bus request Bus request/bus acknowledge Data Data Clock output enable IO VDD (3.3 V) IO GND (0 V) CKE A8 A7 A11 A4 A10 A5 A9 A6 A12 A3 A15 A0 A14 A1 A13 A2 Reset SRAM (Port) DRAM (Port) SDRAM PCMCIA MPX (Port) (Port) (Port) 52 53 54 55 56 57 I I/O I/O O Power Power Rev.7.00 Oct. 10, 2008 Page 25 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin No. 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Pin Name I/O Function D47–D40 select signal D39–D32 select signal D15–D8 select signal D7–D0 select signal Address Address Address Internal VDD Internal GND (0 V) Address Address IO VDD (3.3 V) IO GND (0 V) Address Address Address Address Address Address Clock output IO VDD (3.3 V) IO GND (0 V) Address Address Address Address Address DMAC1 request acknowledge CKIO CKIO CKIO Reset SRAM WE5 WE4 WE1 WE0 DRAM CAS5 CAS4 CAS1 CAS0 SDRAM PCMCIA MPX DQM5 DQM4 DQM1 DQM0 WE1 WE5/CAS5/ O DQM5 WE4/CAS4/ O DQM4 WE1/CAS1/ O DQM1 WE0/CAS0/ O DQM0 A17 A16 A15 VDD VSS A14 A13 VDDQ VSSQ A12 A11 A10 A9 A8 A7 CKIO VDDQ VSSQ A6 A5 A4 A3 A2 DRAK1 O O O Power Power O O Power Power O O O O O O O Power Power O O O O O O Rev.7.00 Oct. 10, 2008 Page 26 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin No. 86 87 88 89 90 91 92 93 94 95 96 Pin Name DRAK0 VDDQ VSSQ CS3 CS2 VDD VSS RAS RD/CASS/ FRAME RD/WR I/O O Power Power O O Power Power O O O Function DMAC0 request acknowledge IO VDD (3.3 V) IO GND (0 V) Chip select 3 Chip select 2 Internal VDD Internal GND (0 V) RAS Read/CAS/ FRAME Read/write D23–D16 select signal D31–D24 select signal D55–D48 select signal IO VDD (3.3 V) IO GND (0 V) D63–D56 select signal Data Data Data SCI Data input Request from DMAC0 Request from DMAC1 Data Data Data Data A20 A25 A21 WE7 CAS7 DQM7 REG A23 A24 A22 OE RAS RAS CAS OE FRAME RD/WR CS3 CS2 (CS3) (CS2) CS3 CS2 CS3 CS2 Reset SRAM DRAM SDRAM PCMCIA MPX RD/WR RD/WR RD/WR RD/WR WE2 CAS2 DQM2 ICIORD WE2/CAS2/ O DQM2/ ICIORD WE3/CAS3/ O DQM3/ ICIOWR WE6/CAS6/ O DQM6 VDDQ VSSQ Power Power 97 WE3 CAS3 DQM3 ICIOWR 98 99 100 101 102 103 104 105 106 107 108 109 110 111 WE6 CAS6 DQM6 WE7/CAS7/ O DQM7/REG D23 D24 D22 RXD DREQ0 DREQ1 D25 D21 D26 D20 I/O I/O I/O I I I I/O I/O I/O I/O Rev.7.00 Oct. 10, 2008 Page 27 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin No. 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 Pin Name D27 VDDQ VSSQ D19 D28 VDD VSS D18 D29 D17 D30 D16 D31 VDDQ VSSQ D55 D56 D54 D57 D53 D58 D52 D59 VDDQ VSSQ D51 D60 D50 D61 D49 D62 VDD I/O I/O Power Power I/O I/O Power Power I/O I/O I/O I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/O Power Function Data IO VDD (3.3 V) IO GND (0 V) Data Data Internal VDD Internal GND (0 V) Data Data Data Data Data Data IO VDD (3.3 V) IO GND (0 V) Data Data Data Data Data Data Data Data IO VDD (3.3 V) IO GND (0 V) Data/port Data Data/port Data Data/port Data Internal VDD (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) ACCSIZE0 (Port) ACCSIZE1 (Port) (Port) (Port) (Port) (Port) A16 A17 A18 A19 Reset SRAM DRAM SDRAM PCMCIA MPX Rev.7.00 Oct. 10, 2008 Page 28 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin No. 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 Pin Name VSS D48 D63 VDDQ VSSQ MD0/SCK MD1/TXD2 MD2/RXD2 IRL0 IRL1 IRL2 IRL3 NMI XTAL2 EXTAL2 VSS-RTC VDD-RTC CA VSS VDDQ CTS2 TCLK MD8/RTS2 MD7/TXD I/O Power I/O I/O Power Power I/O I/O I I I I I I O I Power Power I Power Power I/O I/O I/O I/O Function Internal GND (0 V) Data/port Data IO VDD (3.3 V) IO GND (0 V) Mode/SCI clock MD0 SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 (Port) (Port) (Port) (Port) (Port) ACCSIZE2 Reset SRAM DRAM SDRAM PCMCIA MPX Mode SCIF data MD1 output Mode/SCIF data MD2 input Interrupt 0 Interrupt 1 Interrupt 2 Interrupt 3 Nonmaskable interrupt RTC crystal resonator pin RTC crystal resonator pin RTC GND (0 V) RTC VDD (3.3 V) * Internal GND (0 V) IO VDD (3.3 V) SCIF data control (CTS) RTC/TMU clock Mode/SCIF data MD8 control (RTS) Mode/SCI data output MD7 RTS2 TXD RTS2 TXD RTS2 TXD RTS2 TXD RTS2 TXD Rev.7.00 Oct. 10, 2008 Page 29 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin No. 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 Pin Name SCK2/ MRESET VDD VSS A18 A19 A20 A21 A22 A23 VDDQ VSSQ A24 A25 MD3/CE2A MD4/CE2B MD5/RAS2 DACK0 DACK1 A0 VDDQ VSSQ A1 STATUS0 STATUS1 MD6/ IOIS16 ASEBRK/ BRKACK I/O I Power Power O O O O O O Power Power O O I/O I/O I/O O O O Power Power O O O I I/O Function SCIF clock/ manual reset Internal VDD Internal GND (0 V) Address Address Address Address Address Address IO VDD (3.3 V) IO GND (0 V) Address Address Mode/ PCMCIA-CE Mode/ PCMCIA-CE Mode/RAS (DRAM) DMAC0 bus acknowledge DMAC1 bus acknowledge Address IO VDD (3.3 V) IO GND (0 V) Address Status Status Mode/IOIS16 (PCMCIA) Pin break/ acknowledge (H-UDI) MD6 IOIS16 MD3 MD4 MD5 RAS2 CE2A CE2B Reset SRAM DRAM SCK2 SDRAM PCMCIA MPX SCK2 SCK2 SCK2 MRESET SCK2 Rev.7.00 Oct. 10, 2008 Page 30 of 1074 REJ09B0366-0700 Section 1 Overview Memory Interface Pin No. 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin Name TDO VDD VSS TMS TCK TDI TRST VDD-PLL2 VSS-PLL2 VDD-PLL1 VSS-PLL1 VDD-CPG VSS-CPG XTAL EXTAL I/O O Power Power I I I I Power Power Power Power Power Power O I Function Data out (H-UDI) Internal VDD Internal GND (0 V) Mode (H-UDI) Clock (H-UDI) Data in (H-UDI) Reset (H-UDI) PLL2 VDD (3.3V) PLL2 GND (0V) PLL1 VDD (3.3V) PLL1 GND (0V) CPG VDD (3.3V) CPG GND (0V) Crystal resonator External input clock/crystal resonator Reset SRAM DRAM SDRAM PCMCIA MPX Legend: I: Input O: Output I/O: Input/output Power: Power supply Notes: Supply power to all power pins. For the SH7750S, supply power to RTC at a minimum in hardware standby mode. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the onchip crystal oscillation circuit is used. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the onchip RTC is used. VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package. The RD2, RD/WR2, CKIO2, and CKIO2ENB pins are not provided on the QFP package. For a QFP package, the maximum operating frequency of the external bus is 84 MHz. * Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V. Rev.7.00 Oct. 10, 2008 Page 31 of 1074 REJ09B0366-0700 Section 1 Overview 1.4.3 Table 1.4 Pin No. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 C2 B1 D3 E2 B2 E3 E4 E1 F4 F3 D4 F2 F5 F1 G4 G3 F6 G2 G5 G1 G6 H3 H4 H1 H5 H2 H6 J3 Pin Functions (264-Pin CSP) Pin Functions Memory Interface Pin Name RDY RESET CS0 CS1 CS4 CS5 CS6 BS RD2 VDDQ VSSQ D47 D32 VDD VSS D46 D33 VDDQ VSSQ D45 D34 D44 D35 VDDQ VSSQ D43 D36 D42 I/O I I O O O O O O O Function Bus ready Reset Chip select 0 Chip select 1 Chip select 4 Chip select 5 Chip select 6 Bus start RD/CASS/ FRAME CS0 CS1 CS4 CS5 CS6 (BS) OE (BS) (BS) CAS CE1A CE1B (BS) OE Reset SRAM RDY DRAM SDRAM PCMCIA MPX RDY RESET CS0 CS1 CS4 CS5 CS6 (BS) FRAME RDY Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power Internal VDD (1.5 V) Power Internal GND (0 V) I/O I/O Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data/port Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Rev.7.00 Oct. 10, 2008 Page 32 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 J5 J1 J6 J4 J2 K6 K1 K5 K3 K4 K2 L6 L1 L5 L3 M5 M1 L4 L2 N5 M3 M4 N1 N4 M2 R3 N3 P3 P1 U1 R1 Memory Interface Pin Name D37 VDDQ VSSQ D41 D38 D40 D39 VDDQ VSSQ D15 D0 D14 D1 VDDQ VSSQ D13 D2 VDD VSS D12 D3 VDDQ VSSQ D11 D4 D10 D5 VDDQ VSSQ D9 D6 I/O I/O Function Data/port Reset SRAM (Port) DRAM (Port) SDRAM PCMCIA MPX (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data/port Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A15 A0 A14 A1 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data Data A13 A2 Power Internal VDD (1.5 V) Power Internal GND (0 V) I/O I/O Data Data A12 A3 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A11 A4 A10 A5 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data Data A9 A6 Rev.7.00 Oct. 10, 2008 Page 33 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 60 T1 Memory Interface Pin Name BACK/ BSREQ BREQ/ BSACK D8 D7 CKE VDDQ VSSQ I/O O Function Bus acknowledge/ bus request Bus request/bus acknowledge Data Data Clock output enable CKE A8 A7 Reset SRAM DRAM SDRAM PCMCIA MPX 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 R2 T3 U2 R4 T5 T2 R5 P5 U5 P6 R6 P4 T6 N6 U6 P7 R7 M6 T7 N7 U7 R8 P8 U8 N8 I I/O I/O O Power IO VDD (3.3 V) Power IO GND (0 V) D47–D40 select signal D39–D32 select signal D15–D8 select signal D7–D0 select signal Address WE5 WE4 WE1 WE0 CAS5 CAS4 CAS1 CAS0 DQM5 DQM4 DQM1 DQM0 WE1 WE5/CAS5/ O DQM5 WE4/CAS4/ O DQM4 WE1/CAS1/ O DQM1 WE0/CAS0/ O DQM0 A17 VDDQ VSSQ A16 A15 VDD VSS A14 A13 VDDQ VSSQ A12 A11 A10 VDDQ O Power IO VDD (3.3 V) Power IO GND (0 V) O O Address Address Power Internal VDD (1.5 V) Power Internal GND (0 V) O O Address Address Power IO VDD (3.3 V) Power IO GND (0 V) O O O Address Address Address Power IO VDD (3.3 V) Rev.7.00 Oct. 10, 2008 Page 34 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 86 87 88 89 90 91 92 93 94 95 96 97 98 99 T8 M8 R9 N9 U9 M9 P9 T9 Memory Interface Pin Name VSSQ A9 A8 A7 CKIO VDDQ VSSQ CKIO2 I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX Power IO GND (0 V) O O O O Address Address Address Clock output CKIO CKIO CKIO Power IO VDD (3.3 V) Power IO GND (0 V) O O O O CKIO* Address Address Address CKIO CKIO CKIO M10 A6 U10 N10 R10 P10 T10 A5 A4 VDDQ VSSQ A3 Power IO VDD (3.3 V) Power IO GND (0 V) O O O O Address Address DMAC1 request acknowledge DMAC0 request acknowledge 100 M11 A2 101 U11 102 N11 103 R11 104 N12 105 U12 106 P11 107 T11 108 N13 109 R12 110 P12 111 U13 112 P13 113 T12 114 R15 DRAK1 DRAK0 VDDQ VSSQ CS3 CS2 VDD VSS RAS RD/CASS/ FRAME VDDQ VSSQ RD/WR Power IO VDD (3.3 V) Power IO GND (0 V) O O Chip select 3 Chip select 2 CS3 CS2 (CS3) (CS2) CS3 CS2 CS3 CS2 Power Internal VDD (1.5 V) Power Internal GND (0 V) O O RAS Read/CAS/ FRAME OE RAS RAS CAS OE FRAME Power IO VDD (3.3 V) Power IO GND (0 V) O Read/write D23–D16 select signal RD/WR RD/WR RD/WR RD/WR WE2 CAS2 DQM2 ICIORD RD/WR WE2/CAS2/ O DQM2/ ICIORD Rev.7.00 Oct. 10, 2008 Page 35 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 115 R13 Memory Interface Pin Name I/O Function D31–D24 select signal D55–D48 select signal Reset SRAM WE3 DRAM CAS3 SDRAM PCMCIA MPX DQM3 ICIOWR WE3/CAS3/ O DQM3/ ICIOWR WE6/CAS6/ O DQM6 VDDQ VSSQ 116 R14 117 U14 118 U17 119 U15 120 U16 121 T13 122 T15 123 R16 124 T17 125 P17 126 P15 127 N16 128 T16 129 N15 130 N14 131 N17 WE6 CAS6 DQM6 Power IO VDD (3.3 V) Power IO GND (0 V) D63–D56 select signal Data Data Data SCI1 data input Request from DMAC0 Request from DMAC1 Data A25 WE7 CAS7 DQM7 REG A23 A24 A22 WE7/CAS7/ O DQM7/REG D23 D24 D22 RXD DREQ0 DREQ1 D25 VDDQ VSSQ D21 D26 D20 I/O I/O I/O I I I I/O Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data A20 A21 132 M14 D27 133 M15 VDDQ 134 P14 VSSQ Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data Data A19 135 M16 D19 136 M13 D28 137 M17 VDD 138 L14 139 L15 VSS D18 Power Internal VDD (1.5 V) Power Internal GND (0 V) I/O I/O Data Data A18 140 M12 D29 141 L16 142 L13 VDDQ VSSQ Power IO VDD (3.3 V) Power IO GND (0 V) Rev.7.00 Oct. 10, 2008 Page 36 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 143 L17 144 L12 145 K15 146 K14 147 K17 148 K13 149 K16 150 K12 151 J15 152 J13 153 J17 154 J12 155 J14 156 J16 157 H12 158 H17 159 H13 160 H15 161 H14 162 H16 Memory Interface Pin Name D17 D30 D16 D31 VDDQ VSSQ D55 D56 D54 D57 VDDQ VSSQ D53 D58 D52 D59 VDDQ VSSQ D51 D60 I/O I/O I/O I/O I/O Function Data Data Data Data A16 Reset SRAM DRAM SDRAM PCMCIA MPX A17 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data Data Data Data Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O I/O I/O Data/port Data Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE0 (Port) (Port) (Port) (Port) (Port) 163 G12 D50 164 G17 D61 165 G13 VDDQ 166 G15 VSSQ 167 F13 168 F17 D49 D62 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I/O Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE1 169 G14 VDD 170 G16 VSS 171 E13 172 F15 173 F14 174 E17 D48 D63 VDDQ VSSQ Power Internal VDD (1.5 V) Power Internal GND (0 V) I/O I/O Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE2 Power IO VDD (3.3 V) Power IO GND (0 V) Rev.7.00 Oct. 10, 2008 Page 37 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 175 E14 176 F16 177 C15 178 E15 179 D15 180 D17 181 A17 182 B17 183 C16 184 A15 185 A16 186 A14 187 C14 188 B13 189 C13 190 D13 191 A13 192 D12 193 C12 194 D14 195 B12 196 E12 197 A12 Memory Interface Pin Name RD/WR2 MD0/SCK MD1/TXD2 I/O O I/O I/O Function RD/WR Mode/SCI1 clock Mode/SCIF data output Mode/SCIF data input Interrupt 0 Interrupt 1 Interrupt 2 Interrupt 3 Nonmaskable interrupt RTC crystal resonator pin RTC crystal resonator pin MD0 MD1 MD2 Reset SRAM DRAM SDRAM PCMCIA MPX RD/WR SCK TXD2 RXD2 RD/WR RD/WR RD/WR RD/WR SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 MD2/RXD2 I IRL0 IRL1 IRL2 IRL3 NMI XTAL2 EXTAL2 VSS-RTC VDD-RTC CA VDDQ CTS2 TCLK MD8/RTS2 VDDQ VSSQ MD7/TXD SCK2/ MRESET VDD I I I I I O I Power RTC GND (0 V) Power RTC VDD (3.3 V) I Hardware standby request Power IO VDD (3.3 V) I/O I/O I/O SCIF data control (CTS) RTC/TMU clock Mode/SCIF data MD8 control (RTS) RTS2 RTS2 RTS2 RTS2 RTS2 Power IO VDD (3.3 V) Power IO GND (0 V) I/O I Mode/SCI1 data MD7 output SCIF clock/ manual reset TXD TXD SCK2 TXD SCK2 TXD SCK2 TXD SCK2 MRESET SCK2 Power Internal VDD (1.5 V) Rev.7.00 Oct. 10, 2008 Page 38 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 198 D11 199 C11 200 F12 201 B11 202 E11 203 A11 204 F11 205 C10 206 D10 207 A10 208 E10 209 B10 210 F10 211 C9 212 E9 213 A9 214 F9 215 D9 216 B9 217 F8 218 A8 219 E8 220 C8 221 D8 222 B8 223 F7 224 A7 225 E7 226 C7 Memory Interface Pin Name VSS A18 A19 VDDQ VSSQ A20 A21 A22 A23 VDDQ VSSQ A24 A25 MD3/CE2A MD4/CE2B VDDQ VSSQ MD5/RAS2 DACK0 DACK1 A0 VDDQ VSSQ A1 STATUS0 STATUS1 MD6/ IOIS16 VDDQ VSSQ I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX Power Internal GND (0 V) O O Address Address Power IO VDD (3.3 V) Power IO GND (0 V) O O O O Address Address Address Address Power IO VDD (3.3 V) Power IO GND (0 V) O O I/O I/O Address Address Mode/ PCMCIA-CE Mode/ PCMCIA-CE MD3 MD4 CE2A CE2B Power IO VDD (3.3 V) Power IO GND (0 V) I/O O O O Mode/RAS (DRAM) DMAC0 bus acknowledge DMAC1 bus acknowledge Address MD5 RAS2 Power IO VDD (3.3 V) Power IO GND (0 V) O O O I Address Status Status Mode/IOIS16 (PCMCIA) MD6 IOIS16 Power IO VDD (3.3 V) Power IO GND (0 V) Rev.7.00 Oct. 10, 2008 Page 39 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 227 E6 Memory Interface Pin Name ASEBRK/ BRKACK TDO VDD VSS TMS TCK TDI TRST I/O I/O Function Pin break/ acknowledge (H-UDI) Data out (H-UDI) Reset SRAM DRAM SDRAM PCMCIA MPX 228 A6 229 D7 230 B7 231 E5 232 C6 233 D6 234 A5 235 D5 236 B6 237 C3 238 C5 239 C4 240 A4 241 A1 242 A2 243 A3 244 B3 245 B4 246 B5 247 B14 248 B15 249 B16 250 C1 251 C17 252 D1 253 D2 254 D16 255 E16 O Power Internal VDD (1.5 V) Power Internal GND (0 V) I I I I Mode (H-UDI) Clock (H-UDI) Data in (H-UDI) Reset (H-UDI) CKIO2, RD2, RD/WR2 enable CKIO2ENB I VDD-PLL2 VSS-PLL2 VDD-PLL1 VSS-PLL1 VDD-CPG VSS-CPG XTAL EXTAL NC-1 NC-2 NC-3 NC-4 NC-5 NC-6 NC-7 NC-8 NC-9 NC-10 NC-11 NC-12 Power PLL2 VDD (3.3V) Power PLL2 GND (0V) Power PLL1 VDD (3.3V) Power PLL1 GND (0V) Power CPG VDD (3.3V) Power CPG GND (0V) O I Crystal resonator External clock/ crystal resonator Rev.7.00 Oct. 10, 2008 Page 40 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 256 M7 257 N2 258 P2 259 P16 260 R17 261 T4 262 T14 263 U3 264 U4 Memory Interface Pin Name NC-13 NC-14 NC-15 NC-16 NC-17 NC-18 NC-19 NC-20 NC-21 I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX Legend: I: Input O: Output I/O: Input/output Power: Power supply Notes: Supply power to all power pins. For the SH7750S, supply power to RTC at a minimum in hardware standby mode. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the onchip crystal oscillation circuit is used. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the onchip RTC is used. NC pins must be left completely open, and not connected to a power supply, GND, etc. * CKIO2 is not connected to PLL2. Rev.7.00 Oct. 10, 2008 Page 41 of 1074 REJ09B0366-0700 Section 1 Overview 1.4.4 Table 1.5 Pin No. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 B2 B1 C2 C1 D3 D2 D1 E3 E4 E2 F3 F4 E1 F2 G3 G4 F1 G2 H3 H4 G1 H2 H1 J2 J3 J4 J1 K2 K1 Pin Functions (292-Pin BGA) Pin Functions Memory Interface Pin Name RDY RESET CS0 CS1 CS4 CS5 CS6 BS VSS RD2 VDDQ VSS D47 D32 VDD VSS D46 D33 VDDQ VSS D45 D34 D44 D35 VDDQ VSS D43 D36 D42 I/O I I O O O O O O Function Bus ready Reset Chip select 0 Chip select 1 Chip select 4 Chip select 5 Chip select 6 Bus start RD/CASS/ FRAME CS0 CS1 CS4 CS5 CS6 (BS) OE (BS) (BS) CAS CE1A CE1B (BS) OE Reset SRAM RDY DRAM SDRAM PCMCIA MPX RDY RESET CS0 CS1 CS4 CS5 CS6 (BS) FRAME RDY Power GND (0 V) O Power IO VDD (3.3 V) Power GND (0 V) I/O I/O Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power Internal VDD Power GND (0 V) I/O I/O Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power GND (0 V) I/O I/O I/O I/O Data/port Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power GND (0 V) I/O I/O I/O Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Rev.7.00 Oct. 10, 2008 Page 42 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 L3 K3 K4 L2 L1 M2 M1 M3 L4 N2 N1 P2 P1 N3 M4 R2 R1 P3 P4 T2 T1 R3 R4 U3 U2 U1 V2 T3 T4 V1 W2 W1 Memory Interface Pin Name D37 VDDQ VSS D41 D38 D40 D39 VDDQ VSS D15 D0 D14 D1 VDDQ VSS D13 D2 VDD VSS D12 D3 VDDQ VSS D11 D4 D10 D5 VDDQ VSS D9 D6 BACK/ BSREQ I/O I/O Function Data/port Reset SRAM (Port) DRAM (Port) SDRAM PCMCIA MPX (Port) (Port) (Port) Power IO VDD (3.3 V) Power GND (0 V) I/O I/O I/O I/O Data/port Data/port Data/port Data/port (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) (Port) Power IO VDD (3.3 V) Power GND (0 V) I/O I/O I/O I/O Data Data Data Data A15 A0 A14 A1 Power IO VDD (3.3 V) Power GND (0 V) I/O I/O Data Data A13 A2 Power Internal VDD Power GND (0 V) I/O I/O Data Data A12 A3 Power IO VDD (3.3 V) Power GND (0 V) I/O I/O I/O I/O Data Data Data Data A11 A4 A10 A5 Power IO VDD (3.3 V) Power GND (0 V) I/O I/O O Data Data Bus acknowledge/ bus request A9 A6 Rev.7.00 Oct. 10, 2008 Page 43 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Y1 Y2 V3 W3 V5 U5 Y3 V4 W4 Y4 W5 V6 U6 Y5 W6 V7 U7 Y6 W7 V8 U8 U4 Y7 W8 Y8 V9 U9 W9 Y9 Memory Interface Pin Name BREQ/ BSACK D8 D7 CKE VDDQ VSS I/O I I/O I/O O Function Bus request/ bus acknowledge Data Data Clock output enable CKE A8 A7 Reset SRAM DRAM SDRAM PCMCIA MPX Power IO VDD (3.3 V) Power GND (0 V) D47–D40 select signal D39–D32 select signal D15–D8 select signal D7–D0 select signal Address WE5 WE4 WE1 WE0 CAS5 CAS4 CAS1 CAS0 DQM5 DQM4 DQM1 DQM0 WE1 WE5/CAS5/ O DQM5 WE4/CAS4/ O DQM4 WE1/CAS1/ O DQM1 WE0/CAS0/ O DQM0 A17 VDDQ VSS A16 A15 VDD VSS A14 A13 VDDQ VSS VSS A12 A11 A10 VDDQ VSS A9 A8 O Power IO VDD (3.3 V) Power GND (0 V) O O Address Address Power Internal VDD Power GND (0 V) O O Address Address Power IO VDD (3.3 V) Power GND (0 V) Power GND (0 V) O O O Address Address Address Power IO VDD (3.3 V) Power GND (0 V) O O Address Address Rev.7.00 Oct. 10, 2008 Page 44 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 91 92 93 94 95 96 97 98 99 Memory Interface Pin Name I/O O O Function Address Clock output CKIO CKIO CKIO Reset SRAM DRAM SDRAM PCMCIA MPX W10 A7 Y10 V10 U10 V11 CKIO VDDQ VSS CKIO2 Power IO VDD (3.3 V) Power GND (0 V) O O O O CKIO* Address Address Address CKIO CKIO CKIO W11 A6 Y11 A5 W12 A4 V12 VDDQ VSS A3 Power IO VDD (3.3 V) Power GND (0 V) O O O Address Address DMAC1 request acknowledge DMAC0 request acknowledge 100 U12 101 Y12 102 W13 A2 103 Y13 DRAK1 O 104 W14 DRAK0 105 V13 106 U13 107 Y14 VDDQ VSS CS3 Power IO VDD (3.3 V) Power GND (0 V) O O Chip select 3 Chip select 2 CS3 CS2 (CS3) (CS2) CS3 CS2 CS3 CS2 108 W15 CS2 109 V14 110 U14 111 Y15 VDD VSS RAS Power Internal VDD Power GND (0 V) O O RAS Read/CAS/ FRAME OE RAS RAS CAS OE FRAME 112 W16 RD/CASS/ FRAME 113 V15 114 U15 115 Y16 116 V17 VDDQ VSS RD/WR Power IO VDD (3.3 V) Power GND (0 V) O Read/write D23–D16 select signal D31–D24 select signal D55–D48 select signal RD/WR RD/WR RD/WR RD/WR WE2 CAS2 DQM2 ICIORD RD/WR WE2/CAS2/ O DQM2/ ICIORD 117 W17 WE3/CAS3/ O DQM3/ ICIOWR 118 Y17 WE6/CAS6/ O DQM6 WE3 CAS3 DQM3 ICIOWR WE6 CAS6 DQM6 Rev.7.00 Oct. 10, 2008 Page 45 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 119 V16 120 U16 121 V18 Memory Interface Pin Name VDDQ VSS I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX Power IO VDD (3.3 V) Power GND (0 V) D63–D56 select signal Data Data Data SCI data input Request from DMAC0 Request from DMAC1 Data A25 WE7 CAS7 DQM7 REG A23 A24 A22 WE7/CAS7/ O DQM7/REG I/O I/O I/O I I I I/O 122 W18 D23 123 Y18 124 Y19 125 Y20 D24 D22 RXD 126 W19 DREQ0 127 W20 DREQ1 128 V19 129 T18 130 T17 131 V20 132 U18 133 U19 134 U20 135 R18 136 R17 137 T19 138 T20 139 P18 140 P17 141 R19 142 R20 143 N18 144 N17 145 P19 146 P20 147 N19 148 N20 D25 VDDQ VSS D21 D26 D20 D27 VDDQ VSS D19 D28 VDD VSS D18 D29 VDDQ VSS D17 D30 D16 D31 Power IO VDD (3.3 V) Power GND (0 V) I/O I/O I/O I/O Data Data Data Data A20 A21 Power IO VDD (3.3 V) Power GND (0 V) I/O I/O Data Data A19 Power Internal VDD Power GND (0 V) I/O I/O Data Data A18 Power IO VDD (3.3 V) Power GND (0 V) I/O I/O I/O I/O Data Data Data Data A16 A17 149 M18 VDDQ Power IO VDD (3.3 V) Rev.7.00 Oct. 10, 2008 Page 46 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. Memory Interface Pin Name I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX 150 M17 VSS 151 M19 D55 152 M20 D56 153 L19 154 L20 155 L18 156 L17 157 K18 158 K19 159 K20 160 J19 161 J18 162 K17 163 J20 164 H19 165 H20 D54 D57 VDDQ VSS D53 D58 D52 D59 VDDQ VSS D51 D60 D50 Power GND (0 V) I/O I/O I/O I/O Data Data Data Data Power IO VDD (3.3 V) Power GND (0 V) I/O I/O I/O I/O Data Data Data Data Power IO VDD (3.3 V) Power GND (0 V) I/O I/O I/O I/O Data/port Data Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE0 (Port) (Port) (Port) (Port) (Port) 166 G19 D61 167 H18 168 J17 VDDQ VSS Power IO VDD (3.3 V) Power GND (0 V) I/O I/O Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE1 169 G20 D49 170 F19 D62 171 G18 VDD 172 G17 VSS 173 F20 174 E18 175 F18 176 F17 177 E17 178 E19 179 E20 180 D18 181 D19 D48 D63 VDDQ VSS VSS RD/WR2 MD0/SCK MD1/TXD2 Power Internal VDD Power GND (0 V) I/O I/O Data/port Data (Port) (Port) (Port) (Port) (Port) ACCSIZE2 Power IO VDD (3.3 V) Power GND (0 V) Power GND (0 V) O I/O I/O RD/WR Mode/SCI Clock MD0 Mode/SCIF data MD1 output Mode/SCIF data MD2 input RD/WR RD/WR RD/WR RD/WR SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 SCK TXD2 RXD2 RD/WR SCK TXD2 RXD2 MD2/RXD2 I Rev.7.00 Oct. 10, 2008 Page 47 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 182 D20 183 C19 184 C20 185 B19 186 B20 187 A20 188 A19 189 B18 190 A18 191 D17 192 C17 193 C18 194 B17 195 A17 196 C16 197 C15 198 D15 199 B16 200 A16 201 C14 202 D14 203 B15 204 A15 205 C13 206 D13 207 B14 208 A14 209 B13 Memory Interface Pin Name IRL0 IRL1 IRL2 IRL3 NMI XTAL2 EXTAL2 VSS-RTC VDD-RTC CA VDDQ VSS-RTC CTS2 TCLK MD8/RTS2 VDDQ VSS MD7/TXD SCK2/ MRESET VDD VSS A18 A19 VDDQ VSS A20 A21 A22 I/O I I I I I O I Function Interrupt 0 Interrupt 1 Interrupt 2 Interrupt 3 Nonmaskable interrupt RTC crystal resonator pin RTC crystal resonator pin Reset SRAM DRAM SDRAM PCMCIA MPX Power RTC GND (0 V) Power RTC VDD (3.3 V) I Hardware standby Power IO VDD (3.3 V) Power RTC GND (0 V) I/O I/O I/O SCIF data control (CTS) RTC/TMU clock Mode/SCIF data MD8 control (RTS) RTS2 RTS2 RTS2 RTS2 RTS2 Power IO VDD (3.3 V) Power GND (0 V) I/O I Mode/SCI1 data MD7 output SCIF clock/ manual reset TXD TXD SCK2 TXD SCK2 TXD SCK2 TXD SCK2 MRESET SCK2 Power Internal VDD Power GND (0 V) O O Address Address Power IO VDD (3.3 V) Power GND (0 V) O O O Address Address Address Rev.7.00 Oct. 10, 2008 Page 48 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 210 A13 211 C12 212 D12 213 B12 214 A12 215 B11 216 A11 217 C11 218 D11 219 C10 220 B10 221 A10 222 B9 223 C8 224 D8 225 A9 226 B8 227 A8 228 B7 229 C9 230 D9 231 A7 Memory Interface Pin Name A23 VDDQ VSS A24 A25 MD3/CE2A MD4/CE2B VDDQ VSS MD5/RAS2 DACK0 DACK1 A0 VDDQ VSS A1 STATUS0 STATUS1 I/O O Function Address Reset SRAM DRAM SDRAM PCMCIA MPX Power IO VDD (3.3 V) Power GND (0 V) O O I/O I/O Address Address Mode/ PCMCIA-CE Mode/ PCMCIA-CE MD3 MD4 CE2A CE2B Power IO VDD (3.3 V) Power GND (0 V) I/O O O O Mode/RAS (DRAM) DMAC0 bus acknowledge DMAC1 acknowledge Address MD5 RAS2 Power IO VDD (3.3 V) Power GND (0 V) O O O Address Status Status Mode/IOIS16 (PCMCIA) MD6 IOIS16 MD6/IOIS16 I VDDQ VSS ASEBRK/ BRKACK TDO VDD VSS TMS TCK TDI Power IO VDD (3.3 V) Power GND (0 V) I/O Pin break/ acknowledge (H-UDI) Data out (H-UDI) 232 C6 233 C7 234 D7 235 B6 236 A6 237 C5 O Power Internal VDD Power GND (0 V) I I I Mode (H-UDI) Clock (H-UDI) Data in (H-UDI) Rev.7.00 Oct. 10, 2008 Page 49 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 238 B5 239 C4 240 D6 241 A5 242 B4 243 A4 244 C3 245 B3 246 A3 247 A2 248 A1 249 N4 250 U11 251 U17 252 H17 253 D16 254 D10 255 D5 256 D4 257 H8 258 J8 259 K8 260 L8 261 M8 262 N8 263 N9 264 N10 265 N11 266 N12 267 N13 Memory Interface Pin Name TRST I/O I Function Reset (H-UDI) CKIO2, RD2, RD/WR2 enable Reset SRAM DRAM SDRAM PCMCIA MPX CKIO2ENB I VSS VDD-PLL2 VSS-PLL2 VDD-PLL1 VSS-PLL1 VDD-CPG VSS-CPG XTAL EXTAL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Power GND (0 V) Power PLL2 VDD (3.3 V) Power PLL2 GND (0 V) Power PLL1 VDD (3.3 V) Power PLL1 GND (0 V) Power CPG VDD (3.3 V) Power CPG GND (0 V) O I Crystal resonator External clock/ crystal resonator Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) 268 M13 VSS Rev.7.00 Oct. 10, 2008 Page 50 of 1074 REJ09B0366-0700 Section 1 Overview Pin No. No. 269 L13 270 K13 271 J13 272 H13 273 H12 274 H11 275 H10 276 H9 277 J9 278 K9 279 L9 280 M9 Memory Interface Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS I/O Function Reset SRAM DRAM SDRAM PCMCIA MPX Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) Power GND (0 V) 281 M10 VSS 282 M11 VSS 283 M12 VSS 284 L12 285 K12 286 J12 287 J11 288 J10 289 K10 290 L10 291 L11 292 K11 VSS VSS VSS VSS VSS VSS VSS VSS VSS Legend: I: Input O: Output I/O: Input/output Power: Power supply Notes: Supply power to all power pins. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the onchip crystal oscillation circuit is used. Rev.7.00 Oct. 10, 2008 Page 51 of 1074 REJ09B0366-0700 Section 1 Overview Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the onchip RTC is used. NC pins must be left completely open, and not connected to a power supply, GND, etc. * CKIO2 is not connected to PLL2. Rev.7.00 Oct. 10, 2008 Page 52 of 1074 REJ09B0366-0700 Section 2 Programming Model Section 2 Programming Model 2.1 Data Formats The data formats handled by the SH-4 are shown in figure 2.1. 7 Byte (8 bits) 15 Word (16 bits) 31 Longword (32 bits) 31 30 Single-precision floating-point (32 bits) 63 62 Double-precision floating-point (64 bits) s exp 51 fraction s exp 22 fraction 0 0 0 0 0 Figure 2.1 Data Formats Rev.7.00 Oct. 10, 2008 Page 53 of 1074 REJ09B0366-0700 Section 2 Programming Model 2.2 2.2.1 Register Configuration Privileged Mode and Banks Processor Modes: The SH-4 has two processor modes, user mode and privileged mode. The SH-4 normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be accessed differ in the two processor modes. General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers which are switched by a processor mode change. In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (LDC) and store control register (STC) instructions. When the RB bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC/STC instructions. When the RB bit is 0 (that is, when bank 0 is selected), the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 are accessed by the LDC/STC instructions. In user mode, the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. The eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 cannot be accessed. Control Registers: Control registers comprise the global base register (GBR) and status register (SR), which can be accessed in both processor modes, and the saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug base register (DBR), which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. System Registers: System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure register (PR), the program counter (PC), the floating-point status/control register (FPSCR), and the floating-point communication register (FPUL). Access to these registers does not depend on the processor mode. Rev.7.00 Oct. 10, 2008 Page 54 of 1074 REJ09B0366-0700 Section 2 Programming Model Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floatingpoint registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX. Register values after a reset are shown in table 2.1. Table 2.1 Type General registers Initial Register Values Registers R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, R8–R15 SR Initial Value* Undefined Control registers MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, IMASK = 1111 (H'F), reserved bits = 0, others undefined Undefined H'00000000 Undefined H'A0000000 H'00040001 Undefined GBR, SSR, SPC, SGR, DBR VBR System registers MACH, MACL, PR, FPUL PC FPSCR Floating-point registers Note: * FR0–FR15, XF0–XF15 Initialized by a power-on reset and manual reset. The register configuration in each processor is shown in figure 2.2. Switching between user mode and privileged mode is controlled by the processor mode bit (MD) in the status register. Rev.7.00 Oct. 10, 2008 Page 55 of 1074 REJ09B0366-0700 Section 2 Programming Model 31 R0_BANK0*1 *2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 SR 0 31 R0_BANK1*1 *3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC SGR DBR R0_BANK0*1 *4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 (b) Register configuration in privileged mode (RB = 1) 0 31 R0_BANK0*1 *4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC SGR DBR R0_BANK1*1 *3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 (c) Register configuration in privileged mode (RB = 0) 0 GBR MACH MACL PR PC (a) Register configuration in user mode Notes: 1. The R0 register is used as the index register in indexed register-indirect addressing mode and indexed GBR indirect addressing mode. 2. Banked registers 3. Banked registers Accessed as general registers when the RB bit is set to 1 in the SR register. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. 4. Banked registers Accessed as general registers when the RB bit is cleared to 0 in the SR register. Accessed only by LDC/STC instructions when the RB bit is set to 1. Figure 2.2 CPU Register Configuration in Each Processor Mode Rev.7.00 Oct. 10, 2008 Page 56 of 1074 REJ09B0366-0700 Section 2 Programming Model 2.2.2 General Registers Figure 2.3 shows the relationship between the processor modes and general registers. The SH-4 has twenty-four 32-bit general registers (R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0–R15 in one processor mode. The SH-4 has two processor modes, user mode and privileged mode, in which R0–R7 are assigned as shown below. • R0_BANK0–R7_BANK0 In user mode (SR.MD = 0), R0–R7 are always assigned to R0_BANK0–R7_BANK0. In privileged mode (SR.MD = 1), R0–R7 are assigned to R0_BANK0–R7_BANK0 only when SR.RB = 0. • R0_BANK1–R7_BANK1 In user mode, R0_BANK1–R7_BANK1 cannot be accessed. In privileged mode, R0–R7 are assigned to R0_BANK1–R7_BANK1 only when SR.RB = 1. Rev.7.00 Oct. 10, 2008 Page 57 of 1074 REJ09B0366-0700 Section 2 Programming Model SR.MD = 0 or (SR.MD = 1, SR.RB = 0) R0 R1 R2 R3 R4 R5 R6 R7 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15 (SR.MD = 1, SR.RB = 1) R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Figure 2.3 General Registers Programming Note: As the user's R0–R7 are assigned to R0_BANK0–R7_BANK0, and after an exception or interrupt R0–R7 are assigned to R0_BANK1–R7_BANK1, it is not necessary for the interrupt handler to save and restore the user's R0–R7 (R0_BANK0–R7_BANK0). After a reset, the values of R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15 are undefined. Rev.7.00 Oct. 10, 2008 Page 58 of 1074 REJ09B0366-0700 Section 2 Programming Model 2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4). • Floating-point registers, FPRn_BANKi (32 registers) FPR0_BANK0, FPR1_BANK0, FPR2_BANK0, FPR3_BANK0, FPR4_BANK0, FPR5_BANK0, FPR6_BANK0, FPR7_BANK0, FPR8_BANK0, FPR9_BANK0, FPR10_BANK0, FPR11_BANK0, FPR12_BANK0, FPR13_BANK0, FPR14_BANK0, FPR15_BANK0 FPR0_BANK1, FPR1_BANK1, FPR2_BANK1, FPR3_BANK1, FPR4_BANK1, FPR5_BANK1, FPR6_BANK1, FPR7_BANK1, FPR8_BANK1, FPR9_BANK1, FPR10_BANK1, FPR11_BANK1, FPR12_BANK1, FPR13_BANK1, FPR14_BANK1, FPR15_BANK1 • Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0–FR15 are assigned to FPR0_BANK0–FPR15_BANK0. When FPSCR.FR = 1, FR0–FR15 are assigned to FPR0_BANK1–FPR15_BANK1. • Double-precision floating-point registers or single-precision floating-point register pairs, DRi (8 registers): A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15} • Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises four FR registers FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7}, FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15} • Single-precision floating-point extended registers, XFi (16 registers) When FPSCR.FR = 0, XF0–XF15 are assigned to FPR0_BANK1–FPR15_BANK1. When FPSCR.FR = 1, XF0–XF15 are assigned to FPR0_BANK0–FPR15_BANK0. Rev.7.00 Oct. 10, 2008 Page 59 of 1074 REJ09B0366-0700 Section 2 Programming Model • Single-precision floating-point extended register pairs, XDi (8 registers): An XD register comprises two XF registers XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15} • Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 Rev.7.00 Oct. 10, 2008 Page 60 of 1074 REJ09B0366-0700 Section 2 Programming Model FPSCR.FR = 0 FV0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 DR0 XF0 XF1 XD2 XF2 XF3 XD4 XF4 XF5 XD6 XF6 XF7 XD8 XF8 XF9 XD10 XF10 XF11 XD12 XF12 XF13 XD14 XF14 XF15 XD0 FPR0_BANK0 FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 FPR11_BANK0 FPR12_BANK0 FPR13_BANK0 FPR14_BANK0 FPR15_BANK0 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 FPSCR.FR = 1 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 XMTRX FV4 FV8 FV12 XMTRX DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 Figure 2.4 Floating-Point Registers Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. Rev.7.00 Oct. 10, 2008 Page 61 of 1074 REJ09B0366-0700 Section 2 Programming Model 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X: undefined)) 31 30 29 28 27 — MD RB BL — 16 15 14 FD — 10 9 M 8 Q 7 IMASK 4 3 — 2 1 S 0 T Note: —: Reserved. These bits are always read as 0, and should only be written with 0. • MD: Processor mode MD = 0: User mode (some instructions cannot be executed, and some resources cannot be accessed) MD = 1: Privileged mode • RB: General register bank specifier in privileged mode (set to 1 by a reset, exception, or interrupt) RB = 0: R0_BANK0–R7_BANK0 are accessed as general registers R0–R7. (R0_BANK1– R7_BANK1 can be accessed using LDC/STC R0_BANK–R7_BANK instructions.) RB = 1: R0_BANK1–R7_BANK1 are accessed as general registers R0–R7. (R0_BANK0– R7_BANK0 can be accessed using LDC/STC R0_BANK–R7_BANK instructions.) • BL: Exception/interrupt block bit (set to 1 by a reset, exception, or interrupt) BL = 1: Interrupt requests are masked. If a general exception other than a user break occurs while BL = 1, the processor switches to the reset state. • FD: FPU disable bit (cleared to 0 by a reset) FD = 1: An FPU instruction causes a general FPU disable exception, and if the FPU instruction is in a delay slot, a slot FPU disable exception is generated. (FPU instructions: H'F*** instructions, LDC(.L)/STS(.L) instructions for FPUL/FPSCR) • M, Q: Used by the DIV0S, DIV0U, and DIV1 instructions. • IMASK: Interrupt mask level External interrupts of a same level or a lower level than IMASK are masked. • S: Specifies a saturation operation for a MAC instruction. • T: True/false condition or carry/borrow bit Rev.7.00 Oct. 10, 2008 Page 62 of 1074 REJ09B0366-0700 Section 2 Programming Model Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC. Global base register, GBR (32 bits, initial value undefined): GBR is referenced as the base address in a GBR-referencing MOV instruction. Vector base register, VBR (32 bits, privilege protection, initial value = H'0000 0000): VBR is referenced as the branch destination base address in the event of an exception or interrupt. For details, see section 5, Exceptions. Saved general register 15, SGR (32 bits, privilege protection, initial value undefined): The contents of R15 are saved to SGR in the event of an exception or interrupt. Debug base register, DBR (32 bits, privilege protection, initial value undefined): When the user break debug function is enabled (BRCR.UBDE = 1), DBR is referenced as the user break handler branch destination address instead of VBR. 2.2.5 System Registers Multiply-and-accumulate register high, MACH (32 bits, initial value undefined) Multiply-and-accumulate register low, MACL (32 bits, initial value undefined) MACH/MACL is used for the added value in a MAC instruction, and to store a MAC instruction or MUL operation result. Procedure register, PR (32 bits, initial value undefined): The return address is stored in PR in a subroutine call using a BSR, BSRF, or JSR instruction, and PR is referenced by the subroutine return instruction (RTS). Program counter, PC (32 bits, initial value = H'A000 0000): PC indicates the instruction fetch address. Rev.7.00 Oct. 10, 2008 Page 63 of 1074 REJ09B0366-0700 Section 2 Programming Model Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 31 — 22 21 20 19 18 17 FR SZ PR DN Cause 12 11 Enable 7 6 Flag 2 1 RM 0 Note: —: Reserved. These bits are always read as 0, and should only be written with 0. • FR: Floating-point register bank FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15; FPR0_BANK1– FPR15_BANK1 are assigned to XF0–XF15. FR = 1: FPR0_BANK0–FPR15_BANK0 are assigned to XF0–XF15; FPR0_BANK1– FPR15_BANK1 are assigned to FR0–FR15. • SZ: Transfer size mode SZ = 0: The data size of the FMOV instruction is 32 bits. SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits). • PR: Precision mode PR = 0: Floating-point instructions are executed as single-precision operations. PR = 1: Floating-point instructions are executed as double-precision operations (the result of instructions for which double-precision is not supported is undefined). Do not set SZ and PR to 1 simultaneously; this setting is reserved. [SZ, PR = 11]: Reserved (FPU operation instruction is undefined.) • DN: Denormalization mode DN = 0: A denormalized number is treated as such. DN = 1: A denormalized number is treated as zero. • Cause: FPU exception cause field • Enable: FPU exception enable field • Flag: FPU exception flag field FPU Error (E) Cause Enable Flag FPU exception cause field FPU exception enable field FPU exception flag field Bit 17 None None Invalid Division Operation (V) by Zero (Z) Bit 16 Bit 11 Bit 6 Bit 15 Bit 10 Bit 5 Overflow Underflow Inexact (O) (U) (I) Bit 14 Bit 9 Bit 4 Bit 13 Bit 8 Bit 3 Bit 12 Bit 7 Bit 2 Rev.7.00 Oct. 10, 2008 Page 64 of 1074 REJ09B0366-0700 Section 2 Programming Model When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared. • RM: Rounding mode RM = 00: Round to Nearest RM = 01: Round to Zero RM = 10: Reserved RM = 11: Reserved • Bits 22 to 31: Reserved Floating-point communication register, FPUL (32 bits, initial value undefined): Data transfer between FPU registers and CPU registers is carried out via the FPUL register. Programming Note: When SZ = 1 and big endian mode is selected, FMOV can be used for double-precision floating-point load or store operations. In little endian mode, two 32-bit data size moves must be executed, with SZ = 0, to load or store a double-precision floating-point number. 2.3 Memory-Mapped Registers Appendix A, Address List shows the control registers mapped to memory. The control registers are double-mapped to the following two memory areas. All registers have two addresses. H'1C00 0000–H'1FFF FFFF H'FC00 0000–H'FFFF FFFF These two areas are used as follows. • H'1C00 0000–H'1FFF FFFF This area must be accessed using the address translation function of the MMU. Setting the page number of this area to the corresponding filed of the TLB enables access to a memorymapped register. Accessing this area without using the address translation function of the MMU is not guaranteed. • H'FC00 0000–H'FFFF FFFF Access to area H'FF00 0000–H'FFFF FFFF in user mode will cause an address error. Memorymapped registers can be referenced in user mode by means of access that involves address translation. Rev.7.00 Oct. 10, 2008 Page 65 of 1074 REJ09B0366-0700 Section 2 Programming Model Note: Do not access undefined locations in either area The operation of an access to an undefined location is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined. 2.4 Data Format in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 Longword 0 2.5 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being loaded into a register. A word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). An address error will result if this rule is not observed. A byte operand can be accessed from any address. Big endian or little endian byte order can be selected for the data format. The endian should be set with the MD5 external pin in a power-on reset. Big endian is selected when the MD5 pin is low, and little endian when high. The endian cannot be changed dynamically. Bit positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. The data format in memory is shown in figure 2.5. Rev.7.00 Oct. 10, 2008 Page 66 of 1074 REJ09B0366-0700 Section 2 Programming Model A 31 7 07 A+1 23 07 A+2 15 7 07 A+3 0 0 A + 11 A + 10 A + 9 31 7 23 07 15 07 7 07 A+8 0 0 Address A Byte 0 Byte 1 Byte 2 Byte 3 Address A + 4 Address A + 8 15 0 15 Byte 3 Byte 2 Byte 1 Byte 0 Address A + 8 0 15 0 0 15 Word 0 31 Word 1 0 31 Word 1 Word 0 0 Address A + 4 Address A Longword Big endian Longword Little endian Figure 2.5 Data Formats In Memory Note: The SH-4 does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed. 2.6 Processor States The SH-4 has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The reset state is entered when the RESET pin goes low. The CPU enters the power-on reset state if the MRESET pin is high, and the manual reset state if the MRESET pin is low. For more information on resets, see section 5, Exceptions. In the power-on reset state, the internal state of the CPU and the on-chip peripheral module registers are initialized. In the manual reset state, the internal state of the CPU and registers of onchip peripheral modules other than the bus state controller (BSC) are initialized. Since the bus state controller (BSC) is not initialized in the manual reset state, refreshing operations continue. Refer to the register configurations in the relevant sections for further details. Exception-Handling State: This is a transient state during which the CPU's processor state flow is altered by a reset, general exception, or interrupt exception handling source. In the case of a reset, the CPU branches to address H'A000 0000 and starts executing the usercoded exception handling program. In the case of a general exception or interrupt, the program counter (PC) contents are saved in the saved program counter (SPC), the status register (SR) contents are saved in the saved status register (SSR), and the R15 contents are saved in saved general register 15 (SGR). The CPU branches to the start address of the user-coded exception service routine found from the sum of the Rev.7.00 Oct. 10, 2008 Page 67 of 1074 REJ09B0366-0700 Section 2 Programming Model contents of the vector base address and the vector offset. See section 5, Exceptions, for more information on resets, general exceptions, and interrupts. Program Execution State: In this state the CPU executes program instructions in sequence. Power-Down State: In the power-down state, CPU operation halts and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. There are two modes in the power-down state: sleep mode and standby mode. For details, see section 9, Power-Down Modes. Bus-Released State: In this state the CPU has released the bus to a device that requested it. Transitions between the states are shown in figure 2.6. From any state when RESET = 0 and MRESET = 1 RESET = 0 and MRESET = 0 Power-on reset state RESET = 0, MRESET = 1 Manual reset state Reset state RESET = 1, MRESET = 0 RESET = 1, MRESET = 1 Exception-handling state Bus request Bus request clearance Exception interrupt End of exception transition processing Interrupt Interrupt Bus-released state Bus request Bus request Bus request clearance Bus request clearance Program execution state SLEEP instruction with STBY bit set SLEEP instruction with STBY bit cleared Sleep mode Standby mode Power-down state Figure 2.6 Processor State Transitions Rev.7.00 Oct. 10, 2008 Page 68 of 1074 REJ09B0366-0700 Section 2 Programming Model 2.7 Processor Modes There are two processor modes: user mode and privileged mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset state or exception state is entered, the MD bit is set to 1. There are certain registers and bits which can only be accessed in privileged mode. Rev.7.00 Oct. 10, 2008 Page 69 of 1074 REJ09B0366-0700 Section 2 Programming Model Rev.7.00 Oct. 10, 2008 Page 70 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) Section 3 Memory Management Unit (MMU) 3.1 3.1.1 Overview Features The SH-4 can handle 29-bit external memory space from an 8-bit address space identifier and 32bit logical (virtual) address space. Address translation from virtual address to physical address is performed using the memory management unit (MMU) built into the SH-4. The MMU performs high-speed address translation by caching user-created address translation table information in an address translation buffer (translation lookaside buffer: TLB). The SH-4 has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with support for four page sizes (1, 4, and 64 Kbytes, and 1 Mbyte). It is possible to set the virtual address space access right and implement storage protection independently for privileged mode and user mode. 3.1.2 Role of the MMU The MMU was conceived as a means of making efficient use of physical memory. As shown in figure 3.1, when a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory, but if the process increases in size to the point where it does not fit into physical memory, it becomes necessary to divide the process into smaller parts, and map the parts requiring execution onto physical memory on an ad hoc basis ((1)). Having this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process. The virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden ((2)). With a virtual memory system, the size of the available virtual memory is much larger than the actual physical memory, and processes are mapped onto this virtual memory. Thus processes only have to consider their operation in virtual memory, and mapping from virtual memory to physical memory is handled by the MMU. The MMU is normally managed by the OS, and physical memory switching is carried out so as to enable the virtual memory required by a task to be mapped smoothly onto physical memory. Physical memory switching is performed via secondary storage, etc. The virtual memory system that came into being in this way works to best effect in a time sharing system (TSS) that allows a number of processes to run simultaneously ((3)). Running a number of processes in a TSS did not increase efficiency since each process had to take account of physical memory mapping. Efficiency is improved and the load on each process reduced by the use of a virtual memory system ((4)). In this system, virtual memory is allocated to each process. The task Rev.7.00 Oct. 10, 2008 Page 71 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) of the MMU is to map a number of virtual memory areas onto physical memory in an efficient manner. It is also provided with memory protection functions to prevent a process from inadvertently accessing another process's physical memory. When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a different process is accessed by mistake. In such cases, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could be implemented by software alone, having address translation performed by software each time a process accessed physical memory would be very inefficient. For this reason, a buffer for address translation (the translation lookaside buffer: TLB) is provided in hardware, and frequently used address translation information is placed here. The TLB can be described as a cache for address translation information. However, unlike a cache, if address translation fails—that is, if an exception occurs—switching of the address translation information is normally performed by software. Thus memory management can be performed in a flexible manner by software. There are two methods by which the MMU can perform mapping from virtual memory to physical memory: the paging method, using fixed-length address translation, and the segment method, using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space called a page (usually from 1 to 64 Kbytes in size). In the following descriptions, the address space in virtual memory in the SH-4 is referred to as virtual address space, and the address space in physical memory as physical address space. Rev.7.00 Oct. 10, 2008 Page 72 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) Physical memory Process 1 Process 1 Physical memory Process 1 Virtual memory MMU Physical memory (1) (2) Process 1 Physical memory Process 1 Virtual memory MMU Physical memory Process 2 Process 2 Process 3 Process 3 (3) (4) Figure 3.1 Role of the MMU Rev.7.00 Oct. 10, 2008 Page 73 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 Name Page table entry high register Page table entry low register Page table entry assistance register Translation table base register TLB exception address register MMU control register MMU Registers Abbreviation PTEH PTEL PTEA TTB TEA MMUCR R/W R/W R/W R/W R/W R/W R/W Initial Value*1 Undefined Undefined Undefined Undefined Undefined P4 Address*2 Area 7 Address*2 Access Size H'FF00 0000 H'1F00 0000 32 H'FF00 0004 H'1F00 0004 32 H'FF00 0034 H'1F00 0034 32 H'FF00 0008 H'1F00 0008 32 H'FF00 000C H'1F00 000C 32 H'0000 0000 H'FF00 0010 H'1F00 0010 32 Notes: 1. The initial value is the value after a power-on reset or manual reset. 2. This is the address when using the virtual/physical address space P4 area. When making an access from physical address space area 7 using the TLB, the upper 3 bits of the address are ignored. 3.1.4 Caution Operation is not guaranteed if an area designated as a reserved area in this manual is accessed. Rev.7.00 Oct. 10, 2008 Page 74 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 3.2 Register Descriptions There are six MMU-related registers. 1. PTEH 31 VPN 10 9 8 7 ASID 0 —— 2. PTEL 31 30 29 28 ——— PPN 10 9 8 7 6 5 4 3 2 1 0 — V SZ PR SZ C D SH WT 3. PTEA 31 4 3 TC 2 SA 0 4. TTB 31 TTB 0 5. TEA 31 Virtual address at which MMU exception or address error occurred 6. MMUCR 31 LRUI 26 25 24 23 —— URB 18 17 16 15 —— URC 10 9 8 7 6 5 4 3 2 1 0 SV — — — — — TI — AT SQMD Note: — indicates a reserved bit: the write value must be 0, and a read will return 0. Figure 3.2 MMU-Related Registers Rev.7.00 Oct. 10, 2008 Page 75 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by hardware. VPN varies according to the page size, but the VPN set by hardware when an exception occurs consists of the upper 22 bits of the virtual address which caused the exception. VPN setting can also be carried out by software. The number of the currently executing process is set in the ASID field by software. ASID is not updated by hardware. VPN and ASID are recorded in the UTLB by means of the LDLTB instruction. A branch to the P0, P3, or U0 area which uses the updated ASID after the ASID field in PTEH is rewritten should be made at least 6 instructions after the PTEH update instruction. 2. Page table entry low register (PTEL): Longword access to PTEL can be performed from H'FF00 0004 in the P4 area and H'1F00 0004 in area 7. PTEL is used to hold the physical page number and page management information to be recorded in the UTLB by means of the LDTLB instruction. The contents of this register are not changed unless a software directive is issued. 3. Page table entry assistance register (PTEA): Longword access to PTEA can be performed from H'FF00 0034 in the P4 area and H'1F00 0034 in area 7. PTEL is used to store assistance bits for PCMCIA access to the UTLB by means of the LDTLB instruction. When performing access from the CPU in the SH7750S and SH7750R with MMUCR.AT = 0, access is always performed using the values of the SA and TC bits in this register. In the SH7750, it is not possible to access a PCMCIA interface area with MMUCR.AT = 0. In this LSI, access to a PCMCIA interface area by the DMAC is always performed using the DMAC's CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. The contents of this register are not changed unless a software directive is issued. 4. Translation table base register (TTB): Longword access to TTB can be performed from H'FF00 0008 in the P4 area and H'1F00 0008 in area 7. TTB is used, for example, to hold the base address of the currently used page table. The contents of TTB are not changed unless a software directive is issued. This register can be freely used by software. 5. TLB exception address register (TEA): Longword access to TEA can be performed from H'FF00 000C in the P4 area and H'1F00 000C in area 7. After an MMU exception or address error exception occurs, the virtual address at which the exception occurred is set in TEA by hardware. The contents of this register can be changed by software. 6. MMU control register (MMUCR): MMUCR contains the following bits: LRUI: Least recently used ITLB URB: UTLB replace boundary Rev.7.00 Oct. 10, 2008 Page 76 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) URC: SQMD: SV: TI: AT: UTLB replace counter Store queue mode bit Single virtual mode bit TLB invalidate Address translation bit Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an instruction that performs data access to the P0, P3, U0, or store queue area should be located at least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0, P3, or U0 area should be located at least eight instructions after the MMUCR update instruction. MMUCR contents can be changed by software. The LRUI bits and URC bits may also be updated by hardware. • LRUI: Least recently used ITLB. The LRU (least recently used) method is used to decide the ITLB entry to be replaced in the event of an ITLB miss. The entry to be purged from the ITLB can be confirmed using the LRUI bits. LRUI is updated by means of the algorithm shown below. A dash in this table means that updating is not performed. LRUI [5] When ITLB entry 0 is used When ITLB entry 1 is used When ITLB entry 2 is used When ITLB entry 3 is used Other than the above 0 1 — — — [4] 0 — 1 — — [3] 0 — — 1 — [2] — 0 1 — — [1] — 0 — 1 — [0] — — 0 1 — When the LRUI bit settings are as shown below, the corresponding ITLB entry is updated by an ITLB miss. An asterisk in this table means “don't care”. Rev.7.00 Oct. 10, 2008 Page 77 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) LRUI [5] ITLB entry 0 is updated ITLB entry 1 is updated ITLB entry 2 is updated ITLB entry 3 is updated Other than the above 1 0 * * [4] 1 * 0 * [3] 1 * * 0 [2] * 1 0 * [1] * 1 * 0 [0] * * 1 0 Setting prohibited Ensure that values for which “Setting prohibited” is indicated in the above table are not set at the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0, and therefore a prohibited setting is never made by a hardware update. • URB: UTLB replace boundary. Bits that indicate the UTLB entry boundary at which replacement is to be performed. Valid only when URB > 0. • URC: UTLB replace counter. Random counter for indicating the UTLB entry for which replacement is to be performed with an LDTLB instruction. URC is incremented each time the UTLB is accessed. When URB > 0, URC is reset to 0 when the condition URC = URB occurs. Also note that, if a value is written to URC by software which results in the condition URC > URB, incrementing is first performed in excess of URB until URC = H'3F. URC is not incremented by an LDTLB instruction. • SQMD: Store queue mode bit. Specifies the right of access to the store queues. 0: User/privileged access possible 1: Privileged access possible (address error exception in case of user access) • SV: Single virtual mode bit. Bit that switches between single virtual memory mode and multiple virtual memory mode. 0: Multiple virtual memory mode 1: Single virtual memory mode When this bit is changed, ensure that 1 is also written to the TI bit. • TI: TLB invalidation bit. Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB bits. This bit always returns 0 when read. • AT: Address translation enable bit. Specifies MMU enabling or disabling. 0: MMU disabled 1: MMU enabled Rev.7.00 Oct. 10, 2008 Page 78 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) MMU exceptions are not generated when the AT bit is 0. In the case of software that does not use the MMU, therefore, the AT bit should be cleared to 0. 3.3 3.3.1 Address Space Physical Address Space The SH-4 supports a 32-bit physical address space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical address space. The physical address space is divided into a number of areas, as shown in figure 3.3. The physical address space is permanently mapped onto 29-bit external memory space; this correspondence can be implemented by ignoring the upper 3 bits of the physical address space addresses. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed. In user mode, a 2-Gbyte space in the U0 area can be accessed. Accessing the P1 to P4 areas (except the store queue area) in user mode will cause an address error. External memory space H'0000 0000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'0000 0000 P0 area Cacheable U0 area Cacheable H'8000 0000 H'A000 0000 H'C000 0000 H'E000 0000 H'FFFF FFFF P1 area Cacheable P2 area Non-cacheable Address error P3 area Cacheable P4 area Non-cacheable Privileged mode Store queue area Address error User mode H'8000 0000 H'E000 0000 H'E400 0000 H'FFFF FFFF Figure 3.3 Physical Address Space (MMUCR.AT = 0) Rev.7.00 Oct. 10, 2008 Page 79 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) In the SH7750, the CPU cannot access a PCMCIA interface area. When performing access from the CPU to a PCMCIA interface area in the SH7750S or the SH7750R, access is always performed using the values of the SA and TC bits set in the PTEA register. The PCMCIA interface area is always accessed by the DMAC with the values of CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC in the DMAC. For details, see section 14, Direct Memory Access Controller (DMAC). P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or not the cache is used is determined by the cache control register (CCR). When the cache is used, with the exception of the P1 area, switching between the copy-back method and the write-through method for write accesses is specified by the CCR.WT bit. For the P1 area, switching is specified by the CCR.CB bit. Zeroizing the upper 3 bits of an address in these areas gives the corresponding external memory space address. However, since area 7 in the external memory space is a reserved area, a reserved area also appears in these areas. P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, zeroizing the upper 3 bits of an address gives the corresponding external memory space address. However, since area 7 in the external memory space is a reserved area, a reserved area also appears in this area. P4 Area: The P4 area is mapped onto SH-4 on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4. Rev.7.00 Oct. 10, 2008 Page 80 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) H'E000 0000 H'E400 0000 Reserved area H'F000 0000 H'F100 0000 H'F200 0000 H'F300 0000 H'F400 0000 H'F500 0000 H'F600 0000 H'F700 0000 H'F800 0000 Store queue Instruction cache address array Instruction cache data array Instruction TLB address array Instruction TLB data arrays 1 and 2 Operand cache address array Operand cache data array Unified TLB address array Unified TLB data arrays 1 and 2 Reserved area H'FC00 0000 Control register area Figure 3.4 P4 Area The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues (SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the MMUCR.SQMD bit. For details, see section 4.7, Store Queues. The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache address array. For details, see section 4.5.1, IC Address Array. The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data array. For details, see section 4.5.2, IC Data Array. The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB address array. For details, see section 3.7.1, ITLB Address Array. Rev.7.00 Oct. 10, 2008 Page 81 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data arrays 1 and 2. For details, see sections 3.7.2, ITLB Data Array 1, and 3.7.3, ITLB Data Array 2. The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address array. For details, see section 4.5.3, OC Address Array. The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data array. For details, see section 4.5.4, OC Data Array. The area from H'F600 0000 to H'F6FF FFFF is used for direct access to the unified TLB address array. For details, see section 3.7.4, UTLB Address Array. The area from H'F700 0000 to H'F7FF FFFF is used for direct access to unified TLB data arrays 1 and 2. For details, see sections 3.7.5, UTLB Data Array 1, and 3.7.6, UTLB Data Array 2. The area from H'FF00 0000 to H'FFFF FFFF is the on-chip peripheral module control register area. For details, see appendix A, Address List. 3.3.2 External Memory Space The SH-4 supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State Controller (BSC). H'0000 0000 H'0400 0000 H'0800 0000 H'0C00 0000 H'1000 0000 H'1400 0000 H'1800 0000 H'1C00 0000 H'1FFF FFFF Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 (reserved area) Figure 3.5 External Memory Space Rev.7.00 Oct. 10, 2008 Page 82 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 3.3.3 Virtual Address Space Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in the SH-4 to be mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256. This is called the virtual memory space. Mapping from virtual memory space to 29-bit external memory space is carried out using the TLB. Only when area 7 in external memory space is accessed using virtual memory space, addresses H'1C00 0000 to H'1FFF FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4 area control register area in the physical memory space. Virtual memory space is illustrated in figure 3.6. 256 256 External memory space Area 0 Area 1 Area 2 P0 area Cacheable Address translation possible Area 3 Area 4 Area 5 Area 6 Area 7 U0 area Cacheable Address translation possible P1 area Cacheable Address translation not possible P2 area Non-cacheable Address translation not possible P3 area Cacheable Address translation possible P4 area Non-cacheable Address translation not possible Privileged mode Store queue area Address error User mode Address error Figure 3.6 Virtual Address Space (MMUCR.AT = 1) In the state of cache enabling, when the areas of P0, P3, and U0 are mapped onto a PCMCIA interface area by means of the TLB, it is necessary either to specify 1 for the WT bit or to specify Rev.7.00 Oct. 10, 2008 Page 83 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 0 for the C bit on that page. At that time, the regions are accessed by the values of SA and TC set in page units of the TLB. Here, access to the PCMCIA interface area by accessing an area of P1, P2, or P4 from the CPU is disabled. In addition, the PCMCIA interface area is always accessed by the DMAC with the values of CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC in the DMAC. For details, see section 14, Direct Memory Access Controller (DMAC). P0, P3, U0 Areas: The P0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF), P3 area, and U0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF) allow access using the cache and address translation using the TLB. These areas can be mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte, page units. When CCR is in the cache-enabled state and the TLB enable bit (C bit) is 1, accesses can be performed using the cache. In write accesses to the cache, switching between the copy-back method and the write-through method is indicated by the TLB write-through bit (WT bit), and is specified in page units. Only when the P0, P3, and U0 areas are mapped onto external memory space by means of the TLB, addresses H'1C00 0000 to H'1FFF FFFF of area 7 in external memory space are allocated to the control register area. This enables on-chip peripheral module control registers to be accessed from the U0 area in user mode. In this case, the C bit for the corresponding page must be cleared to 0. P1, P2, P4 Areas: Address translation using the TLB cannot be performed for the P1, P2, or P4 area (except for the store queue area). Accesses to these areas are the same as for physical memory space. The store queue area can be mapped onto any external memory space by the MMU. However, operation in the case of an exception differs from that for normal P0, U0, and P3 spaces. For details, see section 4.7, Store Queues. 3.3.4 On-Chip RAM Space In the SH-4, half of the instruction cache can be used as on-chip RAM. This can be done by changing the CCR settings. When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0 area addresses H'7C00 0000 to H'7FFF FFFF are an on-chip RAM area. Data accesses (byte/word/longword/quadword) can be used in this area. This area can only be used in RAM mode. Rev.7.00 Oct. 10, 2008 Page 84 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 3.3.5 Address Translation When the MMU is used, the virtual address space is divided into units called pages, and translation to physical addresses is carried out in these page units. The address translation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory protection codes. Fast address translation is achieved by caching the contents of the address translation table located in external memory into the TLB. In the SH-4, basically, the ITLB is used for instruction accesses and the UTLB for data accesses. In the event of an access to an area other than the P4 area, the accessed virtual address is translated to a physical address. If the virtual address belongs to the P1 or P2 area, the physical address is uniquely determined without accessing the TLB. If the virtual address belongs to the P0, U0, or P3 area, the TLB is searched using the virtual address, and if the virtual address is recorded in the TLB, a TLB hit is made and the corresponding physical address is read from the TLB. If the accessed virtual address is not recorded in the TLB, a TLB miss exception is generated and processing switches to the TLB miss exception routine. In the TLB miss exception routine, the address translation table in external memory is searched, and the corresponding physical address and page management information are recorded in the TLB. After the return from the exception handling routine, the instruction which caused the TLB miss exception is re-executed. 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems, single virtual memory and multiple virtual memory, either of which can be selected with the MMUCR.SV bit. In the single virtual memory system, a number of processes run simultaneously, using virtual address space on an exclusive basis, and the physical address corresponding to a particular virtual address is uniquely determined. In the multiple virtual memory system, a number of processes run while sharing the virtual address space, and a particular virtual address may be translated into different physical addresses depending on the process. The only difference between the single virtual memory and multiple virtual memory systems in terms of operation is in the TLB address comparison method (see section 3.4.3, Address Translation Method). 3.3.7 Address Space Identifier (ASID) In multiple virtual memory mode, the 8-bit address space identifier (ASID) is used to distinguish between processes running simultaneously while sharing the virtual address space. Software can set the ASID of the currently executing process in PTEH in the MMU. The TLB does not have to be purged when processes are switched by means of ASID. In single virtual memory mode, ASID is used to provide memory protection for processes running simultaneously while using the virtual memory space on an exclusive basis. Rev.7.00 Oct. 10, 2008 Page 85 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) Note: In single virtual memory mode, entries with the same virtual page number (VPN) but different ASIDs cannot be set in the TLB simultaneously. 3.4 3.4.1 TLB Functions Unified TLB (UTLB) Configuration The unified TLB (UTLB) is so called because of its use for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2. As a table of address translation information to be recorded in the instruction TLB in the event of an ITLB miss Information in the address translation table located in external memory is cached into the UTLB. The address translation table contains virtual page numbers and address space identifiers, and corresponding physical page numbers and page management information. Figure 3.7 shows the overall configuration of the UTLB. The UTLB consists of 64 fully-associative type entries. Figure 3.8 shows the relationship between the address format and page size. Entry 0 Entry 1 Entry 2 ASID [7:0] VPN [31:10] V ASID [7:0] VPN [31:10] V ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 63 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Figure 3.7 UTLB Configuration Rev.7.00 Oct. 10, 2008 Page 86 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) • 1-Kbyte page 31 Virtual address 10 9 VPN Offset 0 28 Physical address 10 9 PPN Offset 0 • 4-Kbyte page 31 Virtual address 12 11 VPN Offset 0 28 Physical address 12 11 PPN Offset 0 • 64-Kbyte page 31 VPN Virtual address 16 15 Offset 0 28 Physical address 16 15 PPN Offset 0 • 1-Mbyte page 31 VPN Virtual address 20 19 Offset 0 28 PPN Physical address 20 19 Offset 0 Figure 3.8 Relationship between Page Size and Address Format • VPN: Virtual page number For 1-Kbyte page: upper 22 bits of virtual address For 4-Kbyte page: upper 20 bits of virtual address For 64-Kbyte page: upper 16 bits of virtual address For 1-Mbyte page: upper 12 bits of virtual address • ASID: Address space identifier Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, this identifier is compared with the ASID in PTEH when address comparison is performed. Rev.7.00 Oct. 10, 2008 Page 87 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) • SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. • SZ: Page size bits Specify the page size. 00: 1-Kbyte page 01: 4-Kbyte page 10: 64-Kbyte page 11: 1-Mbyte page • V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset. • PPN: Physical page number Upper 22 bits of the physical address. With a 1-Kbyte page, PPN bits [28:10] are valid. With a 4-Kbyte page, PPN bits [28:12] are valid. With a 64-Kbyte page, PPN bits [28:16] are valid. With a 1-Mbyte page, PPN bits [28:20] are valid. The synonym problem must be taken into account when setting the PPN (see section 3.5.5, Avoiding Synonym Problems). • PR: Protection key data 2-bit data expressing the page access right as a code. 00: Can be read only, in privileged mode 01: Can be read and written in privileged mode 10: Can be read only, in privileged or user mode 11: Can be read and written in privileged mode or user mode Rev.7.00 Oct. 10, 2008 Page 88 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) • C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0 or set the WT bit to 1. • D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed • WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode When performing PCMCIA space mapping in the cache enabled state, either set this bit to 1 or clear the C bit to 0. • SA: Space attribute bits Valid only when the page is mapped onto PCMCIA connected to area 5 or 6. 000: Undefined 001: Variable-size I/O space (base size according to IOIS16 signal) 010: 8-bit I/O space 011: 16-bit I/O space 100: 8-bit common memory space 101: 16-bit common memory space 110: 8-bit attribute memory space 111: 16-bit attribute memory space • TC: Timing control bit Used to select wait control register bits in the bus control unit for areas 5 and 6. 0: WCR2 (A5W2–A5W0) and PCR (A5PCW1–A5PCW0, A5TED2–A5TED0, A5TEH2– A5TEH0) are used 1: WCR2 (A6W2–A6W0) and PCR (A6PCW1–A6PCW0, A6TED2–A6TED0, A6TEH2– A6TEH0) are used Rev.7.00 Oct. 10, 2008 Page 89 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type entries. The address translation information is almost the same as that in the UTLB, but with the following differences: 1. D and WT bits are not supported. 2. There is only one PR bit, corresponding to the upper of the PR bits in the UTLB. Entry 0 ASID [7:0] VPN [31:10] V Entry 1 ASID [7:0] VPN [31:10] V Entry 2 ASID [7:0] VPN [31:10] V Entry 3 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Figure 3.9 ITLB Configuration 3.4.3 Address Translation Method Figures 3.10 and 3.11 show flowcharts of memory accesses using the UTLB and ITLB. Rev.7.00 Oct. 10, 2008 Page 90 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) Data access to virtual address (VA) VA is in P4 area On-chip I/O access VA is in P2 area 0 VA is in P1 area No VA is in P0, U0, or P3 area CCR.OCE? 1 MMUCR.AT = 1 Yes 0 CCR.CB? 1 0 CCR.WT? 1 No SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) Yes No VPNs match and V = 1 Yes No VPNs match and ASIDs match and V=1 Yes Only one entry matches Yes SR.MD? No Data TLB miss exception 0 (User) PR? 00 or 01 W 10 R/W? R Data TLB protection violation exception 11 R/W? R D? 0 W W 1 1 (Privileged) Memory access 01 or 11 R/W? R Data TLB multiple hit exception 00 or 10 R/W? R Data TLB protection violation exception W Initial page write exception C=1 and CCR.OCE = 1 Yes Cache access in copy-back mode 0 WT? 1 Cache access in write-through mode No Memory access (Non-cacheable) Figure 3.10 Flowchart of Memory Access Using UTLB Rev.7.00 Oct. 10, 2008 Page 91 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) Instruction access to virtual address (VA) VA is in P4 area VA is in P2 area 0 VA is in P1 area No CCR.ICE? 1 MMUCR.AT = 1 Yes VA is in P0, U0, or P3 area Access prohibited No SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) Yes No VPNs match and V = 1 Yes No VPNs match and ASIDs match and V=1 Yes Search UTLB Yes Hardware ITLB miss handling Record in ITLB Only one entry matches Yes No Match? No Instruction TLB miss exception 0 SR.MD? 0 (User) 1 (Privileged) PR? 1 Instruction TLB multiple hit exception Instruction TLB protection violation exception C=1 and CCR.ICE = 1 Yes Cache access No Memory access (Non-cacheable) Figure 3.11 Flowchart of Memory Access Using ITLB Rev.7.00 Oct. 10, 2008 Page 92 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 3.5 3.5.1 MMU Functions MMU Hardware Management The SH-4 supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. 2. The MMU determines the cache access status on the basis of the page management information read during address translation (C, WT, SA, and TC bits). 3. If address translation cannot be performed normally in a data access or instruction access, the MMU notifies software by means of an MMU exception. 4. If address translation information is not recorded in the ITLB in an instruction access, the MMU searches the UTLB, and if the necessary address translation information is recorded in the UTLB, the MMU copies this information into the ITLB in accordance with MMUCR.LRUI. 3.5.2 MMU Software Management Software processing for the MMU consists of the following: 1. Setting of MMU-related registers. Some registers are also partially updated by hardware automatically. 2. Recording, deletion, and reading of TLB entries. There are two methods of recording UTLB entries: by using the LDTLB instruction, or by writing directly to the memory-mapped UTLB. ITLB entries can only be recorded by writing directly to the memory-mapped ITLB. For deleting or reading UTLB/ITLB entries, it is possible to access the memory-mapped UTLB/ITLB. 3. MMU exception handling. When an MMU exception occurs, processing is performed based on information set by hardware. 3.5.3 MMU Instruction (LDTLB) A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, the SH-4 copies the contents of PTEH, PTEL, and PTEA to the UTLB entry indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry. As the LDTLB instruction changes address translation information, ensure that it is Rev.7.00 Oct. 10, 2008 Page 93 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) issued by a program in the P1 or P2 area. The operation of the LDTLB instruction is shown in figure 3.12. MMUCR 31 LRUI 26 25 24 23 — URB 18 17 16 15 — URC 10 9 8 7 SV — 3210 TI — AT Entry specification SQMD PTEL 31 29 28 — 10 9 8 7 VPN — ASID 0 PPN 10 9 8 7 6 5 4 3 2 1 0 — V SZ PR SZ C D SH WT PTEH 31 PTEA 31 — 432 TC SA 0 Write Entry 0 Entry 1 Entry 2 ASID [7:0] VPN [31:10] V ASID [7:0] VPN [31:10] V ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 63 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC UTLB Figure 3.12 Operation of LDTLB Instruction 3.5.4 Hardware ITLB Miss Handling In an instruction access, the SH-4 searches the ITLB. If it cannot find the necessary address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB. This Rev.7.00 Oct. 10, 2008 Page 94 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) procedure is known as hardware ITLB miss handling. If the necessary address translation information is not found in the UTLB search, an instruction TLB miss exception is generated and processing passes to software. 3.5.5 Avoiding Synonym Problems When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The problem is that, when a number of virtual addresses are mapped onto a single physical address, the same physical address data is recorded in a number of cache entries, and it becomes impossible to guarantee data integrity. This problem does not occur with the instruction TLB or instruction cache. In the SH-4, entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of a 1-Kbyte page, and bits [13:12] of the virtual address in the case of a 4-Kbyte page, are subject to address translation. As a result, bits [13:10] of the physical address after translation may differ from bits [13:10] of the virtual address. Consequently, the following restrictions apply to the recording of address translation information in UTLB entries. 1. When address translation information whereby a number of 1-Kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:10] values are the same. 2. When address translation information whereby a number of 4-Kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:12] values are the same. 3. Do not use 1-Kbyte page UTLB entry physical addresses with UTLB entries of a different page size. 4. Do not use 4-Kbyte page UTLB entry physical addresses with UTLB entries of a different page size. The above restrictions apply only when performing accesses using the cache. When cache index mode is used, VPN [25] is used for the entry address instead of VPN [13], and therefore the above restrictions apply to VPN [25]. Note: When multiple items of address translation information use the same physical memory to provide for future SuperH RISC engine family expansion, ensure that the VPN [20:10] values are the same. Also, do not use the same physical address for address translation information of different page sizes. Rev.7.00 Oct. 10, 2008 Page 95 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 3.6 MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception. Refer to figures 3.10 and 3.11 for the conditions under which each of these exceptions occurs. 3.6.1 Instruction TLB Multiple Hit Exception An instruction TLB multiple hit exception occurs when more than one ITLB entry matches the virtual address to which an instruction access has been made. If multiple hits occur when the UTLB is searched by hardware in hardware ITLB miss handling, a data TLB multiple hit exception will result. When an instruction TLB multiple hit exception occurs a reset is executed, and cache coherency is not guaranteed. Hardware Processing: In the event of an instruction TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Software Processing (Reset Routine): The ITLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated. 3.6.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling procedure. The instruction TLB miss exception processing carried out by hardware and software is shown below. This is the same as the processing for a data TLB miss exception. Rev.7.00 Oct. 10, 2008 Page 96 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out the following processing: 1. 2. 3. 4. Sets the VPN of the virtual address at which the exception occurred in PTEH. Sets the virtual address at which the exception occurred in TEA. Sets exception code H'040 in EXPEVT. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. Sets the MD bit in SR to 1, and switches to privileged mode. Sets the BL bit in SR to 1, and masks subsequent exception requests. Sets the RB bit in SR to 1. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the instruction TLB miss exception handling routine. 5. 6. 7. 8. 9. Software Processing (Instruction TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. If necessary, the values of the SA and TC bits should be written to PTEA. 2. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the TLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. Rev.7.00 Oct. 10, 2008 Page 97 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 3.6.3 Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an instruction TLB protection violation exception, hardware carries out the following processing: 1. 2. 3. 4. Sets the VPN of the virtual address at which the exception occurred in PTEH. Sets the virtual address at which the exception occurred in TEA. Sets exception code H'0A0 in EXPEVT. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. Sets the MD bit in SR to 1, and switches to privileged mode. Sets the BL bit in SR to 1, and masks subsequent exception requests. Sets the RB bit in SR to 1. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the instruction TLB protection violation exception handling routine. 5. 6. 7. 8. 9. Software Processing (Instruction TLB Protection Violation Exception Handling Routine): Resolve the instruction TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. A data TLB multiple hit exception is also generated if multiple hits occur when the UTLB is searched in hardware ITLB miss handling. When a data TLB multiple hit exception occurs a reset is executed, and cache coherency is not guaranteed. The contents of PPN in the UTLB prior to the exception may also be corrupted. Rev.7.00 Oct. 10, 2008 Page 98 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) Hardware Processing: In the event of a data TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Software Processing (Reset Routine): The UTLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated. 3.6.5 Data TLB Miss Exception A data TLB miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the UTLB entries. The data TLB miss exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write, in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the data TLB miss exception handling routine. Rev.7.00 Oct. 10, 2008 Page 99 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. If necessary, the values of the SA and TC bits should be written to PTEA. 2. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.6 Data TLB Protection Violation Exception A data TLB protection violation exception occurs when, even though a UTLB entry contains address translation information matching the virtual address to which a data access is made, the actual access type is not permitted by the access right specified by the PR bit. The data TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB protection violation exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'0A0 in the case of a read, or H'0C0 in the case of a write, in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. Rev.7.00 Oct. 10, 2008 Page 100 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the data TLB protection violation exception handling routine. Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.7 Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains address translation information matching the virtual address to which a data access (write) is made, and the access is permitted. The initial page write exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an initial page write exception, hardware carries out the following processing: 1. 2. 3. 4. Sets the VPN of the virtual address at which the exception occurred in PTEH. Sets the virtual address at which the exception occurred in TEA. Sets exception code H'080 in EXPEVT. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. Sets the MD bit in SR to 1, and switches to privileged mode. Sets the BL bit in SR to 1, and masks subsequent exception requests. Sets the RB bit in SR to 1. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the initial page write exception handling routine. 5. 6. 7. 8. 9. Rev.7.00 Oct. 10, 2008 Page 101 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) Software Processing (Initial Page Write Exception Handling Routine): The following processing should be carried out as the responsibility of software: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external memory page table entry. 3. Write to PTEL the values of the PPN, PR, SZ, C, D, WT, SH, and V bits in the page table entry recorded in external memory. If necessary, the values of the SA and TC bits should be written to PTEA. 4. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 5. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. 6. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.7 Memory-Mapped TLB Configuration To enable the ITLB and UTLB to be managed by software, their contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. A branch to an area other than the P2 area should be made at least 8 instructions after this MOV instruction. The ITLB and UTLB are allocated to the P4 area in physical memory space. VPN, V, and ASID in the ITLB can be accessed as an address array, PPN, V, SZ, PR, C, and SH as data array 1, and SA and TC as data array 2. VPN, D, V, and ASID in the UTLB can be accessed as an address array, PPN, V, SZ, PR, C, D, WT, and SH as data array 1, and SA and TC as data array 2. V and D can be accessed from both the address array side and the data array side. Only longword access is possible. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified; their read value is undefined. Rev.7.00 Oct. 10, 2008 Page 102 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 3.7.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field. In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array, and the entry is selected by bits [9:8]. As longword access is used, 0 should be specified for address field bits [1:0]. In the data field, VPN is indicated by bits [31:10], V by bit [8], and ASID by bits [7:0]. The following two kinds of operation can be used on the ITLB address array: 1. ITLB address array read VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB address array write VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. 31 24 23 Address field 1 1 1 1 0 0 1 0 31 Data field Legend: VPN: Virtual page number V: Validity bit E: Entry VPN 10 9 8 7 E 10 9 8 7 V ASID 0 0 ASID: Address space identifier : Reserved bits (0 write value, undefined read value) Figure 3.13 Memory-Mapped ITLB Address Array Rev.7.00 Oct. 10, 2008 Page 103 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 3.7.2 ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field. In the address field, bits [31:23] have the value H'F30 indicating ITLB data array 1, and the entry is selected by bits [9:8]. In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bit [6], C by bit [3], and SH by bit [1]. The following two kinds of operation can be used on ITLB data array 1: 1. ITLB data array 1 read PPN, V, SZ, PR, C, and SH are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB data array 1 write PPN, V, SZ, PR, C, and SH specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. 31 24 23 Address field 1 1 1 1 0 0 1 1 0 31 30 29 28 Data field PPN 10 9 8 7 E 10 9 8 7 6 5 4 3 2 1 0 V C 0 Legend: PPN: Physical page number V: Validity bit E: Entry SZ: Page size bits PR SZ PR: C: SH: : SH Protection key data Cacheability bit Share status bit Reserved bits (0 write value, undefined read value) Figure 3.14 Memory-Mapped ITLB Data Array 1 Rev.7.00 Oct. 10, 2008 Page 104 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 3.7.3 ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field. In the address field, bits [31:23] have the value H'F38 indicating ITLB data array 2, and the entry is selected by bits [9:8]. In the data field, SA is indicated by bits [2:0], and TC by bit [3]. The following two kinds of operation can be used on ITLB data array 2: 1. ITLB data array 2 read SA and TC are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB data array 2 write SA and TC specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. 31 24 23 Address field 1 1 1 1 0 0 1 1 1 31 Data field Legend: TC: Timing control bit E: Entry TC SA: Space attribute bits : Reserved bits (0 write value, undefined read value) 10 9 8 7 E 4320 SA 0 Figure 3.15 Memory-Mapped ITLB Data Array 2 Rev.7.00 Oct. 10, 2008 Page 105 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 3.7.4 UTLB Address Array The UTLB address array is allocated to addresses H'F600 0000 to H'F6FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, D, V, and ASID to be written to the address array are specified in the data field. In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether or not address comparison is performed when writing to the UTLB address array. In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits [7:0]. The following three kinds of operation can be used on the UTLB address array: 1. UTLB address array read VPN, D, V, and ASID are read into the data field from the UTLB entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. UTLB address array write (non-associative) VPN, D, V, and ASID specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3. UTLB address array write (associative) When a write is performed with the A bit in the address field set to 1, comparison of all the UTLB entries is carried out using the VPN specified in the data field and PTEH.ASID. The usual address comparison rules are followed, but if a UTLB miss occurs, the result is no operation, and an exception is not generated. If the comparison identifies a UTLB entry corresponding to the VPN specified in the data field, D and V specified in the data field are written to that entry. If there is more than one matching entry, a data TLB multiple hit exception results. This associative operation is simultaneously carried out on the ITLB, and if a matching entry is found in the ITLB, V is written to that entry. Even if the UTLB comparison results in no operation, a write to the ITLB side only is performed as long as there is an ITLB match. If there is a match in both the UTLB and ITLB, the UTLB information is also written to the ITLB. Rev.7.00 Oct. 10, 2008 Page 106 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 31 24 23 Address field 1 1 1 1 0 1 1 0 31 30 29 28 Data field Legend: VPN: Virtual page number Validity bit V: Entry E: Dirty bit D: VPN 14 13 E 87 A 0 ASID 210 10 9 8 7 DV ASID: Address space identifier Association bit A: Reserved bits (0 write value, undefined read value) : Figure 3.16 Memory-Mapped UTLB Address Array 3.7.5 UTLB Data Array 1 UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data array are specified in the data field. In the address field, bits [31:23] have the value H'F70 indicating UTLB data array 1, and the entry is selected by bits [13:8]. In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bits [6:5], C by bit [3], D by bit [2], SH by bit [1], and WT by bit [0]. The following two kinds of operation can be used on UTLB data array 1: 1. UTLB data array 1 read PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry corresponding to the entry set in the address field. 2. UTLB data array 1 write PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. Rev.7.00 Oct. 10, 2008 Page 107 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 31 24 23 Address field 1 1 1 1 0 1 1 1 0 31 30 29 28 Data field Legend: PPN: Physical page number V: Validity bit E: Entry SZ: Page size bits Dirty bit D: PPN 14 13 E 10 9 8 7 6 5 4 3 2 1 0 V PR CD 87 0 SZ SH WT PR: Protection key data C: Cacheability bit SH: Share status bit WT: Write-through bit : Reserved bits (0 write value, undefined read value) Figure 3.17 Memory-Mapped UTLB Data Array 1 3.7.6 UTLB Data Array 2 UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field. In the address field, bits [31:23] have the value H'F78 indicating UTLB data array 2, and the entry is selected by bits [13:8]. In the data field, TC is indicated by bit [3], and SA by bits [2:0]. The following two kinds of operation can be used on UTLB data array 2: 1. UTLB data array 2 read SA and TC are read into the data field from the UTLB entry corresponding to the entry set in the address field. 2. UTLB data array 2 write SA and TC specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. Rev.7.00 Oct. 10, 2008 Page 108 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) 31 24 23 Address field 1 1 1 1 0 1 1 1 1 31 Data field Legend: TC: Timing control bit E: Entry 14 13 E 432 SA TC SA: Space attribute bits : Reserved bits (0 write value, undefined read value) 0 87 0 Figure 3.18 Memory-Mapped UTLB Data Array 2 3.8 Usage Notes 1. Address Space Identifier (ASID) in Single Virtual Memory Mode Refer to the note in 3.3.7, Address Space Identifier (ASID). Rev.7.00 Oct. 10, 2008 Page 109 of 1074 REJ09B0366-0700 Section 3 Memory Management Unit (MMU) Rev.7.00 Oct. 10, 2008 Page 110 of 1074 REJ09B0366-0700 Section 4 Caches Section 4 Caches 4.1 4.1.1 Overview Features An SH7750 or SH7750S has an on-chip 8-Kbyte instruction cache (IC) for instructions and 16Kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 Kbytes) may alternatively be used as on-chip RAM. The features of this cache are summarized in table 4.1 The SH7750R has an on-chip 16-Kbyte instruction cache (IC) for instructions and 32-Kbyte operand cache (OC) for data. Half of the memory of the operand cache (16 Kbytes) may alternatively be used as on-chip RAM. When the EMODE bit of the CCR register is 0, the SH7750R's cache is set to operate in the SH7750/SH7750S-compatible mode and behaves as shown in table 4.1. The features of the cache when the EMODE bit in the CCR register is 1 are given in table 4.2. The EMODE bit is initialized to 0 after a power-on reset or manual reset. For high-speed writing to external memories, this LSI supports 32 bytes × 2 of store queues (SQ). Table 4.3 lists the features of these SQs. Table 4.1 Item Capacity Type Line size Entries Write method Cache Features (SH7750, SH7750S) Instruction Cache 8-Kbyte cache Direct mapping 32 bytes 256 Operand Cache 16-Kbyte cache or 8-Kbyte cache + 8-Kbyte RAM Direct mapping 32 bytes 512 Copy-back/write-through selectable Rev.7.00 Oct. 10, 2008 Page 111 of 1074 REJ09B0366-0700 Section 4 Caches Table 4.2 Item Capacity Type Line size Entries Write method Cache Features (SH7750R) Instruction Cache 16-Kbyte cache 2-way set-associative 32 bytes 256 entries/way Operand Cache 32-Kbyte cache or 16-Kbyte cache + 16-Kbyte RAM 2-way set-associative 32 bytes 512 entries/way Copy-back/write-through selectable LRU (least-recently-used) algorithm LRU algorithm Replacement method Table 4.3 Item Capacity Addresses Write Write-back Access right Features of Store Queues Store Queues 2 × 32 bytes H'E000 0000 to H'E3FF FFFF Store instruction (1-cycle write) Prefetch instruction (PREF instruction) MMU off: according to MMUCR.SQMD MMU on: according to individual page PR Rev.7.00 Oct. 10, 2008 Page 112 of 1074 REJ09B0366-0700 Section 4 Caches 4.1.2 Register Configuration Table 4.4 shows the cache control registers. Table 4.4 Name Cache control register Queue address control register 0 Queue address control register 1 Cache Control Registers Abbreviation R/W CCR QACR0 QACR1 R/W R/W R/W Initial Value*1 H'0000 0000 Undefined Undefined P4 Address*2 H'FF00 001C H'FF00 0038 H'FF00 003C Area 7 Address*2 H'1F00 001C H'1F00 0038 H'1F00 003C Access Size 32 32 32 Notes: 1. The initial value is the value after a power-on or manual reset. 2. This is the address when using the virtual/physical address space P4 area. The area 7 address is the address used when making an access from physical address space area 7 using the TLB. Rev.7.00 Oct. 10, 2008 Page 113 of 1074 REJ09B0366-0700 Section 4 Caches 4.2 Register Descriptions There are three cache and store queue related control registers, as shown in figure 4.1. CCR 31 30 16 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0 CB EMODE* QACR0 31 54 210 IIX ICI ICE OIX ORA OCI WT OCE AREA QACR1 31 54 210 AREA Notes: indicates reserved bits: 0 must be specified in a write; the read value is 0. * SH7750R only Figure 4.1 Cache and Store Queue Control Registers (1) Cache Control Register (CCR): CCR contains the following bits: EMODE: IIX: ICI: ICE: OIX: ORA: OCI: CB: WT: OCE: Double-sized cache mode (Only for SH7750R; reserved bit for SH7750 and SH7750S) IC index enable IC invalidation IC enable OC index enable OC RAM enable OC invalidation Copy-back enable Write-through enable OC enable Longword access to CCR can be performed from H'FF00 001C in the P4 area and H'1F00 001C in area 7. The CCR bits are used for the cache settings described below. Consequently, CCR modifications must only be made by a program in the non-cached P2 area. After CCR is updated, Rev.7.00 Oct. 10, 2008 Page 114 of 1074 REJ09B0366-0700 Section 4 Caches an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or U0 area should be located at least eight instructions after the CCR update instruction. • EMODE: Double-sized cache mode bit In the SH7750R, this bit indicates whether the double-sized cache mode is used or not. This bit is reserved in the SH7750 and SH7750S. The EMODE bit must not be written to while the cache is being used. 0: SH7750/SH7750S-compatible mode*1 (initial value) 1: Double-sized cache mode • IIX: IC index enable bit 0: Effective address bits [12:5] used for IC entry selection 1: Effective address bits [25] and [11:5] used for IC entry selection • ICI: IC invalidation bit When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit always returns 0 when read. • ICE: IC enable bit Indicates whether or not the IC is to be used. When address translation is performed, the IC cannot be used unless the C bit in the page management information is also 1. 0: IC not used 1: IC used • OIX: OC index enable bit*2 0: Effective address bits [13:5] used for OC entry selection 1: Effective address bits [25] and [12:5] used for OC entry selection • ORA: OC RAM enable bit*3 When the OC is enabled (OCE = 1), the ORA bit specifies whether the half of the OC are to be used as RAM. When the OC is not enabled (OCE = 0), the ORA bit should be cleared to 0. 0: Normal mode (the entire OC is used as a cache) 1: RAM mode (half of the OC is used as a cache and the other half is used as RAM) • OCI: OC invalidation bit When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always returns 0 when read. Rev.7.00 Oct. 10, 2008 Page 115 of 1074 REJ09B0366-0700 Section 4 Caches • CB: Copy-back bit Indicates the P1 area cache write mode. 0: Write-through mode 1: Copy-back mode • WT: Write-through bit Indicates the P0, U0, and P3 area cache write mode. When address translation is performed, the value of the WT bit in the page management information has priority. 0: Copy-back mode 1: Write-through mode • OCE: OC enable bit Indicates whether or not the OC is to be used. When address translation is performed, the OC cannot be used unless the C bit in the page management information is also 1. 0: OC not used 1: OC used Notes: 1. No compatibility for RAM mode in OC index mode and address assignment in RAM mode. 2. When the ORA bit is 1 in the SH7750R, the OIX bit should be cleared to 0. 3. When the OIX bit in the SH7750R is 1, the ORA bit should be cleared to 0. (2) Queue Address Control Register 0 (QACR0): Longword access to QACR0 can be performed from H'FF00 0038 in the P4 area and H'1F00 0038 in area 7. QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is off. (3) Queue Address Control Register 1 (QACR1): Longword access to QACR1 can be performed from H'FF00 003C in the P4 area and H'1F00 003C in area 7. QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is off. 4.3 4.3.1 Operand Cache (OC) Configuration The operand cache of the SH7750 or SH7750S is of the direct-mapping type and consists of 512 cache lines, each composed of a 19-bit tag, V bit, U bit, and 32-byte data. The SH7750R's operand cache is 2-way set-associative. Each way consists of 512 cache lines. Figure 4.2 shows the configuration of the operand cache for the SH7750 and SH7750S. Rev.7.00 Oct. 10, 2008 Page 116 of 1074 REJ09B0366-0700 Section 4 Caches Figure 4.3 shows the configuration of the operand cache for the SH7750R. Effective address 31 26 25 13 12 11 10 9 543210 RAM area determination [11:5] OIX [13] ORA [12] 22 9 Entry selection Address array 0 Tag U V 3 Longword (LW) selection Data array LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 MMU 19 511 19 bits 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Compare Read data Write data Hit signal Figure 4.2 Configuration of Operand Cache (SH7750, SH7750S) Rev.7.00 Oct. 10, 2008 Page 117 of 1074 REJ09B0366-0700 Section 4 Caches Effective address 31 26 25 13 12 10 54 2 0 RAM area judgment OIX ORA Entry selection 22 9 0 Address array (way 0, way 1) Tag address U V 3 [12:5] [13] Longword (LW) selection Data array (way 0, way 1) LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 LRU MMU 19 511 19 bits 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 1 bit Compare Compare way 0 way 1 Read data Write data Hit signal Figure 4.3 Configuration of Operand Cache (SH7750R) Rev.7.00 Oct. 10, 2008 Page 118 of 1074 REJ09B0366-0700 Section 4 Caches • Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset. • V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. • U bit (dirty bit) The U bit is set to 1 if data is written to the cache line while the cache is being used in copyback mode. That is, the U bit indicates a mismatch between the data in the cache line and the data in external memory. The U bit is never set to 1 while the cache is being used in writethrough mode, unless it is modified by accessing the memory-mapped cache (see section 4.5, Memory-Mapped Cache Configuration (SH7750, SH7750S)). The U bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. • Data field The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU (SH7750R only) In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each entry address. When an entry is registered, the LRU bit indicates which of the 2 ways it is to be registered in. The LRU bit is a single bit of each entry, and its value is controlled by hardware. The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset. The LRU bits cannot be read or written by software. Rev.7.00 Oct. 10, 2008 Page 119 of 1074 REJ09B0366-0700 Section 4 Caches 4.3.2 Read Operation When the OC is enabled (CCR.OCE = 1) and data is read by means of an effective address from a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: → (3a) • If the tag matches and the V bit is 1 → (3b) • If the tag matches and the V bit is 0 → (3b) • If the tag does not match and the V bit is 0 • If the tag does not match, the V bit is 1, and the U bit is 0 → (3b) • If the tag does not match, the V bit is 1, and the U bit is 1 → (3c) 3a. Cache hit The data indexed by effective address bits [4:0] is read from the data field of the cache line indexed by effective address bits [13:5] in accordance with the access size (quadword/longword/word/byte). 3b. Cache miss (no write-back) Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit. 3c. Cache miss (with write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are saved in the write-back buffer. Then data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, 1 is written to the V bit, and 0 to the U bit. The data in the write-back buffer is then written back to external memory. Rev.7.00 Oct. 10, 2008 Page 120 of 1074 REJ09B0366-0700 Section 4 Caches 4.3.3 Write Operation When the OC is enabled (CCR.OCE = 1) and data is written by means of an effective address to a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: Copy-back Write-through → (3a) → (3b) • If the tag matches and the V bit is 1 → (3c) → (3d) • If the tag matches and the V bit is 0 → (3c) → (3d) • If the tag does not match and the V bit is 0 → (3c) → (3d) • If the tag does not match, the V bit is 1, and the U bit is 0 → (3d) • If the tag does not match, the V bit is 1, and the U bit is 1 → (3e) 3a. Cache hit (copy-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then 1 is set in the U bit. 3b. Cache hit (write-through) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. A write is also performed to the corresponding external memory using the specified access size. 3c. Cache miss (no copy-back/write-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then, data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. During this time, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit and U bit. 3d. Cache miss (write-through) A write of the specified access size is performed to the external memory corresponding to the effective address. In this case, a write to cache is not performed. Rev.7.00 Oct. 10, 2008 Page 121 of 1074 REJ09B0366-0700 Section 4 Caches 3e. Cache miss (with copy-back/write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are first saved in the write-back buffer, and then a data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then, data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. During this time, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit and U bit. The data in the write-back buffer is then written back to external memory. 4.3.4 Write-Back Buffer In order to give priority to data reads to the cache and improve performance, this LSI has a writeback buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. The write-back buffer contains one cache line of data and the physical address of the purge destination. Physical address bits [28:5] LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 Figure 4.4 Configuration of Write-Back Buffer 4.3.5 Write-Through Buffer This LSI has a 64-bit buffer for holding write data when writing data in write-through mode or writing to a non-cacheable area. This allows the CPU to proceed to the next operation as soon as the write to the write-through buffer is completed, without waiting for completion of the write to external memory. Physical address bits [28:0] LW0 LW1 Figure 4.5 Configuration of Write-Through Buffer Rev.7.00 Oct. 10, 2008 Page 122 of 1074 REJ09B0366-0700 Section 4 Caches 4.3.6 RAM Mode Setting CCR.ORA to 1 enables half of the operand cache to be used as RAM. In the SH7750 or SH7750S, the 8 Kbytes of operand cache entries 128 to 255 and 384 to 511 are used as RAM. In the SH7750/SH7750S-compatible mode of the SH7750R, the 8-Kbyte area otherwise used for OC entries 256 to 511 is designated as a RAM area. In the double-sized cache mode of the SH7750R, a total of 16 Kbytes, comprising entries 256 to 511 in both of the ways of the operand cache, is designated as a RAM area. Other entries can still be used as cache. RAM can be accessed using addresses H'7C00 0000 to H'7FFF FFFF. Byte-, word-, longword-, and quadword-size data reads and writes can be performed in the operand cache RAM area. Instruction fetches cannot be performed in this area. With the SH7750R, the OC index mode is not available in RAM mode. An example of RAM use in the SH7750 or SH7750S is shown below. Here, the 4 Kbytes comprising OC entries 128 to 255 are designated as RAM area 1, and the 4 Kbytes comprising OC entries 384 to 511 as RAM area 2. • When OC index mode is off (CCR.OIX = 0) H'7C00 0000 to H'7C00 0FFF (4 KB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 KB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 2FFF (4 KB): Corresponds to RAM area 2 H'7C00 3000 to H'7C00 3FFF (4 KB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 4FFF (4 KB): Corresponds to RAM area 1 : : : RAM areas 1 and 2 in the SH7750 or SH7750S then repeat every 8 Kbytes up to H'7FFF FFFF. Thus, to secure a continuous 8-Kbyte RAM area, the area from H'7C00 1000 to H'7C00 2FFF can be used, for example. • When OC index mode is on (CCR.OIX = 1) H'7C00 0000 to H'7C00 0FFF (4 KB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 KB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 2FFF (4 KB): Corresponds to RAM area 1 : : : H'7DFF F000 to H'7DFF FFFF (4 KB): Corresponds to RAM area 1 H'7E00 0000 to H'7E00 0FFF (4 KB): Corresponds to RAM area 2 H'7E00 1000 to H'7E00 1FFF (4 KB): Corresponds to RAM area 2 : : : H'7FFF F000 to H'7FFF FFFF (4 KB): Corresponds to RAM area 2 Rev.7.00 Oct. 10, 2008 Page 123 of 1074 REJ09B0366-0700 Section 4 Caches As the distinction between RAM areas 1 and 2 is indicated by address bit [25], the area from H'7DFF F000 to H'7E00 0FFF should be used to secure a continuous 8-Kbyte RAM area. Examples of RAM usage with the SH7750R is shown below. • In SH7750/SH7750S-compatible mode (CCR.EMODE = 0) H'7C00 0000 to H'7C00 1FFF (8 KB): RAM area (entries 256 to 511) H'7C00 2000 to H'7C00 3FFF (8 KB): RAM area (entries 256 to 511) : : : In the same pattern, shadows of the RAM area are created in 8-Kbyte blocks until H'7FFF FFFF is reached. • In double-sized cache mode (CCR.EMODE = 1) In this mode, the 8 Kbytes comprising entries 256 to 511 of OC way 0 are designated as RAM area 1 and the 8-Kbytes comprising entries 256 to 511 of OC way 1 are designated as RAM area 2. H'7C00 0000 to H'7C00 1FFF (8 KB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 3FFF (8 KB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 5FFF (8 KB): Corresponds to RAM area 1 H'7C00 6000 to H'7C00 7FFF (8 KB): Corresponds to RAM area 2 : : : In the same pattern, shadows of the RAM area are created in 16-Kbyte blocks until H'7FFF FFFF is reached. 4.3.7 OC Index Mode Setting CCR.OIX to 1 enables OC indexing to be performed using bit [25] of the effective address. This is called OC index mode. In normal mode, with CCR.OIX cleared to 0, OC indexing is performed using bits [13:5] of the effective address. Using index mode allows the OC to be handled as two areas by means of effective address bit [25], providing efficient use of the cache. The SH7750R cannot be used in RAM mode when OC index mode is selected. Rev.7.00 Oct. 10, 2008 Page 124 of 1074 REJ09B0366-0700 Section 4 Caches 4.3.8 Coherency between Cache and External Memory Coherency between cache and external memory should be assured by software. In this LSI, the following four new instructions are supported for cache operations. Details of these instructions are given in the Programming Manual. Invalidate instruction: Purge instruction: Write-back instruction: Allocate instruction: 4.3.9 Prefetch Operation OCBI @Rn OCBP @Rn OCBWB @Rn MOVCA.L R0,@Rn Cache invalidation (no write-back) Cache invalidation (with write-back) Cache write-back Cache allocation This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance. If a prefetch instruction is executed for data already held in the cache, or if the prefetch address results in a UTLB miss or a protection violation, the result is no operation, and an exception is not generated. Details of the prefetch instruction are given in the Programming Manual. Prefetch instruction: 4.3.10 PREF @Rn Notes on Using Cache Enhanced Mode (SH7750R Only) When cache enhanced mode (CCR.EMODE = 1) is specified and OC RAM mode (CCR.ORA = 1) is selected, in which half of the operand cache is used as internal RAM, internal RAM data may be updated incorrectly. Conditions Under which Problem Occurs: Incorrect data may be written to RAM when the following four conditions are satisfied. Condition 1: Cache enhanced mode (CCR.EMODE = 1) is specified. Condition 2: The RAM mode (CCR.ORA = 1) in which half of the operand cache is used as internal RAM is specified. Condition 3: An exception or an interrupt occurs. Rev.7.00 Oct. 10, 2008 Page 125 of 1074 REJ09B0366-0700 Section 4 Caches Note: This includes a break triggered by a debugging tool swapping an instruction (a break occurring when a TRAPA instruction or undefined instruction code H'FFFD is swapped for an instruction). Condition 4: A store instruction (MOV, FMOV, AND.B, OR, B, XOR.B, MOVCA.L, STC.L, or STS.L) that accesses internal RAM (H'7C000000 to H'7FFFFFFF) exists within four instructions after the instruction associated with the exception or interrupt described in condition 3. This includes cases where the store instruction that accesses internal RAM itself generates an exception. Description: When the problem occurs, 8 bytes of incorrect data is written to the 8-byte boundary that includes an address that differs by H'2000 from the address accessed by the store instruction that accesses internal RAM mentioned in condition 4. For example, when a long word is stored at address H'7C000204, the 8 bytes of data in the internal RAM mapped to addresses H'7C002200 to H'7C002207 becomes corrupted. Examples Example 1 A store instruction accessing internal RAM occurs within four instructions after an instruction generating a TLB miss exception. MOV.L #H'0C400000, R0 MOV.L #H'7C000204, R1 MOV.L @R0, R2 NOP NOP NOP MOV.L R3, @R1 R0 is an address causing a TLB miss. R1 is an address mapped to internal RAM. TLB miss exception occurs. 1st word 2nd word 3rd word Store instruction accessing internal RAM Example 2 A store instruction accessing internal RAM occurs within four instructions after an instruction causing an interrupt to be accepted. MOV.L #H'7C002000, R1 MOV.L #H'12345678, R0 NOP NOP NOP MOV.L R0, @R1 R1 is an address mapped to internal RAM. An interrupt is accepted after this instruction. 1st word 2nd word 3rd word Store instruction accessing internal RAM Rev.7.00 Oct. 10, 2008 Page 126 of 1074 REJ09B0366-0700 Section 4 Caches Example 3 A debugging tool generates a break to swap an instruction. Original Instruction String After Instruction Swap Break MOV.L #H'C000000, R0 ADD R0, R0 MOV.L R1, @R0 MOV.L #H'7C000000, R0 TRAPA #H'01 MOV.L R1, @R0 Contains address corresponding to R0. R0 address is not a problem in original instruction string. Internal RAM is accessed by a store operation because ADD is not executed. The store is cancelled, but 2LW starting at H'7C002000 is corrupted. Workarounds: When RAM mode is specified in cache enhanced mode, either of the following workarounds can be used to avoid the problem. Workaround 1: Use only 8 Kbytes of the 16-Kbyte internal RAM area. In this case, RAM areas for which address bits [12:0] are identical and only bit [13] differs must not be used. For example, the 8-Kbyte RAM area from H'7C000000 to H'7C001FFF or from H'7C001000 to H'7C002FFF may be used. Note: When a break is used to swap instructions by a debugging tool, etc., a memory access address may be changed when an instruction following the instruction generating the break is swapped for another instruction, causing the unused 8-Kbyte RAM area to be accessed. This will result in the problem described above. However, this phenomenon only occurs during debugging when a break is used to swap instructions. Using a break with no instruction swapping will not cause the problem. Workaround 2: Ensure that there are no instructions that generate an interrupt or exception within four instructions after an instruction that accesses internal RAM. For example, the internal RAM area can be used as a data table that is accessed only by load instructions, with writes to the internal RAM area only being performed when the table is generated. It this case, set SR.BL to 1 to disable interrupts while writing to the table. Also take measures to ensure that no exceptions due to TLB misses, etc., occur while writing to the table. Note: The problem still may occur when a break is used to swap instructions by a debugging tool. This phenomenon only occurs during debugging when a break is used to swap instructions. Using a break with no instruction swapping will not cause the problem. Rev.7.00 Oct. 10, 2008 Page 127 of 1074 REJ09B0366-0700 Section 4 Caches 4.4 4.4.1 Instruction Cache (IC) Configuration The instruction cache of the SH7750 or SH7750S is of the direct-mapping type and consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32-byte data (16 instructions). The SH7750R's instruction cache is 2-way set associative. Each way consists of 256 cache lines. Figure 4.6 shows the configuration of the instruction cache for the SH7750 and SH7750S. Figure 4.7 shows the configuration of the instruction cache for the SH7750R. Effective address 31 26 25 13 12 11 10 9 543210 [11:5] IIX [12] Longword (LW) selection 8 Entry selection 22 Address array 0 Tag V 3 Data array LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 MMU 19 255 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Compare Read data Hit signal Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S) Rev.7.00 Oct. 10, 2008 Page 128 of 1074 REJ09B0366-0700 Section 4 Caches Effective address 31 25 13 12 11 10 54 2 0 [11:5] IIX [12] Entry selection 22 8 0 Address array (way 0, way1) Tag address V 3 Longword (LW) selection Data array (way 0, way 1) LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 LRU MMU 19 255 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 1 bit Compare Compare way 1 way 0 Read data Hit signal Figure 4.7 Configuration of Instruction Cache (SH7750R) • Tag Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is not initialized by a power-on or manual reset. • V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. Rev.7.00 Oct. 10, 2008 Page 129 of 1074 REJ09B0366-0700 Section 4 Caches • Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU (SH7750R only) In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each entry address. When an entry is registered, the LRU bit indicates which of the 2 ways it is to be registered in. The LRU bit is a single bit of each entry, and its usage is controlled by hardware. The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset. The LRU bits cannot be read or written by software. 4.4.2 Read Operation When the IC is enabled (CCR.ICE = 1) and instruction fetches are performed by means of an effective address from a cacheable area, the instruction cache operates as follows: 1. The tag and V bit are read from the cache line indexed by effective address bits [12:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: • If the tag matches and the V bit is 1 → (3a) • If the tag matches and the V bit is 0 → (3b) • If the tag does not match and the V bit is 0 → (3b) • If the tag does not match and the V bit is 1 → (3b) 3a. Cache hit The data indexed by effective address bits [4:2] is read as an instruction from the data field of the cache line indexed by effective address bits [12:5]. 3b. Cache miss Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU as an instruction. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit. Rev.7.00 Oct. 10, 2008 Page 130 of 1074 REJ09B0366-0700 Section 4 Caches 4.4.3 IC Index Mode Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address. This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is performed using bits [12:5] of the effective address. Using index mode allows the IC to be handled as two areas by means of effective address bit [25], providing efficient use of the cache. 4.5 Memory-Mapped Cache Configuration (SH7750, SH7750S) To enable the IC and OC to be managed by software, their contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should be made at least 8 instructions after this MOV instruction. The IC and OC are allocated to the P4 area in physical memory space. Only data accesses can be used on both the IC address array and data array and the OC address array and data array, and accesses are always longword-size. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified; their read value is undefined. 4.5.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the write tag and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F0 indicating the IC address array, and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the IC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: Rev.7.00 Oct. 10, 2008 Page 131 of 1074 REJ09B0366-0700 Section 4 Caches 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3. IC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is performed, and the write is not executed. If an instruction TLB multiple hit exception occurs during address translation, processing switches to the instruction TLB multiple hit exception handling routine. 31 24 23 13 12 Entry 10 9 Tag 543210 A 10 V Address field 1 1 1 1 0 0 0 0 31 Data field Legend: V: Validity bit A: Association bit : Reserved bits (0 write value, undefined read value) Figure 4.8 Memory-Mapped IC Address Array 4.5.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. Rev.7.00 Oct. 10, 2008 Page 132 of 1074 REJ09B0366-0700 Section 4 Caches In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 31 24 23 Address field 1 1 1 1 0 0 0 1 31 Data field Longword data 13 12 Entry 54 L 0 210 Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.9 Memory-Mapped IC Data Array 4.5.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, and the entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification. The address array bit [3] association bit (A bit) specifies whether or not association Rev.7.00 Oct. 10, 2008 Page 133 of 1074 REJ09B0366-0700 Section 4 Caches is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. OC address array write (non-associative) The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after writeback of that cache line, the tag, U bit, and V bit specified in the data field are written. 3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB. If the addresses match and the V bit is 1, the U bit and V bit specified in the data field are written into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If an UTLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine. Rev.7.00 Oct. 10, 2008 Page 134 of 1074 REJ09B0366-0700 Section 4 Caches 31 24 23 Address field 1 1 1 1 0 1 0 0 31 Data field Tag 14 13 Entry 10 9 543210 A 210 UV Legend: V: Validity bit U: Dirty bit A: Association bit : Reserved bits (0 write value, undefined read value) Figure 4.10 Memory-Mapped OC Address Array 4.5.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding the entry set in the address field. This write does not set the U bit to 1 on the address array side. Rev.7.00 Oct. 10, 2008 Page 135 of 1074 REJ09B0366-0700 Section 4 Caches 31 24 23 Address field 1 1 1 1 0 1 0 1 31 Data field Longword data 14 13 Entry 54 L 0 210 Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.11 Memory-Mapped OC Data Array 4.6 Memory-Mapped Cache Configuration (SH7750R) To enable the management of the IC and OC by software, a program running in the privileged mode is allowed to access their contents. The contents of IC can be read and written by using MOV instructions in a P2-area program running in the privileged mode. Operation is not guaranteed for access from a program in some other area. Any branching to other areas must take place at least 8 instructions after this MOV instruction. The contents of IC can be read and written by using MOV instructions in a P1- or P2-area program running in the privileged mode. Operation is not guaranteed if access is attempted from a program running in some other area. A branch to the P0, U0, or P3 area must be made at least 8 instructions after this MOV instruction. The IC and OC are allocated to the P4 area of the physical memory space. The address and data arrays of both the IC and OC are only accessible by their data fields. Longword operations must be used. Instruction fetches from these areas are not possible. For reserved bits, a write value of 0 should be specified; values read from such bits are undefined. Note that, in the SH7750/SH7750Scompatible mode, the configuration of the SH7750R's memory-mapped cache is the same as that of the SH7750 or SH7750S. Rev.7.00 Oct. 10, 2008 Page 136 of 1074 REJ09B0366-0700 Section 4 Caches 4.6.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed is specified in the address field, and the write tag and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F0 indicating the IC address array, the way is specified by bit [13], and the entry by bits [12:5]. CCR.IIX has no effect on this entry specification. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the IC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the way and the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the way and the entry set in the address field. The A bit in the address field should be cleared to 0. 3. IC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag for each of the ways stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set by bit [13] is not used. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit for that way is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is performed, and the write is not executed. If an instruction TLB multiple hit exception occurs during address translation, processing switches to the instruction TLB multiple hit exception handling routine. Rev.7.00 Oct. 10, 2008 Page 137 of 1074 REJ09B0366-0700 Section 4 Caches 31 24 23 Address field 1 1 1 1 0 0 0 0 13 12 Entry Way 31 Data field Tag 10 9 10 V 543210 A Legend: V: Validity bit A: Association bit : Reserved bits (0 write value, undefined read value Figure 4.12 Memory-Mapped IC Address Array 4.6.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F1 indicating the IC data array, the way is specified by bit [13], and the entry by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field. 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field. Rev.7.00 Oct. 10, 2008 Page 138 of 1074 REJ09B0366-0700 Section 4 Caches 31 24 23 Address field 1 1 1 1 0 0 0 1 13 12 Entry Way 31 Data field Longword data 0 54 L 210 Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.13 Memory-Mapped IC Data Array 4.6.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed is specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, the way is specified by bit [14], and the entry by bits [13:5]. CCR.OIX has no effect on this entry specification. In RAM mode (CCR.ORA = 1), the OC's address arrays are only accessible in the memory-mapped cache area, and bit [13] is used to specify the way. For details about address mapping, see section 4.6.5, Summary of the Memory-Mapping of the OC. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the way and the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. Rev.7.00 Oct. 10, 2008 Page 139 of 1074 REJ09B0366-0700 Section 4 Caches 2. OC address array write (non-associative) The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to the way and the entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after writeback of that cache line, the tag, U bit, and V bit specified in the data field are written. 3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag for each of the ways stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set by bit [14] is not used. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB. If the addresses match and the V bit for that way is 1, the U bit and V bit specified in the data field are written into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If an UTLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine. 31 24 23 Address field 1 1 1 1 0 1 0 0 15 14 13 Entry Way 31 Data field Tag 10 9 210 UV 543210 A Legend: V: Validity bit U: Dirty bit A: Association bit : Reserved bits (0 write value, undefined read value) Figure 4.14 Memory-Mapped OC Address Array Rev.7.00 Oct. 10, 2008 Page 140 of 1074 REJ09B0366-0700 Section 4 Caches 4.6.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F5 indicating the OC data array, the way is specified by bit [14], and the entry by bits [13:5]. CCR.OIX has no effect on this entry specification. In RAM mode (CCR.ORA = 1), the OC's data arrays are only accessible in the memory-mapped cache area, and bit [13] is used to specify the way. For details about address mapping, see section 4.6.5, Summary of the Memory-Mapping of the OC. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding the way and entry set in the address field. This write does not set the U bit to 1 on the address array side. 31 24 23 15 14 13 Entry Way Longword data 54 L 210 Address field 1 1 1 1 0 1 0 1 31 Data field 0 Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.15 Memory-Mapped OC Data Array Rev.7.00 Oct. 10, 2008 Page 141 of 1074 REJ09B0366-0700 Section 4 Caches 4.6.5 Summary of the Memory-Mapping of the OC The address ranges to which the OC is memory-mapped in the double-sized cache mode of the SH7750R are summarized below, using examples of data-array access. • In normal mode (CCR.ORA = 0) H'F500 0000 to H'F500 3FFF (16 KB ): Way 0 (entries 0 to 511) H'F500 4000 to H'F500 7FFF (16 KB ): Way 1 (entries 0 to 511) : : : In the same pattern, shadows of the cache area are created in 32-Kbyte blocks until H'F5FF FFFF. • In RAM mode (CCR. ORA = 1) H'F500 0000 to H'F500 1FFF (8 KB ): Way 0 (entries 0 to 255) H'F500 2000 to H'F500 3FFF (8 KB ): Way 1 (entries 0 to 255) : : : In the same pattern, shadows of the cache area are created in 16-Kbyte blocks until H'F5FF FFFF. 4.7 Store Queues This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. In the SH7750S or SH7750R, if the SQs are not used the low power dissipation power-down modes, in which SQ functions are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be accessed while SQ functions are stopped. See section 9, PowerDown Modes, for the procedure for stopping SQ functions. 4.7.1 SQ Configuration There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 4.16. These two store queues can be set independently. Rev.7.00 Oct. 10, 2008 Page 142 of 1074 REJ09B0366-0700 Section 4 Caches SQ0 SQ0[0] SQ0[1] SQ0[2] SQ0[3] SQ0[4] SQ0[5] SQ0[6] SQ0[7] SQ1 SQ1[0] 4B SQ1[1] 4B SQ1[2] 4B SQ1[3] 4B SQ1[4] 4B SQ1[5] 4B SQ1[6] 4B SQ1[7] 4B Figure 4.16 Store Queue Configuration 4.7.2 SQ Writes A write to the SQs can be performed using a store instruction (MOV) on P4 area H'E000 0000 to H'E3FF FFFC. A longword or quadword access size can be used. The meaning of the address bits is as follows: [31:26]: [25:6]: [5]: [4:2]: [1:0] 4.7.3 111000 Don't care 0/1 LW specification 00 Store queue specification Used for external memory transfer/access right 0: SQ0 specification 1: SQ1 specification Specifies longword position in SQ0/SQ1 Fixed at 0 Transfer to External Memory Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF). Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a burst transfer from the SQs to external memory. The burst transfer length is fixed at 32 bytes, and the start address is always at a 32-byte boundary. While the contents of one SQ are being transferred to external memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in the transfer to external memory is deferred until the transfer is completed. The SQ transfer destination external memory address bit [28:0] specification is as shown below, according to whether the MMU is on or off. • When MMU is on The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer destination external memory address in PPN. The ASID, V, SZ, SH, PR, and D bits have the same meaning as for normal address translation, but the C and WT bits have no meaning with regard to this page. Since burst transfer is prohibited for PCMCIA areas, the SA and TC bits also have no meaning. Rev.7.00 Oct. 10, 2008 Page 143 of 1074 REJ09B0366-0700 Section 4 Caches When a prefetch instruction is issued for the SQ area, address translation is performed and external memory address bits [28:10] are generated in accordance with the SZ bit specification. For external memory address bits [9:5], the address prior to address translation is generated in the same way as when the MMU is off. External memory address bits [4:0] are fixed at 0. Transfer from the SQs to external memory is performed to this address. • When MMU is off The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address to issue a PREF instruction. The meaning of address bits [31:0] is as follows: [31:26]: [25:6]: [5]: [4:2]: [1:0] 111000 Address 0/1 Don't care 00 Store queue specification External memory address bits [25:6] 0: SQ0 specification 1: SQ1 specification and external memory address bit [5] No meaning in a prefetch Fixed at 0 External memory address bits [28:26], which cannot be generated from the above address, are generated from the QACR0/1 registers. QACR0 [4:2]: QACR1 [4:2]: External memory address bits [28:26] corresponding to SQ0 External memory address bits [28:26] corresponding to SQ1 External memory address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. In the SH7750, data transfer to a PCMCIA interface area cannot be performed using an SQ. In the SH7750S or SH7750R, data transfer to a PCMCIA interface area is always performed using the SA and TC bits in the PTEA register. Rev.7.00 Oct. 10, 2008 Page 144 of 1074 REJ09B0366-0700 Section 4 Caches 4.7.4 SQ Protection Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is on or off. In the SH7750 or SH7750S, if an exception occurs in an SQ write, the SQ contents may be corrupted. In the SH7750R, original SQ contents are guaranteed. If an exception occurs in transfer from an SQ to external memory, the transfer to external memory will be aborted. • When MMU is on Operation is in accordance with the address translation information recorded in the UTLB, and MMUCR.SQMD. Write type exception judgment is performed for writes to the SQs, and read type for transfer from the SQs to external memory (PREF instruction), and a TLB miss exception, protection violation exception, or initial page write exception is generated. However, if SQ access is enabled, in privileged mode only, by MMUCR.SQMD, an address error will be flagged in user mode even if address translation is successful. • When MMU is off Operation is in accordance with MMUCR.SQMD. 0: Privileged/user access possible 1: Privileged access possible If the SQ area is accessed in user mode when MMUCR.SQMD is set to 1, an address error will be flagged. 4.7.5 Reading the SQs (SH7750R Only) In the SH7750R, a load instruction may be executed in the privileged mode to read the contents of the SQs from the address range of H'FF001000 to H'FF00103C in the P4 area. Only longword access is possible. [31:6] [5] [4:2] [1:0] : H'FF001000 : 0/1 : LW specification : 00 : Store queue specification : 0: SQ0 specification, 1: SQ1 specification : Specification of longword position in SQ0 or SQ1 : Fixed at 0 Rev.7.00 Oct. 10, 2008 Page 145 of 1074 REJ09B0366-0700 Section 4 Caches 4.7.6 SQ Usage Notes If an exception occurs within the three instructions preceding an instruction that writes to an SQ in the SH7750 and SH7750S, a branch may be made to the exception handling routine after execution of the SQ write that should be suppressed when an exception occurs. This may be due to the bug described in (1) or (2) below. (1) When SQ data is transferred to external memory within a normal program If a PREF instruction for transfer from an SQ to external memory is included in the three instructions preceding an SQ store instruction, the SQ is updated because the SQ write that should be suppressed when a branch is made to the exception handling routine is executed, and after returning from the exception handling routine the execution order of the PREF instruction and SQ store instruction is reversed, so that erroneous data may be transferred to external memory. (2) When SQ data is transferred to external memory in an exception handling routine If store queue contents are transferred to external memory within an exception handling routine, erroneous data may be transferred to external memory. Example 1: When an SQ store instruction is executed after a PREF instruction for transfer from that same SQ to external memory PREF instruction ; PREF instruction for transfer from SQ to external memory ; Address of this instruction is saved to SPC when exception occurs. ; Instruction 1, instruction 2, or instruction 3 may be executed on return from exception handling routine. Instruction 1 ; May be executed if an SQ store instruction. Instruction 2 ; May be executed if an SQ store instruction. Instruction 3 ; May be executed if an SQ store instruction. Instruction 4 ; Not executed even if an SQ store instruction. Rev.7.00 Oct. 10, 2008 Page 146 of 1074 REJ09B0366-0700 Section 4 Caches Example 2: When an instruction that generates an exception branches using a branch instruction Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if instruction 1 is a delay slot instruction and an instruction to store data to SQ. Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7 (branch destination of instruction 1) ; May be executed if an SQ access instruction. Instruction 8 ; May be executed if an SQ store instruction. Example 3: When an instruction that generates an exception does not branch using a branch instruction Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if an SQ store instruction. Instruction 3 ; May be executed if an SQ store instruction. Instruction 4 ; May be executed if an SQ store instruction. Instruction 5 To recover from this problem it is necessary that conditions A and B be satisfied. A: After the PREF instruction to transfer data from the store queue (SQ0, SQ1) to external memory, a store instruction for the same store queue must be executed, and conditions (1) and (2) below must be satisfied. (1) Three NOP instructions*1 must be inserted between the above two instructions. (2) There must not be a PREF instruction to transfer data from the store queue to external memory in the delay slot of the branch instruction. B: There must be no PREF instruction to transfer data from the store queue to external memory executed in the exception handling routine. If such an instruction is executed, and if there is a store to the store queue instruction among the four instructions*2 at the address referred to by SPC, the data transferred to external memory by the PREF instruction may indicate that execution of the store instruction has completed. Notes: 1. If there are other instructions between the above two instructions, the problem can be avoided if the other instructions and NOP instructions together total three or more instructions. Rev.7.00 Oct. 10, 2008 Page 147 of 1074 REJ09B0366-0700 Section 4 Caches 2. If the instruction at the address referred to by SPC is a branch instruction the two instructions at the branch destination may be affected. Rev.7.00 Oct. 10, 2008 Page 148 of 1074 REJ09B0366-0700 Section 5 Exceptions Section 5 Exceptions 5.1 5.1.1 Overview Features Exception handling is processing handled by a special routine, separate from normal program processing, that is executed by the CPU in case of abnormal events. For example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing. The process of generating an exception handling request in response to abnormal termination, and passing control to a user-written exception handling routine, in order to support such functions, is given the generic name of exception handling. SH-4 exception handling is of three kinds: for resets, general exceptions, and interrupts. 5.1.2 Register Configuration The registers used in exception handling are shown in table 5.1. Table 5.1 Name TRAPA exception register Exception event register Interrupt event register Exception-Related Registers Abbreviation R/W TRA EXPEVT INTEVT R/W R/W R/W Initial Value*1 Undefined H'0000 0000/ H'0000 0020*1 Undefined P4 Address*2 Area 7 Address*2 Access Size H'FF00 0020 H'1F00 0020 32 H'FF00 0024 H'1F00 0024 32 H'FF00 0028 H'1F00 0028 32 Notes: 1. H'0000 0000 is set in a power-on reset, and H'0000 0020 in a manual reset. 2. This is the address when using the virtual/physical address space P4 area. The area 7 address is the address used when making an access from physical address space area 7 using the TLB. Rev.7.00 Oct. 10, 2008 Page 149 of 1074 REJ09B0366-0700 Section 5 Exceptions 5.2 Register Descriptions There are three registers related to exception handling. Addresses are allocated to these registers, and they can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs. EXPEVT can also be modified by software. 2. The interrupt event register (INTEVT) resides at P4 address H'FF00 0028, and contains a 12bit exception code. The exception code set in INTEVT is that for an interrupt request. The exception code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software. 3. The TRAPA exception register (TRA) resides at P4 address H'FF00 0020, and contains 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software. The bit configurations of EXPEVT, INTEVT, and TRA are shown in figure 5.1. EXPEVT and INTEVT 31 0 TRA 31 0 10 9 0 imm 210 00 12 11 0 Exception code 0 Legend: 0: Reserved bits. These bits are always read as 0, and should only be written with 0. imm: 8-bit immediate data of the TRAPA instruction Figure 5.1 Register Bit Configurations Rev.7.00 Oct. 10, 2008 Page 150 of 1074 REJ09B0366-0700 Section 5 Exceptions 5.3 5.3.1 Exception Handling Functions Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15(SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address. An exception handling routine is a program written by the user to handle a specific exception. The exception handling routine is terminated and control returned to the original program by executing a return-from-exception instruction (RTE). This instruction restores the PC and SR contents and returns control to the normal processing routine at the point at which the exception occurred. The SGR contents are not written back to R15 by an RTE instruction. The basic processing flow is as follows. See section 2, Programming Model, for the meaning of the individual SR bits. 1. 2. 3. 4. 5. 6. The PC, SR, and R15 contents are saved in SPC, SSR, and SGR. The block bit (BL) in SR is set to 1. The mode bit (MD) in SR is set to 1. The register bank bit (RB) in SR is set to 1. In a reset, the FPU disable bit (FD) in SR is cleared to 0. The exception code is written to bits 11–0 of the exception event register (EXPEVT) or interrupt event register (INTEVT). 7. The CPU branches to the determined exception handling vector address, and the exception handling routine begins. 5.3.2 Exception Handling Vector Addresses The reset vector address is fixed at H'A000 0000. General exception and interrupt vector addresses are determined by adding the offset for the specific event to the vector base address, which is set by software in the vector base register (VBR). In the case of the TLB miss exception, for example, the offset is H'0000 0400, so if H'9C08 0000 is set in VBR, the exception handling vector address will be H'9C08 0400. If a further exception occurs at the exception handling vector address, a duplicate exception will result, and recovery will be difficult; therefore, fixed physical addresses (P1, P2) should be specified for vector addresses. Rev.7.00 Oct. 10, 2008 Page 151 of 1074 REJ09B0366-0700 Section 5 Exceptions 5.4 Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Priority Priority Vector Level Order Address 1 1 1 1 1 2 1 3 4 0 1 2 3 4 4 4 4 5 5 6 6 7 7 8 9 4 10 Offset Exception Code H'000 H'020 H'000 H'140 H'140 Exception Execution Category Mode Exception Reset Abort type Power-on reset Manual reset H-UDI reset Instruction TLB multiple-hit exception H'A000 0000 — H'A000 0000 — H'A000 0000 — H'A000 0000 — H'A000 0000 — (VBR/DBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR/DBR) Data TLB multiple-hit exception 1 General exception ReUser break before instruction 1 execution execution* type Instruction address error Instruction TLB miss exception Instruction TLB protection violation exception General illegal instruction exception 2 2 2 2 2 H'100/— H'1E0 H'100 H'400 H'100 H'100 H'100 H'100 H'100 H'100 H'100 H'400 H'400 H'100 H'100 H'100 H'100 H'100 H'0E0 H'040 H'0A0 H'180 H'1A0 H'800 H'820 H'0E0 H'100 H'040 H'060 H'0A0 H'0C0 H'120 H'080 H'160 Slot illegal instruction exception 2 General FPU disable exception 2 Slot FPU disable exception Data address error (read) Data address error (write) 2 2 2 Data TLB miss exception (read) 2 Data TLB miss exception (write) 2 Data TLB protection violation exception (read) Data TLB protection violation exception (write) FPU exception Initial page write exception Completion Unconditional trap (TRAPA) type User break after instruction 1 execution* 2 2 2 2 2 2 H'100/— H'1E0 Rev.7.00 Oct. 10, 2008 Page 152 of 1074 REJ09B0366-0700 Section 5 Exceptions Exception Execution Category Mode Exception Interrupt Completion Nonmaskable interrupt type External IRL3–IRL0 0 interrupts 1 2 3 4 5 6 7 8 9 A B C D E Peripheral TMU0 module TMU1 interrupt (module/ TMU2 source) TMU3 TMU4 RTC TUNI0 4 TUNI1 TUNI2 TICPI2 TUNI3 TUNI4 ATI PRI CUI SCI ERI RXI TXI TEI WDT REF ITI RCMI ROVI H-UDI GPIO H-UDI GPIOI *2 (VBR) H'600 Priority Priority Vector Level Order Address 3 4 — *2 (VBR) (VBR) Exception Code H'1C0 H'200 H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360 H'380 H'3A0 H'3C0 H'400 H'420 H'440 H'460 H'B00 H'B80 H'480 H'4A0 H'4C0 H'4E0 H'500 H'520 H'540 H'560 H'580 H'5A0 H'600 H'620 Offset H'600 H'600 Rev.7.00 Oct. 10, 2008 Page 153 of 1074 REJ09B0366-0700 Section 5 Exceptions Exception Execution Category Mode Exception Interrupt Completion Peripheral DMAC type module interrupt (module/ source) Priority Priority Vector Level Order Address DMTE0 4 DMTE1 DMTE2 DMTE3 DMTE4 *3 DMTE5 *3 DMTE6 *3 DMTE7 *3 DMAE SCIF ERI RXI BRI TXI *2 (VBR) Exception Code H'640 H'660 H'680 H'6A0 H'780 H'7A0 H'7C0 H'7E0 H'6C0 H'700 H'720 H'740 H'760 Offset H'600 Priority: Priority is first assigned by priority level, then by priority order within each level (the lowest number represents the highest priority). Exception transition destination: Control passes to H'A000 0000 in a reset, and to [VBR + offset] in other cases. Exception code: Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt. IRL: Interrupt request level (pins IRL3–IRL0). Module/source: See the sections on the relevant peripheral modules. Notes: 1. When BRCR.UBDE = 1, PC = DBR. In other cases, PC = VBR + H'100. 2. The priority order of external interrupts and peripheral module interrupts can be set by software. 3. SH7750R only. Rev.7.00 Oct. 10, 2008 Page 154 of 1074 REJ09B0366-0700 Section 5 Exceptions 5.5 5.5.1 Exception Flow Exception Flow Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 5.2 shows the relative priority order of the different kinds of exceptions (reset/general exception/interrupt). Register settings in the event of an exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC, but other registers may be set automatically by hardware, depending on the exception. For details, see section 5.6, Description of Exceptions. Also, see section 5.6.4, Priority Order with Multiple Exceptions, for exception handling during execution of a delayed branch instruction and a delay slot instruction, and in the case of instructions in which two data accesses are performed. Reset requested? No Execute next instruction Yes General exception requested? No Interrupt requested? No Yes Is highestYes priority exception re-exception type? Cancel instruction execution No result Yes SSR ← SR SPC ← PC SGR ← R15 EXPEVT/INTEVT ← exception code SR.{MD,RB,BL} ← 111 PC ← (BRCR.UBDE=1 && User_Break? DBR: (VBR + Offset)) EXPEVT ← exception code SR. {MD, RB, BL, FD, IMASK} ← 11101111 PC ← H'A000 0000 Figure 5.2 Instruction Execution and Exception Handling Rev.7.00 Oct. 10, 2008 Page 155 of 1074 REJ09B0366-0700 Section 5 Exceptions 5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—the general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception—are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline. These exceptions therefore all have the same priority. General exceptions are detected in the order of instruction execution. However, exception handling is performed in the order of instruction flow (program order). Thus, an exception for an earlier instruction is accepted before that for a later instruction. An example of the order of acceptance for general exceptions is shown in figure 5.3. Rev.7.00 Oct. 10, 2008 Page 156 of 1074 REJ09B0366-0700 Section 5 Exceptions Pipeline flow: Instruction n Instruction n+1 IF IF ID ID EX EX TLB miss (data access) MA WB MA WB General illegal instruction exception TLB miss (instruction access) IF ID EX MA WB Legend: IF: Instruction fetch ID: Instruction decode EX: Instruction execution MA: Memory access WB: Write-back Instruction n+2 Instruction n+3 IF ID EX MA WB Order of detection: General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously TLB miss (instruction n) Order of exception handling: TLB miss (instruction n) 1 Re-execution of instruction n General illegal instruction exception (instruction n+1) 2 Re-execution of instruction n+1 Program order TLB miss (instruction n+2) 3 Re-execution of instruction n+2 4 Execution of instruction n+3 Figure 5.3 Example of General Exception Acceptance Order Rev.7.00 Oct. 10, 2008 Page 157 of 1074 REJ09B0366-0700 Section 5 Exceptions 5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, general exception and interrupts are accepted. When the BL bit in SR is 1 and a general exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A000 0000). For the operation in the event of a user break, see section 20, User Break Controller (UBC). If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL bit has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held pending or accepted according to the setting made by software. Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable multiple exception state acceptance. 5.5.4 Return from Exception Handling The RTE instruction is used to return from exception handling. When the RTE instruction is executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns from the exception handling routine by branching to the SPC address. If SPC and SSR were saved to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and issuing the RTE instruction. 5.6 Description of Exceptions The various exception handling operations are described here, covering exception sources, transition addresses, and processor operation when a transition is made. Rev.7.00 Oct. 10, 2008 Page 158 of 1074 REJ09B0366-0700 Section 5 Exceptions 5.6.1 Resets (1) Power-On Reset • Sources: ⎯ SCK2 pin high level and RESET pin low level ⎯ When the watchdog timer overflows while the WT/IT bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits. • Transition address: H'A000 0000 • Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. For some CPU functions, the TRST pin and RESET pin must be driven low. It is therefore essential to execute a power-on reset and drive the TRST pin low when powering on. If the SCK2 pin is changed to the low level while the RESET pin is low, a manual reset may occur after the power-on reset operation. Do not drive the SCK2 pin low during this interval (see figure 22.3). Power_on_reset() { EXPEVT = H'00000000; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD=0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A0000000; } Rev.7.00 Oct. 10, 2008 Page 159 of 1074 REJ09B0366-0700 Section 5 Exceptions (2) Manual Reset • Sources: ⎯ SCK2 pin low level and RESET pin low level ⎯ When a general exception other than a user break occurs while the BL bit is set to 1 in SR ⎯ When the watchdog timer overflows while the WT/IT bit and RSTS bit are both set to 1 in WTCSR. For details, see section 10, Clock Oscillation Circuits. • Transition address: H'A000 0000 • Transition operations: Exception code H'020 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. Manual_reset() { EXPEVT = H'00000020; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } Rev.7.00 Oct. 10, 2008 Page 160 of 1074 REJ09B0366-0700 Section 5 Exceptions Table 5.3 Types of Reset Reset State Transition Conditions Internal States CPU Initialized Initialized On-Chip Peripheral Modules See Register Configuration in each section Type Power-on reset Manual reset SCK2 High Low RESET Low Low (3) H-UDI Reset • Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion) • Transition address: H'A000 0000 • Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. H-UDI_reset() { EXPEVT = H'00000000; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A0000000; } Rev.7.00 Oct. 10, 2008 Page 161 of 1074 REJ09B0366-0700 Section 5 Exceptions (4) Instruction TLB Multiple-Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections. TLB_multi_hit() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; EXPEVT = H'00000140; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } Rev.7.00 Oct. 10, 2008 Page 162 of 1074 REJ09B0366-0700 Section 5 Exceptions (5) Operand TLB Multiple-Hit Exception • Source: Multiple UTLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections. TLB_multi_hit() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; EXPEVT = H'00000140; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.IMASK = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } Rev.7.00 Oct. 10, 2008 Page 163 of 1074 REJ09B0366-0700 Section 5 Exceptions 5.6.2 General Exceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'040 (for a read access) or H'060 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions. Data_TLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'00000040 : H'00000060; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000400; } Rev.7.00 Oct. 10, 2008 Page 164 of 1074 REJ09B0366-0700 Section 5 Exceptions (2) Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'040 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions. ITLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000040; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000400; } Rev.7.00 Oct. 10, 2008 Page 165 of 1074 REJ09B0366-0700 Section 5 Exceptions (3) Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'080 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Initial_write_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000080; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev.7.00 Oct. 10, 2008 Page 166 of 1074 REJ09B0366-0700 Section 5 Exceptions (4) Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits) shown below. PR 00 01 10 11 Privileged Mode Only read access possible Read/write access possible Only read access possible Read/write access possible User Mode Access not possible Access not possible Only read access possible Read/write access possible • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Data_TLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'000000A0 : H'000000C0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev.7.00 Oct. 10, 2008 Page 167 of 1074 REJ09B0366-0700 Section 5 Exceptions (5) Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits) shown below. PR 0 1 Privileged Mode Access possible Access possible User Mode Access not possible Access possible • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'0A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. ITLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'000000A0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev.7.00 Oct. 10, 2008 Page 168 of 1074 REJ09B0366-0700 Section 5 Exceptions (6) Data Address Error • Sources: ⎯ Word data access from other than a word boundary (2n +1) ⎯ Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3) ⎯ Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) ⎯ Access to area H'8000 0000–H'FFFF FFFF in user mode • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'0E0 (for a read access) or H'100 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 3, Memory Management Unit (MMU). Data_address_error() { TEA = EXCEPTION_ADDRESS; PTEN.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access? H'000000E0: H'00000100; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev.7.00 Oct. 10, 2008 Page 169 of 1074 REJ09B0366-0700 Section 5 Exceptions (7) Instruction Address Error • Sources: ⎯ Instruction fetch from other than a word boundary (2n +1) ⎯ Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'0E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 3, Memory Management Unit (MMU). Instruction_address_error() { TEA = EXCEPTION_ADDRESS; PTEN.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'000000E0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev.7.00 Oct. 10, 2008 Page 170 of 1074 REJ09B0366-0700 Section 5 Exceptions (8) Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'0000 0100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The values of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR. The 8-bit immediate value in the TRAPA instruction is multiplied by 4, and the result is set in TRA [9:0]. Exception code H'160 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. TRAPA_exception() { SPC = PC + 2; SSR = SR; SGR = R15; TRA = imm Rm (unsigned), 1→T Otherwise, 0 → T 0011nnnnmmmm0110 — — CMP/GT CMP/PZ CMP/PL Rm,Rn Rn Rn When Rn > Rm (signed), 1 → T 0011nnnnmmmm0111 Otherwise, 0 → T When Rn ≥ 0, 1 → T Otherwise, 0 → T When Rn > 0, 1 → T Otherwise, 0 → T When any bytes are equal, 1→T Otherwise, 0 → T 1-step division (Rn ÷ Rm) MSB of Rn → Q, MSB of Rm → M, M^Q → T 0 → M/Q/T Signed, Rn × Rm → MAC, 32 × 32 → 64 bits Unsigned, Rn × Rm → MAC, 32 × 32 → 64 bits Rn – 1 → Rn; when Rn = 0, 1→T When Rn ≠ 0, 0 → T 0100nnnn00010001 0100nnnn00010101 0010nnnnmmmm1100 — — — — CMP/STR Rm,Rn DIV1 DIV0S DIV0U DMULS.L DMULU.L DT Rm,Rn Rm,Rn 0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 0011nnnnmmmm1101 0011nnnnmmmm0101 0100nnnn00010000 — — — — — — Rm,Rn Rm,Rn Rn Rev.7.00 Oct. 10, 2008 Page 218 of 1074 REJ09B0366-0700 Section 7 Instruction Set Instruction EXTS.B EXTS.W EXTU.B EXTU.W MAC.L Rm,Rn Rm,Rn Rm,Rn Rm,Rn Operation Rm sign-extended from byte → Rn Rm sign-extended from word → Rn Rm zero-extended from byte → Rn Rm zero-extended from word → Rn Instruction Code 0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111 Privileged — — — — — T Bit — — — — — @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → MAC Rn + 4 → Rn, Rm + 4 → Rm 32 × 32 + 64 → 64 bits @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → MAC Rn + 2 → Rn, Rm + 2 → Rm 16 × 16 + 64 → 64 bits Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn × Rm → MACL 32 × 32 → 32 bits Signed, Rn × Rm → MACL 16 × 16 → 32 bits Unsigned, Rn × Rm → MACL 16 × 16 → 32 bits 0 – Rm → Rn 0 – Rm – T → Rn, borrow → T Rn – Rm → Rn MAC.W 0100nnnnmmmm1111 — — MUL.L MULS.W MULU.W NEG NEGC SUB SUBC SUBV 0000nnnnmmmm0111 0010nnnnmmmm1111 0010nnnnmmmm1110 0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 — — — — — — — — — — — — Borrow — Borrow Underflow Rn – Rm – T → Rn, borrow → T 0011nnnnmmmm1010 Rn – Rm → Rn, underflow → T 0011nnnnmmmm1011 Rev.7.00 Oct. 10, 2008 Page 219 of 1074 REJ09B0366-0700 Section 7 Instruction Set Table 7.5 Instruction AND AND Logic Operation Instructions Operation Rn & Rm → Rn R0 & imm → R0 (R0 + GBR) & imm → (R0 + GBR) ~Rm → Rn Rn | Rm → Rn R0 | imm → R0 Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii Privileged — — — — — — — — Test result T Bit — — — — — — Rm,Rn #imm,R0 AND.B #imm,@(R0,GBR) NOT OR OR OR.B TAS.B Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) @Rn (R0 + GBR) | imm → (R0 + GBR)11001111iiiiiiii 0100nnnn00011011 When (Rn) = 0, 1 → T Otherwise, 0 → T In both cases, 1 → MSB of (Rn) Rn & Rm; when result = 0, 1→T Otherwise, 0 → T R0 & imm; when result = 0, 1→T Otherwise, 0 → T 0010nnnnmmmm1000 TST Rm,Rn — Test result TST #imm,R0 11001000iiiiiiii — Test result TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; when result 11001100iiiiiiii = 0, 1 → T Otherwise, 0 → T Rn ∧ Rm → Rn R0 ∧ imm → R0 (R0 + GBR) ∧ imm → (R0 + GBR) 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii — Test result XOR XOR Rm,Rn #imm,R0 — — — — — — XOR.B #imm,@(R0,GBR) Rev.7.00 Oct. 10, 2008 Page 220 of 1074 REJ09B0366-0700 Section 7 Instruction Set Table 7.6 Instruction ROTL ROTR ROTCL ROTCR SHAD Shift Instructions Operation Rn Rn Rn Rn Rm,Rn T ← Rn ← MSB LSB → Rn → T T ← Rn ← T T → Rn → T Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 Privileged — — — — — T Bit MSB LSB MSB LSB — When Rn ≥ 0, Rn > Rm → [MSB → Rn] T ← Rn ← 0 MSB → Rn → T 0100nnnn00100000 0100nnnn00100001 SHAL SHAR SHLD Rn Rn Rm,Rn — — — MSB LSB — When Rn ≥ 0, Rn > Rm → [0 → Rn] T ← Rn ← 0 0 → Rn → T Rn > 2 → Rn Rn > 8 → Rn Rn > 16 → Rn 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16 Rn Rn Rn Rn Rn Rn Rn Rn — — — — — — — — MSB LSB — — — — — — Rev.7.00 Oct. 10, 2008 Page 221 of 1074 REJ09B0366-0700 Section 7 Instruction Set Table 7.7 Instruction BF Branch Instructions Operation label When T = 0, disp × 2 + PC + 4 → PC When T = 1, nop Delayed branch; when T = 0, disp × 2 + PC + 4 → PC When T = 1, nop When T = 1, disp × 2 + PC + 4 → PC When T = 0, nop Delayed branch; when T = 1, disp × 2 + PC + 4 → PC When T = 0, nop Delayed branch, disp × 2 + P C + 4 → PC Delayed branch, Rn + PC + 4 → PC Instruction Code 10001011dddddddd Privileged — T Bit — BF/S label 10001111dddddddd — — BT label 10001001dddddddd — — BT/S label 10001101dddddddd — — BRA BRAF BSR BSRF JMP JSR RTS label Rn label Rn @Rn @Rn 1010dddddddddddd 0000nnnn00100011 — — — — — — — — — — — — — — Delayed branch, PC + 4 → PR, 1011dddddddddddd disp × 2 + PC + 4 → PC Delayed branch, PC + 4 → PR, 0000nnnn00000011 Rn + PC + 4 → PC Delayed branch, Rn → PC 0100nnnn00101011 Delayed branch, PC + 4 → PR, 0100nnnn00001011 Rn → PC Delayed branch, PR → PC 0000000000001011 Rev.7.00 Oct. 10, 2008 Page 222 of 1074 REJ09B0366-0700 Section 7 Instruction Set Table 7.8 Instruction CLRMAC CLRS CLRT LDC LDC LDC LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L LDTLB System Control Instructions Operation 0 → MACH, MACL 0→S 0→T Rm,SR Rm,GBR Rm,VBR Rm,SSR Rm,SPC Rm,DBR Rm,Rn_BANK @Rm+,SR @Rm+,GBR @Rm+,VBR @Rm+,SSR @Rm+,SPC @Rm+,DBR @Rm+,Rn_BANK Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR Rm → SR Rm → GBR Rm → VBR Rm → SSR Rm → SPC Rm → DBR Rm → Rn_BANK (n = 0 to 7) (Rm) → SR, Rm + 4 → R m (Rm) → GBR, Rm + 4 → R m (Rm) → VBR, Rm + 4 → R m (Rm) → SSR, Rm + 4 → R m (Rm) → SPC, Rm + 4 → R m (Rm) → DBR, Rm + 4 → R m (Rm) → Rn_BANK, Rm + 4 → R m Rm → MACH Rm → MACL Rm → PR (Rm) → MACH, Rm + 4 → R m (Rm) → MACL, Rm + 4 → R m (Rm) → PR, Rm + 4 → R m PTEH/PTEL → TLB R0 → (Rn) (without fetching cache block) No operation @Rn @Rn @Rn @Rn Instruction Code 0000000000101000 0000000001001000 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00111110 0100mmmm01001110 0100mmmm11111010 0100mmmm1nnn1110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00110111 0100mmmm01000111 0100mmmm11110110 0100mmmm1nnn0111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000111000 0000nnnn11000011 0000000000001001 Privileged — — — Privileged — Privileged Privileged Privileged Privileged Privileged Privileged — Privileged Privileged Privileged Privileged Privileged — — — — — — Privileged — — — — — — T Bit — — 0 LSB — — — — — — LSB — — — — — — — — — — — — — — — — — — — MOVCA.L R0,@Rn NOP OCBI OCBP OCBWB PREF Invalidates operand cache block 0000nnnn10010011 Writes back and invalidates operand cache block (Rn) → operand cache 0000nnnn10100011 Writes back operand cache block0000nnnn10110011 0000nnnn10000011 Rev.7.00 Oct. 10, 2008 Page 223 of 1074 REJ09B0366-0700 Section 7 Instruction Set Instruction RTE SETS SETT SLEEP STC STC STC STC STC STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STS STS STS STS.L STS.L STS.L TRAPA SR,Rn GBR,Rn VBR,Rn SSR,Rn SPC,Rn SGR,Rn DBR,Rn Rm_BANK,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn SSR,@-Rn SPC,@-Rn SGR,@-Rn DBR,@-Rn Rm_BANK,@-Rn MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn #imm Operation Delayed branch, SSR/SPC → SR/PC 1→S 1→T Sleep or standby SR → R n GBR → R n VBR → R n SSR → R n SPC → R n SGR → Rn DBR → R n Rm_BANK → Rn (m = 0 to 7) Rn – 4 → Rn, SR → (Rn) Rn – 4 → Rn, GBR → (Rn) Rn – 4 → Rn, VBR → (Rn) Rn – 4 → Rn, SSR → (Rn) Rn – 4 → Rn, SPC → (Rn) Rn – 4 → Rn, SGR → (Rn) Rn – 4 → Rn, DBR → (Rn) Instruction Code 0000000000101011 0000000001011000 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn00110010 0000nnnn01000010 0000nnnn00111010 0000nnnn11111010 0000nnnn1mmm0010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0100nnnn00110011 0100nnnn01000011 0100nnnn00110010 0100nnnn11110010 Privileged Privileged — — Privileged Privileged — Privileged Privileged Privileged Privileged Privileged Privileged Privileged — Privileged Privileged Privileged Privileged Privileged Privileged — — — — — — — T Bit — — 1 — — — — — — — — — — — — — — — — — — — — — — — — Rn – 4 → Rn, 0100nnnn1mmm0011 Rm_BANK → (Rn) (m = 0 to 7) MACH → R n MACL → R n PR → R n Rn – 4 → Rn, MACH → (Rn) Rn – 4 → Rn, MACL → (Rn) Rn – 4 → Rn, PR → (Rn) PC + 2 → SPC, SR → SSR, #imm FRm, 1 → T Otherwise, 0 → T FRn/FRm → FRn (float) FPUL → FRn FR0 * FRm + FRn → FRn FRn * FRm → FRn FRn ∧ H'80000000 → FRn FRn → FRn Instruction Code 1111nnnn10001101 1111nnnn10011101 1111nnnnmmmm1100 1111nnnnmmmm1000 1111nnnnmmmm0110 Privileged — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — T Bit — — — — — — — — — — — — — — — — — — — — Comparison result Comparison result — — — — — — — — (Rm) → FRn, Rm + 4 → Rm 1111nnnnmmmm1001 1111nnnnmmmm1010 1111nnnnmmmm1011 1111nnnnmmmm0111 1111nnn0mmm01100 1111nnn0mmmm1000 1111nnn0mmmm0110 (Rm) → DRn, Rm + 8 → Rm 1111nnn0mmmm1001 1111nnnnmmm01010 1111nnnnmmm01011 1111nnnnmmm00111 1111mmmm00011101 1111nnnn00001101 FRn & H'7FFF FFFF → FRn 1111nnnn01011101 1111nnnnmmmm0000 1111nnnnmmmm0100 1111nnnnmmmm0101 1111nnnnmmmm0011 1111nnnn00101101 1111nnnnmmmm1110 1111nnnnmmmm0010 1111nnnn01001101 1111nnnn01101101 1111nnnnmmmm0001 1111mmmm00111101 FRn – FRm → FRn (long) FRm → FPUL Rev.7.00 Oct. 10, 2008 Page 225 of 1074 REJ09B0366-0700 Section 7 Instruction Set Table 7.10 Floating-Point Double-Precision Instructions Instruction FABS FADD FCMP/EQ FCMP/GT FDIV FCNVDS FCNVSD FLOAT FMUL FNEG FSQRT FSUB FTRC DRn DRm,DRn DRm,DRn DRm,DRn DRm,DRn DRm,FPUL FPUL,DRn FPUL,DRn DRm,DRn DRn DRn DRm,DRn DRm,FPUL Operation Instruction Code Privileged — — — — — — — — — — — — — T Bit — — Comparison result Comparison result — — — — — — — — — DRn & H'7FFF FFFF FFFF FFFF 1111nnn001011101 → DRn DRn + DRm → DRn When DRn = DRm, 1 → T Otherwise, 0 → T When DRn > DRm, 1 → T Otherwise, 0 → T DRn /DRm → DRn 1111nnn0mmm00000 1111nnn0mmm00100 1111nnn0mmm00101 1111nnn0mmm00011 double_to_ float[DRm] → FPUL 1111mmm010111101 float_to_ double [FPUL] → DRn 1111nnn010101101 (float)FPUL → DRn DRn * DRm → DRn DRn ^ H'8000 0000 0000 0000 → DRn DRn → DRn 1111nnn000101101 1111nnn0mmm00010 1111nnn001001101 1111nnn001101101 1111nnn0mmm00001 1111mmm000111101 DRn – DRm → DRn (long) DRm → FPUL Table 7.11 Floating-Point Control Instructions Instruction LDS LDS LDS.L LDS.L STS STS STS.L STS.L Rm,FPSCR Rm,FPUL @Rm+,FPSCR @Rm+,FPUL FPSCR,Rn FPUL,Rn FPSCR,@-Rn FPUL,@-Rn Operation Rm → FPSCR Rm → FPUL (Rm) → FPSCR, Rm+4 → Rm (Rm) → FPUL, Rm+4 → Rm FPSCR → R n FPUL → R n Rn – 4 → Rn, FPSCR → (Rn) Rn – 4 → Rn, FPUL → (Rn) Instruction Code 0100mmmm01101010 0100mmmm01011010 0100mmmm01100110 0100mmmm01010110 0000nnnn01101010 0000nnnn01011010 0100nnnn01100010 0100nnnn01010010 Privileged — — — — — — — — T Bit — — — — — — — — Rev.7.00 Oct. 10, 2008 Page 226 of 1074 REJ09B0366-0700 Section 7 Instruction Set Table 7.12 Floating-Point Graphics Acceleration Instructions Instruction FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FIPR FTRV FRCHG FSCHG DRm,XDn XDm,DRn XDm,XDn @Rm,XDn @Rm+,XDn @(R0,Rm),XDn XDm,@Rn XDm,@-Rn XDm,@(R0,Rn) FVm,FVn XMTRX,FVn Operation DRm → XDn XDm → DRn XDm → XDn (Rm) → XDn (Rm) → XDn, Rm + 8 → Rm (R0 + Rm) → XDn XDm → (Rn) Rn – 8 → Rn, XDm → (Rn) XDm → (R0+Rn) inner_product [FVm, FVn] → FR[n+3] Instruction Code 1111nnn1mmm01100 1111nnn0mmm11100 1111nnn1mmm11100 1111nnn1mmmm1000 1111nnn1mmmm1001 1111nnn1mmmm0110 1111nnnnmmm11010 1111nnnnmmm11011 1111nnnnmmm10111 1111nnmm11101101 Privileged — — — — — — — — — — — — — T Bit — — — — — — — — — — — — — transform_vector [XMTRX, FVn] 1111nn0111111101 → FVn ~FPSCR.FR → FPSCR.FR ~FPSCR.SZ → FPSCR.SZ 1111101111111101 1111001111111101 7.4 7.4.1 Usage Notes Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction (H'FFFD) • Incorrect data may be written to the cache when a TRAPA instruction or undefined instruction code H'FFFD is executed. • The ITLB hit judgment may be incorrect when a TRAPA instruction or undefined instruction code H'FFFD is executed, causing a multi-hit exception to occur after re-registration. • Incorrect data may be written to an FPU-related register or to the MACH or MACL register when a TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD is executed. Conditions Under which Problem Occurs 1. Incorrect data may be written to the instruction cache when the following three conditions occur at the same time. a. The instruction cache is enabled (CCR.ICE = 1). Rev.7.00 Oct. 10, 2008 Page 227 of 1074 REJ09B0366-0700 Section 7 Instruction Set b. A TRAPA instruction or undefined instruction code H'FFFD in a cache-enabled area is executed. c. The four words of data following the TRAPA instruction or undefined instruction code H'FFFD mentioned in b. contain code that can be interpreted as an instruction to access (read or write) an address (H'F0000000 to H'F7FFFFFF) mapped to the internal cache or internal TLB. 2. Incorrect data may be written to the operand cache when the following three conditions occur at the same time. a. The operand cache is enabled (CCR.OCE = 1). b. Undefined instruction code H'FFFD is executed. c. The four words of data following the undefined instruction code H'FFFD mentioned in b. contain code that can be interpreted as an OCBI, OCBP, OCBWB, or TAS.B instruction accessing an address (H'E0000000 to H'E3FFFFFF) mapped to the internal store queue. 3. The ITLB hit judgment may be incorrect when the following three conditions occur at the same time. If an ITLB hit is erroneously judged to be a miss, ITLB re-registration is performed. This can cause an ITLB multi-hit exception to occur. a. The MMU enabled (MMUCR.AT = 1). b. A TRAPA instruction or undefined instruction code H'FFFD in a TLB conversion area (area U0, P0, or P3) is executed. c. The four words of data following the TRAPA instruction or undefined instruction code H'FFFD mentioned in b. contain code that can be interpreted as an instruction to access (read or write) an address (H'F0000000 to H'F7FFFFFF) mapped to the internal cache or internal TLB. 4. Incorrect data may be written to an FPU-related register (FR0 to FR15, XF0 to XF15, FPSCR, or FPUL) or to the MACH or MACL register when the following two conditions occur at the same time. a. A TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD is executed b. The eight words of data following the TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD mentioned in a. contain H'Fxxx (an instruction with H'F as the first four bits), excluding H'FFFD, and the code can be interpreted, in combination with FPSCR.PR at that point, as an undefined instruction. Example: Instruction H'FxxE (x: any hexadecimal digit) is defined here as undefined when FPSCR.PR is set to 1. Note: The number of instructions following the instructions mentioned above that may be affected by the problem is as follows: in the case of 1. to 3., the number of instructions that can be executed in 2xIck, and in the case of 4., the number of instructions that can be Rev.7.00 Oct. 10, 2008 Page 228 of 1074 REJ09B0366-0700 Section 7 Instruction Set executed in 4xIck. The maximum number of instructions that can be executed in 2xIck or 4xIck is four or eight, respectively. Therefore, the affected codes are those occurring in “the four words (or eight words) of data following the instruction.” Workarounds: To prevent the problem, use either of workarounds a. or b. below. a. Include a NOP instruction in the eight words of data following each TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD. b. Include an OR R0,R0 instruction in the five words of data following each TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD. This workaround also applies to cases where “the eight words of data following the … instruction … contain H'Fxxx,” as mentioned in condition 4. b., because two OR instructions are never executed simultaneously, so a minimum of 5xIck is required for execution. Rev.7.00 Oct. 10, 2008 Page 229 of 1074 REJ09B0366-0700 Section 7 Instruction Set Rev.7.00 Oct. 10, 2008 Page 230 of 1074 REJ09B0366-0700 Section 8 Pipelining Section 8 Pipelining This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. Definitions in this section may not be applicable to SH-4 Series products other than this LSI. 8.1 Pipelines Figure 8.1 shows the basic pipelines. Normally, a pipeline consists of five or six stages: instruction fetch (I), decode and register read (D), execution (EX/SX/F0/F1/F2/F3), data access (NA/MA), and write-back (S/FS). An instruction is executed as a combination of basic pipelines. Figure 8.2 shows the instruction execution patterns. Rev.7.00 Oct. 10, 2008 Page 231 of 1074 REJ09B0366-0700 Section 8 Pipelining 1. General Pipeline I D EX NA • Non-memory data access S • Write-back • Instruction fetch • Instruction • Operation decode • Issue • Register read • Destination address calculation for PC-relative branch 2. General Load/Store Pipeline I D EX • Address calculation MA • Memory data access S • Write-back • Instruction fetch • Instruction decode • Issue • Register read 3. Special Pipeline I D SX • Operation NA • Non-memory data access S • Write-back • Instruction fetch • Instruction decode • Issue • Register read 4. Special Load/Store Pipeline I D SX • Address calculation MA • Memory data access S • Write-back • Instruction fetch • Instruction decode • Issue • Register read 5. Floating-Point Pipeline I D F1 • Computation 1 F2 • Computation 2 FS • Computation 3 • Write-back • Instruction fetch • Instruction decode • Issue • Register read 6. Floating-Point Extended Pipeline I D F0 • Computation 0 F1 • Computation 1 F2 • Computation 2 FS • Computation 3 • Write-back • Instruction fetch • Instruction decode • Issue • Register read 7. FDIV/FSQRT Pipeline F3 Computation: Takes several cycles Figure 8.1 Basic Pipelines Rev.7.00 Oct. 10, 2008 Page 232 of 1074 REJ09B0366-0700 Section 8 Pipelining 1. 1-step operation: 1 issue cycle EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS, single-/double-precision FABS/FNEG I D EX NA S 2. Load/store: 1 issue cycle MOV.[BWL]. FMOV*@, LDS.L to FPUL, LDTLB, PREF, STS.L from FPUL/FPSCR I D EX MA S 3. GBR-based load/store: 1 issue cycle MOV.[BWL]@(d,GBR) I D SX MA S 4. JMP, RTS, BRAF: 2 issue cycles I D EX D NA EX S NA S 5. TST.B: 3 issue cycles I D SX D MA SX D S NA SX S NA S 6. AND.B, OR.B, XOR.B: 4 issue cycles I D SX D MA SX D S NA SX D S NA SX S MA S 7. TAS.B: 5 issue cycles I D EX D MA EX D S MA EX D S NA EX D S NA EX S MA S 8. RTE: 5 issue cycles I D EX D NA EX D S NA EX D S NA EX D S NA EX S NA S 9. SLEEP: 4 issue cycles I D EX D NA EX D S NA EX D S NA EX S NA S Figure 8.2 Instruction Execution Patterns Rev.7.00 Oct. 10, 2008 Page 233 of 1074 REJ09B0366-0700 Section 8 Pipelining 10. OCBI: 1 issue cycle I D EX MA S MA 11. OCBP, OCBWB: 1 issue cycle I D EX MA S MA MA MA MA 12. MOVCA.L: 1 issue cycle I D EX MA S MA MA MA MA MA MA 13. TRAPA: 7 issue cycles I D EX D NA EX D S NA EX D S NA EX D S NA EX D S NA EX D S NA EX S NA S 14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle I D EX NA SX S SX 15. LDC to GBR: 3 issue cycles I D EX D NA SX D S SX 16. LDC to SR: 4 issue cycles I D EX D NA SX D S SX D SX 17. LDC.L to DBR/Rp_BANK/SSR/SPC/VBR: 1 issue cycle I D EX MA SX S SX 18. LDC.L to GBR: 3 issue cycles I D EX D MA SX D S SX Figure 8.2 Instruction Execution Patterns (cont) Rev.7.00 Oct. 10, 2008 Page 234 of 1074 REJ09B0366-0700 Section 8 Pipelining 19. LDC.L to SR: 4 issue cycles I D EX D MA SX D S SX D SX 20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles I D SX D NA SX S NA S 21. STC.L from SGR: 3 issue cycles I D SX D NA SX D S NA SX S NA S 22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles I D SX D NA SX S MA S 23. STC.L from SGR: 3 issue cycles I D SX D NA SX D S NA SX S MA S 24. LDS to PR, JSR, BSRF: 2 issue cycles I D EX D NA SX S SX 25. LDS.L to PR: 2 issue cycles I D EX D MA SX S SX 26. STS from PR: 2 issue cycles I D SX D NA SX S NA S 27. STS.L from PR: 2 issue cycles I D SX D NA SX S MA S 28. CLRMAC, LDS to MACH/L: 1 issue cycle I D EX NA F1 S F1 F2 FS 29. LDS.L to MACH/L: 1 issue cycle I D EX MA F1 S F1 F2 FS 30. STS from MACH/L: 1 issue cycle I D EX NA S Figure 8.2 Instruction Execution Patterns (cont) Rev.7.00 Oct. 10, 2008 Page 235 of 1074 REJ09B0366-0700 Section 8 Pipelining 31. STS.L from MACH/L: 1 issue cycle I D EX MA S 32. LDS to FPSCR: 1 issue cycle I D EX NA F1 S F1 F1 33. LDS.L to FPSCR: 1 issue cycle I D EX MA F1 S F1 F1 34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W I D EX D f1 f1 f1 f1 F2 FS NA EX S NA (CPU) S (FPU) 35. MAC.W, MAC.L: 2 issue cycles I D EX D f1 f1 f1 f1 F2 FS MA EX S MA (CPU) S (FPU) 36. Single-precision floating-point computation: 1 issue cycle FCMP/EQ,FCMP/GT, FADD,FLOAT,FMAC,FMUL,FSUB,FTRC,FRCHG,FSCHG I D F1 F2 FS 37. Single-precision FDIV/SQRT: 1 issue cycle I D F1 F2 FS F3 F1 F2 FS 38. Double-precision floating-point computation 1: 1 issue cycle FCNVDS, FCNVSD, FLOAT, FTRC I D F1 d F2 F1 FS F2 FS 39. Double-precision floating-point computation 2: 1 issue cycle FADD, FMUL, FSUB I D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d FS F2 F1 FS F2 F1 FS F2 FS Figure 8.2 Instruction Execution Patterns (cont) Rev.7.00 Oct. 10, 2008 Page 236 of 1074 REJ09B0366-0700 Section 8 Pipelining 40. Double-precision FCMP: 2 issue cycles FCMP/EQ,FCMP/GT I D F1 D F2 F1 FS F2 FS 41. Double-precision FDIV/SQRT: 1 issue cycle FDIV, FSQRT I D F1 d F2 F1 FS F2 F3 F1 F2 F1 FS F2 F1 FS F2 42. FIPR: 1 issue cycle I D F0 F1 F2 FS FS 43. FTRV: 1 issue cycle I D F0 d F1 F0 d F2 F1 F0 d FS F2 F1 F0 FS F2 F1 FS F2 FS Notes: ?? : Cannot overlap a stage of the same kind, except when two instructions are executed in parallel. : Locks D-stage : Register read only : Locks, but no operation is executed. : Can overlap another f1, but not another F1. D d ?? f1 Figure 8.2 Instruction Execution Patterns (cont) Rev.7.00 Oct. 10, 2008 Page 237 of 1074 REJ09B0366-0700 Section 8 Pipelining 8.2 Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 8.1 Instruction Groups 1. MT Group CLRT CMP/EQ CMP/EQ CMP/GE CMP/GT 2. EX Group ADD ADD ADDC ADDV AND AND DIV0S DIV0U DIV1 DT EXTS.B EXTS.W EXTU.B EXTU.W MOV MOVA Rm,Rn Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,Rn #imm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn MOVT NEG NEGC NOT OR OR ROTCL ROTCR ROTL ROTR SHAD SHAL SHAR SHLD SHLL Rn Rm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rn Rn Rn Rn Rm,Rn Rn Rn Rm,Rn Rn Rn SHLL2 SHLL8 SHLR SHLR16 SHLR2 SHLR8 SUB SUBC SUBV SWAP.B SWAP.W XOR XOR XTRCT Rn Rn Rn Rn Rn Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn CMP/HI CMP/HS CMP/PL CMP/PZ CMP/STR Rm,Rn Rm,Rn Rn Rn Rm,Rn MOV NOP SETT TST TST #imm,R0 Rm,Rn Rm,Rn @(disp,PC),R0 SHLL16 Rev.7.00 Oct. 10, 2008 Page 238 of 1074 REJ09B0366-0700 Section 8 Pipelining 3. BR Group BF BF/S 4. LS Group FABS FABS FLDI0 FLDI1 FLDS FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV.S FMOV.S DRn FRn FRn FRn FRm,FPUL @(R0,Rm),DRn @(R0,Rm),XDn @Rm,DRn @Rm,XDn @Rm+,DRn @Rm+,XDn DRm,@(R0,Rn) DRm,@-Rn DRm,@Rn DRm,DRn DRm,XDn FRm,FRn XDm,@(R0,Rn) XDm,@-Rn XDm,@Rn XDm,DRn XDm,XDn @(R0,Rm),FRn @Rm,FRn FMOV.S FMOV.S FMOV.S FMOV.S FNEG FNEG FSTS LDS MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.L MOV.L MOV.L MOV.L MOV.L MOV.L @Rm+,FRn FRm,@(R0,Rn) FRm,@-Rn FRm,@Rn DRn FRn FPUL,FRn Rm,FPUL MOV.L MOV.L MOV.L MOV.L MOV.L MOV.W MOV.W MOV.W R0,@(disp,GBR) Rm,@(disp,Rn) Rm,@(R0,Rn) Rm,@-Rn Rm,@Rn @(disp,GBR),R0 @(disp,PC),Rn @(disp,Rm),R0 @(R0,Rm),Rn @Rm,Rn @Rm+,Rn R0,@(disp,GBR) R0,@(disp,Rn) Rm,@(R0,Rn) Rm,@-Rn Rm,@Rn R0,@Rn @Rn @Rn @Rn @Rn FPUL,Rn disp disp BRA BSR disp disp BT BT/S disp disp @(disp,GBR),R0 MOV.W @(disp,Rm),R0 @(R0,Rm),Rn @Rm,Rn @Rm+,Rn MOV.W MOV.W MOV.W MOV.W R0,@(disp,GBR) MOV.W R0,@(disp,Rn) Rm,@(R0,Rn) Rm,@-Rn Rm,@Rn MOV.W MOV.W MOVCA.L OCBI @(disp,GBR),R0 OCBP @(disp,PC),Rn @(disp,Rm),Rn @(R0,Rm),Rn @Rm,Rn @Rm+,Rn OCBWB PREF STS Rev.7.00 Oct. 10, 2008 Page 239 of 1074 REJ09B0366-0700 Section 8 Pipelining 5. FE Group FADD FADD FCMP/EQ FCMP/GT FCNVDS FCNVSD FDIV FDIV DRm,DRn FRm,FRn FRm,FRn FRm,FRn DRm,FPUL FPUL,DRn DRm,DRn FRm,FRn FIPR FLOAT FLOAT FMAC FMUL FMUL FRCHG FSCHG FVm,FVn FPUL,DRn FPUL,FRn FSQRT FSQRT FSUB DRn FRn DRm,DRn FRm,FRn DRm,FPUL FRm,FPUL XMTRX,FVn FR0,FRm,FRn FSUB DRm,DRn FRm,FRn FTRC FTRC FTRV Rev.7.00 Oct. 10, 2008 Page 240 of 1074 REJ09B0366-0700 Section 8 Pipelining 6. CO Group AND.B BRAF BSRF CLRMAC CLRS DMULS.L DMULU.L FCMP/EQ FCMP/GT JMP JSR LDC LDC LDC LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L Rm,Rn Rm,Rn DRm,DRn DRm,DRn @Rn @Rn Rm,DBR Rm,GBR Rm,Rp_BANK Rm,SPC Rm,SR Rm,SSR Rm,VBR @Rm+,DBR @Rm+,GBR #imm,@(R0,GBR) LDS Rm Rm LDS LDS LDS LDS.L LDS.L LDS.L LDS.L LDS.L LDTLB MAC.L MAC.W MUL.L MULS.W MULU.W OR.B RTE RTS SETS SLEEP DBR,Rn GBR,Rn Rp_BANK,Rn SGR,Rn SPC,Rn @Rm+,@Rn+ @Rm+,@Rn+ Rm,Rn Rm,Rn Rm,Rn Rm,FPSCR Rm,MACH Rm,MACL Rm,PR @Rm+,FPSCR @Rm+,FPUL @Rm+,MACH @Rm+,MACL @Rm+,PR STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STS STS STS STS SR,Rn SSR,Rn VBR,Rn DBR,@-Rn GBR,@-Rn Rp_BANK,@-Rn SGR,@-Rn SPC,@-Rn SR,@-Rn SSR,@-Rn VBR,@-Rn FPSCR,Rn MACH,Rn MACL,Rn PR,Rn FPSCR,@-Rn FPUL,@-Rn MACH,@-Rn MACL,@-Rn PR,@-Rn @Rn #imm #imm,@(R0,GBR) #imm,@(R0,GBR) #imm,@(R0,GBR) STS.L STS.L STS.L STS.L STS.L TAS.B TRAPA TST.B XOR.B @Rm+,Rp_BANK STC @Rm+,SPC @Rm+,SR @Rm+,SSR @Rm+,VBR STC STC STC STC Rev.7.00 Oct. 10, 2008 Page 241 of 1074 REJ09B0366-0700 Section 8 Pipelining Table 8.2 Parallel-Executability 2nd Instruction MT EX O X O O O X BR O O X O O X LS O O O X O X FE O O O O X X CO X X X X X X 1st Instruction MT EX BR LS FE CO O O O O O X Legend: O: Can be executed in parallel X: Cannot be executed in parallel 8.3 Execution Cycles and Pipeline Stalling There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware unit operates on one of these clocks, as follows: • I-clock: CPU, FPU, MMU, caches • B-clock: External bus controller • P-clock: Peripheral units The frequency ratios of the three clocks are determined with the frequency control register (FRQCR). In this section, machine cycles are based on the I-clock unless otherwise specified. For details of FRQCR, see section 10, Clock Oscillation Circuits. Instruction execution cycles are summarized in table 8.3. Penalty cycles due to a pipeline stall or freeze are not considered in this table. • Issue rate: Interval between the issue of an instruction and that of the next instruction • Latency: Interval between the issue of an instruction and the generation of its result (completion) • Instruction execution pattern (see figure 8.2) • Locked pipeline stages (see table 8.3) • Interval between the issue of an instruction and the start of locking (see table 8.3) • Lock time: Period of locking in machine cycle units (see table 8.3) Rev.7.00 Oct. 10, 2008 Page 242 of 1074 REJ09B0366-0700 Section 8 Pipelining The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 8.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction; the only exception is when two instructions are executed in parallel under parallel-executability conditions. Refer to (a) through (d) in figure 8.3 for some simple examples. Latency is the interval between issue and completion of an instruction, and is also the interval between the execution of two instructions with an interdependent relationship. When there is interdependency between two instructions fetched simultaneously, the latter of the two is stalled for the following number of cycles: • (Latency) cycles when there is flow dependency (read-after-write) • (Latency - 1) or (latency - 2) cycles when there is output dependency (write-after-write) ⎯ Single/double-precision FDN, FSQRT is the preceding instruction (latency – 1) cycles ⎯ The other FE group is the preceding instruction (latency – 2) cycles • 5 or 2 cycles when there is anti-flow dependency (write-after-read), as in the following cases: ⎯ FTRV is the preceding instruction (5 cycle) ⎯ A double-precision FADD, FSUB, or FMUL is the preceding instruction (2 cycles) In the case of flow dependency, latency may be exceptionally increased or decreased, depending on the combination of sequential instructions (figure 8.3 (e)). • When a floating-point (FP) computation is followed by an FP register store, the latency of the FP computation may be decreased by 1 cycle. • If there is a load of the shift amount immediately before an SHAD/SHLD instruction, the latency of the load is increased by 1 cycle. • If an instruction with a latency of less than 2 cycles, including write-back to an FP register, is followed by a double-precision FP instruction, FIPR, or FTRV, the latency of the first instruction is increased to 2 cycles. The number of cycles in a pipeline stall due to flow dependency will vary depending on the combination of interdependent instructions or the fetch timing (see figure 8.3. (e)). Output dependency occurs when the destination operands are the same in a preceding FE group instruction and a following LS group instruction. For the stall cycles of an instruction with output dependency, the longest latency to the last writeback among all the destination operands must be applied instead of “latency” (see figure 8.3 (f)). A stall due to output dependency with respect to FPSCR, which reflects the result of an FP Rev.7.00 Oct. 10, 2008 Page 243 of 1074 REJ09B0366-0700 Section 8 Pipelining operation, never occurs. For example, when FADD follows FDIV with no dependency between FP registers, FADD is not stalled even if both instructions update the cause field of FPSCR. Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3 (g). If an executing instruction locks any resource—i.e. a function block that performs a basic operation—a following instruction that happens to attempt to use the locked resource must be stalled (figure 8.3 (h)). This kind of stall can be compensated by inserting one or more instructions independent of the locked resource to separate the interfering instructions. For example, when a load instruction and an ADD instruction that references the loaded value are consecutive, the 2cycle stall of the ADD is eliminated by inserting three instructions without dependency. Software performance can be improved by such instruction scheduling. Other penalties arise in the event of exceptions or external data accesses, as follows. • • • • Instruction TLB miss Instruction access to external memory (instruction cache miss, etc.) Data access to external memory (operand cache miss, etc.) Data access to a memory-mapped control register. During the penalty cycles of an instruction TLB miss or external instruction access, no instruction is issued, but execution of instructions that have already been issued continues. The penalty for a data access is a pipeline freeze: that is, the execution of uncompleted instructions is interrupted until the arrival of the requested data. The number of penalty cycles for instruction and data accesses is largely dependent on the user's memory subsystems. Rev.7.00 Oct. 10, 2008 Page 244 of 1074 REJ09B0366-0700 Section 8 Pipelining (a) Serial execution: non-parallel-executable instructions SHAD R0,R1 ADD R2,R3 next I I D 1 issue cycle EX NA EX D 1 stall cycle D ... S NA EX-group SHAD and EX-group ADD cannot be executed in parallel. Therefore, SHAD is issued first, and the following ADD is recombined with the next instruction. S I (b) Parallel execution: parallel-executable and no dependency ADD R2,R1 MOV.L @R4,R5 I I D D 1 issue cycle EX NA EX MA S S EX-group ADD and LS-group MOV.L can be executed in parallel. Overlapping of stages in the 2nd instruction is possible. (c) Issue rate: multi-step instruction 4 issue cycles AND.B#1,@(R0,GBR) I D SX D MA SX D S NA SX D i I S NA SX D ... AND.B and MOV are fetched simultaneously, but MOV is stalled due to resource locking. After the lock is released, MOV is refetched together with the next instruction. S MOV next R1,R2 I 4 stall cycles S MA E S A (d) Branch BT/S L_far ADD R0,R1 SUB R2,R3 I I D D I EX EX D NA NA EX S S NA No stall occurs if the branch is not taken. S BT/S L_far ADD R0,R1 L_far BT L_skip ADD #1,R0 L_skip: I I D D 2-cycle latency for I-stage of branch destination If the branch is taken, the I-stage of the EX S NA branch destination is stalled for the period EX S NA of latency. This stall can be covered with a 1 stall cycle delay slot instruction which is not parallelI D ... executable with the branch instruction. EX — D NA — ... S — Even if the BT/BF branch is taken, the Istage of the branch destination is not stalled if the displacement is zero. I I D D I No stall Figure 8.3 Examples of Pipelined Execution Rev.7.00 Oct. 10, 2008 Page 245 of 1074 REJ09B0366-0700 Section 8 Pipelining (e) Flow dependency MOV ADD R0,R1 R2,R1 I I D D Zero-cycle latency EX NA S EX NA S 1-cycle latency EX NA S EX MA D ... The following instruction, ADD, is not stalled when executed after an instruction with zero-cycle latency, even if there is dependency. ADD and MOV.L are not executed in parallel, since MOV.L references the result of ADD as its destination address. ADD R2,R1 MOV.L @R1,R1 next D i I 1 stall cycle I I S MOV.L @R1,R1 ADD R0,R1 next I D I I EX D ... 2-cycle latency S EX NA 1 stall cycle MA S Because MOV.L and ADD are not fetched simultaneously in this example, ADD is stalled for only 1 cycle even though the latency of MOV.L is 2 cycles. 2-cycle latency 1-cycle increase MOV.L @R1,R1 SHAD R1,R2 next I D I I EX D ... MA S d EX NA S Due to the flow dependency between the load and the SHAD/SHLD shift amount, the latency of the load is increased to 3 cycles. 2 stall cycles 4-cycle latency for FPSCR FADD STS STS FR1,FR2 FPUL,R1 FPSCR,R2 I D I F1 D I F2 EX FS NA S D EX NA S 2 stall cycles 7-cycle latency for lower FR 8-cycle latency for upper FR FADD DR0,DR2 I D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d FS F2 F1 FS F2 F1 FMOV FMOV FR3,FR5 FR2,FR4 I I FS F2 D FR3 write FS FR2 write EX S NA EX D NA S 3-cycle latency for upper/lower FR FLOAT FPUL,DR0 FMOV.S FR0,@-R15 I I D D Zero-cycle latency 3-cycle increase FLDI1 FIPR FR3 FV0,FV4 I I D D EX NA S d F0 F1 3 stall cycles F2 FS F1 d F2 F1 FS F2 FR1 write FS FR0 write EX MA S 2-cycle latency 1-cycle increase FMOV FTRV @R1,XD14 XMTRX,FV0 I I D D EX MA S d F0 d F1 F0 d F2 F1 F0 d FS F2 F1 F0 3 stall cycles FS F2 F1 FS F2 FS Figure 8.3 Examples of Pipelined Execution (cont) Rev.7.00 Oct. 10, 2008 Page 246 of 1074 REJ09B0366-0700 Section 8 Pipelining (e) Flow dependency (cont) Effectively 1-cycle latency for consecutive LDS/FLOAT instructions LDS FLOAT LDS FLOAT R0,FPUL FPUL,FR0 R1,FPUL FPUL,R1 I D I I EX D D I NA F1 EX D S F2 NA F1 FS S F2 FS FTRC STS FTRC STS FR0,FPUL FPUL,R0 FR1,FPUL FPUL,R1 I D I I F1 D D I F2 EX F1 D FS NA F2 EX S FS NA Effectively 1-cycle latency for consecutive FTRC/STS instructions S (f) Output dependency 11-cycle latency FSQRT FR4 I D F1 F2 FS F3 F1 FMOV FR0,FR4 I D 10 stall cycles = latency (11) - 1 F2 FS F1 FS F2 The registers are written-back in program order. 7-cycle latency for lower FR 8-cycle latency for upper FR I D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d FADD DR0,DR2 FS F2 F1 FS F2 F1 FS F2 EX FR3 write FS FR2 write NA S FMOV FR0,FR3 I D 6 stall cycles = longest latency (8) - 2 (g) Anti-flow dependency FTRV XMTRX,FV0 I D F0 d F1 F0 d F2 F1 F0 d FS F2 F1 F0 FS F2 F1 FMOV @R1,XD0 I D 5 stall cycles FS F2 EX FS MA S FADD DR0,DR2 I D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d NA FS F2 F1 S FS F2 F1 FS F2 FS FMOV FR4,FR1 I D 2 stall cycles EX Figure 8.3 Examples of Pipelined Execution (cont) Rev.7.00 Oct. 10, 2008 Page 247 of 1074 REJ09B0366-0700 Section 8 Pipelining (h) Resource conflict #1 #2 F2 #3 FS F3 F1 F2 FS .................................................. #8 #9 #10 #11 #12 1 cycle/issue FDIV FR6,FR7 I D F1 Latency F1 stage locked for 1 cycle FMAC FR0,FR8,FR9 FMAC FR0,FR10,FR11 FMAC FR0,FR12,FR13 ... I D I F1 D F2 F1 FS F2 FS I D F1 F2 FS : 1 stall cycle (F1 stage resource conflict) FIPR FV8,FV0 FADD FR15,FR4 I D I F0 D F1 1 stall cycle F2 F1 FS F2 FS LDS.L @R15+,PR I D EX D MA SX D FS SX STC GBR,R2 I 3 stall cycles FADD DR0,DR2 I D F1 d F2 F1 d FS F2 F1 d SX D NA SX S NA S FS F2 F1 d FS F2 F1 FS F2 F1 MAC.W @R1+,@R2+ I D 5 stall cycles FS F2 EX f1 D FS MA EX f1 S MA f1 S F2 f1 FS F2 FS MAC.W @R1+,@R2+ I D EX f1 D MA EX f1 S MA f1 S F2 f1 MA EX f1 FS F2 S MA f1 f1 stage can overlap preceding f1, but F1 cannot overlap f1. FS MAC.W @R1+,@R2+ I 1 stall cycle D EX f1 D S F2 f1 FS F2 F1 d FADD DR4,DR6 I 3 stall cycles D 2 stall cycles FS F2 F1 d FS F2 F1 d FS F2 F1 d FS F2 F1 FS F2 F1 FS ... Figure 8.3 Examples of Pipelined Execution (cont) Rev.7.00 Oct. 10, 2008 Page 248 of 1074 REJ09B0366-0700 Section 8 Pipelining Table 8.3 Execution Cycles ExecuInstrucLock tion tion Issue Group Rate Latency Pattern Stage Start Cycles Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,Rn @(disp,PC),R0 @(disp,PC),Rn @(disp,PC),Rn @Rm,Rn @Rm,Rn @Rm,Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn @(disp,Rm),R0 @(disp,Rm),R0 @(disp,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn @(disp,GBR),R0 @(disp,GBR),R0 @(disp,GBR),R0 Rm,@Rn Rm,@Rn Rm,@Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn R0,@(disp,Rn) EX EX EX EX MT EX EX LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS LS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 2 2 2 2 2 1/2 1/2 1/2 2 2 2 2 2 2 2 2 2 1 1 1 1/1 1/1 1/1 1 #1 #1 #1 #1 #1 #1 #1 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #3 #3 #3 #2 #2 #2 #2 #2 #2 #2 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Functional Category No. Data transfer 1 instructions 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Instruction EXTS.B EXTS.W EXTU.B EXTU.W MOV MOV MOVA MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B Rev.7.00 Oct. 10, 2008 Page 249 of 1074 REJ09B0366-0700 Section 8 Pipelining ExecuInstrucLock tion tion Issue Group Rate Latency Pattern Stage Start Cycles R0,@(disp,Rn) Rm,@(disp,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) LS LS LS LS LS LS LS LS LS EX LS LS LS LS EX EX EX EX EX EX EX MT MT MT MT MT MT MT MT MT EX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3–7 1 1–2 1–5 1–5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 #2 #2 #2 #2 #2 #3 #3 #3 #12 #1 #10 #11 #11 #2 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 — — — — — — — — MA — MA MA MA — — — — — — — — — — — — — — — — — — — — — — — — — — 4 — 4 4 4 — — — — — — — — — — — — — — — — — — — — — — — — — — 3–7 — 1–2 1–5 1–5 — — — — — — — — — — — — — — — — — — Functional Category No. Data transfer 32 instructions 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Fixed-point 49 arithmetic 50 instructions 51 52 53 54 55 56 57 58 59 60 61 62 Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVCA.L R0,@Rn MOVT OCBI OCBP OCBWB PREF SWAP.B SWAP.W XTRCT ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/GE CMP/GT CMP/HI CMP/HS CMP/PL CMP/PZ Rn @Rn @Rn @Rn @Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn CMP/STR Rm,Rn DIV0S Rm,Rn Rev.7.00 Oct. 10, 2008 Page 250 of 1074 REJ09B0366-0700 Section 8 Pipelining ExecuInstrucLock tion tion Issue Group Rate Latency Pattern Stage Start Cycles EX Rm,Rn Rm,Rn Rm,Rn Rn @Rm+,@Rn+ @Rm+,@Rn+ Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,R0 EX CO CO EX CO CO CO CO CO EX EX EX EX EX EX EX 1 1 2 2 1 2 2 2 2 2 1 1 1 1 1 1 1 4 1 1 1 4 5 1 1 3 1 1 4 1 1 4/4 4/4 1 2/2/4/4 2/2/4/4 4/4 4/4 4/4 1 1 1 1 1 1 1 4 1 1 1 4 5 1 1 3 1 1 4 #1 #1 #34 #34 #1 #35 #35 #34 #34 #34 #1 #1 #1 #1 #1 #1 #1 #6 #1 #1 #1 #6 #7 #1 #1 #5 #1 #1 #6 — — F1 F1 — F1 F1 F1 F1 F1 — — — — — — — — — — — — — — — — — — — — — 4 4 — 4 4 4 4 4 — — — — — — — — — — — — — — — — — — — — — 2 2 — 2 2 2 2 2 — — — — — — — — — — — — — — — — — — — Functional Category No. Fixed-point 63 arithmetic 64 instructions 65 66 67 68 69 70 71 72 73 74 75 76 77 Logical 78 instructions 79 80 81 82 83 84 85 86 87 88 89 90 91 Instruction DIV0U DIV1 DMULS.L DMULU.L DT MAC.L MAC.W MUL.L MULS.W MULU.W NEG NEGC SUB SUBC SUBV AND AND AND.B NOT OR OR OR.B TAS.B TST TST TST.B XOR XOR XOR.B #imm,@(R0,GBR) CO Rm,Rn Rm,Rn #imm,R0 EX EX EX #imm,@(R0,GBR) CO @Rn Rm,Rn #imm,R0 CO MT MT #imm,@(R0,GBR) CO Rm,Rn #imm,R0 EX EX #imm,@(R0,GBR) CO Rev.7.00 Oct. 10, 2008 Page 251 of 1074 REJ09B0366-0700 Section 8 Pipelining ExecuInstrucLock tion tion Issue Group Rate Latency Pattern Stage Start Cycles Rn Rn Rn Rn Rm,Rn Rn Rn Rm,Rn Rn Rn Rn Rn Rn Rn Rn Rn disp disp disp disp disp Rn disp Rn @Rn @Rn EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX BR BR BR BR BR CO BR CO CO CO CO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 (or 1) 2 (or 1) 2 (or 1) 2 (or 1) 2 3 2 3 3 3 3 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #4 #14 #24 #4 #24 #4 — — — — — — — — — — — — — — — — — — — — — — SX SX — SX — — — — — — — — — — — — — — — — — — — — — — — 3 3 — 3 — — — — — — — — — — — — — — — — — — — — — — — 2 2 — 2 — Functional Category No. Shift 92 instructions 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 Branch 108 instructions 109 110 111 112 113 114 115 116 117 118 Instruction ROTL ROTR ROTCL ROTCR SHAD SHAL SHAR SHLD SHLL SHLL2 SHLL8 SHLL16 SHLR SHLR2 SHLR8 SHLR16 BF BF/S BT BT/S BRA BRAF BSR BSRF JMP JSR RTS Rev.7.00 Oct. 10, 2008 Page 252 of 1074 REJ09B0366-0700 Section 8 Pipelining ExecuInstrucLock tion tion Issue Group Rate Latency Pattern Stage Start Cycles MT CO CO MT CO MT #imm CO CO CO CO Rm,DBR Rm,GBR Rm,Rp_BANK Rm,SR Rm,SSR Rm,SPC Rm,VBR @Rm+,DBR @Rm+,GBR @Rm+,Rp_BANK @Rm+,SR @Rm+,SSR @Rm+,SPC @Rm+,VBR Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR DBR,Rn SGR,Rn CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO 1 1 1 1 1 1 7 5 4 1 1 3 1 4 1 1 1 1 3 1 4 1 1 1 1 1 2 1 1 2 2 3 0 3 1 1 1 1 7 5 4 1 3 3 3 4 3 3 3 1/3 3/3 1/3 4/4 1/3 1/3 1/3 3 3 3 1/3 1/3 2/3 2 3 #1 #28 #1 #1 #1 #1 #13 #8 #9 #2 #14 #15 #14 #16 #14 #14 #14 #17 #18 #17 #19 #17 #17 #17 #28 #28 #24 #29 #29 #25 #20 #21 — F1 — — — — — — — — SX SX SX SX SX SX SX SX SX SX SX SX SX SX F1 F1 SX F1 F1 SX — — — 3 — — — — — — — — 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 — — — 2 — — — — — — — — 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 — — Functional Category No. System 119 control 120 instructions 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Instruction NOP CLRMAC CLRS CLRT SETS SETT TRAPA RTE SLEEP LDTLB LDC LDC LDC LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L STC STC Rev.7.00 Oct. 10, 2008 Page 253 of 1074 REJ09B0366-0700 Section 8 Pipelining ExecuInstrucLock tion tion Issue Group Rate Latency Pattern Stage Start Cycles GBR,Rn Rp_BANK,Rn SR,Rn SSR,Rn SPC,Rn VBR,Rn DBR,@-Rn SGR,@-Rn GBR,@-Rn Rp_BANK,@-Rn SR,@-Rn SSR,@-Rn SPC,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn FRn FRn FRm,FRn @Rm,FRn @Rm+,FRn @(R0,Rm),FRn FRm,@Rn FRm,@-Rn FRm,@(R0,Rn) FRm,FPUL FPUL,FRn CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO LS LS LS LS LS LS LS LS LS LS LS 2 2 2 2 2 2 2 3 2 2 2 2 2 2 1 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2/2 3/3 2/2 2/2 2/2 2/2 2/2 2/2 3 3 2 1/1 1/1 2/2 0 0 0 2 1/2 2 1 1/1 1 0 0 #20 #20 #20 #20 #20 #20 #22 #23 #22 #22 #22 #22 #22 #22 #30 #30 #26 #31 #31 #27 #1 #1 #1 #2 #2 #2 #2 #2 #2 #1 #1 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Functional Category No. System 151 control 152 instructions 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 Single171 precision 172 floating-point instructions 173 174 175 176 177 178 179 180 181 Instruction STC STC STC STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STS STS STS STS.L STS.L STS.L FLDI0 FLDI1 FMOV FMOV.S FMOV.S FMOV.S FMOV.S FMOV.S FMOV.S FLDS FSTS Rev.7.00 Oct. 10, 2008 Page 254 of 1074 REJ09B0366-0700 Section 8 Pipelining ExecuInstrucLock tion tion Issue Group Rate Latency Pattern Stage Start Cycles FRn FRm,FRn LS FE FE FE FE 1 1 1 1 1 0 3/4 2/4 2/4 12/13 #1 #36 #36 #36 #37 — — — — F3 F1 187 188 189 190 191 FLOAT FMAC FMUL FNEG FSQRT FPUL,FRn FR0,FRm,FRn FRm,FRn FRn FRn FE FE FE LS FE 1 1 1 1 1 3/4 3/4 3/4 0 11/12 #36 #36 #36 #1 #37 — — — — F3 F1 192 193 194 195 196 197 198 199 200 Double201 precision 202 floating-point instructions 203 204 205 206 207 FSUB FTRC FMOV FMOV FMOV FMOV FMOV FMOV FMOV FABS FADD FRm,FRn FRm,FPUL DRm,DRn @Rm,DRn @Rm+,DRn @(R0,Rm),DRn DRm,@Rn DRm,@-Rn DRm,@(R0,Rn) DRn DRm,DRn FE FE LS LS LS LS LS LS LS LS FE CO CO FE FE FE 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 3/4 3/4 0 2 1/2 2 1 1/1 1 0 (7, 8)/9 3/5 3/5 4/5 (3, 4)/5 #36 #36 #1 #2 #2 #2 #2 #2 #2 #1 #39 #40 #40 #38 #38 — — — — — — — — — — F1 F1 F1 F1 F1 F3 F1 F1 208 209 FLOAT FMUL FPUL,DRn DRm,DRn FE FE 1 1 (3, 4)/5 (7, 8)/9 #38 #39 F1 F1 — — — — 2 11 — — — — 2 10 — — — — — — — — — — 2 2 2 2 2 2 22 2 2 2 — — — — 10 1 — — — — 9 1 — — — — — — — — — — 6 2 2 2 2 23 3 2 2 6 Functional Category No. Single182 precision 183 floating-point instructions 184 185 186 Instruction FABS FADD FCMP/EQ FRm,FRn FCMP/GT FRm,FRn FDIV FRm,FRn FCMP/EQ DRm,DRn FCMP/GT DRm,DRn FCNVDS FCNVSD FDIV DRm,FPUL FPUL,DRn DRm,DRn (24, 25)/ #41 26 Rev.7.00 Oct. 10, 2008 Page 255 of 1074 REJ09B0366-0700 Section 8 Pipelining ExecuInstrucLock tion tion Issue Group Rate Latency Pattern Stage Start Cycles DRn DRn LS FE 1 1 0 #1 — F3 F1 F1 212 213 FPU system 214 control 215 instructions 216 217 218 219 220 221 Graphics 222 acceleration 223 instructions 224 225 226 227 228 229 230 231 232 233 234 FSUB FTRC LDS LDS LDS.L LDS.L STS STS STS.L STS.L FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FIPR FRCHG FSCHG FTRV XMTRX,FVn DRm,DRn DRm,FPUL Rm,FPUL Rm,FPSCR @Rm+,FPUL @Rm+,FPSCR FPUL,Rn FPSCR,Rn FPUL,@-Rn FPSCR,@-Rn DRm,XDn XDm,DRn XDm,XDn @Rm,XDn @Rm+,XDn @(R0,Rm),XDn XDm,@Rn XDm,@-Rm XDm,@(R0,Rn) FVm,FVn FE FE LS CO CO CO LS CO CO CO LS LS LS LS LS LS LS LS LS FE FE FE FE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (7, 8)/9 4/5 1 4 1/2 1/4 3 3 1/1 1/1 0 0 0 2 1/2 2 1 1/1 1 4/5 1/4 1/4 (5, 5, 6, 7)/8 #39 #38 #1 #32 #2 #33 #1 #1 #2 #2 #1 #1 #1 #2 #2 #2 #2 #2 #2 #42 #36 #36 #43 F1 F1 — F1 — F1 — — — — — — — — — — — — — F1 — — F0 F1 — 2 21 2 2 2 — 3 — 3 — — — — — — — — — — — — — 3 — — 2 3 — 22 3 2 6 2 — 3 — 3 — — — — — — — — — — — — — 1 — — 4 4 Functional Category No. Double210 precision 211 floating-point instructions Instruction FNEG FSQRT (23, 24)/ #41 25 Notes: 1. See table 8.1 for the instruction groups. 2. Latency “L1/L2...”: Latency corresponding to a write to each register, including MACH/MACL/FPSCR. Example: MOV.B @Rm+, Rn “1/2”: The latency for Rm is 1 cycle, and the latency for Rn is 2 cycles. 3. Branch latency: Interval until the branch destination instruction is fetched Rev.7.00 Oct. 10, 2008 Page 256 of 1074 REJ09B0366-0700 Section 8 Pipelining 4. Conditional branch latency “2 (or 1)”: The latency is 2 for a nonzero displacement, and 1 for a zero displacement. 5. Double-precision floating-point instruction latency “(L1, L2)/L3”: L1 is the latency for FR [n+1], L2 that for FR [n], and L3 that for FPSCR. 6. FTRV latency “(L1, L2, L3, L4)/L5”: L1 is the latency for FR [n], L2 that for FR [n+1], L3 that for FR [n+2], L4 that for FR [n+3], and L5 that for FPSCR. 7. Latency “L1/L2/L3/L4” of MAC.L and MAC.W instructions: L1 is the latency for Rm, L2 that for Rn, L3 that for MACH, and L4 that for MACL. 8. Latency “L1/L2” of MUL.L, MULS.W, MULU.W, DMULS.L, and DMULU.L instructions: L1 is the latency for MACH, and L2 that for MACL. 9. Execution pattern: The instruction execution pattern number (see figure 8.2) 10. Lock/stage: Stage locked by the instruction 11. Lock/start: Locking start cycle; 1 is the first D-stage of the instruction. 12. Lock/cycles: Number of cycles locked Exceptions: 1. When a floating-point computation instruction is followed by an FMOV store, an STS FPUL, Rn instruction, or an STS.L FPUL, @-Rn instruction, the latency of the floatingpoint computation is decreased by 1 cycle. 2. When the preceding instruction loads the shift amount of the following SHAD/SHLD, the latency of the load is increased by 1 cycle. 3. When an LS group instruction with a latency of less than 3 cycles is followed by a double-precision floating-point instruction, FIPR, or FTRV, the latency of the first instruction is increased to 3 cycles. Example: In the case of FMOV FR4,FR0 and FIPR FV0,FV4, FIPR is stalled for 2 cycles. 4. When MAC/MUL/DMUL is followed by an STS.L MAC, @-Rn instruction, the latency of MAC/MUL/DMUL is 5 cycles. 5. In the case of consecutive executions of MAC/MUL/DMUL, the latency is decreased to 2 cycles. 6. When an LDS to MAC is followed by an STS.L MAC, @-Rn instruction, the latency of the LDS to MAC is 4 cycles. 7. When an LDS to MAC is followed by MAC/MUL/DMUL, the latency of the LDS to MAC is 1 cycle. 8. When an FSCHG or FRCHG instruction is followed by an LS group instruction that reads or writes to a floating-point register, the aforementioned LS group instruction[s] cannot be executed in parallel. 9. When a single-precision FTRC instruction is followed by an “STS FPUL, Rn” instruction, the latency of the single-precision FTRC instruction is 1 cycle. Rev.7.00 Oct. 10, 2008 Page 257 of 1074 REJ09B0366-0700 Section 8 Pipelining 8.4 Usage Notes The following are additional notes on pipeline operation and the method of calculating the number of clock cycles. The number of states (I clock cycles) required for stages where an external bus access, etc., occurs may include an increased number of cycles, in addition to the number of memory access cycles set by the bus state controller (BSC), etc. For example, the occurrence of the following may result in idle cycles as observed from the external bus. 1. Transfer of data from the logical address bus to the physical address bus 2. Transfer of data between buses using different operation clocks The stages where external memory access occurs include some instruction fetch (I) and some memory access (MA) stages. Rev.7.00 Oct. 10, 2008 Page 258 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes Section 9 Power-Down Modes 9.1 Overview In the power-down modes, some of the on-chip peripheral modules and the CPU functions are halted, enabling power consumption to be reduced. 9.1.1 Types of Power-Down Modes The following power-down modes and functions are provided: • • • • • Sleep mode Deep sleep mode Standby mode Hardware standby mode* Module standby function (TMU, RTC, SCI/SCIF, DMAC, SQ*, and UBC*) Note: * SH7750S, SH7750R only Table 9.1 shows the conditions for entering these modes from the program execution state, the status of the CPU and peripheral modules in each mode, and the method of exiting each mode. Rev.7.00 Oct. 10, 2008 Page 259 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes Status PowerDown Mode Sleep Entering Conditions SLEEP instruction executed while STBY bit is 0 in STBCR SLEEP instruction executed while STBY bit is 0 in STBCR, and DSLP bit is 1 in STBCR2 SLEEP instruction executed while STBY bit is 1 in STBCR CPG CPU On-Chip Memory Held On-chip Peripheral Pins Modules Operating Held External Memory Exiting Method Operating Halted (registers held) Refreshing • Interrupt • Reset Deep sleep Operating Halted (registers held) Held Operating (DMA halted) Held Selfrefreshing • Interrupt • Reset Standby Halted Halted (registers held) Held Halted* Held Selfrefreshing • Interrupt • Reset Hardware Setting CA pin low standby (SH7750S, SH7750R) Module standby Setting MSTP bit to 1 in STBCR/ STBCR2 Halted Halted Undefined Halted* High Undefined impedance • Power-on reset Operating Operating Held Specified modules halted* Held Refreshing • Clearing MSTP bit to 0 • Reset Note: * The RTC operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock (RTC)). Rev.7.00 Oct. 10, 2008 Page 260 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.1.2 Register Configuration Table 9.2 shows the registers used for power-down mode control. Table 9.2 Name Standby control register Standby control register 2 Clock stop register 00* Clock release register 00* Note: * Power-Down Mode Registers Abbreviation STBCR STBCR2 CLKSTP00 CLKSTPCLR00 R/W R/W R/W R/W W Initial Value H'00 H'00 H'00000000 H'00000000 P4 Address H'FFC00004 H'FFC00010 H'FE0A0000 H'FE0A0008 Area 7 Address H'1FC00004 H'1FC00010 H'1E0A0000 H'1E0A0008 Access Size 8 8 32 32 SH7750R only 9.1.3 Pin Configuration Table 9.3 shows the pins used for power-down mode control. Table 9.3 Pin Name Processor status 1 Processor status 0 Power-Down Mode Pins Abbreviation STATUS1 STATUS0 I/O Output Function Indicate the processor's operating status. (STATUS1, STATUS0) HH: Reset HL: Sleep mode LH: Standby mode LL: Normal operation Hardware standby request (SH7750S and SH7750R only) Legend: H: High level L: Low level CA Input Transits to hardware standby mode by a low-level input to the pin. Rev.7.00 Oct. 10, 2008 Page 261 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.2 9.2.1 Register Descriptions Standby Control Register (STBCR) The standby control register (STBCR) is an 8-bit readable/writable register that specifies the power-down mode status. It is initialized to H'00 by a power-on reset via the RESET pin or due to watchdog timer overflow. Bit: 7 STBY Initial value: R/W: 0 R/W 6 PHZ 0 R/W 5 PPU 0 R/W 4 MSTP4 0 R/W 3 MSTP3 0 R/W 2 MSTP2 0 R/W 1 MSTP1 0 R/W 0 MSTP0 0 R/W Bit 7—Standby (STBY): Specifies a transition to standby mode. Bit 7: STBY 0 1 Description Transition to sleep mode on execution of SLEEP instruction Transition to standby mode on execution of SLEEP instruction (Initial value) Bit 6—Peripheral Module Pin High Impedance Control (PHZ): Controls the state of peripheral module related pins in standby mode. When the PHZ bit is set to 1, peripheral module related pins go to the high-impedance state in standby mode. For the relevant pins, see section 9.2.2, Peripheral Module Pin High Impedance Control. Bit 6: PHZ 0 1 Description Peripheral module related pins are in normal state Peripheral module related pins go to high-impedance state (Initial value) Bit 5—Peripheral Module Pin Pull-Up Control (PPU): Controls the state of peripheral module related pins. When the PPU bit is cleared to 0, the pull-up resistor is turned on for peripheral module related pins in the input or high-impedance state. For the relevant pins, see section 9.2.3, Peripheral Module Pin Pull-Up Control. Bit 5: PPU 0 1 Description Peripheral module related pin pull-up resistors are on Peripheral module related pin pull-up resistors are off (Initial value) Rev.7.00 Oct. 10, 2008 Page 262 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes Bit 4—Module Stop 4 (MSTP4): Specifies stopping of the clock supply to the DMAC among the on-chip peripheral modules. The clock supply to the DMAC is stopped when the MSTP4 bit is set to 1. When DMA transfer is used, stop the transfer before setting the MSTP4 bit to 1. When DMA transfer is performed after clearing the MSTP4 bit to 0, DMAC settings must be made again. Bit 4: MSTP4 0 1 Description DMAC operates DMAC clock supply is stopped (Initial value) Bit 3—Module Stop 3 (MSTP3): Specifies stopping of the clock supply to serial communication interface channel 2 (SCIF) among the on-chip peripheral modules. The clock supply to the SCIF is stopped when the MSTP3 bit is set to 1. Bit 3: MSTP3 0 1 Description SCIF operates SCIF clock supply is stopped (Initial value) Bit 2—Module Stop 2 (MSTP2): Specifies stopping of the clock supply to the timer unit (TMU) among the on-chip peripheral modules. The clock supply to the TMU is stopped when the MSTP2 bit is set to 1. Bit 2: MSTP2 0 1 Description TMU operates TMU clock supply is stopped (Initial value) Bit 1—Module Stop 1 (MSTP1): Specifies stopping of the clock supply to the realtime clock (RTC) among the on-chip peripheral modules. The clock supply to the RTC is stopped when the MSTP1 bit is set to 1. When the clock supply is stopped, RTC registers cannot be accessed but the counters continue to operate. Bit 1: MSTP1 0 1 Description RTC operates RTC clock supply is stopped (Initial value) Rev.7.00 Oct. 10, 2008 Page 263 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes Bit 0—Module Stop 0 (MSTP0): Specifies stopping of the clock supply to serial communication interface channel 1 (SCI) among the on-chip peripheral modules. The clock supply to the SCI is stopped when the MSTP0 bit is set to 1. Bit 0: MSTP0 0 1 Description SCI operates SCI clock supply is stopped (Initial value) 9.2.2 Peripheral Module Pin High Impedance Control When bit 6 in the standby control register (STBCR) is set to 1, peripheral module related pins go to the high-impedance state in standby mode. • Relevant Pins SCI related pins MD0/SCK MD7/TXD CTS2 DMA related pins DACK0 DACK1 DRAK0 DRAK1 MD1/TXD2 MD8/RTS2 • Other Information The setting in this register is invalid when the above pins are used as port output pins. For details of pin states, see Appendix E, Pin Functions. Rev.7.00 Oct. 10, 2008 Page 264 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.2.3 Peripheral Module Pin Pull-Up Control When bit 5 in the standby control register (STBCR) is cleared to 0, peripheral module related pins are pulled up when in the input or high-impedance state. • Relevant Pins SCI related pins MD0/SCK MD7/TXD RXD DMA related pins DREQ0 DREQ1 TMU related pin TCLK MD1/TXD2 MD8/RTS2 CTS2 DACK0 DACK1 DRAK0 DRAK1 MD2/RXD2 SCK2/MRESET • Other Information The setting in this register is invalid in the hardware standby mode. For details of pin states, see Appendix E, Pin Functions. 9.2.4 Standby Control Register 2 (STBCR2) Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via the RESET pin or due to watchdog timer overflow. Bit: 7 DSLP Initial value: R/W: Note: * 0 R/W 6 STHZ 0 R/W 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 0 MSTP6* MSTP5* 0 R/W 0 R/W Reserved bit in the SH7750. Rev.7.00 Oct. 10, 2008 Page 265 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes Bit 7—Deep Sleep (DSLP): Specifies a transition to deep sleep mode Bit 7: DSLP 0 1 Note: * Description Transition to sleep mode or standby mode on execution of SLEEP instruction, according to setting of STBY bit in STBCR register (Initial value) Transition to deep sleep mode on execution of SLEEP instruction* When the STBY bit in the STBCR register is 0 Bit 6—STATUS Pin High-Impedance Control (STHZ): This bit selects whether the STATUS0 and STATUS1 pins are set to high-impedance when in hardware standby mode. Bit 6: STHZ 0 1 Description Sets STATUS0, 1 pins to high-impedance when in hardware standby mode (Initial value) Drives STATUS0, 1 pins to LH when in hardware standby mode Bits 5 to 2—Reserved: Only 0 should only be written to these bits; operation cannot be guaranteed if 1 is written. These bits are always read as 0. Bits 1 and 0 (SH7750)—Reserved: Only 0 should only be written to these bits; operation cannot be guaranteed if 1 is written. These bits are always read as 0. Bit 1 (SH7750S and SH7750R)—Module Stop 6 (MSTP6): Specifies that the clock supply to the store queue (SQ) in the cache controller (CCN) is stopped. Setting the MSTP6 bit to 1 stops the clock supply to the SQ, and the SQ functions are therefore unavailable. Bit 1: MSTP6 0 1 Description SQ operating Clock supply to SQ stopped (Initial value) Bit 0 (SH7750S and SH7750R)—Module Stop 5 (MSTP5): Specifies stopping of the clock supply to the user break controller (UBC) among the on-chip peripheral modules. See section 20.6, User Break Controller Stop Function, for how to set the clock supply. Bit 0: MSTP5 0 1 Description UBC operating Clock supply to UBC stopped (Initial value) Rev.7.00 Oct. 10, 2008 Page 266 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.2.5 Clock-Stop Register 00 (CLKSTP00) (SH7750R Only) Clock-stop register 00 (CLKSTP00) controls the operation clock for peripheral modules. To resume supply of the clock signal, write a 1 to the corresponding bit in the CLKSTPCLR00 register. Writing a 0 to the CLKSTP00 register does not affect the register's value. The CLKSTP00 register is a 32-bit register that can be read from or written to. It is initialized to H'0000 0000 by a power-on reset, but not by a manual reset or when the device enters standby mode. Bit: 31 — Initial value: R/W: 0 R 30 — 0 R 29 — 0 R 28 — 0 R 27 — 0 R 26 — 0 R 25 — 0 R 24 — 0 R 23 — 0 R 22 — 0 R 21 — 0 R 20 — 0 R 19 — 0 R 18 — 0 R 17 — 0 R 16 — 0 R Bit: 15 — 14 — 0 R 13 — 0 R 12 — 0 R 11 — 0 R 10 — 0 R 9 — 0 R 8 — 0 R 7 — 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 0 CSTP1 CSTP0 Initial value: R/W: 0 R 0 0 R/W R/W Bits 31 to 2—Reserved: Any data written to these bits should always be 0. These bits are always read as 0. Bit 1—Clock stop 1 (CSTP1): This bit specifies stopping of the peripheral clock supply to channels 3 and 4 of the timer unit (TMU). Bit 1: CSTP1 0 1 Description Peripheral clock is supplied to TMU channels 3 and 4 Peripheral clock supply to TMU channels 3 and 4 is stopped (Initial value) Bit 0⎯Clock Stop 0 (CSTP0): Specifies stopping of the peripheral clock supply to the interrupt controller (INTC). If this bit is set, INTC does not detect interrupts on the TMU's channels 3 and 4. Bit 0: CSTP0 0 1 Description INTC detects interrupts on channels 3 and 4 of the TMU (Initial value) INTC does not detect interrupts on channels 3 and 4 of the TMU Rev.7.00 Oct. 10, 2008 Page 267 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.2.6 Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only) The clock-stop clear register 00 (CLKSTPCLR00) is a 32-bit write-only register that clears the corresponding bits of the CLKSTP00 register. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Bits 31 to 0⎯Clock-Stop Clear: Specify whether or not to clear the corresponding bit of the clock-stop setting. See section 9.2.5, Clock-Stop Register 00 (CLKSTP00) (SH7750R only), for the correspondence between the bits and the clocks that are stopped. Bits 31 to 0 0 1 Description Does not change the clock-stop setting for the corresponding clock Clears the clock-stop setting for the corresponding clock 9.3 9.3.1 Sleep Mode Transition to Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches from the program execution state to sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained. The on-chip peripheral modules continue to operate, and the clock continues to be output from the CKIO pin. In sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the STATUS0 pin. Rev.7.00 Oct. 10, 2008 Page 268 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.3.2 Exit from Sleep Mode Sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset. In sleep mode, interrupts are accepted even if the BL bit in the SR register is 1. If necessary, SPC and SSR should be saved to the stack before executing the SLEEP instruction. Exit by Interrupt: When an NMI, IRL, or on-chip peripheral module interrupt is generated, sleep mode is exited and interrupt exception handling is executed. The code corresponding to the interrupt source is set in the INTEVT register. Exit by Reset: Sleep mode is exited by means of a power-on or manual reset via the RESET pin, or a power-on or manual reset executed when the watchdog timer overflows. 9.4 9.4.1 Deep Sleep Mode Transition to Deep Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0 and the DSLP bit in STBCR2 is set to 1, the chip switches from the program execution state to deep sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained. Except for the DMAC*, on-chip peripheral modules continue to operate. The clock continues to be output to the CKIO pin, but all bus access (including auto refresh) stops. When using memory that requires refreshing, set the self-refresh function prior to making the transition to deep sleep mode. In deep sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the STATUS0 pin. Note: * Terminate DMA transfers prior to making the transition to deep sleep mode. If you make a transition to deep sleep mode while DMA transfers are in progress, the results of those transfers cannot be guaranteed. 9.4.2 Exit from Deep Sleep Mode As with sleep mode, deep sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset. Rev.7.00 Oct. 10, 2008 Page 269 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.5 9.5.1 Standby Mode Transition to Standby Mode If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches from the program execution state to standby mode. In standby mode, the on-chip peripheral modules halt as well as the CPU. Clock output from the CKIO pin is also stopped. The CPU and cache register contents are retained. Some on-chip peripheral module registers are initialized. The state of the peripheral module registers in standby mode is shown in table 9.4. Table 9.4 Module Interrupt controller User break controller Bus state controller On-chip oscillation circuits Timer unit Realtime clock Direct memory access controller Serial communication interface State of Registers in Standby Mode Initialized Registers — — — — TSTR register* — — Registers That Retain Their Contents All registers All registers All registers All registers All registers except TSTR All registers All registers See Appendix A, Address List See Appendix A, Address List Notes: DMA transfer should be terminated before making a transition to standby mode. Transfer results are not guaranteed if standby mode is entered during transfer. * Not initialized when the realtime clock (RTC) is in use (see section 12, Timer Unit (TMU)). The procedure for a transition to standby mode is shown below. 1. Clear the TME bit in the WDT timer control register (WTCSR) to 0, and stop the WDT. Set the initial value for the up-count in the WDT timer counter (WTCNT), and set the clock to be used for the up-count in bits CKS2–CKS0 in the WTCSR register. 2. Set the STBY bit in the STBCR register to 1, then execute a SLEEP instruction. 3. When standby mode is entered and the chip's internal clock stops, a low-level signal is output at the STATUS1 pin, and a high-level signal at the STATUS0 pin. Rev.7.00 Oct. 10, 2008 Page 270 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.5.2 Exit from Standby Mode Standby mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset via the RESET pin. Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI, IRL*1, RTC, or GPIO*2 interrupt is detected, the WDT starts counting. After the count overflows, clocks are supplied to the entire chip, standby mode is exited, and the STATUS1 and STATUS0 pins both go low. Interrupt exception handling is then executed, and the code corresponding to the interrupt source is set in the INTEVT register. In standby mode, interrupts are accepted even if the BL bit in the SR register is 1, and so, if necessary, SPC and SSR should be saved to the stack before executing the SLEEP instruction. The phase of the CKIO pin clock output may be unstable immediately after an interrupt is detected, until standby mode is exited. Notes: 1. Only when the RTC clock (32.768 kHz) is operating (see section 19.2.2, IRL Interrupts), standby mode can be exited by means of IRL3–IRL0 (when the IRL3– IRL0 level is higher than the SR register IMASK mask level). 2. GPIO can be used to cancel standby mode when the RTC clock (32.768 kHz) is operating (when the GPIO level is higher than the SR register IMASK mask level). Exit by Reset: Standby mode is exited by means of a reset (power-on or manual) via the RESET pin. The RESET pin should be held low until clock oscillation stabilizes. The internal clock continues to be output at the CKIO pin. 9.5.3 Clock Pause Function In standby mode, it is possible to stop or change the frequency of the clock input from the EXTAL pin. This function is used as follows. 1. Enter standby mode following the transition procedure described above. 2. When standby mode is entered and the chip's internal clock stops, a low-level signal is output at the STATUS1 pin, and a high-level signal at the STATUS0 pin. 3. The input clock is stopped, or its frequency changed, after the STATUS1 pin goes low and the STATUS0 pin high. 4. When the frequency is changed, input an NMI or IRL interrupt after the change. When the clock is stopped, input an NMI or IRL interrupt after applying the clock. 5. After the time set in the WDT, clock supply begins inside the chip, the STATUS1 and STATUS0 pins both go low, and operation is resumed from interrupt exception handling. Rev.7.00 Oct. 10, 2008 Page 271 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.6 9.6.1 Module Standby Function Transition to Module Standby Function Setting the MSTP6–MSTP0, CSTP1, and CSTP0 bits in the standby control register to 1 enables the clock supply to the corresponding on-chip peripheral modules to be halted. Use of this function allows power consumption in sleep mode to be further reduced. In the module standby state, the on-chip peripheral module external pins retain their states prior to halting of the modules, and most registers retain their states prior to halting of the modules. Rev.7.00 Oct. 10, 2008 Page 272 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes Bit CSTP1* CSTP0* 6 Description 0 1 6 Peripheral clock is supplied to TMU channels 3 and 4 Peripheral clock supplied to TMU channels 3 and 4 is stopped INTC detects interrupts on TMU channels 3 and 4 INTC does not detect interrupts on TMU channels 3 and 4 SQ operates Clock supplied to SQ is stopped UBC operates Clock supplied to UBC is stopped*5 DMAC operates Clock supplied to DMAC is stopped*3 SCIF operates Clock supplied to SCIF is stopped TMU operates Clock supplied to TMU is stopped, and register is initialized*1 RTC operates Clock supplied to RTC is stopped*2 SCI operates Clock supplied to SCI is stopped 0 1 MSTP6* 4 0 1 MSTP5*4 0 1 MSTP4 0 1 MSTP3 0 1 MSTP2 0 1 MSTP1 0 1 MSTP0 0 1 Notes: 1. The register initialized is the same as in standby mode, but initialization is not performed if the RTC clock is not in use (see section 12, Timer Unit (TMU)). 2. The counter operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock (RTC)). 3. Terminate DMA transfers prior to making the transition to module standby mode. If you make a transition to module standby mode while DMA transfers are in progress, the results of those transfers cannot be guaranteed. 4. SH7750S, SH7750R only 5. For details, see section 20.6, User Break Controller Stop Function. 6. SH7750R only 9.6.2 Exit from Module Standby Function The module standby function is exited by clearing the MSTP6–MSTP0, CSTP1, and CSTP0 bits to 0, or by a power-on reset via the RESET pin or a power-on reset caused by watchdog timer overflow. Rev.7.00 Oct. 10, 2008 Page 273 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.7 9.7.1 Hardware Standby Mode (SH7750S, SH7750R Only) Transition to Hardware Standby Mode Setting the CA pin level low effects a transition to hardware standby mode. In this mode, all modules other than the RTC stop, as in the standby mode selected using the SLEEP command. Hardware standby mode differs from standby mode as follows: 1. Interrupts and manual resets are not available; 2. All output pins other than the STATUS pin are in the high-impedance state and the pull-up resistance is off. 3. On the SH7750S, the RTC continues to operate even when no power is supplied to power pins other than the RTC power supply pin. The status of the STATUS pin is determined by the STHZ bit of STBCR2. See appendix E, Pin Functions, for details of output pin states. Operation when a low-level is input to the CA pin when in the standby mode depends on the CPG status, as follows: 1. In standby mode The clock remains stopped and a transition is made to the hardware standby state. 2. When WDT is operating when standby mode is exited by interrupt Standby mode is momentarily exited, the CPU restarts, and then a transition is made to hardware standby mode. Note that the level of the CA pin must be kept low while in hardware standby mode. 9.7.2 Exit from Hardware Standby Mode Hardware standby mode can only be exited by effecting a power-on reset. Setting the CA pin level high after the RESET pin level has been set low and the SCK2 pin high starts the clock to oscillate. The RESET pin level should be kept low until the clock has stabilized, then set high so that the CPU starts the power-on reset exiting procedure. Note that hardware standby mode cannot be exited using interrupts or a manual reset. Rev.7.00 Oct. 10, 2008 Page 274 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.7.3 Usage Notes 1. The CA pin level must be kept high when the RTC power supply is started (figure 9.15). 2. On the SH7750R, power must be supplied to the other power supply pins (VDD, VDDQ, VDD−CPG, VDD−PLL1, and VDD−PLL2), in addition to the RTC power supply pin, in hardware standby mode. 9.8 STATUS Pin Change Timing The STATUS1 and STATUS0 pin change timing is shown below. The meaning of the STATUS pin settings is as follows: Reset: Sleep: Standby: Normal: HH (STATUS1 high, STATUS0 high) HL (STATUS1 high, STATUS0 low) LH (STATUS1 low, STATUS0 high) LL (STATUS1 low, STATUS0 low) The meaning of the clock units is as follows: Bcyc: Bus clock cycle Pcyc: Peripheral clock cycle Rev.7.00 Oct. 10, 2008 Page 275 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.8.1 In Reset Power-On Reset CKIO PLL stabilization time RESET SCK2 STATUS Normal Reset 0–30 Bcyc 0–5 Bcyc Normal Figure 9.1 STATUS Output in Power-On Reset Manual Reset CKIO Must be asserted for tRESW or longer RESET* SCK2 STATUS Normal Reset 0–30 Bcyc ≥ 0 Bcyc Normal Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting until the end of the currently executing bus cycle. Figure 9.2 STATUS Output in Manual Reset Rev.7.00 Oct. 10, 2008 Page 276 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.8.2 In Exit from Standby Mode Standby → Interrupt Oscillation stops Interrupt request WDT overflow CKIO WDT count STATUS Normal Standby Normal Figure 9.3 STATUS Output in Standby → Interrupt Sequence Standby → Power-On Reset Oscillation stops Reset CKIO RESET*1 SCK2 STATUS Normal Standby *2 Reset Normal 0–10 Bcyc 0–30 Bcyc Notes: 1. When standby mode is exited by means of a power-on reset, a WDT count is not performed. Hold RESET low for the PLL oscillation stabilization time. 2. Undefined Figure 9.4 STATUS Output in Standby → Power-On Reset Sequence Rev.7.00 Oct. 10, 2008 Page 277 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes Standby → Manual Reset Oscillation stops Reset CKIO RESET*1 SCK2 STATUS Normal Standby *2 Reset Normal 0–10 Bcyc 0–30 Bcyc Notes: 1. When standby mode is exited by means of a manual reset, a WDT count is not performed. Hold RESET low for the PLL oscillation stabilization time. 2. Undefined Figure 9.5 STATUS Output in Standby → Manual Reset Sequence Rev.7.00 Oct. 10, 2008 Page 278 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.8.3 In Exit from Sleep Mode Sleep → Interrupt Interrupt request CKIO STATUS Normal Sleep Normal Figure 9.6 STATUS Output in Sleep → Interrupt Sequence Sleep → Power-On Reset Reset CKIO RESET*1 SCK2 STATUS Normal Sleep *2 Reset Normal 0–10 Bcyc 0–30 Bcyc Notes: 1. When sleep mode is exited by means of a power-on reset, hold RESET low for the oscillation stabilization time. 2. Undefined Figure 9.7 STATUS Output in Sleep → Power-On Reset Sequence Rev.7.00 Oct. 10, 2008 Page 279 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes Sleep → Manual Reset Reset CKIO RESET* SCK2 STATUS Normal Sleep Reset Normal 0–30 Bcyc Note: * Hold RESET low until STATUS = reset. 0–30 Bcyc Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence Rev.7.00 Oct. 10, 2008 Page 280 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.8.4 In Exit from Deep Sleep Mode Deep Sleep → Interrupt Interrupt request CKIO STATUS Normal Sleep Normal Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence Deep Sleep → Power-On Reset Reset CKIO RESET*1 SCK2 STATUS Normal Sleep *2 Reset Normal 0–10 Bcyc 0–30 Bcyc Notes: 1. When deep sleep mode is exited by means of a power-on reset, hold RESET low for the oscillation stabilization time. 2. Undefined Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence Rev.7.00 Oct. 10, 2008 Page 281 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes Deep Sleep → Manual Reset Reset CKIO RESET* SCK2 STATUS Normal Sleep Reset Normal 0–30 Bcyc Note: * Hold RESET low until STATUS = reset. 0–30 Bcyc Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence Rev.7.00 Oct. 10, 2008 Page 282 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only) Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode. The CA pin level must be kept low while in hardware standby mode. After setting the RESET pin level low, the clock starts when the CA pin level is switched to high. CKIO CA RESET SCK2 (High) STATUS Normal*1 Standby*3 *2 Reset 0–10 Bcyc Waiting for end of bus cycle 0–10 Bcyc Notes: 1. Same at sleep and reset. 2. Undefined 3. High impedance when STBCR2. STHZ = 0 Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation) Rev.7.00 Oct. 10, 2008 Page 283 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes Interrupt request WDT overflow CKIO CA RESET (High) SCK2 (High) STATUS Standby Normal 0–10 Bcyc Standby* WDT count Note: * High impedance when STBCR2. STHZ = 0 Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation) Rev.7.00 Oct. 10, 2008 Page 284 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes VDDQ* VDD VDD min CA RESET SCK2 Min 0s Min 0s Max 50 μs Note: * VDDQ, VDD-CPG, VDD-PLL1, VDD-PLL2 Figure 9.14 Timing When Power Other than VDD-RTC Is Off VDD-RTC Power-on oscillation setting time CA VDD, VDDQ* Min 0s RESET SCK2 Note: * VDD, VDD-PLL1/2, VDDQ, VDD-CPG Figure 9.15 Timing When VDD-RTC Power Is Off → On Rev.7.00 Oct. 10, 2008 Page 285 of 1074 REJ09B0366-0700 Section 9 Power-Down Modes 9.9 9.9.1 Usage Notes Note on Current Consumption After a power-on reset, the current consumption may exceed the maximum value for sleep mode or standby mode during the period until one or more of the arithmetic operation or floating-point operation instructions listed below is executed. 1. Arithmetic operation instructions MAC.W, MAC.L 2. Floating-point operation instructions ⎯ When FPSCR.PR = 0 FADD, FSUB, FMUL, FMAC, FLOAT, FTRC, FDIV, FSQRT, FIPR, FTRV ⎯ When FPSCR.PR = 1 FADD, FSUB, FMUL, FLOAT, FTRC, FDIV, FSQRT, FCNVSD, FCNVDS Workaround: After a power-on reset, execute one or more of the above instructions before transitioning to sleep mode or standby mode. Example: To reduce the effect on FPSCR, arrange the following two instructions starting at H'A0000000. Address H'A0000000 H'A0000002 : Instruction String FLDI1 FR0 FADD FR0, FR0 ; FLDI1 FR0 loads 1 into FR0, : ; so the cause and flag bits of FPSCR are not set to 1. Rev.7.00 Oct. 10, 2008 Page 286 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits Section 10 Clock Oscillation Circuits 10.1 Overview The on-chip oscillation circuits comprise a clock pulse generator (CPG) and a watchdog timer (WDT). The CPG generates the clocks supplied inside the processor and performs power-down mode control. The WDT is a single-channel timer used to count the clock stabilization time when exiting standby mode or the frequency is changed. It can be used as a normal watchdog timer or an interval timer. 10.1.1 Features The CPG has the following features: • Three clocks The CPG can generate the CPU clock (Ick) used by the CPU, FPU, caches, and TLB, the peripheral module clock (Pck) used by the peripheral modules, and the bus clock (Bck) used by the external bus interface. • Six clock modes Any of six clock operating modes can be selected, with different combinations of CPU clock, bus clock, and peripheral module clock division ratios after a power-on reset. • Frequency change function PLL (phase-locked loop) circuits and a frequency divider in the CPG enable the CPU clock, bus clock, and peripheral module clock frequencies to be changed independently. Frequency changes are performed by software in accordance with the settings in the frequency control register (FRQCR). • PLL on/off control Power consumption can be reduced by stopping the PLL circuits during low-frequency operation. • Power-down mode control It is possible to stop the clock in sleep mode and standby mode, and to stop specific modules with the module standby function. Rev.7.00 Oct. 10, 2008 Page 287 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits The WDT has the following features • Can be used to secure clock stabilization time Used when exiting standby mode or a temporary standby state when the clock frequency is changed. • Can be switched between watchdog timer mode and interval timer mode • Internal reset generation in watchdog timer mode An internal reset is executed on counter overflow. Power-on reset or manual reset can be selected. • Interrupt generation in interval timer mode An interval timer interrupt is generated on counter overflow. • Selection of eight counter input clocks Any of eight clocks can be selected, scaled from the ×1 clock of frequency divider 2 shown in figure 10.1. The CPG is described in sections 10.2 to 10.6, and the WDT in sections 10.7 to 10.9. Rev.7.00 Oct. 10, 2008 Page 288 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits 10.2 10.2.1 Overview of CPG Block Diagram of CPG Figure 10.1 (1) shows a block diagram of the CPG in the SH7750 and SH7750S, and figure 10.1 (2) a block diagram of the CPG in the SH7750R. Oscillator circuit Frequency divider 2 ×1 ×1/2 ×1/3 ×1/4 ×1/6 ×1/8 PLL circuit 1 ×6 CPU clock (Ick) cycle Icyc XTAL EXTAL MD8 Crystal oscillation circuit Frequency divider 1 ×1/2 Peripheral module clock (Pck) cycle Pcyc Bus clock (Bck) cycle Bcyc PLL circuit 2 CKIO ×1 CPG control unit MD2 MD1 MD0 Clock frequency control circuit Standby control circuit FRQCR STBCR STBCR2 Bus interface Legend: FRQCR: Frequency control register STBCR: Standby control register STBCR2: Standby control register 2 Internal bus Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S) Rev.7.00 Oct. 10, 2008 Page 289 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits Oscillator circuit Frequency divider 2 PLL circuit 1 ×6 ×12 ×1 ×1/2 ×1/3 ×1/4 ×1/6 ×1/8 CPU clock (Ick) cycle Icyc XTAL EXTAL MD8 Crystal oscillation circuit Peripheral module clock (Pck) cycle Pcyc Bus clock (Bck) cycle Bcyc PLL circuit 2 ×1 CKIO CPG control unit MD2 MD1 MD0 Clock frequency control circuit Standby control circuit FRQCR STBCR STBCR2 Bus interface Internal bus Legend: FRQCR: Frequency control register STBCR: Standby control register STBCR2: Standby control register 2 Figure 10.1 (2) Block Diagram of CPG (SH7750R) Rev.7.00 Oct. 10, 2008 Page 290 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits The function of each of the CPG blocks is described below. PLL Circuit 1: PLL circuit 1 has a function for multiplying the clock frequency from the EXTAL pin or crystal oscillation circuit by 6 with the SH7750 and SH7750S, and by 6 or 12 with the SH7750R. Starting and stopping is controlled by a frequency control register setting. Control is performed so that the internal clock rising edge phase matches the input clock rising edge phase. PLL Circuit 2: PLL circuit 2 coordinates the phases of the bus clock and the CKIO pin output clock. Starting and stopping is controlled by a frequency control register setting. Crystal Oscillation Circuit: This is the oscillator circuit used when a crystal resonator is connected to the XTAL and EXTAL pins. Use of the crystal oscillation circuit can be selected with the MD8 pin. Frequency Divider 1 (SH7750 and SH7750S only): Frequency divider 1 has a function for adjusting the clock waveform duty to 50% by halving the input clock frequency when clock input from the EXTAL pin is supplied internally without using PLL circuit 1. Frequency Divider 2: Frequency divider 2 generates the CPU clock (Ick), bus clock (Bck), and peripheral module clock (Pck). The division ratio is set in the frequency control register. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency by means of the MD pins and frequency control register. Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillation circuits and other modules when the clock is switched and in sleep and standby modes. Frequency Control Register (FRQCR): The frequency control register contains control bits for clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU clock, bus clock, and peripheral module clock frequency division ratios. Standby Control Register (STBCR): The standby control register contains power save mode control bits. For further information on the standby control register, see section 9, Power-Down Modes. Standby Control Register 2 (STBCR2): Standby control register 2 contains a power save mode control bit. For further information on standby control register 2, see section 9, Power-Down Modes. Rev.7.00 Oct. 10, 2008 Page 291 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits 10.2.2 CPG Pin Configuration Table 10.1 shows the CPG pins and their functions. Table 10.1 CPG Pins Pin Name Mode control pins Abbreviation MD0 MD1 MD2 Crystal I/O pins (clock input pins) XTAL EXTAL MD8 Output Input Input Connects crystal resonator Connects crystal resonator, or used as external clock input pin Selects use/non-use of crystal resonator When MD8 = 0, external clock is input from EXTAL When MD8 = 1, crystal resonator is connected directly to EXTAL and XTAL Clock output pin CKIO enable pin Note: * CKIO CKE Output Output Used as external clock output pin Level can also be fixed 0 when CKIO output clock is unstable and in case of synchronous DRAM self-refreshing* I/O Input Function Set clock operating mode Set to 1 in a power-on reset. For details of synchronous DRAM self-refreshing, see section 13.3.5, Synchronous DRAM Interface. 10.2.3 CPG Register Configuration Table 10.2 shows the CPG register configuration. Table 10.2 CPG Register Name Frequency control register Note: * Abbreviation FRQCR R/W R/W Initial Value Undefined* P4 Address H'FFC00000 Area 7 Address H'1FC00000 Access Size 16 Depends on the clock operating mode set by pins MD2–MD0. Rev.7.00 Oct. 10, 2008 Page 292 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits 10.3 Clock Operating Modes Tables 10.3 (1) and 10.3 (2) show the clock operating modes corresponding to various combinations of mode control pin (MD2–MD0) settings (initial settings such as the frequency division ratio). Table 10.4 shows FRQCR settings and internal clock frequencies. Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S) External Pin Combination Clock Operating Mode 0 1 2 3 4 5 1 0 1 1/2 Frequency Divider Off Off On Off On Off CPU Clock 6 6 3 6 3 6 Frequency (vs. Input Clock) Bus Clock 3/2 1 1 2 3/2 3 Peripheral Module Clock 3/2 1 1/2 1 3/4 3/2 FRQCR Initial Value H'0E1A H'0E23 H'0E13 H'0E13 H'0E0A H'0E0A MD2 0 MD1 0 MD0 0 1 0 1 0 1 PLL1 On On On On On On PLL2 On On On On On On Notes: 1. Turning on/off of the ½ frequency divider is solely determined by the clock operating mode. 2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input frequency (fEX) and CKIO clock output (fOP) in section 22.3.1, Clock and Control Signal Timing. Table 10.3 (2) Clock Operating Modes (SH7750R) External Pin Combination MD2 0 MD1 0 MD0 0 1 1 0 1 1 0 0 1 1 0 PLL1 On (×12) On (×12) On (×6) On (×12) On (×6) On (×12) Off (×6) PLL2 On On On On On On Off CPU Clock 12 12 6 12 6 12 1 Frequency (vs. Input Clock) Bus Clock 3 3/2 2 4 3 6 1/2 Peripheral Module Clock 3 3/2 1 2 3/2 3 1/2 FRQCR Initial Value H'0E1A H'0E2C H'0E13 H'0E13 H'0E0A H'0E0A H'0808 Clock Operating Mode 0 1 2 3 4 5 6 Rev.7.00 Oct. 10, 2008 Page 293 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode. 2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input frequency (fEX) and CKIO clock output (fOP) in section 22.3.1, Clock and Control Signal Timing. Table 10.4 FRQCR Settings and Internal Clock Frequencies FRQCR (Lower 9 Bits) H'008 H'00A H'00C H'011 H'013 H'01A H'01C H'023 H'02C H'05A H'05C H'063 H'06C H'0A3 H'0EC 1/3 1/4 1/6 1/8 1/6 1/8 1/2 1/6 1/8 1/4 1/4 1/3 Frequency Division Ratio of Frequency Divider 2 CPU Clock 1 Bus Clock 1/2 Peripheral Module Clock 1/2 1/4 1/8 1/3 1/6 1/4 1/8 1/6 1/8 1/4 1/8 1/6 1/8 1/6 1/8 Note: For the lower 9 bits of FRQCR, do not set values other than those shown in the table. Rev.7.00 Oct. 10, 2008 Page 294 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits 10.4 10.4.1 CPG Register Description Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit readable/writable register that specifies use/non-use of clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU clock, bus clock, and peripheral module clock frequency division ratios. Only word access can be used on FRQCR. FRQCR is initialized only by a power-on reset via the RESET pin. The initial value of each bit is determined by the clock operating mode. Bit: 15 — Initial value: R/W: Bit: 0 R/W 7 IFC1 Initial value: R/W: — R/W 14 — 0 R/W 6 IFC0 — R/W 13 — 0 R/W 5 BFC2 — R/W 12 — 0 R 4 BFC1 — R/W 11 10 9 8 IFC2 — R/W 0 PFC0 — R/W CKOEN PLL1EN PLL2EN 1 R/W 3 BFC0 — R/W 1 R/W 2 PFC2 — R/W 1 R/W 1 PFC1 — R/W Bits 15 to 12—Reserved: These bits are always read as 0, and should only be written with 0. Bit 11—Clock Output Enable (CKOEN): Specifies whether a clock is output from the CKIO pin or the CKIO pin is placed in the high-impedance state. When the CKIO pin goes to the highimpedance state, operation continues at the operating frequency before this state was entered. When the CKIO pin becomes high-impedance, it is pulled up. Bit 11: CKOEN 0 1 Note: * Description CKIO pin goes to high-impedance state (pulled up*) Clock is output from CKIO pin It is not pulled up in hardware standby mode. (Initial value) Rev.7.00 Oct. 10, 2008 Page 295 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits Bit 10—PLL Circuit 1 Enable (PLL1EN): Specifies whether PLL circuit 1 is on or off. Bit 10: PLL1EN 0 1 Description PLL circuit 1 is not used PLL circuit 1 is used (Initial value) Bit 9—PLL Circuit 2 Enable (PLL2EN): Specifies whether PLL circuit 2 is on or off. Bit 9: PLL2EN 0 1 Description PLL circuit 2 is not used PLL circuit 2 is used (Initial value) Bits 8 to 6—CPU Clock Frequency Division Ratio (IFC): These bits specify the CPU clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency. Bit 8: IFC2 0 Bit 7: IFC1 0 Bit 6: IFC0 0 1 1 0 1 1 0 0 1 Other than the above Description ×1 ×1/2 ×1/3 ×1/4 ×1/6 ×1/8 Setting prohibited (Do not set) Rev.7.00 Oct. 10, 2008 Page 296 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits Bits 5 to 3—Bus Clock Frequency Division Ratio (BFC): These bits specify the bus clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency. Bit 5: BFC2 0 Bit 4: BFC1 0 Bit 3: BFC0 0 1 1 0 1 1 0 0 1 Other than the above Description ×1 ×1/2 ×1/3 ×1/4 ×1/6 ×1/8 Setting prohibited (Do not set) Bits 2 to 0—Peripheral Module Clock Frequency Division Ratio (PFC): These bits specify the peripheral module clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency. Bit 2: PFC2 0 Bit 1: PFC1 0 Bit 0: PFC0 0 1 1 0 1 1 0 0 Description ×1/2 ×1/3 ×1/4 ×1/6 ×1/8 Setting prohibited (Do not set) Other than the above Rev.7.00 Oct. 10, 2008 Page 297 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits 10.5 Changing the Frequency There are two methods of changing the internal clock frequency: by changing stopping and starting of PLL circuit 1, and by changing the frequency division ratio of each clock. In both cases, control is performed by software by means of the frequency control register. These methods are described below. 10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off) When PLL circuit 1 is changed from the stopped to started state, a PLL stabilization time is required. The oscillation stabilization time count is performed by the on-chip WDT. 1. Set a value in WDT to provide the specified oscillation stabilization time, and stop the WDT. The following settings are necessary: WTCSR register TME bit = 0: WDT stopped WTCSR register CKS2–CKS0 bits: WDT count clock division ratio WTCNT counter: Initial counter value 2. Set the PLL1EN bit to 1. 3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal clock stops and an unstable clock is output to the CKIO pin. 4. After the WDT count overflows, clock supply begins within the chip and the processor resumes operation. The WDT stops after overflowing. 10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On) When PLL circuit 2 is on, a PLL circuit 1 and PLL circuit 2 oscillation stabilization time is required. 1. Make WDT settings as in section 10.5.1. 2. Set the PLL1EN bit to 1. 3. Internal processor operation stops temporarily, PLL circuit 1 oscillates, and the WDT starts counting up. The internal clock stops and an unstable clock is output to the CKIO pin. 4. After the WDT count overflows, PLL circuit 2 starts oscillating. The WDT resumes its upcount from the value set in step 1 above. During this time, also, the internal clock is stopped and an unstable clock is output to the CKIO pin. 5. After the WDT count overflows, clock supply begins within the chip and the processor resumes operation. The WDT stops after overflowing. Rev.7.00 Oct. 10, 2008 Page 298 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits 10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On) If PLL circuit 2 is on when the bus clock frequency division ratio is changed, a PLL circuit 2 oscillation stabilization time is required. 1. Make WDT settings as in section 10.5.1. 2. Set the BFC2–BFC0 bits to the desired value. 3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal clock stops and an unstable clock is output to the CKIO pin. 4. After the WDT count overflows, clock supply begins within the chip and the processor resumes operation. The WDT stops after overflowing. 10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off) If PLL circuit 2 is off when the bus clock frequency division ratio is changed, a WDT count is not performed. 1. Set the BFC2–BFC0 bits to the desired value. 2. The set clock is switched to immediately. 10.5.5 Changing CPU or Peripheral Module Clock Division Ratio When the CPU or peripheral module clock frequency division ratio is changed, a WDT count is not performed. 1. Set the IFC2–IFC0 or PFC2–PFC0 bits to the desired value. 2. The set clock is switched to immediately. 10.6 Output Clock Control The CKIO pin can be switched between clock output and a fixed level setting by means of the CKOEN bit in the FRQCR register. When the CKIO pin goes to the high-impedance state, it is pulled up. Rev.7.00 Oct. 10, 2008 Page 299 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits 10.7 10.7.1 Overview of Watchdog Timer Block Diagram Figure 10.2 shows a block diagram of the WDT. WDT Standby release Standby control Standby mode Frequency divider 2 ×1 clock Internal reset request Reset control Clock selection Frequency divider Clock selector Interrupt request Interrupt control Overflow Clock WTCSR WTCNT Bus interface Legend: WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter Figure 10.2 Block Diagram of WDT Rev.7.00 Oct. 10, 2008 Page 300 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits 10.7.2 Register Configuration The WDT has the two registers summarized in table 10.5. These registers control clock selection and timer mode switching. Table 10.5 WDT Registers Name Watchdog timer counter Watchdog timer control/status register Note: * Abbreviation WTCNT WTCSR R/W R/W* R/W* Initial Value H'00 H'00 P4 Address H'FFC00008 H'FFC0000C Area 7 Address H'1FC00008 H'1FC0000C Access Size R: 8, W: 16* R: 8, W: 16* Use word-size access when writing. Perform the write with the upper byte set to H'5A or H'A5, respectively. Byte- and longword-size writes cannot be used. Use byte access when reading. 10.8 10.8.1 WDT Register Descriptions Watchdog Timer Counter (WTCNT) The watchdog timer counter (WTCNT) is an 8-bit readable/writable counter that counts up on the selected clock. When WTCNT overflows, a reset is generated in watchdog timer mode, or an interrupt in interval timer mode. WTCNT is initialized to H'00 only by a power-on reset via the RESET pin. To write to the WTCNT counter, use a word-size access with the upper byte set to H'5A. To read WTCNT, use a byte-size access. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev.7.00 Oct. 10, 2008 Page 301 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits 10.8.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register containing bits for selecting the count clock and timer mode, and overflow flags. WTCSR is initialized to H'00 only by a power-on reset via the RESET pin. It retains its value in an internal reset due to WDT overflow. When used to count the clock stabilization time when exiting standby mode, WTCSR retains its value after the counter overflows. To write to the WTCSR register, use a word-size access with the upper byte set to H'A5. To read WTCSR, use a byte-size access. Bit: 7 TME Initial value: R/W: 0 R/W 6 WT/IT 0 R/W 5 RSTS 0 R/W 4 WOVF 0 R/W 3 IOVF 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7—Timer Enable (TME): Specifies starting and stopping of timer operation. Clear this bit to 0 when using the WDT in standby mode or to change a clock frequency. Bit 7: TME 0 1 Description Up-count stopped, WTCNT value retained Up-count started (Initial value) Bit 6—Timer Mode Select (WT/IT): Specifies whether the WDT is used as a watchdog timer or interval timer. Bit 6: WT/IT 0 1 Description Interval timer mode Watchdog timer mode (Initial value) Note: The up-count may not be performed correctly if WT/IT is modified while the WDT is running. Rev.7.00 Oct. 10, 2008 Page 302 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits Bit 5—Reset Select (RSTS): Specifies the kind of reset to be performed when WTCNT overflows in watchdog timer mode. This setting is ignored in interval timer mode. Bit 5: RSTS 0 1 Description Power-on reset Manual reset (Initial value) Bit 4—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed in watchdog timer mode. This flag is not set in interval timer mode. Bit 4: WOVF 0 1 Description No overflow WTCNT has overflowed in watchdog timer mode (Initial value) Bit 3—Interval Timer Overflow Flag (IOVF): Indicates that WTCNT has overflowed in interval timer mode. This flag is not set in watchdog timer mode. Bit 3: IOVF 0 1 Description No overflow WTCNT has overflowed in interval timer mode (Initial value) Rev.7.00 Oct. 10, 2008 Page 303 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits Bits 2 to 0—Clock Select 2 to 0 (CKS2–CKS0): These bits select the clock used for the WTCNT count from eight clocks obtained by dividing the frequency divider 2 input clock*. The overflow periods shown in the following table are for use of a 33 MHz input clock, with frequency divider 1 off, and PLL circuit 1 on (×6). Note: * When PLL1 is switched on or off, the clock following the switch is used. Description Bit 2: CKS2 0 Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Division Ratio 1/32 1/64 1/128 1/256 1/512 1/1024 1/2048 1/4096 (Initial value) Overflow Period 41 μs 82 μs 164 μs 328 μs 656 μs 1.31 ms 2.62 ms 5.25 ms Note: The up-count may not be performed correctly if bits CKS2–CKS0 are modified while the WDT is running. Always stop the WDT before modifying these bits. Rev.7.00 Oct. 10, 2008 Page 304 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits 10.8.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) differ from other registers in being more difficult to write to. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written to with a word transfer instruction. They cannot be written to with a byte or longword transfer instruction. When writing to WTCNT, perform the transfer with the upper byte set to H'5A and the lower byte containing the write data. When writing to WTCSR, perform the transfer with the upper byte set to H'A5 and the lower byte containing the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. The write formats are shown in figure 10.3. WTCNT write 15 Address: H'FFC00008 (H'1FC00008) H'5A 8 7 Write data 0 WTCSR write 15 Address: H'FFC0000C (H'1FC0000C) H'A5 8 7 Write data 0 Figure 10.3 Writing to WTCNT and WTCSR 10.9 10.9.1 Using the WDT Standby Clearing Procedure The WDT is used when clearing standby mode by means of an NMI or other interrupt. The procedure is shown below. (As the WDT does not operate when standby mode is cleared with a reset, the RESET pin should be held low until the clock stabilizes.) 1. Be sure to clear the TME bit in the WTCSR register to 0 before making a transition to standby mode. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows. 2. Select the count clock to be used with bits CKS2–CKS0 in the WTCSR register, and set the initial value in the WTCNT counter. Make these settings so that the time until the count Rev.7.00 Oct. 10, 2008 Page 305 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits 3. 4. 5. 6. overflows is at least as long as the clock oscillation stabilization time. For details of the clock oscillation stabilization time, see section 22.3.1, Clock and Control Signal Timing. Make a transition to standby mode, and stop the clock, by executing a SLEEP instruction. The WDT starts counting on detection of an NMI signal transition edge or an interrupt. When the WDT count overflows, the CPG starts clock supply and the processor resumes operation. The WOVF flag in the WTCSR register is not set at this time. The counter stops at a value of H'00–H'01. The value at which the counter stops depends on the clock ratio. Frequency Changing Procedure 10.9.2 The WDT is used in a frequency change using the PLL. It is not used when the frequency is changed simply by making a frequency divider switch. 1. Be sure to clear the TME bit in the WTCSR register to 0 before making a frequency change. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows. 2. Select the count clock to be used with bits CKS2–CKS0 in the WTCSR register, and set the initial value in the WTCNT counter. Make these settings so that the time until the count overflows is at least as long as the clock oscillation stabilization time. For details of the clock oscillation stabilization time, see section 22.3.1, Clock and Control Signal Timing. 3. When the frequency control register (FRQCR) is modified, the clock stops, and the standby state is entered temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG starts clock supply and the processor resumes operation. The WOVF flag in the WTCSR register is not set at this time. 5. The counter stops at a value of H'00–H'01. The value at which the counter stops depends on the clock ratio. 6. When re-setting WTCNT immediately after modifying the frequency control register (FRQCR), first read the counter and confirm that its value is as described in step 5 above. 10.9.3 Using Watchdog Timer Mode 1. Set the WT/IT bit in the WTCSR register to 1, select the type of reset with the RSTS bit, and the count clock with bits CKS2–CKS0, and set the initial value in the WTCNT counter. 2. When the TME bit in the WTCSR register is set to 1, the count starts in watchdog timer mode. 3. During operation in watchdog timer mode, write H'00 to the counter periodically so that it does not overflow. Rev.7.00 Oct. 10, 2008 Page 306 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits 4. When the counter overflows, the WDT sets the WOVF flag in the WTCSR register to 1, and generates a reset of the type specified by the RSTS bit. The counter then continues counting. 10.9.4 Using Interval Timer Mode When the WDT is operating in interval timer mode, an interval timer interrupt is generated each time the counter overflows. This enables interrupts to be generated at fixed intervals. 1. Clear the WT/IT bit in the WTCSR register to 0, select the count clock with bits CKS2–CKS0, and set the initial value in the WTCNT counter. 2. When the TME bit in the WTCSR register is set to 1, the count starts in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF flag in the WTCSR register to 1, and sends an interval timer interrupt request to INTC. The counter continues counting. 10.10 Notes on Board Design When Using a Crystal Resonator: Place the crystal resonator and capacitors close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, ensure that no other signal lines cross the signal lines for these pins. CL1 CL2 Avoid crossing signal lines R Recommended values CL1 = CL2 = 0–33 pF R = 0Ω EXTAL XTAL SH7750 SH7750S SH7750R Note: The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer. Figure 10.4 Points for Attention when Using Crystal Resonator When Inputting External Clock from EXTAL Pin: Make no connection to the XTAL pin. Rev.7.00 Oct. 10, 2008 Page 307 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits When Using a PLL Oscillator Circuit: Separate VDD-CPG and VSS-CPG from the other VDD and VSS lines at the board power supply source, and insert resistors RCB and RB and bypass capacitors CPB and CB close to the pins as noise filters. RCB1 VDD-PLL1 CPB1 VSS-PLL1 Recommended values RCB1 = RCB2 = 10 Ω CPB1 = CPB2 = 10 μF RB = 10 Ω CB = 10 μF RCB2 VDD-PLL2 SH7750 SH7750S SH7750R CPB2 VSS-PLL2 RB VDD-CPG CB VSS-CPG 3.3 V Figure 10.5 Points for Attention when Using PLL Oscillator Circuit Rev.7.00 Oct. 10, 2008 Page 308 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits 10.11 Usage Notes 10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7750 and SH7750S) Under certain conditions the watchdog timer (WDT) may trigger an invalid manual reset. Conditions Under which Problem Occurs: The internal WDT triggers an invalid manual reset when all of the following four conditions are satisfied. 1. 2. 3. 4. After the WDT overflows, regardless of the values of the WT/IT and RSTS bits in WTCSR. Before the counter (WTCNT) is incremented by the clock specified by the WTCSR.CKS bit. The value of at least one of the TME, WT/IT, and RSTS bits in WTCSR is 0. A value of 1 is written to the TME, WT/IT, and RSTS bits in WTCSR. Workaround: A workaround for this problem is to use software to increment WTCNT before writing 1 to the TME, WT/IT, and RSTS bits in WTCSR. Specific lines of code for this purpose are listed below. Example: Add the following lines of code before the instructions for writing 1 to the TME, WT/IT, and RSTS bits in WTCSR. MOV.L MOV.W MOV.W MOV.L MOV.W MOV.W LOOP_WDT: MOV.B @R7,R0 #WTCNT,R7 #H'5A00,R8 R8,@R7 #WTCSR,R9 #H'A580,R10 R10,@R9 CMP/EQ #H'00, R0 BT LOOP_WDT Rev.7.00 Oct. 10, 2008 Page 309 of 1074 REJ09B0366-0700 Section 10 Clock Oscillation Circuits Rev.7.00 Oct. 10, 2008 Page 310 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) Section 11 Realtime Clock (RTC) 11.1 Overview This LSI includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillation circuit for use by the RTC. 11.1.1 Features The RTC has the following features. • Clock and calendar functions (BCD display) Counts seconds, minutes, hours, day-of-week, days, months, and years. • 1 to 64 Hz timer (binary display) The 64 Hz counter register indicates a state of 64 Hz to 1 Hz within the RTC frequency divider • Start/stop function • 30-second adjustment function • Alarm interrupts Comparison with second, minute, hour, day-of-week, day, month, or year (year is available only with the SH7750R) can be selected as the alarm interrupt condition • Periodic interrupts An interrupt period of 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds can be selected • Carry interrupt Carry interrupt function indicating a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read • Automatic leap year adjustment Rev.7.00 Oct. 10, 2008 Page 311 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the RTC. ATI RTCCLK 16.384 kHz PRI CUI RESET, STBY, etc Prescaler 128 Hz 32.768 kHz RTC crystal oscillation circuit RTC operation control unit RCR1 RCR2 Counter unit R64CNT Interrupt control unit RCR3* RSECCNT RMINCNT RHRCNT RDAYCNT RWKCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RDAYAR RWKAR RMONAR RYRAR* To registers Bus interface Internal peripheral module bus Note: * SH7750R only Figure 11.1 Block Diagram of RTC Rev.7.00 Oct. 10, 2008 Page 312 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) 11.1.3 Pin Configuration Table 11.1 shows the RTC pins. Table 11.1 RTC Pins Pin Name Abbreviation I/O Input Function Connects crystal to RTC oscillation circuit RTC oscillation circuit crystal pin EXTAL2 RTC oscillation circuit crystal pin XTAL2 Clock input/clock output TCLK Output Connects crystal to RTC oscillation circuit I/O External clock input pin/input capture control input pin/RTC output pin (shared with TMU) RTC oscillation circuit power supply pin* RTC oscillation circuit GND pin* Dedicated RTC power supply Dedicated RTC GND pin Note: * VDD-RTC VSS-RTC — — Power must be supplied to the RTC power supply pins even when the RTC is not used. 11.1.4 Register Configuration Table 11.2 summarizes the RTC registers. Table 11.2 RTC Registers Initialization Abbreviation R64CNT RSECCNT RMINCNT RHRCNT RWKCNT PowerOn Reset Manual Standby Initial Value Reset Mode Area 7 Address Access Size Name 64 Hz counter Second counter Minute counter Hour counter Day-ofweek counter Day counter R/W R R/W R/W R/W R/W P4 Address Counts Counts Counts Undefined Counts Counts Counts Undefined Counts Counts Counts Undefined Counts Counts Counts Undefined Counts Counts Counts Undefined H'FFC80000 H'1FC80000 8 H'FFC80004 H'1FC80004 8 H'FFC80008 H'1FC80008 8 H'FFC8000C H'1FC8000C 8 H'FFC80010 H'1FC80010 8 RDAYCNT R/W Counts Counts Counts Undefined H'FFC80014 H'1FC80014 8 Rev.7.00 Oct. 10, 2008 Page 313 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) Initialization Name Abbreviation R/W Power-On Manual Reset Reset Counts Counts Counts Counts Standby Initial Mode Value Counts Counts Held Undefined Undefined 1 Area 7 P4 Address Address Access Size Month RMONCNT R/W counter Year RYRCNT counter Second RSECAR alarm register Minute RMINAR alarm register RHRAR Hour alarm register Day-of- RWKAR week alarm register RDAYAR Day alarm register Month RMONAR alarm register RCR1 RTC control register 1 RCR2 RTC control register 2 RCR3 RTC control register 5 3* RYRAR Year alarm 5 register* R/W R/W H'FFC80018 H'1FC80018 8 H'FFC8001C H'1FC8001C 16 1 Initialized* Held Undefined* H'FFC80020 H'1FC80020 8 R/W 1 Initialized* Held Held Undefined* H'FFC80024 H'1FC80024 8 1 R/W 1 Initialized* Held Held Undefined* H'FFC80028 H'1FC80028 8 1 R/W 1 Initialized* Held Held Undefined* H'FFC8002C H'1FC8002C 8 1 R/W 1 Initialized* Held Held Undefined* H'FFC80030 H'1FC80030 8 1 R/W 1 Initialized* Held Held Undefined* H'FFC80034 H'1FC80034 8 1 R/W Initialized Initialized Held H'00* 3 H'FFC80038 H'1FC80038 8 R/W 2 Initialized Initialized* Held H'09* 4 H'FFC8003C H'1FC8003C 8 R/W Initialized Held Held H'00 H'FFC80050 H'1FC80050 8 R/W Held Held Held Undefined H'FFC80054 H'1FC80054 16 Notes: 1. 2. 3. 4. 5. The ENB bit in each register is initialized. Bits other than the RTCEN bit and START bit are initialized. The value of the CF bit and AF bit is undefined. The value of the PEF bit is undefined. SH7750R only Rev.7.00 Oct. 10, 2008 Page 314 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) 11.2 11.2.1 Register Descriptions 64 Hz Counter (R64CNT) R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC frequency divider. If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7 (CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 Hz counter read. In this case, the read value is not valid, and so R64CNT must be read again after first writing 0 to the CF bit in RCR1 to clear it. When the RESET bit or ADJ bit in RTC control register 2 (RCR2) is set to 1, the RTC frequency divider is initialized and R64CNT is initialized to H'00. R64CNT is not initialized by a power-on or manual reset, or in standby mode. Bit 7 is always read as 0 and cannot be modified. Bit: 7 — Initial value: R/W: 0 R 6 1 Hz R 5 2 Hz R 4 4 Hz R 3 8 Hz R 2 16 Hz R 1 32 Hz R 0 64 Hz R Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev.7.00 Oct. 10, 2008 Page 315 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) 11.2.2 Second Counter (RSECCNT) RSECCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded second value in the RTC. It counts on the carry (transition of the R64CNT.1Hz bit from 0 to 1) generated once per second by the 64 Hz counter. The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RSECCNT is not initialized by a power-on or manual reset, or in standby mode. Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0. Bit: 7 — Initial value: R/W: 0 R 6 5 10-second units R/W R/W R/W R/W 4 3 2 1 0 1-second units R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined 11.2.3 Minute Counter (RMINCNT) RMINCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded minute value in the RTC. It counts on the carry generated once per minute by the second counter. The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RMINCNT is not initialized by a power-on or manual reset, or in standby mode. Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0. Bit: 7 — Initial value: R/W: 0 R 6 5 10-minute units R/W R/W R/W R/W 4 3 2 1 0 1-minute units R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev.7.00 Oct. 10, 2008 Page 316 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) 11.2.4 Hour Counter (RHRCNT) RHRCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded hour value in the RTC. It counts on the carry generated once per hour by the minute counter. The setting range is decimal 00 to 23. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RHRCNT is not initialized by a power-on or manual reset, or in standby mode. Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 4 3 2 1 0 10-hour units R/W R/W R/W 1-hour units R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined 11.2.5 Day-of-Week Counter (RWKCNT) RWKCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day-of-week value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 0 to 6. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RWKCNT is not initialized by a power-on or manual reset, or in standby mode. Bits 7 to 3 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 1 Day of week code Undefined Undefined Undefined 0 R/W R/W R/W Rev.7.00 Oct. 10, 2008 Page 317 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) Day-of-week code Day of week 0 Sun 1 Mon 2 Tue 3 Wed 4 Thu 5 Fri 6 Sat 11.2.6 Day Counter (RDAYCNT) RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 01 to 31. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RDAYCNT is not initialized by a power-on or manual reset, or in standby mode. The setting range for RDAYCNT depends on the month and whether the year is a leap year, so care is required when making the setting. Taking the year counter (RYRCNT) value as the year, leap year calculation is performed according to whether or not the value is divisible by 400, 100, and 4. Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 4 3 2 1 0 10-day units R/W R/W R/W 1-day units R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined 11.2.7 Month Counter (RMONCNT) RMONCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded month value in the RTC. It counts on the carry generated once per month by the day counter. The setting range is decimal 01 to 12. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RMONCNT is not initialized by a power-on or manual reset, or in standby mode. Rev.7.00 Oct. 10, 2008 Page 318 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) Bits 7 to 5 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 — 0 R 4 10-month unit R/W R/W 3 2 1 0 1-month units Undefined Undefined Undefined Undefined Undefined R/W R/W R/W 11.2.8 Year Counter (RYRCNT) RYRCNT is a 16-bit readable/writable register used as a counter for setting and counting the BCD-coded year value in the RTC. It counts on the carry generated once per year by the month counter. The setting range is decimal 0000 to 9999. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RYRCNT is not initialized by a power-on or manual reset, or in standby mode. Bit: 15 14 13 12 11 10 9 8 1000-year units R/W: Bit: R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 100-year units R/W 2 R/W 1 R/W 0 Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 10-year units R/W: R/W R/W R/W R/W R/W 1-year units R/W R/W R/W Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev.7.00 Oct. 10, 2008 Page 319 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) 11.2.9 Second Alarm Register (RSECAR) RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared with the RSECCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RSECAR is initialized to 0 by a power-on reset. The other fields in RSECAR are not initialized by a power-on or manual reset, or in standby mode. Bit: 7 ENB Initial value: R/W: 0 R/W 6 5 10-second units R/W R/W R/W R/W 4 3 2 1 0 1-second units R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined 11.2.10 Minute Alarm Register (RMINAR) RMINAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded minute value counter, RMINCNT. When the ENB bit is set to 1, the RMINAR value is compared with the RMINCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RMINAR is initialized by a power-on reset. The other fields in RMINAR are not initialized by a power-on or manual reset, or in standby mode. Bit: 7 ENB Initial value: R/W: 0 R/W 6 5 10-minute units R/W R/W R/W R/W 4 3 2 1 0 1-minute units R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev.7.00 Oct. 10, 2008 Page 320 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) 11.2.11 Hour Alarm Register (RHRAR) RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with the RHRCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 00 to 23 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RHRAR is initialized by a power-on reset. The other fields in RHRAR are not initialized by a power-on or manual reset, or in standby mode. Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0. Bit: 7 ENB Initial value: R/W: 0 R/W 6 — 0 R 5 4 3 2 1 0 10-hour units R/W R/W R/W 1-hour units R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined 11.2.12 Day-of-Week Alarm Register (RWKAR) RWKAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded day-of-week value counter, RWKCNT. When the ENB bit is set to 1, the RWKAR value is compared with the RWKCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 0 to 6 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RWKAR is initialized by a power-on reset. The other fields in RWKAR are not initialized by a power-on or manual reset, or in standby mode. Bits 6 to 3 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Rev.7.00 Oct. 10, 2008 Page 321 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) Bit: 7 ENB Initial value: R/W: 0 R/W 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 1 Day of week code Undefined Undefined Undefined 0 R/W R/W R/W Day-of-week code Day of week 0 Sun 1 Mon 2 Tue 3 Wed 4 Thu 5 Fri 6 Sat 11.2.13 Day Alarm Register (RDAYAR) RDAYAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCDcoded day value counter, RDAYCNT. When the ENB bit is set to 1, the RDAYAR value is compared with the RDAYCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 01 to 31 + ENB bit. The RTC will not operate normally if any other value is set. The setting range for RDAYAR depends on the month and whether the year is a leap year, so care is required when making the setting. The ENB bit in RDAYAR is initialized by a power-on reset. The other fields in RDAYAR are not initialized by a power-on or manual reset, or in standby mode. Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0. Bit: 7 ENB Initial value: R/W: 0 R/W 6 — 0 R 5 4 3 2 1 0 10-day units R/W R/W R/W 1-day units R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Rev.7.00 Oct. 10, 2008 Page 322 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) 11.2.14 Month Alarm Register (RMONAR) RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCDcoded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is compared with the RMONCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 01 to 12 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RMONAR is initialized by a power-on reset. The other fields in RMONAR are not initialized by a power-on or manual reset, or in standby mode. Bits 6 and 5 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: 7 ENB Initial value: R/W: 0 R/W 6 — 0 R 5 — 0 R 4 10-month unit R/W R/W 3 2 1 0 1-month units Undefined Undefined Undefined Undefined Undefined R/W R/W R/W 11.2.15 RTC Control Register 1 (RCR1) RCR1 is an 8-bit readable/writable register containing a carry flag and alarm flag, plus flags to enable or disable interrupts for these flags. The CIE and AIE bits are initialized to 0 by a power-on or manual reset; the value of bits other than CIE and AIE is undefined. In standby mode RCR1 is not initialized, and retains its current value. Bit: 7 CF R/W: R/W 6 — R 5 — R 4 CIE 0 R/W 3 AIE 0 R/W 2 — R 1 — R 0 AF R/W Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Rev.7.00 Oct. 10, 2008 Page 323 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) Bit 7—Carry Flag (CF): This flag is set to 1 on generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read. The count register value read at this time is not guaranteed, and so the count register must be read again. Bit 7: CF 0 Description No second counter carry, or 64 Hz counter carry when 64 Hz counter is read [Clearing condition] When 0 is written to CF 1 Second counter carry, or 64 Hz counter carry when 64 Hz counter is read [Setting conditions] • • Generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read When 1 is written to CF Bit 4—Carry Interrupt Enable Flag (CIE): Enables or disables interrupt generation when the carry flag (CF) is set to 1. Bit 4: CIE 0 1 Description Carry interrupt is not generated when CF flag is set to 1 Carry interrupt is generated when CF flag is set to 1 (Initial value) Bit 3—Alarm Interrupt Enable Flag (AIE): Enables or disables interrupt generation when the alarm flag (AF) is set to 1. Bit 3: AIE 0 1 Description Alarm interrupt is not generated when AF flag is set to 1 Alarm interrupt is generated when AF flag is set to 1 (Initial value) Rev.7.00 Oct. 10, 2008 Page 324 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) Bit 0—Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1 matches the respective counter values. Bit 0: AF 0 Description Alarm registers and counter values do not match [Clearing condition] When 0 is written to AF 1 Alarm registers and counter values match* [Setting condition] When alarm registers in which the ENB bit is set to 1 and counter values match* Note: * Writing 1 does not change the value. (Initial value) Bits 6, 5, 2, and 1—Reserved. The initial value of these bits is undefined. A write to these bits is invalid, but the write value should always be 0. 11.2.16 RTC Control Register 2 (RCR2) RCR2 is an 8-bit readable/writable register used for periodic interrupt control, 30-second adjustment, and frequency divider RESET and RTC count control. RCR2 is basically initialized to H'09 by a power-on reset, except that the value of the PEF bit is undefined. In a manual reset, bits other than RTCEN and START are initialized, while the value of the PEF bit is undefined. In standby mode RCR2 is not initialized, and retains its current value. Bit: 7 PEF Initial value: Undefined R/W: R/W 6 PES2 0 R/W 5 PES1 0 R/W 4 PES0 0 R/W 3 RTCEN 1 R/W 2 ADJ 0 R/W 1 RESET 0 R/W 0 START 1 R/W Rev.7.00 Oct. 10, 2008 Page 325 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) Bit 7—Periodic Interrupt Flag (PEF): Indicates interrupt generation at the interval specified by bits PES2–PES0. When this flag is set to 1, a periodic interrupt is generated. Bit 7: PEF 0 Description Interrupt is not generated at interval specified by bits PES2–PES0 [Clearing condition] When 0 is written to PEF 1 Interrupt is generated at interval specified by bits PES2–PES0 [Setting conditions] • • Generation of interrupt at interval specified by bits PES2–PES0 When 1 is written to PEF Bits 6 to 4—Periodic Interrupt Enable (PES2–PES0): These bits specify the period for periodic interrupts. Bit 6: PES2 0 Bit 5: PES1 0 Bit 4: PES0 0 1 1 0 1 1 0 0 1 1 0 1 Description No periodic interrupt generation (Initial value) Periodic interrupt generated at 1/256-second intervals Periodic interrupt generated at 1/64-second intervals Periodic interrupt generated at 1/16-second intervals Periodic interrupt generated at 1/4-second intervals Periodic interrupt generated at 1/2-second intervals Periodic interrupt generated at 1-second intervals Periodic interrupt generated at 2-second intervals Bit 3— Oscillation Circuit Enable (RTCEN): Controls the operation of the RTC crystal oscillation circuit. Bit 3: RTCEN 0 1 Description RTC crystal oscillation circuit halted RTC crystal oscillation circuit operating (Initial value) Rev.7.00 Oct. 10, 2008 Page 326 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) Bit 2—30-Second Adjustment (ADJ): Used for 30-second adjustment. When 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute. The frequency divider circuits (RTC prescaler and R64CNT) are also reset at this time. This bit always returns 0 if read. Bit 2: ADJ 0 1 Description Normal clock operation 30-second adjustment performed (Initial value) Bit 1—Reset (RESET): The frequency divider circuits are initialized by writing 1 to this bit. When 1 is written to the RESET bit, the frequency divider circuits (RTC prescaler and R64CNT) are reset and the RESET bit is automatically cleared to 0 (i.e. does not need to be written with 0). Bit 1: RESET 0 1 Description Normal clock operation Frequency divider circuits are reset (Initial value) Bit 0—Start Bit (START): Stops and restarts counter (clock) operation. Bit 0: START 0 1 Note: * Description Second, minute, hour, day, day-of-week, month, and year counters are stopped* Second, minute, hour, day, day-of-week, month, and year counters operate normally* (Initial value) The 64 Hz counter continues to operate unless stopped by means of the RTCEN bit. 11.2.17 RTC Control Register 3 (RCR3) and Year-Alarm Register (RYRAR) (SH7750R Only) RCR3 and RYRAR are readable/writable registers. RYRAR is the alarm register for the RTC's BCD-coded year-value counter RYRCNT. When the YENB bit of RCR3 is set to 1, the RYRCNT value is compared with the RYRAR value. Comparison between the counter and the alarm register only takes place with the alarm registers in which the ENB and YENB bits are set to 1. The alarm flag of RCR1 is only set to 1 when the respective values all match. The setting range of RYRAR is decimal 0000 to 9999, and normal operation is not obtained if a value beyond this range is set here. Rev.7.00 Oct. 10, 2008 Page 327 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) RCR3 is initialized by a power-on reset, but RYRAR will not be initialized by a power-on or manual reset, or by the device entering standby mode. Bits 6 to 0 of RCR3 are always read as 0. Writing to these bits is invalid. If a value is written to these bits, it should always be 0. RCR3 Bit: 7 YENB Initial value: R/W: 0 R/W 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R RYRAR Bit: 15 14 13 12 11 10 9 8 1000 years R/W: Bit: R/W 7 R/W 6 R/W 5 10 years R/W: R/W R/W R/W R/W R/W R/W 4 R/W 3 100 years R/W 2 1 year R/W R/W R/W R/W 1 R/W 0 Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Rev.7.00 Oct. 10, 2008 Page 328 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) 11.3 Operation Examples of the use of the RTC are shown below. 11.3.1 Time Setting Procedures Figure 11.2 shows examples of the time setting procedures. Stop clock Reset frequency divider Set RCR2.RESET to 1 Clear RCR2.START to 0 Set second/minute/hour/day/ day-of-week/month/year In any order Start clock operation Set RCR2.START to 1 (a) Setting time after stopping clock Clear carry flag Clear RCR1.CF to 0 (Write 1 to RCR1.AF so that alarm flag is not cleared) Set RYRCNT first and RSECCNT last Write to counter register Yes Carry flag = 1? No Read RCR1 register and check CF bit (b) Setting time while clock is running Figure 11.2 Examples of Time Setting Procedures The procedure for setting the time after stopping the clock is shown in (a). The programming for this method is simple, and it is useful for setting all the counters, from second to year. Rev.7.00 Oct. 10, 2008 Page 329 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) The procedure for setting the time while the clock is running is shown in (b). This method is useful for modifying only certain counter values (for example, only the second data or hour data). If a carry occurs during the write operation, the write data is automatically updated and there will be an error in the set data. The carry flag should therefore be used to check the write status. If the carry flag (RCR1.CF) is set to 1, the write must be repeated. The interrupt function can also be used to determine the carry flag status. 11.3.2 Time Reading Procedures Figure 11.3 shows examples of the time reading procedures. Rev.7.00 Oct. 10, 2008 Page 330 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) Disable carry interrupts Clear RCR1.CIE to 0 Clear RCR1.CF to 0 (Write 1 to RCR1.AF so that alarm flag is not cleared) Clear carry flag Read counter register Yes Carry flag = 1? No Read RCR1 register and check CF bit (a) Reading time without using interrupts Clear carry flag Enable carry interrupts Set RCR1.CIE to 1 Clear RCR1.CF to 0 (Write 1 to RCR1.AF so that alarm flag is not cleared) Clear carry flag Read counter register Yes Interrupt generated? No Disable carry interrupts Clear RCR1.CIE to 0 (b) Reading time using interrupts Figure 11.3 Examples of Time Reading Procedures If a carry occurs while the time is being read, the correct time will not be obtained and the read must be repeated. The procedure for reading the time without using interrupts is shown in (a), and the procedure using carry interrupts in (b). The method without using interrupts is normally used to keep the program simple. Rev.7.00 Oct. 10, 2008 Page 331 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) 11.3.3 Alarm Function The use of the alarm function is illustrated in figure 11.4. Clock running Disable alarm interrupts Clear RCR1.AIE to prevent erroneous interrupts Set alarm time Clear alarm flag Be sure to reset the flag as it may have been set during alarm time setting Enable alarm interrupts Set RCR1.AIE to 1 Monitor alarm time (Wait for interrupt or check alarm flag) Figure 11.4 Example of Use of Alarm Function An alarm can be generated by the second, minute, hour, day-of-week, day, month, or year (year is available only with the SH7750R) value, or a combination of these. Write 1 to the ENB bit in the alarm registers involved in the alarm setting, and set the alarm time in the lower bits. Write 0 to the ENB bit in registers not involved in the alarm setting. When the counter and the alarm time match, RCR1.AF is set to 1. Alarm detection can be confirmed by reading this bit, but normally an interrupt is used. If 1 has been written to RCR1.AIE, an alarm interrupt is generated in the event of alarm, enabling the alarm to be detected. The alarm flag remains set while the counter and alarm time match. If the alarm flag is cleared by writing 0 during this period, it will therefore be set again immediately afterward. This needs to be taken into consideration when writing the program. Rev.7.00 Oct. 10, 2008 Page 332 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) 11.4 Interrupts There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts. An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while the alarm interrupt enable bit (AIE) is also set to 1. A periodic interrupt request (PRI) is generated when the periodic interrupt enable bits (PES2– PES0) in RCR2 are set to a value other than 000 and the periodic interrupt flag (PEF) is set to 1. A carry interrupt request (CUI) is generated when the carry flag (CF) in RCR1 is set to 1 while the carry interrupt enable bit (CIE) is also set to 1. 11.5 11.5.1 Usage Notes Register Initialization After powering on and making the RCR1 register settings, reset the frequency divider (by setting RCR2.RESET to 1) and make initial settings for all the other registers. 11.5.2 Carry Flag and Interrupt Flag in Standby Mode When the carry flag or interrupt flag is set to 1 at the same time this LSI transits to normal mode from standby mode by a reset or interrupt, the flag may not be set to 1. After exiting standby mode, check the counters to judge the flag states if necessary. 11.5.3 Crystal Oscillator Circuit Crystal oscillator circuit constants (recommended values) are shown in table 11.3, and the RTC crystal oscillator circuit in figure 11.5. Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values) fosc 32.768 kHz Cin 10–22 pF Cout 10–22 pF Rev.7.00 Oct. 10, 2008 Page 333 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) SH7750 SH7750S SH7750R VDD-RTC Noise filter CRTC Cin RRTC 3.3 V VSS-RTC EXTAL2 Rf RD XTAL2 XTAL Cout Notes: 1. Select either the Cin or Cout side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc. 2. Built-in resistance value Rf (typ. value) = 10 MΩ, RD (typ. value) = 400 kΩ 3. Cin and Cout values include floating capacitance due to the wiring. Take care when using a solidearth board. 4. The crystal oscillation stabilization time depends on the mounted circuit constants, floating capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip. (Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins.) 6. Ensure that the crystal resonator connection pin (EXTAL2 and XTAL2) wiring is routed as far away as possible from other power lines (except GND) and signal lines. 7. Insert a noise filter in the RTC power supply. Figure 11.5 Example of Crystal Oscillator Circuit Connection 11.5.4 RTC Register Settings (SH7750 only) Description: When setting values are written to an RTC register, values may change in writable RTC counter registers other than that to which the settings are written. The RTC registers are R64CNT, RSECCNT, RMINCNT, RHRCNT, RWKCNT, RDAYCNT, RMONCNT, RYRCNT, RSECAR, RMINAR, RHRAR, RDAYAR, RWKAR, RMONAR, RCR1, and RCR2. Of these, RSECCNT, RMINCNT, RHRCNT, RWKCNT, RDAYCNT, RMONCNT, and RYRCNT are writeable registers. Workarounds: To avoid the problem, use one of methods 1. to 3. below to write settings to the RTC registers. Rev.7.00 Oct. 10, 2008 Page 334 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) 1. Disable the DMAC channels used to access peripheral registers before writing to an RTC register, and write to the RTC register while the exception/interrupt block bit (SR.BL) in the status register is set to 1. Then use the next instruction to read from the same register. 2. Use the following method to write to an RTC register. Read all writeable counter registers (1) Write to the register whose value is to be changed Read all writeable counter registers (2) Compare the values of (1) and (2) Are the compared values valid? Yes Write operation complete No Rev.7.00 Oct. 10, 2008 Page 335 of 1074 REJ09B0366-0700 Section 11 Realtime Clock (RTC) 3. Use the following method to write to an RTC register. Read all writeable counter registers (1) Write 0 to RCR2.RTCEN Read all writeable counter registers (2) Compare the values of (1) and (2) Are the compared values valid? Yes No Write the valid value Write to the register whose value is to be changed Write 1 to RCR2.RTCEN Write operation complete Note: The operation of the RTC counter is stopped when RCR2.RTCEN is cleared to 0. Therefore, using the above method will cause the RTC counter value to fall behind the actual time by the amount of time that RCR2.RTCEN was cleared to 0, and the cycle duration for cycle interrupt generation will be lengthened as well. Rev.7.00 Oct. 10, 2008 Page 336 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) Section 12 Timer Unit (TMU) 12.1 Overview This LSI of microprocessors includes an on-chip 32-bit timer unit (TMU). The TMU of the SH7750 or SH7750S has three 32-bit timer channels (channels 0 to 2), and the TMU of the SH7750R has five channels (channels 0 to 4). 12.1.1 Features The TMU has the following features. • Auto-reload type 32-bit down-counter provided for each channel • Input capture function provided in channel 2 • Selection of rising edge or falling edge as external clock input edge when external clock is selected or input capture function is used • 32-bit timer constant register for auto-reload use, readable/writable at any time, and 32-bit down-counter provided for each channel • For channels 0 to 2, selection of seven counter input clocks for each channel External clock (TCLK), on-chip RTC output clock, five internal clocks (Pck/4, Pck/16, Pck/64, Pck/256, Pck/1024) (Pck is the peripheral module clock) • For channels 3 and 4, selection is made among five internal clocks (SH7750R only). • Channels 0 to 2 can also operate in module standby mode when the on-chip RTC output clock is selected as the counter input clock; that is, timer operation continues even when the clock has been stopped for the TMU. Timer count operations using an external or internal clock are only possible when a clock is supplied to the timer unit. • Two interrupt sources One underflow source (each channel) and one input capture source (channel 2) • DMAC data transfer request capability On channel 2, a data transfer request is sent to the DMAC when an input capture interrupt is generated. Rev.7.00 Oct. 10, 2008 Page 337 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the TMU. Pck/4,16, 64*1 TUNI3, 4*2 RESET, STBY, TUNE0,TUNE1 etc. TUNI2 ICPI2 TCLK RTCCLK TMU control unit Prescaler To each To channels channel 0 to 2 TCLK control unit TOCR TSTR TSTR2*2 Ch 0, 1 Interrupt contrun unit Ch 2 Interrupt contrun unit Ch 3, 4*2 Interrupt contrun unit Counter unit Counter unit Counter unit TCR TCOR TCNT TCR2 TCOR2 TCNT2 TCPR2 TCR TCOR TCNT Bus interface Internal peripheral module bus Notes: 1. Signals with 1/4, 1/16, and 1/64 the Pck frequency, supplied to the on-chip peripheral functions. 2. SH7750R only Figure 12.1 Block Diagram of TMU 12.1.3 Pin Configuration Table 12.1 shows the TMU pins. Table 12.1 TMU Pins Pin Name Clock input/clock output Abbreviation TCLK I/O I/O Function External clock input pin/input capture control input pin/RTC output pin (shared with RTC) Rev.7.00 Oct. 10, 2008 Page 338 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) 12.1.4 Register Configuration Table 12.2 summarizes the TMU registers. Table 12.2 TMU Registers Initialization ChanName nel Com- Timer mon output control register Timer start register Abbreviation TOCR StandPowerArea 7 Manual by On R/W Reset Reset Mode Initial Value P4 Address Address R/W Initialized Initialized Held H'00 Access Size H'FFD80000 H'1FD80000 8 TSTR R/W Initialized 3 Initialized Held IniH'00 1 tialized* Held H'00 H'FFD80004 H'1FD80004 8 TSTR2* R/W IniTimer start tialized register 2 0 TCOR0 R/W IniTimer tialized constant register 0 Timer TCNT0 counter 0 TCR0 Timer control register 0 1 R/W Initialized R/W Initialized H'FE100004 H'1E100004 8 Initialized Initialized Initialized Initialized Initialized Initialized Held H'FFFFFFFF H'FFD80008 H'1FD80008 32 2 Held* H'FFFFFFFF H'FFD8000C H'1FD8000C 32 H'0000 H'FFD80010 H'1FD80010 16 Held TCOR1 R/W IniTimer tialized constant register 1 Timer TCNT1 counter 1 TCR1 Timer control register 1 R/W Initialized R/W Initialized Held H'FFFFFFFF H'FFD80014 H'1FD80014 32 2 Held* H'FFFFFFFF H'FFD80018 H'1FD80018 32 H'0000 H'FFD8001C H'1FD8001C 16 Held Rev.7.00 Oct. 10, 2008 Page 339 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) Initialization ChanName nel 2 Abbreviation StandPowerArea 7 Manual by On R/W Reset Reset Mode Initial Value P4 Address Address Initialized Initialized Initialized Held Held Access Size TCOR2 R/W IniTimer tialized constant register 2 Timer TCNT2 counter 2 TCR2 Timer control register 2 Input capture register R/W Initialized R/W Initialized Held H'FFFFFFFF H'FFD80020 H'1FD80020 32 2 Held* H'FFFFFFFF H'FFD80024 H'1FD80024 32 H'0000 H'FFD80028 H'1FD80028 16 Held TCPR2 R Held Undefined H'FFD8002C H'1FD8002C 32 3* 3 Timer TCOR3 R/W Initialized constant register 3 Timer TCNT3 counter 3 Timer TCR3 control register 3 R/W Initialized R/W Initialized Held Held H'FFFFFFFF H'FE100008 H'1E100008 32 Held Held Held Held H'FFFFFFFF H'FE10000C H'1E10000C 32 H'0000 H'FE100010 H'1E100010 16 4* 3 Timer TCOR4 R/W Initialized constant register 4 Timer TCNT4 counter 4 Timer TCR4 control register 4 R/W Initialized R/W Initialized Held Held H'FFFFFFFF H'FE100014 H'1E100014 32 Held Held Held Held H'FFFFFFFF H'FE100018 H'1E100018 32 H'0000 H'FE10001C H'1E10001C 16 Notes: 1. Not initialized in module standby mode when the input clock is the on-chip RTC output clock. 2. Counts in module standby mode when the input clock is the on-chip RTC output clock. 3. H7750R only Rev.7.00 Oct. 10, 2008 Page 340 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) 12.2 12.2.1 Register Descriptions Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that specifies whether external pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin. TOCR is initialized to H'00 by a power-on or manual reset, but is not initialized in standby mode. Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 TCOE 0 R/W Bits 7 to 1—Reserved: These bits are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit 0—Timer Clock Pin Control (TCOE): Specifies whether timer clock pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin. Bit 0: TCOE 0 1 Note: * Description Timer clock pin (TCLK) is used as external clock input or input capture control input pin (Initial value) Timer clock pin (TCLK) is used as on-chip RTC output clock output pin* Low level output in standby mode. Rev.7.00 Oct. 10, 2008 Page 341 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) 12.2.2 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that specifies whether the channel 0–2 timer counters (TCNT) are operated or stopped. TSTR is initialized to H'00 by a power-on or manual reset, or standby mode. In module standby mode, TSTR is not initialized when the input clock selected by each channel is the on-chip RTC output clock (RTCCLK), and is initialized only when the input clock is the external clock (TCLK) or internal clock (Pck). Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 STR2 0 R/W 1 STR1 0 R/W 0 STR0 0 R/W Bits 7 to 3—Reserved: These bits are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit 2—Counter Start 2 (STR2): Specifies whether timer counter 2 (TCNT2) is operated or stopped. Bit 2: STR2 0 1 Description TCNT2 count operation is stopped TCNT2 performs count operation (Initial value) Bit 1—Counter Start 1 (STR1): Specifies whether timer counter 1 (TCNT1) is operated or stopped. Bit 1: STR1 0 1 Description TCNT1 count operation is stopped TCNT1 performs count operation (Initial value) Rev.7.00 Oct. 10, 2008 Page 342 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) Bit 0—Counter Start 0 (STR0): Specifies whether timer counter 0 (TCNT0) is operated or stopped. Bit 0: STR0 0 1 Description TCNT0 count operation is stopped TCNT0 performs count operation (Initial value) 12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only) TSTR2 is an 8-bit readable/writable register that specifies whether the channels 3−4 timer counters (TSTR2) run or are stopped. TSTR2 is initialized to H'00 by a power-on reset and retains its value in standby mode. If standby mode is entered when the STR3 or STR4 bit is set to 1, counting is halted at the same time as the peripheral module clock is stopped. Counting is restarted on resumption of the clock-signal supply. Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 STR4 0 R/W 0 STR3 0 R/W Bits 7 to 2—Reserved: These bits are always read as 0. Writing to these bits is invalid. If a value is written to these bits, it should always be 0. Bit 1—Counter Start 4 (STR4): Specifies whether timer counter 4 (TCNT4) runs or is stopped. Bit 1: STR4 0 1 Description Counting by TCNT4 is stopped Counting by TCNT4 proceeds (Initial value) Bit 0—Counter Start 3 (STR3): Specifies whether timer counter 3 (TCNT3) runs or is stopped. Bit 0: STR3 0 1 Description Counting by TCNT3 is stopped Counting by TCNT3 proceeds (Initial value) Rev.7.00 Oct. 10, 2008 Page 343 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) 12.2.4 Timer Constant Registers (TCOR) The TCOR registers are 32-bit readable/writable registers. There are TCOR registers, one for each channel. When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value. The TCOR registers for channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual reset, but are not initialized and retain their contents in standby mode. The TCOR registers for channels 3 and 4 of the SH7750R are initialized to H'FFFFFFFF by a power-on reset, but are not initialized and retain their contents on a manual reset and in standby mode. Bit: 31 30 29 ············· Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 2 1 0 12.2.5 Timer Counters (TCNT) The TCNT registers are 32-bit readable/writable registers. There are TCNT registers, one for each channel. Each TCNT counts down on the input clock selected by TPSC2–TPSC0 in the timer control register (TCR). When a TCNT counter underflows while counting down, the underflow flag (UNF) is set in the corresponding timer control register (TCR). At the same time, the timer constant register (TCOR) value is set in TCNT, and the count-down operation continues from the set value. Rev.7.00 Oct. 10, 2008 Page 344 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) The TCNT registers for channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual reset, but are not initialized and retain their contents in standby mode. The TCNT registers for channels 3 and 4 of the SH7750R are initialized to H'FFFFFFFF by a power-on reset, but are not initialized and retain their contents on a manual reset and in standby mode. Bit: 31 30 29 ············· Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 2 1 0 When the input clock is the on-chip RTC output clock (RTCCLK) in channels 0 to 2, TCNT counts even in module standby mode (that is, when the clock for the TMU is stopped). When the input clock is the external clock (TCLK) or internal clock (Pck), TCNT contents are retained in standby mode. 12.2.6 Timer Control Registers (TCR) The TCR registers are 16-bit readable/writable registers. There are five TCR registers, one for each channel. Each TCR selects the count clock, specifies the edge when an external clock is selected in channels 0 to 2, and controls interrupt generation when the flag indicating timer counter (TCNT) underflow is set to 1. TCR2 is also used for channel 2 input capture control, and control of interrupt generation in the event of input capture. The TCR registers for channels 0 to 2 are initialized to H'0000 by a power-on or manual reset, but are not initialized and retain their contents in standby mode. The TCR registers for channels 3 and 4 of the SH7750R are initialized to H'0000 by a power-on reset, but are not initialized and retain their contents on a manual reset and in standby mode. Rev.7.00 Oct. 10, 2008 Page 345 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) 1. Channel 0 and 1 TCR bit configuration Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 UNIE 0 R/W 12 — 0 R 4 CKEG1 0 R/W 11 — 0 R 3 CKEG0 0 R/W 10 — 0 R 2 TPSC2 0 R/W 9 — 0 R 1 TPSC1 0 R/W 8 UNF 0 R/W 0 TPSC0 0 R/W 2. Channel 2 TCR bit configuration Bit: 15 — Initial value: R/W: Bit: 0 R 7 ICPE1 Initial value: R/W: 0 R/W 14 — 0 R 6 ICPE0 0 R/W 13 — 0 R 5 UNIE 0 R/W 12 — 0 R 4 CKEG1 0 R/W 11 — 0 R 3 CKEG0 0 R/W 10 — 0 R 2 TPSC2 0 R/W 9 ICPF 0 R/W 1 TPSC1 0 R/W 8 UNF 0 R/W 0 TPSC0 0 R/W Rev.7.00 Oct. 10, 2008 Page 346 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) 3. TCR bit configuration for channels 3 and 4 (SH7750R only) Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 UNIE 0 R/W 12 — 0 R 4 — 0 R 11 — 0 R 3 — 0 R 10 — 0 R 2 TPSC2 0 R/W 9 — 0 R 1 TPSC1 0 R/W 8 UNF 0 R/W 0 TPSC0 0 R/W Bits 15 to 9, 7, and 6 (Channels 0 and 1); Bits 15 to 10 (Channel 2)—Reserved: These bits are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit 9—Input Capture Interrupt Flag (ICPF) (Channel 2 Only): Status flag, provided in channel 2 only, that indicates the occurrence of input capture. Bit 9: ICPF 0 Description Input capture has not occurred [Clearing condition] When 0 is written to ICPF 1 Input capture has occurred [Setting condition] When input capture occurs* Note: * Writing 1 does not change the value. (Initial value) Rev.7.00 Oct. 10, 2008 Page 347 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) Bit 8—Underflow Flag (UNF): Status flag that indicates the occurrence of underflow. Bit 8: UNF 0 Description TCNT has not underflowed [Clearing condition] When 0 is written to UNF 1 TCNT has underflowed [Setting condition] When TCNT underflows* Note: * Writing 1 does not change the value. (Initial value) Bits 7 and 6—Input Capture Control (ICPE1, ICPE0) (Channel 2 Only): These bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used. When the input capture function is used, a data transfer request is sent to the DMAC in the event of input capture. When using the input capture function, the TCLK pin must be designated as an input pin with the TCOE bit in the TOCR register. The CKEG bits specify whether the rising edge or falling edge of the TCLK signal is used to set the TCNT2 value in the input capture register (TCPR2). The TCNT2 value is set in TCPR2 only when the TCR2.ICPF bit is 0. When the TCR2.ICPF bit is 1, TCPR2 is not set in the event of input capture. When input capture occurs, a DMAC transfer request is generated regardless of the value of the TCR2.ICPF bit. However, a new DMAC transfer request is not generated until processing of the previous request is finished. Bit 7: ICPE1 0 Bit 6: ICPE0 0 1 1 0 Description Input capture function is not used Reserved (Do not set) Input capture function is used, but interrupt due to input capture (TICPI2) is not enabled Data transfer request is sent to DMAC in the event of input capture 1 Input capture function is used, and interrupt due to input capture (TICPI2) is enabled Data transfer request is sent to DMAC in the event of input capture (Initial value) Rev.7.00 Oct. 10, 2008 Page 348 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) Bit 5—Underflow Interrupt Control (UNIE): Controls enabling or disabling of interrupt generation when the UNF status flag is set to 1, indicating TCNT underflow. Bit 5: UNIE 0 1 Description Interrupt due to underflow (TUNI) is not enabled Interrupt due to underflow (TUNI) is enabled (Initial value) Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the external clock input edge when an external clock is selected or the input capture function is used in channels 0 to 2. Bit 4: CKEG1 0 Bit 3: CKEG0 0 1 1 X Note: X: 0 or 1 (don't care) Description Count/input capture register set on rising edge Count/input capture register set on falling edge Count/input capture register set on both rising and falling edges (Initial value) Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2–TPSC0): These bits select the TCNT count clock. With channels 0 to 2, when the on-chip RTC output clock is selected as the count clock for a channel, that channel can operate even in module standby mode. When another clock is selected, the channel does not operate in standby mode. Bit 2: TPSC2 0 Bit 1: TPSC1 0 Bit 0: TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Counts on Pck/4 Counts on Pck/16 Counts on Pck/64 Counts on Pck/256 Counts on Pck/1024 Reserved (Do not set) Counts on on-chip RTC output clock (Do not set this pattern for channel 3 or 4) Counts on external clock (Do not set this pattern for channel 3 or 4) (Initial value) Rev.7.00 Oct. 10, 2008 Page 349 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) 12.2.7 Input Capture Register 2 (TCPR2) TCPR2 is a 32-bit read-only register for use with the input capture function, provided only in channel 2. The input capture function is controlled by means of the input capture control bits (ICPE) and clock edge bits (CKEG) in TCR2. When input capture occurs, the TCNT2 value is copied into TCPR2. The value is set in TCPR2 only when the ICPF bit in TCR2 is 0. TCPR2 is not initialized by a power-on or manual reset, or in standby mode. Bit: 31 30 29 ············· Initial value: R/W: R R R Undefined R R R 2 1 0 12.3 Operation Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32bit timer constant register (TCOR). The channels have an auto-reload function that allows cyclic count operations, and can also perform external event counting. Channel 2 also has an input capture function. 12.3.1 Counter Operation When one of bits STR0–STR4 is set to 1 in the timer start register (TSTR, TSTR2), the timer counter (TCNT) for the corresponding channel starts counting. When TCNT underflows, the UNF flag is set in the corresponding timer control register (TCR). If the UNIE bit in TCR is set to 1 at this time, an interrupt request is sent to the CPU. At the same time, the value is copied from TCOR into TCNT, and the count-down continues (auto-reload function). Rev.7.00 Oct. 10, 2008 Page 350 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) Example of Count Operation Setting Procedure: Figure 12.2 shows an example of the count operation setting procedure. 1. Select the count clock, for channel 0, 1, or 2, with bits TPSC2–TPSC0 in the timer control register (TCR). When an external clock is selected, set the TCLK pin to input mode with the TCOE bit in TOCR, and select the external clock edge with bits CKEG1 and CKEG0 in TCR. 2. Specify whether an interrupt is to be generated on TCNT underflow with the UNIE bit in TCR. 3. When the input capture function is used, set the ICPE bits in TCR, including specification of whether the interrupt function is to be used. 4. Set a value in the timer constant register (TCOR). 5. Set the initial value in the timer counter (TCNT). 6. Set the STR bit to 1 in the timer start register (TSTR, TSTR2) to start the count. Operation selection Select count clock 1 Underflow interrupt generation setting 2 When input capture function is used Input capture interrupt generation setting 3 Timer constant register setting Set initial timer counter value 4 5 Start count 6 Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt enabled state is set without clearing the flag, another interrupt will be generated. Figure 12.2 Example of Count Operation Setting Procedure Rev.7.00 Oct. 10, 2008 Page 351 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) Auto-Reload Count Operation: Figure 12.3 shows the TCNT auto-reload operation. TCNT value TCOR TCOR value set in TCNT on underflow H'00000000 STR0–STR2 Time UNF Figure 12.3 TCNT Auto-Reload Operation TCNT Count Timing: • Operating on internal clock Any of five count clocks (Pck/4, Pck/16, Pck/64, Pck/256, or Pck/1024) scaled from the peripheral module clock can be selected as the count clock by means of the TPSC2–TPSC0 bits in TCR. Figure 12.4 shows the timing in this case. Pck Internal clock TCNT N+1 N N–1 Figure 12.4 Count Timing when Operating on Internal Clock Rev.7.00 Oct. 10, 2008 Page 352 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) • Operating on external clock For channels 0 to 2, external clock pin (TCLK) input can be selected as the timer clock by means of the TPSC2–TPSC0 bits in TCR. The rising edge, falling edge, or both edges can be selected as the detected edge of the external clock with the CKEG1 and CKEG0 bits in TCR. Figure 12.5 shows the timing for both-edge detection. Pck External clock input pin TCNT N+1 N N–1 Figure 12.5 Count Timing when Operating on External Clock • Operating on on-chip RTC output clock The on-chip RTC output clock can be selected as the timer clock in channels 0 to 2 by means of the TPSC2–TPSC0 bits in TCR. Figure 12.6 shows the timing in this case. RTC output clock TCNT N+1 N N–1 Figure 12.6 Count Timing when Operating on On-Chip RTC Output Clock 12.3.2 Input Capture Function Channel 2 has an input capture function. The procedure for using the input capture function is as follows: 1. Use the TCOE bit in the timer output control register (TOCR) to set the TCLK pin to input mode. 2. Use bits TPSC2–TPSC0 in the timer control register (TCR) to set an internal clock or the onchip RTC output clock as the timer operating clock. Rev.7.00 Oct. 10, 2008 Page 353 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) 3. Use bits IPCE1 and IPCE0 in TCR to specify use of the input capture function, and whether interrupts are to generated when this function is used. 4. Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the TCLK signal is to be used to set the timer counter (TCNT) value in the input capture register (TCPR2). This function cannot be used in standby mode. When input capture occurs, the TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is 0. Also, a new DMAC transfer request is not generated until processing of the previous request is finished. Figure 12.7 shows the operation timing when the input capture function is used (with TCLK rising edge detection). TCOR value set in TCNT on underflow TCNT value TCOR H'00000000 TCLK Time TCPR2 TCNT value set TICPI2 Figure 12.7 Operation Timing when Using Input Capture Function Rev.7.00 Oct. 10, 2008 Page 354 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) 12.4 Interrupts There are four TMU interrupt sources, comprising underflow interrupts and the input capture interrupt (when the input capture function is used). Underflow interrupts are generated on each of the channels, and input capture interrupts on channel 2 only. An underflow interrupt request is generated (for each channel) when the UNF bit in TCR is 1 and the interrupt enable bit for the corresponding channel is 1. When the input capture function is used and an input capture request is generated, an interrupt is requested if the input capture input flag (ICPF) in TCR2 is 1 and the input capture control bits (ICPE1, ICPE0) in TCR2 are 11. The TMU interrupt sources are summarized in table 12.3. Table 12.3 TMU Interrupt Sources Channel 0 1 2 Interrupt Source TUNI0 TUNI1 TUNI2 TICPI2 3* 4* Note: * TUNI3 TUNI4 SH7750R only Description Underflow interrupt 0 Underflow interrupt 1 Underflow interrupt 2 Input capture interrupt 2 Underflow interrupt 3 Underflow interrupt 4 Low Priority High 12.5 12.5.1 Usage Notes Register Writes When performing a register write, timer count operation must be stopped by clearing the start bit (STR0–STR4) for the relevant channel in the timer start register (TSTR, TSTR2). Note that the timer start register (TSTR, TSTR2) can be written to, and the underflow flag (UNF) and input capture flag (ICPF) of the timer control registers (TRCR0 to TCR4) can be cleared while the count is in progress. When the flags (UNF, ICPF) are cleared while the count is in progress, make sure not to change the values of bits other than those being cleared. Rev.7.00 Oct. 10, 2008 Page 355 of 1074 REJ09B0366-0700 Section 12 Timer Unit (TMU) 12.5.2 Underflow Flag Writes (SH7750 only) If 1 is written to the UNF bit in TCR when the UNF bit is already set to 1, the UNF bit may be cleared to 0. The following workarounds can be used to avoid this problem. 1. Stopping channel counter operation Use steps (i) to (iii) below to write 1 to UNF. (i) Stop counter operation for the channel used to write to UNF. (ii) Disable the DMAC channels used to access peripheral modules. (iii) While SR.BL is set to 1, write (the same value as that written to TCR and using the same access size (word)) to address H'FFD80080, then write 1 to UNF with the next instruction. 2. Not stopping channel counter operation Make sure to write 0 to UNF. If it is necessary to monitor for underflows, use software to read TCNT before and after writing to UNF and determine if an underflow has occurred. 12.5.3 TCNT Register Reads When performing a TCNT register read, processing for synchronization with the timer count operation is performed. If a timer count operation and register read processing are performed simultaneously, the TCNT counter value prior to the count-down operation is read by means of the synchronization processing. 12.5.4 Resetting the RTC Frequency Divider When the on-chip RTC output clock is selected as the count clock, the RTC frequency divider should be reset. 12.5.5 External Clock Frequency Ensure that the external clock frequency for any channel does not exceed Pck/8. Rev.7.00 Oct. 10, 2008 Page 356 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Section 13 Bus State Controller (BSC) 13.1 Overview The functions of the bus state controller (BSC) include division of the external memory space, and output of control signals in accordance with various types of memory and bus interface specifications. The BSC functions allow DRAM, synchronous DRAM, SRAM, ROM, etc., to be connected to this LSI, and also support the PCMCIA interface protocol, enabling system design to be simplified and data transfers to be carried out at high speed by a compact system. 13.1.1 Features The BSC has the following features: • External memory space is managed as 7 independent areas ⎯ Maximum 64 Mbytes for each of areas 0 to 6 ⎯ Bus width of each area can be set in a register (except area 0, which uses an external pin setting) ⎯ Wait state insertion by RDY pin ⎯ Wait state insertion can be controlled by program ⎯ Specification of types of memory connectable to each area ⎯ Output the control signals of memory to each area ⎯ Automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory accesses to different areas, or a read access followed by a write access to the same area ⎯ Write strobe setup time and hold time periods can be inserted in a write cycle to enable connection to low-speed memory • SRAM interface ⎯ Wait state insertion can be controlled by program ⎯ Wait state insertion by RDY pin Connectable areas: 0 to 6 Settable bus widths: 64, 32, 16, 8 • DRAM interface ⎯ Row address/column address multiplexing according to DRAM capacity ⎯ Burst operation (fast page mode, EDO mode) ⎯ CAS-before-RAS refresh and self-refresh Rev.7.00 Oct. 10, 2008 Page 357 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) • • • • • • • ⎯ 8-CAS byte control for power-down operation ⎯ DRAM control signal timing can be controlled by register settings ⎯ Consecutive accesses to the same row address Connectable areas: 2, 3 Settable bus widths: 64, 32, 16 Synchronous DRAM interface ⎯ Row address/column address multiplexing according to synchronous DRAM capacity ⎯ Burst operation ⎯ Auto-refresh and self-refresh ⎯ Synchronous DRAM control signal timing can be controlled by register settings ⎯ Consecutive accesses to the same row address Connectable areas: 2, 3 Settable bus widths: 64, 32 Burst ROM interface ⎯ Wait state insertion can be controlled by program ⎯ Burst operation, executing the number of transfers set in a register Connectable areas: 0, 5, 6 Settable bus widths: 64*, 32, 16, 8 MPX interface ⎯ Address/data multiplexing Connectable areas: 0 to 6 Settable bus widths: 64, 32 Byte control SRAM interface ⎯ SRAM interface with byte control Connectable areas: 1, 4 Settable bus widths: 64, 32, 16 PCMCIA interface ⎯ Wait state insertion can be controlled by program ⎯ Bus sizing function for I/O bus width Fine refreshing control ⎯ Supports refresh operation immediately after self-refresh operation in low-power DRAM by means of refresh counter overflow interrupt function Refresh counter can be used as interval timer ⎯ Interrupt request generated by compare-match ⎯ Interrupt request generated by refresh counter overflow Rev.7.00 Oct. 10, 2008 Page 358 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Note: * SH7750R only 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the BSC. Bus interface WCR1 RDY Wait control unit WCR2 WCR3 CS6–CS0 CE2A–CE2B BS RD/FRAME RD/WR WE7–WE0 RAS CAS7–CAS0, CASS CKE ICIORD, ICIOWR REG IOIS16 Area control unit BCR1 BCR2 BCR3* BCR4* Memory control unit MCR PCR RFCR Peripheral bus RTCNT Refresh control unit Comparator Interrupt controller RTCOR RTCSR BSC Legend: WCR: Wait control register BCR: Bus control register MCR: Memory control register PCR: PCMCIA control register Note: * SH7750R only RFCR: RTCNT: RTCOR: RTCSR: Refresh count register Refresh timer count register Refresh time constant register Refresh timer control/status register Figure 13.1 Block Diagram of BSC Rev.7.00 Oct. 10, 2008 Page 359 of 1074 REJ09B0366-0700 Module bus Internal bus Section 13 Bus State Controller (BSC) 13.1.3 Pin Configuration Table 13.1 shows the BSC pin configuration. Table 13.1 BSC Pins Name Address bus Data bus Signals A25−A0 D63−D52, D31−D0 I/O O I/O Description Address output Data input/output When port functions are used and DDT mode is selected, input the DTR format. Otherwise, when port functions are used, D63−D52 cannot be used and should be left open. I/O When port functions are not used: data input/output When port functions are used: input/output port (input or output set for each bit by register) O Signal that indicates the start of a bus cycle When setting synchronous DRAM interface: asserted once for a burst transfer For other burst transfers: asserted each data cycle Chip select 6−0 CS6−CS0 O Chip select signals that indicate the area being accessed CS5 and CS6 are also used as PCMCIA CE1A and CE1B Read/write RD/WR O Data bus input/output direction designation signal Also used as the DRAM/synchronous DRAM/PCMCIA interface write designation signal Row address strobe Read/column address strobe/ cycle frame RAS RD/CASS/ FRAME O O RAS signal when setting DRAM/synchronous DRAM interface Strobe signal that indicates a read cycle When setting synchronous DRAM interface: CAS signal When setting MPX interface: FRAME signal Data bus/port D51−D32/ PORT19− PORT0 BS Bus cycle start Rev.7.00 Oct. 10, 2008 Page 360 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Name Data enable 0 Signals WE0/CAS0/ DQM0 I/O O Description When setting synchronous DRAM interface: selection signal for D7–D0 When setting DRAM interface: CAS signal for D7–D0 When setting MPX interface: high-level output In other cases: write strobe signal for D7–D0 Data enable 1 WE1/CAS1/ DQM1 O When setting synchronous DRAM interface: selection signal for D15–D8 When setting DRAM interface: CAS signal for D15–D8 When setting PCMCIA interface: write strobe signal When setting MPX interface: high-level output In other cases: write strobe signal for D15–D8 Data enable 2 WE2/CAS2/ DQM2/ICIORD O When setting synchronous DRAM interface: selection signal for D23–D16 When setting DRAM interface: CAS signal for D23–D16 When setting PCMCIA interface: ICIORD signal When setting MPX interface: high-level output In other cases: write strobe signal for D23–D16 Data enable 3 WE3/CAS3/ O DQM3/ICIOWR When setting synchronous DRAM interface: selection signal for D31–D24 When setting DRAM interface: CAS signal for D31–D24 When setting PCMCIA interface: ICIOWR signal When setting MPX interface: high-level output In other cases: write strobe signal for D31–D24 Data enable 4 WE4/CAS4/ DQM4 O When setting synchronous DRAM interface: selection signal for D39–D32 When setting DRAM interface: CAS signal for D39–D32 When setting MPX interface: high-level output In other cases: write strobe signal for D39–D32 Rev.7.00 Oct. 10, 2008 Page 361 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Name Data enable 5 Signals WE5/CAS5/ DQM5 I/O O Description When setting synchronous DRAM interface: selection signal for D47–D40 When setting DRAM interface: CAS signal for D47–D40 When setting MPX interface: high-level output In other cases: write strobe signal for D47–D40 Data enable 6 WE6/CAS6/ DQM6 O When setting synchronous DRAM interface: selection signal for D55–D48 When setting DRAM interface: CAS signal for D55–D48 When setting MPX interface: high-level output In other cases: write strobe signal for D55–D48 Data enable 7 WE7/CAS7/ DQM7/REG O When setting synchronous DRAM interface: selection signal for D63–D56 When setting DRAM interface: CAS signal for D63–D56 When setting PCMCIA interface: REG signal When setting MPX interface: high-level output In other cases: write strobe signal for D63–D56 Ready Area 0 MPX interface specification/ 16-bit I/O Clock enable Bus release request Bus use permission Area 0 bus width/PCMCIA card select RDY MD6/IOIS16 I I Wait state request signal In power-on reset: Designates area 0 bus as MPX interface (1: SRAM, 0: MPX) When setting PCMCIA interface: 16-bit I/O designation signal. Valid only in little-endian mode. CKE BREQ/ BSACK BACK/ BSREQ MD3/CE2A*1 MD4/CE2B* 2 O I O I/O Synchronous DRAM clock enable control signal Bus release request signal/bus acknowledge signal Bus use permission signal/bus request In power-on reset*4: external space area 0 bus width specification signal When setting PCMCIA interface: CE2A, CE2B Endian specification in a power-on reset.*4 RAS2 when DRAM is connected to area 2 Endian switchover/ MD5/RAS2*3 row address strobe I/O Rev.7.00 Oct. 10, 2008 Page 362 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Name Master/slave switchover DMAC0 acknowledge signal DMAC1 acknowledge signal Read/column address strobe/ cycle frame 2 Read/write 2 Signals MD7/TXD DACK0 I/O I/O O Description Indicates master/slave status in a power-on reset.* Serial interface TXD DMAC channel 0 data acknowledge 4 DACK1 O DMAC channel 1 data acknowledge RD2 O Same signal as RD/CASS/FRAME This signal is used when the RD/CASS/FRAME signal load is heavy. RD/WR2 O Same signal as RD/WR This signal is used when the RD/WR signal load is heavy. Notes: 1. MD3/CE2A input/output switching is performed by BCR1.A56PCM. Output is selected when BCR1.A56PCM = 1. 2. MD4/CE2B input/output switching is performed by BCR1.A56PCM. Output is selected when BCR1.A56PCM = 1. 3. MD5/RAS2 input/output switching is performed by BCR1.DRAMTP. Output is selected when BCR1.DRAMTP (2–0) = 101. 4. In a power-on reset by means of the RESET pin. Rev.7.00 Oct. 10, 2008 Page 363 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.1.4 Register Configuration The BSC has the 11 registers shown in table 13.2. In addition, the synchronous DRAM mode register incorporated in synchronous DRAM can also be accessed as this LSI's register. The functions of these registers include control of interfaces to various types of memory, wait states, and refreshing. Table 13.2 BSC Registers Name Bus control register 1 Bus control register 2 Bus control register 3* Bus control register 4* Wait state control register 1 Wait state control register 2 Wait state control register 3 2 2 Abbrevia- R/W tion BCR1 BCR2 BCR3 BCR4 WCR1 WCR2 WCR3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Initial Value P4 Address Area 7 Address Access Size H'0000 0000 H'FF80 0000 H'1F80 0000 32 H'3FFC H'0000 H'FF80 0004 H'1F80 0004 16 H'FF80 0050 H'1F80 0050 16 H'0000 0000 H'FE0A 00F0 H'1E0A 00F0 32 H'7777 7777 H'FF80 0008 H'1F80 0008 32 H'FFFE EFFF H'FF80 000C H'1F80 000C 32 H'0777 7777 H'FF80 0010 H'1F80 0010 32 H'0000 0000 H'FF80 0014 H'1F80 0014 32 H'0000 H'0000 H'0000 H'0000 H'0000 — H'FF80 0018 H'1F80 0018 16 H'FF80 001C H'1F80 001C 16 H'FF80 0020 H'1F80 0020 16 H'FF80 0024 H'1F80 0024 16 H'FF80 0028 H'1F80 0028 16 H'FF90 xxxx*1 H'1F90 xxxx 1 H'FF94 xxxx* H'1F94 xxxx Memory control register MCR PCMCIA control register PCR Refresh timer control/status register Refresh timer counter Refresh time constant counter Refresh count register Synchronous DRAM mode registers For area 2 For area 3 RTCSR RTCNT RTCOR RFCR SDMR2 SDMR3 8 Notes: 1. For details, see section 13.2.10, Synchronous DRAM Mode Register (SDMR). 2. Settable only for SH7750R. Rev.7.00 Oct. 10, 2008 Page 364 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.1.5 Overview of Areas Space Divisions: The architecture of this LSI provides a 32-bit virtual address space. The virtual address is divided into five areas according to the upper address value. External memory space comprises a 29-bit address space, divided into eight areas. The virtual address can be allocated to any external address by means of the memory management unit (MMU). Details are given in section 3, Memory Management Unit (MMU). This section describes the areas into which the external address is divided. With this LSI, various kinds of memory or PC cards can be connected to the seven areas of external address as shown in table 13.3, and chip select signals (CS0–CS6, CE2A, CE2B) are output for each of these areas. CS0 is asserted when accessing area 0, and CS6 when accessing area 6. When DRAM or synchronous DRAM is connected to area 2 or 3, signals such as RAS, CAS, RD/WR, and DQM are also asserted. When the PCMCIA interface is selected for area 5 or 6, CE2A, CE2B is asserted in addition to CS5, CS6 for the byte to be accessed. 256 H'0000 0000 Area 0 (CS0) Area 1 (CS1) P0 and U0 areas P0 and U0 areas Area 2 (CS2) Area 3 (CS3) Area 4 (CS4) H'8000 0000 P1 area H'A000 0000 H'C000 0000 P2 area P3 area P1 area P2 area P3 area Store queue area P4 area Area 5 (CS5) Area 6 (CS6) Area 7 (reserved area) H'0000 0000 H'0400 0000 H'0800 0000 H'0C00 0000 H'1000 0000 H'1400 0000 H'1800 0000 H'1C00 0000 H'1FFF FFFF H'E000 0000 Store queue area H'E400 0000 P4 area H'FFFF FFFF Physical address space (MMU off) Virtual address space (MMU on) External memory space Notes: 1. When the MMU is off (MMUCR.AT = 0), the top 3 bits of the 32-bit address are ignored, and memory is mapped onto a fixed 29-bit external address. 2. When the MMU is on (MMUCR.AT = 1), the P0, U0, P3, and store queue areas can be mapped onto any external address using the TLB. For details, see section 3, Memory Management Unit (MMU). Figure 13.2 Correspondence between Virtual Address Space and External Memory Space Rev.7.00 Oct. 10, 2008 Page 365 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.3 External Memory Space Map Area 0 External Addresses H'00000000– H'03FFFFFF H'04000000– H'07FFFFFF H'08000000– H'0BFFFFFF Size 64 Mbytes Connectable Memory SRAM Burst ROM MPX SRAM MPX Byte control SRAM 64 Mbytes SRAM Synchronous DRAM DRAM MPX SRAM Synchronous DRAM DRAM MPX SRAM MPX Byte control RAM SRAM MPX Burst ROM PCMCIA SRAM MPX Burst ROM PCMCIA — Settable Bus Widths 8, 16, 32, 64*1 8, 16, 32*1, 64*7 32, 64*1 8, 16, 32, 64*2 2 32, 64* 16, 32, 64*2 8, 16, 32, 64*2 32, 64*2 *3 16, 32*2 *3 32, 64*2 8, 16, 32, 64*2 32, 64*2 *3 16, 32, 64*2 *3 32, 64*2 8, 16, 32, 64*2 32, 64*2 16, 32, 64*2 8, 16, 32, 64*2 32, 64*2 8, 16, 32*2, 64*7 8, 16*2 *4 8, 16, 32, 64*2 32, 64*2 8,16, 32*2, 64*7 8,16*2 *4 — Access Size 8, 16, 32, 6 64* bits, 32 bytes 8, 16, 32, 64*6 bits, 32 bytes 8, 16, 32, 64*6 bits, 32 bytes 1 64 Mbytes 2 3 H'0C000000– H'0FFFFFFF 64 Mbytes 8, 16, 32, 64*6 bits, 32 bytes 4 H'10000000– H'13FFFFFF H'14000000– H'17FFFFFF 64 Mbytes 8, 16, 32, 64*6 bits, 32 bytes 8, 16, 32, 64*6 bits, 32 bytes 5 64 Mbytes 6 H'18000000– H'1BFFFFFF 64 Mbytes 8, 16, 32, 64*6 bits, 32 bytes 7*5 H'1C000000– H'1FFFFFFF 64 Mbytes Notes: 1. Memory bus width specified by external pins 2. Memory bus width specified by register 3. With synchronous DRAM interface, bus width is 32 or 64 bits only. With DRAM interface, bus width is 16 or 32 bits only for area 2, and 16, 32, or 64 bits only for area 3. Bus width of area 2 is as same as that of area 3 which is specified by MCR. 4. With PCMCIA interface, bus width is 8 or 16 bits only. 5. Do not access a reserved area, as operation cannot be guaranteed in this case. Rev.7.00 Oct. 10, 2008 Page 366 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 6. 64-bit access applies only to transfer by the DMAC. (CHCRn. TS = 000) In a transfer to an external memory by FMOV (FPSCR.SZ = 1), two transfer operations, each with an access size of 32 bits, are conducted. 7. Settable only for SH7750R. Area 0: H'00000000 Area 1: H'04000000 Area 2: H'08000000 Area 3: H'0C000000 Area 4: H'10000000 Area 5: H'14000000 Area 6: H'18000000 SRAM/burst ROM/MPX SRAM/MPX/byte control SRAM SRAM/synchronous DRAM/DRAM/ MPX SRAM/synchronous DRAM/DRAM/ MPX SRAM/MPX/byte control SRAM SRAM/burst ROM/PCMCIA/MPX SRAM/burst ROM/PCMCIA/MPX The PCMCIA interface is for memory and I/O card use Figure 13.3 External Memory Space Allocation Memory Bus Width: In this LSI, the memory bus width can be set independently for each space. For area 0, a bus size of 8, 16, 32, or 64 bits can be selected in a power-on reset by the RESET pin, using external pins. The relationship between the external pins (MD4 and MD3) and the bus width in a power-on reset is shown below. MD4 0 MD3 0 1 1 0 1 Bus Width 64 bits 8 bits 16 bits 32 bits When SRAM interface or ROM is used in areas 1 to 6, a bus width of 8, 16, 32, or 64 bits can be selected with bus control register 2 (BCR2). When burst ROM is used, a bus width of 8, 16, 32, or 64* bits can be selected. When byte control SRAM interface is used, a bus width of 16, 32, or 64 bits can be selected. When the MPX interface is used, a bus width of 32 or 64 bits can be selected. When the DRAM interface is used, a bus width of 16, 32, or 64 bits can be selected with the Rev.7.00 Oct. 10, 2008 Page 367 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) memory control register (MCR). When the DRAM interface is used for area 2 or 3, a bus width of 16 or 32 bits should be set. For the synchronous DRAM interface, set a bus width of 32 or 64 bits in the MCR register. When using the PCMCIA interface, set a bus width of 8 or 16 bits. For details, see section 13.3.7, PCMCIA Interface. When using port functions, set a bus width of 8, 16, or 32 bits for all areas. For details, see section 13.2.2, Bus Control Register 2 (BCR2), and section 13.2.8, Memory Control Register (MCR). The area 7 address range, H'1C000000 to H'1FFFFFFFF, is a reserved space and must not be used. Note: * SH7750R only 13.1.6 PCMCIA Support This LSI supports PCMCIA compliant interface specifications for external memory space areas 5 and 6. The interfaces supported are the IC memory card interface and I/O card interface stipulated in JEIDA specifications version 4.2 (PCMCIA2.1). External memory space areas 5 and 6 support both the IC memory card interface and the I/O card interface. The PCMCIA interface is supported only in little-endian mode. Table 13.4 PCMCIA Interface Features Item Access Data bus Memory type Common memory capacity Attribute memory capacity Others Features Random access 8/16 bits Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM Max. 64 Mbytes Max. 64 Mbytes Dynamic bus sizing for I/O bus width, access to PCMCIA interface from address translation areas Rev.7.00 Oct. 10, 2008 Page 368 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.5 PCMCIA Support Interfaces IC Memory Card Interface Signal Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE/PGM RDY/BSY VCC VPP1 I/O Function Ground I/O Data I/O Data I/O Data I/O Data I/O Data I I I I I I I I I O Card enable Address Output enable Address Address Address Address Address Write enable Ready/busy Operating power supply Programming power supply I I I I I I I I I Address Address Address Address Address Address Address Address Address Signal Name GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE/PGM IREQ VCC VPP1 I/O Card Interface I/O Function Ground I/O Data I/O Data I/O Data I/O Data I/O Data I I I I I I I I I O Card enable Address Output enable Address Address Address Address Address Write enable Interrupt request Operating power supply Programming/ peripheral power supply I I I I I I I I I Address Address Address Address Address Address Address Address Address Corresponding LSI Pin — D3 D4 D5 D6 D7 CS5 or CS6 A10 RD A11 A9 A8 A13 A14 WE1 Sensed on port — — 19 20 21 22 23 24 25 26 27 A16 A15 A12 A7 A6 A5 A4 A3 A2 A16 A15 A12 A7 A6 A5 A4 A3 A2 A16 A15 A12 A7 A6 A5 A4 A3 A2 Rev.7.00 Oct. 10, 2008 Page 369 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) IC Memory Card Interface Signal Pin Name 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 A1 A0 D0 D1 D2 WP* GND GND CD1 D11 D12 D13 D14 D15 CE2 RFSH RFU RFU A17 A18 A19 A20 A21 VCC VPP2 I I I I I O I/O Function I I Address Address Signal Name A1 A0 D0 D1 D2 IOIS16 GND GND CD1 D11 D12 D13 D14 D15 CE2 RFSH IORD IOWR A17 A18 A19 A20 A21 VCC VPP2 O I/O Card Interface I/O Function I I Address Address Corresponding LSI Pin A1 A0 D0 D1 D2 IOIS16 — — Sensed on port D11 D12 D13 D14 D15 CE2A or CE2B Output from port ICIORD ICIOWR A17 A18 A19 A20 A21 — — I/O Data I/O Data I/O Data O Write protect Ground Ground Card detection I/O Data I/O Data I/O Data O 16-bit I/O port Ground Ground Card detection I/O Data I/O Data I/O Data I/O Data I/O Data I I Card enable Refresh request Reserved Reserved Address Address Address Address Address Power supply Programming power supply I I I Address Address Address I/O Data I/O Data I/O Data I/O Data I/O Data I I I I I I I I I Card enable Refresh request I/O read I/O write Address Address Address Address Address Power supply Programming/ peripheral power supply I I I Address Address Address 53 54 55 A22 A23 A24 A22 A23 A24 A22 A23 A24 Rev.7.00 Oct. 10, 2008 Page 370 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) IC Memory Card Interface Signal Pin Name 56 57 58 59 60 61 62 63 64 65 66 67 68 Note: A25 RFU RESET WAIT RFU REG BVD2 BVD1 D8 D9 D10 CD2 GND I O O I O I/O Function I Address Reserved Reset Wait request Reserved Attribute memory space select Battery voltage detection Battery voltage detection Signal Name A25 RFU RESET WAIT INPACK REG SPKR STSCHG D8 D9 D10 CD2 GND I O O I O O I/O Card Interface I/O Function I Address Reserved Reset Wait request Input acknowledge Attribute memory space select Digital speech signal Card status change Corresponding LSI Pin A25 — Output from port RDY*2 — WE7 Sensed on port Sensed on port D8 D9 D10 Sensed on port — I/O Data I/O Data I/O Data O Card detection Ground I/O Data I/O Data I/O Data O Card detection Ground 1. WP is not supported. 2. Input an external wait request with correct polarity. Rev.7.00 Oct. 10, 2008 Page 371 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.2 13.2.1 Register Descriptions Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 32-bit readable/writable register that specifies the function, bus cycle status, etc., of each area. BCR1 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. External memory space other than area 0 should not be accessed until register initialization is completed. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 ENDIAN 1 0/1* 30 MASTER 29 A0MPX 28 — 0 R 20 A4MBC 0 R/W 12 A0BST1 27 — 0 R 19 BREQEN 26 DPUP*2 0 R/W 18 PSHR 0 R/W 10 A5BST2 25 IPUP 0 R/W 17 0 R/W 9 A5BST1 24 OPUP 0 R/W 16 2 0/1*1 R 22 — 0 R 14 HIZCNT 0/1*1 R 21 A1MBC 0 R/W 13 A0BST2 R 23 — 0 R 15 HIZMEM MEMMPX DMABST* 0 R/W 11 A0BST0 0 R 8 A5BST0 0 R/W 7 A6BST2 0 R/W 6 A6BST1 0 R/W 5 A6BST0 0 R/W 4 0 R/W 0 R/W 3 0 R/W 0 R/W 2 0 R/W 0 R/W 1 — 0 R/W 0 A56PCM DRAMTP2 DRAMTP1 DRAMTP0 0 R/W 0 R/W 0 R/W 0 R 0 R/W Notes: 1. These bits sample external pin values in a power-on reset by means of the RESET pin. 2. SH7750R only. Rev.7.00 Oct. 10, 2008 Page 372 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bit 31—Endian Flag (ENDIAN): Samples the value of the endian specification external pin (MD5) in a power-on reset by the RESET pin. The endian mode of all spaces is determined by this bit. ENDIAN is a read-only bit. Bit 31: ENDIAN 0 1 Description In a power-on reset, the endian setting external pin (MD5) is low, designating big-endian mode In a power-on reset, the endian setting external pin (MD5) is high, designating little-endian mode Bit 30—Master/Slave Flag (MASTER): Samples the value of the master/slave specification external pin (MD7) in a power-on reset by the RESET pin. The master/slave status of all spaces is determined by this bit. MASTER is a read-only bit. Bit 30: MASTER 0 1 Description In a power-on reset, the master/slave setting external pin (MD7) is high, designating master mode In a power-on reset, the master/slave setting external pin (MD7) is low, designating slave mode Bit 29—Area 0 Memory Type (A0MPX): Samples the value of the area 0 memory type specification external pin (MD6) in a power-on reset by the RESET pin. The memory type of area 0 is determined by this bit. A0MPX is a read-only bit. Bit 29: A0MPX 0 1 Description In a power-on reset, the external pin specifying the area 0 memory type (MD6) is high, designating the area 0 as SRAM interface In a power-on reset, the external pin specifying the area 0 memory type (MD6) is low, designating the area 0 as MPX interface Bits 28, 27, 26*, 23, 22, 16*, and 1—Reserved: These bits are always read as 0, and should only be written with 0. Note: * SH7750, SH7750S only. Rev.7.00 Oct. 10, 2008 Page 373 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bit 26—Data pin Pullup Resistor Control (DPUP) (SH7750R only): Controls the pullup resistance of the data pins (D63 to D0). It is initialized at a power-on reset. The pins are not pulled up when access is performed or when the bus is released, even if the ON setting is selected. Bit 26: DPUP 0 1 Description Sets pullup resistance of data pins (D63 to D0) ON Sets pullup resistance of data pins (D63 to D0) OFF (Initial value) Bit 25—Control Input Pin Pull-Up Resistor Control (IPUP): Specifies the pull-up resistor status for control input pins (NMI, IRL0–IRL3, BREQ, MD6/IOIS16, RDY). IPUP is initialized by a power-on reset. Bit 25: IPUP 0 1 Description Pull-up resistor is on for control input pins (NMI, IRL0–IRL3, BREQ, MD6/IOIS16, RDY) (Initial value) Pull-up resistor is off for control input pins (NMI, IRL0–IRL3, BREQ, MD6/IOIS16, RDY) Bit 24—Control Output Pin Pull-Up Resistor Control (OPUP): Specifies the pull-up resistor status for control output pins (A[25:0], BS, CSn, RD, WEn, RD/WR, RAS, RAS2, CE2A, CE2B, RD2, RD/WR2) when high-impedance. OPUP is initialized by a power-on reset. Bit 24: OPUP 0 1 Description Pull-up resistor is on for control output pins (A[25:0], BS, CSn, RD, WEn, RD/WR, RAS, RAS2, CE2A, CE2B, RD2, RD/WR2) (Initial value) Pull-up resistor is off for control output pins (A[25:0], BS, CSn, RD, WEn, RD/WR, RAS, RAS2, CE2A, CE2B, RD2, RD/WR2) Bit 21—Area 1 SRAM Byte Control Mode (A1MBC): MPX interface has priority when an MPX interface is set. This bit is initialized by a power-on reset. Bit 21: A1MBC 0 1 Description Area 1 SRAM is set to normal mode Area 1 SRAM is set to byte control mode (Initial value) Rev.7.00 Oct. 10, 2008 Page 374 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bit 20—Area 4 SRAM Byte Control Mode (A4MBC): MPX interface has priority when an MPX interface is set. This bit is initialized by a power-on reset. Bit 20: A4MBC 0 1 Description Area 4 SRAM is set to normal mode Area 4 SRAM is set to byte control mode (Initial value) Bit 19—BREQ Enable (BREQEN): Indicates whether external requests can be accepted. BREQEN is initialized to the external request acceptance disabled state by a power-on reset. It is ignored in the case of a slave mode startup. Bit 19: BREQEN 0 1 Description External requests are not accepted External requests are accepted (Initial value) Bit 18—Partial-Sharing Bit (PSHR): Sets partial-sharing mode. PSHR is valid only in the case of a master mode startup. Bit 18: PSHR 0 1 Description Master mode Partial-sharing mode (Initial value) Bit 17—Area 1 to 6 MPX Interface Specification (MEMMPX): Sets the MPX interface when areas 1 to 6 are set as SRAM interface (or burst ROM interface). MEMMPX is initialized by a power-on reset. Bit 17: MEMMPX 0 1 Description SRAM interface (or burst ROM interface) is selected when areas 1 to 6 are set as SRAM interface (or burst ROM interface) (Initial value) MPX interface is selected when areas 1 to 6 are set as SRAM interface (or burst ROM interface) Rev.7.00 Oct. 10, 2008 Page 375 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bit 16—DMAC Burst Mode Transfer Priority Setting (DMABST) (SH7750R Only): Specifies the priority of burst mode transfers by the DMAC. When OFF, the priority is as follows: bus privilege released, refresh, DMAC, CPU. When ON, the bus privileges are released and refresh operations are not performed until the end of the DMAC's burst transfer. This bit is initialized at a power-on reset. Bit 16: DMABST 0 1 Description DMAC burst mode transfer priority specification OFF DMAC burst mode transfer priority specification ON (Initial value) Bit 15—High Impedance Control (HIZMEM): Specifies the state of address and other signals (A[25:0], BS, CSn, RD/WR, CE2A, CE2B) in software standby mode. Bit 15: HIZMEM 0 Description The A[25:0], BS, CSn, RD/WR, CE2A, and CE2B signals go to highimpedance (High-Z) in standby mode and when the bus is released (Initial value) The A[25:0], BS, CSn, RD/WR, CE2A, and CE2B signals are driven in standby mode. When the bus is released, they go to high-impedance. 1 Bit 14—High Impedance Control (HIZCNT): Specifies the state of the RAS and CAS signals in software standby mode and when the bus is released. Bit 14: HIZCNT 0 Description The RAS, RAS2, WEn/CASn/DQMn, RD/CASS/FRAME, and RD2 signals go to high-impedance (High-Z) in standby mode and when the bus is released (Initial value) The RAS, RAS2, WEn/CASn/DQMn, RD/CASS/FRAME, and RD2 signals are driven in standby mode and when the bus is released 1 Rev.7.00 Oct. 10, 2008 Page 376 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 13 to 11—Area 0 Burst ROM Control (A0BST2–A0BST0): These bits specify whether burst ROM interface is used in area 0. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 0 is an MPX interface area, these bits are ignored. Bit 13: A0BST2 0 Bit 12: A0BST1 0 Bit 11: A0BST0 0 1 Description Area 0 is accessed as SRAM interface (Initial value) Area 0 is accessed as burst ROM interface (4 consecutive accesses) Can be used with 8-, 16-, 32-, or 64*-bit bus width 1 0 Area 0 is accessed as burst ROM interface (8 consecutive accesses) Can only be used with 8-, 16-, or 32-bit bus width 1 Area 0 is accessed as burst ROM interface (16 consecutive accesses) Can only be used with 8- or 16-bit bus width. Do not specify for 32-bit bus width 1 0 0 Area 0 is accessed as burst ROM interface (32 consecutive accesses) Can only be used with 8-bit bus width 1 1 Note: * 0 1 Settable only for SH7750R. Reserved Reserved Reserved Rev.7.00 Oct. 10, 2008 Page 377 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 10 to 8—Area 5 Burst Enable (A5BST2–A5BST0): These bits specify whether burst ROM interface is used in area 5. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 5 is an MPX interface area, these bits are ignored. Bit 10: A5BST2 0 Bit 9: A5BST1 0 Bit 8: A5BST0 0 1 Description Area 5 is accessed as SRAM interface (Initial value) Area 5 is accessed as burst ROM interface (4 consecutive accesses) Can be used with 8-, 16-, 32-, or 64*-bit bus width 1 0 Area 5 is accessed as burst ROM interface (8 consecutive accesses) Can only be used with 8-, 16-, or 32-bit bus width 1 Area 5 is accessed as burst ROM interface (16 consecutive accesses) Can only be used with 8- or 16-bit bus width. Do not specify for 32-bit bus width 1 0 0 Area 5 is accessed as burst ROM interface (32 consecutive accesses) Can only be used with 8-bit bus width 1 1 0 1 Notes: Clear to 0 when PCMCIA interface is set. * Settable only for SH7750R. Reserved Reserved Reserved Rev.7.00 Oct. 10, 2008 Page 378 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 7 to 5—Area 6 Burst Enable (A6BST2–A6BST0): These bits specify whether burst ROM interface is used in area 6. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 6 is an MPX interface area, these bits are ignored. Bit 7: A6BST2 0 Bit 6: A6BST1 0 Bit 5: A6BST0 0 1 Description Area 6 is accessed as SRAM interface (Initial value) Area 6 is accessed as burst ROM interface (4 consecutive accesses) Can be used with 8-, 16-, 32-, or 64*-bit bus width 1 0 Area 6 is accessed as burst ROM interface (8 consecutive accesses) Can only be used with 8-, 16-, or 32-bit bus width 1 Area 6 is accessed as burst ROM interface (16 consecutive accesses) Can only be used with 8- or 16-bit bus width. Do not specify for 32-bit bus width 1 0 0 Area 6 is accessed as burst ROM interface (32 consecutive accesses) Can only be used with 8-bit bus width 1 1 0 1 Notes: Clear to 0 when PCMCIA interface is set. * Settable only for SH7750R. Reserved Reserved Reserved Rev.7.00 Oct. 10, 2008 Page 379 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 4 to 2—Area 2 and 3 Memory Type (DRAMTP2–DRAMTP0): These bits specify the type of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as SRAM interface. DRAM and synchronous DRAM can also be connected. Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description 0 0 0 Areas 2 and 3 are SRAM interface or MPX interface*1 (Initial value) Reserved (Cannot be set) Area 2 is SRAM interface or MPX interface*1, area 3 is synchronous DRAM interface Areas 2 and 3 are synchronous DRAM interface Area 2 is SRAM interface or MPX 1 interface* , area 3 is DRAM interface Areas 2 and 3 are DRAM interface*2 Reserved (Cannot be set) Reserved (Cannot be set) 1 1 0 1 1 0 0 1 1 0 1 Notes: 1. Selection of SRAM interface or MPX interface is determined by the setting of the MEMMPX bit 2. When this mode is selected, 16 or 32 bits should be specified as the bus width for areas 2 and 3. In this mode the MD5 pin is designated for output as the RAS2 pin. Bit 0—Area 5 and 6 Bus Type (A56PCM): Specifies whether areas 5 and 6 are accessed as PCMCIA interface. The setting of these bits has priority over the MEMMPX bit settings. Bit 0: A56PCM 0 1 Note: * Description Areas 5 and 6 are accessed as SRAM interface Areas 5 and 6 are accessed as PCMCIA interface* The MD3 pin is designated for output as the CE2A pin. The MD4 pin is designated for output as the CE2B pin. (Initial value) Rev.7.00 Oct. 10, 2008 Page 380 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.2.2 Bus Control Register 2 (BCR2) Bus control register 2 (BCR2) is a 16-bit readable/writable register that specifies the bus width for each area, and whether a 16-bit port is used. BCR2 is initialized to H'3FFC by a power-on reset, but is not initialized by a manual reset or in standby mode. External memory space other than area 0 should not be accessed until register initialization is completed. Bit: 15 A0SZ1 Initial value: R/W: Bit: 0/1* R 7 A3SZ1 Initial value: R/W: Note: * 1 R/W 14 A0SZ0 0/1* R 6 A3SZ0 1 R/W 13 A6SZ1 1 R/W 5 A2SZ1 1 R/W 12 A6SZ0 1 R/W 4 A2SZ0 1 R/W 11 A5SZ1 1 R/W 3 A1SZ1 1 R/W 10 A5SZ0 1 R/W 2 A0SZ0 1 R/W 9 A4SZ1 1 R/W 1 — 0 — 8 A4SZ0 1 R/W 0 PORTEN 0 R/W These bits sample the values of the external pins that specify the area 0 bus size. Bits 15 and 14—Area 0 Bus Width (A0SZ1, A0SZ0): These bits sample the external pins, MD4 and MD3 that specify the bus size in a power-on reset by the RESET pin. They are read-only bits. Bit 15 A0SZ1 0 Bit 14 A0SZ0 0 1 1 0 1 Description Bus width is 64 bits Bus width is 8 bits Bus width is 16 bits Bus width is 32 bits Rev.7.00 Oct. 10, 2008 Page 381 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 2n + 1, 2n—Area n (1 to 6) Bus Width Specification (AnSZ1, AnSZ0): These bits specify the bus width of area n (n = 1 to 6). (Bit 0): PORTEN Bit 2n + 1: AnSZ1 0 0 Bit 2n: AnSZ0 0 1 1 0 1 1 0 0 1 1 0 1 Description Bus width is 64 bits Bus width is 8 bits Bus width is 16 bits Bus width is 32 bits (Initial value) Reserved (Setting prohibited) Bus width is 8 bits Bus width is 16 bits Bus width is 32 bits Bit 1—Reserved: This bit is always read as 0, and should only be written with 0. Bit 0—Port Function Enable (PORTEN): Specifies whether pins D51 to D32 are used as a 20bit port. When this function is used, a bus width of 8, 16, or 32 bits should be set for all areas. Bit 0: PORTEN 0 1 Description D51 to D32 are not used as a port D51 to D32 are used as a port (Initial value) Rev.7.00 Oct. 10, 2008 Page 382 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only) Bus control register 3 (BCR3) is a 16-bit readable/writable register that specifies the selection of either the MPX interface or the SRAM interface and specifies the burst length when the synchronous DRAM interface is used. BCR3 is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. No external memory space other than area 0 should be accessed before register initialization has been completed. Bit: 15 MEMMODE 14 A1MPX 0 R/W 6 — 0 R 13 A4MPX 0 R/W 5 — 0 R 12 — 0 R 4 — 0 R 11 — 0 R 3 — 0 R 10 — 0 R 2 — 0 R 9 — 0 R 1 — 0 R 8 — 0 R 0 SDBL 0 R/W Initial value: R/W: Bit: 0 R/W 7 — Initial value: R/W: 0 R Bit 15⎯A1MPX/A4MPX Enable (MEMMODE): Determines whether or not the selection of either the MPX interface or the SRAM interface is by A1MPX and A4MPX rather than by MEMMPX. Bit 15: MEMMODE 0 1 Description MPX or SRAM interface is selected by MEMMPX MPX or SRAM interface is selected by A1MPX and A4MPX (Initial value) Rev.7.00 Oct. 10, 2008 Page 383 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 14 and 13⎯MPX-Interface Specification for Area 1 and 4 (A1MPX, A4MPX): These bits specify the types of memory connected to areas 1 and 4. These settings are validated by MEMMODE. Bit 14: A1MPX 0 1 Description SRAM/byte control SRAM interface is selected for area 1 MPX interface is selected for area 1 (Initial value) Bit 13: A4MPX 0 1 Description SRAM/byte control SRAM interface is selected for area 4 MPX interface is selected for area 4 (Initial value) Bits 12 to 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 0⎯Burst Length (SDBL): Sets the burst length when the synchronous DRAM interface is used. The burst-length setting is only valid when the bus width is 32 bits. Bit 0: SDBL 0 1 Description Burst length is 8 Burst length is 4 (Initial value) 13.2.4 Bus Control Register 4 (BCR4) (SH7750R Only) Bus control register 4 (BCR4) is a 32-bit readable/writable register that enables asynchronous input to the pin corresponding to each bit. BCR4 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. When asynchronous input is set (ASYNCn = 1), the sampling timing is one cycle earlier than when synchronous input is set (ASYNCn = 0)* (see figure 13.4) The timings shown in this section and section 22, Electrical Characteristics, are all for the case where synchronous input is set (ASYNCn = 0). Note: * With the synchronous input setting, ensure that setup and hold times are observed. Rev.7.00 Oct. 10, 2008 Page 384 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) T1 CKIO Tw Tw Twe T2 RDY (BCR4.ASYNC0 = 0) RDY (BCR4.ASYNC0 = 1) Figure 13.4 Example of RDY Sampling Timing at which BCR4 Is Set (Two Wait Cycles Are Inserted by WCR2) Rev.7.00 Oct. 10, 2008 Page 385 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bit: 31 — Initial value: R/W: Bit: 0 R 23 — Initial value: R/W: Bit: 0 R 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 30 — 0 R 22 — 0 R 14 — 0 R 6 — 0 R 29 — 0 R 21 — 0 R 13 — 0 R 5 — 0 R 0 R/W 0 R/W 28 — 0 R 20 — 0 R 12 — 0 R 4 27 — 0 R 19 — 0 R 11 — 0 R 3 26 — 0 R 18 — 0 R 10 — 0 R 2 ASYNC 0 R/W 0 R/W 0 R/W 25 — 0 R 17 — 0 R 9 — 0 R 1 24 — 0 R 16 — 0 R 8 — 0 R 0 Rev.7.00 Oct. 10, 2008 Page 386 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 31 to 5⎯Reserved: These bits are always read as 0, and should only be written with 0. Bits 4 to 0⎯Asynchronous Input: These bits enable asynchronous input to the corresponding pin. Bits 4 to 0: ASYNCn 0 1 Description Input to corresponding pin is synchronous with CKIO Input to corresponding pin can be asynchronous with CKIO (Initial value) Bit 4 3 2 1 0 Corresponding Pin IOIS16 DREQ1 DREQ0 BREQ RDY Rev.7.00 Oct. 10, 2008 Page 387 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.2.5 Wait Control Register 1 (WCR1) Wait control register 1 (WCR1) is a 32-bit readable/writable register that specifies the number of idle state insertion cycles for each area. With some kinds of memory, data bus drive does not go off immediately after the read signal from off-chip goes off. As a result, there is a possibility of a data bus collision when consecutive memory accesses are performed on memory in different areas, or when a memory write is performed immediately after a read. In this LSI, the number of idle cycles set in the WCR1 register are inserted automatically if there is a possibility of this kind of data bus collision. WCR1 is initialized to H'77777777 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: 31 — Initial value: R/W: Bit: 0 R 23 — Initial value: R/W: Bit: 0 R 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 30 29 28 27 — 0 R 19 — 0 R 11 — 0 R 3 — 0 R 26 A6IW2 1 R/W 18 A4IW2 1 R/W 10 A2IW2 1 R/W 2 A0IW2 1 R/W 25 A6IW1 1 R/W 17 A4IW1 1 R/W 9 A2IW1 1 R/W 1 A0IW1 1 R/W 24 A6IW0 1 R/W 16 A4IW0 1 R/W 8 A2IW0 1 R/W 0 A0IW0 1 R/W DMAIW2 DMAIW1 DMAIW0 1 R/W 22 A5IW2 1 R/W 14 A3IW2 1 R/W 6 A1IW2 1 R/W 1 R/W 21 A5IW1 1 R/W 13 A3IW1 1 R/W 5 A1IW1 1 R/W 1 R/W 20 A5IW0 1 R/W 12 A3IW0 1 R/W 4 A1IW0 1 R/W Rev.7.00 Oct. 10, 2008 Page 388 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 31, 27, 23, 19, 15, 11, 7, and 3—Reserved: These bits are always read as 0, and should only be written with 0. Bits 30 to 28— DMAIW-DACK Device Inter-Cycle Idle Specification (DMAIW2– DMAIW0): These bits specify the number of idle cycles between bus cycles to be inserted when switching from a DACK device to another space, or from a read access to a write access on the same device. The DMAIW bits are valid only for DMA single address transfer; with DMA dual address transfer, inter-area idle cycles are inserted. Bits 4n + 2 to 4n—Area n (6 to 0) Inter-Cycle Idle Specification (AnlW2–AnlW0): These bits specify the number of idle cycles between bus cycles to be inserted when switching from external memory space area n (n = 6 to 0) to another space, or from a read access to a write access in the same space. DMAIW2/AnIW2 0 DMAIW1/AnIW1 0 DMAIW0/AnIW0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Idle Cycles 0 1 2 3 6 9 12 15 (Initial value) Rev.7.00 Oct. 10, 2008 Page 389 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) • Idle Insertion between Accesses Following Cycle Same Area Read Preceding Cycle Read Write DMA read (memory → device) DMA write (device → memory) D D M M CPU DMA Write CPU M DMA M Different Area Read CPU M M M DMA M M M Write CPU DMA M M M M M M Same Area MPX Address Output M (1) *2 — Different Area MPX Address Output M (1) M M (1) D D*1 D D D D — D (1) “DMA” in the table indicates DMA single-address transfer. DMA dual transfer is in accordance with the CPU. Legend: M, D: Idle wait always inserted by WCR1 (M(1): One cycle inserted in MPX access even if WCR1 is cleared to 0) M: Idle cycles according to setting of AnIW2-AnIW0 (area 0 to area 6) D: Idle cycles according to setting of DMAIW2-DMAIW0 Notes: When synchronous DRAM is used in RAS down mode, set bits DMAIW2-DMAIW0 to 000 and bits A3IW2-A3IW0 to 000. 1. Inserted when device is switched 2. On the MPX interface, a WCR1 idle wait may be inserted before an access (either read or write) to the same area after a write access. The specific conditions for idle wait insertion in accesses to the same area are shown below. (a) Synchronous DRAM set to RAS down mode (b) Synchronous DRAM accessed by on-chip DMAC Apart from use under above conditions (a) and (b), an idle wait is also inserted between an MPX interface write access and a following access to the same area. Even under the above conditions, an idle wait may be inserted in a same-area access following an interface write access, depending on the synchronous DRAM pipeline access situation. An idle wait is not inserted when the WCR1 register setting is 0. The setting for the number of idle state cycles inserted after a power-on reset is the default value of 15 (the maximum value), so ensure that the optimum value is set. Rev.7.00 Oct. 10, 2008 Page 390 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.2.6 Wait Control Register 2 (WCR2) Wait control register 2 (WCR2) is a 32-bit readable/writable register that specifies the number of wait states to be inserted for each area. It also specifies the data access pitch when performing burst memory access. This enables low-speed memory to be connected without using external circuitry. WCR2 is initialized to H'FFFEEFFF by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: 31 A6W2 Initial value: R/W: Bit: 1 R/W 23 A5W0 Initial value: R/W: Bit: 1 R/W 15 A3W2 Initial value: R/W: Bit: 1 R/W 7 A1W1 Initial value: R/W: 1 R/W 30 A6W1 1 R/W 22 A5B2 1 R/W 14 A3W1 1 R/W 6 A1W0 1 R/W 29 A6W0 1 R/W 21 A5B1 1 R/W 13 A3W0 1 R/W 5 A0W2 1 R/W 28 A6B2 1 R/W 20 A5B0 1 R/W 12 — 0 R 4 A0W1 1 R/W 27 A6B1 1 R/W 19 A4W2 1 R/W 11 A2W2 1 R/W 3 A0W0 1 R/W 26 A6B0 1 R/W 18 A4W1 1 R/W 10 A2W1 1 R/W 2 A0B2 1 R/W 25 A5W2 1 R/W 17 A4W0 1 R/W 9 A2W0 1 R/W 1 A0B1 1 R/W 24 A5W1 1 R/W 16 — 0 R 8 A1W2 1 R/W 0 A0B0 1 R/W Rev.7.00 Oct. 10, 2008 Page 391 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 31 to 29—Area 6 Wait Control (A6W2—A6W0): These bits specify the number of wait states to be inserted for area 6. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description First Cycle Bit 31: A6W2 0 Bit 30: A6W1 0 Bit 29: A6W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) RDY Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Bits 28 to 26—Area 6 Burst Pitch (A6B2–A6B0): These bits specify the number of wait states to be inserted from the second data access onward in a burst transfer with the burst ROM interface selected. Description Burst Cycle (Excluding First Cycle) Wait States Inserted from Second Data Access Onward RDY Pin 0 1 2 3 4 5 6 7 (Initial value) Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Bit 28: A6B2 0 Bit 27: A6B1 0 Bit 26: A6B0 0 1 1 0 1 1 0 0 1 1 0 1 Rev.7.00 Oct. 10, 2008 Page 392 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 25 to 23—Area 5 Wait Control (A5W2–A5W0): These bits specify the number of wait states to be inserted for area 5. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description First Cycle Bit 25: A5W2 0 Bit 24: A5W1 0 Bit 23: A5W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) RDY Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Bits 22 to 20—Area 5 Burst Pitch (A5B2–A5B0): These bits specify the number of wait states to be inserted from the second data access onward in a burst transfer with the burst ROM interface selected. Description Burst Cycle (Excluding First Cycle) Bit 22: A5B2 0 Bit 21: A5B1 0 Bit 20: A5B0 0 1 1 0 1 1 0 0 1 1 0 1 Wait States Inserted from Second Data Access Onward RDY Pin 0 1 2 3 4 5 6 7 (Initial value) Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev.7.00 Oct. 10, 2008 Page 393 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 19 to 17—Area 4 Wait Control (A4W2–A4W0): These bits specify the number of wait states to be inserted for area 4. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description Bit 19: A4W2 0 Bit 18: A4W1 0 Bit 17: A4W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) RDY Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Bits 16 and 12—Reserved: These bits are always read as 0, and should only be written with 0. Bits 15 to 13—Area 3 Wait Control (A3W2–A3W0): These bits specify the number of wait states to be inserted for area 3. External wait input is only enabled when SRAM interface or MPX interface is used, and is ignored when DRAM or synchronous DRAM is used. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). • When SRAM Interface is Set Description Bit 15: A3W2 0 Bit 14: A3W1 0 Bit 13: A3W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) RDY Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev.7.00 Oct. 10, 2008 Page 394 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) • When DRAM or Synchronous DRAM Interface is Set*1 Description Bit 15: A3W2 0 Bit 14: A3W1 0 Bit 13: A3W0 0 1 1 0 1 1 0 0 1 1 0 1 Notes: 1. External wait input is always ignored. 2. Inhibited in RAS down mode. DRAM CAS Assertion Width 1 2 3 4 7 10 13 16 Synchronous DRAM CAS Latency Cycles Inhibited 1*2 2 3 4*2 5*2 Inhibited Inhibited Bits 11 to 9—Area 2 Wait Control (A2W2–A2W0): These bits specify the number of wait states to be inserted for area 2. External wait input is only enabled when the SRAM interface or MPX interface is used, and is ignored when DRAM or synchronous DRAM is used. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). • When SRAM Interface is Set Description Bit 11: A2W2 0 Bit 10: A2W1 0 Bit 9: A2W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) RDY Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev.7.00 Oct. 10, 2008 Page 395 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) • When DRAM or Synchronous DRAM Interface is Set*1 Description Bit 11: A2W2 0 Bit 10: A2W1 0 Bit 9: A2W0 0 1 1 0 1 1 0 0 1 1 0 1 Notes: 1. External wait input is always ignored. 2. RAS down mode is prohibited. DRAM CAS Assertion Width 1 2 3 4 7 10 13 16 Synchronous DRAM CAS Latency Cycles Inhibited 1*2 2 3 4*2 5*2 Inhibited Inhibited Bits 8 to 6—Area 1 Wait Control (A1W2–A1W0): These bits specify the number of wait states to be inserted for area 1. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description Bit 8: A1W2 0 Bit 7: A1W1 0 Bit 6: A1W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) RDY Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev.7.00 Oct. 10, 2008 Page 396 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 5 to 3—Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait states to be inserted for area 0. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description First Cycle Bit 5: A0W2 0 Bit 4: A0W1 0 Bit 3: A0W0 0 1 1 0 1 1 0 0 1 1 0 1 Inserted Wait States 0 1 2 3 6 9 12 15 (Initial value) RDY Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Bits 2 to 0—Area 0 Burst Pitch (A0B2–A0B0): These bits specify the number of wait states to be inserted afterwards the second data access in a burst transfer with the burst ROM interface selected. Description Burst Cycle (Excluding First Cycle) Bit 2: A0B2 0 Bit 1: A0B1 0 Bit 0: A0B0 0 1 1 0 1 1 0 0 1 1 0 1 Wait States Inserted from Second Data Access Onward 0 1 2 3 4 5 6 7 (Initial value) RDY Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev.7.00 Oct. 10, 2008 Page 397 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.6 MPX Interface is Selected (Areas 0 to 6) Description Inserted Wait States 1st Data AnW2 0 AnW1 0 AnW0 0 1 1 0 1 1 0 0 1 1 Note: n = 6 to 0 0 1 2 3 2 3 1 Read 1 Write 0 1 2 3 0 1 2 3 1 2nd Data Onward 0 RDY Pin Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev.7.00 Oct. 10, 2008 Page 398 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.2.7 Wait Control Register 3 (WCR3) Wait control register 3 (WCR3) is a 32-bit readable/writable register that specifies the cycles inserted in the setup time from the address until assertion of the write strobe, and the data hold time from negation of the strobe, for each area. This enables low-speed memory to be connected without using external circuitry. WCR3 is initialized to H'07777777 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: 31 — Initial value: R/W: Bit: 0 R 23 — Initial value: R/W: Bit: 0 R 15 — Initial value: R/W: Bit: 0 R 7 A1RDH* Initial value: R/W: Note: * 0 R/W* 30 — 0 R 22 A5S0 1 R/W 14 A3S0 1 R/W 6 A1S0 1 R/W 29 — 0 R 21 A5H1 1 R/W 13 A3H1 1 R/W 5 A1H1 1 R/W 28 — 0 R 20 A5H0 1 R/W 12 A3H0 1 R/W 4 A0H0 1 R/W 27 — 0 R 19 A4RDH* 0 R/W* 11 — 0 R 3 — 0 R 26 A6S0 1 R/W 18 A4S0 1 R/W 10 A2S0 1 R/W 2 A0S0 1 R/W 25 A6H1 1 R/W 17 A4H1 1 R/W 9 A2H1 1 R/W 1 A0H1 1 R/W 24 A6H0 1 R/W 16 A4H0 1 R/W 8 A2H0 1 R/W 0 A0H0 1 R/W SH7750R only Bits 31 to 27, 23, 19*, 15, 11, 7*, and 3—Reserved: These bits are always read as 0, and should only be written with 0. Note: * SH7750R only Rev.7.00 Oct. 10, 2008 Page 399 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bit 4n + 2—Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles inserted in the setup time from the address until assertion of the read/write strobe. Valid only for SRAM interface, byte control SRAM interface, and burst ROM interface. Bit 4n + 2: AnS0 0 1 Note: n = 6 to 0 Waits Inserted in Setup 0 1 (Initial value) Bits 4n + 1 and 4n—Area n (6 to 0) Data Hold Time (AnH1, AnH0): When writing, these bits specify the number of cycles to be inserted in the hold time from negation of the write strobe. When reading, they specify the number of cycles to be inserted in the hold time from the data sampling timing. Valid only for SRAM interface, byte control SRAM interface, and burst ROM interface. Bit 4n + 1: AnH1 0 Bit 4n: AnH0 0 1 1 Note: n = 6 to 0 0 1 Waits Inserted in Hold 0 1 2 3 (Initial value) Bits 4n+3⎯Area n (4 or 1) Read-Strobe Negate Timing (AnRDH) (Setting Only Possible in the SH7750R): When reading, these bits specify the timing for the negation of read strobe. These bits should be cleared to 0 when a byte control SRAM setting is made. Valid only for the SRAM interface. Bit 4n + 3: AnRDH 0 1 Note: n = 4 or 1 Read-Strobe Negate Timing Read strobe negated after hold wait cycles specified by WCR3.AnH bits (Initial value) Read strobe negated according to data sampling timing Rev.7.00 Oct. 10, 2008 Page 400 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.2.8 Memory Control Register (MCR) The memory control register (MCR) is a 32-bit readable/writable register that specifies RAS and CAS timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address multiplexing, and refresh control. This enables DRAM and synchronous DRAM to be connected without using external circuitry. MCR is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bits RASD, MRSET, TRC2–0, TPC2–0, RCD1–0, TRWL2–0, TRAS2–0, BE, SZ1–0, AMXEXT, AMX2–0, and EDOMODE are written in the initialization following a poweron reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the same values should be written to the other bits so that they remain unchanged. When using DRAM or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is completed. Bit: 31 RASD Initial value: R/W: Bit: 0 R/W 23 TCAS Initial value: R/W: Bit: 0 R/W 15 TRWL2 Initial value: R/W: Bit: 0 R/W 7 SZ0 Initial value: R/W: 0 R/W 30 MRSET 0 R/W 22 — 0 R 14 TRWL1 0 R/W 6 29 TRC2 0 R/W 21 TPC2 0 R/W 13 TRWL0 0 R/W 5 28 TRC1 0 R/W 20 TPC1 0 R/W 12 TRAS2 0 R/W 4 AMX1 0 R/W 27 TRC0 0 R/W 19 TPC0 0 R/W 11 TRAS1 0 R/W 3 AMX0 0 R/W 26 — 0 R 18 — 0 R 10 TRAS0 0 R/W 2 RFSH 0 R/W 25 — 0 R 17 RCD1 0 R/W 9 BE 0 R/W 1 RMODE 0 R/W 24 — 0 R 16 RCD0 0 R/W 8 SZ1 0 R/W 0 EDO MODE 0 R/W AMXEXT AMX2 0 R/W 0 R/W Rev.7.00 Oct. 10, 2008 Page 401 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bit 31—RAS Down (RASD): Sets RAS down mode. When DRAM/RAS down mode is used, set BE to 1. Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3 are both designated as synchronous DRAM interface. See Connecting a 128-Mbit/256-Mbit Synchronous DRAM with 64-bit Bus Width (SH7750R Only): in section 13.3.5, Synchronous DRAM Interface. Bit 31: RASD 0 1 Description Auto-precharge mode RAS down mode (Initial value) Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2–DMAIW0 to 000 and bits A3IW2–A3IW0 to 000. Bit 30—Mode Register Set (MRSET): Set when a synchronous DRAM mode register setting is used. See Power-On Sequence in section 13.3.5, Synchronous DRAM Interface. Bit 30: MRSET 0 1 Description All-bank precharge Mode register setting (Initial value) Bits 29 to 27—RAS Precharge Time at End of Refresh (TRC2–TRC0) (Synchronous DRAM: auto- and self-refresh both enabled; DRAM: auto- and self-refresh both enabled) Note: For setting values and the period during which no command is issued, see 22.3.3, Bus Timing. Bit 29: TRC2 0 Bit 28: TRC1 0 Bit 27: TRC0 0 1 1 0 1 1 0 0 1 1 0 1 RAS Precharge Interval Immediately after Refresh 0 3 6 9 12 15 18 21 (Initial value) Rev.7.00 Oct. 10, 2008 Page 402 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 26 to 24, 22, and 18—Reserved: These bits are always read as 0, and should only be written with 0. Bit 23—CAS Negation Period (TCAS): This bit is valid only when DRAM interface is set. Bit 23: TCAS 0 1 CAS Negation Period 1 2 (Initial value) Bits 21 to 19—RAS Precharge Period (TPC2–TPC0): When the DRAM interface is selected, these bits specify the minimum number of cycles until RAS is asserted again after being negated. When the synchronous DRAM interface is selected, these bits specify the minimum number of cycles until the next bank active command after precharging. Note: For setting values and the period during which no command is issued, see 22.3.3, Bus Timing. RAS Precharge Interval Bit 21: TPC2 0 Bit 20: TPC1 0 Bit 19: TPC0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Inhibited in RAS down mode. DRAM 0 1 2 3 4 5 6 7 Synchronous DRAM 1* (Initial value) 2 3 4* 5* 6* 7* 8* Rev.7.00 Oct. 10, 2008 Page 403 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 17 and 16—RAS-CAS Delay (RCD1, RCD0): When the DRAM interface is set, these bits set the RAS-CAS assertion delay time. When the synchronous DRAM interface is set, these bits set the bank active-read/write command delay time. Description Bit 17: RCD1 0 Bit 16: RCD0 0 1 1 Note: * 0 1 DRAM 2 cycles 3 cycles 4 cycles 5 cycles Synchronous DRAM Reserved (Setting prohibited) 2 cycles 3 cycles 4 cycles* Inhibited in RAS down mode. Bits 15 to 13—Write Precharge Delay (TRWL2–TRWL0): These bits set the synchronous DRAM write precharge delay time. In auto-precharge mode, they specify the time until the next bank active command is issued after a write cycle. After a write cycle, the next active command is not issued for a period equivalent to the setting values of the TPC[2:0] and TRWL[2:0] bits.* After a write cycle, the next precharge command is not issued for a period of TRWL. This setting is valid only when synchronous DRAM interface is set. Note: * For setting values and the period during which no command is issued, see 22.3.3, Bus Timing. Bit 15: TRWL2 0 Bit 14: TRWL1 0 Bit 13: TRWL0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Inhibited in RAS down mode. Write Precharge ACT Delay Time 1 (Initial value) 2 3* 4* 5* Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) Rev.7.00 Oct. 10, 2008 Page 404 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 12 to 10—CAS-Before-RAS Refresh RAS Assertion Period (TRAS2–TRAS0): When the DRAM interface is set, these bits set the RAS assertion period in CAS-before-RAS refreshing. When the synchronous DRAM interface is set, the bank active command is not issued for the period set by the TRC[2:0]* and TRAS[2:0] bits after an auto-refresh command is issued. Note: For setting values and the period during which no command is issued, see 22.3.3, Bus Timing. Command Interval after Synchronous DRAM Refresh 4 + TRC (Initial value) 5 + TRC 6 + TRC 7 + TRC 8 + TRC 9 + TRC 10 + TRC 11 + TRC Bit 12: TRAS2 0 Bit 11: TRAS1 0 Bit 10: TRAS0 0 1 RAS/DRAM Assertion Period 2 3 4 5 6 7 8 9 1 0 1 1 0 0 1 1 Note: 0 1 TRC (Bits 29 to 27): RAS precharge interval at end of refresh. Bit 9—Burst Enable (BE): Specifies whether burst access is performed on DRAM interface. In synchronous DRAM access, burst access is always performed regardless of the specification of this bit. The DRAM transfer mode depends on EDOMODE. BE 0 EDOMODE 0 1 1 Note: * 0 1 8/16/32/64-Bit Transfer Single Setting prohibited Single/fast page* EDO 32-Byte Transfer Single Setting prohibited Fast page EDO In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit bus. Rev.7.00 Oct. 10, 2008 Page 405 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 8 and 7—Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and synchronous DRAM. This setting has priority over the BCR2 register setting. Description Bit 8: SZ1 0 Bit 7: SZ0 0 1 1 0 1 DRAM 64 bits Reserved (Setting prohibited) 16 bits 32 bits SDRAM 64 bits Reserved (Setting prohibited) Reserved (Setting prohibited) 32 bits Bits 6 to 3—Address Multiplexing (AMXEXT, AMX2–AMX0): These bits specify address multiplexing for DRAM and synchronous DRAM. The address shift value is different for the DRAM interface and the synchronous DRAM interface. • For DRAM Interface: Bit 6: AMXEXT 0* Bit 5: AMX2 0 Bit 4: AMX1 0 Bit 3: AMX0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Description DRAM 8-bit column address product (Initial value) 9-bit column address product 10-bit column address product 11-bit column address product 12-bit column address product Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) When the DRAM interface is used, clear the AMXEXT bit to 0. Rev.7.00 Oct. 10, 2008 Page 406 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) • For Synchronous DRAM Interface: AMX 0 AMXEXT 0 1 1 0 1 2 3 4 5 6 — — — — 0 1 0 1 7 Notes: 1. 2. 3. 4. — SZ 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 64 32 32 64 32 Example of Synchronous DRAM (16M: 512K × 16 bits × 2) × 4 (16M: 512K × 16 bits × 2) × 2 (16M: 512K × 16 bits × 2) × 4 (16M: 512K × 16 bits × 2) × 2 (16M: 1M × 8 bits × 2) × 8 (16M: 1M × 8 bits × 2) × 4 (16M: 1M × 8 bits × 2) × 8 (16M: 1M × 8 bits × 2) × 4 (64M: 1M × 16 bits × 4) × 4 (64M: 1M × 16 bits × 4) × 2 (64M: 2M × 8 bits × 4) × 8 (64M: 2M × 8 bits × 4) × 4 (64M: 512K × 32 bits × 4) × 2 (64M: 512K × 32 bits × 4) × 1 (64M: 1M × 32 bits × 2) × 2 (64M: 1M × 32 bits × 2) × 1 (128M: 4M × 8 bits × 4) × 8*2 (256M: 4M × 16 bits × 4) × 4*2 (128M: 4M × 8 bits × 4) × 4* 3 BANK*4 a[22]* 1 a[21]*1 a[21]*1 a[20]*1 a[23]* 1 a[22]*1 a[22]*1 a[21]*1 a[24:23]*1 a[23:22]*1 a[25:24]*1 a[24:23]*1 a[23:22]*1 a[22:21]*1 a[23]*1 a[22]*1 a[26:25]*1 a[26:25]*1 a[25:24]*1 a[25:24]*1 a[21]*1 a[20]*1 (256M: 4M × 16 bits × 4) × 2*3 (16M: 256K × 32 bits × 2) × 2 (16M: 256K × 32 bits × 2) × 1 a[*]: Not an address pin but an external address Can only be set in the SH7750R. Can only be set in the SH7750S/SH7750R (Setting prohibited in the SH7750). For details on address multiplexing, refer to appendix F, Synchronous DRAM Address Multiplexing Tables. Rev.7.00 Oct. 10, 2008 Page 407 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bit 2—Refresh Control (RFSH): Specifies refresh control. Selects whether refreshing is performed for DRAM and synchronous DRAM. When the refresh function is not used, the refresh request cycle generation timer can be used as an interval timer. Bit 2: RFSH 0 1 Description Refreshing is not performed Refreshing is performed (Initial value) Bit 1—Refresh Mode (RMODE): Specifies whether normal refreshing or self-refreshing is performed when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is cleared to 0, CASbefore-RAS refreshing or auto-refreshing is performed for DRAM and synchronous DRAM, using the cycle set by refresh-related registers RTCNT, RTCOR, and RTCSR. If a refresh request is issued during an external bus cycle, the refresh cycle is executed when the bus cycle ends. When the RFSH bit is 1 and this bit is set to 1, the self-refresh state is set for DRAM and synchronous DRAM, after waiting for the end of any currently executing external bus cycle. All refresh requests for memory in the self-refresh state are ignored. Bit 1: RMODE 0 1 Description CAS-before-RAS refreshing is performed (when RFSH = 1) Self-refreshing is performed (when RFSH = 1) (Initial value) Bit 0—EDO Mode (EDOMODE): Used to specify the data sampling timing for data reads when using EDO mode DRAM interface. The setting of this bit does not affect the operation timing of memory other than DRAM. Set this bit to 1 only when DRAM is used. Rev.7.00 Oct. 10, 2008 Page 408 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.2.9 PCMCIA Control Register (PCR) The PCMCIA control register (PCR) is a 16-bit readable/writable register that specifies the OE and WE signal assertion/negation timing for the PCMCIA interface connected to areas 5 and 6. The OE and WE signal assertion width is set by the wait control bits in the WCR2 register. For details of access to PCMCIA, see section 13.3.7, PCMCIA Interface. PCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: 15 14 13 12 11 10 9 8 A5PCW1 A5PCW0 A6PCW1 A6PCW0 A5TED2 A5TED1 A5TED0 A6TED2 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 A6TED1 A6TED0 A5TEH2 A5TEH1 A5TEH0 A6TEH2 A6TEH1 A6TEH0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 15 and 14—PCMCIA Wait (A5PCW1, A5PCW0): These bits specify the number of waits to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The setting of these bits is selected when the PCMCIA interface access TC bit is cleared to 0. Bit 15: A5PCW1 0 Bit 14: A5PCW0 0 1 1 0 1 Waits Inserted 0 (Initial value) 15 30 50 Rev.7.00 Oct. 10, 2008 Page 409 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 13 and 12—PCMCIA Wait (A6PCW1, A6PCW0): These bits specify the number of waits to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The setting of these bits is selected when the PCMCIA interface access TC bit is set to 1. Bit 13: A6PCW1 0 Bit 12: A6PCW0 0 1 1 0 1 Waits Inserted 0 (Initial value) 15 30 50 Bits 11 to 9—Address-OE/WE Assertion Delay (A5TED2–A5TED0): These bits set the delay time from address output to OE/WE assertion on the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is cleared to 0. Bit 11: A5TED2 0 Bit 10: A5TED1 0 Bit 9: A5TED0 0 1 1 0 1 1 0 0 1 1 0 1 Waits Inserted 0 (Initial value) 1 2 3 6 9 12 15 Rev.7.00 Oct. 10, 2008 Page 410 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 8 to 6—Address-OE/WE Assertion Delay (A6TED2–A6TED0): These bits set the delay time from address output to OE/WE assertion on the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is set to 1. Bit 8: A6TED2 0 Bit 7: A6TED1 0 Bit 6: A6TED0 0 1 1 0 1 1 0 0 1 1 0 1 Waits Inserted 0 (Initial value) 1 2 3 6 9 12 15 Bits 5 to 3—OE/WE Negation-Address Delay (A5TEH2–A5TEH0): These bits set the address hold delay time from OE/WE negation in a write on the connected PCMCIA interface or in an I/O card read. The setting of these bits is selected when the PCMCIA interface access TC bit is cleared to 0. Bit 5: A5TEH2 0 Bit 4: A5TEH1 0 Bit 3: A5TEH0 0 1 1 0 1 1 0 0 1 1 0 1 Waits Inserted 0 (Initial value) 1 2 3 6 9 12 15 Rev.7.00 Oct. 10, 2008 Page 411 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bits 2 to 0—OE/WE Negation-Address Delay (A6TEH2–A6TEH0): These bits set the address hold delay time from OE/WE negation in a write on the connected PCMCIA interface or in an I/O card read. In the case of a memory card read, the address hold delay time from the data sampling timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is set to 1. Bit 2: A6TEH2 0 Bit 1: A6TEH1 0 Bit 0: A6TEH0 0 1 1 0 1 1 0 0 1 1 0 1 Waits Inserted 0 (Initial value) 1 2 3 6 9 12 15 Rev.7.00 Oct. 10, 2008 Page 412 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.2.10 Synchronous DRAM Mode Register (SDMR) The synchronous DRAM mode register (SDMR) is a write-only virtual 16-bit register that is written to via the synchronous DRAM address bus, and sets the mode of the area 2 and area 3 synchronous DRAM. Settings for the SDMR register must be made before accessing synchronous DRAM. Bit: 15 14 13 12 11 10 9 8 Initial value: R/W: Bit: — W 7 — W 6 — W 5 — W 4 — W 3 — W 2 — W 1 — W 0 Initial value: R/W: — W — W — W — W — W — W — W — W Since the address bus, not the data bus, is used to write to the synchronous DRAM mode register, if the value to be set is “X” and the SDMR register address is “Y”, value “X” is written to the synchronous DRAM mode register by performing a write to address X + Y. When the synchronous DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to A2 of this LSI, and A1 of the synchronous DRAM is connected to A3 of this LSI, the value actually written to the synchronous DRAM is the value of “X” shifted 2 bits to the right. For example, to write H'0230 to the area 2 SDMR register, arbitrary data is written to address H'FF900000 (address “Y”) + H'08C0 (value “X”) (= H'FF9008C0). As a result, H'0230 is written to the SDMR register. The range of value “X” is H'0000 to H'0FFC. Similarly, to write H'0230 to the area 3 SDMR register, arbitrary data is written to address H'FF940000 (address “Y”) + H'08C0 (value “X”) (= H'FF9408C0). As a result, H'0230 is written to the SDMR register. The range of value “X” is H'0000 to H'0FFC. The lower 16 bits of the address are set in the synchronous DRAM mode register. When the bus width is 32 bits, the burst length is 4* and 8. When the bus width is 64 bits, the burst length is fixed at 4. When a setting is made in SDMR, byte-size writes are performed at the following addresses. Rev.7.00 Oct. 10, 2008 Page 413 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bus Width 32 Burst Length 4* CAS Latency 1 2 3 32 8 1 2 3 64 4 1 2 3 Area 2 H'FF900048 H'FF900088 H'FF9000C8 H'FF90004C H'FF90008C H'FF9000CC H'FF900090 H'FF900110 H'FF900190 Area 3 H'FF940048 H'FF940088 H'FF9400C8 H'FF94004C H'FF94008C H'FF9400CC H'FF940090 H'FF940110 H'FF940190 For a 32-bit bus: 17 Address 0 16 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 7 6 5 4 3 2 1 0 LMO LMO LMO WT BL2 BL1 BL0 DE2 DE1 DE0 ←⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯→ 10 bits set in case of 32-bit bus width For a 64-bit bus: 17 Address 0 16 0 15 0 14 0 13 0 12 0 11 0 10 0 9 8 7 6 5 4 3 2 1 0 LMO LMO LMO WT BL2 BL1 BL0 DE2 DE1 DE0 ←⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯→ 10 bits set in case of 64-bit bus width LMODE: CAS latency BL: Burst length WT: Wrap type (0: Sequential) Rev.7.00 Oct. 10, 2008 Page 414 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) BL 000: Reserved 001: Reserved 010: 4 011: 8 100: Reserved 101: Reserved 110: Reserved 111: Reserved LMODE 000: Reserved 001: 1 010: 2 011: 3 100: Reserved 101: Reserved 110: Reserved 111: Reserved Note: * SH7750R only. 13.2.11 Refresh Timer Control/Status Register (RTCSR) The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that specifies the refresh cycle and whether interrupts are to be generated. RTCSR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: 15 — Initial value: R/W: Bit: 0 — 7 CMF Initial value: R/W: 0 R/W 14 — 0 — 6 CMIE 0 R/W 13 — 0 — 5 CKS2 0 R/W 12 — 0 — 4 CKS1 0 R/W 11 — 0 — 3 CKS0 0 R/W 10 — 0 — 2 OVF 0 R/W 9 — 0 — 1 OVIE 0 R/W 8 — 0 — 0 LMTS 0 R/W Bits 15 to 8—Reserved: These bits are always read as 0. For the write values, see section 13.2.15, Notes on Accessing Refresh Control Registers. Rev.7.00 Oct. 10, 2008 Page 415 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bit 7—Compare-Match Flag (CMF): Status flag that indicates a match between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR) values. Bit 7: CMF 0 Description RTCNT and RTCOR values do not match [Clearing condition] When 0 is written to CMF 1 RTCNT and RTCOR values match [Setting condition] When RTCNT = RTCOR* Note: * If 1 is written, the original value is retained. (Initial value) Bit 6—Compare-Match Interrupt Enable (CMIE): Controls generation or suppression of an interrupt request when the CMF flag is set to 1 in RTCSR. Do not set this bit to 1 when CASbefore-RAS refreshing or auto-refreshing is used. Bit 6: CMIE 0 1 Description Interrupt requests initiated by CMF are disabled Interrupt requests initiated by CMF are enabled (Initial value) Bits 5 to 3—Clock Select Bits (CKS2–CKS0): These bits select the input clock for RTCNT. The base clock is the external bus clock (CKIO). The RTCNT count clock is obtained by scaling CKIO by the specified factor. Bit 5: CKS2 0 Bit 4: CKS1 0 Bit 3: CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Clock input disabled Bus clock (CKIO)/4 CKIO/16 CKIO/64 CKIO/256 CKIO/1024 CKIO/2048 CKIO/4096 (Initial value) Rev.7.00 Oct. 10, 2008 Page 416 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bit 2—Refresh Count Overflow Flag (OVF): Status flag that indicates that the number of refresh requests indicated by the refresh count register (RFCR) has exceeded the number specified by the LMTS bit in RTCSR. Bit 2: OVF 0 Description RFCR has not overflowed the count limit indicated by LMTS [Clearing condition] When 0 is written to OVF 1 RFCR has overflowed the count limit indicated by LMTS [Setting condition] When RFCR overflows the count limit set by LMTS* Note: * If 1 is written, the original value is retained. (Initial value) Bit 1—Refresh Count Overflow Interrupt Enable (OVIE): Controls generation or suppression of an interrupt request when the OVF flag is set to 1 in RTCSR. Bit 1: OVIE 0 1 Description Interrupt requests initiated by OVF are disabled Interrupt requests initiated by OVF are enabled (Initial value) Bit 0—Refresh Count Overflow Limit Select (LMTS): Specifies the count limit to be compared with the refresh count indicated by the refresh count register (RFCR). If the RFCR register value exceeds the value specified by LMTS, the OVF flag is set. Bit 0: LMTS 0 1 Description Count limit is 1024 Count limit is 512 (Initial value) Rev.7.00 Oct. 10, 2008 Page 417 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.2.12 Refresh Timer Counter (RTCNT) The refresh timer counter (RTCNT) is an 8-bit readable/writable counter that is incremented by the input clock (selected by bits CKS2–CKS0 in the RTCSR register). When the RTCNT counter value matches the RTCOR register value, the CMF bit is set in the RTCSR register and the RTCNT counter is cleared. RTCNT is initialized to H'0000 by a power-on reset, but continues to count when a manual reset is performed. In standby mode, RTCNT is not initialized, and retains its contents. Bit: 15 — Initial value: R/W: Bit: 0 — 7 14 — 0 — 6 13 — 0 — 5 12 — 0 — 4 11 — 0 — 3 10 — 0 — 2 9 — 0 — 1 8 — 0 — 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev.7.00 Oct. 10, 2008 Page 418 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.2.13 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) is a readable/writable register that specifies the upper limit of the RTCNT counter. The RTCOR register and RTCNT counter values (lower 8 bits) are constantly compared, and when they match the CMF bit is set in the RTCSR register and the RTCNT counter is cleared to 0. If the refresh bit (RFSH) has been set to 1 in the memory control register (MCR) and CAS-before-RAS has been selected as the refresh mode, a memory refresh cycle is generated when the CMF bit is set. RTCOR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. Bit: 15 — Initial value: R/W: Bit: 0 — 7 14 — 0 — 6 13 — 0 — 5 12 — 0 — 4 11 — 0 — 3 10 — 0 — 2 9 — 0 — 1 8 — 0 — 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev.7.00 Oct. 10, 2008 Page 419 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.2.14 Refresh Count Register (RFCR) The refresh count register (RFCR) is a 10-bit readable/writable counter that counts the number of refreshes by being incremented each time the RTCOR register and RTCNT counter values match. If the RFCR register value exceeds the count limit specified by the LMTS bit in the RTCSR register, the OVF flag is set in the RTCSR register and the RFCR register is cleared. RFCR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. Bit: 15 — Initial value: R/W: Bit: 0 — 7 14 — 0 — 6 13 — 0 — 5 12 — 0 — 4 11 — 0 — 3 10 — 0 — 2 0 R/W 1 0 R/W 0 9 8 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 13.2.15 Notes on Accessing Refresh Control Registers When the refresh timer control/status register (RTCSR), refresh timer counter (RTCNT), refresh time constant register (RTCOR), and refresh count register (RFCR) are written to, a special code is added to the data to prevent inadvertent rewriting in the event of program runaway, etc. The following procedures should be used for read/write operations. Writing to RTCSR, RTCNT, RTCOR, and RFCR: A word transfer instruction must always be used when writing to RTCSR, RTCNT, RTCOR, or RFCR. A write cannot be performed with a byte transfer instruction. When writing to RTCSR, RTCNT, or RTCOR, set B'10100101 in the upper byte and the write data in the lower byte, as shown in figure 13.5. When writing to RFCR, set B'101001 in the 6 bits starting from the MSB in the upper byte, and the write data in the remaining bits. Rev.7.00 Oct. 10, 2008 Page 420 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 15 1 14 0 13 1 12 0 11 0 10 1 9 0 8 1 7 6 5 4 3 2 1 0 RTCSR, RTCNT, RTCOR Write data 15 RFCR 1 14 0 13 1 12 0 11 0 10 1 9 8 7 6 5 4 3 2 1 0 Write data Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR Reading RTCSR, RTCNT, RTCOR, and RFCR: A 16-bit access must always be used when reading RTCSR, RTCNT, RTCOR, or RFCR. Undefined bits are read as 0. 13.3 13.3.1 Operation Endian/Access Size and Data Alignment This LSI supports both big-endian mode, in which the most significant byte (MSByte) is at the 0 address end in a string of byte data, and little-endian mode, in which the least significant byte (LSByte) is at the 0 address end. The mode is set by means of the MD5 external pin in a power-on reset by the RESET pin, big-endian mode being set if the MD5 pin is low, and little-endian mode if it is high. A data bus width of 8, 16, 32, or 64 bits can be selected for normal memory, 16, 32, or 64 bits for DRAM, 32 or 64 bits for synchronous DRAM, and 8 or 16 bits for the PCMCIA interface. Data alignment is carried out according to the data bus width and endian mode of each device. If the data bus width is smaller than the access size, a number of bus cycles will be generated automatically until the access size is reached. In this case, address incrementing is performed automatically according to the bus width as access is performed. For example, if longword access is performed in an 8-bit bus width area using the SRAM interface, four accesses are executed, with the address automatically incremented by 1 each time. In 32-byte transfer, a total of 32 bytes of data are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on 32byte boundary data using wraparound. Bus release or refresh operations are not performed between these transfers. Data alignment and data length conversion between the different interfaces is performed automatically. Quadword access is used only in transfer by the DMAC. The relationship between the endian mode, device data length, and access unit, is shown in tables 13.7 to 13.14. Rev.7.00 Oct. 10, 2008 Page 421 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Data Configuration MSB Byte Data 7 to 0 LSB MSB Word Data 15 to 8 Data 7 to 0 LSB MSB Longword Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 LSB MSB Quadword Data 63 to 56 Data 55 to 48 Data 47 to 40 Data 39 to 32 Data 31 to 24 Data 23 to 16 Data 15 to 8 LSB Data 7 to 0 Rev.7.00 Oct. 10, 2008 Page 422 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.7 (1) Operation 64-Bit External Device/Big-Endian Access and Data Alignment Data Bus D55–48 — Data 7–0 — — — — — — Data 7–0 — — — Data 23–16 — Data 55–48 D47–40 — — Data 7–0 — — — — — — Data 15–8 — — Data 15–8 — Data 47–40 D39–32 — — — Data 7–0 — — — — — Data 7–0 — — Data 7–0 — Data 39–32 D31–24 — — — — Data 7–0 — — — — — Data 15–8 — — Data 31–24 Data 31–24 D23–16 — — — — — Data 7–0 — — — — Data 7–0 — — Data 23–16 Data 23–16 D15–8 — — — — — — Data 7–0 — — — — Data 15–8 — Data 15–8 Data 15–8 D7–0 — — — — — — — Data 7–0 — — — Data 7–0 — Data 7–0 Data 7–0 Access Size Address No. D63–56 Byte 8n 8n + 1 8n + 2 8n + 3 8n + 4 8n + 5 8n + 6 8n + 7 Word 8n 8n + 2 8n + 4 8n + 6 Longword 8n 8n + 4 Quadword 8n 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data 7–0 — — — — — — — Data 15–8 — — — Data 31–24 — Data 63–56 Rev.7.00 Oct. 10, 2008 Page 423 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.7 (2) Operation 64-Bit External Device/Big-Endian Access and Data Alignment Strobe Signals WE6, CAS6, DQM6 WE5, CAS5, DQM5 WE4, CAS4, DQM4 WE3, CAS3, DQM3 WE2, CAS2, DQM2 WE1, CAS1, DQM1 WE0, CAS0, DQM0 WE7, CAS7, Access Size Address No. DQM7 Byte 8n 8n + 1 8n + 2 8n + 3 8n + 4 8n + 5 8n + 6 8n + 7 Word 8n 8n + 2 8n + 4 8n + 6 Longword Quadword 8n 8n + 4 8n 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Rev.7.00 Oct. 10, 2008 Page 424 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus WE3, CAS3, DQM3 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Strobe Signals WE2, CAS2, DQM2 WE1, CAS1, DQM1 WE0, CAS0, DQM0 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 Byte 4n 4n + 1 4n + 2 4n + 3 Word 4n 4n + 2 Longword Quadword 4n 8n 8n + 4 1 1 1 1 1 1 1 1 2 Data 7–0 — — — Data 15–8 — Data 31–24 Data 63–56 Data 31–24 — Data 7–0 — — Data 7–0 — Data 23–16 Data 55–48 Data 23–16 — — Data 7–0 — — Data 15–8 Data 15–8 Data 47–40 Data 15–8 — — — Data 7–0 — Data 7–0 Data 7–0 Data 39–32 Data 7–0 Rev.7.00 Oct. 10, 2008 Page 425 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus WE3, CAS3, DQM3 Strobe Signals WE2, CAS2, DQM2 WE1, CAS1, DQM1 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted WE0, CAS0, DQM0 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 Byte 2n 2n + 1 Word Longword 2n 4n 4n + 2 Quadword 8n 8n + 2 8n + 4 8n + 6 1 1 1 1 2 1 2 3 4 — — — — — — — — — — — — — — — — — — Data 7–0 — Data 15–8 Data 31–24 Data 15–8 Data 63–56 Data 47–40 Data 31–24 Data 15–8 — Data 7–0 Data 7–0 Data 23–16 Data 7–0 Data 55–48 Data 39–32 Data 23–16 Data 7–0 Rev.7.00 Oct. 10, 2008 Page 426 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus WE3, CAS3, DQM3 Strobe Signals WE2, CAS2, DQM2 WE1, CAS1, DQM1 WE0, CAS0, DQM0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 Byte Word n 2n 2n + 1 Longword 4n 4n + 1 4n + 2 4n + 3 Quadword 8n 8n + 1 8n + 2 8n + 3 8n + 4 8n + 5 8n + 6 8n + 7 1 1 2 1 2 3 4 1 2 3 4 5 6 7 8 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Data 7–0 Data 15–8 Data 7–0 Data 31–24 Data 23–16 Data 15–8 Data 7–0 Data 63–56 Data 55–48 Data 47–40 Data 39–32 Data 31–24 Data 23–16 Data 15–8 Data 7–0 Rev.7.00 Oct. 10, 2008 Page 427 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment Operation Access Size Address No. D63–56 Byte 8n 8n + 1 8n + 2 8n + 3 8n + 4 8n + 5 8n + 6 8n + 7 Word 8n 8n + 2 8n + 4 8n + 6 Longword 8n 8n + 4 Quadword 8n 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 — — — — — — — Data 7–0 — — — Data 15–8 — Data 31–24 Data 63–56 D55–48 — — — — — — Data 7–0 — — — — Data 7–0 — Data 23–16 Data 55–48 Data 15–8 — — Data 15–8 Data 47–40 Data 7–0 — — Data 7–0 Data 39–32 D47–40 — — — — — Data 7–0 — — — Data Bus D39–32 — — — — Data 7–0 — — — — D31–24 — — — Data 7–0 — — — — — Data 15–8 — — Data 31–24 — Data 31–24 D23–16 — — Data 7–0 — — — — — — Data 7–0 — — Data 23–16 — Data 23–16 D15–8 — Data 7–0 — — — — — — Data 15–8 — — — Data 15–8 — Data 15–8 D7–0 Data 7–0 — — — — — — — Data 7–0 — — — Data 7–0 — Data 7–0 Rev.7.00 Oct. 10, 2008 Page 428 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment Operation WE7, CAS7, Access Size Address No. DQM7 Byte 8n 8n + 1 8n + 2 8n + 3 8n + 4 8n + 5 8n + 6 8n + 7 Word 8n 8n + 2 8n + 4 8n + 6 Longword Quadword 8n 8n + 4 8n 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted WE6, CAS6, DQM6 WE5, CAS5, DQM5 Strobe Signals WE4, CAS4, DQM4 WE3, CAS3, DQM3 WE2, CAS2, DQM2 WE1, CAS1, DQM1 WE0, CAS0, DQM0 Asserted Rev.7.00 Oct. 10, 2008 Page 429 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment Operation Access Size Address No. Byte 4n 4n + 1 4n + 2 4n + 3 Word 4n 4n + 2 Longword Quadword 4n 8n 8n + 4 1 1 1 1 1 1 1 1 2 — — Data 7–0 — Data 15–8 Data 31–24 Data 31–24 Data 63–56 Data Bus WE3, CAS3, DQM3 Strobe Signals WE2, CAS2, DQM2 WE1, CAS1, DQM1 WE0, CAS0, DQM0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted D31–D24 D23–D16 — — Data 7–0 — — Data 7–0 Data 23–16 Data 23–16 Data 55–48 D15–D8 — Data 7–0 — — Data 15–8 — Data 15–8 Data 15–8 Data 47–40 D7–D0 Data 7–0 — — — Data 7–0 — Data 7–0 Data 7–0 Data 39–32 Rev.7.00 Oct. 10, 2008 Page 430 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus WE3, CAS3, DQM3 Strobe Signals WE2, CAS2, DQM2 WE1, CAS1, DQM1 WE0, CAS0, DQM0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 Byte 2n 2n + 1 Word Longword 2n 4n 4n + 2 Quadword 8n 8n + 2 8n + 4 8n + 6 1 1 1 1 2 1 2 3 4 — — — — — — — — — — — — — — — — — — — Data 7–0 Data 15–8 Data 15–8 Data 31–24 Data 15–8 Data 31–24 Data 47–40 Data 63–56 Data 7–0 — Data 7–0 Data 7–0 Data 23–16 Data 7–0 Data 23–16 Data 39–32 Data 55–48 Rev.7.00 Oct. 10, 2008 Page 431 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus WE3, CAS3, DQM3 Strobe Signals WE2, CAS2, DQM2 WE1, CAS1, DQM1 WE0, CAS0, DQM0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 Byte Word n 2n 2n + 1 Longword 4n 4n + 1 4n + 2 4n + 3 Quadword 8n 8n + 1 8n + 2 8n + 3 8n + 4 8n + 5 8n + 6 8n + 7 1 1 2 1 2 3 4 1 2 3 4 5 6 7 8 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Data 7–0 Data 7–0 Data 15–8 Data 7–0 Data 15–8 Data 23–16 Data 31–24 Data 7–0 Data 15–8 Data 23–16 Data 31–24 Data 39–32 Data 47–40 Data 55–48 Data 63–56 Rev.7.00 Oct. 10, 2008 Page 432 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.3.2 Areas Area 0: For area 0, external address bits A28 to A26 are 000. SRAM, MPX, and burst ROM can be set to this area. A bus width of 8, 16, 32, or 64 bits can be selected in a power-on reset by means of external pins MD4 and MD3. For details, see Memory Bus Width in section 13.1.5, Overview of Areas. When area 0 is accessed, the CS0 signal is asserted. In addition, the RD signal, which can be used as OE, and write control signals WE0 to WE7, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A0W2 to A0W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (RDY). When the burst ROM interface is used, the number of burst cycle transfer states is selected in the range 2 to 9 according to the number of waits. The read/write strobe signal address and the CS setup/hold time can be set, respectively, to 0 or 1 and to 0 to 3 cycles using the A0S0, A0H1, and A0H0 bits in the WCR3 register. Area 1: For area 1, external address bits A28 to A26 are 001. SRAM, MPX and byte control SRAM can be set to this area. A bus width of 8, 16, 32, or 64 bits can be selected with bits A1SZ1 and A1SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits A1SZ1 and A1SZ0 in the BCR2 register. When byte control SRAM interface is set, select a bus width of 16, 32, or 64 bits. When area 1 is accessed, the CS1 signal is asserted. In addition, the RD signal, which can be used as OE, and write control signals WE0 to WE7, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A1W2 to A1W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (RDY). The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A1S0 and bits A1H1 and A1H0 in the WCR3 register. Rev.7.00 Oct. 10, 2008 Page 433 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Area 2: For area 2, external address bits A28 to A26 are 010. SRAM, MPX, DRAM, and synchronous DRAM can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A2SZ1 and A2SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits A2SZ1 and A2SZ0 in the BCR2 register. When synchronous DRAM interface is set, select 32 or 64 bits with the SZ bits in the MCR register. When DRAM is connected to area 2, select a bus width of 16 or 32 bits with the SZ bits in MCR. For details, see Memory Bus Width in section 13.1.5, Overview of Areas. When area 2 is accessed, the CS2 signal is asserted. When SRAM interface is set, the RD signal, which can be used as OE, and write control signals WE0 to WE7, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A2W2 to A2W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (RDY). The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A2S0 and bits A2H1 and A2H0 in the WCR3 register. When synchronous DRAM interface is set, the RAS and CAS signals, RD/WR signal, and byte control signals DQM0 to DQM7 are asserted, and address multiplexing is performed. RAS, CAS, and data timing control, and address multiplexing control, can be set using the MCR register. When DRAM is connected, the RAS2 signal, CAS4 to CAS7 signals, and RD/WR signal are asserted, and address multiplexing is performed. RAS2, CAS, and data timing control, and address multiplexing control, can be set using the MCR register. Area 3: For area 3, external address bits A28 to A26 are 011. SRAM, MPX, DRAM, and synchronous DRAM can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A3SZ1 and A3SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits A3SZ1 and A3SZ0 in the BCR2 register. When DRAM interface is set, 16, 32, or 64 bits can be selected with the SZ bits in the MCR register. When synchronous DRAM interface is set, select 32 or 64 bits with the SZ bits in MCR. For details, see Memory Bus Width in section 13.1.5, Overview of Areas. Rev.7.00 Oct. 10, 2008 Page 434 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) When area 3 is accessed, the CS3 signal is asserted. When SRAM interface is set, the RD signal, which can be used as OE, and write control signals WE0 to WE7, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A3W2 to A3W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (RDY). The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A3S0 and bits A3H1 and A3H0 in the WCR3 register. When synchronous DRAM interface is set, the RAS and CAS signals, RD/WR signal, and byte control signals DQM0 to DQM7 are asserted, and address multiplexing is performed. When DRAM interface is set, the RAS signal, CAS0 to CAS7 signals, and RD/WR signal are asserted, and address multiplexing is performed. RAS, CAS, and data timing control, and address multiplexing control, can be set using the MCR register. Area 4: For area 4, external address bits A28 to A26 are 100. SRAM, MPX, and byte control SRAM can be set to this area. A bus width of 8, 16, 32, or 64 bits can be selected with bits A4SZ1 and A4SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits A4SZ1 and A4SZ0 in the BCR2 register. When byte control SRAM interface is set, select a bus width of 16, 32, or 64 bits. For details, see Memory Bus Width in section 13.1.5, Overview of Areas. When area 4 is accessed, the CS4 signal is asserted, and the RD signal, which can be used as OE, and write control signals WE0 to WE7, are also asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A4W2 to A4W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (RDY). The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A4S0 and bits A4H1 and A4H0 in the WCR3 register. Rev.7.00 Oct. 10, 2008 Page 435 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Area 5: For area 5, external address bits A28 to A26 are 101. SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A5SZ1 and A5SZ0 in the BCR2 register. When burst ROM interface is set, a bus width of 8, 16 or 32 bits can be selected with bits A5SZ1 and A5SZ0 in BCR2. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits A5SZ1 and A5SZ0 in BCR2. When a PCMCIA interface is set, either 8 or 16 bits should be selected with bits A5SZ1 and A5SZ0 in BCR2. For details, see Memory Bus Width in section 13.1.5, Overview of Areas. When area 5 set is accessed with SRAM interface set, the CS5 signal is asserted. In addition, the RD signal, which can be used as OE, and write control signals WE0 to WE7, are asserted. When a PCMCIA interface is connected, the CE1A and CE2A signals, the RD signal, which can be used as OE, and the WE1, WE2, WE3, and WE7 signals, which can be used as WE, ICIORD, ICIOWR, and REG, respectively, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A5W2 to A5W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (RDY). When the burst function is used, the number of burst cycle transfer states is determined in the range 2 to 9 according to the number of waits. The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A5S0 and bits A5H1 and A5H0 in the WCR3 register. When a PCMCIA interface is used, the address/CE1A/CE2A setup and hold times with respect to the read/write strobe signals can be set in the range of 0 to 15 cycles with bits AnTED1 and AnTED0, and bits AnTEH1 and AnTEH0, in the PCR register. In addition, the number of wait cycles can be set in the range 0 to 50 with bits AnPCW1 and AnPCW0. The number of waits set in PCR is added to the number of waits set in WCR2. Rev.7.00 Oct. 10, 2008 Page 436 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Area 6: For area 6, external address bits A28 to A26 are 110. SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A6SZ1 and A6SZ0 in the BCR2 register. When burst ROM interface is set, a bus width of 8, 16 or 32 bits can be selected with bits A6SZ1 and A6SZ0 in BCR2. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits A6SZ1 and A6SZ0 in BCR2. When a PCMCIA interface is set, either 8 or 16 bits should be selected with bits A6SZ1 and A6SZ0 in BCR2. For details, see Memory Bus Width in section 13.1.5, Overview of Areas. When area 6 is accessed with SRAM interface set, the CS6 signal is asserted. In addition, the RD signal, which can be used as OE, and write control signals WE0 to WE7, are asserted. When a PCMCIA interface is set, the CE1B and CE2B signals, the RD signal, which can be used as OE, and the WE1, WE2, WE3, and WE7 signals, which can be used as WE, ICIORD, ICIOWR, and REG, respectively, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A6W2 to A6W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (RDY). When the burst function is used, the number of burst cycle transfer states is determined in the range 2 to 9 according to the number of waits. The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A6S0 and bits A6H1 and A6H0 in the WCR3 register. When a PCMCIA interface is used, the address/CE1B/CE2B setup and hold times with respect to the read/write strobe signals can be set in the range of 0 to 15 cycles with bits AnTED1 and AnTED0, and bits AnTEH1 and AnTEH0, in the PCR register. In addition, the number of wait cycles can be set in the range 0 to 50 with bits AnPCW1 and AnPCW0. The number of waits set in PCR is added to the number of waits set in WCR2. Rev.7.00 Oct. 10, 2008 Page 437 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.3.3 SRAM Interface Basic Timing: The SRAM interface of this LSI uses strobe signal output in consideration of the fact that mainly SRAM will be connected. Figure 13.6 shows the basic timing of normal space accesses. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. The CSn signal is asserted on the T1 rising edge, and negated on the next T2 clock rising edge. Therefore, there is no negation period in case of access at minimum pitch. There is no access size specification when reading. The correct access address is output to the address pins (A[25:0]), but since there is no access size specification, 32 bits are always read in the case of a 32-bit device, and 16 bits in the case of a 16-bit device. When writing, only the WE signal for the byte to be written is asserted. For details, see section 13.3.1, Endian/Access Size and Data Alignment. In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed in wrap around mode on the data at the 32-byte boundary. The bus is not released during this transfer. Rev.7.00 Oct. 10, 2008 Page 438 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) T1 CKIO A25–A0 CSn RD/WR RD D63–D0 (read) WEn D63–D0 (write) BS T2 RDY DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Legend: SA: Single address DMA DA: Dual address DMA Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.6 Basic Timing of SRAM Interface Rev.7.00 Oct. 10, 2008 Page 439 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Figures 13.7 to 13.10 show examples of connection to 64-, 32-, 16-, and 8-bit data width SRAM. 128K × 8-bit SRAM A16–A0 CS OE I/O7–I/O0 WE A16–A0 CS OE I/O7–I/O0 WE A16–A0 CS OE I/O7–I/O0 WE A16–A0 CS OE I/O7–I/O0 WE A16–A0 CS OE I/O7–I/O0 WE A16–A0 CS OE I/O7–I/O0 WE A16–A0 CS OE I/O7–I/O0 WE A16–A0 CS OE I/O7–I/O0 WE SH7750, SH7750S, SH7750R A19–A3 CSn RD D63–D56 WE7 D55–D48 WE6 D47–D40 WE5 D39–D32 WE4 D31–D24 WE3 D23–D16 WE2 D15–D8 WE1 D7–D0 WE0 Figure 13.7 Example of 64-Bit Data Width SRAM Connection Rev.7.00 Oct. 10, 2008 Page 440 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 128K × 8-bit SRAM •••• SH7750, SH7750S, SH7750R •••• •••• •••• •••• D24 WE3 D23 D16 WE2 D15 •••• •••• •••• •••• •••• I/O0 WE •••• •••• •••• D0 WE0 •••• I/O0 WE A16 A0 CS OE I/O7 I/O0 WE •••• •••• •••• •••• •••• •••• A16 A0 CS OE I/O7 I/O0 WE Figure 13.8 Example of 32-Bit Data Width SRAM Connection Rev.7.00 Oct. 10, 2008 Page 441 of 1074 REJ09B0366-0700 •••• •••• D8 WE1 D7 A0 CS OE I/O7 •••• •••• A16 •••• A2 CSn RD D31 A0 CS OE I/O7 •••• A18 A16 Section 13 Bus State Controller (BSC) 128K × 8-bit SRAM •••• •••• •••• •••• •••• •••• SH7750, SH7750S, SH7750R A17 •••• A16 A0 CS OE I/O7 •••• A1 CSn RD D15 •••• D8 WE1 D7 •••• I/O0 WE •••• •••• D0 WE0 A16 A0 CS OE I/O7 •••• I/O0 WE Figure 13.9 Example of 16-Bit Data Width SRAM Connection Rev.7.00 Oct. 10, 2008 Page 442 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 128K × 8-bit SRAM A16 •••• •••• •••• SH7750, SH7750S, SH7750R A16 •••• A0 CSn RD D7 •••• •••• •••• A0 CS OE I/O7 I/O0 WE •••• D0 WE0 Figure 13.10 Example of 8-Bit Data Width SRAM Connection Wait State Control: Wait state insertion on the SRAM interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. For details, see section 13.2.6, Wait Control Register 2 (WCR2). The specified number of Tw cycles are inserted as wait cycles using the SRAM interface wait timing shown in figure 13.11. Rev.7.00 Oct. 10, 2008 Page 443 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) T1 CKIO A25–A0 CSn RD/WR RD D63–D0 (read) WEn D63–D0 (write) Tw T2 BS RDY DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.11 SRAM Interface Wait Timing (Software Wait Only) Rev.7.00 Oct. 10, 2008 Page 444 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) When software wait insertion is specified by WCR2, the external wait input RDY signal is also sampled. RDY signal sampling is shown in figure 13.12. A single-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, the RDY signal has no effect if asserted in the T1 cycle or the first Tw cycle. The RDY signal is sampled on the rising edge of the clock. T1 CKIO Tw Twe T2 A25–A0 CSn RD/WR RD (read) D63–D0 (read) WEn (write) D63–D0 (write) BS RDY DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.12 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal) Rev.7.00 Oct. 10, 2008 Page 445 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Read-Strobe Negate Timing (Setting Only Possible in the SH7750R): When the SRAM interface is used, timing for the negation of the strobe during read operations can be specified by the setting of the A1RDH and A4RDH bits of the WCR3 register. For information about this setting, see the description of the WCR3 register. When a byte control SRAM setting is made, AnRDH should be cleared to 0. TS1 T1 Tw Tw Tw Tw T2 TH1 TH2 CKIO A25−A0 CSn RD/WR * RD D63−D0 BS TS1: Setup wait WCR3.AnS (0 to 1) Tw: Access wait WCR2.AnW (0 to 15) TH1, TH2: Hold wait WCR3.AnH (0 to 3) Note: * When AnRDH is set to 1 Figure 13.13 SRAM Interface Read-Strobe Negate Timing (AnS = 1, AnW = 4, AnH = 2) Rev.7.00 Oct. 10, 2008 Page 446 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.3.4 DRAM Interface Direct Connection of DRAM: When the memory type bits (DRAMTP2–0) in BCR1 are set to 100, area 3 becomes DRAM space; when set to 101, area 2 and area 3 become DRAM space. The DRAM interface function can then be used to connect DRAM to this LSI. 16, 32, or 64 bits can be selected as the interface data width for area 3 when bits DRAMTP2–0 are set to 100, and 16 or 32 bits can be used for both area 2 and area 3 when bits DRAMTP2–0 are set to 101. 2-CAS 16-bit DRAMs can be connected, since CAS is used to control byte access. Signals used for connection when DRAM is connected to area 3 are RAS, CAS0 to CAS7, and RD/WR. CAS2 to CAS7 are not used when the data width is 16 bits. When DRAM is connected to areas 2 and 3, the signals for area 2 DRAM connection are RAS2, CAS4 to CAS7, and RD/WR, and those for area 3 DRAM connection are RAS, CAS0 to CAS3, and RD/WR. In addition to normal read and write access modes, fast page mode is supported for burst access. For DRAM connected to areas 2 and 3, EDO mode, which enables the DRAM access time to be increased, is supported. Rev.7.00 Oct. 10, 2008 Page 447 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 1M × 16-bit DRAM A9–A0 RAS OE WE I/O15–I/O0 UCAS LCAS A9–A0 RAS OE WE I/O15–I/O0 UCAS LCAS A9–A0 RAS OE WE I/O15–I/O0 UCAS LCAS A9–A0 RAS OE WE I/O15–I/O0 UCAS LCAS SH7750, SH7750S, SH7750R A12–A3 RAS CS3 RD/WR D63–D48 WE7 WE6 D47–D32 WE5 WE4 D31–D16 WE3 WE2 D15–D0 WE1 WE0 Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3) Rev.7.00 Oct. 10, 2008 Page 448 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 256K × 16-bit DRAM •••• SH7750, SH7750S, SH7750R •••• A10 A2 A8 •••• A0 •••• •••• RAS CS3 RD/WR D31 RAS OE WE I/O15 •••• •••• D0 CAS1 CAS0 •••• D16 CAS3 CAS2 D15 I/O0 UCAS LCAS •••• A0 RAS OE WE I/O15 •••• I/O0 UCAS LCAS Figure 13.15 Example of DRAM Connection (32-Bit Data Width, Area 3) Rev.7.00 Oct. 10, 2008 Page 449 of 1074 REJ09B0366-0700 •••• •••• A8 •••• •••• Section 13 Bus State Controller (BSC) 256K × 16-bit DRAM •••• •••• SH7750, SH7750S, SH7750R •••• •••• A9 A8 A0 Area 3 •••• •••• •••• D0 CAS1 CAS0 CAS5 CAS4 I/O0 UCAS LCAS A8 •••• •••• I/O0 UCAS LCAS Figure 13.16 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3) Rev.7.00 Oct. 10, 2008 Page 450 of 1074 REJ09B0366-0700 •••• A0 RAS OE WE I/O15 •••• •••• A1 CS3 CS2 RAS RAS2 RD/WR D15 RAS OE WE I/O15 Area 2 Section 13 Bus State Controller (BSC) Address Multiplexing: When area 2 or area 3 is designated as DRAM space, address multiplexing is always performed in accesses to DRAM. This enables DRAM, which requires row and column address multiplexing, to be connected to this LSI without using an external address multiplexer circuit. Any of the five multiplexing methods shown below can be selected, by setting bits AMXEXT and AMX2–0 in MCR for area 2 or 3 DRAM. The relationship between the AMXEXT and AMX2–0 bits and address multiplexing is shown in table 13.15. The address output pins subject to address multiplexing are A17 to A1. The address signals output by pins A25 to A18 are undefined. Table 13.15 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing Setting AMXEXT 0 AMX2 0 AMX1 0 AMX0 0 Number of Column Address Bits Output Timing 8 bits Column address Row address 1 9 bits Column address Row address 1 0 10 bits Column address Row address 1 11 bits Column address Row address 1 0 0 12 bits Column address Row address Other settings Reserved — External Address Pins A1–A13 A1–A13 A9–A21 A1–A13 A10–A22 A1–A13 A11–A23 A1–A13 A12–A24 A1–A13 A13–A25 — A14 A14 A22 A14 A23 A14 A24 A14 A25 A14 A14 — A15 A15 A23 A15 A24 A15 A25 A15 A15 A15 A15 — A16 A16 A24 A16 A25 A16 A16 A16 A16 A16 A16 — A17 A17 A25 A17 A17 A17 A17 A17 A17 A17 A17 — Rev.7.00 Oct. 10, 2008 Page 451 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in figure 13.17. Tpc is the precharge cycle, Tr the RAS assert cycle, Tc1 the CAS assert cycle, and Tc2 the read data latch cycle. Tr1 CKIO A25–A0 CSn RD/WR RAS Row Column Tr2 Tc1 Tc2 Tpc CAS D63–D0 (read) D63–D0 (write) BS DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer The DACK is in the high-active setting Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.17 Basic DRAM Access Timing Rev.7.00 Oct. 10, 2008 Page 452 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Wait State Control: As the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. Therefore, provision is made for state extension by using the setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in figure 13.18. Additional Tpc cycles (cycles used to secure the RAS precharge time) can be inserted by means of the TPC bit in MCR, giving from 1 to 7 cycles. The number of cycles from RAS assertion to CAS assertion can be set to between 2 and 5 by inserting Trw cycles by means of the RCD bit in MCR. Also, the number of cycles from CAS assertion to the end of the access can be varied between 1 and 16 according to the setting of A2W2 to A2W0 or A3W2 to A3W0 in WCR2. Tr1 Tr2 Trw Tc1 Tcw Tc2 Tpc Tpc CKIO A25–A0 Row Column CSn RD/WR RAS CAS D63–D0 (read) D63–D0 (write) BS DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.18 DRAM Wait State Timing Rev.7.00 Oct. 10, 2008 Page 453 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Burst Access: In addition to the normal DRAM access mode in which a row address is output in each data access, a fast page mode is also provided for the case where consecutive accesses are made to the same row. This mode allows fast access to data by outputting the row address only once, then changing only the column address for each subsequent access. Normal access or burst access using fast page mode can be selected by means of the burst enable (BE) bit in MCR. The timing for burst access using fast page mode is shown in figure 13.19. If the access size exceeds the set bus width, burst access is performed. In a 32-byte burst transfer (cache fill), the first access comprises a longword that includes the data requiring access. The remaining accesses are performed on 32-byte boundary data that includes the relevant data. In burst transfer (cache write-back), wraparound writing is performed for 32-byte data. Tr1 CKIO A25–A0 CSn RD/WR RAS CAS D63–D0 (read) D63–D0 (write) d1 d1 d2 d2 d3 d3 d4 d4 r c1 c2 c3 c4 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tpc BS DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.19 DRAM Burst Access Timing Rev.7.00 Oct. 10, 2008 Page 454 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) EDO Mode: With DRAM, in addition to the mode in which data is output to the data bus only while the CAS signal is asserted in a data read cycle, an EDO (extended data out) mode is also provided in which, once the CAS signal is asserted while the RAS signal is asserted, even if the CAS signal is negated, data is output to the data bus until the CAS signal is next asserted. In this LSI, the EDO mode bit (EDOMODE) in MCR enables either normal access/burst access using fast page mode, or EDO mode normal access/burst access, to be selected for DRAM. When EDO mode is set, BE must be set to 1 in MCR. EDO mode normal access is shown in figure 13.20, and burst access in figure 13.21. CAS Negation Period: The CAS negation period can be set to 1 or 2 by means of the TCAS bit in the MCR register. Tr1 CKIO Tr2 Tc1 Tc2 Tce Tpc A25–A0 Row Column CSn RD/WR RAS CASn D63–D0 (read) BS DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.20 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1) Rev.7.00 Oct. 10, 2008 Page 455 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tr1 CKIO A25–A0 CSn RD/WR RAS CAS D63–D0 (read) d1 d2 d3 d4 r c1 c2 c3 c4 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce Tpc BS DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.21 Burst Access Timing in DRAM EDO Mode RAS Down Mode: This LSI has an address comparator for detecting row address matches in burst mode. By using this address comparator, and also setting RAS down mode specification bit RASD to 1, it is possible to select RAS down mode, in which RAS remains asserted after the end of an access. When RAS down mode is used, if the refresh cycle is longer than the maximum DRAM RAS assert time, the refresh cycle must be decreased to or below the maximum value of tRAS. RAS down mode can only be used when DRAM is connected in area 3. In RAS down mode, in the event of an access to an address with a different row address, an access to a different area, a refresh request, or a bus request, RAS is negated and the necessary operation is performed. When DRAM access is resumed after this, since this is the start of RAS down mode, the operation starts with row address output. Timing charts are shown in figures 13.22 (1) to (4). Rev.7.00 Oct. 10, 2008 Page 456 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tpc CKIO A25–A0 r c1 c2 c3 c4 Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 CSn RD/WR RAS CAS D63–D0 (read) D63–D0 (write) d1 d1 d2 d3 d4 d2 d3 d4 BS DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, AnW = 0) Rev.7.00 Oct. 10, 2008 Page 457 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tnop CKIO Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 A25–A0 c0 c1 c2 c3 CSn RD/WR RAS End of RAS down mode CASn D63–D0 (read) d0 d1 d2 d3 D63–D0 (write) d0 d1 d2 d3 BS DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, AnW = 0) Rev.7.00 Oct. 10, 2008 Page 458 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tpc CKIO A25–A0 CSn RD/WR RAS CAS D63–D0 (read) d1 d2 d3 d4 r c1 c2 c3 c4 Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce BS DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (3) DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, AnW = 0) Rev.7.00 Oct. 10, 2008 Page 459 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tc1 CKIO A25–A0 CSn RD/WR End of RAS down mode RAS CAS D63–D0 (read) d1 d2 d3 d4 c1 c2 c3 c4 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce BS DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, AnW = 0) Rev.7.00 Oct. 10, 2008 Page 460 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Refresh Timing: The bus state controller includes a function for controlling DRAM refreshing. Distributed refreshing using a CAS-before-RAS cycle can be performed for DRAM by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. Self-refresh mode is also supported. • CAS-before-RAS Refresh When CAS-before-RAS refresh cycles are executed, refreshing is performed at intervals determined by the input clock selected by bits CKS2–CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2–CKS0 in RTCOR should be set so as to satisfy the specification for the DRAM refresh interval. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2–CKS0 setting. When the clock is selected by CKS2–CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and the BACK pin goes high. If this LSI's external bus can be used, CAS-before-RAS refreshing is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 13.23 shows the operation of CAS-before-RAS refreshing. RTCNT cleared to 0 when RTCNT = RTCOR RTCNT value RTCOR-1 H'00000000 RTCSR.CKS2–0 = 000 ≠ 000 Time Refresh request External bus Refresh request cleared by start of refresh cycle CAS-before-RAS refresh cycle Figure 13.23 CAS-Before-RAS Refresh Operation Rev.7.00 Oct. 10, 2008 Page 461 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Figure 13.24 shows the timing of the CAS-before-RAS refresh cycle. The number of RAS assert cycles in the refresh cycle is specified by bits TRAS2–TRAS0 in MCR. The specification of the RAS precharge time in the refresh cycle is determined by the setting of bits TRC2–TRC0 in MCR. TRr1 CKIO A25–A0 CSn RD/WR RAS CAS D63–D0 TRr2 TRr3 TRr4 TRr5 Trc Trc Trc BS Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1) Rev.7.00 Oct. 10, 2008 Page 462 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) • Self-Refresh The self-refreshing supported by this LSI is shown in figure 13.25. After the self-refresh is cleared, the refresh controller immediately generates a refresh request. The RAS precharge time immediately after the end of the self-refreshing can be set by bits TRC2–TRC0 in MCR. CAS-before-RAS refreshing is performed in normal operation, in sleep mode, and in the case of a manual reset. Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the case of a manual reset. When the bus has been released in response to a bus arbitration request, or when a transition is made to standby mode, signals generally become high-impedance, but whether the RAS and CAS signals become high-impedance or continue to be output can be controlled by the HIZCNT bit in BCR1. This enables the DRAM to be kept in the self-refreshing state. As the DRAM CAS signal is multiplexed with WEn for normal memory (SRAM, etc.), access to memory that uses the WEn signals must be disabled during self-refreshing. • Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a cache fill or write-back, and also between read and write cycles during execution of a TAS instruction, and between read and write cycles when DMAC dual address transfer is executed. If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. In order for refreshing to be performed normally, care must be taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh interval. When a refresh request is generated, the BACK pin is negated (driven high). Therefore, normal refreshing can be performed by having the BACK pin monitored by a bus master other than this LSI requesting the bus, or the bus arbiter, and returning the bus to this LSI. Rev.7.00 Oct. 10, 2008 Page 463 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) TRr1 CKIO A25–A0 CSn RD/WR RAS CAS D63–D0 TRr2 TRr3 TRr4 TRr5 Trc Trc Trc BS Figure 13.25 DRAM Self-Refresh Cycle Timing Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time (at least 100 μs or 200 μs) during which no access can be performed be provided, followed by at least the prescribed number (usually 8) of dummy CAS-before-RAS refresh cycles. As the bus state controller does not perform any special operations for a power-on reset, the necessary poweron sequence must be carried out by the initialization program executed after a power-on reset. Rev.7.00 Oct. 10, 2008 Page 464 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.3.5 Synchronous DRAM Interface Connection of Synchronous DRAM: Since synchronous DRAM can be selected by the CS signal, it can be connected to physical space areas 2 and 3 using RAS and other control signals in common. If the memory type bits (DRAMTP2–0) in BCR1 are set to 010, area 2 is normal memory space and area 3 is synchronous DRAM space; if set to 011, areas 2 and 3 are both synchronous DRAM space. With this LSI, burst read/burst write mode is supported as the synchronous DRAM operating mode. The data bus width is 32 or 64 bits, and the SZ size bits in MCR must be set to 00 or 11. The burst enable bit (BE) in MCR is ignored, a 32-byte burst transfer is performed in a cache fill/copy-back cycle, and in a write-through area write or a non-cacheable area read/write, 32-byte data is read even in a single read in order to access synchronous DRAM with a burst read/write access. 32-byte data transfer is also performed in a single write, but DQMn is not asserted when unnecessary data is transferred. For details on the burst length, see section 13.2.10, Synchronous DRAM Mode Register (SDMR), and Power-On Sequence in section 13.3.5, Synchronous DRAM Interface. The SH7750R Group supports burst read and burst write operations with a burst length of 4 as a synchronous DRAM operating mode when using a 32-bit data bus. The burst enable (BE) bit in MCR is ignored, and a 32-byte burst transfer is performed in a cache fill or copy-back cycle. In write-through area write operations and non-cacheable area read or write operations, 16 bytes of data is read even in a single read because burst read or write accesses to synchronous DRAM use a burst length of 4. Sixteen bytes of data is transferred in the case of a single write also, but DQMn is not asserted when unnecessary data is transferred. For changing the burst length (a function only available in the SH7750R) for a 32-bit bus, see Notes on Changing the Burst Length (SH7750R Only) in section 13.3.5, Synchronous DRAM Interface. The control signals for connection of synchronous DRAM are RAS, CAS, RD/WR, CS2 or CS3, DQM0 to DQM7, and CKE. All the signals other than CS2 and CS3 are common to all areas, and signals other than CKE are valid and latched only when CS2 or CS3 is asserted. Synchronous DRAM can therefore be connected in parallel to a number of areas. CKE is negated (driven low) when the frequency is changed, when the clock is unstable after the clock supply is stopped and restarted, or when self-refreshing is performed, and is always asserted (high) at other times. Commands for synchronous DRAM are specified by RAS, CAS, RD/WR, and specific address signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks (PALL), precharge specified bank (PRE), row address strobe bank active (ACTV), read (READ), read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register setting (MRS). Rev.7.00 Oct. 10, 2008 Page 465 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Byte specification is performed by DQM0 to DQM7. A read/write is performed for the byte for which the corresponding DQM signal is low. When the bus width is 64 bits, in big-endian mode DQM7 specifies an access to address 8n, and DQM0 specifies an access to address 8n + 7. In little-endian mode, DQM7 specifies an access to address 8n + 7, and DQM0 specifies an access to address 8n. Figures 13.26 and 13.27 show examples of the connection of 16M × 16-bit synchronous DRAMs. 512K × 16-bit × 2-bank synchronous DRAM A9–A0 CLK CKE CS RAS CAS WE I/O15–I/O0 DQMU DQML SH7750, SH7750S, SH7750R A12–A3 CKIO CKE CS3 RAS CASS RD/WR D63–D48 DQM7 DQM6 D47–D32 DQM5 DQM4 A9–A0 CLK CKE CS RAS CAS WE I/O15–I/O0 DQMU DQML D31–D16 DQM3 DQM2 A9–A0 CLK CKE CS RAS CAS WE I/O15–I/O0 DQMU DQML D15–D0 DQM1 DQM0 A9–A0 CLK CKE CS RAS CAS WE I/O15–I/O0 DQMU DQML Figure 13.26 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3) Rev.7.00 Oct. 10, 2008 Page 466 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 512K × 16-bit × 2-bank synchronous DRAM A9–A0 CLK CKE CS RAS CAS WE I/O15–I/O0 DQMU DQML SH7750, SH7750S, SH7750R A11–A2 CKIO CKE CS3 RAS CASS RD/WR D31–D16 DQM3 DQM2 D15–D0 DQM1 DQM0 A9–A0 CLK CKE CS RAS CAS WE I/O15–I/O0 DQMU DQML Figure 13.27 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) Address Multiplexing: Synchronous DRAM can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits AMXEXT and AMX2– AMX0 in MCR. Table 13.16 shows the relationship between the address multiplex specification bits and the bits output at the address pins. See Appendix F, Synchronous DRAM Address Multiplexing Tables. Address pin output at A25–A18, A1, and A0 are undefined. When A0, the LSB of the synchronous DRAM address, is connected to this LSI, with a 32-bit bus width it makes a longword address specification. Connection should therefore be made in this order: connect pin A0 of the synchronous DRAM to pin A2 of this LSI, then connect pin A1 to pin A3. With a 64-bit bus width, the LSB makes a quadword address specification. Connection should therefore be made in this order: connect pin A0 of the synchronous DRAM to pin A3 of this LSI, then connect pin A1 to pin A4. Rev.7.00 Oct. 10, 2008 Page 467 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.16 Example of Correspondence between this LSI and Synchronous DRAM Address Pins (64-Bit Bus Width, AMX2–AMX0 = 011, AMXEXT = 0) LSI Address Pin RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 — — — CAS Cycle A22 H/L 0 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Not used Not used Not used Synchronous DRAM Address Pin Function BANK select bank address Address precharge setting Burst Read: The timing chart for a burst read is shown in figure 13.28. In the following example it is assumed that four 512K × 16-bit × 2-bank synchronous DRAMs are connected, and a 64-bit data width is used. The burst length is 4. Following the Tr cycle in which ACTV command output is performed, a READA command is issued in the Tc1 cycle, and the read data is accepted on the rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is used to wait for completion of auto-precharge based on the READA command inside the synchronous DRAM; no new access command can be issued to the same bank during this cycle. In this LSI, the number of Tpc cycles is determined by the specification of bits TPC2–TPC0 in MCR, and commands are not issued for synchronous DRAM during this interval. The example in figure 13.28 shows the basic cycle. To connect slower synchronous DRAM, the cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV command output cycle, Tr, to the READA command output cycle, Tc1, can be specified by bits RCD1 and RCD0 in MCR, with a value of 0 to 3 specifying 2 to 4 cycles, respectively. In the case of 2 or more cycles, a Trw cycle, in which an NOP command is issued for the synchronous DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READA Rev.7.00 Oct. 10, 2008 Page 468 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) command output cycle Tc1 to the first read data latch cycle, Td1, can be specified as 1 to 5 cycles independently for areas 2 and 3 by means of bits A2W2–A2W0 and A3W2–A3W0 in WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles. Tr CKIO Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Bank Row Precharge-sel Row H/L Address Row c0 CSn RD/WR RAS CASS DQMn D63–D0 (read) d0 d1 d2 d3 BS CKE DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.28 Basic Timing for Synchronous DRAM Burst Read Rev.7.00 Oct. 10, 2008 Page 469 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the start of the bus cycle. The access sequence is as follows: in a fill operation in the event of a cache miss, 64-bit boundary data including the missed data is read first, then 32-byte boundary data including the missed data is read in wraparound mode. Single Read: With this LSI, as synchronous DRAM is set to burst read/burst write mode, read data output continues after the required data has been read. To prevent data collisions, after the required data is read in Td1, empty read cycles Td2 to Td4 are performed, and this LSI waits for the end of the synchronous DRAM operation. The BS signal is asserted only in Td1. When the data width is 64 bits, there are 4 burst transfers in a read. In cache-through and other DMA read cycles, of cycles Td1 to Td4, BS is asserted and data latched only in the Td1 cycle. Since such empty cycles increase the memory access time, and tend to reduce program execution speed and DMA transfer speed, it is important both to avoid unnecessary cache-through area accesses, and to use a data structure that will allow data to be placed at a 32-byte boundary, and to be transferred in 32-byte units, when carrying out DMA transfer with synchronous DRAM specified as the source. Rev.7.00 Oct. 10, 2008 Page 470 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tr CKIO Bank Row Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Tpc Tpc Tpc Precharge-sel Row H/L c1 Address CSn RD/WR RAS CASS DQMn D63–D0 (read) Row c1 BS CKE DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.29 Basic Timing for Synchronous DRAM Single Read Rev.7.00 Oct. 10, 2008 Page 471 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Burst Write: The timing chart for a burst write is shown in figure 13.30. In this LSI, a burst write occurs only in the event of cache copy-back or a 32-byte transfer by the DMAC. In a burst write operation, the WRITA command is issued in the Tc1 cycle following the Tr cycle in which the ACTV command is output. In the write cycle, the write data is output at the same time as the write command. In the case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started following the write command. Issuance of a new command for synchronous DRAM is postponed during this interval. The number of Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. 32-byte boundary data is written in wraparound mode. DACK is asserted two cycles before the data write cycle. Rev.7.00 Oct. 10, 2008 Page 472 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tr CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn Row Row Row H/L c1 Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Tpc D63–D0 (read) c1 c2 c3 c4 BS CKE DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.30 Basic Timing for Synchronous DRAM Burst Write Single Write: The basic timing chart for write access is shown in figure 13.31. In a single write operation, following the Tr cycle in which ACTV command output is performed, a WRITA command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data is output at the same time as the write command. In the case of a write with auto-precharge, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for synchronous DRAM until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started following the write command. Issuance of a new command for synchronous DRAM is postponed during this Rev.7.00 Oct. 10, 2008 Page 473 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) interval. The number of Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. DACK is asserted two cycles before the data write cycle. As this LSI supports burst read/burst write operations for synchronous DRAM, there are empty cycles in a single write operation. Tr CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn Row Row Row H/L c1 Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Tpc D63–D0 (read) BS CKE c1 DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.31 Basic Timing for Synchronous DRAM Single Write Rev.7.00 Oct. 10, 2008 Page 474 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) RAS Down Mode: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command, in the same way as in the DRAM RAS down state. As synchronous DRAM is internally divided into two or four banks, it is possible to activate one row address in each bank. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. In a write, when auto-precharge is performed, a command cannot be issued for a period of Trwl + Tpc cycles after issuance of the WRIT command. When RAS down mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tpc cycles for each write. The number of cycles between issuance of the precharge command and the row address strobe command is determined by bits TPC2– TPC0 in MCR. There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tRAS. In this way, it is possible to observe the restrictions on the maximum active state time for each bank. If auto-refresh is not used, measures must be taken in the program to ensure that the banks do not remain active for longer than the prescribed time. A burst read cycle without auto-precharge is shown in figure 13.32, a burst read cycle for the same row address in figure 13.33, and a burst read cycle for different row addresses in figure 13.34. Similarly, a burst write cycle without auto-precharge is shown in figure 13.35, a burst write cycle for the same row address in figure 13.36, and a burst write cycle for different row addresses in figure 13.37. When synchronous DRAM is read, there is a 2-cycle latency for the DMQn signal that performs the byte specification. As a result, when the READ command is issued in figure 13.32, if the Tc cycle is executed immediately, the DMQn signal specification for Td1 cycle data output cannot be carried out. Therefore, the CAS latency should not be set to 1. When RAS down mode is set, if only accesses to the respective banks in area 3 are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 13.32 or 13.35, followed by repetition of the cycle in figure 13.33 or 13.36. An access to a Rev.7.00 Oct. 10, 2008 Page 475 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) different area during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 13.34 or 13.37 is executed instead of that in figure 13.33 or 13.36. In RAS down mode, too, a PALL command is issued before a refresh cycle or before bus release due to bus arbitration. Tr CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn D63–D0 (read) Row Row Row H/L c1 Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 c1 c2 c3 c4 BS CKE DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.32 Burst Read Timing Rev.7.00 Oct. 10, 2008 Page 476 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tc1 CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn D63–D0 (read) H/L c1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 c1 c2 c3 c4 BS CKE DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.33 Burst Read Timing (RAS Down, Same Row Address) Rev.7.00 Oct. 10, 2008 Page 477 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tpr CKIO Bank Row Tpc Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Precharge-sel Row H/L Address CSn RD/WR RA S CASS DQMn D63–D0 (read) Row c1 c1 c2 c3 c4 BS CKE DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.34 Burst Read Timing (RAS Down, Different Row Addresses) Rev.7.00 Oct. 10, 2008 Page 478 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tr CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn Row Row Row H/L c1 Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl D63–D0 (read) BS CKE c1 c2 c3 c4 DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.35 Burst Write Timing Rev.7.00 Oct. 10, 2008 Page 479 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tncp CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn Row H/L c1 Tnop Tc1 Tc2 Tc3 Tc4 Trwl Trwl D63–D0 (read) BS CKE c1 c2 c3 c4 Single-address DMA DACKn (SA: IO → memory) Normal write Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as shown by the dotted line. DACKn shows an example where DMAC, CHCRn, and AL (acknowledge level) are 0. Figure 13.36 Burst Write Timing (Same Row Address) Rev.7.00 Oct. 10, 2008 Page 480 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tpr CKIO Bank Tpc Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Trwl Row Row Precharge-sel H/L Row Row H/L Address CSn RD/WR RAS CASS DQMn c1 D63–D0 (read) c1 c2 c3 c4 BS CKE DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.37 Burst Write Timing (Different Row Addresses) Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the DMAC, to provide faster access to synchronous DRAM. As synchronous DRAM is internally divided into two or four banks, after a READ or WRIT command is issued for one bank it is possible to issue a PRE, ACTV, or other command during the CAS latency cycle or data latch cycle, or during the data write cycle, and so shorten the access cycle. Rev.7.00 Oct. 10, 2008 Page 481 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) When a read access is followed by another read access to the same row address, after a READ command has been issued, another READ command is issued before the end of the data latch cycle, so that there is read data on the data bus continuously. When an access is made to another row address and the bank is different, the PRE command or ACTV command can be issued during the CAS latency cycle or data latch cycle. If there are consecutive access requests for different row addresses in the same bank, the PRE command cannot be issued until the last-but-one data latch cycle. If a read access is followed by a write access, it may be possible to issue a PRE or ACT command, depending on the bank and row address, but since the write data is output at the same time as the WRIT command, the PRE, ACTV, and WRIT commands are issued in such a way that one or two empty cycles occur automatically on the data bus. Similarly, with a read access following a write access, or a write access following a write access, the PRE, ACTV, READ, or WRIT command is issued during the data write cycle for the preceding access; however, in the case of different row addresses in the same bank, a PRE command cannot be issued, and so in this case the PRE command is issued following the number of Trwl cycles specified by the TRWL bits in MCR, after the end of the last data write cycle. Figure 13.38 shows a burst read cycle for a different bank and row address following a preceding burst read cycle. Pipelined access is enabled only for consecutive access to area 3, and will be discontinued in the event of an access to another area. Pipelined access is also discontinued in the event of a refresh cycle, or bus release due to bus arbitration. The cases in which pipelined access is available are shown in table 13.17. In this table, “DMAC dual” indicates transfer in DMAC dual address mode, and “DMAC single”, transfer in DMAC single address mode. Rev.7.00 Oct. 10, 2008 Page 482 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tc1_A CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn D63–D0 (read) BS CKE a1 a2 a3 a4 b1 b2 H/L c_A H/L c_B Tc1_B Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle Rev.7.00 Oct. 10, 2008 Page 483 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Table 13.17 Cycles for which Pipeline Access is Possible Succeeding Access CPU Preceding Access CPU Read Write DMAC dual Read Write DMAC single Read Write Read X X X O O O Write X X X O O O DMAC Dual Read O O X O X O Write X X X X X X DMAC Single Read O O X O O O Write O O X O O O Legend: O: Pipeline access possible X: Pipeline access not possible Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. • Auto-Refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2– CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2–CKS0 in RTCOR should be set so as to satisfy the refresh interval specification for the synchronous DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2–CKS0 setting last of all. When the clock is selected by CKS2–CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 13.40 shows the auto-refresh cycle timing. First, an REF command is issued in the TRr cycle. After the TRr cycle, new command output cannot be performed for the duration of the number of cycles specified by bits TRAS2–TRAS0 in MCR plus the number of cycles specified by bits TRC2–TRC0 in MCR. The TRAS2– TRAS0 and TRC2–TRC0 bits must be set so as to satisfy the synchronous DRAM refresh cycle time specification (active/active command delay time). Auto-refreshing is performed in normal operation, in sleep mode, and in the case of a manual reset. Rev.7.00 Oct. 10, 2008 Page 484 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) When both areas 2 and 3 are set to the synchronous DRAM, auto-refreshing of area 2 is performed subsequent to area 3. RTCNT value RTCOR-1 RTCNT cleared to 0 when RTCNT = RTCOR H'00000000 RTCSR.CKS2–0 = 000 ≠ 000 Time Refresh request External bus Refresh request cleared by start of refresh cycle Auto-refresh cycle Figure 13.39 Auto-Refresh Operation Rev.7.00 Oct. 10, 2008 Page 485 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) TRr1 CKIO TRr2 TRr3 TRr4 TRrw TRr5 Trc Trc Trc CSn RD/WR RAS CASS DQMn D63–D0 BS CKE Figure 13.40 Synchronous DRAM Auto-Refresh Timing • Self-Refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal is low. Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by bits TRC2–TRC0 in MCR. Self-refresh timing is shown in figure 13.41. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if RFSH is set to 1 and RMODE is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using this LSI's standby function, and is maintained even after recovery from standby mode other than through a power-on reset. Rev.7.00 Oct. 10, 2008 Page 486 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) In the case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared. Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the case of a manual reset. TRs1 CKIO TRs2 TRs3 TRs4 TRs5 Trc Trc Trc CSn RD/WR RAS CASS DQMn D63–D0 BS CKE Figure 13.41 Synchronous DRAM Self-Refresh Timing Rev.7.00 Oct. 10, 2008 Page 487 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) • Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a cache fill or write-back, and also between read and write cycles during execution of a TAS instruction, and between read and write cycles when DMAC dual address transfer is executed. If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. In order for refreshing to be performed normally, care must be taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh interval. When a refresh request is generated, the BACK pin is negated (driven high). Therefore, normal refreshing can be performed by having the BACK pin monitored by a bus master other than this LSI requesting the bus, or the bus arbiter, and returning the bus to this LSI. Rev.7.00 Oct. 10, 2008 Page 488 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be written to the synchronous DRAM mode register by performing a write to address H'FF900000 + X for area 2 synchronous DRAM, and to address H'FF940000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/write, CAS latency 1 to 3, wrap type = sequential, and burst length 4* or 8, supported by this LSI, arbitrary data is written by bytesize access to the following addresses. Bus Width 32 Burst Length 4* CAS Latency 1 2 3 32 8 1 2 3 64 4 1 2 3 Note: * SH7750R only. Area 2 H'FF900048 H'FF900088 H'FF9000C8 H'FF90004C H'FF90008C H'FF9000CC H'FF900090 H'FF900110 H'FF900190 Area 3 H'FF940048 H'FF940088 H'FF9400C8 H'FF94004C H'FF94008C H'FF9400CC H'FF940090 H'FF940110 H'FF940190 The value set in MCR.MRSET is used to select whether a precharge all banks command or a mode register setting command is issued. The timing for the precharge all banks command is shown in figure 13.42 (1), and the timing for the mode register setting command in figure 13.42 (2). Before mode register, a 200 µs idle time (depending on the memory manufacturer) must be guaranteed after the power required for the synchronous DRAM is turned on. If the reset signal pulse width is greater than this idle time, there is no problem in making the precharge all banks setting immediately. First, a precharge all banks (PALL) command is issued in the TRp1 cycle by performing a write to address H'FF900000 + X or H'FF940000 + X while MCR.MRSET = 0. Next, the number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed. This is achieved automatically while various kinds of initialization are being performed after autorefresh setting, but a way of carrying this out more dependably is to change the RTCOR register Rev.7.00 Oct. 10, 2008 Page 489 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) value to set a short refresh request generation interval just while these dummy cycles are being executed. With simple read or write access, the address counter in the synchronous DRAM used for auto-refreshing is not initialized, and so the cycle must always be an auto-refresh cycle. After auto-refreshing has been executed at least the prescribed number of times, a mode register setting command is issued in the TMw1 cycle by setting MCR.MRSET to 1 and performing a write to address H'FF900000 + X or H'FF940000 + X. Synchronous DRAM mode register setting should be executed once only after power-on (reset) and before synchronous DRAM access, and no subsequent changes should be made. TRp1 CKIO TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 Bank Precharge-sel Address CSn RD/WR RAS CASS D63–D0 CKE (High) Figure 13.42 (1) Synchronous DRAM Mode Write Timing (PALL) Rev.7.00 Oct. 10, 2008 Page 490 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) TRp1 CKIO TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 Bank Precharge-sel Address CSn RD/WR RAS CASS D63–D0 CKE (High) Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set) Notes on Changing the Burst Length (SH7750R Only): In the SH7750R, when synchronous DRAM is connected with a 32-bit memory bus, the burst length can be selected as either 4 or 8 by the setting of the SDBL bit of the BCR3 register. For more details, see the description of the BCR3 register. Rev.7.00 Oct. 10, 2008 Page 491 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) • Burst Read Figure 13.43 is the timing chart of a burst-read operation with a burst length of 4. Following the Tr cycle, during which an ACTV command is output, a READ command is issued during cycle Tc1, and a READA command is issued four cycles later. During the Td1 to Td8 cycles, read data are accepted on the rising edges of the external command clock (CKIO). Tpc is the cycle used to wait for the auto-precharging, which is triggered by the READA command, to be completed in the synchronous DRAM. During this cycle, a new command for accessing the same bank cannot be issued. In the SH7750R, the number of Tpc cycles is determined by the setting of the TPC2 to TPC0 bits of MCR, and no command that operates on the synchronous DRAM may be issued during these cycles. Tr CKIO Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Td5 Td6 Td7 Td8 Tpc Bank Row Precharge-sel Row H/L H/L Address Row c1 c5 CSn RD/WR RAS CASS DQMn D31–D0 (read) c1 c2 c3 c4 c5 c6 c7 c8 BS CKE DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.43 Basic Timing of Synchronous DRAM Burst Read (Burst Length = 4) Rev.7.00 Oct. 10, 2008 Page 492 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the beginning of each data transfer cycle that is in response to a READ or READA command. Data are accessed in the following sequence: in the fill operation for a cache miss, the data between 64-bit boundaries that include the missing data are first read by the initial READ command; after that, the data between 16-bit boundaries data that include the missing data are read in a wraparound way. The subsequently issued READA command reads the 16 bytes of data, which is the remainder of the data between 32-byte boundaries, from the start of the 16-byte boundary. • Burst Write Figure 13.44 is the timing chart for a burst-write operation with a burst length of 4. In this LSI, a burst write takes place when a 32-byte data transfer has occurred. In a burst-write operation, subsequent to the Tr cycle, in which ACTV command output takes place, a WRIT command is issued during the Tc1 cycle, and a WRITA command is issued four cycles later. During the write cycle, write data is output together with the write command. With a write command that includes an auto precharge, the precharge is performed on the relevant bank of the synchronous DRAM on completion of the write command so no new command that accesses the same bank can be issued until precharging is completed. For this reason, in addition to the Tpc precharge-waiting cycle used in read access, Trwl cycles, which are a period of waiting for precharging to start after the write command, are added. These cycles delay the issuing of new commands to the synchronous DRAM. These cycles delay the issuing of new commands to the synchronous DRAM. The setting of the TRWL2 to TRWL0 bits of MCR selects the number of Trwl cycles. The data between 16-byte boundaries is first accessed, and the data between 32-byte boundaries are then written in a wraparound way. DACK is asserted for two cycles before the data-write cycle. Rev.7.00 Oct. 10, 2008 Page 493 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tr CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn Row Row Row H/L c1 H/L c5 Trw Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Trw1 Trw1 Tpc D31–D0 (read) c1 c2 c3 c4 c5 c6 c7 c8 BS CKE DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.44 Basic Timing of a Burst Write to Synchronous DRAM Connecting a 128-Mbit/256-Mbit Synchronous DRAM with 64-bit Bus Width (SH7750R Only): It is possible to connect 128-Mbit or 256-Mbit synchronous DRAMs with 64-bit bus width to the SH7750R. RAS down mode is also available using a 128 Mbytes of external memory space in area 2 or 3. Either eight 128-Mbit (4 M × 8 bit × 4 bank) DRAMs or four 256-Mbit (4 M × 8 bit × 4 bank) DRAMs can be connected. Figure 13.45 shows an example in which four 256-Mbit DRAMs are connected. Notes on Usage: • BCR1.DRAMTP2−DRAMTP0 = 011: Sets areas 2 and 3 as synchronous-DRAM-interface spaces. • MCR.SZ = 00: Sets the bus width of the synchronous DRAM to 64 bits. • MCR.AMX = 6: Selects the 128-Mbit or 256-Mbit address-multiplex setting for the synchronous DRAM. • In the auto-refresh operation, the REF command is issued twice continuously in response to a single refresh request. The interval cycle number between the first and second REF commands issuance is specified by the setting of the TRAS2–TRAS0 bits in MCR, which is 4 to 11 CKIO Rev.7.00 Oct. 10, 2008 Page 494 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) cycles. The interval cycle number between the second REF command and the next ACTV command issuance is specified by the settings of both the TRAS2–TRAS0 bits and the TRC2– TRC0 bits in MCR in the sum total, which is 4 to 32 CKIO cycles. Set RTCOR and bits CKS2–CKS0, and MCR so as to satisfy the refresh-interval rating of the synchronous DRAM which you are using. The synchronous DRAM auto-refresh timing with 64-bit bus width is shown below figure. • When setting the mode register of the synchronous DRAM, set the address for area 2. • Control signals required in this connection are RAS, CAS, RD/WR, CS3, DQM0−DQM7, and CKE. CS2 is not used. • Do not use partial-sharing mode. If you use this, correct operation is not guaranteed. SH7750R CKIO CKE CS3 RAS CASS RD/WR A17 A16 A15–A3 D63–D48 DQM7 DQM6 D47–D32 DQM5 DQM4 D31–D16 DQM3 DQM2 D15–D0 DQM1 DQM0 CLK CKE CS RAS CAS WE BANK1 BANK0 A12–A0 I/O15–I/O0 DQMU DQML CLK CKE CS RAS CAS WE BANK1 BANK0 A12–A0 I/O15–I/O0 DQMU DQML CLK CKE CS RAS CAS WE BANK1 BANK0 A12–A0 I/O15–I/O0 DQMU DQML CLK CKE CS RAS CAS WE BANK1 BANK0 A12–A0 I/O15–I/O0 DQMU DQML Figure 13.45 Example of the Connection of Synchronous DRAM with 64-bit Bus Width (256 Mbits) Rev.7.00 Oct. 10, 2008 Page 495 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) TRr1 TRr2 TRr3 TRr4 TRrw*1 TRr1 TRr2 TRr3 TRr4 TRrw*2 TRr5 Trc*2 Trc*2 Trc*2 CKIO *3 CS3 RD/WR RAS CASS DQMn D63−D0 BS CKE MCR.TRAS[2:0] MCR.TRAS[2:0] and MCR.TRC[2:0] Notes: 1. The interval cycle number between the first and second REF commands is 4 + TRrw × m (m = 0 to 7) CKIO cycles by the setting of the TRAS[2:0] bits. 2. The interval cycle number between the second REF command and the ACTV command after the refresh operation is 4 + TRrw × m (m = 0 to 7) + 3Trc × n (n = 0 to 7) CKIO cycles by the setting of the TRAS[2:0] bits and the TRC[2:0] bits. 3. The next ACTV command is issued at TRr3 to TRr5 (including TRrw × m) + 3Trc × n (n = 0 to 7) + 1 CKIO cycles after second REF command in this refresh operation. This 1 CKIO cycle is included in the setting of the TRAS[2:0] bits. Set MCR.TRAS[2:0], MCR.TRC[2:0], RTCOR and RTCSR.CKS[2:0] so as to satisfy the specification of the synchronous DRAM. Figure 13.46 Synchronous DRAM Auto-Refresh Timing with 64-Bit Bus Width (TRAS[2:0] = 001, TRC[2:0] = 001) Rev.7.00 Oct. 10, 2008 Page 496 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.3.6 Burst ROM Interface Setting bits A0BST2–A0BST0, A5BST2–A5BST0, and A6BST2–A6BST0 in BCR1 to a nonzero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a burst access function. The timing for burst access to burst ROM is shown in figure 13.47. Two wait cycles are set. Basically, access is performed in the same way as for SRAM interface, but when the first cycle ends, only the address is changed before the next access is executed. When 8-bit ROM is connected, the number of consecutive accesses can be set as 4, 8, 16, or 32 with bits A0BST2–A0BST0, A5BST2–A5BST0, or A6BST2– A6BST0. When 16-bit ROM is connected, 4, 8, or 16 can be set in the same way. When 32-bit ROM is connected, 4 or 8 can be set. RDY pin sampling is always performed when one or more wait states are set. The second and subsequent access cycles also comprise two cycles when a burst ROM setting is made and the wait specification is 0. The timing in this case is shown in figure 13.48. A write operation for the burst ROM interface is performed as if the SRAM interface is selected. In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on the data at the 32-byte boundary. The bus is not released during this period. Figure 13.49 shows the timing when a burst ROM setting is made, and setup/hold is specified in WCR3. Rev.7.00 Oct. 10, 2008 Page 497 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) T1 CKIO A25–A5 TB2 TB1 TB2 TB1 TB2 TB1 T2 A4–A0 CSn RD/WR RD D63–D0 (read) BS RDY DACKn (SA: IO ← memory) Notes: 1. For a write cycle, a basic bus cycle (write cycle) is performed. 2. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.47 Burst ROM Basic Access Timing Rev.7.00 Oct. 10, 2008 Page 498 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) T1 CKIO A25–A5 Tw Tw TB2 TB1 Tw TB2 TB1 Tw TB2 TB1 Tw T2 A4–A0 CSn RD/WR RD D63–D0 (read) BS RDY DACKn (SA: IO ← memory) Notes: 1. For a write cycle, a basic bus cycle (write cycle) is performed. 2. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.48 Burst ROM Wait Access Timing Rev.7.00 Oct. 10, 2008 Page 499 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) TS1 CKIO A25–A5 A4–A0 CSn RD/WR RD D63–D0 (read) BS RDY DACKn (SA: IO ← memory) T1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 T2 TH1 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.49 Burst ROM Wait Access Timing 13.3.7 PCMCIA Interface In this LSI, setting the A56PCM bit in BCR1 to 1 makes the bus interface for external memory space areas 5 and 6 an IC memory card interface or I/O card interface as stipulated in JEIDA specification version 4.2 (PCMCIA2.1). Figure 13.50 shows an example of PCMCIA card connection to this LSI. To enable active insertion of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a 3-state buffer must be connected between this LSI's bus interface and the PCMCIA cards. As operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA specifications, this LSI supports only a little-endian mode PCMCIA interface. In the SH7750, the PCMCIA interface area can only be accessed when the MMU is used. The PCMCIA interface memory space can be set in page units and there is a choice of 8-bit common memory, 16-bit common memory, 8-bit attribute memory, 16-bit attribute memory, 8-bit I/O space, 16-bit I/O space, or dynamic bus sizing, according to the accessed SA2 to SA0 bits. Rev.7.00 Oct. 10, 2008 Page 500 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) The setting for wait cycles during a bus access can also be made in MMU page units. When the TC bit to be accessed is cleared to 0, bits A5W2 to A5W0 in wait control register 2 (WCR2), and bits A5PCW1 and A5PCW0, A5TED2 to A5TED0, and A5TEH2 to A5TEH0 in the PCMCIA control register (PCR), are selected. When the TC bit to be accessed is set to 1, bits A6W2 to A6W0 in wait control register 2 (WCR2), and bits A6PCW1 and A6PCW0, A6TED2 to A6TED0, and A6TEH2 to A6TEH0 in the PCMCIA control register (PCR), are selected. For the method of setting bits SA2 to SA0 and bit TC for the page to be accessed, see section 3, Memory Management Unit (MMU). In the SH7750S and SH7750R, the PCMCIA interface can be accessed even when the MMU is not used. When the MMU is off (MMUCR.AT=0), access is always performed by means of bits SA2 to SA0 and bit TC in the page table entry assistance register (PTEA). When the MMU is on (MMUCR.AT=1), the situation is the same as for the SH7750. In this LSI, access to a PCMCIA interface area by the DMAC is always performed using the DMAC's CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. SA2 0 SA1 0 SA0 0 1 1 0 1 1 0 0 1 1 0 1 Description Reserved (Setting prohibited) Dynamic I/O bus sizing 8-bit I/O space 16-bit I/O space 8-bit common memory 16-bit common memory 8-bit attribute memory 16-bit attribute memory AnPCW1–AnPCW0 specify the number of wait states to be inserted in a low-speed bus cycle; a value of 0, 15, 30, or 50 can be set, and this value is added to the number of wait states for insertion specified by WCR2. AnTED2–AnTED0 can be set to a value from 0 to 15, enabling the address, CS, CE2A, CE2B, and REG setup times with respect to the RD and WE1 signals to be secured. AnTEH2–AnTEH0 can also be set to a value from 0 to 15, enabling the address, CS, CE2A, CE2B, and REG write data hold times with respect to the RD and WE1 signals to be secured. Wait cycles between cycles are set with bits A5IW2–A5IW0 and A6IW2–A6IW0 in wait control register 1 (WCR1). The inter-cycle write cycles selected depend only on the area accessed (area 5 or 6): when area 5 is accessed, bits A5IW2–A5IW0 are selected, and when area 6 is accessed, bits A6IW2–A6IW0 are selected. Rev.7.00 Oct. 10, 2008 Page 501 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on the data at the 32-byte boundary. The bus is not released during this period. Table 13.18 Relationship between Address and CE when Using PCMCIA Interface Bus Width (Bits) 8 Read/ Write Read Access Size Odd/ 1 (Bits)* Even 8 Even Odd 16 Even Even Odd Write 8 Even Odd 16 Even Even Odd 16 Read 8 Even Odd 16 Even Odd Write 8 Even Odd 16 Even Odd IOIS16 Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Access CE2 — — First Second — — — First Second — — — — — — — — — 1 1 1 1 — 1 1 1 1 — 1 0 0 — 1 0 0 — CE1 0 0 0 0 — 0 0 0 0 — 0 1 0 — 0 1 0 — A0 0 1 0 1 — 0 1 0 1 — 0 1 0 — 0 1 0 — D15–D8 Invalid Invalid Invalid Invalid — Invalid Invalid Invalid Invalid — Invalid Read data D7–D0 Read data Read data Lower read data Upper read data — Write data Write data Lower write data Upper write data — Read data Invalid Upper read data Lower read data — Invalid Write data — Write data Invalid Upper write data Lower write data — — Rev.7.00 Oct. 10, 2008 Page 502 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Bus Width (Bits) Access Size Odd/ 1 (Bits)* Even 8 Even Odd 16 Even Odd Write 8 Even Odd 16 Even Odd Read 8 Even Odd Odd 16 Even Even Odd Write 8 Even Odd Odd 16 Even Even Odd Read/ Write IOIS16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Access CE2 — — — — — — — — — First Second First Second — — First Second First Second — 1 0 0 — 1 0 0 — 1 0 1 0 1 — 1 0 1 0 1 — CE1 0 1 0 — 0 1 0 — 0 1 0 0 0 — 0 1 0 0 0 — A0 0 1 0 — 0 1 0 — 0 1 1 0 1 — 0 1 1 0 1 — D15–D8 Invalid Read data D7–D0 Read data Invalid Dynamic Read bus 2 sizing* Upper read data Lower read data — Invalid Write data — Write data Invalid Upper write data Lower write data — Invalid Ignored Invalid Invalid Invalid — Invalid Invalid Invalid — Read data Invalid Read data Lower read data Upper read data — Write data Write data Write data Upper write data Lower write data Invalid — Upper write data — Notes: 1. In 32-bit/64-bit/32-byte transfer, the above accesses are repeated, with address incrementing performed automatically according to the bus width, until the transfer data size is reached. 2. PCMCIA I/O card interface only Rev.7.00 Oct. 10, 2008 Page 503 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) A25–A0 D15–D0 RD/WR CE1B/(CS6) CE1A/(CS5) CE2B CE2A SH7750 SH7750S SH7750R RD WE1 ICIORD ICIOWR REG RDY IOIS16 Card detection circuit Output Port G D7–D0 G DIR D15–D8 G DIR G D15–D8 G DIR G DIR D7–D0 G A25–A0 D15–D0 PC card (memory I/O) CE1 CE2 OE WE/PGM (IORD) (IOWR) REG WAIT (IOIS16) CD1, CD2 A25–A0 D15–D0 PC card (memory I/O) G CE1 CE2 OE WE/PGM REG WAIT Card detection circuit CD1, CD2 Figure 13.50 Example of PCMCIA Interface Rev.7.00 Oct. 10, 2008 Page 504 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Memory Card Interface Basic Timing: Figure 13.51 shows the basic timing for the PCMCIA IC memory card interface, and figure 13.52 shows the PCMCIA memory card interface wait timing. Tpcm1 Tpcm2 CKIO A25–A0 CExx REG RD/WR RD (read) D15–D0 (read) WE1 (write) D15–D0 (write) BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.51 Basic Timing for PCMCIA Memory Card Interface Rev.7.00 Oct. 10, 2008 Page 505 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tpcm0 CKIO Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w A25–A0 CExx REG RD/WR RD (read) * D15–D0 (read) WE1 (write) D15–D0 (write) BS RDY DACKn (DA) Notes: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. * SH7750S, SH7750R only Figure 13.52 Wait Timing for PCMCIA Memory Card Interface Rev.7.00 Oct. 10, 2008 Page 506 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Common memory (64 MB) Access by CS5 wait controller Virtual address space Physical I/O addresses 1 KB page IO 1 IO 1 IO 2 Virtual address space Common memory 1 Card 1 on CS5 Common memory 2 Attribute memory I/O space 1 I/O space 2 Access by CS6 wait controller Attribute memory (64 MB) . . . IO 2 1 KB page Different virtual pages mapped to the same physical page Example of I/O spaces with different cycle times (less than 1 KB) I/O space (64 MB) Card 2 on CS6 . . . The page size can be 1 KB, 4 KB, 64 KB, or 1 MB. Example of PCMCIA interface mapping Figure 13.53 PCMCIA Space Allocation I/O Card Interface Timing: Figures 13.54 and 13.55 show the timing for the PCMCIA I/O card interface. When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic sizing of the I/O bus width is possible using the IOIS16 pin. When a 16-bit bus width is set, if the IOIS16 signal is high during a word-size I/O bus cycle, the I/O port is recognized as being 8 bits in width. In this case, a data access for only 8 bits is performed in the I/O bus cycle being executed, followed automatically by a data access for the remaining 8 bits. Dynamic bus sizing is also performed in the case of byte-size access to address 2n + 1. Figure 13.56 shows the basic timing for dynamic bus sizing. Rev.7.00 Oct. 10, 2008 Page 507 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tpci1 Tpci2 CKIO A25–A0 CExx REG RD/WR ICIORD (read) D15–D0 (read) ICIOWR (write) D15–D0 (write) BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.54 Basic Timing for PCMCIA I/O Card Interface Rev.7.00 Oct. 10, 2008 Page 508 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tpci0 CKIO Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w A25–A0 CExx REG RD/WR ICIORD (read) D15–D0 (read) ICIOWR (write) D15–D0 (write) BS RDY IOIS16 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.55 Wait Timing for PCMCIA I/O Card Interface Rev.7.00 Oct. 10, 2008 Page 509 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tpci0 CKIO Tpci Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci1w Tpci2 Tpci2w A25–A1 A0 CExx REG (WE7) RD/WR IORD (WE2) (read) D15–D0 (read) IOWR (WE3) (write) D15–D0 (write) BS RDY IOIS16 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.56 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev.7.00 Oct. 10, 2008 Page 510 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.3.8 MPX Interface If the MD6 pin is set to 0 in a power-on reset by the RESET pin, the MPX interface for normal memory is selected for area 0. The MPX interface is selected for areas 1 to 6 by means of the MPX bit in BCR1 and the MEMMODE, A4MPX, and AIMPX bits in BCR3. The MPX interface offers a multiplexed address/data type bus protocol, and permits easy connection to an external memory controller chip that uses a single 32-bit multiplexed address/data bus. A bus cycle consists of an address phase and a data phase. In the address phase, the address information is output to D25−D0, and the access size to D63−D61 and D31–D29*. The BS signal which indicates the address phase is asserted for one cycle. The CSn signal is asserted at the rise of Tm1, and negated after the last data transfer in the data phase. Therefore, a negate period does not exist for access with the minimum pitch. The FRAME signal is asserted at the rise of Tm1, and negated when the cycle of the last data transfer starts in the data phase. Therefore, in an external device supporting the MPX interface, the address information and access size output in the address phase must be saved in the external device memory, and data corresponding to the data phase must be input or output. For details of access sizes and data alignment, see section 13.3.1, Endian/Access Size and Data Alignment. The address pins output at A25–A0 are undefined. 32-byte transfer performed consecutively for a total of 32 bytes according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on the data at the 32-byte boundary. When the access size is larger than the data bus width, as in this case, burst access is generated, with the address output once, followed by multiple data cycles. The bus is not released during this period. Note: * SH7750R only. D63 0 D62 0 D61 0 1 1 0 1 1 Legend: X: Don't care X X Access Size Byte Word Longword Quadword 32-byte burst Rev.7.00 Oct. 10, 2008 Page 511 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) SH7750, SH7750S, SH7750R CKIO CSn BS RD/FRAME RD/WR D63–D0 RDY MPX device CLK CS BS FRAME WE I/O63–I/O0 RDY Figure 13.57 Example of 64-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for areas 1 to 6, a bus size of 32 or 64 bits should be specified in BCR2. For wait control, waits specified by WCR2 and wait insertion by means of the RDY pin can be used. In a read, one wait cycle is automatically inserted after address output, even if WCR2 is cleared to 0. Rev.7.00 Oct. 10, 2008 Page 512 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tm1 CKIO RD/FRAME D63–D0 A D0 Tmd1w Tmd1 CSn RD/WR RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.58 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits) Rev.7.00 Oct. 10, 2008 Page 513 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tm1 CKIO Tmd1w Tmd1w Tmd1 RD/FRAME D63–D0 CSn RD/WR A D0 RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.59 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted, Bus Width: 64 Bits) Rev.7.00 Oct. 10, 2008 Page 514 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tm1 CKIO RD/FRAME D63–D0 CSn RD/WR A D0 Tmd1 RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.60 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No Wait, Bus Width: 64 Bits) Rev.7.00 Oct. 10, 2008 Page 515 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tm1 CKIO RD/FRAME D63–D0 CSn RD/WR A D0 Tmd1w Tmd1w Tmd1 RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.61 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted, Bus Width: 64 Bits) Rev.7.00 Oct. 10, 2008 Page 516 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tm1 CKIO RD/FRAME D63–D0 CSn RD/WR A Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 D0 D1 D2 D3 RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the Figure 13.62 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct. 10, 2008 Page 517 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tm1 CKIO RD/FRAME D63–D0 CSn RD/WR A Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 D0 D1 D2 D3 RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.63 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct. 10, 2008 Page 518 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tm1 CKIO RD/FRAME D63–D0 CSn RD/WR A Tmd1 Tmd2 Tmd3 Tmd4 D0 D1 D2 D3 RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.64 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct. 10, 2008 Page 519 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tm1 CKIO RD/FRAME D63–D0 CSn RD/WR A Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 D0 D1 D2 D3 RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.65 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct. 10, 2008 Page 520 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tm1 CKIO RD/FRAME D31–D0 A D0 D1 Tmd1w Tmd1 Tmd2 CSn RD/WR RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.66 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev.7.00 Oct. 10, 2008 Page 521 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tm1 CKIO Tmd1w Tmd1w Tmd1 Tmd2 RD/FRAME D31–D0 CSn RD/WR A D0 D1 RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.67 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev.7.00 Oct. 10, 2008 Page 522 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tm1 CKIO RD/FRAME D31–D0 CSn RD/WR A D0 D1 Tmd1 Tmd2 RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.68 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev.7.00 Oct. 10, 2008 Page 523 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tm1 CKIO RD/FRAME D31–D0 CSn RD/WR A D0 D1 Tmd1w Tmd1w Tmd1 Tmd2 RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.69 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev.7.00 Oct. 10, 2008 Page 524 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Tmd8 Tmd7 Tmd6 D5 D6 D7 Figure 13.70 MPX Interface Timing 13 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct. 10, 2008 Page 525 of 1074 REJ09B0366-0700 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Tmd5 Tmd4 Tmd3 Tmd2 Tmd1w Tmd1 Tm1 RD/FRAME D31–D0 A D0 D1 D2 D3 D4 RD/WR CSn BS DACKn (DA) CKIO RDY Section 13 Bus State Controller (BSC) Tmd8w Tmd8 D6 D7 RD/FRAME D31–D0 RD/WR CKIO CSn Figure 13.71 MPX Interface Timing 14 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct. 10, 2008 Page 526 of 1074 REJ09B0366-0700 BS DACKn (DA) RDY Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Tmd7 Tmd3 Tmd2w Tmd2 Tmd1w Tmd1 Tm1 A D0 D1 D2 Section 13 Bus State Controller (BSC) Tmd8 Tmd7 D6 D7 Figure 13.72 MPX Interface Timing 15 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct. 10, 2008 Page 527 of 1074 REJ09B0366-0700 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Tmd6 Tmd5 Tmd4 Tmd3 Tmd2 Tmd1 Tm1 RD/FRAME D31–D0 A D0 D1 D2 D3 D4 D5 RD/WR DACKn (DA) CKIO RDY CSn BS Section 13 Bus State Controller (BSC) Tmd8 Tmd8w D6 D7 Figure 13.73 MPX Interface Timing 16 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct. 10, 2008 Page 528 of 1074 REJ09B0366-0700 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Tmd7 Tmd2 Tmd3 Tmd1 Tmd2w Tmd1w Tm1 RD/FRAME D31–D0 A D0 D1 D2 RD/WR DACKn (DA) CKIO RDY CSn BS Section 13 Bus State Controller (BSC) 13.3.9 Byte Control SRAM Interface The byte control SRAM interface is a memory interface that outputs a byte select strobe (WEn) in both read and write bus cycles. It has 16 bit data pins, and can be connected to SRAM which has an upper byte select strobe and lower byte select strobe function such as UB and LB. Areas 1 and 4 can be designated as byte control SRAM interface. However, when these areas are set to MPX mode, MPX mode has priority. The byte control SRAM interface write timing is the same as for the normal SRAM interface. In read operations, the WEn pin timing is different. In a read access, only the WE signal for the byte being read is asserted. Assertion is synchronized with the fall of the CKIO clock, as for the WE signal, while negation is synchronized with the rise of the CKIO clock, using the same timing as the RD signal. In 32-byte transfer such as a cache fill or copy-back, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on the data at the 32-byte boundary. The bus is not released during this period. Figure 13.74 shows an example of byte control SRAM connection to this LSI, and figures 13.75 to 13.77 show examples of byte control SRAM read cycle. Rev.7.00 Oct. 10, 2008 Page 529 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 64K × 16-bit SRAM A15–A0 CS OE WE I/O15–I/O0 UB LB A15–A0 CS OE WE I/O15–I/O0 UB LB A15–A0 CS OE WE I/O15–I/O0 UB LB A15–A0 CS OE WE I/O15–I/O0 UB LB SH7750, SH7750S, SH7750R A18–A3 CSn RD RD/WR D63–D48 WE7 WE6 D47–D32 WE5 WE4 D31–D16 WE3 WE2 D15–D0 WE1 WE0 Figure 13.74 Example of 64-Bit Data Width Byte Control SRAM Rev.7.00 Oct. 10, 2008 Page 530 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) T1 CKIO T2 A25–A0 CSn RD/WR RD D63–D0 (read) WEn BS RDY DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.75 Byte Control SRAM Basic Read Cycle (No Wait) Rev.7.00 Oct. 10, 2008 Page 531 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) T1 CKIO Tw T2 A25–A0 CSn RD/WR RD D63–D0 (read) WEn BS RDY DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.76 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) Rev.7.00 Oct. 10, 2008 Page 532 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) T1 CKIO Tw Twe T2 A25–A0 CSn RD/WR RD D63–D0 (read) WEn BS RDY DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.77 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) Rev.7.00 Oct. 10, 2008 Page 533 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.3.10 Waits between Access Cycles A problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with the data in the next access, and so resulting in lower reliability or incorrect operation. To avoid this problem, a data collision prevention feature has been provided. This memorizes the preceding access area and the kind of read/write, and if there is a possibility of a bus collision when the next access is started, inserts a wait cycle before the access cycle to prevent a data collision. Wait cycle insertion consists of inserting idle cycles between access cycles, as shown in section 13.2.5, Wait Control Register (WCR1). When this LSI performs consecutive write cycles, the data transfer direction is fixed (from this LSI to other memory) and there is no problem. With read accesses to the same area, also, in principle data is output from the same data buffer, and wait cycle insertion is not performed. If there is originally space between accesses, according to the setting of bits AnIW2–AnIW0 (n = 0 to 6) in WCR1, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles. When bus arbitration is performed, the bus is released after waits are inserted between cycles. In single address mode DMA transfer, when data transfer is performed from an I/O device to memory the data on the bus is determined by the speed of the I/O device. With a low-speed I/O device, an inter-cycle idle wait equivalent to the output buffer turn-off time must be inserted. Even with high-speed memory, when DMA transfer is considered, it may be necessary to insert an intercycle wait to adjust to the speed of a low-speed device, preventing the memory from being used at full speed. Bits DMAIW2–DMAIW0 in wait control register 1 (WCR1) allow an inter-cycle wait setting to be made when transferring data from an I/O device to memory using single address mode DMA transfer. From 0 to 15 waits can be inserted. The number of waits specified by DMAIW2– DMAIW0 are inserted in single address DMA transfers to all areas. In dual address mode DMA transfer, the normal inter-cycle wait specified by AnIW2–AnIW0 (n = 0 to 6) is inserted. Rev.7.00 Oct. 10, 2008 Page 534 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) T1 CKIO T2 Twait T1 T2 Twait T1 T2 A25–A0 CSm CSn BS RD/WR RD D31–D0 Area m space read Area n space read Area n space write Area m inter-access wait specification Area n inter-access wait specification Figure 13.78 Waits between Access Cycles Rev.7.00 Oct. 10, 2008 Page 535 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.3.11 Bus Arbitration This LSI is provided with a bus arbitration function that grants the bus to an external device when it makes a bus request. There are three bus arbitration modes: master mode, partial-sharing master mode, and slave mode. In master mode the bus is held on a constant basis, and is released to another device in response to a bus request. In slave mode the bus is not held on a constant basis; a bus request is issued each time an external bus cycle occurs, and the bus is released again at the end of the access. In partialsharing master mode, only area 2 is shared with external devices; slave mode is in effect for area 2, while for other spaces, bus arbitration is not performed and the bus is held constantly. The area in the master mode chip to which area 2 in the partial-sharing master mode chip is allocated is determined by an external circuit. Master mode and slave mode can be specified by the external mode pins. Partial-sharing master mode is entered from master mode by means of a software setting. See Appendix C, Mode Pin Settings, for the external mode pin settings. In master mode and slave mode, the bus goes to the high-impedance state when not being held. In partial-sharing master mode, the bus is constantly driven, and therefore an external buffer is necessary for connection to the master bus. In master mode, it is possible to connect an external device that issues bus requests instead of a slave mode chip. In the following description, an external device that issues bus requests is also referred to as a slave. This LSI has two internal bus masters: the CPU and the DMAC. When synchronous DRAM or DRAM is connected and refresh control is performed, refresh requests constitute a third bus master. In addition to these are bus requests from external devices in master mode. If requests occur simultaneously, priority is given, in high-to-low order, to a bus request from an external device, a refresh request, the DMAC, and the CPU. To prevent incorrect operation of connected devices when the bus is transferred between master and slave, all bus control signals are negated before the bus is released. When mastership of the bus is received, also, bus control signals begin driving the bus from the negated state. Since signals are driven to the same value by the master and slave exchanging the bus, output buffer collisions can be avoided. Bus transfer is executed between bus cycles. When the bus release request signal (BREQ) is asserted, this LSI releases the bus as soon as the currently executing bus cycle ends, and outputs the bus use permission signal (BACK). However, bus release is not performed during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width Rev.7.00 Oct. 10, 2008 Page 536 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) memory) or during a 32-byte transfer such as a cache fill or write-back. In addition, bus release is not performed between read and write cycles during execution of a TAS instruction, or between read and write cycles when DMAC dual address transfer is executed. When BREQ is negated, BACK is negated and use of the bus is resumed. See Appendix E, Pin Functions, for the pin states when the bus is released. When a refresh request is generated, this LSI performs a refresh operation as soon as the currently executing bus cycle ends. However, refresh operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a cache fill or write-back, and also between read and write cycles during execution of a TAS instruction, and between read and write cycles when DMAC dual address transfer is executed. Refresh operations are also deferred in the bus-released state. If the synchronous DRAM interface is set to the RAS down mode the PALL command is issued before a refresh cycle occurs or before the bus is released by bus arbitration. As the CPU in this LSI is connected to cache memory by a dedicated internal bus, reading from cache memory can still be carried out when the bus is being used by another bus master inside or outside this LSI. When writing from the CPU, an external write cycle is generated when writethrough has been set for the cache in this LSI, or when an access is made to a cache-off area. There is consequently a delay until the bus is returned. When this LSI wants to take back the bus in response to an internal memory refresh request, it negates BACK. On receiving the BACK negation, the device that asserted the external bus release request negates BREQ to release the bus. The bus is thereby returned to this LSI, which then carries out the necessary processing. Rev.7.00 Oct. 10, 2008 Page 537 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) CKIO BREQ BACK A25–A0 CSn RD/WR RD WEn D63–D0 (write) BS Hi-Z Asserted for at least 2 cycles Negated within 2 cycles Hi-Z Hi-Z Hi-Z Hi-Z HiZ Hi-Z Hi-Z Master mode device access Must be asserted for at least 2 cycles Must be negated within 2 cycles BREQ/BSACK BACK/BSREQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Slave mode device access Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z A25–A0 CSn RD/WR RD WEn D63–D0 (write) BS Master access Slave access Master access Figure 13.79 Arbitration Sequence Rev.7.00 Oct. 10, 2008 Page 538 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.3.12 Master Mode The master mode processor holds the bus itself unless it receives a bus request. On receiving an assertion (low level) of the bus request signal (BREQ) from off-chip, the master mode processor releases the bus and asserts (drives low) the bus use permission signal (BACK) as soon as the currently executing bus cycle ends. If a bus release request due to a refresh request has not been issued, on receiving the BREQ negation (high level) indicating that the slave has released the bus, the processor negates (drives high) the BACK signal and resumes use of the bus. If a bus request is issued due to a memory refresh request in the bus-released state, the processor negates the bus use permission signal (BACK), and on receiving the BREQ negation indicating that the slave has released the bus, resumes use of the bus. When the bus is released, all bus interface related output signals and input/output signals go to the high-impedance state, except for the synchronous DRAM interface CKE signal and bus arbitration BACK signal, and DACK0 and DACK1 which control DMA transfers. With DRAM, the bus is released after precharging is completed. With synchronous DRAM, also, a precharge command is issued for the active bank and the bus is released after precharging is completed. The actual bus release sequence is as follows. First, the bus use permission signal is asserted in synchronization with the rising edge of the clock. The address bus and data bus go to the high-impedance state in synchronization with the next rising edge of the clock after this BACK assertion. At the same time, the bus control signals (BS, CSn, RAS1, RAS2, WEn, RD, RD/WR, RD2, RD/WR2, CE2A, and CE2B) go to the highimpedance state. These bus control signals are negated no later than one cycle before going to high-impedance. Bus request signal sampling is performed on the rising edge of the clock. The sequence for re-acquiring the bus from the slave is as follows. As soon as BREQ negation is detected on the rising edge of the clock, BACK is negated and bus control signal driving is started. Driving of the address bus and data bus starts at the next rising edge of an in-phase clock. The bus control signals are asserted and the bus cycle is actually started, at the earliest, at the clock rising edge at which the address and data signals are driven. In order to reacquire the bus and start execution of a refresh operation or bus access, the BREQ signal must be negated for at least two cycles. Rev.7.00 Oct. 10, 2008 Page 539 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) If a refresh request is generated when BACK has been asserted and the bus has been released, the BACK signal is negated even while the BREQ signal is asserted to request the slave to relinquish the bus. When this LSI is used in master mode, consecutive bus accesses may be attempted to reduce the overhead due to arbitration in the case of a slave designed independently by the user. When connecting a slave for which the total duration of consecutive accesses exceeds the refresh cycle, the design should provide for the bus to be released as soon as possible after negation of the BACK signal is detected. 13.3.13 Slave Mode In slave mode, the bus is normally in the released state, and an external device cannot be accessed unless the bus is acquired through execution of the bus arbitration sequence. In a reset, also, the bus-released state is established and the bus arbitration sequence is started from the reset vector fetch. To acquire the bus, the slave device asserts (drives low) the BSREQ signal in synchronization with the rising edge of the clock. The bus use permission BSACK signal is sampled for assertion (low level) in synchronization with the rising edge of the clock. When BSACK assertion is detected, the bus control signals and address bus are immediately driven at the negated level. The bus cycle is started at the next rising edge of the clock. The last signal negated at the end of the access cycle is synchronized with the rising edge of the clock. When the bus cycle ends, the BSREQ signal is negated and the release of the bus is reported to the master. On the next rising edge of the clock, the control signals are set to high-impedance. In order for the slave mode processor to begin access, the BSACK signal must be asserted for at least two cycles. For a slave access cycle in DRAM or synchronous DRAM, the bus is released on completion of precharging, as in the case of the master. Refresh control is left to the master mode device, and any refresh control settings made in slave mode are ignored. Do not use DRAM/synchronous DRAM RAS down mode in slave mode. Synchronous DRAM mode register settings should be made by the master mode device. Do not use the DMAC's DDT mode in slave mode. Rev.7.00 Oct. 10, 2008 Page 540 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.3.14 Partial-Sharing Master Mode In partial-sharing master mode, area 2 only is shared with other devices, and other areas can be accessed at all times. Partial-sharing master mode can be set by setting master mode with the external mode pins, and setting the PSHR bit to 1 in BCR1 in the initialization procedure in a power-on reset. Do not access area 2 until these settings have been performed. In a manual reset the bus state controller setting register values are retained, and so need not be set again. Partial-sharing master mode is designed for use in conjunction with a master mode chip. The partial-sharing master can access a device on the master side via area 2, but the master cannot access a device on the partial-sharing master side. An address and control signal buffer and a data buffer must be located between the partial-sharing master and the master, and controlled by a buffer control circuit. The partial-sharing master mode processor uses the following procedure to access area 2. It asserts the BSREQ signal on the rising edge of the clock, and issues a bus request to the master. It samples BSACK on each rising edge of the clock, and on receiving BSACK assertion, starts the access cycle on the next rising edge of the clock. At the end of the access, it negates BSREQ on the rising edge of the clock. Buffer control in an access to an area 2 device by the partial-sharing master is carried out by referencing the CS2 signal or BSREQ and BSACK signals on the partialsharing master side. Permission to use the bus is reported by the BSACK line connected to the partial-sharing master, but the master may also negate the BSACK signal even while the bus is being used, if it needs the bus urgently in order to service a refresh, for example. Consequently, the partial-sharing master has to monitor the BSREQ signal to see whether it can continue to use the bus after detecting BSACK assertion. In the case of the address buffer, after the address buffer is turned on when BSACK assertion is detected, the buffer is kept on until BSREQ is negated, at which point it is turned off. If the turning-off of the buffer used is late, resulting in a collision with the start of an access cycle on the master side, the BSREQ signal output from the partial-sharing master must be routed through a delay circuit as part of the buffer control circuit, and input to the master BREQ signal. In order for a partial-sharing master mode processor to begin area 2 access, the BSACK signal must be asserted for at least two cycles. When the bus is released after area 2 has been accessed in partial-sharing master mode, if area 2 is synchronous DRAM, there is a wait of the period required for auto-precharge before bus release is performed. In partial-sharing master mode, refreshing is not performed for area 2 (refresh requests are ignored). Rev.7.00 Oct. 10, 2008 Page 541 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Do not use DRAM/synchronous DRAM RAS down mode in partial-sharing master mode. Area 2 synchronous DRAM mode register settings should be made by the master mode device. Set partial-sharing master mode (by setting the PSHR bit to 1 in BCR1) after completion of the area 3 synchronous DRAM mode register settings. In partial-sharing master mode, DMA transfer should not be performed on area 2, and the DMAC's DDT mode should not be used. 13.3.15 Cooperation between Master and Slave To enable system resources to be controlled in a harmonious fashion by master and slave, their respective roles must be clearly defined. Before DRAM or synchronous DRAM is used, initialization operations must be carried out. Responsibility must also be assigned when a standby operation is performed to implement the power-down state. The design of this LSI provides for all control, including initialization, refreshing, and standby control, to be carried out by the master mode device. In a dual-processor configuration using direct master/slave connection, all processing except direct access to memory is handled by the master. In a combination of master mode and partial-sharing master mode, the partial-sharing master mode processor performs initialization, refreshing, and standby control for the areas connected to it, with the exception of area 2, while the master performs initialization of the memory connected to it. If this LSI is specified as the master in a power-on reset, it will not accept bus requests from the slave until the BREQ enable bit (BCR1.BREQEN) is set to 1. To ensure that the slave processor does not access memory requiring initialization before use, such as DRAM and synchronous DRAM, until initialization is completed, write 1 to the BREQ enable bit after initialization ends. Before setting self-refresh mode in standby mode, etc., write 0 to the BREQ enable bit to invalidate the BREQ signal from the slave. Write 1 to the BREQ enable bit only after the master has performed the necessary processing (refresh settings, etc.) for exiting self-refresh mode. Rev.7.00 Oct. 10, 2008 Page 542 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) 13.3.16 Notes on Usage Refresh: Auto refresh operations stop when a transition is made to standby mode, hardware standby mode or deep-sleep mode. If the memory system requires refresh operations, set the memory in the self-refresh state prior to making the transition to standby mode, hardware standby mode or deep-sleep mode. Bus Arbitration: On transition to standby mode or deep-sleep mode, the processor in master mode does not release bus privileges. In systems performing bus arbitration, make the transition to standby mode or deep-sleep mode only after setting the bus privilege release enable bit (BCR1.BREQEN) to 0 for the processor in master mode. If the bus privilege release enable bit remains set to 1, operation cannot be guaranteed when the transition is made to standby mode or deep-sleep mode. Synchronous DRAM Mode Register Setting (SH7750, SH7750S Only): The following conditions must be satisfied when setting the synchronous DRAM mode register. • The DMAC must not be activated until synchronous DRAM mode register setting is completed.*1 • Register setting for the on-chip peripheral modules*2 must not be performed until synchronous DRAM mode register setting is completed.*3 Notes: 1. If a conflict occurs between synchronous DRAM mode register setting and memory access using the DMAC, neither operation can be guaranteed. 2. This applies to the following on-chip peripheral modules: CPG, RTC, INTC, TMU, SCI, SCIF, and H-UDI. 3. If synchronous DRAM mode register setting is performed immediately following write access to the on-chip peripheral modules*2, the values written to the on-chip peripheral modules cannot be guaranteed. Note that following power-on, synchronous DRAM mode register settings should be performed before accessing synchronous DRAM. After making mode register settings, do not change them. BSREQ Output in Partial-Sharing Master Mode: When conditions a. to d. below are all satisfied, the BSREQ pin may be driven low during a refresh operation and a bus release request issued to the master mode device, even though there was no request to access area 2. The period that BSREQ is asserted is 3 to 21 CKIO cycles, as specified by the setting of MCR.TRC (see d. below). Rev.7.00 Oct. 10, 2008 Page 543 of 1074 REJ09B0366-0700 Section 13 Bus State Controller (BSC) Conditions Under which Problem Occurs a. The partial-sharing master mode is selected (BCR1.PSHR = 1). b. Refresh is enabled for area 3 (BCR1.DRAMTP[2:0] = 010, 011, or 101; MCR.RFSH = 1; MCR.RMODE = 0). c. Except for refresh requests, no requests to access external memory (chip-internal requests by the CPU or DMAC to access areas 0 to 6) have been issued to the bus status controller following access to the shared area, area 2. d. MCR.TRC is set to a value other than 0 (MCR.TRC[2:0] ≠ 000). Example: If the refresh cycle is approximately 4,096 times/64 ms, one refresh takes place every 15 µs or so. Therefore, the master mode device’s bus performance may be decreased by 3 to 21 CKIO cycles every 15 µs or so when the master mode device responds to a bus request. In addition, if the master mode device is using the bus when BSREQ is asserted, BSACK may not be asserted immediately. In this case the above problem has little effect on the master mode device. Workarounds: Methods 1. or 2. below can be used as workarounds if degradation of the bus performance of the master mode device due to the phenomenon described above poses a problem. 1. Set MCR.TRC[2:0] to 0 0 0. 2. Store the program in an area other than area 2, and insert an instruction to perform a dummy access to external memory (area 0, 1, or 3 to 6) immediately after the instruction accessing area 2. Rev.7.00 Oct. 10, 2008 Page 544 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Section 14 Direct Memory Access Controller (DMAC) 14.1 Overview The SH7750 and SH7750S include an on-chip four-channel direct memory access controller (DMAC). The SH7750R includes an on-chip eight-channel DMAC. The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped with DACK (TMU, SCI, SCIF), external memories, memory-mapped external devices, and on-chip peripheral modules (except the DMAC, BSC, and UBC). Using the DMAC reduces the burden on the CPU and increases the operating efficiency of the chip. When using the SH7750R, see the following sections: Section 14.6, Configuration of DMAC (SH7750R); Section 14.7, Register Descriptions (SH7750R); Section 14.8, Operation (SH7750R). 14.1.1 Features The DMAC has the following features. Four channels (SH7750/SH7750S), eight channels (SH7750R) Physical address space Choice of 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length Maximum of 16 M (16,777,216) transfers Choice of single or dual address mode ⎯ Single address mode: Either the transfer source or the transfer destination (external device) is accessed by a DACK signal while the other is accessed by address. One data transfer is completed in one bus cycle. ⎯ Dual address mode: Both the transfer source and transfer destination are accessed by address. Values set in DMAC internal registers indicate the accessed address for both the transfer source and the transfer destination. Two bus cycles are required for one data transfer. • Choice of bus mode: Cycle steal mode or burst mode • Two types of DMAC channel priority ranking: ⎯ Fixed priority mode: Channel priorities are permanently fixed. ⎯ Round robin mode: Sets the lowest priority for the channel for which an execution request was last accepted. Rev.7.00 Oct. 10, 2008 Page 545 of 1074 REJ09B0366-0700 • • • • • Section 14 Direct Memory Access Controller (DMAC) • An interrupt request can be sent to the CPU on completion of the specified number of transfers. • Transfer requests: The following three DMAC transfer activation requests are supported. ⎯ External request (1) Normal DMA mode From two DREQ pins. Either low level detection or falling edge detection can be specified. External requests can be accepted on channels 0 and 1 only. (2) On-demand data transfer mode (DDT mode) In this mode of the SH7750 and SH7750S, interfacing between an external device and the DMAC is performed using the DBREQ, BAVL, TR, TDACK, ID [1:0], and D [63:0] pins. External requests can be accepted on all four channels. In the SH7750R, the DBREQ, BAVL, TR, TDACK, ID [2:0], and D [63:0] pins are used as the interface between an external device and the DMAC. External requests can be accepted on any of the eight channels. For channel 0, data transfer can be carried out with the transfer mode, number of transfers, transfer address (single only), etc., specified by the external device. Although channel 0 has no request queue, there are four request queues for each of the other channels: i.e., channels 1 to 3 in the SH7750 or SH7750S, and channels 1 to 7 in the SH7750R. In the SH7750R, request queues can be cleared on a channel-by-channel basis in DDT mode in either of the following two ways. • Clearing a request queue by DTR format The request queues of the relevant channel are cleared when it receives DTR.SZ = 110, DTR.ID = 00, DTR.MD = 11, and DTR.COUNT [7:4]* = [1−8]. • Using software to clear the request queue The request queues of the relevant channel are cleared by writing a 1 to the CHCRn.QCL bit (request-queue clear bit) of each channel. Note: * DTR.COUNT [7:4] (DTR [55:52]): Sets the port as not used. ⎯ Requests from on-chip peripheral modules Transfer requests from the SCI, SCIF, and TMU. These can be accepted on all channels. ⎯ Auto-request The transfer request is generated automatically within the DMAC. • Channel functions: Transfer modes that can be set are different for each channel. ⎯ Normal DMA mode • Channel 0: Single or dual address mode. External requests are accepted. • Channel 1: Single or dual address mode. External requests are accepted. Rev.7.00 Oct. 10, 2008 Page 546 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Channel 2: Dual address mode only. Channel 3: Dual address mode only. • Channel 4 (SH7750R only): Dual address mode only. • Channel 5 (SH7750R only): Dual address mode only. • Channel 6 (SH7750R only): Dual address mode only. • Channel 7 (SH7750R only): Dual address mode only. ⎯ DDT mode channel function • Channel 0: Single address mode. External requests are accepted Dual address mode (SH7750S, SH7750R) • Channel 1: Single or dual address mode. External requests are accepted. • Channel 2: Single or dual address mode. External requests are accepted. • Channel 3: Single or dual address mode. External requests are accepted. • Channel 4 (SH7750R only): Single or dual address mode. External requests are accepted. • Channel 5 (SH7750R only): Single or dual address mode. External requests are accepted. • Channel 6 (SH7750R only): Single or dual address mode. External requests are accepted. • Channel 7 (SH7750R only): Single or dual address mode. External requests are accepted. • • 14.1.2 Block Diagram (SH7750, SH7750S) Figure 14.1 shows a block diagram of the DMAC. Rev.7.00 Oct. 10, 2008 Page 547 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) DMAC module Count control Register control SARn DARn DMATCRn CHCRn DMAOR Request priority control Peripheral bus Internal bus On-chip peripheral module Activation control TMU SCI, SCIF DACK0, DACK1 DRAK0, DRAK1 Bus interface External address/on-chip peripheral module address 4 Request SAR0, DAR0, DMATCR0, CHCR0 only DDT module DTR command buffer DREQ0, DREQ1 BAVL D[63:0] ID[1:0] TDACK Legend: DMAOR: SARn: External bus 32B data buffer Bus state controller CH0 CH1 CH2 CH3 DBREQ DDTMODE BAVL DDTD id[1:0] tdack Request controller 48 bits TR DBREQ DMAC operation register DMAC source address register DARn: DMAC destination address register DMATCRn: DMAC transfer count register CHCRn: DMAC channel control register Note: n = 0 to 3 Figure 14.1 Block Diagram of DMAC Rev.7.00 Oct. 10, 2008 Page 548 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.1.3 Pin Configuration (SH7750, SH7750S) Tables 14.1 and 14.2 show the DMAC pins. Table 14.1 DMAC Pins Channel 0 Pin Name DMA transfer request DREQ acceptance confirmation Abbreviation DREQ0 DRAK0 I/O Input Output Function DMA transfer request input from external device to channel 0 Acceptance of request for DMA transfer from channel 0 to external device Notification to external device of start of execution DMA transfer end notification 1 DMA transfer request DREQ acceptance confirmation DACK0 Output Strobe output to external device of DMA transfer request from channel 0 to external device DMA transfer request input from external device to channel 1 Acceptance of request for DMA transfer from channel 1 to external device Notification to external device of start of execution DMA transfer end notification DACK1 Output Strobe output to external device of DMA transfer request from channel 1 to external device DREQ1 DRAK1 Input Output Rev.7.00 Oct. 10, 2008 Page 549 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Table 14.2 DMAC Pins in DDT Mode Pin Name Data bus request Data bus available Abbreviation DBREQ (DREQ0) BAVL (DRAK0) TR (DREQ1) I/O Input Output Function Data bus release request from external device for DTR format input Data bus release notification Data bus can be used 2 cycles after BAVL is asserted Input If asserted 2 cycles after BAVL assertion, DTR format is sent Only TR asserted: DMA request DBREQ and TR asserted simultaneously: Direct request to channel 2 DMAC strobe Channel number notification TDACK (DACK0) ID [1:0] (DRAK1, DACK1) Output Output Reply strobe signal for external device from DMAC Notification of channel number to external device at same time as TDACK output (ID [1] = DRAK1, ID [0] = DACK1) Transfer request signal 14.1.4 Register Configuration (SH7750, SH7750S) Table 14.3 summarizes the DMAC registers. The DMAC has a total of 17 registers: four registers are allocated to each channel, and an additional control register is shared by all four channels. Table 14.3 DMAC Registers Channel Name 0 DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0 Abbreviation SAR0 DAR0 Read/ Write R/W*2 R/W*2 Area 7 Initial Value P4 Address Address Undefined Undefined Undefined Access Size H'FFA00000 H'1FA00000 32 H'FFA00004 H'1FA00004 32 H'FFA00008 H'1FA00008 32 2 DMATCR0 R/W* CHCR0 R/W*1 *2 H'00000000 H'FFA0000C H'1FA0000C 32 Rev.7.00 Oct. 10, 2008 Page 550 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Channel Name 1 DMA source address register 1 DMA destination address register 1 DMA transfer count register 1 DMA channel control register 1 2 DMA source address register 2 DMA destination address register 2 DMA transfer count register 2 DMA channel control register 2 3 DMA source address register 3 DMA destination address register 3 DMA transfer count register 3 DMA channel control register 3 Com- DMA operation mon register Abbreviation SAR1 DAR1 Read/ Write R/W R/W Area 7 Initial Value P4 Address Address Undefined Undefined Undefined Access Size H'FFA00010 H'1FA00010 32 H'FFA00014 H'1FA00014 32 H'FFA00018 H'1FA00018 32 DMATCR1 R/W CHCR1 SAR2 DAR2 R/W*1 R/W R/W H'00000000 H'FFA0001C H'1FA0001C 32 Undefined Undefined Undefined H'FFA00020 H'1FA00020 32 H'FFA00024 H'1FA00024 32 H'FFA00028 H'1FA00028 32 DMATCR2 R/W CHCR2 SAR3 DAR3 R/W*1 R/W R/W H'00000000 H'FFA0002C H'1FA0002C 32 Undefined Undefined Undefined H'FFA00030 H'1FA00030 32 H'FFA00034 H'1FA00034 32 H'FFA00038 H'1FA00038 32 DMATCR3 R/W CHCR3 DMAOR R/W*1 R/W*1 H'00000000 H'FFA0003C H'1FA0003C 32 H'00000000 H'FFA00040 H'1FA00040 32 Notes: Longword access should be used for all control registers. If a different access width is used, reads will return all 0s and writes will not be possible. 1. Bit 1 of CHCR0–CHCR3 and bits 2 and 1 of DMAOR can only be written with 0 after being read as 1, to clear the flags. 2. In the SH7750, writes from the CPU are masked in DDT mode, while writes from external I/O devices using the DTR format are possible. In the SH7750S, writes from the CPU and writes from external I/O devices using the DTR format are possible in DDT mode. Rev.7.00 Oct. 10, 2008 Page 551 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.2 14.2.1 Register Descriptions (SH7750, SH7750S) DMA Source Address Registers 0–3 (SAR0–SAR3) Bit: 31 30 29 28 27 26 25 24 Initial value: R/W: Bit: — R/W 23 — R/W — R/W — R/W — R/W — R/W — R/W — R/W 0 ············································· Initial value: R/W: — R/W ············································· ············································· — R/W DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that specify the source address of a DMA transfer. These registers have a counter feedback function, and during a DMA transfer they indicate the next source address. In single address mode, the SAR value is ignored when an external device with DACK has been specified as the transfer source. Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will be detected and the DMAC will halt. The initial value of these registers after a power-on or manual reset is undefined. They retain their values in standby mode and deep sleep mode. When transfer is performed from memory to an external device with DACK in DDT mode, DTR format [31:0] is set in SAR0 [31:0]. For details, see Data Transfer Request Format in section 14.5.2, Pin in DDT Mode. Rev.7.00 Oct. 10, 2008 Page 552 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) Bit: 31 30 29 28 27 26 25 24 Initial value: R/W: Bit: — R/W 23 — R/W — R/W — R/W — R/W — R/W — R/W — R/W 0 ············································· Initial value: R/W: — R/W ············································· ············································· — R/W DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. These registers have a counter feedback function, and during a DMA transfer they indicate the next destination address. In single address mode, the DAR value is ignored when a device with DACK has been specified as the transfer destination. Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will be detected and the DMAC will halt. The initial value of these registers after a power-on or manual reset is undefined. They retain their values in standby mode and deep sleep mode. When transfer is performed from an external device with DACK to memory in DDT mode, DTR format [31:0] is set in DAR0 [31:0]. For details, see Data Transfer Request Format in section 14.5.2, Pin in DDT Mode. Notes: 1. When a 16-bit, 32-bit, 64-bit, or 32-byte boundary address is specified, take care with the setting of bit 0, bits 1–0, bits 2–0, or bits 4–0, respectively. If an address specification that ignores boundary considerations is made, the DMAC will detect an address error and halt operation on all channels (DMAOR: address error flag AE = 1). The DMAC will also detect an address error and halt if an area 7 address is specified in a data transfer employing the external bus, or if the address of a nonexistent on-chip peripheral module is specified. 2. External addresses are 29-bit. As SAR[31:29] and DAR[31:29] are not used in DMA transfers, settings of SAR[31:29] = 000 and DAR[31:29] = 000 are recommended. Rev.7.00 Oct. 10, 2008 Page 553 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) Bit: 31 30 29 28 27 26 25 24 Initial value: R/W: Bit: 0 R 23 0 R 22 0 R 21 0 R 20 0 R 19 0 R 18 0 R 17 0 R 16 Initial value: R/W: Bit: — R/W 15 — R/W 14 — R/W 13 — R/W 12 — R/W 11 — R/W 10 — R/W 9 — R/W 8 Initial value: R/W: Bit: — R/W 7 — R/W 6 — R/W 5 — R/W 4 — R/W 3 — R/W 2 — R/W 1 — R/W 0 Initial value: R/W: — R/W — R/W — R/W — R/W — R/W — R/W — R/W — R/W DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 32-bit readable/writable registers that specify the transfer count for the corresponding channel (byte count, word count, longword count, quadword count, or 32-byte count). Specifying H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 16,777,216 (16M) transfers. During DMAC operation, the remaining number of transfers is shown. Bits 31–24 of these registers are reserved; they are always read as 0, and should only be written with 0. The initial value of these registers after a power-on or manual reset is undefined. They retain their values in standby mode and deep sleep mode. In DDT mode, settings to DMATCR0[7:0] may be made from DTR format [55:48] as well. For details, see Data Transfer Request Format in section 14.5.2, Pin in DDT Mode. Rev.7.00 Oct. 10, 2008 Page 554 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) Bit: 31 SSA2 Initial value: R/W: Bit: 0 R/W 23 — Initial value: R/W: Bit: 0 R 15 DM1 Initial value: R/W: Bit: 0 R/W 7 TM Initial value: R/W: 0 R/W 30 SSA1 0 R/W 22 — 0 R 14 DM0 0 R/W 6 TS2 0 R/W 29 SSA0 0 R/W 21 — 0 R 13 SM1 0 R/W 5 TS1 0 R/W 28 STC 0 R/W 20 — 0 R 12 SM0 0 R/W 4 TS0 0 R/W 27 DSA2 0 R/W 19 DS 0 R/W 11 RS3 0 R/W 3 — 0 R 26 DSA1 0 R/W 18 RL 0 (R/W) 10 RS2 0 R/W 2 IE 0 R/W 25 DSA0 0 R/W 17 AM 0 R/W 9 RS1 0 R/W 1 TE 0 R/(W) 24 DTC 0 R/W 16 AL 0 (R/W) 8 RS0 0 R/W 0 DE 0 R/W Note: The TE bit can only be written with 0 after being read as 1, to clear the flag. The RL, AM, AL, and DS bits may be absent, depending on the channel. DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that specify the operating mode, transfer method, etc., for each channel. Bits 31–28 and 27–24 indicate the source address and destination address, respectively; these settings are only valid when the transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA interface space. In other cases, these bits should be cleared to 0. For details of the PCMCIA interface, see section 13.3.7, PCMCIA Interface, in section 13, Bus State Controller (BSC). In DDT mode, CHCR0 is set according to the DTR format. (The following settings are fixed: CHCR0 [31:24] = 0, [18:16] = 0, [15:14] = 01, [13:12] = 01, [2] = 0, [1] = 0, [0] = 1) Bits 18 and 16 are not present in CHCR2 and CHCR3. In CHCR2 and CHCR3, these bits cannot be modified (a write value of 0 should always be used) and are always read as 0. Rev.7.00 Oct. 10, 2008 Page 555 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) These registers are initialized to H'00000000 by a power-on or manual reset. They retain their values in standby mode and deep sleep mode. Bits 31 to 29—Source Address Space Attribute Specification (SSA2–SSA0): These bits specify the space attribute for access to a PCMCIA interface area. Bit 31: SSA2 0 Bit 30: SSA1 0 Bit 29: SSA0 0 1 1 0 1 1 0 0 1 1 0 1 Description Reserved in PCMCIA access Dynamic bus sizing I/O space 8-bit I/O space 16-bit I/O space 8-bit common memory space 16-bit common memory space 8-bit attribute memory space 16-bit attribute memory space (Initial value) Bit 28—Source Address Wait Control Select (STC): Specifies CS5 or CS6 space wait cycle control for access to a PCMCIA interface area. This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control. Bit 28: STC 0 Description C5 space wait cycle selection (Initial value) Settings of bits A5W2–A5W0 in wait control register 2 (WCR2), and bits A5PCW1–A5PCW0, A5TED2–A5TED0, and A5TEH2–A5TEH0 in the PCMCIA control register (PCR), are selected 1 C6 space wait cycle selection Settings of bits A6W2–A6W0 in wait control register 2 (WCR2), and bits A6PCW1–A6PCW0, A6TED2–A6TED0, and A6TEH2–A6TEH0 in the PCMCIA control register (PCR), are selected Note: For details, see section 13.3.7, PCMCIA Interface. Rev.7.00 Oct. 10, 2008 Page 556 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Bits 27 to 25—Destination Address Space Attribute Specification (DSA2–DSA0): These bits specify the space attribute for access to a PCMCIA interface area. Bit 27: DSA2 0 Bit 26: DSA1 0 Bit 25: DSA0 0 1 1 0 1 1 0 0 1 1 0 1 Description Reserved in PCMCIA access Dynamic bus sizing I/O space 8-bit I/O space 16-bit I/O space 8-bit common memory space 16-bit common memory space 8-bit attribute memory space 16-bit attribute memory space (Initial value) Bit 24—Destination Address Wait Control Select (DTC): Specifies CS5 or CS6 space wait cycle control for access to a PCMCIA interface area. This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control. Bit 24: DTC 0 Description C5 space wait cycle selection (Initial value) Settings of bits A5W2–A5W0 in wait control register 2 (WCR2), and bits A5PCW1–A5PCW0, A5TED2–A5TED0, and A5TEH2–A5TEH0 in the PCMCIA control register (PCR), are selected 1 C6 space wait cycle selection Settings of bits A6W2–A6W0 in wait control register 2 (WCR2), and bits A6PCW1–A6PCW0, A6TED2–A6TED0, and A6TEH2–A6TEH0 in the PCMCIA control register (PCR), are selected Note: For details, see section 13.3.7, PCMCIA Interface. Bits 23 to 20—Reserved: These bits are always read as 0, and should only be written with 0. Rev.7.00 Oct. 10, 2008 Page 557 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Bit 19—DREQ Select (DS): Specifies either low level detection or falling edge detection as the sampling method for the DREQ pin used in external request mode. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0–CHCR3. Bit 19: DS 0 1 Description Low level detection Falling edge detection (Initial value) Notes: Level detection burst mode when TM = 1 and DS = 0 Edge detection burst mode when TM = 1 and DS = 1 Bit 18—Request Check Level (RL): Selects whether the DRAK signal (that notifies an external device of the acceptance of DREQ) is an active-high or active-low output. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is invalid. Bit 18: RL 0 1 Description DRAK is an active-high output DRAK is an active-low output (Initial value) Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the data read cycle or write cycle. In single address mode, DACK is always output regardless of the setting of this bit. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is valid for CHCR1 to CHCR3 in the SH7750. In the SH7750S, this bit is valid for CHCR0 to CHCR3. (DDT mode: TDACK) Bit 17: AM 0 1 Description DACK is output in read cycle DACK is output in write cycle (Initial value) Rev.7.00 Oct. 10, 2008 Page 558 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or active-low. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is invalid. Bit 16: AL 0 1 Description Active-high output Active-low output (Initial value) Bits 15 and 14—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify incrementing/decrementing of the DMA transfer destination address. The specification of these bits is ignored when data is transferred from external memory to an external device in single address mode. For channel 0, in DDT mode these bits are set to DM1 = 0 and DM0 = 1 with the DTR format. Bit 15: DM1 0 Bit 14: DM0 0 1 Description Destination address fixed (Initial value) Destination address incremented (+1 in 8-bit transfer, +2 in 16bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32byte burst transfer) Destination address decremented (–1 in 8-bit transfer, –2 in 16bit transfer, –4 in 32-bit transfer, –8 in 64-bit transfer, –32 in 32byte burst transfer) Setting prohibited 1 0 1 Rev.7.00 Oct. 10, 2008 Page 559 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Bits 13 and 12—Source Address Mode 1 and 0 (SM1, SM0): These bits specify incrementing/decrementing of the DMA transfer source address. The specification of these bits is ignored when data is transferred from an external device to external memory in single address mode. For channel 0, in DDT mode these bits are set to SM1 = 0 and SM0 = 1 with the DTR format. Bit 13: SM1 0 Bit 12: SM0 0 1 Description Source address fixed (Initial value) Source address incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32byte burst transfer) Source address decremented (–1 in 8-bit transfer, –2 in 16-bit transfer, –4 in 32-bit transfer, –8 in 64-bit transfer, –32 in 32byte burst transfer) Setting prohibited 1 0 1 Rev.7.00 Oct. 10, 2008 Page 560 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source. Bit 11: Bit 10: Bit 9: RS3 RS2 RS1 0 0 0 Bit 8: RS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description External request, dual address mode*1 *4 (external address space → external address space) (Initial value) Setting prohibited External request, single address mode 134 External address space → external device* * * External request, single address mode 134 External device → external address space* * * Auto-request (external address space → external address 2 space)* Auto-request (external address space → on-chip peripheral module)*2 Auto-request (on-chip peripheral module → external address 2 space)* Setting prohibited SCI transmit-data-empty interrupt transfer request 2 (external address space → SCTDR1)* SCI receive-data-full interrupt transfer request 2 (SCRDR1 → external address space)* SCIF transmit-data-empty interrupt transfer request (external address space → SCFTDR2)*2 SCIF receive-data-full interrupt transfer request 2 (SCFRDR2 → external address space)* TMU channel 2 (input capture interrupt, external address space → external address space)*2 TMU channel 2 (input capture interrupt, external address space → on-chip peripheral module)*2 TMU channel 2 (input capture interrupt, on-chip peripheral module → external address space)*2 Setting prohibited Notes: 1. External request specifications are valid only for channels 0 and 1. Requests are not accepted for channels 2 and 3 in normal DMA mode. 2. Dual address mode 3. In DDT mode, selection is possible with the DTR format [60] (R/W bit) and [57-56] (MD1, MD0 bits) specification for channel 0 only. 4. In DDT mode: Rev.7.00 Oct. 10, 2008 Page 561 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) [SH7750] An external request specification should be set for channels 1 to 3. For channel 0, only single address mode can be set with the DTR format. [SH7750S] An external request specification can be set for channels 0 to 3. Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer. Bit 7: TM 0 1 Description Cycle steal mode Burst mode (Initial value) Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size. For external memory access, the setting of these bits serves as the access size in section 13.3, Operation. For register access, the setting of these bits is the size in which the register is accessed. Bit 6: TS2 0 Bit 5: TS1 0 Bit 4: TS0 0 1 1 0 1 1 0 0 Description Quadword size (64-bit) specification (Initial value) Byte size (8-bit) specification Word size (16-bit) specification Longword size (32-bit) specification 32-byte block transfer specification Bit 3—Reserved: This bit is always read as 0, and should only be written with 0. Bit 2—Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated after the number of data transfers specified in DMATCR (when TE = 1). Bit 2: IE 0 1 Description Interrupt request not generated after number of transfers specified in DMATCR (Initial value) Interrupt request generated after number of transfers specified in DMATCR Rev.7.00 Oct. 10, 2008 Page 562 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1, the transfer enabled state is not entered even if the DE bit is set to 1. Bit 1: TE 0 Description Number of transfers specified in DMATCR not completed [Clearing conditions] • • 1 When 0 is written to TE after reading TE = 1 In a power-on or manual reset, and in standby mode (Initial value) Number of transfers specified in DMATCR completed Bit 0—DMAC Enable (DE): Enables operation of the corresponding channel. Bit 0: DE 0 1 Description Operation of corresponding channel is disabled Operation of corresponding channel is enabled (Initial value) When auto-request is specified (with RS3–RS0), transfer is begun when this bit is set to 1. In the case of an external request or on-chip peripheral module request, transfer is begun when a transfer request is issued after this bit is set to 1. Transfer can be suspended midway by clearing this bit to 0. Even if the DE bit has been set, transfer is not enabled when TE is 1, when DME in DMAOR is 0, or when the NMIF or AE bit in DMAOR is 1. For channel 0, in DDT mode this bit is set to 1 when a DTR format is received. DE remains set to 1 even if TE is set to 1. When the mode is switched from DDT mode to normal DMA mode (DDT bit = 0 in DMAOR), the DE bit must be cleared to 0. Rev.7.00 Oct. 10, 2008 Page 563 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.2.5 DMA Operation Register (DMAOR) Bit: 31 — Initial value: R/W: Bit: 0 R 23 — Initial value: R/W: Bit: 0 R 15 DDT Initial value: R/W: Bit: 0 R/W 7 — Initial value: R/W: 0 R 30 — 0 R 22 — 0 R 14 — 0 R 6 — 0 R 29 — 0 R 21 — 0 R 13 — 0 R 5 — 0 R 28 — 0 R 20 — 0 R 12 — 0 R 4 COD 0 R/(W) 27 — 0 R 19 — 0 R 11 — 0 R 3 — 0 R 26 — 0 R 18 — 0 R 10 — 0 R 2 AE 0 R/(W) 25 — 0 R 17 — 0 R 9 PR1 0 R/W 1 NMIF 0 R/(W) 24 — 0 R 16 — 0 R 8 PR0 0 R/W 0 DME 0 R/W Notes: The AE and NMIF bits can only be written with 0 after being read as 1, to clear the flags. The COD bit can be written to in the SH7750S only. DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode. DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in standby mode and deep sleep mode. Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0. Rev.7.00 Oct. 10, 2008 Page 564 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode. Bit 15: DDT 0 1 Description Normal DMA mode On-demand data transfer mode (Initial value) Note: BAVL (DRAK0) is an active-high output in normal DMA mode. When the DDT bit is set to 1, the BAVL pin function is enabled and this pin becomes an active-low output. Bits 14 to 10—Reserved: These bits are always read as 0, and should only be written with 0. Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously. Bit 9: PR1 0 Bit 8: PR0 0 1 1 0 1 Description CH0 > CH1 > CH2 > CH3 CH0 > CH2 > CH3 > CH1 CH2 > CH0 > CH1 > CH3 Round robin mode (Initial value) Bits 7 to 5—Reserved: These bits are always read as 0, and should only be written with 0. Bit 4 (SH7750S)—Check Overrun for DREQ (COD): When this bit is set to 1, cancellation of an accepted DREQ acceptance flag is enabled. When cancellation of an accepted DREQ acceptance flag is enabled by setting COD to 1, clear CHCRn.DS to 0 and then negate DREQ (to the high level). For details, see External Request Mode in section 14.3.2, DMA Transfer Requests. Bit 4: COD 0 1 Description DREQ acceptance flag cancellation disabled DREQ acceptance flag cancellation enabled (Initial value) Note: When external request mode is used in the SH7750S, recommend setting COD to 1 permanently. Bit 4 (SH7750)—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Reserved: This bit is always read as 0, and should only be written with 0. Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an Rev.7.00 Oct. 10, 2008 Page 565 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be cleared by writing 0 after reading 1. Bit 2: AE 0 Description No address error, DMA transfer enabled [Clearing condition] When 0 is written to AE after reading AE = 1 1 Address error, DMA transfer disabled [Setting condition] When an address error is caused by the DMAC (Initial value) Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing 0 after reading 1. Bit 1: NMIF 0 Description No NMI input, DMA transfer enabled [Clearing condition] When 0 is written to NMIF after reading NMIF = 1 1 NMI input, DMA transfer disabled [Setting condition] When an NMI interrupt is generated (Initial value) Bit 0—DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are suspended. Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or when the NMI or AE bit in DMAOR is 1. Bit 0: DME 0 1 Description Operation disabled on all channels Operation enabled on all channels (Initial value) Rev.7.00 Oct. 10, 2008 Page 566 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.3 Operation When a DMA transfer request is issued, the DMAC starts the transfer according to the predetermined channel priority order. It ends the transfer when the transfer end conditions are satisfied. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. There are two modes for DMA transfer: single address mode and dual address mode. Either burst mode or cycle steal mode can be selected as the bus mode. 14.3.1 DMA Transfer Procedure After the desired transfer conditions have been set in the DMA source address register (SAR), DMA destination address register (DAR), DMA transfer count register (DMATCR), DMA channel control register (CHCR), and DMA operation register (DMAOR), the DMAC transfers data according to the following procedure: 1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0). 2. When a transfer request is issued and transfer has been enabled, the DMAC transfers one transfer unit of data (determined by the setting of TS2–TS0). In auto-request mode, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value is decremented by 1 for each transfer. The actual transfer flow depends on the address mode and bus mode. 3. When the specified number of transfers have been completed (when the DMATCR value reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DMTE interrupt request is sent to the CPU. 4. If a DMAC address error or NMI interrupt occurs, the transfer is suspended. Transfer is also suspended when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. In the event of an address error, a DMAE interrupt request is forcibly sent to the CPU. Figure 14.2 shows a flowchart of this procedure. Note: If transfer request is issued while transfer is disabled, the transfer enable wait state (transfer suspended state) is entered. Transfer is started when subsequently enabled (by setting DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0) Rev.7.00 Oct. 10, 2008 Page 567 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1? Yes Illegal address check (reflected in AE bit) No *4 NMIF, AE, TE = 0? Yes Transfer request issued? *1 Yes Transfer (1 transfer unit) DMATCR - 1 → DMATCR Update SAR, DAR No *2 No *3 Bus mode, transfer request mode, DREQ detection method DMATCR = 0? Yes No NMIF or AE = 1 or DE = 0 or DME = 0? Yes Transfer suspended No DMTE interrupt request (when IE = 1) NMIF or AE = 1 or DE = 0 or DME = 0? Yes End of transfer No Normal end Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0, and the DE and DME bits are set to 1. 2. DREQ level detection (external request) in burst mode, or cycle steal mode. 3. DREQ edge detection (external request) in burst mode, or auto-request mode in burst mode. 4. An illegal address is detected by comparing bits TS2–TS0 in CHCRn with SARn and DARn. Figure 14.2 DMAC Transfer Flowchart Rev.7.00 Oct. 10, 2008 Page 568 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.3.2 DMA Transfer Requests DMA transfer requests are basically generated at either the data transfer source or destination, but they can also be issued by external devices or on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. The transfer request mode is selected by means of bits RS3–RS0 in DMA channel control registers 0–3 (CHCR0–CHCR3). Auto Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bit in CHCR0–CHCR3 and the DME bit in the DMA operation register (DMAOR) are set to 1, the transfer begins (so long as the TE bit in CHCR0–CHCR3 and the NMIF and AE bits in DMAOR are all 0). External Request Mode: In this mode a transfer is performed in response to a transfer request signal (DREQ) from an external device. One of the modes shown in table 14.4 should be chosen according to the application system. If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), transfer starts when DREQ is input. The DS bit in CHCR0/CHCR1 is used to select either falling edge detection or low level detection for the DREQ signal (level detection when DS = 0, edge detection when DS = 1). DREQ is accepted after a power-on reset if TE = 0, NMIF = 0, and AE = 0, but transfer is not executed if DMA transfer is not enabled (DE = 0 or DME = 0). In this case, DMA transfer is started when enabled (by setting DE = 1 and DME = 1). Rev.7.00 Oct. 10, 2008 Page 569 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Table 14.4 Selecting External Request Mode with RS Bits RS3 0 RS2 0 RS1 0 RS0 0 Address Mode Dual address mode Transfer Source External memory or memory-mapped external device, or external device with DACK External memory or memory-mapped external device External device with DACK Transfer Destination External memory or memory-mapped external device, or external device with DACK External device with DACK External memory or memory-mapped external device 1 0 Single address mode Single address mode 1 • External Request Acceptance Conditions 1. When at least one of DMAOR.DME and CHCR.DE is 0, and DMAOR.NMIF, DMAOR.AE, and CHCR.TE are all 0, if an external request (DREQ: edge-detected) is input it will be held inside the DMAC until DMA transfer is either executed or canceled. Since DMA transfer is not enabled in this case (DME = 0 or DE = 0), DMA transfer is not initiated. DMA transfer is started after it is enabled (DME = 1, DE = 1, DMAOR.NMIF = 0, DMAOR.AE = 0, CHCR.TE = 0). 2. When DMA transfer is enabled (DME = 1, DE = 1, DMAOR.NMIF = 0, DMAOR.AE = 0, CHCR.TE = 0), if an external request (DREQ) is input, DMA transfer is started. 3. An external request (DREQ) will be ignored if input when CHCR.TE = 1, DMAOR.NMIF = 1, or DMAOR.AE = 1, or during a power-on reset or manual reset, in deep sleep mode or standby mode, or while the DMAC is in the module standby state. 4. A previously input external request will be canceled by the occurrence of an NMI interrupt (DMAOR.NMIF = 1) or address error (DMAOR.AE = 1), or by a power-on reset or manual reset. In the SH7750S, it is possible to cancel a previously input external request (DREQ). With DMAOR.COD set to 1, clear CHCRn.DS to 0 and then drive the DREQ pin high. On the SH7750R, it is possible to cancel an external request that has been accepted by external request (DREQ) edge detection by first negating DREQ and then clearing CHCR.DS from 1 to 0. Afterwards CHCR.DS should be reset to 1 and DREQ asserted. (The SH7750R has no DMAOR.COD bit, but it is possible to cancel an external request that has been accepted by external request (DREQ) edge detection, as is the case when the DMAOR.COD bit of the SH7750S is set to 1.) Rev.7.00 Oct. 10, 2008 Page 570 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) • Usage Notes An external request (DREQ) is detected by a low level or falling edge. Ensure that the external request (DREQ) signal is held high when there is no DMA transfer request from an external device after a power-on reset or manual reset. When DMA transfer is restarted, check whether a DMA transfer request is being held. On-Chip Peripheral Module Request Mode: In this mode a transfer is performed in response to a transfer request signal (interrupt request signal) from an on-chip peripheral module. As shown in table 14.5, there are seven transfer request signals: input capture interrupts from the timer unit (TMU), and receive-data-full interrupts (RXI) and transmit-data-empty interrupts (TXI) from the two serial communication interfaces (SCI, SCIF). If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), transfer starts when a transfer request signal is input. The source of the transfer request does not have to be the data transfer source or destination. However, when the transfer request is set to RXI (transfer request by SCI/SCIF receive-data-full interrupt), the transfer source must be the SCI/SCIF's receive data register (SCRDR1/SCFRDR2). When the transfer request is set to TXI (transfer request by SCI/SCIF transmit-data-empty interrupt), the transfer destination must be the SCI/SCIF's transmit data register (SCTDR1/SCFTDR2). Rev.7.00 Oct. 10, 2008 Page 571 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits DMAC Transfer DMAC Transfer RS3 RS2 RS1 RS0 Request Source Request Signal 1 0 0 0 SCI transmitter SCTDR1 (SCI transmit-dataempty transfer request) SCRDR1 (SCI receive-data-full transfer request) SCFTDR2 (SCIF transmit-dataempty transfer request) SCFRDR2 (SCIF receive-data-full transfer request) Input capture occurrence Input capture occurrence Input capture occurrence Transfer Source External* Transfer Destination Bus Mode SCTDR1 Cycle steal mode 1 SCI receiver SCRDR1 External* Cycle steal mode Cycle steal mode 1 0 SCIF transmitter External* SCFTDR2 1 SCIF receiver SCFRDR2 External* Cycle steal mode Burst/cycle steal mode Burst/cycle steal mode Burst/cycle steal mode 1 0 0 1 TMU channel 2 TMU channel 2 TMU channel 2 External* External* External* On-chip peripheral 1 0 On-chip External* peripheral Legend: TMU: Timer unit SCI: Serial communication interface SCIF: Serial communication interface with FIFO Notes: 1. SCI/SCIF burst transfer setting is prohibited. 2. If input capture interrupt acceptance is set for multiple channels and DE = 1 for each channel, processing will be executed on the highest-priority channel in response to a single input capture interrupt. 3. A DMA transfer request by means of an input capture interrupt can be canceled by setting TCR2.ICPE1 = 0 and ICPE0 = 0 in the TMU. * External memory or memory-mapped external device To output a transfer request from an on-chip peripheral module, set the DMA transfer request enable bit for that module and output a transfer request signal. For details, see sections 12, Timer Unit (TMU), 15, Serial Communication Interface (SCI), and 16, Serial Communication Interface with FIFO (SCIF). Rev.7.00 Oct. 10, 2008 Page 572 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) When a DMA transfer corresponding to a transfer request signal from an on-chip peripheral module shown in table 14.5 is carried out, the signal is discontinued automatically. This occurs every transfer in cycle steal mode, and in the last transfer in burst mode. 14.3.3 Channel Priorities If the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority system, either in a fixed mode or round robin mode. The mode is selected with priority bits PR1 and PR0 in the DMA operation register (DMAOR). Fixed Mode: In this mode, the relative channel priorities remain fixed. The following priority orders are available in fixed mode: • CH0 > CH1 > CH2 > CH3 • CH0 > CH2 > CH3 > CH1 • CH2 > CH0 > CH1 > CH3 The priority order is selected with bits PR1 and PR0 in DMAOR. Round Robin Mode: In round robin mode, each time the transfer of one transfer unit (byte, word, longword, quadword, or 32 bytes) ends on a given channel, that channel is assigned the lowest priority level. This is illustrated in figure 14.3. The order of priority in round robin mode immediately after a reset is CH0 > CH1 > CH2 > CH3. Note: In round robin mode, if no transfer request is accepted for any channel during DMA transfer, the priority order becomes CH0 > CH1 > CH2 > CH3. Rev.7.00 Oct. 10, 2008 Page 573 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Transfer on channel 0 Initial priority order CH0 > CH1 > CH2 > CH3 Channel 0 is given the lowest priority. Priority order after transfer CH1 > CH2 > CH3 > CH0 Transfer on channel 1 Initial priority order CH0 > CH1 > CH2 > CH3 Priority order after transfer Transfer on channel 2 Initial priority order CH2 > CH3 > CH0 > CH1 When channel 1 is given the lowest priority, the priority of channel 0, which was higher than channel 1, is also shifted simultaneously. CH0 > CH1 > CH2 > CH3 Priority order after transfer CH3 > CH0 > CH1 > CH2 Priority after transfer due to issuance of a transfer request for channel 1 only. Transfer on channel 3 Initial priority order When channel 2 is given the lowest priority, the priorities of channels 0 and 1, which were higher than channel 2, are also shifted simultaneously. If there is a transfer request for channel 1 only immediately afterward, channel 1 is given the lowest priority and the priorities of channels 3 and 0 are simultaneously shifted down. CH2 > CH3 > CH0 > CH1 CH0 > CH1 > CH2 > CH3 No change in priority order Priority order after transfer CH0 > CH1 > CH2 > CH3 Figure 14.3 Round Robin Mode Figure 14.4 shows the changes in priority levels when transfer requests are issued simultaneously for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The operation of the DMAC in this case is as follows. Rev.7.00 Oct. 10, 2008 Page 574 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 1. Transfer requests are issued simultaneously for channels 0 and 3. 2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed first (channel 3 is on transfer standby). 3. A transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on transfer standby). 4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level. 5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer is started (channel 3 is on transfer standby). 6. At the end of the channel 1 transfer, channel 1 shifts to the lowest priority level. 7. The channel 3 transfer is started. 8. At the end of the channel 3 transfer, the channel 3 and channel 2 priority levels are lowered, giving channel 3 the lowest priority. Transfer request 1. Issued for channels 0 and 3 3. Issued for channel 1 Channel waiting DMAC operation Channel priority order 0>1>2>3 3 2. Start of channel 0 transfer Change of priority order 1, 3 4. End of channel 0 transfer 1>2>3>0 5. Start of channel 1 transfer 3 6. End of channel 1 transfer Change of priority order 2>3>0>1 7. Start of channel 3 transfer None Change of priority order 8. End of channel 3 transfer 0>1>2>3 Figure 14.4 Example of Changes in Priority Order in Round Robin Mode Rev.7.00 Oct. 10, 2008 Page 575 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.3.4 Types of DMA Transfer The DMAC supports the transfers shown in table 14.6. It can operate in single address mode, in which either the transfer source or the transfer destination is accessed using the acknowledge signal, or in dual address mode, in which both the transfer source and transfer destination addresses are output. The actual transfer operation timing depends on the bus mode, which can be either burst mode or cycle steal mode. Table 14.6 Supported DMA Transfers Transfer Destination Transfer Source External device with DACK External memory Memory-mapped external device On-chip peripheral module External Device with DACK Not available Single address mode Single address mode Not available External Memory Single address mode Dual address mode Dual address mode Dual address mode Memory-Mapped External Device Single address mode On-Chip Peripheral Module Not available Dual address mode Dual address mode Dual address mode Dual address mode Dual address mode Not available Rev.7.00 Oct. 10, 2008 Page 576 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Address Modes Single Address Mode: In single address mode, both the transfer source and the transfer destination are external; one is accessed by the DACK signal and the other by an address. In this mode, the DMAC performs a DMA transfer in one bus cycle by simultaneously outputting the external device strobe signal (DACK) to either the transfer source or transfer destination external device to access it, while outputting an address to the other side of the transfer. Figure 14.5 shows an example of a transfer between external memory and an external device with DACK in which the external device outputs data to the data bus and that data is written to external memory in the same bus cycle. External address bus SH7750, SH7750S, SH7750R DMAC External data bus External memory External device with DACK DACK Legend: : Data flow DREQ Figure 14.5 Data Flow in Single Address Mode Two types of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. Only the external request signal (DREQ) is used in both these cases. Figure 14.6 shows the DMA transfer timing for single address mode. The access timing depends on the type of external memory. For details, see the descriptions of the memory interfaces in section 13, Bus State Controller (BSC). Rev.7.00 Oct. 10, 2008 Page 577 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CKIO A28–A0 CSn D63–D0 DACK WE Data output from external device with DACK DACK signal to external device with DACK WE signal to external memory space Address output to external memory space (a) From external device with DACK to external memory space CKIO A28–A0 CSn D63–D0 RD DACK Data output from external memory space RD signal to external memory space DACK signal to external device with DACK (b) From external memory space to external device with DACK Address output to external memory space Figure 14.6 DMA Transfer Timing in Single Address Mode Dual Address Mode: Dual address mode is used to access both the transfer source and the transfer destination by address. The transfer source and destination can be accessed by either onchip peripheral module or external address. Even if the operand cache is used in RAM mode, the RAM cannot be set as the transfer source or transfer destination. Rev.7.00 Oct. 10, 2008 Page 578 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) In dual address mode, data corresponding to the size specified by CHCRn.TS is read from the transfer source in the data read cycle, and, in the data write cycle, it is transferred in two bus cycles in order to write in the transfer destination the data corresponding to the size specified by CHCRn.TS. In this process, the transfer data is temporarily stored in the data buffer in the bus state controller (BSC). In a transfer between external memories such as that shown in figure 14.7, data is read from external memory into the BSC's data buffer in the read cycle, then written to the other external memory in the write cycle. Figure 14.8 shows the timing for this operation. The DACK output timing is the same as that of CSn in a read or write cycle specified by the CHCRn.AM bit. SAR Address bus Memory Data bus DMAC DAR Transfer source module Transfer destination module BSC Data buffer Taking the SAR value as the address, data is read from the transfer source module and stored temporarily in the data buffer in the bus state controller (BSC). 1st bus cycle SAR Address bus Memory Data bus DMAC DAR Transfer source module Transfer destination module BSC Data buffer Taking the DAR value as the address, the data stored in the BSC's data buffer is written to the transfer destination module. 2nd bus cycle Figure 14.7 Operation in Dual Address Mode Rev.7.00 Oct. 10, 2008 Page 579 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CKIO A26–A0 CSn D63–D0 RD WE DACK Transfer source address Transfer destination address Data read cycle (1st cycle) Data write cycle (2nd cycle) Transfer from external memory space to external memory space Figure 14.8 Example of Transfer Timing in Dual Address Mode Bus Modes There are two bus modes, cycle steal mode and burst mode, selected with the TM bit in CHCR0– CHCR3. Cycle Steal Mode: In cycle steal mode, the DMAC releases the bus to the CPU at the end of each transfer-unit (8-bit, 16-bit, 32-bit, 64-bit, or 32-byte) transfer. When the next transfer request is issued, the DMAC reacquires the bus from the CPU and carries out another transfer-unit transfer. At the end of this transfer, the bus is again given to the CPU. This is repeated until the transfer end condition is satisfied. Cycle steal mode can be used with all categories of transfer request source, transfer source, and transfer destination. Rev.7.00 Oct. 10, 2008 Page 580 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Figure 14.9 shows an example of DMA transfer timing in cycle steal mode. The transfer conditions in this example are dual address mode and DREQ level detection. DREQ Bus returned to CPU Bus cycle CPU CPU CPU DMAC Read DMAC Write CPU DMAC Read DMAC Write CPU CPU Figure 14.9 Example of DMA Transfer in Cycle Steal Mode Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers data continuously until the transfer end condition is satisfied. With DREQ low level detection in external request mode, however, when DREQ is driven high the bus passes to another bus master after the end of the DMAC transfer request that has already been accepted, even if the transfer end condition has not been satisfied. Figure 14.10 shows an example of DMA transfer timing in burst mode. The transfer conditions in this example are single address mode and DREQ level detection (CHCRn.DS = 0, CHCRn.TM = 1). DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU Figure 14.10 Example of DMA Transfer in Burst Mode Note: Burst mode can be set regardless of the transfer size. A 32-byte block transfer burst mode setting can also be made. Relationship between DMA Transfer Type, Request Mode, and Bus Mode Table 14.7 shows the relationship between the type of DMA transfer, the request mode, and the bus mode. Rev.7.00 Oct. 10, 2008 Page 581 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode Address Mode Single Type of Transfer External device with DACK and external memory External device with DACK and memory-mapped external device Dual External memory and external memory External memory and memory-mapped external device Memory-mapped external device and memory-mapped external device External memory and on-chip peripheral module Memory-mapped external device and on-chip peripheral module Legend: 32B: B: C: External: Internal: Request Mode External External Bus Mode B/C B/C Transfer Size Usable (Bits) Channels 8/16/32/64/32B 0, 1 (2, 3)*6 8/16/32/64/32B 0, 1 (2, 3)*6 Internal*1 External*7 Internal*1 7 External* Internal*1 7 External* Internal*2 Internal*2 B/C B/C 8/16/32/64/32B 0 to 3*5 *6 8/16/32/64/32B 0 to 3*5 *6 B/C 8/16/32/64/32B 0 to 3*5 *6 B/C*3 B/C*3 8/16/32/64*4 8/16/32/64*4 0 to 3*5 *6 0 to 3*5 *6 32-byte burst transfer Burst Cycle steal External request Auto-request or on-chip peripheral module request Notes: 1. External request, auto-request, or on-chip peripheral module request (TMU input capture interrupt request) possible. In the case of an on-chip peripheral module request, it is not possible to specify external memory data transfer with the SCI (SCIF) as the transfer request source. 2. Auto-request, or on-chip peripheral module request possible. If the transfer request source is the SCI (SCIF), either the transfer source must be SCRDR1 (SCFRDR2) or the transfer destination must be SCTDR1 (SCFTDR2). 3. When the transfer request source is the SCI (SCIF), only cycle steal mode can be used. 4. Access size permitted for the on-chip peripheral module register that is the transfer source or transfer destination. 5. When the transfer request is an external request, only channels 0 and 1 can be used. 6. In DDT mode, transfer requests can be accepted for all channels from external devices capable of DTR format output. Rev.7.00 Oct. 10, 2008 Page 582 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 7. See tables 14.8 and 14.9 for the transfer sources and transfer destinations in DMA transfer by means of an external request. (a) Normal DMA Mode Table 14.8 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by this LSI in normal DMA mode. Table 14.8 External Request Transfer Sources and Destinations in Normal DMA Mode Transfer Direction (Settable Memory Interface) Transfer Source 1 2 3 4 5 6 7 8 Synchronous DRAM External device with DACK SRAM-type, DRAM External device with DACK Synchronous DRAM SRAM-type, MPX, PCMCIA SRAM-type, DRAM, PCMCIA, MPX SRAM-type, MPX, PCMCIA * * Transfer Destination External device with DACK Synchronous DRAM External device with DACK SRAM-type, DRAM SRAM-type, MPX, PCMCIA Synchronous DRAM SRAM-type, MPX, PCMCIA SRAM-type, DRAM, PCMCIA, MPX * * Usable Address DMAC Mode Channels Single Single Single Single Dual Dual Dual Dual 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 "SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting. Notes: Memory interfaces on which transfer is possible in single address mode are SRAM, byte control SRAM, burst ROM, DRAM, and synchronous DRAM. When performing dual address mode transfer, make the DACK output setting for the SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface. * DACK output setting in dual address mode transfer (b) DDT Mode Table 14.9 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by this LSI in DDT mode. Rev.7.00 Oct. 10, 2008 Page 583 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Table 14.9 External Request Transfer Sources and Destinations in DDT Mode Transfer Direction (Settable Memory Interface) Transfer Source 1 2 3 4 5 6 Synchronous DRAM* 1 Transfer Destination External device with DACK Synchronous DRAM SRAM-type, MPX, PCMCIA * 2 Usable Address DMAC Mode Channels Single Single * 2 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 External device with DACK Synchronous DRAM SRAM-type, MPX, PCMCIA SRAM-type, DRAM, PCMCIA, MPX SRAM-type, MPX, PCMCIA Dual Dual Synchronous DRAM SRAM-type, MPX, PCMCIA *2 Dual Dual *2 SRAM-type, DRAM, PCMCIA, MPX "SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting. Notes: The only memory interface on which single address mode transfer is possible in DDT mode is synchronous DRAM. When performing dual address mode transfer, make the DACK output setting for the SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface. 1. In SH7750, the bus width must be 64 bits 2. DACK output setting in dual address mode transfer Bus Mode and Channel Priority Order When, for example, channel 1 is transferring data in burst mode, and a transfer request is issued to channel 0, which has a higher priority, the channel 0 transfer is started immediately. If fixed mode has been set for the priority levels (CH0 > CH1), transfer on channel 1 is continued after transfer on channel 0 is completely finished, whether cycle steal mode or burst mode is set for channel 0. If round robin mode has been set for the priority levels, transfer on channel 1 is restarted after one transfer unit of data is transferred on channel 0, whether cycle steal mode or burst mode is set for channel 0. Channel execution alternates in the order: channel 1 → channel 0 → channel 1 → channel 0. An example of round robin mode operation is shown in figure 14.11. Since channel 1 is in burst mode (in the case of edge sensing) regardless of whether fixed mode or round robin mode is set for the priority order, the bus is not released to the CPU until channel 1 transfer ends. Rev.7.00 Oct. 10, 2008 Page 584 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CPU DMAC CH1 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH1 CPU CH0 CPU DMAC channel 1 burst mode CH1 CH0 DMAC channel 1 burst mode CPU DMAC channel 0 and channel 1 round robin mode Legend: Priority system: Round robin mode Channel 0: Cycle steal mode Channel 1: Burst mode (edge-sensing) Figure 14.11 Bus Handling with Two DMAC Channels Operating Note: When channel 1 is in level-sensing burst mode with the settings shown in figure 14.11, the bus is passed to the CPU during a break in requests. 14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus master. See section 13, Bus State Controller (BSC), for details. DREQ Pin Sampling Timing: In external request mode, the DREQ pin is sampled at the rising edge of CKIO clock pulses. When DREQ input is detected, a DMAC bus cycle is generated and DMA transfer executed after four CKIO cycles at the earliest. When falling edge detection is selected for DREQ, the DMAC will recognize DREQ two cycles (CKIO) later because the signal must pass through the asynchronous input synchronization circuit. (There is a 1-cycle (CKIO) delay when low-level detection is selected.) The second and subsequent DREQ sampling operations are performed one cycle after the start of the first DMAC transfer bus cycle (in the case of single address mode). DRAK is output for one cycle only, once each time DREQ is detected, regardless of the transfer mode or DREQ detection method. In the case of burst mode edge detection, DREQ is sampled in the first cycle only, and so DRAK is output in the first cycle only . Rev.7.00 Oct. 10, 2008 Page 585 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Operation: Figures 14.12 to 14.22 show the timing in each mode. 1. Cycle Steal Mode In cycle steal mode, The DREQ sampling timing differs for dual address mode and single address mode, and for level detection and edge detection of DREQ. For example, in figure 14.12 (cycle steal mode, dual address mode, level detection), DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer write cycle. If DREQ is not detected at this time, sampling is executed in every subsequent cycle. In figure 14.13 (cycle steal mode, dual address mode, edge detection), DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. The second sampling operation begins from the cycle in which the first DMAC transfer read cycle ends. If DREQ is not detected at this time, sampling is executed in every subsequent cycle. For details of the timing for various kinds of memory access, see section 13, Bus State Controller (BSC). Figure 14.18 shows the case of cycle steal mode, single address mode, and level detection. In this case, too, transfer is started, at the earliest, four CKIO cycles after the first DREQ sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer bus cycle. Figure 14.19 shows the case of cycle steal mode, single address mode, and edge detection. In this case, transfer is started, at the earliest, five CKIO cycles after the first DREQ sampling operation. The second sampling begins one cycle after the first assertion of DRAK. In single address mode, the DACK signal is output every DMAC transfer cycle. 2. Burst Mode, Dual Address Mode, Level Detection DREQ sampling timing in burst mode using dual address mode and level detection is virtually the same as for cycle steal mode. For example, in figure 14.14, DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer write cycle. In the case of dual address mode transfer initiated by an external request, the DACK signal can be output in either the read cycle or the write cycle of the DMAC transfer according to the specification of the AM bit in CHCR. 3. Burst Mode, Single Address Mode, Level Detection DREQ sampling timing in burst mode using single address mode and level detection is shown in figure 14.20. Rev.7.00 Oct. 10, 2008 Page 586 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) In the example shown in figure 14.20, DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation, and the second sampling operation begins one cycle after the start of the first DMAC transfer bus cycle. In single address mode, the DACK signal is output every DMAC transfer cycle. In figure 14.22, with a 32-byte data size, 64-bit bus width, and SDRAM: row hit write, DMAC transfer begins, at the earliest, six CKIO cycles after the first sampling operation. The second sampling operation begins one cycle after DACK is asserted for the first DMAC transfer. 4. Burst Mode, Dual Address Mode, Edge Detection In burst mode using dual address mode and edge detection, DREQ sampling is performed in the first cycle only. For example, in the case shown in figure 14.15, DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of the number of data transfers set in DMATCR. DREQ is not sampled during this time, and therefore DRAK is output in the first cycle only. In the case of dual address mode transfer initiated by an external request, the DACK signal can be output in either the read cycle or the write cycle of the DMAC transfer according to the specification of the AM bit in CHCR. 5. Burst Mode, Single Address Mode, Edge Detection In burst mode using single address mode and edge detection, DREQ sampling is performed only in the first cycle. For example, in the case shown in figure 14.21, DMAC transfer begins, at the earliest, five cycles after the first sampling operation. DMAC transfer then continues until the end of the number of data transfers set in DMATCR. DREQ is not sampled during this time, and therefore DRAK is output in the first cycle only. In single address mode, the DACK signal is output every DMAC transfer cycle. Suspension of DMA Transfer in Case of DREQ Level Detection With DREQ level detection in burst mode or cycle steal mode, and in dual address mode or single address mode, the external device for which DMA transfer is being executed can judge from the rising edge of CKIO that DARK has been asserted, and suspend DMA transfer by negating DREQ. In this case, the next DARK signal is not output. Rev.7.00 Oct. 10, 2008 Page 587 of 1074 REJ09B0366-0700 CKIO Bus locked Source address Destination address Source address Destination address Bus locked A[25:0] D[63:0] Read Write Read Write Rev.7.00 Oct. 10, 2008 Page 588 of 1074 REJ09B0366-0700 2nd acceptance CPU DMAC CPU DMAC CPU DREQ0 (level detection) 1st acceptance Section 14 Direct Memory Access Controller (DMAC) DREQ1 DRAK0 Bus cycle DACK0 Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle) Legend: : DREQ sampling and determination of channel priority CKIO Bus locked Source address Destination address Source address Destination address Bus locked Source address A[25:0] D[63:0] Read Write Read Write Read DREQ0 (edge detection) 2nd acceptance 3rd acceptance 1st acceptance 4th acceptance DREQ1 DRAK0 Bus cycle DMAC CPU CPU DMAC CPU DMAC DACK0 Legend: Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) Section 14 Direct Memory Access Controller (DMAC) Rev.7.00 Oct. 10, 2008 Page 589 of 1074 REJ09B0366-0700 : DREQ sampling and determination of channel priority CKIO Bus locked Source address Destination address Source address Destination address Bus locked A[25:0] D[63:0] Read Write Read Write Rev.7.00 Oct. 10, 2008 Page 590 of 1074 REJ09B0366-0700 2nd acceptance DMAC-1 DMAC-2 CPU DREQ0 (level detection) 1st acceptance Section 14 Direct Memory Access Controller (DMAC) DREQ1 DRAK0 Bus cycle CPU DACK0 Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle) Legend: : DREQ sampling and determination of channel priority CKIO Bus locked Source address Destination address Source address Destination address Bus locked A[25:0] D[63:0] Read Write Read Write DREQ0 (edge detection) TE bit: transfer end 1st acceptance DREQ1 DRAK0 Bus cycle CPU DMAC-1 DMAC-2 CPU Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) DACK0 Section 14 Direct Memory Access Controller (DMAC) Rev.7.00 Oct. 10, 2008 Page 591 of 1074 REJ09B0366-0700 Legend: : DREQ sampling and determination of channel priority CKIO On-chip peripheral address bus Source address Source address Source address On-chip peripheral data bus Read Read Read Destination address Destination address Destination address Rev.7.00 Oct. 10, 2008 Page 592 of 1074 REJ09B0366-0700 Write Write Write A[25:0] Section 14 Direct Memory Access Controller (DMAC) D[63:0] Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) → External Bus CPU CPU DMAC DMAC CPU DMAC Bus cycle CPU (Bcyc:Pcyc = 1:1) CKIO Source address Source address Source address A[25:0] D[63:0] Read Read Read On-chip peripheral address bus Destination address Destination address Destination address On-chip peripheral data bus Write Write Write T1 T2 T1 T2 T1 T2 Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI (Level Detection) DMAC CPU DMAC CPU DMAC Bus cycle CPU Section 14 Direct Memory Access Controller (DMAC) Rev.7.00 Oct. 10, 2008 Page 593 of 1074 REJ09B0366-0700 (Bcyc:Pcyc = 1:1) CKIO Source address Source address Source address Source address A[25:0] D[63:0] Read Read Read Read Rev.7.00 Oct. 10, 2008 Page 594 of 1074 REJ09B0366-0700 2nd acceptance 3rd acceptance 4th acceptance CPU DMAC CPU DMAC CPU DMAC CPU DMAC CPU DREQ0 (level detection) 1st acceptance Section 14 Direct Memory Access Controller (DMAC) DREQ1 DRAK0 Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection) Bus cycle DACK0 Legend: : DREQ sampling and determination of channel priority CKIO Source address Source address Source address A[25:0] D[63:0] Read Read Read DREQ0 (edge detection) 2nd acceptance 3rd acceptance 1st acceptance DREQ1 DRAK0 Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection) CPU DMAC CPU DMAC CPU DMAC Bus cycle CPU DACK0 Section 14 Direct Memory Access Controller (DMAC) Rev.7.00 Oct. 10, 2008 Page 595 of 1074 REJ09B0366-0700 Legend: : DREQ sampling and determination of channel priority CKIO Source address Source address Source address Source address A[25:0] Rev.7.00 Oct. 10, 2008 Page 596 of 1074 REJ09B0366-0700 Read Read Read Read D[63:0] DREQ0 (level detection) 2nd acceptance 3rd acceptance 1st acceptance 4th acceptance Section 14 Direct Memory Access Controller (DMAC) DREQ1 DRAK0 Bus cycle CPU DMAC-1 DMAC-2 DMAC-3 CPU DMAC-4 Figure 14.20 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection) DACK0 Legend: : DREQ sampling and determination of channel priority CKIO Source address Source address Source address Source address A[25:0] D[63:0] Read Read Read Read DREQ0 (edge detection) 1st acceptance TE bit: transfer end DRAK0 Figure 14.21 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection) CPU DMAC-1 DMAC-2 DMAC-3 DMAC-4 CPU Bus cycle DACK0 Section 14 Direct Memory Access Controller (DMAC) Rev.7.00 Oct. 10, 2008 Page 597 of 1074 REJ09B0366-0700 Legend: : DREQ sampling and determination of channel priority CKIO Destination address Destination address Destination address A[25:0] Rev.7.00 Oct. 10, 2008 Page 598 of 1074 REJ09B0366-0700 D1 D2 D3 D4 D1 D2 D3 D4 D1 D2 D3 D4 D[63:0] DREQ0 (level detection) 1st acceptance 2nd acceptance 3rd acceptance Section 14 Direct Memory Access Controller (DMAC) DREQ1 DRAK0 DMAC-1 CPU Asserted 2 cycles before start of bus cycle Asserted 2 cycles before start of bus cycle Asserted 2 cycles before start of bus cycle DMAC-2 DMAC-3 CPU Bus cycle DACK0 Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection)/32-Byte Block Transfer (Bus Width: 64 Bits, SDRAM: Row Hit Write) Legend: : DREQ sampling and determination of channel priority Section 14 Direct Memory Access Controller (DMAC) 14.3.6 Ending DMA Transfer The conditions for ending DMA transfer are different for ending on individual channels and for ending on all channels together. Except for the case where transfer ends when the value in the DMA transfer count register (DMATCR) reaches 0, the following conditions apply to ending transfer. 1. Cycle Steal Mode (External Request, On-Chip Peripheral Module Request, Auto-Request) When a transfer end condition is satisfied, acceptance of DMAC transfer requests is suspended. The DMAC completes transfer for the transfer requests accepted up to the point at which the transfer end condition was satisfied, then stops. In cycle steal mode, the operation is the same for both edge and level transfer request detection. 2. Burst Mode, Edge Detection (External Request, On-Chip Peripheral Module Request, AutoRequest) The delay between the point at which a transfer end condition is satisfied and the point at which the DMAC actually stops is the same as in cycle steal mode. In burst mode with edge detection, only the first transfer request activates the DMAC, but the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the same as the transfer request sampling timing shown in 4 and 5 under Operation in section 14.3.5, Number of Bus Cycle States and DREQ Pin Sampling Timing. Therefore, a transfer request is regarded as having been issued until a stop request is detected, and the corresponding processing is executed before the DMAC stops. 3. Burst Mode, Level Detection (External Request) The delay between the point at which a transfer end condition is satisfied and the point at which the DMAC actually stops is the same as in cycle steal mode. As in the case of burst mode with edge detection, the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the same as the transfer request sampling timing shown in 2 and 3 under Operation in section 14.3.5, Number of Bus Cycle States and DREQ Pin Sampling Timing. Therefore, a transfer request is regarded as having been issued until a stop request is detected, and the corresponding processing is executed before the DMAC stops. 4. Transfer Suspension Bus Timing Transfer suspension is executed on completion of processing for one transfer unit. In dual address mode transfer, write cycle processing is executed even if a transfer end condition is satisfied during the read cycle, and the transfers covered in 1, 2, and 3 above are also executed before operation is suspended. Rev.7.00 Oct. 10, 2008 Page 599 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Conditions for Ending Transfer on Individual Channels: Transfer ends on the corresponding channel when either of the following conditions is satisfied: • The value in the DMA transfer count register (DMATCR) reaches 0. • The DE bit in the DMA channel control register (CHCR) is cleared to 0. 1. End of transfer when DMATCR = 0 When the DMATCR value reaches 0, DMA transfer ends on the corresponding channel and the transfer end flag (TE) in CHCR is set. If the interrupt enable bit (IE) is set at this time, an interrupt (DMTE) request is sent to the CPU. Transfer ending when DMATCR = 0 does not follow the procedures described in 1 to 4 in section 14.3.6, Ending DMA Transfer. 2. End of transfer when DE = 0 in CHCR When the DMA enable bit (DE) in CHCR is cleared, DMA transfer is suspended on the corresponding channel. The TE bit is not set in this case. Transfer ending in this case follows the procedures described in 1 to 4 in section 14.3.6, Ending DMA Transfer. Conditions for Ending Transfer Simultaneously on All Channels: Transfer ends on all channels simultaneously when either of the following conditions is satisfied: • The address error bit (AE) or NMI flag (NMIF) in the DMA operation register (DMAOR) is set to 1. • The DMA master enable bit (DME) in DMAOR is cleared to 0. 1. End of transfer when AE = 1 in DMAOR If the AE bit in DMAOR is set to 1 due to an address error, DMA transfer is suspended on all channels in accordance with the conditions in 1 to 4 in section 14.3.6, Ending DMA Transfer, and the bus is passed to the CPU. Therefore, when AE is set to 1, the values in the DMA source address register (SAR), DMA destination address register (DAR), and DMA transfer count register (DMATCR) indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. The TE bit is not set in this case. Before resuming transfer, it is necessary to make a new setting for the channel that caused the address error, then write 0 to the AE bit after first reading 1 from it. Acceptance of external requests is suspended while AE is set to 1, so a DMA transfer request must be reissued when resuming transfer. Acceptance of internal requests is also suspended, so when resuming transfer, the DMA transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0 before the new setting is made. Rev.7.00 Oct. 10, 2008 Page 600 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 2. End of transfer when NMIF = 1 in DMAOR If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended on all channels in accordance with the conditions in 1 to 4 in section 14.3.6, Ending DMA Transfer, and the bus is passed to the CPU. Therefore, when NMIF is set to 1, the values in the DMA source address register (SAR), DMA destination address register (DAR), and DMA transfer count register (DMATCR) indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. The TE bit is not set in this case. Before resuming transfer after NMI interrupt handling is completed, 0 must be written to the NMIF bit after first reading 1 from it. As in the case of AE being set to 1, acceptance of external requests is suspended while NMIF is set to 1, so a DMA transfer request must be reissued when resuming transfer. Acceptance of internal requests is also suspended, so when resuming transfer, the DMA transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0 before the new setting is made. 3. End of transfer when DME = 0 in DMAOR If the DME bit in DMAOR is cleared to 0, DMA transfer is suspended on all channels in accordance with the conditions in 1 to 4 in section 14.3.6, Ending DMA Transfer, and the bus is passed to the CPU. The TE bit is not set in this case. When DME is cleared to 0, the values in the DMA source address register (SAR), DMA destination address register (DAR), and DMA transfer count register (DMATCR) indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. When resuming transfer, DME must be set to 1. Operation will then be resumed from the next transfer. Rev.7.00 Oct. 10, 2008 Page 601 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.4 14.4.1 Examples of Use Examples of Transfer between External Memory and an External Device with DACK Examples of transfer of data in external memory to an external device with DACK using DMAC channel 1 are considered here. Table 14.10 shows the transfer conditions and the corresponding register settings. Table 14.10 Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings Transfer Conditions Transfer source: external memory Transfer source: external device with DACK Number of transfers: 32 Transfer source address: decremented Transfer destination address: (setting invalid) Transfer request source: external pin (DREQ1) edge detection Bus mode: burst Transfer unit: word No interrupt request at end of transfer Channel priority order: 2 > 0 > 1 > 3 DMAOR H'00000201 Register SAR1 DAR1 DMATCR1 CHCR1 Set Value H'0C000000 (Accessed by DACK) H'00000020 H'000022A5 Rev.7.00 Oct. 10, 2008 Page 602 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.5 14.5.1 On-Demand Data Transfer Mode (DDT Mode) Operation Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT mode). In DDT mode, it is possible to specify direct single address mode transfer to channel 0 via the data bus and DDT module, and simultaneously issue a transfer request, using the DBREQ, BAVL, TR, TDACK, and ID [1:0] signals between an external device and the DMAC. Figure 14.23 shows a block diagram of the DMAC, DDT, BSC, and an external device (with DBREQ, BAVL, TR, TDACK, ID [1:0], and D [63:0] = DTR pins). DMAC SAR0 DAR0 DMATCR0 CHCR0 DREQ0–3 DDT Memory Data buffer Request ddtmode controller bavl BAVL DBREQ TR Address bus Data bus External device (with DTR DBREQ, BAVL, TR, TDACK, and ID [1:0]) FIFO or memory ddtmode tdack id[1:0] BSC Data buffer TDACK ID[1:0] Figure 14.23 On-Demand Transfer Mode Block Diagram For channels 0 to 3, after making the settings for normal DMA transfer using the CPU, a transfer request can be issued from an external device using the DBREQ, BAVL, TR, TDACK, ID [1:0], and D [63:0] = DTR signals (handshake protocol using the data bus). A transfer request can also be issued simply by asserting TR, without using the external bus (handshake protocol without use of the data bus). For channel 2, after making the DMA transfer settings in the normal way, a transfer request can be issued directly from an external device (with DBREQ, BAVL, TR, TDACK, ID [1:0], and D [63:0] = DTR pins) by asserting DBREQ and TR simultaneously. Note: DTR format = Data transfer request format In DDT mode, there is a choice of five modes for performing DMA transfer. Rev.7.00 Oct. 10, 2008 Page 603 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 1. Normal data transfer mode (channel 0) BAVL (the data bus available signal) is asserted in response to DBREQ (the data bus request signal) from an external device. Two CKIO-synchronous cycles after BAVL is asserted, the external data bus drives the data transfer setting command (DTR command) in synchronization with TR (the transfer request signal). The initial settings are then made in the DMAC channel 0 control register, and the DMA transfer is processed. 2. Normal data transfer mode (channels 1 to 3) In this mode, the data transfer settings are made in the DMAC from the CPU, and DMA transfer requests only are performed from the external device. As in 1 above, DBREQ is asserted from the external device and the external bus is secured, then the DTR format is driven. The transfer request channel can be specified by means of the two ID bits in the DTR format. 3. Handshake protocol using the data bus (valid for channel 0 only) This mode is only valid for channel 0. After the initial settings have been made in the DMAC channel 0 control register by means of normal data transfer mode (channel 0) in the SH7750, or after the initial settings have been made in the DMAC channel 0 control register from the CPU or by means of normal data transfer mode (channel 0) in the SH7750S, the DDT module asserts a data transfer request for the DMAC by setting DTR format ID = 00, MD = 00, and SZ ≠ 101 or 110, and driving the DTR format. 4. Handshake protocol without use of the data bus The DDT module includes a function for recording the previously asserted request channel. By using this function, it is possible to assert a transfer request for the channel for which a request was asserted immediately before, by asserting TR only from an external device after a transfer request has once been made to the channel for which an initial setting has been made in the DMAC control register (DTR format and data transfer setting by the CPU in the DMAC). 5. Direct data transfer mode (valid for channel 2 only) A data transfer request can be asserted for channel 2 by asserting DBREQ and TR simultaneously from an external device after the initial settings have been made in the DMAC channel 2 control register. Rev.7.00 Oct. 10, 2008 Page 604 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.5.2 Pins in DDT Mode Figure 14.24 shows the system configuration in DDT mode. DBREQ/DREQ0 BAVL/DRAK0 TR/DREQ1 TDACK/DACK0 SH7750, SH7750S, SH7750R ID1, ID0/DRAK1, DACK1 CKIO D63–D0=DTR External device A25–A0, RAS, CAS, WE, DQMn, CKE Synchronous DRAM Figure 14.24 System Configuration in On-Demand Data Transfer Mode • DBREQ: Data bus release request signal for transmitting the data transfer request format (DTR format) or a DMA request from an external device to the DMAC If there is a wait for release of the data bus, an external device can have the data bus released by asserting DBREQ. When DBREQ is accepted, the BSC asserts BAVL. • BAVL: Data bus D63–D0 release signal Assertion of BAVL means that the data bus will be released two cycles later. This LSI does not switch the data pins to output status for a total of three cycles: the cycle in which the data bus is released and the cycles preceding and following it. • TR: Transfer request signal Assertion of TR has the following different meanings. ⎯ In normal data transfer mode (channel 0, except channel 0), TR is asserted, and at the same time the DTR format is output, two cycles after BAVL is asserted. ⎯ In the case of the handshake protocol without use of the data bus, asserting TR enables a transfer request to be issued for the channel for which a transfer request was made immediately before. This function can be used only when BAVL is not asserted two cycles earlier. Rev.7.00 Oct. 10, 2008 Page 605 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) ⎯ In the case of direct data transfer mode (valid only for channel 2), a direct transfer request can be made to channel 2 by asserting DBREQ and TR simultaneously. • TDACK: Reply strobe signal for external device from DMAC The assert timing of this signal is the same as the DACKn assert timing of the memory interfaces. Note that it is a low active signal. • ID1, ID0: Channel number notification signals ⎯ 00: Channel 0 (means demand data transfer) ⎯ 01: Channel 1 ⎯ 10: Channel 2 ⎯ 11: Channel 3 Data Transfer Request Format 63 61 60 59 ID R/W 57 MD 55 COUNT 48 (Reserved) 31 ADDRESS 0 SZ Figure 14.25 Data Transfer Request Format The data transfer request format (DTR format) consists of 64 bits, with connection to D[63:0]. In the case of normal data transfer mode (channel 0, except channel 0) and the handshake protocol using the data bus, the transfer data size, read/write access, channel number, transfer request mode, number of transfers, and transfer source or transfer destination address are specified. A specification in bits 47–32 is invalid. In the SH7750, only single address mode can be set in normal data transfer mode (channel 0). With the DTR format, DS = (0: MD = 10, 11, 1: MD = 01), RL = 0, AL = 0, DM[1:0] = 01, SM[1:0] = 01, RS[3:0] = (0010: R/W = 0, 0011: R/W = 1), TM = (0: MD = 11, 1: MD = 01, 10), TS[2:0] = (SZ), and IE = 0 settings are made in DMA channel control register 0, COUNT is set in transfer count register 0, and ADDRESS is set in source/destination address register 0. Therefore, in DDT mode, the above control registers cannot be written to by the CPU, but can be read. In the SH7750S, DMAC control registers CHCR0, SAR0, DAR0, and DMATCR0 can be written to and read by the CPU even in normal data transfer mode (channel 0). Caution is necessary in this case, as a DMAC control register written to by the CPU will be overwritten by a subsequent transfer request (MD[1:0] = 01, 10, or 11) using the DTR format. Rev.7.00 Oct. 10, 2008 Page 606 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Bits 63 to 61: Transmit Size (SZ2–SZ0) • 000: Byte size (8-bit) specification • 001: Word size (16-bit) specification • 010: Longword size (32-bit) specification • 011: Quadword size (64-bit) specification • 100: 32-byte block transfer specification • 101: Setting prohibited • 110: Request queue clear specification • 111: Transfer end specification Bit 60: Read/Write (R/W) • 0: Memory read specification • 1: Memory write specification Bits 59 and 58: Channel Number (ID1, ID0) • 00: Channel 0 (demand data transfer) • 01: Channel 1 • 10: Channel 2 • 11: Channel 3 Bits 57 and 56: Transfer Request Mode (MD1, MD0) • 00: Handshake protocol (data bus used) • 01: Burst mode (edge detection) specification • 10: Burst mode (level detection) specification • 11: Cycle steal mode specification Bits 55 to 48: Transfer Count (COUNT7–COUNT0) • Transfer count: 1 to 255 • 00000000: Maximum number of transfers (16M) Bits 47 to 32: Reserved Bits 31 to 0: Address (ADDRESS31–ADDRESS0) • R/W = 0: Transfer source address specification • R/W = 1: Transfer destination address specification Notes: 1. Only the ID field is valid for channels 1 to 3. 2. To start DMA transfer by means of demand data transfer on channel 0, the initial value of MD in the DTR format must be 01, 10, or 11. Rev.7.00 Oct. 10, 2008 Page 607 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 3. The COUNT field is ignored if MD = 00. 4. In edge-sense burst mode, DMA transfer is executed continuously. In level-sense burst mode and cycle steal mode, a handshake protocol is used to transfer each unit of data. 5. The maximum number of transfers can be specified by setting COUNT = 0 as DTR format initialization data. If the amount of data to be transferred is unknown, set COUNT = 0, start DMA transfer, and transfer the DTR format (ID = 00, MD ≠ 00, SZ = 111) when the required amount of data has been transferred. This will terminate DMA transfer on channel 0. In this case, the TE bit in DMA channel control register 0 is not set, but transfer cannot be restarted. 6. When port functions are used (BCR2.PORTEN = 1) and DDT mode is selected, input the DTR format for D[63:52] and D[31:0]. In this case, if ID[1:0] = 00, input MD[1:0] and SZ ≠ 101, 110. 7. For DTR format transfer when ID[1:0] = 00, input MD[1:0] and SZ ≠ 101, 110. 14.5.3 Transfer Request Acceptance on Each Channel On channel 0, a DMA data transfer request can be made by means of the DTR format. No further transfer requests are accepted between DTR format acceptance and the end of the data transfer. On channels 1 to 3, output a transfer request from an external device by means of the DTR format (ID = 01, 10, or 11) after making DMAC control register settings in the same way as in normal DMA mode. Each of channels 1 to 3 has a request queue that can accept up to four transfer requests. When a request queue is full, the fifth and subsequent transfer requests will be ignored, and so transfer requests must not be output. When CHCR.TE = 1 when a transfer request remains in the request queue and a transfer is completed, the request queue retains it. When another transfer request is sent at that time, the transfer request is added to the request queue if the request queue is vacant. Rev.7.00 Oct. 10, 2008 Page 608 of 1074 REJ09B0366-0700 Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk Tl Tm Tn To Tp Tq Tr Ts Tt Tu Tv Tw CKIO tAD Row tAD Row Row tCSD tRWD tRASD tCASD2 tCASD2 tRASD c1 tCSD H/L tAD BANK Precharge-sel Address CSn RD/WR RAS CASn tDQMD tDTRS DTR 1CKIO cycle (10ns F100MHz) [2CKIO cycle - tDTRS] ( 18ns F100MHz) tDTRH tRDS c1 tBSD tRDH c2 tBSD tDQMD DQMn c3 c4 D63–D0 (READ) BS tDBQH tBAVD tBAVD tTRS tTRH DBREQ tDBQS BAVL TR tTDAD tIDD DMAC Channel tTDAD tIDD TDACK Figure 14.26 Single Address Mode: Synchronous DRAM → External Device Longword Transfer SDRAM auto-precharge Read bus cycle, burst (RCD[1:0] = 01, CAS latency = 3, TPC[2:0] = 001) Section 14 Direct Memory Access Controller (DMAC) Rev.7.00 Oct. 10, 2008 Page 609 of 1074 REJ09B0366-0700 ID1–ID0 Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk Tl Tm Tn To Tp Tq Tr Ts Tt Tu Tv Tw CKIO tAD Row tAD Row Row tCSD tRWD tRWD tCSD c1 H/L tAD BANK Precharge-sel Address CSn RD/WR tRASD tCASD2 tCASD2 tRASD Rev.7.00 Oct. 10, 2008 Page 610 of 1074 REJ09B0366-0700 tDQMD tDTRS tWDD c1 DTR 1CKIO cycle (10ns 100MHz) tBSD [2CKIO cycle - tDTRS] (18ns F100MHz) tDTRH tDQMD tWDD c2 tBSD c3 c4 tDBQH tBAVD tBAVD tTRS tTRH tTDAD tIDD DMAC Channel tTDAD tIDD RAS CASn Section 14 Direct Memory Access Controller (DMAC) DQMn D63–D0 (READ) BS DBREQ tDBQS BAVL TR TDACK Figure 14.27 Single Address Mode: External Device → Synchronous DRAM Longword Transfer SDRAM auto-precharge Write bus cycle, burst (RCD[1:0] = 01, TRWL[2:0] = 101, TPC[2:0] = 001) ID1–ID0 Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk Tl Tm Tn To Tp Tq Tr Ts Tt CKIO tAD Row tAD Row Row tCSD tRWD tRASD tCASD2 tCASD2 tRASD tCSD c1 H/L tAD BANK Precharge-sel Addr CSn RD/WR RAS CASn tDQMD tDTRS tRDS c1 DTR= 1CKIO cycle (= 10ns: 100MHz) tBSD [2CKIO cycles - tDTRS] (= 18ns: 100MHz) tDTRH tRDH c2 tBSD tDQMD DQMn c3 c4 D63-D0 (READ) BS tDBQH tBAVD tTRS tTRH tBAVD DBREQ tDBQS BAVL TR tTDAD tTDAD TDACK DMAC Channel DMAC Channel Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer Section 14 Direct Memory Access Controller (DMAC) Rev.7.00 Oct. 10, 2008 Page 611 of 1074 REJ09B0366-0700 ID1-ID0 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 RA CA D63–D0 RAS, CAS, WE TDACK DTR D0 D1 D2 D3 BA RD ID1, ID0 00 Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev.7.00 Oct. 10, 2008 Page 612 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 RA CA D63–D0 RAS, CAS, WE TDACK DTR D0 D1 D2 D3 D4 D5 BA WT ID1, ID0 Figure 14.30 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev.7.00 Oct. 10, 2008 Page 613 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK A25–A0 RA CA CA CA D63–D0 RAS, CAS, WE DQMn DTR BA RD D0 RD D1 RD ID1, ID0 00 00 Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer Rev.7.00 Oct. 10, 2008 Page 614 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 RA CA CA D63–D0 RAS, CAS, WE DQMn TDACK ID1, ID0 DTR BA D0 WT D1 WT Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer Rev.7.00 Oct. 10, 2008 Page 615 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 CA CA D63–D0 DTR MD = 10 or 11 D0 D1 D2 D3 DTR MD = 00 D0 D1 CMD TDACK ID1, ID0 Start of data transfer WT WT Next transfer request Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) Rev.7.00 Oct. 10, 2008 Page 616 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 CA CA D63–D0 CMD TDACK DTR MD = 10 or 11 D0 D1 D2 D3 D0 D1 D2 D3 WT WT ID1, ID0 Start of data transfer Next transfer request Figure 14.34 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data Transfer) Rev.7.00 Oct. 10, 2008 Page 617 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 RA CA D63–D0 RAS, CAS, WE D0 D1 D2 D3 BA RD Figure 14.35 Read from Synchronous DRAM Precharge Bank CLK DBREQ Transfer requests can be accepted BAVL TR A25–A0 RA CA D63–D0 RAS, CAS, WE D0 BA RD D1 D2 D3 PCH Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) Rev.7.00 Oct. 10, 2008 Page 618 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 CA D63–D0 RAS, CAS, WE D0 D1 D2 D3 RD Figure 14.37 Read from Synchronous DRAM (Row Hit) CLK DBREQ BAVL TR A25–A0 RA CA D63–D0 RAS, CAS, WE D0 D1 D2 D3 BA WT Figure 14.38 Write to Synchronous DRAM Precharge Bank Rev.7.00 Oct. 10, 2008 Page 619 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ Transfer requests can be accepted BAVL TR A25–A0 RA CA D63–D0 RAS, CAS, WE D0 BA WT D1 D2 D3 PCH Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss) CLK A25–A0 CA D63–D0 RAS, CAS, WE D0 D1 D2 D3 WT Figure 14.40 Write to Synchronous DRAM (Row Hit) Rev.7.00 Oct. 10, 2008 Page 620 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 RA CA D63–D0 RAS, CAS, WE TDACK DTR D0 D1 D2 BA RD ID1, ID0 00 Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev.7.00 Oct. 10, 2008 Page 621 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) DMA Operation Register (DMAOR) 31 15 9 8 4 2 10 PR[1:0] DDT DDT: 0: Normal DMA mode 1: On-demand data transfer mode COD (SH7750S) AE NMIF DME Figure 14.42 DDT Mode Setting CLK DBREQ BAVL No DMA request sampling TR A25–A0 CA CA D63–D0 CMD TDACK ID1, ID0 DTR MD = 01 D0 D1 D2 D3 D0 D1 D2 D3 D1 D2 D3 WT WT Start of data transfer Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device → External Bus Data Transfer Rev.7.00 Oct. 10, 2008 Page 622 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL Wait for next DMA request TR A25–A0 D63–D0 CMD TDACK ID1, ID0 Start of data transfer DTR MD = 10 CA D0 RD CA D1 D2 D3 RD D0 D1 D2 D3 Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus → External Device Data Transfer Rev.7.00 Oct. 10, 2008 Page 623 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 CA CA CA D63–D0 DTR MD = 01 RD D0 RD Idle cycle D2 Idle cycle RD D3 Idle cycle CMD DQMn TDACK ID1, ID0 Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Bus → External Device Data Transfer Rev.7.00 Oct. 10, 2008 Page 624 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 CA CA CA D63–D0 DTR MD = 01 D0 WT D1 WT D3 WT CMD DQMn TDACK ID1, ID0 Idle cycle Idle cycle Idle cycle Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device → External Bus Data Transfer Rev.7.00 Oct. 10, 2008 Page 625 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 RA CA D63–D0 RAS, CAS, WE TDACK DTR ID = 1, 2, or 3 BA RD D0 D1 D2 D3 ID1, ID0 01 or 10 or 11 Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer Request to Channels 1–3 Using Data Bus Rev.7.00 Oct. 10, 2008 Page 626 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CLK DBREQ BAVL TR A25–A0 RA CA D63–D0 RAS, CAS, WE TDACK D0 D1 D2 D3 D4 D5 D6 D7 BA RD ID1, ID0 No DTR cycle, so requests can be made at any time 10 Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus → External Device Data Transfer/ Direct Data Transfer Request to Channel 2 without Using Data Bus Rev.7.00 Oct. 10, 2008 Page 627 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Four requests can be queued Handshaking is necessary to send additional requests CLK 1st 2nd 3rd 4th 5th No more requests A25–A0 RA CA CA CA D63–D0 RAS, CAS, WE BA RD D0 D1 RD D2 D3 D0 D1 D2 RD D3 D0 D1 NOP D2 ID1, ID0 Must be ignored (no request transmitted) Figure 14.49 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer/Direct Data Transfer Request to Channel 2 Rev.7.00 Oct. 10, 2008 Page 628 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Four requests can be queued Handshaking is necessary to send additional requests CLK 1st 2nd 3rd 4th 5th DBREQ BAVL TR A25–A0 RA CA CA D2 D2 CA CA D63–D0 RAS, CAS, WE TDACK BA D0 D1 D3 D0 D1 D3 D0 D1 D2 D3 WT WT WT WT ID1, ID0 Must be ignored (no request transmitted) Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer/Direct Data Transfer Request to Channel 2 Rev.7.00 Oct. 10, 2008 Page 629 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Handshaking is necessary to send additional requests Four requests can be queued CLK 1st 2nd 3rd 4th 5th DBREQ BAVL TR A25–A0 CA CA CA D2 D2 CA D63–D0 RAS, CAS, WE TDACK RD D0 D1 RD D3 D0 D1 RD D3 D0 D1 RD D2 ID1, ID0 Must be ignored (no request transmitted) Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 Rev.7.00 Oct. 10, 2008 Page 630 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Four requests can be queued Handshaking is necessary to send additional requests CLK 1st 2nd 3rd 4th 5th DBREQ BAVL TR A25–A0 CA CA CA CA D63–D0 RAS, CAS, WE TDACK D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 WT WT WT WT ID1, ID0 Must be ignored (no request transmitted) Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 14.5.4 Notes on Use of DDT Module 1. Normal data transfer mode (channel 0) Initial settings for channel 0 demand transfer must be DTR.ID = 00 and DTR.MD = 01, 10, or 11. In this case, only single address mode can be set for channel 0. 2. Normal data transfer mode (channels 1 to 3) If a setting of DTR.ID = 01, 10, or 11 is made, DTR.MD will be ignored. 3. Handshake protocol using the data bus (valid on channel 0 only) a. The handshake protocol using the data bus can be executed only on channel 0. (Set DTR.ID = 00, DTR.MD = 00, DTR.SZ ≠ 101 or 110. Operation is not guaranteed if settings of DTR.ID = 00, DTR.MD = 00, and DTR.SZ = 101 or 110 are made.) Rev.7.00 Oct. 10, 2008 Page 631 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) b. If, during execution of the handshake protocol using the data bus for channel 0, a request is input for one of channels 1 to 3, and after that DMA transfer is executed settings of DTR.ID = 00, DTR.MD = 00, and DTR, SZ ≠ 101.110 are input in the handshake protocol using the data bus, a transfer request will be asserted for channel 0. c. In the SH7750S and SH7750R, initial settings can be made in the DMAC channel 0 control register from the CPU (possible settings are CHCR0.RS = 0000, 0010, or 0011). If settings of DTR.ID = 00, DTR.MD = 00, and DTR.SZ ≠ 101 or 110 are subsequently input, a transfer request to channel 0 will be asserted. 4. Handshake protocol without use of the data bus a. With the handshake protocol without use of the data bus, a DMA transfer request can be input to the DMAC again for the channel for which transfer was requested immediately before by asserting TR only. b. When using the handshake protocol without use of the data bus, first make the necessary settings in the DMAC control registers. c. When not using the handshake protocol without use of the data bus, if TR only is asserted without outputting DTR, a request will be issued for the channel for which DMA transfer was requested immediately before. Also, if the first DMA transfer request after a power-on reset is input by asserting TR only, it will be ignored and the DMAC will not operate. d. If TR only is asserted by means of the handshake protocol without use of the data bus and a DMA transfer request is input when channel 0 DMA transfer has ended and CHCR0.TE = 1, the DMAC will freeze. Before issuing a DMA transfer request, the TE flag must be cleared by writing CHCR0.TE = 0 after reading CHCR0.TE = 1. 5. Direct data transfer mode (valid on channel 2 only) a. If a DMA transfer request for channel 2 is input by simultaneous assertion of DBREQ and TR during DMA transfer execution with the handshake protocol without use of the data bus, it will be accepted if there is space in the DDT channel 2 request queue. b. In direct data transfer mode (with DBREQ and TR asserted simultaneously), DBREQ is not interpreted as a bus arbitration signal, and therefore the BAVL signal is never asserted. 6. Request queue transfer request acceptance a. The DDT has four request queues for each of channels 1 to 3. When these request queues are full, a DMA transfer request from an external device will be ignored. b. If a DMA transfer request for channel 0 is input during execution of a channel 0 DMA bus cycle, the DDT will ignore that request. Confirm that channel 0 DMA transfer has finished (burst mode) or that a DMA bus cycle is not in progress (cycle steal mode). Rev.7.00 Oct. 10, 2008 Page 632 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 7. DTR format a. The DDT module processes DTR.ID, DTR.MD, and DTR.SZ as follows. When DTR.ID= 00 • MD = 00, SZ ≠ 101, 110: Handshake protocol using the data bus • MD ≠ 00, SZ = 111: CHCR0.DE = 0 setting (DMA transfer end request) • MD ≠ 10, SZ = 110: DDT request queue clear When DTR.ID ≠ 00 • Transfer request to channels 1—3 (items other than ID ignored) 8. Data transfer end request a. A data transfer end request (DTR.ID = 00, MD ≠ 00, SZ = 111) cannot be accepted during channel 0 DMA transfer. Therefore, if edge detection and burst mode are set for channel 0, transfer cannot be ended midway. b. When a transfer end request (DTR.ID = 00, MD ≠ 00, SZ = 111) is accepted, the values set in CHCR0, SAR0, DAR0, and DMATCR0 are retained. With the SH7750, execution cannot be restarted from an external device in this case. To restart execution in the SH7750S and SH7750R, set CHCR0.DE = 1 with an MOV instruction. 9. Request queue clearance a. When settings of DTR.ID = 00, DTR.MD = 10, and SZ = 110 are accepted by the DDT in normal data transfer mode, DDT channel 0 requests and channel 1 to 3 request queues are all cleared. All external requests held on the DMAC side are also cleared. b. In case 4-d, the DMAC freeze state can be cleared. c. When settings of DMAOR.DDT = 1, DTR.ID = 00, DTR.MD = 10, and SZ = 110 are accepted by the DDT in case 11, the DMAC freeze state can be cleared. 10. DBREQ assertion a. After DBREQ is asserted, do not assert DBREQ again until BAVL is asserted, as this will result in a discrepancy between the number of DBREQ and BAVL assertions. b. The BAVL assertion period due to DBREQ assertion is one cycle. If a row address miss occurs in a read or write in the non-precharged bank during synchronous DRAM access, BAVL is asserted for a number of cycles in accordance with the RAS precharge interval set in BSC.MCR.TCP. c. It takes one cycle for DBREQ to be accepted by the DMAC after being asserted by an external device. If a row address miss occurs at this time in a read or write in the nonprecharged bank during synchronous DRAM access, and BAVL is asserted, the DBREQ signal asserted by the external device is ignored. Therefore, BAVL is not asserted again due to this signal. Rev.7.00 Oct. 10, 2008 Page 633 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 11. Clearing DDT mode Check that DMA transfer is not in progress on any channel before setting the DMAOR.DDT bit. If the DMAOR.DDT setting is changed from 1 to 0 during DMA transfer in DDT mode, the DMAC will freeze. This also applies when switching from normal DMA mode (DMAOR.DDT = 0) to DDT mode. 12. Confirming DMA transfer requests and number of transfers executed The channel associated with a DMA bus cycle being executed in response to a DMA transfer request can be confirmed by determining the level of external pins ID1 and ID0 at the rising edge of the CKIO clock while TDACK is asserted. (ID = 00: channel 0; ID = 01: channel 1; ID = 10: channel 2; ID = 11: channel 3) 14.6 14.6.1 Configuration of the DMAC (SH7750R) Block Diagram of the DMAC Figure 14.53 is a block diagram of the DMAC in the SH7750R. Rev.7.00 Oct. 10, 2008 Page 634 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) DMAC module Count control SARn Registr control Peripheral bus DARn Internal bus DMATCRn Activation control CHCRn On-chip peripheral module DMAOR TMU SCI, SCIF Request priority control queclr0–7 DACK0, DACK1 DRAK0, DRAK1 Bus interface dmaqueclr0-7 External address/on-chip peripheral module address 8 Request SAR0, DAR0, DMATCR0, CHCR0 only DDT module DTR command buffer Request controller CH0 CH1 CH5 CH2 CH6 CH3 CH7 DREQ0, DREQ1 BAVL/ID2 D[63:0] ID[1:0] TDACK External bus 32B data buffer Bus state controller DBREQ DDTMODE BAVL DDTD 48 bits id[2:0] CH4 Legend: DMAORn: SARn: DARn: DMATCRn: CHCRn: Note: DMAC operation register DMAC source address register DMAC destination address register DMAC transfer count register DMAC channel control register tdack TR DBREQ n = 0 to 7 Figure 14.53 Block Diagram of the DMAC Rev.7.00 Oct. 10, 2008 Page 635 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.6.2 Pin Configuration (SH7750R) Tables 14.11 and 14.12 show the pin configuration of the DMAC. Table 14.11 DMAC Pins Channel 0 Pin Name DMA transfer request DREQ acceptance confirmation Abbreviation DREQ0 DRAK0 I/O Input Output Function DMA transfer request input from external device to channel 0 Acceptance of request for DMA transfer from channel 0 to external device Notification to external device of start of execution DMA transfer end notification 1 DMA transfer request DREQ acceptance confirmation DACK0 Output Strobe output to external device of DMA transfer request from channel 0 to external device DMA transfer request input from external device to channel 1 Acceptance of request for DMA transfer from channel 1 to external device Notification to external device of start of execution DMA transfer end notification DACK1 Output Strobe output to external device of DMA transfer request from channel 1 to external device DREQ1 DRAK1 Input Output Rev.7.00 Oct. 10, 2008 Page 636 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Table 14.12 DMAC Pins in DDT Mode Pin Name Data bus request Data bus available Abbreviation DBREQ (DREQ0) BAVL/ID2 (DRAK0) I/O Input Output Function Data bus release request from external device for DTR format input Data bus release notification Data bus can be used 2 cycles after BAVL is asserted Notification of channel number to external device at same time as TDACK output Transfer request signal TR (DREQ1) Input If asserted 2 cycles after BAVL assertion, DTR format is sent Only TR asserted: DMA request DBREQ and TR asserted simultaneously: Direct request to channel 2 DMAC strobe Channel number notification TDACK (DACK0) ID[1:0] (DRAK1, DACK1) Output Output Reply strobe signal for external device from DMAC Notification of channel number to external device at same time as TDACK output (ID [1] = DRAK1, ID [0] = DACK1) Requests for DMA transfer from external devices are normally accepted only on channel 0 (DREQ0) and channel 1 (DREQ1). In DDT mode, the BAVL pin functions as both the data-busavailable pin and channel-number-notification (ID2) pin. 14.6.3 Register Configuration (SH7750R) Table 14.13 shows the configuration of the DMAC's registers. The DMAC of the SH7750R has a total of 33 registers: four registers are assigned to each channel, and there is a control register for the overall control of the DMAC. Rev.7.00 Oct. 10, 2008 Page 637 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Table 14.13 Register Configuration Channel Name 0 DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0 1 DMA source address register 1 DMA destination address register 1 DMA transfer count register 1 DMA channel control register 1 2 DMA source address register 2 DMA destination address register 2 DMA transfer count register 2 DMA channel control register 2 3 DMA source address register 3 DMA destination address register 3 DMA transfer count register 3 DMA channel control register 3 Com- DMA operation mon register Abbreviation SAR0 DAR0 Read/ Write R/W*2 R/W*2 2 Area 7 Initial Value P4 Address Address Undefined Undefined Undefined Access Size H'FFA00000 H'1FA00000 32 H'FFA00004 H'1FA00004 32 H'FFA00008 H'1FA00008 32 DMATCR0 R/W* CHCR0 SAR1 DAR1 R/W*1*2 H'00000000 H'FFA0000C H'1FA0000C 32 R/W R/W Undefined Undefined Undefined 1 H'FFA00010 H'1FA00010 32 H'FFA00014 H'1FA00014 32 H'FFA00018 H'1FA00018 32 DMATCR1 R/W CHCR1 SAR2 DAR2 R/W* R/W R/W H'00000000 H'FFA0001C H'1FA0001C 32 Undefined Undefined Undefined H'FFA00020 H'1FA00020 32 H'FFA00024 H'1FA00024 32 H'FFA00028 H'1FA00028 32 DMATCR2 R/W CHCR2 SAR3 DAR3 R/W* R/W R/W 1 H'00000000 H'FFA0002C H'1FA0002C 32 Undefined Undefined Undefined H'FFA00030 H'1FA00030 32 H'FFA00034 H'1FA00034 32 H'FFA00038 H'1FA00038 32 DMATCR3 R/W CHCR3 DMAOR R/W*1 R/W*1 H'00000000 H'FFA0003C H'1FA0003C 32 H'00000000 H'FFA00040 H'1FA00040 32 Rev.7.00 Oct. 10, 2008 Page 638 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Channel Name 4 DMA source address register 4 DMA destination address register 4 DMA transfer count register 4 DMA channel control register 4 5 DMA source address register 5 DMA destination address register 5 DMA transfer count register 5 DMA channel control register 5 6 DMA source address register 6 DMA destination address register 6 DMA transfer count register 6 DMA channel control register 6 7 DMA source address register 7 DMA destination address register 7 DMA transfer count register 7 DMA channel control register 7 Abbreviation SAR4 DAR4 Read/ Write R/W R/W Area 7 Initial Value P4 Address Address Undefined Undefined Undefined Access Size H'FFA00050 H'1FA00050 32 H'FFA00054 H'1FA00054 32 H'FFA00058 H'1FA00058 32 DMATCR4 R/W CHCR4 SAR5 DAR5 R/W*1 R/W R/W H'00000000 H'FFA0005C H'1FA0005C 32 Undefined Undefined Undefined H'FFA00060 H'1FA00060 32 H'FFA00064 H'1FA00064 32 H'FFA00068 H'1FA00068 32 DMATCR5 R/W CHCR5 SAR6 DAR6 R/W*1 R/W R/W H'00000000 H'FFA0006C H'1FA0006C 32 Undefined Undefined Undefined H'FFA00070 H'1FA00070 32 H'FFA00074 H'1FA00074 32 H'FFA00078 H'1FA00078 32 DMATCR6 R/W CHCR6 SAR7 DAR7 R/W*1 R/W R/W H'00000000 H'FFA0007C H'1FA0007C 32 Undefined Undefined Undefined H'FFA00080 H'1FA00080 32 H'FFA00084 H'1FA00084 32 H'FFA00088 H'1FA00088 32 DMATCR7 R/W CHCR7 R/W*1 H'00000000 H'FFA0008C H'1FA0008C 32 Notes: Longword access should be used for all control registers. If a different access width is used, reads will return all 0s and writes will not be possible. 1. Bit 1 of CHCR0–CHCR7 and bits 2 and 1 of DMAOR can only be written with 0 after being read as 1, to clear the flags. Rev.7.00 Oct. 10, 2008 Page 639 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 2. In the SH7750R, writes from the CPU and writes from external I/O devices using the DTR format are possible in DDT mode. 14.7 14.7.1 Register Descriptions (SH7750R) DMA Source Address Registers 0−7 (SAR0−SAR7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: — — — — — — — — — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA source address registers 0−7 (SAR0−SAR7) are 32-bit readable/writable registers that specify the source address for a DMA transfer. The functions of these registers are the same as on the SH7750 or SH7750S. For more information, see section 14.2.1, DMA Source Address Registers 0−3 (SAR0−SAR3). 14.7.2 DMA Destination Address Registers 0−7 (DAR0−DAR7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: — — — — — — — — — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.7.00 Oct. 10, 2008 Page 640 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) DMA destination address registers 0−7 (DAR0−DAR7) are 32-bit readable/writable registers that specify the destination address for a DMA transfer. The functions of these registers are the same as on the SH7750 and SH7750S. For more information, see section 14.2.2, DMA Destination Address Registers 0−3 (DAR0−DAR3). 14.7.3 DMA Transfer Count Registers 0−7 (DMATCR0−DMATCR7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA transfer count registers 0−7 (DMATCR0−DMATCR7) are 32-bit readable/writable registers that specify the number of transfers in transfer operations for the corresponding channel (byte count, word count, longword count, quadword count, or 32-byte count). Functions of these registers are the same as the transfer-count registers of the SH7750 or SH7750S. For more information, see section 14.2.3, DMA Transfer Count Registers 0−3 (DMATCR0−DMATCR3). 14.7.4 DMA Channel Control Registers 0−7 (CHCR0−CHCR7) Bit: 31 30 29 28 27 26 25 24 23 — 0 R 22 — 0 R 21 — 0 R 20 — 0 R 19 DS 0 18 RL 0 17 AM 0 16 AL 0 SSA2 SSA1 SSA0 STC DSA2 DSA1 DSA0 DTC Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W (R/W) R/W (R/W) Bit: 15 14 13 12 11 10 9 8 7 TM 0 6 5 4 3 2 IE 0 1 TE 0 0 DE 0 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 Initial value: 0 0 0 0 0 0 0 0 TS2 TS1 TS0 QCL 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W) R/W R/(W) R/W Rev.7.00 Oct. 10, 2008 Page 641 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) DMA channel control registers 0−7(CHCR0−CHCR7) are 32-bit readable/writable registers that specify the operating mode, transfer method, etc., for each channel. Bits 31−28 and 27−24 correspond to the source address and destination address, respectively; these settings are only valid when the transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA-interface space. In other cases, these bits should be cleared to 0. For more information about the PCMCIA interface, see section 13.3.7, PCMCIA Interface, in section 13, Bus State Controller (BSC). No function is assigned to bits 18 and 16 of the CHCR2–CHCR7 registers. Writing to these bits of the CHCR2–CHCR7 registers is invalid. If, however, a value is written to these bits, it should always be 0. These bits are always read as 0. These registers are initialized to H'00000000 by a power-on or manual reset. Their values are retained in standby, sleep, and deep-sleep modes. Bits 31 to 29—Source Address Space Attribute Specification (SSA2–SSA0): These bits specify the space attribute for PCMCIA access. These bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6. For details of the settings, see the description of the SSA2SSA0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 28—Source Address Wait Control Select (STC): Specifies CS5 or CS6 space wait control for PCMCIA access. This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control. For details of the settings, see the description of the STC bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bits 27 to 25—Destination Address Space Attribute Specification (DSA2–DSA0): These bits specify the space attribute for PCMCIA access. These bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6. For details of the settings, see the description of the DSA2−DSA0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 24—Destination Address Wait Control Select (DTC): Specifies CS5 or CS6 space wait cycle control for PCMCIA access. This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control. For details of the settings, see the description of the DTC bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bits 23 to 20—Reserved: These bits are always read as 0, and should only be written with 0. Rev.7.00 Oct. 10, 2008 Page 642 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Bit 19—DREQ Select (DS): Specifies either low level detection or falling edge detection as the sampling method for the DREQ pin used in external request mode. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0–CHCR7. For details of the settings, see the description of the DS bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 18—Request Check Level (RL): Selects whether the DRAK signal (that notifies an external device of the acceptance of DREQ) is an active-high or active-low output. This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For details of the settings, see the description of the RL bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the data read cycle or write cycle. In single address mode, DACK is always output regardless of the setting of this bit. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0–CHCR7. (DDT mode: TDACK) For details of the settings, see the description of the AM bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or active-low. This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For details of the settings, see the description of the AL bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bits 15 and 14—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify incrementing/decrementing of the DMA transfer destination address. The specification of these bits is ignored when data is transferred from external memory to an external device in single address mode. For details of the settings, see the description of the DM1 and DM0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bits 13 and 12—Source Address Mode 1 and 0 (SM1, SM0): These bits specify incrementing/decrementing of the DMA transfer source address. The specification of these bits is ignored when data is transferred from an external device to external memory in single address mode. For details of the settings, see the description of the SM1 and SM0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Rev.7.00 Oct. 10, 2008 Page 643 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source. For details of the settings, see the description of the RS3−RS0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer. For details of the settings, see the description of the TM bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size (access size). For details of the settings, see the description of the TS2−TS0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 3⎯Request Queue Clear (QCL): Writing a 1 to this bit clears the request queues of the corresponding channel as well as any external requests that have already been accepted. This bit is only functional when DMAOR.DDT = 1 and DMAOR.DBL = 1. CHCR Bit 3 QCL 0 1 Description This bit is always read as 0. Writing a 0 to this bit is invalid. When DMAOR.DBL = 1, writing a 1 to this bit clears the request queues on the DDT side and any external requests stored in the DMAC. The written value is not retained. (Initial value) Bit 2—Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated after the number of data transfers specified in DMATCR (when TE = 1). For details of the settings, see the description of the IE bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1, the transfer enabled state is not entered even if the DE bit is set to 1. For details of the settings, see the description of the TE bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Rev.7.00 Oct. 10, 2008 Page 644 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Bit 0—DMAC Enable (DE): Enables operation of the corresponding channel. For details of the settings, see the description of the DE bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). 14.7.5 DMA Operation Register (DMAOR) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 — 0 R 12 — 0 R 11 — 0 R 10 — 0 R 9 8 7 — 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 1 0 DDT DBL Initial value: 0 0 PR1 PR0 0 0 AE NMIF DME 0 0 0 R/W: R/W R/W R/W R/W R/(W) R/(W) R/W DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode. DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in standby mode and deep sleep mode. Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0. Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode. For details of the settings, see the description of the DDT bit in section 14.2.5, DMA Operation Register (DMAOR) Bit 14⎯Number of DDT-Mode Channels (DBL): Selects the number of channels that are able to accept external requests in DDT mode. Bit 14: DBL 0 1 Description Four DDT-mode channels Eight DDT-mode channels (Initial value) Note: When DMAOR.DBL = 0, channels 4 to 7 cannot accept external requests. When DMAOR.DBL = 1, one channel can be selected from among channels 0−7 by the combination of DTR.SZ and DTR.ID in the DTR format (see figure 14.54). Table 14.14 shows the channel selection by DTR format in the DDT mode. Rev.7.00 Oct. 10, 2008 Page 645 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Table 14.14 Channel Selection by DTR Format (DMAOR.DBL = 1) DTR.ID[1:0] 00 01 10 11 DTR.SZ[2:0] ≠ 101 CH0 CH1 CH2 CH3 DTR.SZ[2:0] = 101 CH4 CH5 CH6 CH7 63 SZ 61 60 59 58 57 56 55 R/W ID MD COUNT 4847 32 31 ADDRESS 0 (Reserved) Figure 14.54 DTR Format (Transfer Request Format) (SH7750R) Bits 13 to 10—Reserved: These bits are always read as 0, and should only be written with 0. Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously. DMAOR Bit 9 PR1 0 0 1 1 DMAOR Bit 8 PR0 0 1 0 1 Description CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 CH0 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH1 CH2 > CH0 > CH1 > CH3 > CH4 > CH5 > CH6 > CH7 Round robin mode (Initial value) Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0. Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be cleared by writing 0 after reading 1. For details of the settings, see the description of the AE bit in section 14.2.5, DMA Operation Register (DMAOR) Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing Rev.7.00 Oct. 10, 2008 Page 646 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 0 after reading 1. For details of the settings, see the description of the NMIF bit in section 14.2.5, DMA Operation Register (DMAOR) Bit 0—DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are suspended. Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or when the NMI or AE bit in DMAOR is 1. For details of the settings, see the description of the DME bit in section 14.2.5, DMA Operation Register (DMAOR) 14.8 Operation (SH7750R) Operation specific to the SH7750R is described here. For details of operation, see section 14.3, Operation. 14.8.1 Channel Specification for a Normal DMA Transfer In normal DMA transfer mode, the DMAC always operates with eight channels, and external requests are only accepted on channel 0 (DREQ) and channel 1 (DREQ1). After setting the registers of the channels in use, including CHCR, SAR, DAR, and DMATCR, DMA transfer is started on receiving a DMA transfer request in the transfer-enabled state (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), in the order of predetermined priority. The transfer ends when the transfer-end condition is satisfied. There are three modes for transfer requests: autorequest, external request, and on-chip peripheral module request. The addressing modes for DMA transfer are the single-address mode and the dual-address mode. Bus mode is selectable between burst mode and cycle steal mode. 14.8.2 Channel Specification for DDT-Mode DMA Transfer For DMA transfer in DDT mode, the DMAOR.DBL setting selects either four or eight channels. External requests are accepted on channels 0−3 when DMAOR.DBL = 0, and on channels 0−7 when DMAOR.DBL = 1. For further information on these settings, see the entry on the DBL bit in section 14.7.5, DMA Operation Register (DMAOR). Rev.7.00 Oct. 10, 2008 Page 647 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.8.3 Transfer Channel Notification in DDT Mode When the DMAC is set up for four-channel external request acceptance in DDT mode (DMAOR.DBL = 0), the ID [1:0] bits are used to notify the external device of the DMAC channel that is to be used. For more details, see section 14.5, On-Demand Data Transfer Mode (DDT Mode). When the DMAC is set up for eight-channel external request acceptance in DDT mode (DMAOR.DBL = 1), the ID [1:0] bits and the simultaneous (on the timing of TDACK assertion) assertion of ID2 from the BAVL (data bus available) pin are used to notify the external device of the DMAC channel that is to be used (see table 14.15). When the DMAC is set up for eight-channel external request acceptance in DDT mode (DMAOR.DBL = 1), it is important to note that the BAVL pin has the two functions as shown in table 14.16. Table 14.15 Notification of Transfer Channel in Eight-Channel DDT Mode BAVL/ID2 1 ID[1:0] 00 01 10 11 0 00 01 10 11 Transfer Channel CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 Table 14.16 Function of BAVL Function of BAVL TDACK = High TDACK = Low Bus available Notification of channel number (ID2) Rev.7.00 Oct. 10, 2008 Page 648 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.8.4 Clearing Request Queues by DTR Format In DDT mode, the request queues of any channel can be cleared by using DTR.ID, DTR.MD, DTR.SZ, and DTR.COUNT [7:4] in a DTR format. This function is only available when DMAOR.DBL = 1. Table 14.17 shows the DTR format settings for clearing request queues. Table 14.17 DTR Format for Clearing Request Queues DMAOR.DBL DTR.ID 0 00 DTR.MD 10 DTR.SZ 110 DTR.COUNT[7:4] * Description Clear the request queues of all channels (1−7). Clear the CH0 request-accepted flag 11 1 00 10 110 * Setting prohibited Clear the request queues of all channels (1−7). Clear the CH0 request-accepted flag. 11 0001 0010 0011 0100 0101 0110 0111 1000 Clear the CH0 request-accepted flag Clear the CH1 request queues. Clear the CH2 request queues. Clear the CH3 request queues. Clear the CH4 request queues. Clear the CH5 request queues. Clear the CH6 request queues. Clear the CH7 request queues. Note: (SH7750R) DTR.SZ = DTR[63:61], DTR.ID = DTR[59:58], DTR.MD = DTR[57:56], DTR.COUNT[7:4] = DTR[55:52] 14.8.5 Interrupt-Request Codes When the number of transfers specified in DMATCR has been finished and the interrupt request is enabled (CHCR.IE = 1), a transfer-end interrupt request can be sent to the CPU from each channel. Table 14.18 lists the interrupt-request codes that are associated with these transfer-end interrupts. Rev.7.00 Oct. 10, 2008 Page 649 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Table 14.18 DMAC Interrupt-Request Codes Source of the Interrupt DMTE0 DMTE1 DMTE2 DMTE3 DMTE4 DMTE5 DMTE6 DMTE7 DMAE Description CH0 transfer-end interrupt CH1 transfer-end interrupt CH2 transfer-end interrupt CH3 transfer-end interrupt CH4 transfer-end interrupt CH5 transfer-end interrupt CH6 transfer-end interrupt CH7 transfer-end interrupt Address error interrupt INTEVT Code H'640 H'660 H'680 H'6A0 H'780 H'7A0 H'7C0 H'7E0 H'6C0 Low Priority High Note: DMTE4−DMTE7: These codes are not used in the SH7750 or SH7750S. CKIO DBREQ BAVL/ID2 TR A25–A0 RA CA D63–D0 RAS, CAS, WE TDACK DTR D0 D1 D2 BA RD ID1, ID0 00 Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev.7.00 Oct. 10, 2008 Page 650 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) CKIO DBREQ BAVL/ID2 TR A25–A0 RA CA D63–D0 RAS, CAS, WE TDACK DTR D0 D1 D2 BA RD ID1, ID0 00 Figure 14.56 Single Address Mode/Burst Mode/External Bus → External Device/32-Byte Block Transfer/On-Demand Data Transfer on Channel 4 Rev.7.00 Oct. 10, 2008 Page 651 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 14.9 Usage Notes 1. When modifying SAR0–SAR3, DAR0–DAR3, DMATCR0–DMATCR3, and CHCR0– CHCR3 in the SH7750 or SH7750S or when modifying SAR0–SAR7, DAR0–DAR7, DMATCR0–DMATCR7, and CHCR0–CHCR7 in the SH7750R, first clear the DE bit for the relevant channel. 2. The NMIF bit in DMAOR is set when an NMI interrupt is input even if the DMAC is not operating. Confirmation method when DMA transfer is not executed correctly: With the SH7750 and SH7750S, read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR0–CHCR3, and DMATCR0–DMATCR3. With the SH7750R, read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR0–CHCR7, and DMATCR0–DMATCR7. If NMIF was set before the transfer, the DMATCR transfer count will remain at the set value. If NMIF was set during the transfer, when the DE bit is 1 and the TE bit is 0 in CHCR0–CHCR3 in the SH7750 or SH7750S or CHCR0–CHCR7 in the SH7750R, the DMATCR value will indicate the remaining number of transfers. Also, the next addresses to be accessed can be found by reading SAR0–SAR3 and DAR0– DAR3 in the SH7750 or SH7750S or SAR0–SAR7 and DAR0–DAR7 in the SH7750R. If the AE bit has been set, an address error has occurred. Check the set values in CHCR, SAR, and DAR. 3. Check that DMA transfer is not in progress before making a transition to the module standby state, standby mode, or deep sleep mode. Either check that TE = 1 in the SH7750 or SH7750S's CHCR0–CHCR3 or in the SH7750R's CHCR0–CHCR7, or clear DME to 0 in DMAOR to terminate DMA transfer. When DME is cleared to 0 in DMAOR, transfer halts at the end of the currently executing DMA bus cycle. Note, therefore, that transfer may not end immediately, depending on the transfer data size. DMA operation is not guaranteed if the module standby state, standby mode, or deep sleep mode is entered without confirming that DMA transfer has ended. 4. Do not specify a DMAC, CCN, BSC, or UBC control register as the DMAC transfer source or destination. 5. When activating the DMAC, make the SAR, DAR, and DMATCR register settings for the relevant channel before setting DE to 1 in CHCR, or make the register settings with DE cleared to 0 in CHCR, then set DE to 1. It does not matter whether setting of the DME bit to 1 in DMAOR is carried out first or last. To operate the relevant channel, DME and DE must both be set to 1. The DMAC may not operate normally if the SAR, DAR, and DMATCR settings are not made (with the exception of the unused register in single address mode). 6. After the DMATCR count reaches 0 and DMA transfer ends normally, always write 0 to DMATCR even when executing the maximum number of transfers on the same channel. Rev.7.00 Oct. 10, 2008 Page 652 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) 7. When falling edge detection is used for external requests, keep the external request pin high when making DMAC settings. 8. When using the DMAC in single address mode, set an external address as the address. All channels will halt due to an address error if an on-chip peripheral module address is set. 9. In external request (DREQ) edge detection in the SH7750R, an external request that has been accepted can be cancelled in the following way. Firstly, negate DREQ and change the value of CHCR.DS from 1 to 0. After that, set the CHCR.DS bit back to 1, then assert DREQ. (Though the SH7750R does not have a DMAOR.COD bit, similar to when the DMAOR.COD bit is 1 in the SH7750S, external requests that have once been accepted can be cancelled when the external request (DREQ) edge is detected.) 10. SH7750 Only: When a DMA transfer is performed between an on-chip peripheral module and external memory, the data may not be transferred correctly if the following conditions apply. To work around this problem, use the CPU to transfer the data. ⎯ Conditions Under which Problem Occurs a. Big endian is selected. b. The external memory bus width is 32 bits. c. Data is being transferred from an on-chip peripheral module*1 to external memory. d. The transmit size*2 of the data to be transferred is 32 bits. Conditions a. to d. must all be satisfied. ⎯ Description of Problem When transferring data from an on-chip peripheral module, bits 15 to 8 of the 32-bit data become misaligned. As a result, the data is not transferred correctly. Data that should be transferred: 12 34 56 78 Data actually transferred to external memory: 12 34 12 78 Notes: 1. The registers corresponding to the above conditions are the following. TMU.TCOR0 TMU.TCNT0 TMU.TCOR1 TMU.TCNT1 TMU.TCOR2 TMU.TCNT2 TMU.TCPR2 H-UDI.SDDR 2. Set by the transmit size bits in the DMA channel control register. Rev.7.00 Oct. 10, 2008 Page 653 of 1074 REJ09B0366-0700 Section 14 Direct Memory Access Controller (DMAC) Rev.7.00 Oct. 10, 2008 Page 654 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Section 15 Serial Communication Interface (SCI) 15.1 Overview This LSI is equipped with a single-channel serial communication interface (SCI) and a singlechannel serial communication interface with built-in FIFO registers (SCI with FIFO: SCIF). The SCI can handle both asynchronous and synchronous serial communication. The SCI supports a smart card interface. This is a serial communication function supporting a subset of the ISO/IEC 7816-3 (identification cards) standard. For details, see section 17, Smart Card Interface. The SCIF is a dedicated asynchronous communication serial interface with built-in 16-stage FIFO registers for both transmission and reception. For details, see section 16, Serial Communication Interface with FIFO (SCIF). 15.1.1 Features SCI features are listed below. • Choice of synchronous or asynchronous serial communication mode ⎯ Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A multiprocessor communication function is also provided that enables serial data communication with a number of processors. There is a choice of 12 serial data transfer formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even/odd/none Multiprocessor bit: 1 or 0 Receive error detection: Parity, overrun, and framing errors Break detection: A break can be detected by reading the RxD pin level directly from the serial port register (SCSPTR1) when a framing error occurs. Rev.7.00 Oct. 10, 2008 Page 655 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) • • • • • ⎯ Synchronous mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other chips that have a synchronous communication function. There is a single serial data transfer format. Data length: 8 bits Receive error detection: Overrun errors Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. On-chip baud rate generator allows any bit rate to be selected. Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin Four interrupt sources There are four interrupt sources—transmit-data-empty, transmit-end, receive-data-full, and receive-error—that can issue requests independently. The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) to execute a data transfer. When not in use, the SCI can be stopped by halting its clock supply to reduce power consumption. Rev.7.00 Oct. 10, 2008 Page 656 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus SCRDR1 RxD SCRSR1 SCTDR1 SCTSR1 TxD Parity generation Parity check SCK SCSSR1 SCSCR1 SCSMR1 SCSPTR1 Transmission/ reception control SCBRR1 Pck Baud rate generator Pck/4 Pck/16 Pck/64 Clock External clock TEI TXI RXI ERI SCI Legend: SCRSR1: SCRDR1: SCTSR1: SCTDR1: SCSMR1: SCSCR1: SCSSR1: SCBRR1: SCSPTR1: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Figure 15.1 Block Diagram of SCI Rev.7.00 Oct. 10, 2008 Page 657 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) 15.1.3 Pin Configuration Table 15.1 shows the SCI pin configuration. Table 15.1 SCI Pins Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation MD0/SCK RxD MD7/TxD I/O I/O Input Output Function Clock input/output Receive data input Transmit data output Note: The serial clock pin and transmit data pin function as mode input pins MD0 and MD7 after a power-on reset. They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR1 and the C/A bit in SCSMR1. Break state transmission and detection, can be set in the SCI's SCSPTR1 register. 15.1.4 Register Configuration The SCI has the internal registers shown in table 15.2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to perform transmitter/receiver control. With the exception of the serial port register, the SCI registers are initialized in standby mode and in the module standby state as well as after a power-on reset or manual reset. When recovering from standby mode or the module standby state, the registers must be set again. Rev.7.00 Oct. 10, 2008 Page 658 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Table 15.2 SCI Registers Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Serial port register Abbreviation SCSMR1 SCBRR1 SCSCR1 SCTDR1 SCSSR1 SCRDR1 SCSPTR1 R/W R/W R/W R/W R/W R/(W)* R R/W 1 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'00*2 P4 Address H'FFE00000 H'FFE00004 H'FFE00008 H'FFE0000C H'FFE00010 H'FFE00014 H'FFE0001C Area 7 Address H'1FE00000 H'1FE00004 H'1FE00008 H'1FE0000C H'1FE00010 H'1FE00014 H'1FE0001C Access Size 8 8 8 8 8 8 8 Notes: 1. Only 0 can be written, to clear flags. 2. The value of bits 2 and 0 is undefined. 15.2 15.2.1 Register Descriptions Receive Shift Register (SCRSR1) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCRSR1 is the register used to receive serial data. The SCI sets serial data input from the RxD pin in SCRSR1 in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to SCRDR1 automatically. SCRSR1 cannot be directly read or written to by the CPU. Rev.7.00 Oct. 10, 2008 Page 659 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) 15.2.2 Receive Data Register (SCRDR1) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R SCRDR1 is the register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received data from SCRSR1 to SCRDR1 where it is stored, and completes the receive operation. SCRSR1 is then enabled for reception. Since SCRSR1 and SCRDR1 function as a double buffer in this way, it is possible to receive data continuously. SCRDR1 is a read-only register, and cannot be written to by the CPU. SCRDR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. 15.2.3 Transmit Shift Register (SCTSR1) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCTSR1 is the register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from SCTDR1 to SCTSR1, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCTDR1 to SCTSR1, and transmission started, automatically. However, data transfer from SCTDR1 to SCTSR1 is not performed if the TDRE flag in the serial status register (SCSSR1) is set to 1. SCTSR1 cannot be directly read or written to by the CPU. Rev.7.00 Oct. 10, 2008 Page 660 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) 15.2.4 Transmit Data Register (SCTDR1) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W SCTDR1 is an 8-bit register that stores data for serial transmission. When the SCI detects that SCTSR1 is empty, it transfers the transmit data written in SCTDR1 to SCTSR1 and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to SCTDR1 during serial transmission of the data in SCTSR1. SCTDR1 can be read or written to by the CPU at all times. SCTDR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the module standby state. 15.2.5 Serial Mode Register (SCSMR1) Bit: 7 C/A Initial value: R/W: 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCSMR1 is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SCSMR1 can be read or written to by the CPU at all times. SCSMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit 7—Communication Mode (C/A): Selects asynchronous mode or synchronous mode as the SCI operating mode. Bit 7: C/A 0 1 Description Asynchronous mode Synchronous mode Rev.7.00 Oct. 10, 2008 Page 661 of 1074 REJ09B0366-0700 (Initial value) Section 15 Serial Communication Interface (SCI) Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting, Bit 6: CHR 0 1 Note: * Description 8-bit data 7-bit data* When 7-bit data is selected, the MSB (bit 7) of SCTDR1 is not transmitted. (Initial value) Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5: PE 0 1 Note: * Description Parity bit addition and checking disabled Parity bit addition and checking enabled* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. (Initial value) Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, and when parity addition and checking is disabled in asynchronous mode. Bit 4: O/E 0 1 Description Even parity*1 Odd parity* 2 (Initial value) Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. Rev.7.00 Oct. 10, 2008 Page 662 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set, the STOP bit setting is invalid since stop bits are not added. Bit 3: STOP 0 1 Description 1 stop bit* 1 (Initial value) 2 stop bits*2 Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. For details of the multiprocessor communication function including notes on use, see section 15.3.3, Multiprocessor Communication Function. Bit 2: MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the onchip baud rate generator. The clock source can be selected from Pck, Pck/4, Pck/16, and Pck/64, according to the setting of bits CKS1 and CKS0. Rev.7.00 Oct. 10, 2008 Page 663 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) For the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.9, Bit Rate Register (SCBRR1). Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Note: Pck: Peripheral clock Description Pck clock Pck/4 clock Pck/16 clock Pck/64 clock (Initial value) 15.2.6 Serial Control Register (SCSCR1) Bit: 7 TIE Initial value: R/W: 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W The SCSCR1 register performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCSCR1 can be read or written to by the CPU at all times. SCSCR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCTDR1 to SCTSR1 and the TDRE flag in SCSSR1 is set to 1. Bit 7: TIE 0 1 Note: * Description Transmit-data-empty interrupt (TXI) request disabled* Transmit-data-empty interrupt (TXI) request enabled TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0. (Initial value) Rev.7.00 Oct. 10, 2008 Page 664 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from SCRSR1 to SCRDR1 and the RDRF flag in SCSSR1 is set to 1. Bit 6: RIE 0 1 Note: * Description Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled* (Initial value) Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5: TE 0 1 Description Transmission disabled*1 Transmission enabled*2 (Initial value) Notes: 1. The TDRE flag in SCSSR1 is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to SCTDR1 and the TDRE flag in SCSSR1 is cleared to 0. SCSMR1 setting must be performed to decide the transmit format before setting the TE bit to 1. Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4: RE 0 1 Description Reception disabled*1 Reception enabled* 2 (Initial value) Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SCSMR1 setting must be performed to decide the receive format before setting the RE bit to 1. Rev.7.00 Oct. 10, 2008 Page 665 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR1 is set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) (Initial value) [Clearing conditions] • • 1 Note: * When the MPIE bit is cleared to 0 When data with MPB = 1 is received Multiprocessor interrupts enabled* When receive data including MPB = 1 is received, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCSCR1 are set to 1) and FER and ORER flag setting is enabled. Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables transmit-end interrupt (TEI) request generation when there is no valid transmit data in SCTDR1 at the time for MSB data transmission. Bit 2: TEIE 0 1 Note: * Description Transmit-end interrupt (TEI) request disabled* Transmit-end interrupt (TEI) request enabled* TEI interrupt requests can be cleared by reading 1 from the TDRE flag in SCSSR1, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. (Initial value) Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as the serial clock output pin or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in synchronous mode and in the case of external clock operation (CKE1 = 1). The CKE1 and CKE0 bits must be set before determining the SCI's operating mode with SCSMR1. For details of clock source selection, see table 15.9 in section 15.3, Operation. Rev.7.00 Oct. 10, 2008 Page 666 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Bit 1: CKE1 0 Bit 0: CKE0 0 Description Asynchronous mode Synchronous mode 1 Asynchronous mode Synchronous mode 1 0 Asynchronous mode Synchronous mode 1 Asynchronous mode Synchronous mode Internal clock/SCK pin functions as input pin (input signal ignored)*1 Internal clock/SCK pin functions as serial clock output*1 Internal clock/SCK pin functions as clock output*2 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as 3 clock input* External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*3 External clock/SCK pin functions as serial clock input Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. 15.2.7 Serial Status Register (SCSSR1) Bit: 7 TDRE Initial value: R/W: 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB — R 0 MPBT 0 R/W Note: * Only 0 can be written, to clear the flag. SCSSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SCSSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SCSSR1 is initialized to H'84 by a power-on reset or manual reset, in standby mode, and in the module standby state. Rev.7.00 Oct. 10, 2008 Page 667 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from SCTDR1 to SCTSR1 and the next serial transmit data can be written to SCTDR1. Bit 7: TDRE 0 Description Valid transmit data has been written to SCTDR1 [Clearing conditions] • • 1 When 0 is written to TDRE after reading TDRE = 1 When data is written to SCTDR1 by the DMAC (Initial value) There is no valid transmit data in SCTDR1 [Setting conditions] • • • Power-on reset, manual reset, standby mode, or module standby When the TE bit in SCSCR1 is 0 When data is transferred from SCTDR1 to SCTSR1 and data can be written to SCTDR1 Bit 6—Receive Data Register Full (RDRF): Indicates that the received data has been stored in SCRDR1. Bit 6: RDRF 0 Description There is no valid receive data in SCRDR1 [Clearing conditions] • • • 1 Power-on reset, manual reset, standby mode, or module standby When 0 is written to RDRF after reading RDRF = 1 When data in SCRDR1 is read by the DMAC (Initial value) There is valid receive data in SCRDR1 [Setting condition] When serial reception ends normally and receive data is transferred from SCRSR1 to SCRDR1 Note: SCRDR1 and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCSCR1 is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Rev.7.00 Oct. 10, 2008 Page 668 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5: ORER 0 Description Reception in progress, or reception has ended normally*1 [Clearing conditions] • • 1 Power-on reset, manual reset, standby mode, or module standby When 0 is written to ORER after reading ORER = 1 (Initial value) An overrun error occurred during reception*2 [Setting condition] When the next serial reception is completed while RDRF = 1 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. 2. The receive data prior to the overrun error is retained in SCRDR1, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued either. Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4: FER 0 Description Reception in progress, or reception has ended normally*1 [Clearing conditions] • • 1 Power-on reset, manual reset, standby mode, or module standby When 0 is written to FER after reading FER = 1 (Initial value) A framing error occurred during reception [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 2 when reception ends, and the stop bit is 0* Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to SCRDR1 but the RDRF flag is not set. Serial reception cannot be continued while the FER flag is set to 1. Rev.7.00 Oct. 10, 2008 Page 669 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception with parity addition in asynchronous mode, causing abnormal termination. Bit 3: PER 0 Description Reception in progress, or reception has ended normally*1 [Clearing conditions] • • 1 Power-on reset, manual reset, standby mode, or module standby When 0 is written to PER after reading PER = 1 (Initial value) A parity error occurred during reception*2 [Setting condition] When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SCSMR1 Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. 2. If a parity error occurs, the receive data is transferred to SCRDR1 but the RDRF flag is not set. Serial reception cannot be continued while the PER flag is set to 1. Bit 2—Transmit End (TEND): Indicates that there is no valid data in SCTDR1 when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2: TEND 0 Description Transmission is in progress [Clearing conditions] • • 1 When 0 is written to TDRE after reading TDRE = 1 When data is written to SCTDR1 by the DMAC (Initial value) Transmission has been ended [Setting conditions] • • • Power-on reset, manual reset, standby mode, or module standby When the TE bit in SCSCR1 is 0 When TDRE = 1 on transmission of the last bit of a 1-byte serial transmit character Bit 1—Multiprocessor Bit (MPB)*: This bit is read-only and cannot be written to. The read value is undefined. Rev.7.00 Oct. 10, 2008 Page 670 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Note: * This bit is prepared for storing a multi-processor bit in the received data when the receipt is carried out with a multi-processor format in asynchronous mode. This bit does not function correctly in this LSI. However, do not use the read value from this bit. Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid in synchronous mode, when a multiprocessor format is not used, and when the operation is not transmission. Unlike transmit data, the MPBT bit is not double-buffered, so it is necessary to check whether transmission has been completed before changing its value. Bit 0: MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value) 15.2.8 Serial Port Register (SCSPTR1) Bit: 7 EIO 6 — 0 — 5 — 0 — 4 — 0 — 3 2 1 0 SPB1IO SPB1DT SPB0IO SPB0DT 0 R/W — R/W 0 R/W — R/W Initial value: R/W: 0 R/W SCSPTR1 is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCI) pins. Input data can be read from the RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt. SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0 are initialized to H'00 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined. SCSPTR1 is not initialized in the module standby state or standby mode. Bit 7—Error Interrupt Only (EIO): When the EIO bit is 1, an RXI interrupt request is not sent to the CPU even if the RIE bit is set to 1. When the DMAC is used, this setting means that only Rev.7.00 Oct. 10, 2008 Page 671 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) ERI interrupts are handled by the CPU. The DMAC transfers read data to memory or another peripheral module. This bit specifies enabling or disabling of the RXI interrupt. Bit 7: EIO 0 1 Description When the RIE bit is 1, RXI and ERI interrupts are sent to INTC (Initial value) When the RIE bit is 1, only ERI interrupts are sent to INTC Bits 6 to 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0. Bit 3: SPB1IO 0 1 Description SPB1DT bit value is not output to the SCK pin SPB1DT bit value is output to the SCK pin (Initial value) Bit 2—Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit. The initial value of this bit after a power-on or manual reset is undefined. Bit 2: SPB1DT 0 1 Description Input/output data is low-level Input/output data is high-level Bit 1—Serial Port Break I/O (SPB0IO): Specifies the serial port TxD pin output condition. When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit, the TE bit in SCSCR1 should be cleared to 0. Bit 1: SPB0IO 0 1 Description SPB0DT bit value is not output to the TxD pin SPB0DT bit value is output to the TxD pin (Initial value) Bit 0—Serial Port Break Data (SPB0DT): Specifies the serial port RxD pin input data and TxD pin output data. The TxD pin output condition is specified by the SPB0IO bit (see the description of bit 1, SPB0IO, for details). When the TxD pin is designated as an output, the value of the Rev.7.00 Oct. 10, 2008 Page 672 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) SPB0DT bit is output to the TxD pin. The RxD pin value is read from the SPB0DT bit regardless of the value of the SPB0IO bit. The initial value of this bit after a power-on or manual reset is undefined. Bit 0: SPB0DT 0 1 Description Input/output data is low-level Input/output data is high-level SCI I/O port block diagrams are shown in figures 15.2 to 15.4. Rev.7.00 Oct. 10, 2008 Page 673 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Reset R Q D SPB1IO C SPTRW Reset MD0/SCK D SPB1DT C SPTRW Mode setting register Q R SCI Clock output enable signal Serial clock output signal Serial clock input signal Clock input enable signal * Internal data bus SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C/A bit in SCSMR1. Figure 15.2 MD0/SCK Pin Rev.7.00 Oct. 10, 2008 Page 674 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Reset R Q D SPB0IO C SPTRW Reset MD7/TxD R Q D SPB0DT C SPTRW Mode setting register Serial transmit data Legend: Internal data bus SCI Transmit enable signal SPTRW: Write to SPTR Figure 15.3 MD7/TxD Pin RxD SCI Serial receive data Internal data bus SPTRR Legend: SPTRR: Read SPTR Figure 15.4 RxD Pin Rev.7.00 Oct. 10, 2008 Page 675 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) 15.2.9 Bit Rate Register (SCBRR1) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W SCBRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR1. SCBRR1 can be read or written to by the CPU at all times. SCBRR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the module standby state. The SCBRR1 setting is found from the following equations. Asynchronous mode: N= Pck 64 × 22n – 1 × B × 106 – 1 Synchronous mode: N= Pck 8 × 22n – 1 × B × 106 – 1 Where B: Bit rate (bits/s) N: SCBRR1 setting for baud rate generator (0 ≤ N ≤ 255) Pck: Peripheral module operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SCSMR1 Setting n 0 1 2 3 Clock Pck Pck/4 Pck/16 Pck/64 CKS1 0 0 1 1 CKS0 0 1 0 1 Rev.7.00 Oct. 10, 2008 Page 676 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) The bit rate error in asynchronous mode is found from the following equation: Error (%) = Pck × 106 (N + 1) × B × 64 × 22n – 1 – 1 × 100 Table 15.3 shows sample SCBRR1 settings in asynchronous mode, and table 15.4 shows sample SCBRR1 settings in synchronous mode. Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode Pck (MHz) 2 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (% ) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 –6.99 8.51 0.00 n 1 1 0 0 0 0 0 0 0 0 2.097152 N 148 108 217 108 54 26 13 6 2 1 1 Error (% ) –0.04 0.21 0.21 0.21 –0.70 1.14 –2.48 –2.48 13.78 4.86 n 1 1 0 0 0 0 0 0 0 0 2.4576 N 174 127 255 127 63 31 15 7 3 1 1 Error (% ) –0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 22.88 0.00 n 1 1 1 0 0 0 0 0 0 0 N 212 155 77 155 77 38 19 9 4 2 3 Error (% ) 0.03 0.16 0.16 0.16 0.16 0.16 –2.34 –2.34 –2.34 0.00 –18.62 0 –14.67 0 Rev.7.00 Oct. 10, 2008 Page 677 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Pck (MHz) 3.6864 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 — 0 N 64 191 95 191 95 47 23 11 5 — 2 Error (% ) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 n 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 4 Error (% ) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –6.99 0.00 8.51 n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (% ) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (% ) –0.25 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 1.73 0.00 1.73 Pck (MHz) 6 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (% ) –0.44 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 –2.34 0.00 –2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (% ) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 7.37288 N 130 95 191 95 191 95 47 23 11 6 5 Error (% ) –0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (% ) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 –6.99 Rev.7.00 Oct. 10, 2008 Page 678 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Pck (MHz) 9.8304 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (% ) –0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (% ) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (% ) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 –2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (% ) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 Pck (MHz) 14.7456 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 Error (% ) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (% ) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (% ) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (% ) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –1.36 0.00 1.73 Rev.7.00 Oct. 10, 2008 Page 679 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Pck (MHz) 24 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 Error (% ) –0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 –2.34 n 3 3 2 2 1 1 0 0 0 0 0 24.576 N 108 79 159 79 159 79 159 79 39 24 19 Error (% ) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 126 92 186 92 186 92 186 92 46 28 22 28.7 Error (% ) 0.31 0.46 –0.08 0.46 –0.08 0.46 –0.08 0.46 –0.61 –1.03 1.55 n 3 3 2 2 1 1 0 0 0 0 0 N 132 97 194 97 194 97 194 97 48 29 23 30 Error (% ) 0.13 –0.35 0.16 –0.35 0.16 –0.35 –1.36 –0.35 –0.35 0.00 1.73 Legend: Blank: No setting is available. —: A setting is available but error occurs. Rev.7.00 Oct. 10, 2008 Page 680 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode Pck (MHz) 4 Bit Rate (bits/s) 10 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M n — 2 2 1 1 0 0 0 0 0 0 0 0 N — 249 124 249 99 199 99 39 19 9 3 1 0* n — 3 2 2 1 1 0 0 0 0 0 0 0 0 8 N — 124 249 124 199 99 199 79 39 19 7 3 1 0* n — 3 3 2 2 1 1 0 0 0 0 0 0 0 16 N — 249 124 249 99 199 99 159 79 39 15 7 3 1 n — — 3 3 2 2 1 1 0 0 — — — — 28.7 N — — 223 111 178 89 178 71 143 71 — — — — n — — 3 3 2 2 1 1 0 0 0 0 — — 30 N — — 233 116 187 93 187 74 149 74 29 14 — — Legend: Blank: No setting is available. —: A setting is available but error occurs. * Continuous transmission/reception is not possible. Note: As far as possible, the setting should be made so that the error is within 1%. Rev.7.00 Oct. 10, 2008 Page 681 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Table 15.5 shows the maximum bit rate for various frequencies in asynchronous mode. Tables 15.6 and 15.7 show the maximum bit rates with external clock input. Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pck (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 Maximum Bit Rate (bits/s) 62500 65536 76800 93750 115200 125000 153600 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev.7.00 Oct. 10, 2008 Page 682 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Pck (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 2.0000 2.4576 3.0000 3.6864 4.0000 4.9152 5.0000 6.0000 6.1440 7.1750 7.5000 Maximum Bit Rate (bits/s) 31250 32768 38400 46875 57600 62500 76800 125000 153600 187500 230400 250000 307200 312500 375000 384000 448436 468750 Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) Pck (MHz) 8 16 24 28.7 30 External Input Clock (MHz) 1.3333 2.6667 4.0000 4.7833 5.0000 Maximum Bit Rate (bits/s) 1333333.3 2666666.7 4000000.0 4783333.3 5000000.0 Rev.7.00 Oct. 10, 2008 Page 683 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) 15.3 15.3.1 Operation Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SCSMR1 as shown in table 15.8. The SCI clock source is determined by a combination of the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1, as shown in table 15.9. • Asynchronous mode ⎯ Data length: Choice of 7 or 8 bits ⎯ Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) ⎯ Detection of framing, parity, and overrun errors, and breaks, during reception ⎯ Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output. When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used). • Synchronous mode ⎯ Transfer format: Fixed 8-bit data ⎯ Detection of overrun errors during reception ⎯ Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip. When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock. Rev.7.00 Oct. 10, 2008 Page 684 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection SCSMR1 Settings Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: C/A CHR MP PE STOP Mode 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 * 0 1 1 0 1 1 * * * * Synchronous mode 8-bit data No Asynchronous 8-bit data mode (multiprocessor 7-bit data format) Yes No Yes 7-bit data No Asynchronous mode Data Length 8-bit data SCI Transfer Format Multiprocessor Parity Bit Bit No No Stop Bit Length 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None Note: An asterisk in the table means “Don't care.” Rev.7.00 Oct. 10, 2008 Page 685 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection SCSMR1 Bit 7: C/A 0 SCSCR1 Setting Bit 1: CKE1 0 Bit 0: CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Synchronous mode Internal Outputs serial clock Mode Asynchronous mode SCI Transmit/Receive Clock Clock Source Internal SCK Pin Function SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate External Inputs serial clock 15.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-bycharacter basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.5 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). Rev.7.00 Oct. 10, 2008 Page 686 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the eighth pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data 0 Start bit 1 bit (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 0/1 Parity bit 1 bit, or none 1 Stop bit(s) 1 or 2 bits 1 1 Transmit/receive data 7 or 8 bits One unit of transfer data (character or frame) Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Data Transfer Format Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SCSMR1 setting. Rev.7.00 Oct. 10, 2008 Page 687 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Table 15.10 Serial Transfer Formats (Asynchronous Mode) SCSMR1 Settings CHR PE 0 0 MP 0 STOP 0 1 S 2 Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 * 1 0 S 8-bit data MPB STOP 0 * 1 1 S 8-bit data MPB STOP STOP 1 * 1 0 S 7-bit data MPB STOP 1 * 1 1 S 7-bit data MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Note: An asterisk in the table means “Don't care.” Rev.7.00 Oct. 10, 2008 Page 688 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see table 15.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.6. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 One frame Figure 15.6 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations SCI Initialization (Asynchronous Mode): Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Figure 15.7 shows a sample SCI initialization flowchart. Rev.7.00 Oct. 10, 2008 Page 689 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Initialization 1. Set the clock selection in SCSCR1. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits in SCSCR1 to 0 Set CKE1 and CKE0 bits in SCSCR1 (leaving TE and RE bits cleared to 0) Set transmit/receive format in SCSMR1 Set value in SCBRR1 Wait No When clock output is selected in asynchronous mode, it is output immediately after SCSCR1 settings are made. 2. Set the transmit/receive format in SCSMR1. 3. Write a value corresponding to the bit rate into SCBRR1. (Not necessary if an external clock is used.) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR1 to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the SCI will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. 1-bit interval elapsed? Yes Set TE and RE bits in SCSCR1 to 1, and set RIE, TIE, TEIE, and MPIE bits End Figure 15.7 Sample SCI Initialization Flowchart Serial Data Transmission (Asynchronous Mode): Figure 15.8 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. Rev.7.00 Oct. 10, 2008 Page 690 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Start of transmission Read TDRE flag in SCSSR1 No 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. 2. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) 3. Break output at the end of serial transmission: To output a break in serial transmission, clear the SPB0DT bit to 0 and set the SPB0IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR1 to 0. TDRE = 1? Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 All data transmitted? Yes Read TEND flag in SCSSR1 No TEND = 1? Yes Break output? Yes Clear SPB0DT to 0 and set SPB0IO to 1 Clear TE bit in SCSCR1 to 0 No No End of transmission Figure 15.8 Sample Serial Transmission Flowchart Rev.7.00 Oct. 10, 2008 Page 691 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. (A format in which neither a parity bit nor a multiprocessor bit is output can also be selected.) d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from SCTDR1 to SCTSR1, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. If the TEIE bit in SCSCR1 is set to 1 at this time, a TEI interrupt request is generated. Figure 15.9 shows an example of the operation for transmission in asynchronous mode. Rev.7.00 Oct. 10, 2008 Page 692 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Serial data 1 Idle state (mark state) TDRE TEND TXI interrupt TXI interrupt request request Data written to SCTDR1 and TDRE flag cleared to 0 by TXI interrupt handler One frame TEI interrupt request Figure 15.9 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Serial Data Reception (Asynchronous Mode): Figure 15.10 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. Rev.7.00 Oct. 10, 2008 Page 693 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) 1. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SCSSR1 to identify the error. After performing the appropriate error handling, ensure that the ORER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the RxD pin. 2. SCI status check and receive data read : Read SCSSR1 and check that RDRF = 1, then read the receive data in SCRDR1 and clear the RDRF flag to 0. 3. Serial reception continuation procedure: To continue serial reception, complete zeroclearing of the RDRF flag before the stop bit for the current frame is received. (The RDRF flag is cleared automatically when the direct memory access controller (DMAC) is activated by an RXI interrupt and the SCRDR1 value is read.) Start of reception Read ORER, PER, and FER flags in SCSSR1 PER or FER or ORER = 1? No Read RDRF flag in SCSSR1 No Yes Error handling RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data received? Yes Clear RE bit in SCSCR1 to 0 End of reception Figure 15.10 Sample Serial Reception Flowchart (1) Rev.7.00 Oct. 10, 2008 Page 694 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCSCR1 to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SCSSR1 to 0 End Figure 15.10 Sample Serial Reception Flowchart (2) Rev.7.00 Oct. 10, 2008 Page 695 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. a. Parity check: The SCI checks whether the number of 1-bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SCSMR1. b. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. c. Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from SCRSR1 to SCRDR1. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in SCRDR1. If a receive error is detected in the error check, the operation is as shown in table 15.11. Note: No further receive operations can be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. 4. If the EIO bit in SCSPTR1 is cleared to 0 and the RIE bit in SCSCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCSCR1 is set to 1 when the ORER, PER, or FER flag changes to 1, a receive-error interrupt (ERI) request is generated. A receive-data-full request is always output to the DMAC when the RDRF flag changes to 1. Table 15.11 Receive Error Conditions Receive Error Overrun error Abbreviation ORER Condition Reception of next data is completed while RDRF flag in SCSSR1 is set to 1 Stop bit is 0 Received data parity differs from that (even or odd) set in SCSMR1 Data Transfer Receive data is not transferred from SCRSR1 to SCRDR1 Receive data is transferred from SCRSR1 to SCRDR1 Receive data is transferred from SCRSR1 to SCRDR1 Framing error Parity error FER PER Rev.7.00 Oct. 10, 2008 Page 696 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Figure 15.11 shows an example of the operation for reception in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 0/1 1 Serial data RDRF FER RXI interrupt request One frame SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler ERI interrupt request generated by framing error Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) Rev.7.00 Oct. 10, 2008 Page 697 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) 15.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a serial transmission line. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two cycles: an ID transmission cycle which specifies the receiving station , and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent*. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received*. In this way, data communication is carried out among a number of processors. Figure 15.12 shows an example of inter-processor communication using a multiprocessor format. Note: * With this LSI, the RDRF flag in SCSSR1 is also set to 1 when data with a 0 multiprocessor bit transmitted to another station is received. When the RDRF flag in SCSSR1 is set to 1, check the state of the MPIE bit in SCSCR1 with the exception handling routine, and if the MPIE bit is 1, skip the data. That is to say, data skipping is implemented in cooperation with the exception handling routine. Rev.7.00 Oct. 10, 2008 Page 698 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Transmitting station Serial transmission line Receiving station A (ID = 01) Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) Serial data H'01 (MPB = 1) ID transmission cycle: Receiving station specification H'AA (MPB = 0) Data transmission cycle: Data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Data Transfer Formats There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 15.10. Clock See the description under Clock in section 15.3.2, Operation in Asynchronous Mode. Data Transfer Operations Multiprocessor Serial Data Transmission: Figure 15.13 shows a sample flowchart for multiprocessor serial data transmission. Use the following procedure for multiprocessor serial data transmission after enabling the SCI for transmission. Rev.7.00 Oct. 10, 2008 Page 699 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Start of transmission 1. SCI status check and ID data write: Read SCSSR1 and check that the TEND flag is set to 1, then set the MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1. Finally, clear the TDRE flag to 0. 2. Preparation for data transfer: Read SCSSR1 and check that the TEND flag is set to 1, then set the MPBT bit in SCSSR1 to 1. 3. Serial data transmission: Write the first transmit data to SCTDR1, then clear the TDRE flag to 0. To continue data transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) Read TEND flag in SCSSR1 No TEND = 1? Yes Set MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1 Clear TDRE flag to 0 Read TEND flag in SCSSR1 No TEND = 1? Yes Clear MPBT bit in SCSSR1 to 0 Write data to SCTDR1 Clear TDRE flag to 0 Read TDRE flag in SCSSR1 No TDRE = 1? Yes No All data transmitted? Yes End of transmission Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart Rev.7.00 Oct. 10, 2008 Page 700 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 4. The SCI monitors the TDRE flag. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 5. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE bit) in SCSCR1 is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. The order of transmission is the same as in step 2. Figure 15.14 shows an example of SCI operation for transmission using a multiprocessor format. Rev.7.00 Oct. 10, 2008 Page 701 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Multiproces- Stop sor bit bit Multiproces- Stop Start bit sor bit bit Multiproces- Stop sor bit bit 1 Serial data Start bit Data Start bit Data Data 1 0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 0 D0 D1 D7 0 Idle state (mark state) TDRE TEND One frame Data written to SCTDR1 and TDRE flag cleared to 0 by TXI interrupt handler MPBT bit cleared to 0, data written to SCTDR1, and TDRE flag cleared to 0 by TEI interrupt handler TXI interrupt request TEI interrupt request Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Multiprocessor Serial Data Reception: Figure 15.15 shows a sample flowchart for multiprocessor serial reception. Use the following procedure for multiprocessor serial data reception after enabling the SCI for reception. 1. Method for determining whether an interrupt generated during receive operation is a multiprocessor interrupt When an interrupt such as RXI occurs during receive operation using the on-chip SCI multiprocessor communication function, check the state of the MPIE bit in the SCSCR1 register as part of the interrupt handling routine. a. If the MPIE bit in the SCSCR1 register is set to 1 Ignore the received data. Data with the multiprocessor bit (MPB) set to 0 and intended for another station was received, and the RDRF bit in the SCSCR1 register was set to 1. Therefore, clear the RDRF bit in the SCSCR1 register to 0. Rev.7.00 Oct. 10, 2008 Page 702 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) b. If the MPIE bit in the SCSCR1 register is cleared to 0 A multiprocessor interrupt indicating that data (ID) with the multiprocessor bit (MPB) set to 1 was received, or a receive data full interrupt (RXI) occurred when data with the multiprocessor bit (MPB) set to 0 and intended for this station was received. 2. Method for determining whether received data is ID or data Do not use the MPB bit in the SCSSR1 register for software processing. When using software processing to determine whether received data is ID (MPB = 1) or data (MPB = 0), use a procedure such as saving a user-defined flag in memory to indicate receive start. Rev.7.00 Oct. 10, 2008 Page 703 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Start of reception Set MPIE bit to 1 RXI = 1? Yes Yes No User-defined receive start flag = 1? No Read ORER and FER flags in SCSSR1 FER or ORER = 1? No Yes Read RDRF flag in SCSSR1 No MPIE = 0? Yes Read receive data in SCRDR1 No This station's ID? Yes Set RDRF = 0 and MPIE = 1 Set user-defined receive start flag to 1 End of ID reception handling Read ORER and FER flags in SCSSR1 FER or ORER = 1? No Yes Read receive data in SCRDR1 No All data received? Yes Clear user-defined receive start flag to 0 RTE End of data reception Error handling Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1) Rev.7.00 Oct. 10, 2008 Page 704 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit in SCSCR1 to 0 Yes Clear ORER and FER flags in SCSSR1 to 0 End Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2) Rev.7.00 Oct. 10, 2008 Page 705 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Figure 15.16 shows an example of SCI operation for multiprocessor format reception. Start Data (ID1) bit 0 D0 D1 D7 Stop Start MPB bit bit 1 1 0 Data (Data1) D0 D1 D7 Stop MPB bit 0 1 1 Serial data 1 Idle state (mark state) MPIE RDRF SCRDR1 value RXI interrupt request (multiprocessor interrupt) MPIE = 0 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler ID1 As data is not this RXI interrupt station's ID, MPIE request bit is set to 1 again MPIE = 1 The RDRF flag is cleared to 0 by the RXI interrupt handler. (a) Data does not match station's ID Start Data (ID2) bit 0 D0 D1 D7 Stop Start MPB bit bit 1 1 0 Data (Data2) D0 D1 D7 Stop MPB bit 0 1 1 Serial data 1 Idle state (mark state) MPIE RDRF SCRDR1 value ID1 ID2 Data2 RXI interrupt request (multiprocessor interrupt) MPIE = 0 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler As data matches this station's ID, reception continues and data is received by RXI interrupt handler MPIE bit set to 1 again (b) Data matches station's ID Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev.7.00 Oct. 10, 2008 Page 706 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) In multiprocessor mode serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3. If the MPIE bit is 1, MPIE is cleared to 0 when a 1 is received in the multiprocessor bit position. If the multiprocessor bit is 0, the MPIE bit is not changed. 4. If the MPIE bit is 0, RDRF is checked at the stop bit position, and if RDRF is 1 the overrun error bit is set. If the stop bit is not 0, the framing error bit is set. If RDRF is 0, the value in SCRSR1 is transferred to SCRDR1, and if the stop bit is 0, RDRF is set to 1. 15.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.17 shows the general format for synchronous serial communication. One unit of transfer data (character or frame) * Serial clock LSB Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 * MSB Bit 7 Don't care Note: * High except in continuous transmission/reception Figure 15.17 Data Format in Synchronous Communication In synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. Rev.7.00 Oct. 10, 2008 Page 707 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) In serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In synchronous mode, the SCI receives data in synchronization with the falling edge of the serial clock. Data Transfer Format A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see table 15.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. In reception only, if an on-chip clock source is selected, clock pulses are output while RE = 1. When the last data is received, RE should be cleared to 0 before the end of bit 7. Data Transfer Operations SCI Initialization (Synchronous Mode): Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1. Rev.7.00 Oct. 10, 2008 Page 708 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Figure 15.18 shows a sample SCI initialization flowchart. 1. Set the clock selection in SCSCR1. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. 2. Set transmit/receive format in SCSMR1. 3. Write a value corresponding to the bit rate into SCBRR1. (Not necessary if an external clock is used.) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR1 to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Initialization Clear TE and RE bits in SCSCR1 to 0 Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCSCR1 (leaving TE and RE bits cleared to 0) Set transmit/receive format in SCSMR1 Set value in SCBRR1 Wait No 1-bit interval elapsed? Yes Set TE and RE bits in SCSCR1 to 1, and set RIE, TIE, TEIE, and MPIE bits End Figure 15.18 Sample SCI Initialization Flowchart Rev.7.00 Oct. 10, 2008 Page 709 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Serial Data Transmission (Synchronous Mode): Figure 15.19 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. No 2. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) Start of transmission Read TDRE flag in SCSSR1 TDRE = 1? Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 All data transmitted? Yes Read TEND flag in SCSSR1 No TEND = 1? Yes Clear TE bit in SCSCR1 to 0 No End Figure 15.19 Sample Serial Transmission Flowchart Rev.7.00 Oct. 10, 2008 Page 710 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). 3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from SCTDR1 to SCTSR1, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 4. After completion of serial transmission, the SCK pin is fixed high. Figure 15.20 shows an example of SCI operation in transmission. Rev.7.00 Oct. 10, 2008 Page 711 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Transfer direction Serial clock LSB Serial data Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND Data written to SCTDR1 and TDRE flag cleared to 0 in TXI interrupt handler One frame TXI interrupt request TEI interrupt request TXI interrupt request Figure 15.20 Example of SCI Transmit Operation Rev.7.00 Oct. 10, 2008 Page 712 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Serial Data Reception (Synchronous Mode): Figure 15.21 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. 1. Receive error handling: If a receive error occurs, read the ORER flag in SCSSR1 , and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. 2. SCI status check and receive data read: Read SCSSR1 and check that the RDRF flag is set to 1, then read the receive data in SCRDR1 and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. 3. Serial reception continuation procedure: To continue serial reception, finish reading the RDRF flag, reading SCRDR1, and clearing the RDRF flag to 0, before the MSB (bit 7) of the current frame is received. (The RDRF flag is cleared automatically when the direct memory access controller (DMAC) is activated by a receive-data-full interrupt (RXI) request and the SCRDR1 value is read.) Start of reception Read ORER flag in SCSSR1 ORER = 1? No Read RDRF flag in SCSSR1 No Yes Error handling RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data received? Yes Clear RE bit in SCSCR1 to 0 End of reception Figure 15.21 Sample Serial Reception Flowchart (1) Rev.7.00 Oct. 10, 2008 Page 713 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag in SCSSR1 to 0 End Figure 15.21 Sample Serial Reception Flowchart (2) In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with serial clock input or output. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from SCRSR1 to SCRDR1. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in SCRDR1. If a receive error is detected in the error check, the operation is as shown in table 15.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. Also, as the RDRF flag is not set to 1 when receiving, the flag must be cleared to 0. 3. If the RIE bit in SCRSR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCRSR1 is set to 1 when the ORER flag changes to 1, a receive-error interrupt (ERI) request is generated. Rev.7.00 Oct. 10, 2008 Page 714 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Figure 15.22 shows an example of SCI operation in reception. Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request Data read from SCRDR1 and RDRF flag cleared to 0 in RXI interrupt handler One frame RXI interrupt request ERI interrupt request due to overrun error Figure 15.22 Example of SCI Receive Operation Simultaneous Serial Data Transmission and Reception (Synchronous Mode): Figure 15.23 shows a sample flowchart for simultaneous serial transmit and receive operations. Use the following procedure for simultaneous serial data transmit and receive operations after enabling the SCI for transmission and reception. Rev.7.00 Oct. 10, 2008 Page 715 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. 2. Receive error handling: If a receive error occurs, read the ORER flag in SCSSR1 , and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. Start of transmission/reception Read TDRE flag in SCSSR1 No TDRE = 1? Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 3. SCI status check and receive data read: Read ORER flag in SCSSR1 Read SCSSR1 and check that the RDRF flag is set to 1, then read the receive data in SCRDR1 and clear the Yes ORER = 1? RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. No Error handling Read RDRF flag in SCSSR1 No RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data transferred? Yes Clear TE and RE bits in SCRSR1 to 0 End of transmission/reception 4. Serial transmission/reception continuation procedure: To continue serial transmission/ reception, finish reading the RDRF flag, reading SCRDR1, and clearing the RDRF flag to 0, before the MSB (bit 7) of the current frame is received. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1 and clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the DMAC is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1. Similarly, the RDRF flag is cleared automatically when the DMAC is activated by a receive-data-full interrupt (RXI) request and the SCRDR1 value is read.) Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1. Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception Rev.7.00 Oct. 10, 2008 Page 716 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) 15.4 SCI Interrupt Sources and DMAC The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 15.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCRSR1, and the EIO bit in SCSPTR1. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in the serial status register (SCSSR1) is set to 1, a TDR-empty request is generated separately from the interrupt request. A TDR-empty request can activate the direct memory access controller (DMAC) to perform data transfer. The TDRE flag is cleared to 0 automatically when a write to the transmit data register (SCTDR1) is performed by the DMAC. When the RDRF flag in SCSSR1 is set to 1, an RDR-full request is generated separately from the interrupt request. An RDR-full request can activate the DMAC to perform data transfer. The RDRF flag is cleared to 0 automatically when a receive data register (SCRDR1) read is performed by the DMAC. When the ORER, FER, or PER flag in SCSSR1 is set to 1, an ERI interrupt request is generated. The DMAC cannot be activated by an ERI interrupt request. When receive data processing is to be carried out by the DMAC and receive error handling is to be performed by means of an interrupt to the CPU, set the RIE bit to 1 and also set the EIO bit in SCSPTR1 to 1 so that an interrupt error occurs only for a receive error. If the EIO bit is cleared to 0, interrupts to the CPU will be generated even during normal data reception. When the TEND flag in SCSSR1 is set to 1, a TEI interrupt request is generated. The DMAC cannot be activated by a TEI interrupt request. A TXI interrupt indicates that transmit data can be written, and a TEI interrupt indicates that the transmit operation has ended. Rev.7.00 Oct. 10, 2008 Page 717 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Table 15.12 SCI Interrupt Sources Interrupt Source ERI RXI TXI TEI Description Receive error (ORER, FER, or PER) Receive data register full (RDRF) Transmit data register empty (TDRE) Transmit end (TEND) DMAC Activation Priority on Reset Release Not possible High Possible Possible Not possible Low See section 5, Exceptions, for the priority order and relation to non-SCI interrupts. 15.5 Usage Notes The following points should be noted when using the SCI. SCTDR1 Writing and the TDRE Flag: The TDRE flag in SCSSR1 is a status flag that indicates that transmit data has been transferred from SCTDR1 to SCTSR1. When the SCI transfers data from SCTDR1 to SCTSR1, the TDRE flag is set to 1. Data can be written to SCTDR1 regardless of the state of the TDRE flag. However, if new data is written to SCTDR1 when the TDRE flag is cleared to 0, the data stored in SCTDR1 will be lost since it has not yet been transferred to SCTSR1. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to SCTDR1. Simultaneous Multiple Receive Errors: If a number of receive errors occur at the same time, the state of the status flags in SCSSR1 is as shown in table 15.13. If there is an overrun error, data is not transferred from SCRSR1 to SCRDR1, and the receive data is lost. Rev.7.00 Oct. 10, 2008 Page 718 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data SCSSR1 Status Flags Receive Errors Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer SCRSR1 → SCRDR1 X O O X X O X Legend: O: Receive data is transferred from SCRSR1 to SCRDR1. X: Receive data is not transferred from SCRSR1 to SCRDR1. Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that the SCI receiver continues to operate in the break state, so if the FER flag is cleared to 0 it will be set to 1 again. Sending a Break Signal: The input/output condition and level of the TxD pin are determined by bits SPB0IO and SPB0DT in the serial port register (SCSPTR1). This feature can be used to send a break signal. After the serial transmitter is initialized, the TxD pin function is not selected and the value of the SPB0DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled). The SPB0IO and SPB0DT bits should therefore be set to 1 (designating output and high level) beforehand. To send a break signal during serial transmission, clear the SPB0DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of its current state, and the TxD pin becomes an output port outputting the value 0. Rev.7.00 Oct. 10, 2008 Page 719 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Handling of TEND Flag and TE Bit: The TEND flag is set to 1 when the stop bit of the final data segment is transmitted. If the TE bit is cleared immediately after confirming that the TEND flag was set, transmission may not complete properly because stop bit transmission processing is still underway. Therefore, wait at least 0.5 serial clock cycles (1.5 cycles if two stop bits are used) after confirming that the TEND flag was set before clearing the TE bit. Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is set to 1. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags are not cleared to 0 by clearing the RE bit to 0. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: The SCI operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 15.24. 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks +7.5 clocks Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode Rev.7.00 Oct. 10, 2008 Page 720 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = (0.5 – 1 | D – 0.5 | ) – (L – 0.5) F – (1 + F) × 100% ................ (1) 2N N M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 – 1/(2 × 16)) × 100% = 46.875% ............................................ (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. When Using the DMAC: • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 peripheral operating clock cycles after SCTDR1 is updated by the DMAC. Incorrect operation may result if the transmit clock is input within 4 cycles after SCTDR1 is updated. (See figure 15.25) SCK t TDRE TxD D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t > 4. Figure 15.25 Example of Synchronous Transmission by DMAC • When SCRDR1 is read by the DMAC, be sure to set the SCI receive-data-full interrupt (RXI) as the activation source with bits RS3 to RS0 in CHCR. Rev.7.00 Oct. 10, 2008 Page 721 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) • When using the DMAC for transmission/reception, making a setting to disable RXI and TXI interrupt requests to the interrupt controller. Even if issuance of interrupt requests is set, interrupt requests to the interrupt controller will be cleared by the DMAC independently of the interrupt handling program. When Using Synchronous External Clock Mode: • Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock SCK has changed from 0 to 1. • Only set both TE and RE to 1 when external clock SCK is 1. • In reception, note that if RE is cleared to 0 from 2.5 to 3.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK input, RDRF will be set to 1 but copying to SCRDR1 will not be possible. When Using Synchronous Internal Clock Mode: In reception, note that if RE is cleared to zero 1.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output, RDRF will be set to 1 but copying to SCRDR1 will not be possible. When Using DMAC: When using the DMAC for transmission/reception, make a setting to suppress output of RXI and TXI interrupt requests to the interrupt controller. Even if a setting is made to output interrupt requests, interrupt requests to the interrupt controller will be cleared by the DMAC independently of the interrupt handling program. SH7750 Only: When the following conditions are satisfied, the same data may be transmitted multiple times. • Conditions Under which Problem Occurs a. External SCK clock input mode is selected (SCSCR1.CKE1 = 1). b. Synchronous mode is selected (SCSMR1C/A = 1). c. Transmit or receive is in progress (SCSCR1.TE = 1). Conditions a. to c. must all be satisfied. • Workarounds Workaround 1 ⎯ PLL2 on As shown in figure 15.26, after synchronizing asynchronous input external clock SCK with CKIO, input it to the SCK pin of the SH7750. In this case the SCK clock cycle minimum value will be: peripheral clock cycle (Pck) × 8. Note that this workaround will reduce the timing margins of the TxD and RxD pins synchronized with the SCK pin. ⎯ PLL2 off Operation cannot be guaranteed. (Usage prohibited.) Rev.7.00 Oct. 10, 2008 Page 722 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Workaround 2 Do not select settings a., b., and c. at the same time. Multiplexer (switches between clock mode and SCK input) Mode setting signal SH7750 Edge trigger FF DQ B A MD0/SCK CKIO Figure 15.26 Example Countermeasure on SH7750 • Clock Timing Make sure that the timing of the clock input to the SCK pin, including the delay from edge trigger FF and the multiplexer in figure 15.26, conforms to that shown below. CKIO tSCKH SCK tSCKS tSCKH tSCKS Figure 15.27 Clock Input Timing of SCK Pin Rev.7.00 Oct. 10, 2008 Page 723 of 1074 REJ09B0366-0700 Section 15 Serial Communication Interface (SCI) Table 15.14 Peripheral Module Signal Timing tSCKS Product HD6417750BP200 HD6417750BP200M HD6417750F167 HD6417750F167I HD6417750VF128 Min 5 5 5 5 8 Max ⎯ ⎯ ⎯ ⎯ ⎯ Min 0 0 0 0 0 tSCKH Max ⎯ ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns ns Rev.7.00 Oct. 10, 2008 Page 724 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Section 16 Serial Communication Interface with FIFO (SCIF) 16.1 Overview This LSI is equipped with a single-channel serial communication interface with built-in FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous serial communication. Sixteen-stage FIFO registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. 16.1.1 Features SCIF features are listed below. • Asynchronous serial communication Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). There is a choice of 8 serial data transfer formats. ⎯ Data length: 7 or 8 bits ⎯ Stop bit length: 1 or 2 bits ⎯ Parity: Even/odd/none ⎯ Receive error detection: Parity, framing, and overrun errors ⎯ Break detection: If the receive data following that in which a framing error occurred is also at the space “0” level, and there is a frame error, a break is detected. When a framing error occurs, a break can also be detected by reading the RxD2 pin level directly from the serial port register (SCSPTR2). • Full-duplex communication capability The transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling fast and continuous serial data transmission and reception. • On-chip baud rate generator allows any bit rate to be selected. Rev.7.00 Oct. 10, 2008 Page 725 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) • Choice of serial clock source: internal clock from baud rate generator or external clock from SCK2 pin • Four interrupt sources There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error—that can issue requests independently. • The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt. • When not in use, the SCIF can be stopped by halting its clock supply to reduce power consumption. • Modem control functions (RTS2 and CTS2) are provided. • The amount of data in the transmit/receive FIFO registers, and the number of receive errors in the receive data in the receive FIFO register, can be ascertained. • A timeout error (DR) can be detected during reception. Rev.7.00 Oct. 10, 2008 Page 726 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the SCIF. Bus interface Module data bus Internal data bus SCFRDR2 (16-stage) SCFTDR2 (16-stage) RxD2 SCRSR2 SCTSR2 SCSMR2 SCLSR2 SCFDR2 SCFCR2 SCFSR2 SCSCR2 SCSPTR2 Transmission/ reception control SCBRR2 Pck Baud rate generator Pck/4 Pck/16 Pck/64 Clock TxD2 Parity generation Parity check SCK2 CTS2 RTS2 External clock TXI RXI ERI BRI SCIF Legend: SCRSR2: SCFRDR2: SCTSR2: SCFTDR2: SCSMR2: SCSCR2: Receive shift register Receive FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register SCFSR2: SCBRR2: SCSPTR2: SCFCR2: SCFDR2: SCLSR2: Serial status register Bit rate register Serial port register FIFO control register FIFO data count register Line status register Figure 16.1 Block Diagram of SCIF Rev.7.00 Oct. 10, 2008 Page 727 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) 16.1.3 Pin Configuration Table 16.1 shows the SCIF pin configuration. Table 16.1 SCIF Pins Pin Name Serial clock pin Receive data pin Transmit data pin Modem control pin Modem control pin Abbreviation SCK2/MRESET MD2/RxD2 MD1/TxD2 CTS2 MD8/RTS2 I/O Input Input Output I/O I/O Function Clock input Receive data input Transmit data output Transmission enabled Transmission request Note: After a power-on reset, these pins function as mode input pins MD1, MD2, and MD8. These pins can function as serial pins by setting the SCIF operation with the TE, RE, and CKE1 bits in SCSCR2 and the MCE bit in SCFCR2. These pins are made to function as serial pins by performing SCIF operation settings with the TE, RE, and CKE1 bits in SCSCR2 and the MCE bit in SCFCR2. Break state transmission and detection can be set in the SCIF's SCSPTR2 register. Rev.7.00 Oct. 10, 2008 Page 728 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) 16.1.4 Register Configuration The SCIF has the internal registers shown in table 16.2. These registers are used to specify the data format and bit rate, and to perform transmitter/receiver control. Table 16.2 SCIF Registers Name Serial mode register Bit rate register Serial control register Abbreviation R/W SCSMR2 SCBRR2 SCSCR2 R/W R/W R/W R/(W)* 1 Initial Value H'0000 H'FF H'0000 P4 Address Area 7 Address Access Size H'FFE80000 H'1FE80000 16 H'FFE80004 H'1FE80004 8 H'FFE80008 H'1FE80008 16 Transmit FIFO data register SCFTDR2 W Serial status register SCFSR2 Undefined H'FFE8000C H'1FE8000C 8 H'0060 H'FFE80010 H'1FE80010 16 Receive FIFO data register SCFRDR2 R FIFO control register FIFO data count register Serial port register Line status register SCFCR2 SCFDR2 R/W R Undefined H'FFE80014 H'1FE80014 8 H'0000 H'0000 H'0000*2 H'FFE80018 H'1FE80018 16 H'FFE8001C H'1FE8001C 16 H'FFE80020 H'1FE80020 16 H'FFE80024 H'1FE80024 16 SCSPTR2 R/W SCLSR2 R/(W)*3 H'0000 Notes: 1. Only 0 can be written, to clear flags. Bits 15 to 8, 3, and 2 are read-only, and cannot be modified. 2. The value of bits 6, 4, and 0 is undefined. 3. Only 0 can be written, to clear flags. Bits 15 to 1 are read-only, and cannot be modified. 16.2 16.2.1 Register Descriptions Receive Shift Register (SCRSR2) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCRSR2 is the register used to receive serial data. The SCIF sets serial data input from the RxD2 pin in SCRSR2 in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to the receive FIFO register, SCFRDR2, automatically. Rev.7.00 Oct. 10, 2008 Page 729 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) SCRSR2 cannot be directly read or written to by the CPU. 16.2.2 Receive FIFO Data Register (SCFRDR2) Bit: 7 6 5 4 3 2 1 0 R/W: R R R R R R R R SCFRDR2 is a 16-stage FIFO register that stores received serial data. When the SCIF has received one byte of serial data, it transfers the received data from SCRSR2 to SCFRDR2 where it is stored, and completes the receive operation. SCRSR2 is then enabled for reception, and consecutive receive operations can be performed until the receive FIFO register is full (16 data bytes). SCFRDR2 is a read-only register, and cannot be written to by the CPU. If a read is performed when there is no receive data in the receive FIFO register, an undefined value will be returned. When the receive FIFO register is full of receive data, subsequent serial data is lost. The contents of SCFRDR2 are undefined after a power-on reset or manual reset. 16.2.3 Transmit Shift Register (SCTSR2) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCTSR2 is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR2 to SCTSR2, then sends the data to the TxD2 pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCFTDR2 to SCTSR2, and transmission started, automatically. SCTSR2 cannot be directly read or written to by the CPU. Rev.7.00 Oct. 10, 2008 Page 730 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.4 Transmit FIFO Data Register (SCFTDR2) Bit: 7 6 5 4 3 2 1 0 R/W: W W W W W W W W SCFTDR2 is an 8-bit 16-stage FIFO register that stores data for serial transmission. If SCTSR2 is empty when transmit data has been written to SCFTDR2, the SCIF transfers the transmit data written in SCFTDR2 to SCTSR2 and starts serial transmission. SCFTDR2 is a write-only register, and cannot be read by the CPU. The next data cannot be written when SCFTDR2 is filled with 16 bytes of transmit data. Data written in this case is ignored. The contents of SCFTDR2 are undefined after a power-on reset or manual reset. 16.2.5 Serial Mode Register (SCSMR2) Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 CHR 0 R/W 13 — 0 R 5 PE 0 R/W 12 — 0 R 4 O/E 0 R/W 11 — 0 R 3 STOP 0 R/W 10 — 0 R 2 — 0 R 9 — 0 R 1 CKS1 0 R/W 8 — 0 R 0 CKS0 0 R/W SCSMR2 is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate generator clock source. SCSMR2 can be read or written to by the CPU at all times. SCSMR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0. Rev.7.00 Oct. 10, 2008 Page 731 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 6—Character Length (CHR): Selects 7 or 8 bits as the asynchronous mode data length. Bit 6: CHR 0 1 Note: * Description 8-bit data 7-bit data* When 7-bit data is selected, the MSB (bit 7) of SCFTDR2 is not transmitted. (Initial value) Bit 5—Parity Enable (PE): Selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. Bit 5: PE 0 1 Note: * Description Parity bit addition and checking disabled Parity bit addition and checking enabled* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. (Initial value) Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking. The O/E bit setting is invalid when parity addition and checking is disabled. Bit 4: O/E 0 1 Description Even parity*1 Odd parity*2 (Initial value) Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. Rev.7.00 Oct. 10, 2008 Page 732 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length. Bit 3: STOP 0 1 Description 1 stop bit*1 2 stop bits* 2 (Initial value) Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2—Reserved: This bit is always read as 0, and should only be written with 0. Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the onchip baud rate generator. The clock source can be selected from Pck, Pck/4, Pck/16, and Pck/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 16.2.8, Bit Rate Register (SCBRR2). Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Note: Pck: Peripheral clock Description Pck clock Pck/4 clock Pck/16 clock Pck/64 clock (Initial value) Rev.7.00 Oct. 10, 2008 Page 733 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.6 Serial Control Register (SCSCR2) Bit: 15 — Initial value: R/W: Bit: 0 R 7 TIE Initial value: R/W: 0 R/W 14 — 0 R 6 RIE 0 R/W 13 — 0 R 5 TE 0 R/W 12 — 0 R 4 RE 0 R/W 11 — 0 R 3 REIE 0 R/W 10 — 0 R 2 — 0 R 9 — 0 R 1 CKE1 0 R/W 8 — 0 R 0 — 0 R The SCSCR2 register performs enabling or disabling of SCIF transfer operations, and interrupt requests, and selection of the serial clock source. SCSCR2 can be read or written to by the CPU at all times. SCSCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 8, 2, and 0—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCFTDR2 to SCTSR2, the number of data bytes in the transmit FIFO register falls to or below the transmit trigger set number, and the TDFE flag in the serial status register (SCFSR2) is set to 1. Bit 7: TIE 0 1 Note: * Description Transmit-FIFO-data-empty interrupt (TXI) request disabled* Transmit-FIFO-data-empty interrupt (TXI) request enabled TXI interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to SCFTDR2 after reading 1 from the TDFE flag, then clearing it to 0, or by clearing the TIE bit to 0. (Initial value) Rev.7.00 Oct. 10, 2008 Page 734 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 6—Receive Interrupt Enable (RIE): Enables or disables generation of a receive-data-full interrupt (RXI) request when the RDF flag or DR flag in SCFSR2 is set to 1, a receive-error interrupt (ERI) request when the ER flag in SCFSR2 is set to 1, and a break interrupt (BRI) request when the BRK flag in SCFSR2 or the ORER flag in SCLSR2 is set to 1. Bit 6: RIE 0 1 Note: * Description Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request disabled* (Initial value) Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request enabled An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag, then clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCIF. Bit 5: TE 0 1 Note: Description Transmission disabled Transmission enabled* * Serial transmission is started when transmit data is written to SCFTDR2 in this state. Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set to 1. (Initial value) Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCIF. Bit 4: RE 0 1 Description Reception disabled*1 Reception enabled*2 (Initial value) Notes: 1. Clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER flags, which retain their states. 2. Serial transmission is started when a start bit is detected in this state. Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be made, the reception format decided, and the receive FIFO reset, before the RE bit is set to 1. Rev.7.00 Oct. 10, 2008 Page 735 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 3—Receive Error Interrupt Enable (REIE): Enables or disables generation of receive-error interrupt (ERI) and break interrupt (BRI) requests. The REIE bit setting is valid only when the RIE bit is 0. Bit 3: REIE 0 1 Note: * Description Receive-error interrupt (ERI) and break interrupt (BRI) requests disabled* (Initial value) Receive-error interrupt (ERI) and break interrupt (BRI) requests enabled Receive-error interrupt (ERI) and break interrupt (BRI) requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. When REIE is set to 1, ERI and BRI interrupt requests will be generated even if RIE is cleared to 0. In DMAC transfer, this setting is made if the interrupt controller is to be notified of ERI and BRI interrupt requests. Bit 1—Clock Enable 1 (CKE1): Selects the SCIF clock source. The CKE1 bit must be set before determining the SCIF's operating mode with SCSMR2. Bit 1: CKE1 0 1 Note: * Description Internal clock/SCK2 pin functions as port External clock/SCK2 pin functions as clock input* Inputs a clock with a frequency 16 times the bit rate. (Initial value) Rev.7.00 Oct. 10, 2008 Page 736 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.7 Serial Status Register (SCFSR2) Bit: 15 PER3 Initial value: R/W: Bit: 0 R 7 ER Initial value: R/W: 0 R/(W)* 14 PER2 0 R 6 TEND 1 R/(W)* 13 PER1 0 R 5 TDFE 1 R/(W)* 12 PER0 0 R 4 BRK 0 R/(W)* 11 FER3 0 R 3 FER 0 R 10 FER2 0 R 2 PER 0 R 9 FER1 0 R 1 RDF 0 R/(W)* 8 FER0 0 R 0 DR 0 R/(W)* Note: * Only 0 can be written, to clear the flag. SCFSR2 is a 16-bit register. The lower 8 bits consist of status flags that indicate the operating status of the SCIF, and the upper 8 bits indicate the number of receive errors in the data in the receive FIFO register. SCFSR2 can be read or written to by the CPU at all times. However, 1 cannot be written to flags ER, TEND, TDFE, BRK, RDF, and DR. Also note that in order to clear these flags they must be read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be modified. SCFSR2 is initialized to H'0060 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 12—Number of Parity Errors (PER3–PER0): These bits indicate the number of data bytes in which a parity error occurred in the receive data stored in SCFRDR2. After the ER bit in SCFSR2 is set, the value indicated by bits 15 to 12 is the number of data bytes in which a parity error occurred. If all 16 bytes of receive data in SCFRDR2 have parity errors, the value indicated by bits PER3 to PER0 will be 0. Bits 11 to 8—Number of Framing Errors (FER3–FER0): These bits indicate the number of data bytes in which a framing error occurred in the receive data stored in SCFRDR2. After the ER bit in SCFSR2 is set, the value indicated by bits 11 to 8 is the number of data bytes in which a framing error occurred. Rev.7.00 Oct. 10, 2008 Page 737 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) If all 16 bytes of receive data in SCFRDR2 have framing errors, the value indicated by bits FER3 to FER0 will be 0. Bit 7—Receive Error (ER): Indicates that a framing error or parity error occurred during reception.* Note: * The ER flag is not affected and retains its previous state when the RE bit in SCSCR2 is cleared to 0. When a receive error occurs, the receive data is still transferred to SCFRDR2, and reception continues. The FER and PER bits in SCFSR2 can be used to determine whether there is a receive error that is to be from SCFRDR2. Bit 7: ER 0 Description No framing error or parity error occurred during reception [Clearing conditions] • • 1 Power-on reset or manual reset When 0 is written to ER after reading ER = 1 (Initial value) A framing error or parity error occurred during reception [Setting conditions] • • When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0* When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SCSMR2 Note: * In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. Rev.7.00 Oct. 10, 2008 Page 738 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 6—Transmit End (TEND): Indicates that there is no valid data in SCFTDR2 when the last bit of the transmit character is sent, and transmission has been ended. Bit 6: TEND 0 Description Transmission is in progress [Clearing conditions] • • 1 When transmit data is written to SCFTDR2, and 0 is written to TEND after reading TEND = 1 When data is written to SCFTDR2 by the DMAC (Initial value) Transmission has been ended [Setting conditions] • • • Power-on reset or manual reset When the TE bit in SCSCR2 is 0 When there is no transmit data in SCFTDR2 on transmission of the last bit of a 1-byte serial transmit character Rev.7.00 Oct. 10, 2008 Page 739 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from SCFTDR2 to SCTSR2, the number of data bytes in SCFTDR2 has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2), and new transmit data can be written to SCFTDR2. Bit 5: TDFE 0 Description A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR2 [Clearing conditions] • • When transmit data exceeding the transmit trigger set number is written to SCFTDR2 after reading TDFE = 1, and 0 is written to TDFE When transmit data exceeding the transmit trigger set number is written to SCFTDR2 by the DMAC 1 The number of transmit data bytes in SCFTDR2 does not exceed the transmit trigger set number (Initial value) [Setting conditions] • • Power-on reset or manual reset When the number of SCFTDR2 transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation* Note: * As SCFTDR2 is a 16-byte FIFO register, the maximum number of bytes that can be written when TDFE = 1 is 16 - (transmit trigger set number). Data written in excess of this will be ignored. The number of data bytes in SCFTDR2 is indicated by the upper bits of SCFDR2. Rev.7.00 Oct. 10, 2008 Page 740 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 4—Break Detect (BRK): Indicates that a receive data break signal has been detected. Bit 4: BRK 0 Description A break signal has not been received [Clearing conditions] • • 1 Power-on reset or manual reset When 0 is written to BRK after reading BRK = 1 (Initial value) A break signal has been received* [Setting condition] When data with a framing error is received, followed by the space “0” level (low level ) for at least one frame length Note: * When a break is detected, the receive data (H'00) following detection is not transferred to SCFRDR2. When the break ends and the receive signal returns to mark “1”, receive data transfer is resumed. Bit 3—Framing Error (FER): Indicates whether or not a framing error has been found in the data that is to be read next from SCFRDR2. Bit 3: FER 0 Description There is no framing error that is to be read from SCFRDR2 [Clearing conditions] • • Power-on reset or manual reset When there is no framing error in the data that is to be read next from SCFRDR2 (Initial value) 1 There is a framing error that is to be read from SCFRDR2 [Setting condition] When there is a framing error in the data that is to be read next from SCFRDR2 Rev.7.00 Oct. 10, 2008 Page 741 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 2—Parity Error (PER): Indicates whether or not a parity error has been found in the data that is to be read next from SCFRDR2. Bit 2: PER 0 Description There is no parity error that is to be read from SCFRDR2 [Clearing conditions] • • Power-on reset or manual reset When there is no parity error in the data that is to be read next from SCFRDR2 (Initial value) 1 There is a parity error in the receive data that is to be read from SCFRDR2 [Setting condition] When there is a parity error in the data that is to be read next from SCFRDR2 Rev.7.00 Oct. 10, 2008 Page 742 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 1—Receive FIFO Data Full (RDF): Indicates that the received data has been transferred from SCRSR2 to SCFRDR2, and the number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR2). Bit 1: RDF 0 Description The number of receive data bytes in SCFRDR2 is less than the receive trigger set number (Initial value) [Clearing conditions] • • Power-on reset or manual reset When SCFRDR2 is read until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number after reading RDF = 1, and 0 is written to RDF When SCFRDR2 is read by the DMAC until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number • 1 The number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger set number [Setting condition] When SCFRDR2 contains at least the receive trigger set number of receive data bytes* Note: * SCFRDR2 is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set number of data bytes can be read. If all the data in SCFRDR2 is read and another read is performed, the data value will be undefined. The number of receive data bytes in SCFRDR2 is indicated by the lower bits of SCFDR2. Rev.7.00 Oct. 10, 2008 Page 743 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR2, and no further data has arrived for at least 15 etu after the stop bit of the last data received. Bit 0: DR 0 Description Reception is in progress or has ended normally and there is no receive data left in SCFRDR2 (Initial value) [Clearing conditions] • • • 1 Power-on reset or manual reset When all the receive data in SCFRDR2 has been read after reading DR = 1, and 0 is written to DR When all the receive data in SCFRDR2 has been read by the DMAC No further receive data has arrived [Setting condition] When SCFRDR2 contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received* Note: * Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format. etu: Elementary time unit (time for transfer of 1 bit) 16.2.8 Bit Rate Register (SCBRR2) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W SCBRR2 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR2. SCBRR2 can be read or written to by the CPU at all times. SCBRR2 is initialized to H'FF by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Rev.7.00 Oct. 10, 2008 Page 744 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) The SCBRR2 setting is found from the following equation. Asynchronous mode: N= Pck 64 × 22n – 1 × B × 106 – 1 Where B: Bit rate (bits/s) N: SCBRR2 setting for baud rate generator (0 ≤ N ≤ 255) Pck: Peripheral module operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SCSMR2 Setting n 0 1 2 3 Clock Pck Pck/4 Pck/16 Pck/64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following equation: Error (%) = Pck × 106 (N + 1) × B × 64 × 22n – 1 – 1 × 100 16.2.9 FIFO Control Register (SCFCR2) Bit: 15 — 14 — 0 R 6 RTRG0 0 R/W 13 — 0 R 5 TTRG1 0 R/W 12 — 0 R 4 TTRG0 0 R/W 11 — 0 R 3 MCE 0 R/W 10 9 8 RSTRG2* RSTRG1* RSTRG0* Initial value: R/W: Bit: 0 R 7 RTRG1 0 R/W 2 TFRST 0 R/W 0 R/W 1 RFRST 0 R/W 0 R/W 0 LOOP 0 R/W Initial value: R/W: Note: * 0 R/W Reserved bit in the SH7750. Rev.7.00 Oct. 10, 2008 Page 745 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR2 can be read or written to by the CPU at all times. SCFCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 11—Reserved: These bits are always read as 0, and should only be written with 0. Bits 10 to 8 (SH7750)—Reserved: These bits are always read as 0, and should only be written with 0. Bits 10 to 8 (SH7750S, SH7750R)—RTS2 Output Active Trigger (RSTRG2, RSTG1, and RSTG0): These bits output the high level to the RTS2 signal when the number of received data stored in the receive FIFO data register (SCFRDR2) exceeds the trigger number, as shown in the table below. Bit 10: RSTRG2 0 Bit 9: RSTRG1 0 Bit 8: RSTRG0 0 1 1 0 1 1 0 0 1 1 0 1 RTS2 Output Active Trigger 15 1 4 6 8 10 12 14 (Initial value) Rev.7.00 Oct. 10, 2008 Page 746 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bits 7 and 6—Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status register (SCFSR2). The RDF flag is set when the number of receive data bytes in SCFRDR2 is equal to or greater than the trigger set number shown in the following table. Bit 7: RTRG1 0 Bit 6: RTRG0 0 1 1 0 1 Receive Trigger Number 1 4 8 14 (Initial value) Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR2). The TDFE flag is set when the number of transmit data bytes in SCFTDR2 is equal to or less than the trigger set number shown in the following table. • SH7750 Bit 5: TTRG1 0 Bit 4: TTRG0 0 1 1 0 1 Transmit Trigger Number 7 (9) 3 (13) 1 (15) 0 (16) (Initial value) Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set. • SH7750S/SH7750R Bit 5: TTRG1 0 Bit 4: TTRG0 0 1 1 0 1 Transmit Trigger Number 8 (8) 4 (12) 2 (14) 1 (15) (Initial value) Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set. Rev.7.00 Oct. 10, 2008 Page 747 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 3—Modem Control Enable (MCE): Enables the CTS2 and RTS2 modem control signals. Bit 3: MCE 0 1 Note: * Description Modem signals disabled* Modem signals enabled CTS2 is fixed at active-0 regardless of the input value, and RTS2 output is also fixed at 0. (Initial value) Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state. Bit 2: TFRST 0 1 Note: * Description Reset operation disabled* Reset operation enabled A reset operation is performed in the event of a power-on reset or manual reset. (Initial value) Bit 1—Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive FIFO data register and resets it to the empty state. Bit 1: RFRST 0 1 Note: * Description Reset operation disabled* Reset operation enabled A reset operation is performed in the event of a power-on reset or manual reset. (Initial value) Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD2) and receive input pin (RxD2), and the RTS2 pin and CTS2 pin, enabling loopback testing. Bit 0: LOOP 0 1 Description Loopback test disabled Loopback test enabled (Initial value) Rev.7.00 Oct. 10, 2008 Page 748 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.10 FIFO Data Count Register (SCFDR2) SCFDR2 is a 16-bit register that indicates the number of data bytes stored in SCFTDR2 and SCFRDR2. The upper 8 bits show the number of transmit data bytes in SCFTDR2, and the lower 8 bits show the number of receive data bytes in SCFRDR2. SCFDR2 can be read by the CPU at all times. Bit: 15 — Initial value: R/W: 0 R 14 — 0 R 13 — 0 R 12 T4 0 R 11 T3 0 R 10 T2 0 R 9 T1 0 R 8 T0 0 R These bits show the number of untransmitted data bytes in SCFTDR2. A value of H'00 indicates that there is no transmit data, and a value of H'10 indicates that SCFTDR2 is full of transmit data. Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 — 0 R 4 R4 0 R 3 R3 0 R 2 R2 0 R 1 R1 0 R 0 R0 0 R These bits show the number of receive data bytes in SCFRDR2. A value of H'00 indicates that there is no receive data, and a value of H'10 indicates that SCFRDR2 is full of receive data. Rev.7.00 Oct. 10, 2008 Page 749 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.11 Serial Port Register (SCSPTR2) Bit: 15 — Initial value: R/W: Bit: 0 R 7 RTSIO Initial value: R/W: 0 R/W 14 — 0 R 6 RTSDT — R/W 13 — 0 R 5 CTSIO 0 R/W 12 — 0 R 4 CTSDT — R/W 11 — 0 R 3 — 0 R 10 — 0 R 2 — — R 9 — 0 R 1 8 — 0 R 0 SPB2IO SPB2DT 0 R/W — R/W SCSPTR2 is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins. Input data can be read from the RxD2 pin, output data written to the TxD2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. Data can be read from, and output data written to, the CTS2 pin by means of bits 5 and 4. Data can be read from, and output data written to, the RTS2 pin by means of bits 6 and 7. SCSPTR2 can be read or written to by the CPU at all times. All SCSPTR2 bits except bits 6, 4, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, and 0 is undefined. SCSPTR2 is not initialized in standby mode or in the module standby state. Bits 15 to 8—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Serial Port RTS Port I/O (RTSIO): Specifies the serial port RTS2 pin input/output condition. When the RTS2 pin is actually set as a port output pin and outputs the value set by the RTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 7: RTSIO 0 1 Description RTSDT bit value is not output to RTS2 pin RTSDT bit value is output to RTS2 pin (Initial value) Rev.7.00 Oct. 10, 2008 Page 750 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port RTS2 pin input/output data. Input or output is specified by the RTSIO bit (see the description of bit 7, RTSIO, for details). In output mode, the RTSDT bit value is output to the RTS2 pin. The RTS2 pin value is read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 6: RTSDT 0 1 Description Input/output data is low-level Input/output data is high-level Bit 5—Serial Port CTS Port I/O (CTSIO): Specifies the serial port CTS2 pin input/output condition. When the CTS2 pin is actually set as a port output pin and outputs the value set by the CTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 5: CTSIO 0 1 Description CTSDT bit value is not output to CTS2 pin CTSDT bit value is output to CTS2 pin (Initial value) Bit 4—Serial Port CTS Port Data (CTSDT): Specifies the serial port CTS2 pin input/output data. Input or output is specified by the CTSIO bit (see the description of bit 5, CTSIO, for details). In output mode, the CTSDT bit value is output to the CTS2 pin. The CTS2 pin value is read from the CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 4: CTSDT 0 1 Description Input/output data is low-level Input/output data is high-level Bit 3—Reserved: This bit is always read as 0, and should only be written with 0. Bit 2—Reserved: The value of this bit is undefined when read. The write value should always be 0. Rev.7.00 Oct. 10, 2008 Page 751 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 1—Serial Port Break I/O (SPB2IO): Specifies the serial port TxD2 pin output condition. When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT bit, the TE bit in SCSCR2 should be cleared to 0. Bit 1: SPB2IO 0 1 Description SPB2DT bit value is not output to the TxD2 pin SPB2DT bit value is output to the TxD2 pin (Initial value) Bit 0—Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value of the SPB2DT bit is output to the TxD2 pin. The RxD2 pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB2DT 0 1 Description Input/output data is low-level Input/output data is high-level Rev.7.00 Oct. 10, 2008 Page 752 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) SCIF I/O port block diagrams are shown in figures 16.2 to 16.5. Reset R D7 Q D RTSIO C Internal data bus SPTRW MD8/RTS2 Reset R D6 Q D RTSDT C SCIF Modem control enable signal* RTS2 signal SPTRW Mode setting register SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * The RTS2 pin function is designated as modem control by the MCE bit in SCFCR2. Figure 16.2 MD8/RTS2 Pin Rev.7.00 Oct. 10, 2008 Page 753 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Reset R Q D CTSIO C D5 Internal data bus SPTRW CTS2 Reset R Q D CTSDT C D4 SCIF SPTRW CTS2 signal Modem control enable signal* SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * The CTS2 pin function is designated as modem control by the MCE bit in SCFCR2. Figure 16.3 CTS2 Pin Rev.7.00 Oct. 10, 2008 Page 754 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Reset R Q D SPB2IO C D1 Internal data bus SPTRW MD1/TxD2 Reset R Q D SPB2DT C D0 SCIF Transmit enable signal SPTRW Mode setting register Legend: SPTRW: Write to SPTR Serial transmit data Figure 16.4 MD1/TxD2 Pin MD2/RxD2 SCIF Mode setting register D0 Internal data bus SPTRR Legend: SPTRR: Read SPTR Serial receive data Figure 16.5 MD2/RxD2 Pin Rev.7.00 Oct. 10, 2008 Page 755 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.12 Line Status Register (SCLSR2) Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: Note: * 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 — 0 R 12 — 0 R 4 — 0 R 11 — 0 R 3 — 0 R 10 — 0 R 2 — 0 R 9 — 0 R 1 — 0 R 8 — 0 R 0 ORER 0 (R/W)* Only 0 can be written, to clear the flag. Bits 15 to 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 0—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 0: ORER 0 Description Reception in progress, or reception has ended normally*1 [Clearing conditions] • • 1 Power-on reset or manual reset When 0 is written to ORER after reading ORER = 1 (Initial value) An overrun error occurred during reception*2 [Setting condition] When the next serial reception is completed while the receive FIFO is full Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR2 is cleared to 0. 2. The receive data prior to the overrun error is retained in SCFRDR2, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. Rev.7.00 Oct. 10, 2008 Page 756 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) 16.3 16.3.1 Operation Overview The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character. See section 15.3.2, Operation in Asynchronous Mode, for details. Sixteen-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed. RTS2 and CTS2 signals are also provided as modem control signals. The transmission format is selected using the serial mode register (SCSMR2), as shown in table 16.3. The SCIF clock source is determined by the CKE1 bit in the serial control register (SCSCR2), as shown in table 16.4. • Data length: Choice of 7 or 8 bits • Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) • Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receivedata-ready state, and breaks, during reception • Indication of the number of data bytes stored in the transmit and receive FIFO registers • Choice of internal or external clock as SCIF clock source When internal clock is selected: The SCIF operates on the baud rate generator clock, and can output a clock with a frequency of 16 times the bit rate. When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used). Rev.7.00 Oct. 10, 2008 Page 757 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection SCSMR2 Settings Bit 6: CHR 0 Bit 5: PE 0 Bit 3: STOP 0 1 1 0 1 1 0 0 1 1 0 1 Yes 7-bit data No Yes Mode Asynchronous mode Data Length SCIF Transfer Format Multiprocessor Bit Parity Bit No Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 8-bit data No Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection SCSCR2 Setting Bit 1: CKE1 0 1 Mode Asynchronous mode SCIF Transmit/Receive Clock Clock Source Internal External SCK2 Pin Function SCIF does not use SCK2 pin Inputs clock with frequency of 16 times the bit rate 16.3.2 Serial Operation Transmit/Receive Format Table 16.5 shows the transmit/receive formats that can be used. Any of 8 transfer formats can be selected according to the SCSMR2 settings. Rev.7.00 Oct. 10, 2008 Page 758 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.5 Serial Transmit/Receive Formats SCSMR2 Settings CHR PE 0 0 STOP 0 1 S 2 Serial Transmit/Receive Format and Frame Length 3 4 5 8-bit data 6 7 8 9 10 STOP 11 12 0 0 1 S 8-bit data STOP STOP 0 1 0 S 8-bit data P STOP 0 1 1 S 8-bit data P STOP STOP 1 0 0 S 7-bit data STOP 1 0 1 S 7-bit data STOP STOP 1 1 0 S 7-bit data P STOP 1 1 1 S 7-bit data P STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK2 pin can be selected as the SCIF's serial clock, according to the setting of the CKE1 bit in SCSCR2. For details of SCIF clock source selection, see table 16.4. When an external clock is input at the SCK2 pin, the clock frequency should be 16 times the bit rate used. Rev.7.00 Oct. 10, 2008 Page 759 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Data Transfer Operations SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR2 to 0, then initialize the SCIF as described below. When the transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, SCTSR2 is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR2, SCFTDR2, or SCFRDR2. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND flag in SCFSR2 has been set. TEND can also be cleared to 0 during transmission, but the data being transmitted will go to the mark state after the clearance. Before setting TE again to start transmission, the TFRST bit in SCFCR2 should first be set to 1 to reset SCFTDR2. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Rev.7.00 Oct. 10, 2008 Page 760 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.6 shows a sample SCIF initialization flowchart. Initialization 1. Set the clock selection in SCSCR2. Be sure to clear bits RIE and TIE, and bits TE and RE, to 0. Clear TE and RE bits in SCSCR2 to 0 Set TFRST and RFRST bits in SCFCR2 to 1 Set CKE1 bit in SCSCR2 (leaving TE and RE bits cleared to 0) Set transmit/receive format in SCSMR2 Set value in SCBRR2 Wait 1-bit interval elapsed? Yes Set RTRG1–0, TTRG1–0, and MCE bits in SCFCR2 Clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR2 to 1, and set RIE, TIE, and REIE bits No 2. Set the transmit/receive format in SCSMR2. 3. Write a value corresponding to the bit rate into SCBRR2. (Not necessary if an external clock is used.) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR2 to 1. Also set the RIE, REIE, and TIE bits. Setting the TE and RE bits enables the TxD2 and RxD2 pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. End Figure 16.6 Sample SCIF Initialization Flowchart Rev.7.00 Oct. 10, 2008 Page 761 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Serial Data Transmission: Figure 16.7 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start of transmission 1. SCIF status check and transmit data write: Read SCFSR2 and check that the TDFE flag is set to 1, then write transmit data to SCFTDR2, read 1 from the TDFE and TEND flags, then clear these flags to 0. The number of transmit data bytes that can be written is 16 - (transmit trigger set number). 2. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR2, and then clear the TDFE flag to 0. 3. Break output at the end of serial transmission: No To output a break in serial transmission, clear the SPB2DT bit to 0 and set the SPB2IO bit to 1 in SCSPTR2, then clear the TE bit in SCSCR2 to 0. In steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR2 indicated by the upper 8 bits of SCFDR2. Read TDFE flag in SCFSR2 No TDFE = 1? Yes Write transmit data (16 - transmit trigger set number) to SCFTDR2, read 1 from TDFE flag and TEND flag in SCFSR2, then clear to 0 All data transmitted? Yes Read TEND flag in SCFSR2 No TEND = 1? Yes Break output? Yes Clear SPB2DT to 0 and set SPB2IO to 1 Clear TE bit in SCSCR2 to 0 No End of transmission Figure 16.7 Sample Serial Transmission Flowchart Rev.7.00 Oct. 10, 2008 Page 762 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR2, the SCIF transfers the data from SCFTDR2 to SCTSR2 and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR2) is set to 1 before writing transmit data to SCFTDR2. The number of data bytes that can be written is at least 16 - transmit trigger setting. 2. When data is transferred from SCFTDR2 to SCTSR2 and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR2. When the number of transmit data bytes in SCFTDR2 falls to or below the transmit trigger number set in the FIFO control register (SCFCR2), the TDFE flag is set. If the TIE bit in SCSCR2 is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD2 pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR2 transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR2 to SCTSR2, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR2 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. Rev.7.00 Oct. 10, 2008 Page 763 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.8 shows an example of the operation for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Serial data 1 Idle state (mark state) TDFE TEND TXI interrupt TXI interrupt request request Data written to SCFTDR2 and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame Figure 16.8 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with the CTS2 input value. When CTS2 is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When CTS2 is set to 0, the next transmit data is output starting from the start bit. Figure 16.9 shows an example of the operation when modem control is used. Start bit Serial data TxD2 0 D0 D1 Parity Stop bit bit D7 0/1 1 Start bit 0 D0 D1 D7 0/1 CTS2 Drive high before stop bit Figure 16.9 Example of Operation Using Modem Control (CTS2) Rev.7.00 Oct. 10, 2008 Page 764 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Serial Data Reception: Figure 16.10 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Start of reception Read ER, DR, BRK flags in SCFSR2 and ORER flag in SCLSR2 ER or DR or BRK or ORER = 1? No Read RDF flag in SCFSR2 No Yes 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR2, and the ORER flag in SCLSR2, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD2 pin. 2. SCIF status check and receive data read : Read SCFSR2 and check that RDF = 1, then read the receive data in SCFRDR2, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. 3. Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR2, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR2 can be ascertained by reading the lower bits of SCFDR2. Error handling RDF = 1? Yes Read receive data in SCFRDR2, and clear RDF flag in SCFSR2 to 0 No All data received? Yes Clear RE bit in SCSCR2 to 0 End of reception Figure 16.10 Sample Serial Reception Flowchart (1) Rev.7.00 Oct. 10, 2008 Page 765 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Error handling No 1. Whether a framing error or parity error has occurred that is to be read from SCFRDR2 can be ascertained from the FER and PER bits in SCFSR2. 2. When a break signal is received, receive data is not transferred to SCFRDR2 while the BRK flag is set. However, note that the last data in SCFRDR2 is H'00 (the break data in which a framing error occurred is stored). ORER = 1? Yes Overrun error handling No ER = 1? Yes Receive error handling No BRK = 1? Yes Break handling No DR = 1? Yes Read receive data in SCFRDR2 Clear DR, ER, BRK flags in SCFSR2, and ORER flag in SCLSR2, to 0 End Figure 16.10 Sample Serial Reception Flowchart (2) Rev.7.00 Oct. 10, 2008 Page 766 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR2 in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. a. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. b. The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR2) to SCFRDR2. c. Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun error has occurred. d. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If b, c, and d checks are passed, the receive data is stored in SCFRDR2. Note: Reception continues when parity error, framing error occurs. 4. If the RIE bit in SCSCR2 is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or REIE bit in SCSCR2 is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or REIE bit in SCSCR2 is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated. Rev.7.00 Oct. 10, 2008 Page 767 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.11 shows an example of the operation for reception in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 0/1 1 Serial data RDF FER RXI interrupt request One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler ERI interrupt request generated by receive error Figure 16.11 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 5. When modem control is enabled, the RTS2 signal is output when SCFRDR2 is empty. When RTS2 is 0, reception is possible. SH7750: When RTS2 is 1, this indicates that SCFRDR2 contains 15 or more bytes of data. SH7750S, SH7750R: When RTS2 is 1, this indicates that SCFRDR2 contains a number of data bytes equal to or greater than the RTS2 output active trigger set number. The RTS2 output active trigger value is specified by bits 10 to 8 in the FIFO control register (SCFCR2), described in section 16.2.9, FIFO control register (SCFCR2). RTS2 also becomes 1 when bit 4 (RE) in SCSCR2 is 0. Rev.7.00 Oct. 10, 2008 Page 768 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.12 shows an example of the operation when modem control is used. Start bit Serial data RxD2 0 D0 D1 D2 Parity Stop bit bit D7 0/1 1 Start bit 0 RTS2 Figure 16.12 Example of Operation Using Modem Control (RTS2) 16.4 SCIF Interrupt Sources and the DMAC The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receiveerror interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt (BRI) request. Table 16.6 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR2. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When transmission/reception is carried out using the DMAC, output of interrupt requests to the interrupt controller can be inhibited by clearing the RIE bit in SCSCR2 to 0. By setting the REIE bit to 1 while the RIE bit is cleared to 0, it is possible to output ERI and BRI interrupt requests, but not RXI interrupt requests. When the TDFE flag in the serial status register (SCFSR2) is set to 1, a transmit-FIFO-data-empty request is generated separately from the interrupt request. A transmit-FIFO-data-empty request can activate the DMAC to perform data transfer. When the RDF flag or DR flag in SCFSR2 is set to 1, a receive-FIFO-data-full request is generated separately from the interrupt request. A receive-FIFO-data-full request can activate the DMAC to perform data transfer. When using the DMAC for transmission/reception, set and enable the DMAC before making the SCIF settings. See section 14, Direct Memory Access Controller (DMAC), for details of the DMAC setting procedure. Rev.7.00 Oct. 10, 2008 Page 769 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) When the BRK flag in SCFSR2 or the ORER flag in the line status register (SCLSR2) is set to 1, a BRI interrupt request is generated. The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that there is receive data in SCFRDR2. Table 16.6 SCIF Interrupt Sources Interrupt Source ERI RXI BRI TXI Description Interrupt initiated by receive error flag (ER) Interrupt initiated by receive FIFO data full flag (RDF) or receive data ready flag (DR) DMAC Activation Not possible Possible Priority on Reset Release High Interrupt initiated by break flag (BRK) or overrun Not possible error flag (ORER) Interrupt initiated by transmit FIFO data empty flag (TDFE) Possible Low See section 5, Exceptions, for priorities and the relationship with non-SCIF interrupts. 16.5 Usage Notes Note the following when using the SCIF. SCFTDR2 Writing and the TDFE Flag: The TDFE flag in the serial status register (SCFSR2) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR2) has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR2 can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR2 is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR2 contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR2 can be found from the upper 8 bits of the FIFO data count register (SCFDR2). SCFRDR2 Reading and the RDF Flag: The RDF flag in the serial status register (SCFSR2) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR2) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the Rev.7.00 Oct. 10, 2008 Page 770 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) FIFO control register (SCFCR2). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR2, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR2 is equal to or greater than the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after all the receive data has been read. The number of receive data bytes in SCFRDR2 can be found from the lower 8 bits of the FIFO data count register (SCFDR2). Break Detection and Processing: Break signals can be detected by reading the RxD2 pin directly when a framing error (FER) is detected. In the break state the input from the RxD2 pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Although the SCIF stops transferring receive data to SCFRDR2 after receiving a break, the receive operation continues. Sending a Break Signal: The input/output condition and level of the TxD2 pin are determined by bits SPB2IO and SPB2DT in the serial port register (SCSPTR2). This feature can be used to send a break signal. After the serial transmitter is initialized, the TxD2 pin function is not selected and the value of the SPB2DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled). The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high level) beforehand. To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized, regardless of its current state, and 0 is output from the TxD2 pin. Receive Data Sampling Timing and Receive Margin: The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 16.13. Rev.7.00 Oct. 10, 2008 Page 771 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks +7.5 clocks Receive data (RxD2) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = (0.5 – 1 | D – 0.5 | ) – (L – 0.5) F – (1 + F) × 100% ...................... (1) 2N N M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 – 1 / (2 × 16)) × 100% = 46.875% ................................................ (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Rev.7.00 Oct. 10, 2008 Page 772 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) SCK2/MRESET: As the manual reset pin is multiplexed with the SCK2 pin, a manual reset must not be executed while the SCIF is operating in external clock mode. When Using the DMAC: When using the DMAC for transmission/reception, inhibit output of RXI and TXI interrupt requests to the interrupt controller. If interrupt request output is enabled, interrupt requests to the interrupt controller will be cleared by the DMAC without regard to the interrupt handler. Serial Ports: Note that, when the SCIF pin value is read using a serial port, the value read will be the value two peripheral clock cycles earlier. Overrun Error Flag (SH7750): SCIF overrun error flag is not set in the case that overrun error and flaming error occurred simultaneously in receiving data, that means 17th byte data which overrun was accompanying with flaming error. In such case, only SCFSR2. ER flag which shows occurrence of flaming error is set. Receive FIFO stores data received before the overrun and does not store (i. e. lose) overrun data. SCIF has no bit which corresponds to SCFSR2. FER for the lost data. In addition to the overrun error handling software routine, exception handler should check cooccurrence of overrun error when a flaming error is occurred and when a co-occurrence is found, it should handle also overrun error (When (i) a overrun error solely occurred without accompanying with other receive error and (ii) when a parity error is accompanied with overrun error, usual overrun error handling can be used. Overrun error handling should rather be done primarily). Rev.7.00 Oct. 10, 2008 Page 773 of 1074 REJ09B0366-0700 Section 16 Serial Communication Interface with FIFO (SCIF) Framing error occurrence Flow chart: When flaming error (SCFSR.ER=1) is occurred, bit7 to Bits 7 to 0 in SCFDR2 = H'10? Yes No bit0 should be read out from SCFDR2. If bit7 to bit0 equals H'10, contents of the receive FIFO should be read. When the data received last is not accompanied with flaming error (SCFSR2.FER=0) both overrun error Normal error handling handling and flaming error handling shoud be PER or FER bit in SCFSR2 set to 1? Yes conducted. No Error handling Read receive FIFO No Last data? Yes Overrun error handling + framing error handling Figure 16.14 Overrun Error Flag Rev.7.00 Oct. 10, 2008 Page 774 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Section 17 Smart Card Interface 17.1 Overview The serial communication interface (SCI) supports a subset of the ISO/IEC 7816-3 (identification cards) standard as an extended function. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 17.1.1 Features Features of the smart card interface are listed below. • Asynchronous mode ⎯ Data length: 8 bits ⎯ Parity bit generation and checking ⎯ Transmission of error signal (parity error) in receive mode ⎯ Error signal detection and automatic data retransmission in transmit mode ⎯ Direct convention and inverse convention both supported • On-chip baud rate generator allows any bit rate to be selected • Three interrupt sources There are three interrupt sources—transmit-data-empty, receive-data-full, and transmit/receive error—that can issue requests independently. The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) to execute data transfer. Rev.7.00 Oct. 10, 2008 Page 775 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the smart card interface. Bus interface Module data bus Internal data bus SCRDR1 RxD SCRSR1 SCTDR1 SCTSR1 SCSCMR1 SCSSR1 SCSCR1 SCSMR1 SCSPTR1 Transmission/ reception control SCBRR1 Pck Baud rate generator Pck/4 Pck/16 Pck/64 TxD Parity generation Parity check SCK Clock External clock TXI RXI ERI SCI Legend: SCSCMR1: SCRSR1: SCRDR1: SCTSR1: SCTDR1: SCSMR1: SCSCR1: SCSSR1: SCBRR1: SCSPTR1: Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Figure 17.1 Block Diagram of Smart Card Interface Rev.7.00 Oct. 10, 2008 Page 776 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface 17.1.3 Pin Configuration Table 17.1 shows the smart card interface pin configuration. Table 17.1 Smart Card Interface Pins Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation MD0/SCK RxD MD7/TxD I/O I/O Input Output Function Clock input/output Receive data input Transmit data output Note: The serial clock pin and transmit data pin function as mode input pins MD0 and MD7 after a power-on reset. 17.1.4 Register Configuration The smart card interface has the internal registers shown in table 17.2. Details of the SCBRR1, SCTDR1, SCRDR1, and SCSPTR1 registers are the same as for the normal SCI function: see the register descriptions in section 15, Serial Communication Interface (SCI). With the exception of the serial port register, the smart card interface registers are initialized in standby mode and in the module standby state as well as by a power-on reset or manual reset. When recovering from standby mode or the module standby state, the registers must be set again. Table 17.2 Smart Card Interface Registers Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial port register Abbreviation SCSMR1 SCBRR1 SCSCR1 SCTDR1 SCSSR1 SCRDR1 SCSCMR1 SCSPTR1 R/W R/W R/W R/W R/W R/(W)* R R/W R/W 1 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'00 H'00*2 P4 Address H'FFE00000 H'FFE00004 H'FFE00008 H'FFE0000C H'FFE00010 H'FFE00014 H'FFE00018 H'FFE0001C Area 7 Address H'1FE00000 H'1FE00004 H'1FE00008 H'1FE0000C H'1FE00010 H'1FE00014 H'1FE00018 H'1FE0001C Access Size 8 8 8 8 8 8 8 8 Notes: 1. Only 0 can be written, to clear flags. 2. The value of bits 2 and 0 is undefined. Rev.7.00 Oct. 10, 2008 Page 777 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface 17.2 Register Descriptions Only registers that have been added, and bit functions that have been modified, for the smart card interface are described here. 17.2.1 Smart Card Mode Register (SCSCMR1) SCSCMR1 is an 8-bit readable/writable register that selects the smart card interface function. SCSCMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit: 7 — Initial value: R/W: — — 6 — — — 5 — — — 4 — — — 3 SDIR 0 R/W 2 SINV 0 R/W 1 — — — 0 SMIF 0 R/W Bits 7 to 4 and 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3: SDIR 0 1 Description SCTDR1 contents are transmitted LSB-first Receive data is stored in SCRDR1 LSB-first SCTDR1 contents are transmitted MSB-first Receive data is stored in SCRDR1 MSB-first (Initial value) Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the bit 3 function for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 17.3.4, Register Settings. Bit 2: SINV 0 1 Description SCTDR1 contents are transmitted as they are Receive data is stored in SCRDR1 as it is SCTDR1 contents are inverted before being transmitted Receive data is stored in SCRDR1 in inverted form (Initial value) Rev.7.00 Oct. 10, 2008 Page 778 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface function. Bit 0: SMIF 0 1 Description Smart card interface function is disabled Smart card interface function is enabled (Initial value) 17.2.2 Serial Mode Register (SCSMR1) Bit 7 of SCSMR1 has a different function in smart card interface mode. Bit: 7 GM(C/A) Initial value: R/W: 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode. With the normal smart card interface, this bit is cleared to 0. Setting this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the TEND flag that indicates completion of transmission, and the type of clock output used. The details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in the serial control register (SCSCR1). In GSM mode, the pulse width is guaranteed when SCK start/stop specifications are made by CKE1 and CKE0. Bit 7: GM 0 Description Normal smart card interface mode operation • • 1 Clock output on/off control only (Initial value) The TEND flag is set 12.5 etu after the beginning of the start bit GSM mode smart card interface mode operation • • The TEND flag is set 11.0 etu after the beginning of the start bit Clock output on/off and fixed-high/fixed-low control (set in SCSCR1) Note: etu: Elementary time unit (time for transfer of 1 bit) Rev.7.00 Oct. 10, 2008 Page 779 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Bits 6 to 0: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. With the smart card interface, the following settings should be used: CHR = 0, PE = 1, STOP = 1, MP = 0. 17.2.3 Serial Control Register (SCSCR1) Bits 1 and 0 of SCSCR1 have a different function in smart card interface mode. Bit: 7 TIE Initial value: R/W: 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 — 0 R/W 2 — 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Bits 7 to 4: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. Bits 3 and 2—Reserved: Not used with the smart card interface. Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits specify the function of the SCK pin. In smart card interface mode, an internal clock is always used as the clock source. In smart card interface mode, it is possible to specify a fixed high level or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output. GM 0 CKE1 0 CKE0 0 1 1 0 1 1 0 0 1 1 0 1 SCK Pin Function Port I/O pin Clock output as SCK output pin Invalid setting: must not be used Invalid setting: must not be used Output pin with output fixed low Clock output as output pin Output pin with output fixed high Clock output as output pin Rev.7.00 Oct. 10, 2008 Page 780 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface 17.2.4 Serial Status Register (SCSSR1) Bit 4 of SCSSR1 has a different function in smart card interface mode. Coupled with this, the setting conditions for bit 2 (TEND) are also different. Bit: 7 TDRE Initial value: R/W: Note: * 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER/ ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 — 0 R 0 — 0 R/W Only 0 can be written, to clear the flag. Bits 7 to 5: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. Bit 4—Error Signal Status (ERS): In smart card interface mode, bit 4 indicates the status of the error signal sent back from the receiving side during transmission. Framing errors are not detected in smart card interface mode. Bit 4: ERS 0 Description Normal reception, no error signal [Clearing conditions] • • 1 Power-on reset, manual reset, standby mode, or module standby When 0 is written to ERS after reading ERS = 1 (Initial value) An error signal has been sent from the receiving side indicating detection of a parity error [Setting condition] When the low level of the error signal is detected Note: Clearing the TE bit in SCSCR1 to 0 does not affect the ERS flag, which retains its previous state. Bit 3—Parity Error (PER): Operates in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. Rev.7.00 Oct. 10, 2008 Page 781 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Bit 2—Transmit End (TEND): The setting conditions for the TEND flag are as follows. Bit 2: TEND 0 Description Transmission in progress [Clearing condition] When 0 is written to TDRE after reading TDRE = 1 1 Transmission has been ended [Setting conditions] • • • Power-on reset, manual reset, standby mode, or module standby When the TE bit in SCSCR1 is 0 and the FER/ERS bit is also 0 When the GM bit in SCSMR1 is 0, and TDRE = 1 and FER/ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character When the GM bit in SCSMR1 is 1, and TDRE = 1 and FER/ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character (Initial value) • Note: etu: Elementary Time Unit (time for transfer for 1 bit) Bits 1 and 0—Reserved: Not used with the smart card interface. 17.3 17.3.1 Operation Overview The main functions of the smart card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (elementary time unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. • If a parity error is detected during reception, a low error signal level is output for a 1-etu period 10.5 etu after the start bit. • If an error signal is detected during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. • Only asynchronous communication is supported; there is no synchronous communication function. Rev.7.00 Oct. 10, 2008 Page 782 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface 17.3.2 Pin Connections Figure 17.2 shows a schematic diagram of smart card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected outside the chip. The data transmission line should be pulled up on the VCC power supply side with a resistor. When the clock generated on the smart card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. Chip port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. Note: If an IC card is not connected, and both TE and RE are set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. VCC TxD Data line RxD SCK SH7750 SH7750S SH7750R Px (port) Clock line Reset line IO CLK RST IC card Connected equipment Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections Rev.7.00 Oct. 10, 2008 Page 783 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface 17.3.3 Data Format Figure 17.3 shows the smart card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting side to request retransmission of the data. If an error signal is detected during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Receiving station output Ds: D0–D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 17.3 Smart Card Interface Data Format The operation sequence is as follows. 1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. 2. The transmitting station starts transmission of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). 3. With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. Rev.7.00 Oct. 10, 2008 Page 784 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface 4. The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. 5. If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it receives an error signal, however, it returns to step 2 and retransmits the erroneous data. 17.3.4 Register Settings Table 17.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 17.3 Smart Card Interface Register Settings Bit Register SCSMR1 SCBRR1 SCSCR1 SCTDR1 SCSSR1 SCRDR1 Bit 7 GM BRR7 TIE TDR7 TDRE RDR7 Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 — — Bit 5 1 BRR5 TE TDR5 ORER RDR5 — — Bit 4 O/E BRR4 RE TDR4 Bit 3 1 BRR3 0 TDR3 Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1 TDR1 0 RDR1 — Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF SPB0DT FER/ERS PER RDR4 — — RDR3 SDIR SPB1IO SCSCMR1 — SCSPTR1 EIO SPB1DT SPB0IO Note: A dash indicates an unused bit. Serial Mode Register (SCSMR1) Settings: The GM bit is used to select the timing of TEND flag setting, and, together with the CKE1 and CKE0 bits in the serial control register (SCSCR1), to select the clock output state. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Rev.7.00 Oct. 10, 2008 Page 785 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 17.3.5, Clock. I/O data Ds Da Db Dc Dd De Df Dg Dh Dp DE Guard time TXI (TEND interrupt) 12.5 etu GM = 0 11.0 etu GM = 1 Note: etu: Elementary Time Unit (time for transfer for 1 bit) Figure 17.4 TEND Generation Timing Bit Rate Register (SCBRR1) Setting: SCBRR1 is used to set the bit rate. See section 17.3.5, Clock, for the method of calculating the value to be set. Serial Control Register (SCSCR1) Settings: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. The CKE1 and CKE0 bits specify the clock output state. See section 17.3.5, Clock, for details. Smart Card Mode Register (SCSCMR1) Settings: The SDIR bit and SINV bit are both cleared to 0 if the IC card is of the direct convention type, and both set to 1 if of the inverse convention type. The SMIF bit is set to 1 when the smart card interface is used. Figure 17.5 shows examples of register settings and the waveform of the start character for the two types of IC card (direct convention and inverse convention). With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data in this case is H'3B. The parity bit is 1 since even parity is stipulated for the smart card. Rev.7.00 Oct. 10, 2008 Page 786 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data in this case is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the smart card. Inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SCSMR1 is set to odd parity mode. (This applies to both transmission and reception). (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State (a) Direct convention (SDIR = SINV = O/E = 0) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State (b) Inverse convention (SDIR = SINV = O/E = 1) Figure 17.5 Sample Start Character Waveforms 17.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register (SCBRR1) and the CKS1 and CKS0 bits in the serial mode register (SCSMR1). The equation for calculating the bit rate is shown below. Table 17.5 shows some sample bit rates. If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin. B= Pck × 106 1488 × 22n – 1 × (N + 1) Where: N = Value set in SCBRR1 (0 ≤ N ≤ 255) B = Bit rate (bits/s) Rev.7.00 Oct. 10, 2008 Page 787 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Pck = Peripheral module operating frequency (MHz) n = 0 to 3 (See table 17.4) Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1 Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0) Pck (MHz) N 0 1 2 7.1424 9600.0 4800.0 3200.0 10.00 13440.9 6720.4 4480.3 10.7136 14400.0 7200.0 4800.0 14.2848 19200.0 9600.0 6400.0 25.0 33602.2 16801.1 11200.7 33.0 44354.8 22177.4 14784.9 50.0 67204.3 33602.2 22401.4 Note: Bit rates are rounded to one decimal place. The method of calculating the value to be set in the bit rate register (SCBRR1) from the peripheral module operating frequency and bit rate is shown below. Here, N is an integer in the range 0 ≤ N ≤ 255, and the smaller error is specified. N= Pck × 106 – 1 1488 × 22n – 1 × B Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) Pck (MHz) 7.1424 Bits/s 9600 N 0 Error 0.00 N 1 10.00 Error 30.00 N 1 10.7136 Error 25.00 N 1 14.2848 Error 8.99 N 3 25.00 Error 14.27 N 4 33.00 Error 8.22 N 6 50.00 Error 0.01 Rev.7.00 Oct. 10, 2008 Page 788 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) Pck (MHz) 7.1424 10.00 10.7136 16.00 20.00 25.0 30.0 33.0 50.0 Maximum Bit Rate (bits/s) 19200 26882 28800 43010 53763 67204 80645 88710 67204 N 0 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0 0 The bit rate error is given by the following equation: Error (%) = Pck 1488 × 22n – 1 × B × (N + 1) × 106 – 1 × 100 Table 17.8 shows the relationship between the smart card interface transmit/receive clock register settings and the output state. Table 17.8 Register Settings and SCK Pin State Register Values Setting 1*1 SMIF 1 1 2* 2 SCK Pin CKE0 0 1 0 1 0 1 High output Low output Output Port State Determined by setting of SPB1IO and SPB1DT bits in SCSPTR1 SCK (serial clock) output state Low-level output state SCK (serial clock) output state High-level output state SCK (serial clock) output state GM 0 0 1 1 1 1 CKE1 0 0 0 0 1 1 1 1 3* 2 1 1 Notes: 1. The SCK output state changes as soon as the CKE0 bit setting is changed. Clear the CKE1 bit to 0. 2. Stopping and starting the clock by changing the CKE0 bit setting does not affect the clock duty cycle. Rev.7.00 Oct. 10, 2008 Page 789 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Width is undefined Width is undefined Port value Port value SCK (a) When GM = 0 Specified width Specified width CKE1 value CKE1 value SCK (b) When GM = 1 Figure 17.6 Difference in Clock Output According to GM Bit Setting 17.3.6 Data Transmit/Receive Operations Initialization: Before transmitting and receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. Figure 17.7 shows a sample initialization processing flowchart. 1. Clear the TE and RE bits in the serial control register (SCSCR1) to 0. 2. Clear error flags FER/ERS, PER, and ORER in the serial status register (SCSSR1) to 0. 3. Set the GM bit, parity bit (O/E), and baud rate generator select bits (CKS1 and CKS0) in the serial mode register (SCSMR1). Clear the CHR and MP bits to 0, and set the STOP and PE bits to 1. 4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCSCMR1). When the SMIF bit is set to 1, the TxD pin and RxD pin both go to the high-impedance state. 5. Set the value corresponding to the bit rate in the bit rate register (SCBRR1). 6. Set the clock source select bits (CKE1 and CKE0) in SCSCR1. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCSCR1. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Rev.7.00 Oct. 10, 2008 Page 790 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Initialization Clear TE and RE bits in SCSCR1 to 0 Clear FER/ERS, PER, and ORER flags in SCSCR1 to 0 In SCSMR1, set parity in O/E bit, clock in CKS1 and CKS0 bits, and set GM Set SMIF, SDIR, and SINV bits in SCSCMR1 Set value in SCBRR1 In SCSCR1, set clock in CKE1 and CKE0 bits, and clear TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. Wait 1-bit interval elapsed? Yes Set TIE, RIE, TE, and RE bits in SCSCR1 1 2 3 4 5 6 No 7 End Figure 17.7 Sample Initialization Flowchart Rev.7.00 Oct. 10, 2008 Page 791 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 17.8 shows a sample transmission processing flowchart. 1. 2. 3. 4. Perform smart card interface mode initialization as described in Initialization above. Check that the FER/ERS error flag in SCSSR1 is cleared to 0. Repeat steps 2 and 3 until it can be confirmed that the TEND flag in SCSSR1 is set to 1. Write the transmit data to SCTDR1, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. 5. To continue transmitting data, go back to step 2. 6. To end transmission, clear the TE bit to 0. With the above processing, interrupt handling is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transmit/receive-error interrupt (ERI) request will be generated. See Interrupt Operation in section 17.3.6 below for details. Rev.7.00 Oct. 10, 2008 Page 792 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Start Initialization Start of transmission 2 FER/ERS = 0? Yes Error handling No TEND = 1? Yes Write transmit data to SCTDR1, and clear TDRE flag in SCSSR1 to 0 No All data transmitted? Yes FER/ERS = 0? Yes Error handling No TEND = 1? Yes Clear TE bit in SCSCR1 to 0 6 No 4 3 1 No 5 End of transmission Figure 17.8 Sample Transmission Processing Flowchart Rev.7.00 Oct. 10, 2008 Page 793 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Serial Data Reception: Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 17.9 shows a sample reception processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2. Check that the ORER flag and PER flag in SCSSR1 are cleared to 0. If either is set, perform the appropriate receive error handling, then clear both the ORER and the PER flag to 0. 3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1. 4. Read the receive data from SCRDR1. 5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2. 6. To end reception, clear the RE bit to 0. With the above processing, interrupt handling is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) request will be generated. See Interrupt Operation in section 17.3.6 below for details. If a parity error occurs during reception and the PER flag is set to 1, the received data is still transferred to SCRDR1, and therefore this data can be read. Rev.7.00 Oct. 10, 2008 Page 794 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Start Initialization Start of reception 2 ORER = 0 and PER = 0? Yes Error handling No RDRF = 1? Yes Read receive data from SCRDR1 and clear RDRF flag in SCSSR1 to 0 No All data received? Yes Clear RE bit in SCSCR1 to 0 6 4 3 No 1 5 End of reception Figure 17.9 Sample Reception Processing Flowchart Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE to 0 and setting TE to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND flag can be used to check that the transmit operation has been completed. Rev.7.00 Oct. 10, 2008 Page 795 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Interrupt Operation: There are three interrupt sources in smart card interface mode, generating transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request cannot be used in this mode. When the TEND flag in SCSSR1 is set to 1, a TXI interrupt request is generated. When the RDRF flag in SCSSR1 is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and FER/ERS in SCSSR1 is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 17.9. Table 17.9 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit mode Normal operation Error Receive mode Normal operation Error Flag TEND FER/ERS RDRF PER, ORER Mask Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI Data Transfer Operation by DMAC: In smart card mode, as with the normal SCI, transfer can be carried out using the DMAC. In a transmit operation, when the TEND flag in SCSSR1 is set to 1, a TXI interrupt is requested. If the TXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TEND flag is automatically cleared to 0 when data transfer is performed by the DMAC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DMAC is not activated. Thus, the number of bytes specified by the SCI and DMAC are transmitted automatically, including retransmission following an error. However, the ERS flag is not cleared automatically when an error occurs, and therefore the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SCSSR1 is set to 1. If the RXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC. If an error occurs, an error flag is set but the RDRF flag is not. The DMAC is not activated, but instead, an ERI interrupt request is sent to the CPU. The error flag must therefore be cleared. Rev.7.00 Oct. 10, 2008 Page 796 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface When performing data transfer using the DMAC, it is essential to set and enable the DMAC before carrying out SCI settings. For details of the DMAC setting procedures, see section 14, Direct Memory Access Controller (DMAC). 17.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. (1) Receive Data Sampling Timing and Receive Margin In asynchronous mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the 186th base clock pulse. The timing is shown in figure 17.10. 372 clocks 186 clocks 0 Base clock 185 371 0 185 371 0 Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 17.10 Receive Data Sampling Timing in Smart Card Mode Rev.7.00 Oct. 10, 2008 Page 797 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface The receive margin in smart card mode can therefore be expressed as shown in the following equation. M = (0.5 – 1 | D – 0.5 | ) – (L – 0.5) F – (1 + F) × 100% 2N N M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 372) Clock duty cycle (D = 0 to 1.0) Frame length (L =10) Absolute deviation of clock frequency From the above equation, if F = 0 and D = 0.5, the receive margin is 49.866%, as given by the following equation. When D = 0.5 and F = 0: M = (0.5 – 1/2 × 372) × 100% = 49.866% (2) Retransfer Operations Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. Retransfer Operation when SCI is in Receive Mode: Figure 17.11 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is automatically set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt request is generated. The PER bit in SCSSR1 should be cleared to 0 before the next parity bit is sampled. 2. The RDRF bit in SCSSR1 is not set for a frame in which an error has occurred. 3. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is not set to 1. 4. If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF bit in SCSSR1 is automatically set to 1. If the RIE bit in SCSCR1 is enabled at this time, an RXI interrupt request is generated. 5. When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. Rev.7.00 Oct. 10, 2008 Page 798 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Transfer frame n+1 Ds D0 D1 D2 D3 D4 5 RDRF 2 PER 1 3 4 Figure 17.11 Retransfer Operation in SCI Receive Mode Retransfer Operation when SCI is in Transmit Mode: Figure 17.12 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sent back from the receiving side after transmission of one frame is completed, the FER/ERS bit in SCSSR1 is set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt request is generated. The FER/ERS bit in SCSSR1 should be cleared to 0 before the next parity bit is sampled. 2. The TEND bit in SCSSR1 is not set for a frame for which an error signal indicating an error is received. 3. If an error signal is not sent back from the receiving side, the FER/ERS bit in SCSSR1 is not set. 4. If an error signal is not sent back from the receiving side, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SCSSR1 is set to 1. If the TIE bit in SCSCR1 is enabled at this time, a TXI interrupt request is generated. nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer from SCTDR1 to SCTSR1 TEND 2 FER/ERS 1 3 4 Transfer from SCTDR1 to SCTSR1 Transfer from SCTDR1 to SCTSR1 Retransferred frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 Transfer frame n+1 Figure 17.12 Retransfer Operation in SCI Transmit Mode Rev.7.00 Oct. 10, 2008 Page 799 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface (3) Standby Mode and Clock When switching between smart card interface mode and standby mode, the following procedures should be used to maintain the clock duty cycle. Switching from Smart Card Interface Mode to Standby Mode: 1. Set the SBP1IO and SBP1DT bits in SCSPTR1 to the values for the fixed output state in standby mode. 2. Write 0 to the TE and RE bits in the serial control register (SCSCR1) to stop transmit/receive operations. At the same time, set the CKE1 bit to the value for the fixed output state in standby mode. 3. Write 0 to the CKE0 bit in SCSCR1 to stop the clock. 4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock output is fixed at the specified level. 5. Write H'00 to the serial mode register (SCSMR1) and smart card mode register (SCSMR1). 6. Make the transition to the standby state. Returning from Standby Mode to Smart Card Interface Mode: 7. Clear the standby state. 8. Set the CKE1 bit in SCSCR1 to the value for the fixed output state at the start of standby (the current SCK pin state). 9. Set smart card interface mode and output the clock. Clock signal generation is started with the normal duty cycle. Standby mode Normal operation Normal operation 123 4 56 7 89 Figure 17.13 Procedure for Stopping and Restarting the Clock Rev.7.00 Oct. 10, 2008 Page 800 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface (4) Power-On and Clock The following procedure should be used to secure the clock duty cycle after powering on. 1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the potential. 2. Fix at the output specified by the CKE1 bit in the serial control register (SCSCR1). 3. Set the serial mode register (SCSMR1) and smart card mode register (SCSCMR1), and switch to smart card mode operation. 4. Set the CKE0 bit in SCSCR1 to 1 to start clock output. Rev.7.00 Oct. 10, 2008 Page 801 of 1074 REJ09B0366-0700 Section 17 Smart Card Interface Rev.7.00 Oct. 10, 2008 Page 802 of 1074 REJ09B0366-0700 Section 18 I/O Ports Section 18 I/O Ports 18.1 Overview This LSI has a 20-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port. 18.1.1 Features The features of the general-purpose I/O port are as follows: • • • • 20-bit I/O port with input/output direction independently specifiable for each bit Pull-up can be specified independently for each bit. Interrupt input is possible for 16 of the 20 I/O port bits. Use or non-use of the I/O port can be selected with the PORTEN bit in bus control register 2 (BCR2). The features of the SCI I/O port are as follows: • Data can be output when the I/O port is designated for output and SCI enabling has not been set. This allows break function transmission. • The RxD pin value can be read at all times, allowing break state detection. • SCK pin control is possible when the I/O port is designated for output and SCI enabling has not been set. • The SCK pin value can be read at all times. The features of the SCIF I/O port are as follows: • Data can be output when the I/O port is designated for output and SCIF enabling has not been set. This allows break function transmission. • The RxD2 pin value can be read at all times, allowing break state detection. • CTS2 and RTS2 pin control is possible when the I/O port is designated for output and SCIF enabling has not been set. • The CTS2 and RTS2 pin values can be read at all times. Rev.7.00 Oct. 10, 2008 Page 803 of 1074 REJ09B0366-0700 Section 18 I/O Ports 18.1.2 Block Diagrams Figure 18.1 shows a block diagram of the 16-bit general-purpose I/O port. PBnPUP PORTEN Pull-up resistor Internal bus MPX Dn output data DQ C BCK 0 1 PDTRW Port 15 (input/ output)/D47 to Port 0 (input/ output)/D32 1 PBnIO 0 Data input strobe C D BCK MPX 1 Q Interrupt controller PTIRENn Dn input data PORTEN PBnPuP DnDIR PBnIO PTIRENn 0: Port not available 0: Pull-up 0: Input 0: Input 0: Interrupt input disabled 1: Port available 1: Pull-up off 1: Output 1: Output 1: Interrupt input enabled Figure 18.1 16-Bit Port Rev.7.00 Oct. 10, 2008 Page 804 of 1074 REJ09B0366-0700 MPX DnDIR 0 Section 18 I/O Ports Figure 18.2 shows a block diagram of the 4-bit general-purpose I/O port. PBnPUP PORTEN Pull-up resistor Internal bus MPX Dn output data DQ C BCK 0 1 PDTRW Port 19 (input/ output)/D51 to Port 16 (input/ output)/D48 1 PBnIO 0 MPX Data input strobe C QD BCK 1 Dn input data PORTEN PBnPuP DnDIR PBnIO 0: Port not available 0: Pull-up 0: Input 0: Input 1: Port available 1: Pull-up off 1: Output 1: Output Figure 18.2 4-Bit Port MPX DnDIR 0 Rev.7.00 Oct. 10, 2008 Page 805 of 1074 REJ09B0366-0700 Section 18 I/O Ports SCI I/O port block diagrams are shown in figures 18.3 to 18.5. Reset R Q D SPB1IO C Internal data bus SPTRW Reset MD0/SCK D SPB1DT C SPTRW Mode setting register Q R SCI Clock output enable signal Serial clock output signal Serial clock input signal Clock input enable signal * SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C/A bit in SCSMR1. Figure 18.3 MD0/SCK Pin Rev.7.00 Oct. 10, 2008 Page 806 of 1074 REJ09B0366-0700 Section 18 I/O Ports Reset R Q D SPB0IO C SPTRW MD7/TxD Reset R Q D SPB0DT C SPTRW Mode setting register Serial transmit data Legend: SPTRW: Write to SPTR Internal data bus SCI Transmit enable signal Figure 18.4 MD7/TxD Pin RxD SCI Serial receive data Internal data bus SPTRR Legend: Read SPTR Figure 18.5 RxD Pin Rev.7.00 Oct. 10, 2008 Page 807 of 1074 REJ09B0366-0700 Section 18 I/O Ports SCIF I/O port block diagrams are shown in figures 18.6 to 18.9. Reset R Q D SPB2IO C Internal data bus SPTRW MD1/TxD2 Reset R Q D SPB2DT C SCIF Transmit enable signal SPTRW Mode setting register Legend: Serial transmit data SPTRW: Write to SPTR Figure 18.6 MD1/TxD2 Pin MD2/RxD2 SCIF Mode setting register Serial receive data Internal data bus SPTRR Legend: SPTRR: Read SPTR Figure 18.7 MD2/RxD2 Pin Rev.7.00 Oct. 10, 2008 Page 808 of 1074 REJ09B0366-0700 Section 18 I/O Ports Reset R Q D CTSIO C Internal data bus SPTRW CTS2 Reset R Q D CTSDT C SCIF SPTRW CTS2 signal Modem control enable signal* SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the CTS2 pin function. Figure 18.8 CTS2 Pin Rev.7.00 Oct. 10, 2008 Page 809 of 1074 REJ09B0366-0700 Section 18 I/O Ports Reset R Q D RTSIO C Internal data bus SPTRW MD8/RTS2 Reset R Q D RTSDT C SCIF Modem control enable signal* SPTRW Mode setting register RTS2 signal SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the RTS2 pin function. Figure 18.9 MD8/RTS2 Pin Rev.7.00 Oct. 10, 2008 Page 810 of 1074 REJ09B0366-0700 Section 18 I/O Ports 18.1.3 Pin Configuration Table 18.1 shows the 20-bit general-purpose I/O port pin configuration. Table 18.1 20-Bit General-Purpose I/O Port Pins Pin Name Port 19 pin Port 18 pin Port 17 pin Port 16 pin Port 15 pin Port 14 pin Port 13 pin Port 12 pin Port 11 pin Port 10 pin Port 9 pin Port 8 pin Port 7 pin Port 6 pin Port 5 pin Port 4 pin Port 3 pin Port 2 pin Port 1 pin Port 0 pin Note: * Signal PORT19/D51 PORT18/D50 PORT17/D49 PORT16/D48 PORT15/D47 PORT14/D46 PORT13/D45 PORT12/D44 PORT11/D43 PORT10/D42 PORT9/D41 PORT8/D40 PORT7/D39 PORT6/D38 PORT5/D37 PORT4/D36 PORT3/D35 PORT2/D34 PORT1/D33 PORT0/D32 I/O I/O I/O I/O I/O I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* Function I/O port I/O port I/O port I/O port I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt I/O port / GPIO interrupt When port pins are used as GPIO interrupts, they must be set to input mode. The input setting can be made in the PCTRA register. Rev.7.00 Oct. 10, 2008 Page 811 of 1074 REJ09B0366-0700 Section 18 I/O Ports Table 18.2 shows the SCI I/O port pin configuration. Table 18.2 SCI I/O Port Pins Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation MD0/SCK RxD MD7/TxD I/O I/O Input Output Function Clock input/output Receive data input Transmit data output Note: Pins MD0/SCK and MD7/TxD function as mode input pins MD0 and MD7 after a power-on reset. They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR1 and the C/A bit in SCSMR1. Break state transmission and detection can be performed by means of a setting in the SCI's SCSPTR1 register. Table 18.3 shows the SCIF I/O port pin configuration. Table 18.3 SCIF I/O Port Pins Pin Name Serial clock pin Receive data pin Transmit data pin Modem control pin Modem control pin Abbreviation MRESET/SCK2 MD2/RxD2 MD1/TxD2 CTS2 MD8/RTS2 I/O Input Input Output I/O I/O Function Clock input Receive data input Transmit data output Transmission enabled Transmission request Note: The MRESET/SCK2 pin functions as the MRESET manual reset pin when a manual reset is executed. The MD1/TxD2, MD2/RxD2, and MD8/RTS2 pins function as the MD1, MD2, and MD8 mode input pins after a power-on reset. These pins are made to function as serial pins by performing SCIF operation settings with the TE and RE bits in SCSCR2 and the MCE bit in SCFCR2. Break state transmission and detection can be set in the SCIF's SCSPTR2 register. Rev.7.00 Oct. 10, 2008 Page 812 of 1074 REJ09B0366-0700 Section 18 I/O Ports 18.1.4 Register Configuration The 20-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port have seven registers, as shown in table 18.4. Table 18.4 I/O Port Registers Name Port control register A Port data register A Port control register B Port data register B GPIO interrupt control register Serial port register Serial port register Note: * Abbreviation R/W PCTRA PDTRA PCTRB PDTRB GPIOIC SCSPTR1 SCSPTR2 R/W R/W R/W R/W R/W R/W R/W Initial Value* P4 Address H'00000000 Undefined H'00000000 Undefined H'00000000 Undefined Undefined Area 7 Address Access Size H'FF80002C H'1F80002C 32 H'FF800030 H'FF800040 H'FF800044 H'FF800048 H'1F800030 H'1F800040 H'1F800044 H'1F800048 16 32 16 16 H'FFE0001C H'1FE0001C 8 H'FFE80020 H'1FE80020 16 Initialized by a power-on reset. Rev.7.00 Oct. 10, 2008 Page 813 of 1074 REJ09B0366-0700 Section 18 I/O Ports 18.2 18.2.1 Register Descriptions Port Control Register A (PCTRA) Port control register A (PCTRA) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 16-bit port (port 15 pin to port 0 pin). As the initial value of port data register A (PDTRA) is undefined, all the bits in the 16-bit port should be set to output with PCTRA after writing a value to the PDTRA register. PCTRA is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. Bit: 31 PB15PUP 30 PB15IO 29 PB14PUP 28 PB14IO 27 PB13PUP 26 PB13IO 25 PB12PUP 24 PB12IO Initial value: R/W: Bit: 0 R/W 23 PB11PUP 0 R/W 22 PB11IO 0 R/W 21 PB10PUP 0 R/W 20 PB10IO 0 R/W 19 PB9PUP 0 R/W 18 PB9IO 0 R/W 17 PB8PUP 0 R/W 16 PB8IO Initial value: R/W: Bit: 0 R/W 15 PB7PUP 0 R/W 14 PB7IO 0 R/W 13 PB6PUP 0 R/W 12 PB6IO 0 R/W 11 PB5PUP 0 R/W 10 PB5IO 0 R/W 9 PB4PUP 0 R/W 8 PB4IO Initial value: R/W: Bit: 0 R/W 7 PB3PUP 0 R/W 6 PB3IO 0 R/W 5 PB2PUP 0 R/W 4 PB2IO 0 R/W 3 PB1PUP 0 R/W 2 PB1IO 0 R/W 1 PB0PUP 0 R/W 0 PB0IO Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev.7.00 Oct. 10, 2008 Page 814 of 1074 REJ09B0366-0700 Section 18 I/O Ports Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16bit port is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO. Bit 2n + 1: PBnPUP 0 1 Description Bit m (m = 0–15) of 16-bit port is pulled up Bit m (m = 0–15) of 16-bit port is not pulled up (Initial value) Bit 2n (n = 0–15)—Port I/O Control (PBnIO): Specifies whether each bit in the 16-bit port is an input or an output. Bit 2n: PBnIO 0 1 Description Bit m (m = 0–15) of 16-bit port is an input Bit m (m = 0–15) of 16-bit port is an output (Initial value) 18.2.2 Port Data Register A (PDTRA) Port data register A (PDTRA) is a 16-bit readable/writable register used as a data latch for each bit in the 16-bit port. When a bit is set as an output, the value written to the PDTRA register is output from the external pin. When a value is read from the PDTRA register while a bit is set as an input, the external pin value sampled on the external bus clock is read. When a bit is set as an output, the value written to the PDTRA register is read. PDTRA is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. Bit: 15 14 13 12 11 10 9 8 PB8DT — R/W 0 PB0DT — R/W PB15DT PB14DT PB13DT PB12DT PB11DT PB10DT PB9DT Initial value: R/W: Bit: — R/W 7 PB7DT Initial value: R/W: — R/W — R/W 6 PB6DT — R/W — R/W 5 PB5DT — R/W — R/W 4 PB4DT — R/W — R/W 3 PB3DT — R/W — R/W 2 PB2DT — R/W — R/W 1 PB1DT — R/W Rev.7.00 Oct. 10, 2008 Page 815 of 1074 REJ09B0366-0700 Section 18 I/O Ports 18.2.3 Port Control Register B (PCTRB) Port control register B (PCTRB) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 4-bit port (port 19 pin to port 16 pin). As the initial value of port data register B (PDTRB) is undefined, each bit in the 4-bit port should be set to output with PCTRB after writing a value to the PDTRB register. PCTRB is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. Bit: 31 — Initial value: R/W: Bit: 0 R 23 — Initial value: R/W: Bit: 0 R 15 — Initial value: R/W: Bit: 0 R 7 PB19PUP 30 — 0 R 22 — 0 R 14 — 0 R 6 PB19IO 29 — 0 R 21 — 0 R 13 — 0 R 5 PB18PUP 28 — 0 R 20 — 0 R 12 — 0 R 4 PB18IO 27 — 0 R 19 — 0 R 11 — 0 R 3 PB17PUP 26 — 0 R 18 — 0 R 10 — 0 R 2 PB17IO 25 — 0 R 17 — 0 R 9 — 0 R 1 PB16PUP 24 — 0 R 16 — 0 R 8 — 0 R 0 PB16IO Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev.7.00 Oct. 10, 2008 Page 816 of 1074 REJ09B0366-0700 Section 18 I/O Ports Bit 2n + 1 (n = 0–3)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 4-bit port is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO. Bit 2n + 1: PBnPUP 0 1 Description Bit m (m = 16–19) of 4-bit port is pulled up Bit m (m = 16–19) of 4-bit port is not pulled up (Initial value) Bit 2n (n = 0–3)—Port I/O Control (PBnIO): Specifies whether each bit in the 4-bit port is an input or an output. Bit 2n: PBnIO 0 1 Description Bit m (m = 16–19) of 4-bit port is an input Bit m (m = 16–19) of 4-bit port is an output (Initial value) 18.2.4 Port Data Register B (PDTRB) Port data register B (PDTRB) is a 16-bit readable/writable register used as a data latch for each bit in the 4-bit port. When a bit is set as an output, the value written to the PDTRB register is output from the external pin. When a value is read from the PDTRB register while a bit is set as an input, the external pin value sampled on the external bus clock is read. When a bit is set as an output, the value written to the PDTRB register is read. PDTRB is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 — 0 R 12 — 0 R 4 — 0 R 11 — 0 R 3 10 — 0 R 2 9 — 0 R 1 8 — 0 R 0 PB19DT PB18DT PB17DT PB16DT — R/W — R/W — R/W — R/W Rev.7.00 Oct. 10, 2008 Page 817 of 1074 REJ09B0366-0700 Section 18 I/O Ports 18.2.5 GPIO Interrupt Control Register (GPIOIC) The GPIO interrupt control register (GPIOIC) is a 16-bit readable/writable register that performs 16-bit interrupt input control. GPIOIC is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. GPIO interrupts are active-low level interrupts. Bit-by-bit masking is possible, and the OR of all the bits set as GPIO interrupts is used for interrupt detection. Which bits interrupts are input to can be identified by reading the PDTRA register. Bit: 15 14 13 12 11 10 9 8 PTIREN15 PTIREN14 PTIREN13 PTIREN12 PTIREN11 PTIREN10 PTIREN9 PTIREN8 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 PTIREN7 PTIREN6 PTIREN5 PTIREN4 PTIREN3 PTIREN2 PTIREN1 PTIREN0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit n (n = 0–15)—Port Interrupt Enable (PTIRENn): Specifies whether interrupt input is performed for each bit. Bit n: PTIRENn 0 1 Note: * Description Port m (m = 0–15) of 16-bit port is used as a normal I/O port (Initial value) Port m (m = 0–15) of 16-bit port is used as a GPIO interrupt* When using an interrupt, set the corresponding port to input in the PCTRA register before making the PTIRENn setting. Rev.7.00 Oct. 10, 2008 Page 818 of 1074 REJ09B0366-0700 Section 18 I/O Ports 18.2.6 Serial Port Register (SCSPTR1) Bit: 7 EIO Initial value: R/W: 0 R/W 6 — 0 — 5 — 0 — 4 — 0 — 3 2 1 0 SPB1IO SPB1DT SPB0IO SPB0DT 0 R/W — R/W 0 R/W — R/W The serial port register (SCSPTR1) is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCI) pins. Input data can be read from the RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt. SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0 are initialized to H'00 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined. SCSPTR1 is not initialized in the module standby state or standby mode. Bit 7—Error Interrupt Only (EIO): See section 15.2.8, Serial Port Register (SCSPTR1). Bits 6 to 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0. Bit 3: SPB1IO 0 1 Description SPB1DT bit value is not output to the SCK pin SPB1DT bit value is output to the SCK pin (Initial value) Rev.7.00 Oct. 10, 2008 Page 819 of 1074 REJ09B0366-0700 Section 18 I/O Ports Bit 2—Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 2: SPB1DT 0 1 Description Input/output data is low-level Input/output data is high-level Bit 1—Serial Port Break I/O (SPB0IO): Specifies the serial port TxD pin output condition. When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit, the TE bit in SCSCR1 should be cleared to 0. Bit 1: SPB0IO 0 1 Description SPB0DT bit value is not output to the TxD pin SPB0DT bit value is output to the TxD pin (Initial value) Bit 0—Serial Port Break Data (SPB0DT): Specifies the serial port RxD pin input data and TxD pin output data. The TxD pin output condition is specified by the SPB0IO bit (see the description of bit 1, SPB0IO, for details). When the TxD pin is designated as an output, the value of the SPB0DT bit is output to the TxD pin. The RxD pin value is read from the SPB0DT bit regardless of the value of the SPB0IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB0DT 0 1 Description Input/output data is low-level Input/output data is high-level Rev.7.00 Oct. 10, 2008 Page 820 of 1074 REJ09B0366-0700 Section 18 I/O Ports 18.2.7 Serial Port Register (SCSPTR2) Bit: 15 — Initial value: R/W: Bit: 0 R 7 RTSIO Initial value: R/W: 0 R/W 14 — 0 R 6 RTSDT — R/W 13 — 0 R 5 CTSIO 0 R/W 12 — 0 R 4 CTSDT — R/W 11 — 0 R 3 — 0 R 10 — 0 R 2 — 0 R 9 — 0 R 1 8 — 0 R 0 SPB2IO SPB2DT 0 R/W — R/W The serial port register (SCSPTR2) is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins. Input data can be read from the RxD2 pin, output data written to the TxD2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. CTS2 pin data reading and output data writing can be performed by means of bits 5 and 4, and RTS2 pin data reading and output data writing by means of bits 7 and 6. SCSPTR2 can be read or written to by the CPU at all times. All SCSPTR2 bits except bits 6, 4, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, and 0 is undefined. SCSPTR2 is not initialized in standby mode or in the module standby state. Bits 15 to 8—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Serial Port RTS Port I/O (RTSIO): Specifies serial port RTS2 pin input/output. When the RTS2 pin is actually set as a port output pin and outputs the value set by the RTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 7: RTSIO 0 1 Description RTSDT bit value is not output to the RTS2 pin RTSDT bit value is output to the RTS2 pin (Initial value) Rev.7.00 Oct. 10, 2008 Page 821 of 1074 REJ09B0366-0700 Section 18 I/O Ports Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port RTS2 pin input/output data. Input or output is specified by the RTSIO pin (see the description of bit 7, RTSIO, for details). When the RTS2 pin is designated as an output, the value of the RTSDT bit is output to the RTS2 pin. The RTS2 pin value is read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 6: RTSDT 0 1 Description Input/output data is low-level Input/output data is high-level Bit 5—Serial Port CTS Port I/O (CTSIO): Specifies serial port CTS2 pin input/output. When the CTS2 pin is actually set as a port output pin and outputs the value set by the CTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 5: CTSIO 0 1 Description CTSDT bit value is not output to the CTS2 pin CTSDT bit value is output to the CTS2 pin (Initial value) Bit 4—Serial Port CTS Port Data (CTSDT): Specifies the serial port CTS2 pin input/output data. Input or output is specified by the CTSIO pin (see the description of bit 5, CTSIO, for details). When the CTS2 pin is designated as an output, the value of the CTSDT bit is output to the CTS2 pin. The CTS2 pin value is read from the CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 4: CTSDT 0 1 Description Input/output data is low-level Input/output data is high-level Bits 3 and 2—Reserved: These bits are always read as 0, and should only be written with 0. Bit 1—Serial Port Break I/O (SPB2IO): Specifies the serial port TxD2 pin output condition. When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT bit, the TE bit in SCSCR2 should be cleared to 0. Bit 1: SPB2IO 0 1 Description SPB2DT bit value is not output to the TxD2 pin SPB2DT bit value is output to the TxD2 pin (Initial value) Rev.7.00 Oct. 10, 2008 Page 822 of 1074 REJ09B0366-0700 Section 18 I/O Ports Bit 0—Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value of the SPB2DT bit is output to the TxD2 pin. The RxD2 pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB2DT 0 1 Description Input/output data is low-level Input/output data is high-level Rev.7.00 Oct. 10, 2008 Page 823 of 1074 REJ09B0366-0700 Section 18 I/O Ports Rev.7.00 Oct. 10, 2008 Page 824 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) Section 19 Interrupt Controller (INTC) 19.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to handle interrupt requests according to user-set priority. 19.1.1 Features The INTC has the following features. • Fifteen interrupt priority levels can be set By setting the three interrupt priority registers, the priorities of on-chip peripheral module interrupts can be selected from 15 levels for different request sources. • NMI noise canceler function The NMI input level bit indicates the NMI pin state. The pin state can be checked by reading this bit in the interrupt exception service routine, enabling it to be used as a noise canceler. • NMI request masking when SR.BL bit is set to 1 It is possible to select whether or not NMI requests are to be masked when the SR.BL bit is set to 1. 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the INTC. Rev.7.00 Oct. 10, 2008 Page 825 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) NMI IRL3– IRL0 TMU RTC SCI SCIF WDT REF DMAC H-UDI GPIO Input control 4 (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) Priority identifier Comparator Interrupt request SR IMASK CPU 4 IPR ICR IPRA–IPRD*1 INTPRI00*2 Bus interface INTC Legend: TMU: Timer unit RTC: Realtime clock unit SCI: Serial communication interface SCIF: Serial communication interface with FIFO WDT: Watchdog timer REF: Memory refresh controller section of the bus state controller DMAC: Direct memory access controller H-UDI: High-performance user debug interface GPIO: I/O port ICR: Interrupt control register IPRA–IPRD: Interrupt priority registers A–D*1 INTPRI00: Interrupt priority level setting register 00*2 SR: Status register Notes: 1. IPRD is provided only in the SH7750S and SH7750R. 2. INTPRI00 is provided only in the SH7750R. Figure 19.1 Block Diagram of INTC Rev.7.00 Oct. 10, 2008 Page 826 of 1074 REJ09B0366-0700 Internal bus Section 19 Interrupt Controller (INTC) 19.1.3 Pin Configuration Table 19.1 shows the INTC pin configuration. Table 19.1 INTC Pins Pin Name Nonmaskable interrupt input pin Interrupt input pins Abbreviation NMI IRL3–IRL0 I/O Input Input Function Input of nonmaskable interrupt request signal Input of interrupt request signals (maskable by IMASK in SR) 19.1.4 Register Configuration The INTC has the registers shown in table 19.2. Table 19.2 INTC Registers Initial Value*1 Name Interrupt control register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D*3 Interrupt priority level setting 4 register 00* Interrupt source register 00*4 Interrupt mask register 00*4 Abbreviation ICR IPRA IPRB IPRC IPRD INTPRI00 R/W R/W R/W R/W R/W R/W R/W *2 H'0000 H'0000 H'0000 H'DA74 H'00000000 P4 Address H'FFD00000 H'FFD00004 H'FFD00008 H'FFD0000C H'FFD00010 H'FE080000 Area 7 Address H'1FD00000 H'1FD00004 H'1FD00008 H'1FD0000C H'1FD00010 H'1E080000 Access Size 16 16 16 16 16 32 INTREQ00 INTMSK00 R R/W H'00000000 H'00000300 — H'FE080020 H'FE080040 H'FE080060 H'1E080020 H'1E080040 H'1E080060 32 32 32 Interrupt mask INTMSKCLR00 R clear register 00*4 Notes: 1. Initialized by a power-on reset or manual reset. Rev.7.00 Oct. 10, 2008 Page 827 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) 2. H'8000 when the NMI pin is high, H'0000 when the NMI pin is low. 3. SH7750S and SH7750R only 4. SH7750R only 19.2 Interrupt Sources There are three types of interrupt sources: NMI, RL, and on-chip peripheral modules. Each interrupt has a priority level (16–0), with level 16 as the highest and level 1 as the lowest. When level 0 is set, the interrupt is masked and interrupt requests are ignored. 19.2.1 NMI Interrupt The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in the status register in the CPU is set to 1. In sleep or standby mode, the interrupt is accepted even if the BL bit is set to 1. A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1. Input from the NMI pin is edge-detected. The NMI edge select bit (NMIE) in the interrupt control register (ICR) is used to select either rising or falling edge. When the NMIE bit in the ICR register is modified, the NMI interrupt is not detected for a maximum of 6 bus clock cycles after the modification. NMI interrupt exception handling does not affect the interrupt mask level bits (IMASK) in the status register (SR). Rev.7.00 Oct. 10, 2008 Page 828 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) 19.2.2 IRL Interrupts IRL interrupts are input by level at pins IRL3–IRL0. The priority level is the level indicated by pins IRL3–IRL0. An IRL3–IRL0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0). SH7750 SH7750S SH7750R Interrupt requests Priority encoder 4 IRL3 to IRL0 IRL3 to IRL0 Figure 19.2 Example of IRL Interrupt Connection Rev.7.00 Oct. 10, 2008 Page 829 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) Table 19.3 IRL3–IRL0 Pins and Interrupt Levels IRL3 0 IRL2 0 IRL1 0 IRL0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Interrupt Priority Level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt Request Level 15 interrupt request Level 14 interrupt request Level 13 interrupt request Level 12 interrupt request Level 11 interrupt request Level 10 interrupt request Level 9 interrupt request Level 8 interrupt request Level 7 interrupt request Level 6 interrupt request Level 5 interrupt request Level 4 interrupt request Level 3 interrupt request Level 2 interrupt request Level 1 interrupt request No interrupt request A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels sampled at every bus clock cycle remain unchanged for three consecutive cycles, so that no transient level on the IRL pin change is detected. In standby mode, as the bus clock is stopped, noise cancellation is performed using the 32.768 kHz clock for the RTC instead. When the RTC is not used, therefore, interruption by means of IRL interrupts cannot be performed in standby mode. The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the interrupt handling starts. However, the priority level can be changed to a higher one. The interrupt mask bits (IMASK) in the status register (SR) are not affected by IRL interrupt handling. Pins IRL0–IRL3 can be used for four independent interrupt requests by setting the IRLM bit to 1 in the ICR register. When independent interrupt requests are used in the SH7750, the interrupt priority levels are fixed (table 19.4). When independent interrupt requests are used in the SH7750S or SH7750R, the interrupt priority levels can be set in interrupt priority register D (IPRD). Rev.7.00 Oct. 10, 2008 Page 830 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) Table 19.4 SH7750 IRL3–IRL0 Pins and Interrupt Levels (When IRLM = 1) IRL3 1/0 1/0 1/0 0 IRL2 1/0 1/0 0 1 IRL1 1/0 0 1 1 IRL0 0 1 1 1 Interrupt Priority Level 13 10 7 4 Interrupt Request IRL0 IRL1 IRL2 IRL3 19.2.3 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following nine modules: • • • • • • • • • High-performance user debug interface (H-UDI) Direct memory access controller (DMAC) Timer unit (TMU) Realtime clock (RTC) Serial communication interface (SCI) Serial communication interface with FIFO (SCIF) Bus state controller (BSC) Watchdog timer (WDT) I/O port (GPIO) Not every interrupt source is assigned a different interrupt vector, bus sources are reflected in the interrupt event register (INTEVT), so it is easy to identify sources by using the INTEVT register value as a branch offset in the exception handling routine. A priority level from 15 to 0 can be set for each module by means of interrupt priority registers A to D (IPRA–IPRD), 00 (INTPRI00). The interrupt mask bits (IMASK) in the status register (SR) are not affected by on-chip peripheral module interrupt handling. On-chip peripheral module interrupt source flag and interrupt enable flag updating should only be carried out when the BL bit in the status register (SR) is set to 1. To prevent acceptance of an erroneous interrupt from an interrupt source that should have been updated, first read the on-chip peripheral register containing the relevant flag, then clear the BL bit to 0. In the case of interrupts on channel 3 or 4 of the TMU, also read from the interrupt source register 00 (INTREQ00). This Rev.7.00 Oct. 10, 2008 Page 831 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) will secure the necessary timing internally. When updating a number of flags, there is no problem if only the register containing the last flag updated is read. If flag updating is performed while the BL bit is cleared to 0, the program may jump to the interrupt handling routine when the INTEVT register value is 0. In this case, interrupt handling is initiated due to the timing relationship between the flag update and interrupt request recognition within the chip. Processing can be continued without any problem by executing an RTE instruction. 19.2.4 Interrupt Exception Handling and Priority Table 19.5 lists the codes for the interrupt event register (INTEVT), and the order of interrupt priority. Each interrupt source is assigned a unique INTEVT code. The start address of the interrupt handler is common to each interrupt source. This is why, for instance, the value of INTEVT is used as an offset at the start of the interrupt handler and branched to in order to identify the interrupt source. The order of priority of the on-chip peripheral modules is specified as desired by setting priority levels from 0 to 15 in interrupt priority registers A to D (IPRA–IPRD). The order of priority of the on-chip peripheral modules is set to 0 by a reset. When the priorities for multiple interrupt sources are set to the same level and such interrupts are generated simultaneously, they are handled according to the default priority order shown in table 19.5. Updating of interrupt priority registers A to D, 00 should only be carried out when the BL bit in the status register (SR) is set to 1. To prevent erroneous interrupt acceptance, first read one of the interrupt priority registers, then clear the BL bit to 0. This will secure the necessary timing internally. Rev.7.00 Oct. 10, 2008 Page 832 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) Table 19.5 Interrupt Exception Handling Sources and Priority Order Interrupt Source NMI IRL INTEVT Interrupt Priority IPR (Bit Code (Initial Value) Numbers) H'1C0 IRL3–IRL0 = 0 H'200 IRL3–IRL0 = 1 H'220 IRL3–IRL0 = 2 H'240 IRL3–IRL0 = 3 H'260 IRL3–IRL0 = 4 H'280 IRL3–IRL0 = 5 H'2A0 IRL3–IRL0 = 6 H'2C0 IRL3–IRL0 = 7 H'2E0 IRL3–IRL0 = 8 H'300 IRL3–IRL0 = 9 H'320 IRL3–IRL0 = A H'340 IRL3–IRL0 = B H'360 IRL3–IRL0 = C H'380 IRL3–IRL0 = D H'3A0 IRL3–IRL0 = E H'3C0 IRL0 IRL1 IRL2 IRL3 H-UDI GPIO DMAC H-UDI GPIOI DMTE0 DMTE1 DMTE2 DMTE3 DMTE4*2 DMTE5* 2 Priority within IPR Setting Unit — — — — — — — — — — — — — — — — Default Priority High ↑ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ↓ Low 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15–0 (13)*1 15–0 (10)*1 15–0 (7)*1 15–0 (4)* 15–0 (0) 15–0 (0) 15–0 (0) 1 — — — — — — — — — — — — — — — — H'240 H'2A0 H'300 H'360 H'600 H'620 H'640 H'660 H'680 H'6A0 H'780 H'7A0 H'7C0 H'7E0 H'6C0 IPRD (15–12)*1 — IPRD (11–8)*1 — IPRD (7–4)*1 IPRD (3–0)*1 IPRC (3–0) IPRC (15–12) IPRC (11–8) — — — — High ↑ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ↓ Low DMTE6*2 DMTE7*2 DMAE Rev.7.00 Oct. 10, 2008 Page 833 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) INTEVT Interrupt Priority IPR (Bit Code (Initial Value) Numbers) H'B00 H'B80 H'400 H'420 H'440 H'460 H'480 H'4A0 H'4C0 H'4E0 H'500 H'520 H'540 H'700 H'720 H'740 H'760 H'560 H'580 H'5A0 15–0 (0) 15–0 (0) IPRB (15–12) IPRB (11–8) 15–0 (0) IPRC (7–4) 15–0 (0) IPRB (7–4) 15–0 (0) IPRA (3–0) 15–0 (0) 15–0 (0) 15–0 (0) 15–0 (0) 15–0 (0) INTPRI00 (11–8) INTPRI00 (15–12) IPRA (15–12) IPRA (11–8) IPRA (7–4) Priority within IPR Setting Unit — — — — High Low High ↑ ⏐ ↓ Low High ↑ ⏐ ⏐ ↓ Low High ↑ ⏐ ⏐ ↓ Low — High Low Default Priority High ↑ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ⏐ ↓ Low Interrupt Source TMU3 TMU4 TMU0 TMU1 TMU2 TUNI3*2 TUNI4*2 TUNI0 TUNI1 TUNI2 TICPI2 RTC ATI PRI CUI SCI ERI RXI TXI TEI SCIF ERI RXI BRI TXI WDT REF ITI RCMI ROVI Legend: TUNI0–TUNI4: Underflow interrupts TICPI2: Input capture interrupt ATI: Alarm interrupt PRI: Periodic interrupt CUI: Carry-up interrupt ERI: Receive-error interrupt RXI: Receive-data-full interrupt TXI: Transmit-data-empty interrupt TEI: Transmit-end interrupt BRI: Break interrupt request ITI: Interval timer interrupt Rev.7.00 Oct. 10, 2008 Page 834 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) RCMI: Compare-match interrupt ROVI: Refresh counter overflow interrupt H-UDI: High-performance use debug interface GPIOI: I/O port interrupt DMTE0–DMTE7: DMAC transfer end interrupts DMAE: DMAC address error interrupt Notes: 1. Interrupt priority levels can only be changed in the SH7750S or SH7750R. In the SH7750, the initial values cannot be changed. 2. SH7750R only 19.3 19.3.1 Register Descriptions Interrupt Priority Registers A to D (IPRA–IPRD) Interrupt priority registers A to D (IPRA–IPRD) are 16-bit readable/writable registers that set priority levels from 0 to 15 for on-chip peripheral module interrupts. IPRA to IPRC are initialized to H'0000 and IPRD is to H'DA74 by a reset. They are not initialized in standby mode. IPRA to IPRC Bit: Initial value: R/W: Bit: Initial value: R/W: 15 0 R/W 7 0 R/W 14 0 R/W 6 0 R/W 13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W Rev.7.00 Oct. 10, 2008 Page 835 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) IPRD (SH7750S and SH7750R only) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 1 R/W 7 0 R/W 14 1 R/W 6 1 R/W 13 0 R/W 5 1 R/W 12 1 R/W 4 1 R/W 11 1 R/W 3 0 R/W 10 0 R/W 2 1 R/W 9 1 R/W 1 0 R/W 8 0 R/W 0 0 R/W Table 19.6 shows the relationship between the interrupt request sources and the IPRA–IPRD register bits. Table 19.6 Interrupt Request Sources and IPRA–IPRD Registers Bits Register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D* 3 15–12 TMU0 WDT GPIO IRL0 11–8 TMU1 REF* 1 7–4 TMU2 SCI SCIF IRL2 3–0 RTC Reserved*2 H-UDI IRL3 DMAC IRL1 Notes: 1. REF is the memory refresh unit in the bus state controller (BSC). See section 13, Bus State Controller (BSC), for details. 2. Reserved bits: These bits are always read as 0 and should always be written with 0. 3. SH7750S and SH7750R only As shown in table 19.6, four on-chip peripheral modules are assigned to each register. Interrupt priority levels are established by setting a value from H'F (1111) to H'0 (0000) in each of the fourbit groups: 15–12, 11–8, 7–4, and 3–0. Setting H'F designates priority level 15 (the highest level), and setting H'0 designates priority level 0 (requests are masked). Rev.7.00 Oct. 10, 2008 Page 836 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) 19.3.2 Interrupt Control Register (ICR) The interrupt control register (ICR) is a 16-bit register that sets the input signal detection mode for external interrupt input pin NMI and indicates the input signal level at the NMI pin. This register is initialized by a power-on reset or manual reset. It is not initialized in standby mode. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: Note: * 15 NMIL 0/1* R 7 IRLM 0 R/W 14 MAI 0 R/W 6 — 0 — 13 — 0 — 5 — 0 — 12 — 0 — 4 — 0 — 11 — 0 — 3 — 0 — 10 — 0 — 2 — 0 — 9 NMIB 0 R/W 1 — 0 — 8 NMIE 0 R/W 0 — 0 — 1 when NMI pin input is high, 0 when low. Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. It cannot be modified. Bit 15: NMIL 0 1 Description NMI pin input level is low NMI pin input level is high Bit 14—NMI Interrupt Mask (MAI): Specifies whether or not all interrupts are to be masked while the NMI pin input level is low, irrespective of the CPU's SR.BL bit. Bit 14: MAI 0 1 Note: * Description Interrupts enabled even while NMI pin is low Interrupts disabled while NMI pin is low* NMI interrupts are accepted in normal operation and in sleep mode. In standby mode, all interrupts are masked, and standby is not cleared, while the NMI pin is low. (Initial value) Rev.7.00 Oct. 10, 2008 Page 837 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) Bit 9—NMI Block Mode (NMIB): Specifies whether an NMI request is to be held pending or detected immediately while the SR.BL bit is set to 1. Bit 9: NMIB 0 1 Description NMI interrupt requests held pending while SR.BL bit is set to 1 (Initial value) NMI interrupt requests detected while SR.BL bit is set to 1 Notes: 1. If interrupt requests are enabled while SR.BL = 1, the previous exception information will be lost, and so must be saved beforehand. 2. This bit is cleared automatically by NMI acceptance. Bit 8—NMI Edge Select (NMIE): Specifies whether the falling or rising edge of the interrupt request signal to the NMI pin is detected. Bit 8: NMIE 0 1 Description Interrupt request detected on falling edge of NMI input Interrupt request detected on rising edge of NMI input (Initial value) Bit 7—IRL Pin Mode (IRLM): Specifies whether pins IRL3–IRL0 are to be used as levelencoded interrupt requests or as four independent interrupt requests. Bit 7: IRLM 0 1 Description IRL pins used as level-encoded interrupt requests (Initial value) IRL pins used as four independent interrupt requests (level-sense IRQ mode) Bits 13 to 10 and 6 to 0—Reserved: These bits are always read as 0, and should only be written with 0. Rev.7.00 Oct. 10, 2008 Page 838 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) 19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only) The interrupt-priority-level setting register 00 (INTPRI00) sets the priority levels (levels 15−0) for the on-chip peripheral module interrupts. INTPRI00 is a 32-bit readable/writable register. It is initialized to H'00000000 by a reset, but is not initialized when the device enters standby mode. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R R/W: R/W R/W R/W R/W R/W R/W R/W R/W Table 19.7 shows the correspondence between interrupt request sources and the bits in INTPRI00. Table 19.7 Interrupt Request Sources and the Bits of the INTPRI00 Register Bit Register 31 to 28 27 to 24 Reserved 23 to 20 Reserved 19 to 16 Reserved 15 to 12 11 to 8 7 to 4 3 to 0 Reserved Reserved Interruptpriority-level setting register 00 TMU ch4 TMU ch3 Reserved Note: As shown in the table above, levels for all eight on-chip peripheral modules are assigned in a single register. The interrupt priority level for the interrupt source that corresponds to each set of four bits is set as a value from H'F (1111) to H'0 (0000). The setting H'F selects interrupt priority level 15, which is the highest, and H'0 selects level 0, which means that interrupt requests from that source are masked. Reserved bits are always read as 0. When writing, only 0s should be written to these bits. Rev.7.00 Oct. 10, 2008 Page 839 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) 19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only) The interrupt source register 00 (INTREQ00) indicates the origin of the interrupt request that has been sent to the INTC. The states of the bits in this register is not affected by masking of the corresponding interrupts by the settings in the INTPRI00 or INTMSK00 register. INTREQ00 is a 32-bit read-only register. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 0—Interrupt Request: Each of the non-reserved bits in this register indicates that there is an interrupt request relevant to that bit. For the correspondence between the bits and interrupt sources, see section 19.3.7, Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only). Bits 31 to 0 0 1 Description There is no interrupt request that corresponds to this bit There is an interrupt request that corresponds to this bit. Rev.7.00 Oct. 10, 2008 Page 840 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) 19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only) The interrupt mask register 00 (INTMSK00) sets the masking of individual interrupt requests. INTMSK00 is a 32-bit register. It is initialized to H'000003FF by a reset, and retains this value in standby mode. To cancel masking of an interrupt, write a 1 to the corresponding bit in the INTMSKCLR00 register. Note that writing a 0 to a bit in INTMSK00 does not change its value. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 31 to 0—Interrupt Mask: Sets the masking of the interrupt request that corresponds to the given bit. For the correspondence between bits and interrupt sources, see section 19.3.7, Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only). Bits 31 to 0 0 1 Description Interrupt requests from the source that corresponds to this bit are accepted Interrupt requests from the source that corresponds to this bit are masked (Initial value) Rev.7.00 Oct. 10, 2008 Page 841 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) 19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only) The interrupt mask clear register 00 (INTMSKCLR00) clears the masking of individual interrupt requests. INTMSKCLR00 is a 32-bit write-only register. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: — W — W — W — W — W — W — W — W — W — W — W — W — W — W — W — W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: — W — W — W — W — W — W — W — W — W — W — W — W — W — W — W — W Bit 31 to 0⎯Interrupt Mask Clear: Each bit selects whether or not to clear the masking of the interrupt source that corresponds to that bit. For the correspondence between the bits and interrupt sources, see section 19.3.7, Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only). Bits 31 to 0 0 1 Description Masking of interrupt requests from the source that corresponds to the bit is not changed Masking of interrupt requests from the source that corresponds to the bit is cleared 19.3.7 Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only) The relationship between the bits in these registers and interrupt sources is as shown below. Table 19.8 Bit Assignments Bit number 31 to 10, 7 to 0 9 8 Module Reserved TMU TMU Interrupt Reserved TUNI4 TUNI3 Rev.7.00 Oct. 10, 2008 Page 842 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) 19.4 19.4.1 INTC Operation Interrupt Operation Sequence The sequence of operations when an interrupt is generated is described below. Figure 19.3 shows a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, according to the priority levels set in interrupt priority registers A to C (IPRA–IPRC). Lowerpriority interrupts are held pending. If two of these interrupts have the same priority level, or if multiple interrupts occur within a single module, the interrupt with the highest priority according to table 19.5, Interrupt Exception Handling Sources and Priority Order, is selected. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (IMASK) in the status register (SR) of the CPU. If the request priority level is higher that the level in bits IMASK, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. The CPU accepts an interrupt at a break between instructions. 5. The interrupt source code is set in the interrupt event register (INTEVT). 6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. The R15 contents at this time are saved in SGR. 7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1. 8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (VBR) and H'00000600). The interrupt handler may branch with the INTEVT register value as its offset in order to identify the interrupt source. This enables it to branch to the handling routine for the particular interrupt source. Notes: 1. The interrupt mask bits (IMASK) in the status register (SR) are not changed by acceptance of an interrupt in this LSI. 2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, then wait for the interval shown in table 19.9 (Time for priority decision and SR mask bit comparison) before clearing the BL bit or executing an RTE instruction. 3. For some interrupt sources, their interrupt masks (INTMSK00) must e cleared using the INTMSKCLR00 register. Rev.7.00 Oct. 10, 2008 Page 843 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) Program execution state Interrupt generated? Yes (BL bit in SR = 0) or (sleep or standby mode)? Yes NMI? Yes No No NMIB in ICR = 1 and NMI? No Yes No Level 15 interrupt? Yes Yes IMASK* = level 14 or lower? No Set interrupt source in INTEVT Save SR to SSR; save PC to SPC Set BL, MD, RB bits in SR to 1 Branch to exception handler Yes No Level 14 interrupt? Yes IMASK = level 13 or lower? No Yes No Level 1 interrupt? Yes IMASK = level 0? No No Note: * IMASK: Interrupt mask bits in status register (SR) Figure 19.3 Interrupt Operation Flowchart Rev.7.00 Oct. 10, 2008 Page 844 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) 19.4.2 Multiple Interrupts When handling multiple interrupts, interrupt handling should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in the INTEVT register. The code in INTEVT can be used as a branch-offset for branching to the specific handler. 2. Clear the interrupt source in the corresponding interrupt handler. 3. Save SPC and SSR to the stack. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR. 5. Handle the interrupt. 6. Set the BL bit in SR to 1. 7. Restore SSR and SPC from memory. 8. Execute the RTE instruction. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4. This enables the interrupt response time to be shortened for urgent processing. 19.4.3 Interrupt Masking with MAI Bit By setting the MAI bit to 1 in the ICR register, it is possible to mask interrupts while the NMI pin is low, irrespective of the BL and IMASK bits in the SR register. • In normal operation and sleep mode All interrupts are masked while the NMI pin is low. However, an NMI interrupt only is generated by a transition at the NMI pin. • In standby mode All interrupts are masked while the NMI pin is low, and an NMI interrupt is not generated by a transition at the NMI pin. Therefore, standby cannot be cleared by an NMI interrupt while the MAI bit is set to 1. Rev.7.00 Oct. 10, 2008 Page 845 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) 19.5 Interrupt Response Time The time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception service routine is started (the interrupt response time) is shown in table 19.9. Table 19.9 Interrupt Response Time Number of States Item Time for priority decision and SR mask bit comparison* Wait time until end of sequence being executed by CPU Time from interrupt exception handling (save of SR and PC) until fetch of first instruction of exception handler is started Response time Total Minimum case Maximum case NMI 1Icyc + 4Bcyc S – 1 (≥ 0) × Icyc 4 × Icyc RL 1Icyc + 7Bcyc S – 1 (≥ 0) × Icyc 4 × Icyc Peripheral Modules 1Icyc + 2Bcyc S – 1 (≥ 0) × Icyc 4 × Icyc Notes 5Icyc + 4Bcyc + (S – 1)Icyc 13Icyc 36 + S Icyc 5Icyc + 7Bcyc + (S – 1)Icyc 19Icyc 60 + S Icyc 5Icyc + 2Bcyc + (S – 1)Icyc 9Icyc 20 + S Icyc When Icyc: Bcyc = 2:1 When Icyc: Bcyc = 8:1 Legend: Icyc: One cycle of internal clock supplied to CPU, etc. Bcyc: One CKIO cycle S: Latency of instruction Note: * In the SH7750 and SH7750S including the case where the mask bit (IMASK) in SR is changed, and a new interrupt is generated. Rev.7.00 Oct. 10, 2008 Page 846 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) 19.6 19.6.1 Usage Notes NMI Interrupts (SH7750 and SH7750S Only) When multiple NMI interrupts are input to the NMI pin within a set period of time (which is dependent on the internal state of the CPU and the external bus state), subsequent interrupts may not be accepted. Note that this problem does not occur when sufficient time*1 is provided between NMI interrupt inputs or with non-NMI interrupts such as IRL interrupts. Workarounds: Methods 1, 2, or 3 below may be used to avoid the above problem. 1. Allow sufficient time between NMI interrupt inputs, as described in note 1, below. Note that it may not be possible to assure the above interval between NMI interrupt inputs if hazard is input to NMI, and that this may cause the device to malfunction. Design the external circuits so that no hazard is input via NMI.*2 2. Do not use NMI interrupts. Use IRL interrupts instead. 3. Workaround using software The above problem can be avoided by inserting the following lines of code*3*4 into the NMI exception handling routine. Notes: 1. If SR.BL is cleared to 0 so that one or more instructions may be executed between the handling of two NMI interrupts. 2. When changing the level of the NMI input, ensure that the high and low durations are at least 5 CKIO cycles. Also ensure that no noise pulses occur before or after level changes. 3. If the NMI exception handling routine contains code that changes the value of the SR.BL bit, the code listed below should be inserted before the point at which the change is made. 4. Registers R0 to R3 in the code sample can be changed to any general register. Also, the necessary register save and restore instructions should be inserted before and after the code listed below, as appropriate. Rev.7.00 Oct. 10, 2008 Page 847 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; R0 : tmp ;; R1 : Original SR ;; R2 : Original ICR ;; R3 : ICR Address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; NMIH: ; (1) Set SR.IMASK = H'F stc mov or ldc SR, R1 ; R1,R0 #H'F0,R0 R0, SR Store SR ; (2) Reverse ICR.NMIE mov.l mov.w mov.w xor mov.w bra nop .pool .align 4 NMIH2: ; mov.w mov.w stc ldc ldc ldc ldc ldc ldc ldc ldc @R3, R0 R2, @R3 SR, R0 R0, SR R0, SR R0, SR R0, SR R0, SR R0, SR R0, SR R0, SR ; ; dummy read Write ICR.NMIE #ICR, R3 @R3, R2 ; Store ICR #H'0100, R0 R2, R0 R0, @R3 NMIH1 ; Write ICR.NMIE inverted (dummy) Rev.7.00 Oct. 10, 2008 Page 848 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) ldc bra nop NMIH1: bra nop NMIH3: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; NMIH2 R1, SR ; NMIH3 Restore SR Rev.7.00 Oct. 10, 2008 Page 849 of 1074 REJ09B0366-0700 Section 19 Interrupt Controller (INTC) Rev.7.00 Oct. 10, 2008 Page 850 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) Section 20 User Break Controller (UBC) 20.1 Overview The user break controller (UBC) provides functions that simplify program debugging. When break conditions are set in the UBC, a user break interrupt is generated according to the contents of the bus cycle generated by the CPU. This function makes it easy to design an effective self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. 20.1.1 Features The UBC has the following features. • Two break channels (A and B) User break interrupts can be generated on independent conditions for channels A and B, or on sequential conditions (sequential break setting: channel A → channel B). • The following can be set as break compare conditions: ⎯ Address (selection of 32-bit virtual address and ASID for comparison): Address: All bits compared/lower 10 bits masked/lower 12 bits masked/lower 16 bits masked/lower 20 bits masked/all bits masked ASID: All bits compared/all bits masked ⎯ Data (channel B only, 32-bit mask capability) ⎯ Bus cycle: Instruction access/operand access ⎯ Read/write ⎯ Operand size: Byte/word/longword/quadword • An instruction access cycle break can be effected before or after the instruction is executed. Rev.7.00 Oct. 10, 2008 Page 851 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) 20.1.2 Block Diagram Figure 20.1 shows a block diagram of the UBC. Access control Address bus Channel A Access comparator BBRA Data bus BARA Address comparator BASRA BAMRA Channel B Access comparator BBRB BARB Address comparator BASRB BAMRB Data comparator BDRB BDMRB Legend: BBRA: BARA: BASRA: BAMRA: BBRB: BARB: BASRB: BAMRB: BDRB: BDMRB: BRCR: Break bus cycle register A Break address register A Break ASID register A Break address mask register A Break bus cycle register B Break address register B Break ASID register B Break address mask register B Break data register B Break data mask register B Break control register Control BRCR User break trap request Figure 20.1 Block Diagram of User Break Controller Rev.7.00 Oct. 10, 2008 Page 852 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) Table 20.1 shows the UBC registers. Table 20.1 UBC Registers Name Break address register A Break address mask register A Break bus cycle register A Break ASID register A Break address register B Break address mask register B Break bus cycle register B Break ASID register B Break data register B Break data mask register B Break control register Note: * Abbreviation BARA BAMRA R/W R/W R/W Initial Value Undefined Undefined P4 Address H'FF200000 H'FF200004 Area 7 Address H'1F200000 H'1F200004 Access Size 32 8 BBRA BASRA BARB BAMRB R/W R/W R/W R/W H'0000 Undefined Undefined Undefined H'FF200008 H'FF000014 H'FF20000C H'FF200010 H'1F200008 H'1F000014 H'1F20000C H'1F200010 16 8 32 8 BBRB BASRB BDRB BDMRB BRCR R/W R/W R/W R/W R/W H'0000 Undefined Undefined Undefined H'0000* H'FF200014 H'FF000018 H'FF200018 H'FF20001C H'FF200020 H'1F200014 H'1F000018 H'1F200018 H'1F20001C H'1F200020 16 8 32 32 16 Some bits are not initialized. See section 20.2.12, Break Control Register (BRCR), for details. Rev.7.00 Oct. 10, 2008 Page 853 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) 20.2 20.2.1 Register Descriptions Access to UBC Control Registers The access size must be the same as the control register size. If the sizes are different, a write will not be effected in a UBC register write operation, and a read operation will return an undefined value. UBC control register contents cannot be transferred to a floating-point register using a floating-point memory load instruction. When a UBC control register is updated, use either of the following methods to make the updated value valid: 1. Execute an RTE instruction after the memory store instruction that updated the register. The updated value will be valid from the RTE instruction jump destination onward. 2. Execute instructions requiring 5 states for execution after the memory store instruction that updated the register. As the CPU executes two instructions in parallel and a minimum of 0.5 state is required for execution of one instruction, 11 instructions must be inserted. The updated value will be valid from the 6th state onward. Rev.7.00 Oct. 10, 2008 Page 854 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) 20.2.2 Break Address Register A (BARA) Bit: 31 BAA31 Initial value: R/W: Bit: * R/W 23 BAA23 Initial value: R/W: Bit: * R/W 15 BAA15 Initial value: R/W: Bit: * R/W 7 BAA7 Initial value: R/W: * R/W 30 BAA30 * R/W 22 BAA22 * R/W 14 BAA14 * R/W 6 BAA6 * R/W 29 BAA29 * R/W 21 BAA21 * R/W 13 BAA13 * R/W 5 BAA5 * R/W 28 BAA28 * R/W 20 BAA20 * R/W 12 BAA12 * R/W 4 BAA4 * R/W 27 BAA27 * R/W 19 BAA19 * R/W 11 BAA11 * R/W 3 BAA3 * R/W 26 BAA26 * R/W 18 BAA18 * R/W 10 BAA10 * R/W 2 BAA2 * R/W 25 BAA25 * R/W 17 BAA17 * R/W 9 BAA9 * R/W 1 BAA1 * R/W 24 BAA24 * R/W 16 BAA16 * R/W 8 BAA8 * R/W 0 BAA0 * R/W Legend: *: Undefined Break address register A (BARA) is a 32-bit readable/writable register that specifies the virtual address used in the channel A break conditions. BARA is not initialized by a power-on reset or manual reset. Bits 31 to 0—Break Address A31 to A0 (BAA31–BAA0): These bits hold the virtual address (bits 31–0) used in the channel A break conditions. Rev.7.00 Oct. 10, 2008 Page 855 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) 20.2.3 Break ASID Register A (BASRA) Bit: 7 BASA7 Initial value: R/W: * R/W 6 BASA6 * R/W 5 BASA5 * R/W 4 BASA4 * R/W 3 BASA3 * R/W 2 BASA2 * R/W 1 BASA1 * R/W 0 BASA0 * R/W Legend: *: Undefined Break ASID register A (BASRA) is an 8-bit readable/writable register that specifies the ASID used in the channel A break conditions. BASRA is not initialized by a power-on reset or manual reset. Bits 7 to 0—Break ASID A7 to A0 (BASA7–BASA0): These bits hold the ASID (bits 7–0) used in the channel A break conditions. 20.2.4 Break Address Mask Register A (BAMRA) Bit: 7 — Initial value: R/W: Legend: *: Undefined 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 2 1 0 BAMA0 * R/W BAMA2 BASMA BAMA1 * R/W * R/W * R/W Break address mask register A (BAMRA) is an 8-bit readable/writable register that specifies which bits are to be masked in the break ASID set in BASRA and the break address set in BARA. BAMRA is not initialized by a power-on reset or manual reset. Bits 7 to 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 2—Break ASID Mask A (BASMA): Specifies whether all bits of the channel A break ASID7 to ASID0 (BASA7–BASA0) are to be masked. Bit 2: BASMA 0 1 Description All BASRA bits are included in break conditions No BASRA bits are included in break conditions Rev.7.00 Oct. 10, 2008 Page 856 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) Bits 3, 1, and 0—Break Address Mask A2 to A0 (BAMA2–BAMA0): These bits specify which bits of the channel A break address 31 to 0 (BAA31–BAA0) set in BARA are to be masked. Bit 3: BAMA2 0 Bit 1: BAMA1 0 Bit 0: BAMA0 0 1 1 0 1 1 0 0 1 1 Legend: *: Don't care * Description All BARA bits are included in break conditions Lower 10 bits of BARA are masked, and not included in break conditions Lower 12 bits of BARA are masked, and not included in break conditions All BARA bits are masked, and not included in break conditions Lower 16 bits of BARA are masked, and not included in break conditions Lower 20 bits of BARA are masked, and not included in break conditions Reserved (cannot be set) 20.2.5 Break Bus Cycle Register A (BBRA) Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 SZA2 0 R/W 13 — 0 R 5 IDA1 0 R/W 12 — 0 R 4 IDA0 0 R/W 11 — 0 R 3 RWA1 0 R/W 10 — 0 R 2 RWA0 0 R/W 9 — 0 R 1 SZA1 0 R/W 8 — 0 R 0 SZA0 0 R/W Break bus cycle register A (BBRA) is a 16-bit readable/writable register that sets three conditions—(1) instruction access/operand access, (2) read/write, and (3) operand size—from among the channel A break conditions. BBRA is initialized to H'0000 by a power-on reset. It retains its value in standby mode. Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0. Rev.7.00 Oct. 10, 2008 Page 857 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) Bits 5 and 4—Instruction Access/Operand Access Select A (IDA1, IDA0): These bits specify whether an instruction access cycle or an operand access cycle is used as the bus cycle in the channel A break conditions. Bit 5: IDA1 0 Bit 4: IDA0 0 1 1 0 1 Description Condition comparison is not performed (Initial value) Instruction access cycle is used as break condition Operand access cycle is used as break condition Instruction access cycle or operand access cycle is used as break condition Bits 3 and 2—Read/Write Select A (RWA1, RWA0): These bits specify whether a read cycle or write cycle is used as the bus cycle in the channel A break conditions. Bit 3: RWA1 0 Bit 2: RWA0 0 1 1 0 1 Description Condition comparison is not performed Read cycle is used as break condition Write cycle is used as break condition Read cycle or write cycle is used as break condition (Initial value) Bits 6, 1, and 0—Operand Size Select A (SZA2–SZA0): These bits select the operand size of the bus cycle used as a channel A break condition. Bit 6: SZA2 0 Bit 1: SZA1 0 Bit 0: SZA0 0 1 1 0 1 1 0 0 1 1 Legend: *: Don't care * Description Operand size is not included in break conditions (Initial value) Byte access is used as break condition Word access is used as break condition Longword access is used as break condition Quadword access is used as break condition Reserved (cannot be set) Reserved (cannot be set) Rev.7.00 Oct. 10, 2008 Page 858 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) 20.2.6 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 20.2.7 Break ASID Register B (BASRB) BASRB is the channel B break ASID register. The bit configuration is the same as for BASRA. 20.2.8 Break Address Mask Register B (BAMRB) BAMRB is the channel B break address mask register. The bit configuration is the same as for BAMRA. 20.2.9 Break Data Register B (BDRB) Bit: 31 BDB31 Initial value: R/W: Bit: * R/W 23 BDB23 Initial value: R/W: Bit: * R/W 15 BDB15 Initial value: R/W: Bit: * R/W 7 BDB7 Initial value: R/W: Legend: *: Undefined * R/W 30 BDB30 * R/W 22 BDB22 * R/W 14 BDB14 * R/W 6 BDB6 * R/W 29 BDB29 * R/W 21 BDB21 * R/W 13 BDB13 * R/W 5 BDB5 * R/W 28 BDB28 * R/W 20 BDB20 * R/W 12 BDB12 * R/W 4 BDB4 * R/W 27 BDB27 * R/W 19 BDB19 * R/W 11 BDB11 * R/W 3 BDB3 * R/W 26 BDB26 * R/W 18 BDB18 * R/W 10 BDB10 * R/W 2 BDB2 * R/W 25 BDB25 * R/W 17 BDB17 * R/W 9 BDB9 * R/W 1 BDB1 * R/W 24 BDB24 * R/W 16 BDB16 * R/W 8 BDB8 * R/W 0 BDB0 * R/W Rev.7.00 Oct. 10, 2008 Page 859 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) Break data register B (BDRB) is a 32-bit readable/writable register that specifies the data (bits 31– 0) to be used in the channel B break conditions. BDRB is not initialized by a power-on reset or manual reset. Bits 31 to 0—Break Data B31 to B0 (BDB31–BDB0): These bits hold the data (bits 31–0) to be used in the channel B break conditions. 20.2.10 Break Data Mask Register B (BDMRB) Bit: 31 30 29 28 27 26 25 24 BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 Initial value: R/W: Bit: * R/W 23 * R/W 22 * R/W 21 * R/W 20 * R/W 19 * R/W 18 * R/W 17 * R/W 16 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 Initial value: R/W: Bit: * R/W 15 * R/W 14 * R/W 13 * R/W 12 * R/W 11 * R/W 10 * R/W 9 * R/W 8 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8 Initial value: R/W: Bit: * R/W 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 Initial value: R/W: Legend: *: Undefined * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W Break data mask register B (BDMRB) is a 32-bit readable/writable register that specifies which bits of the break data set in BDRB are to be masked. BDMRB is not initialized by a power-on reset or manual reset. Rev.7.00 Oct. 10, 2008 Page 860 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) Bits 31 to 0—Break Data Mask B31 to B0 (BDMB31–BDMB0): These bits specify whether the corresponding bit of the channel B break data B31 to B0 (BDB31–BDB0) set in BDRB is to be masked. Bit 31–0: BDMBn 0 1 Description Channel B break data bit BDBn is included in break conditions Channel B break data bit BDBn is masked, and not included in break conditions n = 31 to 0 Note: When the data bus value is included in the break conditions, the operand size should be specified. When byte size is specified, set the same data in bits 15–8 and 7–0 of BDRB and BDMRB. 20.2.11 Break Bus Cycle Register B (BBRB) BBRB is the channel B bus break register. The bit configuration is the same as for BBRA. 20.2.12 Break Control Register (BRCR) Bit: 15 CMFA Initial value: R/W: Bit: 0 R/W 7 DBEB Initial value: R/W: Legend: *: Undefined * R/W 14 CMFB 0 R/W 6 PCBB * R/W 13 — 0 R 5 — 0 R 12 — 0 R 4 — 0 R 11 — 0 R 3 SEQ * R/W 10 PCBA * R/W 2 — 0 R 9 — 0 R 1 — 0 R 8 — 0 R 0 UBDE 0 R/W The break control register (BRCR) is a 16-bit readable/writable register that specifies (1) whether channels A and B are to be used as two independent channels or in a sequential condition, (2) whether the break is to be effected before or after instruction execution, (3) whether the BDRB register is to be included in the channel B break conditions, and (4) whether the user break debug function is to be used. BRCR also contains condition match flags. The CMFA, CMFB, and UBDE bits in BRCR are initialized to 0 by a power-on reset, but retain their value in standby mode. The Rev.7.00 Oct. 10, 2008 Page 861 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) value of the PCBA, DBEB, PCBB, and SEQ bits is undefined after a power-on reset or manual reset, so these bits should be initialized by software as necessary. Bit 15—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write.) Bit 15: CMFA 0 1 Description Channel A break condition is not matched Channel A break condition match has occurred (Initial value) Bit 14—Condition Match Flag B (CMFB): Set to 1 when a break condition set for channel B is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write.) Bit 14: CMFB 0 1 Description Channel B break condition is not matched Channel B break condition match has occurred (Initial value) Bits 13 to 11—Reserved: These bits are always read as 0, and should only be written with 0. Bit 10—Instruction Access Break Select A (PCBA): Specifies whether a channel A instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset. Bit 10: PCBA 0 1 Description Channel A PC break is effected before instruction execution Channel A PC break is effected after instruction execution Bits 9 and 8—Reserved: These bits are always read as 0, and should only be written with 0. Rev.7.00 Oct. 10, 2008 Page 862 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) Bit 7—Data Break Enable B (DBEB): Specifies whether the data bus condition is to be included in the channel B break conditions. This bit is not initialized by a power-on reset or manual reset. Bit 7: DBEB 0 1 Description Data bus condition is not included in channel B conditions Data bus condition is included in channel B conditions Note: When the data bus is included in the break conditions, bits IDB1–0 in break bus cycle register B (BBRB) should be set to 10 or 11. Bit 6—PC Break Select B (PCBB): Specifies whether a channel B instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset. Bit 6: PCBB 0 1 Description Channel B PC break is effected before instruction execution Channel B PC break is effected after instruction execution Bits 5 and 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Sequence Condition Select (SEQ): Specifies whether the conditions for channels A and B are to be independent or sequential. This bit is not initialized by a power-on reset or manual reset. Bit 3: SEQ 0 1 Description Channel A and B comparisons are performed as independent conditions Channel A and B comparisons are performed as sequential conditions (channel A → channel B) Bits 2 and 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 0—User Break Debug Enable (UBDE): Specifies whether the user break debug function (see section 20.4, User Break Debug Support Function) is to be used. Bit 0: UBDE 0 1 Description User break debug function is not used User break debug function is used (Initial value) Rev.7.00 Oct. 10, 2008 Page 863 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) 20.3 20.3.1 Operation Explanation of Terms Relating to Accesses An instruction access is an access that obtains an instruction. An operand access is any memory access for the purpose of instruction execution. For example, the access to address PC+disp×2+4 in the instruction MOV.W @(disp,PC), Rn (an access very close to the program counter) is an operand access. The fetching of an instruction from the branch destination when a branch instruction is executed is also an instruction access. As the term “data” is used to distinguish data from an address, the term “operand access” is used in this section. In this LSI, all operand accesses are treated as either read accesses or write accesses. The following instructions require special attention: • PREF, OCBP, and OCBWB instructions: Treated as read accesses. • MOVCA.L and OCBI instructions: Treated as write accesses. • TAS.B instruction: Treated as one read access and one write access. The operand accesses for the PREF, OCBP, OCBWB, and OCBI instructions are accesses with no access data. This LSI handles all operand accesses as having a data size. The data size can be byte, word, longword, or quadword. The operand data size for the PREF, OCBP, OCBWB, MOVCA.L, and OCBI instructions is treated as longword. 20.3.2 Explanation of Terms Relating to Instruction Intervals In this section, “1 (2, 3, ...) instruction(s) after...”, as a measure of the distance between two instructions, is defined as follows. A branch is counted as an interval of two instructions. • Example of sequence of instructions with no branch: 100 Instruction A (0 instructions after instruction A) 102 Instruction B (1 instruction after instruction A) 104 Instruction C (2 instructions after instruction A) 106 Instruction D (3 instructions after instruction A) Rev.7.00 Oct. 10, 2008 Page 864 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) • Example of sequence of instructions with a branch (however, the example of a sequence of instructions with no branch should be applied when the branch destination of a delayed branch instruction is the instruction itself + 4): 100 Instruction A: BT/S L200 (0 instructions after instruction A) 102 Instruction B (1 instruction after instruction A, 0 instructions after instruction B) L200 200 Instruction C (3 instructions after instruction A, 2 instructions after instruction B) 202 Instruction D (4 instructions after instruction A, 3 instructions after instruction B) 20.3.3 User Break Operation Sequence The sequence of operations from setting of break conditions to user break exception handling is described below. 1. Specify pre- or post-execution breaking in the case of an instruction access, inclusion or exclusion of the data bus value in the break conditions in the case of an operand access, and use of independent or sequential channel A and B break conditions, in the break control register (BRCR). Set the break addresses in the break address registers for each channel (BARA, BARB), the ASIDs corresponding to the break space in the break ASID registers (BASRA, BASRB), and the address and ASID masking methods in the break address mask registers (BAMRA, BAMRB). If the data bus value is to be included in the break conditions, also set the break data in the break data register (BDRB) and the data mask in the break data mask register (BDMRB). 2. Set the break bus conditions in the break bus cycle registers (BBRA, BBRB). If even one of the BBRA/BBRB instruction access/operand access select (ID bit) and read/write select groups (RW bit) is set to 00, a user break interrupt will not be generated on the corresponding channel. Make the BBRA and BBRB settings after all other break-related register settings have been completed. If breaks are enabled with BBRA/BBRB while the break address, data, or mask register, or the break control register is in the initial state after a reset, a break may be generated inadvertently. 3. The operation when a break condition is satisfied depends on the BL bit (in the CPU's SR register). When the BL bit is 0, exception handling is started and the condition match flag (CMFA/CMFB) for the respective channel is set for the matched condition. When the BL bit is 1, the condition match flag (CMFA/CMFB) for the respective channel is set for the matched condition but exception handling is not started. The condition match flags (CMFA, CMFB) are set by a branch condition match, but are not automatically cleared. Therefore, a memory store instruction should be used on the BRCR Rev.7.00 Oct. 10, 2008 Page 865 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) register to clear the flags to 0. See section 20.3.6, Condition Match Flag Setting, for the exact setting conditions for the condition match flags. 4. When sequential condition mode has been selected, and the channel B condition is matched after the channel A condition has been matched, a break is effected at the instruction at which the channel B condition was matched. See section 20.3.8, Contiguous A and B Settings for Sequential Conditions, for the operation when the channel A condition match and channel B condition match occur close together. With sequential conditions, only the channel B condition match flag is set. When sequential condition mode has been selected, if it is wished to clear the channel A match when the channel A condition has been matched but the channel B condition has not yet been matched, this can be done by writing 0 to the SEQ bit in the BRCR register. 20.3.4 Instruction Access Cycle Break 1. When an instruction access/read/word setting is made in the break bus cycle register (BBRA/BBRB), an instruction access cycle can be used as a break condition. In this case, breaking before or after execution of the relevant instruction can be selected with the PCBA/PCBB bit in the break control register (BRCR). When an instruction access cycle is used as a break condition, clear the LSB of the break address registers (BARA, BARB) to 0. A break will not be generated if this bit is set to 1. 2. When a pre-execution break is specified, the break is effected when it is confirmed that the instruction is to be fetched and executed. Therefore, an overrun-fetched instruction (an instruction that is fetched but not executed when a branch or exception occurs) cannot be used in a break. However, if a TLB miss or TLB protection violation exception occurs at the time of the fetch of an instruction subject to a break, the break exception handling is carried out first. The instruction TLB exception handling is performed when the instruction is re-executed (see section 5.4, Exception Types and Priorities). Also, since a delayed branch instruction and the delay slot instruction are executed as a single instruction, if a pre-execution break is specified for a delay slot instruction, the break will be effected before execution of the delayed branch instruction. However, a pre-execution break cannot be specified for the delay slot instruction for an RTE instruction. 3. With a pre-execution break, the instruction set as a break condition is executed, then a break interrupt is generated before the next instruction is executed. When a post-execution break is set for a delayed branch instruction, the delay slot is executed and the break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made). Rev.7.00 Oct. 10, 2008 Page 866 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) 4. When an instruction access cycle is set for channel B, break data register B (BDRB) is ignored in judging whether there is an instruction access match. Therefore, a break condition specified by the DBEB bit in BRCR is not executed. 20.3.5 Operand Access Cycle Break 1. In the case of an operand access cycle break, the bits included in address bus comparison vary as shown below according to the data size specification in the break bus cycle register (BBRA/BBRB). Data Size Quadword (100) Longword (011) Word (010) Byte (001) Not included in condition (000) Address Bits Compared Address bits A31–A3 Address bits A31–A2 Address bits A31–A1 Address bits A31–A0 In quadword access, address bits A31–A3 In longword access, address bits A31–A2 In word access, address bits A31–A1 In byte access, address bits A31–A0 2. When data value is included in break conditions in channel B When a data value is included in the break conditions, set the DBEB bit in the break control register (BRCR) to 1. In this case, break data register B (BDRB) and break data mask register B (BDMRB) settings are necessary in addition to the address condition. A user break interrupt is generated when all three conditions—address, ASID, and data—are matched. When a quadword access occurs, the 64-bit access data is divided into an upper 32 bits and lower 32 bits, and interpreted as two 32-bit data units. A break is generated if either of the 32-bit data units satisfies the data match condition. Set the IDB1–0 bits in break bus cycle register B (BBRB) to 10 or 11. When byte data is specified, the same data should be set in the two bytes comprising bits 15–8 and bits 7–0 in break data register B (BDRB) and break data mask register B (BDMRB). When word or byte is set, bits 31–16 of BDRB and BDMRB are ignored. 3. When the DBEB bit in the break control register (BRCR) is set to 1, a break is not generated by an operand access with no access data (an operand access in a PREF, OCBP, OCBWB, or OCBI instruction). Rev.7.00 Oct. 10, 2008 Page 867 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) 20.3.6 Condition Match Flag Setting 1. Instruction access with post-execution condition, or operand access The flag is set when execution of the instruction that causes the break is completed. As an exception to this, however, in the case of an instruction with more than one operand access the flag may be set on detection of the match condition alone, without waiting for execution of the instruction to be completed. Example 1: 100 BT L200 (branch performed) 102 Instruction (operand access break on channel A) → flag not set Example 2: 110 FADD (FPU exception) 112 Instruction (operand access break on channel A) → flag not set 2. Instruction access with pre-execution condition The flag is set when the break match condition is detected. Example 1: 110 Instruction (pre-execution break on channel A) → flag set 112 Instruction (pre-execution break on channel B) → flag not set Example 2: 110 Instruction (pre-execution break on channel B, instruction access TLB miss) → flag set 20.3.7 Program Counter (PC) Value Saved 1. When instruction access (pre-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction at which the break condition match occurred. In this case, a user break interrupt is generated and the fetched instruction is not executed. 2. When instruction access (post-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction to be executed after the instruction at which the break condition match occurred. In this case, the fetched instruction is executed, and a user break interrupt is generated before execution of the next instruction. 3. When an instruction access (post-execution) break condition is set for a delayed branch instruction, the delay slot instruction is executed and a user break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two Rev.7.00 Oct. 10, 2008 Page 868 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) instructions ahead of the branch instruction (when the branch is not made). In this case, the PC value saved to SPC is the address of the branch destination (when the branch is made) or the instruction following the delay slot instruction (when the branch is not made). 4. When operand access (address only) is set as a break condition, the address of the instruction to be executed after the instruction at which the condition match occurred is saved to SPC. The instruction at which the condition match occurred is executed, and a user break interrupt occurs before the following instruction is executed. 5. When operand access (address + data) is set as a break condition, execution of the instruction at which the condition match occurred is completed. A user break interrupt is generated before execution of instructions from one instruction later to four instructions later. It is not possible to specify at which instruction, from one later to four later, the interrupt will be generated. The start address of the instruction after the instruction for which execution is completed at the point at which user break interrupt handling is started is saved to SPC. If an instruction between one instruction later and four instructions later causes another exception, control is performed as follows. Designating the exception caused by the break as exception 1, and the exception caused by an instruction between one instruction later and four instructions later as exception 2, the fact that memory updating and register updating that essentially cannot be performed by exception 2 cannot be performed is guaranteed irrespective of the existence of exception 1. The program counter value saved is the address of the first instruction for which execution is suppressed. Whether exception 1 or exception 2 is used for the exception jump destination and the value written to the exception register (EXPEVT/INTEVT) is not guaranteed. However, if exception 2 is from a source not synchronized with an instruction (external interrupt or peripheral module interrupt), exception 1 is used for the exception jump destination and the value written to the exception register (EXPEVT/INTEVT). 20.3.8 Contiguous A and B Settings for Sequential Conditions When channel A match and channel B match timings are close together, a sequential break may not be guaranteed. Rules relating to the guaranteed range are given below. 1. Instruction access matches on both channel A and channel B Instruction B is 0 instructions after instruction A Instruction B is 1 instruction after instruction A Instruction B is 2 or more instructions after instruction A Equivalent to setting the same address. Do not use this setting. Sequential operation is not guaranteed. Sequential operation is guaranteed. Rev.7.00 Oct. 10, 2008 Page 869 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) 2. Instruction access match on channel A, operand access match on channel B Instruction B is 0 or 1 instruction after instruction A Instruction B is 2 or more instructions after instruction A Sequential operation is not guaranteed. Sequential operation is guaranteed. 3. Operand access match on channel A, instruction access match on channel B Instruction B is 0 to 3 instructions after instruction A Instruction B is 4 or more instructions after instruction A Sequential operation is not guaranteed. Sequential operation is guaranteed. 4. Operand access matches on both channel A and channel B Do not make a setting such that a single operand access will match the break conditions of both channel A and channel B. There are no other restrictions. For example, sequential operation is guaranteed even if two accesses within a single instruction match channel A and channel B conditions in turn. 20.3.9 Usage Notes 1. Do not execute a post-execution instruction access break for the SLEEP instruction. 2. Do not make an operand access break setting between 1 and 3 instructions before a SLEEP instruction. 3. The value of the BL bit referenced in a user break exception depends on the break setting, as follows. a. Pre-execution instruction access break: The BL bit value before the executed instruction is referenced. b. Post-execution instruction access break: The OR of the BL bit values before and after the executed instruction is referenced. c. Operand access break (address/data): The BL bit value after the executed instruction is referenced. d. In the case of an instruction that modifies the BL bit Rev.7.00 Oct. 10, 2008 Page 870 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) PreExecution Instruction Access A M A M PostExecution Instruction Access A M M M PreExecution Instruction Access A M A M PostExecution Instruction Access A M M M SL.BL 0→0 1→0 0→1 1→1 Legend: A: Accepted M: Masked Operand Access (Address/Data) A A M M e. In the case of an RTE delay slot The BL bit value before execution of a delay slot instruction is the same as the BL bit value before execution of an RTE instruction. The BL bit value after execution of a delay slot instruction is the same as the first BL bit value for the first instruction executed on returning by means of an RTE instruction (the same as the value of the BL bit in SSR before execution of the RTE instruction). f. If an interrupt or exception is accepted with the BL bit cleared to 0, the value of the BL bit before execution of the first instruction of the exception handling routine is 1. 4. If channels A and B both match independently at virtually the same time, and, as a result, the SPC value is the same for both user break interrupts, only one user break interrupt is generated, but both the CMFA bit and the CMFB bit are set. For example: 110 Instruction (post-execution instruction break on channel A) → SPC = 112, CMFA = 1 112 Instruction (pre-execution instruction break on channel B) → SPC = 112, CMFB = 1 5. The PCBA or PCBB bit in BRCR is invalid for an instruction access break setting. 6. When the SEQ bit in BRCR is 1, the internal sequential break state is initialized by a channel B condition match. For example: A → A → B (user break generated) → B (no break generated) 7. In the event of contention between a re-execution type exception and a post-execution break in a multistep instruction, the re-execution type exception is generated. In this case, the CMF bit may or may not be set to 1 when the break condition occurs. 8. A post-execution break is classified as a completion type exception. Consequently, in the event of contention between a completion type exception and a post-execution break, the postRev.7.00 Oct. 10, 2008 Page 871 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) execution break is suppressed in accordance with the priorities of the two events. For example, in the case of contention between a TRAPA instruction and a post-execution break, the user break is suppressed. However, in this case, the CMF bit is set by the occurrence of the break condition. 20.4 User Break Debug Support Function The user break debug support function enables the processing used in the event of a user break exception to be changed. When a user break exception occurs, if the UBDE bit is set to 1 in the BRCR register, the DBR register value will be used as the branch destination address instead of [VBR + offset]. The value of R15 is saved in the SGR register regardless of the value of the UBDE bit in the BRCR register or the kind of exception event. A flowchart of the user break debug support function is shown in figure 20.2. Rev.7.00 Oct. 10, 2008 Page 872 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) Exception/interrupt generation Hardware operation SPC ← PC SSR ← SR SR.BL ← B'1 SR.MD ← B'1 SR.RB ← B'1 Exception Exception/ interrupt/trap? Interrupt Trap EXPEVT ← exception code INTEVT ← interrupt code EXPEVT ← H'160 TRA ← TRAPA (imm) SGR ← R15 No Yes Reset exception? Yes (BRCR.UBDE == 1) && (user break exception)? No PC ← DBR PC ← VBR + vector offset PC ← H'A0000000 Debug program R15 ← SGR (STC instruction) Exception service routine Execute RTE instruction PC ← SPC SR ← SSR End of exception operations Figure 20.2 User Break Debug Support Function Flowchart Rev.7.00 Oct. 10, 2008 Page 873 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) 20.5 Examples of Use Instruction Access Cycle Break Condition Settings • Register settings: BASRA = H'80 / BARA = H'00000404 / BAMRA = H'00 / BBRA = H'0014 / BASRB = H'70 / BARB = H'00008010 / BAMRB = H'01 / BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0400 Conditions set: Independent channel A/channel B mode ⎯ Channel A: ASID: H'80 / address: H'00000404 / address mask: H'00 Bus cycle: instruction access (post-instruction-execution), read (operand size not included in conditions) ⎯ Channel B: ASID: H'70 / address: H'00008010 / address mask: H'01 Data: H'00000000 / data mask: H'00000000 Bus cycle: instruction access (pre-instruction-execution), read (operand size not included in conditions) A user break is generated after execution of the instruction at address H'00000404 with ASID = H'80, or before execution of an instruction at addresses H'00008000–H'000083FE with ASID = H'70. • Register settings: BASRA = H'80 / BARA = H'00037226 / BAMRA = H'00 / BBRA = H'0016 / BASRB = H'70 / BARB = H'0003722E / BAMRB = H'00 / BBRB = H'0016 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0008 Conditions set: Channel A → channel B sequential mode ⎯ Channel A: ASID: H'80 / address: H'00037226 / address mask: H'00 Bus cycle: instruction access (pre-instruction-execution), read, word ⎯ Channel B: ASID: H'70 / address: H'0003722E / address mask: H'00 Data: H'00000000 / data mask: H'00000000 Bus cycle: instruction access (pre-instruction-execution), read, word The instruction at address H'00037266 with ASID = H'80 is executed, then a user break is generated before execution of the instruction at address H'0003722E with ASID = H'70. • Register settings: BASRA = H'80 / BARA = H'00027128 / BAMRA = H'00 / BBRA = H'001A / BASRB = H'70 / BARB = H'00031415 / BAMRB = H'00 / BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0000 Rev.7.00 Oct. 10, 2008 Page 874 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) Conditions set: Independent channel A/channel B mode ⎯ Channel A: ASID: H'80 / address: H'00027128 / address mask: H'00 Bus cycle: CPU, instruction access (pre-instruction-execution), write, word ⎯ Channel B: ASID: H'70 / address: H'00031415 / address mask: H'00 Data: H'00000000 / data mask: H'00000000 Bus cycle: CPU, instruction access (pre-instruction-execution), read (operand size not included in conditions) A user break interrupt is not generated on channel A since the instruction access is not a write cycle. A user break interrupt is not generated on channel B since instruction access is performed on an even address. Operand Access Cycle Break Condition Settings • Register settings: BASRA = H'80 / BARA = H'00123456 / BAMRA = H'00 / BBRA = H'0024 / BASRB = H'70/ BARB = H'000ABCDE / BAMRB = H'02 / BBRB = H'002A / BDRB = H'0000A512 / BDMRB = H'00000000 / BRCR = H'0080 Conditions set: Independent channel A/channel B mode ⎯ Channel A: ASID: H'80 / address: H'00123456 / address mask: H'00 Bus cycle: operand access, read (operand size not included in conditions) ⎯ Channel B: ASID: H'70 / address: H'000ABCDE / address mask: H'02 Data: H'0000A512 / data mask: H'00000000 Bus cycle: operand access, write, word Data break enabled On channel A, a user break interrupt is generated in the event of a longword read at address H'00123454, a word read at address H'00123456, or a byte read at address H'00123456, with ASID = H'80. On channel B, a user break interrupt is generated when H'A512 is written by word access to any address from H'000AB000 to H'000ABFFE with ASID = H'70. Rev.7.00 Oct. 10, 2008 Page 875 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) 20.6 User Break Controller Stop Function In the SH7750S, this function stops the clock supplied to the user break controller and is used to minimize power dissipation when the chip is operating. Note that, if you use this function, you cannot use the user break controller. This function is not provided in the SH7750. 20.6.1 Transition to User Break Controller Stopped State Setting the MSTP5 bit of the STBCR2 (inside the CPG) to 1 stops the clock supply and causes the user break controller to enter the stopped state. Follow steps (1) to (5) below to set the MSTP5 bit to 1 and enter the stopped state. (1) Initialize BBRA and BBRB to 0; (2) Initialize BRCR to 0; (3) Make a dummy read of BRCR; (4) Read STBCR2, then set the MSTP5 bit in the read data to 1 and write back. (5) Make two dummy reads of STBCR2. Make sure that, if an exception or interrupt occurs while performing steps (1) to (5), you do not change the values of these registers in the exception handling routine. Do not read or write the following registers while the user break controller clock is stopped: BARA, BAMRA, BBRA, BARB, BAMRB, BBRB, BDRB, BDMRB, and BRCR. If these registers are read or written, the value cannot be guaranteed. 20.6.2 Cancelling the User Break Controller Stopped State The clock supply can be restarted by setting the MSTP5 bit of STBCR2 (inside the CPG) to 0. The user break controller can then be operated again. Follow steps (6) and (7) below to clear the MSTP5 bit to 0 to cancel the stopped state. (6) Read STBCR2, then clear the MSTP5 bit in the read data to 0 and write the modified data back; (7) Make two dummy reads of STBCR2. As with the transition to the stopped state, if an exception or interrupt occurs while processing steps (6) and (7), make sure that the values in these registers are not changed in the exception handling routine. Rev.7.00 Oct. 10, 2008 Page 876 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) 20.6.3 Examples of Stopping and Restarting the User Break Controller The following are example programs: ; Transition to user break controller stopped state ; (1) Initialize BBRA and BBRB to 0. mov mov.l mov.w mov.l mov.w #0, R0 #BBRA, R1 R0, @R1 #BBRB, R1 R0, @R1 ; (2) Initialize BRCR to 0. mov.l mov.w #BRCR, R1 R0, @R1 ; (3) Dummy read BRCR. mov.w @R1, R0 ; (4) Read STBCR2, then set MSTP5 bit in the read data to 1 and write it back mov.l mov.b #STBCR2, R1 @R1, R0 or #H'1, R0 mov.b R0, @R1 ; (5) Twice dummy read STBCR2. mov.b mov.b @R1, R0 @R1, R0 ; Canceling user break controller stopped state ; (6) Read STBCR2, then clear MSTP5 bit in the read data to 0 and write it back mov.l mov.b and mov.b #STBCR2, R1 @R1, R0 #H'FE, R0 R0, @R1 ; (7) Twice dummy read STBCR2. mov.b mov.b @R1, R0 @R1, R0 Rev.7.00 Oct. 10, 2008 Page 877 of 1074 REJ09B0366-0700 Section 20 User Break Controller (UBC) Rev.7.00 Oct. 10, 2008 Page 878 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) Section 21 High-performance User Debug Interface (H-UDI) 21.1 21.1.1 Overview Features The high-performance user debug interface (H-UDI) is a serial input/output interface supporting a subset of the JTAG, IEEE 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. The SH7750R's H-UDI supports boundary-scan, but is used for emulator connection as well. The functions of this interface should not be used when using an emulator. Refer to the emulator manual for the method of connecting the emulator. The H-UDI uses six pins (TCK, TMS, TDI, TDO, TRST, and ASEBRK/BRKACK). The pin functions and serial transfer protocol conform to the JTAG specifications. 21.1.2 Block Diagram Figure 21.1 shows a block diagram of the H-UDI. The TAP (test access port) controller and control registers are reset independently of the chip reset pin by driving the TRST pin low or setting TMS to 1 and applying TCK for at least five clock cycles. The other circuits are reset and initialized in an ordinary reset. The H-UDI circuit has four internal registers: SDBPR, SDIR, SDDRH, and SDDRL (these last two together designated SDDR). The SDBPR register supports the JTAG bypass mode, SDIR is the command register, and SDDR is the data register. SDIR can be accessed directly from the TDI and TDO pins. Rev.7.00 Oct. 10, 2008 Page 879 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) Interrupt/reset etc. ASEBRK/BRKACK TCK TMS TRST Break control TAP controller Decoder SDIR Shift register * SDBPR SDBSR * SDINT SDDRH SDDRL TDO MUX Note: * Provided only in the SH7750R. Figure 21.1 Block Diagram of H-UDI Circuit Rev.7.00 Oct. 10, 2008 Page 880 of 1074 REJ09B0366-0700 Peripheral module bus TDI Section 21 High-performance User Debug Interface (H-UDI) 21.1.3 Pin Configuration Table 21.1 shows the H-UDI pin configuration. Table 21.1 H-UDI Pins Pin Name Clock pin Abbreviation I/O TCK Input Function When Not Used Same as the JTAG serial clock input pin. Data Open*1 is transferred from data input pin TDI to the HUDI circuit, and data is read from data output pin TDO, in synchronization with this signal. The mode select input pin. Changing this Open*1 signal in synchronization with TCK determines the meaning of the data input from TDI. The protocol conforms to the JTAG (IEEE Std 1149.1) specification. The input pin that resets the H-UDI. This signal *2 *3 is received asynchronously with respect to TCK, and effects a reset of the JTAG interface circuit when low. TRST must be driven low for a certain period when powering on, regardless of whether or not JTAG is used. This differs from the IEEE specification. The data input pin. Data is sent to the H-UDI circuit by changing this signal in synchronization with TCK. Open*1 Mode pin TMS Input Reset pin TRST Input Data input pin Data output pin Emulator pin TDI Input TDO Output The data output pin. Data is sent to the H-UDI Open circuit by reading this signal in synchronization with TCK. Input/ output Dedicated emulator pin Open*1 ASEBRK/ BRKACK Notes: 1. Pulled up inside the chip. When designing a board that allows use of an emulator, or when using interrupts and resets via the H-UDI, there is no problem in connecting a pullup resistance externally. 2. When designing a board that enables the use of an emulator, or when using interrupts and resets via the H-UDI, drive TRST low for a period overlapping RESET at power-on, and also provide for control by TRST alone. 3. Fixed to the ground or connected to the same signal line as RESET, or to a signal line that behaves in the same way. However, there is a problem when this pin is fixed to the ground. TRST is pulled up in the chip so, when this pin is fixed to the ground via external connection, a minute current will flow. The size of this current is determined by Rev.7.00 Oct. 10, 2008 Page 881 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) the rating of the pull-up resistor. Although this current has no effect on the chip's operation, unnecessary current will be dissipated. The maximum frequency of TCK (TMS, TDI, TDO) is 20 MHz. Make the TCK or CPG setting of this LSI such that the TCK frequency is lower than that of this LSI’s on-chip peripheral module clock. 21.1.4 Register Configuration Table 21.2 shows the H-UDI registers. Except for SDBPR, these registers are mapped in the control register space and can be referenced by the CPU. Table 21.2 H-UDI Registers CPU Side Name Instruction register Data register H Data register L Bypass register Interrupt source 4 register* Abbreviation SDIR P4 R/W Address R Area 7 Address Access Initial 1 Size Value* 16 H'FFFF R/W R/W H-UDI Side Access Initial 1 Size Value* 32 H'FFFFFFFD (Fixed 2 value* ) — — — H'00000000 H'FFF00000 H'1FF00000 SDDR/ R/W H'FFF00008 H'1FF00008 SDDRH SDDRL 32/16 Undefined Undefined Undefined H'0000 — — R/W W* 3 — — 1 32 R/W H'FFF0000A H'1FF0000A 16 — — — 16 SDBPR — SDINT R/W H'FFF00014 H'1FF00014 Boundary SDBSR — 4 scan register* — — — Undefined R/W — Undefined Notes: 1. Initialized when the TRST pin goes low or when the TAP is in the Test-Logic-Reset state. 2. The value read from H-UDI is fixed (H'FFFFFFFD). 3. Using the H-UDI interrupt command, a 1 can be written to the least significant bit. 4. SH7750R only Rev.7.00 Oct. 10, 2008 Page 882 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) 21.2 21.2.1 Register Descriptions Instruction Register (SDIR) The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. In the initial state, bypass mode is set. The value (command) is set from the serial input pin (TDI). SDIR is initialized by the TRST pin or in the TAP Test-Logic-Reset state. When this register is written to from the H-UDI, writing is possible regardless of the CPU mode. However, if a read is performed by the CPU while writing is in progress, it may not be possible to read the correct value. In this case, SDIR should be read twice, and then read again if the read values do not match. Operation is undefined if a reserved command is set in this register. SH7750, SH7750S: Bit: 15 TI3 Initial value: R/W: Bit: 1 R 7 — Initial value: R/W: 1 R 14 TI2 1 R 6 — 1 R 13 TI1 1 R 5 — 1 R 12 TI0 1 R 4 — 1 R 11 — 1 R 3 — 1 R 10 — 1 R 2 — 1 R 9 — 1 R 1 — 1 R 8 — 1 R 0 — 1 R Bits 15 to 12—Test Instruction Bits (TI3−TI0) Bit 15: TI3 0 Bit 14: TI2 0 1 Bit 13: TI1 — 0 1 Bit 12: TI0 — — 0 1 1 0 0 1 1 0 1 — — — 0 1 Description Reserved Reserved H-UDI reset negate H-UDI reset assert Reserved H-UDI interrupt Reserved Reserved Bypass mode (Initial value) Rev.7.00 Oct. 10, 2008 Page 883 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) Bits 11 to 0—Reserved: These bits are always read as 1, and should only be written with 1. SH7750R: Bit: 15 TI7 Initial value: R/W: Bit: 1 R 7 — Initial value: R/W: 1 R 14 TI6 1 R 6 — 1 R 13 TI5 1 R 5 — 1 R 12 TI4 1 R 4 — 1 R 11 TI3 1 R 3 — 1 R 10 TI2 1 R 2 — 1 R 9 TI1 1 R 1 — 1 R 8 TI0 1 R 0 — 1 R Bits 15 to 8—Test Instruction Bits (TI7–TI0) Bit 15: Bit 14: Bit 13: Bit 12: Bit 11: Bit 10: Bit 9: TI7 TI6 TI5 TI4 TI3 TI2 TI1 0 0 0 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 0 0 0 1 — 1 0 0 — — — 1 0 1 — — — 1 0 0 — — — 1 Bit 8: TI0 0 0 — — — 1 Description EXTEST SAMPLE/PRELOAD H-UDI reset negate H-UDI reset assert H-UDI interrupt Bypass mode (Initial value) Reserved Other than above Bits 7 to 0—Reserved: These bits are always read as 1, and should only be written with 1. Rev.7.00 Oct. 10, 2008 Page 884 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) 21.2.2 Data Register (SDDR) The data register (SDDR) is a 32-bit register, comprising the two 16-bit registers SDDRH and SDDRL, that can be read and written to by the CPU. The value in this register is not initialized by a TRST or CPU reset. Bit: 31 30 29 28 27 26 25 24 Initial value: R/W: Bit: * R/W 23 * R/W 22 * R/W 21 * R/W 20 * R/W 19 * R/W 18 * R/W 17 * R/W 16 Initial value: R/W: Bit: * R/W 15 * R/W 14 * R/W 13 * R/W 12 * R/W 11 * R/W 10 * R/W 9 * R/W 8 Initial value: R/W: Bit: * R/W 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 Initial value: R/W: Legend: *: Undefined * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W Bits 31 to 0—DR Data: These bits store the SDDR value. 21.2.3 Bypass Register (SDBPR) The bypass register (SDBPR) is a one-bit register that cannot be accessed by the CPU. When bypass mode is set in SDIR, SDBPR is connected between the TDI pin and TDO pin of the H-UDI. Rev.7.00 Oct. 10, 2008 Page 885 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) 21.2.4 Interrupt Source Register (SDINT) (SH7750R Only) The interrupt source register (SDINT) is a 16-bit register that can be read from and written to by the CPU. From the H-UDI pins, the INTREQ bit is set to 1 when a H-UDI interrupt command is set in the SDIR register (Update-IR). While SDIR is holding a H-UDI interrupt command, the SDINT register is connected between the TDI and TDO pins of the H-UDI, allowing it to be read as a 32bit register. In this case, the upper 16 bits will all be 0, and the lower 16 bits will represent SDINT. From the CPU, only writing a 0 to the INTREQ bit is possible. While this bit holds a 1, the interrupt requests continue to be issued, so this bit should always be cleared in the interrupt handler. This register is initialized in the Test-Logic-Reset state of TRST or TAP. Bit: 15 — Initial value: R/W: Bit: 0 R 7 — Initial value: R/W: 0 R 14 — 0 R 6 — 0 R 13 — 0 R 5 — 0 R 12 — 0 R 4 — 0 R 11 — 0 R 3 — 0 R 10 — 0 R 2 — 0 R 9 — 0 R 1 — 0 R 8 — 0 R 0 INTREQ 0 R/W Bits 15 to 1—Reserved: These bits are always read as 0. When writing, only 0s should be written here. Bit 0⎯Interrupt Request (INTREQ): Indicates whether or not an interrupt request has been issued by an H-UDI interrupt command. From the CPU, the interrupt request can be cleared by writing a 0 to this bit. If a 1 is written to this bit, it retains the value it had before the write operation. Rev.7.00 Oct. 10, 2008 Page 886 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) 21.2.5 Boundary Scan Register (SDBSR) (SH7750R Only) The boundary scan register (SDBSR) is a shift register that is placed on the pads to control the chip's I/O pins. This register can perform a boundary scan test equivalent to the JTAG (IEEE Std 1149.1) standard using EXTEST, SAMPLE, and PRELOAD commands. Table 21.3 shows the relationship between the SH7750R's pins and the boundary scan register. Rev.7.00 Oct. 10, 2008 Page 887 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) Table 21.3 Configuration of the Boundary Scan Register No. Pin Name CKIO2ENB MD6/IOIS16 STATUS1 STATUS1 STATUS0 STATUS0 A1 A1 A0 A0 DACK1 DACK1 DACK0 DACK0 MD5/RAS2 MD5/RAS2 MD5/RAS2 MD4/CE2B MD4/CE2B MD4/CE2B MD3/CE2A MD3/CE2A MD3/CE2A A25 A25 A24 A24 A23 A23 A22 A22 A21 A21 A20 A20 A19 Type No. 309 IN IN CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL 308 307 306 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 Pin Name A19 A18 A18 SCK2/MRESET SCK2/MRESET SCK2/MRESET MD7/TXD MD7/TXD MD7/TXD MD8/RTS2 MD8/RTS2 MD8/RTS2 TCLK TCLK TCLK CTS2 CTS2 CTS2 NMI IRL3 IRL2 IRL1 IRL0 MD2/RXD2 MD1/TXD2 MD1/TXD2 MD1/TXD2 MD0/SCK MD0/SCK MD0/SCK RD/WR2 RD/WR2 D63 D63 D63 D48 D48 Type OUT CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN IN IN IN IN IN IN CTL OUT IN CTL OUT CTL OUT IN CTL OUT IN CTL No. 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 Pin Name D48 D62 D62 D62 D49 D49 D49 D61 D61 D61 D50 D50 D50 D60 D60 D60 D51 D51 D51 D59 D59 D59 D52 D52 D52 D58 D58 D58 D53 D53 D53 D57 D57 D57 D54 D54 D54 Type OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT to TDO 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 Rev.7.00 Oct. 10, 2008 Page 888 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) No. 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 Pin Name D56 D56 D56 D55 D55 D55 D31 D31 D31 D16 D16 D16 D30 D30 D30 D17 D17 D17 D29 D29 D29 D18 D18 D18 D28 D28 D28 D19 D19 D19 D27 D27 D27 D20 D20 D20 D26 D26 D26 Type IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT No. 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 Pin Name D21 D21 D21 D25 D25 D25 DREQ1 DREQ0 RXD D22 D22 D22 D24 D24 D24 D23 D23 D23 WE7/CAS7/DQM7/REG WE7/CAS7/DQM7/REG WE6/CAS6/DQM6 WE6/CAS6/DQM6 Type IN CTL OUT IN CTL OUT IN IN IN IN CTL OUT IN CTL OUT IN CTL OUT CTL OUT CTL OUT No. 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 Pin Name DRAK1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 A7 A7 A8 A8 A9 A9 A10 A10 A11 A11 A12 A12 A13 A13 A14 A14 A15 A15 A16 A16 A17 A17 WE0/CAS0/DQM0 WE0/CAS0/DQM0 WE1/CAS1/DQM1 WE1/CAS1/DQM1 WE4/CAS4/DQM4 WE4/CAS4/DQM4 Type OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT WE3/CAS3/DQM3/ICIOWR CTL WE3/CAS3/DQM3/ICIOWR OUT WE2/CAS2/DQM2/ICIORD CTL WE2/CAS2/DQM2/ICIORD OUT RD/WR RD/WR RD/CASS/FRAME RD/CASS/FRAME RAS RAS CS2 CS2 CS3 CS3 DRAK0 DRAK0 DRAK1 CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL Rev.7.00 Oct. 10, 2008 Page 889 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) No. 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 Pin Name WE5/CAS5/DQM5 WE5/CAS5/DQM5 CKE CKE D7 D7 D7 D8 D8 D8 BREQ/BSACK BACK/BSREQ BACK/BSREQ D6 D6 D6 D9 D9 D9 D5 D5 D5 D10 D10 D10 D4 D4 D4 D11 D11 D11 D3 D3 D3 D12 D12 D12 D2 D2 D2 Type CTL OUT CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT No. 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 Pin Name D13 D13 D13 D1 D1 D1 D14 D14 D14 D0 D0 D0 D15 D15 D15 D39 D39 D39 D40 D40 D40 D38 D38 D38 D41 D41 D41 D37 D37 D37 D42 D42 D42 D36 D36 D36 D43 D43 D43 D35 Type IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN No. 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Pin Name D35 D35 D44 D44 D44 D34 D34 D34 D45 D45 D45 D33 D33 D33 D46 D46 D46 D32 D32 D32 D47 D47 D47 RD2 RD2 BS BS CS6 CS6 CS5 CS5 CS4 CS4 CS1 CS1 CS0 CS0 RDY Type CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT IN from TDI Note: CTL is an active-low signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev.7.00 Oct. 10, 2008 Page 890 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) 21.3 21.3.1 Operation TAP Control Figure 21.2 shows the internal states of the TAP control circuit. These conform to the state transitions specified by JTAG. • The transition condition is the TMS value at the rising edge of TCK. • The TDI value is sampled at the rising edge of TCK, and shifted at the falling edge. • The TDO value changes at the falling edge of TCK. When not in the Shift-DR or Shift-IR state, TDO is in the high-impedance state. • In a transition to TRST = 0, a transition is made to the Test-Logic-Reset state asynchronously with respect to TCK. 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR-Scan 1 Select-IR-Scan 1 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 Figure 21.2 TAP Control State Transition Diagram Rev.7.00 Oct. 10, 2008 Page 891 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) 21.3.2 H-UDI Reset A power-on reset is effected by an SDIR command. A reset is effected by sending an H-UDI reset assert command, and then sending an H-UDI reset negate command, from the H-UDI pin (see figure 21.3). The interval required between the H-UDI reset assert command and the H-UDI reset negate command is the same as the length of time the reset pin is held low in order to effect a power-on reset. H-UDI pin H-UDI reset assert H-UDI reset negate Chip internal reset CPU state Normal Reset Reset processing Figure 21.3 H-UDI Reset 21.3.3 H-UDI Interrupt The H-UDI interrupt function generates an interrupt by setting a command value in SDIR from the H-UDI. The H-UDI interrupt is of general exception/interrupt operation type, with a branch to an address based on VBR and return effected by means of an RTE instruction. The exception code stored in control register INTEVT in this case is H'600. The priority of the H-UDI interrupt can be controlled with bits 3 to 0 of control register IPRC. In the SH7750 or SH7750S, the H-UDI interrupt request signal is asserted for about eight cycles of the LSI's on-chip peripheral clock after the command is set. The number of cycles for assertion is determined by the ratio of TCK to the frequency of the on-chip peripheral clock. Since the period of assertion is limited, the CPU may miss a request. In the SH7750R, the H-UDI interrupt request signal is asserted when the INTREQ bit in the SDINT register is set to 1 after the command is set (Update-IR). The interrupt request signal will not be negated unless a 0 is written to the INTREQ bit by software; therefore, the CPU will not miss a request. As long as the H-UDI interrupt command is set in SDIR, the SDINT register is connected between the TDI and TDO pins. Note that, in the SH7750 or SH7750S, the H-UDI interrupt command automatically becomes a bypass command immediately after it has been set. In the SH7750R, the command is not changed Rev.7.00 Oct. 10, 2008 Page 892 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) except by the following operations: update in the Update-IR state, initialization in the Test-LogicReset state, and initialization by assertion of TRST. 21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only) In the SH7750R, setting a command from the H-UDI in SDIR can place the H-UDI pins in the boundary scan mode. However, the following limitations apply. 1. Boundary scan does not cover clock-related signals (EXTAL, EXTAL2, XTAL, XTAL2, and CKIO). 2. Boundary scan does not cover reset-related signals (RESET, CA) 3. Boundary scan does not cover H-UDI-related signals (TCK, TDI, TDO, TMS, TRST). 4. With EXTEST, assert the MRESET pin (low), the RESET pin (low), and CA pin (high). With SAMPLE/PRELOAD, assert the CA pin (high). 5. To perform boundary scan, supply a clock to the EXTAL pin, and wait for the power-on oscillation settling time to elapse before starting boundary scan. The frequency range of the input clock is from 1 to 33.3 MHz. Note that after the power-on oscillation settling time has elapsed, a clock does not need to be supplied to the EXTAL pin any longer. For details on the power-on oscillation settling time, see section 22, Electrical Characteristics. 21.4 Usage Notes 1. SDIR Command Once an SDIR command has been set, it remains unchanged until initialization by asserting TRST or placing the TAP in the Test-Logic-Reset state, or until another command (other than an H-UDI interrupt command) is written from the H-UDI. 2. SDIR Commands in Sleep Mode Sleep mode is cleared by an H-UDI interrupt or H-UDI reset, and these exception requests are accepted in this mode. In standby mode, neither an H-UDI interrupt nor an H-UDI reset is accepted. 3. In standby mode, the H-UDI function cannot be used. Furthermore, TCK must be retained at a high level when entering the standby mode in order to retain the TAP state before and after standby mode. 4. The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when an emulator is used. 5. The H-UDI pins of the SH7750 and SH7750S must not be connected to a boundary-scan signal loop on the board. Rev.7.00 Oct. 10, 2008 Page 893 of 1074 REJ09B0366-0700 Section 21 High-performance User Debug Interface (H-UDI) 6. In BYPASS mode on the SH7750 or SH7750S, the contents of the bypass register (SDBPR) are undefined in the Capture-DR state. On the SH7750R, SDBPR has a value of 0. Rev.7.00 Oct. 10, 2008 Page 894 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22.1 Absolute Maximum Ratings Item I/O, PLL, RTC, CPG power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-RTC VDD-CPG VDD Vin Topr Tstg Value –0.3 to 4.2, –0.3 to 4.6* Unit V Internal power supply voltage Input voltage Operating temperature Storage temperature –0.3 to 2.5, –0.3 to 2.1* –0.3 to VDDQ +0.3 –20 to 75 –55 to 125 V V °C °C Notes: Permanent damage to the chip may result if the maximum ratings are exceeded. Permanent damage to the chip may result if all VSS pins are not connected to GND. For information on the power-on and power-off procedures, refer to appendix H, Power-On and Power-Off Procedures. * HD6417750R only Rev.7.00 Oct. 10, 2008 Page 895 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics 22.2 DC Characteristics Table 22.2 DC Characteristics (HD6417750RBP240 (V), HD6417750RBG240 (V)) Ta = –20 to +75°C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 240 MHz 1.4 1.5 1.6 Current dissipation Normal operation Sleep mode Standby mode IDD — — — — 230 — — — 170 35 — — 15 3 580 120 400 800 215 40 440 880 25 5 VDDQ + 0.3 VDDQ + 0.3 VDDQ × 0.1 VDDQ × 0.2 1 μA Ta = 25°C*1 Ta > 50°C*1 Ick = 240 MHz, Bck = 120 MHz Ta = 25°C*1 Ta > 50°C* 1 Current dissipation Normal operation Sleep mode Standby mode IDDQ — — — — mA μA μA RTC current dissipation Standby mode IDD-RTC VIH — RTC on*2 RTC off Input voltage RESET, NMI, TRST Other input pins RESET, NMI, TRST Other input pins Input leakage All input current pins VDDQ × 0.9 2.0 — — — — — V VIL –0.3 –0.3 |Iin| — μA VIN = 0.5 to VDDQ –0.5 V Rev.7.00 Oct. 10, 2008 Page 896 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item Three-state leakage current Output voltage Pull-up resistance Pin capacitance I/O, all output pins (off state) All output pins All pull-up resistance All pins Symbol |Isti| Min — Typ — Max 1 Unit μA Test Conditions VIN = 0.5 to VDDQ –0.5 V VOH VOL Rpull CL 2.4 — 20 — — — 60 — — 0.55 180 10 V kΩ pF IOH = –2 mA IOL = 2 mA Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and connect VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the total current value for the 3.3 V versions of VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG. 1. RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode. (There is no need to input a clock from EXTAL2.) 2. RTCON refers to the status in which RCR2.RTCEN is set to 1 and a clock is being input to EXTAL2. Rev.7.00 Oct. 10, 2008 Page 897 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.3 DC Characteristics (HD6417750RF240 (V)) Ta = –20 to +75°C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 240 MHz 1.4 1.5 1.6 Current dissipation Normal operation Sleep mode Standby mode IDD — — — — 230 — — — 140 35 — — 15 3 580 120 400 800 180 40 440 880 25 5 VDDQ + 0.3 VDDQ + 0.3 VDDQ × 0.1 VDDQ × 0.2 1 1 μA Ta = 25°C*1 Ta > 50°C* 1 Current dissipation Normal operation Sleep mode Standby mode IDDQ — — — — mA Ick = 240 MHz, Bck = 80 MHz Ta = 25°C*1 Ta > 50°C*1 RTC on*2 RTC off μA μA RTC current dissipation Standby mode IDD-RTC VIH — Input voltage RESET, NMI, TRST Other input pins RESET, NMI, TRST Other input pins Input leakage All input current pins Three-state leakage current I/O, all output pins (off state) VDDQ × 0.9 2.0 — — — — — — V VIL –0.3 –0.3 |Iin| |Isti| — — μA μA VIN = 0.5 to VDDQ –0.5 V VIN = 0.5 to VDDQ –0.5 V Rev.7.00 Oct. 10, 2008 Page 898 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins Symbol VOH VOL Rpull CL Min 2.4 — 20 — Typ — — 60 — Max — 0.55 180 10 kΩ pF Unit V Test Conditions IOH = –2 mA IOL = 2 mA Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the total current value for the 3.3 V versions of VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG. 1. RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode. (There is no need to input a clock from EXTAL2.) 2. RTCON refers to the status in which RCR2.RTCEN is set to 1 and a clock is being input to EXTAL2. Rev.7.00 Oct. 10, 2008 Page 899 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.4 DC Characteristics (HD6417750RBP200 (V), HD6417750RBG200 (V)) Ta = –20 to +75°C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 200 MHz 1.35 1.5 1.6 Current dissipation Normal operation Sleep mode Standby mode IDD — — — — 190 — — — 140 30 — — 15 3 480 100 400 800 180 35 440 880 25 5 VDDQ + 0.3 VDDQ + 0.3 VDDQ × 0.1 VDDQ × 0.2 1 1 μA Ta = 25°C*1 Ta > 50°C* 1 Current dissipation Normal operation Sleep mode Standby mode IDDQ — — — — mA Ick = 200 MHz, Bck = 100 MHz Ta = 25°C*1 Ta > 50°C*1 RTC on*2 RTC off μA μA RTC current dissipation Standby mode IDD-RTC VIH — Input voltage RESET, NMI, TRST Other input pins RESET, NMI, TRST Other input pins Input leakage All input current pins Three-state leakage current I/O, all output pins (off state) VDDQ × 0.9 2.0 — — — — — — V VIL –0.3 –0.3 |Iin| |Isti| — — μA μA VIN = 0.5 to VDDQ –0.5 V VIN = 0.5 to VDDQ –0.5 V Rev.7.00 Oct. 10, 2008 Page 900 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins Symbol VOH VOL Rpull CL Min 2.4 — 20 — Typ — — 60 — Max — 0.55 180 10 kΩ pF Unit V Test Conditions IOH = –2 mA IOL = 2 mA Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and connect VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG 3.3 V system currents. 1. RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode. (There is no need to input a clock from EXTAL2.) 2. RTCON refers to the status in which RCR2.RTCEN is set to 1 and a clock is being input to EXTAL2. Rev.7.00 Oct. 10, 2008 Page 901 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.5 DC Characteristics (HD6417750RF200 (V)) Ta = –20 to +75°C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 200 MHz 1.35 1.5 1.6 Current dissipation Normal operation Sleep mode Standby mode IDD — — — — 190 — — — 140 30 — — 15 3 480 100 400 800 180 35 440 880 25 5 VDDQ + 0.3 VDDQ + 0.3 VDDQ × 0.1 VDDQ × 0.2 1 1 μA Ta = 25°C*1 Ta > 50°C* 1 Current dissipation Normal operation Sleep mode Standby mode IDDQ — — — — mA Ick = 200 MHz, Bck = 67 MHz Ta = 25°C*1 Ta > 50°C*1 RTC on*2 RTC off μA μA RTC current dissipation Standby mode IDD-RTC VIH — Input voltage RESET, NMI, TRST Other input pins RESET, NMI, TRST Other input pins Input leakage All input current pins Three-state leakage current I/O, all output pins (off state) VDDQ × 0.9 2.0 — — — — — — V VIL –0.3 –0.3 |Iin| |Isti| — — μA μA VIN = 0.5 to VDDQ –0.5 V VIN = 0.5 to VDDQ –0.5 V Rev.7.00 Oct. 10, 2008 Page 902 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins Symbol VOH VOL Rpull CL Min 2.4 — 20 — Typ — — 60 — Max — 0.55 180 10 kΩ pF Unit V Test Conditions IOH = –2 mA IOL = 2 mA Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. 1. RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode. (There is no need to input a clock from EXTAL2.) 2. RTCON refers to the status in which RCR2.RTCEN is set to 1 and a clock is being input to EXTAL2. Rev.7.00 Oct. 10, 2008 Page 903 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.6 DC Characteristics (HD6417750SBP200 (V)) Ta = –20 to +75°C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 200 MHz 1.8 1.95 2.07 Current dissipation Normal operation Sleep mode Standby mode IDD — — — — 410 165 — — 140 40 — — 15 780 210 2000 5000 180 50 2200 5500 25 μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) Ick = 200 MHz, Bck = 100 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC Current dissipation Normal operation Sleep mode Standby mode IDDQ — — — — — mA μA μA RTC current dissipation During RTC IDD-RTC operation Input voltage RESET, NMI, TRST Other input pins RESET, NMI, TRST Other input pins Output voltage All output pins VIH VDDQ × 0.9 2.0 — — — — — — VDDQ + 0.3 VDDQ + 0.3 VDDQ × 0.1 VDDQ × 0.2 — 0.55 V VIL –0.3 –0.3 VOH VOL 2.4 — V IOH = –2 mA IOL = 2 mA Rev.7.00 Oct. 10, 2008 Page 904 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item Pull-up resistance Pin capacitance All pull-up resistance All pins Symbol Rpull CL Min 20 — Typ 60 — Max 180 10 Unit kΩ pF Test Conditions Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev.7.00 Oct. 10, 2008 Page 905 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.7 DC Characteristics (HD6417750SF200 (V)) Ta = –20 to +75°C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 200 MHz 1.8 1.95 2.07 Current dissipation Normal operation Sleep mode Standby mode IDD — — — — 410 165 — — 140 40 — — 15 780 210 2000 5000 180 50 2200 5500 25 μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) Ick = 200 MHz, Bck = 67 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC Current dissipation Normal operation Sleep mode Standby mode IDDQ — — — — — mA μA μA RTC current dissipation During RTC IDD-RTC operation Input voltage RESET, NMI, TRST Other input pins RESET, NMI, TRST Other input pins Output voltage All output pins VIH VDDQ × 0.9 2.0 — — — — — — VDDQ + 0.3 VDDQ + 0.3 VDDQ × 0.1 VDDQ × 0.2 — 0.55 V VIL –0.3 –0.3 VOH VOL 2.4 — V IOH = –2 mA IOL = 2 mA Rev.7.00 Oct. 10, 2008 Page 906 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item Pull-up resistance Pin capacitance All pull-up resistance All pins Symbol Rpull CL Min 20 — Typ 60 — Max 180 10 Unit kΩ pF Test Conditions Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev.7.00 Oct. 10, 2008 Page 907 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.8 DC Characteristics (HD6417750BP200M (V)) Ta = –20 to +75°C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 200 MHz 1.8 1.95 2.07 Current dissipation Normal operation Sleep mode Standby mode IDD — — — — 1000 165 — — 160 40 — — — — — — — — 60 — 1200 — 2000 5000 200 — 2200 5500 VDDQ + 0.3 VDDQ + 0.3 VDDQ × 0.1 VDDQ × 0.2 — 0.55 180 10 μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) Ick = 200 MHz, Bck = 100 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) Current dissipation Normal operation Sleep mode Standby mode IDDQ — — — — mA μA Input voltage RESET, NMI, TRST Other input pins RESET, NMI, TRST Other input pins Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins VIH VDDQ × 0.9 2.0 V VIL –0.3 –0.3 VOH VOL Rpull CL 2.4 — 20 — V kΩ pF IOH = –2 mA IOL = 2 mA Rev.7.00 Oct. 10, 2008 Page 908 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev.7.00 Oct. 10, 2008 Page 909 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.9 DC Characteristics (HD6417750SF167 (V)) Ta = –20 to +75°C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 167 MHz 1.6 1.8 2.0 Current dissipation Normal operation Sleep mode Standby mode IDD — — — — 320 120 50 100 140 40 110 220 15 650 150 400 800 180 50 440 880 45 μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) Ick = 167 MHz, Bck = 84 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC Current dissipation Normal operation Sleep mode Standby mode IDDQ — — — — — mA μA μA RTC current dissipation During RTC IDD-RTC operation Input voltage RESET, NMI, TRST Other input pins RESET, NMI, TRST Other input pins Output voltage All output pins VIH VDDQ × 0.9 2.0 — — — — — — VDDQ + 0.3 VDDQ + 0.3 VDDQ × 0.1 VDDQ × 0.2 — 0.55 V VIL –0.3 –0.3 VOH VOL 2.4 — V IOH = –2 mA IOL = 2 mA Rev.7.00 Oct. 10, 2008 Page 910 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item Pull-up resistance Pin capacitance All pull-up resistance All pins Symbol Rpull CL Min 20 — Typ 60 — Max 180 10 Unit kΩ pF Test Conditions Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev.7.00 Oct. 10, 2008 Page 911 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.10 DC Characteristics (HD6417750F167 (V)) Ta = –20 to +75°C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 167 MHz 1.6 1.8 2.0 Current dissipation Normal operation Sleep mode Standby mode IDD — — — — 630 120 — — 160 40 — — — — — — — — 60 — 700 — 400 800 200 — 440 880 VDDQ + 0.3 VDDQ + 0.3 VDDQ × 0.1 VDDQ × 0.2 — 0.55 180 10 μA Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) Ick = 167 MHz, Bck = 84 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) Current dissipation Normal operation Sleep mode Standby mode IDDQ — — — — mA μA Input voltage RESET, NMI, TRST Other input pins RESET, NMI, TRST Other input pins Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins VIH VDDQ × 0.9 2.0 V VIL –0.3 –0.3 VOH VOL Rpull CL 2.4 — 20 — V kΩ pF IOH = –2 mA IOL = 2 mA Rev.7.00 Oct. 10, 2008 Page 912 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev.7.00 Oct. 10, 2008 Page 913 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.11 DC Characteristics (HD6417750SVF133 (V)) Ta = –20 to +75°C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 133 MHz, Bck = 67 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) mA Ick = 133 MHz, Bck = 67 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) μA RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC Input voltage RESET, NMI, TRST Other input pins RESET, NMI, TRST Other input pins Output voltage All output pins VOH VOL VIL VIH VDDQ × 0.9 2.0 –0.3 –0.3 2.4 — — — — — — — VDDQ + 0.3 VDDQ + 0.3 VDDQ × 0.1 VDDQ × 0.2 — 0.55 V IOH = –2 mA IOL = 2 mA V 1.4 1.5 1.7 Current dissipation Normal operation Sleep mode Standby mode IDD — — — — 210 50 — — 80 35 — — 15 520 60 100 200 160 40 110 220 25 μA Current dissipation Normal operation Sleep mode Standby mode IDDQ — — — — — μA RTC current dissipation During RTC IDD-RTC operation Rev.7.00 Oct. 10, 2008 Page 914 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item Pull-up resistance Pin capacitance All pull-up resistance All pins Symbol Rpull CL Min 20 — Typ 60 — Max 180 10 Unit kΩ pF Test Conditions Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev.7.00 Oct. 10, 2008 Page 915 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.12 DC Characteristics (HD6417750SVBT133 (V)) Ta = –30 to +70°C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 133 MHz, Bck = 66 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) mA Ick = 133 MHz, Bck = 67 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) μA RTC input clock: 32.768 kHz Power is supplied only to VDD-RTC Input voltage RESET, NMI, TRST Other input pins RESET, NMI, TRST Other input pins Output voltage All output pins VOH VOL VIL VIH VDDQ × 0.9 2.0 –0.3 –0.3 2.4 — — — — — — — VDDQ + 0.3 VDDQ + 0.3 VDDQ × 0.1 VDDQ × 0.2 — 0.55 V IOH = –2 mA IOL = 2 mA V 1.4 1.5 1.7 Current dissipation Normal operation Sleep mode Standby mode IDD — — — — 210 50 — — 80 35 — — 15 520 60 100 200 160 40 110 220 45 μA Current dissipation Normal operation Sleep mode Standby mode IDDQ — — — — — μA RTC current dissipation During RTC IDD-RTC operation Rev.7.00 Oct. 10, 2008 Page 916 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item Pull-up resistance Pin capacitance All pull-up resistance All pins Symbol Rpull CL Min 20 — Typ 60 — Max 180 10 Unit kΩ pF Test Conditions Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Rev.7.00 Oct. 10, 2008 Page 917 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.13 DC Characteristics (HD6417750VF128 (V)) Ta = –20 to +75°C Item Power supply voltage Symbol VDDQ VDD-PLL1/2 VDD-CPG VDD-RTC VDD Min 3.0 Typ 3.3 Max 3.6 Unit V Test Conditions Normal mode, sleep mode, deep sleep mode, standby mode Normal mode, sleep mode, deep sleep mode, standby mode mA Ick = 128 MHz, Bck = 64 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) mA Ick = 128 MHz, Bck = 64 MHz Ta = 25°C (RTC on*) Ta > 50°C (RTC on*) V 1.4 1.5 1.7 Current dissipation Normal operation Sleep mode Standby mode IDD — — — — — — — — — — — — — — — — — — 60 — 520 60 100 200 160 40 110 220 VDDQ + 0.3 VDDQ + 0.3 VDDQ × 0.1 VDDQ × 0.2 — 0.55 180 10 μA Current dissipation Normal operation Sleep mode Standby mode IDDQ — — — — μA Input voltage RESET, NMI, TRST Other input pins RESET, NMI, TRST Other input pins Output voltage Pull-up resistance Pin capacitance All output pins All pull-up resistance All pins VIH VDDQ × 0.9 2.0 VIL –0.3 –0.3 VOH VOL Rpull CL 2.4 — 20 — V kΩ pF IOH = –2 mA IOL = 2 mA Rev.7.00 Oct. 10, 2008 Page 918 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Notes: Connect VDD-PLL1/2, VDD-RTC, and VDD-CPG to VDDQ, and VSS-CPG, VSS-PLL1/2, and VSSQ-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. IDDQ is the sum of the VDDQ, VDD-PLL1/2, VDD-RTC, and VDD-CPG 3.3 V system currents. * To reduce the leakage current in standby mode, the RTC must be turned on (input the clock from EXTAL2 and set RCR2.RTCEN to 1). Table 22.14 Permissible Output Currents Ta = –20 to +75°C Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Symbol IOL ΣIOL –IOH Σ(–IOH) Min — — — — Typ — — — — Max 2 120 2 40 Unit mA Note: To protect chip reliability, do not exceed the output current values in table 22.14. Rev.7.00 Oct. 10, 2008 Page 919 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics 22.3 AC Characteristics In principle, this LSI input should be synchronous. Unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. Table 22.15 Clock Timing (HD6417750RBP240 (V), HD6417750RBG240 (V)) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ — — — Max 240 120 60 Unit MHz Table 22.16 Clock Timing (HD6417750RF240 (V)) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ — — — Max 240 84 60 Unit MHz Table 22.17 Clock Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750RBP200 (V), HD6417750RBG200 (V)) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ — — — Max 200 100 50 Unit MHz Table 22.18 Clock Timing (HD6417750RF200 (V)) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ — — — Max 200 84 50 Unit MHz Rev.7.00 Oct. 10, 2008 Page 920 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.19 Clock Timing (HD6417750SF200 (V)) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ — — — Max 200 67 50 Unit MHz Table 22.20 Clock Timing (HD6417750F167 (V), HD6417750SF167 (V)) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ — — — Max 167 84 42 Unit MHz Table 22.21 Clock Timing (HD6417750SVF133 (V), HD6417750SVBT133 (V)) Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min 1 1 1 Typ — — — Max 134 67 34 Unit MHz Table 22.22 Item Operating frequency Clock Timing (HD6417750VF128 (V)) Symbol CPU, FPU, cache, TLB External bus Peripheral modules f Min 1 1 1 Typ — — — Max 128 64 32 Unit MHz Rev.7.00 Oct. 10, 2008 Page 921 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics 22.3.1 Clock and Control Signal Timing Table 22.23 Clock and Control Signal Timing (HD6417750RBP240 (V), HD6417750RBG240 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency PLL1 6-times/PLL2 operation PLL1 12-times/PLL2 operation PLL1/PLL2 not operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL1/PLL2 operating PLL1/PLL2 not operating Symbol fEX fEX fEX tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW Min 16 14 1 30 3.5 3.5 — — 25 1 8.3 1 1 — — 3 3 10 10 20 20 3 20 20 Max 34 20 34 1000 — — 4 4 120 34 1000 — — 3 3 — — — — — — — — — ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (2) 22.2 (2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time RESET assert time Rev.7.00 Oct. 10, 2008 Page 922 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item PLL synchronization settling time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tPLL tOSC2 tOSC3 tOSC4 Min 200 3 3 3 2 2 2 — 0 Max — — — — — — — 200 — Unit μs ms ms ms ms ms ms μs ns 22.10 22.3, 22.5 Figure 22.9, 22.10 22.4, 22.6 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) TRST reset hold time tIRLSTB tTRSTRH Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev.7.00 Oct. 10, 2008 Page 923 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.24 Clock and Control Signal Timing (HD6417750RF240 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency PLL1 6-times/PLL2 operation PLL1 12-times/PLL2 operation PLL1/PLL2 not operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL1/PLL2 operating PLL1/PLL2 not operating Symbol fEX fEX fEX tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW tPLL tOSC2 Min 16 14 1 30 3.5 3.5 — — 25 1 11.9 1 1 — — 3 3 10 10 20 20 3 20 20 200 3 Max 34 20 34 1000 — — 4 4 84 34 1000 — — 3 3 — — — — — — — — — — — ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc μs ms 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(1) 22.2(2) 22.2(2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.4, 22.6 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time RESET assert time PLL synchronization settling time Standby return oscillation settling time 1 Rev.7.00 Oct. 10, 2008 Page 924 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tOSC3 tOSC4 Min 3 3 2 2 2 — 0 Max — — — — — 200 — Unit ms ms ms ms ms μs ns 22.10 22.3, 22.5 Figure 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) TRST reset hold time tIRLSTB tTRSTRH Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev.7.00 Oct. 10, 2008 Page 925 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.25 Clock and Control Signal Timing (HD6417750RBP200 (V), HD6417750RBG200 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency PLL1 6-times/PLL2 operation PLL1 12-times/PLL2 operation PLL1/PLL2 not operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL1/PLL2 operating PLL1/PLL2 not operating Symbol fEX fEX fEX tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW tPLL tOSC2 Min 16 14 1 30 3.5 3.5 — — 25 1 10 1 1 — — 3 3 10 10 20 20 3 20 20 200 5 Max 34 17 34 1000 — — 4 4 100 100 1000 — — 3 3 — — — — — — — — — — — ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc μs ms 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (2) 22.2 (2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.4, 22.6 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time RESET assert time PLL synchronization settling time Standby return oscillation settling time 1 Rev.7.00 Oct. 10, 2008 Page 926 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tOSC3 tOSC4 Min 5 5 2 2 2 — 0 Max — — — — — 200 — Unit ms ms ms ms ms μs ns 22.10 22.3, 22.5 Figure 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) TRST reset hold time tIRLSTB tTRSTRH Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev.7.00 Oct. 10, 2008 Page 927 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.26 Clock and Control Signal Timing (HD6417750RF200 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency PLL1 6-times/PLL2 operation PLL1 12-times/PLL2 operation PLL1/PLL2 not operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL1/PLL2 operating PLL1/PLL2 not operating Symbol fEX fEX fEX tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW tPLL tOSC2 Min 16 14 1 30 3.5 3.5 — — 25 1 11.9 1 1 — — 3 3 10 10 20 20 3 20 20 200 5 Max 34 17 34 1000 — — 4 4 84 34 1000 — — 3 3 — — — — — — — — — — — ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc μs ms 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (2) 22.2 (2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.4, 22.6 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time RESET assert time PLL synchronization settling time Standby return oscillation settling time 1 Rev.7.00 Oct. 10, 2008 Page 928 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tOSC3 tOSC4 Min 5 5 2 2 2 — 0 Max — — — — — 200 — Unit ms ms ms ms ms μs ns 22.10 22.3, 22.5 Figure 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) TRST reset hold time tIRLSTB tTRSTRH Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev.7.00 Oct. 10, 2008 Page 929 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.27 Clock and Control Signal Timing (HD6417750BP200M (V), HD6417750SBP200 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency PLL2 operating 1/2 divider operating Symbol fEX Min 16 8 2 1 15 3.5 3.5 — — 25 1 10 1 1 — — 3 3 10 10 20 20 3 20 Max 67 34 67 34 1000 — — 4 4 100 100 1000 — — 3 3 — — — — — — — — ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (2) 22.2 (2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure 1/2 divider not fEX operating PLL2 not operating 1/2 divider operating fEX 1/2 divider not fEX operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL2 operating PLL2 not operating tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time Rev.7.00 Oct. 10, 2008 Page 930 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item RESET assert time PLL synchronization settling time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tRESW tPLL tOSC2 tOSC3 tOSC4 Min 20 200 10 5 5 2 2 2 — 0 Max — — — — — — — — 200 — Unit tcyc μs ms ms ms ms ms ms μs ns 22.10 22.3, 22.5 Figure 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.4, 22.6 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) TRST reset hold time tIRLSTB tTRSTRH Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev.7.00 Oct. 10, 2008 Page 931 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.28 Clock and Control Signal Timing (HD6417750SF200 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency PLL2 operating 1/2 divider operating Symbol fEX Min 16 8 2 1 15 3.5 3.5 — — 25 1 10 1 1 — — 3 3 10 10 20 20 3 20 20 Max 67 34 67 34 1000 — — 4 4 67 67 1000 — — 3 3 — — — — — — — — — ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (2) 22.2 (2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure 1/2 divider not fEX operating PLL2 not operating 1/2 divider operating fEX 1/2 divider not fEX operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL2 operating PLL2 not operating tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time RESET assert time Rev.7.00 Oct. 10, 2008 Page 932 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item PLL synchronization settling time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tPLL tOSC2 tOSC3 tOSC4 Min 200 10 5 5 2 2 2 — 0 Max — — — — — — — 200 — Unit μs ms ms ms ms ms ms μs ns 22.10 22.3, 22.5 Figure 22.9, 22.10 22.4, 22.6 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) TRST reset hold time tIRLSTB tTRSTRH Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev.7.00 Oct. 10, 2008 Page 933 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.29 Clock and Control Signal Timing (HD6417750F167 (V), HD6417750SF167 (V)) HD6417750SF167 (V), HD6417750F167 (V): Item EXTAL clock input frequency PLL2 operating 1/2 divider operating VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF Min 16 8 2 1 18 3.5 3.5 — — 25 1 12 1 1 — — 3 3 10 10 20 20 3 20 Max 56 28 56 28 1000 — — 4 4 84 84 1000 — — 3 3 — — — — — — — — ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (2) 22.2 (2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure Symbol fEX 1/2 divider not fEX operating PLL2 not operating 1/2 divider operating fEX 1/2 divider not fEX operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL2 operating PLL2 not operating tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time Rev.7.00 Oct. 10, 2008 Page 934 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item RESET assert time PLL synchronization settling time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tRESW tPLL tOSC2 tOSC3 tOSC4 Min 20 200 10 5 5 2 2 2 — 0 Max — — — — — — — — 200 — Unit tcyc μs ms ms ms ms ms ms μs ns 22.10 22.3, 22.5 Figure 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.4, 22.6 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) TRST reset hold time tIRLSTB tTRSTRH Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev.7.00 Oct. 10, 2008 Page 935 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.30 Clock and Control Signal Timing (HD6417750SVF133 (V), HD6417750SVBT133 (V)) HD6417750SVBT133 (V): VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –30 to +70°C, CL = 30 pF HD6417750SVF133 (V): VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency PLL2 operating 1/2 divider operating Symbol fEX Min 16 8 2 1 22 3.5 3.5 — — 25 1 14 1 1 — — 3 3 10 10 20 20 3 20 Max 45 23 45 23 1000 — — 4 4 67 67 1000 — — 3 3 — — — — — — — — ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (2) 22.2 (2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure 1/2 divider not fEX operating PLL2 not operating 1/2 divider operating fEX 1/2 divider not fEX operating EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL2 operating PLL2 not operating tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time Rev.7.00 Oct. 10, 2008 Page 936 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item RESET assert time PLL synchronization settling time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tRESW tPLL tOSC2 tOSC3 tOSC4 Min 20 200 10 5 5 2 2 2 — 0 Max — — — — — — — — 200 — Unit tcyc μs ms ms ms ms ms ms μs ns 22.10 22.3, 22.5 Figure 22.3, 22.4, 22.5, 22.6, 22.11 22.9, 22.10 22.4, 22.6 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) TRST reset hold time tIRLSTB tTRSTRH Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev.7.00 Oct. 10, 2008 Page 937 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.31 Clock and Control Signal Timing (HD6417750VF128 (V)) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF Item EXTAL clock input frequency PLL2 operating 1/2 divider operating Symbol fEX Min 16 8 2 1 23 3.5 3.5 — — 25 1 15 1 1 — — 3 3 10 10 20 20 3 20 20 Max 43 22 43 22 1000 — — 4 4 64 64 1000 — — 3 3 — — — — — — — — — ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ms ms ns ns tcyc ns tcyc 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (1) 22.2 (2) 22.2 (2) 22.3, 22.5 22.3, 22.5 22.11 22.3, 22.5, 22.11 22.12 22.3, 22.5, 22.12 22.3, 22.4, 22.5, 22.6, 22.11 22.1 22.1 22.1 22.1 22.1 Unit MHz Figure 1/2 divider not fEX operating PLL2 not operating 1/2 divider operating fEX 1/2 divider not fEX operating tEXcyc tEXL tEXH tEXr tEXf fOP fOP tcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tOSCMD tSCK2RS tSCK2RH tMDRS tMDRH tRESW EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL2 operating PLL2 not operating CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time Power-on oscillation settling time/mode settling SCK2 reset setup time SCK2 reset hold time MD reset setup time MD reset hold time RESET assert time Rev.7.00 Oct. 10, 2008 Page 938 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Item PLL synchronization settling time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Symbol tPLL tOSC2 tOSC3 tOSC4 Min 200 10 5 5 2 2 2 — 0 Max — — — — — — — 200 — Unit μs ms ms ms ms ms ms μs ns 22.10 22.3, 22.5 Figure 22.9, 22.10 22.4, 22.6 22.7 22.8 Standby return oscillation settling time 1* tOSC2 Standby return oscillation settling time 2* tOSC3 Standby return oscillation settling time 3* tOSC4 IRL interrupt determination time (RTC used, standby mode) TRST reset hold time tIRLSTB tTRSTRH Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. The maximum load capacitance to be connected to CKIO pin should be 50 pF in PLL2 operation, because there is a feedback from CKIO pin. * When the oscillation settling time of a crystal resonator is lower than or equal to 1 ms. Rev.7.00 Oct. 10, 2008 Page 939 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics tEXcyc tEXH tEXL VIH 1/2VDDQ VIH VIL tEXf VIL VIH 1/2VDDQ tEXr Note: When the clock is input from the EXTAL pin Figure 22.1 EXTAL Clock Input Timing tcyc tCKOH1 tCKOL1 VOH 1/2VDDQ VOH VOL tCKOf VOL VOH 1/2VDDQ tCKOr Figure 22.2 (1) CKIO Clock Output Timing tCKOH2 tCKOL2 1.5 V 1.5 V 1.5 V Figure 22.2 (2) CKIO Clock Output Timing Rev.7.00 Oct. 10, 2008 Page 940 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Stable oscillation CKIO, internal clock VDD VDD min tRESW tOSC1 RESET tSCK2RH SCK2 tOSCMD MD8, MD7, MD2–MD0 tTRSTRH TRST tMDRH Notes: 1. Oscillation settling time when on-chip oscillator is used 2. PLL2 not operating Figure 22.3 Power-On Oscillation Settling Time Standby CKIO, internal clock tRESW tOSC2 RESET Stable oscillation Notes: 1. Oscillation settling time when on-chip oscillator is used 2. PLL2 not operating Figure 22.4 Standby Return Oscillation Settling Time (Return by RESET) Rev.7.00 Oct. 10, 2008 Page 941 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Stable oscillation Internal clock VDD VDD min tRESW tOSC1 RESET tSCK2RH SCK2 tOSCMD MD8, MD7, MD2–MD0 tTRSTRH TRST tMDRH CKIO Notes: 1. Oscillation settling time when on-chip oscillator is used 2. PLL2 operating Figure 22.5 Power-On Oscillation Settling Time Standby Internal clock tRESW tOSC2 RESET CKIO Stable oscillation Notes: 1. Oscillation settling time when on-chip oscillator is used 2. PLL2 operating Figure 22.6 Standby Return Oscillation Settling Time (Return by RESET) Rev.7.00 Oct. 10, 2008 Page 942 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Standby CKIO, internal clock tOSC3 Stable oscillation NMI Note: Oscillation settling time when on-chip oscillator is used Figure 22.7 Standby Return Oscillation Settling Time (Return by NMI) Standby CKIO, internal clock tOSC4 Stable oscillation IRL3 to IRL0 Note: Oscillation settling time when on-chip oscillator is used Figure 22.8 Standby Return Oscillation Settling Time (Return by IRL3 to IRL0) Rev.7.00 Oct. 10, 2008 Page 943 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Reset or NMI interrupt request Stable input clock EXTAL input PLL synchronization PLL output, CKIO output tPLL × 2 PLL synchronization Stable input clock Internal clock STATUS1, STATUS0 Normal Standby Normal Note: When external clock from EXTAL is input Figure 22.9 PLL Synchronization Settling Time in Case of RESET or NMI Interrupt IRL3–IRL0 interrupt request Stable input clock Stable input clock EXTAL input PLL synchronization PLL output, CKIO output tIRLSTB tPLL × 2 PLL synchronization Internal clock STATUS1, STATUS0 Normal Standby Normal Note: When external clock from EXTAL is input Figure 22.10 PLL Synchronization Settling Time in Case of IRL Interrupt Rev.7.00 Oct. 10, 2008 Page 944 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Bus idle CKIO tRESW RESET tSCK2RS tSCK2RH SCK2 Figure 22.11 Manual Reset Input Timing RESET tMDRS tMDRH MD6–MD3 Figure 22.12 Mode Input Timing Rev.7.00 Oct. 10, 2008 Page 945 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics 22.3.2 Control Signal Timing Table 22.32 Control Signal Timing (1) HD6417750 RBP240 (V) HD6417750 RBG240 (V) * Item BREQ setup time BREQ hold time BACK delay time Bus tri-state delay time Bus tri-state delay time to standby mode Bus buffer on time Bus buffer on time from standby STATUS0/1 delay time Symbol Min tBREQS tBREQH tBACKD tBOFF1 tBOFF2 2 1.5 — — — Max — — 5.3 12 2 Min 2.5 1.5 — — — HD6417750 RBP200 (V) HD6417750 RBG200 (V) * Max — — 6 12 2 Min 3.5 1.5 — — — HD6417750 RF240 (V) * Max — — 6 12 2 Min 3.5 1.5 — — — HD6417750 RF200 (V) * Max — — 6 12 2 Unit Figure ns ns ns ns tcyc 22.13 22.13 22.13 22.13 22.14 (2) Notes tBON1 tBON2 — — 12 2 — — 12 2 — — 12 2 — — 12 2 ns tcyc 22.13 22.14 (2) 22.14 (1) 22.14 (1), (2) 22.14 (2) tSTD1 tSTD2 tSTD3 — — — 6 2 2 — — — 6 2 2 — — — 6 2 2 — — — 6 2 2 ns tcyc tcyc Note: * VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on Rev.7.00 Oct. 10, 2008 Page 946 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.32 Control Signal Timing (2) HD6417750 F167 (V) HD6417750 SVF133 (V) HD6417750 VF128 (V) *1 Item BREQ setup time BREQ hold time BACK delay time Bus tri-state delay time Bus tri-state delay time to standby mode Bus buffer on time Bus buffer on time from standby STATUS0/1 delay time Symbol Min tBREQS tBREQH tBACKD tBOFF1 tBOFF2 3.5 1.5 — — — Max — — 10 15 2 Min 3.5 1.5 — — — HD6417750 SVBT133 (V) *1 Max — — 10 15 2 Min 3.5 1.5 — — — HD6417750 SF167 (V) HD6417750 SF200 (V) *2 Max — — 8 12 2 Min 3 1.5 — — — HD6417750 BP200M (V) HD6417750 SBP200 (V) *3 Max — — 6 10 2 Unit Figure ns ns ns ns tcyc 22.13 22.13 22.13 22.13 22.14 (2) Notes tBON1 tBON2 — — 12 2 — — 12 2 — — 12 2 — — 12 2 ns tcyc 22.13 22.14 (2) 22.14 (1) 22.14 (1), (2) 22.14 (2) tSTD1 tSTD2 tSTD3 — — — 6 2 2 — — — 6 2 2 — — — 6 2 2 — — — 6 2 2 ns tcyc tcyc Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 2. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on Rev.7.00 Oct. 10, 2008 Page 947 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics CKIO tBREQH BREQ tBACKD BACK A[25-0], CSn, BS, RD/WR, CE2A, CE2B, RD/WR2, RAS, RAS2, WEn, RD RD2 tBOFF1 tBON1 tBACKD tBREQS tBREQH tBREQS Figure 22.13 Control Signal Timing Normal operation Reset or sleep mode Normal operation CKIO STATUS1, STATUS0 normal tSTD2 reset or sleep tSTD1 normal Figure 22.14 (1) Pin Drive Timing for Reset or Sleep Mode Rev.7.00 Oct. 10, 2008 Page 948 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Normal operation Software standby mode Normal operation CKIO STATUS1, STATUS0 normal tSTD2 CSn, RD, RD/WR, WEn, BS, RAS, CE2A, CE2B, CASn software standby tSTD3 normal tBOFF2 tBON2 A25−A0, D31−D0 DACKn, DRAKn, SCK, TXD, TXD2, CTS2, RTS2 Note: * These pins can be put into the state od high-impedance with STBCR. * Figure 22.14 (2) Pin Drive Timing for Software Standby Mode Rev.7.00 Oct. 10, 2008 Page 949 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics 22.3.3 Bus Timing Table 22.33 Bus Timing (1) HD6417750 RBP240 (V) HD6417750 RBG240 (V) * Item Address delay time BS delay time CS delay time RW delay time RD delay time Read data setup time Read data hold time WE delay time (falling edge) Symbol tAD tBSD tCSD tRWD tRSD tRDS tRDH tWEDF Min 1.5 1.5 1.5 1.5 1.5 2 1.5 — Max 5.3 5.3 5.3 5.3 5.3 — — 5.3 Min 1.5 1.5 1.5 1.5 1.5 2.5 1.5 — HD6417750 RBP200 (V) HD6417750 RBG200 (V) * Max 6 6 6 6 6 — — 6 Min 1.5 1.5 1.5 1.5 1.5 3.5 1.5 — HD6417750 RF240 (V) * Max 6 6 6 6 6 — — 6 Min 1.5 1.5 1.5 1.5 1.5 3.5 1.5 — HD6417750 RF200 (V) * Max 6 6 6 6 6 — — 6 Unit ns ns ns ns ns ns ns ns Relative to CKIO falling edge Notes WE delay time Write data delay time RDY setup time RDY hold time RAS delay time CAS delay time 1 CAS delay time 2 CKE delay time DQM delay time FRAME delay time IOIS16 setup time IOIS16 hold time ICIOWR delay time (falling edge) ICIORD delay time tWED1 tWDD tRDYS tRDYH tRASD tCASD1 tCASD2 tCKED tDQMD tFMD tIO16S tIO16H tICWSDF tICRSD 1.5 1.5 2 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2 1.5 1.5 1.5 5.3 5.3 — — 5.3 5.3 5.3 5.3 5.3 5.3 — — 5.3 5.3 1.5 1.5 2.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 1.5 1.5 6 6 — — 6 6 6 6 6 6 — — 6 6 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.5 1.5 1.5 1.5 6 6 — — 6 6 6 6 6 6 — — 6 6 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.5 1.5 1.5 1.5 6 6 — — 6 6 6 6 6 6 — — 6 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns DRAM SDRAM SDRAM SDRAM MPX PCMCIA PCMCIA PCMCIA PCMCIA Rev.7.00 Oct. 10, 2008 Page 950 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics HD6417750 RBP240 (V) HD6417750 RBG240 (V) * Item DACK delay time DACK delay time (falling edge) Symbol tDACD tDACDF Min 1.5 1.5 Max 5.3 5.3 Min 1.5 1.5 HD6417750 RBP200 (V) HD6417750 RBG200 (V) * Max 6 6 Min 1.5 1.5 HD6417750 RF240 (V) * Max 6 6 Min 1.5 1.5 HD6417750 RF200 (V) * Max 6 6 Unit ns ns Relative to CKIO falling edge Notes DTR setup time DTR hold time DBREQ setup time DBREQ hold time TR setup time TR hold time BAVL delay time TDACK delay time ID1, ID0 delay time tDTRS tDTRH tDBQS tDBQH tTRS tTRH tBAVD tTDAD tIDD 2.0 1.5 2.0 1.5 2.0 1.5 1.5 1.5 1.5 — — — — — — 5.3 5.3 5.3 2.5 1.5 2.5 1.5 2.5 1.5 1.5 1.5 1.5 — — — — — — 6 6 6 3.5 1.5 3.5 1.5 3.5 1.5 1.5 1.5 1.5 — — — — — — 6 6 6 3.5 1.5 3.5 1.5 3.5 1.5 1.5 1.5 1.5 — — — — — — 6 6 6 ns ns ns ns ns ns ns ns ns Note: * VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on Rev.7.00 Oct. 10, 2008 Page 951 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.33 Bus Timing (2) HD6417750S VF133 (V) HD6417750S VBT133 (V) *1 Item Address delay time BS delay time CS delay time RW delay time RD delay time Symbol tAD tBSD tCSD tRWD tRSD Min 1.5 1.5 1.5 1.5 1.5 3.5 1.5 — 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 3.5 1.5 Max 10 10 10 10 10 — — 10 10 10 — — 10 10 10 10 10 10 — — 10 10 10 10 — — Min 1.5 1.5 1.5 1.5 1.5 3.5 1.5 — 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.5 1.5 1.5 1.5 1.5 1.5 3.5 1.5 HD6417750S F167 (V) HD6417750S F200 (V) *2 Max 8 8 8 8 8 — — 8 8 8 — — 8 8 8 8 8 8 — — 8 8 8 8 — — Min 1.5 1.5 1.5 1.5 1.5 3 1.5 — 1.5 1.5 3 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3 1.5 1.5 1.5 1.5 1.5 3 1.5 HD6417750S BP200 (V) *3 Max 6 6 6 6 6 — — 6 6 6 — — 6 6 6 6 6 6 — — 6 6 6 6 — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Relative to CKIO falling edge DRAM SDRAM SDRAM SDRAM MPX PCMCIA PCMCIA PCMCIA PCMCIA Relative to CKIO falling edge Notes Read data setup time tRDS Read data hold time WE delay time (falling edge) WE delay time RDY setup time RDY hold time RAS delay time CAS delay time 1 CAS delay time 2 CKE delay time DQM delay time FRAME delay time IOIS16 setup time IOIS16 hold time ICIOWR delay time (falling edge) ICIORD delay time DACK delay time DACK delay time (falling edge) DTR setup time DTR hold time tRDH tWEDF tWED1 Write data delay time tWDD tRDYS tRDYH tRASD tCASD1 tCASD2 tCKED tDQMD tFMD tIO16S tIO16H tICWSDF tICRSD tDACD tDACDF tDTRS tDTRH Rev.7.00 Oct. 10, 2008 Page 952 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics HD6417750S VF133 (V) HD6417750S VBT133 (V) *1 Item DBREQ setup time DBREQ hold time TR setup time TR hold time BAVL delay time TDACK delay time ID1, ID0 delay time Symbol tDBQS tDBQH tTRS tTRH tBAVD tTDAD tIDD Min 3.5 1.5 3.5 1.5 1.5 1.5 1.5 Max — — — — 10 10 10 Min 3.5 1.5 3.5 1.5 1.5 1.5 1.5 HD6417750S F167 (V) HD6417750S F200 (V) *2 Max — — — — 8 8 8 Min 3 1.5 3 1.5 1.5 1.5 1.5 HD6417750S BP200 (V) *3 Max — — — — 6 6 6 Unit ns ns ns ns ns ns ns Notes Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 2. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on Rev.7.00 Oct. 10, 2008 Page 953 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.33 Bus Timing (3) HD6417750 VF128 (V) *1 Item Address delay time BS delay time CS delay time RW delay time RD delay time Read data setup time Read data hold time WE delay time (falling edge) WE delay time Write data delay time RDY setup time RDY hold time RAS delay time CAS delay time 1 CAS delay time 2 CKE delay time DQM delay time FRAME delay time IOIS16 setup time IOIS16 hold time ICIOWR delay time (falling edge) ICIORD delay time DACK delay time DACK delay time (falling edge) Symbol tAD tBSD tCSD tRWD tRSD tRDS tRDH tWEDF tWED1 tWDD tRDYS tRDYH tRASD tCASD1 tCASD2 tCKED tDQMD tFMD tIO16S tIO16H tICWSDF tICRSD tDACD tDACDF Min 1.3 1.3 1.3 1.3 1.3 3.5 1.5 — 1.3 1.3 3.5 1.5 1.3 1.3 1.3 0.5 1.3 1.3 3.5 1.5 1.3 1.3 1.3 1.3 Max 10 10 10 10 10 — — 10 10 10 — — 10 10 10 10 10 10 — — 10 10 10 10 Min 1.3 1.3 1.3 1.3 1.3 3.5 1.5 — 1.3 1.3 3.5 1.5 1.3 1.3 1.3 0.5 1.3 1.3 3.5 1.5 1.3 1.3 1.3 1.3 HD6417750 F167 (V) *2 Max 8 8 8 8 8 — — 8 8 8 — — 8 8 8 8 8 8 — — 8 8 8 8 Min 1.2 1.2 1.2 1.2 1.2 3 1.5 — 1.2 1.2 3 1.5 1.2 1.2 1.2 0.5 1.2 1.2 3 1.5 1.2 1.2 1.2 1.2 HD6417750 BP200M (V) *3 Max 6 6 6 6 6 — — 6 6 6 — — 6 6 6 6 6 6 — — 6 6 6 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Relative to CKIO falling edge DRAM SDRAM SDRAM SDRAM MPX PCMCIA PCMCIA PCMCIA PCMCIA Relative to CKIO falling edge Notes Rev.7.00 Oct. 10, 2008 Page 954 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics HD6417750 VF128 (V) *1 Item DTR setup time DTR hold time DBREQ setup time DBREQ hold time TR setup time TR hold time BAVL delay time TDACK delay time ID1, ID0 delay time Symbol tDTRS tDTRH tDBQS tDBQH tTRS tTRH tBAVD tTDAD tIDD Min 3.5 1.5 3.5 1.5 3.5 1.5 1.3 1.3 1.3 Max — — — — — — 10 10 10 Min 3.5 1.5 3.5 1.5 3.5 1.5 1.3 1.3 1.3 HD6417750 F167 (V) *2 Max — — — — — — 8 8 8 Min 3 1.5 3 1.5 3 1.5 1.2 1.2 1.2 HD6417750 BP200M (V) *3 Max — — — — — — 6 6 6 Unit ns ns ns ns ns ns ns ns ns Notes Notes: 1. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 2. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on Rev.7.00 Oct. 10, 2008 Page 955 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics T1 CKIO T2 tAD A25–A0 tAD tCSD CSn tCSD tRWD RD/WR tRWD tRSD RD tRSD tRSD D63–D0 (read) tRDS tWED1 tRDH tWEDF tWEDF WEn tWDD D63–D0 (write) tWDD tWDD tBSD BS tBSD RDY tDACD DACKn (SA: IO ← memory) tDACD tDACD tDACDF DACKn (SA: IO → memory) tDACDF tDACD DACKn (DA) tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait) Rev.7.00 Oct. 10, 2008 Page 956 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics T1 CKIO Tw T2 tAD A25–A0 tAD tCSD CSn tCSD tRWD RD/WR tRWD tRSD RD tRSD tRSD D63–D0 tRDS tWED1 tRDH (read) tWEDF tWEDF WEn tWDD D63–D0 tWDD tWDD (write) tBSD BS tBSD tRDYS RDY tRDYH tDACD DACKn (SA: IO ← memory) tDACD tDACD tDACDF DACKn (SA: IO → memory) tDACDF tDACD DACKn (DA) tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) Rev.7.00 Oct. 10, 2008 Page 957 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics T1 CKIO Tw Twe T2 tAD A25–A0 tAD tCSD CSn tCSD tRWD RD/WR tRWD tRSD RD tRSD tRSD D63–D0 (read) tRDS tWED1 tRDH tWEDF tWEDF WEn tWDD D63–D0 (write) tWDD tWDD tBSD BS tBSD tRDYS RDY tRDYH tRDYS tRDYH tDACD tDACD DACKn (SA: IO ← memory) tDACD tDACDF DACKn (SA: IO → memory) tDACDF tDACD DACKn (DA) tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.17 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) Rev.7.00 Oct. 10, 2008 Page 958 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics TS1 CKIO T1 T2 TH1 tAD A25–A0 tAD CSn tCSD tCSD tRWD RD/WR tRWD tRSD RD tRSD * tRSD D63–D0 (read) tRDS tWED1 tRDH WEn tWEDF tWEDF tWDD D63–D0 (write) tWDD tWDD tBSD BS tBSD RDY tDACD DACKn (SA: IO ← memory) tDACD tDACD tDACDF DACKn (SA: IO → memory) tDACDF DACKn (DA) tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Note: * SH7750R only Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) Rev.7.00 Oct. 10, 2008 Page 959 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics T1 CKIO TB2 TB1 TB2 TB1 TB2 TB1 T2 tAD A25–A5 tAD tAD A4–A0 tCSD CSn tCSD tRWD tRSD tRDH tRDS tRSD tRDH tRWD RD/WR RD D63–D0 (read) BS RDY DACKn (SA: IO ← memory) DACKn (DA) tRSD tRDS tBSD tBSD tDACD tDACD tDACD tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.19 Burst ROM Bus Cycle (No Wait) Rev.7.00 Oct. 10, 2008 Page 960 of 1074 REJ09B0366-0700 T1 Tw Twe TB2 TB1 Twb TB2 TB1 Twb TB2 TB1 Twb T2 CKIO tAD tAD tCSD tRWD tRSD tRDS tRDH tBSD tRDYS tDACD tDACD tDACD tRDYS tRDYH tDACD tRDYH tRDYS tRSD tRDS tCSD tAD A25–A5 A4–A0 CSn tRWD RD/WR RD tRDH D63–D0 (read) BS tRDYH RDY DACKn (SA: IO ← memory) DACKn (DA) Figure 22.20 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait) Section 22 Electrical Characteristics Rev.7.00 Oct. 10, 2008 Page 961 of 1074 REJ09B0366-0700 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high TS1 T1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 T2 TH1 CKIO tAD tAD tAD A25–A5 A4–A0 tCSD tCSD tRWD tRSD tRDS tBSD tRDH tRDS tRDH tRSD CSn Section 22 Electrical Characteristics tRWD Rev.7.00 Oct. 10, 2008 Page 962 of 1074 REJ09B0366-0700 tDACD tDACD tDACD RD/WR RD D63–D0 (read) tBSD BS RDY DACKn (SA: IO ← memory) tDACD DACKn (DA) tDACD Figure 22.21 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high T1 Tw Twe TB2 TB1 Twb Twbe TB2 TB1 Twb Twb Twbe TB2 TB1 Twbe T2 CKIO tAD tAD tAD A25–A5 A4–A0 CSn tCSD tCSD tRWD tRSD tRDS tBSD tRDH tBSD tBSD tRDS tRSD tRDH RD/WR tRWD tRSD RD D63–D0 (read) tBSD BS tRDYS tRDYS tDACD tDACD tRDYH tRDYH tRDYS tRDYH tRDYS tRDYH RDY DACKn (SA: IO ← memory) tDACD DACKn (DA) tDACD tDACD Figure 22.22 Burst ROM Bus Cycle (One Internal Wait + One External Wait) Legend: Section 22 Electrical Characteristics Rev.7.00 Oct. 10, 2008 Page 963 of 1074 REJ09B0366-0700 IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr CKIO Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Tpc Tpc Tpc tAD BANK Row tAD tAD Precharge-sel Row H/L Address Row column tCSD CSn tCSD tRWD tRASD tCASD2 tCASD2 tRWD RD/WR Section 22 Electrical Characteristics tRASD RAS Rev.7.00 Oct. 10, 2008 Page 964 of 1074 REJ09B0366-0700 tCASD2 CASS tDQMD DQMn tDQMD tRDS tRDH d0 D63–D0 (read) tWDD tWDD tBSD tBSD D63–D0 (write) BS CKE tDACD DACKn (SA: IO ← memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.23 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) tDACD tDACD Tr CKIO Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Tpc Tpc Tpc tAD tAD tAD Precharge-sel Row H/L BANK Row Address Row c0 CSn tCSD tRWD tRWD tRASD tCASD2 tCASD2 tCSD RD/WR tRASD RAS tCASD2 CASS tDQMD DQMn tDQMD tRDH d0 d1 d2 d3 D63–D0 (read) tRDS tWDD D63–D0 (write) BS tWDD tBSD tBSD CKE tDACD DACKn (SA: IO ← memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.24 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) tDACD tDACD Section 22 Electrical Characteristics Rev.7.00 Oct. 10, 2008 Page 965 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Tr CKIO Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 tAD BANK Row tAD tAD H/L tRWD Precharge-sel Row tRWD Address Row c0 CSn tCSD tRWD tRASD tRASD tCSD tRWD RD/WR RAS tCASD2 tCASD2 CASS tCASD2 tDQMD tDQMD DQMn D63–D0 (read) D63–D0 (write) tRDS d0 tRDH d1 d2 d3 tWDD tBSD tBSD tWDD BS CKE tDACD DACKn (SA: IO ← memory) tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RASD = 1, RCD[1:0] = 01, CAS Latency = 3) Rev.7.00 Oct. 10, 2008 Page 966 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Tpr CKIO Tpc Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 tAD BANK tAD Row tAD tAD Precharge-sel Row H/L Address Row c0 CSn tCSD tRWD tRWD tCSD RD/WR tRASD tRASD tRASD tRASD RAS tCASD2 CASS tCASD2 tDQMD tCASD2 tDQMD DQMn D63–D0 (read) D63–D0 (write) BS tRDS d0 tRDH d1 d2 d3 tWDD tBSD tBSD tWDD CKE DACKn (SA: IO ← memory) tDACD tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.26 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst ((RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, CAS Latency = 3) Rev.7.00 Oct. 10, 2008 Page 967 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Tc1 CKIO Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 tAD BANK Row tAD Precharge-sel H/L Address c0 tCSD CSn tCSD tRWD RD/WR tRWD tRASD RAS tRASD tCASD2 CASS tCASD2 tDQMD DQMn tDQMD D63–D0 (read) tRDS d0 tRDH d1 d2 d3 D63–D0 (write) tWDD tWDD tBSD BS tBSD CKE tDACD DACKn (SA: IO ← memory) tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.27 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst ((RASD = 1, CAS Latency = 3) Rev.7.00 Oct. 10, 2008 Page 968 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Tr CKIO Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Tpc tAD BANK Row tAD tAD Precharge-sel Row H/L Address Row Column tCSD CSn tCSD tRWD RD/WR tRWD tRASD RAS tRASD tCASD2 tCASD2 tCASD2 CASS tDQMD DQMn tDQMD tWDD D63–D0 (write) tWDD c0 tWDD BS tBSD tBSD CKE DACKn (SA: IO → memory) tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.28 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) Rev.7.00 Oct. 10, 2008 Page 969 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Tr CKIO Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Tpc tAD BANK Row tAD tAD Precharge-sel Row H/L Address Row c0 CSn tCSD tRWD tRWD tCSD RD/WR tRASD RAS tRASD tCASD2 tCASD2 tCASD2 CASS tDQMD DQMn tDQMD tWDD tWDD D63–D0 (write) d0 tWDD d1 d2 d3 BS tBSD tBSD CKE DACKn (SA: IO → memory) tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) Rev.7.00 Oct. 10, 2008 Page 970 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Tr CKIO Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl tAD BANK Row tAD tAD Precharge-sel Row H/L Address Row c0 tCSD CSn tCSD tRWD RD/WR tRWD tRASD RAS tRASD tCASD2 tCASD2 tCASD2 CASS tDQMD DQMn tDQMD tWDD D63–D0 (write) tWDD d0 tWDD d1 d2 d3 BS tBSD tBSD CKE tDACD DACKn tDACD (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RASD = 1, RCD[1:0] = 01, TRWL[2:0] = 010) Rev.7.00 Oct. 10, 2008 Page 971 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Tpr CKIO Tpc Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl tAD BANK Row tAD Row tAD tAD Precharge-sel H/L Row H/L Address Row c0 CSn tCSD tRWD tRWD tRASD tRASD tRASD tCASD2 tCASD2 tRWD tRWD tCSD RD/WR tRASD RAS tCASD2 CASS tDQMD DQMn tDQMD tWDD D63–D0 (write) tWDD d0 tWDD d1 d2 d3 BS tBSD tBSD CKE tDACD DACKn (SA: IO → memory) tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RASD = 1, RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010) Rev.7.00 Oct. 10, 2008 Page 972 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Tnop CKIO (Tnop) Tc1 Tc2 Tc3 Tc4 Trwl Trwl tAD BANK Row tAD Precharge-sel H/L Address c0 tCSD CSn tCSD tRWD RD/WR tRWD RAS tCASD2 CASS tCASD2 tDQMD DQMn tDQMD tWDD tWDD D63–D0 (write) d0 tWDD d1 d2 d3 tBSD BS tBSD CKE tDACD DACKn (SA: IO → memory) SA-DMA tDACD Normal write Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as shown by the dotted line. Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (RASD = 1, TRWL[2:0] = 010) Rev.7.00 Oct. 10, 2008 Page 973 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Tpr CKIO Tpc tAD BANK Row tAD Precharge-sel H/L Address tCSD CSn tCSD tRWD RD/WR tRWD tRASD RAS tRASD tCASD2 CASS tCASD2 tDQMD DQMn tDQMD D63–D0 (write) tWDD tWDD tBSD BS CKE tDACD DACKn tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command (RASD = 1, TPC[2:0] = 001) Rev.7.00 Oct. 10, 2008 Page 974 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics TRr1 CKIO TRr2 TRr3 TRr4 TRrw TRr5 Trc Trc Trc tAD BANK tAD Precharge-sel Address tCSD CSn tCSD tCSD tCSD tRWD RD/WR tRWD tRASD RAS tRASD tRASD tRASD tCASD2 CASS tCASD2 tCASD2 tCASD2 tDQMD DQMn tDQMD D63–D0 (write) tWDD tWDD tBSD BS CKE tDACD DACKn tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh (TRAS = 1, TRC[2:0] = 001) Rev.7.00 Oct. 10, 2008 Page 975 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics TRs1 CKIO TRs2 TRs3 TRs4 TRs5 Trc Trc Trc tAD BANK tAD Precharge-sel Address tCSD tCSD CSn tCSD tCSD tRWD RD/WR tRWD tRASD tRASD RAS tRASD tRASD tCASD2 CASS tCASD2 tCASD2 tCASD2 tDQMD DQMn tDQMD tWDD D63–D0 (write) tWDD tBSD BS tCKED CKE tCKED tDACD tDACD DACKn Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh (TRC[2:0] = 001) Rev.7.00 Oct. 10, 2008 Page 976 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics TRp1 CKIO TRp2 TRp3 TRp4 TMw TMw2 TMw3 TMw4 TMw5 tAD BANK tAD tAD Precharge-sel Address tCSD CSn tCSD tRWD tRASD tCSD tRWD tRASD tRWD RD/WR tRASD RAS tCASD2 CASS tCASD2 tCASD2 tCASD2 tDQMD DQMn tDQMD D63–D0 (write) tWDD tWDD tBSD BS CKE tDACD DACKn tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.36 (a) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (PALL) Rev.7.00 Oct. 10, 2008 Page 977 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics TRp1 CKIO TRp2 TRp3 TRp4 TMw TMw2 TMw3 TMw4 TMw5 tAD BANK tAD tAD Precharge-sel Address tCSD CSn tCSD tRWD tRASD tCSD tRWD tRASD tRWD RD/WR tRASD RAS tCASD2 CASS tCASD2 tCASD2 tCASD2 tDQMD DQMn tDQMD D63–D0 (write) tWDD tWDD tBSD BS CKE tDACD DACKn tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.36 (b) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (SET) Rev.7.00 Oct. 10, 2008 Page 978 of 1074 REJ09B0366-0700 Tr1 Tc1 Tc2 Tr2 Tpc Tr1 Tr2 Trw Tc1 Tcw Tc2 Tpc Tpc CKIO tAD tAD tAD tAD column tAD tAD tCSD tRWD tRASD tCASD1 tRASD column Row A25–A0 Row tCSD tRWD tRASD tRASD tRASD tRWD tCSD tCSD CSn tRWD RD/WR tRASD RAS tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 CASn D63–D0 (read) tRDS tWDD tWDD tWDD tWDD tRDH tRDS tRDH tWDD D63–D0 (write) tWDD BS tBSD tBSD tBSD tBSD DACKn (SA: IO ← memory) tDACD tDACD tDACD tDACD tDACD tDACD Figure 22.37 DRAM Bus Cycles (1) RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001 (2) RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 010 tDACD tDACD tDACD tDACD tDACD (1) (2) tDACD DACKn (SA: IO → memory) Section 22 Electrical Characteristics Rev.7.00 Oct. 10, 2008 Page 979 of 1074 REJ09B0366-0700 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Section 22 Electrical Characteristics T1r CKIO Tr2 Tc1 Tc2 Tce Tpc tAD A25–A0 Row tAD Column tAD tCSD CSn tCSD tRWD RD/WR tRWD RAS tRASD tRASD tRASD CASn tCASD1 tCASD1 tCASD1 D63–D0 (read) tRDS tRDH tWDD D63–D0 (write) tBSD BS tBSD DACKn (SA: IO ← memory) tDACD tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) Rev.7.00 Oct. 10, 2008 Page 980 of 1074 REJ09B0366-0700 T1r Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce Tpc CKIO tAD Row c0 c1 c2 c3 tAD tAD tAD A25–A0 tCSD tCSD CSn tRWD tRWD RD/WR tRASD tRASD tRASD RAS CASn tRWD tCASD1 tCASD1 tCASD1 tCASD1 D63–D0 (read) d0 d1 tRDS tWDD tRDH d2 tRDS d3 tRDH D63–D0 (write) tBSD tBSD tBSD tBSD Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) tDACD tDACD tDACD BS Section 22 Electrical Characteristics Rev.7.00 Oct. 10, 2008 Page 981 of 1074 REJ09B0366-0700 DACKn (SA: IO ← memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr1 Tr2 Trw Tc1 Tcw Tc2 Tc1 Tcw Tc2 Tc1 Tc1 Tcw Tc2 Tcw Tc2 Tce Tpc CKIO tAD tAD c0 c1 c2 c3 Row tAD tCSD tRWD tRASD tCASD1 tCASD1 A25–A0 tCSD CSn tRWD RD/WR Section 22 Electrical Characteristics tRASD tRASD RAS Rev.7.00 Oct. 10, 2008 Page 982 of 1074 REJ09B0366-0700 tCASD1 tCASD1 tCASD1 tRDS d0 d1 tCASD1 CASn D63–D0 (read) tRDH d2 tRDS d3 tRDH D63–D0 (write) tWDD tBSD tBSD BS tDACD tDACD tDACD Figure 22.40 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001) DACKn (SA: IO ← memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr1 Tcw Tr2 Trw Tc1 Tcw Tc2 Tcnw Tc1 Tcw Tc2 Tc2 Tcnw Tce Tpc Tcnw Tc1 Tc2 Tcnw Tc1 Tcw CKIO tAD tAD Row c0 c1 c2 c3 tAD tCSD tRWD A25–A0 CSn tCSD RD/WR tRWD tRASD tCASD1 tRDS d0 d1 tRASD RAS tRASD tCASD1 tRDH tCASD1 tRDS d2 d3 tCASD1 CASn tCASD1 tRDH D63–D0 (read) D63–D0 (write) tWDD tBSD tBSD BS DACKn (SA: IO ← memory) tDACD t DACD tDACD Figure 22.41 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width) Section 22 Electrical Characteristics Rev.7.00 Oct. 10, 2008 Page 983 of 1074 REJ09B0366-0700 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tpc Tr2 Tc1 Tc2 Tc1 Tc2 Tr1 Tc1 Tc2 Tc1 Tc2 Tce CKIO tAD Row c0 c1 c2 c3 tAD tCSD tAD tAD A25–A0 tCSD CSn tRWD tRWD Section 22 Electrical Characteristics RD/WR tRASD tRASD tCASD1 tCASD1 Rev.7.00 Oct. 10, 2008 Page 984 of 1074 REJ09B0366-0700 tCASD1 tCASD1 tCASD1 tRDS d0 RAS CASn D63–D0 (read) tRDH d1 d2 tRDS d3 tRDH tWDD tBSD D63–D0 (write) tBSD tBSD tBSD BS Figure 22.42 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000) tDACD tDACD tDACD DACKn (SA: IO ← memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce CKIO tAD c0 c1 c2 c3 tAD tCSD tAD A25–A0 tCSD CSn tRWD tRWD RAS-down mode ended RD/WR tRASD tCASD1 tCASD1 RAS tCASD1 tCASD1 tCASD1 CASn D63–D0 (read) d0 d1 tRDS tWDD tRDH d2 tRDS d3 tRDH D63–D0 (write) tBSD tBSD tBSD tBSD BS tDACD tDACD Figure 22.43 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000) Section 22 Electrical Characteristics Rev.7.00 Oct. 10, 2008 Page 985 of 1074 REJ09B0366-0700 DACKn (SA: IO ← memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tpc CKIO tAD Row c0 c1 c2 c3 tAD tAD A25–A0 tCSD tCSD CSn tRWD tRWD RD/WR Section 22 Electrical Characteristics tRASD tRASD tRASD RAS Rev.7.00 Oct. 10, 2008 Page 986 of 1074 REJ09B0366-0700 tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 tRDS d0 d1 CASn D63–D0 (read) tRDH d2 tRDS d3 tRDH tWDD tWDD d0 d1 tWDD d2 d3 D63–D0 (write) tWDD tBSD tBSD BS tDACD tDACD tDACD DACKn (SA: IO ← memory) Figure 22.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) tDACD tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr1 Tr2 Trw Tc1 Tcw Tc2 Tc1 Tcw Tc2 Tc1 Tcw Tc2 Tc2 Tc1 Tcw Tpc CKIO tAD tAD Row c0 c1 c2 c3 tAD tCSD tRWD A25–A0 CSn tCSD RD/WR tRWD tRASD tCASD1 tCASD1 tRDH d0 d1 d2 tRASD tRASD tCASD1 tRDS d3 RAS tCASD1 tRDS tWDD d0 d1 tCASD1 tRDH tWDD CASn D63–D0 (read) tWDD tWDD D63–D0 (write) d2 d3 tBSD tBSD tDACD tDACD tDACD tDACD BS tDACD DACKn (SA: IO ← memory) tDACD Figure 22.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001) DACKn (SA: IO → memory) Section 22 Electrical Characteristics Rev.7.00 Oct. 10, 2008 Page 987 of 1074 REJ09B0366-0700 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tr1 Tr2 Trw Tc1 Tcw Tc2 Tcnw Tc1 Tc1 Tcw Tc2 Tcw Tc2 Tcnw Tpc Tcw Tcnw Tc2 Tcnw Tc1 CKIO tAD tAD c0 c1 c2 c3 Row tAD tCSD tRWD tRASD tCASD1 tRDS d0 d1 A25–A0 CSn tCSD RD/WR tRWD Section 22 Electrical Characteristics tRASD tCASD1 tRDH d2 d2 d3 tRASD tCASD1 tRDS d3 d1 RAS Rev.7.00 Oct. 10, 2008 Page 988 of 1074 REJ09B0366-0700 tCASD1 tRDH tWDD tWDD tWDD d0 CASn tCASD1 D63–D0 (read) tWDD D63–D0 (write) tBSD tBSD tDACD tDACD tDACD tDACD BS tDACD DACKn (SA: IO ← memory) tDACD DACKn (SA: IO → memory) Figure 22.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tpc CKIO Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 tAD tAD Row c0 c1 c2 c3 tAD tAD tCSD tRWD A25–A0 tCSD CSn tCSD tRWD tRASD tCASD1 tCASD1 tCASD1 tRWD RD/WR tRASD RAS tCASD1 CASn tCASD1 D63–D0 (read) tRDS tWDD tWDD d0 d0 tRDH d1 d2 tRDS d3 tRDH tWDD tWDD d1 d2 d3 D63–D0 (write) tBSD BS tBSD tDACD DACKn (SA: IO ← memory) tDACD tDACD tDACD tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.47 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000) Section 22 Electrical Characteristics Rev.7.00 Oct. 10, 2008 Page 989 of 1074 REJ09B0366-0700 Tnop CKIO Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 tAD tAD c0 c1 c2 c3 A25–A0 tCSD CSn tCSD tRWD tCSD tRWD tRASD tCASD1 tCASD1 RD/WR tRWD Section 22 Electrical Characteristics RAS down mode ended RAS Rev.7.00 Oct. 10, 2008 Page 990 of 1074 REJ09B0366-0700 tCASD1 CASn tCASD1 tCASD1 tRDS tRDH d0 tRDS d1 d2 d3 D63–D0 (read) tRDH tWDD tWDD tWDD d0 tWDD d1 d2 d3 D63–D0 (write) tBSD BS tBSD tDACD DACKn (SA: IO ← memory) tDACD tDACD tDACD tDACD tDACD DACKn (SA: IO → memory) Figure 22.48 DRAM Burst Bus Cycle: RAS Down Mode Continuation (Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Section 22 Electrical Characteristics TRr1 CKIO TRr2 TRr3 TRr4 TRr5 Trc Trc Trc tAD A25–A0 tCSD CSn tRWD RD/WR tRASD RAS tRASD tRASD tCASD1 CASn tCASD1 tCASD1 tWDD D63–D0 (write) BS DACKn (SA: IO ← memory) tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 000, TRC[2:0] = 001) Rev.7.00 Oct. 10, 2008 Page 991 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics TRr1 CKIO TRr2 TRr3 TRr4 TRr4w TRr5 Trc Trc Trc tAD A25–A0 tCSD CSn tRWD RD/WR tRASD RAS tRASD tRASD tCASD1 CASn tCASD1 tCASD1 tWDD D63–D0 (write) BS DACKn (SA: IO ← memory) tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS[2:0] = 001, TRC[2:0] = 001) Rev.7.00 Oct. 10, 2008 Page 992 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics TRr1 CKIO TRr2 TRr3 TRr4 TRr5 Trc Trc Trc tAD A25–A0 tCSD CSn tRWD RD/WR tRASD RAS tRASD tRASD tCASD1 tCASD1 CASn tCASD1 tWDD D63–D0 (write) BS DACKn (SA: IO ← memory) tDACD tDACD DACKn (SA: IO → memory) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001) Rev.7.00 Oct. 10, 2008 Page 993 of 1074 REJ09B0366-0700 Tpcm1 Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO Tpcm2 tAD A25–A0 tAD tCSD tRWD tRWD tCSD tCSD tRWD tAD tAD tCSD CExx REG (WE7) tRWD RD/WR tRSD tRSD tRSD RD D15–D0 (read) Section 22 Electrical Characteristics tRSD tRDS tRDH tWEDF tWEDF tWDD tWDD tBSD tBSD tRDYS tRDYH tDACD tRDYS tWDD tWED1 tRSD * tRDS tWEDF tRDH Rev.7.00 Oct. 10, 2008 Page 994 of 1074 REJ09B0366-0700 tRSD tWED1 tWEDF tWDD WE1 D15–D0 (write) tWDD tBSD tWDD BS tBSD RDY tDACD DACKn (DA) tDACD tRDYH tDACD TED TEH Figure 22.52 PCMCIA Memory Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait (1) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Note: *: SH7750S and SH7750R (2) Tpci1 Tpci0 Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO Tpci2 tAD A25–A0 tAD tCSD tRWD tRWD tCSD tCSD tRWD tAD tAD tCSD CExx REG (WE7) tRWD RD/WR tICRSD tICRSD tICRSD tICRSD tRDH tICWSDF tICWSDF tWDD ICIORD (WE2) D15–D0 (read) tICRSD tRDS tICWSDF tICWSDF tRDS tRDH tICWSDF tWDD ICIOWR (WE3) tWDD tWDD tWDD tBSD tBSD D15–D0 (write) tBSD BS RDY tBSD tRDYS tIO16S tIO16H tDACD tDACD IOIS16 tRDYH tRDYS tIO16S tRDYH tIO16H tDACD tDACD DACKn (DA) Figure 22.53 PCMCIA I/O Bus Cycle (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait + One External Wait (1) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Section 22 Electrical Characteristics Rev.7.00 Oct. 10, 2008 Page 995 of 1074 REJ09B0366-0700 (2) Tpci0 Tpci2w Tpci2w CKIO Tpci1 Tpci1w Tpci2 Tpci0 Tpci1 Tpci1w Tpci2 tAD A25–A1 tAD tAD A0 CExx REG (WE7) tCSD tRWD tCSD tCSD tRWD RD/WR Section 22 Electrical Characteristics tICRSD tICRSD tRDS tICWSDF tICWSDF ICIOWR (WE3) tICRSD tRDH tICWSDF tWDD tWDD tICWSDF Rev.7.00 Oct. 10, 2008 Page 996 of 1074 REJ09B0366-0700 ICIORD (WE2) D15–D0 (read) tICWSDF D15–D0 (write) tWDD tBSD tBSD tRDYS tRDYH tWDD tWDD BS tRDYS tRDYH RDY IOIS16 Figure 22.54 PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait, Bus Sizing) tIO16S tIO16H Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tm1 Tm0 Tmd1w Tmd1w Tmd1 CKIO Tmd1w Tmd1 tFMD RD/FRAME tFMD tWDD tRDH A D0 tFMD tRDS tWDD tWDD D0 tFMD tRDS tRDH tWDD D63–D0 A tCSD CSn tCSD tRWD tRWD tCSD tCSD tRWD tRWD RD/WR WEn tWED1 tRDYS tRDYH tBSD tRDYS tWED1 tWED1 tRDYH tRDYS tBSD tRDYH tWED1 RDY tBSD tBSD tDACD BS tDACD DACKn (DA) tDACD tDACD Figure 22.55 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data (One Internal Wait + One External Wait) (1) 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high (2) 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address Section 22 Electrical Characteristics Rev.7.00 Oct. 10, 2008 Page 997 of 1074 REJ09B0366-0700 Tm1 Tmd1 Tm1 Tmd1w Tmd1 Tm1 Tmd1w Tmd1w Tmd1 CKIO tFMD tWDD A D0 A D0 A D0 tFMD tWDD tCSD tRWD tWED1 tRDYH tBSD tDACD tDACD tDACD tBSD tBSD tBSD tRDYS tRDYH tRDYS tRDYS tBSD tDACD tWED1 tWED1 tWED1 tRDYH tRDYH tRWD tRWD tRWD tCSD tCSD tCSD tWDD tWDD tWDD tWDD tWDD tWDD tWDD tCSD tRWD tWED1 tFMD tFMD tFMD tFMD RD/FRAME D63–D0 tCSD tRWD CSn Section 22 Electrical Characteristics RD/WR Rev.7.00 Oct. 10, 2008 Page 998 of 1074 REJ09B0366-0700 tWED1 tRDYS tBSD tDACD tDACD (1) 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address (2) 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address (3) 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address WEn RDY BS Figure 22.56 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data (One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait) DACKn (DA) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tm1 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 Tm1 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CKIO tFMD tWDD tRDS D0 D1 D2 D3 A D0 D1 D2 tFMD tRDH tCSD tRWD tWED1 tRDYH tBSD tBSD tRDYS tRDYH tRDYS tRDYH tWED1 tRWD tCSD tWDD tWDD tRDS tRDH D3 tFMD tFMD RD/FRAME tWDD A D63–D0 tCSD tCSD tRWD tWED1 CSn tRWD RD/WR WEn tWED1 tRDYS tBSD tDACD tDACD RDY tBSD BS tDACD tDACD DACKn (DA) (1) 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address (2) 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address Figure 22.57 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait) (2) 1st Data (One Internal Wait), 2nd to 4th Data (One Internal Wait + One External Wait) Section 22 Electrical Characteristics Rev.7.00 Oct. 10, 2008 Page 999 of 1074 REJ09B0366-0700 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Tm1 Tmd1 Tmd2 Tmd3 Tmd4 Tm1 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CKIO tFMD tFMD tWDD tWDD D0 D1 D2 D3 D1 D2 D3 A tFMD tWDD D0 tFMD RD/FRAME tWDD A D63–D0 tCSD tRWD tRWD tWED1 tRDYH tBSD tDACD tDACD tBSD tBSD tRDYS tRDYH tRDYS tRDYH tWED1 tRWD tCSD tCSD tCSD tRWD tWED1 CSn Section 22 Electrical Characteristics RD/WR Rev.7.00 Oct. 10, 2008 Page 1000 of 1074 REJ09B0366-0700 tWED1 tBSD tDACD tDACD (1) 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address (2) 1st data bus cycle information D63–D61: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address WEn tRDYS RDY BS DACKn (DA) Figure 22.58 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait), 2nd to 4th Data (No Internal Wait + External Wait Control) Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high T1 T2 T1 Tw T2 T1 Tw Twe T2 CKIO tAD tAD tAD tAD tCSD tCSD tRWD tRSD tRSD tRDS tWED1 tWEDF tRWD tRSD tRDS tWED1 tWEDF tBSD tWED1 tRDH tRSD tCSD tRWD tRSD tRDH tWED1 tAD tCSD tRWD tRSD tAD tCSD tRWD tRSD tRDS tWED1 tWEDF tBSD tBSD tBSD tRDYS tRDYH tDACD tDACD tDACD tDACD tDACD tDACD tBSD tWED1 tRDH tRSD tCSD tRWD tRSD A25–A0 CSn RD/WR RD D63–D0 (read) WEn tBSD tRDYS tRDYH tRDYH tDACD tDACD tRDYS tDACD BS RDY DACKn (SA: IO ← memory) tDACD tDACD tDACD tDACD tDACD tDACD Figure 22.59 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait) (1) (2) (3) DACKn (DA) Section 22 Electrical Characteristics Rev.7.00 Oct. 10, 2008 Page 1001 of 1074 REJ09B0366-0700 Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Section 22 Electrical Characteristics TS1 CKIO T1 T2 TH1 tAD A25–A0 tAD tCSD tCSD CSn tRWD RD/WR tRWD tRSD tRDS tRDH tWED1 tRSD tRSD RD D63–D0 (read) tWED1 tWEDF WEn tBSD BS tBSD RDY tDACD DACKn (SA: IO ← memory) tDACD tDACD DACKn (DA) tDACD Legend: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, AnS[0] = 1, AnH[1:0] =0 1) Rev.7.00 Oct. 10, 2008 Page 1002 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics 22.3.4 Peripheral Module Signal Timing Table 22.34 Peripheral Module Signal Timing (1) HD6417750 RBP240 (V) HD6417750 RBG240 (V) *2 Module TMU, RTC Item Timer clock pulse width (high) Timer clock pulse width (low) Timer clock rise time Timer clock fall time Oscillation settling time SCI Input clock cycle (asynchronous) Input clock cycle (synchronous) Input clock pulse width Input clock rise time Input clock fall time Transfer data delay time Symbol tTCLKWH Min 4 Max — Min 4 HD6417750 RBP200 (V) HD6417750 RBG200 (V) *2 Max — Min 4 HD6417750 RF240 (V) *2 Max — Min 4 HD6417750 RF200 (V) *2 Max — Unit Pcyc*1 Figure 22.61 tTCLKWL 4 — 4 — 4 — 4 — Pcyc*1 22.61 tTCLKr tTCLKf tROSC tScyc — — — 4 0.8 0.8 3 — — — — 4 0.8 0.8 3 — — — — 4 0.8 0.8 3 — — — — 4 0.8 0.8 3 — Pcyc*1 Pcyc*1 s Pcyc*1 22.61 22.61 22.62 22.63 tScyc 6 — 6 — 6 — 6 — Pcyc*1 22.63 tSCKW tSCKr tSCKf tTXD 0.4 — — 1.5 16 0.6 0.8 0.8 5.3 — 0.4 — — 1.5 16 0.6 0.8 0.8 6 — 0.4 — — 1.5 16 0.6 0.8 0.8 6 — 0.4 — — 1.5 16 0.6 0.8 0.8 6 — tScyc Pcyc*1 Pcyc*1 ns ns 22.63 22.63 22.63 22.64 22.64 Receive data tRXS setup time (synchronous) Receive data tRXH hold time (synchronous) I/O ports Output data delay time Input data setup time Input data hold time tPORTD tPORTS tPORTH 16 — 16 — 16 — 16 — ns 22.64 1.5 2 1.5 5.3 — — 1.5 2.5 1.5 6 — — 1.5 3.5 1.5 6 — — 1.5 3.5 1.5 6 — — ns ns ns 22.65 22.65 22.65 Rev.7.00 Oct. 10, 2008 Page 1003 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics HD6417750 RBP240 (V) HD6417750 RBG240 (V) *2 Module DMAC Item DREQn setup time DREQn hold time DRAKn delay time INTC NMI pulse width (high) Symbol tDRQS tDRQH tDRAKD tNMIH Min 2 1.5 1.5 5 Max — — 5.3 — Min 2.5 1.5 1.5 5 HD6417750 RBP200 (V) HD6417750 RBG200 (V) *2 Max — — 6 — Min 3.5 1.5 1.5 5 HD6417750 RF240 (V) *2 Max — — 6 — Min 3.5 1.5 1.5 5 HD6417750 RF200 (V) *2 Max — — 6 — Unit ns ns ns tcyc Figure 22.66 22.66 22.66 22.71 Normal or sleep mode Standby mode Normal or sleep mode Standby mode 30 NMI pulse width (low) tNMIL 5 — — 30 5 — — 30 5 — — 30 5 — — ns tcyc 22.71 22.71 30 H-UDI Input clock cycle Input clock pulse width (high) Input clock pulse width (low) Input clock rise time tTCKcyc tTCKH 50 15 — — — 30 50 15 — — — 30 50 15 — — — 30 50 15 — — — ns ns ns 22.71 22.67 22.67 tTCKL 15 — 15 — 15 — 15 — ns 22.67 tTCKr — — 10 10 15 15 0 2 10 10 — — — — 10 — — — 10 10 15 15 0 2 10 10 — — — — 10 — — — 10 10 15 15 0 2 10 10 — — — — 10 — — — 10 10 15 15 0 2 10 10 — — — — 10 — ns ns tcyc tcyc ns ns ns Pcyc*1 22.67 22.67 22.68 22.68 22.69 22.69 22.69 22.70 Input clock fall tTCKf time ASEBRK setup time tASEBRKS ASEBRK hold tASEBRKH time TDI/TMS setup time tTDIS TDI/TMS hold tTDIH time TDO delay time ASE-PINBRK pulse width tTDO tPINBRK Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on Rev.7.00 Oct. 10, 2008 Page 1004 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.34 Peripheral Module Signal Timing (2) HD6417750S VF133 (V) HD6417750S VBT133 (V) *2 Module TMU, RTC Item Timer clock pulse width (high) Timer clock pulse width (low) Timer clock rise time Timer clock fall time Oscillation settling time SCI Input clock cycle (asynchronous) Input clock cycle (synchronous) Input clock pulse width Input clock rise time Symbol tTCLKWH Min 4 Max — Min 4 HD6417750 SF167 (V) HD6417750 SF200 (V) *3 Max — Min 4 HD6417750 SBP200 (V) *4 Max — Unit Pcyc*1 Figure 22.61 tTCLKWL 4 — 4 — 4 — Pcyc*1 22.61 tTCLKr tTCLKf tROSC tScyc — — — 4 0.8 0.8 3 — — — — 4 0.8 0.8 3 — — — — 4 0.8 0.8 3 — Pcyc*1 Pcyc*1 s Pcyc*1 22.61 22.61 22.62 22.63 tScyc 6 — 6 — 6 — Pcyc*1 22.63 tSCKW tSCKr 0.4 — — 1.5 16 0.6 0.8 0.8 10 — 0.4 — — 1.5 16 0.6 0.8 0.8 8 — 0.4 — — 1.5 16 0.6 0.8 0.8 6 — tScyc Pcyc*1 Pcyc*1 ns ns 22.63 22.63 22.63 22.64 22.64 Input clock fall tSCKf time Transfer data delay time tTXD Receive data tRXS setup time (synchronous) Receive data tRXH hold time (synchronous) 16 — 16 — 16 — ns 22.64 Rev.7.00 Oct. 10, 2008 Page 1005 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics HD6417750S VF133 (V) HD6417750S VBT133 (V) *2 Module I/O ports Item Output data delay time Input data setup time Symbol tPORTD tPORTS Min 1.5 3.5 1.5 3.5 1.5 1.5 Max 10 — — — — 10 Min 1.5 3.5 1.5 3.5 1.5 1.5 HD6417750 SF167 (V) HD6417750 SF200 (V) *3 Max 8 — — — — 8 Min 1.5 3 1.5 3 1.5 1.5 HD6417750 SBP200 (V) *4 Max 6 — — — — 6 Unit ns ns ns ns ns ns Figure 22.65 22.65 22.65 22.66 22.66 22.66 Input data hold tPORTH time DMAC DREQn setup tDRQS time DREQn hold time DRAKn delay time tDRQH tDRAKD Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 4. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on Rev.7.00 Oct. 10, 2008 Page 1006 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.34 Peripheral Module Signal Timing (3) HD6417750S VF133 (V) HD6417750S VBT133 (V) *2 Module INTC Item NMI pulse width (high) NMI pulse width (low) H-UDI Input clock cycle Input clock pulse width (high) Input clock pulse width (low) Input clock rise time Symbol tNMIH tNMIL tTCKcyc tTCKH Min 5 30 5 30 50 15 Max — — — — — — Min 5 30 5 30 50 15 HD6417750 SF167 (V) HD6417750 SF200 (V) *3 Max — — — — — — Min 5 30 5 30 50 15 HD6417750 SBP200 (V) *4 Max — — — — — — Unit tcyc ns tcyc ns ns ns Figure 22.71 22.71 22.71 22.71 22.67 22.67 Normal or sleep mode Standby mode Normal or sleep mode Standby mode tTCKL 15 — 15 — 15 — ns 22.67 tTCKr — — 10 10 15 15 0 2 10 10 — — — — 10 — — — 10 10 15 15 0 2 10 10 — — — — 10 — — — 10 10 15 15 0 2 10 10 — — — — 10 — ns ns tcyc tcyc ns ns ns Pcyc*1 22.67 22.67 22.68 22.68 22.69 22.69 22.69 22.70 Input clock fall tTCKf time ASEBRK setup time tASEBRKS ASEBRK hold tASEBRKH time TDI/TMS setup time tTDIS TDI/TMS hold tTDIH time TDO delay time ASE-PINBRK pulse width tTDO tPINBRK Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 4. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on Rev.7.00 Oct. 10, 2008 Page 1007 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.34 Peripheral Module Signal Timing (4) HD6417750 VF128 (V) *2 Module TMU, RTC Item Timer clock pulse width (high) Timer clock pulse width (low) Timer clock rise time Timer clock fall time Oscillation settling time SCI Input clock cycle (asynchronous) Input clock cycle (synchronous) Input clock pulse width Input clock rise time Symbol tTCLKWH Min 4 Max — Min 4 HD6417750 F167 (V) *3 Max — Min 4 HD6417750 BP200M (V) *4 Max — Unit Pcyc*1 Figure 22.61 tTCLKWL 4 — 4 — 4 — Pcyc*1 22.61 tTCLKr tTCLKf tROSC tScyc — — — 4 0.8 0.8 3 — — — — 4 0.8 0.8 3 — — — — 4 0.8 0.8 3 — Pcyc*1 Pcyc*1 s Pcyc*1 22.61 22.61 22.62 22.63 tScyc 6 — 6 — 6 — Pcyc*1 22.63 tSCKW tSCKr 0.4 — — 1.3 16 0.6 0.8 0.8 10 — 0.4 — — 1.3 16 0.6 0.8 0.8 8 — 0.4 — — 1.2 16 0.6 0.8 0.8 6 — tScyc Pcyc*1 Pcyc*1 ns ns 22.63 22.63 22.63 22.64 22.64 Input clock fall tSCKf time Transfer data delay time tTXD Receive data tRXS setup time (synchronous) Receive data tRXH hold time (synchronous) I/O ports Output data delay time Input data setup time tPORTD tPORTS 16 — 16 — 16 — ns 22.64 0.5 3.5 1.5 10 — — 0.5 3.5 1.5 8 — — 0.5 3 1.5 6 — — ns ns ns 22.65 22.65 22.65 Input data hold tPORTH time Rev.7.00 Oct. 10, 2008 Page 1008 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics HD6417750 VF128 (V) *2 Module DMAC Item Symbol Min 3.5 1.5 1.0 Max — — 10 Min 3.5 1.5 1.0 HD6417750 F167 (V) *3 Max — — 8 Min 3 1.5 1.0 HD6417750 BP200M (V) *4 Max — — 6 Unit ns ns ns Figure 22.66 22.66 22.66 DREQn setup tDRQS time DREQn hold time DRAKn delay time tDRQH tDRAKD Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 4. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on Rev.7.00 Oct. 10, 2008 Page 1009 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics Table 22.34 Peripheral Module Signal Timing (5) HD6417750 VF128 (V) *2 Module INTC Item NMI pulse width (high) NMI pulse width (low) H-UDI Input clock cycle Input clock pulse width (high) Input clock pulse width (low) Input clock rise time Symbol tNMIH tNMIL tTCKcyc tTCKH Min 5 30 5 30 50 15 Max — — — — — — Min 5 30 5 30 50 15 HD6417750 F167 (V) *3 Max — — — — — — Min 5 30 5 30 50 15 HD6417750 BP200M (V) *4 Max — — — — — — Unit tcyc ns tcyc ns ns ns Figure 22.71 22.71 22.71 22.71 22.67 22.67 Normal or sleep mode Standby mode Normal or sleep mode Standby mode tTCKL 15 — 15 — 15 — ns 22.67 tTCKr — — 10 10 15 15 0 2 10 10 — — — — 10 — — — 10 10 15 15 0 2 10 10 — — — — 10 — — — 10 10 15 15 0 2 10 10 — — — — 10 — ns ns tcyc tcyc ns ns ns Pcyc*1 22.67 22.67 22.68 22.68 22.69 22.69 22.69 22.70 Input clock fall tTCKf time ASEBRK setup time ASEBRK hold time TDI/TMS setup time tASEBRKS tASEBRKH tTDIS TDI/TMS hold tTDIH time TDO delay time ASE-PINBRK pulse width tTDO tPINBRK Notes: 1. Pcyc: P clock cycles 2. VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 3. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on 4. VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on Rev.7.00 Oct. 10, 2008 Page 1010 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics TCLK tTCLKWH tTCLKWL tTCLKf tTCLKr Figure 22.61 TCLK Input Timing Stable oscillation RTC internal clock VDD-RTC VDD-RTC min tROSC Figure 22.62 RTC Oscillation Settling Time at Power-On tSCKW SCK, SCK2 tScyc tSCKf tSCKr Figure 22.63 SCK Input Clock Timing Rev.7.00 Oct. 10, 2008 Page 1011 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics tScyc SCK tTXD TXD tTXD RXD tRXS tRXH Figure 22.64 SCI I/O Synchronous Mode Clock Timing CKIO Ports 19–0 (read) tPORTS tPORTH Ports 19–0 (write) tPORTD tPORTD Figure 22.65 I/O Port Input/Output Timing CKIO tDRQH DREQn tDRQH tDRQS tDRQS DRAKn tDRAKD Figure 22.66 (a) DREQ/DRAK Timing Rev.7.00 Oct. 10, 2008 Page 1012 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics CKIO tDBQS DBREQ tDBQH tBAVD tBAVD BAVL tTRS TR tTRH D63 to D0 (READ) tDTRS (2) tDTRH (1) (1): [2CKIO cycle – tDTRS] (= 18 ns: 100 MHz) (2): DTR = 1CKIO cycle (= 10 ns: 100 MHz) (tDTRS + tDTRH) < DTR < 10 ns Figure 22.66 (b) DBREQ/TR Input Timing and BAVL Output Timing tTCKcyc tTCKH tTCKL VIH 1/2VDDQ VIH VIL tTCKf VIL VIH 1/2VDDQ tTCKr Note: When clock is input from TCK pin Figure 22.67 TCK Input Timing Rev.7.00 Oct. 10, 2008 Page 1013 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics RESET (Low) SCK2/ MRESET (High) tASEBRKS tASEBRKH tASEBRKS tASEBRKH ASEBRK/ BRKACK Figure 22.68 RESET Hold Timing tTCKcyc TCK TDI TMS tTDIS tTDIH TDO tTDO Figure 22.69 H-UDI Data Transfer Timing tPINBRK ASEBRK Figure 22.70 Pin Break Timing tNMIH tNMIL NMI Figure 22.71 NMI Input Timing Rev.7.00 Oct. 10, 2008 Page 1014 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics 22.3.5 AC Characteristic Test Conditions The AC characteristic test conditions are as follows: • Input/output signal reference level: 1.5 V (VDDQ = 3.3 ±0.3 V) • Input pulse level: VSSQ to 3.0 V (VSSQ to VDDQ for RESET, TRST, NMI, and ASEBRK/BRKACK) • Input rise/fall time: 1 ns The output load circuit is shown in figure 22.72. IOL LSI output pin CL DUT output VREF IOH Notes: CL is the total value, including the capacitance of the test jig, etc. The capacitance of each pin is set to 30 pF. IOL and IOH values are as shown in table 22.16, Permissible Output Currents. Figure 22.72 Output Load Circuit Rev.7.00 Oct. 10, 2008 Page 1015 of 1074 REJ09B0366-0700 Section 22 Electrical Characteristics 22.3.6 Delay Time Variation Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 pF) is connected to this LSI' pins is shown below. The graph shown in figure 22.73 should be taken into consideration if the stipulated capacitance is exceeded when connecting an external device. The graph will not be linear if the connected load capacitance exceeds the range shown in figure 22.73. +4.0 ns +3.0 ns Delay Time +2.0 ns +1.0 ns +0.0 ns +0 pF +25 pF Load Capacitance +50 pF Figure 22.73 Load Capacitance vs. Delay Time Rev.7.00 Oct. 10, 2008 Page 1016 of 1074 REJ09B0366-0700 Appendix A Address List Appendix A Address List Table A.1 Address List Area 7 1 Address* Power-On Size Reset Undefined Undefined Undefined Undefined Manual Reset Undefined Undefined Undefined Held Synchronization Sleep Standby Clock Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Ick Ick Ick Ick Ick Ick Ick Ick Ick Ick Ick Ick Ick Ick Module Register CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN CCN PTEH PTEL TTB TEA MMUCR BASRA BASRB CCR TRA EXPEVT INTEVT PTEA QACR0 QACR1 P4 Address H'FF00 0000 H'1F00 0000 32 H'FF00 0004 H'1F00 0004 32 H'FF00 0008 H'1F00 0008 32 H'FF00 000C H'1F00 000C 32 H'FF00 0010 H'1F00 0010 32 H'FF00 0014 H'1F00 0014 8 H'FF00 0018 H'1F00 0018 8 H'FF00 001C H'1F00 001C 32 H'FF00 0020 H'1F00 0020 32 H'FF00 0024 H'1F00 0024 32 H'FF00 0028 H'1F00 0028 32 H'FF00 0034 H'1F00 0034 32 H'FF00 0038 H'1F00 0038 32 H'FF00 003C H'1F00 003C 32 H'0000 0000 H'0000 0000 Held Undefined Undefined Held Held Held Held H'0000 0000 H'0000 0000 Held Undefined Undefined Held H'0000 0000 H'0000 0020 Held Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held Held UBC UBC UBC UBC UBC UBC UBC UBC UBC BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMRB BRCR H'FF20 0000 H'1F20 0000 32 H'FF20 0004 H'1F20 0004 8 H'FF20 0008 H'1F20 0008 16 H'FF20 000C H'1F20 000C 32 H'FF20 0010 H'1F20 0010 8 H'FF20 0014 H'1F20 0014 16 H'FF20 0018 H'1F20 0018 32 H'FF20 001C H'1F20 001C 32 H'FF20 0020 H'1F20 0020 16 Undefined Undefined H'0000 Undefined Undefined H'0000 Undefined Undefined H'0000* 2 Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Ick Ick Ick Ick Ick Ick Ick Ick Ick BSC BSC BSC BSC BCR1 BCR2 5 BCR3* H'FF80 0000 H'1F80 0000 32 H'FF80 0004 H'1F80 0004 16 H'FF80 0050 H'1F80 0050 16 H'FE0A00F0 H'1E0A00F0 32 H'0000 0000* Held H'3FFC* H'0000 2 2 Held Held Held Held Held Held Held Held Bck Bck Bck Bck Held Held BCR4* 5 H'0000 0000 Held Rev.7.00 Oct. 10, 2008 Page 1017 of 1074 REJ09B0366-0700 Appendix A Address List Synchronization Sleep Standby Clock Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Module Register BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC WCR1 WCR2 WCR3 MCR PCR RTCSR RTCNT RTCOR RFCR PCTRA PDTRA PCTRB PDTRB GPIOIC SDMR2 SDMR3 P4 Address Area 7 1 Address* Power-On Size Reset Manual Reset H'FF80 0008 H'1F80 0008 32 H'FF80 000C H'1F80 000C 32 H'FF80 0010 H'1F80 0010 32 H'FF80 0014 H'1F80 0014 32 H'FF80 0018 H'1F80 0018 16 H'FF80 001C H'1F80 001C 16 H'FF80 0020 H'1F80 0020 16 H'FF80 0024 H'1F80 0024 16 H'FF80 0028 H'1F80 0028 16 H'FF80 002C H'1F80 002C 32 H'FF80 0030 H'1F80 0030 16 H'FF80 0040 H'1F80 0040 32 H'FF80 0044 H'1F80 0044 16 H'FF80 0048 H'1F80 0048 16 H'FF90 xxxx H'1F90 xxxx H'FF94 xxxx H'1F94 xxxx 8 8 H'7777 7777 Held H'FFFE EFFF Held H'0777 7777 Held H'0000 0000 Held H'0000 H'0000 H'0000 H'0000 H'0000 Held Held Held Held Held H'0000 0000 Held Undefined Held H'0000 0000 Held Undefined Held H'0000 0000 Held Write-only DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC SAR0 DAR0 H'FFA0 0000 H'1FA0 0000 32 H'FFA0 0004 H'1FA0 0004 32 Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck DMATCR0 H'FFA0 0008 H'1FA0 0008 32 CHCR0 SAR1 DAR1 H'FFA0 000C H'1FA0 000C 32 H'FFA0 0010 H'1FA0 0010 32 H'FFA0 0014 H'1FA0 0014 32 H'0000 0000 H'0000 0000 Held Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held DMATCR1 H'FFA0 0018 H'1FA0 0018 32 CHCR1 SAR2 DAR2 H'FFA0 001C H'1FA0 001C 32 H'FFA0 0020 H'1FA0 0020 32 H'FFA0 0024 H'1FA0 0024 32 H'0000 0000 H'0000 0000 Held Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held DMATCR2 H'FFA0 0028 H'1FA0 0028 32 CHCR2 SAR3 DAR3 H'FFA0 002C H'1FA0 002C 32 H'FFA0 0030 H'1FA0 0030 32 H'FFA0 0034 H'1FA0 0034 32 H'0000 0000 H'0000 0000 Held Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held DMATCR3 H'FFA0 0038 H'1FA0 0038 32 CHCR3 H'FFA0 003C H'1FA0 003C 32 H'0000 0000 H'0000 0000 Held Rev.7.00 Oct. 10, 2008 Page 1018 of 1074 REJ09B0366-0700 Appendix A Address List Synchronization Sleep Standby Clock Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Module Register DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAOR 5 SAR4* P4 Address Area 7 1 Address* Power-On Size Reset Manual Reset H'FFA0 0040 H'1FA0 0040 32 H'FFA0 0050 H'1FA0 0050 32 H'FFA0 0054 H'1FA0 0054 32 5 H'0000 0000 H'0000 0000 Held Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held DAR4* 5 DMATCR4* H'FFA0 0058 H'1FA0 0058 32 CHCR4* SAR5* 5 5 H'FFA0 005C H'1FA0 005C 32 H'FFA0 0060 H'1FA0 0060 32 H'FFA0 0064 H'1FA0 0064 32 5 H'0000 0000 H'0000 0000 Held Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held 5 DAR5* DMATCR5* H'FFA0 0068 H'1FA0 0068 32 CHCR5* 5 SAR6* 5 H'FFA0 006C H'1FA0 006C 32 H'FFA0 0070 H'1FA0 0070 32 H'FFA0 0074 H'1FA0 0074 32 5 H'0000 0000 H'0000 0000 Held Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held DAR6* 5 DMATCR6* H'FFA0 0078 H'1FA0 0078 32 CHCR6* SAR7* 5 5 H'FFA0 007C H'1FA0 007C 32 H'FFA0 0080 H'1FA0 0080 32 H'FFA0 0084 H'1FA0 0084 32 5 H'0000 0000 H'0000 0000 Held Undefined Undefined Undefined Undefined Undefined Undefined Held Held Held 5 DAR7* DMATCR7* H'FFA0 0088 H'1FA0 0088 32 CHCR7* 5 H'FFA0 008C H'1FA0 008C 32 H'0000 0000 H'0000 0000 Held CPG CPG* CPG* CPG* 6 FRQCR STBCR WTCNT WTCSR STBCR2 H'FFC0 0000 H'1FC0 0000 16 H'FFC0 0004 H'1FC0 0004 8 *2 H'00 Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Pck Pck Pck Pck Pck 6 3 H'FFC0 0008 H'1FC0 0008 8/16* H'00 3 H'FFC0 000C H'1FC0 000C 8/16* H'00 6 6 CPG* H'FFC0 0010 H'1FC0 0010 8 H'00 RTC RTC RTC RTC RTC RTC RTC RTC RTC R64CNT H'FFC8 0000 H'1FC8 0000 8 Held Held Held Held Held Held Held Held Held * 2 Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Pck Pck Pck Pck Pck Pck Pck Pck Pck RSECCNT H'FFC8 0004 H'1FC8 0004 8 RMINCNT H'FFC8 0008 H'1FC8 0008 8 RHRCNT H'FFC8 000C H'1FC8 000C 8 RWKCNT H'FFC8 0010 H'1FC8 0010 8 RDAYCNT H'FFC8 0014 H'1FC8 0014 8 RMONCNT H'FFC8 0018 H'1FC8 0018 8 RYRCNT RSECAR H'FFC8 001C H'1FC8 001C 16 H'FFC8 0020 H'1FC8 0020 8 Rev.7.00 Oct. 10, 2008 Page 1019 of 1074 REJ09B0366-0700 Appendix A Address List Synchronization Sleep Standby Clock Held Held Held Held Held 2 Module Register RTC RTC RTC RTC RTC RTC RTC RTC RTC RMINAR RHRAR RWKAR RDAYAR P4 Address Area 7 1 Address* Power-On Size Reset Held * 2 Manual Reset Held Held Held Held Held H'00* H'FFC8 0024 H'1FC8 0024 8 H'FFC8 0028 H'1FC8 0028 8 H'FFC8 002C H'1FC8 002C 8 H'FFC8 0030 H'1FC8 0030 8 Held Held Held Held Held Held Held Held Held Pck Pck Pck Pck Pck Pck Pck Pck Pck 2 Held * Held * Held * Held * H'00* 2 2 2 RMONAR H'FFC8 0034 H'1FC8 0034 8 RCR1 RCR2 RCR3* 5 2 H'FFC8 0038 H'1FC8 0038 8 H'FFC8 003C H'1FC8 003C 8 H'FFC8 0050 H'1FC8 0050 8 5 Held Held Held Held 2 H'09* 2 H'00* H'00 Undefined Held Held RYRAR* H'FFC8 0054 H'1FC8 0054 16 INTC INTC INTC INTC INTC INTC INTC INTC INTC ICR IPRA IPRB IPRC 4 IPRD* H'FFD0 0000 H'1FD0 0000 16 H'FFD0 0004 H'1FD0 0004 16 H'FFD0 0008 H'1FD0 0008 16 H'FFD0 000C H'1FD0 000C 16 H'FFD00010 H'1F000010 16 H'0000* H'0000 H'0000 H'0000 H'DA74 2 H'0000* H'0000 H'0000 H'0000 H'DA74 2 Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Pck Pck Pck Pck Pck Pck Pck Pck Pck INTPRI00 H'FE08 0000 H'1E08 0000 32 *5 INTREQ00 H'FE08 0020 H'1E08 0020 32 *5 INTMSK00 H'FE08 0040 H'1E08 0040 32 *5 INTMSKCL H'FE08 0060 H'1E08 0060 32 5 R00* H'0000 0000 Held H'0000 0000 Held H'0000 0300 Held Write-only CPG* CPG* 6 CLKSTP00 H'FE0A 0000 H'1E0A 0000 32 *5 CLKSTPCL H'FE0A 0008 H'1E0A 0008 32 5 R00* H'0000 0000 Held Write-only Held Held Pck Pck 6 TMU TMU TMU TMU TMU TMU TSTR2* 5 H'FE10 0004 H'1E10 0004 8 H'FE10 0008 H'1E10 0008 32 H'FE10 000C H'1E10 000C 32 H'FE10 0010 H'1E10 0010 16 H'00 Held Held Held Held Held Held Held Held Held Held Held Held Held Pck Pck Pck Pck Pck Pck TCOR3* 5 H'FFFF FFFF Held H'FFFF FFFF Held H'0000 Held 5 TCNT3* TCR3* 5 TCOR4* 5 H'FE10 0014 H'1E10 0014 32 H'FE10 0018 H'1E10 0018 32 H'FFFF FFFF Held H'FFFF FFFF Held 5 TCNT4* Rev.7.00 Oct. 10, 2008 Page 1020 of 1074 REJ09B0366-0700 Appendix A Address List Synchronization Sleep Standby Clock Held Held Held Held Held H'00* Held Held Held Held Held Held Held Held Held Held 2 Module Register TMU TMU TMU TMU TMU TMU TMU TMU TMU TMU TMU TMU TMU TCR4* TOCR TSTR TCOR0 TCNT0 TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 TCPR2 5 P4 Address Area 7 1 Address* Power-On Size Reset H'0000 H'00 H'00 Manual Reset Held H'00 H'00 H'FE10 001C H'1E10 001C 16 H'FFD8 0000 H'1FD8 0000 8 H'FFD8 0004 H'1FD8 0004 8 H'FFD8 0008 H'1FD8 0008 32 H'FFD8 000C H'1FD8 000C 32 H'FFD8 0010 H'1FD8 0010 16 H'FFD8 0014 H'1FD8 0014 32 H'FFD8 0018 H'1FD8 0018 32 H'FFD8 001C H'1FD8 001C 16 H'FFD8 0020 H'1FD8 0020 32 H'FFD8 0024 H'1FD8 0024 32 H'FFD8 0028 H'1FD8 0028 16 H'FFD8 002C H'1FD8 002C 32 Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck H'FFFF FFFF H'FFFF FFFF Held H'FFFF FFFF H'FFFF FFFF Held H'0000 H'0000 Held H'FFFF FFFF H'FFFF FFFF Held H'FFFF FFFF H'FFFF FFFF Held H'0000 H'0000 Held H'FFFF FFFF H'FFFF FFFF Held H'FFFF FFFF H'FFFF FFFF Held H'0000 Held H'0000 Held Held Held SCI SCI SCI SCI SCI SCI SCI SCI SCSMR1 SCBRR1 SCSCR1 SCTDR1 SCSSR1 SCRDR1 H'FFE0 0000 H'1FE0 0000 8 H'FFE0 0004 H'1FE0 0004 8 H'FFE0 0008 H'1FE0 0008 8 H'FFE0 000C H'1FE0 000C 8 H'FFE0 0010 H'1FE0 0010 8 H'FFE0 0014 H'1FE0 0014 8 H'00 H'FF H'00 H'FF H'84 H'00 H'00 H'00* 2 H'00 H'FF H'00 H'FF H'84 H'00 H'00 H'00* 2 Held Held Held Held Held Held Held Held H'00 H'FF H'00 H'FF H'84 H'00 H'00 H'00* 2 Pck Pck Pck Pck Pck Pck Pck Pck SCSCMR1 H'FFE0 0018 H'1FE0 0018 8 SCSPTR1 H'FFE0 001C H'1FE0 001C 8 SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCSMR2 SCBRR2 SCSCR2 H'FFE8 0000 H'1FE8 0000 16 H'FFE8 0004 H'1FE8 0004 8 H'FFE8 0008 H'1FE8 0008 16 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000* H'0000 2 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000* H'0000 2 Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck SCFTDR2 H'FFE8 000C H'1FE8 000C 8 SCFSR2 H'FFE8 0010 H'1FE8 0010 16 SCFRDR2 H'FFE8 0014 H'1FE8 0014 8 SCFCR2 SCFDR2 H'FFE8 0018 H'1FE8 0018 16 H'FFE8 001C H'1FE8 001C 16 SCSPTR2 H'FFE8 0020 H'1FE8 0020 16 SCLSR2 H'FFE8 0024 H'1FE8 0024 16 Rev.7.00 Oct. 10, 2008 Page 1021 of 1074 REJ09B0366-0700 Appendix A Address List Synchronization Sleep Standby Clock Held Held Held Held Held Held Pck Pck Pck Module Register H-UDI H-UDI H-UDI SDIR SDDR SDINT* 5 P4 Address Area 7 1 Address* Power-On Size Reset 2 H'FFFF* Manual Reset Held Held Held H'FFF0 0000 H'1FF0 0000 16 H'FFF0 0008 H'1FF0 0008 32 H'FFF0 0014 H'1FF0 0014 16 Undefined H'0000 Notes: 1. With control registers, the above addresses in the physical page number field can be accessed by means of a TLB setting. When these addresses are referenced directly without using the TLB, operations are limited. 2. Includes undefined bits. See the descriptions of the individual modules. 3. Use word-size access when writing. Perform the write with the upper byte set to H'5A or H'A5, respectively. Byte- and longword-size writes cannot be used. Use byte-size access when reading. 4. SH7750S, SH7750R only 5. SH7750R only 6. Includes power-down states Rev.7.00 Oct. 10, 2008 Page 1022 of 1074 REJ09B0366-0700 Appendix B Package Dimensions Appendix B Package Dimensions JEITA Package Code P-BGA256-27x27-1.27 RENESAS Code PRBG0256DE-B Previous Code BP-256A/BP-256AV MASS[Typ.] 3.0g D A B ×4 v y1 S S y S e SD Y W V U T R P N e A1 A E Reference Symbol Dimension in Millimeters Min Nom 27.0 27.0 Max D SE M L K J H G F E D C B A E v w A A1 e b x y y1 SD SE ZD ZE 0.60 0.5 0.20 2.5 0.6 1.27 0.75 0.90 0.30 0.20 0.35 0.635 0.635 0.7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 φb φ× M S A B φ0.10 M S Figure B.1 Package Dimensions (256-Pin BGA) Rev.7.00 Oct. 10, 2008 Page 1023 of 1074 REJ09B0366-0700 Appendix B Package Dimensions JEITA Package Code P-HQFP208-28x28-0.50 RENESAS Code PRQP0208KE-B Previous Code FP-208E/FP-208EV MASS[Typ.] 5.3g HD *1 D 156 157 105 104 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp *2 HE E b1 c1 c ZE Reference Dimension in Millimeters Symbol 208 1 ZD Index mark 52 53 Terminal cross section F θ A1 L L1 x M e *3 y bp Detail F D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Min Nom Max 28 28 3.20 30.4 30.6 30.8 30.4 30.6 30.8 3.56 0.00 0.15 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0° 8° 0.5 0.10 0.10 1.25 1.25 0.4 0.5 0.6 1.3 A A2 Figure B.2 Package Dimensions (208-Pin QFP) Rev.7.00 Oct. 10, 2008 Page 1024 of 1074 REJ09B0366-0700 c Appendix B Package Dimensions JEITA Package Code P-LFBGA264-15x15-0.80 RENESAS Code PLBG0264GA-A Previous Code BP-264/BP-264V MASS[Typ.] 0.6g D wSA wSB ×4 v y1 S S E y S e ZD A T R P N M L K J H G F E D C B A e U A1 A Reference Symbol Dimension in Millimeters B Min Nom 15.00 15.00 Max D E v w A ZE 0.15 0.20 1.40 0.35 0.45 0.40 0.80 0.50 0.55 0.08 0.10 0.2 0.45 A1 e b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 x y y1 SD SE ZD ZE 1.10 1.10 φb φ ×M S A B Figure B.3 Package Dimensions (264-Pin CSP) Rev.7.00 Oct. 10, 2008 Page 1025 of 1074 REJ09B0366-0700 Appendix B Package Dimensions JEITA Package Code P-FBGA292-17x17-0.80 RENESAS Code PRBG0292GA-A Previous Code — MASS[Typ.] 0.9g E wSB wSA 4× v y1 S S A y S e SE ZE B W V U T R P N M L K H G F E D J e Y A1 D Reference Symbol Dimension in Millimeters A Min Nom 17.00 17.00 Max D E SD v w A A1 ZD 0.15 0.20 2.00 0.35 0.45 0.40 0.80 0.50 0.55 0.08 0.10 0.20 0.40 0.40 0.9 0.9 0.45 C B A e b x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 φb y φ ×M S A B y1 SD SE ZD ZE Figure B.4 Package Dimensions (292-Pin BGA) Rev.7.00 Oct. 10, 2008 Page 1026 of 1074 REJ09B0366-0700 Appendix C Mode Pin Settings Appendix C Mode Pin Settings The MD8–MD0 pin values are input in the event of a power-on reset via the RESET or SCK2/MRESET pin. (1) Clock Modes • Clock Operating Modes (SH7750, SH7750S) External Pin Combination Frequency (vs. Input Clock) Clock 1/2 Peripheral FRQCR Operating Frequency CPU Bus Module Initial Mode MD2 MD1 MD0 Divider Value PLL1 PLL2 Clock Clock Clock 0 1 2 3 4 5 1 0 1 0 0 0 1 0 1 0 1 Off Off On Off On Off On On On On On On On On On On On On 6 6 3 6 3 6 3/2 1 1 2 3/2 3 3/2 1 1/2 1 3/4 3/2 H'0E1A H'0E23 H'0E13 H'0E13 H'0E0A H'0E0A Notes: 1. Turning on/off of the ½ frequency divider is solely determined by the clock operating mode. 2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input frequency (fEX) and CKIO clock output (fOP) in section 22.3.1, Clock and Control Signal Timing. Rev.7.00 Oct. 10, 2008 Page 1027 of 1074 REJ09B0366-0700 Appendix C Mode Pin Settings • Clock Operating Modes (SH7750R) Clock Operating Mode MD2 0 1 2 3 4 5 6 1 1 0 1 0 External Pin Combination MD1 0 MD0 0 1 0 1 0 1 0 PLL1 CPU PLL2 Clock 12 12 6 12 6 12 1 Frequency (vs. Input Clock) Bus Clock 3 3/2 2 4 3 6 1/2 Peripheral FRQCR Module Clock Initial Value 3 3/2 1 2 3/2 3 1/2 H'0E1A H'0E2C H'0E13 H'0E13 H'0E0A H'0E0A H'0808 On (×12) On On (×12) On On (×6) On (×6) Off (×6) On On (×12) On On On (×12) On Off Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode. 2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input frequency (fEX) and CKIO clock output (fOP) in section 22.3.1, Clock and Control Signal Timing. (2) Area 0 Bus Width Pin Value MD6 0 MD4 0 MD3 0 1 1 0 1 1 0 0 1 1 0 1 Bus Width 64 bits 8 bits 16 bits 32 bits 64 bits 8 bits 16 bits 32 bits Memory Type MPX interface Reserved (setting prohibited) Reserved MPX interface SRAM interface SRAM interface SRAM interface SRAM interface Rev.7.00 Oct. 10, 2008 Page 1028 of 1074 REJ09B0366-0700 Appendix C Mode Pin Settings (3) Endian Pin Value MD5 0 1 Endian Big endian Little endian (4) Master/Slave Pin Value MD7 0 1 Master/Slave Slave Master (5) Clock Input Pin Value MD8 0 1 Clock Input External input clock Crystal resonator Rev.7.00 Oct. 10, 2008 Page 1029 of 1074 REJ09B0366-0700 Appendix C Mode Pin Settings Rev.7.00 Oct. 10, 2008 Page 1030 of 1074 REJ09B0366-0700 Appendix D CKIO2ENB Pin Configuration Appendix D CKIO2ENB Pin Configuration SH7750 SH7750S SH7750R rd_pullup_control rd_dt_ rd_hiz_control VDDQ VDDQ RD/CASS/FRAME RD2 VDDQ rdwr_pullup_control rdwr_dt_ rdwr_hiz_control VDDQ RD/WR RD/WR2 Bus clock PLL2 ckio_hiz_control CKIO CKIO2 VDDQ VSSQ CKIO2ENB Figure D.1 CKIO2ENB Pin Configuration Rev.7.00 Oct. 10, 2008 Page 1031 of 1074 REJ09B0366-0700 Appendix D CKIO2ENB Pin Configuration CKIO2ENB 0 1 Description RD2, RD/WR2, and CKIO2 have the same pin states as RD, RD/WR, and CKIO, respectively RD2, RD/WR2, and CKIO2 are in the high-impedance state Note: CKIO is fed back to PLL2 to coordinate the external clock and internal clock phases. However, CKIO2 is not fed back. Rev.7.00 Oct. 10, 2008 Page 1032 of 1074 REJ09B0366-0700 Appendix E Pin Functions Appendix E Pin Functions E.1 Pin States Pin States in Reset, Power-Down State, and Bus-Released State Reset (Power-On) Signal Name D0–D7 D8–D15 D16–D23 D24–D31 D32–D51 D52–D55 D56–D63 A0, A1, A18–A25 A2–A17 RESET BACK/BSREQ BREQ/BSACK BS CKE CS6–CS0 RAS RD/CASS/FRAME RD/WR RDY WE7/CAS7/DQM7 WE6/CAS6/DQM6 WE5/CAS5/DQM5 WE4/CAS4/DQM4 WE3/CAS3/DQM3 WE2/CAS2/DQM2 I/O I/O I/O I/O I/O I/O I/O I/O O O I O I O O O O O O I O O O O O O Master Z Z Z Z Z Z Z P P I H P H H H H H H PI H H H H H H Slave Z Z Z Z Z Z Z P P I H P PZ H PZ PZ PZ PZ PI PZ PZ PZ PZ PZ PZ Reset (Manual) Master 19 Z* 19 Z* 19 Z* Table E.1 Slave 19 Z* 19 Z* 19 Z* Standby 19 Z* 19 Z* 19 Z* Bus Hardware Released Standby 19 Z* 19 Z* 19 Z* Z Z Z Z 18 Z* 19 Z* 18 19 Z* 18 19 Z* 18 19 Z* K* Z* Z* 19 19 Z* K* Z* Z* 19 19 Z* K* Z* Z* 19 19 Z* K* Z* Z* 19 19 Z Z Z Z Z I Z Z Z Z 19 19 19 19 Z* O* 13 15 Z* 13 Z* O* 13 6 Z* 13 13 8 Z* O* 13 Z* 13 6 Z* O* 13 Z* I H 12 I* I H I* 12 I H I* 12 I O I* 6 12 H O H O O H I* O O O O O O 12 Z* O 13 Z* H* L 13 Z* O 13 Z* Z* 13 Z* H* 13 13 6 Z* 13 Z 4 13 Z* O* 4 Z* O* 13 Z Z Z Z Z Z Z Z Z Z 13 Z* 13 Z* 13 4 Z* O* 13 6 Z* H* 12 Z* 13 4 Z* O* 13 4 Z* O* 13 Z* I* 12 I* 12 Z* Z* Z* Z* Z* 13 13 4 Z* O* 13 Z* O* Z* O* Z* O* Z* O* 13 13 13 13 4 Z* O* Z* O* Z* O* Z* O* 13 13 13 13 4 13 4 4 13 4 4 13 4 4 13 Z* 13 4 Z* O* 13 4 Z* O* Rev.7.00 Oct. 10, 2008 Page 1033 of 1074 REJ09B0366-0700 Appendix E Pin Functions Reset (Power-On) Signal Name WE1/CAS1/DQM1 WE0/CAS0/DQM0 DACK1–DACK0 MD7/TXD MD6/IOIS16 MD5/RAS2 MD4/CE2B MD3/CE2A CKIO STATUS1–STATUS0 IRL3–IRL0 NMI DREQ1–DREQ0 DRAK1–DRAK0 MD0/SCK RXD SCK2/MRESET MD1/TXD2 MD2/RXD2 CTS2 MD8/RTS2 TCLK TDO TMS TCK TDI TRST CKIO2* 21 Reset (Manual) Master O O L Slave Z* Z* L 11 13 I/O O O O I/O I 1 I/O* Master H H L PI* 14 Slave PZ PZ L P I* 14 Standby 13 4 Z* O* Bus Hardware Released Standby 13 4 Z* O* Z Z Z 13 Z* O* Z* O * 11 13 4 Z* O* O 7 11 13 4 7 Z* Z* 11 Z* K* O* Z* K* O* Z 12 Z* 13 4 Z* O* 13 6 Z* H* 13 6 Z* H* 10 11 18 18 7 14 P I* 14 P I* 14 P I* 14 P I* 12 I* 13 5 Z* O* 13 6 Z* H* 13 6 Z* H* 12 I* 13 Z* 13 Z* 13 Z* I* 12 Z Z Z Z 10 13 4 Z* O* 13 Z* 13 Z* I/O* I/O* O O I I I O I/O I I I/O I I/O I/O I/O O I I I I O 3 P I* P I* O O PI PI PI L 14 P I* P I* O O PI PI PI L P I* PI PI 14 2 14 14 O* Z* O I* I* 12 10 10 O* Z* O I* I* 12 10 PZ O I* I* 12 O* Z* O I* I* 12 10 Z ZO* I I I Z Z Z Z 16 12 12 12 12 11 I* 11 I* 11 Z* 11 7 Z* O * 11 I* L 14 L 11 O 14 PI* I* I* I* I* 11 11 18 7 11 18 Z* K* O* I* OK* 11 Z* PI PI PI* PI* PI 14 PI* 14 I* I* 14 11 11 I* 11 11 11 I* 11 I* 18 7 11 P I* P I* PI Z* I* 11 Z* I* I* 11 Z* K* O* Z* K* O* Z 11 Z* 11 11 18 7 14 14 11 11 I* 18 11 Z 18 I* 11 11 Z* K* 11 I* K * 11 Z Z Z Z Z Z Z Z 14 P I* 11 I* 11 I* 11 I* 11 I* 11 18 Z* K* 11 17 K* O * 11 18 I* K * 11 17 I* O* PI O PI PI PI PI 20 9 PI O PI PI PI PI 20 9 O PI PI PI PI PZ* 9 20 O* * 20 O PI PI PI PI PZ* 9 20 O* * 20 O PZ PZ PZ PZ PZ O PI PI PI PI 20 9 20 PZ* O* PZ* O* PZ* O* * Z Rev.7.00 Oct. 10, 2008 Page 1034 of 1074 REJ09B0366-0700 Appendix E Pin Functions Reset (Power-On) Signal Name RD2* 21 Reset (Manual) Master 13 20 Z* * 9 O* 13 20 Z* * *9 H I/O O Master 20 Z* 9 20 H* * 20 Z* *9*20 H Slave 20 9 Z* PZ* Slave 9 13 Z* * Standby 9 13 4 Z* * O* Bus Hardware Released Standby 9 13 4 Z* * O* Z Z Z I RD/WR2* 21 O I I I/O 20 9 Z* PZ* 9 13 Z* * 9 13 4 Z* * H* 9 13 Z* * CKIO2ENB CA ASEBRK/BRKACK PI I PI* O* 22 22 PI I PI* O* 22 22 PI I PI* O* 22 22 PI I PI* O* 22 22 PI I PI* O* 22 22 PI I PI* O* 22 22 Z Legend: I: Input (not Pulled Up) O: Output Z: High-impedance (not Pulled Up) H: High-level output L: Low-level output K: Output state held PI: Input (Pulled Up) PZ: High-impedance (Pulled Up) Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Output when area 2 is used as DRAM. Output when area 5 is used as PCMCIA. Output when area 6 is used as PCMCIA. Z (I) or O on refresh operations, depending on register setting (BCR1.HIZCNT). Depends on refresh operations. Z (I) or H (state held), depending on register setting (BCR1.HIZMEM). Z or O, depending on register setting (STBCR.PHZ). Output when refreshing is set. Operation in respective state when CKIO2ENB = 0 (SH7750/SH7750S) (High-level outputs as SH7750R). PZ or O, depending on register setting (FRQCR.CKOEN). Pulled up or not pulled up, depending on register setting (STBCR.PPU). Pulled up or not pulled up, depending on register setting (BCR1.IPUP). Pulled up or not pulled up, depending on register setting (BCR1.OPUP). Pulled up with a built-in pull-up resistance. However it, cannot use for fixation of an input MD pin at the time of power-on reset. Pull up or down outside this LSI. Output when refreshing is set (SH7750R only). Z or O, depending on register setting (STBCR2.STHZ) (SH7750R only). Z or O, depending on register setting (TOCR, TCOE) Rev.7.00 Oct. 10, 2008 Page 1035 of 1074 REJ09B0366-0700 Appendix E Pin Functions 18. Output state held when used as port. 19. Pulled up or not pulled up, depending on register setting (BCR1.DPUP) (SH7750R only). 20. Z when CKIO2ENB = 1 21. BGA Package only. 22. Depends on Emulator operations. E.2 Handling of Unused Pins • When RTC is not used ⎯ EXTAL2: Pull up to 3.3 V ⎯ XTAL2: Leave unconnected ⎯ VDD-RTC: Power supply (3.3 V) ⎯ VSS-RTC: Power supply (0 V) • When PLL1 is not used ⎯ VDD-PLL1: Power supply (3.3 V) ⎯ VSS-PLL1: Power supply (0 V) • When PLL2 is not used ⎯ VDD-PLL2: Power supply (3.3 V) ⎯ VSS-PLL2: Power supply (0 V) • When on-chip crystal oscillator is not used ⎯ XTAL: Leave unconnected ⎯ VDD-CPG: Power supply (3.3 V) ⎯ VSS-CPG: Power supply (0 V) Note: To prevent unwanted effects on other pins when using external pull-up or pull-down resistors, use independent pull-up or pull-down resistors for individual pins. Rev.7.00 Oct. 10, 2008 Page 1036 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables Appendix F Synchronous DRAM Address Multiplexing Tables (1) BUS 64 AMX 0 (16M: 512k × 16b × 2) × 4 * AMXEXT 0 16M, column-addr-8bit Synchronous DRAM Address Pins A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 8MB Function BANK selects bank address Address precharge setting Address LSI Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Not used CAS Cycle A22 H/L 0 0 A10 A9 A8 A7 A6 A5 A4 A3 Rev.7.00 Oct. 10, 2008 Page 1037 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (2) BUS 32 AMX 0 (16M: 512k × 16b × 2) × 2 * AMXEXT 0 16M, column-addr-8bit Synchronous DRAM Address Pins 4MB Function LSI Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A21 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev.7.00 Oct. 10, 2008 Page 1038 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (3) BUS 64 AMX 0 (16M: 512k × 16b × 2) × 4 * AMXEXT 1 16M, column-addr-8bit Synchronous DRAM Address Pins A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 8MB Function BANK selects bank address Address precharge setting Address LSI Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A21 A22 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Not used CAS Cycle A21 H/L 0 0 A10 A9 A8 A7 A6 A5 A4 A3 Rev.7.00 Oct. 10, 2008 Page 1039 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (4) BUS 32 AMX 0 (16M: 512k × 16b × 2) × 2 * AMXEXT 1 16M, column-addr-8bit Synchronous DRAM Address Pins 4MB Function LSI Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A20 A21 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A20 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev.7.00 Oct. 10, 2008 Page 1040 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (5) BUS 64 AMX 1 (16M: 1M × 8b × 2) × 8 * AMXEXT 0 16M, column-addr-9bit Synchronous DRAM Address Pins A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16MB Function BANK selects bank address Address precharge setting Address LSI Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Not used Not used Not used CAS Cycle A23 H/L 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 Rev.7.00 Oct. 10, 2008 Page 1041 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (6) BUS 32 AMX 1 (16M: 1M × 8b × 2) × 4 * AMXEXT 0 16M, column-addr-9bit Synchronous DRAM Address Pins 8MB Function LSI Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used A22 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev.7.00 Oct. 10, 2008 Page 1042 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (7) BUS 64 AMX 1 (16M: 1M × 8b × 2) × 8 * AMXEXT 1 16M, column-addr-9bit Synchronous DRAM Address Pins A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16MB Function BANK selects bank address Address precharge setting Address LSI Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A23 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Not used Not used Not used CAS Cycle A22 H/L 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 Rev.7.00 Oct. 10, 2008 Page 1043 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (8) BUS 32 AMX 1 (16M: 1M × 8b × 2) × 4 * AMXEXT 1 16M, column-addr-9bit Synchronous DRAM Address Pins 8MB Function LSI Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A21 A22 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used A21 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev.7.00 Oct. 10, 2008 Page 1044 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (9) BUS 64 AMX 2 (64M: 1M × 16b × 4) × 4 * 64M, column-addr-8bit 32MB Function BANK selects bank address LSI Address Pins RAS Cycle A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Not used CAS Cycle A24 A23 0 H/L 0 0 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Address precharge setting Rev.7.00 Oct. 10, 2008 Page 1045 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (10) BUS 32 AMX 2 (64M: 1M × 16b × 4) × 2 * 64M, column-addr-8bit 16MB Function LSI Address Pins RAS Cycle A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A23 A22 0 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle Synchronous DRAM Address Pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev.7.00 Oct. 10, 2008 Page 1046 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (11) BUS 64 AMX 3 (64M: 2M × 8b × 4) × 8 * (128M: 2M × 16b × 4) × 4 * 64M, column-addr-9bit 64MB Function BANK selects bank address LSI Address Pins RAS Cycle A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Not used Not used Not used CAS Cycle A25 A24 0 H/L 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Address precharge setting Rev.7.00 Oct. 10, 2008 Page 1047 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (12) BUS 32 AMX 3 (64M: 2M × 8b × 4) × 4 * (128M: 2M × 16b × 4) × 2 64M, column-addr-9bit 32MB Function LSI Address Pins RAS Cycle A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used A24 A23 0 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle Synchronous DRAM Address Pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev.7.00 Oct. 10, 2008 Page 1048 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (13) BUS 64 AMX 4 (64M: 512k × 32b × 4) × 2 * 64M, column-addr-8bit 16MB Function BANK selects bank address LSI Address Pins RAS Cycle A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Not used CAS Cycle A23 A22 H/L 0 0 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address precharge setting Address Rev.7.00 Oct. 10, 2008 Page 1049 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (14) BUS 32 AMX 4 (64M: 512k × 32b × 4) × 1 * 64M, column-addr-8bit 8MB Function LSI Address Pins RAS Cycle A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A22 A21 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle Synchronous DRAM Address Pins A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev.7.00 Oct. 10, 2008 Page 1050 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (15) BUS 64 AMX 5 (64M: 1M × 32b × 2) × 2 * 64M, column-addr-8bit 16MB Function BANK selects bank address LSI Address Pins RAS Cycle A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Not used CAS Cycle A23 0 H/L 0 0 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address precharge setting Address Rev.7.00 Oct. 10, 2008 Page 1051 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (16) BUS 32 AMX 5 (64M: 1M × 32b × 2) × 1 * 64M, column-addr-8bit 8MB Function LSI Address Pins RAS Cycle A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A22 0 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle Synchronous DRAM Address Pins A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Rev.7.00 Oct. 10, 2008 Page 1052 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (17) BUS 64 (128M: 4M × 8b × 4) × 8* (SH7750R only) AMX 6 128M, column-addr-10bit 128MB AMXEXT0 LSI Address Pins RAS Cycle CAS Cycle A26 A25 0 H/L A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address precharge setting Address Function BANK selects bank address A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 Not used Not used Not used Rev.7.00 Oct. 10, 2008 Page 1053 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (18) BUS 64 (256M: 4M × 16b × 4) × 4 (SH7750R only) * AMX 6 256M, column-addr-9bit 128MB AMXEXT1 LSI Address Pins RAS Cycle CAS Cycle A26 A25 0 0 H/L 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address precharge setting Address Function BANK selects bank address A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Not used Not used Not used Rev.7.00 Oct. 10, 2008 Page 1054 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (19) BUS 32 (128M: 4M × 8b × 4) × 4 (SH7750S and SH7750R only) * AMX 6 column-addr-10bit 64MB AMXEXT 0 LSI Address Pins RAS Cycle CAS Cycle A25 A24 0 H/L A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Synchronous DRAM Address Pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address precharge setting Address Function BANK selects bank address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Not used Not used Rev.7.00 Oct. 10, 2008 Page 1055 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (20) BUS 32 (256M: 4M × 16b × 4) × 2 (SH7750S and SH7750R only) * AMX 6 256M, column-addr-9bit 64MB AMXEXT 1 LSI Address Pins RAS Cycle CAS Cycle A25 A24 0 0 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 Synchronous DRAM Address Pins A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address precharge setting Address Function BANK selects bank address A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Rev.7.00 Oct. 10, 2008 Page 1056 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (21) BUS 64 AMX 7 (16M: 256k × 32b × 2) × 2 * 16M, column-addr-8bit 4MB Function BANK selects bank address Address precharge setting Address LSI Address Pins RAS Cycle A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used Not used CAS Cycle A21 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 Synchronous DRAM Address Pins A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Rev.7.00 Oct. 10, 2008 Page 1057 of 1074 REJ09B0366-0700 Appendix F Synchronous DRAM Address Multiplexing Tables (22) BUS 32 AMX 7 (16M: 256k × 32b × 2) × 1 * 16M, column-addr-8bit 2MB Function LSI Address Pins RAS Cycle A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A20 H/L 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle Synchronous DRAM Address Pins A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BANK selects bank address Address precharge setting Address Note: * Example of a synchronous DRAM configuration Rev.7.00 Oct. 10, 2008 Page 1058 of 1074 REJ09B0366-0700 Appendix G Prefetching of Instructions and its Side Effects Appendix G Prefetching of Instructions and its Side Effects This LSI incorporates an on-chip buffer for holding instructions that have been read ahead of their execution (prefetching of instructions). Therefore, do not allocate programs to memory in such a way that instructions are in the last 20 bytes of any memory space. If a program is allocated in such a way, the prefetching of instructions may lead to a bus access for reading an instruction from beyond the memory space. The following shows a case in which such bus access is a problem. . . . . . . ADD R1,R4 JMP @R2 NOP NOP PC (Program counter) Address H'03FFFFF8 H'03FFFFFA H'03FFFFFC H'03FFFFFE H'04000000 H'04000002 Area 0 Area 1 Address of instruction for prefetching Figure G.1 Instruction Prefetch Figure G.1 depicts a case in which the instruction (ADD) indicated by the program counter and the instruction at the address H'04000002 are fetched simultaneously. The program is assumed to branch to a region other than area 1 after the subsequent JMP instruction and delay slot instruction have been executed. In this case, a bus access to area 1 (instruction prefetch), which is not visible in the program flow, may occur. 1. Side effects of the prefetching of instructions a. An external bus access caused by an instruction prefetch may cause malfunctions in external devices, such as FIFOs, that are connected to the region accessed. b. If no device responds to an external bus request that is triggered by an instruction prefetch, execution may hang. 2. Methods of preventing the invalid prefetching of instructions a. Use an MMU. b. Do not allocate programs so that they run into the last 20-byte region of any memory space. Rev.7.00 Oct. 10, 2008 Page 1059 of 1074 REJ09B0366-0700 Appendix G Prefetching of Instructions and its Side Effects Rev.7.00 Oct. 10, 2008 Page 1060 of 1074 REJ09B0366-0700 Appendix H Power-On and Power-Off Procedures Appendix H Power-On and Power-Off Procedures H.1 Power-On Stipulations 1. Supply power to power supply VDDQ and to I/O, RTC, CPG, PLL1, and PLL2 simultaneously. 2. Perform input to the signal lines (RESET, MRESET, MD0 to MD10, external clock, etc.) after or at the same time power is supplied to VDDQ. Applying input to signal lines before power is supplied to VDDQ could damage the product. ⎯ Drive the RESET signal low when power is first supplied to VDDQ. ⎯ Input a high-level MRESET signal in the same sequence as power supply VDDQ when power is first supplied to VDDQ. 3. It is recommended to apply power first to power supply VDDQ and then to power supply VDD. 4. In addition to 1., 2., and 3. above, also observe the stipulations in H.3. Furthermore: ⎯ There are no time restrictions on the power-on sequence for power supply VDDQ and power supply VDD with regard to the LSI alone. Refer to figure H.1. Nevertheless, it is recommended that the power-on sequence be completed in as short a time as possible. ⎯ When the LSI is mounted on a board and connected to other elements, ensure that –0.3 V < Vin < VDDQ + 0.3 V. In addition, the time limit for the rise of power supply VDDQ and power supply VDD from GND (0 V) to above the minimum values in the LSI’s guaranteed operation voltage range (VDDQ (min.) and VDD (min.)) is 100 ms (max.), as shown in figure H.2. The product may be damaged if this time limit is exceeded. It is recommended that the power-on sequence be completed in as short a time as possible. H.2 Power-Off Stipulations 1. Power off power supply VDDQ and I/O, RTC, CPG, PLL1, and PLL2 simultaneously. 2. There are no timing restrictions for the RESET and MRESET signal lines at power-off. 3. Cut off the input signal level for signal lines other than RESET and MRESET in the same sequence as power supply VDDQ. 4. It is recommended to first power off power supply VDD and then power supply VDDQ. 5. In addition to 1., 2., 3., and 4. above, also observe the stipulations in H.3. Furthermore: ⎯ There are no time restrictions on the power-off sequence for power supply VDDQ and power supply VDD with regard to the LSI alone. Refer to figure H.1. Nevertheless, it is recommended that the power-off sequence be completed in as short a time as possible. Rev.7.00 Oct. 10, 2008 Page 1061 of 1074 REJ09B0366-0700 Appendix H Power-On and Power-Off Procedures ⎯ When the LSI is mounted on a board and connected to other elements, ensure that –0.3 V < Vin < VDDQ + 0.3 V. In addition, the time limit for the fall of power supply VDDQ and power supply VDD from the minimum values in the LSI’s guaranteed operation voltage range (VDDQ (min.) and VDD (min.)) to GND (0 V) is 150 ms (max.), as shown in figure H.2. The product may be damaged if this time limit is exceeded. It is recommended that the power-off sequence be completed in as short a time as possible. H.3 Common Stipulations for Power-On and Power-Off 1. Always ensure that VDDQ = VDD−CPG = VDD−RTC = VDD−PLL1/2. Refer to 9.8.5, Hardware Standby Mode Timing (SH7750S, SH7750R Only), regarding VDD−RTC in hardware standby mode on the SH7750S and SH7750R. 2. Ensure that −0.3 V < VDD < VDDQ + 0.3 V. 3. Ensure that VSS = VSSQ = VSS−PLL1/2 = VSS−CPG = VSS−RTC = GND (0 V). The product may be damaged if conditions 1., 2., and 3. above are not satisfied. [V] Power-on Power supply VDDQ Power-off Power supply VDD 0.3 V (max) 0.3 V (max) GND [t] Figure H.1 Power-On Procedure 1 Rev.7.00 Oct. 10, 2008 Page 1062 of 1074 REJ09B0366-0700 Appendix H Power-On and Power-Off Procedures [V] VDDQ(min) Power-on Power supply VDDQ Power-off Power supply VDD VDD(min) GND tpwu tpwu