SH77641

REJ09B0360-0100 32 SH7764 Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series SH77641 SH77640 R5S77641 R5S77640 Rev.1.00 Revision Date: Nov. 22, 2007 Rev. 1.00 Nov. 22, 2007 Page ii of lvi Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 1.00 Nov. 22, 2007 Page iii of lvi General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed. 5. Reading from/Writing to Reserved Bit of Each Register Note: Treat the reserved bit of register used in each module as follows except in cases where the specifications for values which are read from or written to the bit are provided in the description. The bit is always read as 0. The write value should be 0 or one, which has been read immediately before writing. Writing the value, which has been read immediately before writing has the advantage of preventing the bit from being affected on its extended function when the function is assigned. Rev. 1.00 Nov. 22, 2007 Page iv of lvi Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. Electrical Characteristics 8. Appendix 9. Index Rev. 1.00 Nov. 22, 2007 Page v of lvi Preface This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users. Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. • In order to understand the details on FPU functions and each instructions Read the additional volume, SH-4A Extended Functions Software Manual. Rules: Bit order: Number notation: Signal notation: The MSB is on the left and the LSB is on the right. Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. An overbar is added to a low-active signal: xxxx Rev. 1.00 Nov. 22, 2007 Page vi of lvi Abbreviations ATAPI CPG DMAC E-DMAC EtherC FLCTL G2D GPIO H-UDI IIC INTC MCU MMU SCIF TMU UBC USB VDC2 WDT SSI LCDC SRC ATAPI Controller Clock Pulse Generator Direct Memory Access Controller Ethernet Controller Direct Memory Access Controller Ethernet Controller NAND Flash Memory Controller 2D Graphics Engine General Purpose I/O User Debugging Interface I2C Bus Interface Interrupt Controller Memory Controller Unit Memory Management Unit Serial Communication Interface with FIFO Timer Unit User Break Controller USB Host/Function Interface Video Display Controller 2 Watchdog Timer and Reset Serial Sound Interface LCD Controller Sampling Rate Converter Rev. 1.00 Nov. 22, 2007 Page vii of lvi bps CRC DMA DMAC Hi-Z I/O LSB MSB NC PLL bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller High Impedance Input/Output Least Significant Bit Most Significant Bit Non-Connection Phase Locked Loop All trademarks and registered trademarks are the property of their respective owners. Rev. 1.00 Nov. 22, 2007 Page viii of lvi Contents Section 1 Overview......................................................................................................................... 1 1.1 SH7764 Features.................................................................................................................... 1 1.2 Block Diagram ..................................................................................................................... 12 1.3 Pin Arrangement .................................................................................................................. 14 1.4 Pin Functions ....................................................................................................................... 15 1.5 Address Map ........................................................................................................................ 28 Section 2 Programming Model ............................................................................31 2.1 2.2 Data Formats........................................................................................................................ 31 Register Descriptions ........................................................................................................... 32 2.2.1 Privileged Mode and Banks .................................................................................... 32 2.2.2 General Registers.................................................................................................... 36 2.2.3 Floating-Point Registers.......................................................................................... 37 2.2.4 Control Registers .................................................................................................... 39 2.2.5 System Registers..................................................................................................... 41 Memory-Mapped Registers.................................................................................................. 45 Data Formats in Registers .................................................................................................... 46 Data Formats in Memory ..................................................................................................... 46 Processing States.................................................................................................................. 47 Usage Notes ......................................................................................................................... 49 2.7.1 Notes on Self-Modifying Code ............................................................................... 49 2.3 2.4 2.5 2.6 2.7 Section 3 Instruction Set ......................................................................................51 3.1 3.2 3.3 Execution Environment ....................................................................................................... 51 Addressing Modes ............................................................................................................... 53 Instruction Set ...................................................................................................................... 58 Section 4 Pipelining .............................................................................................71 4.1 4.2 4.3 Pipelines............................................................................................................................... 71 Parallel-Executability........................................................................................................... 82 Issue Rates and Execution Cycles........................................................................................ 85 Section 5 Exception Handling .............................................................................95 5.1 5.2 Summary of Exception Handling......................................................................................... 95 Register Descriptions ........................................................................................................... 95 5.2.1 TRAPA Exception Register (TRA) ........................................................................ 96 5.2.2 Exception Event Register (EXPEVT)..................................................................... 97 Rev. 1.00 Nov. 22, 2007 Page ix of lvi 5.3 5.4 5.5 5.6 5.7 5.2.3 Interrupt Event Register (INTEVT)........................................................................ 98 5.2.4 Non-Support Detection Exception Register (EXPMASK) ..................................... 99 Exception Handling Functions........................................................................................... 101 5.3.1 Exception Handling Flow ..................................................................................... 101 5.3.2 Exception Handling Vector Addresses ................................................................. 101 Exception Types and Priorities .......................................................................................... 102 Exception Flow .................................................................................................................. 104 5.5.1 Exception Flow..................................................................................................... 104 5.5.2 Exception Source Acceptance............................................................................... 106 5.5.3 Exception Requests and BL Bit ............................................................................ 107 5.5.4 Return from Exception Handling.......................................................................... 107 Description of Exceptions.................................................................................................. 108 5.6.1 Resets.................................................................................................................... 108 5.6.2 General Exceptions............................................................................................... 110 5.6.3 Interrupts............................................................................................................... 126 5.6.4 Priority Order with Multiple Exceptions .............................................................. 127 Usage Notes ....................................................................................................................... 129 Section 6 Floating-Point Unit (FPU)................................................................. 131 6.1 6.2 Features.............................................................................................................................. 131 Data Formats...................................................................................................................... 132 6.2.1 Floating-Point Format........................................................................................... 132 6.2.2 Non-Numbers (NaN) ............................................................................................ 135 6.2.3 Denormalized Numbers ........................................................................................ 136 Register Descriptions......................................................................................................... 137 6.3.1 Floating-Point Registers ....................................................................................... 137 6.3.2 Floating-Point Status/Control Register (FPSCR) ................................................. 139 6.3.3 Floating-Point Communication Register (FPUL) ................................................. 142 Rounding............................................................................................................................ 143 Floating-Point Exceptions.................................................................................................. 144 6.5.1 General FPU Disable Exceptions and Slot FPU Disable Exceptions ................... 144 6.5.2 FPU Exception Sources ........................................................................................ 144 6.5.3 FPU Exception Handling ...................................................................................... 145 Graphics Support Functions............................................................................................... 146 6.6.1 Geometric Operation Instructions......................................................................... 146 6.6.2 Pair Single-Precision Data Transfer...................................................................... 147 6.3 6.4 6.5 6.6 Section 7 Memory Management Unit (MMU).................................................. 149 7.1 Overview of MMU ............................................................................................................ 150 7.1.1 Address Spaces ..................................................................................................... 152 Rev. 1.00 Nov. 22, 2007 Page x of lvi 7.2 7.3 7.4 7.5 7.6 7.7 7.8 Register Descriptions ......................................................................................................... 158 7.2.1 Page Table Entry High Register (PTEH) .............................................................. 159 7.2.2 Page Table Entry Low Register (PTEL) ............................................................... 160 7.2.3 Translation Table Base Register (TTB) ................................................................ 161 7.2.4 TLB Exception Address Register (TEA) .............................................................. 162 7.2.5 MMU Control Register (MMUCR) ...................................................................... 162 7.2.6 Page Table Entry Assistance Register (PTEA)..................................................... 166 7.2.7 Physical Address Space Control Register (PASCR)............................................. 167 7.2.8 Instruction Re-Fetch Inhibit Control Register (IRMCR) ...................................... 168 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0)............................................ 170 7.3.1 Unified TLB (UTLB) Configuration .................................................................... 170 7.3.2 Instruction TLB (ITLB) Configuration................................................................. 173 7.3.3 Address Translation Method................................................................................. 173 TLB Functions (TLB Extended Mode; MMUCR.ME = 1) ............................................... 176 7.4.1 Unified TLB (UTLB) Configuration .................................................................... 176 7.4.2 Instruction TLB (ITLB) Configuration................................................................. 179 7.4.3 Address Translation Method................................................................................. 180 MMU Functions................................................................................................................. 183 7.5.1 MMU Hardware Management .............................................................................. 183 7.5.2 MMU Software Management ............................................................................... 183 7.5.3 MMU Instruction (LDTLB).................................................................................. 184 7.5.4 Hardware ITLB Miss Handling ............................................................................ 186 7.5.5 Avoiding Synonym Problems ............................................................................... 187 MMU Exceptions............................................................................................................... 189 7.6.1 Instruction TLB Multiple Hit Exception............................................................... 189 7.6.2 Instruction TLB Miss Exception........................................................................... 190 7.6.3 Instruction TLB Protection Violation Exception .................................................. 191 7.6.4 Data TLB Multiple Hit Exception ........................................................................ 192 7.6.5 Data TLB Miss Exception .................................................................................... 192 7.6.6 Data TLB Protection Violation Exception............................................................ 194 7.6.7 Initial Page Write Exception................................................................................. 195 Memory-Mapped TLB Configuration................................................................................ 197 7.7.1 ITLB Address Array ............................................................................................. 198 7.7.2 ITLB Data Array (TLB Compatible Mode).......................................................... 199 7.7.3 ITLB Data Array (TLB Extended Mode) ............................................................. 200 7.7.4 UTLB Address Array............................................................................................ 202 7.7.5 UTLB Data Array (TLB Compatible Mode) ........................................................ 203 7.7.6 UTLB Data Array (TLB Extended Mode)............................................................ 204 Usage Notes ....................................................................................................................... 206 7.8.1 Note on Using LDTLB Instruction ....................................................................... 206 Rev. 1.00 Nov. 22, 2007 Page xi of lvi Section 8 Caches................................................................................................ 207 8.1 8.2 Features.............................................................................................................................. 207 Register Descriptions......................................................................................................... 211 8.2.1 Cache Control Register (CCR) ............................................................................. 212 8.2.2 Queue Address Control Register 0 (QACR0)....................................................... 214 8.2.3 Queue Address Control Register 1 (QACR1)....................................................... 215 8.2.4 On-Chip Memory Control Register (RAMCR) .................................................... 216 Operand Cache Operation.................................................................................................. 218 8.3.1 Read Operation ..................................................................................................... 218 8.3.2 Prefetch Operation ................................................................................................ 219 8.3.3 Write Operation .................................................................................................... 220 8.3.4 Write-Back Buffer ................................................................................................ 221 8.3.5 Write-Through Buffer........................................................................................... 221 8.3.6 OC Two-Way Mode ............................................................................................. 222 Instruction Cache Operation .............................................................................................. 223 8.4.1 Read Operation ..................................................................................................... 223 8.4.2 Prefetch Operation ................................................................................................ 223 8.4.3 IC Two-Way Mode............................................................................................... 224 8.4.4 Instruction Cache Way Prediction Operation ....................................................... 224 Cache Operation Instruction .............................................................................................. 225 8.5.1 Coherency between Cache and External Memory ................................................ 225 8.5.2 Prefetch Operation ................................................................................................ 227 Memory-Mapped Cache Configuration ............................................................................. 228 8.6.1 IC Address Array.................................................................................................. 228 8.6.2 IC Data Array ....................................................................................................... 230 8.6.3 OC Address Array ................................................................................................ 230 8.6.4 OC Data Array...................................................................................................... 232 8.6.5 Memory-Mapped Cache Associative Write Operation......................................... 233 Store Queues ...................................................................................................................... 234 8.7.1 SQ Configuration.................................................................................................. 234 8.7.2 Writing to SQ........................................................................................................ 234 8.7.3 Transfer to External Memory ............................................................................... 235 8.7.4 Determination of SQ Access Exception................................................................ 236 8.7.5 Reading from SQ .................................................................................................. 236 8.3 8.4 8.5 8.6 8.7 Section 9 On-Chip Memory .............................................................................. 237 9.1 9.2 9.3 Features.............................................................................................................................. 237 Register Descriptions......................................................................................................... 238 9.2.1 On-Chip Memory Control Register (RAMCR) .................................................... 239 Operation ........................................................................................................................... 241 Rev. 1.00 Nov. 22, 2007 Page xii of lvi 9.4 9.5 9.3.1 Instruction Fetch Access from the CPU................................................................ 241 9.3.2 Operand Access from the CPU and Access from the FPU ................................... 241 9.3.3 Access from the SuperHyway Bus Master Module .............................................. 241 On-Chip Memory Protective Functions ............................................................................. 242 Usage Notes ....................................................................................................................... 243 9.5.1 Page Conflict ........................................................................................................ 243 9.5.2 Access Across Different Pages ............................................................................. 243 9.5.3 On-Chip Memory Coherency ............................................................................... 243 9.5.4 Sleep Mode ........................................................................................................... 243 Section 10 Clock Pulse Generator (CPG)..........................................................245 10.1 10.2 10.3 10.4 Features.............................................................................................................................. 245 Input/Output Pins ............................................................................................................... 248 Clock Operating Mode....................................................................................................... 249 Register Descriptions ......................................................................................................... 250 10.4.1 Frequency Control Register (FRQCR) ................................................................. 251 10.4.2 PLL Control Register (PLLCR)............................................................................ 253 10.4.3 VDC2 Clock Control Register (VDC2CLKCR)................................................... 254 Section 11 Memory Controller Unit (MCU) .....................................................255 11.1 Features.............................................................................................................................. 255 11.2 Input/Output Pins ............................................................................................................... 258 11.3 Area Overview ................................................................................................................... 260 11.3.1 Space Divisions..................................................................................................... 260 11.3.2 Memory Bus Width .............................................................................................. 261 11.3.3 Endian Setting....................................................................................................... 262 11.4 Register Description........................................................................................................... 263 11.4.1 Version Control Register (VCR)........................................................................... 266 11.4.2 Memory Interface Mode Register (MIM) ............................................................. 267 11.4.3 SDRAM Control Register (SCR).......................................................................... 271 11.4.4 SDRAM Timing Register (STR) .......................................................................... 273 11.4.5 SDRAM Row Attribute Register (SDRA)............................................................ 276 11.4.6 SDRAM Mode Register (SDMR)......................................................................... 278 11.4.7 Arbitration Mode Register (AMR) ....................................................................... 279 11.4.8 Linear-to-Tiled Memory Address Translation Control Register (LTCn).............. 280 11.4.9 Linear-to-Tiled Memory Address Translation Area Start Address Register (LTADn) ............................................................................................................... 282 11.4.10 Linear-to-Tiled Memory Address Translation Area Start Address Mask Register (LTAMn) ................................................................................................ 283 11.4.11 Request Mask Setting Register (RQM) ................................................................ 284 Rev. 1.00 Nov. 22, 2007 Page xiii of lvi 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.4.12 Bus Control Register (BCR) ................................................................................. 287 11.4.13 CS0 Bus Control Register (CS0BCR) .................................................................. 290 11.4.14 CSn Wait Control Register (CSnWCR) ................................................................ 295 11.4.15 CS3 Bus Control Register (CS3BCR) .................................................................. 301 Operation ........................................................................................................................... 307 11.5.1 Endian/Access Size and Data Alignment.............................................................. 307 11.5.2 Data Alignment in Various Modules .................................................................... 316 SRAM Interface................................................................................................................. 316 11.6.1 Basic Timing......................................................................................................... 316 11.6.2 Wait Cycle Control ............................................................................................... 320 11.6.3 Read-Strobe Negate Timing ................................................................................. 322 SDRAM Interface .............................................................................................................. 323 11.7.1 SDRAM Direct Connection.................................................................................. 323 11.7.2 Address Multiplexing ........................................................................................... 326 11.7.3 Burst Read ............................................................................................................ 328 11.7.4 Burst Write ........................................................................................................... 329 11.7.5 Single Read........................................................................................................... 330 11.7.6 Single Write .......................................................................................................... 331 11.7.7 Bank Open Mode.................................................................................................. 332 11.7.8 Refresh.................................................................................................................. 337 11.7.9 SDRAM Initialization Sequence........................................................................... 338 Wait Cycles between Accesses .......................................................................................... 339 11.8.1 Wait Cycles between Accesses to Area 0 or 3...................................................... 339 11.8.2 Wait Cycles between Accesses to Area 1 or 2...................................................... 339 11.8.3 Wait Cycles between Access to Area 1 or 2 and the Subsequent Access to Area 0 or 3 ............................................................................................................ 339 Bus Arbitration .................................................................................................................. 340 11.9.1 Arbitration of Accesses between Internal Modules .............................................. 340 11.9.2 Multi-Step Arbitration .......................................................................................... 343 11.9.3 Bus Requests from External Devices.................................................................... 346 11.9.4 Bus Release and Recovery Sequences .................................................................. 347 11.9.5 Cooperation between Master and Slave................................................................ 349 Data Coherency.................................................................................................................. 349 Linear-to-Tiled Memory Address Translation ................................................................... 352 Usage Notes ....................................................................................................................... 357 11.12.1 Refresh.................................................................................................................. 357 11.12.2 External Bus Arbitration....................................................................................... 357 Rev. 1.00 Nov. 22, 2007 Page xiv of lvi Section 12 Direct Memory Access Controller (DMAC) ...................................359 12.1 Features.............................................................................................................................. 359 12.2 Input/Output Pins ............................................................................................................... 361 12.3 Register Descriptions ......................................................................................................... 362 12.3.1 DMA Source Address Registers (SAR0 to SAR5) ............................................... 366 12.3.2 DMA Source Address Registers (SARB0 to SARB3).......................................... 367 12.3.3 DMA Destination Address Registers (DAR0 to DAR5) ...................................... 367 12.3.4 DMA Destination Address Registers (DARB0 to DARB3) ................................. 368 12.3.5 DMA Transfer Count Registers (TCR0 to TCR5) ................................................ 368 12.3.6 DMA Transfer Count Registers (TCRB0 to TCRB3)........................................... 369 12.3.7 DMA Channel Control Registers (CHCR0 to CHCR5)........................................ 370 12.3.8 DMA Operation Register 0 (DMAOR0) .............................................................. 378 12.3.9 DMA Extended Resource Selectors (DMARS0 to DMARS2)............................. 381 12.4 Operation ........................................................................................................................... 384 12.4.1 DMA Transfer Requests ....................................................................................... 384 12.4.2 Channel Priority.................................................................................................... 388 12.4.3 DMA Transfer Types............................................................................................ 391 12.4.4 DMA Transfer Flow ............................................................................................. 398 12.4.5 Repeat Mode Transfer........................................................................................... 400 12.4.6 Reload Mode Transfer .......................................................................................... 401 12.4.7 DREQ Pin Sampling Timing ................................................................................ 402 12.5 Usage Notes ....................................................................................................................... 406 12.5.1 Module Stop.......................................................................................................... 406 12.5.2 Address Error........................................................................................................ 406 12.5.3 Notes on Burst Mode Transfer.............................................................................. 406 12.5.4 DACK Output Division and External Request ..................................................... 407 12.5.5 DMA Transfer to DMAC Prohibited .................................................................... 407 12.5.6 NMI Interrupt........................................................................................................ 407 Section 13 Interrupt Controller (INTC) .............................................................409 13.1 Features.............................................................................................................................. 409 13.1.1 Interrupt Method ................................................................................................... 411 13.1.2 Interrupt Types in INTC ....................................................................................... 412 13.2 Input/Output Pins ............................................................................................................... 414 13.3 Register Descriptions ......................................................................................................... 415 13.3.1 Interrupt Control Register 0 (ICR0)...................................................................... 419 13.3.2 Interrupt Control Register 1 (ICR1)...................................................................... 421 13.3.3 Interrupt Priority Register (INTPRI)..................................................................... 422 13.3.4 Interrupt Source Register (INTREQ).................................................................... 423 Rev. 1.00 Nov. 22, 2007 Page xv of lvi 13.4 13.5 13.6 13.7 13.3.5 Interrupt Mask Register (INTMSK) ..................................................................... 424 13.3.6 Interrupt Mask Clear Register (INTMSKCLR) .................................................... 425 13.3.7 NMI Flag Control Register (NMIFCR) ................................................................ 426 13.3.8 User Interrupt Mask Level Register (USERIMASK) ........................................... 428 13.3.9 On-Chip Module Interrupt Priority Registers (INT2PRI0 to INT2PRI12) ........... 430 13.3.10 Interrupt Source Register 0 (Mask State is not affected) (INT2A0) ..................... 432 13.3.11 Interrupt Source Register 01 (Mask State is not affected) (INT2A01) ................. 434 13.3.12 Interrupt Source Register (Mask State is affected) (INT2A1) .............................. 436 13.3.13 Interrupt Source Register 11 (Mask State is affected) (INT2A11) ....................... 438 13.3.14 Interrupt Mask Register (INT2MSKR)................................................................. 440 13.3.15 Interrupt Mask Register 1 (INT2MSKR1)............................................................ 442 13.3.16 Interrupt Mask Clear Register (INT2MSKCR) .................................................... 444 13.3.17 Interrupt Mask Clear Register 1 (INT2MSKCR1)................................................ 446 13.3.18 On-Chip Module Interrupt Source Registers (INT2B0 and INT2B2 to INT2B7) ....................................................................... 448 13.3.19 GPIO Interrupt Set Register (INT2GPIC) .............................................................. 453 Interrupt Sources................................................................................................................ 455 13.4.1 NMI Interrupt........................................................................................................ 455 13.4.2 IRQ Interrupts....................................................................................................... 455 13.4.3 On-Chip Module Interrupts .................................................................................. 456 13.4.4 Interrupt Priority Level of On-Chip Module Interrupts ........................................ 456 13.4.5 Interrupt Exception Handling and Priority............................................................ 457 Operation ........................................................................................................................... 462 13.5.1 Interrupt Sequence ................................................................................................ 462 13.5.2 Multiple Interrupts ................................................................................................ 464 13.5.3 Interrupt Masking by MAI Bit.............................................................................. 464 Interrupt Response Time.................................................................................................... 465 Usage Notes ....................................................................................................................... 466 13.7.1 To Clear Interrupt Request When Holding Function Selected ............................. 466 13.7.2 Notes on Setting IRQ1 and IRQ0 Pin Function .................................................... 467 13.7.3 To Clear IRQ Interrupt Requests .......................................................................... 467 Section 14 Timer Unit (TMU)........................................................................... 469 14.1 Features.............................................................................................................................. 469 14.2 Input/Output Pins............................................................................................................... 471 14.3 Register Descriptions......................................................................................................... 472 14.3.1 Timer Output Control Register (TOCR)............................................................... 474 14.3.2 Timer Start Register (TSTR0, TSTR1)................................................................. 475 14.3.3 Timer Constant Register (TCORn) (n = 0 to 5) .................................................... 477 14.3.4 Timer Counter (TCNTn) (n = 0 to 5).................................................................... 477 Rev. 1.00 Nov. 22, 2007 Page xvi of lvi 14.3.5 Timer Control Registers (TCRn) (n = 0 to 5) ....................................................... 478 14.3.6 Input Capture Register 2 (TCPR2)........................................................................ 480 14.4 Operation ........................................................................................................................... 481 14.4.1 Counter Operation................................................................................................. 481 14.4.2 Input Capture Function ......................................................................................... 484 14.5 Interrupts............................................................................................................................ 486 14.6 Usage Notes ....................................................................................................................... 487 14.6.1 Register Writes ..................................................................................................... 487 14.6.2 Reading from TCNT............................................................................................. 487 14.6.3 External Clock Frequency..................................................................................... 487 Section 15 Serial Communication Interface with FIFO (SCIF) ........................489 15.1 Features.............................................................................................................................. 489 15.2 Input/Output Pins ............................................................................................................... 492 15.3 Register Descriptions ......................................................................................................... 493 15.3.1 Receive Shift Register (SCRSR)........................................................................... 496 15.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 496 15.3.3 Transmit Shift Register (SCTSR) ......................................................................... 497 15.3.4 Transmit FIFO Data Register (SCFTDR) ............................................................. 497 15.3.5 Serial Mode Register (SCSMR)............................................................................ 498 15.3.6 Serial Control Register (SCSCR).......................................................................... 501 15.3.7 Serial Status Register (SCFSR) ............................................................................ 505 15.3.8 Bit Rate Register (SCBRR) .................................................................................. 513 15.3.9 FIFO Control Register (SCFCR) .......................................................................... 518 15.3.10 FIFO Data Count Set Register (SCFDR) .............................................................. 521 15.3.11 Serial Port Register (SCSPTR) ............................................................................. 522 15.3.12 Line Status Register (SCLSR) .............................................................................. 525 15.3.13 Serial Extension Mode Register (SCEMR)........................................................... 526 15.4 Operation ........................................................................................................................... 527 15.4.1 Overview............................................................................................................... 527 15.4.2 Operation in Asynchronous Mode ........................................................................ 530 15.4.3 Operation in Clock Synchronous Mode................................................................ 541 15.5 SCIF Interrupts .................................................................................................................. 549 15.6 Usage Notes ....................................................................................................................... 550 15.6.1 SCFTDR Writing and TDFE Flag ........................................................................ 550 15.6.2 SCFRDR Reading and RDF Flag ......................................................................... 550 15.6.3 Break Detection and Processing ........................................................................... 551 15.6.4 Sending a Break Signal......................................................................................... 551 15.6.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 551 15.6.6 Selection of Base Clock in Asynchronous Mode.................................................. 553 Rev. 1.00 Nov. 22, 2007 Page xvii of lvi Section 16 I2C Bus Interface (IIC)..................................................................... 555 16.1 Features.............................................................................................................................. 555 16.2 Input/Output Pins............................................................................................................... 556 16.3 Register Descriptions......................................................................................................... 556 16.3.1 Slave Control Register (ICSCR)........................................................................... 558 16.3.2 Slave Status Register (ICSSR).............................................................................. 559 16.3.3 Slave Interrupt Enable Register (ICSIER) ............................................................ 562 16.3.4 Slave Address Register (ICSAR).......................................................................... 563 16.3.5 Master Control Register (ICMCR) ....................................................................... 564 16.3.6 Master Status Register (ICMSR) .......................................................................... 566 16.3.7 Master Interrupt Enable Register (ICMIER) ........................................................ 568 16.3.8 Master Address Register (ICMAR) ...................................................................... 569 16.3.9 Clock Control Register (ICCCR).......................................................................... 569 16.3.10 Receive and Transmit Data Registers (ICRXD and ICTXD) ............................... 571 16.4 Operations.......................................................................................................................... 572 16.4.1 Data and Clock Filters .......................................................................................... 572 16.4.2 Clock Generator.................................................................................................... 572 16.4.3 Master/Slave Interfaces......................................................................................... 572 16.4.4 Software Status Interlocking................................................................................. 572 16.4.5 I2C Bus Data Format ............................................................................................. 574 16.4.6 7-Bit Address Format............................................................................................ 575 16.4.7 10-Bit Address Format.......................................................................................... 576 16.4.8 Master Transmit Operation................................................................................... 578 16.4.9 Master Receive Operation .................................................................................... 580 16.5 Programming Examples..................................................................................................... 582 16.5.1 Master Transmitter................................................................................................ 582 16.5.2 Master Receiver .................................................................................................... 583 16.5.3 Master Transmitter - Restart - Master Receiver.................................................... 584 Section 17 ATAPI ............................................................................................. 587 17.1 Features.............................................................................................................................. 587 17.2 Input/Output Pins............................................................................................................... 588 17.3 Register Description .......................................................................................................... 589 17.3.1 ATAPI Control (ATAPI_CONTROL) ................................................................. 592 17.3.2 ATAPI Status (ATAPI_STATUS) ....................................................................... 594 17.3.3 Interrupt Enable (ATAPI_INT_ENABLE)........................................................... 596 17.3.4 PIO Timing Register (ATAPI_PIO_TIMING)..................................................... 597 17.3.5 Multiword DMA Timing Register (ATAPI_MULTI_TIMING).......................... 598 17.3.6 Ultra DMA Timing Register (ATAPI_ULTRA_TIMING) .................................. 600 17.3.7 Descriptor Table Base Address Register (ATAPI_DTB_ADR)........................... 601 Rev. 1.00 Nov. 22, 2007 Page xviii of lvi 17.3.8 Descriptor Table ................................................................................................... 602 17.3.9 Termination Flag and Descriptor DMA Start Address ......................................... 603 17.3.10 Descriptor DMA Transfer Count .......................................................................... 604 17.3.11 DMA Start Address Register (ATAPI_DMA_START_ADR)............................. 605 17.3.12 DMA Transfer Count Register (ATAPI_DMA_TRANS_CNT) .......................... 606 17.3.13 ATAPI Control 2 (ATAPI_CONTROL2) ............................................................ 607 17.3.14 ATAPI Signal Status Register (ATAPI_SIG_ST) ................................................ 608 17.3.15 Byteswap (ATAPI_BYTE_SWAP)...................................................................... 609 17.3.16 ATAPI Data Bus Alignment................................................................................. 610 17.4 Functional Description....................................................................................................... 611 17.4.1 Data Transfer Modes ............................................................................................ 611 17.4.2 Descriptor Function .............................................................................................. 611 17.5 Operating Procedure .......................................................................................................... 612 17.5.1 Initialization .......................................................................................................... 612 17.5.2 Procedure in PIO Transfer Mode .......................................................................... 612 17.5.3 Procedure in Multiword DMA Transfer Mode ..................................................... 613 17.5.4 Procedure in Ultra DMA Transfer Mode .............................................................. 616 17.5.5 Procedure in Hardware Reset for ATAPI Device ................................................. 617 Section 18 Serial Sound Interface (SSI) ............................................................619 18.1 Features.............................................................................................................................. 619 18.1.1 SSI Module Configuration.................................................................................... 619 18.1.2 SSI Features .......................................................................................................... 619 18.2 Input/Output Pins ............................................................................................................... 621 18.3 Register Descriptions ......................................................................................................... 621 18.3.1 DMA Mode Registers 0 to 5 (SSIDMMR0 to SSIDMMR5)................................ 633 18.3.2 RDMA Transfer Source Address Registers 0 to 5 (SSIRDMADR0 to SSIRDMADR5) .................................................................... 634 18.3.3 RDMA Transfer Word Count Registers 0 to 5 (SSIRDMCNTR0 to SSIRDMCNTR5)................................................................ 635 18.3.4 WDMA Transfer Destination Address Registers 0 to 5 (SSIWDMADR0 to SSIWDMADR5) .................................................................. 637 18.3.5 WDMA Transfer Word Count Registers 0 to 5 (SSIWDMCNTR0 to SSIWDMCNTR5).............................................................. 637 18.3.6 DMA Control Registers 0 to 5 (SSIDMCOR0 to SSIDMCOR5)......................... 638 18.3.7 Transmit Suspension Block Counters 0 to 5 (SSISTPBLCNT0 to SSISTPBLCNT5) ............................................................... 649 18.3.8 Transmit Suspension Transfer Data Registers 0 to 5 (SSISTPDR0 to SSISTPDR5) .............................................................................. 650 18.3.9 Block Count Source Registers 0 to 5 (SSIBLCNTSR0 to SSIBLCNTSR5) ........ 651 Rev. 1.00 Nov. 22, 2007 Page xix of lvi 18.3.10 Block Counters 0 to 5 (SSIBLCNT0 to SSIBLCNT5) ......................................... 652 18.3.11 n-Times Block Transfer Interrupt Count Source Registers 0 to 5 (SSIBLNCNTSR0 to SSIBLNCNTSR5).............................................................. 652 18.3.12 n-Times Block Counters 0 to 5 (SSIBLNCNT0 to SSIBLNCNT5) ..................... 653 18.3.13 DMA Operation Registers 0 and 1 (SSIDMAOR0 and SSIDMAOR1) ............... 654 18.3.14 Interrupt Status Registers 0 and 1 (SSIDMINTSR0 and SSIDMINTSR1)........... 656 18.3.15 Interrupt Mask Registers 0 and 1 (SSIDMINTMR0 and SSIDMINTMR1)......... 661 18.3.16 Control Registers 0 to 5 (SSICR0 to SSICR5) ..................................................... 664 18.3.17 Status Registers 0 to 5 (SSISR0 to SSISR5)......................................................... 671 18.3.18 Transmit Data Registers 0 to 5 (SSITDR0 to SSITDR5) ..................................... 677 18.3.19 Receive Data Registers 0 to 5 (SSIRDR0 to SSIRDR5)....................................... 677 18.4 Operation ........................................................................................................................... 678 18.4.1 Operation of SSI_CLKSEL .................................................................................. 678 18.4.2 Operation of SSI_DMAC0 and SSI_DMAC1 ...................................................... 678 18.4.3 Operation of SSI_CH0 to SSI_CH5 ..................................................................... 680 18.5 Usage Note......................................................................................................................... 698 18.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation ............ 698 18.5.2 Restrictions during Operation in Slave Mode....................................................... 698 18.5.3 Restrictions when Specify Each Register ............................................................. 698 Section 19 Ethernet Controller (EtherC) ........................................................... 701 19.1 Features.............................................................................................................................. 701 19.2 Input/Output Pins............................................................................................................... 702 19.3 Register Descriptions......................................................................................................... 703 19.3.1 EtherC Mode Register (ECMR)............................................................................ 705 19.3.2 EtherC Status Register (ECSR) ............................................................................ 709 19.3.3 EtherC Interrupt Permission Register (ECSIPR) .................................................. 711 19.3.4 PHY Interface Register (PIR) ............................................................................... 712 19.3.5 MAC Address High Register (MAHR) ................................................................ 713 19.3.6 MAC Address Low Register (MALR) ................................................................. 714 19.3.7 Receive Frame Length Register (RFLR) .............................................................. 715 19.3.8 PHY Status Register (PSR)................................................................................... 716 19.3.9 Transmit Retry Over Counter Register (TROCR) ................................................ 717 19.3.10 Delayed Collision Detect Counter Register (CDCR)............................................ 718 19.3.11 Lost Carrier Counter Register (LCCR)................................................................. 719 19.3.12 Carrier Not Detect Counter Register (CNDCR) ................................................... 720 19.3.13 CRC Error Frame Receive Counter Register (CEFCR)........................................ 721 19.3.14 Frame Receive Error Counter Register (FRECR)................................................. 722 19.3.15 Too-Short Frame Receive Counter Register (TSFRCR) ...................................... 723 19.3.16 Too-Long Frame Receive Counter Register (TLFRCR) ...................................... 724 Rev. 1.00 Nov. 22, 2007 Page xx of lvi 19.3.17 Residual-Bit Frame Receive Counter Register (RFCR) ....................................... 725 19.3.18 Multicast Address Frame Receive Counter Register (MAFCR)........................... 726 19.3.19 IPG Register (IPGR)............................................................................................. 727 19.3.20 Automatic PAUSE Frame Register (APR) ........................................................... 728 19.3.21 Manual PAUSE Frame Register (MPR) ............................................................... 729 19.3.22 Automatic PAUSE Frame Retransmit Count Register (TPAUSER) .................... 730 19.3.23 Random Number Generation Counter Upper Limit Setting Register (RDMLR) ............................................................................................................. 731 19.3.24 PAUSE Frame Receive Counter Register (RFCF) ............................................... 732 19.3.25 PAUSE Frame Retransmit Counter Register (TPAUSECR) ................................ 733 19.3.26 Broadcast Frame Receive Count Setting Register (BCFRR)................................ 734 19.4 Operation ........................................................................................................................... 735 19.4.1 Transmission......................................................................................................... 735 19.4.2 Reception .............................................................................................................. 737 19.4.3 MII Frame Timing ................................................................................................ 739 19.4.4 Accessing MII Registers ....................................................................................... 741 19.4.5 Magic Packet Detection ........................................................................................ 744 19.4.6 Operation by IPG Setting...................................................................................... 745 19.4.7 Flow Control......................................................................................................... 745 19.5 Connection to LSI .............................................................................................................. 747 19.6 Usage Notes ....................................................................................................................... 748 Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC) .......................................................................................749 20.1 Features.............................................................................................................................. 749 20.2 Register Descriptions ......................................................................................................... 751 20.2.1 E-DMAC Mode Register (EDMR) ....................................................................... 753 20.2.2 E-DMAC Transmit Request Register (EDTRR)................................................... 754 20.2.3 E-DMAC Receive Request Register (EDRRR) .................................................... 755 20.2.4 Transmit Descriptor List Start Address Register (TDLAR) ................................. 756 20.2.5 Receive Descriptor List Start Address Register (RDLAR)................................... 757 20.2.6 E-MAC/E-DMAC Status Register (EESR) .......................................................... 758 20.2.7 E-MAC/E-DMAC Status Interrupt Permission Register (EESIPR) ..................... 763 20.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................. 766 20.2.9 Receive Missed-Frame Counter Register (RMFCR) ............................................ 769 20.2.10 Transmit FIFO Threshold Register (TFTR).......................................................... 770 20.2.11 FIFO Depth Register (FDR) ................................................................................. 772 20.2.12 Receiving Method Control Register (RMCR) ...................................................... 773 20.2.13 Transmit FIFO Underrun Counter (TFUCR)........................................................ 775 20.2.14 Receive FIFO Overflow Counter (RFOCR) ......................................................... 776 Rev. 1.00 Nov. 22, 2007 Page xxi of lvi 20.2.15 Receive Buffer Write Address Register (RBWAR).............................................. 777 20.2.16 Receive Descriptor Fetch Address Register (RDFAR)......................................... 778 20.2.17 Transmit Buffer Read Address Register (TBRAR) .............................................. 779 20.2.18 Transmit Descriptor Fetch Address Register (TDFAR) ....................................... 780 20.2.19 Flow Control Start FIFO Threshold Setting Register (FCFTR) ........................... 781 20.2.20 Receive Data Padding Insert Register (RPADIR) ................................................ 783 20.2.21 Transmit Interrupt Setting Register (TRIMD) ...................................................... 784 20.2.22 Independent Output Signal Setting Register (IOSR) ............................................ 785 20.3 Operation ........................................................................................................................... 786 20.3.1 Descriptor Lists and Data Buffers......................................................................... 786 20.3.2 Transmission......................................................................................................... 795 20.3.3 Reception .............................................................................................................. 797 20.3.4 Transmit/Receive Processing of Multi-Buffer Frame (Single-Frame/ Multi-Descriptor)......................................................................... 799 Section 21 USB 2.0 Host/Function Module (USB)........................................... 801 21.1 Features.............................................................................................................................. 801 21.2 Input / Output Pins............................................................................................................. 804 21.3 Register Description .......................................................................................................... 805 21.3.1 System Configuration Control Register (SYSCFG) ............................................. 811 21.3.2 CPU Bus Wait Setting Register (BUSWAIT) ...................................................... 815 21.3.3 System Configuration Status Register (SYSSTS)................................................. 816 21.3.4 Device State Control Register (DVSTCTR)......................................................... 818 21.3.5 Test Mode Register (TESTMODE) ...................................................................... 823 21.3.6 DMA-FIFO Bus Configuration Registers (D0FBCFG, D1FBCFG) .................... 826 21.3.7 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO) ................................................ 827 21.3.8 FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)................. 830 21.3.9 FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR) ............ 837 21.3.10 Interrupts Enable Register 0 (INTENB0) ............................................................. 841 21.3.11 Interrupt Enable Register 1 (INTENB1)............................................................... 843 21.3.12 BRDY Interrupt Enable Register (BRDYENB) ................................................... 845 21.3.13 NRDY Interrupt Enable Register (NRDYENB) ................................................... 847 21.3.14 BEMP Interrupt Enable Register (BEMPENB).................................................... 849 21.3.15 SOF Control Register (SOFCFG)......................................................................... 851 21.3.16 Interrupt Status Register 0 (INTSTS0) ................................................................. 852 21.3.17 Interrupt Status Register 1 (INTSTS1) ................................................................. 858 21.3.18 BRDY Interrupt Status Register (BRDYSTS)...................................................... 864 21.3.19 NRDY Interrupt Status Register (NRDYSTS) ..................................................... 866 21.3.20 BEMP Interrupt Status Register (BEMPSTS) ...................................................... 868 21.3.21 Frame Number Register (FRMNUM) .................................................................. 869 Rev. 1.00 Nov. 22, 2007 Page xxii of lvi 21.3.22 µFrame Number Register (UFRMNUM) ............................................................. 872 21.3.23 USB Address Register (USBADDR).................................................................... 873 21.3.24 USB Request Type Register (USBREQ) .............................................................. 874 21.3.25 USB Request Value Register (USBVAL)............................................................. 876 21.3.26 USB Request Index Register (USBINDX) ........................................................... 877 21.3.27 USB Request Length Register (USBLENG) ........................................................ 878 21.3.28 DCP Configuration Register (DCPCFG) .............................................................. 879 21.3.29 DCP Maximum Packet Size Register (DCPMAXP)............................................. 880 21.3.30 DCP Control Register (DCPCTR) ........................................................................ 881 21.3.31 Pipe Window Select Register (PIPESEL)............................................................. 891 21.3.32 Pipe Configuration Register (PIPECFG) .............................................................. 892 21.3.33 Pipe Buffer Setting Register (PIPEBUF).............................................................. 899 21.3.34 Pipe Maximum Packet Size Register (PIPEMAXP)............................................. 902 21.3.35 Pipe Timing Control Register (PIPEPERI)........................................................... 904 21.3.36 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9)............................................... 906 21.3.37 PIPEn Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5)............... 926 21.3.38 PIPEn Transaction Counter Registers (PIPEnTRN) (n = 1 to 5) .......................... 928 21.3.39 Device Address n Configuration Registers (DEVADDn) (n = 0 to A)................. 930 21.4 Operation ........................................................................................................................... 933 21.4.1 System Control and Oscillation Control ............................................................... 933 21.4.2 Interrupt Functions................................................................................................ 935 21.4.3 Pipe Control .......................................................................................................... 959 21.4.4 FIFO Buffer Memory............................................................................................ 969 21.4.5 Control Transfers (DCP)....................................................................................... 979 21.4.6 Bulk Transfers (PIPE1 to PIPE5).......................................................................... 983 21.4.7 Interrupt Transfers (PIPE6 to PIPE9) ................................................................... 985 21.4.8 Isochronous Transfers (PIPE1 and PIPE2) ........................................................... 986 21.4.9 SOF Interpolation Function .................................................................................. 997 21.4.10 Pipe Schedule........................................................................................................ 998 21.5 Usage Notes ..................................................................................................................... 1000 21.5.1 USB Startup and Stop Procedures ...................................................................... 1000 Section 22 LCD Controller (LCDC)................................................................1001 22.1 Features............................................................................................................................ 1001 22.2 Input/Output Pins ............................................................................................................. 1003 22.3 Register Configuration..................................................................................................... 1004 22.3.1 LCDC Input Clock Register (LDICKR) ............................................................. 1007 22.3.2 LCDC Module Type Register (LDMTR) ........................................................... 1009 22.3.3 LCDC Data Format Register (LDDFR).............................................................. 1012 22.3.4 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) ......... 1014 Rev. 1.00 Nov. 22, 2007 Page xxiii of lvi 22.3.5 LCDC Start Address Register for Lower Display Data Fetch (LDSARL) ......... 1015 22.3.6 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) ......... 1016 22.3.7 LCDC Palette Control Register (LDPALCR)..................................................... 1017 22.3.8 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ..................................... 1018 22.3.9 LCDC Horizontal Character Number Register (LDHCNR) ............................... 1019 22.3.10 LCDC Horizontal Sync Signal Register (LDHSYNR)....................................... 1020 22.3.11 LCDC Vertical Display Line Number Register (LDVDLNR) ........................... 1021 22.3.12 LCDC Vertical Total Line Number Register (LDVTLNR)................................ 1022 22.3.13 LCDC Vertical Sync Signal Register (LDVSYNR) ........................................... 1023 22.3.14 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ..... 1024 22.3.15 LCDC Interrupt Control Register (LDINTR) ..................................................... 1025 22.3.16 LCDC Power Management Mode Register (LDPMMR) ................................... 1028 22.3.17 LCDC Power-Supply Sequence Period Register (LDPSPR).............................. 1030 22.3.18 LCDC Control Register (LDCNTR)................................................................... 1032 22.3.19 LCDC User Specified Interrupt Control Register (LDUINTR).......................... 1033 22.3.20 LCDC User Specified Interrupt Line Number Register (LDUINTLNR) ........... 1035 22.3.21 LCDC Memory Access Interval Number Register (LDLIRNR) ........................ 1036 22.4 Operation ......................................................................................................................... 1037 22.4.1 LCD Module Sizes which can be Displayed in this LCDC ................................ 1037 22.4.2 Color Palette Specification ................................................................................. 1039 22.4.3 Data Format ........................................................................................................ 1040 22.4.4 Setting the Display Resolution ........................................................................... 1044 22.4.5 Power-Supply Control Sequence ........................................................................ 1044 22.5 Clock and LCD Data Signal Examples............................................................................ 1050 22.6 Usage Notes ..................................................................................................................... 1063 22.6.1 Procedure for Halting Access to Display Data Storage VRAM (SDRAM in Area 1 or 2) .................................................................................... 1063 22.6.2 Notes on Holding the Access Request by MCU ................................................. 1063 Section 23 G2D ............................................................................................... 1065 23.1 Basic Functions................................................................................................................ 1065 23.1.1 List of Commands and Rendering Attributes ..................................................... 1065 23.1.2 Basic Functions................................................................................................... 1068 23.1.3 Coordinate Systems ............................................................................................ 1078 23.1.4 Data Formats....................................................................................................... 1083 23.1.5 Rendering Attributes........................................................................................... 1084 23.2 Display List...................................................................................................................... 1097 23.2.1 4-Vertex Screen Drawing Commands ................................................................ 1097 23.2.2 Line Drawing Commands................................................................................... 1108 23.2.3 Work Screen Drawing Commands ..................................................................... 1139 Rev. 1.00 Nov. 22, 2007 Page xxiv of lvi 23.2.4 Work Line Drawing Commands ......................................................................... 1151 23.2.5 Rectangle Drawing Commands .......................................................................... 1155 23.2.6 Control Commands ............................................................................................. 1166 23.3 Register Specifications..................................................................................................... 1184 23.3.1 System Control Registers.................................................................................... 1190 23.3.2 Memory Control Registers.................................................................................. 1196 23.3.3 Color Control Registers ...................................................................................... 1201 23.3.4 Rendering Control Registers............................................................................... 1204 23.3.5 Coordinate Transformation Control Registers .................................................... 1212 Section 24 Video Display Controller (VDC2).................................................1221 24.1 24.2 24.3 24.4 24.5 Overview.......................................................................................................................... 1221 Features............................................................................................................................ 1221 Input/Output Pins ............................................................................................................. 1223 VDC2 Configuration........................................................................................................ 1224 Functional Descriptions ................................................................................................... 1226 24.5.1 Graphics (Layers 1 to 4) ..................................................................................... 1226 24.5.2 Sync Signal Generation....................................................................................... 1227 24.5.3 External Sync Mode............................................................................................ 1230 24.5.4 Digital Video Output .......................................................................................... 1230 24.5.5 Conversion from RGB565 to YC444.................................................................. 1231 24.5.6 Conversion from YC444 to YC422 .................................................................... 1231 24.5.7 Data Enable Signal (Composite)......................................................................... 1232 24.6 Register Descriptions ....................................................................................................... 1233 24.6.1 Graphics Block Control Registers (GRCMEN1 to GRCMEN4)........................ 1239 24.6.2 Bus Control Registers (GRCBUSCNT1 to GRCBUSCNT4)............................. 1241 24.6.3 Graphic Image Base Address Registers (GROPSADR1 to GROPSADR4) ....... 1242 24.6.4 Graphic Image Area Registers (GROPSWH1 to GROPSWH4)......................... 1243 24.6.5 Graphic Image Line Offset Registers (GROPSOFST1 to GROPSOFST4) ........ 1245 24.6.6 Graphic Image Start Position Registers (GROPDPHV1 to GROPDPHV4)....... 1246 24.6.7 α Control Area Registers (GROPEWH2 to GROPEWH4) ................................ 1246 24.6.8 α Control Area Start Position Registers (GROPEDPHV2 to GROPEDPHV4)................................................................. 1247 24.6.9 α Control Registers (GROPEDPA2 to GROPEDPA4) ...................................... 1249 24.6.10 Chroma-Key Control Registers (GROPCRKY0_2 to GROPCRKY0_4)........... 1251 24.6.11 Chroma-Key Color Registers (GROPCRKY1_2 to GROPCRKY1_4).............. 1252 24.6.12 Color Registers for Outside of Graphic Image Area (GROPBASERGB1 to GROPBASERGB4)....................................................... 1253 24.6.13 SG Mode Register (SGMODE) .......................................................................... 1255 24.6.14 Interrupt Output Control Register (SGINTCNT)................................................ 1257 Rev. 1.00 Nov. 22, 2007 Page xxv of lvi 24.6.15 Sync Signal Control Register (SYNCNT) .......................................................... 1258 24.6.16 External Sync Signal Input Timing Control Register (EXTSYNCNT) .............. 1261 24.6.17 Sync Signal Size Register (SYNSIZE) ............................................................... 1262 24.6.18 Vertical Sync Signal Timing Control Register (VSYNCTIM)........................... 1263 24.6.19 Horizontal Sync Signal Timing Control Register (HSYNCTIM)....................... 1264 24.6.20 Gate Clock Signal Timing Control Register (CLSTIM)..................................... 1265 24.6.21 Sampling Start Signal Timing Control Register (SPLTIM)................................ 1266 24.6.22 Gate Control Signal Timing Control Register (COMTIM) ................................ 1267 24.6.23 SGDE Area Start Position Register (SGDESTART).......................................... 1268 24.6.24 SGDE Area Size Register (SGDESIZE)............................................................. 1270 24.6.25 CDE Chroma-Key Color Register (CDECRKY)................................................ 1271 24.6.26 T1004 Control Register (T1004CNT) ................................................................ 1272 24.6.27 T1004 Video Start Position Register (T1004OFFSET) ...................................... 1273 24.7 Operating Procedures....................................................................................................... 1275 24.7.1 Display Control Block ........................................................................................ 1275 24.7.2 Graphics Blocks.................................................................................................. 1275 Section 25 NAND Flash Memory Controller (FLCTL).................................. 1277 25.1 Features............................................................................................................................ 1277 25.2 Input/Output Pins............................................................................................................. 1281 25.3 Register Descriptions....................................................................................................... 1282 25.3.1 Common Control Register (FLCMNCR) ........................................................... 1284 25.3.2 Command Control Register (FLCMDCR).......................................................... 1287 25.3.3 Command Code Register (FLCMCDR) ............................................................. 1290 25.3.4 Address Register (FLADR) ................................................................................ 1291 25.3.5 Address Register 2 (FLADR2) ........................................................................... 1293 25.3.6 Data Counter Register (FLDTCNTR) ................................................................ 1294 25.3.7 Data Register (FLDATAR) ................................................................................ 1295 25.3.8 Interrupt DMA Control Register (FLINTDMACR) ........................................... 1296 25.3.9 Ready Busy Timeout Setting Register (FLBSYTMR) ....................................... 1301 25.3.10 Ready Busy Timeout Counter (FLBSYCNT)..................................................... 1302 25.3.11 Data FIFO Register (FLDTFIFO)....................................................................... 1303 25.3.12 Control Code FIFO Register (FLECFIFO)......................................................... 1304 25.3.13 Transfer Control Register (FLTRCR)................................................................. 1305 25.4 Operation ......................................................................................................................... 1306 25.4.1 Operating Modes ................................................................................................ 1306 25.4.2 Register Setting Procedure.................................................................................. 1306 25.4.3 Command Access Mode ..................................................................................... 1308 25.4.4 Sector Access Mode ........................................................................................... 1311 25.4.5 ECC Error Correction ......................................................................................... 1315 Rev. 1.00 Nov. 22, 2007 Page xxvi of lvi 25.4.6 Status Read ......................................................................................................... 1315 25.5 Interrupt Sources.............................................................................................................. 1316 25.6 DMA Transfer Specifications .......................................................................................... 1316 Section 26 Sampling Rate Converter (SRC)....................................................1317 26.1 Features............................................................................................................................ 1317 26.2 Register Descriptions ....................................................................................................... 1319 26.2.1 SRC Input Data Register (SRCID) ..................................................................... 1320 26.2.2 SRC Output Data Register (SRCOD) ................................................................. 1321 26.2.3 SRC Input Data Control Register (SRCIDCTRL) .............................................. 1322 26.2.4 SRC Output Data Control Register (SRCODCTRL).......................................... 1323 26.2.5 SRC Control Register (SRCCTRL) .................................................................... 1325 26.2.6 SRC Status Register (SRCSTAT)....................................................................... 1328 26.3 Operation ......................................................................................................................... 1331 26.3.1 Initial Setting ...................................................................................................... 1331 26.3.2 Data Input ........................................................................................................... 1332 26.3.3 Data Output......................................................................................................... 1333 26.4 Interrupts.......................................................................................................................... 1335 26.5 Usage Note....................................................................................................................... 1336 26.5.1 Note on Access Register ..................................................................................... 1336 26.5.2 Note on Flash Processing.................................................................................... 1336 Section 27 General Purpose I/O (GPIO)..........................................................1337 27.1 Features............................................................................................................................ 1337 27.2 Register Descriptions ....................................................................................................... 1346 27.2.1 Port A Control Register (PTIO_A) ..................................................................... 1349 27.2.2 Port B Control Register (PTIO_B)...................................................................... 1351 27.2.3 Port C Control Register (PTIO_C)...................................................................... 1353 27.2.4 Port D Control Register (PTIO_D) ..................................................................... 1355 27.2.5 Port E Control Register (PTIO_E) ...................................................................... 1357 27.2.6 Port F Control Register (PTIO_F) ...................................................................... 1359 27.2.7 Port G Control Register (PTIO_G) ..................................................................... 1361 27.2.8 Port H Control Register (PTIO_H) ..................................................................... 1363 27.2.9 Port I Control Register (PTIO_I) ........................................................................ 1365 27.2.10 Port J Control Register (PTIO_J)........................................................................ 1366 27.2.11 Port A Data Register (PTDAT_A)...................................................................... 1368 27.2.12 Port B Data Register (PTDAT_B) ...................................................................... 1369 27.2.13 Port C Data Register (PTDAT_C) ...................................................................... 1370 27.2.14 Port D Data Register (PTDAT_D)...................................................................... 1371 27.2.15 Port E Data Register (PTDAT_E)....................................................................... 1372 Rev. 1.00 Nov. 22, 2007 Page xxvii of lvi 27.2.16 Port F Data Register (PTDAT_F) ....................................................................... 1373 27.2.17 Port G Data Register (PTDAT_G)...................................................................... 1374 27.2.18 Port H Data Register (PTDAT_H)...................................................................... 1375 27.2.19 Port I Data Register (PTDAT_I)......................................................................... 1376 27.2.20 Port J Data Register (PTDAT_J) ........................................................................ 1377 27.2.21 Input-Pin Pull-Up Control Register (PTPUL_SPCL) ......................................... 1378 27.2.22 Pin Select Register 0 (PTSEL_A)....................................................................... 1379 27.2.23 Pin Select Register 1 (PTSEL_B) ....................................................................... 1381 27.2.24 Pin Select Register 2 (PTSEL_C) ....................................................................... 1383 27.2.25 Pin Select Register 3 (PTSEL_D)....................................................................... 1385 27.2.26 Pin Select Register 4 (PTSEL_E) ....................................................................... 1387 27.2.27 Pin Select Register 5 (PTSEL_F) ....................................................................... 1389 27.2.28 Pin Select Register 6 (PTSEL_G)....................................................................... 1391 27.2.29 Pin Select Register 7 (PTSEL_H)....................................................................... 1393 27.2.30 Pin Select Register 8 (PTSEL_I) ........................................................................ 1395 27.2.31 Pin Select Register 9 (PTSEL_J) ........................................................................ 1397 27.2.32 Pin Select Register 10 (PTSEL_K)..................................................................... 1399 27.2.33 Pin Select Register 11 (PTSEL_P) ..................................................................... 1401 27.2.34 Pin Select Register 12 (PTSEL_R) ..................................................................... 1402 27.2.35 Pin Select Register 13 (PTSEL_S) ..................................................................... 1404 27.2.36 HI-Z Register A (PTHIZ_A) .............................................................................. 1406 27.2.37 HI-Z Register B (PTHIZ_B)............................................................................... 1407 27.2.38 Special Select Register (PTSEL_SPCL)............................................................. 1409 27.3 Usage Examples............................................................................................................... 1410 27.3.1 Port Function Select............................................................................................ 1410 27.3.2 Port Output Function .......................................................................................... 1410 27.3.3 Port Input Function ............................................................................................. 1410 27.3.4 On-Chip Module Function.................................................................................. 1410 Section 28 Power-Down Mode ....................................................................... 1411 28.1 Features............................................................................................................................ 1411 28.1.1 Types of Power-Down Modes ............................................................................ 1411 28.2 Input/Output Pins............................................................................................................. 1413 28.3 Register Descriptions....................................................................................................... 1413 28.3.1 Standby Control Register (STBCR).................................................................... 1414 28.3.2 Module Stop Register 0 (MSTPCR0) ................................................................. 1415 28.3.3 Module Stop Register 1 (MSTPCR1) ................................................................. 1419 28.4 Sleep Mode ...................................................................................................................... 1420 28.4.1 Transition to Sleep Mode.................................................................................... 1420 28.4.2 Canceling Sleep Mode ........................................................................................ 1420 Rev. 1.00 Nov. 22, 2007 Page xxviii of lvi 28.5 Refresh Standby Mode..................................................................................................... 1421 28.5.1 Transition to Refresh Standby Mode .................................................................. 1421 28.5.2 Canceling Refresh Standby Mode....................................................................... 1421 28.6 Module Standby Mode..................................................................................................... 1422 28.6.1 Transition to Module Standby Mode .................................................................. 1422 28.6.2 Canceling Module Standby Mode....................................................................... 1422 28.7 STATUS Pin Signal Change Timing ............................................................................... 1423 28.7.1 Timing at Reset................................................................................................... 1423 28.7.2 Timing at Sleep Mode Cancellation.................................................................... 1423 Section 29 Watchdog Timer and Reset............................................................1425 29.1 Features............................................................................................................................ 1425 29.2 Input/Output Pins ............................................................................................................. 1427 29.3 Register Descriptions ....................................................................................................... 1428 29.3.1 Watchdog Timer Stop Time Register (WDTST) ................................................ 1429 29.3.2 Watchdog Timer Control/Status Register (WDTCSR)....................................... 1430 29.3.3 Watchdog timer Base Stop Time Register (WDTBST) ...................................... 1431 29.3.4 Watchdog Timer Counter (WDTCNT)............................................................... 1432 29.3.5 Watchdog Timer Base Counter (WDTBCNT) ................................................... 1432 29.4 Operation ......................................................................................................................... 1433 29.4.1 Reset request....................................................................................................... 1433 29.4.2 Using watchdog timer mode ............................................................................... 1434 29.4.3 Using Interval timer mode .................................................................................. 1434 29.4.4 Time for WDT Overflow .................................................................................... 1434 29.4.5 Clearing WDT Counter....................................................................................... 1435 29.5 Status Pin Change Timing during Reset .......................................................................... 1436 29.5.1 Power-On Reset by PRESET.............................................................................. 1436 29.5.2 Power-On Reset by Watchdog Timer Overflow................................................. 1439 Section 30 User Break Controller (UBC) ........................................................1441 30.1 Features............................................................................................................................ 1441 30.2 Register Descriptions ....................................................................................................... 1443 30.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1) ......................... 1445 30.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1) ......................... 1451 30.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1)............................ 1453 30.2.4 Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)........... 1454 30.2.5 Match Data Setting Register 1 (CDR1) .............................................................. 1456 30.2.6 Match Data Mask Setting Register 1 (CDMR1) ................................................. 1457 30.2.7 Execution Count Break Register 1 (CETR1) ...................................................... 1458 30.2.8 Channel Match Flag Register (CCMFR) ............................................................ 1459 Rev. 1.00 Nov. 22, 2007 Page xxix of lvi 30.3 30.4 30.5 30.6 30.2.9 Break Control Register (CBCR) ......................................................................... 1460 Operation Description...................................................................................................... 1461 30.3.1 Definition of Words Related to Accesses ........................................................... 1461 30.3.2 User Break Operation Sequence ......................................................................... 1461 30.3.3 Instruction Fetch Cycle Break ............................................................................ 1462 30.3.4 Operand Access Cycle Break ............................................................................. 1464 30.3.5 Sequential Break................................................................................................. 1465 30.3.6 Program Counter Value to be Saved................................................................... 1467 User Break Debugging Support Function ........................................................................ 1468 User Break Examples....................................................................................................... 1470 Usage Notes ..................................................................................................................... 1474 Section 31 User Debugging Interface (H-UDI)............................................... 1477 31.1 Features............................................................................................................................ 1477 31.2 Input/Output Pins............................................................................................................. 1479 31.3 Boundary Scan TAP Controllers (IDCODE, EXTEST, SAMPLE/PRELOAD, BYPASS, CLAMP and HIGHZ) ..................................................................................... 1480 31.4 Register Descriptions....................................................................................................... 1482 31.4.1 Instruction Register (SDIR) ................................................................................ 1483 31.4.2 Interrupt Source Register (SDINT)..................................................................... 1484 31.4.3 Bypass Register (SDBPR) .................................................................................. 1485 31.4.4 Boundary Scan Register (SDBSR) ..................................................................... 1485 31.5 Operation ......................................................................................................................... 1506 31.5.1 TAP Control ....................................................................................................... 1506 31.5.2 H-UDI Reset ....................................................................................................... 1507 31.5.3 H-UDI Interrupt .................................................................................................. 1507 31.6 Usage Notes ..................................................................................................................... 1507 Section 32 List of Registers............................................................................. 1509 32.1 Register Addresses........................................................................................................... 1509 32.2 Register States in Each Operation Mode ......................................................................... 1547 Section 33 Electrical Characteristics ............................................................... 1573 33.1 33.2 33.3 33.4 Absolute Maximum Ratings ............................................................................................ 1573 Power-on/Power-off Sequence ........................................................................................ 1574 DC Characteristics ........................................................................................................... 1575 AC Characteristics ........................................................................................................... 1581 33.4.1 Clock and Control Signal Timing ....................................................................... 1581 33.4.2 Control Signal Timing ........................................................................................ 1584 33.4.3 Bus Timing ......................................................................................................... 1586 Rev. 1.00 Nov. 22, 2007 Page xxx of lvi 33.4.4 INTC Module Signal Timing.............................................................................. 1603 33.4.5 DMAC Module Signal Timing ........................................................................... 1605 33.4.6 TMU Module Signal Timing .............................................................................. 1605 33.4.7 IIC Module Signal Timing.................................................................................. 1606 33.4.8 SCIF Module SignalTiming................................................................................ 1608 33.4.9 SSI Module Signal Timing ................................................................................. 1609 33.4.10 ATAPI Interface Module Signal timing.............................................................. 1612 33.4.11 USB Module Signal Timing ............................................................................... 1640 33.4.12 GPIO Signal Timing ........................................................................................... 1641 33.4.13 H-UDI Module Signal Timing............................................................................ 1642 33.4.14 EtherC Module Signal Timing............................................................................ 1644 33.4.15 FLCTL Module Signal Timing ........................................................................... 1648 33.4.16 LCDC Module Signal Timing ............................................................................ 1652 33.4.17 VDC2 Module Signal Timing............................................................................. 1654 33.5 AC Characteristics Measurement Conditions .................................................................. 1657 Appendix A. B. C. D. E. F. G. H. .......................................................................................................1659 CPU Operation Mode Register (CPUOPM) .................................................................... 1659 Instruction Prefetching and Its Side Effects..................................................................... 1661 Speculative Execution for Subroutine Return.................................................................. 1662 Version Registers (PVR, PRR) ........................................................................................ 1663 Pin State ........................................................................................................................... 1665 Pin Treatment When Not in Use ...................................................................................... 1675 Type Name....................................................................................................................... 1683 Package Dimensions ........................................................................................................ 1684 Index .......................................................................................................1685 Rev. 1.00 Nov. 22, 2007 Page xxxi of lvi Rev. 1.00 Nov. 22, 2007 Page xxxii of lvi Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.3 Section 2 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 2.7 Figure 2.8 Section 4 Figure 4.1 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Figure 4.2 Overview Block Diagram ............................................................................................................... 13 Pin Arrangement ............................................................................................................ 14 Physical Address Space (1) ............................................................................................ 28 Physical Address Space (2) ............................................................................................ 29 Programming Model Data Formats .................................................................................................................. 31 CPU Register Configuration in Each Processing Mode................................................. 35 General Registers ........................................................................................................... 36 Floating-Point Registers................................................................................................. 38 Relationship between SZ bit and Endian........................................................................ 44 Formats of Byte Data and Word Data in Register.......................................................... 46 Data Formats in Memory ............................................................................................... 47 Processing State Transitions........................................................................................... 48 Pipelining Basic Pipelines ............................................................................................................... 71 Instruction Execution Patterns (1).................................................................................. 73 Instruction Execution Patterns (2).................................................................................. 74 Instruction Execution Patterns (3).................................................................................. 75 Instruction Execution Patterns (4).................................................................................. 76 Instruction Execution Patterns (5).................................................................................. 77 Instruction Execution Patterns (6).................................................................................. 78 Instruction Execution Patterns (7).................................................................................. 79 Instruction Execution Patterns (8).................................................................................. 80 Instruction Execution Patterns (9).................................................................................. 81 Section 5 Exception Handling Figure 5.1 Instruction Execution and Exception Handling............................................................ 105 Figure 5.2 Example of General Exception Acceptance Order....................................................... 106 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Floating-Point Unit (FPU) Format of Single-Precision Floating-Point Number..................................................... 132 Format of Double-Precision Floating-Point Number ................................................... 132 Single-Precision NaN Bit Pattern................................................................................. 135 Floating-Point Registers............................................................................................... 138 Relation between SZ Bit and Endian ........................................................................... 141 Rev. 1.00 Nov. 22, 2007 Page xxxiii of lvi Section 7 Memory Management Unit (MMU) Figure 7.1 Role of MMU...............................................................................................................151 Figure 7.2 Virtual Address Space (AT in MMUCR= 0) ...............................................................152 Figure 7.3 Virtual Address Space (AT in MMUCR= 1) ...............................................................153 Figure 7.4 P4 Area.........................................................................................................................154 Figure 7.5 Physical Address Space................................................................................................156 Figure 7.6 UTLB Configuration (TLB Compatible Mode) ...........................................................170 Figure 7.7 Relationship between Page Size and Address Format (TLB Compatible Mode).........172 Figure 7.8 ITLB Configuration (TLB Compatible Mode).............................................................173 Figure 7.9 Flowchart of Memory Access Using UTLB (TLB Compatible Mode)........................174 Figure 7.10 Flowchart of Memory Access Using ITLB (TLB Compatible Mode) .......................175 Figure 7.11 UTLB Configuration (TLB Extended Mode).............................................................176 Figure 7.12 Relationship between Page Size and Address Format (TLB Extended Mode) ..........179 Figure 7.13 ITLB Configuration (TLB Extended Mode) ..............................................................179 Figure 7.14 Flowchart of Memory Access Using UTLB (TLB Extended Mode) .........................181 Figure 7.15 Flowchart of Memory Access Using ITLB (TLB Extended Mode)...........................182 Figure 7.16 Operation of LDTLB Instruction (TLB Compatible Mode).......................................185 Figure 7.17 Operation of LDTLB Instruction (TLB Extended Mode) ..........................................186 Figure 7.18 Memory-Mapped ITLB Address Array......................................................................198 Figure 7.19 Memory-Mapped ITLB Data Array (TLB Compatible Mode) ..................................199 Figure 7.20 Memory-Mapped ITLB Data Array 1 (TLB Extended Mode)...................................200 Figure 7.21 Memory-Mapped ITLB Data Array 2 (TLB Extended Mode)...................................201 Figure 7.22 Memory-Mapped UTLB Address Array ....................................................................203 Figure 7.23 Memory-Mapped UTLB Data Array (TLB Compatible Mode).................................204 Figure 7.24 Memory-Mapped UTLB Data Array 1 (TLB Extended Mode) .................................204 Figure 7.25 Memory-Mapped UTLB Data Array 2 (TLB Extended Mode) .................................205 Section 8 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Figure 8.9 Caches Configuration of Operand Cache (Cache size = 32 Kbytes) ........................................208 Configuration of Instruction Cache (Cache size = 32 Kbytes).....................................209 Configuration of Write-Back Buffer ............................................................................221 Configuration of Write-Through Buffer.......................................................................221 Memory-Mapped IC Address Array (Cache size = 32 Kbytes) ...................................229 Memory-Mapped IC Data Array (Cache size = 32 Kbytes).........................................230 Memory-Mapped OC Address Array (Cache size = 32 Kbytes)..................................232 Memory-Mapped OC Data Array (Cache size = 32 Kbytes) .......................................233 Store Queue Configuration...........................................................................................234 Section 10 Clock Pulse Generator (CPG) Figure 10.1 Block Diagram of CPG ..............................................................................................246 Rev. 1.00 Nov. 22, 2007 Page xxxiv of lvi Section 11 Memory Controller Unit (MCU) Figure 11.1 Block Diagram of MCU............................................................................................. 256 Figure 11.2 Correspondence between Virtual Address Space and External Memory Space......... 260 Figure 11.3 Basic Timing of SRAM Interface .............................................................................. 317 Figure 11.4 Example of 32-Bit Data-Width SRAM Connection................................................... 318 Figure 11.5 Example of 16-Bit Data-Width SRAM Connection................................................... 319 Figure 11.6 Example of 8-Bit Data-Width SRAM Connection..................................................... 319 Figure 11.7 SRAM Interface Wait Timing (Software Wait Only) ................................................ 320 Figure 11.8 SRAM Interface Wait Cycle Timing (Wait Cycle Insertion by RDY Signal) ........... 321 Figure 11.9 SRAM Interface Wait State Timing (Read-Strobe Negate Timing Setting) .............. 322 Figure 11.10 Connection Example of Synchronous DRAMs for 64-Bit Data Bus (Area 1) ......... 325 Figure 11.11 Connection Example of Synchronous DRAMs for 32-Bit Data Bus (Area 1) ......... 326 Figure 11.12 Basic SDRAM Interface Timing (1) Burst Read...................................................... 328 Figure 11.13 Basic SDRAM Interface Timing (2) Burst Write..................................................... 329 Figure 11.14 Basic SDRAM Interface Timing (3) Single Read .................................................... 330 Figure 11.15 Basic SDRAM Interface Timing (4) Single Write ................................................... 331 Figure 11.16 Basic SDRAM Interface Timing (5) Burst Read Timing (Bank Open Mode; Same Row Address Accessed) ................................................. 333 Figure 11.17 Basic SDRAM Interface Timing (6) Burst Read Timing (Bank Open Mode; Different Row Addresses Accessed)........................................ 334 Figure 11.18 Basic SDRAM Interface Timing (7) Burst Write Timing (Bank Open Mode; Same Row Address Accessed) ................................................. 335 Figure 11.19 Basic SDRAM Interface Timing (8) Burst Write Timing (Bank Open Mode; Different Row Addresses Accessed)........................................ 336 Figure 11.20 Arbitration of Access Requests (1) .......................................................................... 341 Figure 11.21 Arbitration of Access Requests (2) .......................................................................... 341 Figure 11.22 Block Diagram of MCU (with Symbols Shown for Multi-Step Arbitration Circuit) ...................................... 345 Figure 11.23 Arbitration Sequence................................................................................................ 348 Figure 11.24 Reflection of Data Written by SuperHyway Bus Device ......................................... 351 Figure 11.25 Data Arrangement in Tiled Memory Areas.............................................................. 353 Figure 11.26 Schematic of Linear-to-Tiled Memory Address Translation.................................... 354 Figure 11.27 Operation of Linear-to-Tiled Memory Address Translation .................................... 356 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Direct Memory Access Controller (DMAC) Block Diagram of DMAC .......................................................................................... 360 Round-Robin Mode.................................................................................................... 389 Changes in Channel Priority in Round-Robin Mode.................................................. 390 Data Flow of Dual Address Mode.............................................................................. 391 Example of DMA Transfer Timing in Dual Address Mode (Source: Ordinary Memory, Destination: Ordinary Memory) ................................... 392 Rev. 1.00 Nov. 22, 2007 Page xxxv of lvi Figure 12.6 DMA Transfer Timing Example in Cycle-Steal Normal Mode 1 (DREQ Low Level Detection) ...................................................................................393 Figure 12.7 DMA Transfer Timing Example in Cycle-Steal Normal Mode 2 (DREQ Low Level Detection) ...................................................................................394 Figure 12.8 Example of DMA Transfer Timing in Cycle Steal Intermittent Mode (DREQ Low Level Detection) ...................................................................................394 Figure 12.9 DMA Transfer Timing Example in Burst Mode (DREQ Low Level Detection) .......395 Figure 12.10 Bus State when Multiple Channels are Operating....................................................398 Figure 12.11 DMA Transfer Flowchart.........................................................................................399 Figure 12.12 Reload Mode Transfer..............................................................................................401 Figure 12.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection...............402 Figure 12.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection..............402 Figure 12.15 Example of DREQ Input Detection in Burst Mode Edge Detection ........................403 Figure 12.16 Example of DREQ Input Detection in Burst Mode Level Detection .......................403 Figure 12.17 DMA Transfer End Signal (Cycle Steal Mode Level Detection) .............................404 Figure 12.18 Example of BSC Ordinary Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)..................................405 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Interrupt Controller (INTC) Block Diagram of INTC.............................................................................................410 On-Chip Module Interrupt Priority ............................................................................457 Interrupt Operation Flowchart....................................................................................463 Example of Interrupt Handling Routine .....................................................................466 The time requested to detect interrupts from IRQ1 and IRQ0 ...................................466 Timer Unit (TMU) Block Diagram of TMU .............................................................................................470 Example of Count Operation Setting Procedure ........................................................482 TCNT Auto-Reload Operation ...................................................................................483 Count Timing when Operating on Internal Clock ......................................................483 Count Timing when Operating on External Clock .....................................................484 Operation Timing when Using Input Capture Function .............................................485 Section 15 Serial Communication Interface with FIFO (SCIF) Figure 15.1 Block Diagram of SCIF..............................................................................................491 Figure 15.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) ...............................................................530 Figure 15.3 Sample Flowchart for SCIF Initialization ..................................................................533 Figure 15.4 Sample Flowchart for Transmitting Serial Data.........................................................534 Figure 15.5 Example of Transmit Operation (8-Bit Data, Parity, 1 Stop Bit) ...............................536 Figure 15.6 Example of Operation Using Modem Control (CTS).................................................536 Figure 15.7 Sample Flowchart for Receiving Serial Data .............................................................537 Rev. 1.00 Nov. 22, 2007 Page xxxvi of lvi Figure 15.8 Sample Flowchart for Receiving Serial Data (cont)................................................... 538 Figure 15.9 Example of SCIF Receive Operation (8-Bit Data, Parity, 1 Stop Bit) ....................... 540 Figure 15.10 Example of Operation Using Modem Control (RTS) .............................................. 540 Figure 15.11 Data Format in Clock Synchronous Communication............................................... 541 Figure 15.12 Sample Flowchart for SCIF Initialization ................................................................ 543 Figure 15.13 Sample Flowchart for Transmitting Serial Data....................................................... 544 Figure 15.14 Example of SCIF Transmit Operation...................................................................... 545 Figure 15.15 Sample Flowchart for Receiving Serial Data (1)...................................................... 546 Figure 15.16 Sample Flowchart for Receiving Serial Data (2)...................................................... 546 Figure 15.17 Example of SCIF Receive Operation ....................................................................... 547 Figure 15.18 Sample Flowchart for Transmitting/Receiving Serial Data...................................... 548 Figure 15.19 Receive Data Sampling Timing in Asynchronous Mode (Operation on a Base Clock with a Frequency 16 Times the Bit Rate) ................... 552 Section 16 I2C Bus Interface (IIC) Figure 16.1 Block Diagram for I2C Bus Interface ......................................................................... 555 Figure 16.2 I2C Bus Timing .......................................................................................................... 574 Figure 16.3 Master Data Transmit Format .................................................................................... 575 Figure 16.4 Master Data Receive Format...................................................................................... 575 Figure 16.5 Combination Transfer Format of Master Transfer ..................................................... 576 Figure 16.6 10-Bit Address Data Transmit Format ....................................................................... 576 Figure 16.7 10-Bit Address Data Receive Format......................................................................... 577 Figure 16.8 10-Bit Address Transmit/Receive Combined Format ................................................ 577 Figure 16.9 Data Transmit Mode Operation Timing ..................................................................... 579 Figure 16.10 Data Receive Mode Operation Timing .................................................................... 581 Section 17 ATAPI Figure 17.1 ATAPI Block Diagram............................................................................................... 587 Figure 17.2 PIO Timing Register .................................................................................................. 598 Figure 17.3 Multiword DMA Timing Register ............................................................................. 599 Figure 17.4 Ultra DMA Timing Register ...................................................................................... 600 Figure 17.5 ATAPI Data Bus Alignment ...................................................................................... 610 Figure 17.6 Procedure in PIO Transfer Mode ............................................................................... 612 Figure 17.7 Transfer to and from Memory via Pixel Bus by Polling ............................................ 614 Figure 17.8 Transfer to and from Memory via Pixel Bus by Interrupt .......................................... 615 Figure 17.9 Transfer to and from Memory via Pixel Bus by Polling ............................................ 616 Figure 17.10 Transfer to and from Memory via Pixel Bus by Interrupt ........................................ 617 Figure 17.11 Procedure in Hardware Reset for ATAPI Device .................................................... 617 Section 18 Serial Sound Interface (SSI) Figure 18.1 Block Diagram of SSI ................................................................................................ 620 Figure 18.2 Philips Format (with no Padding) .............................................................................. 681 Rev. 1.00 Nov. 22, 2007 Page xxxvii of lvi Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Figure 18.8 Philips Format (with Padding) ...................................................................................682 Sony Format (with Serial Data First, Followed by Padding Bits) ..............................682 Matsushita Format (with Padding Bits First, Followed by Serial Data).....................683 Multichannel Format (2 Channels, No Padding)........................................................685 Multichannel Format (3 Channels with High Padding)..............................................685 Multichannel Format (4 Channels, with Padding Bits First, Followed by Serial Data, with Padding) .........................................................................................686 Figure 18.9 Basic Sample Format (Transmit Mode with Example System/ Data Word Length) ....................................................................................................687 Figure 18.10 Inverted Clock ..........................................................................................................688 Figure 18.11 Inverted Word Select................................................................................................688 Figure 18.12 Inverted Padding Polarity.........................................................................................688 Figure 18.13 Padding Bits First, Followed by Serial Data, with Delay.........................................689 Figure 18.14 Padding Bits First, Followed by Serial Data, without Delay....................................689 Figure 18.15 Serial Data First, Followed by Padding Bits, without Delay....................................689 Figure 18.16 Parallel Right-Aligned with Delay ...........................................................................690 Figure 18.17 Mute Enabled ...........................................................................................................690 Figure 18.18 Transition Diagram between Operation Modes........................................................690 Figure 18.19 Transmission Using SSI_DMAC0 and SSI_DMAC1..............................................692 Figure 18.20 Transmission Using Interrupt Data Flow Control ....................................................693 Figure 18.21 Reception Using SSI_DMAC0 and SSI_DMAC1 ...................................................695 Figure 18.22 Reception Using Interrupt Data Flow Control .........................................................696 Section 19 Ethernet Controller (EtherC) Figure 19.1 Configuration of EtherC.............................................................................................701 Figure 19.2 EtherC Transmitter State Transitions .........................................................................736 Figure 19.3 EtherC Receiver State Transmissions ........................................................................738 Figure 19.4 (1) MII Frame Transmit Timing (Normal Transmission)...........................................739 Figure 19.4 (2) MII Frame Transmit Timing (Collision)...............................................................739 Figure 19.4 (3) MII Frame Transmit Timing (Transmit Error) .....................................................740 Figure 19.4 (4) MII Frame Receive Timing (Normal Reception) .................................................740 Figure 19.4 (5) MII Frame Receive Timing (Reception Error (1): Receive Error Notification) ...740 Figure 19.4 (6) MII Fame Receive Timing (Reception Error (2): Carrier Error Notification) ......741 Figure 19.5 MII Management Frame Format ................................................................................741 Figure 19.6 (1) 1-Bit Data Write Flowchart ..................................................................................742 Figure 19.6 (2) Bus Release Flowchart (TA in Read in Figure 19.5)............................................743 Figure 19.6 (3) 1-Bit Data Read Flowchart ...................................................................................743 Figure 19.6 (4) Independent Bus Release Flowchart (IDLE in Write in Figure 19.5)...................744 Figure 19.7 Changing IPG and Transmission Efficiency ..............................................................745 Figure 19.8 Example of Connection to DP83846AVHG ..............................................................747 Rev. 1.00 Nov. 22, 2007 Page xxxviii of lvi Section 20 Figure 20.1 Figure 20.2 Figure 20.3 Figure 20.4 Figure 20.5 Figure 20.6 Figure 20.7 Section 21 Figure 21.1 Figure 21.2 Figure 21.3 Figure 21.4 Ethernet Controller Direct Memory Access Controller (E-DMAC) Configuration of E-DMAC, and Descriptors and Buffers.......................................... 750 Relationship between Transmit Descriptor and Transmit Buffer............................... 787 Relationship between Receive Descriptor and Receive Buffer.................................. 791 Sample Transmission Flowchart (Single-Frame/Two-Descriptor) ................................... 796 Sample Reception Flowchart (Single-Frame/Two-Descriptor).................................. 798 E-DMAC Operation after Transmit Error .................................................................. 799 E-DMAC Operation after Receive Error.................................................................... 800 USB 2.0 Host/Function Module (USB) UBS Connector Connection ....................................................................................... 935 Items Relating to Interrupts........................................................................................ 940 Timing at which a BRDY Interrupt is Generated....................................................... 945 Timing at which NRDY Interrupt is Generated when Function Controller Function is Selected ................................................................................................... 951 Figure 21.5 Timing at which BEMP Interrupt is Generated when Function Controller Function is Selected ................................................................................................... 953 Figure 21.6 Device State Transitions............................................................................................. 954 Figure 21.7 Control Transfer Stage Transitions ............................................................................ 956 Figure 21.8 Example of SOFR Interrupt Output Timing............................................................... 957 Figure 21.9 Example of a Buffer Memory Map ............................................................................ 970 Figure 21.10 Example of Buffer Memory Settings ....................................................................... 974 Figure 21.11 Example of Buffer Memory Operation .................................................................... 976 Figure 21.12 Token Issuance when IITV = 0 ................................................................................ 990 Figure 21.13 Token Issuance when IITV = 1 ................................................................................ 991 Figure 21.14 Relationship between (µ) Frames and Expected Token Reception when IITV = 0 ................................................................................................................... 992 Figure 21.15 Relationship between (µ) Frames and Expected Token Reception when IITV ≠ 0 ................................................................................................................... 993 Figure 21.16 Example of Data Setup Function Operation............................................................. 995 Figure 21.17 Example of Buffer Flush Function Operation .......................................................... 996 Figure 21.18 Example of an Interval Error Being Generated when IITV = 1 ............................... 997 Section 22 Figure 22.1 Figure 22.2 Figure 22.3 Figure 22.4 Figure 22.5 Figure 22.6 Figure 22.7 LCD Controller (LCDC) LCDC Block Diagram.............................................................................................. 1002 Valid Display and the Retrace Period ...................................................................... 1038 Color-Palette Data Format ....................................................................................... 1039 Power-Supply Control Sequence and States of the LCD Module ............................ 1045 Power-Supply Control Sequence and States of the LCD Module ............................ 1045 Power-Supply Control Sequence and States of the LCD Module ............................ 1046 Power-Supply Control Sequence and States of the LCD Module ............................ 1046 Rev. 1.00 Nov. 22, 2007 Page xxxix of lvi Figure 22.8 Clock and LCD Data Signal Example......................................................................1050 Figure 22.9 Clock and LCD Data Signal Example (STN Monochrome 8-Bit Data Bus Module)...........................................................1050 Figure 22.10 Clock and LCD Data Signal Example (STN Color 4-Bit Data Bus Module).........1051 Figure 22.11 Clock and LCD Data Signal Example (STN Color 8-Bit Data Bus Module).........1051 Figure 22.12 Clock and LCD Data Signal Example (STN Color 12-Bit Data Bus Module).......1052 Figure 22.13 Clock and LCD Data Signal Example (STN Color 16-Bit Data Bus Module).......1053 Figure 22.14 Clock and LCD Data Signal Example (DSTN Monochrome 8-Bit Data Bus Module)......................................................1054 Figure 22.15 Clock and LCD Data Signal Example (DSTN Monochrome 16-Bit Data Bus Module)....................................................1055 Figure 22.16 Clock and LCD Data Signal Example (DSTN Color 8-Bit Data Bus Module)......1056 Figure 22.17 Clock and LCD Data Signal Example (DSTN Color 12-Bit Data Bus Module)....1057 Figure 22.18 Clock and LCD Data Signal Example (DSTN Color 16-Bit Data Bus Module)....1058 Figure 22.19 Clock and LCD Data Signal Example (TFT Color 12-Bit Data Bus Module) .......1059 Figure 22.20 Clock and LCD Data Signal Example (TFT Color 16-Bit Data Bus Module) .......1060 Figure 22.21 Clock and LCD Data Signal Example (8-Bit Interface Color 640 × 480)..............1061 Figure 22.22 Clock and LCD Data Signal Example (16-Bit Interface Color 640 × 480)............1062 Section 23 G2D Figure 23.1 Coordinate Transformation Flow Image ..................................................................1074 Figure 23.2 Example of Antialias Specification ..........................................................................1078 Figure 23.3 Screen Coordinates...................................................................................................1079 Figure 23.4 Rendering Coordinates .............................................................................................1080 Figure 23.5 Work Coordinates ....................................................................................................1081 Figure 23.6 2-Dimensional Source Coordinates (SS = 1)............................................................1082 Figure 23.7 1-Dimensional Source Coordinates (SS = 0)............................................................1082 Figure 23.8 Example of Source Style Specification ....................................................................1085 Figure 23.9 Example of Clipping Specification ..........................................................................1086 Figure 23.10 Example of Relative User Clipping Specification..................................................1087 Figure 23.11 Example of Source Address Specification .............................................................1090 Figure 23.12 Example of Source Direction Specification ...........................................................1092 Figure 23.13 Example of Destination Direction Specification ....................................................1092 Figure 23.14 Example of Block Enable Specification.................................................................1094 Section 24 Figure 24.1 Figure 24.2 Figure 24.3 Figure 24.4 Figure 24.5 Video Display Controller (VDC2) Block Diagram of VDC2..........................................................................................1225 Examples of Overlaid Display..................................................................................1226 Format 1 (Vsync, Hsync, DEV, DEH, DEC, and CDE Output) ..............................1228 Format 2 (SPS, SPL, CLS, and COM Output) .........................................................1229 Timing of Conversion from YC444 to YC422.........................................................1231 Rev. 1.00 Nov. 22, 2007 Page xl of lvi Figure 24.6 Data Enable Signals ................................................................................................. 1232 Figure 24.7 Pixel Bus Endian (ENDIAN = 0) ............................................................................. 1241 Figure 24.8 Pixel Bus Endian (ENDIAN = 1) ............................................................................. 1242 Figure 24.9 Graphic Image Area Settings (Reading from Memory) ........................................... 1244 Figure 24.10 Graphic Image Memory Area Settings................................................................... 1245 Figure 24.11 α Control Area Settings ......................................................................................... 1248 Figure 24.12 Screen Format ........................................................................................................ 1254 Figure 24.13 COM Signal Timing............................................................................................... 1268 Figure 24.14 Settings of DE Area Generated in SG Block.......................................................... 1269 Figure 24.15 T-1004 Video Output Position ............................................................................... 1274 Section 25 Figure 25.1 Figure 25.2 Figure 25.3 Figure 25.4 Figure 25.5 Figure 25.6 Figure 25.7 Figure 25.8 Figure 25.9 NAND Flash Memory Controller (FLCTL) FLCTL Block Diagram ............................................................................................ 1280 Register Setting Flow............................................................................................... 1307 Read Operation Timing for NAND-Type Flash Memory (1) .................................. 1308 Programming Operation Timing for NAND-Type Flash Memory (1)..................... 1309 Programming Operation Timing for NAND-Type Flash Memory (2)..................... 1309 Read Operation Timing for NAND-Type Flash Memory ........................................ 1310 Programming Operation Timing for NAND-Type Flash Memory (1)..................... 1310 Programming Operation Timing for NAND-Type Flash Memory (2)..................... 1311 Relationship between DMA Transfer and Sector (Data and Control Code), and Memory and DMA Transfer .................................................................................... 1312 Figure 25.10 Relationship between Sector Number and Address Expansion of NAND-Type Flash Memory .................................................................................. 1313 Figure 25.11 Sector Access when Unusable Sector Exists in Continuous Sectors...................... 1314 Section 26 Figure 26.1 Figure 26.2 Figure 26.3 Figure 26.4 Sampling Rate Converter (SRC) Block Diagram of SRC ............................................................................................ 1318 Sample Flowchart for Initial Setting ........................................................................ 1331 Sample Flowchart for Data Input ............................................................................. 1332 Sample Flowchart for Data Output .......................................................................... 1333 Section 28 Power-Down Mode Figure 28.1 STATUS Output when an Interrupt Occurs in Sleep Mode ..................................... 1423 Section 29 Figure 29.1 Figure 29.2 Figure 29.3 Figure 29.4 Figure 29.5 Watchdog Timer and Reset Block Diagram ......................................................................................................... 1426 WDT Counting Operations (Example in Interval Timer Mode) .............................. 1435 STATUS Output during Power-on........................................................................... 1437 STATUS Output by Reset input during Normal Operation ..................................... 1438 STATUS Output by Reset input during Sleep Mode ............................................... 1438 Rev. 1.00 Nov. 22, 2007 Page xli of lvi Figure 29.6 STATUS Output by Watchdog timer overflow Power-On Reset during Normal Operation .........................................................................................1439 Figure 29.7 STATUS Output by Watchdog timer overflow Power-On Reset during Sleep Mode ...................................................................................................1440 Section 30 User Break Controller (UBC) Figure 30.1 Block Diagram of UBC............................................................................................1442 Figure 30.2 Flowchart of User Break Debugging Support Function ...........................................1469 Section 31 Figure 31.1 Figure 31.2 Figure 31.3 Figure 31.4 User Debugging Interface (H-UDI) H-UDI Block Diagram .............................................................................................1478 Sequence for switching from Boundary-Scan TAP Controller to H-UDI................1481 TAP Controller State Transitions .............................................................................1506 H-UDI Reset.............................................................................................................1507 Section 33 Electrical Characteristics Figure 33.1 Power-on/Power-off Sequence.................................................................................1574 Figure 33.2 EXTAL Clock Input Timing ....................................................................................1582 Figure 33.3 CLKOUT Clock Output Timing (1).........................................................................1583 Figure 33.4 Power-On Oscillation Settling Time ........................................................................1583 Figure 33.5 MODE Pin Setup / Hold Timing ..............................................................................1584 Figure 33.6 Pin Drive Timing in Standby....................................................................................1584 Figure 33.7 Control Signal Timing..............................................................................................1585 Figure 33.8 Basic Bus Cycle in SRAM Bus Cycle (No Wait Cycle) ..........................................1587 Figure 33.9 Basic Bus Cycle in SRAM Bus Cycle (One Internal Wait Cycle) ...........................1588 Figure 33.10 Basic Bus Cycle in SRAM Bus Cycle (Internal Wait Cycle + One External Wait Cycle) ......................................................................................1589 Figure 33.11 Basic Bus Cycle in SRAM Bus Cycle (No Wait Cycle, Address Setup / Hold Time Insert, AnS= 1, AnH= 1) ..................................................................... 1590 Figure 33.12 SRAM Bus Cycle in Bank Open Mode Read Bus Cycle (ACT-READ) (BOMODE[1:0]= 00, SCL[2:0]= 000, SRCD= 0, CAS Latency= 2cyc, IRCD= 2cyc)..........................................................................................................1591 Figure 33.13 SRAM Bus Cycle in Bank Open Mode Pre-charge Read Bus Cycle (PRE-ACT-READ) (BOMODE[1:0]= 00, SRP[1:0]= 00, SCL[2:0]= 000, SRCD=0, IRP= 2cyc, CAS Latency= 2cyc, IRCD= 2cyc) ...................................1592 Figure 33.14 SRAM Bus Cycle in Bank Open Mode Read Bus Cycle (Read) (BOMODE[1:0]= 00, SCL[2:0]= 000, SRCD=0, CAS Latency= 2cyc, IRCD= 2cyc)..........................................................................................................1593 Figure 33.15 SRAM Bus Cycle in Bank Open Mode Write Bus Cycle (ACT-WRITE) (BOMODE[1:0]= 00, SRCD= 0, IRCD= 2cyc).....................................................1594 Rev. 1.00 Nov. 22, 2007 Page xlii of lvi Figure 33.16 SRAM Bus Cycle in Bank Open Mode Pre-charge Write Bus Cycle (PRE-ACT-SRITE) (BOMODE[1:0]= 00, SRP[1:0]= 00, SRCD=0, IRP= 2cyc, IRCD= 2cyc)....................................................................................... 1595 Figure 33.17 SRAM Bus Cycle in Bank Open Mode Write Bus Cycle (WRITE) (BOMODE[1:0]= 00, SRCD= 0, IRCD= 2cyc)..................................................... 1596 Figure 33.18 SRAM Bus Cycle in Bank Close Mode Read Bus Cycle (ACT-READA) (BOMODE[1:0]= 1, SCL[2:0]= 000, SRCD= 0, IRP= 2cyc, CAS Latency= 2cyc).............................................................................................. 1597 Figure 33.19 SRAM Bus Cycle in Bank Close Mode Write Bus Cycle (ACT-WRITEA) (BOMODE[1:0]= 00, SWR[1:0]= 00, SRP[1:0]= 00, SRCD= 0, IDAL= 4cyc, IRCD= 2cyc) ................................................................................... 1598 Figure 33.20 SRAM Bus Cycle in Pre-charge Cycle (PALL) (SRP[1:0]= 00, IRP= 2cyc) ........ 1599 Figure 33.21 SRAM Bus Cycle in Mode Register Setting Cycle (MRS).................................... 1600 Figure 33.22 SRAM Bus Cycle in Auto Refresh Cycle (REF) (SRFC[2:0]= 000, IRC= 8cyc)............................................................................... 1601 Figure 33.23 SRAM Bus Cycle in Refresh Cycle (SREF) .......................................................... 1602 Figure 33.24 NMI Input Timing.................................................................................................. 1603 Figure 33.25 IRQ, PINT Input, IRQOUT Output Timing ........................................................... 1604 Figure 33.26 DREQ/DTEND/DACK Timing ............................................................................. 1605 Figure 33.27 TCLK Input Timing ............................................................................................... 1606 Figure 33.28 I2C Timing.............................................................................................................. 1607 Figure 33.29 AC Characteristics Load Condition ....................................................................... 1607 Figure 33.30 SCK Input Clock Timing ....................................................................................... 1608 Figure 33.31 SCIF Input/Output Timing in Clocked Synchronous Mode................................... 1608 Figure 33.32 Clock Input/Output Timing .................................................................................... 1609 Figure 33.33 SSI Transmit Timing (1) ........................................................................................ 1610 Figure 33.34 SSI Transmit Timing (2) ........................................................................................ 1610 Figure 33.35 SSI Receive Timing (1).......................................................................................... 1610 Figure 33.36 SSI Receive Timing (2).......................................................................................... 1611 Figure 33.37 AUDIO_CLK Timing ............................................................................................ 1611 Figure 33.38 PIO Data Transmission In-between Devices.......................................................... 1619 Figure 33.39 Multiword DMA Data Transmission Start ............................................................. 1620 Figure 33.40 Multiword Data Transmission................................................................................ 1621 Figure 33.41 End of Multiword Data Transmission from Device ............................................... 1622 Figure 33.42 End of Multiword Data Transmission from Host................................................... 1623 Figure 33.43 Ultra-DMA Data In-burst Start .............................................................................. 1624 Figure 33.44 Ultra-DMA Data In-burst....................................................................................... 1625 Figure 33.45 Ultra-DMA Data In-burst from Host Pause ........................................................... 1625 Figure 33.46 End of Ultra-DMA Data In-burst from Device ...................................................... 1626 Figure 33.47 End of Ultra-DMA Data In-burst from Host.......................................................... 1627 Rev. 1.00 Nov. 22, 2007 Page xliii of lvi Figure 33.48 Figure 33.49 Figure 33.50 Figure 33.51 Figure 33.52 Figure 33.53 Figure 33.54 Figure 33.55 Figure 33.56 Figure 33.57 Figure 33.58 Figure 33.59 Figure 33.60 Figure 33.61 Figure 33.62 Figure 33.63 Figure 33.64 Figure 33.65 Figure 33.66 Figure 33.67 Figure 33.68 Figure 33.69 Figure 33.70 Figure 33.71 Figure 33.72 Figure 33.73 Figure 33.74 Figure 33.75 Figure 33.76 Figure 33.77 Figure 33.78 Figure 33.79 Figure 33.80 Figure 33.81 Figure 33.82 Figure 33.83 Figure 33.84 Figure 33.85 Figure 33.86 Figure 33.87 Ultra-DMA Data Out-burst Start............................................................................1628 Ultra-DMA Data Out-burst ....................................................................................1629 Ultra-DMA Data Out-burst from Device Pause .....................................................1629 End of Ultra-DMA Data Out-burst from Host ........................................................1630 End of Ultra-DMA Data Out-burst from Device....................................................1631 PIO Data Transmission (DIRECTIO) to Device ....................................................1632 PIO Data Transmission (DIRECTIO) from Device ...............................................1632 Multiword DMA Transmission (DIRECTION) .....................................................1633 Ultra-DMA Transmission Data In-burst Start(DIRECTION) ................................1634 End of Ultra-DMA Transmission Data In-burst from Device (DIRECTION).......1635 End of Ultra-DMA Transmission Data In-burst from Host (DIRECTION)...........1636 Ultra-DMA Transmission Data Out-burst Start (DIRECTION) ............................1637 End of Ultra-DMA Transmission Data Out-burst from Host (DIRECTION) ........1638 End of Ultra-DMA Transmission Data Out-burst from Device (DIRECTION) ....1639 USB Clock Timing.................................................................................................1640 GPIO Timing..........................................................................................................1641 TCK Input Timing..................................................................................................1642 PRESET Hold Timing............................................................................................1643 H-UDI Data Transmission Timing.........................................................................1643 ASEBRKAK/BRKACK Pin Break Timing ...........................................................1643 MII Transmission Timing (during Normal Operation) ..........................................1645 MII Transmission Timing (in the Event of a Collision) .........................................1645 MII Receive Timing (during Normal Operation) ................................................... 1646 MII Receive Timing (in the Event of a Collision)..................................................1646 MDIO Input Timing ................................................................................................1646 MDIO Output Timing ............................................................................................1646 WOL Output Timing ..............................................................................................1647 EXOUT Output Timing..........................................................................................1647 NAND Flush Memory Command Issue Timing ....................................................1649 NAND Flush Memory Address Issue Timing........................................................1649 NAND Flush Memory Data Read Timing ............................................................1650 NAND Flush Memory Data Write Timing.............................................................1650 NAND Flush Memory Status Read Timing ...........................................................1651 LCDC Module Signal Timing ................................................................................1653 Clock Input/Output Timing ....................................................................................1654 VDC2 Transmission Timing (1).............................................................................1655 VDC2 Transmission Timing (2).............................................................................1655 VDC2 Reception Timing (1) .................................................................................1655 VDC2 Reception Timing (2).................................................................................1656 Output Load Circuit ...............................................................................................1657 Rev. 1.00 Nov. 22, 2007 Page xliv of lvi Appendix Figure B.1 Instruction Prefetch ................................................................................................... 1661 Figure H.1 Package Dimensions .................................................................................................1684 Rev. 1.00 Nov. 22, 2007 Page xlv of lvi Rev. 1.00 Nov. 22, 2007 Page xlvi of lvi Tables Section 1 Overview Table 1.1 SH7764 Features....................................................................................................... 2 Table 1.2 Pin Functions .......................................................................................................... 15 Section 2 Programming Model Table 2.1 Initial Register Values............................................................................................. 34 Table 2.2 Bit Allocation for FPU Exception Handling........................................................... 44 Section 3 Instruction Set Table 3.1 Execution Order of Delayed Branch Instructions ................................................... 52 Table 3.2 Addressing Modes and Effective Addresses........................................................... 53 Table 3.3 Notation Used in Instruction List............................................................................ 58 Table 3.4 Fixed-Point Transfer Instructions ........................................................................... 59 Table 3.5 Arithmetic Operation Instructions .......................................................................... 61 Table 3.6 Logic Operation Instructions .................................................................................. 63 Table 3.7 Shift Instructions..................................................................................................... 64 Table 3.8 Branch Instructions ................................................................................................. 65 Table 3.9 System Control Instructions.................................................................................... 65 Table 3.10 Floating-Point Single-Precision Instructions .......................................................... 68 Table 3.11 Floating-Point Double-Precision Instructions......................................................... 69 Table 3.12 Floating-Point Control Instructions ........................................................................ 70 Table 3.13 Floating-Point Graphics Acceleration Instructions ................................................. 70 Section 4 Pipelining Table 4.1 Representations of Instruction Execution Patterns.................................................. 72 Table 4.2 Instruction Groups .................................................................................................. 82 Table 4.3 Combination of Preceding and Following Instructions........................................... 84 Table 4.4 Issue Rates and Execution Cycles........................................................................... 86 Section 5 Exception Handling Table 5.1 Register Configuration............................................................................................ 95 Table 5.2 States of Register in Each Operating Mode ............................................................ 96 Table 5.3 Exceptions............................................................................................................. 102 Table 5.4 UTLB Protection Information (TLB Compatible Mode)...................................... 113 Table 5.5 UTLB Protection Information (TLB Extended Mode) ......................................... 113 Table 5.6 ITLB Protection Information (TLB Compatible Mode) ....................................... 115 Table 5.7 ITLB Protection Information (TLB Extended Mode)........................................... 115 Rev. 1.00 Nov. 22, 2007 Page xlvii of lvi Section 6 Floating-Point Unit (FPU) Table 6.1 Floating-Point Number Formats and Parameters.................................................. 133 Table 6.2 Floating-Point Ranges .......................................................................................... 134 Table 6.3 Bit Allocation for FPU Exception Handling......................................................... 142 Section 7 Memory Management Unit (MMU) Table 7.1 Register Configuration.......................................................................................... 158 Table 7.2 Register States in Each Processing State .............................................................. 158 Table 7.3 Cache Size and Countermeasure for Avoiding Synonym Problems..................... 188 Section 8 Caches Table 8.1 Cache Features...................................................................................................... 207 Table 8.2 Store Queue Features ............................................................................................ 207 Table 8.3 Register Configuration.......................................................................................... 211 Table 8.4 Register States in Each Processing State .............................................................. 211 Section 9 On-Chip Memory Table 9.1 IL Memory Addresses .......................................................................................... 237 Table 9.2 Register Configuration.......................................................................................... 238 Table 9.3 Register States in Each Processing Mode ............................................................. 238 Table 9.4 Protective Function Exceptions to Access On-Chip Memory .............................. 242 Section 10 Clock Pulse Generator (CPG) Table 10.1 Pin Configuration and Functions of CPG ............................................................. 248 Table 10.2 Clock Operating Modes ........................................................................................ 249 Table 10.3 Register Configuration.......................................................................................... 250 Table 10.4 Register States in Each Operating Mode .............................................................. 250 Section 11 Memory Controller Unit (MCU) Table 11.1 MCU Pin Configuration........................................................................................ 258 Table 11.2 External Memory Space Map ............................................................................... 261 Table 11.3 MODE Pin Settings for Memory Bus Width of Area 0 ........................................ 261 Table 11.4 Endian Setting by Pin ........................................................................................... 262 Table 11.5 Register Configuration.......................................................................................... 263 Table 11.6 Address Multiplexing ........................................................................................... 277 Table 11.7 32-Bit External Device/Big-Endian Access and Data Alignment (Areas 0 and 3)...................................................................................................... 308 Table 11.8 16-Bit External Device/Big-Endian Access and Data Alignment (Areas 0 and 3)...................................................................................................... 308 Table 11.9 8-Bit External Device/Big-Endian Access and Data Alignment (Areas 0 and 3)...................................................................................................... 309 Table 11.10 32-Bit External Device/Little-Endian Access and Data Alignment (Areas 0 and 3).................................................................................................. 310 Rev. 1.00 Nov. 22, 2007 Page xlviii of lvi Table 11.11 Table 11.12 Table 11.13 Table 11.14 Table 11.15 Table 11.16 Table 11.17 Table 11.18 Table 11.19 16-Bit External Device/Little-Endian Access and Data Alignment (Areas 0 and 3).................................................................................................. 310 8-Bit External Device/Little-Endian Access and Data Alignment (Areas 0 and 3).................................................................................................. 311 32-Bit External Device/Big-Endian Access and Data Alignment (Areas 1 and 2).................................................................................................. 312 32-Bit External Device/Little-Endian Access and Data Alignment (Areas 1 and 2).................................................................................................. 313 64-Bit External Device/Big-Endian Access and Data Alignment (Areas 1 and 2).................................................................................................. 314 64-Bit External Device/Little-Endian Access and Data Alignment (Areas 1 and 2).................................................................................................. 315 Supported Commands for SDRAM .................................................................. 324 SDRAM Bus Widths and Address Multiplexing (External Bus Width is 32 Bits) ........................................................................ 327 Correspondence between Linear Addresses and Tiled Memory Addresses...... 355 Section 12 Direct Memory Access Controller (DMAC) Table 12.1 Pin Configuration.................................................................................................. 361 Table 12.2 Register Configuration of DMAC......................................................................... 362 Table 12.3 State of Registers in Each Operating Mode .......................................................... 364 Table 12.4 Transfer Request Sources ..................................................................................... 383 Table 12.5 Setting External Request Mode with RS Bits ....................................................... 384 Table 12.6 Selecting External Request Detection with DL, DS Bits ...................................... 385 Table 12.7 Selecting External Request Detection with DO Bit .............................................. 385 Table 12.8 Selecting On-Chip Peripheral Module Request Modes with Bits RS[3:0] ........... 386 Table 12.9 DMA Transfer Matrix in Auto-Request Mode ..................................................... 396 Table 12.10 DMA Transfer Matrix in External Request Mode (Only Channels 0 and 1) .... 396 Table 12.11 DMA Transfer Matrix in On-Chip Peripheral module Request Mode.............. 397 Section 13 Interrupt Controller (INTC) Table 13.1 Interrupt Types...................................................................................................... 412 Table 13.2 INTC Pin Configuration ....................................................................................... 414 Table 13.3 INTC Register Configuration ............................................................................... 415 Table 13.4 Register States in Each Operating Mode .............................................................. 417 Table 13.5 Interrupt Request Sources and INT2PRI0 to INT2PRI12..................................... 431 Table 13.6 Interrupt Exception Handling and Priority............................................................ 458 Table 13.7 Interrupt Response Time....................................................................................... 465 Table 13.8 Switching Sequence of IRQ1 and IRQ0 Pin Function.......................................... 467 Rev. 1.00 Nov. 22, 2007 Page xlix of lvi Section 14 Timer Unit (TMU) Table 14.1 Pin Configuration.................................................................................................. 471 Table 14.2 Register Configuration.......................................................................................... 472 Table 14.3 Register States in Each Processing Mode ............................................................. 473 Table 14.4 TMU Interrupt Sources......................................................................................... 486 Section 15 Serial Communication Interface with FIFO (SCIF) Table 15.1 Pin Configuration.................................................................................................. 492 Table 15.2 Register Configuration.......................................................................................... 493 Table 15.3 Register State in Each Operation Mode................................................................ 494 Table 15.4 SCSMR Settings ................................................................................................... 514 Table 15.5 Bit Rates and SCBRR Settings (Asynchronous Mode, BGDM = 0, ABCS = 0).................................................... 515 Table 15.6 Bit Rates and SCBRR Settings (Clock Synchronous Mode) ................................ 516 Table 15.7 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) .......................................................................................... 517 Table 15.8 Maximum Bit Rates with External Clock Input (Asynchronous Mode)............... 517 Table 15.9 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode, tScyc = 12tpcyc)......................................................................................................... 518 Table 15.10 SCSMR Settings and SCIF Communication Formats ...................................... 528 Table 15.11 SCSMR and SCSCR Settings and SCIF Clock Source Selection..................... 529 Table 15.12 Serial Communication Formats (Asynchronous Mode).................................... 531 Table 15.13 SCIF Interrupt Sources ..................................................................................... 549 Section 16 I2C Bus Interface (IIC) Table 16.1 Pin Configuration.................................................................................................. 556 Table 16.2 Register Configuration.......................................................................................... 556 Table 16.3 Register State in Each Operating Mode................................................................ 557 Table 16.4 Suggested Settings for CDF and SCGD ............................................................... 571 Table 16.5 Description on Symbols of I2C Bus Data Format ................................................. 574 Section 17 ATAPI Table 17.1 Pin Configuration.................................................................................................. 588 Table 17.2 ATA Task File Register Map................................................................................ 589 Table 17.3 ATAPI Packet Command Task File Register Map ............................................... 590 Table 17.4 ATAPI Interface Control Register Map................................................................ 591 Table 17.5 Data Transfer Modes ............................................................................................ 611 Section 18 Serial Sound Interface (SSI) Table 18.1 Pin Configuration.................................................................................................. 621 Table 18.2 SSI_DMAC0 Register Configuration ................................................................... 621 Table 18.3 SSI_DMAC0 Register State in Each Operating Mode ......................................... 624 Rev. 1.00 Nov. 22, 2007 Page l of lvi Table 18.4 Table 18.5 Table 18.6 Table 18.7 Table 18.8 Table 18.9 SSI_DMAC1 Register Configuration ................................................................... 626 SSI_DMAC1 Register State in Each Operating Mode ......................................... 628 Register Configuration of SSI_CH0 to SSI_CH5 ................................................. 631 Register State in Each Operating Mode for SSI_CH0 to SSI_CH5...................... 632 Bus Formats of SSI Module.................................................................................. 680 Number of Padding Bits for Each Valid Configuration........................................ 684 Section 19 Ethernet Controller (EtherC) Table 19.1 Pin Configuration.................................................................................................. 702 Table 19.2 Register Configuration.......................................................................................... 703 Table 19.3 Register States in Each Operation Mode .............................................................. 704 Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC) Table 20.1 Register Configuration.......................................................................................... 751 Table 20.2 Register States in Each Operating Mode .............................................................. 752 Section 21 USB 2.0 Host/Function Module (USB) Table 21.1 USB Pin Configuration ......................................................................................... 804 Table 21.2 Register Configuration.......................................................................................... 805 Table 21.3 Register State in Each Processing Mode............................................................... 808 Table 21.4 Register Bits Initialized by Writing USBE = 0 (when Function Controller Function is Selected)............................................................................................. 814 Table 21.5 Register Bits Initialized by Writing USBE = 0 (when Host Controller Function is Selected) ........................................................ 814 Table 21.6 USB Data Bus Line Status.................................................................................... 817 Table 21.7 Test Mode Operation ............................................................................................ 825 Table 21.8 Endian Operation in 32-Bit Access (when MBW = 10) ....................................... 828 Table 21.9 Endian Operation in 16-Bit Access (when MBW = 01) ....................................... 829 Table 21.10 Endian Operation in 8-Bit Access (when MBW = 00) ..................................... 829 Table 21.11 Meaning of BSTS Bit........................................................................................ 915 Table 21.12 Information Cleared by this Module by Setting ACLRM = 1 .......................... 916 Table 21.13 Operation of This Module depending on PID Setting (when Host Controller Function is Selected) .................................................... 916 Table 21.14 Operation of This Module depending on PID Setting (when Function Controller Function is Selected) ............................................. 917 Table 21.15 Information Cleared by this Module by Setting ACLRM = 1 .......................... 926 Table 21.16 Types of Reset .................................................................................................. 933 Table 21.17 Interrupt Generation Conditions ....................................................................... 936 Table 21.18 Pipe Setting Items ............................................................................................. 960 Table 21.19 Buffer Status Indicated by the BSTS Bit .......................................................... 971 Table 21.20 Buffer Status Indicated by the INBUFM Bit .................................................... 971 Table 21.21 List of Buffer Clearing Methods....................................................................... 972 Rev. 1.00 Nov. 22, 2007 Page li of lvi Table 21.22 Table 21.23 Table 21.24 Table 21.25 Table 21.26 Table 21.27 Table 21.28 Table 21.29 Table 21.30 Table 21.31 Buffer Memory Map......................................................................................... 973 Relationship between Transfer Mode Settings by CNTMD Bit and Timings at which Reading Data or Transmitting Data from FIFO Buffer is Enabled ............................................................................................................. 975 FIFO Port Function Settings ............................................................................. 977 FIFO Port Access Categorized by Pipe............................................................. 977 Packet Reception and Buffer Memory Clearing Processing............................. 979 NYET Handshake Responses ........................................................................... 984 Error Detection when a Token is Received ...................................................... 987 Error Detection when a Data Packet is Received.............................................. 988 Functions of the Interval Counter when the Function Controller Function is Selected............................................................................................................. 989 Conditions for Generating a Transaction .......................................................... 998 Section 22 LCD Controller (LCDC) Table 22.1 Pin Configuration................................................................................................ 1003 Table 22.2 Register Configuration........................................................................................ 1004 Table 22.3 Register State in Each Operating Mode.............................................................. 1005 Table 22.4 I/O Clock Frequency and Clock Division Ratio ................................................. 1008 Table 22.5 Available Power-Supply Control-Sequence Periods at Typical Frame Rates..... 1047 Table 22.6 LCDC Operating Modes..................................................................................... 1048 Table 22.7 LCD Module Power-Supply States..................................................................... 1048 Section 23 G2D Table 23.1 Commands and Rendering Attributes ................................................................. 1065 Table 23.2 Commands and Rendering Attributes. ................................................................ 1067 Table 23.3 Setting Ranges of Parameters Set by Registers and Saturation Processing ........ 1075 Table 23.4 Vertex Ranges after Operation and Saturation Processing ................................. 1075 Table 23.5 Register Configuration........................................................................................ 1184 Table 23.6 Register Bit Configuration.................................................................................. 1187 Table 23.7 Initial Register Values at Hardware Reset and Software Reset .......................... 1189 Section 24 Video Display Controller (VDC2) Table 24.1 Pin Configuration................................................................................................ 1223 Table 24.2 Functional Blocks in VDC2................................................................................ 1224 Table 24.3 Register Configuration in Graphics Block 1....................................................... 1234 Table 24.4 Register Configuration in Graphics Block 2....................................................... 1235 Table 24.5 Register Configuration in Graphics Block 3....................................................... 1236 Table 24.6 Register Configuration in Graphics Block 4....................................................... 1237 Table 24.7 Register Configuration in Display Control Block............................................... 1238 Table 24.8 Functions of Display Enable Bits ....................................................................... 1240 Table 24.9 α Value and Blending Ratio ............................................................................... 1250 Rev. 1.00 Nov. 22, 2007 Page lii of lvi Table 24.10 Example of Register Settings for T-1004 Output............................................ 1273 Section 25 NAND Flash Memory Controller (FLCTL) Table 25.1 Pin Configuration................................................................................................ 1281 Table 25.2 Register Configuration of FLCTL ...................................................................... 1282 Table 25.3 Register State of FLCTL in Each Processing Mode ........................................... 1283 Table 25.4 Status Read of NAND-Type Flash Memory....................................................... 1315 Table 25.5 FLCTL Interrupt Requests.................................................................................. 1316 Table 25.6 DMA Transfer Specifications ............................................................................. 1316 Section 26 Sampling Rate Converter (SRC) Table 26.1 Register Configuration........................................................................................ 1319 Table 26.2 State of Registers in Each Operating Mode ........................................................ 1319 Table 26.3 Alignment of Data before Sampling Rate Conversion........................................ 1320 Table 26.4 Alignment of Data in SRCOD ............................................................................ 1321 Table 26.5 Relationship between Sampling Rate Setting and Number of Output Data........ 1328 Table 26.6 Interrupt Requests and Generation Conditions ................................................... 1335 Section 27 General Purpose I/O (GPIO) Table 27.1 Multiplexed Pins Controlled by Port Control Registers...................................... 1338 Table 27.2 Multiplexed Pins Controlled by Pin Select Registers ......................................... 1343 Table 27.3 Register Configuration........................................................................................ 1346 Table 27.4 Register States in Each Operating Mode ............................................................ 1348 Section 28 Power-Down Mode Table 28.1 States in Power-Down Modes............................................................................. 1412 Table 28.2 Pin Configuration................................................................................................ 1413 Table 28.3 Register Configuration........................................................................................ 1413 Table 28.4 Register States in Each Operating Mode ............................................................ 1413 Section 29 Watchdog Timer and Reset Table 29.1 Pin Configuration................................................................................................ 1427 Table 29.2 Register Configuration........................................................................................ 1428 Table 29.3 Register States in Each Processing Mode ........................................................... 1428 Section 30 User Break Controller (UBC) Table 30.1 Register Configuration........................................................................................ 1443 Table 30.2 Register Status in Each Processing State ............................................................ 1444 Table 30.3 Settings for Match Data Setting Register............................................................ 1456 Table 30.4 Relation between Operand Sizes and Address Bits to be Compared .................. 1464 Section 31 User Debugging Interface (H-UDI) Table 31.1 Pin Configuration................................................................................................ 1479 Table 31.2 Commands Supported by Boundary-Scan TAP Controller ................................ 1481 Rev. 1.00 Nov. 22, 2007 Page liii of lvi Table 31.3 Table 31.4 Table 31.5 Table 31.6 Register Configuration (1) .................................................................................. 1482 Register Configuration (2) .................................................................................. 1482 Register Status in Each Processing State ............................................................ 1482 SDBSR Configuration ........................................................................................ 1486 Section 32 List of Registers Table 32.1 Register Configuration........................................................................................ 1510 Table 32.2 Register States in Each Operation Mode (1)....................................................... 1547 Section 33 Electrical Characteristics Table 33.1 Absolute Maximum Ratings ............................................................................... 1573 Table 33.2 Recommended Time for Power-on/Power-off Sequence.................................... 1574 Table 33.3 DC Characteristics [Common Items].................................................................. 1575 Table 33.4 DC Characteristics [Excluding the Pins Related to USB Transceiver and I2C ]..................................................................................................................... 1576 Table 33.5 DC Characteristics [Pins Related to I2C] ............................................................ 1578 Table 33.6 DC Characteristics [Pins Related to USB (1)] ................................................... 1578 Table 33.7 DC Characteristics [Pins Related to USB (2) (for Full-Speed/High-Speed Common Items)] ................................................... 1579 Table 33.8 DC Characteristics [Pins Related to USB (3) (for Full Speed)]......................... 1579 Table 33.9 DC Characteristics [Pins Related to USB (4) (for High Speed)] ........................ 1580 Table 33.10 DC Characteristics [Pins Related to USB (5) (for Low Speed)]..................... 1580 Table 33.11 Output Permissible Current Value .................................................................. 1581 Table 33.12 Clock and Control Signal Timing ................................................................... 1581 Table 33.13 Control Signal Timing .................................................................................... 1584 Table 33.14 Bus Timing ..................................................................................................... 1586 Table 33.15 INTC Module Signal Timing.......................................................................... 1603 Table 33.16 DMAC Module Signal Timing ....................................................................... 1605 Table 33.17 TMU Module Signal Timing .......................................................................... 1605 Table 33.18 I2C Module Signal Timing.............................................................................. 1606 Table 33.19 SCIF Module Signal Timing........................................................................... 1608 Table 33.20 SSI Module Signal Timing ............................................................................. 1609 Table 33.21 ATAPI Interface Resister Access Timing in PIO Transmission..................... 1612 Table 33.22 ATAPI Interface Data Transmission Timing in PIO Transmission ................ 1613 Table 33.23 ATAPI Interface Multiword Transmission Timing ........................................ 1614 Table 33.24 ATAPI Interface Ultra-DMA Transmission Timing....................................... 1615 Table 33.25 Symbol for ATAPI Interface Ultra-DMA Transmission Timing.................... 1617 Table 33.26 ATAPI Interface DIRECTION Timing .......................................................... 1618 Table 33.27 USB Module Clock Timing ............................................................................ 1640 Table 33.28 USB Electrical Characteristics (for Full Speed) ............................................. 1640 Table 33.29 USB Electrical Characteristics (for Low Speed) ............................................ 1641 Rev. 1.00 Nov. 22, 2007 Page liv of lvi Table 33.30 Table 33.31 Table 33.32 Table 33.33 Table 33.34 Table 33.35 Appendix Table D.1 Table E.1 Table F.1 Table G.1 GPIO Signal Timing ....................................................................................... 1641 H-UDI Module Signal Timing........................................................................ 1642 Ether Net Controller Timing ........................................................................... 1644 NAND Flush Memory Interface Timing......................................................... 1648 LCDC Module Signal timing.......................................................................... 1652 VDC2 Module Signal Timing......................................................................... 1654 Register Configuration........................................................................................ 1663 Pin States in Reset, Power-Down State, and Bus-Released State ....................... 1665 Treatment of Unused Pins................................................................................... 1675 Type name of the products.................................................................................. 1683 Rev. 1.00 Nov. 22, 2007 Page lv of lvi Rev. 1.00 Nov. 22, 2007 Page lvi of lvi Section 1 Overview Section 1 Overview 1.1 SH7764 Features This is a system LSI that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The CPU in this LSI has a RISC-type (Reduced Instruction Set Computer) instruction set and uses a superscalar architecture, which greatly improves instruction execution speed. This LSI features the SH-4A CPU, and it has become possible to assemble low-cost, high-performance, and highfunctioning systems, even for applications that were previously impossible with microprocessors, such as realtime control, which demands high speeds. This LSI has a 32-Kbyte instruction cache and a 32-Kbyte operand cache that can be switched between copy-back and write-through modes. It also has a memory management unit (MMU), which enables access to a 4-Gbyte virtual address space, a 4-entry fully-associative TLB for instructions, and a 64-entry fully-associative TLB for both instructions and operands. It includes 16-Kbyte on-chip SRAM, which can be accessed at a high speed and used as the system stack area or the resident area for the core of the functions requiring high performance. This LSI also has a 2D graphic engine (G2D) for fast display processing. The pictures drawn by the G2D can be displayed through the LCD controller (LCDC). In addition, this LSI provides on-chip peripheral functions necessary for system configuration, such as an Ethernet controller (EtherC), a USB host interface (supporting V2.0 high speed and full speed), an ATAPI controller (supporting Ultra DMA), a serial communication interface with FIFO (SCIF), an I2C bus interface (IIC), a serial sound interface with dedicated DMAC (SSI), a 32-bit timer (TMU), a watchdog timer (WDT), an interrupt controller (INTC), and I/O ports. This LSI also provides an external memory access support function to enable direct connection to various memory devices such as SDRAM or peripheral LSIs. These on-chip functions significantly reduce costs of designing and manufacturing application systems. The features of this LSI are listed in table 1.1. Rev. 1.00 Nov. 22, 2007 Page 1 of 1692 REJ09B0360-0100 Section 1 Overview Table 1.1 Items CPU SH7764 Features Specification • • • • Renesas Technology original SuperH architecture (SH-4A) Compatible with SH-1, SH-2, SH-3, and SH-4 at object code level 32-bit internal data bus General register file:  Sixteen 32-bit general registers (and eight 32-bit shadow registers)  Seven 32-bit control registers  Four 32-bit system registers  Register bank for high-speed response to interrupts • RISC-type instruction set (upward compatible with SH series):  Instruction length: 16-bit fixed-length basic instructions for improved code efficiency  Load/store architecture  Delayed branch instructions  Conditional execution  Instruction set based on C language • • • • • • • Superscalar architecture (providing simultaneous execution of two instructions) including FPU Instruction execution time: Up to two instructions/cycle Address space: 4 Gbytes Space identifier ASIDs: 8 bits, 256 virtual address spaces Internal multiplier Eight-stage pipeline Harvard architecture Rev. 1.00 Nov. 22, 2007 Page 2 of 1692 REJ09B0360-0100 Section 1 Overview Items FPU Specification • • • • • • • • • • • On-chip floating-point coprocessor Supports single precision (32 bits) and double precision (64 bits) Supports IEEE754-compliant data types and exceptions Two rounding modes: Round to Nearest and Round to Zero Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754 Floating-point registers: 32 bits x 16 words x 2 banks (single-precision x 16 words or double-precision x 8 words) x 2 banks 32-bit CPU-FPU floating-point communication register (FPUL) Supports FMAC (multiply-and-accumulate) instruction Supports FDIV (divide) and FSQRT (square root) instructions Supports FLDI0/FLDI1 (load constant 0/1) instructions Instruction execution time:  Latency (FADD/FSUB): 3 cycles (single-precision) or 5 cycles (double-precision)  Latency (FMAC/FMUL): 5 cycles (single-precision) or 7 cycles (double-precision)  Pitch (FADD/FSUB): 1 cycle (single-precision) or 1 cycle (doubleprecision)  Pitch (FMAC/FMUL): 1 cycle (single-precision) or 3 cycles (doubleprecision) Note: FMAC is supported for single-precision only. • 3-D graphics instructions (single-precision only)  4-dimensional vector conversion and matrix operations (FTRV): 4 cycles (pitch), 8 cycles (latency)  4-dimensional vector inner product (FIPR): 1 cycle (pitch), 5 cycles (latency) • 11-stage pipeline Rev. 1.00 Nov. 22, 2007 Page 3 of 1692 REJ09B0360-0100 Section 1 Overview Items Specification 4-Gbyte address space, 256 address space identifiers (8-bit ASIDs) Single virtual memory mode and multiple virtual memory mode Supports multiple page sizes: 1 Kbyte, 4 Kbytes, 8 Kbytes, 64 Kbytes, 256 Kbytes, 1 Mbyte, 4 Mbytes, and 64 Mbytes 4-entry fully-associative TLB for instructions 64-entry fully-associative TLB for instructions and operands Supports software-controlled replacement and random-counter replacement algorithm TLB contents can be accessed directly by address mapping Access right check Instruction cache (IC)  32-Kbyte, 4-way set associative  256 entries/way, 32-byte block length  Power-down function (way prediction) • Operand cache (OC)  32-Kbyte, 4-way set associative  256 entries/way, 32-byte block length • • Single-stage copy-back buffer and single-stage write-through buffer Store queue (32 bytes × 2 entries) 16-Kbyte fast RAM Consists of one page Accessible from the following three read/write ports  SuperHyway bus  Cache/RAM internal bus  Instruction bus • • Supports 8-, 16-, 32-, or 64-bit operand access from the CPU Supports 8-, 16-, 32-, or 64-bit access and 16- or 32-byte access through external requests Memory management • unit (MMU) • • • • • • • Cache memory • On-chip memory (IL memory) • • • Rev. 1.00 Nov. 22, 2007 Page 4 of 1692 REJ09B0360-0100 Section 1 Overview Items User break controller (UBC) Specification • • • • Supports debugging by means of user break interrupts Two break channels Address, data value, access type, and data size can all be set as break conditions Supports sequential break function Choice of main clock: 10 to 12 times EXTAL input clock Clock modes:  CPU clock: 324 MHz max.  Local bus clock: 108 MHz max.  SDRAM clock: 108 MHz max.  USB clock: 48 MHz  VDC2 clock: Appropriate frequency input depending on the display panel size Clock pulse generator (CPG) • • Watchdog timer (WDT) • Supports watchdog timer mode, in which a counter overflow resets the internal circuits, and interval mode, in which a counter overflow generates an interrupt Outputs an overflow signal externally and can assert a reset signal (power-on reset) for the circuits in the LSI in watchdog timer mode One channel Direct jump mode (compatible with SH-4) Three external interrupt pins: NMI, IRQ1, and IRQ0 On-chip peripheral module interrupts: Priority level can be set for each module Six channels; external requests available for two of them Transfer data size: Byte, word (2 bytes), longword (4 bytes), 16 bytes, or 32 bytes Maximum transfer byte count: 16,777,216 Address mode: Dual address mode Bus mode: Cycle-steal or burst mode Transfer requests: External requests (channels 0 and 1), on-chip peripheral module requests, or auto-requests selectable Priority: Fixed channel priority mode or round robin mode selectable • • Interrupt controllers (INTC) • • • Direct memory access • controller (DMAC) • • • • • • Rev. 1.00 Nov. 22, 2007 Page 5 of 1692 REJ09B0360-0100 Section 1 Overview Items Memory control unit (MCU) Specification • Supports external memory access  Outputs four external memory select signals  Supports four external memory areas (FLASH, SDRAM), each of which has 64 Mbytes max. • • • • • • SRAM: 32-, 16-, or 8-bit data bus width selectable SDRAM: 64- or 32-bit data bus width selectable Big endian or little endian mode can be set NOR-type flash memory can be connected Cycle wait function: Wait control by hardware through signals Wait control for preventing collisions on the data bus (idle cycle insertion):  Wait setting between read cycles  Wait setting between a read cycle and a write cycle [SDRAM interface] • Refresh function:  Auto-refresh (programmable refresh counter provided)  Self-refresh • Timing control: Row-column latency, column latency, row active period, write recovery period, row precharge period, auto-refresh request interval, initial precharge cycle count, and initial auto-refresh request interval • • Burst access mode: Random column (SDRAM burst length: eight for 32-bit bus or four for 64-bit bus) Initialization sequencer function: Issues precharge and auto-refresh commands [SRAM interface] Rev. 1.00 Nov. 22, 2007 Page 6 of 1692 REJ09B0360-0100 Section 1 Overview Items Timer (TMU) Specification • • • 6-channel auto-reload 32-bit timer Input-capture function (only channel 2) Choice of six counter input clocks for each channel  External clock and five peripheral clocks (Pck/4, Pck/16, Pck/64, Pck/256, and Pck/1024) (Pck is the peripheral module clock) Serial communication interface with FIFO (SCIF) • • • • • • Three channels Separate 16-byte FIFOs for transmission and reception Asynchronous mode or clock synchronous mode selectable Full-duplex communications Transmit/receive clock source: Internal clock from the baudrate generator or external clock from the SCK pin selectable Modem control function (in asynchronous mode) Supports the Philips I C bus (Inter IC Bus) interface Master and slave functions Multi-master function Supports transfer speed up to 400 kbps Programmably generates a clock from the system clock Supports primary channel Master and slave functions Transfer mode: PIO modes 0 to 4, multiword DMA modes 0 to 2, and Ultra DMA modes 0 to 4 (66 Mbps max.) High-speed transfer using 32-byte double buffer Supports descriptor mode On-chip dedicated DMAC (one channel) I/O: Supports 3.3 V 2 I C bus interface (IIC) 2 • • • • • ATAPI interface (ATAPI) • • • • • • • Note: The ATAPI controller has two groups of I/O pins: primary I/O group and secondary I/O group (mirror pins). Both groups always work in the same way but pins in different groups should not be used together. Rev. 1.00 Nov. 22, 2007 Page 7 of 1692 REJ09B0360-0100 Section 1 Overview Items Specification Six-channel bidirectional serial transfers Supports various real audio formats Master and slave functions Programmably generates a word clock or bit clock Supports multichannel format Supports 8-, 16-, 18-, 20-, 22-, 24-, or 32-bit data format SSI network function Any audio clock channels can be connected. See the following examples.  Example 1: All audio clocks are connected.  Example 2: Audio clocks for channels 0 to 2 are connected.  Example 3: Audio clocks are connected for channels 0 and 1, channels 2 and 3, and channels 4 and 5, respectively.  Example 4: Audio clocks for all channels are used independently. In the same way, the SSISCK and SSIWS pins for any channels can be connected as a set. This setting can be made independently from the audio clock connection settings. • SSI-DMAC A dedicated DMAC for the SSI is provided to transfer data between the SSI and external or on-chip memory.  Number of channels: Six for transmission and six for reception  Transfer data size: 8, 16, or 32 bytes  Maximum transfer byte count: 4,294,967,296  Bus mode: Cycle-steal mode  Priority: Fixed channel priority mode or round robin mode selectable Serial sound interface • (SSI) • • • • • • Rev. 1.00 Nov. 22, 2007 Page 8 of 1692 REJ09B0360-0100 Section 1 Overview Items Ethernet controller (EtherC) Specification • Ethernet MAC (Media Access Control) function Data frame assembly/disassembly (frame format conforming to IEEE802.3) CSMA/CD link management (data collision prevention and collision processing) CRC processing Separate 2-Kbyte FIFOs for transmission and reception Full-duplex or half-duplex transmission and reception Detects short packets and long packets • Conforms to MII (Media Independent Interface) standard Station management (STA function) 10 or 100-Mbps transfer rate • Magic Packet detection (WOL (Wake-On-LAN) signal output) Reduces the load on the CPU by means of a descriptor management system One channel for data transfer from the Ether receive FIFO (2 Kbytes) to receive buffer One channel for data transfer from the transmit buffer to EtherC transmit FIFO (2 Kbytes) Achieves efficient bus utilization through 32-byte burst transfer Supports single-frame multi-buffer transfer Conforms to USB version 2.0 Supports 480-Mbps and 12-Mbps transfer speeds Can be switched between the USB host and function by software PHY is provided Connectable with multiple peripheral devices through a hub 5-Kbyte RAM provided as a communication buffer Supports 16 x 1 to 1024 x 1024-dot display size Supports 4, 8, 15, and 16 bpp color modes Supports 1, 2, 4, and 6 bpp grayscale modes Supports TFT, DSTN, and STN display Selectable signal polarities 24-bit color palette memory (16 of 24 bits are valid: R: 5; G: 6; B: 5) Unified graphics memory architecture DMAC for Ethernet controller (E-DMAC) • • • • • USB host/function interface (USB) • • • • • • LCD controller (LCDC) • • • • • • • Rev. 1.00 Nov. 22, 2007 Page 9 of 1692 REJ09B0360-0100 Section 1 Overview Items 2D graphic engine (2D Engine: G2D) Specification [Drawing functions] • • • • • • • • • • Four-vertex drawing Polygon drawing Line drawing High-functional bold line drawing Antialiasing Raster operation/BitBLT with alpha blending 4 × 4 matrix operation + W division of perspective Source: 1, 8, or 16 bits/pixel Drawing: 8 or 16 bits/pixel Work: Binary X-direction: 0 to 4095 Y-direction: 0 to 4095 Current pointer setting Local offset setting Specific address mapped register setting Vsync wait Jump Subroutine (nesting level: 1) Plane configuration: Graphic display composed of four planes Alpha blending and chroma-key functions for graphics (supports RGB16-format input data) Digital RGB output (6 bits for each color) Panel output conforming to the VESA standard (RGB6:6:6, HD, VD, DE) BTA T-1004 digital (8:4:4 parallel) interface output Supports external synchronous mode [Coordinate transformation functions] [Color representation] [Screen coordinates] [Register setting] • • • • • • Video display controller 2 (VDC2) • • [Sequence control] [Graphic processing functions] [Output functions] • • • • Rev. 1.00 Nov. 22, 2007 Page 10 of 1692 REJ09B0360-0100 Section 1 Overview Items NAND flash memory controller (FLCTL) Specification • • • • • Directly connectable to a NAND-type flash memory Read or write in sector units (512 + 16 bytes) and ECC processing Read or write in byte units 256-byte FIFO provided Does not support multil-level (MLC) flash memory Data format: 32-bit stereo (16 bits each for L and R) or 16-bit monaural data Input sampling rate: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, or 48 kHz Output sampling rate: 44.1 or 48 kHz 77 general I/O ports Input or output can be selected for each bit Multiplexed with interrupt pins or on-chip peripheral module pins Three power-down modes provided to reduce the power consumption in this LSI  Sleep mode: Stops clock supply to the CPU.  Refresh standby mode: The CPU and on-chip peripheral modules stop operation. The CPG continues operation and the SDRAM can continue refresh operation. Module standby mode: Stops clock supply to the on-chip peripheral modules. Sampling rate converter (SRC) • • • I/O ports (GPIO) • • • Power-down modes • Debugging interfaces Power supply voltage Package Process • • • • H-UDI (User Debugging Interface) AUD (Advanced User Debugger) VDD and VDD-PLL: 1.2 ± 0.1 V VDDQ: 3.3 ± 0.3 V BGA-404 pin (19 mm x 19 mm) 90-µm CMOS process Rev. 1.00 Nov. 22, 2007 Page 11 of 1692 REJ09B0360-0100 Section 1 Overview 1.2 Block Diagram Figure 1.1 shows a block diagram of the SH7764. Rev. 1.00 Nov. 22, 2007 Page 12 of 1692 REJ09B0360-0100 Section 1 Overview SH-4A (324 MHz max.) CPU Cache FPU ILRAM MMU DMAC (6 channels) DMAC (6 channels) SuperHyway bridge Debugging H-UDI UBC ini 64 tgt 64 ini 64 SHwyPR tgt 64 ini 64 tgt 64 tgt 64 SuperHyway bus (108 MHz max., 64 bits) Ether EtherC E-DMAC SuperHyway bridge ini 64 tgt 64 INTC HPB bridge 32 32 32 32 16 16 16 16 SRC SCIF0 SCIF1 SCIF2 USB SuperHyway bus (108 MHz max., 64 bits) tgt 64 ini 64 tgt 64 32 FLCTL WDT WDT Reset GPIO CPG TMU (6 channels) Peripheral bus (54 MHz max.) USB Supercontroller Hyway PHY bridge 16 16 16 16 8 32 SSI (6 channels) SSI SSI-DMAC 32 32 16 16 32 32 32 32 32 32 32 32 32 32 32 ATAPI 64 G2D 64 64 128 128 VDC2 128 128 TMU (3 channels) 32 TMU (3 channels) LCDC 256 32 32 SuperHyway I/F LCDC I/F MCU Pixel bus I/F Request arbiter SDRAM controller [Legend] ATAPI: CPG: CPU: DMAC: E-DMAC: EtherC: FLCTL: FPU: GPIO: G2D: HPB: H-UDI: IIC: INTC: LCDC: Local bus controller ATAPI controller Clock pulse generator Central processing unit Direct memory access controller Direct memory access controller for Ethernet controller Ethernet controller NAND flash memory controller Floating-point unit General I/O 2D graphics engine Peripheral bus bridge User debugging interface I2C bus interface Interrupt controller LCD controller ILRAM: MCU: MMU: SCIF: SHwpPR: SRC: SSI: SSI-DMAC: TMU: UBC: USB: VDC2: WDT: ini: tgt: IL memory Memory controller unit Memory management unit Serial communication interface with FIFO SuperHyway bus packet router Sampling rate converter Serial sound interface DMAC for serial sound interface Timer unit User break controller USB host/function interface Video display controller 2 Watchdog timer Port for outputting requests to the bus Port for receiving requests from the bus Figure 1.1 Block Diagram Rev. 1.00 Nov. 22, 2007 Page 13 of 1692 REJ09B0360-0100 Pixel bus (108 MHz max.) SuperHyway bridge IIC 8 32 32 32 Section 1 Overview 1.3 Pin Arrangement Figure 1.2 shows the pin arrangement. 1 VSS 2 VSS VSS 3 4 VDDA_USB 5 VDD_USB DP 6 DM 7 8 VDDQ_USB 9 VDDQ 10 D52 IDED9 11 D50 IDED11 12 D48 IDED13 13 WE1 DQM64LU 14 WE0 DQM64LL 15 D38 IDED15 16 D36 IDEA2 17 D34 PF5 18 D32 PF7 A2 19 A3 20 21 CS1 22 VSS A XIN A A1 CS2 VSS VSS VSS VSSA_USB VSS_USB VBUS VSS VSSQ_USB VSS B XOUT D53 IDED8 D51 IDED10 D49 IDED12 WE3 DQM64UU WE2 DQM64UL D39 IDED14 D37 IDEA1 D35 IDEA0 D33 PF6 CLKOUT B A0 VDDQ RAS VSS VDDQ VSS VSS VSS VSS VSS VSS C D E F G H J K L M N P R T U V W Y AA AB 1 2 3 EXOUT PF4 IDECS1_M D54 IDERST D56 IDED6 D58 IDED4 D60 IDED2 D62 IDED0 D40 IDEIOWR D42 IDEIORD D44 IDEINT D46 IDECS1 CKE C VDDQ CAS R/W LNKSTA PF3 IDECS0_M WOL PF2 IDEA0_M VDDQ VSS UG12 VSSQA_USB VSS VSS D55 DIRECTION D57 IDED7 D59 IDED5 D61 IDED3 D63 IDED1 D41 IODREQ D43 IDEIORDY D45 IODACK D47 IDECS0 A4 D A7 A6 A5 COL PE7 IDEA2_M CRS PD7 IDEA1_M SSISCK2 PC3 VSS VDDQ UV12 VDDQA_USB REFRIN VDDQ VDDQ VSS VDD VSS VSS VSS VSS VDDQ VDDQ A10 E VDDQ VDDQ A9 A8 A14 MII_TXD3 MII_TXD2 AUDIO_CLK5 SSIDATA5 IODACK_M IDEINT_M PD0 PD1 MII_TXD0 MII_TXD1 SSISCK5 SSIWS5 IDEIORDY_M IDEIORD_M PD3 PD2 TX_CLK PD5 IDED15_M AUDIO_CLK2 SSIDATA2 PC2 PC5 A13 F VSS VDDQ A12 A11 A16 TX_ER PD6 IDEIOWR_M SSIWS2 PC4 A15 G VDDQ VDD VDD VDD VDD VDD VDD VDD VDD TX_EN PD4 IDED0_M RX_ER PE6 IODREQ_M MPMD VSS D25 D24 D23 D22 H SSIDATA3 PH4 VDDQ VDD VSS VSS VSS VSS VSS VSS VDD RX_DV PE4 IDED14_M RX_CLK PE5 IDED1_M SSIWS3 PH6 VSS D27 D26 D21 D20 J VSS VDD VSS VSS VSS VSS VSS VSS VDD MII_RXD1 SSISCK4 IDED13_M PE2 MII_RXD0 SSIWS4 IDED2_M PE3 SSISCK3 PH5 IRQ0 DTEND1 VSS D29 D28 D19 D18 K VSS VDD VSS VSS VSS VSS VSS VSS VDD MII_RXD2 MII_RXD3 AUDIO_CLK4 SSIDATA4 IDED3_M IDED12_M PE1 PE0 MDIO PF1 IDED11_M AUDIO_CLK3 IRQOUT PH7 DREQ1 VDDQ D31 D30 D17 D16 L VDDQ VDD VSS VSS VSS VSS VSS VSS VDD MDC PF0 IDED4_M SSIWS0 STATUS1 RTS2 PA7 VDDQ DQMUU DQMLU DQMUL DQMLL M VDDQ VDD VSS VSS VSS VSS VSS VSS VDD AUDIO_CLK0 SSISCK0 PC7 SSIDATA0 STATUS0 CTS2 PA6 VDDQ D9 D8 D7 D6 N VSS VDD VSS VSS VSS VSS VSS VSS VDD AUDIO_CLK1 SSISCK1 PC6 SSIWS1 FRE PA4 VSS D11 D10 D5 D4 P VDD VDD VDD VDD VDD VDD VDD VDD VDD PJ7 IDED10_M PJ6 IDED5_M SSIDATA1 FCE PA5 VSS D13 D12 D3 D2 R VSS VSS D15 D14 D1 PJ5 IDED9_M PJ4 IDED6_M FWE PA3 FALE PC0 D0 T VDDQ VDDQ A17 A18 PB0 A19 PB1 PJ2 IDED8_M PJ3 IDED7_M MODE7 FD6 MODE8 FD7 A20 PB2 U V W Y PJ1 IDERST_M MODE5 DIRECTION_M FD5 PJ0 MODE4 FD4 VDDQ VSS VSS VDDQ VDDQ VDDQ VDD VDD VDDQ VDDQ VSS VSS VDDQ VDDQ A25 PB7 DREQ0 RTS0 VSS A21 PB3 A23 PB5 DTEND0 RTS1 A22 PB4 CTS1 MODE3 FD3 MODE2 FD2 MODE1 FD1 VDDQ WDTOVF IRQ1 AUDCK DACK1 RXD0 AUDATA0 TDO TRST VSS VSS VSS VSS VSS VSS VSS VSS VSS CS3 CS0 VSS ASEBRKAK /BRKACK TCLK PC1 A24 PB6 DACK0 CTS0 PRESET TXD2 PA2 RXD2 PA1 VDDQ RXD1 AUDATA2 TMS VSS LCD_VEPWC LCD_VCPWC LCD_DATA15 DR4 DR3 DR5 PG7 PH1 PH0 LCD_DATA12 LCD_DATA9 DG3 DR0 PG1 PG4 LCD_DATA6 DG0 BT_DATA6 PI3 LCD_DATA5 DB5 BT_DATA5 PI2 LCD_DATA4 DB4 BT_DATA4 PI1 LCD_DATA3 DB3 BT_DATA3 LCD_CL2 DE_V/CLS PH3 PI0 COM/CDE RD VSS BREQ BS VSS SCK2 PA0 VDDQ MODE0 FD0 TXD1 AUDATA3 TXD0 AUDATA1 TDI VSS LCD_FLM VSYNC/SPS /EX_VSYNC BT_VSYNC LCD_CL1 HSYNC/SPL /EX_HSYNC BT_HSYNC LCD_M_DISP LCD_DATA14 LCD_DATA11 LCD_DATA8 DE_H/DE_C DR2 DG2 DG5 BT_DE_C PG6 PG0 PG3 LCD_DATA2 DB2 BT_DATA2 LCD_DATA0 DB0 BT_DATA0 VSS NMI BACK VSS-PLL2 VSS-PLL1 VSS VSS AA VSS RDY VDDQ SCL SDA SCK1 FR/B SCK0 AUDSYNC FCLE TCK VSS LCD_CLK DCLKIN LCD_DATA13 LCD_DATA10 LCD_DATA7 DR1 DG4 DG1 PG5 PG2 BT_DATA7 PI4 LCD_DATA1 DB1 BT_DATA1 LCD_DON DCLKOUT PH2 VSS VDD-PLL2 VDD-PLL1 EXTAL XTAL AB 16 17 18 19 20 21 22 4 5 6 7 8 9 10 11 12 13 14 15 Figure 1.2 Pin Arrangement Rev. 1.00 Nov. 22, 2007 Page 14 of 1692 REJ09B0360-0100 Section 1 Overview 1.4 Pin Functions Table 1.2 lists the pin functions. Table 1.2 Pin Functions Symbol VDD I/O I Name Power supply for internal power Function Power supply pins for the internal core power. All the VDD pins must be connected to the system power supply. This LSI does not operate if there is a pin left open. Classification Power supply VSS I Ground for Ground pins for the internal core internal power and power and I/O circuits. All the VSS I/O circuits pins must be connected to the system power supply (0 V). This LSI does not operate if there is a pin left open Power supply for I/O circuits Power supply pins for the I/O pins. All the VDDQ pins must be connected to the system power supply. This LSI does not operate if there is a pin left open. Power supply pins for the on-chip PLL1 oscillator. This LSI does not operate if there is a pin left open. Ground pins for the on-chip PLL1 oscillator. This LSI does not operate if there is a pin left open. Power supply pins for the on-chip PLL2 oscillator. This LSI does not operate if there is a pin left open. Ground pins for the on-chip PLL2 oscillator. This LSI does not operate if there is a pin left open. VDDQ I VDD_PLL1 I Power supply for PLL1 Ground for PLL1 VSS_PLL1 I VDD_PLL2 I Power supply for PLL2 Ground for PLL2 VSS_PLL2 I Clock EXTAL I Crystal Connected to a crystal resonator. An resonator/external external clock signal can also be clock input to the EXTAL pin. Crystal resonator System clock output Connected to a crystal resonator. Supplies the system clock to external devices. XTAL CLKOUT O O Rev. 1.00 Nov. 22, 2007 Page 15 of 1692 REJ09B0360-0100 Section 1 Overview Classification Operating mode control Symbol MODE2 MODE1 MODE0 MODE4 MODE3 I/O I Name Clock mode set Function These pins set the clock operating mode. Do not change the signal levels on these pins during operation. These pins set the bus operating mode. Do not change the signal levels on these pins during operation. Selects the endian for the CPU. Do not change the signal level on this pin during operation. Enables the external clock or crystal resonator for the USB. I Bus mode set MODE5 I Endian set MODE7 MODE8 System control PRESET WDTOVF BREQ I I I O I XIN/XOUT pin function set EXTAL/XTAL pin Enables the external clock or crystal function set resonator. Power-on reset Watchdog timer overflow Bus-mastership request Bus-mastership request acknowledge This LSI enters the power-on reset state when this signal goes low. Outputs an overflow signal from the WDT. A low level should be input to this pin when an external device requests the release of the bus mastership. Indicates that the bus mastership has been released to an external device. Reception of the BACK signal informs the device which has output the BREQ signal that it has acquired the bus. BACK O Rev. 1.00 Nov. 22, 2007 Page 16 of 1692 REJ09B0360-0100 Section 1 Overview Classification Interrupts Symbol NMI IRQ, IRQ0 I/O I I Name Non-maskable interrupt Function Non-maskable interrupt request pin. Fix it high when not in use. Interrupt requests Maskable interrupt request pins. 1 and 0 Level-input or edge-input detection can be selected. When the edgeinput detection is selected, the rising edge, falling edge, or both edges can also be selected. Port interrupts Pins for interrupt requests from ports. PA7 to PA0 and PB7 to PB0 are used to generate interrupts. A low level should be input to generate an interrupt. PINT15 to PINT0 I IRQOUT O Interrupt detection Address bus Data bus Status signal that indicates that an interrupt request has been detected and accepted. Address output. Bidirectional data bus. Address bus Data bus Operation status A25 to A0 D63 to D0 STATUS1, STATUS0 O I/O O Internal operation These pins indicate the following status indication status. 00: Normal state 01: Standby state 10: Sleep state 11: Reset state Rev. 1.00 Nov. 22, 2007 Page 17 of 1692 REJ09B0360-0100 Section 1 Overview Classification Bus control Symbol CS3 to CS0 BS I/O O O Name Function Chip select 3 to 0 Chip-select signals for external memory or devices. Bus cycle start Bus-cycle start signal. It is asserted for the first of the multiple bus cycles of a bus transaction. Indicates that data is read from an external device. Indicates the read/write state for an external device. It outputs a high level for a read access or a low level for a write access. Input signal for inserting a wait cycle into the bus cycles during access to the external space. Indicates a write access to bits 7 to 0 of data of an external memory or device (for 8-, 16-, or 32-bit access). This pin is multiplexed with DQM64LL. Indicates a write access to bits 15 to 8 of data of an external memory or device (for 16-, or 32-bit access). This pin is multiplexed with DQM64LU. Indicates a write access to bits 23 to 16 of data of an external memory or device (for 16-, or 32-bit access). This pin is multiplexed with DQM64UL. Indicates a write access to bits 31 to 24 of data of an external memory or device (for 8-, 16-, or 32-bit access). This pin is multiplexed with DQM64UU. RD R/W O O Read Read/write RDY I Wait WE0 O Byte select WE1 O Byte select WE2 O Byte select WE2 O Byte select Rev. 1.00 Nov. 22, 2007 Page 18 of 1692 REJ09B0360-0100 Section 1 Overview Classification Bus control DRAM interface Symbol RAS CAS CKE DQMUU DQMUL DQMLU DQMLL DQM64UU I/O O O O O O O O O Name RAS CAS CK enable Byte select 0 Byte select 1 Byte select 2 Byte select 3 Byte select 0 for 64 bits Byte select 1 for 64 bits Byte select 2 for 64 bits Byte select 3 for 64 bits Function Connected to the RAS pin when SDRAM is connected. Connected to the CAS pin when SDRAM is connected. Connected to the CKE pin when SDRAM is connected. Selects bits 31 to 24 when SDRAM is connected. Selects bits 23 to 16 when SDRAM is connected. Selects bits 15 to 8 when SDRAM is connected. Selects bits 7 to 0 when SDRAM is connected. Selects bits 63 to 56 when SDRAM is connected. This pin is multiplexed with WE3. Selects bits 55 to 48 when SDRAM is connected. This pin is multiplexed with WE2. Selects bits 47 to 40 when SDRAM is connected. This pin is multiplexed with WE1. Selects bits 39 to 32 when SDRAM is connected. This pin is multiplexed with WE0. DQM64UL O DQM64LU O DQM64LL O Rev. 1.00 Nov. 22, 2007 Page 19 of 1692 REJ09B0360-0100 Section 1 Overview Classification Symbol I/O O O O O O Name Digital red data output Function Video data output. Video display DR5 to DR0 controller 2 (VDC2) DG5 to DG0 DB5 to DB0 VSYNC/SPS HSYNC/SPL Digital green data Video data output. output Digital blue data output Video data output. Vertical sync/gate Vertical sync signal/gate start start signal signal. Horizontal sync/ sampling start signal Horizontal sync/ sampling start signal. DE_V/CLS O Vertical data Vertical data enable/gate clock enable/gate clock signal. signal Horizontal data enable/display enable signal Gate control/chroma data enable signal BTA-T1004 display data BTA-T1004 horizontal sync BTA-T1004 vertical sync BTA-T1004 display enable HSYNC input VSYNC input Panel source clock input Horizontal data enable/display enable signal. Gate control/display enable signal (asserted when the data matches the chroma-key target color specified in the register). BTA-T1004 display data output. BTA-T1004 horizontal sync signal. BTA-T1004 vertical sync signal. BTA-T1004 display enable signal. HSYNC input in external synchronous mode. VSYNC input in external synchronous mode. Display source clock input. Input an appropriate frequency depending on the display panel size. Panel clock output. DE_H/DE_C O COM/CDE O BT_DATA7 to BT_DATA0 BT_HSYNC BT_VSYNC BT_DE_C EX_HSYNC EX_VSYNC DCLKIN I/O O O O I I I DCLKOUT O Panel clock output Rev. 1.00 Nov. 22, 2007 Page 20 of 1692 REJ09B0360-0100 Section 1 Overview Classification Direct memory access controller (DMAC) Symbol DREQ0, DREQ1 DACK0, DACK1 DTEND0, DTEND1 I/O I O Name DMA-transfer request DMA-transfer request acknowledge Function Input pins to receive external requests for DMA transfer. Output pins for signals indicating acknowledge of external requests from external devices. O I I DMA-transfer end Output pins for DMA transfer end. output Carrier sense Collision Transmit data Transmit enable Transmit clock Transmit error Receive data Receive data valid Receive clock Receive error Management clock Management data MAGIC packet receive Link status General output Carrier sense signal input. Signal collision detection signal input. 4-bit transmit data. Connect them to the data transmit pins of the PHY. Indicates that transmit data is ready on MII_TXD pins. Clock signal for TX_EN, TX_ER, and MII_TXD. Notifies PHY_LSI of error during transmission. 4-bit receive data. Connect them to the data receive pins of the PHY. Indicates that receive data is ready on MII_RXD pins. Clock signal for RX_DV, RX_ER, and MII_RXD. Indicates the error during reception. Clock signal for information transfer via MDIO. Bidirectional data for exchange of management information. Receives Magic packets. Inputs link status from the PHY-LSI. External output. Ethernet controller (EtherC) CRS COL MII_TXD3 to O MII_TXD0 TX_EN TX_CLK TX_ER O I O MII_RXD3 to I MII_RXD0 RX_DV RX_CLK RX_ER MDC MDIO WOL LNKSTA EXOUT I I I O I/O O I O Rev. 1.00 Nov. 22, 2007 Page 21 of 1692 REJ09B0360-0100 Section 1 Overview Classification Symbol I/O I/O Name IDE data bus Function Bidirectional data bus. IDED15_M to IDED0_M are mirror pins. ATAPI interface IDED15 to (ATAPI) IDED0, IDED15_M to IDED0_M IDEA2 to IDEA0, O IDEA2_M to IDEA0_M IODACKI, ODACK_M IODREQ, IODREQ_M IDECS1, IDECS0, IDECS1_M, IDECS0_M IDEIOWR, IDEIOWR_M IDEIORD, IDEIORD_M IDEIORDY, IDEIORDY_M IDEINT, IDEINT_M IDERST, IDERST_M DIRECTION, DIRECTION_M O IDE address bus IDE address output. IDEA2_M to IDEA0_M are mirror pins. IDEDMA acknowledge Primary channel DMA acknowledge signal (active low). IODACK_M is a mirror pin. I IDEDMA request Primary channel DMA request signal (active high). IODREQ_M is a mirror pin. IDE chip select Primary channel chip select signal (active low). IDECS1_M and IDECS0_M are mirror pins. O O IDE write Primary channel write signal (active low). IDEIOWR_M is a mirror pin. Primary channel read signal (active low). IDEIORD_M is a mirror pin. Primary channel ready signal (active high). IDEIORDY_M is a mirror pin. Primary channel interrupt request signal (active high). IDEINT_M is a mirror pin. Primary channel ATAPI device reset signal (active low). IDERST_M is a mirror pin. External level shifter direction signal (0 when writing to the device). DIRECTION_M is a mirror pin. O IDE read I IDE ready I IDE interrupt O IDE reset O Direction Rev. 1.00 Nov. 22, 2007 Page 22 of 1692 REJ09B0360-0100 Section 1 Overview Classification Serial communication interface with FIFO (SCIF) Symbol I/O Name Serial clock Transmit data Receive data Modem control transmit enable Modem control transmit request Serial clock Serial data Function Serial clock I/O. Serial data output. Serial data input. Modem control signals to stop or restart data transmission. Modem control signals to stop or restart data reception. Serial clock I/O. Serial data I/O. SCK0, SCK1, I/O SCK2 TXD0, TXD1, TXD2 O RXD0, RXD1, I RXD2 CTS0, CTS1, CTS2 RTS0, RTS1, RTS2 I2C bus interface SCL (IIC) SDA USB XIN host/function controller (USB) XOUT DP DM VBUS REFRIN VDD_USB I/O I/O I/O I/O I Crystal resonator/ Connected to a crystal resonator or external clock for the external clock for USB operation. USB Crystal resonator Connected to a crystal resonator for for USB USB operation. D+ DVbus Reference input USB D+ signal USB D- signal USB Vbus signal Connected to the analog ground through a resistance of 5.6 kΩ (±1%) O I/O I/O I I Digital power supply Power supply for Power supply for the digital section USB PHY digital of the USB PHY. section Input 1.2 V. Ground for the digital section of the USB PHY. Input 0 V. VSS_USB Digital Ground for USB ground PHY digital section Digital power supply VDDQ_USB Power supply for Power supply for the digital section USB PHY digital of the USB PHY. section Input 3.3 V. Ground for the digital section of the USB PHY. Input 0 V. VSSQ_USB Digital Ground for USB ground PHY digital section Rev. 1.00 Nov. 22, 2007 Page 23 of 1692 REJ09B0360-0100 Section 1 Overview Classification Symbol I/O Analog power supply Analog ground Name Power supply for USB PHY analog section Function Power supply for the analog section of the USB PHY. Input 1.2 V. USB VDDA_USB host/function controller (USB) VSSA_USB Ground for USB Ground for the analog section of the PHY analog USB PHY. section Input 0 V. Power supply for USB PHY analog section Power supply for the analog section of the USB PHY. Input 3.3 V. VDDQA_USB Analog power supply VSSQA_USB Analog ground UV12 Analog power supply Analog ground I Ground for USB Ground for the analog section of the PHY analog USB PHY. section Input 0 V. USB480 MHz power supply USB480 MHz ground Timer clock Power supply for 480 MHz operation block. Input 1.2 V. Ground for 480 MHz operation block. Input 0 V. External clock input for the timer. It can also be used for the input capture signal in channel 2. UG12 32-bit timer (TMU) TCLK Rev. 1.00 Nov. 22, 2007 Page 24 of 1692 REJ09B0360-0100 Section 1 Overview Classification Serial sound interface (SSI) Symbol SSIDATA0, SSIDATA1, SSIDATA2, SSIDATA3, SSIDATA4, SSIDATA5 SSISCK0, SSISCK1, SSISCK2, SSISCK3, SSISCK4, SSISCK5, SSIWS0, SSIWS1, SSIWS2, SSIWS3, SSIWS4, SSIWS5 AUDIO_CLK0, AUDIO_CLK1, AUDIO_CLK2, AUDIO_CLK3, AUDIO_CLK4, AUDIO_CLK5 I/O I/O Name SSI data I/O Function Serial data I/O. I/O SSI clock I/O Serial clock I/O. I/O SSI clock L R I/O SSI audio external clock Word select I/O. I External clock input for audio. This clock is input to the frequency divider. LCD controller (LCDC) LCD_DATA15 to LCD_DATA0 LCD_DON LCD_CL1 LCD_CL2 LCD_CLK LCD_FLM LCD_VCPWC LCD_VEPWC LCD_M_DISP O O O O I O O O O LCD data Display start Shift clock 1 Shift clock 2 Clock source Line marker Power control (VCC) Power control (VEE) LCD currentalternating LCD panel data output. Display start (DON) signal. LCD shift clock 1/horizontal sync signal. LCD shift clock 2/dot clock. LCD clock source input. First line marker/vertical sync signal. LCD module power control (VCC). LCD module power control (VEE). LCD current-alternating/DISP signal. Rev. 1.00 Nov. 22, 2007 Page 25 of 1692 REJ09B0360-0100 Section 1 Overview Classification NAND flash memory controller (FLCTL) Symbol FCE FD7 to FD0 FCLE I/O O I/O O Name Chip enable Data I/O Command latch enable Address latch enable Function Chip enable pin. Command, address, and data I/O. Command latch enable (CLE). Asserted when a command is output. Address latch enable (ALE). Asserted when an address is output and negated when data is input or output. Read enable (RE). Reads data at the falling edge of RE. FALE O FRE O Read enable FWE O Write enable Write enable. Flash memory latches a command, address, and data at the rising edge of WE. FR/B I Ready/busy Ready/busy. Indicates ready state at a high level or busy state at a low level. I/O ports (GPIO) PA7 to PA0 PB7 to PB0 PC7 to PC0 PD7 to PD0 PE7 to PE0 PF7 to PF0 PG7 to PG0 PH7 to PH0 PI4 to PI0 PJ7 to PJ0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O General port General port General port General port General port General port General port General port General port General port 8-bit general I/O port. 8-bit general I/O port. 8-bit general I/O port. 8-bit general I/O port. 8-bit general I/O port. 8-bit general I/O port. 8-bit general I/O port. 8-bit general I/O port. 5-bit general I/O port. 8-bit general I/O port. Rev. 1.00 Nov. 22, 2007 Page 26 of 1692 REJ09B0360-0100 Section 1 Overview Classification User debugging interface (H-UDI) Symbol TCK TMS TRST TDI TDO I/O I I I I O Name Test clock Function Test clock input. Test mode select Test mode select signal input. Test reset Test data input Test data output Emulator pins Initialization signal input. Serial input for instructions and data. Serial output for instructions and data. Dedicated emulator pins. Advanced user debugger (AUD) AUDATA3 to O AUDATA0, AUDCK, AUDSYNC ASEBRKAK/ I/O BRKACK MPMD I Emulator pins Chip mode pin Dedicated emulator pins. Selects emulation support mode (MPMD =low) or LSI operation mode (MPMD = high). Rev. 1.00 Nov. 22, 2007 Page 27 of 1692 REJ09B0360-0100 Section 1 Overview 1.5 Address Map Figure 1.3 shows the address map of this LSI. 29-bit physical address space H'0000 0000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 SRAM SDRAM SDRAM SRAM Reserved Reserved Reserved On-chip peripheral modules 64 Mbytes 64 Mbytes 64 Mbytes 64 Mbytes 64 Mbytes 64 Mbytes 64 Mbytes 64 Mbytes H'E000 0000 Store queue 64 Mbytes Reserved 16 Mbytes ILRAM 16 Kbytes 512 Mbytes H'2000 0000 Reserved 512 Mbytes H'4000 0000 Reserved H'E400 0000 H'E520 0000 H'E520 4000 Reserved 1 Gbyte H'8000 0000 Reserved H'F000 0000 H'F100 0000 H'F200 0000 H'F300 0000 H'F400 0000 H'F500 0000 H'F600 0000 H'F700 0000 H'F800 0000 ICA ICD ITLBA ITLBD OCA OCD UTLBA UTLBD 160 Mbytes 16 Mbytes 16 Mbytes 16 Mbytes 16 Mbytes 16 Mbytes 16 Mbytes 16 Mbytes 16 Mbytes 1 Gbyte H'C000 0000 Reserved 512 Mbytes H'E000 0000 On-chip peripheral modules 512 Mbytes 64 Mbytes Control registers TLB translation H'FFFF FFFF 128 Mbytes H'FFFF FFFF Figure 1.3 Physical Address Space (1) Rev. 1.00 Nov. 22, 2007 Page 28 of 1692 REJ09B0360-0100 Section 1 Overview H'F800 0000 H'FE40 0000 Reserved H'FE50 0000 H'FE60 0000 H'FE80 0000 USB 1 Mbyte Reserved 1 Mbyte Reserved 2 Mbytes Reserved 3 Mbytes H'FEB0 0000 Reserved 3 Mbytes H'FEE0 0000 H'FF00 0000 Ether 2 Mbytes CPU H'FFE0 0000 H'FFE1 0000 H'FFE2 0000 H'FFE3 0000 H'FFE4 0000 H'FFE5 0000 H'FFE6 0000 H'FFE7 0000 H'FFE8 0000 H'FFE9 0000 H'FFEA 0000 H'FFEB 0000 H'FFEC 0000 H'FFED 0000 H'FFEE 0000 H'FFEF 0000 H'FFF0 0000 H'FFF1 0000 H'FFF2 0000 H'FFF3 0000 SCIF0 SCIF1 SCIF2 LCDC Reserved Reserved Reserved IIC Reserved FLCTL G2D VDC2 (POUT) VDC2 (GRA1) VDC2 (GRA2) VDC2 (GRA3) VDC2 (GRA4) ATAPI GPIO Reserved SRC 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 4 Mbytes 64 Mbytes H'FC00 0000 Debugging H'FF40 0000 H'FF60 0000 SSI 2 Mbytes DMAC 2 Mbytes 16 Mbytes H'FD00 0000 Reserved 16 Mbytes H'FE40 0000 Target registers H'FFC0 0000 H'FFC8 0000 H'FFD0 0000 H'FFD8 0000 H'FFE0 0000 H'FFE8 0000 H'FFF0 0000 H'FFF4 0000 H'FF80 0000 MCU H'FFC0 0000 HPB 4 Mbytes 4 Mbytes Reserved CPG/WDT INTC TMU SCIF, etc. FLCTL, etc. ATAPI, etc. Reserved 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 256 Kbytes 768 Kbytes Figure 1.3 Physical Address Space (2) Rev. 1.00 Nov. 22, 2007 Page 29 of 1692 REJ09B0360-0100 Section 1 Overview Rev. 1.00 Nov. 22, 2007 Page 30 of 1692 REJ09B0360-0100 Section 2 Programming Model Section 2 Programming Model The programming model of the SH-4A is explained in this section. The SH-4A has registers and data formats as shown below. 2.1 Data Formats The data formats supported in the SH-4A are shown in figure 2.1. 7 Byte (8 bits) 0 15 Word (16 bits) 0 31 Longword (32 bits) 0 Single-precision floating-point (32 bits) 31 30 s e 22 f 0 Double-precision floating-point (64 bits) 63 62 s e 51 f 0 [Legend] s :Sign field e :Exponent field f :Fraction field Figure 2.1 Data Formats Rev. 1.00 Nov. 22, 2007 Page 31 of 1692 REJ09B0360-0100 Section 2 Programming Model 2.2 2.2.1 (1) Register Descriptions Privileged Mode and Banks Processing Modes This LSI has two processing modes, user mode and privileged mode. This LSI normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be accessed differ in the two processing modes. (2) General Registers There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers which are switched by a processing mode change. • Privileged mode In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (LDC) and store control register (STC) instructions. When the RB bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC/STC instructions. When the RB bit is 0 (that is, when bank 0 is selected), the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 are accessed by the LDC/STC instructions. • User mode In user mode, the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. The eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 cannot be accessed. (3) Control Registers Control registers comprise the global base register (GBR) and status register (SR), which can be accessed in both processing modes, and the saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug base register Rev. 1.00 Nov. 22, 2007 Page 32 of 1692 REJ09B0360-0100 Section 2 Programming Model (DBR), which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. (4) System Registers System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure register (PR), and the program counter (PC). Access to these registers does not depend on the processing mode. (5) Floating-Point Registers and System Registers Related to FPU There are thirty-two floating-point registers, FR0–FR15 and XF0–XF15. FR0–FR15 and XF0– XF15 can be assigned to either of two banks (FPR0_BANK0–FPR15_BANK0 or FPR0_BANK1– FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floatingpoint registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX. System registers related to the FPU comprise the floating-point communication register (FPUL) and the floating-point status/control register (FPSCR). These registers are used for communication between the FPU and the CPU, and the exception handling setting. Register values after a reset are shown in table 2.1. Rev. 1.00 Nov. 22, 2007 Page 33 of 1692 REJ09B0360-0100 Section 2 Programming Model Table 2.1 Type Initial Register Values Registers Initial Value* Undefined General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, R8 to R15 Control registers SR MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, IMASK = B'1111, reserved bits = 0, others = undefined GBR, SSR, SPC, SGR, DBR Undefined VBR System registers MACH, MACL, PR PC Floating-point registers Note: * FR0 to FR15, XF0 to XF15, FPUL FPSCR Initialized by a power-on reset. H'00000000 Undefined H'A0000000 Undefined H'00040001 The CPU register configuration in each processing mode is shown in figure 2.2. User mode and privileged mode are switched by the processing mode bit (MD) in the status register. Rev. 1.00 Nov. 22, 2007 Page 34 of 1692 REJ09B0360-0100 Section 2 Programming Model 31 R0_BANK0*1,*2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 SR 0 31 R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC SGR DBR 0 31 R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC SGR DBR 0 GBR MACH MACL PR PC (a) Register configuration in user mode R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 (b) Register configuration in privileged mode (RB = 1) R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 (c) Register configuration in privileged mode (RB = 0) Notes: 1. R0 is used as the index register in indexed register-indirect addressing mode and indexed GBR indirect addressing mode. 2. Banked registers 3. Banked registers Accessed as general registers when the RB bit is set to 1 in SR. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. 4. Banked registers Accessed as general registers when the RB bit is cleared to 0 in SR. Accessed only by LDC/STC instructions when the RB bit is set to 1. Figure 2.2 CPU Register Configuration in Each Processing Mode Rev. 1.00 Nov. 22, 2007 Page 35 of 1692 REJ09B0360-0100 Section 2 Programming Model 2.2.2 General Registers Figure 2.3 shows the relationship between the processing modes and general registers. The SH-4A has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15). However, only 16 of these can be accessed as general registers R0 to R15 in one processing mode. The SH-4A has two processing modes, user mode and privileged mode. • R0_BANK0 to R7_BANK0 Allocated to R0 to R7 in user mode (SR.MD = 0) Allocated to R0 to R7 when SR.RB = 0 in privileged mode (SR.MD = 1). • R0_BANK1 to R7_BANK1 Cannot be accessed in user mode. Allocated to R0 to R7 when SR.RB = 1 in privileged mode. SR.MD = 0 or (SR.MD = 1, SR.RB = 0) R0 R1 R2 R3 R4 R5 R6 R7 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15 (SR.MD = 1, SR.RB = 1) R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Figure 2.3 General Registers Rev. 1.00 Nov. 22, 2007 Page 36 of 1692 REJ09B0360-0100 Section 2 Programming Model Note on Programming: As the user's R0 to R7 are assigned to R0_BANK0 to R7_BANK0, and after an exception or interrupt R0 to R7 are assigned to R0_BANK1 to R7_BANK1, it is not necessary for the interrupt handler to save and restore the user's R0 to R7 (R0_BANK0 to R7_BANK0). 2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point register configuration. There are thirty-two 32-bit floatingpoint registers, FPR0_BANK0 to FPR15_BANK0, AND FPR0_BANK1 to FPR15_BANK1, comprising two banks. These registers are referenced as FR0 to FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0 to XF15, XD0/2/4/6/8/10/12/14, or XMTRX. Reference names of each register are defined depending on the state of the FR bit in FPSCR (see figure 2.4). 1. Floating-point registers, FPRn_BANKj (32 registers) FPR0_BANK0 to FPR15_BANK0 FPR0_BANK1 to FPR15_BANK1 2. Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0 to FR15 are assigned to FPR0_BANK0 to FPR15_BANK0; when FPSCR.FR = 1, FR0 to FR15 are assigned to FPR0_BANK1 to FPR15_BANK1. 3. Double-precision floating-point registers or single-precision floating-point registers, DRi (8 registers): A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15} 4. Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises four FR registers. FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7}, FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15} 5. Single-precision floating-point extended registers, XFi (16 registers) When FPSCR.FR = 0, XF0 to XF15 are assigned to FPR0_BANK1 to FPR15_BANK1; when FPSCR.FR = 1, XF0 to XF15 are assigned to FPR0_BANK0 to FPR15_BANK0. 6. Double-precision floating-point extended registers, XDi (8 registers): An XD register comprises two XF registers. XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15} Rev. 1.00 Nov. 22, 2007 Page 37 of 1692 REJ09B0360-0100 Section 2 Programming Model 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FPSCR.FR = 1 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FPR0_BANK0 FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 FPR11_BANK0 FPR12_BANK0 FPR13_BANK0 FPR14_BANK0 FPR15_BANK0 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 XMTRX FPSCR.FR = 0 FV0 DR0 DR2 FV4 DR4 DR6 FV8 DR8 DR10 FV12 DR12 DR14 XMTRX XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 Figure 2.4 Floating-Point Registers Rev. 1.00 Nov. 22, 2007 Page 38 of 1692 REJ09B0360-0100 Section 2 Programming Model 2.2.4 (1) Control Registers Status Register (SR) BIt: 31 0 R 15 30 MD 1 R/W 14 0 R 29 RB 1 R/W 13 0 R 28 BL 1 R/W 12 0 R 0 R 11 0 R 0 R 10 0 R 0 R 9 M 0 R/W 0 R 8 Q 0 R/W 0 R 7 1 R/W 0 R 6 0 R 5 0 R 4 1 R/W 0 R 3 0 R 0 R 2 0 R 0 R 1 S 0 R/W 0 R 0 T 0 R/W 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: BIt: FD Initial value: 0 R/W: R/W IMASK 1 1 R/W R/W Bit 31 Bit Name — Initial Value 0 R/W R Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. 30 MD 1 R/W Processing Mode Selects the processing mode. 0: User mode (Some instructions cannot be executed and some resources cannot be accessed.) 1: Privileged mode This bit is set to 1 by an exception or interrupt. 29 RB 1 R/W Privileged Mode General Register Bank Specification Bit 0: R0_BANK0 to R7_BANK0 are accessed as general registers R0 to R7 and R0_BANK1 to R7_BANK1 can be accessed using LDC/STC instructions 1: R0_BANK1 to R7_BANK1 are accessed as general registers R0 to R7 and R0_BANK0–R7_BANK0 can be accessed using LDC/STC instructions This bit is set to 1 by an exception or interrupt. 28 BL 1 R/W Exception/Interrupt Block Bit This bit is set to 1 by a reset, a general exception, or an interrupt. While this bit is set to 1, an interrupt request is masked. In this case, this processor enters the reset state when a general exception other than a user break occurs. Rev. 1.00 Nov. 22, 2007 Page 39 of 1692 REJ09B0360-0100 Section 2 Programming Model Bit Bit Name Initial Value All 0 R/W R Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. 27 to 16 — 15 FD 0 R/W FPU Disable Bit When this bit is set to 1 and an FPU instruction is not in a delay slot, a general FPU disable exception occurs. When this bit is set to 1 and an FPU instruction is in a delay slot, a slot FPU disable exception occurs. (FPU instructions: H'F*** instructions and LDS (.L)/STS(.L) instructions using FPUL/FPSCR) 14 to 10 — All 0 R Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. 9 8 7 to 4 M Q IMASK 0 0 1111 R/W R/W R/W M Bit Used by the DIV0S, DIV0U, and DIV1 instructions. Q Bit Used by the DIV0S, DIV0U, and DIV1 instructions. Interrupt Mask Level Bits An interrupt whose priority is equal to or less than the value of the IMASK bits is masked. It can be chosen by CPU operation mode register (CPUOPM) whether the level of IMASK is changed to accept an interrupt or not when an interrupt is occurred. For details, see appendix A, CPU Operation Mode Register (CPUOPM). Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. 3, 2 — All 0 R 1 0 S T 0 0 R/W R/W S Bit Used by the MAC instruction. T Bit Indicates true/false condition, carry/borrow, or overflow/underflow. For details, see section 3, Instruction Set. Rev. 1.00 Nov. 22, 2007 Page 40 of 1692 REJ09B0360-0100 Section 2 Programming Model (2) Saved Status Register (SSR) (32 bits, Privileged Mode, Initial Value = Undefined) The contents of SR are saved to SSR in the event of an exception or interrupt. (3) Saved Program Counter (SPC) (32 bits, Privileged Mode, Initial Value = Undefined) The address of an instruction at which an interrupt or exception occurs is saved to SPC. (4) Global Base Register (GBR) (32 bits, Initial Value = Undefined) GBR is referenced as the base address of addressing @(disp,GBR) and @(R0,GBR). (5) Vector Base Register (VBR) (32 bits, Privileged Mode, Initial Value = H'00000000) VBR is referenced as the branch destination base address in the event of an exception or interrupt. For details, see section 5, Exception Handling. (6) Saved General Register 15 (SGR) (32 bits, Privileged Mode, Initial Value = Undefined) The contents of R15 are saved to SGR in the event of an exception or interrupt. (7) Debug Base Register (DBR) (32 bits, Privileged Mode, Initial Value = Undefined) When the user break debugging function is enabled (CBCR.UBDE = 1), DBR is referenced as the branch destination address of the user break handler instead of VBR. 2.2.5 (1) System Registers Multiply-and-Accumulate Registers (MACH and MACL) (32 bits, Initial Value = Undefined) MACH and MACL are used for the added value in a MAC instruction, and to store the operation result of a MAC or MUL instruction. (2) Procedure Register (PR) (32 bits, Initial Value = Undefined) The return address is stored in PR in a subroutine call using a BSR, BSRF, or JSR instruction. PR is referenced by the subroutine return instruction (RTS). (3) Program Counter (PC) (32 bits, Initial Value = H'A0000000) PC indicates the address of the instruction currently being executed. Rev. 1.00 Nov. 22, 2007 Page 41 of 1692 REJ09B0360-0100 Section 2 Programming Model (4) Floating-Point Status/Control Register (FPSCR) BIt: 31 0 R 15 0 R/W 30 0 R 14 0 R/W 29 0 R 13 0 R/W 28 0 R 12 0 R/W 27 0 R 11 0 R/W 26 0 R 10 0 R/W 25 0 R 9 Enable (EN) 24 0 R 8 0 R/W 23 0 R 7 0 R/W 22 0 R 6 0 R/W 21 FR 20 SZ 19 PR 18 DN 17 0 R/W 1 RM 16 0 R/W 0 1 R/W Cause Initial value: R/W: BIt: Initial value: R/W: 0 R/W 5 0 R/W 0 R/W 4 Flag 0 R/W 3 0 R/W 1 R/W 2 0 R/W Cause 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. Floating-Point Register Bank 0: FPR0_BANK0 to FPR15_BANK0 are assigned to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1 are assigned to XF0 to XF15 1: FPR0_BANK0 to FPR15_BANK0 are assigned to XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1 are assigned to FR0 to FR15 31 to 22 — 21 FR 0 R/W 20 SZ 0 R/W Transfer Size Mode 0: Data size of FMOV instruction is 32-bits 1: Data size of FMOV instruction is a 32-bit register pair (64 bits) For relationship between the SZ bit, PR bit, and endian, see figure 2.5. 19 PR 0 R/W Precision Mode 0: Floating-point instructions are executed as single-precision operations 1: Floating-point instructions are executed as double-precision operations (graphics support instructions are undefined) For relationship between the SZ bit, PR bit, and endian, see figure 2.5 18 DN 1 R/W Denormalization Mode 0: Denormalized number is treated as such 1: Denormalized number is treated as zero Rev. 1.00 Nov. 22, 2007 Page 42 of 1692 REJ09B0360-0100 Section 2 Programming Model Bit Bit Name Initial Value 000000 R/W R/W R/W R/W Description FPU Exception Cause Field FPU Exception Enable Field FPU Exception Flag Field Each time an FPU operation instruction is executed, the FPU exception cause field is cleared to 0. When an FPU exception occurs, the bits corresponding to FPU exception cause field and flag field are set to 1. The FPU exception flag field remains set to 1 until it is cleared to 0 by software. For bit allocations of each field, see table 2.2. Rounding Mode These bits select the rounding mode. 00: Round to Nearest 01: Round to Zero 10: Reserved 11: Reserved 17 to 12 Cause 11 to 7 6 to 2 Enable (EN) 00000 Flag 00000 1, 0 RM 01 R/W Rev. 1.00 Nov. 22, 2007 Page 43 of 1692 REJ09B0360-0100 Section 2 Programming Model 63 Floating-point register 63 FR (2i) FR (2i+1) DR (2i) 0 0 63 Memory area 8n 32 31 8n+3 8n+4 0 8n+7 63 Floating-point register 63 FR (2i) FR (2i+1) DR (2i) 0 63 DR (2i) 0 63 DR (2i) 0 *1, *2 0 63 FR (2i) *2 0 FR (2i+1) 63 FR (2i) FR (2i+1) 0 63 Memory area 4n+3 32 31 4n 4m+3 (1) SZ = 0 0 4m 63 8n+3 32 31 8n 8n+7 (2) SZ = 1, PR = 0 0 8n+4 63 8n+7 32 31 8n+4 8n+3 (3) SZ = 1, PR = 1 0 8n Notes: 1. In the case of SZ = 0 and PR = 0, DR register can not be used. 2. The bit-location of DR register is used for double precision format when PR = 1. (In the case of (2), it is used when PR is changed from 0 to 1.) Figure 2.5 Relationship between SZ bit and Endian Table 2.2 Field Name Cause Enable Flag FPU exception cause field FPU exception enable field Bit Allocation for FPU Exception Handling FPU Error (E) Bit 17 None Invalid Division Operation (V) by Zero (Z) Bit 16 Bit 11 Bit 6 Bit 15 Bit 10 Bit 5 Overflow Underflow Inexact (O) (U) (I) Bit 14 Bit 9 Bit 4 Bit 13 Bit 8 Bit 3 Bit 12 Bit 7 Bit 2 FPU exception flag None field (5) Floating-Point Communication Register (FPUL) (32 bits, Initial Value = Undefined) Information is transferred between the FPU and CPU via FPUL. Rev. 1.00 Nov. 22, 2007 Page 44 of 1692 REJ09B0360-0100 Section 2 Programming Model 2.3 Memory-Mapped Registers Some control registers are mapped to the following memory areas. Each of the mapped registers has two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are used as follows. • H'1C00 0000 to H'1FFF FFFF This area must be accessed using the address translation function of the MMU. Setting the page number of this area to the corresponding field of the TLB enables access to a memory-mapped register. The operation of an access to this area without using the address translation function of the MMU is not guaranteed. • H'FC00 0000 to H'FFFF FFFF Access to area H'FC00 0000 to H'FFFF FFFF in user mode will cause an address error. Memory-mapped registers can be referenced in user mode by means of access that involves address translation. Note: Do not access addresses to which registers are not mapped in either area. The operation of an access to an address with no register mapped is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined. Rev. 1.00 Nov. 22, 2007 Page 45 of 1692 REJ09B0360-0100 Section 2 Programming Model 2.4 Data Formats in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 76 S 0 31 S 76 S 0 15 14 S 0 31 S 15 14 S 0 Figure 2.6 Formats of Byte Data and Word Data in Register 2.5 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in an 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being loaded into a register. A word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). An address error will result if this rule is not observed. A byte operand can be accessed from any address. Big endian or little endian byte order can be selected for the data format. The endian should be set with the external pin after a power-on reset. The endian cannot be changed dynamically. Bit positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. The data format in memory is shown in figure 2.7. Rev. 1.00 Nov. 22, 2007 Page 46 of 1692 REJ09B0360-0100 Section 2 Programming Model A 31 7 07 A+1 23 07 A+2 15 7 07 A+3 0 0 A + 11 A + 10 A + 9 31 7 23 07 15 07 7 07 A+8 0 0 Address A Byte 0 Byte 1 Byte 2 Byte 3 Address A + 4 Address A + 8 15 0 15 Byte 3 Byte 2 Byte 1 Byte 0 Address A + 8 0 15 0 0 15 Word 0 31 Word 1 0 31 Word 1 Word 0 0 Address A + 4 Address A Longword Longword Big endian Little endian Figure 2.7 Data Formats in Memory For the 64-bit data format, see figure 2.5. 2.6 Processing States This LSI has major three processing states: the reset state, instruction execution state, and powerdown state. (1) Reset State In this state the CPU is reset. In the power-on reset state, the internal state of the CPU and the on-chip peripheral module registers are initialized. For details, see register descriptions for each section. (2) Instruction Execution State In this state, the CPU executes program instructions in sequence. The Instruction execution state has the normal program execution state and the exception handling state. (3) Power-Down State In a power-down state, CPU halts operation and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. There are two modes in the power-down state: sleep mode and standby mode. For details, see section 28, Power-Down Mode. Rev. 1.00 Nov. 22, 2007 Page 47 of 1692 REJ09B0360-0100 Section 2 Programming Model From any state when reset input Reset state Reset clearance Reset input Reset input Instruction execution state Sleep instruction execution Power-down state Interrupt occurence Figure 2.8 Processing State Transitions Rev. 1.00 Nov. 22, 2007 Page 48 of 1692 REJ09B0360-0100 Section 2 Programming Model 2.7 2.7.1 Usage Notes Notes on Self-Modifying Code To accelerate the processing speed, the instruction prefetching capability of the SH-4A has been significantly enhanced from that of the SH-4. Therefore, in the case when a code in memory is rewritten and attempted to be executed immediately, there is increased possibility that the code before being modified, which has already been prefetched, is executed. To ensure execution of the modified code, one of the following sequence of instructions should be executed between the code rewriting instruction and execution of the modified code. (1) When the Codes to be Modified are in Non-Cacheable Area SYNCO ICBI @Rn The target for the ICBI instruction can be any address within the range where no address error exception occurs. (2) When the Codes to be Modified are in Cacheable Area (Write-Through) SYNCO ICBI @Rn All instruction cache areas corresponding to the modified codes should be invalidated by the ICBI instruction. The ICBI instruction should be issued to each cache line. One cache line is 32 bytes. (3) When the Codes to be Modified are in Cacheable Area (Copy-Back) OCBP @Rm or OCBWB @Rm SYNCO ICBI @Rn All operand cache areas corresponding to the modified codes should be written back to the main memory by the OCBP or OCBWB instruction. Then all instruction cache areas corresponding to the modified codes should be invalidated by the ICBI instruction. The OCBP, OCBWB, and ICBI instruction should be issued to each cache line. One cache line is 32 bytes. Note: Self-modifying code is the processing which executes instructions while dynamically rewriting the codes in memory. Rev. 1.00 Nov. 22, 2007 Page 49 of 1692 REJ09B0360-0100 Section 2 Programming Model Rev. 1.00 Nov. 22, 2007 Page 50 of 1692 REJ09B0360-0100 Section 3 Instruction Set Section 3 Instruction Set The SH-4A's instruction set is implemented with 16-bit fixed-length instructions. The SH-4A can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved to and from memory using longword or quadword size. Double-precision floating-point data (64 bits) can be moved to and from memory using longword size. When the SH-4A moves byte-size or word-size data from memory to a register, the data is sign-extended. 3.1 (1) PC Execution Environment At the start of instruction execution, the PC indicates the address of the instruction itself. (2) Load-Store Architecture The SH-4A has a load-store architecture in which operations are basically executed using registers. Except for bit-manipulation operations such as logical AND that are executed directly in memory, operands in an operation that requires memory access are loaded into registers and the operation is executed between the registers. (3) Delayed Branches Except for the two branch instructions BF and BT, the SH-4A's branch instructions and RTE are delayed branches. In a delayed branch, the instruction following the branch is executed before the branch destination instruction. (4) Delay Slot This execution slot following a delayed branch is called a delay slot. For example, the BRA execution sequence is as follows: Rev. 1.00 Nov. 22, 2007 Page 51 of 1692 REJ09B0360-0100 Section 3 Instruction Set Table 3.1 Execution Order of Delayed Branch Instructions Instructions BRA ADD : : TARGET (Delayed branch instruction) (Delay slot) Execution Order BRA ↓ ADD ↓ (Branch destination instruction) target-inst TARGET target-inst A slot illegal instruction exception may occur when a specific instruction is executed in a delay slot. For details, see section 5, Exception Handling. The instruction following BF/S or BT/S for which the branch is not taken is also a delay slot instruction. (5) T Bit The T bit in SR is used to show the result of a compare operation, and is referenced by a conditional branch instruction. An example of the use of a conditional branch instruction is shown below. ADD #1, R0 CMP/EQ R1, R0 BT TARGET ; T bit is not changed by ADD operation ; If R0 = R1, T bit is set to 1 ; Branches to TARGET if T bit = 1 (R0 = R1) In an RTE delay slot, the SR bits are referenced as follows. In instruction access, the MD bit is used before modification, and in data access, the MD bit is accessed after modification. The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot instruction execution. The STC and STC.L SR instructions access all SR bits after modification. (6) Constant Values An 8-bit constant value can be specified by the instruction code and an immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in memory, and can be referenced by a PC-relative load instruction. MOV.W @(disp, PC), Rn MOV.L @(disp, PC), Rn There are no PC-relative load instructions for floating-point operations. However, it is possible to set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on a single-precision floating-point register. Rev. 1.00 Nov. 22, 2007 Page 52 of 1692 REJ09B0360-0100 Section 3 Instruction Set 3.2 Addressing Modes Addressing modes and effective address calculation methods are shown in table 3.2. When a location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (SV in MMUCR = 0), the least significant bit of PTEH is also referenced as the access ASID. For details, see section 7, Memory Management Unit (MMU). Table 3.2 Addressing Modes and Effective Addresses Effective Address Calculation Method Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents. Rn Rn Addressing Instruction Mode Format Register direct Register indirect Register indirect with postincrement Rn @Rn Calculation Formula — Rn → EA (EA: effective address) Rn → EA After instruction execution Byte: Rn + 1 → Rn Word: Rn + 2 → Rn Longword: Rn + 4 → Rn Quadword: Rn + 8 → Rn @Rn+ Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. Rn Rn + 1/2/4 + Rn 1/2/4 Rev. 1.00 Nov. 22, 2007 Page 53 of 1692 REJ09B0360-0100 Section 3 Instruction Set Addressing Mode Register indirect with predecrement Instruction Format @–Rn Effective Address Calculation Method Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. Rn Rn – 1/2/4 Calculation Formula Byte: Rn – 1 → Rn Word: Rn – 2 → Rn Longword: Rn – 4 → Rn Quadword: Rn – 8 → Rn Rn → EA (Instruction executed with Rn after calculation) Byte: Rn + disp → EA Word: Rn + disp × 2 → EA Longword: Rn + disp × 4 → EA – Rn – 1/2/4/8 1/2/4 Register @(disp:4, Rn) Effective address is register Rn contents with indirect with 4-bit displacement disp added. After disp is displacement zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. Rn disp (zero-extended) × 1/2/4 + Rn + disp × 1/2/4 Indexed register indirect @(R0, Rn) Effective address is sum of register Rn and R0 contents. Rn + Rn + R0 → EA Rn + R0 R0 Rev. 1.00 Nov. 22, 2007 Page 54 of 1692 REJ09B0360-0100 Section 3 Instruction Set Addressing Mode Instruction Format Effective Address Calculation Method Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. GBR disp (zero-extended) Calculation Formula Byte: GBR + disp → EA Word: GBR + disp × 2 → EA Longword: GBR + disp × 4 → EA GBR indirect @(disp:8, with displace- GBR) ment + × GBR + disp × 1/2/4 1/2/4 Indexed GBR @(R0, GBR) indirect Effective address is sum of register GBR and R0 contents. GBR + GBR + R0 → EA GBR + R0 R0 PC-relative @(disp:8, PC) with displacement Effective address is PC + 4 with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 2 (word), or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. PC &* Word: PC + 4 + disp × 2 → EA Longword: PC & H'FFFF FFFC + 4 + disp × 4 → EA H'FFFF FFFC 4 + + disp (zero-extended) PC + 4 + disp ×2 or PC & H'FFFF FFFC + 4 + disp × 4 × 2/4 * With longword operand Rev. 1.00 Nov. 22, 2007 Page 55 of 1692 REJ09B0360-0100 Section 3 Instruction Set Addressing Instruction Mode Format Effective Address Calculation Method PC-relative disp:8 Effective address is PC + 4 with 8-bit displacement disp added after being sign-extended and multiplied by 2. PC Calculation Formula PC + 4 + disp × 2 → BranchTarget + 4 + disp (sign-extended) PC + 4 + disp × 2 × 2 PC-relative disp:12 Effective address is PC + 4 with 12-bit displacement disp added after being sign-extended and multiplied by 2. PC + PC + 4 + disp × 2 → BranchTarget 4 + disp (sign-extended) PC + 4 + disp × 2 × 2 Rn Effective address is sum of PC + 4 and Rn. PC + PC + 4 + Rn → Branch-Target 4 Rn + PC + 4 + Rn Rev. 1.00 Nov. 22, 2007 Page 56 of 1692 REJ09B0360-0100 Section 3 Instruction Set Addressing Instruction Mode Format Effective Address Calculation Method Immediate #imm:8 #imm:8 #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4. Calculation Formula — — — Note: For the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling (×1, ×2, or ×4) is performed according to the operand size. This is done to clarify the operation of the LSI. Refer to the relevant assembler notation rules for the actual assembler descriptions. @ (disp:4, Rn) ; Register indirect with displacement @ (disp:8, GBR) ; GBR indirect with displacement @ (disp:8, PC) ; PC-relative with displacement disp:8, disp:12 ; PC-relative Rev. 1.00 Nov. 22, 2007 Page 57 of 1692 REJ09B0360-0100 Section 3 Instruction Set 3.3 Instruction Set Table 3.3 shows the notation used in the SH instruction lists shown in tables 3.4 to 3.13. Table 3.3 Item Instruction mnemonic Notation Used in Instruction List Format OP.Sz SRC, DEST Description OP: Sz: SRC: DEST: Rm: Rn: imm: disp: →, ← (xx) M/Q/T & | Operation code Size Source operand Source and/or destination operand Source register Destination register Immediate data Displacement Operation notation Transfer direction Memory operand SR flag bits Logical AND of individual bits Logical OR of individual bits ∧ Logical exclusive-OR of individual bits ~ Logical NOT of individual bits n n-bit shift MSB ↔ LSB mmmm: nnnn: 0000: 0001: : 1111: mmm: nnn: 000: 001: : 111: mm: nn: 00: 01: 10: 11: iiii: dddd: Register number (Rm, FRm) Register number (Rn, FRn) R0, FR0 R1, FR1 R15, FR15 Register number (DRm, XDm, Rm_BANK) Register number (DRn, XDn, Rn_BANK) DR0, XD0, R0_BANK DR2, XD2, R1_BANK DR14, XD14, R7_BANK Register number (FVm) Register number (FVn) FV0 FV4 FV8 FV12 Immediate data Displacement Instruction code Rev. 1.00 Nov. 22, 2007 Page 58 of 1692 REJ09B0360-0100 Section 3 Instruction Set Item Privileged mode T bit New Format Description "Privileged" means the instruction can only be executed in privileged mode. Value of T bit after —: No change instruction execution  "New" means the instruction which has been newly added in the SH-4A with H’20-valued VER bits in the processor version register (PVR). Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand. Table 3.4 Instruction MOV MOV.W MOV.L MOV MOV.B MOV.W MOV.L MOV.B Fixed-Point Transfer Instructions Operation imm → sign extension → Rn Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd Privileged T Bit New — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — #imm,Rn @(disp*,PC), Rn (disp × 2 + PC + 4) → sign extension → Rn @(disp*,PC), Rn (disp × 4 + PC & H'FFFF FFFC 1101nnnndddddddd + 4) → Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn Rm → Rn Rm → (Rn) Rm → (Rn) Rm → (Rn) (Rm) → sign extension → Rn (Rm) → sign extension → Rn (Rm) → Rn Rn-1 → Rn, Rm → (Rn) Rn-2 → Rn, Rm → (Rn) Rn-4 → Rn, Rm → (Rn) (Rm)→ sign extension → Rn, Rm + 1 → Rm (Rm) → sign extension → Rn, Rm + 2 → Rm (Rm) → Rn, Rm + 4 → Rm R0 → (disp + Rn) R0 → (disp × 2 + Rn) Rm → (disp × 4 + Rn) 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd MOV.W @Rm,Rn MOV.L MOV.B @Rm,Rn Rm,@-Rn MOV.W Rm,@-Rn MOV.L MOV.B Rm,@-Rn @Rm+,Rn MOV.W @Rm+,Rn MOV.L MOV.B @Rm+,Rn R0,@(disp*,Rn) MOV.W R0,@(disp*,Rn) MOV.L Rm,@(disp*,Rn) Rev. 1.00 Nov. 22, 2007 Page 59 of 1692 REJ09B0360-0100 Section 3 Instruction Set Instruction MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA @(disp*,Rm),R0 Operation (disp + Rm) → sign extension → R0 (disp × 2 + Rm) → sign extension → R0 (disp × 4 + Rm) → Rn Rm → (R0 + Rn) Rm → (R0 + Rn) Rm → (R0 + Rn) (R0 + Rm) → sign extension → Rn (R0 + Rm) → sign extension → Rn (R0 + Rm) → Rn R0 → (disp + GBR) R0 → (disp × 2 + GBR) R0 → (disp × 4 + GBR) (disp + GBR) → sign extension → R0 (disp × 2 + GBR) → sign extension → R0 (disp × 4 + GBR) → R0 disp × 4 + PC & H'FFFF FFFC + 4 → R0 LDST → T If (T == 1) R0 → (Rn) 0 → LDST Instruction Code 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd 11000101dddddddd 11000110dddddddd 11000111dddddddd Privileged — — — — — — — — — — — — — — — — T Bit — — — — — — — — — — — — — — — — New — — — — — — — — — — — — — — — — @(disp*,Rm),R0 @(disp*,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn R0,@(disp*,GBR) R0,@(disp*,GBR) R0,@(disp*,GBR) @(disp*,GBR),R0 @(disp*,GBR),R0 @(disp*,GBR),R0 @(disp*,PC),R0 MOVCO.L R0,@Rn 0000nnnn01110011  LDST New MOVLI.L @Rm,R0 0000mmmm01100011 1 → LDST (Rm) → R0 When interrupt/exception occurred 0 → LDST (Rm) → R0 Load non-boundary alignment data (Rm) → R0, Rm + 4 → Rm Load non-boundary alignment data 0100mmmm10101001   New MOVUA.L @Rm,R0   New MOVUA.L @Rm+,R0 0100mmmm11101001   New Rev. 1.00 Nov. 22, 2007 Page 60 of 1692 REJ09B0360-0100 Section 3 Instruction Set Instruction MOVT SWAP.B SWAP.W XTRCT Rn Rm,Rn Rm,Rn Rm,Rn Operation T → Rn Rm → swap lower 2 bytes → Rn Rm → swap upper/lower words → Rn Instruction Code Privileged T Bit — — — — New — — — — 0000nnnn00101001 — 0110nnnnmmmm1000 — 0110nnnnmmmm1001 — Rm:Rn middle 32 bits → Rn 0010nnnnmmmm1101 — Note: * The assembler of Renesas uses the value after scaling (×1, ×2, or ×4) as the displacement (disp). Table 3.5 Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS Arithmetic Operation Instructions Operation Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rn + Rm → Rn Rn + imm → Rn Rn + Rm + T → Rn, carry → T Rn + Rm → Rn, overflow → T When R0 = imm, 1 → T Otherwise, 0 → T When Rn = Rm, 1 → T Otherwise, 0 → T When Rn ≥ Rm (unsigned), 1→T Otherwise, 0 → T When Rn ≥ Rm (signed), 1→T Otherwise, 0 → T When Rn > Rm (unsigned), 1→T Otherwise, 0 → T When Rn > Rm (signed), 1→T Otherwise, 0 → T When Rn ≥ 0, 1 → T Otherwise, 0 → T When Rn > 0, 1 → T Otherwise, 0 → T Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 Privileged T Bit — — — — — — — — — Carry Overflow New — — — — Comparison — result Comparison — result Comparison — result Comparison — result Comparison — result Comparison — result Comparison — result Comparison — result CMP/GE Rm,Rn 0011nnnnmmmm0011 — CMP/HI Rm,Rn 0011nnnnmmmm0110 — CMP/GT Rm,Rn 0011nnnnmmmm0111 — CMP/PZ CMP/PL Rn Rn 0100nnnn00010001 0100nnnn00010101 — — Rev. 1.00 Nov. 22, 2007 Page 61 of 1692 REJ09B0360-0100 Section 3 Instruction Set Instruction CMP/STR Rm,Rn Operation Instruction Code Privileged T Bit — New When any bytes are equal, 0010nnnnmmmm1100 1→T Otherwise, 0 → T 1-step division (Rn ÷ Rm) MSB of Rn → Q, MSB of Rm → M, M^Q → T 0 → M/Q/T 0011nnnnmmmm0100 0010nnnnmmmm0111 Comparison — result Calculation result Calculation result 0 — — — DIV1 DIV0S Rm,Rn Rm,Rn — — DIV0U DMULS.L Rm,Rn 0000000000011001 0011nnnnmmmm1101 — — — — Signed, Rn × Rm → MAC, 32 × 32 → 64 bits Unsigned, Rn × Rm → MAC, 32 × 32 → 64 bits Rn – 1 → Rn; when Rn = 0, 1 → T When Rn ≠ 0, 0 → T Rm sign-extended from byte → Rn Rm sign-extended from word → Rn Rm zero-extended from byte → Rn Rm zero-extended from word → Rn DMULU.L Rm,Rn 0011nnnnmmmm0101 — — — DT Rn 0100nnnn00010000 — Comparison — result — — — — — — — — — — EXTS.B EXTS.W EXTU.B EXTU.W MAC.L Rm,Rn Rm,Rn Rm,Rn Rm,Rn 0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111 — — — — — @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → MAC Rn + 4 → Rn, Rm + 4 → Rm 32 × 32 + 64 → 64 bits @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → MAC Rn + 2 → Rn, Rm + 2 → Rm 16 × 16 + 64 → 64 bits Rm,Rn Rm,Rn Rn × Rm → MACL 32 × 32 → 32 bits Signed, Rn × Rm → MACL 16 × 16 → 32 bits MAC.W 0100nnnnmmmm1111 — — — MUL.L MULS.W 0000nnnnmmmm0111 0010nnnnmmmm1111 — — — — — — Rev. 1.00 Nov. 22, 2007 Page 62 of 1692 REJ09B0360-0100 Section 3 Instruction Set Instruction MULU.W Rm,Rn Operation Unsigned, Rn × Rm → MACL 16 × 16 → 32 bits 0 – Rm → Rn 0 – Rm – T → Rn, borrow → T Rn – Rm → Rn Rn – Rm – T → Rn, borrow → T Rn – Rm → Rn, underflow → T Instruction Code 0010nnnnmmmm1110 Privileged T Bit — — New — NEG NEGC SUB SUBC SUBV Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 — — — — — — Borrow — Borrow Underflow — — — — — Table 3.6 Instruction AND AND Logic Operation Instructions Operation Rn & Rm → Rn R0 & imm → R0 (R0 + GBR) & imm → (R0 + GBR) ~Rm → Rn Rn | Rm → Rn R0 | imm → R0 (R0 + GBR) | imm → (R0 + GBR) When (Rn) = 0, 1 → T Otherwise, 0 → T In both cases, 1 → MSB of (Rn) Rn & Rm; when result = 0, 1 → T Otherwise, 0 → T R0 & imm; when result = 0, 1 → T Otherwise, 0 → T (R0 + GBR) & imm; when result = 0, 1 → T Otherwise, 0 → T Rn ∧ Rm → Rn Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 Privileged T Bit — — — — — — — — — — — — — — — Test result New — — — — — — — — Rm,Rn #imm,R0 AND.B #imm, @(R0,GBR) NOT OR OR OR.B Rm,Rn Rm,Rn #imm,R0 #imm, @(R0,GBR) TAS.B @Rn TST Rm,Rn 0010nnnnmmmm1000 — Test result Test result Test result — — TST #imm,R0 11001000iiiiiiii — — TST.B #imm, @(R0,GBR) 11001100iiiiiiii — — XOR Rm,Rn 0010nnnnmmmm1010 — — Rev. 1.00 Nov. 22, 2007 Page 63 of 1692 REJ09B0360-0100 Section 3 Instruction Set Instruction XOR #imm,R0 Operation R0 ∧ imm → R0 (R0 + GBR) ∧ imm → (R0 + GBR) Instruction Code 11001010iiiiiiii 11001110iiiiiiii Privileged T Bit — — — — New — — XOR.B #imm, @(R0,GBR) Table 3.7 Instruction ROTL ROTR ROTCL ROTCR SHAD Rn Rn Rn Rn Shift Instructions Operation T ← Rn ← MSB LSB → Rn → T T ← Rn ← T T → Rn → T When Rm ≥ 0, Rn > Rm → [MSB → Rn] T ← Rn ← 0 MSB → Rn → T When Rm ≥ 0, Rn > Rm → [0 → Rn] T ← Rn ← 0 0 → Rn → T Rn > 2 → Rn Rn > 8 → Rn Rn > 16 → Rn Instruction Code Privileged T Bit MSB LSB MSB LSB — New — — — — — 0100nnnn00000100 — 0100nnnn00000101 — 0100nnnn00100100 — 0100nnnn00100101 — 0100nnnnmmmm1100 — Rm,Rn SHAL SHAR SHLD Rn Rn Rm,Rn 0100nnnn00100000 — 0100nnnn00100001 — 0100nnnnmmmm1101 — MSB LSB — — — — SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16 Rn Rn Rn Rn Rn Rn Rn Rn 0100nnnn00000000 — 0100nnnn00000001 — 0100nnnn00001000 — 0100nnnn00001001 — 0100nnnn00011000 — 0100nnnn00011001 — 0100nnnn00101000 — 0100nnnn00101001 — MSB LSB — — — — — — — — — — — — — — Rev. 1.00 Nov. 22, 2007 Page 64 of 1692 REJ09B0360-0100 Section 3 Instruction Set Table 3.8 Instruction BF Branch Instructions Operation label When T = 0, disp × 2 + PC + 4 → PC When T = 1, nop Delayed branch; when T = 0, disp × 2 + PC + 4 → PC When T = 1, nop When T = 1, disp × 2 + PC + 4 → PC When T = 0, nop Delayed branch; when T = 1, disp × 2 + PC + 4 → PC When T = 0, nop Delayed branch, disp × 2 + P C + 4 → PC Instruction Code Privileged T Bit — New — 10001011dddddddd — BF/S label 10001111dddddddd — — — BT label 10001001dddddddd — — — BT/S label 10001101dddddddd — — — BRA BRAF BSR BSRF JMP JSR RTS label Rn label Rn @Rn @Rn 1010dddddddddddd — — — — — — — — — — — — — — — Delayed branch, Rn + PC + 4 → 0000nnnn00100011 — PC Delayed branch, PC + 4 → PR, 1011dddddddddddd — disp × 2 + PC + 4 → PC Delayed branch, PC + 4 → PR, 0000nnnn00000011 — Rn + PC + 4 → PC Delayed branch, Rn → PC 0100nnnn00101011 — Delayed branch, PC + 4 → PR, 0100nnnn00001011 — Rn → PC Delayed branch, PR → PC 0000000000001011 — Table 3.9 Instruction CLRMAC CLRS CLRT ICBI LDC LDC LDC LDC System Control Instructions Operation 0 → MACH, MACL 0→S 0→T @Rn Rm,SR Rm,GBR Rm,VBR Rm,SGR Instruction Code 0000000000101000 0000000001001000 0000000000001000 Privileged T Bit — — —  — — 0  New — — — New — — — — Invalidates instruction cache block 0000nnnn11100011 Rm → SR Rm → GBR Rm → VBR Rm → SGR 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00111010 Privileged LSB — — Privileged — Privileged — Rev. 1.00 Nov. 22, 2007 Page 65 of 1692 REJ09B0360-0100 Section 3 Instruction Set Instruction LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L LDTLB MOVCA.L NOP OCBI OCBP OCBWB PREF PREFI RTE @Rn @Rn @Rn @Rn @Rn R0,@Rn Rm,SSR Rm,SPC Rm,DBR Operation Rm → SSR Rm → SPC Rm → DBR Instruction Code 0100mmmm00111110 0100mmmm01001110 0100mmmm11111010 Privileged Privileged Privileged Privileged Privileged Privileged — Privileged Privileged Privileged Privileged Privileged Privileged — — — — — — Privileged — — — — — —  Privileged T Bit — — — — LSB — — — — — — — — — — — — — — — — — — — —  — New — — — — — — — — — — — — — — — — — — — — — — — — — New — Rm,Rn_BANK Rm → Rn_BANK (n = 0 to 7) 0100mmmm1nnn1110 @Rm+,SR @Rm+,GBR @Rm+,VBR @Rm+,SGR @Rm+,SSR @Rm+,SPC @Rm+,DBR @Rm+,Rn_ BANK Rm,MACH Rm,MACL Rm,PR (Rm) → SR, Rm + 4 → R m 0100mmmm00000111 (Rm) → GBR, Rm + 4 → R m 0100mmmm00010111 (Rm) → VBR, Rm + 4 → R m 0100mmmm00100111 (Rm) → SGR, Rm + 4 → R m 0100mmmm00110110 (Rm) → SSR, Rm + 4 → R m 0100mmmm00110111 (Rm) → SPC, Rm + 4 → R m 0100mmmm01000111 (Rm) → DBR, Rm + 4 → R m 0100mmmm11110110 (Rm) → Rn_BANK, Rm + 4 → R m Rm → MACH Rm → MACL Rm → PR 0100mmmm1nnn0111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 @Rm+,MACH (Rm) → MACH, Rm + 4 → Rm @Rm+,MACL @Rm+,PR (Rm) → MACL, Rm + 4 → Rm (Rm) → PR, Rm + 4 → R m R0 → (Rn) (without fetching cache block) No operation Invalidates operand cache block Writes back and invalidates operand cache block Writes back operand cache block (Rn) → operand cache Reads 32-byte instruction block into instruction cache Delayed branch, SSR/SPC → SR/PC PTEH/PTEL (/PTEA) → TLB 0000000000111000 0000nnnn11000011 0000000000001001 0000nnnn10010011 0000nnnn10100011 0000nnnn10110011 0000nnnn10000011 0000nnnn11010011 0000000000101011 Rev. 1.00 Nov. 22, 2007 Page 66 of 1692 REJ09B0360-0100 Section 3 Instruction Set Instruction SETS SETT SLEEP STC STC STC STC STC STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L SR,Rn GBR,Rn VBR,Rn SSR,Rn SPC,Rn SGR,Rn DBR,Rn Operation 1→S 1→T Sleep or standby SR → R n GBR → R n VBR → R n SSR → R n SPC → R n SGR → Rn DBR → R n Instruction Code 0000000001011000 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn00110010 0000nnnn01000010 0000nnnn00111010 0000nnnn11111010 0000nnnn1mmm0010 Privileged — — Privileged Privileged — Privileged Privileged Privileged Privileged Privileged Privileged Privileged — Privileged Privileged Privileged Privileged Privileged Privileged T Bit — 1 — — — — — — — — — — — — — — — — — New — — — — — — — — — — — — — — — — — — — Rm_BANK,Rn Rm_BANK → Rn (m = 0 to 7) SR,@-Rn GBR,@-Rn VBR,@-Rn SSR,@-Rn SPC,@-Rn SGR,@-Rn DBR,@-Rn Rn – 4 → Rn, SR → (Rn) 0100nnnn00000011 Rn – 4 → Rn, GBR → (Rn) Rn – 4 → Rn, VBR → (Rn) Rn – 4 → Rn, SSR → (Rn) Rn – 4 → Rn, SPC → (Rn) Rn – 4 → Rn, SGR → (Rn) Rn – 4 → Rn, DBR → (Rn) 0100nnnn00010011 0100nnnn00100011 0100nnnn00110011 0100nnnn01000011 0100nnnn00110010 0100nnnn11110010 0100nnnn1mmm0011 Rm_BANK,@- Rn – 4 → Rn, Rn Rm_BANK → (Rn) (m = 0 to 7) MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn MACH → R n MACL → R n PR → R n Rn – 4 → Rn, MACH → (Rn) Rn – 4 → Rn, MACL → (Rn) STS STS STS STS.L STS.L STS.L 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 — — — — — — — — — — — — — — — — — — Rn – 4 → Rn, PR → (Rn) 0100nnnn00100010 Rev. 1.00 Nov. 22, 2007 Page 67 of 1692 REJ09B0360-0100 Section 3 Instruction Set Instruction SYNCO Operation Data accesses invoked by the following instructions are not executed until execution of data accesses which precede this instruction has been completed. #imm Instruction Code 0000000010101011 Privileged  T Bit  New New TRAPA PC + 2 → SPC, 11000011iiiiiiii SR → SSR, R15 → SGR, 1 → SR.MD/BL/RB, #imm H'7FFF FFFF: H'7FFF FFFF When TX, TY, W < −H'7FFF FFFF: −H'7FFF FFFF (32-bit fixed-point) WC Z saturation value MIN ≤ WC ≤ H'7FFF When WC < Z saturation value MIN: Z FFFF saturation value MIN (32-bit fixed-point) (32-bit fixed-point) Rev. 1.00 Nov. 22, 2007 Page 1075 of 1692 REJ09B0360-0100 Section 23 G2D Vertex Coordinates after Operation Range TX/WC, TY/WC and TX/WC + offset X, TY/WC + offset Y −H'7FFF ≤ TX/WC, TY/WC ≤ H'7FFF −H'7FFF ≤ TX/WC + offset X, TY/WC + offset Y ≤ H'7FFF (16-bit integer) Saturation Processing When TX/WC, TY/WC > H'7FFF: H'7FFF When TX/WC, TY/WC < −H'7FFF: −H'7FFF When TX/WC + offset X, TY/WC + offset Y > H'7FFF: H'7FFF When TX/WC + offset X, TY/WC + offset Y < −H'7FFF: −H'7FFF (16-bit integer) X', Y' Output vertex −H'7FFF ≤ X', Y' ≤ H'7FFF (16-bit integer) −H'8000 ≤ Output vertex ≤ H'7FFF (16-bit integer)   (6) Bold Line Drawing A bold line can be drawn by setting a value greater than 0 as line width W in a LINE type or RLINE type command. The bold line coordinates a, b, c, and d are obtained from the starting and final coordinate points and line width W, and the bold line drawn. W is set in the 6-bit integer part. When 0 is set in W, a line of line width 1 is drawn. The connection drawing mask bit (COM) in the rendering control register (RCLR) is used to select whether the linkage parts of bold lines are drawn or not. When the starting and final coordinate points of a line segment match in bold line drawing, nothing is drawn. In bold line drawing, specify the starting and final coordinate points in the range of -215 + (W + 2) ≤ x, y ≤ 215 – 1 – (W + 2) in the logical space. Rev. 1.00 Nov. 22, 2007 Page 1076 of 1692 REJ09B0360-0100 Section 23 G2D (0, 0) c (DX2, DY2) e X f d a W (DX1, DY1) b g (DX3, DY3) h Y (7) Antialiasing Antialiasing which reduces alias can be used in a LINE type or RLINE type command. Setting the rendering attribute antialias enable bit (AA) to 1 performs antialiasing. When antialiasing is specified, specify the starting and final coordinate points in the range of -215 + 1 ≤ x, y ≤ 215 – 2 in the logical space. In bold line drawing, specify the starting and final coordinate points in the range of -215 + 1 + (W + 2) ≤ x, y ≤ 215 – 2 – (W + 2). • For a dashed line, antialiasing is not performed for the gaps in the dashed line. • When the starting and final coordinate points of a line segment match in the LINEA, LINEB, LINEC, RLINEA, RLINEB, or RLINEC command, a single dot is drawn for a 1-bit-wide line (W = 0) without antialiasing and nothing is drawn for bold line drawing. • When the starting and final coordinate points of a line segment match in the LINED, or RLINED command, nothing is drawn. • Antialiasing is not performed for horizontal, vertical, and 45-degree diagonal line segments. Rev. 1.00 Nov. 22, 2007 Page 1077 of 1692 REJ09B0360-0100 Section 23 G2D Figure 23.2 Example of Antialias Specification 23.1.3 Coordinate Systems The G2D has four 2-dimensional coordinate systems (screen coordinates, rendering coordinates, 2-dimensional source coordinates, and work coordinates), and one 1-dimensional coordinate system (1-dimensional source coordinates). Screen coordinates are the display control coordinates. Screen coordinate X corresponds to the horizontal dimension of the display screen and Y to the vertical dimension. The origin is the topleft corner in the display screen. The screen coordinate positive directions are right for the X-axis and down for the Y-axis. Either 16 bits (16 bits/pixel) or 8 bits (8 bits/pixel) can be selected as the data width of one screen coordinate. Rendering coordinates are drawing control coordinates. Rendering coordinates are shifted horizontally and vertically with respect to screen coordinates by the offset amounts specified in drawing commands. According to the drawing commands, the G2D performs drawing operations using these coordinates. Either 16 bits (16 bits/pixel) or 8 bits (8 bits/pixel) can be selected as the data width of one rendering coordinate. 2-dimensional source coordinates are drawing control coordinates. When a drawing command is executed with SS = 1, these are the source data (rectangle) coordinates specified by the drawing command. Either 16 bits (16 bits/pixel) or 8 bits (8 bits/pixel) can be selected as the data width of one 2-dimensional source coordinate. 1-dimensional source coordinates are drawing control coordinates. When a drawing command is executed with SS = 0, these are the source data (1-dimensional) coordinates specified by the drawing command. 1 bit (1 bit/pixel), 16 bits (16 bits/pixel), or 8 bits (8 bits/pixel) can be selected as the data width of one 1-dimensional source coordinate. For one 1-dimensional source, one physical address (top-left) and the horizontal width and vertical height of the 1-dimensional source are specified. Rev. 1.00 Nov. 22, 2007 Page 1078 of 1692 REJ09B0360-0100 Section 23 G2D Work coordinates are drawing control coordinates that correspond one-to-one with the rendering coordinates. When a drawing command is executed, these are the work coordinates specified by the drawing command. The data width of one work coordinate is 1 bit. The maximum values of the screen coordinates are X = 4095, Y = 4095. X (max.: 4096) (0, 0) X (min.: 16) Y (max.: 4096) The stride of the screen coordinates is set in the destination stride register (DSTRR) (the register setting is made in pixel units). Figure 23.3 Screen Coordinates Rev. 1.00 Nov. 22, 2007 Page 1079 of 1692 REJ09B0360-0100 Section 23 G2D -32768 When offset values = 0 Screen coordinate origin Rendering coordinate origin -32768 (0, 0) 32767 X 32767 Rendering coordinates Y -32768 When offset values = (a, b) The size of the logical space from the rendering coordinate origin in accordance with the offset values never exceeds -32767. X Screen coordinate origin (0, 0) -32768 Offset 32767 - a (a, b) Rendering coordinate origin 32767 - b Y Rendering coordinates -32768 + b When offset values = (-a, -b) The size of the logical space from the rendering coordinate origin in accordance with the offset values never exceeds -32768. X -32768 + a Rendering coordinate origin (-a, -b) 32767 Offset (0, 0) Screen coordinate origin 32767 Y Rendering coordinates Figure 23.4 Rendering Coordinates Rev. 1.00 Nov. 22, 2007 Page 1080 of 1692 REJ09B0360-0100 Section 23 G2D -32768 Physical coordinate origin Work coordinate origin -32768 (0, 0) 32767 X When offset values = 0 32767 Work coordinates Y -32768 + b When offset values = (-a, -b) Work coordinate origin -32768 + a (-a, -b) Offset 32767 X The size of the logical space from the work coordinate origin in accordance with the offset values never exceeds -32768. (0, 0) Physical coordinate origin 32767 Y Work coordinates -32768 When offset values = (a, b) The size of the logical space from the work coordinate origin in accordance with the offset values never exceeds 32767. X Physical coordinate origin (0, 0) -32768 Offset 32767 - a (a, b) Work coordinate origin 32767 - b Y Work coordinates Figure 23.5 Work Coordinates Rev. 1.00 Nov. 22, 2007 Page 1081 of 1692 REJ09B0360-0100 Section 23 G2D X (max.: 4096) (0, 0) X (min.: 16) Y (max.: 4096) The stride of the 2-dimensional source coordinates is set in the source stride register (SSTRR) (the register setting is made in pixel units). Figure 23.6 2-Dimensional Source Coordinates (SS = 1) X (max.: 4088) (0, 0) X (min.: 8) Y (max.: 4096) 1-dimensional source coordinates (one coordinate system per one 1-dimensional source) Figure 23.7 1-Dimensional Source Coordinates (SS = 0) Rev. 1.00 Nov. 22, 2007 Page 1082 of 1692 REJ09B0360-0100 Section 23 G2D 23.1.4 Data Formats • 1-bit/pixel data Bit Pixel number 63 63 56 55 56 55 48 47 48 47 40 39 40 39 32 31 32 31 24 23 24 23 16 15 16 15 87 87 0 0 The pixel number is 0 at the left side of the screen, and increments as it shifts right. • 8-bit/pixel data Bit Pixel number 63 7 56 55 6 48 47 5 40 39 4 32 31 3 24 23 2 16 15 1 87 0 0 The pixel number is 0 at the left side of the screen, and increments as it shifts right. • 16-bit/pixel data (RGB) Bit Pixel number 63 R3 59 58 G3 53 52 B3 48 47 R2 43 42 G2 37 36 B2 32 31 R1 27 26 G1 21 20 B1 16 15 R0 11 10 G0 5 4 B0 0 3 2 1 0 The pixel number is 0 at the left side of the screen, and increments as it shifts right. • 16-bit/pixel data (ARGB) Bit Pixel number 63 62 A3 R3 58 57 G3 53 52 B3 48 47 46 A2 R2 42 41 G2 37 36 B2 32 31 30 A1 R1 26 25 G1 21 20 B1 16 15 14 A0 R0 10 9 G0 5 4 B0 0 3 2 1 0 The pixel number is 0 at the left side of the screen, and increments as it shifts right. • 32-bit data (display list) Bit 63 Adress 8n+4 32 31 Adress 8n 0 Rev. 1.00 Nov. 22, 2007 Page 1083 of 1692 REJ09B0360-0100 Section 23 G2D 23.1.5 (1) Rendering Attributes Source Transparency Specification (STRANS) When referencing source data, the STRANS bit can be used to select transparency or nontransparency on an individual drawing command basis. If transparency is selected, the source color becomes transparent at register value = source color when the source transparent color polarity bit (STP) in the rendering control register (RCLR) is 0, and the source color becomes transparent at register value ≠ source color when the STP bit is 1, and the pixels are not drawn in either case. The source transparency specification can be used with the POLYGON4A, POLYGON4B, LINEA, LINEB, RLINEA, RLINEB, BITBLTA, and BITBLTB commands. The STRANS bit should be cleared to 0 in other commands. When the source pixel format is ARGB, the A value is not compared. Note that when the STRANS bit is set to 1, the source data is always read in the BITBLTA or BITBLTB command, regardless of the ROP code. (2) Destination Transparency Specification (DTRANS) When referencing destination data, the DTRANS bit can be used to select transparency or nontransparency on an individual drawing command basis. If transparency is selected, the destination color becomes transparent at register value = destination color when the destination transparent color polarity bit (DTP) in the rendering control register (RCLR) is 0, and the destination color becomes transparent at register value ≠ destination color when the DTP bit is 1, and the pixels are not drawn in either case. The destination transparency specification can be used with the BITBLTA, BITBLTB, and BITBLTC commands. The DTRANS bit should be cleared to 0 in other commands. When the destination pixel format is ARGB, the A value is not compared. Note that when the DTRANS bit is set to 1, the destination data is always read, regardless of the ROP code. (3) Source Style Specification (STYLE) The STYLE bit can be used to select, on an individual drawing command basis, whether to enlarge or reduce the source data or repeatedly reference it. If no style specification is made, the source data is enlarged or reduced in proportion to the size of the rendering area. When a style specification is made, the source data is referenced repeatedly in proportion to the size of the rendering area. This attribute is therefore used when drawing repeated patterns such as hatch patterns. The source style specification can be used with the POLYGON4A, POLYGON4B, LINEA, LINEB, RLINEA, and RLINEB commands. The STYLE bit should be cleared to 0 in other commands. The STYLE bit must be set to 1 when BLKE = 1 in the POLYGON4A, POLYGON4B, LINEA, LINEB, RLINEA, or RLINEB command. Rev. 1.00 Nov. 22, 2007 Page 1084 of 1692 REJ09B0360-0100 Section 23 G2D In the LINEA, LINEB, RLINEA, and RLINEB commands, the source data is repeatedly referenced in only the X direction of the source data. The source data is enlarged or reduced in proportion to the line width in the Y direction of the source data. No style specification (STYLE = 0) X Y Enlarged by a factor of 2 Style specification used (STYLE = 1) X Y Referenced twice Source data Drawing data Figure 23.8 Example of Source Style Specification Rev. 1.00 Nov. 22, 2007 Page 1085 of 1692 REJ09B0360-0100 Section 23 G2D (4) Clipping Specification (CLIP) The G2D can perform clipping area management. There are three kinds of clipping areas: system clipping area, user clipping area, and relative user clipping area. The system clipping area has a fixed drawing range. The system clipping area is always valid, regardless of attribute specifications. A user clipping area can be designated as desired within the system clipping area. Whether or not clipping is performed in that area can be selected on an individual command basis with the rendering attribute CLIP bit. The boundary is drawn. The local offset values specified by the LCOFS or RLCOFS command are not added. When setting a user clipping area, the following ranges must be satisfied: XMIN < XMAX, YMIN < YMAX. Clipping is set with screen coordinates. Since the clipping area is undefined after the power is turned on, set the clipping area by the WPR command at the top of the display list that is executed first. XMAX must be set to a value less than the value set in the destination stride register (DSTRR). CLIP bit = 1 CLIP bit = 0 (0, 0) (UXMIN, UYMIN) Designated user clipping area (UXMAX, UYMAX) System clipping area (SXMAX, SYMAX) Figure 23.9 Example of Clipping Specification Rev. 1.00 Nov. 22, 2007 Page 1086 of 1692 REJ09B0360-0100 Section 23 G2D (5) Relative Clipping Specification (RCLIP) The G2D can perform clipping area management. There are three kinds of clipping areas: system clipping area, user clipping area, and relative user clipping area. The system clipping area has a fixed drawing range. The system clipping area is always valid, regardless of attribute specifications. A relative user clipping area can be designated as desired within the system clipping area at a relative setting with respect to the local offset. Whether or not clipping is performed in that area can be selected on an individual command basis with the rendering attribute RCLIP bit. The boundary is drawn. The local offset values specified by the LCOFS or RLCOFS command are added. When setting a relative user clipping area, the following ranges must be satisfied: XMIN < XMAX, YMIN < YMAX. Clipping is set with screen coordinates. Since the clipping area is undefined after the power is turned on, set the clipping area by the WPR command at the top of the display list that is executed first. XMAX must be set to a value less than the value set in the destination stride register (DSTRR). If both the RCLIP and CLIP bits are set to 1 simultaneously, the region where the two clipping areas overlap is drawn. (0, 0) Local offset (XO, YO) System clipping area Designated user clipping area (XO + RUXMIN, YO + RUYMIN) Designated relative user clipping area Drawing area (XO + RUXMAX, YO + RUYMAX) Figure 23.10 Example of Relative User Clipping Specification Rev. 1.00 Nov. 22, 2007 Page 1087 of 1692 REJ09B0360-0100 Section 23 G2D When a relative user clipping area ((XO + RUXMIN, YO + RUYMIN) - (XO + RUXMAX, YO + RUYMAX)) intersects with the system clipping area, saturation processing is performed as follows: XO + RUXMIN < 0 → XO + RUXMIN = 0 XO + RUXMAX > SXMAX → XO + RUXMAX = SXMAX YO + RUYMIN < 0 → YO + RUYMIN = 0 YO + RUYMAX > SYMAX → YO + RUYMAX = SYMAX Note: Set the local offset values and relative user clipping area without exceeding the following ranges: -4096 ≤ XO + RUXMIN ≤ 4095 -4096 ≤ YO + RUYMIN ≤ 4095 0 ≤ XO + RUXMAX ≤ 8191 0 ≤ YO + RUYMAX ≤ 8191 When RCLIP = 1 and the relative user clipping area satisfies one of the following conditions, the relative user clipping area is disabled internally by the G2D (same operation as RCLIP = 0). 4095 < XO + RUXMIN 4095 < YO + RUYMIN XO + RUXMAX < 0 YO + RUYMAX < 0 Rev. 1.00 Nov. 22, 2007 Page 1088 of 1692 REJ09B0360-0100 Section 23 G2D (6) Net Drawing Specification (NET) The NET bit can be used to select, on an individual drawing command basis, whether or not net drawing is to be performed. Net drawing is a function for drawing only pixels at coordinates for which the condition "rendering coordinates X + Y = EOS (0: even number, 1: odd number)" is true. For example, if EOS = 0, drawing is only performed on the pixels at coordinates Y = 0, X = 0, 2, 4, 6, 8… and Y = 1, X = 1, 3, 5, 7, 9…. This function enables the drawn figure and ground to be mutually semi-composed. The net drawing specification can be used with the POLYGON4 type, LINEA, LINEB, LINEC, RLINEA, RLINEB, and RLINEC commands. The NET bit should be cleared to 0 in other commands. The NET bit cannot be used together with the antialias enable bit (AA). (7) Even/Odd Select Specification (EOS) Even pixels are selected when EOS = 0, and odd pixels when EOS = 1. The even/odd select specification is used together with the net drawing specification (NET). With the LINEWC and RLINEWC commands, drawing is performed at the work coordinates with 0 when EOS = 0, and with 1 when EOS = 1. (8) Work Specification (WORK) When drawing is performed at rendering coordinates with the POLYGON4 type or BITBLT type command, the WORK bit can be used to select, on an individual drawing command basis, whether or not binary work data is to be referenced. When binary work data referencing is selected, drawing is performed if the work data for the pixel corresponding to the rendering coordinates is 1, but not if the work data is 0. The same shape as that drawn at work coordinates can thus be drawn at rendering coordinates. Drawing at work coordinates can be performed either by means of the FTRAPC, RFTRAPC, LINEWC, RLINEWC, or CLRWC command or else by the CPU. Ensure that memory drawing access by a command and memory drawing access by the CPU are not performed simultaneously. The work specification can be used with the POLYGON4 type, and BITBLT type, commands. The WORK bit should be cleared to 0 in the other commands. Rev. 1.00 Nov. 22, 2007 Page 1089 of 1692 REJ09B0360-0100 Section 23 G2D (9) Source Address Specification (SS) The SS bit is used to select whether the source is to be referenced at a 2-dimensional source area address or at the address indicated by the Base Address parameter in the display list. The source address specification can be used with the POLYGON4A, POLYGON4B, BITBLTA, and BITBLTB commands. The SS bit should be clear to 0 in the other commands. If the offset values are set, the source is referenced from (TXOFS, TYOFS). SS = 1 Source stride (SSTRR) 2-dimensional source area start address (SSAR) SS = 0 (TXS, TYS) Base Address (TXOFS, TYOFS) (TXOFS, TYOFS) Height Height Width Height: POLYGON4 type command (TDY) or BITBLT type command (TH + BH + 1) Width: POLYGON4 type command (TDX) or BITBLT type command (LW + RW + 1) The source start address is set by the 2-dimensional source area start address register (SSAR). The source stride is set by the source stride register (SSTRR). Width = source stride Height: POLYGON4 type command (TDY) or BITBLT type command (TH + BH + 1) Width: POLYGON4 type command (TDX) or BITBLT type command (LW + RW + 1) The source start address is the address indicated by the Base Address parameter in the display list. The source stride is the Width parameter in the display list. Figure 23.11 Example of Source Address Specification Note: When SS = 1, settings must be made within the ranges of 0 ≤ TXS ≤ SSTRR – Width (TDX, LW + RW + 1), 0 ≤ TYS ≤ 4096 – Height (TDY, TH + BH + 1). Rev. 1.00 Nov. 22, 2007 Page 1090 of 1692 REJ09B0360-0100 Section 23 G2D (10) Source Coordinate Relative Address Specification (REL) Setting the REL bit to 1 in the POLYGON4A, POLYGON4B, BITBLTA, BITBLTB, LINEA, LINEB, RLINEA, RLINEB, JUMP, and GOSUB commands enables source referencing and branching to be performed at an address relative to (before or after) the command code. Clear the SS bit to 0 in the POLYGON4A or BITBLTA command; correct operation is not guaranteed when the SS bit is set to 1. The command code address is the origin of the relative address (longword address). Note: With the POLYGON4A, POLYGON4B, BITBLTA, BITBLTB, LINEA, LINEB, RLINEA, and RLINEB commands, adding the address (longword: 32-bit units) where the command code is located to the source start relative address (longword: 32-bit units) must result in a quad word address (64-bit units). (11) Edge Drawing (EDG) With the FTRAP and RFTRAP commands, setting the EDG bit to 1 enables edge lines to be drawn after completion of trapezoid painting to the work area. Whether edge line drawing is performed with 0 or with 1 is specified by the EOS bit. (12) Color Offset (COOF) The color offset specification can be used with the POLYGON4 type, LINEA, LINEB, LINEC, RLINEA, RLINEB, RLINEC, BITBLT type, and AAFA commands. In 16-bit/pixel drawing, if the rendering attribute COOF bit is set to 1, the result of adding the value in COFSR to the value of the source data (color expanded data for a binary source and the specified color for the monochrome specification) is drawn. In 8-bit/pixel drawing, the COOF bit should be cleared to 0. When the source pixel format is ARGB, the A value is not used in operation. (13) Source Direction X, Y (SRCDIRX, SRCDIRY) The source direction X, Y specification can be used with the BITBLTA and BITBLTB commands. The directions in which to scan the source data are selected. (TXS, TYS) or the Base Address specifies the top-left corner of the rectangle source, regardless of the source scan directions. Rev. 1.00 Nov. 22, 2007 Page 1091 of 1692 REJ09B0360-0100 Section 23 G2D X Y (TXS, TYS) or Base Address SRCDIRX = 0 SRCDIRY = 0 SRCDIRX = 1 SRCDIRY = 0 SRCDIRX = 0 SRCDIRY = 1 SRCDIRX = 1 SRCDIRY = 1 Source reference directions Figure 23.12 Example of Source Direction Specification (14) Destination Direction X, Y (DSTDIRX, DSTDIRY) The destination direction X, Y specification can be used with the BITBLTA, BITBLTB, and BITBLTC commands. The directions in which to draw the destination data are selected. X Y DRCDIRX = 0 DRCDIRY = 0 DRCDIRX = 1 DRCDIRY = 0 DRCDIRX = 0 DRCDIRY = 1 DRCDIRX = 1 DRCDIRY = 1 Destination drawing directions Figure 23.13 Example of Destination Direction Specification Rev. 1.00 Nov. 22, 2007 Page 1092 of 1692 REJ09B0360-0100 Section 23 G2D (15) Antialias Enable (AA) The antialias enable specification can be used with the LINE type and RLINE type commands to reduce alias. The antialias enable specification is enabled only in 16-bit/pixel drawing. For 8bit/pixel drawing, the AA bit should be cleared to 0. The AA bit should be set to 1 with the LINED and RLINED commands. The antialias enable specification cannot be used together with the net drawing specification (NET). (16) Alpha Blend Enable (αE) The alpha blend enable specification can be used with the POLYGON4 type and BITBLT type commands. The source data (color expanded data for a binary source and the specified color for the monochrome specification) and ground data are alpha blended and drawn. The alpha value is set in the alpha value register (ALPHR). The alpha blend enable specification is enabled only in 16-bit/pixel drawing. For 8-bit/pixel drawing, the αE bit should be cleared to 0. In the POLYGON4 type commands, the alpha blend enable specification is enabled only when BLKE = 1. The αE bit should be cleared to 0 when BLKE = 0. In the BITBLT type commands, the alpha blend enable specification is enabled only when the ROP code is H'CC (source copy). For other ROP codes, the αE bit should be cleared to 0. The A value in the ARGB format is not alpha blended. The A value is drawn according to the source A value use (SAU) and A value (AVALUE) bits in the rendering control register (RCLR). (17) Source Alpha Enable (SαE) The source alpha enable specification can be used with the POLYGON4A, and BITBLTA commands. The SαE bit is used together with the alpha blend enable bit (αE). When αE = 0, the SαE bit should be cleared to 0. When the source pixel format bit (SPF) is 1 (ARGB format), only the pixels whose source A value is 1 are alpha blended. Pixels whose source A value is 0 are not alpha blended and the source data is drawn as it is. The source alpha enable specification is enabled only when SPF = 1. The SαE bit should be cleared to 0 when SPF = 0. (18) Block Enable (BLKE) The block enable specification can be used with the POLYGON4 type commands. When BLKE = 1, the input vertex coordinates (DXn, DYn) are internally transformed to circumscribed rectangle coordinates (DX'n, DY'n) and four-vertex drawing performed. When coordinate transformation is to be performed, the transformed vertices are internally converted into a rectangle and drawn. This is effective for vertically pasting the pattern even after coordinate transformation. When BLKE = 1, the fixed drawing direction is from the upper-left corner to the lower-right corner (up-and-down and right-and-left directions cannot be reversed). Rev. 1.00 Nov. 22, 2007 Page 1093 of 1692 REJ09B0360-0100 Section 23 G2D When coordinate transformation is performed by the CLRWC command, the four vertices are internally obtained from the input left and right X coordinate values and upper and lower Y coordinate values, and the coordinates for these four vertices are transformed. The transformed four vertices are then internally converted into a circumscribed rectangle drawn. When coordinate transformation is performed by the FTRAPC or RFTRAPC command, the four vertices are internally obtained from the coordinate values for the circumscribed quadrangle of the input polygon, and the coordinates for these four vertices are transformed. The transformed four vertices are then internally converted into a circumscribed rectangle, the left edge obtained, and the polygon drawn. The BLKE bit should be set to 1 with the CLRWC, FTRAPC, and RFTRAPC commands. Destination BLKE = 0 (DX2, DY2) (DX1, DY1) BLKE = 1 (DX1', DY1') (DX2, DY2) (DX2', DY2') Multi-valued source A POLYGON4 type command performs four-vertex drawing while referencing the work coordinates. (DX1, DY1) (DX3, DY3) (DX3, DY3) (DX2, DY2) (DX4, DY4) (DX4', DY4') (DX4, DY4) (DX3', DY3') (DX1, DY1) (DX3, DY3) Input vertex coordinates are not transformed. Input vertex coordinates (DXn, DYn) are transformed to circumscribed rectangle coordinates (DX'n, DY'n). (DX4, DY4) Work coordinates Figure 23.14 Example of Block Enable Specification (19) Coordinate Transformation Enable (MTRE) The coordinate transformation enable specification can be used with all drawing commands. Setting the MTRE bit to 1 when the coordinate transformation enable bit (GTE) in the coordinate transformation control register (GTRCR) is 1 performs coordinate transformation for the input vertex. Rev. 1.00 Nov. 22, 2007 Page 1094 of 1692 REJ09B0360-0100 Section 23 G2D (20) Link Specification Enable (LINKE) The link specification enable specification can be used with the LINEC, LINED, RLINEC, RLINED, FTRAPC, RFTRAPC, and WPR commands. From the memory address specified by the LINK Address, the vertex coordinates are read with the LINEC, LINED, RLINEC, RLINED, FTRAPC, and RFTRAPC commands, and the register write data is read with the WPR command. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by the LINK Address. (21) Link Address Relative Specification (LREL) The link address relative specification can be used with the LINEC, LINED, RLINEC, RLINED, FTRAPC, RFTRAPC, and WPR commands. The LREL bit is used together with the link specification enable bit (LINKE). The LREL bit should be cleared to 0 when LINKE = 0. The link destination address is specified as a relative address. The command code address is the origin of the relative address. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by the LINK Address. (22) Clockwise (CLKW) The clockwise specification can be used with the LINED and RLINED commands. The CLKW bit is used to specify whether the order in giving the n vertices is clockwise or counterclockwise. The order is clockwise when CLKW = 1 and counterclockwise when CLKW = 0. (23) Raster Operation (ROP) The raster operation specification can be used with the BITBLT type commands. The ROP code is specified in the ROP field, which is a BITBLT command parameter. Rev. 1.00 Nov. 22, 2007 Page 1095 of 1692 REJ09B0360-0100 Section 23 G2D ROP Code H'00 H'11 H'22 H'33 H'44 H'55 H'66 H'77 H'88 H'99 H'AA H'BB H'CC H'DD H'EE H'FF Operation 0 ∼ ∼ ∼ (S | D) S&D S S & ∼D ∼ D S^D ∼ (S & D) S&D ∼ (S ^ D) D ∼ S|D S S | ∼D S|D 1 Set the ROP code to H'CC when alpha blending is enabled (αE = 1). Neither alpha blending nor raster operation is performed for the A value in the ARGB format. The A value is drawn according to the source A value use (SAU) and A value (AVALUE) bits in the rendering control register (RCLR). Rev. 1.00 Nov. 22, 2007 Page 1096 of 1692 REJ09B0360-0100 Section 23 G2D 23.2 23.2.1 (1) (a) Display List 4-Vertex Screen Drawing Commands POLYGON4A Function Performs any four-vertex drawing in the destination area while referencing a multi-valued (8- or 16-bit/pixel) source. (b) Command Format • SS = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1000_0010 0 0 0 Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) TXS (0 ≤ TXS ≤ 4088) TDX (8 ≤ TDX ≤ 4095) 0 0 0 Sign Draw Mode 0 0 0 0 0 0 0 0 0 TYS (0 ≤ TYS ≤ 4095) TDY (1 ≤ TDY ≤ 4095) TYOFS (0 ≤ TYOFS ≤ TDY – 1) DY1 (-32768 ≤ DY1 ≤ 32767) DY2 (-32768 ≤ DY2 ≤ 32767) DY3 (-32768 ≤ DY3 ≤ 32767) DY4 (-32768 ≤ DY4 ≤ 32767) 0 0 0 0 0 0 0 0 0 TXOFS (0 ≤ TXOFS ≤ TDX − 1) DX1 (-32768 ≤ DX1 ≤ 32767) DX2 (-32768 ≤ DX2 ≤ 32767) DX3 (-32768 ≤ DX3 ≤ 32767) DX4 (-32768 ≤ DX4 ≤ 32767) Sign Sign Sign Sign Sign Sign Note: 0 ≤ TXS ≤ SSTRR − TDX, 0 ≤ TYS ≤ 4096 − TDY (SSTRR: Source stride register setting) Rev. 1.00 Nov. 22, 2007 Page 1097 of 1692 REJ09B0360-0100 Section 23 G2D • SS = 0 and REL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1000_0010 0 0 0 Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Base Address (quad word address) Draw Mode 0 TDY (1 ≤ TDY ≤ 4095) TYOFS (0 ≤ TYOFS ≤ TDY – 1) DY1 (-32768 ≤ DY1 ≤ 32767) DY2 (-32768 ≤ DY2 ≤ 32767) DY3 (-32768 ≤ DY3 ≤ 32767) DY4 (-32768 ≤ DY4 ≤ 32767) 0 0 0 0 0 0 0 0 0 0 TDX (8 ≤ TDX ≤ 4088) 0 0 0 0 0 Sign 0 0 0 0 0 0 TXOFS (0 ≤ TXOFS ≤ TDX − 1) DX1 (-32768 ≤ DX1 ≤ 32767) DX2 (-32768 ≤ DX2 ≤ 32767) DX3 (-32768 ≤ DX3 ≤ 32767) DX4 (-32768 ≤ DX4 ≤ 32767) Sign Sign Sign Sign Sign Sign • SS = 0 and REL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1000_0010 Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Base Address (longword address) Draw Mode 0 TDY (1 ≤ TDY ≤ 4095) TYOFS (0 ≤ TYOFS ≤ TDY – 1) DY1 (-32768 ≤ DY1 ≤ 32767) DY2 (-32768 ≤ DY2 ≤ 32767) DY3 (-32768 ≤ DY3 ≤ 32767) DY4 (-32768 ≤ DY4 ≤ 32767) 0 0 0 Sign 0 0 0 0 0 0 TDX (8 ≤ TDX ≤ 4088) 0 0 0 0 0 Sign 0 0 0 0 0 0 TXOFS (0 ≤ TXOFS ≤ TDX − 1) DX1 (-32768 ≤ DX1 ≤ 32767) DX2 (-32768 ≤ DX2 ≤ 32767) DX3 (-32768 ≤ DX3 ≤ 32767) DX4 (-32768 ≤ DX4 ≤ 32767) Sign Sign Sign Sign Sign Sign Note: Adding the address (longword: 32-bit units) where the command code is located to the Base Address (longword: 32-bit units) must result in a quad word address (64-bit units). Rev. 1.00 Nov. 22, 2007 Page 1098 of 1692 REJ09B0360-0100 Section 23 G2D 1. Code B'10000010 2. Rendering Attributes Reference Data Multi-Valued Source O Binary Source Binary Work O (only WORK = 1) Drawing Destination Specified Color Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 RCLIP b11 STRANS b10 Fixed to 0 b9 WORK b8 SS b7 REL b6 b5 b4 NET b3 EOS b2 b1 b0 SαE MTRE Fixed STYLE BLKE COOF αE 3. Command Parameters TXS, TYS: Base Address: Source starting point. Write 0 to the unused bits. Source start absolute address (Quad word address. Write 0 to bits A31 to A29 and A2 to A0.) Source start relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. TDX, TDY: Source size. Write 0 to the unused bits. DXn, DYn (n = 1 to 4): Rendering coordinates (absolute coordinates). Negative numbers expressed as two's complement. TXOFS, TYOFS: Source offset. Write 0 to the unused bits. Rev. 1.00 Nov. 22, 2007 Page 1099 of 1692 REJ09B0360-0100 Section 23 G2D (c) Description Transfers multi-valued (8- or 16-bit/pixel) source data to any quadrilateral rendering coordinates. The source data is always scanned horizontally, but diagonal scanning may be used in the drawing, depending on the shape. In diagonally-scanned drawing, double-writing occurs to fill in gaps. When SS = 0, set a multiple of 8 pixels as the TDX value. When SS = 1, set 8 or more pixels as the TDX value. If the TDX setting is less than 8 pixels, multi-valued source references will not be performed normally. If TXOFS or TYOFS is set, the source at a location shifted by the offset amount is referenced. Make the TXOFS and TYOFS settings in pixel units. 1. When source style specification is selected as a rendering attribute (STYLE = 1), the source data is not enlarged or reduced, but is referenced repeatedly. 2. When work specification is selected as a rendering attribute (WORK = 1), only places where the work coordinate pixel is 1 are drawn at rendering coordinates while referencing work coordinates for the same coordinates as the rendering coordinates. 3. When SS = 1, the source data is referenced from the 2-dimensional source area. When SS = 0, the source data is referenced from the Base Address in the display list. When REL = 0, the source address can be specified as an absolute address. When REL = 1, the source address can be specified as a relative address with respect to the memory address at which the POLYGON4A command code is located. 4. In 16-bit/pixel drawing, if the rendering attribute COOF bit is set to 1, the result of adding the value in COFSR to the value of the multi-valued source data is drawn. The operation is performed by saturation processing. In 8-bit/pixel drawing, the COOF bit should be cleared to 0. Rev. 1.00 Nov. 22, 2007 Page 1100 of 1692 REJ09B0360-0100 Section 23 G2D (d) Example (TXS, TYS) TDX (DX1, DY1) No work specification TDY (DX2, DY2) (WORK = 0) (DX4, DY4) (DX3, DY3) 2-dimensional source coordinates Work specification provided (WORK = 1) Rendering coordinates (WORK = 1) (DX1, DY1) (DX2, DY2) (DX1, DY1) (DX2, DY2) (DX4, DY4) (DX3, DY3) (DX4, DY4) (DX3, DY3) Work coordinates Rendering coordinates Rev. 1.00 Nov. 22, 2007 Page 1101 of 1692 REJ09B0360-0100 Section 23 G2D (2) (a) POLYGON4B Function Performs any four-vertex drawing in the destination area while referencing a binary (1-bit/pixel) source. (b) Command Format • SS = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1000_0001 Color1 0 0 0 Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode Color0 0 0 0 0 0 0 0 0 0 0 TYS (0 ≤ TYS ≤ 4095) TDY (1 ≤ TDY ≤ 4095) TYOFS (0 ≤ TYOFS ≤ TDY – 1) DY1 (-32768 ≤ DY1 ≤ 32767) DY2 (-32768 ≤ DY2 ≤ 32767) DY3 (-32768 ≤ DY3 ≤ 32767) DY4 (-32768 ≤ DY4 ≤ 32767) 0 0 0 0 0 0 0 0 0 TXS (0 ≤ TXS ≤ 4088) TDX (8 ≤ TDX ≤ 4088) 0 0 0 0 0 Sign TXOFS (0 ≤ TXOFS ≤ TDX − 1) DX1 (-32768 ≤ DX1 ≤ 32767) DX2 (-32768 ≤ DX2 ≤ 32767) DX3 (-32768 ≤ DX3 ≤ 32767) DX4 (-32768 ≤ DX4 ≤ 32767) Sign Sign Sign Sign Sign Sign Note: 0 ≤ TXS ≤ SSTRR − TDX, 0 ≤ TYS ≤ 4096 − TDY (SSTRR: Source stride register setting) • SS = 0 and REL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1000_0001 Color1 0 0 0 Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode Color0 0 0 0 0 0 0 0 0 TDX (8 ≤ TDX ≤ 4088) Base Address (quad word address) 0 0 0 0 0 Sign 0 TDY (1 ≤ TDY ≤ 4095) TYOFS (0 ≤ TYOFS ≤ TDY – 1) DY1 (-32768 ≤ DY1 ≤ 32767) DY2 (-32768 ≤ DY2 ≤ 32767) DY3 (-32768 ≤ DY3 ≤ 32767) DY4 (-32768 ≤ DY4 ≤ 32767) 0 0 0 0 0 0 0 0 TXOFS (0 ≤ TXOFS ≤ TDX − 1) DX1 (-32768 ≤ DX1 ≤ 32767) DX2 (-32768 ≤ DX2 ≤ 32767) DX3 (-32768 ≤ DX3 ≤ 32767) DX4 (-32768 ≤ DX4 ≤ 32767) Sign Sign Sign Sign Sign Sign Rev. 1.00 Nov. 22, 2007 Page 1102 of 1692 REJ09B0360-0100 Section 23 G2D • SS = 0 and REL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1000_0001 Color1 Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode Color0 Base Address (longword address) TDX (8 ≤ TDX ≤ 4088) 0 0 0 0 0 Sign 0 TDY (1 ≤ TDY ≤ 4095) TYOFS (0 ≤ TYOFS ≤ TDY – 1) 0 0 0 Sign 0 0 0 0 0 0 0 0 0 0 0 0 TXOFS (0 ≤ TXOFS ≤ TDX − 1) DX1 (-32768 ≤ DX1 ≤ 32767) DX2 (-32768 ≤ DX2 ≤ 32767) DX3 (-32768 ≤ DX3 ≤ 32767) DX4 (-32768 ≤ DX4 ≤ 32767) DY1 (-32768 ≤ DY1 ≤ 32767) DY2 (-32768 ≤ DY2 ≤ 32767) DY3 (-32768 ≤ DY3 ≤ 32767) DY4 (-32768 ≤ DY4 ≤ 32767) Sign Sign Sign Sign Sign Sign Note: Adding the address (longword: 32-bit units) where the command code is located to the Base Address (longword: 32-bit units) must result in a quad word address (64-bit units). 1. Code B'10000001 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work O O (only WORK = 1) Drawing Destination Specified Color Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 RCLIP b11 STRANS b10 Fixed to 0 b9 WORK b8 SS b7 REL b6 b5 b4 NET b3 EOS b2 b1 b0 Fixed to 0 MTRE Fixed STYLE BLKE COOF αE Rev. 1.00 Nov. 22, 2007 Page 1103 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters TXS, TYS: Base Address: Source starting point. Write 0 to the unused bits. Source start absolute address (Quad word address. Write 0 to bits A31 to A29 and A2 to A0.) Source start relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. TDX, TDY: Source size. Write 0 to the unused bits. DXn, DYn (n = 1 to 4): Rendering coordinates (absolute coordinates). Negative numbers expressed as two's complement. TXOFS, TYOFS: Source offset. Write 0 to the unused bits. Color0, Color1: 8- or 16-bit/pixel color specification. For 16-bit/pixel drawing, the color specification should match the destination pixel format. For 8-bit/pixel drawing, the same value should be set in the upper and lower bytes. (c) Description Draws binary (1-bit/pixel) source data in any quadrilateral rendering area, using the colors specified by parameters Color0 and Color1. For the color specifications (Color0 and Color1) in 8bit/pixel drawing, set the same 8-bit data in the upper and lower bytes. The source data is always scanned horizontally, but diagonal scanning may be used in the drawing, depending on the shape. In diagonally-scanned drawing, double-writing occurs to fill in gaps. A multiple of 8 pixels must be set as the TDX value, regardless of the SS bit value. If TXOFS or TYOFS is set, the source at a location shifted by the offset amount is referenced. Make the TXOFS and TYOFS settings in pixel units. 1. When source style specification is selected as a rendering attribute (STYLE = 1), the source data is not enlarged or reduced, but is referenced repeatedly. 2. When work specification is selected as a rendering attribute (WORK = 1), only places where the work coordinate pixel is 1 are drawn at rendering coordinates while referencing work coordinates for the same coordinates as the rendering coordinates. 3. When REL = 0, the source address can be specified as an absolute address. When REL = 1, the source address can be specified as a relative address with respect to the memory address at which the POLYGON4B command code is located. Rev. 1.00 Nov. 22, 2007 Page 1104 of 1692 REJ09B0360-0100 Section 23 G2D (d) Example Base Address TDY TDX (DX1, DY1) COLOR0 COLOR1 Non-transparent mode (STRANS = 0) (DX4, DY4) (DX2, DY2) (DX3, DY3) Rendering coordinates 1-dimensional source coordinates Transparent mode (STRANS = 1) (DX1, DY1) COLOR1 Binary source 0 data is transparent. (DX4, DY4) (DX2, DY2) (DX3, DY3) Rendering coordinates Rev. 1.00 Nov. 22, 2007 Page 1105 of 1692 REJ09B0360-0100 Section 23 G2D (3) (a) POLYGON4C Function Performs any four-vertex drawing at rendering coordinates with a monochrome specification. (b) Command Format 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1000_0000 All 0 Sign Reserve (all 0) Draw Mode Color Sign DX1 (-32768 ≤ DX1 ≤ 32767) DX2 (-32768 ≤ DX2 ≤ 32767) DX3 (-32768 ≤ DX3 ≤ 32767) DX4 (-32768 ≤ DX4 ≤ 32767) DY1 (-32768 ≤ DY1 ≤ 32767) DY2 (-32768 ≤ DY2 ≤ 32767) DY3 (-32768 ≤ DY3 ≤ 32767) DY4 (-32768 ≤ DY4 ≤ 32767) Sign Sign Sign Sign Sign Sign 1. Code B'10000000 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work O (only WORK = 1) Drawing Destination Specified Color O Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 b11 to 0 b10 Fixed to 0 b9 WORK b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 b4 b3 EOS b2 b1 b0 Fixed to 0 MTRE Fixed RCLIP Fixed BLKE NET COOF αE 3. Command Parameters DXn, DYn (n = 1 to 4): Rendering coordinates (absolute coordinates). Negative numbers expressed as two's complement. Color: 8- or 16-bit/pixel color specification. For 16-bit/pixel drawing, the color specification should match the destination pixel format. For 8-bit/pixel drawing, the same value should be set in the upper and lower bytes. Rev. 1.00 Nov. 22, 2007 Page 1106 of 1692 REJ09B0360-0100 Section 23 G2D (c) Description Draws any quadrilateral in the rendering area in the single color specified by the Color parameter. When work specification is selected as a rendering attribute (WORK = 1), only places where the work coordinate pixel is 1 are drawn at rendering coordinates while referencing work coordinates for the same coordinates as the rendering coordinates. (d) Example No work specification (DX1, DY1) COLOR Specified color (DX4, DY4) (DX2, DY2) (DX3, DY3) Rendering coordinates Work specification provided (DX1, DY1) (DX2, DY2) COLOR (DX1, DY1) (DX2, DY2) Specified color (DX4, DY4) (DX3, DY3) (DX4, DY4) (DX3, DY3) Work coordinates Rendering coordinates Rev. 1.00 Nov. 22, 2007 Page 1107 of 1692 REJ09B0360-0100 Section 23 G2D 23.2.2 (1) (a) Line Drawing Commands LINEA Function Draws a polygonal line with any width in the destination area while referencing a multi-valued (8or 16-bit/pixel) source. (b) Command Format • REL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0010 0 0 0 0 0 0 0 0 0 0 0 TDX (8 ≤ TDX ≤ 4088) Reserve (all 0) Base Address (quad word address) 0 0 0 0 0 0 0 TDY (1 ≤ TDY ≤ 4095) n (2 ≤ n ≤ 65535) 0 Sign 8 7 6 5 4 3 2 1 0 Draw Mode 0 0 0 TXOFS (0 ≤ TXOFS ≤ TDX − 1) Reserve (all 0) 0 0 0 0 0 0 0 0 0 W (0,2 ≤ W ≤ 63) Sign DX1 (-32768 ≤ DX1 ≤ 32767) : : DXn (-32768 ≤ DXn ≤ 32767) DY1 (-32768 ≤ DY1 ≤ 32767) : : DYn (-32768 ≤ DYn ≤ 32767) Sign Sign Sign Sign Sign Sign Notes: 1. When W = 0, set TDY to 1. 2. When n = 0 or 1, correct operation is not guaranteed. Rev. 1.00 Nov. 22, 2007 Page 1108 of 1692 REJ09B0360-0100 Section 23 G2D • REL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0010 Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Base Address (longword address) Draw Mode 0 TDY (1 ≤ TDY ≤ 4095) n (2 ≤ n ≤ 65535) 0 Sign 0 0 0 0 0 0 0 0 0 TDX (8 ≤ TDX ≤ 4088) 0 0 0 0 0 0 0 TXOFS (0 ≤ TXOFS ≤ TDX − 1) Reserve (all 0) 0 0 0 0 0 0 0 0 0 W (0,2 ≤ W ≤ 63) Sign DX1 (-32768 ≤ DX1 ≤ 32767) : : DXn (-32768 ≤ DXn ≤ 32767) DY1 (-32768 ≤ DY1 ≤ 32767) : : DYn (-32768 ≤ DYn ≤ 32767) Sign Sign Sign Sign Sign Sign Notes: 1. Adding the address (longword: 32-bit units) where the command code is located to the Base Address (longword: 32-bit units) must result in a quad word address (64-bit units). 2. When W = 0, set TDY to 1. 3. When n = 0 or 1, correct operation is not guaranteed. 1. Code B'10110010 2. Rendering Attributes Reference Data Multi-Valued Source O Binary Source Binary Work Specified Color Drawing Destination Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 RCLIP b11 STRANS b10 Fixed to 0 b9 Fixed to 0 b8 b7 b6 (1) b5 to 0 b4 NET b3 EOS b2 b1 b0 Fixed to 0 MTRE Fixed SS (0) REL STYLE Fixed COOF AA Notes: 1. Clear the SS bit to 0. 2. Set the STYLE bit to 1. Rev. 1.00 Nov. 22, 2007 Page 1109 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters Base Address: Source start absolute address (Quad word address. Write 0 to bits A31 to A29 and A2 to A0.) Source start relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. TDX, TDY: TXOFS: n (n = 2 to 65,535): W: Source size. Write 0 to the unused bits. Source offset. Write 0 to the unused bits. Number of vertices Line width. Set a 6-bit integer. Write 0 to the unused bits. When 0 is set in W, a polygonal line of line width 1 is drawn. Setting 1 in W is prohibited. DXn (n = 2 to 65,535): Rendering coordinate (absolute coordinate). Negative number expressed as two's complement. DYn (n = 2 to 65,535): Rendering coordinate (absolute coordinate). Negative number expressed as two's complement. (c) Description Draws a polygonal line from vertex 1 (DX1, DY1), through vertex 2 (DX2, DY2), ...., vertex n – 1 (DXn – 1, DYn – 1), to vertex n (DXn, DYn). Set a multiple of 8 pixels as the TDX value. If TXOFS is set, the source at a location shifted by the offset amount is referenced. Make the TXOFS setting in pixel units. Pattern repetition selected by the STYLE bit is only performed in the X direction of the source data. The source data is enlarged or reduced in proportion to the line width in the Y direction. When a value greater than 1 is set in W, a bold line can be drawn. Rev. 1.00 Nov. 22, 2007 Page 1110 of 1692 REJ09B0360-0100 Section 23 G2D Notes: 1. 8-point drawing is used for a line width of 1. Both of the 8-point drawing and 4-point drawing are used for bold line drawing. 2. The final point of each line segment is drawn. When the starting and final coordinate points of a line segment match, a single dot is drawn for a line width of 1 and nothing is drawn for bold line drawing 3. When AA = 1, note the following: • For a dashed line, antialiasing is not performed for the gaps in the dashed line. • When the starting and final coordinate points of a line segment match, antialiasing is not performed. • Antialiasing is not performed for horizontal, vertical, and 45-degree diagonal line segments. (2) (a) LINEB Function Draws a polygonal line with any width in the destination area while referencing a binary (1bit/pixel) source. (b) Command Format • REL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0001 Color1 0 0 0 0 0 0 0 0 0 0 0 TDX (8 ≤ TDX ≤ 4088) Base Address (quad word address) 0 0 0 0 0 0 0 TDY (1 ≤ TDY ≤ 4095) n (2 ≤ n ≤ 65535) 0 Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode Color0 0 0 0 TXOFS (0 ≤ TXOFS ≤ TDX − 1) Reserve (all 0) 0 0 0 0 0 0 0 0 0 W (0,2 ≤ W ≤ 63) Sign DX1 (-32768 ≤ DX1 ≤ 32767) : : DXn (-32768 ≤ DXn ≤ 32767) DY1 (-32768 ≤ DY1 ≤ 32767) : : DYn (-32768 ≤ DYn ≤ 32767) Sign Sign Sign Sign Sign Sign Notes: 1. When W = 0, set TDY to 1. 2. When n = 0 or 1, correct operation is not guaranteed. Rev. 1.00 Nov. 22, 2007 Page 1111 of 1692 REJ09B0360-0100 Section 23 G2D • REL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0001 Color1 Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode Color0 Base Address (longword address) TDX (8 ≤ TDX ≤ 4088) 0 0 0 0 0 0 0 TDY (1 ≤ TDY ≤ 4095) n (2 ≤ n ≤ 65535) 0 Sign 0 0 0 0 0 0 0 0 0 0 TXOFS (0 ≤ TXOFS ≤ TDX − 1) Reserve (all 0) 0 0 0 0 0 0 0 0 0 W (0,2 ≤ W ≤ 63) Sign DX1 (-32768 ≤ DX1 ≤ 32767) : : DXn (-32768 ≤ DXn ≤ 32767) DY1 (-32768 ≤ DY1 ≤ 32767) : : DYn (-32768 ≤ DYn ≤ 32767) Sign Sign Sign Sign Sign Sign Notes: 1. Adding the address (longword: 32-bit units) where the command code is located to the Base Address (longword: 32-bit units) must result in a quad word address (64-bit units). 2. When W = 0, set TDY to 1. 3. When n = 0 or 1, correct operation is not guaranteed. 1. Code B'10110001 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work O Specified Color Drawing Destination Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 RCLIP b11 STRANS b10 Fixed to 0 b9 Fixed to 0 b8 b7 b6 (1) b5 to 0 b4 NET b3 EOS b2 b1 b0 Fixed to 0 MTRE Fixed SS (0) REL STYLE Fixed COOF AA Notes: 1. Clear the SS bit to 0. 2. Set the STYLE bit to 1. Rev. 1.00 Nov. 22, 2007 Page 1112 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters Color0, Color1: Base Address: 8- or 16-bit/pixel color specification. For 16-bit/pixel drawing, the color specification should match the destination pixel format. For 8-bit/pixel drawing, the same value should be set in the upper and lower bytes. Source start absolute address (Quad word address. Write 0 to bits A31 to A29 and A2 to A0. Source start relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. Source size. Write 0 to the unused bits. Source offset. Write 0 to the unused bits. Number of vertices Line width. Set a 6-bit integer. Write 0 to the unused bits. When 0 is set in W, a polygonal line of line width 1 is drawn. Setting 1 in W is prohibited. DXn (n = 2 to 65,535): Rendering coordinate (absolute coordinate). Negative number expressed as two's complement. DYn (n = 2 to 65,535): Rendering coordinate (absolute coordinate). Negative number expressed as two's complement. (c) Description TDX, TDY: TXOFS: n (n = 2 to 65,535): W: Draws a polygonal line from vertex 1 (DX1, DY1), through vertex 2 (DX2, DY2), ...., vertex n – 1 (DXn – 1, DYn – 1), to vertex n (DXn, DYn). Set a multiple of 8 pixels as the TDX value. If TXOFS is set, the source at a location shifted by the offset amount is referenced. Make the TXOFS setting in pixel units. Pattern repetition selected by the STYLE bit is only performed in the X direction of the source data. The source data is enlarged or reduced in proportion to the line width in the Y direction. When a value greater than 1 is set in W, a bold line can be drawn. Rev. 1.00 Nov. 22, 2007 Page 1113 of 1692 REJ09B0360-0100 Section 23 G2D Notes: 1. 8-point drawing is used for a line width of 1. Both of the 8-point drawing and 4-point drawing are used for bold line drawing. 2. The final point of each line segment is drawn. When the starting and final coordinate points of a line segment match, a single dot is drawn for a line width of 1 and nothing is drawn for bold line drawing. 3. When AA = 1, note the following: • For a dashed line, antialiasing is not performed for the gaps in the dashed line. • When the starting and final coordinate points of a line segment match, antialiasing is not performed. • Antialiasing is not performed for horizontal, vertical, and 45-degree diagonal line segments. (d) Example TDX (0, 0) Base Address (DX2, DY2) 1100 1100 L S B (DX1, DY1) (DX3, DY3) STRANS = 1 and STYLE = 1 specified Rendering coordinates 1100 1100 M S B n=3 Rev. 1.00 Nov. 22, 2007 Page 1114 of 1692 REJ09B0360-0100 Section 23 G2D (3) (a) LINEC Function Draws a polygonal line with any width in the destination area with a monochrome specification. (b) Command Format • LINKE = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0000 Color Reserve (all 0) Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (2 ≤ n ≤ 65535) 0 Sign 0 0 0 0 0 0 0 0 0 W (0,2 ≤ W ≤ 63) DX1 (-32768 ≤ DX1 ≤ 32767) : : DXn (-32768 ≤ DXn ≤ 32767) DY1 (-32768 ≤ DY1 ≤ 32767) : : DYn (-32768 ≤ DYn ≤ 32767) Sign Sign Sign Sign Sign Sign Note: When n = 0 or 1, correct operation is not guaranteed. • LINKE = 1 and LREL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0000 Color Reserve (all 0) 0 0 0 0 0 0 0 0 0 Reserve (all 0) 8 7 6 5 4 3 2 1 0 Draw Mode n (2 ≤ n ≤ 65535) 0 0 0 0 W (0,2 ≤ W ≤ 63) 0 0 LINK Address (longword address) Notes: 1. When n = 0 or 1, correct operation is not guaranteed. 2. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by the LINK Address. Rev. 1.00 Nov. 22, 2007 Page 1115 of 1692 REJ09B0360-0100 Section 23 G2D • LINKE = 1 and LREL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0000 Color Reserve (all 0) Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (2 ≤ n ≤ 65535) 0 0 0 0 0 0 0 0 0 0 W (0,2 ≤ W ≤ 63) 0 0 LINK Address (longword address) Notes: 1. When n = 0 or 1, correct operation is not guaranteed. 2. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by adding the address where the command code is located to the LINK Address. 1. Code B'10110000 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work Specified Color O Drawing Destination Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 b11 to 0 b10 b9 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 NET b3 EOS b2 b1 b0 Fixed to 0 MTRE Fixed RCLIP Fixed LINKE LREL COOF AA Rev. 1.00 Nov. 22, 2007 Page 1116 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters Color: 8- or 16-bit/pixel color specification. For 16-bit/pixel drawing, the color specification should match the destination pixel format. For 8-bit/pixel drawing, the same value should be set in the upper and lower bytes. n (n = 2 to 65,535): Number of vertices W: Line width. Set a 6-bit integer. Write 0 to the unused bits. When 0 is set in W, a polygonal line of line width 1 is drawn. Setting 1 in W is prohibited. DXn (n = 2 to 65,535): Rendering coordinate (absolute coordinate). Negative number expressed as two's complement. DYn (n = 2 to 65,535): Rendering coordinate (absolute coordinate). Negative number expressed as two's complement. LINK Address: LINK absolute address (Longword address. Write 0 to bits A31 to A29, A1, and A0.) LINK relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. (c) Description Draws a polygonal line from vertex 1 (DX1, DY1), through vertex 2 (DX2, DY2), ...., vertex n – 1 (DXn – 1, DYn – 1), to vertex n (DXn, DYn). When a value greater than 1 is set in W, a bold line can be drawn. When LINKE = 1, the vertex coordinates are read from the memory address specified by the LINK Address. The LINK Address can be specified through the LREL bit as an absolute address or a relative address with respect to the memory address at which the LINEC command code is located. Rev. 1.00 Nov. 22, 2007 Page 1117 of 1692 REJ09B0360-0100 Section 23 G2D Notes: 1. 8-point drawing is used for a line width of 1. Both of the 8-point drawing and 4-point drawing are used for bold line drawing. 2. The final point of each line segment is drawn. When the starting and final coordinate points of a line segment match, a single dot is drawn for a line width of 1 and nothing is drawn for bold line drawing. 3. When AA = 1, note the following: • When the starting and final coordinate points of a line segment match, antialiasing is not performed. • Antialiasing is not performed for horizontal, vertical, and 45-degree diagonal line segments. (d) Example n=3 (0, 0) (DX2, DY2) (DX1, DY1) (DX3, DY3) Rendering coordinates Rev. 1.00 Nov. 22, 2007 Page 1118 of 1692 REJ09B0360-0100 Section 23 G2D (4) (a) LINED Function Performs antialiasing for the exterior frame of a polygon. This command can only be executed for a 16-bit/pixel destination. (b) Command Format • LINKE = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0011 Reserve (all 0) Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (2 ≤ n ≤ 65535) Sign DX1 (-32768 ≤ DX1 ≤ 32767) : : DXn (-32768 ≤ DXn ≤ 32767) DY1 (-32768 ≤ DY1 ≤ 32767) : : DYn (-32768 ≤ DYn ≤ 32767) Sign Sign Sign Sign Sign Sign Note: When n = 0 or 1, correct operation is not guaranteed. • LINKE = 1 and LREL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0011 Reserve (all 0) 0 0 0 LINK Address (longword address) Reserve (all 0) 8 7 6 5 4 3 2 1 0 Draw Mode n (2 ≤ n ≤ 65535) 0 0 Notes: 1. When n = 0 or 1, correct operation is not guaranteed. 2. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by the LINK Address. Rev. 1.00 Nov. 22, 2007 Page 1119 of 1692 REJ09B0360-0100 Section 23 G2D • LINKE = 1 and LREL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0011 Reserve (all 0) Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (2 ≤ n ≤ 65535) LINK Address (longword address) 0 0 Notes: 1. When n = 0 or 1, correct operation is not guaranteed. 2. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by adding the address where the command code is located to the LINK Address. 1. Code B'10110011 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 b11 to 0 b10 b9 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 Fixed to 0 b3 Fixed to 0 b2 Fixed to 0 b1 b0 MTRE Fixed RCLIP Fixed LINKE LREL AA (1) CLKW Note: Set the AA bit to 1. Rev. 1.00 Nov. 22, 2007 Page 1120 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters n (n = 2 to 65,535): Number of vertices DXn (n = 2 to 65,535): Rendering coordinate (absolute coordinate). Negative number expressed as two's complement. DYn (n = 2 to 65,535): Rendering coordinate (absolute coordinate). Negative number expressed as two's complement. LINK Address: LINK absolute address (Longword address. Write 0 to bits A31 to A29, A1, and A0). LINK relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. (c) Description Performs antialiasing for the exterior frame of a polygon drawn using work reference. The CLKW bit specifies whether the order to give the n vertices is clockwise or counterclockwise: CLKW = 1 selects clockwise and CLKW = 0 selects counterclockwise. When clockwise is specified, the left image with respect to the drawing direction is referenced by antialiasing. On the other hand, the right image is referenced when counterclockwise is selected. When LINKE = 1, the vertex coordinates are read from the memory address specified by the LINK Address. The LINK Address can be specified through the LREL bit as an absolute address or a relative address with respect to the memory address at which the LINED command code is located. This command can only be executed for a 16-bit/pixel destination. When a polygon used in work reference is drawn by the FTRAPC (RFTRAPC) command, perform drawing with both the EDG and EOS bits set to 1. Rev. 1.00 Nov. 22, 2007 Page 1121 of 1692 REJ09B0360-0100 Section 23 G2D Notes: 1. 8-point drawing is used. 2. The final point of each line segment is not drawn. When antialiasing is performed for the exterior frame of a polygon drawn by a POLYGON4 type command, the paths may not match. 3. When the starting and final coordinate points of a line segment match, nothing is drawn. 4. Antialiasing is not performed for horizontal, vertical, and 45-degree diagonal line segments, which are pre-clipped inside the G2D. 5. Clipping is performed on a pixel basis when either the referenced pixel or the pixel to be drawn is outside the clipping area, and antialiasing is not performed in such a case. (d) Example n=6 (0, 0) (DX6, DY6) (DX1, DY1) (DX5, DY5) n=6 (0, 0) (DX6, DY6) (DX1, DY1) (DX2, DY2) (DX2, DY2) (DX5, DY5) (DX4, DY4) (DX3, DY3) (DX3, DY3) (DX4, DY4) Rendering coordinates CLKW = 1 CLKW = 0 Rendering coordinates Rev. 1.00 Nov. 22, 2007 Page 1122 of 1692 REJ09B0360-0100 Section 23 G2D (5) (a) RLINEA Function Draws a polygonal line with any width in the destination area with a relative coordinate specification from the current pointer value while referencing a multi-valued (8- or 16-bit/pixel) source. (b) Command Format • REL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0110 0 0 0 0 0 0 0 0 0 0 0 TDX (8 ≤ TDX ≤ 4088) Reserve (all 0) Base Address (quad word address) 0 0 0 0 0 0 0 TDY (1 ≤ TDY ≤ 4095) n (1 ≤ n ≤ 65535) 0 Sign 8 7 6 5 4 3 2 1 0 Draw Mode 0 0 0 TXOFS (0 ≤ TXOFS ≤ TDX − 1) Reserve (all 0) 0 0 0 0 0 0 0 0 Sign 0 W (0,2 ≤ W ≤ 63) Sign DX2 (-128 ≤ DX2 ≤ 127) : : DXn (-128 ≤ DXn ≤ 127) Sign DY2 (-128 ≤ DY2 ≤ 127) : : DYn (-128 ≤ DYn ≤ 127) DX1 (-128 ≤ DX1 ≤ 127) : : DXn-1 (-128 ≤ DXn-1 ≤ 127) DY1 (-128 ≤ DY1 ≤ 127) : : DYn-1 (-128 ≤ DYn-1 ≤ 127) Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Notes: 1. When W = 0, set TDY to 1. 2. When n = 0, correct operation is not guaranteed. 3. When n is an odd number, insert a dummy word of 0 at the end. Rev. 1.00 Nov. 22, 2007 Page 1123 of 1692 REJ09B0360-0100 Section 23 G2D • REL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0110 Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Base Address (longword address) Draw Mode 0 TDY (1 ≤ TDY ≤ 4095) n (1 ≤ n ≤ 65535) 0 Sign 0 0 0 0 0 0 0 0 0 TDX (8 ≤ TDX ≤ 4088) 0 0 0 0 0 0 0 TXOFS (0 ≤ TXOFS ≤ TDX − 1) Reserve (all 0) 0 0 0 0 0 0 0 0 Sign 0 W (0,2 ≤ W ≤ 63) Sign DX2 (-128 ≤ DX2 ≤ 127) : : DXn (-128 ≤ DXn ≤ 127) Sign DY2 (-128 ≤ DY2 ≤ 127) : : DYn (-128 ≤ DYn ≤ 127) DX1 (-128 ≤ DX1 ≤ 127) : : DXn-1 (-128 ≤ DXn-1 ≤ 127) DY1 (-128 ≤ DY1 ≤ 127) : : DYn-1 (-128 ≤ DYn-1 ≤ 127) Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Notes: 1. Adding the address (longword: 32-bit units) where the command code is located to the Base Address (longword: 32-bit units) must result in a quad word address (64-bit units). 2. When W = 0, set TDY to 1. 3. When n = 0, correct operation is not guaranteed. 4. When n is an odd number, insert a dummy word of 0 at the end. 1. Code B'10110110 2. Rendering Attributes Reference Data Multi-Valued Source O Binary Source Binary Work Specified Color Drawing Destination Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 RCLIP b11 STRANS b10 Fixed to 0 b9 Fixed to 0 b8 b7 b6 (1) b5 to 0 b4 NET b3 EOS b2 b1 b0 Fixed to 0 MTRE Fixed SS (0) REL STYLE Fixed COOF AA Notes: 1. Clear the SS bit to 0. 2. Set the STYLE bit to 1. Rev. 1.00 Nov. 22, 2007 Page 1124 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters Base Address: Source start absolute address (Quad word address. Write 0 to bits A31 to A29 and A2 to A0.) Source start relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. Source size. Write 0 to the unused bits. Source offset. Write 0 to the unused bits. Number of vertices Line width. Set a 6-bit integer. Write 0 to the unused bits. When 0 is set in W, a polygonal line of line width 1 is drawn. Setting 1 in W is prohibited. DXn (n = 1 to 65,535): Rendering coordinate (relative coordinate). Negative number expressed as two's complement. DYn (n = 1 to 65,535): Rendering coordinate (relative coordinate). Negative number expressed as two's complement. (c) Description TDX, TDY: TXOFS: n (n = 1 to 65,535): W: Draws a polygonal line comprising line segments (XC, YC) – (XC + DX1, YC + DY1), (XC + DX1, YC + DY1) – (XC + DX1 + DX2, YC + DY1 + DY2), ..., (XC + ... + DXn – 1, YC + ... + DYn – 1) – (XC + ... + DXn – 1 + DXn, YC + ... + DYn – 1 + DYn) to the coordinates specified by the relative shift (DX, DY) from the current pointer values (XC, YC). The final coordinate point is stored as the current pointer values (XC, YC). Set a multiple of 8 pixels as the TDX value. If TXOFS is set, the source at a location shifted by the offset amount is referenced. Make the TXOFS setting in pixel units. Pattern repetition selected by the STYLE bit is only performed in the X direction of the source data. The source data is enlarged or reduced in proportion to the line width in the Y direction. When a value greater than 0 is set in W, a bold line can be drawn. Rev. 1.00 Nov. 22, 2007 Page 1125 of 1692 REJ09B0360-0100 Section 23 G2D Notes: 1. 8-point drawing is used for a line width of 1. Both of the 8-point drawing and 4-point drawing are used for bold line drawing. 2. The final point of each line segment is drawn. When the starting and final coordinate points of a line segment match, a single dot is drawn for a line width of 1 and nothing is drawn for bold line drawing. 3. When AA = 1, note the following: • For a dashed line, antialiasing is not performed for the gaps in the dashed line. • When the starting and final coordinate points of a line segment match, antialiasing is not performed. • Antialiasing is not performed for horizontal, vertical, and 45-degree diagonal line segments 4. The final coordinate point before coordinate transformation is stored as the current pointer values (XC, YC). Rev. 1.00 Nov. 22, 2007 Page 1126 of 1692 REJ09B0360-0100 Section 23 G2D (6) (a) RLINEB Function Draws a polygonal line with any width in the destination area with a relative coordinate specification from the current pointer value while referencing a binary (1-bit/pixel) source. (b) Command Format • REL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0101 Color1 0 0 0 0 0 0 0 0 0 0 0 TDX (8 ≤ TDX ≤ 4088) Base Address (quad word address) 0 0 0 0 0 0 0 TDY (1 ≤ TDY ≤ 4095) n (1 ≤ n ≤ 65535) 0 Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode Color0 0 0 0 TXOFS (0 ≤ TXOFS ≤ TDX − 1) Reserve (all 0) 0 0 0 0 0 0 0 0 Sign 0 W (0,2 ≤ W ≤ 63) Sign DX2 (-128 ≤ DX2 ≤ 127) : : DXn (-128 ≤ DXn ≤ 127) Sign DY2 (-128 ≤ DY2 ≤ 127) : : DYn (-128 ≤ DYn ≤ 127) DX1 (-128 ≤ DX1 ≤ 127) : : DXn-1 (-128 ≤ DXn-1 ≤ 127) DY1 (-128 ≤ DY1 ≤ 127) : : DYn-1 (-128 ≤ DYn-1 ≤ 127) Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Notes: 1. When W = 0, set TDY to 1. 2. When n = 0, correct operation is not guaranteed. 3. When n is an odd number, insert a dummy word of 0 at the end. Rev. 1.00 Nov. 22, 2007 Page 1127 of 1692 REJ09B0360-0100 Section 23 G2D • REL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0101 Color1 Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode Color0 Base Address (longword address) TDX (8 ≤ TDX ≤ 4088) 0 0 0 0 0 0 0 TDY (1 ≤ TDY ≤ 4095) n (1 ≤ n ≤ 65535) 0 Sign 0 0 0 0 0 0 0 0 0 0 TXOFS (0 ≤ TXOFS ≤ TDX − 1) Reserve (all 0) 0 0 0 0 0 0 0 0 Sign 0 W (0,2 ≤ W ≤ 63) Sign DX2 (-128 ≤ DX2 ≤ 127) : : DXn (-128 ≤ DXn ≤ 127) Sign DY2 (-128 ≤ DY2 ≤ 127) : : DYn (-128 ≤ DYn ≤ 127) DX1 (-128 ≤ DX1 ≤ 127) : : DXn-1 (-128 ≤ DXn-1 ≤ 127) DY1 (-128 ≤ DY1 ≤ 127) : : DYn-1 (-128 ≤ DYn-1 ≤ 127) Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Notes: 1. Adding the address (longword: 32-bit units) where the command code is located to the Base Address (longword: 32-bit units) must result in a quad word address (64-bit units). 2. When W = 0, set TDY to 1. 3. When n = 0, correct operation is not guaranteed. 4. When n is an odd number, insert a dummy word of 0 at the end. 1. Code B'10110101 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work O Specified Color Drawing Destination Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 RCLIP b11 STRANS b10 Fixed to 0 b9 Fixed to 0 b8 b7 b6 (1) b5 to 0 b4 NET b3 EOS b2 b1 b0 Fixed to 0 MTRE Fixed SS (0) REL STYLE Fixed COOF AA Notes: 1. Clear the SS bit to 0. 2. Set the STYLE bit to 1. Rev. 1.00 Nov. 22, 2007 Page 1128 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters Color0, Color1: Base Address: 8- or 16-bit/pixel color specification. For 16-bit/pixel drawing, the color specification should match the destination pixel format. For 8-bit/pixel drawing, the same value should be set in the upper and lower bytes. Source start absolute address (Quad word address. Write 0 to bits A31 to A29 and A2 to A0.) Source start relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. Source size. Write 0 to the unused bits. Source offset. Write 0 to the unused bits. Number of vertices Line width. Set a 6-bit integer. Write 0 to the unused bits. When 0 is set in W, a polygonal line of line width 1 is drawn. Setting 1 in W is prohibited. DXn (n = 1 to 65,535): Rendering coordinate (relative coordinate). Negative number expressed as two's complement. DYn (n = 1 to 65,535): Rendering coordinate (relative coordinate). Negative number expressed as two's complement. (c) Description TDX, TDY: TXOFS: n (n = 1 to 65,535): W: Draws a polygonal line comprising line segments (XC, YC) – (XC + DX1, YC + DY1), (XC + DX1, YC + DY1) – (XC + DX1 + DX2, YC + DY1 + DY2), ..., (XC + ... + DXn – 1, YC + ... + DYn – 1) – (XC + ... + DXn – 1 + DXn, YC + ... + DYn – 1 + DYn) to the coordinates specified by the relative shift (DX, DY) from the current pointer values (XC, YC). The final coordinate point is stored as the current pointer values (XC, YC). Set a multiple of 8 pixels as the TDX value. If TXOFS is set, the source at a location shifted by the offset amount is referenced. Make the TXOFS setting in pixel units. Pattern repetition selected by the STYLE bit is only performed in the X direction of the source data. The source data is enlarged or reduced in proportion to the line width in the Y direction. Rev. 1.00 Nov. 22, 2007 Page 1129 of 1692 REJ09B0360-0100 Section 23 G2D When a value greater than 1 is set in W, a bold line can be drawn. Notes: 1. 8-point drawing is used for a line width of 1. Both of the 8-point drawing and 4-point drawing are used for bold line drawing. 2. The final point of each line segment is drawn. When the starting and final coordinate points of a line segment match, a single dot is drawn for a line width of 1 and nothing is drawn for bold line drawing. 3. When AA = 1, note the following: • For a dashed line, antialiasing is not performed for the gaps in the dashed line. • When the starting and final coordinate points of a line segment match, antialiasing is not performed. • Antialiasing is not performed for horizontal, vertical, and 45-degree diagonal line segments. 4. The final coordinate point before coordinate transformation is stored as the current pointer values (XC, YC). (d) n=2 (0, 0) 1100 Base Address DY2 L S DY1 B TDX 1100 1100 1100 M S B Example (XC + DX1, YC + DY1) DX1 DX2 (XC + DX1 + DX2, YC + DY1 + DY2) (XC, YC) STRANS = 1 and STYLE = 1 specified Rendering coordinates Rev. 1.00 Nov. 22, 2007 Page 1130 of 1692 REJ09B0360-0100 Section 23 G2D (7) (a) RLINEC Function Draws a polygonal line with any width in the destination area with a monochrome specification and with a relative coordinate specification from the current pointer value. (b) Command Format • LINKE = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0100 Color Reserve (all 0) Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (1 ≤ n ≤ 65535) 0 Sign 0 0 0 0 0 0 0 0 Sign 0 W (0,2 ≤ W ≤ 63) DX2 (-128 ≤ DX2 ≤ 127) : : DXn (-128 ≤ DXn ≤ 127) Sign DY2 (-128 ≤ DY2 ≤ 127) : : DYn (-128 ≤ DYn ≤ 127) DX1 (-128 ≤ DX1 ≤ 127) : : DXn-1 (-128 ≤ DXn-1 ≤ 127) DY1 (-128 ≤ DY1 ≤ 127) : : DYn-1 (-128 ≤ DYn-1 ≤ 127) Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Notes: 1. When n = 0, correct operation is not guaranteed. 2. When n is an odd number, insert a dummy word of 0 at the end. • LINKE = 1 and LREL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0100 Color Reserve (all 0) 0 0 0 0 0 0 0 0 0 Reserve (all 0) 8 7 6 5 4 3 2 1 0 Draw Mode n (1 ≤ n ≤ 65535) 0 0 0 0 W (0,2 ≤ W ≤ 63) 0 0 LINK Address (longword address) Notes: 1. When n = 0, correct operation is not guaranteed. 2. When n is an odd number, insert a dummy word of 0 at the end. 3. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by the LINK Address. Rev. 1.00 Nov. 22, 2007 Page 1131 of 1692 REJ09B0360-0100 Section 23 G2D • LINKE = 1 and LREL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0100 Color Reserve (all 0) Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (1 ≤ n ≤ 65535) 0 0 0 0 0 0 0 0 0 0 W (0,2 ≤ W ≤ 63) 0 0 LINK Address (longword address) Notes: 1. When n = 0, correct operation is not guaranteed. 2. When n is an odd number, insert a dummy word of 0 at the end. 3. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by adding the address where the command code is located to the LINK Address. 1. Code B'10110100 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work Specified Color O Drawing Destination Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 b11 to 0 b10 b9 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 NET b3 EOS b2 b1 b0 Fixed to 0 MTRE Fixed RCLIP Fixed LINKE LREL COOF AA Rev. 1.00 Nov. 22, 2007 Page 1132 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters Color: 8- or 16-bit/pixel color specification. For 16-bit/pixel drawing, the color specification should match the destination pixel format. For 8-bit/pixel drawing, the same value should be set in the upper and lower bytes. n (n = 1 to 65,535): Number of vertices W: Line width. Set a 6-bit integer. Write 0 to the unused bits. When 0 is set in W, a polygonal line of line width 1 is drawn. Setting 1 in W is prohibited. DXn (n = 1 to 65,535): Rendering coordinate (relative coordinate). Negative number expressed as two's complement. DYn (n = 1 to 65,535): Rendering coordinate (relative coordinate). Negative number expressed as two's complement. LINK Address: LINK absolute address (Longword address. Write 0 to bits A31 to A29, A1, and A0.) LINK relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. (c) Description Draws a polygonal line comprising line segments (XC, YC) – (XC + DX1, YC + DY1), (XC + DX1, YC + DY1) – (XC + DX1 + DX2, YC + DY1 + DY2), ..., (XC + ... + DXn – 1, YC + ... + DYn – 1) – (XC + ... + DXn – 1 + DXn, YC + ... + DYn – 1 + DYn) to the coordinates specified by the relative shift (DX, DY) from the current pointer values (XC, YC). When a value greater than 1 is set in W, a bold line can be drawn. When LINKE = 1, the vertex coordinates are read from the memory address specified by the LINK Address. The LINK Address can be specified through the LREL bit as an absolute address or a relative address with respect to the memory address at which the RLINEC command code is located. The final coordinate point is stored as the current pointer values (XC, YC). Rev. 1.00 Nov. 22, 2007 Page 1133 of 1692 REJ09B0360-0100 Section 23 G2D Notes: 1. 8-point drawing is used for a line width of 1. Both of the 8-point drawing and 4-point drawing are used for bold line drawing. 2. The final point of each line segment is drawn. When the starting and final coordinate points of a line segment match, a single dot is drawn for a line width of 1 and nothing is drawn for bold line drawing. 3. When AA = 1, note the following: • When the starting and final coordinate points of a line segment match, antialiasing is not performed. • Antialiasing is not performed for horizontal, vertical, and 45-degree diagonal line segments. 4. The final coordinate point before coordinate transformation is stored as the current pointer values (XC, YC). Example n=2 (0, 0) (d) (XC + DX1, YC + DY1) DX1 DY1 DX2 DY2 (XC, YC) (XC + DX1 + DX2, YC + DY1 + DY2) Rendering coordinates Rev. 1.00 Nov. 22, 2007 Page 1134 of 1692 REJ09B0360-0100 Section 23 G2D (8) (a) RLINED Function Performs antialiasing for the exterior frame of a polygon with a relative coordinate specification from the current pointer value. This command can only be executed for a 16-bit/pixel destination. (b) Command Format • LINKE = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0111 Reserve (all 0) Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (1 ≤ n ≤ 65535) Sign DX2 (-128 ≤ DX2 ≤ 127) : : DXn (-128 ≤ DXn ≤ 127) Sign DY2 (-128 ≤ DY2 ≤ 127) : : DYn (-128 ≤ DYn ≤ 127) DX1 (-128 ≤ DX1 ≤ 127) : : DXn-1 (-128 ≤ DXn-1 ≤ 127) Sign DY1 (-128 ≤ DY1 ≤ 127) : : DYn-1 (-128 ≤ DYn-1 ≤ 127) Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Notes: 1. When n = 0, correct operation is not guaranteed. 2. When n is an odd number, insert a dummy word of 0 at the end. • LINKE = 1 and LREL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0111 Reserve (all 0) 0 0 0 LINK Address (longword address) Reserve (all 0) 8 7 6 5 4 3 2 1 0 Draw Mode n (1 ≤ n ≤ 65535) 0 0 Notes: 1. When n = 0, correct operation is not guaranteed. 2. When n is an odd number, insert a dummy word of 0 at the end. 3. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by the LINK Address. Rev. 1.00 Nov. 22, 2007 Page 1135 of 1692 REJ09B0360-0100 Section 23 G2D • LINKE = 1 and LREL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1011_0111 Reserve (all 0) Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (1 ≤ n ≤ 65535) LINK Address (longword address) 0 0 Notes: 1. When n = 0, correct operation is not guaranteed. 2. When n is an odd number, insert a dummy word of 0 at the end. 3. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by adding the address where the command code is located to the LINK Address. 1. Code B'10110111 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 b11 to 0 b10 b9 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 Fixed to 0 b3 Fixed to 0 b2 Fixed to 0 b1 b0 MTRE Fixed RCLIP Fixed LINKE LREL AA (1) CLKW Note: Set the AA bit to 1. Rev. 1.00 Nov. 22, 2007 Page 1136 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters n (n = 1 to 65,535): Number of vertices DXn (n = 1 to 65,535): Rendering coordinate (relative coordinate). Negative number expressed as two's complement. DYn (n = 1 to 65,535): Rendering coordinate (relative coordinate). Negative number expressed as two's complement. LINK Address: LINK absolute address (Longword address. Write 0 to bits A31 to A29, A1, and A0.) LINK relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. (c) Description Performs antialiasing for the exterior frame of a polygon drawn using work reference, with a relative coordinate specification from the current pointer value. The CLKW bit specifies whether the order to give the n vertices is clockwise or counterclockwise: CLKW = 1 selects clockwise and CLKW = 0 selects counterclockwise. When clockwise is specified, the left image with respect to the drawing direction is referenced by antialiasing. On the other hand, the right image is referenced when counterclockwise is selected. When LINKE = 1, the vertex coordinates are read from the memory address specified by the LINK Address. The LINK Address can be specified through the LREL bit as an absolute address or a relative address with respect to the memory address at which the RLINED command code is located. This command can only be executed for a 16-bit/pixel destination. When a polygon used in work reference is drawn by the FTRAPC (RFTRAPC) command, perform drawing with both the EDG and EOS bits set to 1. The final coordinate point is stored as the current pointer values (XC, YC). Rev. 1.00 Nov. 22, 2007 Page 1137 of 1692 REJ09B0360-0100 Section 23 G2D Notes: 1. 8-point drawing is used. 2. The final point of each line segment is not drawn. When antialiasing is performed for the exterior frame of a polygon drawn by a POLYGON4 type command, the paths may not match. 3. When the starting and final coordinate points of a line segment match, nothing is drawn. 4. Antialiasing is not performed for horizontal, vertical, and 45-degree diagonal line segments, which are pre-clipped inside the G2D. 5. Clipping is performed on a pixel basis when either the referenced pixel or the pixel to be drawn is outside the clipping area, and antialiasing is not performed in such a case. 6. The final coordinate point before coordinate transformation is stored as the current pointer values (XC, YC). (d) Example n=5 (0, 0) (XC + DX1 + DX2 + DX3 + DX4 + DX5, YC + DY1 + DY2 + DY3 + DY4 + DY5) (XC, YC) (XC + DX1, YC + DY1) n=5 (0, 0) (XC + DX1 + DX2 + DX3 + DX4 + DX5, YC + DY1 + DY2 + DY3 + DY4 + DY5) (XC, YC) (XC + DX1 + DX2, YC + DY1 + DY2) (XC + DX1 + DX2 + DX3 + DX4, YC + DY1 + DY2 + DY3 + DY4) (XC + DX1 + DX2 + DX3, YC + DY1 + DY2 + DY3) (XC + DX1 + DX2 + DX3 + DX4, YC + DY1 + DY2 + DY3 + DY4) (XC + DX1 + DX2 + DX3, YC + DY1 + DY2 + DY3) (XC + DX1, YC + DY1) (XC + DX1 + DX2, YC + DY1 + DY2 Rendering coordinates CLKW = 1 CLKW = 0 Rendering coordinates Rev. 1.00 Nov. 22, 2007 Page 1138 of 1692 REJ09B0360-0100 Section 23 G2D 23.2.3 (1) (a) Work Screen Drawing Commands FTRAPC Function Draws a polygon at work coordinates. (b) Command Format • LINKE = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1101_0000 Reserve (all 0) Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (2 ≤ n ≤ 65535) Sign Xmin (-32768 ≤ Xmin ≤ 32767) Xmax (-32768 ≤ Xmax ≤ 32767) DX1 (-32768 ≤ DX1 ≤ 32767) : : DXn (-32768 ≤ DXn ≤ 32767) Ymin (-32768 ≤ Ymin ≤ 32767) Ymax (-32768 ≤ Ymax ≤ 32767) DY1 (-32768 ≤ DY1 ≤ 32767) : : DYn (-32768 ≤ DYn ≤ 32767) Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Note: When n = 0 or 1, correct operation is not guaranteed. • LINKE = 1 and LREL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1101_0000 Reserve (all 0) Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (2 ≤ n ≤ 65535) Sign Xmin (-32768 ≤ Xmin ≤ 32767) Xmax (-32768 ≤ Xmax ≤ 32767) 0 0 Ymin (-32768 ≤ Ymin ≤ 32767) Ymax (-32768 ≤ Ymax ≤ 32767) 0 0 Sign Sign 0 LINK Address (longword address) Notes: 1. When n = 0 or 1, correct operation is not guaranteed. 2. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by the LINK Address. Rev. 1.00 Nov. 22, 2007 Page 1139 of 1692 REJ09B0360-0100 Section 23 G2D • LINKE = 1 and LREL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1101_0000 Reserve (all 0) Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (2 ≤ n ≤ 65535) Sign Xmin (-32768 ≤ Xmin ≤ 32767) Xmax (-32768 ≤ Xmax ≤ 32767) Ymin (-32768 ≤ Ymin ≤ 32767) Ymax (-32768 ≤ Ymax ≤ 32767) 0 0 Sign Sign Sign extended Sign LINK Address (longword address) Notes: 1. When n = 0 or 1, correct operation is not guaranteed. 2. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by adding the address where the command code is located to the LINK Address. 1. Code B'11010000 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work O Draw Mode b15 b14 to 0 b13 CLIP b12 b11 to 0 b10 b9 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 BLKE (1) b4 EDG b3 b2 to 0 b1 Fixed to 0 b0 Fixed to 0 MTRE Fixed RCLIP Fixed LINKE LREL EOS Fixed Note: Set the BLKE bit to 1. Rev. 1.00 Nov. 22, 2007 Page 1140 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters n (n = 2 to 65,535): Xmin: Number of vertices Xmin value in the circumscribed quadrangle of the polygon. Work coordinate (absolute coordinate). Negative number expressed as two's complement. Ymin: Ymin value in the circumscribed quadrangle of the polygon. Work coordinate (absolute coordinate). Negative number expressed as two's complement. Xmax: Xmax value in the circumscribed quadrangle of the polygon. Work coordinate (absolute coordinate). Negative number expressed as two's complement. Ymax: Ymax value in the circumscribed quadrangle of the polygon. Work coordinate (absolute coordinate). Negative number expressed as two's complement. DXn (n = 2 to 65,535): Work coordinate (absolute coordinate). Negative number expressed as two's complement. DYn (n = 2 to 65,535): Work coordinate (absolute coordinate). Negative number expressed as two's complement. LINK Address: LINK absolute address (Longword address. Write 0 to bits A31 to A29, A1, and A0.) LINK relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. Rev. 1.00 Nov. 22, 2007 Page 1141 of 1692 REJ09B0360-0100 Section 23 G2D (c) Description Draws a polygon with n – 1 vertices at work coordinates. Paints n – 1 trapezoids at work coordinates using binary EOR, with X = Xmin as the left-hand side, and line segments (DX1, DY1) – (DX2, DY2), (DX2, DY2) – (DX3, DY3), ..., (DXn – 1, DYn – 1) – (DXn, DYn) as the right-hand sides, and with the top and bottom bases parallel to the X-axis. Bottom base drawing is not performed. Set (DXN, DYN) = (DX1, DY1) to give a closed figure. If the rendering attribute EDG bit is set to 1, an edge line is drawn after the paint operation. The line drawing data is selected with the EOS bit. The FTRAPC command performs coordinate transformation by internally obtaining the four vertices from the coordinates for the circumscribed quadrangle of the input polygon and then transforming the coordinates for these four vertices. The transformed four vertices are then internally converted into a circumscribed rectangle, the left edge obtained, and the polygon drawn. Note: When enabling edge drawing (EDG = 1), Z pre-clipping is not performed for the edge line. Rev. 1.00 Nov. 22, 2007 Page 1142 of 1692 REJ09B0360-0100 Section 23 G2D (d) Example n=5 (0, 0) (Xmin, Ymin) (DX1, DY1) (DX4, DY4) (DX2, DY2) (Xmax, Ymax) (DX3, DY3) Work coordinates Painting order Xmin Xmin Xmin Xmin Xmin Order of listing FTRAP parameters n Xmin,Ymin Xmax,Ymax DX1, DY1 DX2, DY2 DX3, DY3 DX4, DY4 DX1, DY1 Add the starting point at the end. Rev. 1.00 Nov. 22, 2007 Page 1143 of 1692 REJ09B0360-0100 Section 23 G2D (2) (a) RFTRAPC Function Draws a polygon at work coordinates with a relative coordinate specification from the current pointer value. (b) Command Format • LINKE = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1101_0100 Reserve (all 0) Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (1 ≤ n ≤ 65535) Sign Xmin (-32768 ≤ Xmin ≤ 32767) Xmax (-32768 ≤ Xmax ≤ 32767) DX2 (-128 ≤ DX2 ≤ 127) : : DXn (-128 ≤ DXn ≤ 127) Sign Ymin (-32768 ≤ Ymin ≤ 32767) Ymax (-32768 ≤ Ymax ≤ 32767) DX1 (-128 ≤ DX1 ≤ 127) : : DXn-1 (-128 ≤ DXn-1 ≤ 127) Sign Sign Sign Sign DY2 (-128 ≤ DY2 ≤ 127) : : DYn (-128 ≤ DYn ≤ 127) Sign DY1 (-128 ≤ DY1 ≤ 127) : : DYn-1 (-128 ≤ DYn-1 ≤ 127) Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Notes: 1. When n = 0, correct operation is not guaranteed. 2. When n is an odd number, insert a dummy word of 0 at the end. • LINKE = 1 and LREL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1101_0100 Reserve (all 0) Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (1 ≤ n ≤ 65535) Sign Xmin (-32768 ≤ Xmin ≤ 32767) Xmax (-32768 ≤ Xmax ≤ 32767) 0 0 Ymin (-32768 ≤ Ymin ≤ 32767) Ymax (-32768 ≤ Ymax ≤ 32767) 0 0 Sign Sign 0 LINK Address (longword address) Notes: 1. When n = 0, correct operation is not guaranteed. 2. When n is an odd number, insert a dummy word of 0 at the end. 3. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by the LINK Address. Rev. 1.00 Nov. 22, 2007 Page 1144 of 1692 REJ09B0360-0100 Section 23 G2D • LINKE = 1 and LREL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1101_0100 Reserve (all 0) Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) Draw Mode n (1 ≤ n ≤ 65535) Sign Xmin (-32768 ≤ Xmin ≤ 32767) Xmax (-32768 ≤ Xmax ≤ 32767) Ymin (-32768 ≤ Ymin ≤ 32767) Ymax (-32768 ≤ Ymax ≤ 32767) 0 0 Sign Sign Sign extended Sign LINK Address (longword address) Notes: 1. When n = 0, correct operation is not guaranteed. 2. When n is an odd number, insert a dummy word of 0 at the end. 3. The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by the address where the command code is located plus the LINK Address. 1. Code B'11010100 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work O Draw Mode b15 b14 to 0 b13 CLIP b12 b11 to 0 b10 b9 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 BLKE (1) b4 EDG b3 b2 to 0 b1 Fixed to 0 b0 Fixed to 0 MTRE Fixed RCLIP Fixed LINKE LREL EOS Fixed Note: Set the BLKE bit to 1. Rev. 1.00 Nov. 22, 2007 Page 1145 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters n (n = 1 to 65,535): Xmin: Number of vertices Xmin value in the circumscribed quadrangle of the polygon. Work coordinate (absolute coordinate). Negative number expressed as two's complement. Ymin: Ymin value in the circumscribed quadrangle of the polygon. Work coordinate (absolute coordinate). Negative number expressed as two's complement. Xmax: Xmax value in the circumscribed quadrangle of the polygon. Work coordinate (absolute coordinate). Negative number expressed as two's complement. Ymax: Ymax value in the circumscribed quadrangle of the polygon. Work coordinate (absolute coordinate). Negative number expressed as two's complement. DXn (n = 1 to 65,535): Work coordinate (relative coordinate). Negative number expressed as two's complement. DYn (n = 1 to 65,535): Work coordinate (relative coordinate). Negative number expressed as two's complement. LINK Address: LINK absolute address (Longword address. Write 0 to bits A31 to A29, A1, and A0.) LINK relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. Rev. 1.00 Nov. 22, 2007 Page 1146 of 1692 REJ09B0360-0100 Section 23 G2D (c) Description Draws a polygon with n – 1 vertices at work coordinates. Paints n – 1 trapezoids at work coordinates using binary EOR, with X = Xmin as the left-hand side, and line segments specified by the relative shift (DX, DY) from the current pointer values (XC, YC) ((XC, YC) – (XC + DX1, YC + DY1), (XC + DX1, YC + DY1) – (XC + DX1 + DX2, YC + DY1 + DY2), ..., (XC + ... + DXn – 1, YC + ... + DYn – 1) – (XC + ... + DXn – 1 + DXn, YC + ...+ DYn – 1 + DYn)) as the right-hand sides, and with the top and bottom bases parallel to the X-axis. Bottom base drawing is not performed. The final coordinate point is stored as the current pointer values (XC, YC). Set (DX1 + DX2 + ...+ DXn = 0, DY1 + DY2 + ... + DYn = 0) to give a closed figure. If the rendering attribute EDG bit is set to 1, an edge line is drawn after the paint operation. The line drawing data is selected with the EOS bit. The RFTRAPC command performs coordinate transformation by internally obtaining the four vertices from the coordinates for the circumscribed quadrangle of the input polygon and then transforming the coordinates for these four vertices. The transformed four vertices are then internally converted into a circumscribed rectangle, the left edge obtained, and the polygon drawn. Notes: 1. The final coordinate point before coordinate transformation is stored as the current pointer values (XC, YC). 2. When enabling edge drawing (EDG = 1), Z pre-clipping is not performed for the edge line. Rev. 1.00 Nov. 22, 2007 Page 1147 of 1692 REJ09B0360-0100 Section 23 G2D (d) Example n=4 (0, 0) (XC + DX1 + DX2 + DX3 + DX4, YC + DY1 + DY2 + DY3 + DY4) (Xmin, Ymin) (XC, YC) (XC + DX1, YC + DY1) (XC + DX1 + DX2 + DX3, YC + DY1 + DY2 + DY3) (Xmax, Ymax) (XC + DX1 + DX2, YC + DY1 + DY2) Work coordinates Painting order Xmin Xmin Xmin Xmin Xmin Rev. 1.00 Nov. 22, 2007 Page 1148 of 1692 REJ09B0360-0100 Section 23 G2D (3) (a) CLRWC Function Clear the work coordinates to 0. (b) Command Format 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1110_0000 Sign Reserve (all 0) Sign Draw Mode Ymin (-32768 ≤ Ymin ≤ 32767) Ymax (-32768 ≤ Ymax ≤ 32767) Xmin (-32768 ≤ Xmin ≤ 32767) Xmax (-32768 ≤ Xmax ≤ 32767) Sign Sign 1. Code B'11100000 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work O Draw Mode b15 b14 to 0 b13 CLIP b12 b11 to 0 b10 Fixed to 0 b9 Fixed to 0 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 (1) b4 to 0 b3 Fixed to 0 b2 Fixed to 0 b1 Fixed to 0 b0 Fixed to 0 MTRE Fixed RCLIP Fixed BLKE Fixed Note: Set the BLKE bit to 1. 3. Command Parameters Xmin, Xmax: Ymin, Ymax: Left and right X coordinate values. Work coordinates (absolute coordinates. Negative numbers expressed as two's complement. Upper and lower Y coordinate values. Work coordinates (absolute coordinates. Negative numbers expressed as two's complement. Rev. 1.00 Nov. 22, 2007 Page 1149 of 1692 REJ09B0360-0100 Section 23 G2D (c) Description Zero-clears the area specified by upper-left coordinates (Xmin, Ymin) and lower-right coordinates (Xmax, Ymax) at work coordinates. The CLRWC command performs coordinate transformation by internally obtaining the four vertices from the left and right X coordinate values and upper and lower Y coordinate values, and then transforming the coordinates for these four vertices. The transformed four vertices are then internally converted into a circumscribed rectangle and the polygon drawn. (d) Example (0, 0) (XMIN, YMIN) (XMAX, YMAX) Work coordinates Rev. 1.00 Nov. 22, 2007 Page 1150 of 1692 REJ09B0360-0100 Section 23 G2D 23.2.4 (1) (a) Work Line Drawing Commands LINEWC Function Draws a polygon at work coordinates. (b) Command Format 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1111_0000 Reserve (all 0) Sign Reserve (all 0) Draw Mode n (2 ≤ n ≤ 65535) Sign DX1 (-32768 ≤ DX1 ≤ 32767) : : DXn (-32768 ≤ DXn ≤ 32767) DY1 (-32768 ≤ DY1 ≤ 32767) : : DYn (-32768 ≤ DYn ≤ 32767) Sign Sign Sign Sign Sign Sign Note: When n = 0 or 1, correct operation is not guaranteed. 1. Code B'11110000 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work Specified Color O (EOS of binary work) Drawing Destination Rendering Work O Draw Mode b15 b14 to 0 b13 CLIP b12 b11 to 0 b10 Fixed to 0 b9 Fixed to 0 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 Fixed to 0 b3 EOS b2 Fixed to 0 b1 Fixed to 0 b0 Fixed to 0 MTRE Fixed RCLIP Fixed Rev. 1.00 Nov. 22, 2007 Page 1151 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters n (n = 2 to 65,535): Number of vertices DXn (n = 2 to 65,535): Work coordinate (absolute coordinate). Negative number expressed as two's complement. DYn (n = 2 to 65,535): Work coordinate (absolute coordinate). Negative number expressed as two's complement. (c) Description Performs binary drawing at work coordinates of a polygonal line from vertex 1 (DX1, DY1), through vertex 2 (DX2, DY2), ...., vertex n – 1 (DXn – 1, DYn – 1), to vertex n (DXn, DYn). 0 drawing or 1 drawing is selected with the drawing mode EOS bit. Drawing is performed at work coordinates with 0 when EOS = 0, and at work coordinates with 1 when EOS = 1 (Used for edge drawing at work coordinates for a polygonal painted figure). Note: 8-point drawing is used. The final point of each line segment is drawn. (d) Example n=3 (0, 0) (DX2, DY2) (DX1, DY1) (DX3, DY3) Work coordinates Rev. 1.00 Nov. 22, 2007 Page 1152 of 1692 REJ09B0360-0100 Section 23 G2D (2) (a) RLINEWC Function Draws a 1-bit-wide solid line at work coordinates with a relative coordinate specification from the current pointer value. (b) Command Format 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1111_0100 Reserve (all 0) Sign Reserve (all 0) Draw Mode n (1 ≤ n ≤ 65535) Sign DX2 (-128 ≤ DX2 ≤ 127) : : DXn (-128 ≤ DXn ≤ 127) Sign DY2 (-128 ≤ DY2 ≤ 127) : : DYn (-128 ≤ DYn ≤ 127) DX1 (-128 ≤ DX1 ≤ 127) : : DXn-1 (-128 ≤ DXn-1 ≤ 127) Sign DY1 (-128 ≤ DY1 ≤ 127) : : DYn-1 (-128 ≤ DYn-1 ≤ 127) Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Sign Notes: 1. When n = 0, correct operation is not guaranteed. 2. When n is an odd number, insert a dummy word of 0 at the end. 1. Code B'11110100 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work Specified Color O (EOS of binary work) Drawing Destination Rendering Work O Draw Mode b15 b14 to 0 b13 CLIP b12 b11 to 0 b10 Fixed to 0 b9 Fixed to 0 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 Fixed to 0 b3 EOS b2 Fixed to 0 b1 Fixed to 0 b0 Fixed to 0 MTRE Fixed RCLIP Fixed Rev. 1.00 Nov. 22, 2007 Page 1153 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters n (n = 1 to 65,535): Number of vertices DXn (n = 1 to 65,535): Work coordinate (relative coordinate). Negative number expressed as two's complement. DYn (n = 1 to 65,535): Work coordinate (relative coordinate). Negative number expressed as two's complement. (c) Description Performs binary drawing at work coordinates of a polygonal line comprising line segments (XC, YC) – (XC + DX1, YC + DY1), (XC + DX1, YC + DY1) – (XC + DX1 + DX2, YC + DY1 + DY2), ..., (XC + ... + DXn – 1, YC + ... + DYn – 1) – (XC + ... + DXn – 1 + DXn, YC + ... + DYn – 1 + DYn) to the coordinates specified by the relative shift (DX, DY) from the current pointer values (XC, YC). 0 drawing or 1 drawing is selected with the drawing mode EOS bit. Drawing is performed at work coordinates with 0 when EOS = 0, and at work coordinates with 1 when EOS = 1. (Used for edge drawing at work coordinates for a polygonal painted figure.) The final coordinate point is stored as the current pointer values (XC, YC). Notes: 1. 8-point drawing is used. The end of a line is drawn. 2. The final coordinate point before coordinate transformation is stored as the current pointer values (XC, YC). (d) Example n=2 (0, 0) (XC + DX1, YC + DY1) DX1 DY1 DX2 DY2 (XC, YC) (XC + DX1 + DX2, YC + DY1 + DY2) Work coordinates Rev. 1.00 Nov. 22, 2007 Page 1154 of 1692 REJ09B0360-0100 Section 23 G2D 23.2.5 (1) (a) Rectangle Drawing Commands BITBLTA Function Transfers multi-valued (8- or 16-bit/pixel) rectangle source data to the destination area. (b) Command Format • SS = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1010_0010 Reserve (all 0) 0 0 0 Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) 0 0 0 0 Sign Draw Mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROP 0 0 0 0 0 0 0 0 0 TXS (0 ≤ TXS ≤ 4088) LW (0 ≤ LW ≤ 4094) TH (0 ≤ TH ≤ 4094) BXC (-32768 ≤ BXC ≤ 32767) TYS (0 ≤ TYS ≤ 4095) RW (0 ≤ RW ≤ 4094) BH (0 ≤ BH ≤ 4094) BYC (-32768 ≤ BYC ≤ 32767) Notes: 1. 0 ≤ TXS ≤ SSTRR − (LW + RW + 1), 0 ≤ TYS ≤ 4096 − (TH + BH + 1) (SSTRR: Source stride register setting) 2. 8 ≤ LW + RW + 1 ≤ 4095, 1 ≤ TH + BH + 1 ≤ 4095 3. −32768 ≤ BXC − LW ≤ 32767, −32768 ≤ BYC − TH ≤ 32767, −32768 ≤ BXC + RW ≤ 32767, −32768 ≤ BYC + BH ≤ 32767 • SS = 0 and REL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1010_0010 Reserve (all 0) 0 0 0 Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) 0 0 0 0 0 0 Draw Mode 0 0 ROP 0 RW (0 ≤ RW ≤ 4087) BH (0 ≤ BH ≤ 4094) BYC (-32768 ≤ BYC ≤ 32767) 0 0 0 0 0 0 0 0 0 0 Base Address (quad word address) LW (0 ≤ LW ≤ 4087) TH (0 ≤ TH ≤ 4094) BXC (-32768 ≤ BXC ≤ 32767) 0 0 Sign 0 0 0 0 0 0 Notes: 1. 8 ≤ LW + RW + 1 ≤ 4088 (multiple of 8), 1 ≤ TH + BH + 1 ≤ 4095 2. −32768 ≤ BXC − LW ≤ 32767, −32768 ≤ BYC − TH ≤ 32767, −32768 ≤ BXC + RW ≤ 32767, −32768 ≤ BYC + BH ≤ 32767 Rev. 1.00 Nov. 22, 2007 Page 1155 of 1692 REJ09B0360-0100 Section 23 G2D • SS = 0 and REL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1010_0010 Reserve (all 0) Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) 0 0 0 0 0 0 Draw Mode 0 0 ROP 0 RW (0 ≤ RW ≤ 4087) BH (0 ≤ BH ≤ 4094) BYC (-32768 ≤ BYC ≤ 32767) 0 Base Address (longword address) LW (0 ≤ LW ≤ 4087) TH (0 ≤ TH ≤ 4094) BXC (-32768 ≤ BXC ≤ 32767) 0 0 Sign 0 0 Sign 0 0 0 0 0 0 0 0 0 0 0 0 Notes: 1. 8 ≤ LW + RW + 1 ≤ 4088 (multiple of 8), 1 ≤ TH + BH + 1 ≤ 4095 2. −32768 ≤ BXC − LW ≤ 32767, −32768 ≤ BYC − TH ≤ 32767, −32768 ≤ BXC + RW ≤ 32767, −32768 ≤ BYC + BH ≤ 32767 3. Adding the address (longword: 32-bit units) where the command code is located to the Base Address (longword: 32-bit units) must result in a quad word address (64-bit units). 1. Code B'10100010 2. Rendering Attributes Reference Data Multi-Valued Source O Binary Source Binary Work O (only WORK = 1) Drawing Destination Specified Color Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 RCLIP b11 b10 b9 WORK b8 SS b7 REL b6 SRCDIRX b5 SRCDIRY b4 DSTDIRX b3 DSTDIRY b2 b1 b0 SαE MTRE Fixed STRANS DTRANS COOF αE Rev. 1.00 Nov. 22, 2007 Page 1156 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters TXS, TYS: Base Address: Source starting point. Write 0 to the unused bits. Source start absolute address (Quad word address. Write 0 to bits A31 to A29 and A2 to A0.) Source start relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. BXC, BYC: LW, RW: Center X and Y coordinate values. Rendering coordinates (absolute coordinates). Negative numbers expressed as two's complement. Left and right widths. Relative value from (BXC, BYC). Rendering coordinates. Make the setting in pixel units. Write 0 to the unused bits. Top and bottom heights. Relative value from (BXC, BYC). Rendering coordinates. Make the setting in pixel units. Write 0 to the unused bits. Raster operation code TH, BH: ROP: (c) Description Transfers multi-valued (8- or 16-bit/pixel) rectangle source data to rendering coordinates. When SS = 0, set the (LW + RW + 1) value to be a multiple of 8 pixels. When SS = 1, set the (LW + RW + 1) value to be 8 or more pixels. 1. When work specification is selected as a rendering attribute (WORK = 1), only places where the work coordinate pixel is 1 are drawn at rendering coordinates while referencing work coordinates for the same coordinates as the rendering coordinates. 2. When SS = 1, the source data is referenced from the 2-dimensional source area. When SS = 0, the source data is referenced from the Base Address in the display list. When REL = 0, the source address can be specified as an absolute address. When REL = 1, the source address can be specified as a relative address with respect to the memory address at which the BITBLTA command code is located. 3. In 16-bit/pixel drawing, if the rendering attribute COOF bit is set to 1, the result of adding the value in COFSR to the value of the multi-valued source data is drawn. The operation is performed by saturation processing. In 8-bit/pixel drawing, the COOF bit should be cleared to 0. Rev. 1.00 Nov. 22, 2007 Page 1157 of 1692 REJ09B0360-0100 Section 23 G2D 4. The direction to reference the source data can be selected by the SRCDIRX and SRCDIRY bits. 5. The drawing direction can be selected by the DSTDIRX and DSTDIRY bits. 6. When αE = 1, the source data and ground data are alpha blended before drawing. When setting αE = 1, also set the ROP code = H'CC (source copy). The A value in the ARGB format is not alpha blended. The A value is drawn according to the source A value use (SAU) and A value (AVALUE) bits in the rendering control register (RCLR). Alpha blending is valid only in 16bit/pixel drawing. 7. 16 raster operations are possible. The A value in the ARGB format is not subject to raster operations. The A value is drawn according to the source A value use (SAU) and A value (AVALUE) bits in the rendering control register (RCLR). Note: System clipping or (relative) user clipping is performed when drawing a rectangle. Z clipping is performed only at the center coordinates. (d) Example SS = 1 X SSAR Source stride Y (TXS, TYS) LW + RW + 1 (BXC, BYC) (BXC - LW, BYC - TH) LW RW TH BH TH + BH + 1 (BXC + RW, BYC + BH) 2-dimensional source coordinates Rendering coordinates SS = 0 LW + RW + 1 Base Address TH + BH + 1 Rev. 1.00 Nov. 22, 2007 Page 1158 of 1692 REJ09B0360-0100 Section 23 G2D (2) (a) BITBLTB Function Transfers binary (1-bit/pixel) rectangle source data that has been color expanded to the destination area. (b) Command Format • SS = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1010_0001 Reserve (all 0) Color1 0 0 0 Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) 0 0 0 0 0 0 Draw Mode 0 0 Color0 0 0 0 Sign ROP 0 0 0 0 0 0 0 0 0 TXS (0 ≤ TXS ≤ 4088) LW (0 ≤ LW ≤ 4087) TH (0 ≤ TH ≤ 4094) BXC (-32768 ≤ BXC ≤ 32767) 0 0 0 0 0 0 0 0 0 TYS (0 ≤ TYS ≤ 4095) RW (0 ≤ RW ≤ 4087) BH (0 ≤ BH ≤ 4094) BYC (-32768 ≤ BYC ≤ 32767) Notes: 1. 0 ≤ TXS ≤ SSTRR − (LW + RW + 1), 0 ≤ TYS ≤ 4096 − (TH + BH + 1) (SSTRR: Source stride register setting) 2. 8 ≤ LW + RW + 1 ≤ 4088 (multiple of 8), 1 ≤ TH + BH + 1 ≤ 4095 3. −32768 ≤ BXC − LW ≤ 32767, −32768 ≤ BYC − TH ≤ 32767, −32768 ≤ BXC + RW ≤ 32767, −32768 ≤ BYC + BH ≤ 32767 • SS = 0 and REL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1010_0001 Reserve (all 0) Color1 0 0 0 Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) 0 0 0 0 0 0 Draw Mode 0 0 Color0 ROP 0 0 0 0 0 0 0 0 Base Address (quad word address) LW (0 ≤ LW ≤ 4087) TH (0 ≤ TH ≤ 4094) BXC (-32768 ≤ BXC ≤ 32767) 0 0 Sign 0 RW (0 ≤ RW ≤ 4087) BH (0 ≤ BH ≤ 4094) BYC (-32768 ≤ BYC ≤ 32767) 0 0 0 0 0 0 0 0 Notes: 1. 8 ≤ LW + RW + 1 ≤ 4088 (multiple of 8), 1 ≤ TH + BH + 1 ≤ 4095 2. −32768 ≤ BXC − LW ≤ 32767, −32768 ≤ BYC − TH ≤ 32767, −32768 ≤ BXC + RW ≤ 32767, −32768 ≤ BYC + BH ≤ 32767 Rev. 1.00 Nov. 22, 2007 Page 1159 of 1692 REJ09B0360-0100 Section 23 G2D • SS = 0 and REL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1010_0001 Reserve (all 0) Color1 Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) 0 0 0 0 0 0 Draw Mode 0 0 Color0 ROP Base Address (longword address) LW (0 ≤ LW ≤ 4087) TH (0 ≤ TH ≤ 4094) BXC (-32768 ≤ BXC ≤ 32767) 0 0 Sign 0 RW (0 ≤ RW ≤ 4087) BH (0 ≤ BH ≤ 4094) 0 0 0 Sign 0 0 0 0 0 0 0 0 0 0 0 0 BYC (-32768 ≤ BYC ≤ 32767) Notes: 1. 8 ≤ LW + RW + 1 ≤ 4088 (multiple of 8), 1 ≤ TH + BH + 1 ≤ 4095 2. −32768 ≤ BXC − LW ≤ 32767, −32768 ≤ BYC − TH ≤ 32767, −32768 ≤ BXC + RW ≤ 32767, −32768 ≤ BYC + BH ≤ 32767 3. Adding the address (longword: 32-bit units) where the command code is located to the Base Address (longword: 32-bit units) must result in a quad word address (64-bit units). 1. Code B'10100001 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work O O (only WORK = 1) Drawing Destination Specified Color Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 RCLIP b11 b10 b9 WORK b8 SS b7 REL b6 SRCDIRX b5 SRCDIRY b4 DSTDIRX b3 DSTDIRY b2 b1 b0 Fixed to 0 MTRE Fixed STRANS DTRANS COOF αE Rev. 1.00 Nov. 22, 2007 Page 1160 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters TXS, TYS: Base Address: Source starting point. Write 0 to the unused bits. Source start absolute address (Quad word address. Write 0 to bits A31 to A29 and A2 to A0.) Source start relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. BXC, BYC: LW, RW: Center X and Y coordinate values. Rendering coordinates (absolute coordinates). Negative numbers expressed as two's complement. Left and right widths. Relative value from (BXC, BYC). Rendering coordinates. Make the setting in pixel units. Write 0 to the unused bits. Top and bottom heights. Relative value from (BXC, BYC). Rendering coordinates. Make the setting in pixel units. Write 0 to the unused bits. Raster operation code 8- or 16-bit/pixel color specification. For 16-bit/pixel drawing, the color specification should match the destination pixel format. For 8-bit/pixel drawing, the same value should be set in the upper and lower bytes. TH, BH: ROP: Color0, Color1: (c) Description Transfers binary (1-bit/pixel) rectangle source data to rendering coordinates. A multiple of 8 pixels must be set as the (LW + RW + 1) value, regardless of the SS bit value. 1. When work specification is selected as a rendering attribute (WORK = 1), only places where the work coordinate pixel is 1 are drawn at rendering coordinates while referencing work coordinates for the same coordinates as the rendering coordinates. 2. The binary source data is arranged in memory in linear fashion. When REL = 0, the source address can be specified as an absolute address. When REL = 1, the source address can be specified as a relative address with respect to the memory address at which the BITBLTB command code is located. 3. In 16-bit/pixel drawing, if the rendering attribute COOF bit is set to 1, the result of adding the value in COFSR to the value of the binary source data that has been color expanded is drawn. Rev. 1.00 Nov. 22, 2007 Page 1161 of 1692 REJ09B0360-0100 Section 23 G2D 4. 5. 6. 7. The operation is performed by saturation processing. In 8-bit/pixel drawing, the COOF bit should be cleared to 0. The direction to reference the source data can be selected by the SRCDIRX and SRCDIRY bits. The drawing direction can be selected by the DSTDIRX and DSTDIRY bits. When αE = 1, the data obtained by color expanding the binary source data and the ground data are alpha blended before drawing. When setting αE = 1, also set the ROP code = H'CC (source copy). The A value in the ARGB format is not alpha blended. The A value is drawn according to the source A value use (SAU) and A value (AVALUE) bits in the rendering control register (RCLR). Alpha blending is valid only in 16-bit/pixel drawing. 16 raster operations are possible. The A value in the ARGB format is not subject to raster operations. The A value is drawn according to the source A value use (SAU) and A value (AVALUE) bits in the rendering control register (RCLR). Note: System clipping or (relative) user clipping is performed when drawing a rectangle. Z clipping is performed only at the center coordinates. (d) Example X LW + RW + 1 Base Address Y (BXC - LW, BYC - TH) LW TH + BH + 1 (BXC, BYC) RW TH BH COLOR1 COLOR0 (BXC + RW, BYC + BH) Rendering coordinates Rev. 1.00 Nov. 22, 2007 Page 1162 of 1692 REJ09B0360-0100 Section 23 G2D (3) (a) BITBLTC Function Draws a rectangle with a monochrome specification to the destination area. (b) Command Format 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 1010_0000 Reserve (all 0) Reserve (all 0) 0 0 Sign Reserve (all 0) 0 0 0 0 0 0 Draw Mode 0 0 Color 0 0 Sign ROP 0 0 0 0 0 0 LW (0 ≤ LW ≤ 4094) TH (0 ≤ TH ≤ 4094) BXC (-32768 ≤ BXC ≤ 32767) 0 0 0 0 0 0 RW (0 ≤ RW ≤ 4094) BH (0 ≤ BH ≤ 4094) BYC (-32768 ≤ BYC ≤ 32767) Notes: 1. 1 ≤ LW + RW + 1 ≤ 4095, 1 ≤ TH + BH + 1 ≤ 4095 2. −32768 ≤ BXC − LW ≤ 32767, −32768 ≤ BYC − TH ≤ 32767, −32768 ≤ BXC + RW ≤ 32767, −32768 ≤ BYC + BH ≤ 32767 1. Code B'10100000 2. Rendering Attributes Reference Data Multi-Valued Source Binary Source Binary Work O (only WORK = 1) Drawing Destination Specified Color O Rendering O Work Draw Mode b15 b14 to 0 b13 CLIP b12 b11 to 0 b10 DTRANS b9 WORK b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 DSTDIRX b3 DSTDIRY b2 b1 b0 Fixed to 0 MTRE Fixed RCLIP Fixed COOF αE Rev. 1.00 Nov. 22, 2007 Page 1163 of 1692 REJ09B0360-0100 Section 23 G2D 3. Command Parameters BXC, BYC: LW, RW: TH, BH: Color: ROP: (c) Description Center X and Y coordinate values. Rendering coordinates (absolute coordinates). Negative numbers expressed as two's complement. Left and right widths. Relative value from (BXC, BYC). Rendering coordinates. Make the setting in pixel units. Write 0 to the unused bits. Top and bottom heights. Relative value from (BXC, BYC). Rendering coordinates. Make the setting in pixel units. Write 0 to the unused bits. 8- or 16-bit/pixel color specification. For 16-bit/pixel drawing, the color specification should match the destination pixel format. For 8-bit/pixel drawing, the same value should be set in the upper and lower bytes. Raster operation code Draws a rectangle in the destination area in the single color specified by the Color parameter. 1. When work specification is selected as a rendering attribute (WORK = 1), only places where the work coordinate pixel is 1 are drawn at rendering coordinates while referencing work coordinates for the same coordinates as the rendering coordinates. 2. In 16-bit/pixel drawing, if the rendering attribute COOF bit is set to 1, the result of adding the value in COFSR to the value of the specified color is drawn. The operation is performed by saturation processing. In 8-bit/pixel drawing, the COOF bit should be cleared to 0. 3. The drawing direction can be selected by the DSTDIRX and DSTDIRY bits. 4. When αE = 1, the specified color data and ground data are alpha blended before drawing. When setting αE = 1, also set the ROP code = H'CC (source copy). The A value in the ARGB format is not alpha blended. The A value is drawn according to the source A value use (SAU) and A value (AVALUE) bits in the rendering control register (RCLR). Alpha blending is valid only in 16-bit/pixel drawing. 5. 16 raster operations are possible. The A value in the ARGB format is not subject to raster operations. The A value is drawn according to the source A value use (SAU) and A value (AVALUE) bits in the rendering control register (RCLR). Note: System clipping or (relative) user clipping is performed when drawing a rectangle. Z clipping is performed only at the center coordinates. Rev. 1.00 Nov. 22, 2007 Page 1164 of 1692 REJ09B0360-0100 Section 23 G2D (d) Example X Y (BXC - LW, BYC - TH) LW COLOR (BXC, BYC) RW TH BH (BXC + RW, BYC + BH) Rendering coordinates Rev. 1.00 Nov. 22, 2007 Page 1165 of 1692 REJ09B0360-0100 Section 23 G2D 23.2.6 (1) (a) Control Commands MOVE Function Sets the current pointer. (b) Command Format 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0100_1000 Reserve (all 0) Draw Mode YC (-32768 ≤ YC ≤ 32767) XC (-32768 ≤ XC ≤ 32767) 1. Code B'01001000 2. Rendering Attributes Draw Mode b15 Fixed to 0 b14 Fixed to 0 b13 Fixed to 0 b12 Fixed to 0 b11 Fixed to 0 b10 Fixed to 0 b9 Fixed to 0 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 Fixed to 0 b3 Fixed to 0 b2 Fixed to 0 b1 Fixed to 0 b0 Fixed to 0 3. Command Parameters XC: YC: Rendering coordinate (absolute coordinate) or work coordinate (absolute coordinate). Negative number expressed as two's complement. Rendering coordinate (absolute coordinate) or work coordinate (absolute coordinate). Negative number expressed as two's complement. Rev. 1.00 Nov. 22, 2007 Page 1166 of 1692 REJ09B0360-0100 Section 23 G2D (c) Description Sets the values obtained by adding the local offset values to XC and YC in the current pointers. XC and YC are set as absolute coordinates. The current pointers are used by relative drawing commands only. After issuing a MOVE command, use relative drawing commands in succession. If an absolute drawing command is used during this sequence, the current pointers will be used as registers for internal computation, and the current pointer values will be lost. A MOVE command must be therefore be issued before using relative drawing commands again. (d) Example (0, 0) (XC, YC) Work coordinates Rendering coordinates (2) (a) RMOVE Function Adds XC and YC to the current pointers. (b) Command Format 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0100_1100 Reserve (all 0) Draw Mode YC (-32768 ≤ YC ≤ 32767) XC (-32768 ≤ XC ≤ 32767) 1. Code B'01001100 Rev. 1.00 Nov. 22, 2007 Page 1167 of 1692 REJ09B0360-0100 Section 23 G2D 2. Rendering Attributes Draw Mode b15 Fixed to 0 b14 Fixed to 0 b13 Fixed to 0 b12 Fixed to 0 b11 Fixed to 0 b10 Fixed to 0 b9 Fixed to 0 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 Fixed to 0 b3 Fixed to 0 b2 Fixed to 0 b1 Fixed to 0 b0 Fixed to 0 3. Command Parameters XC: YC: Rendering coordinate (relative coordinate) or work coordinate (relative coordinate). Negative number expressed as two's complement. Rendering coordinate (relative coordinate) or work coordinate (relative coordinate). Negative number expressed as two's complement. (c) Description Adds XC and YC to the current pointers. (d) Example (0, 0) Former (XC, YC) XC YC (former XC + XC, former YC + YC) Work coordinates Rendering coordinates Rev. 1.00 Nov. 22, 2007 Page 1168 of 1692 REJ09B0360-0100 Section 23 G2D (3) (a) LCOFS Function Sets the offset values (local offset) of the destination area and work area. (b) Command Format 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0100_0000 Reserve (all 0) Draw Mode YO (-32768 ≤ YO ≤ 32767) XO (-32768 ≤ XO ≤ 32767) 1. Code B'01000000 2. Rendering Attributes Draw Mode b15 Fixed to 0 b14 Fixed to 0 b13 Fixed to 0 b12 Fixed to 0 b11 Fixed to 0 b10 Fixed to 0 b9 Fixed to 0 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 Fixed to 0 b3 Fixed to 0 b2 Fixed to 0 b1 Fixed to 0 b0 Fixed to 0 3. Command Parameters XO: YO: Local offset value. Rendering coordinate (absolute coordinate) or work coordinate (absolute coordinate). Negative number expressed as two's complement. Local offset value. Rendering coordinate (absolute coordinate) or work coordinate (absolute coordinate). Negative number expressed as two's complement. Rev. 1.00 Nov. 22, 2007 Page 1169 of 1692 REJ09B0360-0100 Section 23 G2D (c) Description After the local offset values are set, these offset values are added in all subsequent coordinate specifications made in drawing commands. These settings must be made at the start of the display list (the initial values are undefined). To reflect the local offset values in the current pointers, issue a MOVE command after the LCOFS command. (d) Example (0, 0) (XO + DX2, YO + DY2) (XO, YO) LINE (XO + DX1, YO + DY1) Work coordinates Rendering coordinates Rev. 1.00 Nov. 22, 2007 Page 1170 of 1692 REJ09B0360-0100 Section 23 G2D (4) (a) RLCOFS Function Adds XO and YO to the local offset. (b) Command Format 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0100_0100 Reserve (all 0) Draw Mode YO (-32768 ≤ YO ≤ 32767) XO (-32768 ≤ XO ≤ 32767) 1. Code B'01000100 2. Rendering Attributes Draw Mode b15 Fixed to 0 b14 Fixed to 0 b13 Fixed to 0 b12 Fixed to 0 b11 Fixed to 0 b10 Fixed to 0 b9 Fixed to 0 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 Fixed to 0 b3 Fixed to 0 b2 Fixed to 0 b1 Fixed to 0 b0 Fixed to 0 3. Command Parameters XO: YO: Local offset value. Rendering coordinate (relative coordinate) or work coordinate (relative coordinate). Negative number expressed as two's complement. Local offset value. Rendering coordinate (relative coordinate) or work coordinate (relative coordinate). Negative number expressed as two's complement. (c) Description Adding X0 and Y0 to the local offset makes the local offset values. After the local offset values are set, these offset values are added in all subsequent coordinate specifications made in drawing commands. To reflect the local offset values in the current pointers, issue a MOVE command after setting the local offset with the LCOFS or RLCOFS command. Rev. 1.00 Nov. 22, 2007 Page 1171 of 1692 REJ09B0360-0100 Section 23 G2D (d) Example (0, 0) XO Former (XO, YO) YO LINE (former XO + XO, former YO + YO) (former XO + XO + DX1, former YO + YO + DY1) Work coordinates Rendering coordinates Rev. 1.00 Nov. 22, 2007 Page 1172 of 1692 REJ09B0360-0100 Section 23 G2D (5) (a) WPR Function Sets a value in a specific address-mapped register. (b) Command Format • LINKE = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0001_1000 Reserve (all 0) Reserve (all 0) n – 1 (0 ≤ n – 1 ≤ 255) 0 Data0 : : Data n–1 0 0 0 8 7 6 5 4 3 2 1 0 Draw Mode W Reg No • LINKE = 1 and LREL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0001_1000 Reserve (all 0) 0 0 0 Reserve (all 0) n – 1 (0 ≤ n – 1 ≤ 255) 0 0 0 0 8 7 6 5 4 3 2 1 0 Draw Mode W Reg No 0 0 LINK Address (longword address) Note: The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by the LINK Address. • LINKE = 1 and LREL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0001_1000 Reserve (all 0) Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) n – 1 (0 ≤ n – 1 ≤ 255) 0 0 0 0 Draw Mode W Reg No 0 0 LINK Address (longword address) Note: The longword address following the LINK Address is handled as the next command code. Therefore, do not specify the longword address following the address where the LINK Address is to be assigned as the link destination address specified by the address where the command code is located plus the LINK Address. Rev. 1.00 Nov. 22, 2007 Page 1173 of 1692 REJ09B0360-0100 Section 23 G2D 1. Code B'00011000 2. Rendering Attributes Draw Mode b15 Fixed to 0 b14 Fixed to 0 b13 Fixed to 0 b12 Fixed to 0 b11 Fixed to 0 b10 b9 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 Fixed to 0 b3 b2 b1 b0 LINKE LREL ByteM3 ByteM2 ByteM1 ByteM0 3. Command Parameters W reg No: Data n (n = 1 to 256): n − 1: LINK Address: Register number Write data The number of write data LINK absolute address (Longword address. Write 0 to bits A31 to A29, A1, and A0.) LINK relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. (c) Description Writes data to the address-mapped registers. The register number is set in W reg No, and the write data in Data n. Also ensure that there is no conflict with access by the CPU. 1. When the LINKE bit is set to 1, data is read from the memory address specified by the LINK Address and written to a register. 2. The LINK Address can be specified through the LREL bit as an absolute address or a relative address with respect to the memory address at which the WPR command code is located. 3. Setting the ByteM3 to ByteM0 bits to 1 allows writing to a register to be masked in byte units. Rev. 1.00 Nov. 22, 2007 Page 1174 of 1692 REJ09B0360-0100 Section 23 G2D (6) (a) JUMP Function Changes the display list fetch destination. (b) Command Format • REL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0010_1000 0 0 0 Reserve (all 0) JUMP Address (longword address) 8 7 6 5 4 3 2 1 0 Draw Mode 0 0 • REL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0010_1000 Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) JUMP Address (longword address) Draw Mode 0 0 1. Code B'00101000 2. Rendering Attributes Draw Mode b15 Fixed to 0 b14 Fixed to 0 b13 Fixed to 0 b12 Fixed to 0 b11 Fixed to 0 b10 Fixed to 0 b9 Fixed to 0 b8 Fixed to 0 b7 REL b6 Fixed to 0 b5 Fixed to 0 b4 Fixed to 0 b3 Fixed to 0 b2 Fixed to 0 b1 Fixed to 0 b0 Fixed to 0 3. Command Parameter JUMP Address: Jump destination absolute address (Longword address. Write 0 to bits A31 to A29, A1, and A0.) Jump destination relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. Rev. 1.00 Nov. 22, 2007 Page 1175 of 1692 REJ09B0360-0100 Section 23 G2D (c) Description Changes the display list fetch destination to the specified address. When REL = 0, the jump destination address can be specified as an absolute address. When REL = 1, the jump destination address can be specified as a relative address with respect to the memory address at which the command code is located. (d) Example Display list area Register setting command Drawing starts Drawing command JUMP command : : Drawing command Drawing command Rev. 1.00 Nov. 22, 2007 Page 1176 of 1692 REJ09B0360-0100 Section 23 G2D (7) (a) GOSUB Function Makes a subroutine call for the display list. (b) Command Format • REL = 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0011_0000 0 0 0 Reserve (all 0) GOSUB Address (longword address) 8 7 6 5 4 3 2 1 0 Draw Mode 0 0 • REL = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0011_0000 Sign extended Sign 8 7 6 5 4 3 2 1 0 Reserve (all 0) GOSUB Address (longword address) Draw Mode 0 0 1. Code B'00110000 2. Rendering Attributes Draw Mode b15 Fixed to 0 b14 Fixed to 0 b13 Fixed to 0 b12 Fixed to 0 b11 Fixed to 0 b10 Fixed to 0 b9 Fixed to 0 b8 Fixed to 0 b7 REL b6 Fixed to 0 b5 Fixed to 0 b4 Fixed to 0 b3 Fixed to 0 b2 Fixed to 0 b1 Fixed to 0 b0 No 3. Command Parameter GOSUB Address: Subroutine absolute address (Longword address. Write 0 to bits A31 to A29, A1, and A0.) Subroutine relative address (Longword address. Negative number expressed as two's complement. Bits A31 to A29 are used to extend the sign in bit A28. Write 0 to bits A1 and A0.) Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit address to bits A28 to A3. Rev. 1.00 Nov. 22, 2007 Page 1177 of 1692 REJ09B0360-0100 Section 23 G2D (c) Description Changes the display list fetch destination to the specified subroutine address. The fetch address is restored by an RET instruction. As only one level of nesting is permitted, it will not be possible to return if a subroutine call is issued within the subroutine. When REL = 0, the subroutine address can be specified as an absolute address. When REL = 1, the jump destination address can be specified as a relative address with respect to the memory address at which the command code is located. When the No bit is 0, the return address is set in the return address 0 register (RTN0R). When the No bit is 1, the return address is set in the return address 1 register (RTN1R). (d) Example Display list area Register setting command Drawing starts Drawing command GOSUB command Drawing command : : Drawing command Subroutine Drawing command RET command Rev. 1.00 Nov. 22, 2007 Page 1178 of 1692 REJ09B0360-0100 Section 23 G2D (8) (a) RET Function Returns from a subroutine call made by the GOSUB command. (b) Command Format 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0011_1000 Reserve (all 0) Draw Mode 1. Code B'00111000 2. Rendering Attributes Draw Mode b15 Fixed to 0 b14 Fixed to 0 b13 Fixed to 0 b12 Fixed to 0 b11 Fixed to 0 b10 Fixed to 0 b9 Fixed to 0 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 Fixed to 0 b3 Fixed to 0 b2 Fixed to 0 b1 Fixed to 0 b0 No (c) Description Restores the display list fetch destination to the address following the source of the subroutine call. When the No bit is 0, the return address is set in the return address 0 register (RTN0R). When the No bit is 1, the return address is set in the return address 1 register (RTN1R). Rev. 1.00 Nov. 22, 2007 Page 1179 of 1692 REJ09B0360-0100 Section 23 G2D (9) (a) NOP/INT Function Executes no operation. (b) Command Format 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0000_1000 Reserve (all 0) Draw Mode 1. Code B'00001000 2. Rendering Attributes Draw Mode b15 INT b14 Fixed to 0 b13 Fixed to 0 b12 Fixed to 0 b11 Fixed to 0 b10 Fixed to 0 b9 Fixed to 0 b8 Fixed to 0 b7 b6 b5 b4 b3 INT No b2 b1 b0 (c) Description This command does not perform any operation. This command simply fetches the next instruction. However when the INT bit is set to 1 in this command, after this command has been fetched, the INT bit in the status register (SR) is set to 1, INT No is saved in the interrupt command ID register (ICIDR), and the drawing operation is halted. Clearing the INT bit in the status register (SR) restarts the drawing operation from the next command. Rev. 1.00 Nov. 22, 2007 Page 1180 of 1692 REJ09B0360-0100 Section 23 G2D (10) VBKEM (a) Function Performs synchronization with the frame change timing. (b) Command Format 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0001_0000 Reserve (all 0) Draw Mode 1. Code B'00010000 2. Rendering Attributes Draw Mode b15 Fixed to 0 b14 Fixed to 0 b13 Fixed to 0 b12 Fixed to 0 b11 Fixed to 0 b10 Fixed to 0 b9 Fixed to 0 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Fixed to 0 b4 Fixed to 0 b3 Fixed to 0 b2 Fixed to 0 b1 Fixed to 0 b0 Fixed to 0 (c) Description When this command is executed, the drawing operation is kept waiting until the timing for a frame change. As soon as the frame change timing has elapsed, control passes to the next command. The frame change timing is the next VSYNC in non-interlace mode display or interlace sync & video mode display, and the starting point of the next frame in interlace sync mode display. Note: This command can only be used in manual display charge mode or auto-rendering mode. Rev. 1.00 Nov. 22, 2007 Page 1181 of 1692 REJ09B0360-0100 Section 23 G2D (11) TRAP (a) Function Informs the end of the display list. (b) Command Format 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OP CODE = 0000_0000 Reserve (all 0) Draw Mode 1. Code B'00000000 2. Rendering Attributes Draw Mode b15 Fixed to 0 b14 Fixed to 0 b13 Fixed to 0 b12 Fixed to 0 b11 Fixed to 0 b10 Fixed to 0 b9 Fixed to 0 b8 Fixed to 0 b7 Fixed to 0 b6 Fixed to 0 b5 Flip5 b4 Flip4 b3 Flip3 b2 Flip2 b1 Flip1 b0 Flip0 (c) Description Halts the drawing operation and sets the TRA bit in the status register (SR) to 1. If the TRE bit in the interrupt enable register (IER) is set to 1, an interrupt is sent to the CPU. This command must be placed at the end of the display list. If the Flip5 to Flip0 bits are set, the corresponding plane is flipped (only valid in auto-rendering mode). The flip timing is the next VSYNC in non-interlace mode display or interlace sync & video mode display, and the starting point of the next frame in interlace sync mode display. Rev. 1.00 Nov. 22, 2007 Page 1182 of 1692 REJ09B0360-0100 Section 23 G2D (d) Example Display list area Register setting command Drawing starts Drawing command : : Drawing command Drawing command TRA bit in status register (SR) is set to 1. If TRE = 1 at this time, an interrupt is generated externally. Drawing stops TRAP command Rev. 1.00 Nov. 22, 2007 Page 1183 of 1692 REJ09B0360-0100 Section 23 G2D 23.3 Register Specifications The CPU writing to the registers, excluding the system control registers, is prohibited after rendering has started and until the TRAP command is executed, except for the drawing halted period specified by the INT command. However, if a CPU write to the interrupt enable register (IER) conflicts with a WPR command write, the CPU write is given priority. Hereafter, “reset” refers to both a hardware reset and software reset unless specified otherwise. A hardware reset is a power-on reset. Table 23.5 Register Configuration Class System control Register Name System control STatus Status register clear Interrupt enable Interrupt command ID Memory control Return address 0 Return address 1 Display list start address 2-dimensional source area start address Rendering start address Work area start address Source stride Destination stride Abbrev. SCLR SR SRCR IER ICIDR RTN0R RTN1R DLSAR SSAR RW R/W R W R/W R R R R/W R/W WPR* N N N Y N Y Y N Y 1 Area P4 2 Address* H'FFEA 0000 H'FFEA 0004 H'FFEA 0008 H'FFEA 000C H'FFEA 0010 H'FFEA 0040 H'FFEA 0044 H'FFEA 0048 H'FFEA 004C Area 7 2 Address* H'1FEA 0000 H'1FEA 0004 H'1FEA 0008 H'1FEA 000C H'1FEA 0010 H'1FEA 0040 H'1FEA 0044 H'1FEA 0048 H'1FEA 004C Access Size 32 32 32 32 32 32 32 32 32 RSAR WSAR SSTRR DSTRR R/W R/W R/W R/W R/W R/W Y Y Y Y N Y H'FFEA 0050 H'FFEA 0054 H'FFEA 0058 H'FFEA 005C H'FFEA 0060 H'FFEA 0080 H'1FEA 0050 H'1FEA 0054 H'1FEA 0058 H'1FEA 005C H'1FEA 0060 H'1FEA 0080 32 32 32 32 32 32 Endian conversion ENDCVR control Color control Source transparent color STCR Rev. 1.00 Nov. 22, 2007 Page 1184 of 1692 REJ09B0360-0100 Section 23 G2D Class Color control Register Name Destination transparent color Alpha value Color offset Abbrev. DTCR ALPHR COFSR RW R/W R/W R/W R/W R R R R R R WPR*1 Y Y Y Y N N N Y Y Y Y Y Y Y Y Area P4 Address*2 H'FFEA 0084 H'FFEA 0088 H'FFEA 008C H'FFEA 00C0 H'FFEA 00C4 H'FFEA 00C8 H'FFEA 00CC H'FFEA 00D0 H'FFEA 00D4 H'FFEA 00D8 H'FFEA 00DC H'FFEA 00E0 H'FFEA 00F0 H'FFEA 00F8 H'FFEA 0100 Area 7 Address*2 H'1FEA 0084 H'1FEA 0088 H'1FEA 008C H'1FEA 00C0 H'1FEA 00C4 H'1FEA 00C8 H'1FEA 00CC H'1FEA 00D0 H'1FEA 00D4 H'1FEA 00D8 H'1FEA 00DC H'1FEA 00E0 H'1FEA 00F0 H'1FEA 00F8 H'1FEA 0100 Access Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Rendering control Rendering control RCLR Command status Current pointer Local offset System clipping area MAX CSTR CURR LCOR SCLMAR User clipping area UCLMIR MIN User clipping area UCLMAR MAX Relative user clipping area MIN RUCLMIR R R R/W R/W R/W Relative user RUCLMA clipping area MAX R Rendering control RCL2R 2 Pattern offset Coordinate transformation control Coordinate transformation control Matrix parameter A Matrix parameter B Matrix parameter C Matrix parameter D Matrix parameter E POFSR GTRCR MTRAR MTRBR MTRCR MTRDR MTRER R/W R/W R/W R/W R/W Y Y Y Y Y H'FFEA 0104 H'FFEA 0108 H'FFEA 010C H'FFEA 0110 H'FFEA 0114 H'1FEA 0104 H'1FEA 0108 H'1FEA 010C H'1FEA 0110 H'1FEA 0114 32 32 32 32 32 Rev. 1.00 Nov. 22, 2007 Page 1185 of 1692 REJ09B0360-0100 Section 23 G2D Class Coordinate transformation control Register Name Matrix parameter F Matrix parameter G Matrix parameter H Abbrev. MTRFR MTRGR MTRHR RW R/W R/W R/W R/W WPR*1 Y Y Y Y Y Area P4 Address*2 H'FFEA 0118 H'FFEA 011C H'FFEA 0120 H'FFEA 0124 H'FFEA 0128 Area 7 Address*2 H'1FEA 0118 H'1FEA 011C H'1FEA 0120 H'1FEA 0124 H'1FEA 0128 Access Size 32 32 32 32 32 Matrix parameter I MTRIR Coordinate transformation offset X Coordinate transformation offset Y Z clipping area MIN Z clipping area MAX GTROFSX R/W R GTROFSY R/W R ZCLPMIN R R/W Y H'FFEA 012C H'1FEA 012C 32 Y Y Y H'FFEA 0130 H'FFEA 0134 H'FFEA 0138 H'1FEA 0130 H'1FEA 0134 H'1FEA 0138 32 32 32 ZCLPMAX R/W R R/W Z saturation value ZSATVMI MIN NR Notes: *1 Y: WPR command setting is enable. N: WPR command setting is not disable. *2 The area P4 address is an address when accessing through area P4 in a virtual address space. The area 7 address is an address when accessing through area 7 in a physical space using the TLB. Writing to the undefined address space is prohibited. If writing to such an address space is done, the G2D operation is not guaranteed. Rev. 1.00 Nov. 22, 2007 Page 1186 of 1692 REJ09B0360-0100 Section 23 G2D Table 23.6 Register Bit Configuration Data Class System control SCLR SRES RS SR VER MTRER CER INT TRA SRCR MTCL CECL INCL TRCL IER MTE CEE INE TRE ICIDR Memory control RTN0R RTN1R DLSAR SSAR RSAR WSAR SSTRR DSTRR ENDCVR LWSWAP WSWAP BYTESWAP BITSWAP Color control STCR STC1 STC8 STC16 DTCR DTC8 DTC16 ALPHR COFSR RGB: 565 Abbrev. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 COR COG COB ARGB: COR 1555 COG COB Rev. 1.00 Nov. 22, 2007 Page 1187 of 1692 REJ09B0360-0100 Section 23 G2D Data Type Rendering control Register Abbrev. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCLR STP DTP SPF DPF GBM SAU AVALUE LPCE COM CSTR CURR XC YC LCOR XO YO SCLMAR SXMAX SYMAX UCLMIR UXMIN UYMIN UCLMAR UXMAX UYMAX RUCLMIR RUXMIN RUYMIN RUCLMAR RUXMAX RUYMAX RCL2R DAE PSTYLE PXSIZE PYSIZE POFSR POFSX POFSY Coordinate transformation control GTRCR GTE AFE MTRAR MTRBR MTRCR MTRDR MTRER Rev. 1.00 Nov. 22, 2007 Page 1188 of 1692 REJ09B0360-0100 Section 23 G2D Data TYPE Coordinate transformation control Register Abbrev. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MTRFR MTRGR MTRHR MTRIR GTROFSXR GTROFSYR ZCLPMINR ZCLPMAXR ZSATVMINR Table 23.7 Initial Register Values at Hardware Reset and Software Reset Register abbrev. SCLR Data Hardware Software reset reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Y Y SR SRCR IER ICIDR RTN0R RTN1R DLSAR Y Y Y N N N N N N N N N Y N N N N Y N N N N N N N N Y Y Y Y Y N N N N N N N N N Y N N N N Y N N N N N N N N Y Y 00 * * * * * * * * * * * * * * * * * * * 000 * * * * * * ******** ******** 1 1000 0 0 0 0 0 000 000 000 ******** ******** *** System control *************************** *************************** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Memory control SSAR DSAR WSAR SSTRR DSTRR ENDCVR ********* ********* 00000 ************************* ************************ ****** * * * * * 00 00 00 Color control STCR DTCR ALPHR COFSR RCLR CSTR CURR *************************** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Rendering control LCOR SCLMAR UCLMIR UCLMAR RUCLMIR RUCLMAR RCL2R POF3R ************ * * * * * * * * * * * * * * * * * * ** * * * * ************ ************ 00000000100 000000000000 00000000100 000000000000 Rev. 1.00 Nov. 22, 2007 Page 1189 of 1692 REJ09B0360-0100 Section 23 G2D Register abbrev. GTRCR MTRAR MTRBR Data Hardware Software reset reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Y N N N N N N N N N N N N N N Y N N N N N N N N N N N N N N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 ***************************** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * 0 * * * * * * * * * * * * * * Coordinate transformation control * 0 1 MTRCR MTRDR MTRER MTRFR MTRGR MTRHR MTRIR GTROFSXR GTROFSYR ZCLPMIN ZCLPMAX ZSATVMINR [Legend] : Undefined value. Value is retained at a hardware reset and software reset. : Initialized to 0 at a hardware reset and software reset. : Initialized to 1 at a hardware reset. : Reserved. This bit is always read as 0. The write value should always be 0. * : Reserved. Value is retained at a hardware reset and software reset. The read value is undefined. The write value should always be 0. : Reserved. Initialized to 0 at a hardware reset and software reset. The write value should always be 0. : Reserved. Initialized to 1 at a hardware reset and software reset. The write value should always be 1. 0 1 23.3.1 (1) System Control Registers System Control Register (SCLR) H'000 H'80000000 Offset: Initial Value: The system control register (SCLR) is a 32-bit readable/writable register that specifies system operation. SCLR is initialized as follows at a hardware reset: • Bit SRES is set to 1. • Bit RS is cleared to 0. Setting both the SRES and RS bits to 1 simultaneously is prohibited. Rev. 1.00 Nov. 22, 2007 Page 1190 of 1692 REJ09B0360-0100 Section 23 G2D Bit 31—Software Reset (SRES): Resets the G2D. Bit 31: SRES 0 1 Description Command processing execution is enabled. This bit is set to 1 when a hardware reset is performed. Clear this bit to 0 in initialization. When this bit is set to 1 by software, a reset is performed for drawing operations only. The G2D registers are also initialized. While this bit is set to 1, this is the only register that can be written to. Note: For the software reset to be correctly reflected in this LSI, a method for reflecting and confirming write access is necessary, similar to that for memory access. Accordingly, after a software reset starts, execute the following processing before the software reset is canceled. 1. When the G2D priority is equal to the CPU priority, execute dummy read three times for a random SDRAM area. 2. When the G2D priority is level 2 whereas the CPU priority is level 3, execute dummy read once for a random SDRAM area. 3. When the G2D priority is level 3 whereas the CPU priority is level 2, finish all SDRAM accesses by modules of level 2 or level 3, excluding the G2D. (Initial value) Bits 30 to 1—Reserved: The write value should always be 0. These bits are always read as 0. Bit 0—Rendering Start (RS): Specifies the start of rendering. During the drawing period (from rendering start to TRAP command execution), writing 1 to this bit is prohibited. Bit 0: RS 0 1 Description Rendering is not started. (Initial value) Rendering is started. This bit is cleared to 0 after rendering starts. (2) Status Register (SR) H'004 H'80000000 Offset: Initial Value: The status register (SR) is a 32-bit read-only register used to read the internal status of the G2D from outside. SR is initialized as follows at a hardware reset: Rev. 1.00 Nov. 22, 2007 Page 1191 of 1692 REJ09B0360-0100 Section 23 G2D • The VER flag is set to 1000. • All other flags are cleared to 0. Bits 31 to 28—Version Flag (VER): This flag is read as 1000. Bit 18—Matrix Operation Error Flag (MTRER): Flag that indicates that a coordinate transformation matrix operation result TX, TY, or W has exceeded the allowable range and saturation processing was executed. Note: The MTRER bit is not masked by the coordinate transformation enable bit (GTE) in the coordinate transformation control register (GTRCR) or the rendering attribute MTRE bit. Thus, when GTE = 0 or when GTE = 1 with MTRE = 0, the MTRER bit may be set to 1 even when coordinate transformation is not performed. Therefore, do not use the MTRER bit unless both the GTE and MTRE bits are set to 1 throughout the period from rendering start to TRAP command issuance. Bit 18: MTRER 0 Description Normal state. After MTRER flag clearing by the SRES bit in SCLR or the MTCL bit in SRCR, the coordinate transformation matrix operation result TX, TY, or W has not exceeded the allowable range (saturation processing not performed). (Initial value) The coordinate transformation matrix operation result TX, TY, or W has exceeded the allowable range, and saturation processing was performed. Drawing operation is not halted. The MTRER flag retains its state until cleared by a reset or by SRCR. 1 Rev. 1.00 Nov. 22, 2007 Page 1192 of 1692 REJ09B0360-0100 Section 23 G2D Bit 2—Command Error Flag (CER): Flag that indicates that an illegal command has been fetched. Bit 2: CER 0 Description Normal state. An illegal command has not been fetched since CER flag clearing by the SRES bit in SCLR or the CECL bit in SRCR. An illegal command is one in which the upper eight bits of the command code are undefined. The G2D does not check the legality of the rendering attributes in the lower 16 bits. (Initial value) 1 Drawing operation halt state. Drawing operation remains halted because an illegal command was fetched after CER flag clearing by the SRES bit in SCLR or the CECL bit in SRCR. To resume drawing operation, after executing a software reset, make the bit setting for rendering start. The CER flag retains its state until cleared by a reset or by SRCR. Bit 1—Interrupt Flag (INT): Flag that indicates that the NOP/INT command has been fetched (only when the rendering attribute INT bit is 1). Bit 1: INT 0 1 Description The NOP/INT command has not been fetched since INT flag clearing by the SRES bit in SCLR or the INCL bit in SRCR. (Initial value) Drawing operation halt state. Drawing operation remains halted because the NOP/INT command was fetched after INT flag clearing by the SRES bit in SCLR or the INCL bit in SRCR (only when the rendering attribute INT bit is 1). Clearing the INT flag by the INCL bit in SRCR resumes drawing operation from the next command. The INT flag retains its state until cleared by a reset or by SRCR. Note: Do not rewrite the display list when drawing operation is halted by the INT command. Bit 0—Trap Flag (TRA): Flag that indicates the end of command execution. Bit 0: TRA 0 1 Description The TRAP command has not been fetched since TRA flag clearing by the SRES bit in SCLR or the TRCL bit in SRCR. (Initial value) Command execution has ended, or the current command is not being executed. The TRA flag retains its state until cleared by a reset or by SRCR. Rev. 1.00 Nov. 22, 2007 Page 1193 of 1692 REJ09B0360-0100 Section 23 G2D Bits 27 to 19 and 17 to 3—Reserved: These bits are always read as 0. (3) Status Register Clear Register (SRCR) H'008 H'00000000 Offset: Initial Value: The status register clear register (SRCR) is a 32-bit write-only register that clears the corresponding flags in the status register (SR). When SR clearing is completed, all of the values in SRCR are cleared to 0 internally (the bits are read as 0). Bit 18 2 1 0 Bit Name Abbreviation Description Writing 1 to the MTCL bit clears the MTRER flag in SR to 0. Writing 1 to the CECL bit clears the CER flag in SR to 0. Writing 1 to the INCL bit clears the INT flag in SR to 0. Writing 1 to the TRCL bit clears the TRA flag in SR to 0. The write value should always be 0. Matrix operation error MTCL flag clear Command error flag clear Interrupt flag clear Trap flag clear CECL INCL TRCL — 31 to 19 Reserved and 17 to 3 (4) Interrupt Enable Register (IER) H'00C H'00000000 Offset: Initial Value: The interrupt enable register (IER) is a 32-bit readable/writable register that enables or disables interrupts by the corresponding flags in the status register (SR). When a bit in SR is set to 1 and the bit at the corresponding bit position in IER is also 1, an interrupt request is sent to the CPU. The interrupt generation condition is as follows. Interrupt generation condition = a + b + c + d a = MTRER. MTE b = CER. CEE Rev. 1.00 Nov. 22, 2007 Page 1194 of 1692 REJ09B0360-0100 Section 23 G2D c = INT. INE d = TRA. TRE Bit 18—Matrix Operation Error Flag Enable (MTE): Enables or disables interrupts initiated by the MTRER flag in SR. Note: The MTRER bit is not masked by the coordinate transformation enable bit (GTE) in the coordinate transformation control register (GTRCR) or the rendering attribute MTRE bit. Thus, when GTE = 0 or when GTE = 1 with MTRE = 0, the MTRER bit may be set to 1 even when coordinate transformation is not performed. Therefore, do not use the MTRER bit unless both the GTE and MTRE bits are set to 1 throughout the period from rendering start to TRAP command issuance. Bit 18: MTE 0 1 Description Interrupts initiated by the MTRER flag in SR are disabled. (Initial value) Interrupts initiated by the MTRER flag in SR are enabled. Bit 2—Command Error Flag Enable (CEE): Enables or disables interrupts initiated by the CER flag in SR. Bit 2: CEE 0 1 Description Interrupts initiated by the CER flag in SR are disabled. (Initial value) Interrupts initiated by the CER flag in SR are enabled. Bit 1—Interrupt Flag Enable (INE): Enables or disables interrupts initiated by the INT flag in SR. Bit 1: INE 0 1 Description Interrupts initiated by the INT flag in SR are disabled. (Initial value) Interrupts initiated by the INT flag in SR are enabled. Bit 0—Trap Flag Enable (TRE): Enables or disables interrupts initiated by the TRA flag in SR. Bit 0: TRE 0 1 Description Interrupts initiated by the TRA flag in SR are disabled. (Initial value) Interrupts initiated by the TRA flag in SR are enabled. Bits 31 to 19 and 17 to 3—Reserved: The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1195 of 1692 REJ09B0360-0100 Section 23 G2D (5) Interrupt Command ID Register (ICIDR) H'010 Undefined Offset: Initial Value: The interrupt command ID register (ICIDR) is a 32-bit read-only register used to store the ID specified by the rendering attribute if the rendering attribute INT bit is set to 1 when the NOP/INT command is fetched. The unused bits are always read as 0. ICIDR retains its value at a reset. Bits 7 to 0—Interrupt Command ID Bits 31 to 8—Reserved: These bits are always read as 0. 23.3.2 (1) Memory Control Registers Return Address Register 0 (RTN0R) H'040 Undefined Offset: Initial Value: The return address register 0 (RTN0R) is a 32-bit read-only register which stores the return address when the rendering attribute No bit is 0 in the GOSUB command. The address indicated by RTN0R is a longword address (bits A28 to A2). RTN0R retains its value at a reset. (The unused bits are always read as undefined values.) (2) Return Address Register 1 (RTN1R) H'044 Undefined Offset: Initial Value: The return address register 1 (RTN1R) is a 32-bit read-only register which stores the return address when the rendering attribute No bit is 1 in the GOSUB command. The address indicated by RTN1R is a longword address (bits A28 to A2). RTN1R retains its value at a reset. (The unused bits are always read as undefined values.) (3) Display List Start Address Register (DLSAR) H'048 Undefined Offset: Initial Value: Rev. 1.00 Nov. 22, 2007 Page 1196 of 1692 REJ09B0360-0100 Section 23 G2D The display list start address register (DLSAR) is a 32-bit readable/writable register which specifies the memory area to be used as the display list. The start physical address (bits A28 to A0) of the display list is set in 16-byte units. Even in 32-bit addressing mode, write the lower 29 bits of the specified 32-bit address to bits 28 to 0. Write 0 to the lower four bits. Write 0 to the unused bits (these unused bits are always read as undefined values.) DLSAR retains its value at a reset. Do not map the display list to a tile addressing area (for details, see section 11, Memory Controller Unit (MCU)). (4) 2-Dimensional Source Area Start Address Register (SSAR) H'04C Undefined Offset: Initial Value: The 2-dimensional source area start address register (SSAR) is a 32-bit readable/writable register which specifies the memory area to be used as the 2-dimensional source area. The physical address set in this register becomes the physical address for the origin of the 2-dimensional source coordinates. The start physical address (bits A28 to A0) of the 2-dimensional source area is set in 16-byte units. Even in 32-bit addressing mode, write the lower 29 bits of the specified 32-bit address to bits 28 to 0. Write 0 to the lower four bits. Write 0 to the unused bits (these unused bits are always read as undefined values.) SSAR retains its value at a reset. When mapping the 2dimensional source area to a tile addressing area (for details, see section 11, Memory Controller Unit (MCU)), write 0 to the lower nine bits (512-byte units). (5) Rendering Start Address Register (RSAR) H'050 Undefined Offset: Initial Value: The rendering start address register (RSAR) is a 32-bit readable/writable register which specifies the memory area to be used as the rendering area. The physical address set in this register becomes the physical address for the rendering coordinate origin. The start physical address (bits A28 to A0) of the rendering area is set in 16-byte units. Even in 32-bit addressing mode, write the lower 29 bits of the specified 32-bit address to bits 28 to 0. Write 0 to the lower four bits. Write 0 to the unused bits (these unused bits are always read as undefined values.) RSAR retains its value at a reset. When mapping the rendering area to a tile addressing area (for details, see section 11, Memory Controller Unit (MCU)), write 0 to the lower nine bits (512-byte units). Set the rendering start address so that the rendering area does not overlap with the work area. Rev. 1.00 Nov. 22, 2007 Page 1197 of 1692 REJ09B0360-0100 Section 23 G2D (6) Work Area Start Address Register (WSAR) H'054 Undefined Offset: Initial Value: The work area start address register (WSAR) is a 32-bit readable/writable register which specifies the memory area to be used as the work area. The physical address set in this register becomes the physical address for the work coordinate origin. The start physical address (bits A28 to A0) of the work area is set in 16-byte units. Even in 32-bit addressing mode, write the lower 29 bits of the specified 32-bit address to bits 28 to 0. Write 0 to the lower four bits. Write 0 to the unused bits (these unused bits are always read as undefined values.) WSAR retains its value at a reset. Do not map the work area to a tile addressing area (for details, see section 11, Memory Controller Unit (MCU)). Use only the work drawing commands for drawing in the work area. When writing to the work area by the CPU, avoid the drawing period (from rendering start to TRAP command execution (including the drawing halt period specified by the NOP/INT command)). Do not use a figure drawn by a work drawing command as the source figure. (7) Source Stride Register (SSTRR) H'058 Undefined Offset: Initial Value: The source stride register (SSTRR) is a 32-bit readable/writable register which specifies the stride of the 2-dimensional source area. SSTRR retains its value at a reset. Bits 12 to 0—Source Stride (SSTRIDE): These bits specify the stride of the 2-dimensional source area in pixel units. Set the value in the range of 16 ≤ SSTRIDE ≤ 4096. Write 0 to the lower four bits (16-pixel units). When the 2-dimensional source area to be used is mapped to a tile addressing area (for details, see section 11, Memory Controller Unit (MCU)), only a value of 512, 1024, 2048, or 4096 can be set. Bits 31 to 13—Reserved: The write value should always be 0. These bits are always read as 0. (8) Destination Stride Register (DSTRR) H'05C Undefined Offset: Initial Value: Rev. 1.00 Nov. 22, 2007 Page 1198 of 1692 REJ09B0360-0100 Section 23 G2D The destination stride register (DSTRR) is a 32-bit readable/writable register which specifies the stride of the destination area. DSTRR retains its value at a reset. Bits 12 to 0—Destination Stride (DSTRIDE): These bits specify the stride of the destination area in pixel units. Set the value in the range of 256 ≤ DSTRIDE ≤ 4096. Write 0 to the lower four bits (16-pixel units). When the destination area to be used is mapped to a tile addressing area (for details, see section 11, Memory Controller Unit (MCU)), only a value of 512, 1024, 2048, or 4096 can be set. Bits 31 to 13—Reserved: The write value should always be 0. These bits are always read as 0. (9) Endian Conversion Control Register (ENDCVR) H'060 H'00000000 Offset: Initial Value: The endian conversion control register (ENDCVR) is a 32-bit readable/writable register which specifies the endian conversion mode. Bits 31 to 4—Reserved: The write value should always be 0. These bits are always read as 0. Bit 3—Longword Swap (LWSWAP): Swaps data in longword (32-bit) units. Bit 3: LWSWAP 0 1 Description Data is not swapped. (Initial value) Data is swapped in longword (32-bit) units. Bit 2—Word Swap (WSWAP): Swaps data in word (16-bit) units. Bit 2: WSWAP 0 1 Description Data is not swapped. (Initial value) Data is swapped in word (16-bit) units. Rev. 1.00 Nov. 22, 2007 Page 1199 of 1692 REJ09B0360-0100 Section 23 G2D Bit 1—Byte Swap (BYTESWAP): Swaps data in byte (8-bit) units. Bit 1: BYTESWAP 0 1 Description Data is not swapped. (Initial value) Data is swapped in byte (8-bit) units. Bit 0—Bit Swap (BITSWAP): Swaps data in bit units. Bit 0: BITSWAP 0 1 Description Data is not swapped. (Initial value) Data is swapped in bit units. Rev. 1.00 Nov. 22, 2007 Page 1200 of 1692 REJ09B0360-0100 Section 23 G2D • 1bit/pixel data LWSWAP BYTESWAP Bit Pixel number 63 63 56 55 56 55 48 47 48 47 40 39 40 39 32 31 32 31 24 23 24 23 16 15 16 15 87 87 0 0 BITSWAP WSWAP • 8-bit/pixel data (BITSWAP setting is disabled) BYTESWAP LWSWAP Bit Pixel number 63 7 56 55 6 48 47 5 40 39 4 32 31 3 24 23 2 16 15 1 87 0 0 WSWAP • 16-bit/pixel data (RGB) (BYTESWAP and BITSWAP settings are disabled) LWSWAP Bit Pixel number 63 R3 59 58 G3 53 52 B3 48 47 R2 43 42 G2 37 36 B2 32 31 R1 27 26 G1 21 20 B1 16 15 R0 11 10 G0 5 4 B0 0 3 2 1 0 WSWAP • 16-bit/pixel data (ARGB) (BYTESWAP and BITSWAP settings are disabled) LWSWAP Bit Pixel number 63 62 A3 R3 58 57 G3 53 52 B3 48 47 46 A2 R2 42 41 G2 37 36 B2 32 31 30 A1 R1 26 25 G1 21 20 B1 16 15 14 A0 R0 10 9 G0 5 4 B0 0 3 2 1 0 WSWAP • 32-bit data (display list) (WSWAP, BYTESWAP, and BITSWAP settings are disabled) LWSWAP Bit 63 Adress 8n + 4 32 31 Adress 8n 0 23.3.3 (1) Color Control Registers Source Transparent Color Register (STCR) H'080 Undefined Offset: Initial Value: The source transparent color register (STCR) is a 32-bit readable/writable register which compares the source data with the color set in this register when the rendering attribute STRANS bit is set to 1. The source color becomes transparent and drawing not performed when the source data matches Rev. 1.00 Nov. 22, 2007 Page 1201 of 1692 REJ09B0360-0100 Section 23 G2D the color set in this register if the source transparent color polarity bit (STP) in the rendering control register (RCLR) is 0, and when the source data does not match the color set in this register if the STP bit in RCLR is 1. STCR retains its value at a reset. Bit 24 23 to 16 15 to 0 Bit Name STC1 STC8 STC16 Description Transparent color for 1-bit/pixel source Transparent color for 8-bit/pixel source Transparent color for 16-bit/pixel source For 16-bit/pixel source data, use the same format specified by the SPF bit in the rendering control register (RCLR). When SPF = 1 (ARGB = 1555), the A value is not compared. Bits 31 to 25—Reserved: The write value should always be 0. These bits are always read as 0. (2) Destination Transparent Color Register (DTCR) H'084 Undefined Offset: Initial Value: The destination transparent color register (DTCR) is a 32-bit readable/writable register which compares the destination data with the color set in this register when the rendering attribute DTRANS bit is set to 1. The destination color becomes transparent and drawing not performed when the destination data matches the color set in this register if the destination transparent color polarity bit (DTP) in the rendering control register (RCLR) is 0, and when the destination data does not match the color set in this register if the DTP bit in RCLR is 1. DTCR retains its value at a reset. Bit 23 to 16 15 to 0 Bit Name DTC8 DTC16 Description Transparent color for 8-bit/pixel destination Transparent color for 16-bit/pixel destination For 16-bit/pixel destination data, use the same format specified by the DPF bit in the rendering control register (RCLR). When DPF = 1 (ARGB = 1555), the A value is not compared. Bits 31 to 24—Reserved: The write value should always be 0. These bits are always read as 0. Rev. 1.00 Nov. 22, 2007 Page 1202 of 1692 REJ09B0360-0100 Section 23 G2D (3) Alpha Value Register (ALPHR) H'088 Undefined Offset: Initial Value: The alpha value register (ALPHR) is a 32-bit readable/writable register which specifies the alpha blending value when the rendering attribute αE bit is set to 1. ALPHR retains its value at a reset. For blending of the blue and red components, the upper five bits of the alpha value are valid. For blending of the green component, the upper six bits are valid when the destination pixel format is RGB and the upper five bits are valid when it is ARGB. Bit 7 to 0 Bit Name ALPH Description These bits set the alpha value. Destination ≈ source × ALPH/255 + destination (1 − ALPH/255) (approximate expression when ALPH is an 8-bit value) Bits 31 to 8—Reserved: The write value should always be 0. These bits are always read as 0. (4) Color Offset Register (COFSR) H'08C Undefined Offset: Initial Value: The color offset register (COFSR) is a 32-bit readable/writable register. In 16-bit/pixel drawing, if the rendering attribute COOF bit is set to 1, the result of adding the value in COFSR to the value of the source data (color expanded data for a binary source and the specified color for the monochrome specification) is drawn. The operation is performed by saturation processing. In 8bit/pixel drawing, the rendering attribute COOF bit must be cleared to 0. The offset components are treated as signed integers. Negative numbers are expressed as two's complement. COFSR retains its value at a reset. Rev. 1.00 Nov. 22, 2007 Page 1203 of 1692 REJ09B0360-0100 Section 23 G2D • Source pixel format is RGB = 565 (SPF = 0) Bit 23 to 19 15 to 10 7 to 3 Name COR (Color offset R) COG (Color offset G) COB (Color offset B) Description Color offset red component Color offset green component Color offset blue component Bits 18 to 16, 9, 8, and 2 to 0 are discarded. These bits are always read as 0. • Source pixel format is ARGB = 1555 (SPF = 1) Bit 23 to 19 15 to 11 7 to 3 Name COR (Color offset R) COG (Color offset G) COB (Color offset B) Description Color offset red component Color offset green component Color offset blue component Bits 18 to 16, 10 to 8, and 2 to 0 are discarded. These bits are always read as 0. Bits 31 to 24—Reserved: The write value should always be 0. These bits are always read as 0. 23.3.4 (1) Rendering Control Registers Rendering Control Register (RCLR) H'0C0 H'00000000 Offset: Initial Value: The rendering control register (RCLR) is a 32-bit readable/writable register which specifies the rendering attributes. Bit 25—Source Transparent Color Polarity (STP): Selects whether source transparency occurs when the source data and the value set in the source transparent color register (STCR) match or do not match. Bit 25: STP 0 1 Description Source transparency at a match (Initial value) Source transparency at a mismatch Rev. 1.00 Nov. 22, 2007 Page 1204 of 1692 REJ09B0360-0100 Section 23 G2D Bit 24—Destination Transparent Color Polarity (DTP): Selects whether destination transparency occurs when the destination data and the value set in the destination transparent color register (DTCR) match or do not match. Bit 24: DTP 0 1 Description Destination transparency at a match (Initial value) Destination transparency at a mismatch Bit 21—Source Pixel Format (SPF): Specifies the pixel format for the multi-valued source. This setting is valid only for a multi-valued 16-bit/pixel source. This bit should be cleared to 0 for an 8bit-pixel source. Set this bit to match the destination pixel format. Bit 21: SPF 0 1 Description RGB = 565 format (Initial value) ARGB = 1555 format Bit 20—Destination Pixel Format (DPF): Specifies the pixel format for the destination. This setting is valid only for a 16-bit/pixel destination. This bit should be cleared to 0 for an 8-bit-pixel destination. Set this bit to match the multi-valued source pixel format. Bit 20: DPF 0 1 Description RGB = 565 format (Initial value) ARGB = 1555 format Bit 18—Graphic Bit Mode (GBM): Specifies the graphic bit mode for the multi-valued source and destination. Bit 18: GBM 0 1 Description 8-bit/pixel (Initial value) 16-bit/pixel Bit 17—Source A Value Use (SAU): When the pixel format of the source and destination is the ARGB format, drawing is performed while referencing the source A value as the destination A value. Bit 16—A Value (AVALUE): When the pixel format of the source and destination is the ARGB format, drawing is performed with the destination A value as 0 or 1. Rev. 1.00 Nov. 22, 2007 Page 1205 of 1692 REJ09B0360-0100 Section 23 G2D Relationship between Source/Destination Pixel Format (SPF/DPF) and SAU and AVALUE Bits SPF 0 0 1 1 DPF 0 1 0 1 SAU * * * 0 0 1 AVALUE Description * * * 0 1 * Source = RGB (565) and destination = RGB (565). The SAU and AVALUE bit settings are invalid. Setting prohibited. Setting prohibited. Source = ARGB (1555) and destination = ARGB (1555). The destination A value is drawn as 0. Source = ARGB (1555) and destination = ARGB (1555). The destination A value is drawn as 1. Source = ARGB (1555) and destination = ARGB (1555). The destination A value is drawn referencing the source A value. The AVALUE bit setting is invalid. Note: * Don't care When SAU = 1, the A value of the command parameter Color0 or Color1 is referenced in a binary source reference command and the A value of the command parameter Color is referenced in a monochrome specification command. In the LINED command, the A value of the ground (destination) is written back, regardless of the settings of the SAU and AVALUE bits. Bit 1—Line Pre-Clipping Enable (LPCE): This bit setting is valid in a LINE, RLINE, LINEW, or RLINEW command. When this bit is set to 1, pre-clipping is performed in line-segment units in the 2-dimensional clipping areas (system clipping, user clipping, and relative user clipping areas). If a line segment in the middle is pre-clipped, the pattern continuity is broken (the pattern starts from the final point of the line segment previously drawn). Bit 1: LPCE 0 1 Description Pre-clipping is not performed (Initial value) Pre-clipping is performed in line-segment units in the 2-dimensional clipping areas Rev. 1.00 Nov. 22, 2007 Page 1206 of 1692 REJ09B0360-0100 Section 23 G2D Bit 0—Connection Drawing Mask (COM): Selects whether the linkage parts of bold lines are drawn or not. Bit 0: COM 0 1 Description Linkage parts of bold lines are drawn (Initial value) Linkage parts of bold lines are not drawn Bits 31 to 26, 23, 22, 19, and 15 to 2—Reserved: The write value should always be 0. These bits are always read as 0. (2) Command Status Register (CSTR) H'0C4 Undefined Offset: Initial Value: The command status register (CSTR) is a 32-bit read-only register which stores the address of the fetched command word (op code word). The address indicated by CSTR is a longword address (bits A28 to A2). The unused bits are always read as 0. CSTR retains its value at a reset. (3) Current Pointer Register (CURR) H'0C8 Undefined Offset: Initial Value: The current pointer register (CURR) is a 32-bit read-only register which indicates the current pointer coordinates. The upper word indicates the X coordinate (XC) of the pointer and the lower word indicates the Y coordinate (YC) of the pointer. CURR retains its value at a reset. Rev. 1.00 Nov. 22, 2007 Page 1207 of 1692 REJ09B0360-0100 Section 23 G2D (4) Local Offset Register (LCOR) H'0CC Undefined Offset: Initial Value: The local offset register (LCOR) is a 32-bit read-only register which indicates the offset coordinates. The upper word indicates the X coordinate (XO) of the offset and the lower word indicates the Y coordinate (YO) of the offset. LCOR retains its value at a reset. (5) System Clipping Area MAX Register (SCLMAR) H'0D0 Undefined Offset: Initial Value: The system clipping area MAX register (SCLMAR) is a 32-bit read-only register which indicates the maximum values of the system clipping coordinates. The upper word indicates the maximum value of the system clipping X coordinate (SXMAX) and the lower word indicates the maximum value of the system clipping Y coordinate (SYMAX). The unused bits are always read as 0. When setting this register by the WPR command, set the maximum values of the drawing range (Max. 4095. SXMAX < DSTRR). SCLMAR retains its value at a reset. (6) User Clipping Area MIN Register (UCLMIR) H'0D4 Undefined Offset: Initial Value: The user clipping area MIN register (UCLMIR) is a 32-bit read-only register which indicates the minimum values of the user clipping coordinates. The upper word indicates the minimum value of the user clipping X coordinate (UXMIN) and the lower word indicates the minimum value of the user clipping Y coordinate (UYMIN). The unused bits are always read as 0. When setting this register by the WPR command, set UXMIN and UYMIN in the following ranges: 0 ≤ UXMIN ≤ UXMAX ≤ SXMAX ≤ 4095, 0 ≤ UYMIN ≤ UYMAX ≤ SYMAX ≤ 4095. UCLMIR retains its value at a reset. Rev. 1.00 Nov. 22, 2007 Page 1208 of 1692 REJ09B0360-0100 Section 23 G2D (7) User Clipping Area MAX Register (UCLMAR) H'0D8 Undefined Offset: Initial Value: The user clipping area MAX register (UCLMAR) is a 32-bit read-only register which indicates the maximum values of the user clipping coordinates. The upper word indicates the maximum value of the user clipping X coordinate (UXMAX) and the lower word indicates the maximum value of the user clipping Y coordinate (UYMAX). The unused bits are always read as 0. When setting this register by the WPR command, set UXMAX and UYMAX in the following ranges: 0 ≤ UXMIN ≤ UXMAX ≤ SXMAX ≤ 4095, 0 ≤ UYMIN ≤ UYMAX ≤ SYMAX ≤ 4095. UCLMAR retains its value at a reset. (8) Relative User Clipping Area MIN Register (RUCLMIR) H'0DC Undefined Offset: Initial Value: The relative user clipping area MIN register (RUCLMIR) is a 32-bit read-only register which indicates the minimum values of the relative user clipping coordinates (offset values added to the local offset). When setting this register by the WPR command, set the relative coordinates from the local offset. The upper word indicates the minimum value of the relative user clipping X coordinate (RUXMIN) and the lower word indicates the minimum value of the relative user clipping Y coordinate (RUYMIN). The unused bits are always read as 0. When setting this register by the WPR command, set RUXMIN and RUYMIN in the following ranges: 0 ≤ RUXMIN ≤ RUXMAX ≤ SXMAX ≤ 4095, 0 ≤ RUYMIN ≤ RUYMAX ≤ SYMAX ≤ 4095. For details on the setting ranges, see (5) Relative Clipping Specification (RCLIP), in section 23.1.5, Rendering Attributes. RUCLMIR retains its value at a reset. (9) Relative User Clipping Area MAX Register (RUCLMAR) H'0E0 Undefined Offset: Initial Value: The relative user clipping area MAX register (RUCLMAR) is a 32-bit read-only register which indicates the maximum values of the relative user clipping coordinates (offset values added to the local offset). When setting this register by the WPR command, set the relative coordinates from Rev. 1.00 Nov. 22, 2007 Page 1209 of 1692 REJ09B0360-0100 Section 23 G2D the local offset. The upper word indicates the maximum value of the relative user clipping X coordinate (RUXMAX) and the lower word indicates the maximum value of the relative user clipping Y coordinate (RUYMAX). The unused bits are always read as 0. When setting this register by the WPR command, set RUXMAX and RUYMAX in the following ranges: 0 ≤ RUXMIN ≤ RUXMAX ≤ SXMAX ≤ 4095, 0 ≤ RUYMIN ≤ RUYMAX ≤ SYMAX ≤ 4095. For details on the setting ranges, see (5) Relative Clipping Specification (RCLIP), in section 23.1.5, Rendering Attributes. RUCLMAR retains its value at a reset. (10) Rendering Control 2 Register (RCL2R) Offset: Initial Value: H'0F0 H'00004004 The rendering control 2 register (RCL2R) is a 32-bit readable/writable register which specifies the rendering attributes. Bit 21—Destination Alpha Enable (DAE): This bit is used in combination with the alpha blend enable (αE) bit. With the ARGB = 1555 format, only the pixels whose destination (ground) A value is 1 are alpha blended. Pixels whose destination (ground) A value is 0 are not drawn. Bit 21: DAE 0 1 Notes: 1. 2. 3. 4. Description Alpha blending is performed regardless of the destination (ground) A value (Initial value) Alpha blending is performed for only the pixels whose destination (ground) A value is 1 Clear this bit to 0 for the RGB = 565 format or at 8-bit-pixel drawing. Clear this bit to 0 for commands other than the POLYGON4 type commands. Clear this bit to 0 when the alpha blend enable bit (αE) is 0. This bit is not decoded by a command so it must be set or cleared in each relevant command. Bit 20—Pattern Style Enable (PSTYLE): This bit is used in combination with the source style specification (STYLE). The source pattern is created repeatedly in the pattern size based on the destination coordinates. Rev. 1.00 Nov. 22, 2007 Page 1210 of 1692 REJ09B0360-0100 Section 23 G2D Bit 20: PSTYLE 0 1 Notes: 1. 2. 3. 4. Description Pattern style disabled (Initial value) Source pattern is created based on the destination coordinates Set the source offset TXOFS and TYOFS to 0. Clear this bit to 0 when the source style specification bit (STYLE) is 0. Clear the source address specification bit (SS) to 0. Clear this bit to 0 for commands other than the POLYGON4A and POLYGON4B commands. 5. This bit is not decoded by a command so it must be set or cleared in each relevant command. Bits 19 and 18—Pattern X Size (PXSIZE): These bits specify the pattern X size when the pattern style enable (PSTYLE) bit is 1. Bit 19: PXSIZE[1] 0 1 Bit 18: PXSIZE[0] 0 1 0 1 Description Pattern X size = 8 pixels Pattern X size = 16 pixels Pattern X size = 32 pixels Pattern X size = 64 pixels Note: Set the specified pattern X size (8, 16, 32, or 64) in the source size TDX. Bits 17 and 16—Pattern Y Size (PYSIZE): These bits specify the pattern Y size when the pattern style enable (PSTYLE) bit is 1. Bit 17: PYSIZE[1] 0 1 Bit 16: PYSIZE[0] 0 1 0 1 Description Pattern Y size = 8 pixels Pattern Y size = 16 pixels Pattern Y size = 32 pixels Pattern Y size = 64 pixels Note: Set the specified pattern Y size (8, 16, 32, or 64) in the source size TDY. Bits 31 to 22 and 15 to 0—Reserved: The write value should be the initial value. Rev. 1.00 Nov. 22, 2007 Page 1211 of 1692 REJ09B0360-0100 Section 23 G2D (11) Pattern Offset Register (POFSR) Offset: Initial Value: H'0F8 H'00000000 The pattern offset register (POFSR) is a 32-bit readable/writable register which specifies the offset value when the pattern style enable (PSTYLE) bit is 1. The setting of this bit is referenced only when the pattern style enable (PSTYLE) bit is 1. Bits 31 to 16—Pattern Offset X (POFSX): These bits specify the pattern offset value in the X direction as a 16-bit integer. A negative number is expressed as two's complement. Bits 15 to 0—Pattern Offset Y (POFSY): These bits specify the pattern offset value in the Y direction as a 16-bit integer. A negative number is expressed as two's complement. 23.3.5 (1) Coordinate Transformation Control Registers Coordinate Transformation Control Register (GTRCR) H'100 H'00000000 Offset: Initial Value: The coordinate transformation control register (GTRCR) is a 32-bit readable/writable register which sets the enable bits for enabling or disabling coordinate transformation. Bit 31—Coordinate Transformation Enable (GTE): Performs coordinate transformation. Bit 31: GTE 0 1 Description Coordinate transformation is not performed. The rendering attribute MTRE bit is disabled. (Initial value) The rendering attribute MTRE bit is enabled. Rev. 1.00 Nov. 22, 2007 Page 1212 of 1692 REJ09B0360-0100 Section 23 G2D Bit 0—Affine Transformation Enable (AFE): Does not perform W division and offset addition at coordinate transformation. This bit is enabled when both the rendering attribute MTRE bit and GTE bit are set to 1. Bit 0: AFE 0 Description The vertex coordinates X', Y' are obtained by dividing the matrix operation result coordinates TX, TY by WC, and then adding the offset values. X' = TX/WC + GTROFSX Y' = TY/WC + GTROFSY GTROFSX and GTROFSY are set in the coordinate transformation offset X register (GTROFSX) and coordinate transformation offset Y register (GTROFSY), respectively. (Initial value) 1 The vertex coordinates X', Y' are the matrix operation result coordinates TX, TY. X' = TX Y' = TY Bits 30 to 1—Reserved: The write value should always be 0. These bits are always read as 0. (2) Matrix Parameter A Register (MTRAR) H'104 Undefined Offset: Initial Value: The matrix parameter A register (MTRAR) is a 32-bit readable/writable register which specifies a matrix parameter at coordinate change in the single-precision floating-point format defined by the IEEE 754 standard. However, since internal computation is carried out with 32-bit fixed-point operations (16-bit integer portion and 16-bit fractional portion), MTRAR should be set within the range of −215 ≤ MTRAR < 215. MTRAR retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. Rev. 1.00 Nov. 22, 2007 Page 1213 of 1692 REJ09B0360-0100 Section 23 G2D (3) Matrix Parameter B Register (MTRBR) H'108 Undefined Offset: Initial Value: The matrix parameter B register (MTRBR) is a 32-bit readable/writable register which specifies a matrix parameter at coordinate change in the single-precision floating-point format defined by the IEEE 754 standard. However, since internal computation is carried out with 32-bit fixed-point operations (16-bit integer portion and 16-bit fractional portion), MTRBR should be set within the range of −215 ≤ MTRBR < 215. MTRBR retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. (4) Matrix Parameter C Register (MTRCR) H'10C Undefined Offset: Initial Value: The matrix parameter C register (MTRCR) is a 32-bit readable/writable register which specifies a matrix parameter at coordinate change in the single-precision floating-point format defined by the IEEE 754 standard. However, since internal computation is carried out with 32-bit fixed-point operations (16-bit integer portion and 16-bit fractional portion), MTRCR should be set within the range of −215 ≤ MTRCR < 215. MTRCR retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. (5) Matrix Parameter D Register (MTRDR) H'110 Undefined Offset: Initial Value: The matrix parameter D register (MTRDR) is a 32-bit readable/writable register which specifies a matrix parameter at coordinate change in the single-precision floating-point format defined by the IEEE 754 standard. However, since internal computation is carried out with 32-bit fixed-point Rev. 1.00 Nov. 22, 2007 Page 1214 of 1692 REJ09B0360-0100 Section 23 G2D operations (16-bit integer portion and 16-bit fractional portion), MTRDR should be set within the range of −215 ≤ MTRDR < 215. MTRDR retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. (6) Matrix Parameter E Register (MTRER) H'114 Undefined Offset: Initial Value: The matrix parameter E register (MTRER) is a 32-bit readable/writable register which specifies a matrix parameter at coordinate change in the single-precision floating-point format defined by the IEEE 754 standard. However, since internal computation is carried out with 32-bit fixed-point operations (16-bit integer portion and 16-bit fractional portion), MTRER should be set within the range of −215 ≤ MTRER < 215. MTRER retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. (7) Matrix Parameter F Register (MTRFR) H'118 Undefined Offset: Initial Value: The matrix parameter F register (MTRFR) is a 32-bit readable/writable register which specifies a matrix parameter at coordinate change in the single-precision floating-point format defined by the IEEE 754 standard. However, since internal computation is carried out with 32-bit fixed-point operations (16-bit integer portion and 16-bit fractional portion), MTRFR should be set within the range of −215 ≤ MTRFR < 215. MTRFR retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. Rev. 1.00 Nov. 22, 2007 Page 1215 of 1692 REJ09B0360-0100 Section 23 G2D (8) Matrix Parameter G Register (MTRGR) H'11C Undefined Offset: Initial Value: The matrix parameter G register (MTRGR) is a 32-bit readable/writable register which specifies a matrix parameter at coordinate change in the single-precision floating-point format defined by the IEEE 754 standard. However, since internal computation is carried out with 32-bit fixed-point operations (16-bit integer portion and 16-bit fractional portion), MTRGR should be set within the range of −215 ≤ MTRGR < 215. MTRGR retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. (9) Matrix Parameter H Register (MTRHR) H'120 Undefined Offset: Initial Value: The matrix parameter H register (MTRHR) is a 32-bit readable/writable register which specifies a matrix parameter at coordinate change in the single-precision floating-point format defined by the IEEE 754 standard. However, since internal computation is carried out with 32-bit fixed-point operations (16-bit integer portion and 16-bit fractional portion), MTRHR should be set within the range of −215 ≤ MTRHR < 215. MTRHR retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. (10) Matrix Parameter I Register (MTRIR) Offset: Initial Value: H'124 Undefined The matrix parameter I register (MTRIR) is a 32-bit readable/writable register which specifies a matrix parameter at coordinate change in the single-precision floating-point format defined by the IEEE 754 standard. However, since internal computation is carried out with 32-bit fixed-point Rev. 1.00 Nov. 22, 2007 Page 1216 of 1692 REJ09B0360-0100 Section 23 G2D operations (16-bit integer portion and 16-bit fractional portion), MTRIR should be set within the range of −215 ≤ MTRIR < 215. MTRIR retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. (11) Coordinate Transformation Offset X Register (GTROFSXR) Offset: Initial Value: H'128 Undefined The coordinate transformation offset X register (GTROFSXR) is a 32-bit readable/writable register which specifies the X offset value at coordinate change as a 16-bit integer. A negative number is expressed as two's complement. GTROFSXR retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. (12) Coordinate Transformation Offset Y Register (GTROFSYR) Offset: Initial Value: H'12C Undefined The coordinate transformation offset Y register (GTROFSYR) is a 32-bit readable/writable register which specifies the Y offset value at coordinate change as a 16-bit integer. A negative number is expressed as two's complement. GTROFSYR retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. (13) Z Clipping Area MIN Register (ZCLPMINR) Offset: Initial Value: H'130 Undefined Rev. 1.00 Nov. 22, 2007 Page 1217 of 1692 REJ09B0360-0100 Section 23 G2D The Z clipping area MIN register (ZCLPMINR) is a 32-bit readable/writable register which specifies the minimum value of the Z clipping area in the single-precision floating-point format defined by the IEEE 754 standard. Since the setting is compared with the W value, set a value corresponding to W in ZCLPMINR. Since internal computation is carried out with 32-bit fixed-point operations (16-bit integer portion and 16-bit fractional portion), ZCLPMINR should be set within the range of 2−16 ≤ ZCLPMINR ≤ ZCLPMAXR < 215. ZCLPMINR retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. (14) Z Clipping Area MAX Register (ZCLPMAXR) Offset: Initial Value: H'134 Undefined The Z clipping area MAX register (ZCLPMAXR) is a 32-bit readable/writable register which specifies the maximum value of the Z clipping area in the single-precision floating-point format defined by the IEEE 754 standard. Since the setting is compared with the W value, set a value corresponding to W in ZCLPMAXR. Since internal computation is carried out with 32-bit fixed-point operations (16-bit integer portion and 16-bit fractional portion), ZCLPMAXR should be set within the range of 2−16 ≤ ZCLPMINR ≤ ZCLPMAXR < 215. ZCLPMAXR retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. (15) Z Saturation Value MIN Register (ZSATVMINR) Offset: Initial Value: H'138 Undefined The Z saturation value MIN register (ZSATVMINR) is a 32-bit readable/writable register which specifies the minimum Z saturation value in the single-precision floating-point format defined by Rev. 1.00 Nov. 22, 2007 Page 1218 of 1692 REJ09B0360-0100 Section 23 G2D the IEEE 754 standard. Since the setting is compared with the W value, set a value corresponding to W in ZSATVMINR. Since internal computation is carried out with 32-bit fixed-point operations (16-bit integer portion and 16-bit fractional portion), ZSATVMINR should be set within the range of 2−16 ≤ ZSATVMINR ≤ ZCLPMINR ≤ ZCLPMAXR < 215. ZSATVMINR retains its value at a reset. Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions. Rev. 1.00 Nov. 22, 2007 Page 1219 of 1692 REJ09B0360-0100 Section 23 G2D Rev. 1.00 Nov. 22, 2007 Page 1220 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Section 24 Video Display Controller (VDC2) 24.1 Overview The video display controller (VDC2) provides functions for reading four planes of graphic images (layers 1 to 4) stored in the external memory and overlaying them. It outputs 18-bit RGB video (each color is represented by six bits) and digital video data conforming to BTA T-1004. 24.2 Item Features Function T-1004 display clock: 54 MHz RGB666 display clock: 6.0 MHz to 36.0 MHz (depends on the display panel size) Operating frequency Input image format Display size 16-bit RGB565 progressive (SDRAM) • 18-bit progressive RGB output 720 × 480 (NTSC) 720 × 576 (PAL) 320 × 240 (QVGA) 640 × 480 (VGA) 800 × 480 (WVGA) • 8-bit digital output conforming to BTA T-1004 (parallel interface in the 8:4:4 bit format) (the RGB data output timing can be set to the rising or falling edge of the clock through the SYNCNT register setting) 720 × 480 (NTSC) Display planes α blending Chroma-keying Up to four planes (layers 1 to 4) Mixes layers 1 to 4 according to the transparency (α value). Applies chroma-key processing to the specified RGB color (transparency can be specified as the α value) Rev. 1.00 Nov. 22, 2007 Page 1221 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Item Output video format Function RGB666 progressive video output (each of RGB colors is represented by 6 bits: 18 bits in total) 8-bit digital video output conforming to BTA T-1004 (parallel interface in the 8:4:4 bit format) (the RGB data output timing can be set to the rising or falling edge of the clock through the SYNCNT register setting) Sync signal output Either a combination of Vsync, Hsync, data enable, and COM/CDE signals, or a combination of SPL, CLS, SPS, data enable, and COM/CDE signals can be selected (each signal output timing can be set to the rising or falling edge of the clock and the polarity can be selected through the SYNCNT register setting). The VDC2 can operate with external sync signals (EX-VSYNC and EXHSYNC) and the panel clock (the external sync signal timing can be set to the rising or falling edge of the clock and the polarity can be selected through the SYNCNT register setting). Note that only RGB666 video data can be output in this mode. External sync mode Chroma enable signal Outputs a chroma data enable (CDE) signal for the specified color in the output video image. Rev. 1.00 Nov. 22, 2007 Page 1222 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.3 Input/Output Pins Table 24.1 Pin Configuration Symbol DR [5:0] DG [5:0] DB [5:0] VSYNC/SPS HSYNC/SPL I/O Output Output Output Output Output Pin Name Digital red data Digital green data Digital blue data Vertical sync signal/gate start signal Horizontal sync signal/sampling start signal Vertical data enable signal/gate clock signal Horizontal data enable signal/display enable signal Gate control signal/chroma data enable signal BTA-T1004 display data BTA-T1004 vertical sync BTA-T1004 horizontal sync BTA-T1004 display enable VSYNC input HSYNC input Panel source clock input Function Video data output pins. Video data output pins. Video data output pins. Vertical sync signal/gate start signal. Horizontal sync signal/sampling start signal. Vertical data enable signal/gate clock signal. Horizontal data enable signal/display enable signal. Gate control signal/display enable signal (asserted when the data matches the chroma-key color specified in the register). BTA-T1004 display data output pins. BTA-T1004 vertical sync signal. BTA-T1004 horizontal sync signal. BTA-T1004 display enable signal. VSYNC input pin used in external sync mode. HSYNC input pin used in external sync mode. Display source clock input pin. Input an appropriate frequency depending on the display panel. Panel clock output pin. DE_V/CLS DE_H/DE_C Output Output COM/CDE Output BT_DATA[7:0] BT_VSYNC BT_HSYNC BT_DE_C EX_VSYNC EX_HSYNC DCLKIN Output Output Output Output Input Input Input DCLKOUT Output Panel clock output Rev. 1.00 Nov. 22, 2007 Page 1223 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.4 VDC2 Configuration The VDC2 consists of seven functional blocks listed in table 24.2. Figure 24.1 shows the entire block diagram of the VDC2. Table 24.2 Functional Blocks in VDC2 Block Name Graphics block 1 (layer 1) Graphics block 2 (layer 2) Graphics block 3 (layer 3) Graphics block 4 (layer 4) Display control block Overview of Functions Reads a graphic image (RGB565: layer 1) stored in the external memory through the pixel bus and outputs it to graphics block 2. Reads a graphic image (RGB565: layer 2) stored in the external memory through the pixel bus, overlays it on the output from graphics block 1, and outputs the result to graphics block 3. Reads a graphic image (RGB565: layer 3) stored in the external memory through the pixel bus, overlays it on the output from graphics block 2, and outputs the result to graphics block 4. Reads a graphic image (RGB565: layer 4) stored in the external memory through the pixel bus, overlays it on the output from graphics block 3, and outputs the resultant image data. Converts the output (RGB) from graphics block 4 into the YCbCr(4:2:2) format and outputs the data in the 8:4:4 parallel format conforming to the BTA T-1004 standard. It also outputs the control signals for the TFT-LCD panel. Selects the timing of the external sync signal input with respect to the clock rising or falling edge and selects the sync signal polarity. Controls the timing of the sync signal output with respect to the clock rising or falling edge and controls the sync signal polarity. It also controls the timing of the RGB666 video output signals with respect to the clock rising or falling edge. Input timing control block Output timing control block Note: Layers 1 to 4 have the same configuration except that the bottom layer (layer 1) receives no image from another layer as the target of α blending. Rev. 1.00 Nov. 22, 2007 Page 1224 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) DCLKIN 1/2 or 1/1 (Layer 1) Graphics blocks (Layer 2) α blending (Layer 3) (Layer 4) RGB8:8:8 Display control block DCLKOUT RGB8:8:8 BTAT-1004 digital video output Output timing controller BT_DATA[7:0] BT_VSYNC BT_HSYNC BT_DE_C Conversion to Vertical/horizontal RGB8:8:8 timing control Internal sync signals Line buffer Pixel bus I/F Registers Input timing controller Timing control DR[5:0] DG[5:0] DB[5:0] VSYNC/SPS HSYNC/SPL DE_V/CLS DE_H/DEC COM/CDE DEH/LP DEC/PS Sync signal generator EX_VSYHC EX_HSYHC Registers Pixel bus graphic data 1 RGB565 Pixel bus graphic data 2 RGB565 Pixel bus graphic data 3 RGB565 Pixel bus graphic data 4 RGB565 Peripheral bus Figure 24.1 Block Diagram of VDC2 Rev. 1.00 Nov. 22, 2007 Page 1225 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.5 24.5.1 Functional Descriptions Graphics (Layers 1 to 4) The graphics blocks display in the RGB565 (16-bit) format the image data stored in the memory area. The graphics blocks control display by using the external input sync signals or internally generated sync signals. A single plane of an image can be displayed, and two to four planes of images can also be displayed through overlay processing. In overlaid display, the lower-layer images can be displayed through the current image (current layer) by specifying the α control area for the current layer (transparent processing). The transparency can be specified in 1/256 × 100% units. Transparent processing for the lower-layer images is also available through chroma-keying, which specifies the transparency of the specified target color. Figure 24.2 shows examples of overlaid display. Graphics block 1: Layer 1 (lower layer) α control area Graphics block 2: Layer 2 (current layer) Layers 1 and 2 can be α-blended by specifying an alpha control area in the graphic image area. Example 1: Output of Graphics Block 2 (Overlaid Display of Layers 1 and 2) Graphics block 2 output: Layers 1 and 2 overlaid (lower layers) ABC, MPG Graphics block 3: Layer 3 (current layer) ABC, MPG 2007/1/1 2007/1/1 The transparency of the chroma-key target color of layer 3 can be set to 100% through chroma-keying (a desired transparency can be specified). Chroma-key target color Example 2: Output of Graphics Block 3 (Overlaid Display of Layers 1 to 3) Figure 24.2 Examples of Overlaid Display Rev. 1.00 Nov. 22, 2007 Page 1226 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.5.2 Sync Signal Generation Figures 24.3 and 24.4 show examples of sync signal formats that can be generated. The VDC2 generates and outputs Vsync, Hsync, DEV, and DEH/DEC. VSYNC: Vertical sync signal HSYNC: Horizontal sync signal DEV: DEH: CDE: Vertical data enable signal Horizontal data enable signal Chroma data enable signal SPS: SPL: CLS: Gate start signal Sampling start signal Gate clock signal DEC: Data enable signal (composite) COM: Gate control signal Rev. 1.00 Nov. 22, 2007 Page 1227 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Panel clock Internal Hsync DEV VSYNC Internal Hsync HSYNC DEH Display area Internal Hsync DEV DEH DEC Note: The DEC signal is obtained by logically ANDing DEV and DEH (when DEC_MODE = 0 in SGMODE). The CDE signal is asserted when the graphic data matches the chroma-key target color specified in CDECRKY. Figure 24.3 Format 1 (Vsync, Hsync, DEV, DEH, DEC, and CDE Output) Rev. 1.00 Nov. 22, 2007 Page 1228 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Panel clock Internal Hsync SPL SPS CLS Internal Vsync CLS COM Display area Blanking interval COM signal: When com_mode = 0: Toggles in every line (inverted in every frame) When com_mode = 1: Inverted in every line SPS signal: The above figure shows the waveform when VSYNC_TIM = 1 (inverted output) in SYNCNT. Figure 24.4 Format 2 (SPS, SPL, CLS, and COM Output) Rev. 1.00 Nov. 22, 2007 Page 1229 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.5.3 External Sync Mode External sync mode outputs the graphic images with synchronizing the vertical or the horizontal sync signal that are from the external sync signal generating circuit such as TV or video. Inputs the vertical sync signal, the horizontal sync signal or the clock to corresponding pins, EX_VSYNC, EX_HSYNC or DCLKIN. Set up the registers related to the sync signals as follows. (1) Setting up External Sync Mode Set the SYNC_SEL bit to 1 in SGMODE register in order to make the external sync mode. If the electrode of input vertical/horizontal signal is negative, reverse the input data with setting the EX_V_TYPE bit to 1 and the EX_H_TYPE bit to 1 in SYNCNT register. (2) Setting up Output for COM/CDE Pins Set the COM_CDE_SEL bit to 1 and the CDE_EXE bit to 1 in SGMODEA register, and output CDE signal to the COM/CDE pins. Assert the CDE signal only if the signal corresponds to the target color of chroma-keying setting in the CDECRKY register. The COM_TYPE bit in SYNCNT controls the electrode of CDE signal. (3) Setting up Timing for Input and Output Set up the sampling timing for vertical/horizontal signal which is input data and the output timing for RGB data and CDE signal which are output data with DCLKIN rising or falling according to the specifications of the display as an external sync signal generating circuit. (refer to the SYNCNT register) VDC2 wait the EX_VSYNC signal staying in the vertical blanking interval until the signal input. (Vsync does not perform self-processing.) In the same way, when the EX_HSYNC signal is input to VDC2, VDC2 performs horizontal indicating completion and transfer to the next processing. VDC2 wait the EX_HSYNC signal staying in the horizontal blanking interval until the signal input. (Hsync does not perform self-processing.) 24.5.4 Digital Video Output For the BTA T-1004 digital video output, the VDC2 generates an 8-bit luminance signal (Y), chrominance signals (CB and CR), EAV, and SAV conforming to the BTA T-1004 (8:4:4-format parallel bit interface) standard. Rev. 1.00 Nov. 22, 2007 Page 1230 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.5.5 Conversion from RGB565 to YC444 The VDC2 converts the RGB565 format into the YC444 format in accordance with the ITU-R BT601 standard. First, RGB565 is converted to RGB888 through equation (1) shown below to control the R, G, and B values within the range from 0 to 255. Conversion from RGB to YC uses colorimetry conversion equation (2) prescribed in the BT601 standard. R1 = 255 R 31 G1 = 255 G 63 B1 = 255 B 31 Y 0.299 0.587 -0.331 0.114 R1 0.500 G1 + . . . . . (1) 16 128 128 . . . . . (2) Cb = -0.169 Cr 0.500 -0.419 -0.081 B1 24.5.6 Conversion from YC444 to YC422 The VDC2 converts the YC444 format to the YCbCr422 format. Figure 24.5 shows the timing of this conversion. The chrominance conversion from YC444 to YC422 uses the holding method. Internal HSYNC Y[7:0] Cb[7:0] Cr[7:0] Y (0) Cb (0) Cr (0) Y (1) Cb (1) Cr (1) Y (2) Cb (2) Cr (2) Y (3) Cb (3) Cr (3) ... ... Y (N - 1) Cb (N - 1) Cr (N - 1) Y[7:0] CbCr[7:0] Y (0) Cb (0) Y (1) Cr (0) Y (2) Cb (2) Y (3) Cr (2) ... ... Y (N - 2) Cb (N - 2) Y (N - 1) Cr (N - 2) Figure 24.5 Timing of Conversion from YC444 to YC422 Rev. 1.00 Nov. 22, 2007 Page 1231 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.5.7 Data Enable Signal (Composite) Either the data enable signal generated in the graphics blocks (obtained by logically ORing signals for layers 1 to 4) or the date enable signal (rectangle) generated in the display control block can be selected through the DEC_MODE bit in SGMODE. Internal HSYNC Internal HSYNC Internal VSYNC Internal VSYNC The data enable signal is asserted for the graphic image display areas of layers 1 to 4. Layers 1 to 4 The data enable signal generated in the display control area is asserted for this area. Figure 24.6 Data Enable Signals Rev. 1.00 Nov. 22, 2007 Page 1232 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6 Register Descriptions The following registers are allocated to the SH register map space. Legends for register description: Initial value: Register value after reset —: Undefined value R/W: Can be read from or written to; the written value can be read. R/WC0: Can be read from or written to; writing 0 initializes the bit but writing 1 is ignored. R/WC1: Can be read from or written to; writing 1 initializes the bit but writing 0 is ignored. R: Read-only; the write value should always be 0. —/W: Write-only; an undefined value is read. Rev. 1.00 Nov. 22, 2007 Page 1233 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Table 24.3 Register Configuration in Graphics Block 1 Register Name Graphics block control register Bus control register Reserved Reserved Reserved Reserved Graphic image base address register Graphic image area register Graphic image line offset register Graphic image start position register Reserved Reserved Reserved Reserved Reserved Abbreviation GRCMEN1 GRCBUSCNT1     GROPSADR1 GROPSWH1 GROPSOFST1 GROPDPHV1      R/W R/W R/W R R R R R/W R/W R/W R/W R R R R R P4 Area Address* Area 7 Address* Access Size 32, 16, or 8 32, 16, or 8 32, 16, or 8 H'FFEC 0000 H'1FEC 0000 H'FFEC 0004 H'1FEC 0004 H'FFEC 0008 H'1FEC 0008 H'FFEC 000C H'1FEC 000C 32, 16, or 8 H'FFEC 0300 H'1FEC 0300 H'FFEC 0304 H'1FEC 0304 H'FFEC 0308 H'1FEC 0308 32, 16, or 8 32, 16, or 8 32, 16, or 8 H'FFEC 030C H'1FEC 030C 32, 16, or 8 H'FFEC 0310 H'1FEC 0310 H'FFEC 0314 H'1FEC 0314 H'FFEC 0318 H'1FEC 0318 32, 16, or 8 32, 16, or 8 32, 16, or 8 H'FFEC 031C H'1FEC 031C 32, 16, or 8 H'FFEC 0320 H'1FEC 0320 H'FFEC 0324 H'1FEC 0324 H'FFEC 0328 H'1FEC 0328 32, 16, or 8 32, 16, or 8 32, 16, or 8 Color register for outside GROPBASERGB1 R/W of graphic image area Note: * H'FFEC 032C H'1FEC 032C 32, 16, or 8 Use a P4 area address to access a register in the P4 area in the virtual address space. Use an area 7 address to access a register from area 7 in the physical address space through the TLB. Rev. 1.00 Nov. 22, 2007 Page 1234 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Table 24.4 Register Configuration in Graphics Block 2 Register Name Graphics block control register Bus control register Reserved Reserved Reserved Reserved Graphic image base address register Graphic image area register Graphic image line offset register Graphic image start position register α control area register α control area start position register α control register Chroma-key control register Chroma-key color register Abbreviation GRCMEN2 GRCBUSCNT2     GROPSADR2 GROPSWH2 GROPSOFST2 GROPDPHV2 GROPEWH2 GROPEDPHV2 GROPEDPA2 GROPCRKY0_2 GROPCRKY1_2 R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W P4 Area Address* Area 7 Address* Access Size 32, 16, or 8 32, 16, or 8 32, 16, or 8 H'FFED 0000 H'1FED 0000 H'FFED 0004 H'1FED 0004 H'FFED 0008 H'1FED 0008 H'FFED 000C H'1FED 000C 32, 16, or 8 H'FFED 0300 H'1FED 0300 H'FFED 0304 H'1FED 0304 H'FFED 0308 H'1FED 0308 32, 16, or 8 32, 16, or 8 32, 16, or 8 H'FFED 030C H'1FED 030C 32, 16, or 8 H'FFED 0310 H'1FED 0310 H'FFED 0314 H'1FED 0314 H'FFED 0318 H'1FED 0318 32, 16, or 8 32, 16, or 8 32, 16, or 8 H'FFED 031C H'1FED 031C 32, 16, or 8 H'FFED 0320 H'1FED 0320 H'FFED 0324 H'1FED 0324 H'FFED 0328 H'1FED 0328 32, 16, or 8 32, 16, or 8 32, 16, or 8 Color register for outside GROPBASERGB2 R/W of graphic image area Note: * H'FFED 032C H'1FED 032C 32, 16, or 8 Use a P4 area address to access a register in the P4 area in the virtual address space. Use an area 7 address to access a register from area 7 in the physical address space through the TLB. Rev. 1.00 Nov. 22, 2007 Page 1235 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Table 24.5 Register Configuration in Graphics Block 3 Register Name Graphics block control register Bus control register Reserved Reserved Reserved Reserved Graphic image base address register Graphic image area register Graphic image line offset register Graphic image start position register α control area register α control area start position register α control register Chroma-key control register Chroma-key color register Abbreviation GRCMEN3 GRCBUSCNT3     GROPSADR3 GROPSWH3 GROPSOFST3 GROPDPHV3 GROPEWH3 GROPEDPHV3 GROPEDPA3 GROPCRKY0_3 GROPCRKY1_3 R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W P4 Area Address* H'FFEE 0000 H'FFEE 0004 H'FFEE 0008 Area 7 Address* H'1FEE 0000 H'1FEE 0004 H'1FEE 0008 Access Size 32, 16, or 8 32, 16, or 8 32, 16, or 8 H'FFEE 000C H'1FEE 000C 32, 16, or 8 H'FFEE 0300 H'FFEE 0304 H'FFEE 0308 H'1FEE 0300 H'1FEE 0304 H'1FEE 0308 32, 16, or 8 32, 16, or 8 32, 16, or 8 H'FFEE 030C H'1FEE 030C 32, 16, or 8 H'FFEE 0310 H'FFEE 0314 H'FFEE 0318 H'1FEE 0310 H'1FEE 0314 H'1FEE 0318 32, 16, or 8 32, 16, or 8 32, 16, or 8 H'FFEE 031C H'1FEE 031C 32, 16, or 8 H'FFEE 0320 H'FFEE 0324 H'FFEE 0328 H'1FEE 0320 H'1FEE 0324 H'1FEE 0328 32, 16, or 8 32, 16, or 8 32, 16, or 8 Color register for outside GROPBASERGB3 R/W of graphic image area Note: * H'FFEE 032C H'1FEE 032C 32, 16, or 8 Use a P4 area address to access a register in the P4 area in the virtual address space. Use an area 7 address to access a register from area 7 in the physical address space through the TLB. Rev. 1.00 Nov. 22, 2007 Page 1236 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Table 24.6 Register Configuration in Graphics Block 4 Register Name Graphics block control register Bus control register Reserved Reserved Reserved Reserved Graphic image base address register Graphic image area register Graphic image line offset register Graphic image start position register α control area register α control area start position register α control register Chroma-key control register Chroma-key color register Abbreviation GRCMEN4 GRCBUSCNT4     GROPSADR4 GROPSWH4 GROPSOFST4 GROPDPHV4 GROPEWH4 GROPEDPHV4 GROPEDPA4 GROPCRKY0_4 GROPCRKY1_4 R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W P4 Area Address* H'FFEF 0000 H'FFEF 0004 H'FFEF 0008 Area 7 Address* H'1FEF 0000 H'1FEF 0004 H'1FEF 0008 Access Size 32, 16, or 8 32, 16, or 8 32, 16, or 8 H'FFEF 000C H'1FEF 000C 32, 16, or 8 H'FFEF 0300 H'FFEF 0304 H'FFEF 0308 H'1FEF 0300 H'1FEF 0304 H'1FEF 0308 32, 16, or 8 32, 16, or 8 32, 16, or 8 H'FFEF 030C H'1FEF 030C 32, 16, or 8 H'FFEF 0310 H'FFEF 0314 H'FFEF 0318 H'1FEF 0310 H'1FEF 0314 H'1FEF 0318 32, 16, or 8 32, 16, or 8 32, 16, or 8 H'FFEF 031C H'1FEF 031C 32, 16, or 8 H'FFEF 0320 H'FFEF 0324 H'FFEF 0328 H'1FEF 0320 H'1FEF 0324 H'1FEF 0328 32, 16, or 8 32, 16, or 8 32, 16, or 8 Color register for outside GROPBASERGB4 R/W of graphic image area Note: * H'FFEF 032C H'1FEF 032C 32, 16, or 8 Use a P4 area address to access a register in the P4 area in the virtual address space. Use an area 7 address to access a register from area 7 in the physical address space through the TLB. Rev. 1.00 Nov. 22, 2007 Page 1237 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Table 24.7 Register Configuration in Display Control Block Register Name SG mode register Interrupt output control register Sync signal control register External sync signal input timing control register Reserved Abbreviation SGMODE SGINTCNT SYNCNT EXTSYNCNT R/W R/W R/W R/W R/W P4 Area Address* H'FFEB 0000 H'FFEB 0004 H'FFEB 0008 Area 7 Address* H'1FEB 0000 H'1FEB 0004 H'1FEB 0008 Access Size 32, 16, or 8 32, 16, or 8 32, 16, or 8 H'FFEB 000C H'1FEB 000C 32, 16, or 8  VSYNCTIM HSYNCTIM R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R H'FFEB 0100 H'FFEB 0104 H'FFEB 0108 H'1FEB 0100 H'1FEB 0104 H'1FEB 0108 32, 16, or 8 32, 16, or 8 32, 16, or 8 Sync signal size register SYNSIZE Vertical sync signal timing control register Horizontal sync signal timing control register H'FFEB 010C H'1FEB 010C 32, 16, or 8 H'FFEB 0110 H'FFEB 0118 H'1FEB 0110 H'1FEB 0118 32, 16, or 8 32, 16, or 8 Gate clock signal timing CLSTIM control register Sampling start signal timing control register Gate control signal timing control register SGDE area start position register SPLTIM COMTIM SGDESTART H'FFEB 011C H'1FEB 011C 32, 16, or 8 H'FFEB 0120 H'FFEB 0124 H'FFEB 0128 H'FFEB 0148 H'FFEB 0200 H'FFEB 0204 H'FFEB 0208 H'1FEB 0120 H'1FEB 0124 H'1FEB 0128 H'1FEB 0148 H'1FEB 0200 H'1FEB 0204 H'1FEB 0208 32, 16, or 8 32, 16, or 8 32, 16, or 8 32, 16, or 8 32, 16, or 8 32, 16, or 8 32, 16, or 8 SGDE area size register SGDESIZE CDE chroma-key color register Reserved T-1004 control register T-1004 video start position register Reserved Reserved Note: * CDECRKY  T1004CNT T1004OFFSET   H'FFEB 020C H'1FEB 020C 32, 16, or 8 Use a P4 area address to access a register in the P4 area in the virtual address space. Use an area 7 address to access a register from area 7 in the physical address space through the TLB. Rev. 1.00 Nov. 22, 2007 Page 1238 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.1 Graphics Block Control Registers (GRCMEN1 to GRCMEN4) Bit: 31 WE 30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: 0 R/W: R/W Bit: 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7  0 R 6  0 R 5  0 R 4  0 R 3  0 R 2  0 R 1 DEN 0 R 0 VEN Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 31 Bit Name WE Initial Value 0 R/W R/W Description Enables register value transfer. Writing 1 to this bit transfers the register values (registers at H'000 to H'31C and H'32C) in synchronization with Vsync. After register transfer is competed, this bit is cleared to 0. Reserved These bits are always read as 0. The write value should always be 0. 30 to 2  All 0 R 1 DEN 0 R/W Enables graphics display. 0: Disables display operation 1: Enables display operation 0 VEN 0 R/W Enables lower-layer graphics display. 0: Disables display operation 1: Enables display operation Rev. 1.00 Nov. 22, 2007 Page 1239 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Table 24.8 Functions of Display Enable Bits DEN 0 VEN 0 Operation Does not read image data from memory or process lower-layer graphics display. Output Outputs the color specified in GROPBASERGB over the entire screen (negates the enable signal output). Control 0 1 Does not read image data Outputs only the lower-layer Displays only the lowerfrom memory but graphics (outputs the lower- layer graphics. processes lower-layer layer graphics enable signal) graphics display. Reads image data from memory but does not process lower-layer graphics display. Reads image data from memory and processes lower-layer graphics display. Outputs only the current Displays only the current graphics (outputs the current graphics. graphics enable signal). Performs the specified processing for the current graphics and lower-layer graphics and displays them (logically ORs the current graphics and lower-layer graphics enable signals and outputs the result). Displays the current and lower-layer graphics. 1 0 1 1 Notes: 1. When the α control area (specified by GROPEW and GROPEDPHV) is larger than the graphic image area (specified by GROPSWH and GROPDPHV), only the lower-layer graphic images are displayed. 2. These bits should be set for each layer. When (DEN,VEN) = (0,0) in the upper layer, the graphics in the lower layers are not output. Rev. 1.00 Nov. 22, 2007 Page 1240 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.2 Bus Control Registers (GRCBUSCNT1 to GRCBUSCNT4) Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7  0 R 6  0 R 5  0 R 4  0 R 3  0 R 2  0 R 1  0 R 0 ENDIAN Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit 31 to 1 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 ENDIAN 0 R/W Specifies the endian for the pixel bus. 0: Little endian 1: Big endian MSB 127 16 bits 15 Pixel bus RGB7 0 RGB6 RGB5 RGB4 128 bits LSB 0 RGB3 RGB2 RGB1 RGB0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 Note: The image is displayed in the order of pixels (RGB0 -> RGB1 -> RGB2 -> ... -> RGB6 -> RGB7) from left to right. Figure 24.7 Pixel Bus Endian (ENDIAN = 0) Rev. 1.00 Nov. 22, 2007 Page 1241 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) MSB 127 16 bits 15 Pixel bus RGB0 0 RGB1 RGB2 RGB3 128 bits LSB 127 RGB4 RGB5 RGB6 RGB7 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 Note: The image is displayed in the order of pixels (RGB0 -> RGB1 -> RGB2 -> ... -> RGB6 -> RGB7) from left to right. Figure 24.8 Pixel Bus Endian (ENDIAN = 1) 24.6.3 Graphic Image Base Address Registers (GROPSADR1 to GROPSADR4) Bit: 31  30  29  28 27 26 25 24 23 22 21 20 19 18 17 16 GROPSADR[28:16] Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 GROPSADR[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 29 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 28 to 0 GROPSADR H'0000000 R/W [28:0] These bits specify the address from which a graphic image is to be read. The lowest bit should always be 0. Note: The VDC2 processes 16-bit RGB data; it cannot handle data located beyond a 2-byte alignment boundary. Rev. 1.00 Nov. 22, 2007 Page 1242 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.4 Graphic Image Area Registers (GROPSWH1 to GROPSWH4) Bit: 31  30  29  28  27  26  25 24 23 22 21 20 19 18 17 16 GROPSH[9:0] Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 GROPSW[9:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 26 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 15 to 10 GROPSH [9:0]  H'000 All 0 R/W R These bits specify the height of the graphic image area in number of lines. Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 GROPSW [9:0] H'000 R/W These bits specify the width of the graphic image area in number of panel clock cycles. Rev. 1.00 Nov. 22, 2007 Page 1243 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Internal Hsync GROPDPH + 16 GROPDPV + 1 GROPSW Graphic image area Figure 24.9 Graphic Image Area Settings (Reading from Memory) A graphic image area should be specified within the following range; otherwise, correct operation is not guaranteed. (Panel clock cycles for 1H) > GROPSW (width) + GROPDPH (horizontal display start position) + (16 panel clock cycles) (Lines for 1 frame) > GROPSH (height) + GROPDPV (vertical display start position) + (1 line) Rev. 1.00 Nov. 22, 2007 Page 1244 of 1692 REJ09B0360-0100 Internal Vsync GROPSH Section 24 Video Display Controller (VDC2) 24.6.5 Graphic Image Line Offset Registers (GROPSOFST1 to GROPSOFST4) Bit: 31  30  29  28 27 26 25 24 23 22 21 20 19 18 17 16 GROPSOFST[28:16] Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 GROPSOFST[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 29 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 28 to 0 GROPSOFST H'0000000 R/W [28:0] These bits specify the line offset for the graphic image. The lower four bits should always be 0000. GROPSOFST1 to GROPSOFST4 GROPSADR1 to GROPSADR4 Graphic image area Memory area for display Figure 24.10 Graphic Image Memory Area Settings The start (left side) address of line n is obtained by adding the base address register value (GROPSADR1 to GROPSADR4) and the line offset (GROPSOFST1 to GROPSOFST4) × n. Rev. 1.00 Nov. 22, 2007 Page 1245 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.6 Graphic Image Start Position Registers (GROPDPHV1 to GROPDPHV4) Bit: 31  30  29  28  27  26  25 24 23 22 21 20 19 18 17 16 GROPDPV[9:0] Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 GROPDPH[9:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 26 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 15 to 10 GROPDPV [9:0]  H'000 All 0 R/W R These bits specify the vertical display start position of the graphic image area in number of lines. Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 GROPDPH H'000 [9:0] R/W These bits specify the horizontal display start position of the graphic image area in number of panel clock cycles. Note: The display start address is offset as follows (see figure 24.9). Vertical offset: (GROPDPV value) + 1 line Horizontal offset: (GROPDPH value) + 16 panel clock cycles 24.6.7 α Control Area Registers (GROPEWH2 to GROPEWH4) Bit: 31  30  29  28  27  26  25 24 23 22 21 20 19 18 17 16 GROPEH[9:0] Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 GROPEW[9:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 1.00 Nov. 22, 2007 Page 1246 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Bit 31 to 26 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 15 to 10 GROPEH [9:0]  H'000 All 0 R/W R These bits specify the height of the α control area in number of lines. Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 GROPEW [9:0] H'000 R/W These bits specify the width of the α control area in number of panel clock cycles. Note: Layer 1 is the bottom image which has no α control target, so the above settings are prohibited for layer 1. Each register specifies the size of the α control area (rectangle). See figure 24.11. 24.6.8 α Control Area Start Position Registers (GROPEDPHV2 to GROPEDPHV4) Bit: 31  30  29  28  27  26  25 24 23 22 21 20 19 18 17 16 GROPEDPV[9:0] Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 GROPEDPH[9:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 1.00 Nov. 22, 2007 Page 1247 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Bit 31 to 26 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 15 to 10 GROPEDPV H'000 [9:0]  All 0 R/W R These bits specify the vertical start position of the α control area in number of lines. Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 GROPEDPH H'000 [9:0] R/W These bits specify the horizontal start position of the α control area in number of panel clock cycles. Note: Layer 1 is the bottom image which has no α control target, so the above settings are prohibited for layer 1. Internal HSync GROPEDPH + 16 GROPEW GROPEDPV + 1 Graphic image area α control area Internal VSync Figure 24.11 α Control Area Settings Rev. 1.00 Nov. 22, 2007 Page 1248 of 1692 REJ09B0360-0100 GROPEH Section 24 Video Display Controller (VDC2) 24.6.9 α Control Registers (GROPEDPA2 to GROPEDPA4) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DEFA[7:0] ACOEF[7:0] Initial value: 1 R/W: R/W Bit: 15 1 R/W 14 1 R/W 13 1 R/W 12 1 R/W 11 1 R/W 10 1 R/W 9 1 R/W 8 0 R/W 7 WE 0 R/W 6  0 R/W 5  0 R/W 4 AST 0 R/W 3  0 R/W 2 0 R/W 1 0 R/W 0 AEN ARATE[7:0] AMOD[1:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 31 to 24 23 to 16 Bit Name DEFA[7:0] Initial Value H'FF R/W R/W R/W Description These bits specify the initial α value. These bits specify a coefficient for α value calculation. This value is added to or subtracted from the DEFA value. These bits specify the frame rate of α control. (480p Vsync is used as the unit of counting.) Enables transfer of the α control register values. Writing 1 to this bit transfers the register values (registers at H'320 to H'328) in synchronization with Vsync. After register transfer is competed, this bit is cleared to 0. 0: Disables transfer 1: Enables transfer ACOEF[7:0] H'00 15 to 8 7 ARATE[7:0] H'00 WE 0 R/W R/W 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 AST 0 R α blending status flag. 0: Addition or subtraction has been completed 1: Addition or subtraction is in progress 3  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1249 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Bit 2, 1 Bit Name AMOD[1:0] Initial Value 00 R/W R/W Description These bits specify the α processing mode. 00: Initial α value (does not change the value) 01: α value addition 10: α value subtraction 11: Setting prohibited 0 AEN 0 R/W Enables or disables α control. 0: Disables α control (same as α value = 1) 1: enables α control Note: Layer 1 is the bottom image which has no α control target, so the above settings are prohibited for layer 1. When AEN = 1 and WE = 1, the α value is loaded in the internal circuits in synchronization with Vsync. If AMOD[1:0] = [0 0], the α value specified in DEFA is applied to the video area. If AMOD[1:0] = [0 1], the ACOEF value is added to the DEFA value according to the field rate and the result is applied to the video area as the α value. When the α value becomes 255 or larger, processing stops (fade-out). If AMOD[1:0] = [1 0], the ACOEF value is subtracted from the DEFA value according to the field rate and the result is applied to the video area as the α value. When the α value becomes 0 or smaller, processing stops (fade-in). Table 24.9 α Value and Blending Ratio α Value (Decimal) 255 254 253 252 Graphics 256/256 254/256 253/256 252/256 : 2/256 1 0 1/256 0/256 Lower-Layer Graphics 0/256 1/256 2/256 3/256 : 253/256 254/256 256/256 Rev. 1.00 Nov. 22, 2007 Page 1250 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.10 Chroma-Key Control Registers (GROPCRKY0_2 to GROPCRKY0_4) Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16 CKEN Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R/W 0 CROMAKR[4:0] CROMAKG[5:0] CROMARKB[4:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 17 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 16 CKEN 0 R/W Enables or disables chroma-key processing. 0: Disables chroma-key processing 1: Enables chroma-key processing 15 to 11 10 to 5 4 to 0 CROMAKR 00000 [4:0] CROMAKG 000000 [5:0] CROMAKB 00000 [4:0] R/W R/W R/W These bits specify chroma-key target color R. These bits specify chroma-key target color G. These bits specify chroma-key target color B. Note: Layer 1 is the bottom image which has no α control target, so the above settings are prohibited for layer 1. When WE =1 in GROPEDPA, the register setting is loaded in the internal circuits in synchronization with Vsync. While the chroma-key processing is enabled, if the graphics data values (RGB16 format) of a pixel all match the CROMAKR[4:0], CROMAKG[5:0], and CROMAKB[4:0] settings, the pixel color is replaced with the color (RGB16 format) specified in the chroma-key color register (GROPCRKY1) and α processing specified through the ALPHA[7:0] bits is applied. Chroma-keying thus enables characters or a cursor to be displayed on lower-layer graphics. Rev. 1.00 Nov. 22, 2007 Page 1251 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.11 Chroma-Key Color Registers (GROPCRKY1_2 to GROPCRKY1_4) Bit: 31  30  29  28  27  26  25  24  23 22 21 20 19 18 17 16 ALPHA[7:0] Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 R[4:0] 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R/W 7 G[5:0] 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 B[4:0] 0 R/W 1 0 R/W 0 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 24 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 15 to 11 10 to 5 4 to 0 ALPHA[7:0] H'00 R[4:0] G[5:0] B[4:0] 00000 000000 00000 R/W R/W R/W R/W These bits specify the α value after replacement. These bits specify the R value after replacement. These bits specify the G value after replacement. These bits specify the B value after replacement. Note: Layer 1 is the bottom image which has no α control target, so the above settings are prohibited for layer 1. Each register specifies a set of color information to replace the color that matches the chroma-key target RGB values. α calculation is done as follows. Output R = R (current graphic image) × α + R (lower-layer graphic image) × (1 - α) Output G = G (current graphic image) × α + G (lower-layer graphic image) × (1 - α) Output B = B (current graphic image) × α + B (lower-layer graphic image) × (1 - α) Rev. 1.00 Nov. 22, 2007 Page 1252 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.12 Color Registers for Outside of Graphic Image Area (GROPBASERGB1 to GROPBASERGB4) Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 BASE_R[4:0] 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 BASE_B[4:0] 0 R 1 0 R 0 BASE_G[5:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 16 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 11 10 to 5 4 to 0 BASE_R [4:0] BASE_G [5:0] BASE_B [4:0] 00000 000000 00000 R/W R/W R/W These bits specify the R value for outside of the graphic image area. These bits specify the G value for outside of the graphic image area. These bits specify the B value for outside of the graphic image area. Note: This setting is valid only when VEN = 0 in GRCMEN. Rev. 1.00 Nov. 22, 2007 Page 1253 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) DCLKOUT Panel clock Internal Hsync SYN_WIDTH HSYNC_START HSYNC_END IMAGE_START_H IMAGE_WIDTH HSYNC DEH DEV VSYNC IMAGE_START_V VSYNC_START IMAGE_HEIGHT SYN_HEIGHT VSYNC_END Internal Vsync Display area Internal Vsync DEV DEH DEC Note: The DEC signal is obtained by logically ANDing DEV and DEH (when DEC_MODE = 0 in SGMODE). The CDE signal is asserted when the graphic data matches the chroma-key target color specified in CDECRKY. Figure 24.12 Screen Format Rev. 1.00 Nov. 22, 2007 Page 1254 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.13 SG Mode Register (SGMODE) Bit: 31 WE 30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: 0 R/W: R/W Bit: 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9 COM_ CDE_SEL 0 R 8 CDE_ EXE 0 R 7  0 R 6  0 R 5 DE_ SEL 0 R 4 DEC_ MODE 0 R 3  0 R 2  0 R 1 SYNC _SEL 0 R 0  Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R Bit 31 Bit Name WE Initial Value 0 R/W R/W Description Enables register value transfer* . Writing 1 to this bit transfers the register values (registers at H'FFEB_0000 to H'FFEB_0208). Reserved These bits are always read as 0. The write value should always be 0. 1 30 to 10  All 0 R 9 COM_CDE_ 0 SEL R/W Selects the COM or CDE signal output. 0: Outputs COM 1: Outputs CDE 8 CDE_EXE 0 R/W Enables CDE operation. This setting becomes effective in synchronization with the internal Vsync timing. 0: Disables CDE operation (0 is always output through CDE when the COM_TYPE bit is 0 in SYNCNT) 1: Enables CDE operation 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 DE_SEL 0 R/W Selects the DEH or DEC signal output. 0: Outputs DEH (horizontal data enable) 1: Outputs DEC (horizontal and vertical composite data enable) Rev. 1.00 Nov. 22, 2007 Page 1255 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Bit 4 Bit Name Initial Value R/W R/W Description Selects the enable mode. 0: Outputs the data enable signal selected through the SGDESTART and SGDESIZE settings 1: Outputs the data enable signal generated in the graphics blocks (composite signal obtained by logically ORing the data enable signals of the layers)*2 DEC_MODE 0 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 SYNC_SEL 0 R/W Selects the sync signals. 0: Uses the internal sync signals 1: Uses the external sync signals (delayed by five panel clock cycles in the VDC2) 0  0 R Reserved This bit is always read as 0. The write value should always be 0. Notes: 1. Clear the WE bit to 0 before modifying the values of the registers located at H'000 to H'208; set the WE bit to 1 after modifying the registers. 2. When setting the DEC_MODE bit to 1, also set the DE_SEL bit to 1. Rev. 1.00 Nov. 22, 2007 Page 1256 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.14 Interrupt Output Control Register (SGINTCNT) Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7  0 R 6  0 R 5  0 R 4 VSYNC _MASK 0 R 3  0 R 2  0 R 1  0 R 0 VSYNC_ STATUS Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R/WC0 Bit 31 to 5 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 VSYNC_ MASK 0 R/W Masks the VSYNC interrupt*1. 0: Enables interrupts 1: Masks interrupts 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 VSYNC_ STATUS 1 R/WC0 Indicates the VSYNC interrupt status*2. 0: An interrupt has occurred 1: No interrupts have occurred Notes: 1. Writing 1 to the interrupt mask bit clears the interrupt status. 2. Writing 0 to the interrupt status bit clears the interrupt status. The VSYNC_STATUS value is output through the db_n_int_n signal terminal (low-active signal) of the VDC block. Rev. 1.00 Nov. 22, 2007 Page 1257 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.15 Sync Signal Control Register (SYNCNT) Bit: 31  30  29  28 RGB_ TIM 27  26  25 EX_V _TIM 24 EX_H _TIM 23  22  21 20 19 18 DEH _TIM 17 DEC _TIM 16 COM _TIM VSYNC HSYNC DEV _TIM _TIM _TIM Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R/W 12  0 R 11  0 R 10  0 R/W 9 0 R/W 8 0 R 7  0 R 6  0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 EX_V_ EX_H_ TYPE TYPE VSYNC HSYNC DEV DEH DEC COM _TYPE _TYPE _TYPE _TYPE _TYPE _TYPE Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 29 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 28 RGB_TIM 0 R/W Specifies the RGB data output timing. 0: Outputs data at the rising edge of the panel clock 1: Outputs data at the falling edge of the panel clock 27, 26  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25 EX_V_TIM 0 R/W Specifies the external VSYNC input timing. 0: Latches the external VSYNC at the rising edge of the panel clock 1: Latches the external VSYNC at the falling edge of the panel clock 24 EX_H_TIM 0 R/W Specifies the external HSYNC input timing. 0: Latches the external HSYNC at the rising edge of the panel clock 1: Latches the external HSYNC at the falling edge of the panel clock 23 to 22  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1258 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Bit 21 Bit Name VSYNC_ TIM Initial Value 0 R/W R/W Description Specifies the VSYNC/SPS output timing. 0: Outputs VSYNC/SPS at the rising edge of the panel clock 1: Outputs VSYNC/SPS at the falling edge of the panel clock 20 HSYNC_ TIM 0 R/W Specifies the HSYNC/SPL output timing. 0: Outputs HSYNC/SPL at the rising edge of the panel clock 1: Outputs HSYNC/SPL at the falling edge of the panel clock 19 DEV_TIM 0 R/W Specifies the DEV/CLS output timing. 0: Outputs DEV/CLS at the rising edge of the panel clock 1: Outputs DEV/CLS at the falling edge of the panel clock 18 DEH_TIM 0 R/W Specifies the DEH/LP output timing. 0: Outputs DEH/LP at the rising edge of the panel clock 1: Outputs DEH/LP at the falling edge of the panel clock 17 DEC_TIM 0 R/W Specifies the DEC/PS output timing. 0: Outputs DEC/PS at the rising edge of the panel clock 1: Outputs DEC/PS at the falling edge of the panel clock 16 COM_TIM 0 R/W Specifies the COM/CDE output timing. 0: Outputs COM/CDE at the rising edge of the panel clock 1: Outputs COM/CDE at the falling edge of the panel clock 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1259 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Bit 9 Bit Name EX_V_ TYPE Initial Value 0 R/W R/W Description Controls whether to invert the external VSYNC input. 0: Does not invert the external VSYNC input 1: Inverts the external VSYNC input 8 EX_H_ TYPE 0 R/W Controls whether to invert the external HSYNC input. 0: Does not invert the external HSYNC input 1: Inverts the external HSYNC input 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 VSYNC_ TYPE 0 R/W Controls whether to invert the VSYNC/SPS output. 0: Does not invert the VSYNC/SPS output. 1: Inverts the VSYNC/SPS output. 4 HSYNC_ TYPE 0 R/W Controls whether to invert the HSYNC/SPL output. 0: Does not invert the HSYNC/SPL output 1: Inverts the HSYNC/SPL output 3 DEV_TYPE 0 R/W Controls whether to invert the DEV/CLS output. 0: Does not invert the DEV/CLS output 1: Inverts the DEV/CLS output 2 DEH_TYPE 0 R/W Controls whether to invert the DEH/LP output. 0: Does not invert the DEH/LP output 1: Inverts the DEH/LP output 1 DEC_TYPE 0 R/W Controls whether to invert the DEC/PS output. 0: Does not invert the DEC/PS output 1: Inverts the DEC/PS output 0 COM_TYPE 0 R/W Controls whether to invert the COM/CDE output. 0: Does not invert the COM/CDE output 1: Inverts the COM/CDE output Rev. 1.00 Nov. 22, 2007 Page 1260 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.16 External Sync Signal Input Timing Control Register (EXTSYNCNT) Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16 EX_ STATUS Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7  0 R 6  0 R 5 0 R 4 0 R 3  0 R 2  0 R 1 0 R 0 EX_V_DLY EX_H_DLY Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit 31 to 17 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 16 EX_STATAS 0 R Indicates the status of the external VSYNC and HSYNC phases. 0: VSYNC and HSYNC are in phase 1: VSYNC and HSYNC are out of phase 15 to 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5, 4 EX_V_DLY [1:0] H'0 R/W These bits delay the external VSYNC input (dot clock cycles). 00: No delay 01: Delays by one dot clock cycle 10: Delays by two dot clock cycles 11: Delays by three dot clock cycles 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 EX_H_DLY [1:0] H'0 R/W These bits delay the external HSYNC input (dot clock cycles). 00: No delay 01: Delays by one dot clock cycle 10: Delays by two dot clock cycles 11: Delays by three dot clock cycles Rev. 1.00 Nov. 22, 2007 Page 1261 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) The VDC2 assumes that the external sync signals are input with the horizontal and vertical sync signal timing for the LCD panel conforming to the VESA standard. This register adjusts the phases of the external input sync signals when they are sampled in the VDC2. 24.6.17 Sync Signal Size Register (SYNSIZE) Bit: 31  30  29  28  27  26  25 24 23 22 21 20 19 18 17 16 SYN_HEIGHT[9:0] Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10 1 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 1 R/W 3 1 R/W 2 0 R/W 1 1 R/W 0 SYN_WIDTH[10:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 0 R/W Bit 31 to 26 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 SYN_HEIGHT H'20D [9:0]  All 0 R/W These bits specify the height including the vertical blanking interval in number of lines. Initial value: H'20D = 525 lines Reserved These bits are always read as 0. The write value should always be 0. 15 to 11 R 10 to 0 SYN_WIDTH [10:0] H'35A R/W These bits specify the width including the horizontal blanking interval in number of panel clock cycles. Initial value: H'35A = 858 dots Rev. 1.00 Nov. 22, 2007 Page 1262 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.18 Vertical Sync Signal Timing Control Register (VSYNCTIM) Bit: 31  30  29  28  27  26  25 24 23 22 21 20 19 18 17 16 VSYNC_START[9:0] Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 VSYNC_END[9:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W Bit 31 to 26 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 VSYNC_START H'000 [9:0] R/W These bits specify in number of lines the interval between the internal vertical sync signal and the point where the vertical sync signal (VSYNC) for the screen is set to 1. Reserved These bits are always read as 0. The write value should always be 0. 15 to 10  All 0 R 9 to 0 VSYNC_END [9:0] H'001 R/W These bits specify in number of lines the interval between the internal vertical sync signal and the point where the vertical sync signal (VSYNC) for the screen is cleared to 0. Note: Be sure to satisfy VSYNC_START ≠ VSYNC_END; otherwise, correct operation is not guaranteed. Rev. 1.00 Nov. 22, 2007 Page 1263 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.19 Horizontal Sync Signal Timing Control Register (HSYNCTIM) Bit: 31  30  29  28  27  26 25 24 23 22 21 20 19 18 17 16 HSYNC_START[10:0] Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 HSYNC_END[10:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W Bit 31 to 27 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 HSYNC_START H'000 [10:0] R/W These bits should always be set to H'000. These bits specify in number of panel clock cycles the interval between the internal horizontal sync signal and the point where the horizontal sync signal (HSYNC) for the screen is set to 1. Reserved These bits are always read as 0. The write value should always be 0. 15 to 11  All 0 R 10 to 0 HSYNC_END [10:0] H'00A R/W These bits specify in number of panel clock cycles the interval between the internal horizontal sync signal and the point where the horizontal sync signal (HSYNC) for the screen is cleared to 0. Note: Be sure to satisfy HSYNC_START ≠ HSYNC_END; otherwise, correct operation is not guaranteed. Rev. 1.00 Nov. 22, 2007 Page 1264 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.20 Gate Clock Signal Timing Control Register (CLSTIM) Bit: 31  30  29  28  27  26 25 24 23 22 21 20 19 18 17 16 CLS_START[10:0] Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 CLS_END[10:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 27 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 CLS_START [10:0] H'000 R/W These bits specify in number of panel clock cycles the interval between the internal horizontal sync signal and the point where the gate clock signal (CLS) is set to 1. Reserved These bits are always read as 0. The write value should always be 0. 15 to 11  All 0 R 10 to 0 CLS_END [10:0] H'000 R/W These bits specify in number of panel clock cycles the interval between the internal horizontal sync signal and the point where the gate clock signal (CLS) is cleared to 0. Note: Be sure to satisfy CLS_START ≠ CLS_END; otherwise, correct operation is not guaranteed. Rev. 1.00 Nov. 22, 2007 Page 1265 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.21 Sampling Start Signal Timing Control Register (SPLTIM) Bit: 31  30  29  28  27  26 25 24 23 22 21 20 19 18 17 16 SPL_START[10:0] Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 SPL_END[10:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 27 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 SPL_START H'000 [10:0] R/W These bits specify in number of panel clock cycles the interval between the internal horizontal sync signal and the point where the sampling start signal (SPL) is set to 1. Reserved These bits are always read as 0. The write value should always be 0. 15 to 11  All 0 R 10 to 0 SPL_END [10:0] H'000 R/W These bits specify in number of panel clock cycles the interval between the internal horizontal sync signal and the point where the sampling start signal (SPL) is cleared to 0. Note: Be sure to satisfy SPL_START ≠ SPL_END; otherwise, correct operation is not guaranteed. Rev. 1.00 Nov. 22, 2007 Page 1266 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.22 Gate Control Signal Timing Control Register (COMTIM) Bit: 31 COM_ MODE 30  29  28  27  26  25 24 23 22 21 20 19 18 17 16 COMTIM_V[9:0] Initial value: 0 R/W: R/W Bit: 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 COMTIM_H[10:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 Bit Name Initial Value R/W R/W Description Selects the gate control signal (COM) toggle mode. 0: Toggles the signal output in every line in an alternating sequence of high and low and inverts the phase in every frame (when the sequence in frame n is high -> low -> high ..., it is inverted to low -> high -> low ... in frame n + 1). 1: Toggles the signal output in every frame. COM_MODE 0 30 to 26  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 COMTIM_V [9:0] H'000 R/W These bits specify in number of lines the interval between the internal vertical sync signal and the frame start position of the gate control signal (COM). A value of 0 specifies that a frame starts in the first line, and a value of 1 specifies that a frame starts in the second line. Reserved These bits are always read as 0. The write value should always be 0. 15 to 11  All 0 R 10 to 0 COMTIM_H [10:0] H'000 R/W These bits specify in number of panel clock cycles the horizontal interval between the internal horizontal sync signal and the position where the gate control signal (COM) toggles. Note: Be sure to satisfy COMTIM_V < SYN_HEIGHT; otherwise, correct operation is not guaranteed. Rev. 1.00 Nov. 22, 2007 Page 1267 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) CLS SPS (low-active) Last line COM Frame (internal signal) First line Second line Frame timing (when COMTIM_V = 0) Figure 24.13 COM Signal Timing 24.6.23 SGDE Area Start Position Register (SGDESTART) Bit: 31  30  29  28  27  26  25 24 23 22 21 20 19 18 17 16 SGDE_START_V[9:0] Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 SGDE_START_H[10:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 26 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 SGDE_START H'000 _V[9:0] R/W These bits specify in number of lines the vertical interval between the internal vertical sync signal and the start of the data enable (DE) signal output. Setting to 0 is prohibited. Reserved These bits are always read as 0. The write value should always be 0. 15 to 11  All 0 R 10 to 0 SGDE_START H'000 _H[10:0] R/W These bits specify in number of panel clock cycles the horizontal interval between the internal horizontal sync signal and the start of the data enable (DE) signal output. Notes: 1. Be sure to satisfy SYN_HEIGHT > SGDE_HEIGHT + SGDE_START_V; otherwise, correct operation is not guaranteed. 2. Be sure to satisfy SYN_WIDTH > SGDE_WIDTH + SGDE_START_H; otherwise, correct operation is not guaranteed. Rev. 1.00 Nov. 22, 2007 Page 1268 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Internal Hsync SGDE_START_H SGDE_WIDTH SGDE_HEIGHT SGDE_START_V SDDE area Figure 24.14 Settings of DE Area Generated in SG Block Internal Vsync Rev. 1.00 Nov. 22, 2007 Page 1269 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.24 SGDE Area Size Register (SGDESIZE) Bit: 31  30  29  28  27  26  25 24 23 22 21 20 19 18 17 16 SGDE_HEIGHT[9:0] Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 SGDE_WIDTH[10:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 26 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 15 to 11 SGDE_HEIGHT H'000 [9:0]  All 0 R/W R These bits specify the vertical length (height) of the data enable (DE) signal area in number of lines. Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 SGDE_WIDTH [10:0] H'000 R/W These bits specify the horizontal length (width) of the data enable (DE) signal area in number of panel clock cycles. Rev. 1.00 Nov. 22, 2007 Page 1270 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.25 CDE Chroma-Key Color Register (CDECRKY) Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 CDE_R[4:0] 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 CDE_B[4:0] 0 R 1 0 R 0 CDE_G[5:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 16 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 11 10 to 5 4 to 0 CDE_R[4:0] 00000 CDE_G[5:0] 000000 CDE_B[4:0] 00000 R/W R/W R/W These bits specify the R value as the target of chroma-keying to output the CDE signal. These bits specify the G value as the target of chroma-keying to output the CDE signal. These bits specify the B value as the target of chroma-keying to output the CDE signal. Note: After the overlay processing (layer 1 + layer 2 + layer 3 + layer 4) is applied to a graphic image, the resultant image data is compared with the above specified color and the VDC2 outputs the CDE signal when they match (chroma-keying is not applied for each layer). Rev. 1.00 Nov. 22, 2007 Page 1271 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.26 T1004 Control Register (T1004CNT) Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7  0 R 6  0 R 5  0 R 4  0 R 3  0 R 2 0 R 1 0 R 0 VSYNC HSYNC DEC _TYPE _TYPE _TYPE Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 31 to 3 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 VSYNC_ TYPE 0 R/W Selects the polarity of VSYNC in T-1004 format. 0: Positive 1: Negative 1 HSYNC_ TYPE 0 R/W Selects the polarity of HSYNC in T-1004 format. 0: Positive 1: Negative 0 DEC_TYPE 0 R/W Selects the polarity of DEC (data enable) in T-1004 format. 0: Positive 1: Negative Rev. 1.00 Nov. 22, 2007 Page 1272 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) 24.6.27 T1004 Video Start Position Register (T1004OFFSET) Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 T1004OFFSET_H[10:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 11 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 T1004OFFSET 0 _H[10:0] R/W These bits adjust the horizontal phase of the video signal and blanking interval in 2-pixel units. Specifying a larger value shifts the video display position left. The lowest two bits (bits 1 and 0) should always be 0. Table 24.10 shows an example of register settings to display the video at the top-left corner of the active area. Table 24.10 Example of Register Settings for T-1004 Output Register Setting Description Starts video output from line 40 with respect to the internal Vsync and panel clock cycle 131 with respect to the internal Hsync. Specifies 525 lines for the vertical sync signal period and 858 panel clock cycles for the horizontal sync signal. Adjusts the horizontal phase of the video signal and blanking interval. Increasing the register value by H'4 shifts the display position left by two pixels; decreasing the value by H'4 shifts the display position right by two pixels. Graphics blocks GROPDPHV1 to H'0026_0072 GROPDPHV4 Display control block SYNSIZE H'020D_35A T1004OFFSET H'0000_0010 Rev. 1.00 Nov. 22, 2007 Page 1273 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Internal Hsync GROPDPH + 16 (130 pclk) GROPSW (720 pclk) (8 pclk) GROPDPV + 1 (39 lines) Active area (2F) Internal Vsync (6 lines) Blanking interval (Y = 0 x 10, C = 0 x 80) Figure 24.15 T-1004 Video Output Position Rev. 1.00 Nov. 22, 2007 Page 1274 of 1692 REJ09B0360-0100 Active area (1F) (480 lines) GROPSH Image area Section 24 Video Display Controller (VDC2) 24.7 24.7.1 Operating Procedures Display Control Block 1. Disabling register value transfer Clear the WE bit to 0 in the SG mode register. 2. Setting the registers in the display control block Make appropriate settings in the registers shown in table 24.9. Specify the polarity of the external pins first. 3. Enabling register value transfer Set the WE bit to 1 in the SG mode register. 24.7.2 Graphics Blocks 1. Disabling register value transfer Clear the WE bit to 0 in the graphics block control registers. Clear the WE bit to 0 in the α control registers. 2. Setting the registers in the graphics blocks Make appropriate settings in the registers shown in tables 24.5 through 24.8. 3. Enabling register value transfer Set the WE bit to 1 in the graphics block control registers. Set the WE bit to 1 in the α control registers. The display operation specified in the registers starts from the next frame. Rev. 1.00 Nov. 22, 2007 Page 1275 of 1692 REJ09B0360-0100 Section 24 Video Display Controller (VDC2) Rev. 1.00 Nov. 22, 2007 Page 1276 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Section 25 NAND Flash Memory Controller (FLCTL) The NAND flash memory controller (FLCTL) provides interfaces for an external NAND-type flash memory. To take measures for errors specific to flash memory, the FLCTL supports the ECC-code generation function and error detection function. Note: The flash memory using Multi Level Cell (MLC) technology is not supported by this LSI. 25.1 Features NAND-Type Flash Memory Interface: • Interface directly connectable to NAND-type flash memory • Read or write in sector units (512 + 16 bytes) and ECC processing executed An access unit of 2048 + 64 bytes, referred to as a page, is used in some datasheets for NANDtype flash memory. In this manual, an access unit of 512 + 16 bytes, referred to as a sector, is always used. • Read or write in byte units Access Modes: The FLCTL can select one of the following two access modes. • Command access mode: Performs an access by specifying a command to be issued from the FLCTL to flash memory, address, and data size to be input or output. Read, write, or erasure of data without ECC processing can be achieved. • Sector access mode: Performs a read or write in physical sector units by specifying a physical sector and controls ECC-code generation and check. By specifying the number of sectors, the continuous physical sectors can be read or written. Sectors and Control Codes: • A sector is comprised of 512-byte data and 16-byte control code. The 16-byte control code includes 8-byte ECC. • The position of the ECC in the control code can be specified in 4-byte units. • User information can be written to the control code other than the ECC. Rev. 1.00 Nov. 22, 2007 Page 1277 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) ECC: • 8-byte ECC code is generated and error check is performed for a sector (512-byte data + 16byte control code). (Note that the ECC code generation in the 16-byte control code and the number of bytes to be checked differ depending on the specifications.) • Error correction capability is up to three errors. • In a write operation, an ECC code is generated for data and control code prior to the ECC. The control code following the ECC is not considered. • In a read operation, an ECC error is checked for data and control code prior to the ECC. An ECC on the control code in the FIFO is replaced with the check result by the ECC circuit, not an ECC code read from flash memory. • An error correction is not performed even when an ECC error occurs. Error corrections must be performed by software. Data Error: • When a program error or erase error occurs, the error is reflected on the error source flags. Interrupts for each source can be specified. • When a read error occurs, an ECC in the control code is other than 0. This read error is reflected on the ECC error source flag. • When an ECC error occurs, perform an error correction, specify another sector to be replaced, and copy the contents of the block to another sector as required. Data Transfer FIFO and Data Register: • The 224-byte FLDTFIFO is incorporated for data transfer of flash memory. • The 32-byte FLECFIFO is incorporated for data transfer of control code. • The overrun/underrun detection flag is provided for the access from the CPU and DMA. DMA Transfer: • By individually specifying the destinations of data and control code of flash memory to the DMA controller, data and control code can be sent to different areas. Access Size: • Registers can be accessed in 32 bits or 8 bits. Registers must be accessed in the specified access size. Rev. 1.00 Nov. 22, 2007 Page 1278 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Access Time: • The operating frequency of the FLCTL pins can be specified by the FCKSEL bit and the QTSEL bit in the common control register (FLCMNCR), regardless of the operating frequency of the peripheral bus. • Before changing the CPG specification, the FLCTL must be placed in a module stop state. • In NAND-type flash memory, the FRE and FWE pins operate with the frequency on the pins which CPG designated. To ensure the setup time, these operating frequencies must be specified within the maximum operating frequency of memory to be connected. • The operating clock FCLK on the pins for the NAND-type flash memory is generated by dividing the peripheral bus operating clock Pck. Rev. 1.00 Nov. 22, 2007 Page 1279 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Figure 25.1 shows a block diagram of the FLCTL. DMAC Peripheral bus DMA transfer requests (2 lines) Interrupts (4 lines) 32 Peripheral bus interface 32 32 Registers 32 QTSEL FCKSEL State machine 32 FIFO 256 bytes ECC Transmission/ reception control FCLK ×1, ×1/2, CPG ×1/4 Peripheral clock Pck 8 8 8 FLASH IF FLCTL 8 Control signal Note: FCLK is an operating clock for interface signals with flash memory. It is specified by the CPG. NAND FLASH Figure 25.1 FLCTL Block Diagram Rev. 1.00 Nov. 22, 2007 Page 1280 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) 25.2 Input/Output Pins The pin configuration of the FLCTL is listed in table 25.1. Table 25.1 Pin Configuration Corresponding Flash Memory Pin CE I/O7 to I/O0 CLE Pin Name FCE FD7 to FD0 FCLE Function Chip enable Data I/O pins I/O Output I/O Description Enables flash memory connected to this LSI. I/O pins for command, address, and data. Command Latch Enable (CLE) Asserted when a command is output. Command data Output enable Address latch enable Output FALE ALE Address Latch Enable (ALE) Asserted when an address is output and negated when data is input or output. FRE FWE Read enable Output RE WE Read Enable (RE) Reads data at the falling edge of RE. Write enable Output Write Enable Flash memory latches a command, address, and data at the rising edge of WE. FR/B Ready/busy Input R/B Ready/Busy Indicates ready state at high level; indicates busy state at low level. Rev. 1.00 Nov. 22, 2007 Page 1281 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) 25.3 Register Descriptions Table 25.2 shows the FLCTL register configuration. Table 25.3 shows the register state in each processing mode. Table 25.2 Register Configuration of FLCTL Name Common control register Command control register Command code register Address register Address register 2 Data register Data counter register Interrupt DMA control register Ready busy timeout setting register Ready busy timeout counter Data FIFO register Control code FIFO register Transfer control register Abbreviation FLCMNCR FLCMDCR FLCMCDR FLADR FLADR2 FLDATAR FLDTCNTR R/W R/W R/W R/W R/W R/W R/W R/W Area P4 Address H'FFE9 0000 H'FFE9 0004 H'FFE9 0008 H'FFE9 000C H'FFE9 003C H'FFE9 0010 H'FFE9 0014 H'FFE9 0018 H'FFE9 001C H'FFE9 0020 H'FFE9 0024/ H'FFE9 0050 H'FFE9 0028/ H'FFE9 0060 H'FFE9 002C Area 7 Address H'1FE9 0000 H'1FE9 0004 H'1FE9 0008 H'1FE9 000C H'1FE9 003C H'1FE9 0010 H'1FE9 0014 H'1FE9 0018 H'1FE9 001C H'1FE9 0020 H'1FE9 0024/ H'1FE9 0050 H'1FE9 0028/ H'1FE9 0060 H'1FE9 002C Access Size 32 32 32 32 32 32 32 32 32 32 32 32 8 FLINTDMACR R/W FLBSYTMR FLBSYCNT FLDTFIFO FLECFIFO FLTRCR R/W R R/W R/W R/W Rev. 1.00 Nov. 22, 2007 Page 1282 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Table 25.3 Register State of FLCTL in Each Processing Mode Register Abbreviation FLCMNCR FLCMDCR FLCMCDR FLADR FLADR2 FLDATAR FLDTCNTR FLINTDMACR FLBSYTMR FLBSYCNT FLDTFIFO FLECFIFO FLTRCR Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1283 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) 25.3.1 Common Control Register (FLCMNCR) FLCMNCR is a 32-bit readable/writable register that specifies the type (NAND) of flash memory, access mode, and FCE pin output. Bit: 31 — Initial value: R/W: Bit: 0 R 15 FCK SEL 30 — 0 R 14 — 0 R 29 — 0 R 13 28 — 0 R 12 27 — 0 R 11 26 — 0 R 10 25 — 0 R 9 NAND WF 24 — 0 R 8 — 0 R 23 — 0 R 7 — 0 R 22 — 0 R 6 — 0 R 21 — 0 R 5 — 0 R 20 — 0 R 4 — 0 R 19 — 0 R 3 CE0 0 R/W 18 SNAND 17 QT SEL 16 — 0 R 0 TYPE SEL 0 R/W 2 — 0 R 0 R/W 1 — 0 R ECCPOS[1:0] ACM[1:0] 0 R/W 0 R/W Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 19 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 18 SNAND 0 R/W Large-Capacity NAND Flash Memory Select This bit is used to specify 1-Gbit or larger NAND flash memory with the page configuration of 2048 + 64 bytes. 0: When flash memory with the page configuration of 512 + 16 bytes is used. 1: When NAND flash memory with the page configuration of 2048 + 64 bytes is used. Note: When TYPESEL = 0, this bit should not be set to 1. Rev. 1.00 Nov. 22, 2007 Page 1284 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 17 Bit Name QTSEL Initial Value 0 R/W R/W Description Select Dividing Rates for Flash Clock Selects the dividing rate of clock FCLK in the flash memory. This bit is used together with FCKSEL. • • • • QTSEL = 0, FCKSEL = 0: Divides a clock (Pck) provided from the CPG by two and uses it as FCLK. QTSEL = 0, FCKSEL = 1: Uses a clock (Pck) provided from the CPG as FCLK. QTSEL = 1, FCKSEL = 0: Divides a clock (Pck) provided from the CPG by four and uses it as FCLK. QTSEL = 1, FCKSEL = 1: Setting prohibited 16 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 15 FCKSEL 0 R/W Flash Clock Select Selects the dividing rate of clock FCLK in the flash memory. This bit is used together with QTSEL. Refer to the description of QTSEL. 14 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 13, 12 ECCPOS [1:0] 00 R/W ECC Position Specification 1 and 0 Specify the position (0/4th/8th byte) to place the ECC in the control code area. 00: Places the ECC at the 0 to 7th byte of control code area 01: Places the ECC at the 4th to 11th byte of control code area 10: Places the ECC at the 8th to 15th byte of control code area 11: Setting prohibited Rev. 1.00 Nov. 22, 2007 Page 1285 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 11, 10 Bit Name ACM[1:0] Initial Value 00 R/W R/W Description Access Mode Specification 1 and 0 Specify access mode. 00: Command access mode 01: Sector access mode 10: Setting prohibited 11: Setting prohibited 9 NANDWF 0 R/W NAND Wait Insertion Operation 0: Performs address or data input/output in one FCLK cycle 1: Performs address or data input/output in two FCLK cycles 8 to 4 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 CE0 0 R/W Chip Enable 0 0: Disables the chip (Outputs high level to the FCE pin) 1: Enables the chip (Outputs low level to the FCE pin) 2, 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 TYPESEL 0 R/W Memory Select 0: Reserved 1: NAND-type flash memory is selected Note: Set this bit to 1 when using FLCTL. Rev. 1.00 Nov. 22, 2007 Page 1286 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) 25.3.2 Command Control Register (FLCMDCR) FLCMDCR is a 32-bit readable/writable register that issues a command in command access mode, specifies address issue, and specifies source or destination of data transfer. In sector access mode, FLCMDCR specifies the number of sector transfers. Bit: 31 ADR CNT2 30 29 28 27 26 ADR MD 25 CDS RC 24 DOSR 23 — 0 R 7 22 — 0 R 6 21 SEL RW 20 DOA DR 19 18 17 DOC MD2 16 DOC MD1 SCTCNT[19:16] ADRCNT[1:0] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 SCTCNT[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 Bit Name Initial Value R/W R Description Address Issue Byte Count Specification Specifies the number of bytes for the address data to be issued in address stage. This bit is used together with ADRCNT[1:0]. 0: Issue the address of byte count, specified by ADRCNT[1:0]. 1: Issue 5-byte address. ADRCNT[1:0] should be set to 00. ADRCNT2 0 30 to 27 SCTCNT [19:16] All 0 R/W Sector Transfer Count Specification [19:16] These bits are extended bits of the sector transfer count specification [15:0], SCTCNT[15:0]. SCTCNT[19:16] and SCTCNT[15:0] are used together to operate as SCTCNT[19:0], the 20-bit counter. Rev. 1.00 Nov. 22, 2007 Page 1287 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 26 Bit Name ADRMD Initial Value 0 R/W R/W Description Sector Access Address Specification This bit is invalid in command access mode. This bit is valid only in sector access mode. 0: The value of the address register is handled as a physical sector number. Use this value usually in sector access. 1: The value of the address register is output as the address of flash memory. Note: Clear this bit to 0 in continuous sector access. 25 CDSRC 0 R/W Data Buffer Specification Specifies the data buffer to be read from or written to in the data stage in command access mode. 0: Specifies FLDATAR as the data buffer. 1: Specifies FLDTFIFO as the data buffer. 24 DOSR 0 R/W Status Read Check Specifies whether or not the status read is performed after the second command has been issued in command access mode. 0: Performs no status read 1: Performs status read 23, 22 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 21 SELRW 0 R/W Data Read/Write Specification Specifies the direction of read or write in data stage. 0: Read 1: Write 20 DOADR 0 R/W Address Stage Execution Specification Specifies whether or not the address stage is executed in command access mode. 0: Performs no address stage 1: Performs address stage Rev. 1.00 Nov. 22, 2007 Page 1288 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 19, 18 Bit Name ADRCNT [1:0] Initial Value 00 R/W R/W Description Address Issue Byte Count Specification Specify the number of bytes for the address data to be issued in address stage. 00: Issue 1-byte address 01: Issue 2-byte address 10: Issue 3-byte address 11: Issue 4-byte address 17 DOCMD2 0 R/W Second Command Stage Execution Specification Specifies whether or not the second command stage is executed in command access mode. 0: Does not execute the second command stage 1: Executes the second command stage 16 DOCMD1 0 R/W First Command Stage Execution Specification Specifies whether or not the first command stage is executed in command access mode. 0: Does not execute the first command stage 1: Executes the first command stage 15 to 0 SCTCNT [15:0] H'0000 R/W Sector Transfer Count Specification [15:0] Specify the number of sectors to be read continuously in sector access mode. These bits are counted down for each sector transfer end and stop when they reach 0. These bits are used together with SCTCNT[19:16]. In command access mode, these bits are H'0 0001. Rev. 1.00 Nov. 22, 2007 Page 1289 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) 25.3.3 Command Code Register (FLCMCDR) FLCMCDR is a 32-bit readable/writable register that specifies a command to be issued in command access or sector access. Bit: 31 — Initial value: R/W: Bit: 0 R 15 30 — 0 R 14 29 — 0 R 13 28 — 0 R 12 27 — 0 R 11 26 — 0 R 10 25 — 0 R 9 24 — 0 R 8 23 — 0 R 7 22 — 0 R 6 21 — 0 R 5 20 — 0 R 4 19 — 0 R 3 18 — 0 R 2 17 — 0 R 1 16 — 0 R 0 CMD[15:8] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W CMD[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 16 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 8 7 to 0 CMD[15:8] H'00 CMD[7:0] H'00 R/W R/W Specify a command code to be issued in the second command stage. Specify a command code to be issued in the first command stage. Rev. 1.00 Nov. 22, 2007 Page 1290 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) 25.3.4 Address Register (FLADR) FLADR is a 32-bit readable/writable register that specifies an address to be output in command access mode. In sector access mode, a physical sector number specified in the physical sector address bits is converted into an address to be output. • Command Access Mode Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADR[31:24] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 ADR[23:16] 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 ADR[15:8] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W ADR[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W R/W Description Fourth Address Data Specify 4th data to be output to flash memory as an address in command access mode. 31 to 24 ADR[31:24] H'00 23 to 16 ADR[23:16] H'00 R/W Third Address Data Specify 3rd data to be output to flash memory as an address in command access mode. 15 to 8 ADR[15:8] H'00 R/W Second Address Data Specify 2nd data to be output to flash memory as an address in command access mode. 7 to 0 ADR[7:0] H'00 R/W First Address Data Specify 1st data to be output to flash memory as an address in command access mode. Rev. 1.00 Nov. 22, 2007 Page 1291 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) • Sector Access Mode Bit: 31 — Initial value: R/W: Bit: 0 R 15 30 — 0 R 14 29 — 0 R 13 28 — 0 R 12 27 — 0 R 11 26 — 0 R 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 25 24 23 22 21 20 19 18 17 16 ADR[25:16] 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 ADR[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 26 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 25 to 0 ADR[25:0] H'000 0000 R/W Physical Sector Address Specify a physical sector number to be accessed in sector access mode. The physical sector number is converted into an address and is output to flash memory. When the ADRCNT2 bit in FLCMDCR = 1, the ADR[25:0] bits are valid. When the ADRCNT2 bit in FLCMDCR = 0, the ADR[17:0] bits are valid. Rev. 1.00 Nov. 22, 2007 Page 1292 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) 25.3.5 Address Register 2 (FLADR2) FLADR2 is a 32-bit readable/writable register, and is valid when the ADRCNT2 bit in FLCMDCR is set to 1. FLADR2 specifies an address to be output in command access mode. Bit: 31 — Initial value: R/W: Bit: 0 R 15 — Initial value: R/W: 0 R 30 — 0 R 14 — 0 R 29 — 0 R 13 — 0 R 28 — 0 R 12 — 0 R 27 — 0 R 11 — 0 R 26 — 0 R 10 — 0 R 25 — 0 R 9 — 0 R 24 — 0 R 8 — 0 R 0 R/W 0 R/W 0 R/W 23 — 0 R 7 22 — 0 R 6 21 — 0 R 5 20 — 0 R 4 19 — 0 R 3 18 — 0 R 2 17 — 0 R 1 16 — 0 R 0 ADR[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 8 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 ADR[7:0] All 0 R/W Fifth Address Data Specify 5th data to be output to flash memory as an address in command access mode. Rev. 1.00 Nov. 22, 2007 Page 1293 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) 25.3.6 Data Counter Register (FLDTCNTR) FLDTCNTR is a 32-bit readable/writable register that specifies the number of bytes to be read or written in command access mode. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ECFLW[7:0] Initial value: R/W: Bit: 0 R 15 — Initial value: R/W: 0 R 0 R 14 — 0 R 0 R 13 — 0 R 0 R 12 — 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 DTFLW[7:0] 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 DTCNT[11:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 24 Bit Name Initial Value R/W R Description FLECFIFO Access Count Specify the number of longwords in FLECFIFO to be read or written. These bit values are used when the CPU reads from or writes to FLECFIFO. In FLECFIFO read, these bits specify the number of longwords of the data that can be read from FLECFIFO. In FLECFIFO write, these bits specify the number of longwords of unoccupied area that can be written in FLECFIFO. ECFLW[7:0] H'00 23 to 16 DTFLW[7:0] H'00 R FLDTFIFO Access Count Specify the number of longwords in FLDTFIFO to be read or written. These bit values are used when the CPU reads from or writes to FLDTFIFO. In FLDTFIFO read, these bits specify the number of longwords of the data that can be read from FLDTFIFO. In FLDTFIFO write, these bits specify the number of longwords of unoccupied area that can be written in FLDTFIFO. 15 to 12 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1294 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 11 to 0 Bit Name Initial Value R/W R/W Description Data Count Specification Specify the number of bytes of data to be read or written in command access mode. (Up to 2048 + 64 bytes can be specified.) DTCNT[11:0] H'000 25.3.7 Data Register (FLDATAR) FLDATAR is a 32-bit readable/writable register. It stores input/output data used when 0 is written to the CDSRC bit in FLCMDCR in command access mode. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DT[31:24] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 DT[23:16] 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 DT[15:8] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W DT[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 24 Bit Name DT[31:24] Initial Value H'00 R/W R/W Description Fourth Data Specify the 4th data to be input or output via the FD7 to FD0 pins. In write: Specify write data In read: Store read data 23 to 16 DT[23:16] H'00 R/W Third Data Specify the 3rd data to be input or output via the FD7 to FD0 pins. In write: Specify write data In read: Store read data Rev. 1.00 Nov. 22, 2007 Page 1295 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 15 to 8 Bit Name DT[15:8] Initial Value H'00 R/W R/W Description Second Data Specify the 2nd data to be input or output via the FD7 to FD0 pins. In write: Specify write data In read: Store read data 7 to 0 DT[7:0] H'00 R/W First Data Specify the 1st data to be input or output via the FD7 to FD0 pins. In write: Specify write data In read: Store read data 25.3.8 Interrupt DMA Control Register (FLINTDMACR) FLINTDMACR is a 32-bit readable/writable register that enables or disables DMA transfer requests or interrupts. A transfer request from the FLCTL to the DMAC is issued after each access mode has been started. Bit: 31 — Initial value: R/W: Bit: 0 R 15 — Initial value: R/W: 0 R 30 — 0 R 14 — 0 R 29 — 0 R 13 — 0 R 28 — 0 R 12 — 0 R 27 — 0 R 11 — 0 R 26 — 0 R 10 — 0 R 25 — 0 R 9 EC ERB 24 ECER INTE 23 — 0 R 7 BTO ERB 22 — 0 R 6 TRR EQF1 21 20 19 AC1 CLR 18 17 16 FIFOTRG [1:0] AC0 DREQ1 DREQ0 CLR EN EN 0 R/W 8 ST ERB 0 R/W 5 TRR EQF0 0 R/W 4 0 R/W 3 0 R/W 2 TE INTE 0 R/W 1 0 R/W 0 STER RBER INTE INTE TR TR INTE1 INTE0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 25 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 24 ECERINTE 0 R/W ECC Error Interrupt Enable 0: Disables an interrupt when an ECC error occurs 1: Enables an interrupt when an ECC error occurs Rev. 1.00 Nov. 22, 2007 Page 1296 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 23, 22 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21, 20 FIFOTRG [1:0] 00 R/W FIFO Trigger Setting Change the condition for the FIFO transfer request. In flash-memory read: 00: Issue an interrupt or a DMA transfer request to the CPU when FLDTFIFO stores 4 bytes of data. 01: Issue an interrupt or a DMA transfer request to the CPU when FLDTFIFO stores 16 bytes of data. 10: Issue an interrupt or a DMA transfer request to the CPU when FLDTFIFO stores 128 bytes of data. 11: Issue an interrupt to the CPU when FLDTFIFO stores 128 bytes of data, or issue a DMA transfer request to the CPU when FLDTFIFO stores 16 bytes of data. In flash-memory programming: 00: Issue an interrupt to the CPU when FLDTFIFO has empty area of 4 bytes or more (do not set DMA transfer). 01: Issue an interrupt or a DMA transfer request to the CPU when FLDTFIFO has empty area of 16 bytes or more. 10: Issue an interrupt to the CPU when FLDTFIFO has empty area of 128 bytes or more (do not set DMA transfer). 11: Issue an interrupt to the CPU when FLDTFIFO has empty area of 128 bytes or more, or issue a DMA transfer request to the CPU when FLDTFIFO has empty area of 16 bytes or more. 19 AC1CLR 0 R/W FLECFIFO Clear Clears FLECFIFO. 0: Retains the FLECFIFO value. In flash-memory access, this bit should be cleared to 0. 1: Clears FLECFIFO. After FLECFIFO has been cleared, this bit should be cleared to 0. Rev. 1.00 Nov. 22, 2007 Page 1297 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 18 Bit Name AC0CLR Initial Value 0 R/W R/W Description FLDTFIFO Clear Clears FLDTFIFO. 0: Retains the FLDTFIFO value. In flash-memory access, this bit should be cleared to 0. 1: Clears FLDTFIFO. After FLDTFIFO has been cleared, this bit should be cleared to 0. 17 DREQ1EN 0 R/W FLECFIFODMA Request Enable Enables or disables the DMA transfer request issued from FLECFIFO. 0: Disables the DMA transfer request issued from FLECFIFO 1: Enables the DMA transfer request issued from FLECFIFO 16 DREQ0EN 0 R/W FLDTFIFODMA Request Enable Enables or disables the DMA transfer request issued from FLDTFIFO. 0: Disables the DMA transfer request issued from the FLDTFIFO 1: Enables the DMA transfer request issued from the FLDTFIFO 15 to 10 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 ECERB 0 R/W ECC Error Indicates the result of ECC error detection. This bit is set to 1 if an ECC error occurs while flash memory is read in sector access mode. No interrupt occurs even if this bit is set to 1. This bit is a flag. 1 cannot be written to this bit. Only 0 can be written to clear the flag. 0: Indicates that no ECC error occurs (Latched ECC is all 0.) 1: Indicates that an ECC error occurs Rev. 1.00 Nov. 22, 2007 Page 1298 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 8 Bit Name STERB Initial Value 0 R/W R/W Description Status Error Indicates the result of status read. This bit is set to 1 if the specific bit in the bits STAT[7:0] in FLBSYCNT is set to 1 in status read. This bit is a flag. 1 cannot be written to this bit. Only 0 can be written to clear the flag. 0: Indicates that no status error occurs (the specific bit in the bits STAT[7:0] in FLBSYCNT is 0.) 1: Indicates that a status error occurs For details on the specific bit in STAT[7:0] bits, see section 25.4.6, Status Read. 7 BTOERB 0 R/W Timeout Error This bit is set to 1 if a timeout error occurs (the bits RBTIMCNT[19:0] in FLBSYCNT are decremented to 0). This bit is a flag. 1 cannot be written to this bit. Only 0 can be written to clear the flag. 0: Indicates that no timeout error occurs 1: Indicates that a timeout error occurs 6 TRREQF1 0 R/W FLECFIFO Transfer Request Flag Indicates that a transfer request is issued from FLECFIFO. This bit is a flag. 1 cannot be written to this bit. Only 0 can be written to clear the flag. 0: Indicates that no transfer request is issued from FLECFIFO 1: Indicates that a transfer request is issued from FLECFIFO 5 TRREQF0 0 R/W FLDTFIFO Transfer Request Flag Indicates that a transfer request is issued from FLDTFIFO. This bit is a flag. 1 cannot be written to this bit. Only 0 can be written to clear the flag. 0: Indicates that no transfer request is issued from FLDTFIFO 1: Indicates that a transfer request is issued from FLDTFIFO Rev. 1.00 Nov. 22, 2007 Page 1299 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 4 Bit Name Initial Value R/W R/W Description Interrupt Enable at Status Error Enables or disables an interrupt request to the CPU when a status error has occurred. 0: Disables the interrupt request to the CPU by a status error 1: Enables the interrupt request to the CPU by a status error STERINTE 0 3 RBERINTE 0 RW Interrupt Enable at Timeout Error Enables or disables an interrupt request to the CPU when a timeout error has occurred. 0: Disables the interrupt request to the CPU by a timeout error 1: Enables the interrupt request to the CPU by a timeout error 2 TEINTE 0 R/W Transfer End Interrupt Enable Enables or disables an interrupt request to the CPU when a transfer has been ended (TREND bit in FLTRCR). 0: Disables the transfer end interrupt request to the CPU 1: Enables the transfer end interrupt request to the CPU 1 TRINTE1 0 R/W FLECFIFO Transfer Request Enable to CPU Enables or disables an interrupt request to the CPU by a transfer request issued from FLECFIFO. 0: Disables an interrupt request to the CPU by a transfer request from FLECFIFO. 1: Enables an interrupt request to the CPU by a transfer request from FLECFIFO. When the DMA transfer is enabled, this bit should be cleared to 0. Rev. 1.00 Nov. 22, 2007 Page 1300 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 0 Bit Name TRINTE0 Initial Value 0 R/W R/W Description FLDTFIFO Transfer Request Enable to CPU Enables or disables an interrupt request to the CPU by a transfer request issued from FLDTFIFO. 0: Disables an interrupt request to the CPU by a transfer request from FLDTFIFO 1: Enables an interrupt request to the CPU by a transfer request from FLDTFIFO When the DMA transfer is enabled, this bit should be cleared to 0. 25.3.9 Ready Busy Timeout Setting Register (FLBSYTMR) FLBSYTMR is a 32-bit readable/writable register that specifies the timeout time when the FR/B pin is busy. Bit: 31 — Initial value: R/W: Bit: 0 R 15 30 — 0 R 14 29 — 0 R 13 28 — 0 R 12 27 — 0 R 11 26 — 0 R 10 25 — 0 R 9 24 — 0 R 8 23 — 0 R 7 22 — 0 R 6 21 — 0 R 5 20 — 0 R 4 19 18 17 16 RBTMOUT[19:16] 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 RBTMOUT[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 20 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 19 to 0 RBTMOUT[19:0] H'00000 R/W Ready Busy Timeout Specify timeout time (the number of Pck clocks) in busy state. When these bits are set to 0, timeout is not generated. Rev. 1.00 Nov. 22, 2007 Page 1301 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) 25.3.10 Ready Busy Timeout Counter (FLBSYCNT) FLBSYCNT is a 32-bit read-only register. The status of flash memory obtained by the status read is stored in the bits STAT[7:0]. The timeout time set in the bits RBTMOUT[19:0] in FLBSYTMR is copied to the bits RBTIMCNT[19:0] and counting down is started when the FR/B pin is placed in a busy state. When values in the RBTIMCNT[19:0] become 0, 1 is set to the BTOERB bit in FLINTDMACR, thus notifying that a timeout error has occurred. In this case, an FLSTE interrupt request can be issued if an interrupt is enabled by the RBERINTE bit in FLINTDMACR. Bit: 31 30 29 28 27 26 25 24 23 — 0 R 10 0 R 9 0 R 8 0 R 7 22 — 0 R 6 21 — 0 R 5 20 — 0 R 4 0 R 3 19 18 17 16 STAT[7:0] Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 RBTIMCNT[19:16] 0 R 2 0 R 1 0 R 0 RBTIMCNT[15:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 24 23 to 20 19 to 0 Bit Name STAT[7:0] — Initial Value H'00 All 0 R/W R R Description Indicate the flash memory status obtained by the status read. Reserved These bits are always read as 0. Ready Busy Timeout Counter When the FR/B pin is placed in a busy state, the values of the bits RBTMOUT[19:0] in FLBSYTMR are copied to these bits. These bits are counted down while the FR/B pin is busy. A timeout error occurs when these bits are decremented to 0. RBTIMCNT[19:0] H'00000 R Rev. 1.00 Nov. 22, 2007 Page 1302 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) 25.3.11 Data FIFO Register (FLDTFIFO) FLDTFIFO is used to read or write the data FIFO area. In DMA transfer, data in this register must be specified as the destination (source). Note that the direction of read or write specified by the SELRW bit in FLCMDCR must match that specified in this register. When transferring 16-byte DMA, access FLDTFIFO from the address on the 16-byte address boundary. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DTFO[31:24] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 DTFO[23:16] 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 DTFO[15:8] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W DTFO[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 24 Bit Name DTFO [31:24] Initial Value H'00 R/W R/W Description First Data Specify 1st data to be input or output via the FD7 to FD0 pins. In write: Specify write data In read: Store read data 23 to 16 DTFO [23:16] H'00 R/W Second Data Specify 2nd data to be input or output via the FD7 to FD0 pins. In write: Specify write data In read: Store read data 15 to 8 DTFO[15:8] H'00 R/W Third Data Specify 3rd data to be input or output via the FD7 to FD0 pins. In write: Specify write data In read: Store read data Rev. 1.00 Nov. 22, 2007 Page 1303 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 7 to 0 Bit Name DTFO[7:0] Initial Value H'00 R/W R/W Description Fourth Data Specify 4th data to be input or output via the FD7 to FD0 pins. In write: Specify write data In read: Store read data 25.3.12 Control Code FIFO Register (FLECFIFO) FLECFIFO is used to read or write the control code FIFO area. In DMA transfer, data in this register must be specified as the destination (source). Note that the direction of read or write specified by the SELRW bit in FLCMDCR must match that specified in this register. When transferring 16-byte DMA, access FLECFIFO from the address on the 16-byte address boundary. Before accessing the FLECFIFO, clear the FIFO data by setting the AC1CLR bit in the FINTDMACR to 1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ECFO[31:24] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 ECFO[23:16] 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 ECFO[15:8] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W ECFO[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 24 Bit Name ECFO [31:24] Initial Value H'00 R/W R/W Description First Data Specify 1st data to be input or output via the FD7 to FD0 pins. In write: Specify write data In read: Store read data Rev. 1.00 Nov. 22, 2007 Page 1304 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 23 to 16 Bit Name ECFO [23:16] Initial Value H'00 R/W R/W Description Second Data Specify 2nd data to be input or output via the FD7 to FD0 pins. In write: Specify write data In read: Store read data 15 to 8 ECFO[15:8] H'00 R/W Third Data Specify 3rd data to be input or output via the FD7 to FD0 pins. In write: Specify write data In read: Store read data 7 to 0 ECFO[7:0] H'00 R/W Fourth Data Specify 4th data to be input or output via the FD7 to FD0 pins. In write: Specify write data In read: Store read data 25.3.13 Transfer Control Register (FLTRCR) Setting the TRSTRT bit to 1 initiates access to flash memory. Access completion can be checked by the TREND bit. During the transfer (from when the TRSTRT bit is set to 1 until the TREND bit is set to 1), the processing should not be forcibly ended (by setting the TRSTRT bit to 0). Bit: 7 — Initial value: R/W: 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 0 TR TR END STRT 0 0 R/W R/W Bit 7 to 2 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1305 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Bit 1 Bit Name TREND Initial Value 0 R/W R/W Description Processing End Flag Bit Indicates that the processing performed in the specified access mode has been completed. The write value should always be 0. 0 TRSTRT 0 R/W Transfer Start By setting this bit from 0 to 1 when the TREND bit is 0, processing in the access mode specified by the access mode specification bits ACM[1:0] is initiated. 0: Stops transfer 1: Starts transfer 25.4 25.4.1 Operation Operating Modes Two operating modes are supported. • Command access mode • Sector access mode The ECC generation and error check are performed in sector access mode. 25.4.2 Register Setting Procedure Figure 25.2 shows the register setting flow required for accessing to the flash memory. Rev. 1.00 Nov. 22, 2007 Page 1306 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Start No FLTRCR = All 0? Yes Set FLCMNCR Set FLCMDCR Set FLCMCDR Set FLADR Set FLDTCNTR Set FLDATAR Set FLCMNCR Set FLINTDMACR Set FLBSYTMR Not required in reading Not required in reading Set FLDTFIFO Set FLECFIFO No Start the setting procedure after the current transfer has been completed Not required in sector access Not required in reading. Not required when FLDTFIFO is used. Except FLTRCR, register settings completed? Yes Start the transfer Set FLTRCR to H'01 No Wait until the transfter is completed TREND in FLTRCR = 1? Yes Set FLTRCR to H'00 End Figure 25.2 Register Setting Flow Rev. 1.00 Nov. 22, 2007 Page 1307 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) 25.4.3 Command Access Mode Command access mode accesses flash memory by specifying a command to be issued to flash memory, address, data, read or write direction, and number of times to the registers. In this mode, I/O data can be transferred by the DMA via FLDTFIFO. NAND-Type Flash Memory Access: Figure 25.3 shows an example of read operation for NAND-type flash memory. In this example, the first command is specified as H'00, address data length is specified as 3 bytes, and the number of read bytes is specified as 8 bytes in the data counter. CLE ALE WE RE I/O7 to I/O0 R/B H'00 A1 A2 A3 1 2 3 4 5 8 Figure 25.3 Read Operation Timing for NAND-Type Flash Memory (1) Figures 25.4 and 25.5 show examples of programming operation for NAND-type flash memory. Rev. 1.00 Nov. 22, 2007 Page 1308 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) CLE ALE WE RE I/O7 to I/O0 R/B H'80 A1 A2 A3 1 2 3 4 5 8 Figure 25.4 Programming Operation Timing for NAND-Type Flash Memory (1) CLE ALE WE RE I/O7 to I/O0 R/B H'10 H'70 Status Figure 25.5 Programming Operation Timing for NAND-Type Flash Memory (2) NAND-Type Flash Memory (2048 + 64 Bytes) Access: Figure 25.6 shows an example of read operation for NAND-type flash memory (2048 + 64 bytes). In this example, the first command is specified as H'00, the second command is specified as H'30, and address data length is specified as 4 bytes. The number of read bytes is specified as 4 bytes in the data counter. Rev. 1.00 Nov. 22, 2007 Page 1309 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) CLE ALE WE RE H'00 H'30 A1 A2 A3 A4 1 2 3 4 I/O7 to I/O0 R/B Figure 25.6 Read Operation Timing for NAND-Type Flash Memory Figures 26.7 and 26.8 show examples of programming operation for NAND-type flash memory (2048 + 64 bytes). CLE ALE WE RE H'80 H'10 A1 A2 A3 A4 1 2 3 4 I/O7 to I/O0 R/B Figure 25.7 Programming Operation Timing for NAND-Type Flash Memory (1) Rev. 1.00 Nov. 22, 2007 Page 1310 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) CLE ALE WE RE H'10 H'70 I/O7 to I/O0 Status R/B Figure 25.8 Programming Operation Timing for NAND-Type Flash Memory (2) 25.4.4 Sector Access Mode In sector access mode, flash memory can be read or programmed in sector units by specifying the number of physical sectors to be accessed. In programming, an ECC is added. In read, an ECC error check (detection) is performed. Since 512-byte data is stored in FLDTFIFO and 16-byte control code is stored in FLECFIFO, the DREQ1EN and DREQ0EN bits in FLINTDMACR can be set to transfer by the DMA. Figure 25.9 shows the relationship of DMA transfer between sectors in flash memory (data and control code) and memory on the address space. Rev. 1.00 Nov. 22, 2007 Page 1311 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Flash memory Data (512 bytes) Control code (16 bytes) Address area (external memory area) Data area FLCTL FLDT FIFO DMA transfer FLEC FIFO Control code area DMA transfer Figure 25.9 Relationship between DMA Transfer and Sector (Data and Control Code), and Memory and DMA Transfer Physical Sector: Figure 25.10 shows the relationship between the physical sector address of NAND-type flash memory and the address of flash memory. Rev. 1.00 Nov. 22, 2007 Page 1312 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) NAND-type flash memory (512 + 16 bytes) Bit 17 Physical sector address Bit 0 Note: FLADR2 is not used. Bit 17 Physical sector address bit (FLADR[17:0]) Bit 0 Row3 Row2 Row2 Row1 Row1 Col 00000000 [Legend] CA: Column address Row: Row address (page address) Note: FLADR[1:0] specify the boundary address for column address in the unit of 512 + 16 bytes. When NAND-type flash memory (2048 + 64 bytes) is used, set FLADR[1:0] as follows. 00: 0 byte 01: 512 + 16 bytes 10: 1024 + 32 bytes 11: 1536 + 48 bytes Col1 00 Row3 000000 Order of address output to NAND-type flash memory I/O Col Row1 Row2 Row3 NAND-type flash memory (2048 + 64 bytes) Bit 25 Physical sector address Bit 0 Bit 25 Physical sector address bit (FLADR[25:0]) Bit 0 Row3 When ADRCNT2 = 0 Row2 Row2 Row1 Row1 Col Col2 00000 0 0000 Order of address output to NAND-type flash memory I/O Col1 Col2 Row1 Row2 [Legend] CA: Column address Row: Row address (page address) When ADRCNT2 = 1 (Bits[25:18] are valid.) Row3 Note: When FADRCNT2 = 1, FLADR[25:18] are valid. Set the invalid bit to 0 depending on the capacity of flash memory. Order of address output to NAND-type flash memory I/O Col1 Col2 Row1 Row1 Row3 Figure 25.10 Relationship between Sector Number and Address Expansion of NAND-Type Flash Memory Rev. 1.00 Nov. 22, 2007 Page 1313 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) Continuous Sector Access: Continuous physical sectors can be read or written by specifying the start physical sector of NAND-type flash memory and the number of sectors to be transferred. Figure 25.11 shows an example of physical sector specification register and transfer count specification register settings when transferring logical sectors 0 to 40, which are not contiguous because of an unusable sector in NAND-type flash memory. Physical sector 0 Logical sector 0 11 12 13 11 13 40 40 Values specified in registers by the CPU Physical sector Sector transfer count specification register specification register (FLADR, ADR17 to 0) (FLCMDCR, SCTCNT) Transfer start 00 12 Sector 0 to sector 11 are transferred Transfer start Sector 12 is transferred Transfer start Sector 13 to sector 40 are transferred 300 300 12 1 13 28 Figure 25.11 Sector Access when Unusable Sector Exists in Continuous Sectors Rev. 1.00 Nov. 22, 2007 Page 1314 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) 25.4.5 ECC Error Correction The FLCTL generates and adds an ECC code during write operation in sector access mode and performs ECC error check during read operation in sector access mode. The FLCTL, however, does not perform error correction. Note that errors must be corrected by software. 25.4.6 Status Read The FLCTL can read the status register of a NAND-type flash memory. The data in the status register of a NAND-type flash memory is input through the I/O7 to I/O0 pins and stored in the bits STAT[7:0] in FLBSYCNT. The bits STAT[7:0] in FLBSYCNT can be read by the CPU. If a program error or erase error is detected when the status register value is stored in the bits STAT[7:0] in FLBSYCNT, the STERB bit in FLINTDMACR is set to 1 and generates an interrupt to the CPU if the STERINTE bit in FLINTDMACR is enabled. The status register of NAND-type flash memory can be read by inputting command H'70 to NAND-type flash memory. If programming is executed in command access mode or sector access mode while the DOSR bit in FLCMDCR is set to 1, the FLCTL automatically inputs command H'70 to NAND-type flash memory and reads the status register of NAND-type flash memory. When the status register of NAND-type flash memory is read, the I/O7 to I/O0 pins indicate the following information as described in table 25.4. Table 25.4 Status Read of NAND-Type Flash Memory I/O I/O7 I/O6 I/O5 to I/O1 I/O0 Status (definition) Program protection Ready/busy Reserved Program/erase Description 0: Cannot be programmed 1: Can be programmed 0: Busy state 1: Ready state  0: Pass 1: Fail Rev. 1.00 Nov. 22, 2007 Page 1315 of 1692 REJ09B0360-0100 Section 25 NAND Flash Memory Controller (FLCTL) 25.5 Interrupt Sources The FLCTL has six interrupt sources: Status error, ready/busy timeout error, ECC error, transfer end, FIFO0 transfer request, and FIFO1 transfer request. Each of the interrupt sources has its corresponding interrupt flag and the interrupt can be requested independently to the CPU if the interrupt is enabled by the interrupt enable bit. Note that the status error, ready/busy timeout error, and ECC error use the common FLSTE interrupt to the CPU. Table 25.5 FLCTL Interrupt Requests Interrupt Source FLSTE interrupt Interrupt Flag STERB BTOERB ECERB FLTEND interrupt FLTRQ0 interrupt FLTRQ1 interrupt TREND TRREQF0 TRREQF1 Enable Bit STERINTE RBERINTE ECERINTE TEINTE TRINTE0 TRINTE1 Description Status error Ready/busy timeout error ECC error Transfer end FIFO0 transfer request FIFO1 transfer request Lowest Priority Highest Note: Flags for the FIFO0 overrun error/underrun error and FIFO1 overrun error/underrun error also exist. However, no interrupt is requested to the CPU. 25.6 DMA Transfer Specifications The FLCTL can request DMA transfers separately to the data area FLDTFIFO and control code area FLECFIFO. Table 25.6 summarizes DMA transfer enable or disable states in each access mode. Table 25.6 DMA Transfer Specifications Sector Access Mode FLDTFIFO FLECFIFO DMA transfer enabled DMA transfer enabled Command Access Mode DMA transfer enabled DMA transfer disabled For the setting of DMAC, see section 12, Direct Memory Access Controller (DMAC). Rev. 1.00 Nov. 22, 2007 Page 1316 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) Section 26 Sampling Rate Converter (SRC) The sampling rate converter (SRC) converts the sampling rate for data produced by decoders such as WMA, MP3, or AAC. 26.1 Features • Data size: 16 bits (stereo/monaural) • Sampling rates Input: Either 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, or 48 kHz is selectable. Output: Either 32 kHz, 44.1 kHz or 48 kHz is selectable. • Processing capacity: A maximum of 10 µs sample output interval (Pch = 54 MHz) • SNR: 93 db or higher • Three interrupt sources: Input data FIFO empty, output data FIFO full, and output data FIFO overwrite • Two DMA transfer sources: Input data FIFO empty and output data FIFO full • Module standby mode Power consumption can be reduced by stopping clock supply to the SRC when not used. Rev. 1.00 Nov. 22, 2007 Page 1317 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) Figure 26.1 shows a block diagram of the SRC. Peripheral bus SRCID SRCOD SRCIDCTRL SRCODCTRL Input data FIFO (32 bits × 16 stages) Input buffer memory (16 bits × 64 words × 2) ch0 Intermediate buffer memory (16 bits × 64 words × 2) ch0 Output data FIFO (32 bits × 8 stages) SRCCTRL SRCSTAT Input/output controller ch1 ch1 Coefficient ROM Registers Interrupt/DMA transfer requests [Legend] SRCID: SRC input data register SRCOD: SRC output data register SRCIDCTRL: SRC input data control register SRCODCTRL: SRC output data control register SRCCTRL: SRC control register SRCSTAT: SRC status register Figure 26.1 Block Diagram of SRC Rev. 1.00 Nov. 22, 2007 Page 1318 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) 26.2 Register Descriptions The SRC has the following registers: Table 26.1 Register Configuration Register Name SRC input data register SRC output data register SRC input data control register SRC output data control register SRC control register SRC status register Note: * Abbreviation SRCID SRCOD SRCIDCTRL SRCODCTRL SRCCTRL SRCSTAT R/W R/W R R/W R/W R/W Area 7 P4 Address Address Access Size H'FFF2 0000 H'1FF2 0000 16, 32 H'FFF2 0004 H'1FF2 0004 16, 32 H'FFF2 0008 H'1FF2 0008 16 H'FFF2 000A H'1FF2 000A 16 H'FFF2 000C H'1FF2 000C 16 R/(W)* H'FFF2 000E H'1FF2 000E 16 Bits 15 to 3 are read-only. Only 0 can be written to bits 2 to 0 after having read as 1. Table 26.2 State of Registers in Each Operating Mode Register Name SRC input data register SRC output data register SRC input data control register SRC output data control register SRC control register SRC status register Abbreviation SRCID SRCOD SRCIDCTRL SRCODCTRL SRCCTRL SRCSTAT Power-on Reset Sleep Module Standby Retained Retained Retained Retained Retained Retained H'0000 0000 Retained H'0000 0000 Retained H'0000 H'0000 H'0000 H'0002 Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1319 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) 26.2.1 SRC Input Data Register (SRCID) SRCID is a 32-bit readable/writable register that is used to input the data before sampling rate conversion. All the bits are read as 0. The data input to SRCID is stored in the 16-stage input data FIFO. When the number of data in input data FIFO is 16, writing to SRCID is invalid. For stereo data, bits 31 to 16 are for ch 0 data, and bits 15 to 0 are for ch 1 data. For monaural data, data in bits 31 to 16 is valid, and data in bits 15 to 0 is invalid. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The data subject to sampling rate conversion is aligned differently depending on the IED bit setting in SRCIDCTRL. Table 26.3 shows the relationship between the IED bit setting and data alignment. Table 26.3 Alignment of Data before Sampling Rate Conversion IED 0 1 ch0[15:8] SRCID[31:24] SRCID[23:16] ch0[7:0] SRCID[23:16] SRCID[31:24] ch1[15:8] SRCID[15:8] SRCID[7:0] ch1[7:0] SRCID[7:0] SRCID[15:8] Rev. 1.00 Nov. 22, 2007 Page 1320 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) 26.2.2 SRC Output Data Register (SRCOD) SRCOD is a 32-bit read-only register used to output the data after sampling rate conversion. The data in 8-stage output data FIFO is read through SRCOD. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0* 3 R/W: R Bit: 15 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0* 3 R/W: R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R 0* 3 R The data in SRCOD is aligned differently depending on the OCH and OED bit setting in SRCODCTRL. Table 26.4 shows the correspondence between the OCH and OED bit setting and data alignment in SRCOD. Table 26.4 Alignment of Data in SRCOD OCH 0 1 OED 0 1 SRCOD[31:24] ch0[15:8] ch0[7:0] ch1[15:8] ch1[7:0] SRCOD[23:16] ch0[7:0] ch0[15:8] ch1[7:0] ch1[15:8] SRCOD[15:8] ch1[15:8]* ch1[7:0]*2 ch0[15:8] ch0[7:0] 2 SRCOD[7:0] ch1[7:0]*2 ch1[15:8]*2 ch0[7:0] ch0[15:8] 1* 0 1 Notes: 1. When processing monaural data, do not set the bit to 1. 2. When processing monaural data, the data in these bits is invalid. 3. If the CL bit in the SRCCTRL register is read after 1 is written to it, it is read as 0. If the CL bit is read before 1 is written to it, the read value cannot be guaranteed. Rev. 1.00 Nov. 22, 2007 Page 1321 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) 26.2.3 SRC Input Data Control Register (SRCIDCTRL) SRCIDCTRL is a 16-bit readable/writable register that specifies the endian format of input data, enables/disables the interrupt requests, and specifies the triggering number of data units. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 IED 8 IEN 7 - 6 - 5 - 4 - 3 - 2 - 1 0 IFTRG[1:0] Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 15 to 10 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 9 IED 0 R/W Input Data Endian Specifies the endian format of the input data. 0: Big endian 1: Little endian 8 IEN 0 R/W Input Data FIFO Empty Interrupt Enable Enables/disables the input data FIFO empty interrupt request to be issued when the number of data units in the input FIFO becomes equal to or smaller than the triggering number specified by the IFTRG1 and IFTRG0 bits, thus resulting in the IINT bit in the SRC status register (SRCSTAT) being set to 1. 0: Input data FIFO empty interrupt is disabled. 1: Input data FIFO empty interrupt is enabled. 7 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1322 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) Bit 1, 0 Bit Name IFTRG[1:0] Initial Value 00 R/W R/W Description Input FIFO Data Triggering Number Specifies the condition in terms of the number on which the IINT bit in the SRC status register (SRCSTAT) is set to 1. When the number of data units in the input FIFO becomes equal to or smaller than the triggering number listed below, the IINT bit is set to 1. 00: 0 01: 4 10: 8 11: 12 26.2.4 SRC Output Data Control Register (SRCODCTRL) SRCODCTRL is a 16-bit readable/writable register that specifies whether to exchange the channels for the output data, specifies the endian format of output data, enables/disables the interrupt requests, and specifies the triggering number of data units. Bit: 15 - 14 - 13 - 12 - 11 - 10 OCH 9 OED 8 OEN 7 - 6 - 5 - 4 - 3 - 2 - 1 0 OFTRG[1:0] Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 15 to 11 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 OCH 0 R/W Output Data Channel Exchange Specifies whether to exchange the channels for the SRC output data register (SRCOD). When processing monaural data, do not set this bit to 1. 0: Does not exchange the channels (the same order as data input) 1: Exchanges the channels (the opposite order from data input) Rev. 1.00 Nov. 22, 2007 Page 1323 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) Bit 9 Bit Name OED Initial Value 0 R/W R/W Description Output Data Endian Specifies the endian format of the output data. 0: Big endian 1: Little endian 8 OEN 0 R/W Output Data FIFO Full Interrupt Enable Enables/disables the output data FIFO full interrupt request to be issued when the number of data units in the output FIFO becomes equal to or greater than the number specified by the OFTRG1 and OFTRG0 bits, thus resulting in the OINT bit in SRC status register (SRCSTAT) being set to 1. 0: Output data FIFO full interrupt is disabled. 1: Output data FIFO full interrupt is enabled. 7 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 OFTRG[1:0] 00 R/W Output FIFO Data Trigger Number Specifies the condition in terms of the number on which the OINT bit in the SRC status register (SRCSTAT) is set to 1. When the number of data units in the output FIFO becomes equal to or greater than the number listed below, the OINT bit is set to 1. 00: 1 01: 2 10: 4 11: 6 Rev. 1.00 Nov. 22, 2007 Page 1324 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) 26.2.5 SRC Control Register (SRCCTRL) SRCCTRL is a 16-bit readable/writable register that enables/disables the SRC module operation, enables/disables the interrupt requests, and specifies flush processing, clear processing of the internal work memory, and the input and output sampling rates. Bit: 15 - 14 - 13 - 12 SRCEN 11 - 10 EEN 9 FL 8 CL 7 6 5 4 3 - 2 - 1 0 IFS[3:0] OFS [1:0] Initial value: 0 R/W: R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit 15 to 13 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12 SRCEN 0 R/W SRC Module Enable Enables/disables the SRC module operation. 0: Disables the SRC module operation. 1: Enables the SRC module operation. Note: When the SRCEN bit is 1, do not modify the following bits: Register Name SRCIDCTRL SRCODCTRL SRCCTRL Bit 9 9, 10 7 to 4, 0 Bit Name IED OCH, OED IFS[3:0], OFS 11  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1325 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) Bit 10 Bit Name EEN Initial Value 0 R/W R/W Description Output Data FIFO Overwrite Interrupt Enable Enables/disables the output data FIFO overwrite interrupt request to be issued when the data in the output FIFO has been overwritten before being read thus setting the OVF bit in SRC status register (SRCSTAT) to 1. 0: Output data FIFO overwrite interrupt is disabled. 1: Output data FIFO overwrite interrupt is enabled. 9 FL 0 R/W Internal Work Memory Flush Writing 1 to this bit starts converting the sampling rate of all the data in the input FIFO, input buffer memory, and intermediate memory (i.e., flush processing). This bit is always read as 0. When SRCEN = 0, writing 1 to this bit does not trigger flush processing. If this bit is set to 1 while the number of data units in the input buffer memory is less than 64, the flash processing is not performed because valid output data cannot be obtained. 8 CL 0 R/W Internal Work Memory Clear Writing 1 to this bit clears the input FIFO, output FIFO, input buffer memory, intermediate memory, and accumulator. This bit is always read as 0. Before operating the SRC, the SRC should be internally cleared by writing 1 to this bit. To perform the clearing processing correctly, wait 32 cycles of peripheral bus clock after wring 1 to this bit and then perform the next processing. In addition, when this bit is set to 1, IFS[3:0] and OFS should also be set. Rev. 1.00 Nov. 22, 2007 Page 1326 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) Bit 7 to 4 Bit Name IFS[3:0] Initial Value All 0 R/W R/W Description Input Sampling Rate Specifies the input sampling rate. 0000: 8.0 kHz 0001: 11.025 kHz 0010: 12.0 kHz 0011: Setting prohibited 0100: 16.0 kHz 0101: 22.05 kHz 0110: 24.0 kHz 0111: Setting prohibited 1000: 32.0 kHz 1001: 44.1 kHz 1010: 48.0 kHz 1011: Setting prohibited 1100: Setting prohibited 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited 3 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 to 0 OFS[1:0] All 0 R/W Output Sampling Rate Specifies the output sampling rate. 00: 44.1 kHz 01: 48.0 kHz 10: 32.0 kHz 01: Setting prohibited Rev. 1.00 Nov. 22, 2007 Page 1327 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) The number of output data units obtained as conversion result can be calculated by using the following expression (A) or (B). Table 26.5 shows the relationship of setting value and applicable formula between IFS and OFS[1:0]. Number of output data = Number of input data × Output sampling rate Input sampling rate ... (A) Number of output data = Number of input data × Output sampling rate -1 Input sampling rate ... (B) Table 26.5 Relationship between Sampling Rate Setting and Number of Output Data OFS[1:0] Value (Output Sampling 0000 Rate (kHz)) (8.0) IFS [3:0]Setting (Input Sampling Rate [kHz]) 0001 (11.025) A B B 0010 (12.0) A A B 0100 (16.0) B B A 0101 (22.05) A B B 0110 (24.0) A A A 1000 (32.0) B B  1001 (44.1)  B B 1010 (48.0) A  A 00 (44.1) B 01 (48.0) B 10 (32.0) A 26.2.6 SRC Status Register (SRCSTAT) SRCSTAT is a 16-bit readable/writable register that indicates the number of data units in the input and output data FIFOs, whether the various interrupt sources have been generated or not, and the flush processing status. Bit: 15 14 13 12 11 10 9 IFDN[4:0] 8 7 6 - 5 - 4 FLF 3 - 2 OVF 1 IINT 0 OINT OFDN[3:0] Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 0 0 R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written after having read as 1. Bit 15 to 12 Bit Name OFDN[3:0] Initial Value All 0 R/W R Description Output FIFO Data Count Indicates the number of data units in the output FIFO. Rev. 1.00 Nov. 22, 2007 Page 1328 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) Bit 11 to 7 6, 5 Bit Name IFDN[4:0]  Initial Value All 0 All 0 R/W R R Description Input FIFO Data Count Indicates the number of data units in the input FIFO. Reserved These bits are always read as 0. The write value should always be 0. 4 FLF 0 R Flush Processing Status Flag Indicates whether flush processing is in progress or not. [Clearing conditions] • • When flush processing has been completed. When 1 has been written to the CL bit in SRCCTRL. When 1 has been written to the FL bit in SRCCTRL. [Setting condition] • 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 OVF 0 R/(W)* Output Data FIFO Overwrite Interrupt Request Flag Indicates that the sampling rate conversion for the next data has been completed when there are eight units of data in the output FIFO. The sampling rate conversion stops until the output data FIFO becomes not full after the SRC output data register (SRCOD) has been read. [Clearing condition] • • When 0 has been written to the OVF bit after reading OVF = 1. When 1 has been written to the CL bit in SRCCTRL. When the sampling rate conversion for the next data has been completed when there are eight units of data in the output FIFO. [Setting condition] • Rev. 1.00 Nov. 22, 2007 Page 1329 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) Bit 1 Bit Name IINT Initial Value 1 R/W Description R/(W)* Input Data FIFO Empty Interrupt Request Flag Indicates that the number of data units in the input FIFO has become equal to or smaller than the triggering number specified by the IFTRG1 and IFTRG0 bits in the SRC input data control register (SRCIDCTRL). [Clearing conditions] • • When 0 has been written to the IINT bit after reading IINT = 1. When the DMAC has transferred data to the input FIFO resulting in the number of data units in the FIFO exceeding that of the specified triggering number. When the number of data units in the input FIFO has become equal to or smaller than the specified triggering number. When 1 has been written to the CL bit in SRCCTRL. [Setting condition] • • 0 OINT 0 R/(W)* Output Data FIFO Full Interrupt Request Flag Indicates that the number of data units in the output FIFO has become equal to or greater than the triggering number specified by the OFTRG[1:0] bits in the SRC output data control register (SRCODCTRL). [Clearing conditions] • • When 0 has been written to the OINT bit after reading OINT = 1. When the DMAC has transferred data from the output FIFO resulting in the number of data units in the FIFO being less than the specified triggering number. When the number of data units in the output FIFO has become equal to or greater than the specified triggering number. [Setting condition] • Note: * Only 0 can be written after having read as 1. Rev. 1.00 Nov. 22, 2007 Page 1330 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) 26.3 26.3.1 Operation Initial Setting Figure 26.2 shows a sample flowchart for initial setting. Start initial setting Register SRCCTRL EEN Bit Items to be Set Enabling/disabling of the OVF interrupt Input sampling rate Output sampling rate Input data endian Enabling/disabling of the IDE interrupt Input data FIFO triggering number Exchanging of output data channels Output data endian Enabling/disabling of the ODF interrupt IFS[3:0] Set necessary parameters. OFS SRCIDCTRL Set the SRCEN bit in SRCCTRL to 1 IED IEN IFTRG[1:0] Initial setting completed SRCODCTRL OCH OED OEN OFTRG[1:0] Output data FIFO triggering number Figure 26.2 Sample Flowchart for Initial Setting Rev. 1.00 Nov. 22, 2007 Page 1331 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) 26.3.2 Data Input Figure 26.3 is a sample flowchart for data input. Start data input Read the IINT bit in SRCSTAT. IINT = 1? Yes No Write the data to be converted to SRCID and clear the IINT bit to 0. Has all the data been input? Yes No Set the FL bit in SRCCTRL to 1. Data input completed Figure 26.3 Sample Flowchart for Data Input (1) When Interrupts are Issued to CPU 1. Set the IEN bit in SRCIDCTRL to 1. 2. Set the interrupt controller. 3. When the IINT bit in SRCSTAT is set to 1, the IDE interrupt request is issued. In the interrupt processing routine, read the IINT bit and confirm that it is 1, write data to SRCID, and write 0 to the IINT bit. Then return from the interrupt processing routine. 4. Repeat step 3 until all the data has been input, and write 1 to the FL bit in SRCCTRL. Rev. 1.00 Nov. 22, 2007 Page 1332 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) (2) When Interrupts are Used to Activate DMAC 1. Assign IDEI of the SRC to one channel of the DMAC. 2. Set the IEN bit in SRCIDCTRL to 1. 3. When the IINT bit in SRCSTAT is set to 1, the IDE interrupt request is issued thus activating the DMAC. When the DMAC has written data to the SRCID thus resulting in the number of data units in the input data FIFO exceeding that of the triggering number specified by the IFTRG1 and IFTRG 0 bits in SRCIDCTRL, the IINT bit is cleared to 0. 4. Repeat step 3 until all the data has been input, and write 1 to the FL bit in SRCCTRL. 26.3.3 Data Output Figure 26.4 is a sample flowchart for data output. Start data output Read the OINT bit in SRCSTAT. OINT = 1? Yes No Read the data after conversion from SRCOD and clear the OINT bit to 0. No Flush processing started? Yes Read the FLF bit in SRCSTAT. No FLF = 0? Yes Data output completed Figure 26.4 Sample Flowchart for Data Output Rev. 1.00 Nov. 22, 2007 Page 1333 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) (1) When Interrupts are Issued to CPU 1. Set the OEN bit in SRCODCTRL to 1. 2. Set the interrupt controller. 3. When the OINT bit in SRCSTAT is set to 1, the ODF interrupt request is issued. In the interrupt processing routine, read the OINT bit and confirm that it is 1, read data from SRCOD, and write 0 to the OINT bit. Then return from the interrupt processing routine. 4. After flush processing starts, repeat step 3 until the FLF bit in SRCSTAT is read as 0. (2) When Interrupts are Used to Activate DMAC 1. Assign ODFI of the SRC to one channel of the DMAC. 2. Set the OEN bit in SRCODCTRL to 1. 3. When the OINT bit in SRCSTAT is set to 1, the ODF interrupt request is issued thus activating the DMAC. When the DMAC has read data from SRCOD thus resulting in the number of data units in the output data FIFO being less than the triggering number specified by the OFTRG1 and OFTRG0 bits in SRCODCTRL, the OINT bit is cleared to 0. 4. After flush processing starts, repeat step 3 until the FLF bit in SRCSTAT is read as 0. Rev. 1.00 Nov. 22, 2007 Page 1334 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) 26.4 Interrupts The SRC has three interrupt sources: input data FIFO empty (IDEI), output data FIFO full (ODFI), and output data FIFO overwrite (OVF). Table 26.6 summarizes the interrupts. Table 26.6 Interrupt Requests and Generation Conditions Interrupt Request Input data FIFO empty Output data FIFO full Output data FIFO overwrite Abbreviation IDEI ODFI OVF Interrupt Condition IINT = 1, IEN = 1, and SRCEN = 1 OINT = 1, OEN = 1, and SRCEN = 1 OVF = 1, EEN = 1, and SRCEN = 1 DMAC Activation Possible Possible Not possible When the interrupt condition is satisfied, the CPU executes the interrupt exception handling routine. The interrupt source flags should be cleared in the routine. The IDEI and ODFI interrupts can activate the DMAC when the DMAC is set to allow this. When the DMAC has written data to SRCID resulting in the number of data units in the input data FIFO exceeding that of the specified triggering number, the IINT bit is cleared to 0. Similarly, when the DMAC has read data from SRCOD resulting in the number of data units in the output data FIFO being less than the specified triggering number, the OINT bit is cleared to 0. Rev. 1.00 Nov. 22, 2007 Page 1335 of 1692 REJ09B0360-0100 Section 26 Sampling Rate Converter (SRC) 26.5 26.5.1 Usage Note Note on Access Register After the FL bit in SRCCTRL is set to 1, it takes 3 cycles of peripheral bus clock until the FLF bit in SRCSTAT is set to 1. While the CPU executes the next instruction without waiting the register write completion. Accordingly, the FLF set status cannot be read by the instruction immediately. To check the execution status of flash processing, dummy read the SRCCTRL or SRCSTAT after following the SRCCTRL write instruction and wait until the FLF bit is set. 26.5.2 Note on Flash Processing After set 1 to the FL bit in SRCCTRL, the SRC continues exchange processing with setting to 0 after following the destination of the data that has already input. Flash processing allowed to be executed only under the condition that the destination bit of audio data has input completely and no following data exists. In a case that implement the exchange processing after the flash processing, clear the internal work memories with using either way listed as follows. • Set 1 to the CL bit in SRCCTRL. • Set 0 to the SRCEN bit in SRCCTRL and back to 1. Rev. 1.00 Nov. 22, 2007 Page 1336 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Section 27 General Purpose I/O (GPIO) 27.1 Features This LSI has ten general purpose I/O (GPIO) ports (A to J), which provide 77 input/output pins in total. The port pins are multiplexed with on-chip peripheral module pins, and their functions (GPIO or on-chip peripheral module pins) can be selected. The GPIO has the following features. • Each port pin is a multiplexed pin, for which the pin function and pull-up MOS can be controlled individually through the corresponding port control register. • Each port has a data register that stores data for the pins. • GPIO interrupts are supported (for ports A and B). Tables 27.1 and 27.2 list the multiplexed pins controlled through the GPIO registers. Rev. 1.00 Nov. 22, 2007 Page 1337 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Table 27.1 Multiplexed Pins Controlled by Port Control Registers Port Function (Related Module) Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module)  Function 4 (Related Module)  GPIO Interrupt PINT15 input (INTC) PINT14 input (INTC) PINT13 input (INTC) PINT12 input (INTC) PINT11 input (INTC) PINT10 input (INTC) PINT9 input (INTC) PINT8 input (INTC) PINT7 input (INTC) PINT6 input (INTC) PINT5 input (INTC) PINT4 input (INTC) PINT3 input (INTC) PINT2 input (INTC) Port A PA7 input/output STATUS1 output RTS2 (port) input/output (SYSTEM) (SCIF) PA6 input/output STATUS0 output CTS2 (port) input/output (SYSTEM) (SCIF) PA5 input/output FCE output (port) (FLCTL) PA4 input/output FRE output (port) (FLCTL) PA3 input/output FWE output (port) (FLCTL) PA2 input/output TxD2 output (port) (SCIF) PA1 input/output RxD2 input (port) (SCIF) PA0 input/output SCK2 (port) input/output (SCIF)                     B PB7 input/output A25 output (port) (ADDRESS) PB6 input/output A24 output (port) (ADDRESS) PB5 input/output A23 output (port) (ADDRESS) PB4 input/output A22 output (port) (ADDRESS) PB3 input/output A21 output (port) (ADDRESS) PB2 input/output A20 output (port) (ADDRESS) DREQ0 input (DMAC) DACK0 output (DMAC) DTEND0 output (DMAC) CTS1 input/output (SCIF)   RTS0 input/output (SCIF) CTS0 input/output (SCIF) RTS1 input/output (SCIF)          Rev. 1.00 Nov. 22, 2007 Page 1338 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Port B Port Function (Related Module) PB1 input/output (port) PB0 input/output (port) Function 1 Function 2 (Related Module) (Related Module) A19 output (ADDRESS) A18 output (ADDRESS) AUDIO_CLK0 input (SSI) AUDIO_CLK1 input (SSI) AUDIO_CLK2 input (SSI) SSIWS2 input/output (SSI) SSISCK2 input/output (SSI) SSIDATA2 input/output (SSI)         Function 3 (Related Module)          Function 4 (Related GPIO Module) Interrupt          PINT1 input (INTC) PINT0 input (INTC)        C PC7 input/output (port) PC6 input/output (port) PC5 input/output (port) PC4 input/output (port) PC3 input/output (port) PC2 input/output (port) PC1 input/output (port) PC0 input/output (port) ASEBRKAK/ TCLK input (TMU) BRKACK input/output (AUD) FALE output (FLCTL) CRS input (EtherC) TX_ER output (EtherC) TX_CLK input (EtherC) TX_EN output (EtherC) MII_TXD0 output (EtherC) MII_TXD1 output (EtherC)  IDEA1_M output (ATAPI)                D PD7 input/output (port) PD6 input/output (port) PD5 input/output (port) PD4 input/output (port) PD3 input/output (port) PD2 input/output (port) IDEIOWR_M output  (ATAPI) IDED15_M  input/output (ATAPI) IDED0_M  input/output (ATAPI) SSISCK5 input/output (SSI) SSIWS5 input/output (SSI) IDEIORDY_M input (ATAPI) IDEIORD_M  output (ATAPI) Rev. 1.00 Nov. 22, 2007 Page 1339 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Port D Function 3 Port Function Function 1 Function 2 (Related (Related Module) (Related Module) (Related Module) Module) PD1 input/output (port) PD0 input/output (port) MII_TXD2 output (EtherC) MII_TXD3 output (EtherC) COL input (EtherC) RX_ER input (EtherC) RX_CLK input (EtherC) RX_DV input (EtherC) MII_RXD0 input (EtherC) MII_RXD1 input (EtherC) MII_RXD2 input (EtherC) MII_RXD3 input (EtherC) D32 input/output (DATA) D33 input/output (DATA) D34 input/output (DATA) EXOUT output (EtherC) LNKSTA input (EtherC) WOL output (EtherC) AUDIO_CLK5 input (SSI) SSIDATA5 input/output (SSI) IDEA2_M output (ATAPI) IODREQ_M input (ATAPI) Function 4 (Related GPIO Module) Interrupt        IDEINT_M input  (ATAPI) IODACK_M output (ATAPI)         E PE7 input/output (port) PE6 input/output (port) PE5 input/output (port) PE4 input/output (port) PE3 input/output (port) PE2 input/output (port) PE1 input/output (port) PE0 input/output (port) IDED1_M  input/output (ATAPI) IDED14_M  input/output (ATAPI) SSIWS4 input/output IDED2_M (SSI) input/output (ATAPI) SSISCK4 input/output (SSI) SSIDATA4 input/output (SSI) AUDIO_CLK4 input (SSI)    IDECS1_M output (ATAPI) IDECS0_M output (ATAPI) IDEA0_M output (ATAPI) IDED13_M input/output (ATAPI) IDED3_M input/output (ATAPI) IDED12_M input/output (ATAPI)             F PF7 input/output (port) PF6 input/output (port) PF5 input/output (port) PF4 input/output (port) PF3 input/output (port) PF2 input/output (port)             Rev. 1.00 Nov. 22, 2007 Page 1340 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Port F Port Function Function 1 (Related Module) (Related Module) PF1 input/output (port) PF0 input/output (port) MDIO input/output (EtherC) MDC output (EtherC) LCD_DATA15 output (LCDC) LCD_DATA14 output (LCDC) LCD_DATA13 output (LCDC) LCD_DATA12 output (LCDC) LCD_DATA11 output (LCDC) LCD_DATA10 output (LCDC) LCD_DATA9 output (LCDC) LCD_DATA8 output (LCDC) Function 2 (Related Module) IDED11_M input/output (ATAPI) Function 3 (Related Module)  Function 4 (Related GPIO Module) Interrupt                                 IDED4_M input/output  (ATAPI) DR3 output (VDC2) DR2 output (VDC2) DR1 output (VDC2) DR0 output (VDC2) DG5 output (VDC2) DG4 output (VDC2) DG3 output (VDC2) DG2 output (VDC2)               G PG7 input/output (port) PG6 input/output (port) PG5 input/output (port) PG4 input/output (port) PG3 input/output (port) PG2 input/output (port) PG1 input/output (port) PG0 input/output (port) H PH7 input/output (port) PH6 input/output (port) PH5 input/output (port) PH4 input/output (port) PH3 input/output (port) PH2 input/output (port) AUDIO_CLK3 input  (SSI) SSIWS3 input/output (SSI) SSISCK3 input/output (SSI) SSIDATA3 input/output (SSI) LCD_CL2 output (LCDC) LCD_DON output (LCDC)    DE_V output (VDC2) DCLKOUT output (VDC2) Rev. 1.00 Nov. 22, 2007 Page 1341 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Function 3 Port Function Function 1 Function 2 (Related (Related Module) (Related Module) (Related Module) Module) PH1 input/output (port) PH0 input/output (port) I PI4 input/output (port) PI3 input/output (port) PI2 input/output (port) PI1 input/output (port) PI0 input/output (port) J PJ7 input/output (port) PJ6 input/output (port) PJ5 input/output (port) PJ4 input/output (port) PJ3 input/output (port) PJ2 input/output (port) PJ1 input/output (port) PJ0 input/output (port) LCD_VCP_WC output (LCDC) LCD_VEP_WC output (LCDC) LCD_DATA7 output (LCDC) LCD_DATA6 output (LCDC) LCD_DATA5 output (LCDC) LCD_DATA4 output (LCDC) PI0 input/output (port) PJ7 input/output (port) PJ6 input/output (port) PJ5 input/output (port) PJ4 input/output (port) PJ3 input/output (port) PJ2 input/output (port) PJ1 input/output (port) PJ0 input/output (port) DR4 output (VDC2) DR5 output (VDC2) DG1 output (VDC2) DG0 output (VDC2) DB5 output (VDC2) DB4 output (VDC2)   BT_DATA7 output (VDC2) BT_DATA6 output (VDC2) BT_DATA5 output (VDC2) BT_DATA4 output (VDC2) Function 4 (Related Module)        IDED10_M input/output (ATAPI) IDED5_M input/output (ATAPI) IDED9_M input/output (ATAPI) IDED6_M input/output (ATAPI) IDED7_M input/output (ATAPI) IDED8_M input/output (ATAPI) Port H GPIO Interrupt         COM/CDE output  (VDC2)                      IDERST_M  output (ATAPI) DIRECTION_ M output (ATAPI)  Note: In the table, the pin functions in the shaded column can be used immediately after a reset. Rev. 1.00 Nov. 22, 2007 Page 1342 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Table 27.2 Multiplexed Pins Controlled by Pin Select Registers Register PTSEL_K Bit PTSEL_K7 [1:0] PTSEL_K6 [1:0] PTSEL_K5 PTSEL_K4 [1:0] PTSEL_K3 [1:0] PTSEL_K2 [1:0] PTSEL_K1 [1:0] PTSEL_K0 [1:0] PTSEL_P PTSEL_P11 PTSEL_P10 PTSEL_P9 PTSEL_P8 PTSEL_R PTSEL_R15 PTSEL_R14 PTSEL_R13 PTSEL_R12 PTSEL_R11 Function 1 WDTOVF output (SYSTEM) SCK0 input/output (SCIF) SCK1 input/output (SCIF) Function 2 IRQ1 input (INT) AUDSYNC output (AUD) Function 3 AUDCK output (AUD) FCLE output (FLCTL) Function 4 DACK1 output (DMAC)   FR/B input (FLCTL)  LCD_DATA0 output DB0 output (VDC2) BT_DATA0 output  (VDC2) (LCDC) LCD_CL1 output (LCDC) LCD_CLK input (LCDC) LCD_FLM output (LCDC) LCD_M_DISP output (LCDC) RXD0 input (SCIF) HSYNC/SPL* BT_HSYNC output  input/output (VDC2) (VDC2) DCLKIN input (VDC2)   VSYNC/SPS* BT_VSYNC output input/output (VDC2) (VDC2) DE_H/DE_C output BT_DE_C output (VDC2) (VDC2) AUDATA0 output (AUD)                   TXD0 output (SCIF) AUDATA1 output (AUD) RXD1 input (SCIF) AUDATA2 output (AUD) TXD1 output (SCIF) AUDATA3 output (AUD) D63 input/output (DATA) D62 input/output (DATA) D61 input/output (DATA) D60 input/output (DATA) D59 input/output (DATA) IDED1 input/output (ATAPI) IDED0 input/output (ATAPI) IDED3 input/output (ATAPI) IDED2 input/output (ATAPI) IDED5 input/output (ATAPI) Rev. 1.00 Nov. 22, 2007 Page 1343 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Register PTSEL_R Bit PTSEL_R10 PTSEL_R9 PTSEL_R8 PTSEL_R7 PTSEL_R6 PTSEL_R5 PTSEL_R4 PTSEL_R3 PTSEL_R2 PTSEL_R1 PTSEL_R0 Function 1 D58 input/output (DATA) D57 input/output (DATA) D56 input/output (DATA) D55 input/output (DATA) D54 input/output (DATA) D53 input/output (DATA) D52 input/output (DATA) D51 input/output (DATA) D50 input/output (DATA) D49 input/output (DATA) D48 input/output (DATA) IRQ0 input (INT) Function 2 IDED4 input/output (ATAPI) IDED7 input/output (ATAPI) IDED6 input/output (ATAPI) DIRECTION output (ATAPI) IDERST output (ATAPI) IDED8 input/output (ATAPI) IDED9 input/output (ATAPI) IDED10 input/output (ATAPI) IDED11 input/output (ATAPI) IDED12 input/output (ATAPI) IDED13 input/output (ATAPI) DTEND1 output (DMAC) Function 3  Function 4                  PTSEL_S PTSEL_S15 PTSEL_S14 PTSEL_S13 PTSEL_S12 PTSEL_S11 PTSEL_S10 PTSEL_S9 PTSEL_S8          IRQOUT output (INT) DREQ1 input (DMAC)  D47 input/output (DATA) D46 input/output (DATA) D45 input/output (DATA) D44 input/output (DATA) D43 input/output (DATA) D42 input/output (DATA) IDECS0 output (ATAPI) IDECS1 output (ATAPI) IODACK output (ATAPI) IDEINT input (ATAPI) IDEIORDY input (ATAPI) IDEIORD output (ATAPI)       Rev. 1.00 Nov. 22, 2007 Page 1344 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Register PTSEL_S Bit PTSEL_S7 PTSEL_S6 PTSEL_S5 PTSEL_S4 PTSEL_S3 PTSEL_S2 PTSEL_S1 Function 1 D41 input/output (DATA) D40 input/output (DATA) D39 input/output (DATA) D38 input/output (DATA) D37 input/output (DATA) D36 input/output (DATA) D35 input/output (DATA) Function 2 IODREQ input (ATAPI) IDEIOWR output (ATAPI) IDED14 input/output (ATAPI) IDED15 input/output (ATAPI) Function 3     Function 4        IDEA1 output (ATAPI)  IDEA2 output (ATAPI)  IDEA0 output (ATAPI)  Note: In the table, the pin functions in the shaded column can be used immediately after a reset. * This pin function switches over input/output functions in a special select register. Rev. 1.00 Nov. 22, 2007 Page 1345 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2 Register Descriptions Table 27.3 shows the GPIO register configuration. Table 27.4 shows the register states in each operating mode. Table 27.3 Register Configuration Register Name Port A control register Port B control register Port C control register Port D control register Port E control register Port F control register Port G control register Port H control register Port I control register Port J control register Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port G data register Port H data register Port I data register Port J data register Input-pin pull-up control register Pin select register A Pin select register B Pin select register C Abbreviation PTIO_A PTIO_B PTIO_C PTIO_D PTIO_E PTIO_F PTIO_G PTIO_H PTIO_I PTIO_J PTDAT_A PTDAT_B PTDAT_C PTDAT_D PTDAT_E PTDAT_F PTDAT_G PTDAT_H PTDAT_I PTDAT_J PTPUL_SPCL PTSEL_A PTSEL_B PTSEL_C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P4 Area Address*1 H'FFF1 0000 H'FFF1 0004 H'FFF1 0008 H'FFF1 000C H'FFF1 0010 H'FFF1 0014 H'FFF1 0018 H'FFF1 001C H'FFF1 0020 H'FFF1 0024 H'FFF1 0040 H'FFF1 0044 H'FFF1 0048 H'FFF1 004C H'FFF1 0050 H'FFF1 0054 H'FFF1 0058 H'FFF1 005C H'FFF1 0060 H'FFF1 0064 H'FFF1 00E0 H'FFF1 0080 H'FFF1 0084 H'FFF1 0088 Area 7 Address*1 H'1FF1 0000 H'1FF1 0004 H'1FF1 0008 H'1FF1 000C H'1FF1 0010 H'1FF1 0014 H'1FF1 0018 H'1FF1 001C H'1FF1 0020 H'1FF1 0024 H'1FF1 0040 H'1FF1 0044 H'1FF1 0048 H'1FF1 004C H'1FF1 0050 H'1FF1 0054 H'1FF1 0058 H'1FF1 005C H'1FF1 0060 H'1FF1 0064 H'1FF1 00E0 H'1FF1 0080 H'1FF1 0084 H'1FF1 0088 Access Size*2 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Rev. 1.00 Nov. 22, 2007 Page 1346 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Register Name Pin select register D Pin select register E Pin select register F Pin select register G Pin select register H Pin select register I Pin select register J Pin select register K Pin select register P Pin select register R Pin select register S Hi-Z register A Hi-Z register B Special select register Abbreviation PTSEL_D PTSEL_E PTSEL_F PTSEL_G PTSEL_H PTSEL_I PTSEL_J PTSEL_K PTSEL_P PTSEL_R PTSEL_S PTHIZ_A PTHIZ_B PTSEL_SPCL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P4 Area Address*1 H'FFF1 008C H'FFF1 0090 H'FFF1 0094 H'FFF1 0098 H'FFF1 009C H'FFF1 00A0 H'FFF1 00A4 H'FFF1 00A8 Area 7 Address*1 H'1FF1 008C H'1FF1 0090 H'1FF1 0094 H'1FF1 0098 H'1FF1 009C H'1FF1 00A0 H'1FF1 00A4 H'1FF1 00A8 Access Size*2 16 16 16 16 16 16 16 16 H'FFF1 00AC H'1FF1 00AC 16 H'FFF1 00B0 H'FFF1 00B4 H'FFF1 00E8 H'1FF1 00B0 H'1FF1 00B4 H'1FF1 00E8 16 16 16 H’FFF1 00EC H’1FF1 00EC 16 H’FFF1 00F0 H’1FF1 00F0 16 Notes: 1. Use a P4 area address to access a register in the P4 area in the virtual address space. Use an area 7 address to access a register from area 7 in the physical address space through the TLB. 2. The registers should always be read or written to in 16 bits. Rev. 1.00 Nov. 22, 2007 Page 1347 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Table 27.4 Register States in Each Operating Mode Register name Port A control register Port B control register Port C control register Port D control register Port E control register Port F control register Port G control register Port H control register Port I control register Port J control register Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port G data register Port H data register Port I data register Port J data register Input-pin pull-up control register Pin select register A Pin select register B Pin select register C Pin select register D Pin select register E Pin select register F Pin select register G Pin select register H Abbreviation PTIO_A PTIO_B PTIO_C PTIO_D PTIO_E PTIO_F PTIO_G PTIO_H PTIO_I PTIO_J PTDAT_A PTDAT_B PTDAT_C PTDAT_D PTDAT_E PTDAT_F PTDAT_G PTDAT_H PTDAT_I PTDAT_J PTPUL_SPCL PTSEL_A PTSEL_B PTSEL_C PTSEL_D PTSEL_E PTSEL_F PTSEL_G PTSEL_H Power-on Reset H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0002 H'AAAA H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1348 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Register name Pin select register I Pin select register J Pin select register K Pin select register P Pin select register R Pin select register S Hi-Z register A Hi-Z register B Special select register Abbreviation PTSEL_I PTSEL_J PTSEL_K PTSEL_P PTSEL_R PTSEL_S PTHIZ_A PTHIZ_B PTSEL_SPCL Power-on Reset H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained 27.2.1 Port A Control Register (PTIO_A) PTIO_A is a 16-bit readable/writable register that controls each pin function and input pull-up MOS. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTIO_A7[1:0] Initial value: 0 0 R/W PTIO_A6[1:0] 0 R/W 0 R/W PTIO_A5[1:0] 0 R/W 0 R/W PTIO_A4[1:0] 0 R/W 0 R/W PTIO_A3[1:0] 0 R/W 0 R/W PTIO_A2[1:0] 0 R/W 0 R/W PTIO_A1[1:0] 0 R/W 0 R/W PTIO_A0[1:0] 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTIO_A7[1:0] Initial Value R/W 00 R/W Description PTA7 Mode 00: Other functions (STATUS1 and RTS2) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 13, 12 PTIO_A6[1:0] 00 R/W PTA6 Mode 00: Other functions (STATUS0 and CTS2) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1349 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 11, 10 Bit Name PTIO_A5[1:0] Initial Value R/W 00 R/W Description PTA5 Mode 00: Other functions (FCE) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 9, 8 PTIO_A4[1:0] 00 R/W PTA4 Mode 00: Other functions (FRE) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 7, 6 PTIO_A3[1:0] 00 R/W PTA3 Mode 00: Other functions (FWE) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 5, 4 PTIO_A2[1:0] 00 R/W PTA2 Mode 00: Other functions (TxD2) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 3, 2 PTIO_A1[1:0] 00 R/W PTA1 Mode 00: Other functions (RxD2) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 1, 0 PTIO_A0[1:0] 00 R/W PTA0 Mode 00: Other functions (SCK2) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1350 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.2 Port B Control Register (PTIO_B) PTIO_B is a 16-bit readable/writable register that controls each pin function and input pull-up MOS. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTIO_B7[1:0] Initial value: 0 0 R/W PTIO_B6[1:0] 0 R/W 0 R/W PTIO_B5[1:0] 0 R/W 0 R/W PTIO_B4[1:0] 0 R/W 0 R/W PTIO_B3[1:0] 0 R/W 0 R/W PTIO_B2[1:0] 0 R/W 0 R/W PTIO_B1[1:0] 0 R/W 0 R/W PTIO_B0[1:0] 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTIO_B7[1:0] Initial Value R/W 00 R/W Description PTB7 Mode 00: Other functions (A25, DREQ0, and RTS0) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 13, 12 PTIO_B6[1:0] 00 R/W PTB6 Mode 00: Other functions (A24, DACK0, and CTS0) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 11, 10 PTIO_B5[1:0] 00 R/W PTB5 Mode 00: Other functions (A23, DTEND0, and RTS1) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 9, 8 PTIO_B4[1:0] 00 R/W PTB4 Mode 00: Other functions (A22 and CTS1) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1351 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTIO_B3[1:0] Initial Value R/W 00 R/W Description PTB3 Mode 00: Other functions (A21) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 5, 4 PTIO_B2[1:0] 00 R/W PTB2 Mode 00: Other functions (A20) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 3, 2 PTIO_B1[1:0] 00 R/W PTB1 Mode 00: Other functions (A19) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 1, 0 PTIO_B0[1:0] 00 R/W PTB0 Mode 00: Other functions (A18) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1352 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.3 Port C Control Register (PTIO_C) PTIO_C is a 16-bit readable/writable register that controls each pin function and input pull-up MOS. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTIO_C7[1:0] Initial value: 0 0 R/W PTIO_C6[1:0] 0 R/W 0 R/W PTIO_C5[1:0] 0 R/W 0 R/W PTIO_C4[1:0] 0 R/W 0 R/W PTIO_C3[1:0] 0 R/W 0 R/W PTIO_C2[1:0] 0 R/W 0 R/W PTIO_C1[1:0] 0 R/W 0 R/W PTIO_C0[1:0] 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTIO_C7[1:0] Initial Value R/W 00 R/W Description PTC7 Mode 00: Other functions (AUDIO_CLK0) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 13, 12 PTIO_C6[1:0] 00 R/W PTC6 Mode 00: Other functions (AUDIO_CLK1) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 11, 10 PTIO_C5[1:0] 00 R/W PTC5 Mode 00: Other functions (AUDIO_CLK2) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 9, 8 PTIO_C4[1:0] 00 R/W PTC4 Mode 00: Other functions (SSIWS2) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1353 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTIO_C3[1:0] Initial Value R/W 00 R/W Description PTC3 Mode 00: Other functions (SSISCK2) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 5, 4 PTIO_C2[1:0] 00 R/W PTC2 Mode 00: Other functions (SSIDATA2) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 3, 2 PTIO_C1[1:0] 00 R/W PTC1 Mode 00: Other functions (ASEBRKAK/BRKACK and TCLK) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 1, 0 PTIO_C0[1:0] 00 R/W PTC0 Mode 00: Other functions (FALE) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1354 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.4 Port D Control Register (PTIO_D) PTIO_D is a 16-bit readable/writable register that controls each pin function and input pull-up MOS. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTIO_D7[1:0] Initial value: 0 0 R/W PTIO_D6[1:0] 0 R/W 0 R/W PTIO_D5[1:0] 0 R/W 0 R/W PTIO_D4[1:0] 0 R/W 0 R/W PTIO_D3[1:0] 0 R/W 0 R/W PTIO_D2[1:0] 0 R/W 0 R/W PTIO_D1[1:0] 0 R/W 0 R/W PTIO_D0[1:0] 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTIO_D7[1:0] Initial Value R/W 00 R/W Description PTD7 Mode 00: Other functions (CRS and IDEA1_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 13, 12 PTIO_D6[1:0] 00 R/W PTD6 Mode 00: Other functions (TX_ER and IDEIOWR_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 11, 10 PTIO_D5[1:0] 00 R/W PTD5 Mode 00: Other functions (TX_CLK and IDED15_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 9, 8 PTIO_D4[1:0] 00 R/W PTD4 Mode 00: Other functions (TX_EN and IDED0_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1355 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTIO_D3[1:0] Initial Value R/W 00 R/W Description PTD3 Mode 00: Other functions (MII_TXD0, SSISCK5, and IDEIORDY_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 5, 4 PTIO_D2[1:0] 00 R/W PTD2 Mode 00: Other functions (MII_TXD1, SSIWS5, and IDEIORD_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 3, 2 PTIO_D1[1:0] 00 R/W PTD1 Mode 00: Other functions (MII_TXD2, AUDIO_CLK5, and IDEINT_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 1, 0 PTIO_D0[1:0] 00 R/W PTD0 Mode 00: Other functions (MII_TXD3, SSIDATA5, and IODACK_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1356 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.5 Port E Control Register (PTIO_E) PTIO_E is a 16-bit readable/writable register that controls each pin function and input pull-up MOS. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTIO_E7[1:0] Initial value: 0 0 R/W PTIO_E6[1:0] 0 R/W 0 R/W PTIO_E5[1:0] 0 R/W 0 R/W PTIO_E4[1:0] 0 R/W 0 R/W PTIO_E3[1:0] 0 R/W 0 R/W PTIO_E2[1:0] 0 R/W 0 R/W PTIO_E1[1:0] 0 R/W 0 R/W PTIO_E0[1:0] 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTIO_E7[1:0] Initial Value R/W 00 R/W Description PTE7 Mode 00: Other functions (COL and IDEA2_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 13, 12 PTIO_E6[1:0] 00 R/W PTE6 Mode 00: Other functions (RX_ER and IODREQ_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 11, 10 PTIO_E5[1:0] 00 R/W PTE5 Mode 00: Other functions (RX_CLK and IDED1_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 9, 8 PTIO_E4[1:0] 00 R/W PTE4 Mode 00: Other functions (RX_DV and IDED14_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1357 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTIO_E3[1:0] Initial Value R/W 00 R/W Description PTE3 Mode 00: Other functions (MII_RXD0, SSIWS4, and IDED2_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 5, 4 PTIO_E2[1:0] 00 R/W PTE2 Mode 00: Other functions (MII_RXD1, SSISCK4, and IDED13_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 3, 2 PTIO_E1[1:0] 00 R/W PTE1 Mode 00: Other functions (MII_RXD2, SSIDATA4, and IDED3_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 1, 0 PTIO_E0[1:0] 00 R/W PTE0 Mode 00: Other functions (MII_RXD3, AUDIO_CLK4, and IDED12_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1358 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.6 Port F Control Register (PTIO_F) PTIO_F is a 16-bit readable/writable register that controls each pin function and input pull-up MOS. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTIO_F7[1:0] Initial value: 0 0 R/W PTIO_F6[1:0] 0 R/W 0 R/W PTIO_F5[1:0] 0 R/W 0 R/W PTIO_F4[1:0] 0 R/W 0 R/W PTIO_F3[1:0] 0 R/W 0 R/W PTIO_F2[1:0] 0 R/W 0 R/W PTIO_F1[1:0] 0 R/W 0 R/W PTIO_F0[1:0] 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTIO_F7[1:0] Initial Value R/W 00 R/W Description PTF7 Mode 00: Other functions (D32) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 13, 12 PTIO_F6[1:0] 00 R/W PTF6 Mode 00: Other functions (D33) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 11, 10 PTIO_F5[1:0] 00 R/W PTF5 Mode 00: Other functions (D34) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 9, 8 PTIO_F4[1:0] 00 R/W PTF4 Mode 00: Other functions (EXOUT and IDECS1_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1359 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTIO_F3[1:0] Initial Value R/W 00 R/W Description PTF3 Mode 00: Other functions (LNKSTA and IDECS0_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 5, 4 PTIO_F2[1:0] 00 R/W PTF2 Mode 00: Other functions (WOL and IDEA0_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 3, 2 PTIO_F1[1:0] 00 R/W PTF1 Mode 00: Other functions (MDIO and IDED11_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 1, 0 PTIO_F0[1:0] 00 R/W PTF0 Mode 00: Other functions (MDC and IDED4_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1360 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.7 Port G Control Register (PTIO_G) PTIO_G is a 16-bit readable/writable register that controls each pin function and input pull-up MOS. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTIO_G7[1:0] Initial value: 0 0 R/W PTIO_G6[1:0] 0 R/W 0 R/W PTIO_G5[1:0] 0 R/W 0 R/W PTIO_G4[1:0] 0 R/W 0 R/W PTIO_G3[1:0] 0 R/W 0 R/W PTIO_G2[1:0] 0 R/W 0 R/W PTIO_G1[1:0] 0 R/W 0 R/W PTIO_G0[1:0] 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTIO_G7[1:0] Initial Value R/W 00 R/W Description PTG7 Mode 00: Other functions (LCD_DATA15 and DR3) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 13, 12 PTIO_G6[1:0] 00 R/W PTG6 Mode 00: Other functions (LCD_DATA14 and DR2) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 11, 10 PTIO_G5[1:0] 00 R/W PTG5 Mode 00: Other functions (LCD_DATA13 and DR1) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 9, 8 PTIO_G4[1:0] 00 R/W PTG4 Mode 00: Other functions (LCD_DATA12 and DR0) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1361 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTIO_G3[1:0] Initial Value R/W 00 R/W Description PTG3 Mode 00: Other functions (LCD_DATA11 and DG5) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 5, 4 PTIO_G2[1:0] 00 R/W PTG2 Mode 00: Other functions (LCD_DATA10 and DG4) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 3, 2 PTIO_G1[1:0] 00 R/W PTG1 Mode 00: Other functions (LCD_DATA9 and DG3) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 1, 0 PTIO_G0[1:0] 00 R/W PTG0 Mode 00: Other functions (LCD_DATA8 and DG2) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1362 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.8 Port H Control Register (PTIO_H) PTIO_H is a 16-bit readable/writable register that controls each pin function and input pull-up MOS. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTIO_H7[1:0] Initial value: 0 0 R/W PTIO_H6[1:0] 0 R/W 0 R/W PTIO_H5[1:0] 0 R/W 0 R/W PTIO_H4[1:0] 0 R/W 0 R/W PTIO_H3[1:0] 0 R/W 0 R/W PTIO_H2[1:0] 0 R/W 0 R/W PTIO_H1[1:0] 0 R/W 0 R/W PTIO_H0[1:0] 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTIO_H7[1:0] Initial Value R/W 00 R/W Description PTH7 Mode 00: Other functions (AUDIO_CLK3) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 13, 12 PTIO_H6[1:0] 00 R/W PTH6 Mode 00: Other functions (SSIWS3) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 11, 10 PTIO_H5[1:0] 00 R/W PTH5 Mode 00: Other functions (SSISCK3) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 9, 8 PTIO_H4[1:0] 00 R/W PTH4 Mode 00: Other functions (SSIDATA3) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1363 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTIO_H3[1:0] Initial Value R/W 00 R/W Description PTH3 Mode 00: Other functions (LCD_CL2 and DE_V) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 5, 4 PTIO_H2[1:0] 00 R/W PTH2 Mode 00: Other functions (LCD_DON and DCLKOUT) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 3, 2 PTIO_H1[1:0] 00 R/W PTH1 Mode 00: Other functions (LCD_VCP_WC and DR4) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 1, 0 PTIO_H0[1:0] 00 R/W PTH0 Mode 00: Other functions (LCD_VEP_WC and DR5) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1364 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.9 Port I Control Register (PTIO_I) PTIO_I is a 16-bit readable/writable register that controls each pin function and input pull-up MOS. Bit: 15  Initial value: R/W: 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9 8 7 6 5 4 3 2 1 0 PTIO_I4[1:0] 0 R/W 0 R/W PTIO_I3[1:0] 0 R/W 0 R/W PTIO_I2[1:0] 0 R/W 0 R/W PTIO_I1[1:0] 0 R/W 0 R/W PTIO_I0[1:0] 1 R/W 0 R/W Bit 15 to 10 Bit Name  Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PTIO_I4[1:0] 00 R/W PTI4 Mode 00: Other functions (LCD_DATA7, DG1, and BT_DATA7) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 7, 6 PTIO_I3[1:0] 00 R/W PTI3 Mode 00: Other functions (LCD_DATA6, DG0, and BT_DATA6) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 5, 4 PTIO_I2[1:0] 00 R/W PTI2 Mode 00: Other functions (LCD_DATA5, DB5, and BT_DATA5) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1365 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 3, 2 Bit Name PTIO_I1[1:0] Initial Value R/W 00 R/W Description PTI1 Mode 00: Other functions (LCD_DATA4, DB4, and BT_DATA4) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 1, 0 PTIO_I0[1:0] 10 R/W PTI0 Mode 00: Other functions (COM/CDE) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 27.2.10 Port J Control Register (PTIO_J) PTIO_J is a 16-bit readable/writable register that controls each pin function and input pull-up MOS. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTIO_J7[1:0] Initial value: 1 0 R/W PTIO_J6[1:0] 1 R/W 0 R/W PTIO_J5[1:0] 1 R/W 0 R/W PTIO_J4[1:0] 1 R/W 0 R/W PTIO_J3[1:0] 1 R/W 0 R/W PTIO_J2[1:0] 1 R/W 0 R/W PTIO_J1[1:0] 1 R/W 0 R/W PTIO_J0[1:0] 1 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTIO_J7[1:0] Initial Value R/W 10 R/W Description PTJ7 Mode 00: Other functions (IDED10_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 13, 12 PTIO_J6[1:0] 10 R/W PTJ6 Mode 00: Other functions (IDED5_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1366 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 11, 10 Bit Name PTIO_J5[1:0] Initial Value R/W 10 R/W Description PTJ5 Mode 00: Other functions (IDED9_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 9, 8 PTIO_J4[1:0] 10 R/W PTJ4 Mode 00: Other functions (IDED6_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 7, 6 PTIO_J3[1:0] 10 R/W PTJ3 Mode 00: Other functions (IDED7_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 5, 4 PTIO_J2[1:0] 10 R/W PTJ2 Mode 00: Other functions (IDED8_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 3, 2 PTIO_J1[1:0] 10 R/W PTJ1 Mode 00: Other functions (IDERST_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) 1, 0 PTIO_J0[1:0] 10 R/W PTJ0 Mode 00: Other functions (DIRECTION_M) 01: Port output 10: Port input (Pull-up MOS: Off) 11: Port input (Pull-up MOS: On) Rev. 1.00 Nov. 22, 2007 Page 1367 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.11 Port A Data Register (PTDAT_A) PTDAT_A is a 16-bit readable/writable register that stores port A data. Bit: 15  Initial value: R/W: 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7 6 5 4 3 2 1 0 PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ A7 A6 A5 A4 A3 A2 A1 A0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name  Initial Value R/W All 0 R Description Reserved The lower 8-bit value is always read from these bits. The write value should always be 0. 7 6 5 4 3 2 1 0 PTDAT_A7 PTDAT_A6 PTDAT_A5 PTDAT_A4 PTDAT_A3 PTDAT_A2 PTDAT_A1 PTDAT_A0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Each bit stores output data of a pin used as a general output port. When the pin is used as a general output port, if the port is read, the value of the corresponding bit in this register will be read. When the pin is used as a general input port, if this register is read, the status of the corresponding pin will be read. Rev. 1.00 Nov. 22, 2007 Page 1368 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.12 Port B Data Register (PTDAT_B) PTDAT_B is a 16-bit readable/writable register that stores port B data. Bit: 15  Initial value: R/W: 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7 6 5 4 3 2 1 0 PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ B7 B6 B5 B4 B3 B2 B1 B0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name  Initial Value R/W All 0 R Description Reserved The lower 8-bit value is always read from these bits. The write value should always be 0. 7 6 5 4 3 2 1 0 PTDAT_B7 PTDAT_B6 PTDAT_B5 PTDAT_B4 PTDAT_B3 PTDAT_B2 PTDAT_B1 PTDAT_B0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Each bit stores output data of a pin used as a general output port. When the pin is used as a general output port, if the port is read, the value of the corresponding bit in this register will be read. When the pin is used as a general input port, if this register is read, the status of the corresponding pin will be read. When the pin is set to a function other than the general port, if it is used as an input pin, the pin status will be read from the corresponding bit in this register and writing to the bit is ignored; for an output pin, an undefined value will be read from the bit and writing to the bit is ignored. Rev. 1.00 Nov. 22, 2007 Page 1369 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.13 Port C Data Register (PTDAT_C) PTDAT_C is a 16-bit readable/writable register that stores port C data. Bit: 15  Initial value: R/W: 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7 6 5 4 3 2 1 0 PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ C7 C6 C5 C4 C3 C2 C1 C0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name  Initial Value R/W All 0 R Description Reserved The lower 8-bit value is always read from these bits. The write value should always be 0. 7 6 5 4 3 2 1 0 PTDAT_C7 PTDAT_C6 PTDAT_C5 PTDAT_C4 PTDAT_C3 PTDAT_C2 PTDAT_C1 PTDAT_C0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Each bit stores output data of a pin used as a general output port. When the pin is used as a general output port, if the port is read, the value of the corresponding bit in this register will be read. When the pin is used as a general input port, if this register is read, the status of the corresponding pin will be read. When the pin is set to a function other than the general port, if it is used as an input pin, the pin status will be read from the corresponding bit in this register and writing to the bit is ignored; for an output pin, an undefined value will be read from the bit and writing to the bit is ignored. Rev. 1.00 Nov. 22, 2007 Page 1370 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.14 Port D Data Register (PTDAT_D) PTDAT_D is a 16-bit readable/writable register that stores port D data. Bit: 15  Initial value: R/W: 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7 6 5 4 3 2 1 0 PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ D7 D6 D5 D4 D3 D2 D1 D0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name  Initial Value R/W All 0 R Description Reserved The lower 8-bit value is always read from these bits. The write value should always be 0. 7 6 5 4 3 2 1 0 PTDAT_D7 PTDAT_D6 PTDAT_D5 PTDAT_D4 PTDAT_D3 PTDAT_D2 PTDAT_D1 PTDAT_D0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Each bit stores output data of a pin used as a general output port. When the pin is used as a general output port, if the port is read, the value of the corresponding bit in this register will be read. When the pin is used as a general input port, if this register is read, the status of the corresponding pin will be read. When the pin is set to a function other than the general port, if it is used as an input pin, the pin status will be read from the corresponding bit in this register and writing to the bit is ignored; for an output pin, an undefined value will be read from the bit and writing to the bit is ignored. Rev. 1.00 Nov. 22, 2007 Page 1371 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.15 Port E Data Register (PTDAT_E) PTDAT_E is a 16-bit readable/writable register that stores port E data. Bit: 15  Initial value: R/W: 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7 6 5 4 3 2 1 0 PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ E7 E6 E5 E4 E3 E2 E1 E0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name  Initial Value R/W All 0 R Description Reserved The lower 8-bit value is always read from these bits. The write value should always be 0. 7 6 5 4 3 2 1 0 PTDAT_E7 PTDAT_E6 PTDAT_E5 PTDAT_E4 PTDAT_E3 PTDAT_E2 PTDAT_E1 PTDAT_E0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Each bit stores output data of a pin used as a general output port. When the pin is used as a general output port, if the port is read, the value of the corresponding bit in this register will be read. When the pin is used as a general input port, if this register is read, the status of the corresponding pin will be read. When the pin is set to a function other than the general port, if it is used as an input pin, the pin status will be read from the corresponding bit in this register and writing to the bit is ignored; for an output pin, an undefined value will be read from the bit and writing to the bit is ignored. Rev. 1.00 Nov. 22, 2007 Page 1372 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.16 Port F Data Register (PTDAT_F) PTDAT_F is a 16-bit readable/writable register that stores port F data. Bit: 15  Initial value: R/W: 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7 6 5 4 3 2 1 0 PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ F7 F6 F5 F4 F3 F2 F1 F0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name  Initial Value R/W All 0 R Description Reserved The lower 8-bit value is always read from these bits. The write value should always be 0. 7 6 5 4 3 2 1 0 PTDAT_F7 PTDAT_F6 PTDAT_F5 PTDAT_F4 PTDAT_F3 PTDAT_F2 PTDAT_F1 PTDAT_F0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Each bit stores output data of a pin used as a general output port. When the pin is used as a general output port, if the port is read, the value of the corresponding bit in this register will be read. When the pin is used as a general input port, if this register is read, the status of the corresponding pin will be read. When the pin is set to a function other than the general port, if it is used as an input pin, the pin status will be read from the corresponding bit in this register and writing to the bit is ignored; for an output pin, an undefined value will be read from the bit and writing to the bit is ignored. Rev. 1.00 Nov. 22, 2007 Page 1373 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.17 Port G Data Register (PTDAT_G) PTDAT_G is a 16-bit readable/writable register that stores port G data. Bit: 15  Initial value: R/W: 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7 6 5 4 3 2 1 0 PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ G7 G6 G5 G4 G3 G2 G1 G0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name  Initial Value R/W All 0 R Description Reserved The lower 8-bit value is always read from these bits. The write value should always be 0. 7 6 5 4 3 2 1 0 PTDAT_G7 PTDAT_G6 PTDAT_G5 PTDAT_G4 PTDAT_G3 PTDAT_G2 PTDAT_G1 PTDAT_G0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Each bit stores output data of a pin used as a general output port. When the pin is used as a general output port, if the port is read, the value of the corresponding bit in this register will be read. When the pin is used as a general input port, if this register is read, the status of the corresponding pin will be read. When the pin is set to a function other than the general port, if it is used as an input pin, the pin status will be read from the corresponding bit in this register and writing to the bit is ignored; for an output pin, an undefined value will be read from the bit and writing to the bit is ignored. Rev. 1.00 Nov. 22, 2007 Page 1374 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.18 Port H Data Register (PTDAT_H) PTDAT_H is a 16-bit readable/writable register that stores port H data. Bit: 15  Initial value: R/W: 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7 6 5 4 3 2 1 0 PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ H7 H6 H5 H4 H3 H2 H1 H0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name  Initial Value R/W All 0 R Description Reserved The lower 8-bit value is always read from these bits. The write value should always be 0. 7 6 5 4 3 2 1 0 PTDAT_H7 PTDAT_H6 PTDAT_H5 PTDAT_H4 PTDAT_H3 PTDAT_H2 PTDAT_H1 PTDAT_H0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Each bit stores output data of a pin used as a general output port. When the pin is used as a general output port, if the port is read, the value of the corresponding bit in this register will be read. When the pin is used as a general input port, if this register is read, the status of the corresponding pin will be read. When the pin is set to a function other than the general port, if it is used as an input pin, the pin status will be read from the corresponding bit in this register and writing to the bit is ignored; for an output pin, an undefined value will be read from the bit and writing to the bit is ignored. Rev. 1.00 Nov. 22, 2007 Page 1375 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.19 Port I Data Register (PTDAT_I) PTDAT_I is a 16-bit readable/writable register that stores port I data. Bit: 15  Initial value: R/W: 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7  0 R 6  0 R 5  0 R 4 3 2 1 0 PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ I4 I3 I2 I1 I0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name  Initial Value R/W All 0 R Description Reserved The lower 8-bit value is always read from these bits. The write value should always be 0. 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 3 2 1 0 PTDAT_I4 PTDAT_I3 PTDAT_I2 PTDAT_I1 PTDAT_I0 0 0 0 0 0 R/W R/W R/W R/W R/W Each bit stores output data of a pin used as a general output port. When the pin is used as a general output port, if the port is read, the value of the corresponding bit in this register will be read. When the pin is used as a general input port, if this register is read, the status of the corresponding pin will be read. When the pin is set to a function other than the general port, if it is used as an input pin, the pin status will be read from the corresponding bit in this register and writing to the bit is ignored; for an output pin, an undefined value will be read from the bit and writing to the bit is ignored. Rev. 1.00 Nov. 22, 2007 Page 1376 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.20 Port J Data Register (PTDAT_J) PTDAT_J is a 16-bit readable/writable register that stores port J data. Bit: 15  Initial value: R/W: 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7 6 5 4 3 2 1 0 PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ PTDAT_ J7 J6 J5 J4 J3 J2 J1 J0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name  Initial Value R/W All 0 R Description Reserved The lower 8-bit value is always read from these bits. The write value should always be 0. 7 6 5 4 3 2 1 0 PTDAT_J7 PTDAT_J6 PTDAT_J5 PTDAT_J4 PTDAT_J3 PTDAT_J2 PTDAT_J1 PTDAT_J0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Each bit stores output data of a pin used as a general output port. When the pin is used as a general output port, if the port is read, the value of the corresponding bit in this register will be read. When the pin is used as a general input port, if this register is read, the status of the corresponding pin will be read. When the pin is set to a function other than the general port, if it is used as an input pin, the pin status will be read from the corresponding bit in this register and writing to the bit is ignored; for an output pin, an undefined value will be read from the bit and writing to the bit is ignored. Rev. 1.00 Nov. 22, 2007 Page 1377 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.21 Input-Pin Pull-Up Control Register (PTPUL_SPCL) PTPUL_SPCL is a 16-bit readable/writable register that individually controls the pull-up for the pin corresponding to each bit. Bit: 15  Initial value: R/W: 0 R 14 13 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7  0 R 6  0 R 5  0 R 4  0 R 3  0 R 2  0 R 1  0 R 0  0 R PTPUL_ PTPUL_ IRQ1 IRQ0 0 R/W 0 R/W Bit 15 Bit Name  Initial Value R/W 0 R Description Reserved This bit is always read as 0. The write value should always be 0. 14 PTPUL_IRQ1 0 R/W Controls pull-up of the IRQ1 pin. 0: IRQ1 pin pull-up off 1: IRQ1 pin pull-up on 13 PTPUL_IRQ0 0 R/W Controls pull-up of the IRQ0 pin. 0: IRQ0 pin pull-up off 1: IRQ0 pin pull-up on 12 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1378 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.22 Pin Select Register 0 (PTSEL_A) PTSEL_A is a 16-bit readable/writable register that selects the functions for the port A (PA) pins that multiplex two or more functions other than the port function. To use one of these multiplexed functions for a pin, the port control register should be set to select the functions other than the port function after setting the corresponding bit in PTSEL_A. Bit: 15 14 13 12 11  10 PTSEL_ A5 9  8 PTSEL_ A4 7  6 PTSEL_ A3 5  4 PTSEL_ A2 3  2 PTSEL_ A1 1  0 PTSEL_ A0 PTSEL_A7[1:0] PTSEL_A6[1:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 R/W Bit 15, 14 Bit Name PTSEL_A7[1:0] Initial Value R/W 00 R/W Description Port A (PA7) Function Select 00: STATUS1 01: RTS2 function 10: PA7 function 11: Setting prohibited 13, 12 PTSEL_A6[1:0] 00 R/W Port A (PA6) Function Select 00: STATUS0 01: CTS2 function 10: PA6 function 11: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PTSEL_A5 0 R/W Port A (PA5) Function Select 0: FCE function 1: PA5 function 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8 PTSEL_A4 0 R/W Port A (PA4) Function Select 0: FRE function 1: PA4 function Rev. 1.00 Nov. 22, 2007 Page 1379 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7 Bit Name  Initial Value R/W 0 R Description Reserved This bit is always read as 0. The write value should always be 0. 6 PTSEL_A3 0 R/W Port A (PA3) Function Select 0: FWE function 1: PA3 function 5  0 R Reserved This bit is always read as 0. The write value should always be 0. 4 PTSEL_A2 0 R/W Port A (PA2) Function Select 0: TXD2 function 1: PA2 function 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PTSEL_A1 0 R/W Port A (PA1) Function Select 0: RXD2 function 1: PA1 function 1  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 PTSEL_A0 0 R/W Port A (PA0) Function Select 0: SCK2 function 1: PA0 function Rev. 1.00 Nov. 22, 2007 Page 1380 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.23 Pin Select Register 1 (PTSEL_B) PTSEL_B is a 16-bit readable/writable register that selects the functions for the port B (PB) pins that multiplex two or more functions other than the port function. To use one of these multiplexed functions for a pin, the port control register should be set to select the functions other than the port function after setting the corresponding bit in PTSEL_B. Bit: 15 14 13 12 11 10 9 8 7  6 PTSEL_ B3 5  4 PTSEL_ B2 3  2 PTSEL_ B1 1  0 PTSEL_ B0 PTSEL_B7[1:0] PTSEL_B6[1:0] PTSEL_B5[1:0] PTSEL_B4[1:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 R/W Bit 15, 14 Bit Name PTSEL_B7[1:0] Initial Value R/W 00 R Description Port B (PB7) Function Select 00: A25 function 01: PB7 function 10: DREQ0 function 11: RTS0 function 13, 12 PTSEL_B6[1:0] 00 R/W Port B (PB6) Function Select 00: A24 function 01: PB6 function 10: DACK0 function 11: CTS0 function 11, 10 PTSEL_B5[1:0] 00 R/W Port B (PB5) Function Select 00: A23 function 01: PB5 function 10: DTEND0 function 11: RTS1 function 9, 8 PTSEL_B4[1:0] 00 R/W Port B (PB4) Function Select 00: A22 function 01: PB4 function 10: CTS1 function 11: Setting prohibited Rev. 1.00 Nov. 22, 2007 Page 1381 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7 Bit Name  Initial Value R/W 0 R Description Reserved This bit is always read as 0. The write value should always be 0. 6 PTSEL_B3 0 R/W Port B (PB3) Function Select 0: A21 function 1: PB3 function 5  0 R Reserved This bit is always read as 0. The write value should always be 0. 4 PTSEL_B2 All 0 R/W Port B (PB2) Function Select 0: A20 function 1: PB2 function 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 PTSEL_B1 All 0 R/W Port B (PB1) Function Select 0: A19 function 1: PB1 function 1  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 PTSEL_B0 All 0 R/W Port B (PB0) Function Select 0: A18 function 1: PB0 function Rev. 1.00 Nov. 22, 2007 Page 1382 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.24 Pin Select Register 2 (PTSEL_C) PTSEL_C is a 16-bit readable/writable register that selects the functions for the pins that multiplex two or more functions other than the port function. Bit: 15  14 PTSEL_ C7 13  12 PTSEL_ C6 11  10 PTSEL_ C5 9  8 PTSEL_ C4 7  6 PTSEL_ C3 5  4 PTSEL_ C2 3 2 1  0 PTSEL_ C0 PTSEL_C1[1:0] Initial value: 0 R/W: R 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W Bit 15 Bit Name  Initial Value R/W 0 R Description Reserved This bit is always read as 0. The write value should always be 0. 14 PTSEL_C7 0 R/W Port C (PC7) Function Select 0: AUDIO_CLK0 function 1: PC7 function 13  0 R Reserved This bit is always read as 0. The write value should always be 0. 12 PTSEL_C6 0 R/W Port C (PC6) Function Select 0: AUDIO_CLK1 function 1: PC6 function 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PTSEL_C5 0 R/W Port C (PC5) Function Select 0: AUDIO_CLK2 function 1: PC5 function 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8 PTSEL_C4 0 R/W Port C (PC4) Function Select 0: SSIWS2 function 1: PC4 function Rev. 1.00 Nov. 22, 2007 Page 1383 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7 Bit Name  Initial Value R/W 0 R Description Reserved This bit is always read as 0. The write value should always be 0. 6 PTSEL_C3 0 R/W Port C (PC3) Function Select 0: SSISCK2 function 1: PC3 function 5  0 R Reserved This bit is always read as 0. The write value should always be 0. 4 PTSEL_C2 0 R/W Port C (PC2) Function Select 0: SSIDATA2 function 1: PC2 function 3, 2 PTSEL_C1[1:0] 00 R/W Port C (PC1) Function Select 00: ASEBRKAK/BRKACK function 01: TCLK function 10: PC1 function 11: Setting prohibited 1  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 PTSEL_C0 0 R/W Port C (PC0) Function Select 0: FALE function 1: PC0 function Rev. 1.00 Nov. 22, 2007 Page 1384 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.25 Pin Select Register 3 (PTSEL_D) PTSEL_D is a 16-bit readable/writable register that selects the functions for the pins that multiplex two or more functions other than the port function. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTSEL_D7[1:0] PTSEL_D6[1:0] PTSEL_D5[1:0] PTSEL_D4[1:0] PTSEL_D3[1:0] PTSEL_D2[1:0] PTSEL_D1[1:0] PTSEL_D0[1:0] Initial value: 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTSEL_D7[1:0] Initial Value R/W 00 R/W Description Port D (PD7) Function Select 00: CRS function 01: PD7 function 10: IDEA1_M function 11: Setting prohibited 13, 12 PTSEL_D6[1:0] 00 R/W Port D (PD6) Function Select 00: TX_ER function 01: PD6 function 10: IDEIOWR_M function 11: Setting prohibited 11, 10 PTSEL_D5[1:0] 00 R/W Port D (PD5) Function Select 00: TX_CLK function 01: PD5 function 10: IDED15_M function 11: Setting prohibited 9, 8 PTSEL_D4[1:0] 00 R/W Port D (PD4) Function Select 00: TX_EN function 01: PD4 function 10: IDED0_M function 11: Setting prohibited Rev. 1.00 Nov. 22, 2007 Page 1385 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTSEL_D3[1:0] Initial Value R/W 00 R/W Description Port D (PD3) Function Select 00: MII_TXD0 function 01: SSISCK5 function 10: IDEIORDY_M function 11: PD3 function 5, 4 PTSEL_D2[1:0] 00 R/W Port D (PD2) Function Select 00: MII_TXD1 function 01: SSIWS5 function 10: IDEIORD_M function 11: PD2 function 3, 2 PTSEL_D1[1:0] 00 R/W Port D (PD1) Function Select 00: MII_TXD2 function 01: AUDIO_CLK5 function 10: IDEINT_M function 11: PD1 function 1, 0 PTSEL_D0[1:0] 00 R/W Port D (PD0) Function Select 00: MII_TXD3 function 01: SSIDATA5 function 10: IODACK_M function 11: PD0 function Rev. 1.00 Nov. 22, 2007 Page 1386 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.26 Pin Select Register 4 (PTSEL_E) PTSEL_E is a 16-bit readable/writable register that selects the functions for the pins that multiplex two or more functions other than the port function. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTSEL_E7[1:0] PTSEL_E6[1:0] PTSEL_E5[1:0] PTSEL_E4[1:0] PTSEL_E3[1:0] PTSEL_E2[1:0] PTSEL_E1[1:0] PTSEL_E0[1:0] Initial value: 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTSEL_E7[1:0] Initial Value R/W 00 R/W Description Port E (PE7) Function Select 00: COL function 01: PE7 function 10: IDEA2_M function 11: Setting prohibited 13, 12 PTSEL_E6[1:0] 00 R/W Port E (PE6) Function Select 00: RX_ER function 01: PE6 function 10: IODREQ_M function 11: Setting prohibited 11, 10 PTSEL_E5[1:0] 00 R/W Port E (PE5) Function Select 00: RX_CLK function 01: PE5 function 10: IDED1_M function 11: Setting prohibited 9, 8 PTSEL_E4[1:0] 00 R/W Port E (PE4) Function Select 00: RX_DV function 01: PE4 function 10: IDED14_M function 11: Setting prohibited Rev. 1.00 Nov. 22, 2007 Page 1387 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTSEL_E3[1:0] Initial Value R/W 00 R/W Description Port E (PE3) Function Select 00: MII_RXD0 function 01: SSIWS4 function 10: IDED2_M function 11: PE3 function 5, 4 PTSEL_E2[1:0] 00 R/W Port E (PE2) Function Select 00: MII_RXD1 function 01: SSISCK4 function 10: IDED13_M function 11: PE2 function 3, 2 PTSEL_E1[1:0] 00 R/W Port E (PE1) Function Select 00: MII_RXD2 function 01: SSIDATA4 function 10: IDED3_M function 11: PE1 function 1, 0 PTSEL_E0[1:0] 00 R/W Port E (PE0) Function Select 00: MII_RXD3 function 01: AUDIO_CLK4 function 10: IDED12_M function 11: PE0 function Rev. 1.00 Nov. 22, 2007 Page 1388 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.27 Pin Select Register 5 (PTSEL_F) PTSEL_F is a 16-bit readable/writable register that selects the functions for the pins that multiplex two or more functions other than the port function. Bit: 15  Initial value: R/W: 0 R 14 PTSEL_ F7 13  0 R 12 11 10 9 8 7 6 5 4 3 2 1 0 PTSEL_ PTSEL_F5[1:0] PTSEL_F4[1:0] PTSEL_F3[1:0] PTSEL_F2[1:0] PTSEL_F1[1:0] PTSEL_F0[1:0] F6 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 Bit Name  Initial Value R/W 0 R Description Reserved This bit is always read as 0. The write value should always be 0. 14 PTSEL_F7 0 R/W Port F (PF7) Function Select 0: D32 function 1: PF7 function 13  0 R Reserved This bit is always read as 0. The write value should always be 0. 12 PTSEL_F6 0 R/W Port F (PF6) Function Select 0: D33 function 1: PF6 function 11, 10 PTSEL_F5[1:0] 00 R/W Port F (PF5) Function Select 00: D34 function 01: PF5 function 10: Setting prohibited 11: Setting prohibited 9, 8 PTSEL_F4[1:0] 00 R/W Port F (PF4) Function Select 00: EXOUT function 01: PF4 function 10: IDECS1_M function 11: Setting prohibited Rev. 1.00 Nov. 22, 2007 Page 1389 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTSEL_F3[1:0] Initial Value R/W 00 R/W Description Port F (PF3) Function Select 00: LNKSTA function 01: PF3 function 10: IDECS0_M function 11: Setting prohibited 5, 4 PTSEL_F2[1:0] 00 R/W Port F (PF2) Function Select 00: WOL function 01: PF2 function 10: IDEA0_M function 11: Setting prohibited 3, 2 PTSEL_F1[1:0] 00 R/W Port F (PF1) Function Select 00: MDIO function 01: PF1 function 10: IDED11_M function 11: Setting prohibited 1, 0 PTSEL_F0[1:0] 00 R/W Port F (PF0) Function Select 00: MDC function 01: PF0 function 10: IDED4_M function 11: Setting prohibited Rev. 1.00 Nov. 22, 2007 Page 1390 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.28 Pin Select Register 6 (PTSEL_G) PTSEL_G is a 16-bit readable/writable register that selects the functions for the pins that multiplex two or more functions other than the port function. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTSEL_G7[1:0] PTSEL_G6[1:0] PTSEL_G5[1:0] PTSEL_G4[1:0] PTSEL_G3[1:0] PTSEL_G2[1:0] PTSEL_G1[1:0] PTSEL_G0[1:0] Initial value: 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTSEL_G7[1:0] Initial Value R/W 00 R/W Description Port G (PG7) Function Select 00: LCD_DATA15 function 01: DR3 function 10: PG7 function 11: Setting prohibited 13, 12 PTSEL_G6[1:0] 00 R/W Port G (PG6) Function Select 00: LCD_DATA14 function 01: DR2 function 10: PG6 function 11: Setting prohibited 11, 10 PTSEL_G5[1:0] 00 R/W Port G (PG5) Function Select 00: LCD_DATA13 function 01: DR1 function 10: PG5 function 11: Setting prohibited 9, 8 PTSEL_G4[1:0] 00 R/W Port G (PG4) Function Select 00: LCD_DATA12 function 01: DR0 function 10: PG4 function 11: Setting prohibited Rev. 1.00 Nov. 22, 2007 Page 1391 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTSEL_G3[1:0] Initial Value R/W 00 R/W Description Port G (PG3) Function Select 00: LCD_DATA11 function 01: DG5 function 10: PG3 function 11: Setting prohibited 5, 4 PTSEL_G2[1:0] 00 R/W Port G (PG2) Function Select 00: LCD_DATA10 function 01: DG4 function 10: PG2 function 11: Setting prohibited 3, 2 PTSEL_G1[1:0] 00 R/W Port G (PG1) Function Select 00: LCD_DATA9 function 01: DG3 function 10: PG1 function 11: Setting prohibited 1, 0 PTSEL_G0[1:0] 00 R/W Port G (PG0) Function Select 00: LCD_DATA8 function 01: DG2 function 10: PG0 function 11: Setting prohibited Rev. 1.00 Nov. 22, 2007 Page 1392 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.29 Pin Select Register 7 (PTSEL_H) PTSEL_H is a 16-bit readable/writable register that selects the functions for the pins that multiplex two or more functions other than the port function. Bit: 15  Initial value: R/W: 0 R 14 PTSEL_ H7 13  0 R 12 PTSEL_ H6 11  0 R 10 PTSEL_ H5 9  0 R 8 7 6 5 4 3 2 1 0 PTSEL_ PTSEL_H3[1:0] PTSEL_H2[1:0] PTSEL_H1[1:0] PTSEL_H0[1:0] H4 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 Bit Name  Initial Value R/W 0 R Description Reserved This bit is always read as 0. The write value should always be 0. 14 PTSEL_H7 0 R/W Port H (PH7) Function Select 0: AUDIO_CLK3 function 1: PH7 function 13  0 R Reserved This bit is always read as 0. The write value should always be 0. 12 PTSEL_H6 0 R/W Port H (PH6) Function Select 0: SSIWS3 function 1: PH6 function 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PTSEL_H5 0 R/W Port H (PH5) Function Select 0: SSISCK3 function 1: PH5 function 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8 PTSEL_H4 0 R/W Port H (PH4) Function Select 0: SSIDATA3 function 1: PH4 function Rev. 1.00 Nov. 22, 2007 Page 1393 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTSEL_H3[1:0] Initial Value R/W 00 R/W Description Port H (PH3) Function Select 00: LCD_CL2 function 01: DE_V function 10: PH3 function 11: Setting prohibited 5, 4 PTSEL_H2[1:0] 00 R/W Port H (PH2) Function Select 00: LCD_DON function 01: DCLKOUT function 10: Setting prohibited 11: PH2 function 3, 2 PTSEL_H1[1:0] 00 R/W Port H (PH1) Function Select 00: LCD_VCP_WC function 01: DR4 function 10: PH1 function 11: Setting prohibited 1, 0 PTSEL_H0[1:0] 00 R/W Port H (PH0) Function Select 00: LCD_VEP_WC function 01: DR5 function 10: PH0 function 11: Setting prohibited Rev. 1.00 Nov. 22, 2007 Page 1394 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.30 Pin Select Register 8 (PTSEL_I) PTSEL_I is a 16-bit readable/writable register that selects the functions for the pins that multiplex two or more functions other than the port function. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTSEL_I7[1:0] PTSEL_I6[1:0] PTSEL_I5[1:0] PTSEL_I4[1:0] PTSEL_I3[1:0] PTSEL_I2[1:0] PTSEL_I1[1:0] PTSEL_I0[1:0] Initial value: 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTSEL_I7[1:0] Initial Value R/W 00 R/W Description Port I (PI7) Function Select 00: LCD_DATA3 function 01: DB3 function 10: BT_DATA3 function 11: Setting prohibited 13, 12 PTSEL_I6[1:0] 00 R/W Port I (PI6) Function Select 00: LCD_DATA2 function 01: DB2 function 10: BT_DATA2 function 11: Setting prohibited 11, 10 PTSEL_I5[1:0] 00 R/W Port I (PI5) Function Select 00: LCD_DATA1 function 01: DB1 function 10: BT_DATA1 function 11: Setting prohibited 9, 8 PTSEL_I4[1:0] 00 R/W Port I (PI4) Function Select 00: LCD_DATA7 function 01: DG1 function 10: BT_DATA7 function 11: PI4 function Rev. 1.00 Nov. 22, 2007 Page 1395 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTSEL_I3[1:0] Initial Value R/W 00 R/W Description Port I (PI3) Function Select 00: LCD_DATA6 function 01: DG0 function 10: BT_DATA6 function 11: PI3 function 5, 4 PTSEL_I2[1:0] 00 R/W Port I (PI2) Function Select 00: LCD_DATA5 function 01: DB5 function 10: BT_DATA5 function 11: PI2 function 3, 2 PTSEL_I1[1:0] 00 R/W Port I (PI1) Function Select 00: LCD_DATA4 function 01: DB4 function 10: BT_DATA4 function 11: PI1 function 1, 0 PTSEL_I0[1:0] 00 R/W Port I (PI0) Function Select 00: PI0 function 01: COM/CDE function 10: Setting prohibited 11: Setting prohibited Rev. 1.00 Nov. 22, 2007 Page 1396 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.31 Pin Select Register 9 (PTSEL_J) PTSEL_J is a 16-bit readable/writable register that selects the functions for the pins that multiplex two or more functions other than the port function. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTSEL_J7[1:0] PTSEL_J6[1:0] PTSEL_J5[1:0] PTSEL_J4[1:0] PTSEL_J3[1:0] PTSEL_J2[1:0] PTSEL_J1[1:0] PTSEL_J0[1:0] Initial value: 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTSEL_J7[1:0] Initial Value R/W 00 R/W Description Port J (PJ7) Function Select 00: PJ7 function 01: Setting prohibited 10: Setting prohibited 11: IDED10_M function 13, 12 PTSEL_J6[1:0] 00 R/W Port J (PJ6) Function Select 00: PJ6 function 01: Setting prohibited 10: Setting prohibited 11: IDED5_M function 11, 10 PTSEL_J5[1:0] 00 R/W Port J (PJ5) Function Select 00: PJ5 function 01: Setting prohibited 10: Setting prohibited 11: IDED9_M function 9, 8 PTSEL_J4[1:0] 00 R/W Port J (PJ4) Function Select 00: PJ4 function 01: Setting prohibited 10: Setting prohibited 11: IDED6_M function Rev. 1.00 Nov. 22, 2007 Page 1397 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTSEL_J3[1:0] Initial Value R/W 00 R/W Description Port J (PJ3) Function Select 00: PJ3 function 01: Setting prohibited 10: Setting prohibited 11: IDED7_M function 5, 4 PTSEL_J2[1:0] 00 R/W Port J (PJ2) Function Select 00: PJ2 function 01: Setting prohibited 10: Setting prohibited 11: IDED8_M function 3, 2 PTSEL_J1[1:0] 00 R/W Port J (PJ1) Function Select 00: PJ1 function 01: Setting prohibited 10: Setting prohibited 11: IDERST_M function 1, 0 PTSEL_J0[1:0] 00 R/W Port J (PJ0) Function Select 00: PJ0 function 01: Setting prohibited 10: Setting prohibited 11: DIRECTION_M function Rev. 1.00 Nov. 22, 2007 Page 1398 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.32 Pin Select Register 10 (PTSEL_K) PTSEL_K is a 16-bit readable/writable register that selects the functions for the pins that multiplex two or more functions other than the port function. Bit: 15 14 13 12 11  0 R 10 9 8 7 6 5 4 3 2 1 0 PTSEL_K7[1:0] PTSEL_K6[1:0] Initial value: 0 0 R/W 0 R/W 0 R/W PTSEL_ PTSEL_K4[1:0] PTSEL_K3[1:0] PTSEL_K2[1:0] PTSEL_K1[1:0] PTSEL_K0[1:0] K5 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W: R/W Bit 15, 14 Bit Name PTSEL_K7[1:0] Initial Value R/W 00 R/W Description Port K (PK7) Function Select 00: WDTOVF function 01: IRQ1 function 10: AUDCK function 11: DACK1 function 13, 12 PTSEL_K6[1:0] 00 R/W Port K (PK6) Function Select 00: SCK0 function 01: AUDSYNC function 10: FCLE function 11: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 PTSEL_K5 0 R/W Port K (PK5) Function Select 0: SCK1 function 1: FR/B function 9, 8 PTSEL_K4[1:0] 00 R/W Port K (PK4) Function Select 00: LCD_DATA0 function 01: DB0 function 10: BT_DATA0 function 11: Setting prohibited Rev. 1.00 Nov. 22, 2007 Page 1399 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7, 6 Bit Name PTSEL_K3[1:0] Initial Value R/W 00 R/W Description Port K (PK3) Function Select 00: LCD_CL1 function 01: HSYNC/SPL function 10: BT_HSYNC function 11: Setting prohibited 5, 4 PTSEL_K2[1:0] 00 R/W Port K (PK2) Function Select 00: LCD_CLK function 01: DCLKIN function 10: Setting prohibited 11: Setting prohibited 3, 2 PTSEL_K1[1:0] 00 R/W Port K (PK1) Function Select 00: LCD_FLM function 01: VSYNC/SPS function* 10: BT_VSYNC function 11: Setting prohibited 1, 0 PTSEL_K0[1:0] 00 R/W Port K (PK0) Function Select 00: LCD_M_DISP function 01: DE_C/DE_H function 10: BT_DE_C function 11: Setting prohibited Note: * This pin function switches over input/output functions in a special select register. Rev. 1.00 Nov. 22, 2007 Page 1400 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.33 Pin Select Register 11 (PTSEL_P) PTSEL_P is a 16-bit readable/writable register that selects the functions for the pins that multiplex two or more functions other than the port function. Bit: 15  Initial value: R/W: 0 R 14  0 R 13  0 R 12  0 R 11 10 9 8 7  0 R 6  0 R 5  0 R 4  0 R 3  0 R 2  0 R 1  0 R 0  0 R PTSEL_ PTSEL_ PTSEL_ PTSEL_ 11 10 9 8 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 12 Bit Name  Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 11 PTSEL_P11 0 R/W Port P (PP11) Function Select 0: RXD0 function 1: AUDATA0 function 10 PTSEL_P10 0 R/W Port P (PP10) Function Select 0: TXD0 function 1: AUDATA1 function 9 PTSEL_P9 0 R/W Port P (PP9) Function Select 0: RXD1 function 1: AUDATA2 function 8 PTSEL_P8 0 R/W Port P (PP8) Function Select 0: TXD1 function 1: AUDATA3 function 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1401 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.34 Pin Select Register 12 (PTSEL_R) PTSEL_R is a 16-bit readable/writable register that selects the functions for the pins that multiplex two or more functions other than the port function. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Initial value: 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W: R/W Bit 15 Bit Name PTSEL_R15 Initial Value R/W 0 R/W Description Port P (PR15) Function Select 0: D63 function 1: IDED1 function 14 PTSEL_R14 0 R/W Port P (PR14) Function Select 0: D62 function 1: IDED0 function 13 PTSEL_R13 0 R/W Port P (PR13) Function Select 0: D61 function 1: IDED3 function 12 PTSEL_R12 0 R/W Port P (PR12) Function Select 0: D60 function 1: IDED2 function 11 PTSEL_R11 0 R/W Port P (PR11) Function Select 0: D59 function 1: IDED5 function 10 PTSEL_R10 0 R/W Port P (PR10) Function Select 0: D58 function 1: IDED4 function 9 PTSEL_R9 0 R/W Port P (PR9) Function Select 0: D57 function 1: IDED7 function 8 PTSEL_R8 0 R/W Port P (PR8) Function Select 0: D56 function 1: IDED6 function Rev. 1.00 Nov. 22, 2007 Page 1402 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7 Bit Name PTSEL_R7 Initial Value R/W 0 R/W Description Port P (PR7) Function Select 0: D55 function 1: DIRECTION function 6 PTSEL_R6 0 R/W Port P (PR6) Function Select 0: D54 function 1: IDERST function 5 PTSEL_R5 0 R/W Port P (PR5) Function Select 0: D53 function 1: IDED8 function 4 PTSEL_R4 0 R/W Port P (PR4) Function Select 0: D52 function 1: IDED9 function 3 PTSEL_R3 0 R/W Port P (PR3) Function Select 0: D51 function 1: IDED10 function 2 PTSEL_R2 0 R/W Port P (PR2) Function Select 0: D50 function 1: IDED11 function 1 PTSEL_R1 0 R/W Port P (PR1) Function Select 0: D49 function 1: IDED12 function 0 PTSEL_R0 0 R/W Port P (PR0) Function Select 0: D48 function 1: IDED13 function Rev. 1.00 Nov. 22, 2007 Page 1403 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.35 Pin Select Register 13 (PTSEL_S) PTSEL_S is a 16-bit readable/writable register that selects the functions for the pins that multiplex two or more functions other than the port function. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0  0 R PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ PTSEL_ S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 Initial value: 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W: R/W Bit 15 Bit Name PTSEL_S15 Initial Value R/W 0 R/W Description Port S (PS15) Function Select 0: IRQ0 function 1: DTEND1 function 14 PTSEL_S14 0 R/W Port S (PS14) Function Select 0: IRQOUT function 1: DREQ1 function 13 PTSEL_S13 0 R/W Port S (PS13) Function Select 0: D47 function 1: IDECS0 function 12 PTSEL_S12 0 R/W Port S (PS12) Function Select 0: D46 function 1: IDECS1 function 11 PTSEL_S11 0 R/W Port S (PS11) Function Select 0: D45 function 1: IODACK function 10 PTSEL_S10 0 R/W Port S (PS10) Function Select 0: D44 function 1: IODINT function 9 PTSEL_S9 0 R/W Port S (PS9) Function Select 0: D43 function 1: IDEIORDY function 8 PTSEL_S8 0 R/W Port S (PS8) Function Select 0: D42 function 1: IDEIORD function Rev. 1.00 Nov. 22, 2007 Page 1404 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 7 Bit Name PTSEL_S7 Initial Value R/W 0 R/W Description Port S (PS7) Function Select 0: D41 function 1: IODREQ function 6 PTSEL_S6 0 R/W Port S (PS6) Function Select 0: D40 function 1: IDEIOWR function 5 PTSEL_S5 0 R/W Port S (PS5) Function Select 0: D39 function 1: IDED14 function 4 PTSEL_S4 0 R/W Port S (PS4) Function Select 0: D38 function 1: IDED15 function 3 PTSEL_S3 0 R/W Port S (PS3) Function Select 0: D37 function 1: IDEA1 function 2 PTSEL_S2 0 R/W Port S (PS2) Function Select 0: D36 function 1: IDEA2 function 1 PTSEL_S1 0 R/W Port S (PS1) Function Select 0: D35 function 1: IDEA0 function 0  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1405 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.36 HI-Z Register A (PTHIZ_A) PTHIZ_A is a 16-bit readable/writable register that controls the high-impedance state of the onchip module pins. Bit: 15 PTHIZ _ATA 14 PTHIZ _TMU 13 PTHIZ _LCD 12 11 10 9 8 PTHIZ _SCI1 7 PTHIZ _SCI2 6 5 4 3  0 R 2 — 0 R 1 — 0 R 0 — 0 R PTHIZ PTHIZ PTHIZ PTHIZ _IIC _FLCTL _DMAC _SCI0 PTHIZ PTHIZ PTHIZ _ETH _VDC2 _USB Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 Bit Name PTHIZ_ATA Initial Value R/W 0 R/W Description High-Impedance Control for ATAPI Pins 0: Normal state 1: High-impedance state 14 PTHIZ_TMU 0 R/W High-Impedance Control for TMU Pins 0: Normal state 1: High-impedance state 13 PTHIZ_LCD 0 R/W High-Impedance Control for LCD Pins 0: Normal state 1: High-impedance state 12 PTHIZ_IIC 0 R/W High-Impedance Control for IIC Pins 0: Normal state 1: High-impedance state 11 PTHIZ_FLCTL 0 R/W High-Impedance Control for FLCTL Pins 0: Normal state 1: High-impedance state 10 PTHIZ_DMAC 0 R/W High-Impedance Control for DMAC Pins 0: Normal state 1: High-impedance state 9 PTHIZ_SCI0 0 R/W High-Impedance Control for SCIF Channel 0 Pins 0: Normal state 1: High-impedance state Rev. 1.00 Nov. 22, 2007 Page 1406 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 8 Bit Name PTHIZ_SCI1 Initial Value R/W 0 R/W Description High-Impedance Control for SCIF Channel 1 Pins 0: Normal state 1: High-impedance state 7 PTHIZ_SCI2 0 R/W High-Impedance Control for SCIF Channel 2 Pins 0: Normal state 1: High-impedance state 6 PTHIZ_ETH 0 R/W High-Impedance Control for EtherC Pins 0: Normal state 1: High-impedance state 5 PTHIZ_VDC2 0 R/W High-Impedance Control for VDC2 Pins 0: Normal state 1: High-impedance state 4 PTHIZ_USB 0 R/W High-Impedance Control for USB Pins 0: Normal state 1: High-impedance state 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27.2.37 HI-Z Register B (PTHIZ_B) PTHIZ_B is a 16-bit readable/writable register that controls the high-impedance state of the onchip module pins. Bit: 15 PTHIZ _SSI0 14 PTHIZ _SSI1 13 PTHIZ _SSI2 12 PTHIZ _SSI3 11 PTHIZ _SSI4 10 PTHIZ _SSI5 9 — 0 R 8 — 0 R 7 — 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 1.00 Nov. 22, 2007 Page 1407 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) Bit 15 Bit Name PTHIZ_SSI0 Initial Value R/W 0 R/W Description High-Impedance Control for SSI Channel 0 Pins 0: Normal state 1: High-impedance state 14 PTHIZ_SSI1 0 R/W High-Impedance Control for SSI Channel 1 Pins 0: Normal state 1: High-impedance state 13 PTHIZ_SSI2 0 R/W High-Impedance Control for SSI Channel 2 Pins 0: Normal state 1: High-impedance state 12 PTHIZ_SSI3 0 R/W High-Impedance Control for SSI Channel 3 Pins 0: Normal state 1: High-impedance state 11 PTHIZ_SSI4 0 R/W High-Impedance Control for SSI Channel 4 Pins 0: Normal state 1: High-impedance state 10 PTHIZ_SSI5 0 R/W High-Impedance Control for SSI Channel 5 Pins 0: Normal state 1: High-impedance state 9 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1408 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.2.38 Special Select Register (PTSEL_SPCL) PTSEL_SPCL is a 16-bit readable/writable register that selects the functions input/output for HSYNC and VSYNC other than the port function. Bit: 15  Initial value: R/W: 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7  0 R 6  0 R 5  0 R 4  0 R 3  0 R 2  0 R 1 0 PTSEL_ PTSEL_ VSYNC HSYNC 0 R/W 0 R/W Bit 15 to 2 Bit Name  Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 1 PTSEL_VSYNC 0 R/W VSYNC Function Select 0: VSYNC/SPS function 1: EX_VSYNC function 0 PTSEL_HSYNC 0 R/W HSYNC Function Select 0: HSYNC/SPL function 1: EX_HSYNC function Rev. 1.00 Nov. 22, 2007 Page 1409 of 1692 REJ09B0360-0100 Section 27 General Purpose I/O (GPIO) 27.3 Usage Examples The following describes examples of GPIO setting procedures. 27.3.1 Port Function Select Before selecting the port function, be sure to select the port output or input function as described later. Then, select the port function through the corresponding pin select register (PTSEL_A to PTSEL_J). Note that an error such as a signal conflict will occur if the port function is selected through the pin select register while the input/output setting for the port is wrong. 27.3.2 Port Output Function To select the port output function for a pin, write B'01 to the corresponding two bits in the port control register (PTIO_A to PTIO_J); the data in the corresponding bit in the port data register (PTDAT_A to PTDAT_J) is output from the port. When the port output function is selected for a pin, the setting in the pull-up control register (PTPUL_AB to PTUPL_IJ) for the pin is ignored. 27.3.3 Port Input Function To select the port input function for a pin, write B'10 to the corresponding two bits in the port control register (PTIO_A to PTIO_J) when turning off the pull-up MOS or B'11 when turning on the pull-up MOS; the data input through the pin can be read from the corresponding bit in the port data register (PTDAT_A to PTDAT_J). 27.3.4 On-Chip Module Function To select the on-chip module function, first select the on-chip module to be used through the pin select register (PTSEL_A to PTSEL_J). Then, write B'00 to the corresponding two bits in the port control register (PTIO_A to PTIO_J). Rev. 1.00 Nov. 22, 2007 Page 1410 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode Section 28 Power-Down Mode In power-down modes, operations of the CPU and some of the on-chip peripheral modules are stopped to reduce power consumption. 28.1 Features • Supports refresh standby mode • Supports sleep mode and module standby mode 28.1.1 Types of Power-Down Modes The types and functions of power-down modes are as shown below. • Sleep mode • Refresh standby mode • Module standby mode Rev. 1.00 Nov. 22, 2007 Page 1411 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode Table 28.1 lists the states of the CPU and on-chip peripheral modules in each mode. Table 28.1 States in Power-Down Modes State PowerDown Mode Sleep Transition Condition SLEEP instruction executed with STBY = 0 in STBCR SLEEP instruction executed with STBY = 1 in STBCR CPG Run CPU Halt (register contents retained) Halt (register contents retained) Run On-Chip Memory Retained On-Chip Peripheral Module Run Pin Held DDRSDRAM AR or SR*1 Cancellation - Interrupt - Power-on reset S1*2 S0*2 1 0 Refresh standby Halt Halt (contents retained) Halt Held (only CLKOUT operates) SR*1 - NMI or IRQ - Power-on reset 0 1 Module standby Corresponding Run bit in MSTPCR0/ MSTPCR1 set to 1 PRESET pin driven low Initial state Run Run Selected Held modules halt AR or SR*1 Clear 0 corresponding bit in MSTPCR0/ MSTPCR1 to 0   1 0 0 Power-on reset Normal operation Initial state Run Initial state Run Initial state Run Initial state Run Initial state Run 1 0 Notes: 1. AF: auto-refresh: SF: self-refresh 2. S1 and S0 are the output states on the STATUS1 and STATUS0 pins, respectively. Rev. 1.00 Nov. 22, 2007 Page 1412 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode 28.2 Input/Output Pins Table 28.2 lists the pin configuration related to power-down modes. Table 28.2 Pin Configuration Pin Name STATUS1 STATUS0 Function Processing state 1 Processing state 0 I/O Output Output Description These pins indicate the operating state of this LSI. STATUS[1:0] H, H: H, L: L, H: L, L: Operating state Power-on reset Sleep mode Refresh standby mode Normal operation 28.3 Register Descriptions Table 28.3 shows the register configuration for power-down modes. Table 28.4 shows the register states in each operating mode. Table 28.3 Register Configuration Register Name Standby control register Module stop register 0 Module stop register 1 Abbreviation R/W STBCR MSTPCR0 MSTPCR1 R/W R/W R/W Area P4 Address H'FFC8 0020 H'FFC8 0030 H'FFC8 0038 Area 7 Address H'1FC8 0020 H'1FC8 0030 H'1FC8 0038 Access Size 32 32 32 Table 28.4 Register States in Each Operating Mode Register Name Standby control register Module stop register 0 Module stop register 1 Abbreviation STBCR MSTPCR0 MSTPCR1 Power-On Reset H'0000 0000 H'0000 0000 H'0000 0000 Sleep Retained Retained Retained Standby Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1413 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode 28.3.1 Standby Control Register (STBCR) STBCR is a 32-bit readable/writable register that selects a power-down mode to be entered after a SLEEP instruction is executed. STBCR can be accessed only in longwords. Bit: 31 — Initial value: R/W: Bit: 0 R 15 30 — 0 R 14 — 0 R 29 — 0 R 13 28 — 0 R 12 27 — 0 R 11 26 — 0 R 10 25 — 0 R 9 24 — 0 R 8 23 — 0 R 7 STBY 0 R/W 22 — 0 R 6 21 — 20 — 0 R 4 19 — 18 — 17 — 16 — 0 R 5 0 R 3 0 R 2 0 R 1 0 R 0 — — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R Initial value: R/W: 0 R Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 8  7 STBY 0 R/W Standby Selects whether to enter sleep mode or refresh standby mode after a SLEEP instruction is executed. 0: Sleep mode 1: Refresh standby mode Clear this bit to 0 when returning from the refresh standby mode by an interrupt. 6 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1414 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode 28.3.2 Module Stop Register 0 (MSTPCR0) MSTPCR0 is a 32-bit readable/writable register that can individually start or stop the module assigned to each bit. MSTPCR0 can be accessed only in longwords. Bit: 31 — Initial value: R/W: Bit: 0 R 15 30 — 0 R 14 — 0 R 29 — 0 R 13 28 — 0 R 12 27 — 0 R 11 26 — 0 R 10 25 — 0 R 9 24 — 0 R 8 23 — 0 R 7 22 21 20 — 0 R 4 19 H-UDI 18 — 17 UBC 16 — INTC DMAC 0 R/W 6 0 R/W 5 0 R/W 3 0 R 2 0 R/W 1 0 R 0 LCDC TMU FLCTL 0 R/W 0 R/W — 0 R SCIF2 SCIF1 SCIF0ETHER IIC 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W ATAPI G2D 0 R/W 0 R/W — 0 R VDC2 0 R/W — 0 R USB 0 R/W Initial value: R/W: 0 R/W Bit 31 to 23 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 22 INTC 0 R/W INTC Module Stop Bit When set to 1, the clock supply to the INTC module is halted. 0: INTC operates 1: Clock supply to INTC is halted 21 DMAC 0 R/W DMAC Module Stop Bit When set to 1, the clock supply to the DMAC module is halted. 0: DMAC operates 1: Clock supply to DMAC is halted 20  0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1415 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode Bit 19 Bit Name H-UDI Initial Value 0 R/W R/W Description H-UDI Module Stop Bit When set to 1, the clock supply to the H-UDI module is halted. 0: H-UDI operates 1: Clock supply to H-UDI is halted 18  0 R Reserved These bits are always read as 0. The write value should always be 0. 17 UBC 0 R/W UBC Module Stop Bit When set to 1, the clock supply to the UBC module is halted. 0: UBC operates 1: Clock supply to UBC is halted 16  0 R Reserved These bits are always read as 0. The write value should always be 0. 15 LCDC 0 R/W LCDC Module Stop Bit When set to 1, the clock supply to the LCDC module is halted. 0: LCDC operates 1: Clock supply to LCDC is halted 14  0 R Reserved These bits are always read as 0. The write value should always be 0. 13 TMU 0 R/W TMU Module Stop Bit When set to 1, the clock supply to the TMU module is halted. 0: TMU operates 1: Clock supply to TMU is halted 12 FLCTL 0 R/W FLCTL Module Stop Bit When set to 1, the clock supply to the FLCTL module is halted. 0: FLCTL operates 1: Clock supply to FLCTL is halted Rev. 1.00 Nov. 22, 2007 Page 1416 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode Bit 11 Bit Name  Initial Value 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 SCIF2 0 R/W SCIF2 Module Stop Bit When set to 1, the clock supply to the SCIF2 module is halted. 0: SCIF2 operates 1: Clock supply to SCIF2 is halted 9 SCIF1 0 R/W SCIF1 Module Stop Bit When set to 1, the clock supply to the SCIF1 module is halted. 0: SCIF1 operates 1: Clock supply to SCIF1 is halted 8 SCIF0 0 R/W SCIF0 Module Stop Bit When set to 1, the clock supply to the SCIF0 module is halted. 0: SCIF0 operates 1: Clock supply to SCIF0 is halted 7 ETHER 0 R/W ETHER Module Stop Bit When set to 1, the clock supply to the ETHER module is halted. 0: ETHER operates 1: Clock supply to ETHER is halted 6 IIC 0 R/W IIC Module Stop Bit When set to 1, the clock supply to the IIC module is halted. 0: IIC operates 1: Clock supply to IIC is halted 5 ATAPI 0 R/W ATAPI Module Stop Bit When set to 1, the clock supply to the ATAPI module is halted. 0: ATAPI operates 1: Clock supply to ATAPI is halted Rev. 1.00 Nov. 22, 2007 Page 1417 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode Bit 4 Bit Name G2D Initial Value 0 R/W R/W Description G2D Module Stop Bit When set to 1, the clock supply to the G2D module is halted. 0: G2D operates 1: Clock supply to G2D is halted 3  0 R Reserved These bits are always read as 0. The write value should always be 0. 2 VDC2 0 R/W VDC2 Module Stop Bit When set to 1, the clock supply to the VDC2 module is halted. 0: VDC2 operates 1: Clock supply to VDC2 is halted 1  0 R Reserved These bits are always read as 0. The write value should always be 0. 0 USB 0 R/W USB Module Stop Bit When set to 1, the clock supply to the USB module is halted. 0: USB operates 1: Clock supply to USB is halted Rev. 1.00 Nov. 22, 2007 Page 1418 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode 28.3.3 Module Stop Register 1 (MSTPCR1) MSTPCR1 is a 32-bit readable/writable register that can individually start or stop the module assigned to each bit. MSTPCR1 can be accessed only in longwords. Bit: 31 SRC Initial value: R/W: Bit: 0 R/W 15 30 — 0 R 14 — 0 R 29 — 0 R 13 28 — 0 R 12 27 — 0 R 11 26 — 0 R 10 25 24 23 — 0 R 7 22 — 0 R 6 21 — 20 — 0 R 4 19 — 18 — 17 — 16 — SSI_B SSI_A 0 R/W 9 0 R/W 8 0 R 5 0 R 3 0 R 2 0 R 1 0 R 0 — — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R — 0 R Initial value: R/W: 0 R Bit 31 Bit Name SRC Initial Value 0 R/W R/W Description SRC Module Stop Bit When set to 1, the clock supply to the SRC module is halted. 0: SRC operates 1: Clock supply to SRC is halted 30 to 26  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25 SSI_B 0 R/W SSI_B Module Stop Bit When set to 1, the clock supply to the SSI_B module is halted. 0: SSI_B operates 1: Clock supply to SSI_B is halted 24 SSI_A 0 R/W SSI_A Module Stop Bit When set to 1, the clock supply to the SSI_A module is halted. 0: SSI_A operates 1: Clock supply to SSI_A is halted 23 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 22, 2007 Page 1419 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode 28.4 28.4.1 Sleep Mode Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of the CPU registers remain unchanged. On-chip peripheral modules continue to operate, and the clock output on the CLKOUT pin also continues. In sleep mode, a high level is output to the STATUS1 pin and a low level to the STATUS0 pin. 28.4.2 Canceling Sleep Mode Sleep mode is canceled by an interrupt (NMI, IRQ1, IRQ0 or on-chip peripheral module interrupt) or a reset. Interrupts are accepted in sleep mode even when the BL bit in SR is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP instruction. (1) Canceling with Interrupt When an NMI, IRQ1, IRQ0 or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. A code indicating the interrupt source is set in INTEVT. (2) Canceling with Reset Sleep mode is canceled by a power-on reset caused by the PRESET pin or watchdog timer overflow. Rev. 1.00 Nov. 22, 2007 Page 1420 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode 28.5 28.5.1 Refresh Standby Mode Transition to Refresh Standby Mode Executing the SLEEP instruction when the STBY bit in STBCR is 1 causes a transition from the program execution state to refresh standby mode. In refresh standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. However, the clock output from the CLKOUT pin continues. The contents of the CPU and cache registers remain unchanged. Some registers of the on-chip peripheral modules are initialized. The procedure for a transition to software standby mode is as follows: 1. Set the STBY bit in STBCR to 1. 2. Execute the SLEEP instruction. 3. Software standby mode is entered and the clocks within the LSI are halted. The output on the STATUS0 pin goes high. 28.5.2 Canceling Refresh Standby Mode Refresh standby mode is canceled by an interrupt (NMI or IRQ/IRL) or a reset. (1) Canceling with Interrupt When an NMI or IRQ, occurs, refresh standby mode is canceled and the STATUS0 pin goes low. Thereafter, interrupt exception handling is executed and a code indicating the interrupt source is set in INTEVT. After branching to the interrupt service routine, clear the STBY bit in the STBCR register back to 0. Since interrupts are accepted in refresh standby mode even when the BL bit in SR is 1, save SPC and SSR to the stack before executing the SLEEP instruction if necessary. Immediately after an interrupt is detected, the clock output on the CLKOUT pin may be unstable until software standby mode is canceled. (2) Canceling with Reset Refresh standby mode is cancelled by a power-on reset by the PRESET pin. Rev. 1.00 Nov. 22, 2007 Page 1421 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode 28.6 28.6.1 Module Standby Mode Transition to Module Standby Mode Setting the bits in the module stop register to 1 halts the clock supply to the corresponding on-chip peripheral modules. Modules in module standby mode keep the state immediately before the transition to the module standby mode. The registers retain their contents before the module is halted, and the external pins also hold their states before halted. At waking up from the module standby state, operation starts from the condition immediately before the module was halted. 28.6.2 Canceling Module Standby Mode The module standby mode can be canceled by clearing the respective bit in the module stop register to 0 or by a power-on reset. Rev. 1.00 Nov. 22, 2007 Page 1422 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode 28.7 28.7.1 STATUS Pin Signal Change Timing Timing at Reset Refer to section 29.5, Status Pin Change Timing during Reset. 28.7.2 (1) Timing at Sleep Mode Cancellation When an Interrupt Occurs in Sleep Mode Figure 28.1 shows the timing of signal changes on the STATUS pins. Interrupt request CLKOUT IRQOUT output STATUS[1:0] output LL (Normal operation) HL (sleep) LL (Normal operation) Figure 28.1 STATUS Output when an Interrupt Occurs in Sleep Mode Rev. 1.00 Nov. 22, 2007 Page 1423 of 1692 REJ09B0360-0100 Section 28 Power-Down Mode Rev. 1.00 Nov. 22, 2007 Page 1424 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset Section 29 Watchdog Timer and Reset The reset and watchdog timer (WDT) control circuit comprises the reset control unit and WDT control unit which control the power-on reset sequence and a reset for on-chip peripheral modules and external devices. The WDT is a one-channel timer which can be used as the watchdog timer or interval timer. 29.1 Features • WDT monitors a system crash using a timer counting at specified intervals. • WDT supports the watchdog timer mode and the interval timer mode. • WDT generates an internal reset and output the WDTOVF signal when a WDT counter overflow occurs in watchdog timer mode. • WDT generates the interval timer interrupt when a WDT counter overflow occurs in interval timer mode. • The maximum time until the watchdog timer overflows is approximately 21 seconds (when the peripheral clock Pck is 50 MHz). • Writing to WDT-related registers is not normally allowed. A specified code in the upper bits of write data enables writing to the registers. Rev. 1.00 Nov. 22, 2007 Page 1425 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset Figure 29.1 shows a block diagram of the WDT. Watchdog timer and Reset Reset control circuit WDTOVF 2 STATUS1 STATUS0 PRESET Internal reset request CPG Interrupt control circuit INTC Interrupt request WDTCSR Count-up signal WDTCNT Comparator WDTBCNT Comparator Peripheral clock WDTST WDTBST [Legend] WDTBCNT: WDTBST: WDTCNT: WDTCSR: WDTST: Watchdog timer base counter Watchdog timer base stop time register Watchdog timer counter Watchdog timer control/status register Watchdog timer stop time register Figure 29.1 Block Diagram Rev. 1.00 Nov. 22, 2007 Page 1426 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset 29.2 Input/Output Pins Table 29.1 shows the pin configuration of the WDT. Table 29.1 Pin Configuration Pin name PRESET STATUS1 STATUS0 Function Reset Processing state 1 Processing state 0 I/O Input Output Description Power-on reset Indicate the processor's operating status STATUS1 High High Low Low STATUS0 High Low High Low Operating Status Reset Sleep mode Refresh standby mode Normal operation Pins for STATUS1 and STATUS0 are multiplexed to each other function independently. WDTOVF Watchdog timer overflow Output Counter overflow signal output in the watchdog timer mode. Rev. 1.00 Nov. 22, 2007 Page 1427 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset 29.3 Register Descriptions Table 29.2 shows the registers of the WDT. Table 29.3 shows the register states in each processing mode. Table 29.2 Register Configuration Register Name Watchdog timer stop time register Watchdog timer control/status register Watchdog timer base stop time register Watchdog timer counter Watchdog timer base counter Abbreviation R/W WDTST WDTCSR WDTBST WDTCNT WDTBCNT R/W R/W R/W R R P4 Address H'FFCC 0000 H'FFCC 0004 H'FFCC 0008 H'FFCC 0010 H'FFCC 0018 Area 7 Address H'1FCC 0000 H'1FCC 0004 H'1FCC 0008 H'1FCC 0010 H'1FCC 0018 Access Size 32 32 32 32 32 Table 29.3 Register States in Each Processing Mode Power-on Reset by Abbreviation PRESET Pin WDTST WDTCSR WDTBST WDTCNT WDTBCNT H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Power-on Reset by WDT/H-UDI Retained Retained Retained Retained Retained Register Name Watchdog timer stop time register Watchdog timer control/status register Watchdog timer base stop time register Watchdog timer counter Watchdog timer base counter Sleep Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1428 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset 29.3.1 Watchdog Timer Stop Time Register (WDTST) WDTST is a readable/writable 32-bit register that specifies the time until a watchdog timer overflows. The time until WDTCNT overflows becomes the minimum value when set H'001 to the bits 11 to 0, and the maximum value when set H'000 to the bits 11 to 0. Use a longword access to write to the WDTST, with H'5A in the bits 31 to 24. The reading value of bits 31 to 24 is always H'00. Bit: 31 30 29 28 27 26 25 24 23  0 R/W 10 0 R/W 9 0 R/W 8 0 R 7 22  0 R 6 21  0 R 5 20  0 R 4 19  0 R 3 18  0 R 2 17  0 R 1 16  0 R 0 (Given code) Initial value: R/W: Bit: 0 R/W 15  Initial value: R/W: 0 R 0 R/W 14  0 R 0 R/W 13  0 R 0 R/W 12  0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 11 WDTST 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 24 Bit Name (Given code)  Initial Value H'00 R/W R/W Description Reserved (Given code for writing) These bits are always read as H'00. To write to this register, the write value must be H'5A. 23 to 12 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 WDTST All 0 R/W Counter value Rev. 1.00 Nov. 22, 2007 Page 1429 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset 29.3.2 Watchdog Timer Control/Status Register (WDTCSR) WDTCSR is a readable/writable 32-bit register that comprises the timer mode-selecting bit and overflow flags. Use a longword access to write to the WDTCSR, with H'A5 in the bits 31 to 24. The reading value of bits 31 to 24 is always H'00. Bit: 31 30 29 28 27 26 25 24 23  0 R/W 10  0 R 0 R/W 9  0 R 0 R/W 8  0 R 0 R 7 TME 22  0 R 6 WT/IT 21  0 R 5  0 R 20  0 R 4 19  0 R 3 18  0 R 2  0 R 17  0 R 1  0 R 16  0 R 0  0 R (Given code) Initial value: R/W: Bit: 0 R/W 15  0 R/W 14  0 R 0 R/W 13  0 R 0 R/W 12  0 R 0 R/W 11  0 R WOVF IOVF Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 24 Bit Name (Given code)  Initial Value H'00 R/W R/W Description Reserved (Given code for writing) These bits are always read as H'00. To write to this register, the write value must be H'A5. 23 to 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 TME 0 R/W Timer Enable Specifies starting and stopping of timer operation. 0: Stops counting up 1: Starts counting up 6 WT/IT 0 R/W Timer Mode Select Specifies whether the WDT is used as a watchdog timer or interval timer. Up counting may not be performed correctly if this bit is modified while the WDT is running. 0: Interval timer mode 1: Watchdog timer mode Rev. 1.00 Nov. 22, 2007 Page 1430 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset Bit 5 Bit Name  Initial Value 0 R/W  Description Reserved This bit is always read as 0. The write value should always be 0 4 WOVF 0 R/W Watchdog Timer Overflow Flag Indicates that WDTCNT has overflowed in watchdog timer mode. This flag is not set in interval timer mode. 0: An overflow has not occurred 1: An overflow on WDTCNT has occurred 3 IOVF 0 R/W Interval Timer Overflow Flag Indicates that WDTCNT has overflowed in interval timer mode. This flag is not set in watchdog timer mode. 0: An overflow has not occurred 1: An overflow on WDTCNT has occurred 2 to 0  R All 0 Reserved These bits are always read as 0. The write value should always be 0. 29.3.3 Watchdog timer Base Stop Time Register (WDTBST) WDTBST is a readable/writable 32-bit register that clears WDTBCNT. Use a longword write access to clear the WDTBCNT, with H'55 in the bits 31 to 24. The reading value of this register is always H'00. Bit: 31 30 29 28 27 26 25 24 23  0 R/W 10 22  0 R 6 21  0 R 5  0 R 20  0 R 4  0 R 19  18  17  16  (Given code) Initial value: R/W: Bit: 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 9  0 R 0 R/W 8 0 R 7 0 R 3  0 R 0 R 2  0 R 0 R 1  0 R 0 R 0  0 R  Initial value: R/W: 0 R  0 R  0 R  0 R  0 R  0 R  0 R  0 R  0 R Rev. 1.00 Nov. 22, 2007 Page 1431 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset 29.3.4 Watchdog Timer Counter (WDTCNT) WDTCNT is a 32-bit read-only register that comprises 12-bit watchdog timer counter and counts up on the WDTBCNT overflow signal. When WDTCNT overflows, a reset is generated in watchdog timer mode, or an interrupt is generated in interval timer mode. Writing to WDTCNT is invalid. Bit: 31  Initial value: R/W: Bit: 0 R 15  Initial value: R/W: 0 R 30  0 R 14  0 R 29  0 R 13  0 R 28  0 R 12  0 R 0 R 0 R 0 R 0 R 0 R 27  0 R 11 26  0 R 10 25  0 R 9 24  0 R 8 23  0 R 7 22  0 R 6 21  0 R 5 20  0 R 4 19  0 R 3 18  0 R 2 17  0 R 1 16  0 R 0 WDTCNT 0 R 0 R 0 R 0 R 0 R 0 R 0 R 29.3.5 Watchdog Timer Base Counter (WDTBCNT) WDTBCNT is a 32-bit read-only register that comprises 18-bit counter and counts up on the peripheral clock (Pck). When WDTBCNT overflows, WDTCNT is counted up and WDTBCNT is cleared to 0. Writing to WDTBCNT is invalid. Bit: 31  Initial value: R/W: Bit: 30  0 R 14 29  0 R 13 28  0 R 12 27  0 R 11 26  0 R 10 25  0 R 9 24  0 R 8 23  0 R 7 22  0 R 6 21  0 R 5 20  0 R 4 19  18  17 16 WDTBCNT 0 R 1 0 R 15 0 R 3 0 R 2 0 R 0 WDTBCNT Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Rev. 1.00 Nov. 22, 2007 Page 1432 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset 29.4 29.4.1 Operation Reset request Power-on reset is available. (1) 1. • • • Power-on reset Reset sources Input low level via PRESET pin. The WDTCNT overflows when the WT/IT bit in the WDTCSR is 1. The H-UDI reset occurs (For details, see section 31, User Debugging Interface (H-UDI)). 2. Branch destination address: H'A000 0000 3. Operation in branch Exception code H'000 is set in the EXPEVT register. The VBR and SR registers are initialized, and the program branches to PC =H'A000 0000. By initialization, the VBR register is set to H'0000 0000. In the SR register, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the IMASK3 to IMASK0 bits (interrupt mask level) are set to B'1111. The CPU and the peripheral modules are also initialized. For details, see the register descriptions in each section. When the power is turned on, be sure to input a low level to the PRESET pin. The TRST pin should also be brought low level to initialize the H-UDI. Power_on_reset() { EXPEVT = H'0000 0000; VBR = H'0000 0000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A000 0000; } Rev. 1.00 Nov. 22, 2007 Page 1433 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset 29.4.2 1. 2. 3. 4. Using watchdog timer mode Set the WDTCNT overflow interval value in WDTST. Set the WT/IT bit in WDTCSR to 1. When the TME bit in WTCSR is set to 1, the WDT count starts. During operation in watchdog timer mode, clear to the WDTCNT or WDTBCNT periodically so that WDTCNT does not overflow. See section 29.4.5, Clearing WDT Counter for WDT counter clear method. 5. When the WDTCNT overflows, the WDT sets the WOVF flag in WDTCSR to 1, and generates a power-on reset. Using Interval timer mode 29.4.3 When the WDT is operating in interval timer mode, an interval timer interrupt is generated each time the counter overflows. This enables interrupts to be generated at fixed intervals. 1. 2. 3. 4. Set the WDTCNT overflow time in WDTST. Clear the WT/IT bit in WDTCSR to 0. When the TME bit in WDTCSR is set to 1, the WDT count starts. When the WDTCNT overflows, the WDT sets the IOVF flag in WDTCSR to 1, and sends an interval timer interrupt (ITI) request to INTC. The counter continues counting. Time for WDT Overflow 29.4.4 The relationship between WDTCNT and WDTBCNT is shown in figure 29.2. The example shown in the figure is the operation in interval timer mode, where WDTCNT restarts counting after it has overflowed. In watchdog timer mode, WDTCNT and WDTBCNT are cleared to 0 after the reset state is exited and start counting up again. Rev. 1.00 Nov. 22, 2007 Page 1434 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset WDTCNT value Cleared to 0 on overflow WDTST Incremented on each WDTBCNT overflow H'0000 0000 Time WDTBCNT value H'0003 FFFF Cleared to 0 on overflow Incremented every peripheral clock (Pck) cycle H'0000 0000 Counting starts TME WOVF IOVF Flag is set Time Figure 29.2 WDT Counting Operations (Example in Interval Timer Mode) WDTBCNT is a 18-bit up-counter operated on the peripheral clock (Pck). WDTBCNT is cleared when H'55 is set to the bits 31 to 24 in WDTBST. If the peripheral clock frequency is 50 MHz, the WDTBCNT overflow time is approximately 5.243 ms (= 2^18 [bit] × 1/50 [MHz]). WDTCNT is a 12-bit counter, starts count up operation when overflow occurs in WDTBCNT. The time until WDTCNT overflows becomes the maximum value when H'000 are set to WDTST. Where the peripheral clock frequency is 50 MHz, the maximum overflow time is approximately 21.475 s (= 2^12 [bit] × 5.243 [ms]). And the time until WDTCNT overflows becomes the minimum value when H'001 is set to WDTST. The minimum overflow time is approximately 5.243 ms (= 2^1 [bit] × 5.243 [ms]). 29.4.5 Clearing WDT Counter Writing H'55 to WDTBST with longword access clears WDTBCNT and writing the overflow setting value to WDTST clears WDTCNT. Rev. 1.00 Nov. 22, 2007 Page 1435 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset 29.5 29.5.1 Status Pin Change Timing during Reset Power-On Reset by PRESET A power-on reset is to initialize the on-chip PLL circuit when this LSI goes to the power-on reset state by the PERSET pin low level input and then it is necessary to ensure the synchronization settling time of the PLL circuit. Therefore, do not input high level to the PRESET pin during the synchronization settling time of the PLL. The PLL synchronization settling time is the total value of the PLL1 synchronization settling time and the PLL2 synchronization settling time. After the PRESET pin input level is changed from low level to high level, the reset state is continued during the reset holding time in the LSI. The reset holding time is equal to or more than 10240 cycles of the input signal from EXTAL pin. Turning On Power Supply When turning on the power supply, the PRESET pin input level should be low level. And the TRST pin input level should be low level to initialize the H-UDI. The STATUS [1:0] pins output timing that indicates the reset state is asynchronous, and that indicates a normal operation is synchronous with the peripheral clock (Pck) and asynchronous with both the EXTAL pin input clock and the CLKOUT pin output clock. Rev. 1.00 Nov. 22, 2007 Page 1436 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset EXTAL input CLKOUT output VDD PRESET input TRST input STATUS[1:0] output HH (reset) LL (normal) EXTAL input stabilization time Reset holding time PLL synchronization settling time Figure 29.3 STATUS Output during Power-on PRESET input during normal operation It is necessary to ensure the PLL synchronization settling time when the PRESET input during normal operation. The STATUS [1:0] pins output timing that indicates the reset state is asynchronous, and that indicates a normal operation is synchronous with the peripheral clock (Pck) and asynchronous with both the EXTAL pin input clock and the CLKOUT pin output clock. Rev. 1.00 Nov. 22, 2007 Page 1437 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset EXTAL input CLKOUT output PRESET input STATUS[1:0] output LL (normal) HH (reset) LL (normal) Reset holding time PLL synchronization settling time Figure 29.4 STATUS Output by Reset input during Normal Operation PRESET input during Sleep Mode It is necessary to ensure the PLL oscillation time when power-on reset generates by the PRESET pin low revel input during sleep mode. The STATUS [1:0] pins output timing that indicates the reset state is asynchronous, and that indicates a normal operation is synchronous with the peripheral clock (Pck) and asynchronous with both the EXTAL pin input clock and the CLKOUT pin output clock. EXTAL input CLKOUT output PRESET input STATUS[1:0] output HL (sleep) HH (reset) LL (normal) Reset holding time PLL synchronization settling time Figure 29.5 STATUS Output by Reset input during Sleep Mode Rev. 1.00 Nov. 22, 2007 Page 1438 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset 29.5.2 Power-On Reset by Watchdog Timer Overflow The transition time from the watchdog timer overflowed to the power-on reset state (watchdog timer reset setup time) is 9 clock cycle of the EXTAL input clock and thereafter equal to or more than 18 clock cycles of the peripheral clock (Pck). The power-on reset time (watchdog timer reset holding time) by the watchdog timer overflowed is equal to or more than one cycle of input signal from EXTAL pin and thereafter equal to or more than 5 clock cycles of the peripheral clock (Pck). Power-On Reset by Watchdog timer Overflowed in Normal Operation The STATUS [1:0] pins output timing that indicates the reset state or a normal operation is asynchronous with both the EXTAL pin input clock and the CLKOUT pin output clock because the STATUS [1:0] pins output timing is synchronous with the peripheral clock (Pck). EXTAL input CLKOUT output WDT overflow signal STATUS[1:0] output LL (normal) HH (reset) LL (normal) WDT reset setup time WDT reset holding time Figure 29.6 STATUS Output by Watchdog timer overflow Power-On Reset during Normal Operation Power-On Reset by Watchdog timer Overflowed in Sleep Mode The STATUS [1:0] pins output timing that indicates the reset state or a normal operation is asynchronous with both the EXTAL pin input clock and the CLKOUT pin output clock because the STATUS [1:0] pins output timing is synchronous with the peripheral clock (Pck). Rev. 1.00 Nov. 22, 2007 Page 1439 of 1692 REJ09B0360-0100 Section 29 Watchdog Timer and Reset EXTAL input CLKOUT output WDT overflow signal STATUS[1:0] output HL (sleep) HH (reset) LL (normal) WDT reset setup time WDT reset holding time Figure 29.7 STATUS Output by Watchdog timer overflow Power-On Reset during Sleep Mode Rev. 1.00 Nov. 22, 2007 Page 1440 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) Section 30 User Break Controller (UBC) The user break controller (UBC) provides versatile functions to facilitate program debugging. These functions help to ease creation of a self-monitor/debugger, which allows easy program debugging using this LSI alone, without using the in-circuit emulator. Various break conditions can be set in the UBC: instruction fetch or read/write access of an operand, operand size, data contents, address value, and program stop timing for instruction fetch. 30.1 Features 1. The following break conditions can be set. Break channels: Two (channels 0 and 1) User break conditions can be set independently for channels 0 and 1, and can also be set as a single sequential condition for the two channels, that is, a sequential break. (Sequential break involves two cases such that the channel 0 break condition is satisfied in a certain bus cycle and then the channel 1 break condition is satisfied in a different bus cycle, and vice versa.) • Address When 40 bits containing ASID and 32-bit address are compared with the specified value, all the ASID bits can be compared or masked. 32-bit address can be masked bit by bit, allowing the user to mask the address in desired page sizes such as lower 12 bits (4-Kbyte page) and lower 10 bits (1-Kbyte page). • Data 32 bits can be masked only for channel 1. • Bus cycle The program can break either for instruction fetch (PC break) or operand access. • Read or write access • Operand sizes Byte, word, longword, and quadword are supported. 2. The user-designated exception handling routine for the user break condition can be executed. 3. Pre-instruction-execution or post-instruction-execution can be selected as the PC break timing. 4. A maximum of 212 – 1 repetition counts can be specified as the break condition (available only for channel 1). Rev. 1.00 Nov. 22, 2007 Page 1441 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) Figure 30.1 shows the UBC block diagram. SDB SAB ASID Access control Internal bus Access comparator ASID comparator Address comparator Channel 0 operation control CAR0 CAMR0 CRR0 CBR0 Access comparator ASID comparator Address comparator CBR1 CAR1 CAMR1 CDR1 CDMR1 CETR1 CRR1 Data comparator Channel 1 operation control CCMFR Control CBCR User break is requested. [Legend] CBR0: CRR0: CAR0: CAMR0: CBR1: CRR1: CAR1: Match condition setting register 0 Match operation setting register 0 Match address setting register 0 Match address mask setting register 0 Match condition setting register 1 Match operation setting register 1 Match address setting register 1 CAMR1: Match address mask setting register 1 CDR1: Match data setting register 1 CDMR1: Match data mask setting register 1 CETR1: Execution count break register CCMFR: Channel match flag register CBCR: Break control register Operand address bus SAB: Operand data bus SDB: Figure 30.1 Block Diagram of UBC Rev. 1.00 Nov. 22, 2007 Page 1442 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 30.2 Register Descriptions The UBC has the following registers. Table 30.1 Register Configuration Name Match condition setting register 0 Match operation setting register 0 Match address setting register 0 Abbreviation CBR0 CRR0 CAR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P4 Address* H'FF200000 H'FF200004 H'FF200008 H'FF20000C H'FF200020 H'FF200024 H'FF200028 H'FF20002C H'FF200030 H'FF200034 H'FF200038 H'FF200600 H'FF200620 Area 7 Address* H'1F200000 H'1F200004 H'1F200008 H'1F20000C H'1F200020 H'1F200024 H'1F200028 H'1F20002C H'1F200030 H'1F200034 H'1F200038 H'1F200600 H'1F200620 Access Size 32 32 32 32 32 32 32 32 32 32 32 32 32 Match address mask setting CAMR0 register 0 Match condition setting register 1 Match operation setting register 1 Match address setting register 1 CBR1 CRR1 CAR1 Match address mask setting CAMR1 register 1 Match data setting register 1 CDR1 Match data mask setting register 1 Execution count break register 1 Channel match flag register Break control register Note: * CDMR1 CETR1 CCMFR CBCR P4 addresses are used when area P4 in the virtual address space is used, and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB. Rev. 1.00 Nov. 22, 2007 Page 1443 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) Table 30.2 Register Status in Each Processing State Register Name Match condition setting register 0 Match operation setting register 0 Match address setting register 0 Match address mask setting register 0 Match condition setting register 1 Match operation setting register 1 Match address setting register 1 Match address mask setting register 1 Match data setting register 1 Match data mask setting register 1 Execution count break register 1 Channel match flag register Break control register Abbreviation CBR0 CRR0 CAR0 CAMR0 CBR1 CRR1 CAR1 CAMR1 CDR1 CDMR1 CETR1 CCMFR CBCR Power-on Reset H'20000000 H'00002000 Undefined Undefined H'20000000 H'00002000 Undefined Undefined Undefined Undefined Undefined H'00000000 H'00000000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained The access size must be the same as the control register size. If the size is different, the register is not written to if attempted, and reading the register returns the undefined value. A desired break may not occur between the time when the instruction for rewriting the control register is executed and the time when the written value is actually reflected on the register. In order to confirm the exact timing when the control register is updated, read the data which has been written most recently. The subsequent instructions are valid for the most recently written register value. Rev. 1.00 Nov. 22, 2007 Page 1444 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 30.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1) CBR0 and CBR1 are readable/writable 32-bit registers which specify the break conditions for channels 0 and 1, respectively. The following break conditions can be set in the CBR0 and CBR1: (1) whether or not to include the match flag in the conditions, (2) whether or not to include the ASID, and the ASID value when included, (3) whether or not to include the data value, (4) operand size, (5) whether or not to include the execution count, (6) bus type, (7) instruction fetch cycle or operand access cycle, and (8) read or write access cycle. • CBR0 Bit : Initial value : R/W: Bit : Initial value : R/W: 31 MFE 0 R/W 15 0 R 30 AIE 0 R/W 14 0 R/W 1 R/W 13 SZ 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 12 29 28 27 MFI 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 CD 0 R/W 0 R/W 0 R/W 0 R/W 6 0 R/W 5 ID 0 R/W 0 R 26 25 24 23 22 21 20 AIV 0 R/W 4 0 R/W 3 0 R/W 2 RW 0 R/W 0 R/W 0 R/W 1 0 R/W 0 CE 0 R/W 19 18 17 16 Bit 31 Bit Name MFE Initial Value 0 R/W R/W Description Match Flag Enable Specifies whether or not to include the match flag value specified by the MFI bit of this register in the match conditions. When the specified match flag value is 1, the condition is determined to be satisfied. 0: The match flag is not included in the match conditions; thus, not checked. 1: The match flag is included in the match conditions. 30 AIE 0 R/W ASID Enable Specifies whether or not to include the ASID specified by the AIV bit of this register in the match conditions. 0: The ASID is not included in the match conditions; thus, not checked. 1: The ASID is included in the match conditions. Rev. 1.00 Nov. 22, 2007 Page 1445 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) Bit 29 to 24 Bit Name MFI Initial Value 100000 R/W R/W Description Match Flag Specify Specifies the match flag to be included in the match conditions. 000000: MF0 bit of the CCMFR register 000001: MF1 bit of the CCMFR register Others: Reserved (setting prohibited) Note: The initial value is the reserved value, but when 1 is written into CBR0[0], MFI must be set to 000000 or 000001. And note that the channel 0 is not hit when MFE bit of this register is 1 and MFI bits are 000000 in the condition of CCRMF.MF0 = 0. 23 to 16 AIV All 0 R/W ASID Specify Specifies the ASID value to be included in the match conditions. 15 — 0 R Reserved For read/write in this bit, refer to General Precautions on Handling of Product. 14 to 12 SZ All 0 R/W Operand Size Select Specifies the operand size to be included in the match conditions. This bit is valid only when the operand access cycle is specified as a match condition. 000: The operand size is not included in the match conditions; thus, not checked (any operand size specifies the match condition).*1 001: Byte access 010: Word access 011: Longword access 100: Quadword access* 2 Others: Reserved (setting prohibited) 11 to 8 — All 0 R Reserved For read/write in this bit, refer to General Precautions on Handling of Product. Rev. 1.00 Nov. 22, 2007 Page 1446 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) Bit 7, 6 Bit Name CD Initial Value All 0 R/W R/W Description Bus Select Specifies the bus to be included in the match conditions. This bit is valid only when the operand access cycle is specified as a match condition. 00: Operand bus for operand access Others: Reserved (setting prohibited) 5, 4 ID All 0 R/W Instruction Fetch/Operand Access Select Specifies the instruction fetch cycle or operand access cycle as the match condition. 00: Instruction fetch cycle or operand access cycle 01: Instruction fetch cycle 10: Operand access cycle 11: Instruction fetch cycle or operand access cycle 3 — 0 R Reserved For read/write in this bit, refer to General Precautions on Handling of Product. 2, 1 RW All 0 R/W Bus Command Select Specifies the read/write cycle as the match condition. This bit is valid only when the operand access cycle is specified as a match condition. 00: Read cycle or write cycle 01: Read cycle 10: Write cycle 11: Read cycle or write cycle 0 CE 0 R/W Channel Enable Validates/invalidates the channel. If this bit is 0, all the other bits of this register are invalid. 0: Invalidates the channel. 1: Validates the channel. Rev. 1.00 Nov. 22, 2007 Page 1447 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) • CBR1 Bit : 31 MFE Initial value : 0 R/W: R/W Bit : 15 30 AIE 0 R/W 14 0 R/W 1 R/W 13 SZ 0 R/W 0 R/W 12 29 28 27 MFI 0 R/W 11 0 R/W 10 0 R 0 R/W 9 0 R 0 R/W 8 0 R 0 R/W 7 CD 0 R/W 0 R/W 0 R/W 0 R/W 6 0 R/W 5 ID 0 R/W 0 R 26 25 24 23 22 21 20 AIV 0 R/W 4 0 R/W 3 0 R/W 2 RW 0 R/W 0 R/W 0 R/W 1 0 R/W 0 CE 0 R/W 19 18 17 16 DBE Initial value : 0 R/W: R/W ETBE 0 0 R/W R/W Bit 31 Bit Name MFE Initial Value 0 R/W R/W Description Match Flag Enable Specifies whether or not to include the match flag value specified by the MFI bit of this register in the match conditions. When the specified match flag value is 1, the condition is determined to be satisfied. 0: The match flag is not included in the match conditions; thus, not checked. 1: The match flag is included in the match conditions. 30 AIE 0 R/W ASID Enable Specifies whether or not to include the ASID specified by the AIV bit of this register in the match conditions. 0: The ASID is not included in the match conditions; thus, not checked. 1: The ASID is included in the match conditions. 29 to 24 MFI 100000 R/W Match Flag Specify Specifies the match flag to be included in the match conditions. 000000: The MF0 bit of the CCMFR register 000001: The MF1 bit of the CCMFR register Others: Reserved (setting prohibited) Note: The initial value is the reserved value, but when 1 is written into CBR1[0], MFI must be set to 000000 or 000001. And note that the channel 1 is not hit when MFE bit of this register is 1 and MFI bits are 000001 in the condition of CCRMF.MF1 = 0. Rev. 1.00 Nov. 22, 2007 Page 1448 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) Bit 23 to 16 Bit Name AIV Initial Value All 0 R/W R/W Description ASID Specify Specifies the ASID value to be included in the match conditions. 15 DBE 0 R/W Data Value Enable*3 Specifies whether or not to include the data value in the match condition. This bit is valid only when the operand access cycle is specified as a match condition. 0: The data value is not included in the match conditions; thus, not checked. 1: The data value is included in the match conditions. 14 to 12 SZ All 0 R/W Operand Size Select Specifies the operand size to be included in the match conditions. This bit is valid only when the operand access cycle is specified as a match condition. 000: The operand size is not included in the match condition; thus, not checked (any operand size 1 specifies the match condition). * 001: Byte access 010: Word access 011: Longword access 100: Quadword access* 2 Others: Reserved (setting prohibited) 11 ETBE 0 R/W Execution Count Value Enable Specifies whether or not to include the execution count value in the match conditions. If this bit is 1 and the match condition satisfaction count matches the value specified by the CETR1 register, the operation specified by the CRR1 register is performed. 0: The execution count value is not included in the match conditions; thus, not checked. 1: The execution count value is included in the match conditions. 10 to 8 — All 0 R Reserved For read/write in this bit, refer to General Precautions on Handling of Product. Rev. 1.00 Nov. 22, 2007 Page 1449 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) Bit 7, 6 Bit Name CD Initial Value All 0 R/W R/W Description Bus Select Specifies the bus to be included in the match conditions. This bit is valid only when the operand access cycle is specified as a match condition. 00: Operand bus for operand access Others: Reserved (setting prohibited) 5, 4 ID All 0 R/W Instruction Fetch/Operand Access Select Specifies the instruction fetch cycle or operand access cycle as the match condition. 00: Instruction fetch cycle or operand access cycle 01: Instruction fetch cycle 10: Operand access cycle 11: Instruction fetch cycle or operand access cycle 3 — 0 R Reserved For read/write in this bit, refer to General Precautions on Handling of Product. 2, 1 RW All 0 R/W Bus Command Select Specifies the read/write cycle as the match condition. This bit is valid only when the operand access cycle is specified as a match condition. 00: Read cycle or write cycle 01: Read cycle 10: Write cycle 11: Read cycle or write cycle 0 CE 0 R/W Channel Enable Validates/invalidates the channel. If this bit is 0, all the other bits in this register are invalid. 0: Invalidates the channel. 1: Validates the channel. Notes: 1. If the data value is included in the match conditions, be sure to specify the operand size. 2. If the quadword access is specified and the data value is included in the match conditions, the upper and lower 32 bits of 64-bit data are each compared with the contents of both the match data setting register and the match data mask setting register. Rev. 1.00 Nov. 22, 2007 Page 1450 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 3. The OCBI instruction is handled as longword write access without the data value, and the PREF, OCBP, and OCBWB instructions are handled as longword read access without the data value. Therefore, do not include the data value in the match conditions for these instructions. 30.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1) CRR0 and CRR1 are readable/writable 32-bit registers which specify the operation to be executed when channels 0 and 1 satisfy the match condition, respectively. The following operations can be set in the CRR0 and CRR1 registers: (1) breaking at a desired timing for the instruction fetch cycle and (2) requesting a break. • CRR0 Bit : Initial value : R/W: Bit : Initial value : R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 1 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 PCB 0 R/W 16 0 R 0 BIE 0 R/W Bit 31 to 14 Bit Name — Initial Value All 0 R/W R Description Reserved For read/write in this bit, refer to General Precautions on Handling of Product. 13 — 1 R Reserved This bit is always read as 1. The write value should always be 1. 12 to 2 — All 0 R Reserved For read/write in this bit, refer to General Precautions on Handling of Product. Rev. 1.00 Nov. 22, 2007 Page 1451 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) Bit 1 Bit Name PCB Initial Value 0 R/W R/W Description PC Break Select Specifies either before or after instruction execution as the break timing for the instruction fetch cycle. This bit is invalid for breaks other than the ones for the instruction fetch cycle. 0: Sets the PC break before instruction execution. 1: Sets the PC break after instruction execution. 0 BIE 0 R/W Break Enable Specifies whether or not to request a break when the match condition is satisfied for the channel. 0: Does not request a break. 1: Requests a break. • CRR1 Bit : Initial value : R/W: Bit : Initial value : R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 1 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 PCB 0 R/W 16 0 R 0 BIE 0 R/W Bit 31 to 14 Bit Name — Initial Value All 0 R/W R Description Reserved For read/write in this bit, refer to General Precautions on Handling of Product. 13 — 1 R Reserved This bit is always read as 1. The write value should always be 1. 12 to 2 — All 0 R Reserved For read/write in this bit, refer to General Precautions on Handling of Product. Rev. 1.00 Nov. 22, 2007 Page 1452 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) Bit 1 Bit Name PCB Initial Value 0 R/W R/W Description PC Break Select Specifies either before or after instruction execution as the break timing for the instruction fetch cycle. This bit is invalid for breaks other than ones for the instruction fetch cycle. 0: Sets the PC break before instruction execution. 1: Sets the PC break after instruction execution. 0 BIE 0 R/W Break Enable Specifies whether or not to request a break when the match condition is satisfied for the channel. 0: Does not request a break. 1: Requests a break. 30.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1) CAR0 and CAR1 are readable/writable 32-bit registers specifying the virtual address to be included in the break conditions for channels 0 and 1, respectively. • CAR0 Bit : Initial value : R/W: Bit : Initial value : R/W: 31 30 29 28 27 26 25 24 CA R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 CA R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 23 22 21 20 19 18 17 16 Bit 31 to 0 Bit Name CA Initial Value Undefined R/W R/W Description Compare Address Specifies the address to be included in the break conditions. When the operand bus has been specified using the CBR0 register, specify the SAB address in CA[31:0]. Rev. 1.00 Nov. 22, 2007 Page 1453 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) • CAR1 Bit : Initial value : R/W: Bit : Initial value : R/W: 31 30 29 28 27 26 25 24 CA R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 CA R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 23 22 21 20 19 18 17 16 Bit 31 to 0 Bit Name CA Initial Value Undefined R/W R/W Description Compare Address Specifies the address to be included in the break conditions. When the operand bus has been specified using the CBR1 register, specify the SAB address in CA[31:0]. 30.2.4 Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1) CMAR0 and CMAR1 are readable/writable 32-bit registers which specify the bits to be masked among the address bits specified by using the match address setting register of the corresponding channel. (Set the bits to be masked to 1.) • CAMR0 Bit : Initial value : R/W: Bit : Initial value : R/W: 31 30 29 28 27 26 25 24 23 CAM R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 CAM R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 22 21 20 19 18 17 16 Rev. 1.00 Nov. 22, 2007 Page 1454 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) Bit 31 to 0 Bit Name CAM Initial Value Undefined R/W R/W Description Compare Address Mask Specifies the bits to be masked among the address bits which are specified using the CAR0 register. (Set the bits to be masked to 1.) 0: Address bits CA[n] are included in the break condition. 1: Address bits CA[n] are masked and not included in the break condition. [n] = any values from 31 to 0 • CAMR1 Bit : Initial value : R/W: Bit : Initial value : R/W: 31 30 29 28 27 26 25 24 23 CAM R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 CAM R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 22 21 20 19 18 17 16 Bit 31 to 0 Bit Name CAM Initial Value Undefined R/W R/W Description Compare Address Mask Specifies the bits to be masked among the address bits which are specified using the CAR1 register. (Set the bits to be masked to 1.) 0: Address bits CA[n] are included in the break condition. 1: Address bits CA[n] are masked and not included in the break condition. [n] = any values from 31 to 0 Rev. 1.00 Nov. 22, 2007 Page 1455 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 30.2.5 Match Data Setting Register 1 (CDR1) CDR1 is a readable/writable 32-bit register which specifies the data value to be included in the break conditions for channel 1. Bit : Initial value : R/W: Bit : Initial value : R/W: 31 30 29 28 27 26 25 24 CD R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 CD R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 23 22 21 20 19 18 17 16 Bit 31 to 0 Bit Name CD Initial Value Undefined R/W R/W Description Compare Data Value Specifies the data value to be included in the break conditions. When the operand bus has been specified using the CBR1 register, specify the SDB data value in CD[31:0]. Table 30.3 Settings for Match Data Setting Register Bus and Size Selected Using CBR1 CD[31:24] Operand bus (byte) Operand bus (word) Don't care Don't care CD[23:16] Don't care Don't care CD[15:8] Don't care SDB15 to SDB8 CD[7:0] SDB7 to SDB0 SDB7 to SDB0 SDB7 to SDB0 Operand bus (longword) SDB31 to SDB24 SDB23 to SDB16 SDB15 to SDB8 Notes: 1. If the data value is included in the match conditions, be sure to specify the operand size. 2. The OCBI instruction is handled as longword write access without the data value, and the PREF, OCBP, and OCBWB instructions are handled as longword read access without the data value. Therefore, do not include the data value in the match conditions for these instructions. 3. If the quadword access is specified and the data value is included in the match conditions, the upper and lower 32 bits of 64-bit data are each compared with the contents of both the match data setting register and match data mask setting register. Rev. 1.00 Nov. 22, 2007 Page 1456 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 30.2.6 Match Data Mask Setting Register 1 (CDMR1) CDMR1 is a readable/writable 32-bit register which specifies the bits to be masked among the data value bits specified using the match data setting register. (Set the bits to be masked to 1.) Bit : Initial value : R/W: Bit : Initial value : R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CDM R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 CDM R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 Bit 31 to 0 Bit Name CDM Initial Value Undefined R/W R/W Description Compare Data Value Mask Specifies the bits to be masked among the data value bits specified using the CDR1 register. (Set the bits to be masked to 1.) 0: Data value bits CD[n] are included in the break condition. 1: Data value bits CD[n] are masked and not included in the break condition. [n] = any values from 31 to 0 Rev. 1.00 Nov. 22, 2007 Page 1457 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 30.2.7 Execution Count Break Register 1 (CETR1) CETR1 is a readable/writable 32-bit register which specifies the number of the channel hits before a break occurs. A maximum value of 212 – 1 can be specified. When the execution count value is included in the match conditions by using the match condition setting register, the value of this register is decremented by one every time the channel is hit. When the channel is hit after the register value reaches H'001, a break occurs. Bit : Initial value : R/W: Bit : Initial value : R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 26 0 R 10 25 0 R 9 24 0 R 8 23 0 R 7 22 0 R 6 CET R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0 Bit Initial Bit Name Value All 0 R/W R Description Reserved For read/write in this bit, refer to General Precautions on Handling of Product. 31 to 12 — 11 to 0 CET Undefined R/W Execution Count Specifies the execution count to be included in the break conditions. Rev. 1.00 Nov. 22, 2007 Page 1458 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 30.2.8 Channel Match Flag Register (CCMFR) CCMFR is a readable/writable 32-bit register which indicates whether or not the match conditions have been satisfied for each channel. When a channel match condition has been satisfied, the corresponding flag bit is set to 1. To clear the flags, write the data containing value 0 for the bits to be cleared and value 1 for the other bits to this register. (The logical AND between the value which has been written and the current register value is actually written to the register.) Sequential operation using multiple channels is available by using these match flags. Bit : Initial value : R/W: Bit : Initial value : R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 MF1 0 R/W 16 0 R 0 MF0 0 R/W Bit 31 to 2 Bit Name — Initial Value All 0 R/W R Description Reserved For read/write in this bit, refer to General Precautions on Handling of Product. 1 MF1 0 R/W Channel 1 Condition Match Flag This flag is set to 1 when the channel 1 match condition has been satisfied. To clear the flag, write 0 to this bit. 0: Channel 1 match condition has not been satisfied. 1: Channel 1 match condition has been satisfied. 0 MF0 0 R/W Channel 0 Condition Match Flag This flag is set to 1 when the channel 0 match condition has been satisfied. To clear the flag, write 0 to this bit. 0: Channel 0 match condition has not been satisfied. 1: Channel 0 match condition has been satisfied. Rev. 1.00 Nov. 22, 2007 Page 1459 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 30.2.9 Break Control Register (CBCR) CBCR is a readable/writable 32-bit register which specifies whether or not to use the user break debugging support function. For details on the user break debugging support function, refer to section 30.4, User Break Debugging Support Function. Bit : Initial value : R/W: Bit : Initial value : R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 0 R 16 0 R 0 UBDE 0 R/W Bit 31 to 1 Bit Name — Initial Value All 0 R/W R Description Reserved For read/write in this bit, refer to General Precautions on Handling of Product. 0 UBDE 0 R/W User Break Debugging Support Function Enable Specifies whether or not to use the user break debugging support function. 0: Does not use the user break debugging support function. 1: Uses the user break debugging support function. Rev. 1.00 Nov. 22, 2007 Page 1460 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 30.3 30.3.1 Operation Description Definition of Words Related to Accesses "Instruction fetch" refers to an access in which an instruction is fetched. For example, fetching the instruction located at the branch destination after executing a branch instruction is an instruction access. "Operand access" refers to any memory access accompanying execution of an instruction. For example, accessing an address (PC + disp × 2 + 4) in the instruction MOV.W@(disp,PC),Rn is an operand access. "Data" is used in contrast to "address". All types of operand access are classified into read or write access. Special care must be taken in using the following instructions. • PREF, OCBP, and OCBWB: Instructions for a read access • MOVCA.L and OCBI: Instructions for a write access • TAS.B: Instruction for a single read access or a single write access The operand access accompanying the PREF, OCBP, OCBWB, and OCBI instructions is access without the data value; therefore, do not include the data value in the match conditions for these instructions. The operand size should be defined for all types of operand access. Available operand sizes are byte, word, longword, and quadword. For operand access accompanying the PREF, OCBP, OCBWB, MOVCA.L, and OCBI instructions, the operand size is defined as longword. 30.3.2 User Break Operation Sequence The following describes the sequence from when the break condition is set until the user break exception handling is initiated. 1. Specify the operand size, bus, instruction fetch/operand access, and read/write as the match conditions using the match condition setting register (CBR0 or CBR1). Specify the break address using the match address setting register (CAR0 or CAR1), and specify the address mask condition using the match address mask setting register (CAMR0 or CAMR1). To include the ASID in the match conditions, set the AIE bit in the match condition setting register and specify the ASID value by the AIV bit in the same register. To include the data value in the match conditions, set the DBE bit in the match condition setting register; specify the break data using the match data setting register (CDR1); and specify the data mask condition using the match data mask setting register (CDMR1). To include the execution count in the match conditions, set the ETBE bit of the match condition setting register; and Rev. 1.00 Nov. 22, 2007 Page 1461 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 2. 3. 4. 5. 6. 7. specify the execution count using the execution count break register (CETR1). To use the sequential break, set the MFE bit of the match condition setting register; and specify the number of the first channel using the MFI bit. Specify whether or not to request a break when the match condition is satisfied and the break timing when the match condition is satisfied as a result of fetching the instruction using the match operation setting register (CRR0 or CRR1). After having set all the bits in the match condition setting register except the CE bit and the other necessary registers, set the CE bit and read the match condition setting register again. This ensures that the set values in the control registers are valid for the subsequent instructions immediately after reading the register. Setting the CE bit of the match condition setting register in the initial state after reset via the control registers may cause an undesired break. When the match condition has been satisfied, the corresponding condition match flag (MF1 or MF0) in the channel match flag register (CCMFR) is set. A break is also requested to the CPU according to the set values in the match operation setting register (CRR0 or CRR1). The CPU operates differently according to the BL bit value of the SR register: when the BL bit is 0, the CPU accepts the break request and executes the specified exception handling; and when the BL bit is 1, the CPU does not execute the exception handling. The match flags (MF1 and MF0) can be used to confirm whether or not the corresponding match condition has been satisfied. Although the flag is set when the condition is satisfied, it is not cleared automatically; therefore, write 0 to the flag bit by issuing a memory store instruction to the channel match flag register (CCMFR) in order to use the flag again. Breaks may occur virtually at the same time for channels 0 and 1. In this case, only one break request is sent to the CPU; however, the two condition match flags corresponding to these breaks may be set. While the BL bit in the SR register is 1, no break requests are accepted. However, whether or not the condition has been satisfied is determined. When the condition is determined to be satisfied, the corresponding condition match flag is set. If the sequential break conditions are set, the condition match flag is set every time the match conditions are satisfied for each channel. When the conditions have been satisfied for the first channel in the sequence but not for the second channel in the sequence, clear the condition match flag for the first channel in the sequence in order to release the first channel in the sequence from the match state. Instruction Fetch Cycle Break 30.3.3 1. If the instruction fetch cycle is set in the match condition setting register (CBR0 or CBR1), the instruction fetch cycle is handled as a match condition. To request a break upon satisfying the match condition, set the BIE bit in the match operation setting register (CRR0 or CRR1) of the corresponding channel. Either before or after executing the instruction can be selected as the Rev. 1.00 Nov. 22, 2007 Page 1462 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) break timing according to the PCB bit value. If the instruction fetch cycle is specified as a match condition, be sure to clear the LSB to 0 in the match address setting register (CAR0 or CAR1); otherwise, no break occurs. 2. If pre-instruction-execution break is specified for the instruction fetch cycle, the break is requested when the instruction is fetched and determined to be executed. Therefore, this function cannot be used for the instructions which are fetched through overrun (i.e., the instructions fetched during branching or making transition to the interrupt routine but not executed). For priorities of pre-instruction-execution break and the other exceptions, refer to section 5, Exception Handling. If pre-instruction-execution break is specified for the delayed slot of the delayed branch instruction, the break is requested before the delayed branch instruction is executed. However, do not specify pre-instruction-execution break for the delayed slot of the RTE instruction. 3. If post-instruction-execution break is specified for the instruction fetch cycle, the break is requested after the instruction which satisfied the match condition has been executed and before the next instruction is executed. Similar to pre-instruction-execution break, this function cannot be used for the instructions which are fetched through overrun. For priorities of post-instruction-execution break and the other exceptions, refer to section 5, Exception Handling. If post-instruction-execution break is specified for the delayed branch instruction and its delayed slot, the break does not occur until the first instruction at the branch destination. 4. If the instruction fetch cycle is specified as the channel 1 match condition, the DBE bit of match condition setting register CBR1 becomes invalid, the settings of match data setting register CDR1 and match data mask setting register CDMR1 are ignored. Therefore, the data value cannot be specified for the instruction fetch cycle break. Rev. 1.00 Nov. 22, 2007 Page 1463 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 30.3.4 Operand Access Cycle Break 1. Table 30.4 shows the relation between the operand sizes specified using the match condition setting register (CBR0 or CBR1) and the address bits to be compared for the operand access cycle break. Table 30.4 Relation between Operand Sizes and Address Bits to be Compared Selected Operand Size Quadword Longword Word Byte Operand size is not included in the match conditions Address Bits to be Compared Address bits A31 to A3 Address bits A31 to A2 Address bits A31 to A1 Address bits A31 to A0 Address bits A31 to A3 for quadword access Address bits A31 to A2 for longword access Address bits A31 to A1 for word access Address bits A31 to A0 for byte access The above table means that if address H'00001003 is set in the match address setting register (CAR0 or CAR1), for example, the match condition is satisfied for the following access cycles (assuming that all the other conditions are satisfied):  Longword access to address H'00001000  Word access to address H'00001002  Byte access to address H'00001003 2. When the data value is included in the channel 1 match conditions: If the data value is included in the match conditions, be sure to select the quadword, longword, word, or byte as the operand size using the operand size select bit (SZ) of the match condition setting register (CBR1), and also set the match data setting register (CDR1) and the match data mask setting register (CDMR1). With these settings, the match condition is satisfied when both of the address and data conditions are satisfied. The data value and mask control for byte access, word access, and longword access should be set in bits 7 to 0, 15 to 0, and 31 to 0 in the bits CDR1 and CDMR1, respectively. For quadword access, 64-bit data is divided into the upper and lower 32-bit data units, and each unit is independently compared with the specified condition. When either the upper or lower 32-bit data unit satisfies the match condition, the match condition for the 64-bit data is determined to be satisfied. Rev. 1.00 Nov. 22, 2007 Page 1464 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 3. The operand access accompanying the PREF, OCBP, OCBWB, and OCBI instructions are access without the data value; therefore, if the data value is included in the match conditions for these instructions, the match conditions will never be satisfied. 4. If the operand bus is selected, a break occurs after executing the instruction which has satisfied the conditions and immediately before executing the next instruction. However, if the data value is included in the match conditions, a break may occur after executing several instructions after the instruction which has satisfied the conditions; therefore, it is impossible to identify the instruction causing the break. If such a break has occurred for the delayed branch instruction or its delayed slot, the break does not occur until the first instruction at the branch destination. However, do not specify the operand break for the delayed slot of the RTE instruction. And if the data value is included in the match conditions, it is not allowed to set the break for the preceding the RTE instruction by one to six instructions. 30.3.5 Sequential Break 1. Sequential break conditions can be specified by setting the MFE and MFI bits in the match condition setting registers (CBR0 and CBR1). (Sequential break involves two cases such that channel 0 break condition is satisfied then channel 1 break condition is satisfied, and vice versa.) To use the sequential break function, clear the MFE bit of the match condition setting register and the BIE bit of the match operation setting register of the first channel in the sequence, and set the MFE bit and specify the number of the second channel in the sequence using the MFI bit in the match condition setting register of the second channel in the sequence. If the sequential break condition is set, the condition match flag is set every time the match condition is satisfied for each channel. When the condition has been satisfied for the first channel in the sequence but not for the second channel in the sequence, clear the condition match flag for the first channel in the sequence in order to release the first channel in the sequence from the match state. 2. For channel 1, the execution count break condition can also be included in the sequential break conditions. 3. If the match conditions for the first and second channels in the sequence are satisfied within a significantly short time, sequential operation may not be guaranteed in some cases, as shown below. Rev. 1.00 Nov. 22, 2007 Page 1465 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) • When the Match Condition is Satisfied at the Instruction Fetch Cycle for Both the First and Second Channels in the Sequence: Instruction B is 0 instruction after instruction A Equivalent to setting the same addresses; do not use this setting. Instruction B is one instruction after instruction A Sequential operation is not guaranteed. Instruction B is two or more instructions after instruction A Sequential operation is guaranteed. • When the match condition is satisfied at the instruction fetch cycle for the first channel in the sequence whereas the match condition is satisfied at the operand access cycle for the second channel in the sequence: Instruction B is 0 or one instruction after instruction A Instruction B is two or more instructions after instruction A Sequential operation is not guaranteed. Sequential operation is guaranteed. • When the match condition is satisfied at the operand access cycle for the first channel in the sequence whereas the match condition is satisfied at the instruction fetch cycle for the second channel in the sequence: Instruction B is 0 to five instructions after instruction A Instruction B is six or more instructions after instruction A Sequential operation is not guaranteed. Sequential operation is guaranteed. • When the match condition is satisfied at the operand access cycle for both the first and second channels in the sequence: Instruction B is 0 to five instructions after instruction A Instruction B is six or more instructions after instruction A Sequential operation is not guaranteed. Sequential operation is guaranteed. Rev. 1.00 Nov. 22, 2007 Page 1466 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 30.3.6 Program Counter Value to be Saved When a break has occurred, the address of the instruction to be executed when the program restarts is saved in the SPC then the exception handling state is initiated. A unique instruction causing a break can be identified unless the data value is included in the match conditions. • When the instruction fetch cycle (before instruction execution) is specified as the match condition: The address of the instruction which has satisfied the match conditions is saved in the SPC. The instruction which has satisfied the match conditions is not executed, but a break occurs instead. However, if the match conditions are satisfied for the delayed slot instruction, the address of the delayed branch instruction is saved in the SPC. • When the instruction fetch cycle (after instruction execution) is specified as the match condition: The address of the instruction immediately after the instruction which has satisfied the match conditions is saved in the SPC. The instruction which has satisfied the match conditions is executed, then a break occurs before the next instruction. If the match conditions are satisfied for the delayed branch instruction or its delayed slot, these instructions are executed and the address of the branch destination is saved in the SPC. • When the operand access (address only) is specified as the match condition: The address of the instruction immediately after the instruction which has satisfied the break conditions is saved in the SPC. The instruction which has satisfied the match conditions are executed, then a break occurs before the next instruction. However, if the conditions are satisfied for the delayed slot, the address of the branch destination is saved in the SPC. • When the operand access (address and data) is specified as the match condition: If the data value is added to the match conditions, the instruction which has satisfied the match conditions is executed. A user break occurs before executing an instruction that is one through six instructions after the instruction which has satisfied the match conditions. The address of the instruction is saved in the SPC; thus, it is impossible to identify exactly where a break will occur. If the conditions are satisfied for the delayed slot instruction, the address of the branch destination is saved in the SPC. If a branch instruction follows the instruction which has satisfied the match conditions, a break may occur after the delayed instruction and delayed slot are executed. In this case, the address of the branch destination is also saved in the SPC. Rev. 1.00 Nov. 22, 2007 Page 1467 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 30.4 User Break Debugging Support Function By using the user break debugging support function, the branch destination address can be modified when the CPU accepts the user break request. Specifically, setting the UBDE bit of break control register CBCR to 1 allows branching to the address indicated by DBR instead of branching to the address indicated by the [VBR + offset]. Figure 30.2 shows the flowchart of the user break debugging support function. Rev. 1.00 Nov. 22, 2007 Page 1468 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) Exception/interrupt is generated Hardware operations SPC ← PC SSR ← SR SR.BL ← B'1 SR.MD ← B'1 SR.RB ← B'1 Exception Trap Exception/interrupt/trap? Interrupt EXPEVT ← Exception code INTEVT ← Interrupt code EXPEVT ← H'160 TRA ← TRAPA (imm) SGR ← R15 No Yes Reset exception? No Yes (CBCR.UBDE == 1) && (user break)? PC ← DBR PC ← VBR + vector offset PC ← H'A000 0000 Debugging program R15 ← SGR (STC instruction) Exception handling routine Execute RTE instruction PC ← SPC SR ← SSR Exception operation ends Figure 30.2 Flowchart of User Break Debugging Support Function Rev. 1.00 Nov. 22, 2007 Page 1469 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 30.5 (1) User Break Examples Match Conditions are Specified for an Instruction Fetch Cycle • Example 1-1 Register settings: CBR0 = H'00000013 / CRR0 = H'00002003 / CAR0 = H'00000404 / CAMR0 = H'00000000 / CBR1 = H'00000013 / CRR1 = H'00002001 / CAR1 = H'00008010 / CAMR1 = H'00000006 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 = H'00000000 / CBCR = H'00000000 Specified conditions: Independent for channels 0 and 1  Channel 0 Address: H'00000404 / Address mask: H'00000000 Bus cycle: Instruction fetch (after executing the instruction) ASID is not included in the conditions.  Channel 1: Address: H'00008010 / Address mask: H'00000006 Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000 Bus cycle: Instruction fetch (before executing instruction) ASID, data values, and execution count are not included in the conditions. With the above settings, the user break occurs after executing the instruction at address H'00000404 or before executing the instruction at address H'00008010 to H'00008016. • Example 1-2 Register settings: CBR0 = H'40800013 / CRR0 = H'00002000 / CAR0 = H'00037226 / CAMR0 = H'00000000 / CBR1 = H'C0700013 / CRR1 = H'00002001 / CAR1 = H'0003722E / CAMR1 = H'00000000 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 = H'00000000 / CBCR = H'00000000 Specified conditions: Channel 0 → Channel1 sequential mode  Channel 0 Address: H'00037226 / Address mask: H'00000000 / ASID: H'80 Bus cycle: Instruction fetch (before executing the instruction)  Channel 1 Address: H'0003722E / Address mask: H'00000000 / ASID: H'70 Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000 Bus cycle: Instruction fetch (before executing the instruction) Data values and execution count are not included in the conditions. Rev. 1.00 Nov. 22, 2007 Page 1470 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) With the above settings, the user break occurs after executing the instruction at address H'00037226 where ASID is H'80 before executing the instruction at address H'0003722E where ASID is H'70. • Example 1-3 Register settings: CBR0 = H'00000013 / CRR0 = H'00002001 / CAR0 = H'00027128 / CAMR0 = H'00000000 / CBR1 = H'00000013 / CRR1 = H'00002001 / CAR1 = H'00031415 / CAMR1 = H'00000000 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 = H'00000000 / CBCR = H'00000000 Specified conditions: Independent for channels 0 and 1  Channel 0 Address: H'00027128 / Address mask: H'00000000 Bus cycle: Instruction fetch (before executing the instruction) ASID is not included in the conditions.  Channel 1 Address: H'00031415 / Address mask: H'00000000 Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000 Bus cycle: Instruction fetch (before executing the instruction) ASID, data values, and execution count are not included in the conditions. With the above settings, the user break occurs for channel 0 before executing the instruction at address H'00027128. No user break occurs for channel 1 since the instruction fetch is executed only at even addresses. • Example 1-4 Register settings: CBR0 = H'40800013 / CRR0 = H'00002000 / CAR0 = H'00037226 / CAMR0 = H'00000000 / CBR1 = H'C0700013 / CRR1 = H'00002001 / CAR1 = H'0003722E / CAMR1 = H'00000000 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 = H′00000000 / CBCR = H'00000000 Specified conditions: Channel 0 → Channel 1 sequential mode  Channel 0 Address: H'00037226 / Address mask: H'00000000 / ASID: H'80 Bus cycle: Instruction fetch (before executing the instruction)  Channel 1 Address: H'0003722E / Address mask: H'00000000 / ASID: H'70 Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000 Bus cycle: Instruction fetch (before executing the instruction) Data values and execution count are not included in the conditions. Rev. 1.00 Nov. 22, 2007 Page 1471 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) With the above settings, the user break occurs after executing the instruction at address H'00037226 where ASID is H'80 and before executing the instruction at address H'0003722E where ASID is H'70. • Example 1-5 Register settings: CBR0 = H'00000013 / CRR0 = H'00002001 / CAR0 = H'00000500 / CAMR0 = H'00000000 / CBR1 = H'00000813 / CRR1 = H'00002001 / CAR1 = H'00001000 / CAMR1 = H'00000000 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 = H'00000005 / CBCR = H'00000000 Specified conditions: Independent for channels 0 and 1  Channel 0 Address: H'00000500 / Address mask: H'00000000 Bus cycle: Instruction fetch (before executing the instruction) ASID is not included in the conditions.  Channel 1 Address: H'00001000 / Address mask: H'00000000 Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000005 Bus cycle: Instruction fetch (before executing the instruction) Execution count: 5 ASID and data values are not included in the conditions. With the above settings, the user break occurs for channel 0 before executing the instruction at address H'00000500. The user break occurs for channel 1 after executing the instruction at address H'00001000 four times; before executing the instruction five times. • Example 1-6 Register settings: CBR0 = H'40800013 / CRR0 = H'00002003 / CAR0 = H'00008404 / CAMR0 = H'00000FFF / CBR1 = H'40700013 / CRR1 = H'00002001 / CAR1 = H'00008010 / CAMR1 = H'00000006 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 = H'00000000 / CBCR = H'00000000 Specified conditions: Independent for channels 0 and 1  Channel 0 Address: H'00008404 / Address mask: H'00000FFF / ASID: H'80 Bus cycle: Instruction fetch (after executing the instruction)  Channel 1 Address: H'00008010 / Address mask: H'00000006 / ASID: H'70 Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000 Bus cycle: Instruction fetch (before executing the instruction) Rev. 1.00 Nov. 22, 2007 Page 1472 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) Data values and execution count are not included in the conditions. With the above settings, the user break occurs after executing the instruction at address H'00008000 to H'00008FFE where ASID is H'80 or before executing the instruction at address H'00008010 to H'00008016 where ASID is H'70. (2) Match Conditions are Specified for an Operand Access Cycle • Example 2-1 Register settings: CBR0 = H'40800023 / CRR0 = H'00002001 / CAR0 = H'00123456 / CAMR0 = H'00000000 / CBR1 = H'4070A025 / CRR1 = H'00002001 / CAR1 = H'000ABCDE / CAMR1 = H'000000FF / CDR1 = H'0000A512 / CDMR1 = H'00000000 / CETR1 = H'00000000 / CBCR = H'00000000 Specified conditions: Independent for channels 0 and 1  Channel 0 Address: H'00123456 / Address mask: H'00000000 / ASID: H'80 Bus cycle: Operand bus, operand access, and read (operand size is not included in the conditions.)  Channel 1 Address: H'000ABCDE / Address mask: H'000000FF / ASID: H'70 Data: H'0000A512 / Data mask: H'00000000 / Execution count: H'00000000 Bus cycle: Operand bus, operand access, write, and word size Execution count is not included in the conditions. With these settings, the user break occurs for channel 0 for the following accesses: longword read access to address H'000123454, word read access to address H'000123456, byte read access to address H'000123456 where ASID is H'80. The user break occurs for channel 1 when word H'A512 is written to address H'000ABC00 to H'000ABCFE where ASID is H'70. Rev. 1.00 Nov. 22, 2007 Page 1473 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) 30.6 Usage Notes • A desired break may not occur between the time when the instruction for rewriting the UBC register is executed and the time when the written value is actually reflected on the register. After the UBC register is updated, execute one of the following three methods. A. Read the updated UBC register, and execute a branch using the RTE instruction. (It is not necessary that a branch using the RTE instruction is next to a reading UBC register.) B. Execute the ICBI instruction for any address (including non-cacheable area). (It is not necessary that the ICBI instruction is next to a reading UBC register.) C. Set 0(initial value) to IRMCR.R1 before updating the UBC register and update with following sequence. a. Write the UBC register. b. Read the UBC register which is updated at 1. c. Write the value which is read at 2 to the UBC register. Note: When two or more UBC registers are updated, executing these methods at each updating the UBC registers is not necessary. At only last updating the UBC register, execute one of these methods. • The PCB bit of the CRR0 and CRR1 registers is valid only when the instruction fetch is specified as the match condition. • If the sequential break conditions are set, the sequential break conditions are satisfied when the conditions for the first and second channels in the sequence are satisfied in this order. Therefore, if the conditions are set so that the conditions for channels 0 and 1 should be satisfied simultaneously for the same bus cycle, the sequential break conditions will not be satisfied, causing no break. • For the SLEEP instruction, do not allow the post-instruction-execution break where the instruction fetch cycle is the match condition. For the instructions preceding the SLEEP instruction by one to five instructions, do not allow the break where the operand access is the match condition. • If the user break and other exceptions occur for the same instruction, they are determined according to the specified priority. For the priority, refer to section 5, Exception Handling. If the exception having the higher priority occurs, the user break does not occur.  The pre-instruction-execution break is accepted prior to any other exception. Rev. 1.00 Nov. 22, 2007 Page 1474 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC)  If the post-instruction-execution break and data access break have occurred simultaneously with the re-execution type exception (including the pre-instruction-execution break) having a higher priority, only the re-execution type exception is accepted, and no condition match flags are set. When the exception handling has finished thus clearing the exception source, and when the same instruction has been executed again, the break occurs setting the corresponding flag.  If the post-instruction-execution break or operand access break has occurred simultaneously with the completion-type exception (TRAPA) having a higher priority, then no user break occurs; however, the condition match flag is set. • When conditions have been satisfied simultaneously and independently for channels 0 and 1, resulting in identical SPC values for both of the breaks, the user break occurs only once. However, the condition match flags are set for both channels. For example, Instruction at address 110 (post-instruction-execution break for instruction fetch for channel 0) → SPC = 112, CCMFR.MF0 = 1 Instruction at address 112 (pre-instruction-execution break for instruction fetch for channel 1) → SPC = 112, CCMFR.MF1 = 1 • It is not allowed to set the pre-instruction-execution break or the operand break in the delayed slot instruction of the RTE instruction. And if the data value is included in the match conditions of the operand break, do not set the break for the preceding the RTE instruction by one to six instructions. • If the re-execution type exception and the post-instruction-execution break are in conflict for the instruction requiring two or more execution states, then the re-execution type exception occurs. Here, the CCMFR.MF0 (or CCMFR.MF1) bit may or may not be set to 1 when the break conditions have been satisfied. Rev. 1.00 Nov. 22, 2007 Page 1475 of 1692 REJ09B0360-0100 Section 30 User Break Controller (UBC) Rev. 1.00 Nov. 22, 2007 Page 1476 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Section 31 User Debugging Interface (H-UDI) The H-UDI is a serial interface which conforms to the JTAG (IEEE 1149.1: IEEE Standard Test Access Port and Boundary-Scan Architecture) standard. The H-UDI is also used for emulator connection. 31.1 Features The H-UDI is a serial interface which conforms to the JTAG standard. The H-UDI is also used for emulator connection. When using an emulator, H-UDI functions should not be used. Refer to the appropriate emulator users manual for the method of connecting the emulator. The H-UDI has six pins: TCK, TMS, TDI, TDO, TRST, and ASEBRKAK/BRKACK. The pin functions except ASEBRKAK/BRKACK and serial communications protocol conform to the JTAG standard. This LSI has additional six pins for emulator connection: (AUDSYNC, AUDCK, and AUDATA3 to AUDATA0). These six pins for emulator are multiplexed with on-chip modules. And the H-UDI has one chip-mode setting pin: (MPMD). The H-UDI has two TAP controller blocks; one is for the boundary-scan test and another is H-UDI function except the boundary-scan test. The H-UDI initial state is for the boundary scan after power-on or TRST asserted. It is necessary to set H-UDI switchover command to use the H-UDI function. And the CPU cannot access the boundary scan TAP controller. Figure 31.1 shows a block diagram of the H-UDI. The H-UDI has the TAP (Test Access Port) controller and four registers (SDBPR, SDBSR, SDIR, and SDINT). SDBPR supports the JTAG bypass mode, SDBSR supports the JTAG boundary scan mode, SDIR is used for commands, and SDINT is used for H-UDI interrupts. SDIR is directly accessed from the TDI and TDO pins. The TAP controller, control registers and boundary scan TAP controller are initialized by driving the TRST pin low or by applying the TCK signal for five or more clock cycles with the TMS pin set to 1. This initialization sequence is independent of the reset pin for this LSI. Other circuits are initialized by a normal reset. Rev. 1.00 Nov. 22, 2007 Page 1477 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Interrupt/reset etc ASEBRKAK/BRKACK Break controller Boundary-scan TAP controller SDBSR SDBPR TCK TMS TRST Pin multiplexer TAP controller Decoder TDI SDIR TDO SDINT [Legend] SDBPR: SDBSR: SDINT: SDIR: Bypass register Boundary scan register Interrupt source register Instruction register Figure 31.1 H-UDI Block Diagram Rev. 1.00 Nov. 22, 2007 Page 1478 of 1692 REJ09B0360-0100 Peripheral bus Shift register Section 31 User Debugging Interface (H-UDI) 31.2 Input/Output Pins Table 31.1 shows the pin configuration for the H-UDI. Table 31.1 Pin Configuration Pin Name TCK Function Clock I/O Input Description Functions as the serial clock input pin stipulated in the JTAG standard. Data input to the H-UDI via the TDI pin or data Output via the TDO pin is performed in synchronization with this signal. Mode Select Input Changing this signal in synchronization with the TCK signal determines the significance of data input via the TDI pin. Its protocol conforms to the JTAG standard (IEEE standard 1149.1). When Not in Use Open*1 TMS Mode Input Open*1 TRST*2 Reset Input H-UDI Reset Input This signal is received asynchronously with a TCK signal. Asserting this signal resets the JTAG interface circuit. When a power is supplied, the TRST pin should be asserted for a given period regardless of whether or not the JTAG function is used, which differs from the JTAG standard. Fixed to ground or connected to the PRESET pin*3 TDI Data input Input Data Input Data is sent to the H-UDI by changing this signal in synchronization with the TCK signal. Open*1 TDO Data output Output Data Output Data is read from the H-UDI in synchronization with the TCK signal. Open ASEBRKAK/ BRKACK Emulator I/O Pins for an emulator Open*1 Open AUDSYNC, Emulator AUDCK, AUDATA3 to AUDATA0 MPMD Chip-mode Output Pins for an emulator Input Selects the operation mode of this LSI, whether emulation support mode (Low level) or LSI operation mode (High level). Open Notes: 1. This pin is pulled up in this LSI. When using interrupts or resets via the H-UDI or emulator, the use of external pull-up resistors will not cause any problem. 2. When using interrupts or resets via the H-UDI or emulator, the TRST pin should be designed so that it can be controlled independently and can be controlled to retain low level while the PRESET pin is asserted at a power-on reset. Rev. 1.00 Nov. 22, 2007 Page 1479 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) 3. This pin should be connected to ground, the PRESET, or another pin which operates in the same manner as the PRESET pin. However, when connected to a ground pin, the following problem occurs. Since the TRST pin is pulled up within this LSI, a weak current flows when the pin is externally connected to ground pin. The value of the current is determined by a resistance of the pull-up MOS for the port pin. Although this current does not affect the operation of this LSI, it consumes unnecessary power. The TCK clock or the CPG of this LSI should be set to ensure that the frequency of the TCK clock is less than the peripheral-clock frequency of this LSI. 31.3 Boundary Scan TAP Controllers (IDCODE, EXTEST, SAMPLE/PRELOAD, BYPASS, CLAMP and HIGHZ) The H-UDI contains two separate TAP controllers: one for controlling the boundary-scan function and another for controlling the H-UDI reset and interrupt functions. Assertion of TRST, for example at power-on reset, activates the boundary-scan TAP controller and enables the boundaryscan function prescribed in the JTAG standards. Executing a switchover command to the H-UDI allows usage of the H-UDI reset and H-UDI interrupts. This LSI, however, has the following limitations: • Clock-related pins (EXTAL and XTAL) are out of the scope of the boundary-scan test. • Reset-related pin (PRESET) is out of the scope of the boundary-scan test. • H-UDI-related pins (TCK, TDI, TDO, TMS, TRST and MPMD) are out of the scope of the boundary-scan test. • USB-related pins (DM, DP, VBUS, and REFRIN) are out of the scope of the boundary-scan test • During the boundary scan (IDCODE, EXTEST, SAMPLE/PRELOAD, BYPASS, CLAMP, HIGHZ, and H-UDI switchover command), the maximum TCK signal frequency is 2 MHz. • The external controller has 4-bit access to the boundary-scan TAP controller via the H-UDI. Note: During the boundary scan, the PRESET pin should be fixed high-level. Table 31.2 shows the commands supported by the boundary-scan TAP controller. Rev. 1.00 Nov. 22, 2007 Page 1480 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Table 31.2 Commands Supported by Boundary-Scan TAP Controller Bit 3 1 0 0 0 0 0 0 Bit 2 1 0 0 1 1 1 0 Bit 1 1 0 0 0 1 1 1 Bit 0 1 0 1 0 0 1 1 Description BYPASS EXTEST SAMPLE/PRELOAD IDCODE CLAMP HIGHZ H-UDI (select command) Setting prohibited Other than above TRST is asserted H-UDI select command is input to boundary-scan TAP controller H-UDI is used TRST is asserted TCK External pins TMS TRST TDI H-UDI select command (B'0011) (when Shift-IR state > 4 cycles, input of last 4 cycles is valid) 1 1 0 0 Boundary-scan TAP controller Capture-IR Test-Logic -Reset Update-IR Select-DR Test-Logic -Reset Test-Logic -Reset Run-Test -Idle Select-IR Status Shift-IR Run-Test-Idle Switchover is determined at falling of first tck cycle after the boundary-scan TAP controller has entered the Run-Test/Idle state H-UDI selection Capture-IR Select-DR Test-Logic -Reset Select-IR Status Run-Test-Idle Shift-IR --- Figure 31.2 Sequence for switching from Boundary-Scan TAP Controller to H-UDI Rev. 1.00 Nov. 22, 2007 Page 1481 of 1692 REJ09B0360-0100 Run-Test -Idle H-UDI Run-Test -Idle Exit1-IR Section 31 User Debugging Interface (H-UDI) 31.4 Register Descriptions The H-UDI has the following registers. Table 31.3 Register Configuration (1) CPU Side Register Name Abbrev. R/W Area P4 1 Address* Area 7 Address* 1 Size Initial 2 Value* Instruction register Interrupt source register Boundary scan register Bypass register SDIR SDINT SDBSR SDBPR R R/W   H'FC11 0000 H'FC11 0018   H'1C11 0000 H'1C11 0018   16 16   H'0EFF H'0000   Notes: 1. The area P4 address is an address when accessing through area P4 in a virtual address space. The area 7 address is an address when accessing through area 7 in a physical space using the TLB. 2. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller initializes to these values. Table 31.4 Register Configuration (2) H-UDI Side Register Name Abbrev. R/W Size Initial Value* 1 Instruction register Interrupt source register Boundary scan register Bypass register Note: SDIR SDINT SDBSR SDBPR R/W W*  R/W 3 32 32  1 H'FFFF FFFD (fixed value*2) H'0000 0000  Undefined 1. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller initializes to these values. 2. When reading via the H-UDI, the value is always H'FFFF FFFD. 3. Only 1 can be written to the LSB by the H-UDI interrupt command. Table 31.5 Register Status in Each Processing State Register Name Abbrev. Power-On Reset Sleep Standby Instruction register SDIR H'0EFF H'0000 Retained Retained Retained Retained Interrupt source register SDINT Rev. 1.00 Nov. 22, 2007 Page 1482 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) 31.4.1 Instruction Register (SDIR) SDIR is a 16-bit read-only register that can be read from the CPU. Commands are set via the serial input (TDI). SDIR is initialized by TRST or in the Test-Logic-Reset state and can be written by the H-UDI irrespective of the CPU mode. Operation is not guaranteed when a reserved command is set to this register. Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 TI 0 R 1 R 1 R 1 R 0 R 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 R 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 to 8 Bit Name TI Initial Value R/W 0000 1110 R Description Test Instruction Bits 7 to 0 0110 xxxx : 0111 xxxx : 101x xxxx : 0000 1110: H-UDI reset negate H-UDI reset assert H-UDI interrupt Initial state Other than above: Setting prohibited Note: Though H-UDI reset asserted, CPG and WDT registers are not initialized. 7 to 0  All 1 R Reserved These bits are always read as 1. Rev. 1.00 Nov. 22, 2007 Page 1483 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) 31.4.2 Interrupt Source Register (SDINT) SDINT is a 16-bit register that can be read from or written to by the CPU. Specifying an H-UDI interrupt command in SDIR via H-UDI pin (Update-IR) sets the INTREQ bit to 1. While an HUDI interrupt command is set in SDIR, SDINT which is connected between the TDI and TDO pins can be read as a 32-bit register. In this case, the upper 16 bits will be 0 and the lower 16 bits represent the SDINT value. Only 0 can be written to the INTREQ bit by the CPU. While this bit is set to 1, an interrupt request will continue to be generated. This bit, therefore, should be cleared by the interrupt handling routine. It is initialized by TRST or in the Test-Logic-Reset state. Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 INTREQ 0 R/W Bit 15 to 1 Bit Name  Initial Value All 0 R/W R Description Reserved For reading from or writing to this bit, see General Precautions on Handling of Product. Interrupt Request Indicates whether or not an interrupt by an H-UDI interrupt command has occurred. Clearing this bit to 0 by the CPU cancels an interrupt request. When writing 1 to this bit, the previous value is maintained. 0 INTREQ 0 R/W Rev. 1.00 Nov. 22, 2007 Page 1484 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) 31.4.3 Bypass Register (SDBPR) SDBPR is a one-bit register that supports the J-TAG bypass mode. When the BYPASS command is set to the boundary scan TAP controller, the TDI and TDO are connected by way of SDBPR. This register cannot be accessed from the CPU regardless of the LSI mode. Though this register is not initialized by a power-on reset and the TRST pin asserted, initialized to 0 in the Capture-DR state. 31.4.4 Boundary Scan Register (SDBSR) SDBSR is a shift register, located on the PAD, for controlling the input/Output pins, which supports the boundary scan mode of the JTAG standard. Using the EXTEST and SAMPLE/PRELOAD commands, a boundary-scan test complying with the JTAG standards (IEEE1149.1) can be carried out. This register cannot be accessed from the CPU regardless of the LSI mode. This register is not initialized by a power-on reset and the TRST pin asserted. Rev. 1.00 Nov. 22, 2007 Page 1485 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Table 31.6 SDBSR Configuration Number Pin Name From TDI 603 602 601 600 599 598 597 596 595 594 593 592 591 590 589 588 587 586 585 584 583 582 581 580 579 578 577 576 575 SCK0/AUDSYNC/FCLE SCK0/AUDSYNC/FCLE SCK0/AUDSYNC/FCLE LCD_VEP_WC/DR5/PH0 LCD_VEP_WC/DR5/PH0 LCD_VEP_WC/DR5/PH0 LCD_FLM/VSYNC SPS EX_VSYNC/BT_VSYNC LCD_FLM/VSYNC SPS EX_VSYNC/BT_VSYNC LCD_FLM/VSYNC SPS EX_VSYNC/BT_VSYNC LCD_CL1/HSYNC SPL EX_HSYNC/BT_HSYNC LCD_CL1/HSYNC SPL EX_HSYNC/BT_HSYNC LCD_CL1/HSYNC SPL EX_HSYNC/BT_HSYNC LCD_M_DISP/DE_C DE_H/BT_DE_C LCD_M_DISP/DE_C DE_H/BT_DE_C LCD_M_DISP/DE_C DE_H/BT_DE_C LCD_VCP_WC/DR4/PH1 LCD_VCP_WC/DR4/PH1 LCD_VCP_WC/DR4/PH1 LCD_CLK/DCLKIN LCD_CLK/DCLKIN LCD_CLK/DCLKIN LCD_DATA15/DR3/PG7 LCD_DATA15/DR3/PG7 LCD_DATA15/DR3/PG7 LCD_DATA14/DR2/PG6 LCD_DATA14/DR2/PG6 LCD_DATA14/DR2/PG6 LCD_DATA13/DR1/PG5 LCD_DATA13/DR1/PG5 CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT I/O* Rev. 1.00 Nov. 22, 2007 Page 1486 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 574 573 572 571 570 569 568 567 566 565 564 563 562 561 560 559 558 557 556 555 554 553 552 551 550 549 548 547 546 545 544 Pin Name LCD_DATA13/DR1/PG5 LCD_DATA12/DR0/PG4 LCD_DATA12/DR0/PG4 LCD_DATA12/DR0/PG4 LCD_DATA11/DG5/PG3 LCD_DATA11/DG5/PG3 LCD_DATA11/DG5/PG3 LCD_DATA10/DG4/PG2 LCD_DATA10/DG4/PG2 LCD_DATA10/DG4/PG2 LCD_DATA9/DG3/PG1 LCD_DATA9/DG3/PG1 LCD_DATA9/DG3/PG1 LCD_DATA8/DG2/PG0 LCD_DATA8/DG2/PG0 LCD_DATA8/DG2/PG0 LCD_DATA7/DG1/BT_DATA7/PI4 LCD_DATA7/DG1/BT_DATA7/PI4 LCD_DATA7/DG1/BT_DATA7/PI4 LCD_DATA6/DG0/BT_DATA6/PI3 LCD_DATA6/DG0/BT_DATA6/PI3 LCD_DATA6/DG0/BT_DATA6/PI3 LCD_DATA5/DB5/BT_DATA5/PI2 LCD_DATA5/DB5/BT_DATA5/PI2 LCD_DATA5/DB5/BT_DATA5/PI2 LCD_DATA4/DB4/BT_DATA4/PI1 LCD_DATA4/DB4/BT_DATA4/PI1 LCD_DATA4/DB4/BT_DATA4/PI1 LCD_DATA3/DB3/BT_DATA3 LCD_DATA3/DB3/BT_DATA3 LCD_DATA3/DB3/BT_DATA3 I/O* INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT Rev. 1.00 Nov. 22, 2007 Page 1487 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 543 542 541 540 539 538 537 536 535 534 533 532 531 530 529 528 527 526 525 524 523 522 521 520 519 518 517 516 515 514 513 Pin Name LCD_DATA2/DB2/BT_DATA2 LCD_DATA2/DB2/BT_DATA2 LCD_DATA2/DB2/BT_DATA2 LCD_DATA1/DB1/BT_DATA1 LCD_DATA1/DB1/BT_DATA1 LCD_DATA1/DB1/BT_DATA1 LCD_DATA0/DB0/BT_DATA0 LCD_DATA0/DB0/BT_DATA0 LCD_DATA0/DB0/BT_DATA0 LCD_CL2/DE_V/PH3 LCD_CL2/DE_V/PH3 LCD_CL2/DE_V/PH3 LCD_DON/DCLKOUT/PH2 LCD_DON/DCLKOUT/PH2 LCD_DON/DCLKOUT/PH2 PI0/COM/CDE PI0/COM/CDE PI0/COM/CDE RDY  NMI BACK BACK BACK RD RD RD CS3 CS3 CS3 BREQ I/O* CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT INPUT INTERNAL INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT INPUT Rev. 1.00 Nov. 22, 2007 Page 1488 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 512 511 510 509 508 507 506 505 504 503 502 501 500 499 498 497 496 495 494 493 492 491 490 489 488 487 486 485 484 483 482 481 Pin Name BS BS CS0 CS0 CS0 ASEBRKAK/BRKACK/TCLK/PC1 ASEBRKAK/BRKACK/TCLK/PC1 ASEBRKAK/BRKACK/TCLK/PC1 A25/PB7/DREQ0/RTS0 A25/PB7/DREQ0/RTS0 A25/PB7/DREQ0/RTS0 A24/PB6/DACK0/CTS0 A24/PB6/DACK0/CTS0 A24/PB6/DACK0/CTS0 A17 A17 A17 A23/PB5/DTEND0/RTS1 A23/PB5/DTEND0/RTS1 A23/PB5/DTEND0/RTS1 A21/PB3 A21/PB3 A21/PB3 A20/PB2 A20/PB2 A20/PB2 A22/PB4/CTS1 A22/PB4/CTS1 A22/PB4/CTS1 A19/PB1 A19/PB1 A19/PB1 I/O* CONTROL OUTPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT Rev. 1.00 Nov. 22, 2007 Page 1489 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 480 479 478 477 476 475 474 473 472 471 470 469 468 467 466 465 464 463 462 461 460 459 458 457 456 455 454 453 452 451 450 449 Pin Name A18/PB0 A18/PB0 A18/PB0 D15 D15 D15 D14 D14 D14 D1 D1 D1 D0 D0 D0 D13 D13 D13 D12 D12 D12 D3 D3 D3 D2 D2 D2 D11 D11 D11 D10 D10 I/O* CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT Rev. 1.00 Nov. 22, 2007 Page 1490 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 448 447 446 445 444 443 442 441 440 439 438 437 436 435 434 433 432 431 430 429 428 427 426 425 424 423 422 421 420 419 418 417 Pin Name D10 D5 D5 D5 D4 D4 D4 D9 D9 D9 D6 D6 D6 D7 D7 D7 D8 D8 D8 DQMLL DQMLL DQMLL DQMUL DQMUL DQMUL DQMUU DQMUU DQMUU D16 D16 D16 DQMLU I/O* INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL Rev. 1.00 Nov. 22, 2007 Page 1491 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 416 415 414 413 412 411 410 409 408 407 406 405 404 403 402 401 400 399 398 397 396 395 394 393 392 391 390 389 388 387 386 385 Pin Name DQMLU DQMLU D17 D17 D17 D18 D18 D18 D19 D19 D19 D31 D31 D31 D30 D30 D30 D20 D20 D20 D21 D21 D21 D22 D22 D22 D28 D28 D28 D29 D29 D29 I/O* OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT Rev. 1.00 Nov. 22, 2007 Page 1492 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 384 383 382 381 380 379 378 377 376 375 374 373 372 371 370 369 368 367 366 365 364 363 362 361 360 359 358 357 356 355 354 Pin Name A15 A15 A15 D23 D23 D23 D26 D26 D26 A13 A13 A16 A16 A16 D27 D27 D27 D24 D24 D24 A10 A10 A14 A14 D25 D25 D25 A4 A4 A11 A11 I/O* CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT INPUT CONTROL OUTPUT CONTROL OUTPUT Rev. 1.00 Nov. 22, 2007 Page 1493 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 353 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 Pin Name A5 A5 R/W R/W A8 A8 A12 A12 CKE CKE RAS RAS CLKOUT CLKOUT A9 A9 A6 A6 A7 A7 CAS CAS CS1 CS1 CS1 CS2 CS2 CS2 A0 A0 D47/IDECS0 D47/IDECS0 I/O* CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT CONTROL OUTPUT Rev. 1.00 Nov. 22, 2007 Page 1494 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 Pin Name D47/IDECS0 A3 A3 A1 A1 D45/IODACK D45/IODACK D45/IODACK D46/IDECS1 D46/IDECS1 D46/IDECS1 D33/PF6 D33/PF6 D33/PF6 A2 A2 D44/IDEINT D44/IDEINT D44/IDEINT D43/IDEIORDY D43/IDEIORDY D43/IDEIORDY D42/IDEIORD D42/IDEIORD D42/IDEIORD D32/PF7 D32/PF7 D32/PF7 D40/IDEIOWR D40/IDEIOWR D40/IDEIOWR D41/IODREQ I/O* INPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL Rev. 1.00 Nov. 22, 2007 Page 1495 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 Pin Name D41/IODREQ D41/IODREQ D35/IDEA0 D35/IDEA0 D35/IDEA0 D37/IDEA1 D37/IDEA1 D37/IDEA1 D39/IDED14 D39/IDED14 D39/IDED14 D34/PF5 D34/PF5 D34/PF5 D36/IDEA2 D36/IDEA2 D36/IDEA2 D63/IDED1 D63/IDED1 D63/IDED1 D38/IDED15 D38/IDED15 D38/IDED15 D62/IDED0 D62/IDED0 D62/IDED0 WE2/DQM64UL WE2/DQM64UL WE0/DQM64LL WE0/DQM64LL D60/IDED2 D60/IDED2 I/O* OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT Rev. 1.00 Nov. 22, 2007 Page 1496 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 Pin Name D60/IDED2 WE3/DQM64UU WE3/DQM64UU WE1/DQM64LU WE1/DQM64LU D61/IDED3 D61/IDED3 D61/IDED3 D48/IDED13 D48/IDED13 D48/IDED13 D59/IDED5 D59/IDED5 D59/IDED5 D58/IDED4 D58/IDED4 D58/IDED4 D49/IDED12 D49/IDED12 D49/IDED12 D51/IDED10 D51/IDED10 D51/IDED10 D50/IDED11 D50/IDED11 D50/IDED11 D56/IDED6 D56/IDED6 D56/IDED6 D52/IDED9 D52/IDED9 D52/IDED9 I/O* INPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT Rev. 1.00 Nov. 22, 2007 Page 1497 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 Pin Name D53/IDED8 D53/IDED8 D53/IDED8 D57/IDED7 D57/IDED7 D57/IDED7 D54/IDERST D54/IDERST D54/IDERST D55/DIRECTION D55/DIRECTION D55/DIRECTION WOL/PF2/IDEA0_M WOL/PF2/IDEA0_M WOL/PF2/IDEA0_M SSISCK2/PC3 SSISCK2/PC3 SSISCK2/PC3 SSIDATA2/PC2 SSIDATA2/PC2 SSIDATA2/PC2 SSIWS2/PC4 SSIWS2/PC4 SSIWS2/PC4 LNKSTA/PF3/IDECS0_M LNKSTA/PF3/IDECS0_M LNKSTA/PF3/IDECS0_M EXOUT/PF4/IDECS1_M EXOUT/PF4/IDECS1_M EXOUT/PF4/IDECS1_M AUDIO_CLK2/PC5 AUDIO_CLK2/PC5 I/O* CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT Rev. 1.00 Nov. 22, 2007 Page 1498 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 Pin Name AUDIO_CLK2/PC5 CRS/PD7/IDEA1_M CRS/PD7/IDEA1_M CRS/PD7/IDEA1_M COL/PE7/IDEA2_M COL/PE7/IDEA2_M COL/PE7/IDEA2_M TX_ER/PD6/IDEIOWR_M TX_ER/PD6/IDEIOWR_M TX_ER/PD6/IDEIOWR_M MII_TXD3/SSIDATA5/IODACK_M/PD0 MII_TXD3/SSIDATA5/IODACK_M/PD0 MII_TXD3/SSIDATA5/IODACK_M/PD0 MII_TXD2/AUDIO_CLK5/IDEINT_M/PD1 MII_TXD2/AUDIO_CLK5/IDEINT_M/PD1 MII_TXD2/AUDIO_CLK5/IDEINT_M/PD1 RX_ER/PE6/IODREQ_M RX_ER/PE6/IODREQ_M RX_ER/PE6/IODREQ_M MII_TXD1/SSIWS5/IDEIORD_M/PD2 MII_TXD1/SSIWS5/IDEIORD_M/PD2 MII_TXD1/SSIWS5/IDEIORD_M/PD2 SSIDATA3/PH4 SSIDATA3/PH4 SSIDATA3/PH4 MII_TXD0/SSISCK5/IDEIORDY_M/PD3 MII_TXD0/SSISCK5/IDEIORDY_M/PD3 MII_TXD0/SSISCK5/IDEIORDY_M/PD3 TX_EN/PD4/IDED0_M TX_EN/PD4/IDED0_M TX_EN/PD4/IDED0_M SSIWS3/PH6 I/O* INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL Rev. 1.00 Nov. 22, 2007 Page 1499 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 Pin Name SSIWS3/PH6 SSIWS3/PH6 TX_CLK/PD5/IDED15_M TX_CLK/PD5/IDED15_M TX_CLK/PD5/IDED15_M RX_CLK/PE5/IDED1_M RX_CLK/PE5/IDED1_M RX_CLK/PE5/IDED1_M RX_DV/PE4/IDED14_M RX_DV/PE4/IDED14_M RX_DV/PE4/IDED14_M SSISCK3/PH5 SSISCK3/PH5 SSISCK3/PH5 IRQ0/DTEND1 IRQ0/DTEND1 IRQ0/DTEND1 MII_RXD0/SSIWS4/IDED2_M/PE3 MII_RXD0/SSIWS4/IDED2_M/PE3 MII_RXD0/SSIWS4/IDED2_M/PE3 MII_RXD1/SSISCK4/IDED13_M/PE2 MII_RXD1/SSISCK4/IDED13_M/PE2 MII_RXD1/SSISCK4/IDED13_M/PE2 AUDIO_CLK3/PH7 AUDIO_CLK3/PH7 AUDIO_CLK3/PH7 MII_RXD2/SSIDATA4/IDED3_M/PE1 MII_RXD2/SSIDATA4/IDED3_M/PE1 MII_RXD2/SSIDATA4/IDED3_M/PE1 IRQOUT/DREQ1 IRQOUT/DREQ1 IRQOUT/DREQ1 I/O* OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT Rev. 1.00 Nov. 22, 2007 Page 1500 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 Pin Name MII_RXD3/AUDIO_CLK4/IDED12_M/PE0 MII_RXD3/AUDIO_CLK4/IDED12_M/PE0 MII_RXD3/AUDIO_CLK4/IDED12_M/PE0 MDC/PF0/IDED4_M MDC/PF0/IDED4_M MDC/PF0/IDED4_M MDIO/PF1/IDED11_M MDIO/PF1/IDED11_M MDIO/PF1/IDED11_M AUDIO_CLK0/PC7 AUDIO_CLK0/PC7 AUDIO_CLK0/PC7 SSIWS0 SSIWS0 SSIWS0 STATUS1/RTS2/PA7 STATUS1/RTS2/PA7 STATUS1/RTS2/PA7 SSISCK0 SSISCK0 SSISCK0 AUDIO_CLK1/PC6 AUDIO_CLK1/PC6 AUDIO_CLK1/PC6 STATUS0/CTS2/PA6 STATUS0/CTS2/PA6 STATUS0/CTS2/PA6 SSIDATA0 SSIDATA0 SSIDATA0 SSISCK1 SSISCK1 I/O* CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT Rev. 1.00 Nov. 22, 2007 Page 1501 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 Pin Name SSISCK1 PJ7/IDED10_M PJ7/IDED10_M PJ7/IDED10_M SSIWS1 SSIWS1 SSIWS1 PJ6/IDED5_M PJ6/IDED5_M PJ6/IDED5_M FRE/PA4 FRE/PA4 FRE/PA4 SSIDATA1 SSIDATA1 SSIDATA1 PJ5/IDED9_M PJ5/IDED9_M PJ5/IDED9_M PJ4/IDED6_M PJ4/IDED6_M PJ4/IDED6_M PJ2/IDED8_M PJ2/IDED8_M PJ2/IDED8_M PJ3/IDED7_M PJ3/IDED7_M PJ3/IDED7_M FEW/PA3 FEW/PA3 FEW/PA3 FCE/PA5 I/O* INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL Rev. 1.00 Nov. 22, 2007 Page 1502 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 Pin Name FCE/PA5 FCE/PA5 PJ1/IDERST_M PJ1/IDERST_M PJ1/IDERST_M PJ0/DIRECTION_M PJ0/DIRECTION_M PJ0/DIRECTION_M MODE7/FD6 MODE7/FD6 MODE7/FD6 FALE/PC0 FALE/PC0 FALE/PC0 MODE3/FD3 MODE3/FD3 MODE3/FD3 MODE5/FD5 MODE5/FD5 MODE5/FD5 TXD2/PA2 TXD2/PA2 TXD2/PA2 MODE2/FD2 MODE2/FD2 MODE2/FD2 MODE4/FD4 MODE4/FD4 MODE4/FD4 MODE8/FD7 MODE8/FD7 I/O* OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT Rev. 1.00 Nov. 22, 2007 Page 1503 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Pin Name MODE8/FD7 MODE1/FD1 MODE1/FD1 MODE1/FD1 RXD2/PA1 RXD2/PA1 RXD2/PA1 SCK2/PA0 SCK2/PA0 SCK2/PA0 SCL SCL SDA SDA RXD1/AUDATA2 RXD1/AUDATA2 RXD1/AUDATA2 WDTOVF/IRQ1/AUDCK/DACK1 WDTOVF/IRQ1/AUDCK/DACK1 WDTOVF/IRQ1/AUDCK/DACK1 MODE0/FD0 MODE0/FD0 MODE0/FD0 RXD0/AUDATA0 RXD0/AUDATA0 RXD0/AUDATA0 TXD1/AUDATA3 TXD1/AUDATA3 TXD1/AUDATA3 TXD0/AUDATA1 TXD0/AUDATA1 TXD0/AUDATA1 I/O* INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT CONTROL OUTPUT INPUT Rev. 1.00 Nov. 22, 2007 Page 1504 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Number 2 1 0 Pin Name SCK1/FR/B SCK1/FR/B SCK1/FR/B To TDO I/O* CONTROL OUTPUT INPUT Rev. 1.00 Nov. 22, 2007 Page 1505 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) 31.5 31.5.1 Operation TAP Control Figure 31.3 shows the internal states of the TAP controller. The state transitions basically conform to the JTAG standard. • State transitions occur according to the TMS value at the rising edge of the TCK signal. • The TDI value is sampled at the rising edge of the TCK signal and shifted at the falling edge of the TCK signal. • The TDO value is changed at the falling edge of the TCK signal. The TDO signal is in a Hi-Z state other than in the Shift-DR or Shift-IR state. • A transition to the Test-Logic-Reset by clearing TRST to 0 is performed asynchronously with the TCK signal. 1 Test -Logic-Reset 0 1 1 Select-DR-Scan 0 0 1 Capture-DR 0 Shift-DR 1 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 Exit2-IR 1 Update-IR 1 0 Exit1-IR 0 Pause-IR 1 0 0 1 Capture-IR 0 Shift-IR 1 1 0 Select-IR-Scan 1 0 Run-Test/Idle Figure 31.3 TAP Controller State Transitions Rev. 1.00 Nov. 22, 2007 Page 1506 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) 31.5.2 H-UDI Reset A power-on reset is generated by the SDIR command. After the H-UDI reset assert command has been sent from the H-UDI pin, sending the H-UDI reset negate command resets the CPU (see Figure 31.4). The required time between the H-UDI reset assert and H-UDI reset negate commands is the same as the time for holding the reset pin low in order to reset this LSI by a power-on reset. H-UDI pin H-UDI reset assert H-UDI reset negate Chip internal reset CPU state Normal Reset Reset handling Figure 31.4 H-UDI Reset 31.5.3 H-UDI Interrupt The H-UDI interrupt function generates an interrupt by setting the appropriate command in SDIR from the H-UDI. An H-UDI interrupt request signal is asserted when the INTREQ bit in SDINT is set to 1 by setting the appropriate command. Since the interrupt request signal is not negated until the INTREQ bit is cleared to 0 by software, it is not possible to lose the interrupt request. While an H-UDI interrupt command is set in SDIR, SDINT is connected between the TDI and TDO pins. 31.6 Usage Notes Once an SDIR command is set, it will be changed only by an assertion of the TRST signal, making the TAP controller Test-Logic-Reset state, or writing other commands from the H-UDI. The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when using an emulator. Rev. 1.00 Nov. 22, 2007 Page 1507 of 1692 REJ09B0360-0100 Section 31 User Debugging Interface (H-UDI) Rev. 1.00 Nov. 22, 2007 Page 1508 of 1692 REJ09B0360-0100 Section 32 List of Registers Section 32 32.1 Register Addresses List of Registers • The on-chip I/O registers of this LSI are described by functional module, in order of the corresponding section numbers. • Access to reserved addresses which are not described in this list is disabled. Operation or continued operation is not guaranteed when these registers are accessed. • When registers consist of 16 or 32 bits, the addresses of the MSBs are given, on the presumption of a big-endian system. • Entries under Access size indicates numbers of bits. • For details on each register, refer to the description of the register in the corresponding section. Rev. 1.00 Nov. 22, 2007 Page 1509 of 1692 REJ09B0360-0100 Section 32 List of Registers Table 32.1 Register Configuration Module Exception handling Register Name TRAPA exception register Abbreviation R/W TRA R/W P4 Area Address* H'FF00 0020 Area 7 Address* H'1F00 0020 Access Size Remarks 32 Exception event register EXPEVT Interrupt event register Non-support detection exception register MMU Page table entry high register Page table entry low register Translation table base register TLB exception address register MMU control register Page table entry assistance register Physical address space control register Instruction re-fetch inhibit control register Cache Cache control register Queue address control register 0 Queue address control register 1 On-chip memory control RAMCR register On-chip memory On-chip memory control RAMCR register QACR1 CCR QACR0 IRMCR PASCR MMUCR PTEA TEA TTB PTEL PTEH INTEVT EXPMASK R/W R/W R/W H'FF00 0024 H'FF00 0028 H'FF2F 0004 H'1F00 0024 H'1F00 0028 H'1F2F 0004 32 32 32 R/W H'FF00 0000 H'1F00 0000 32 R/W H'FF00 0004 H'1F00 0004 32 R/W H'FF00 0008 H'1F00 0008 32 R/W H'FF00 000C H'1F00 000C 32 R/W R/W H'FF00 0010 H'FF00 0034 H'1F00 0010 H'1F00 0034 32 32 R/W H'FF00 0070 H'1F00 0070 32 R/W H'FF00 0078 H'1F00 0078 32 R/W R/W H'FF00 001C H'FF00 0038 H'1F00 001C H'1F00 0038 32 32 R/W H'FF00 003C H'1F00 003C 32 R/W H'FF00 0074 H'1F00 0074 32 R/W H'FF00 0074* H'1F00 0074* 32 Rev. 1.00 Nov. 22, 2007 Page 1510 of 1692 REJ09B0360-0100 Section 32 List of Registers Module CPG Register Name Frequency control register PLL control register VDC2 clock control register Abbreviation R/W FRQCR R P4 Area Address* H'FFC8 0000 Area 7 Address* H'1FC8 0000 Access Size Remarks 32 PLLCR VDC2CLKCR R/W R/W H'FFC8 0024 H'FFC8 0004 H'1FC8 0024 H'1FC8 0004 32 32 WDT Watchdog timer stop time register Watchdog timer control/status register Watchdog timer base stop time register WDTST R/W H'FFCC 0000 H'1FCC 0000 32 WDTCSR R/W H'FFCC 0004 H'1FCC 0004 32 WDTBST R/W H'FFCC 0008 H'1FCC 0008 32 Watchdog timer counter WDTCNT Watchdog timer base counter DMAC DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0 DMA source address register 1 DMA destination address register 1 DMA transfer count register 1 DMA channel control register 1 DMA source address register 2 DMA destination address register 2 DMA transfer count register 2 TCR2 DAR2 SAR2 CHCR1 TCR1 DAR1 SAR1 CHCR0 TCR0 DAR0 SAR0 WDTBCNT R R H'FFCC 0010 H'FFCC 0018 H'1FCC 0010 H'1FCC 0018 32 32 R/W H'FF60 8020 H'1F60 8020 32*3 R/W H'FF60 8024 H'1F60 8024 32*3 R/W H'FF60 8028 H'1F60 8028 32*3 R/W*1 H'FF60 802C H'1F60 802C 32*3 R/W H'FF60 8030 H'1F60 8030 32*3 R/W H'FF60 8034 H'1F60 8034 32*3 R/W H'FF60 8038 H'1F60 8038 32*3 R/W*1 H'FF60 803C H'1F60 803C 32*3 R/W H'FF60 8040 H'1F60 8040 32*3 R/W H'FF60 8044 H'1F60 8044 32*3 R/W H'FF60 8048 H'1F60 8048 32*3 Rev. 1.00 Nov. 22, 2007 Page 1511 of 1692 REJ09B0360-0100 Section 32 List of Registers Module DMAC Register Name DMA channel control register 2 DMA source address register 3 DMA destination address register 3 DMA transfer count register 3 DMA channel control register 3 DMA operation register 0 DMA source address register 4 DMA destination address register 4 DMA transfer count register 4 DMA channel control register 4 DMA source address register 5 DMA destination address register 5 DMA transfer count register 5 DMA channel control register 5 DMA source address register B0 DMA destination address register B0 DMA transfer count register B0 DMA source address register B1 Abbreviation R/W CHCR2 P4 Area Address* Area 7 Address* H'1F60 804C Access Size Remarks 32*3 R/W*1 H'FF60 804C SAR3 R/W H'FF60 8050 H'1F60 8050 32*3 DAR3 R/W H'FF60 8054 H'1F60 8054 32*3 TCR3 R/W H'FF60 8058 H'1F60 8058 32*3 CHCR3 R/W*1 H'FF60 805C H'1F60 805C 32*3 DMAOR0 R/W*2 H'FF60 8060 H'1F60 8060 16*3 SAR4 R/W H'FF60 8070 H'1F60 8070 32*3 DAR4 R/W H'FF60 8074 H'1F60 8074 32*3 TCR4 R/W H'FF60 8078 H'1F60 8078 32*3 CHCR4 R/W*1 H'FF60 807C H'1F60 807C 32*3 SAR5 R/W H'FF60 8080 H'1F60 8080 32*3 DAR5 R/W H'FF60 8084 H'1F60 8084 32*3 TCR5 R/W H'FF60 8088 H'1F60 8088 32*3 CHCR5 R/W*1 H'FF60 808C H'1F60 808C 32*3 SARB0 R/W H'FF60 8120 H'1F60 8120 32*3 DARB0 R/W H'FF60 8124 H'1F60 8124 32*3 TCRB0 R/W H'FF60 8128 H'1F60 8128 32*3 SARB1 R/W H'FF60 8130 H'1F60 8130 32*3 Rev. 1.00 Nov. 22, 2007 Page 1512 of 1692 REJ09B0360-0100 Section 32 List of Registers Module DMAC Register Name DMA destination address register B1 DMA transfer count register B1 DMA source address register B2 DMA destination address register B2 DMA transfer count register B2 DMA source address register B3 DMA destination address register B3 DMA transfer count register B3 Abbreviation R/W DARB1 R/W P4 Area Address* H'FF60 8134 Area 7 Address* H'1F60 8134 Access Size Remarks 32*3 TCRB1 R/W H'FF60 8138 H'1F60 8138 32*3 SARB2 R/W H'FF60 8140 H'1F60 8140 32*3 DARB2 R/W H'FF60 8144 H'1F60 8144 32*3 TCRB2 R/W H'FF60 8148 H'1F60 8148 32*3 SARB3 R/W H'FF60 8150 H'1F60 8150 32*3 DARB3 R/W H'FF60 8154 H'1F60 8154 32*3 TCRB3 R/W H'FF60 8158 H'1F60 8158 32*3 DMA extended resource DMARS0 selector 0 DMA extended resource DMARS1 selector 1 DMA extended resource DMARS2 selector 2 INTC Interrupt control register ICR0 0 Interrupt control register ICR1 1 Interrupt priority register INTPRI Interrupt source register INTREQ Interrupt mask register Interrupt mask clear register NMI flag control register NMIFCR User interrupt mask level register Interrupt priority register INT2PRI0 0 USERIMASK INTMSK INTMSKCLR R/W H'FF60 9000 H'1F60 9000 16*3 R/W H'FF60 9004 H'1F60 9004 16*3 R/W H'FF60 9008 H'1F60 9008 16*3 R/W H'FFD0 0000 H'1FD0 0000 32 R/W H'FFD0 001C H'1FD0 001C 32 R/W R/W R/W R/W H'FFD0 0010 H'FFD0 0024 H'FFD0 0044 H'FFD0 0064 H'1FD0 0010 H'1FD0 0024 H'1FD0 0044 H'1FD0 0064 32 32 32 32 R/W R/W H'FFD0 00C0 H'FFD3 0000 H'1FD0 00C0 H'1FD3 0000 32 32 R/W H'FFD4 0000 H'1FD4 0000 32 Rev. 1.00 Nov. 22, 2007 Page 1513 of 1692 REJ09B0360-0100 Section 32 List of Registers Module INTC Register Name Abbreviation R/W R/W P4 Area Address* H'FFD4 0004 Area 7 Address* H'1FD4 0004 Access Size Remarks 32 Interrupt priority register INT2PRI1 1 Interrupt priority register INT2PRI2 2 Interrupt priority register INT2PRI3 3 Interrupt priority register INT2PRI4 4 Interrupt priority register INT2PRI5 5 Interrupt priority register INT2PRI6 6 Interrupt priority register INT2PRI7 7 Interrupt priority register 8 Interrupt priority register 9 Interrupt priority register 10 INT2PRI10 INT2PRI9 INT2PRI8 R/W H'FFD4 0008 H'1FD4 0008 32 R/W H'FFD4 000C H'1FD4 000C 32 R/W H'FFD4 0010 H'1FD4 0010 32 R/W H'FFD4 0014 H'1FD4 0014 32 R/W H'FFD4 0018 H'1FD4 0018 32 R/W H'FFD4 001C H'1FD4 001C 32 32 R/W H'FFD4 00A0 H'1FD4 00A0 32 R/W H'FFD4 00A4 H'1FD4 00A4 32 R/W R/W H'FFD4 00A8 H'FFD4 00AC H'1FD4 00A8 H'1FD4 00AC 32 Interrupt priority register INT2PRI11 11 Interrupt priority register 12 INT2PRI12 32 R/W R H'FFD4 00B0 H'FFD4 0030 H'1FD4 00B0 H'1FD4 0030 32 Interrupt source register INT2A0 0 (mask state is not affected) Interrupt source register INT2A01 01 (mask state is not affected) Interrupt source register INT2A1 1 (mask state is affected) R H'FFD4 00C0 H'1FD4 00C0 32 R H'FFD4 0034 H'1FD4 0034 32 Rev. 1.00 Nov. 22, 2007 Page 1514 of 1692 REJ09B0360-0100 Section 32 List of Registers Module INTC Register Name Abbreviation R/W R P4 Area Address* H'FFD4 00C4 Area 7 Address* H'1FD4 00C4 Access Size Remarks 32 Interrupt source register INT2A11 11 (mask state is affected) Interrupt mask register INT2MSKR R/W R/W W H'FFD4 0038 H'FFD4 00D0 H'FFD4 003C H'1FD4 0038 H'1FD4 00D0 H'1FD4 003C 32 32 32 Interrupt mask register 1 INT2MSKR1 Interrupt mask clear register Interrupt mask clear register 1 Individual module interrupt source register 0 Individual module interrupt source register 2 Individual module interrupt source register 3 Individual module interrupt source register 4 Individual module interrupt source register 5 Individual module interrupt source register 6 Individual module interrupt source register 7 GPIO interrupt set register TMU Timer output control register Timer start register 0 Timer constant register 0 TSTR0 TCOR0 TOCR INT2GPIC INT2B7 INT2B6 INT2B5 INT2B4 INT2B3 INT2B2 INT2MSKCR1 INT2B0 INT2MSKCR H'FFD4 00D4 W R H'FFD4 0040 H'1FD4 00D4 32 H'1FD4 0040 32 R H'FFD4 0048 H'1FD4 0048 32 R H'FFD4 004C H'1FD4 004C 32 R H'FFD4 0050 H'1FD4 0050 32 R H'FFD4 0054 H'1FD4 0054 32 R H'FFD4 0058 H'1FD4 0058 32 R H'FFD4 005C H'1FD4 005C 32 R/W H'FFD4 0090 H'1FD4 0090 32 R/W H'FFD8 0000 H'1FD8 0000 8 R/W R/W H'FFD8 0004 H'FFD8 0008 H'1FD8 0004 H'1FD8 0008 8 32 Rev. 1.00 Nov. 22, 2007 Page 1515 of 1692 REJ09B0360-0100 Section 32 List of Registers Module TMU Register Name Timer counter 0 Timer control register 0 Timer constant register 1 Timer counter 1 Timer control register 1 Timer constant register 2 Timer counter 2 Timer control register 2 Input capture register 2 Timer start register 1 Timer constant register 3 Timer counter 3 Timer control register 3 Timer constant register 4 Timer counter 4 Timer control register 4 Timer constant register 5 Timer counter 5 Timer control register 5 Abbreviation R/W TCNT0 TCR0 TCOR1 R/W R/W R/W P4 Area Address* H'FFD8 000C H'FFD8 0010 H'FFD8 0014 Area 7 Address* H'1FD8 000C H'1FD8 0010 H'1FD8 0014 Access Size Remarks 32 16 32 TCNT1 TCR1 TCOR2 R/W R/W R/W H'FFD8 0018 H'FFD8 001C H'FFD8 0020 H'1FD8 0018 H'1FD8 001C H'1FD8 0020 32 16 32 TCNT2 TCR2 TCPR2 TSTR1 TCOR3 R/W R/W R R/W R/W H'FFD8 0024 H'FFD8 0028 H'FFD8 002C H'FFDC 0004 H'FFDC 0008 H'1FD8 0024 H'1FD8 0028 H'1FD8 002C H'1FDC 0004 H'1FDC 0008 32 16 32 8 32 TCNT3 TCR3 TCOR4 R/W R/W R/W H'FFDC 000C H'FFDC 0010 H'FFDC 0014 H'1FDC 000C H'1FDC 0010 H'1FDC 0014 32 16 32 TCNT4 TCR4 TCOR5 R/W R/W R/W H'FFDC 0018 H'FFDC 001C H'FFDC 0020 H'1FDC 0018 H'1FDC 001C H'1FDC 0020 32 16 32 TCNT5 TCR5 SCSMR_0 SCBRR_0 R/W R/W R/W R/W R/W W H'FFDC 0024 H'FFDC 0028 H'FFE00000 H'FFE00004 H'FFE00008 H'FFE0000C H'1FDC 0024 H'1FDC 0028 H'1FE00000 H'1FE00004 H'1FE00008 H'1FE0000C 32 16 16 8 16 8 SCIF Serial mode register_0 Bit rate register_0 Serial control register_0 SCSCR_0 Transmit FIFO data register_0 Serial status register_0 SCFSR_0 SCFTDR_0 R/ (W)*4 H'FFE00010 H'1FE00010 16 Receive FIFO data register_0 SCFRDR_0 R H'FFE00014 H'1FE00014 8 Rev. 1.00 Nov. 22, 2007 Page 1516 of 1692 REJ09B0360-0100 Section 32 List of Registers Module SCIF Register Name FIFO control register_0 FIFO data count register_0 Serial port register_0 Line status register_0 Abbreviation R/W SCFCR_0 SCFDR_0 R/W R P4 Area Address* H'FFE00018 H'FFE0001C Area 7 Address* H'1FE00018 H'1FE0001C Access Size Remarks 16 16 SCSPTR_0 SCLSR_0 R/W R/ (W)*5 H'FFE00020 H'FFE00024 H'1FE00020 H'1FE00024 16 16 Serial extension mode register_0 Serial mode register_1 Bit rate register_1 SCEMR_0 R/W H'FFE00028 H'1FE00028 16 SCSMR_1 SCBRR_1 R/W R/W R/W W H'FFE10000 H'FFE10004 H'FFE10008 H'FFE1000C H'1FE10000 H'1FE10004 H'1FE10008 H'1FE1000C 16 8 16 8 Serial control register_1 SCSCR_1 Transmit FIFO data register_1 Serial status register_1 SCFSR_1 SCFTDR_1 R/ (W)*4 H'FFE10010 H'1FE10010 16 Receive FIFO data register_1 FIFO control register_1 FIFO data count register_1 Serial port register_1 Line status register_1 SCFRDR_1 R H'FFE10014 H'1FE10014 8 SCFCR_1 SCFDR_1 R/W R H'FFE10018 H'FFE1001C H'1FE10018 H'1FE1001C 16 16 SCSPTR_1 SCLSR_1 R/W R/ (W)*5 H'FFE10020 H'FFE10024 H'1FE10020 H'1FE10024 16 16 Serial extension mode register_1 Serial mode register_2 Bit rate register_2 SCEMR_1 R/W H'FFE10028 H'1FE10028 16 SCSMR_2 SCBRR_2 R/W R/W R/W W H'FFE20000 H'FFE20004 H'FFE20008 H'FFE2000C H'1FE20000 H'1FE20004 H'1FE20008 H'1FE2000C 16 8 16 8 Serial control register_2 SCSCR_2 Transmit FIFO data register_2 Serial status register_2 SCFSR_2 SCFTDR_2 R/ (W)*4 H'FFE20010 H'1FE20010 16 Receive FIFO data register_2 SCFRDR_2 R H'FFE20014 H'1FE20014 8 Rev. 1.00 Nov. 22, 2007 Page 1517 of 1692 REJ09B0360-0100 Section 32 List of Registers Module SCIF Register Name FIFO control register_2 FIFO data count register_2 Serial port register_2 Line status register_2 Abbreviation R/W SCFCR_2 SCFDR_2 R/W R P4 Area Address* H'FFE20018 H'FFE2001C Area 7 Address* H'1FE20018 H'1FE2001C Access Size Remarks 16 16 SCSPTR_2 SCLSR_2 R/W R/ (W)*5 H'FFE20020 H'FFE20024 H'1FE20020 H'1FE20024 16 16 Serial extension mode register_2 IIC Slave control register Master control register Slave status register SCEMR_2 R/W H'FFE20028 H'1FE20028 16 ICSCR ICMCR ICSSR R/W R/W R/ (W)*6 H'FFE7 0000 H'FFE7 0004 H'FFE7 0008 H'1FF7 0000 H'1FF7 0004 H'1FF7 0008 8 8 8 Master status register ICMSR R/ (W)*7 H'FFE7 000C H'1FF7 000C 8 Slave interrupt enable register Master interrupt enable register Clock control register Slave address register Master address register Receive data register Transmit data register SSI_DMAC0 DMA mode register 0 RDMA transfer source address register 0 RDMA transfer word count register 0 WDMA transfer destination address register 0 WDMA transfer word count register 0 DMA control register 0 ICSIER R/W H'FFE7 0010 H'1FF7 0010 8 ICMIER R/W H'FFE7 0014 H'1FF7 0014 8 ICCCR ICSAR ICMAR ICRXD ICTXD SSIDMMR0 SSIRDMADR0 R/W R/W R/W R/W R/W R/W R/W H'FFE7 0018 H'FFE7 001C H'FFE7 0020 H'FFE7 0024 H'FFE7 0024 H'FF40 1000 H'FF40 1008 H'1FF7 0018 H'1FF7 001C H'1FF7 0020 H'1FF7 0024 H'1FF7 0024 H'1F40 1000 H'1F40 1008 8 8 8 8 8 32 32 SSIRDMCNTR0 R/W H'FF40 1010 H'1F40 1010 32 SSIWDMADR0 R/W H'FF40 1018 H'1F40 1018 32 SSIWDMCNTR0 R/W H'FF40 1020 H'1F40 1020 32 SSIDMCOR0 R/W H'FF40 1028 H'1F40 1028 32 Rev. 1.00 Nov. 22, 2007 Page 1518 of 1692 REJ09B0360-0100 Section 32 List of Registers Module SSI_DMAC0 Register Name Transmit suspension block counter 0 Transmit suspension transfer data register 0 Block count source register 0 Block counter 0 n-times block transfer interrupt count source register 0 n-times block counter 0 DMA mode register 1 RDMA transfer source address register 1 RDMA transfer word count register 1 WDMA transfer destination address register 1 WDMA transfer word count register 1 DMA control register 1 Transmit suspension block counter 1 Transmit suspension transfer data register 1 Block count source register 1 Block counter 1 n-times block transfer interrupt count source register 1 n-times block counter 1 DMA mode register 2 RDMA transfer source address register 2 Abbreviation R/W SSISTPBLCNT0 P4 Area Address* H'FF40 1030 Area 7 Address* H'1F40 1030 Access Size Remarks 32 R/W SSISTPDR0 R/W H'FF40 1038 H'1F40 1038 32 SSIBLCNTSR0 R/W H'FF40 1040 H'1F40 1040 32 SSIBLCNT0 SSIBLNCNTSR0 R/W R/W H'FF40 1048 H'FF40 1050 H'1F40 1048 H'1F40 1050 32 32 SSIBLNCNT0 SSIDMMR1 SSIRDMADR1 R/W R/W R/W H'FF40 1058 H'FF40 1060 H'FF40 1068 H'1F40 1058 H'1F40 1060 H'1F40 1068 32 32 32 SSIRDMCNTR1 R/W H'FF40 1070 H'1F40 1070 32 SSIWDMADR1 R/W H'FF40 1078 H'1F40 1078 32 SSIWDMCNTR1 R/W H'FF40 1080 H'1F40 1080 32 SSIDMCOR1 SSISTPBLCNT1 R/W R/W H'FF40 1088 H'FF40 1090 H'1F40 1088 H'1F40 1090 32 32 SSISTPDR1 R/W H'FF40 1098 H'1F40 1098 32 SSIBLCNTSR1 R/W H'FF40 10A0 H'1F40 10A0 32 SSIBLCNT1 SSIBLNCNTSR1 R/W R/W H'FF40 10A8 H'FF40 10B0 H'1F40 10A8 H'1F40 10B0 32 32 SSIBLNCNT1 SSIDMMR2 SSIRDMADR2 R/W R/W R/W H'FF40 10B8 H'FF40 10C0 H'FF40 10C8 H'1F40 10B8 H'1F40 10C0 H'1F40 10C8 32 32 32 Rev. 1.00 Nov. 22, 2007 Page 1519 of 1692 REJ09B0360-0100 Section 32 List of Registers Module SSI_DMAC0 Register Name RDMA transfer word count register 2 WDMA transfer destination address register 2 WDMA transfer word count register 2 DMA control register 2 Transmit suspension block counter 2 Transmit suspension transfer data register 2 Block count source register 2 Block counter 2 n-times block transfer interrupt count source register 2 n-times block counter 2 DMA operation register 0 Interrupt status register 0 Abbreviation R/W SSIRDMCNTR2 R/W P4 Area Address* H'FF40 10D0 Area 7 Address* H'1F40 10D0 Access Size Remarks 32 SSIWDMADR2 R/W H'FF40 10D8 H'1F40 10D8 32 SSIWDMCNTR2 R/W H'FF40 10E0 H'1F40 10E0 32 SSIDMCOR2 SSISTPBLCNT2 R/W R/W H'FF40 10E8 H'FF40 10F0 H'1F40 10E8 H'1F40 10F0 32 32 SSISTPDR2 R/W H'FF40 10F8 H'1F40 10F8 32 SSIBLCNTSR2 R/W H'FF40 1100 H'1F40 1100 32 SSIBLCNT2 SSIBLNCNTSR2 R/W R/W H'FF40 1108 H'FF40 1110 H'1F40 1108 H'1F40 1110 32 32 SSIBLNCNT2 SSIDMAOR0 R/W R/W H'FF40 1118 H'FF40 1180 H'1F40 1118 H'1F40 1180 32 32 SSIDMINTSR0 R/W H'FF40 1188 H'1F40 1188 32 Interrupt mask register 0 SSIDMINTMR0 R/W SSI_DMAC1 DMA mode register 3 RDMA transfer source address register 3 RDMA transfer word count register 3 WDMA transfer destination address register 3 WDMA transfer word count register 3 DMA control register 3 SSIDMCOR3 R/W SSIWDMCNTR3 H'FF40 1190 H'FF50 1000 H'FF50 1008 H'1F40 1190 H'1F50 1000 H'1F50 1008 32 32 32 SSIDMMR3 SSIRDMADR3 R/W R/W SSIRDMCNTR3 R/W H'FF50 1010 H'1F50 1010 32 SSIWDMADR3 R/W H'FF50 1008 H'1F50 1018 32 R/W H'FF50 1020 H'1F50 1020 32 H'FF50 1028 H'1F50 1028 32 Rev. 1.00 Nov. 22, 2007 Page 1520 of 1692 REJ09B0360-0100 Section 32 List of Registers Module SSI_DMAC1 Register Name Transmit suspension block counter 3 Transmit suspension transfer data register 3 Block count source register 3 Block counter 3 n-times block transfer interrupt count source register 3 n-times block counter 3 DMA mode register 4 RDMA transfer source address register 4 RDMA transfer word count register 4 WDMA transfer destination address register 4 WDMA transfer word count register 4 DMA control register 4 Transmit suspension block counter 4 Transmit suspension transfer data register 4 Block count source register 4 Block counter 4 n-times block transfer interrupt count source register 4 n-times block counter 4 DMA mode register 5 Abbreviation R/W SSISTPBLCNT3 P4 Area Address* H'FF50 1030 Area 7 Address* H'1F50 1030 Access Size Remarks 32 R/W SSISTPDR3 R/W H'FF50 1038 H'1F50 1038 32 SSIBLCNTSR3 R/W H'FF50 1040 H'1F50 1040 32 SSIBLCNT3 SSIBLNCNTSR3 R/W R/W H'FF50 1048 H'FF50 1050 H'1F50 1048 H'1F50 1050 32 32 SSIBLNCNT3 SSIDMMR4 SSIRDMADR4 R/W R/W R/W H'FF50 1058 H'FF50 1060 H'FF50 1068 H'1F50 1058 H'1F50 1060 H'1F50 1068 32 32 32 SSIRDMCNTR4 R/W H'FF50 1070 H'1F50 1070 32 SSIWDMADR4 R/W H'FF50 1078 H'1F50 1078 32 SSIWDMCNTR4 R/W H'FF50 1080 H'1F50 1080 32 SSIDMCOR4 SSISTPBLCNT4 R/W R/W H'FF50 1088 H'FF50 1090 H'1F50 1088 H'1F50 1090 32 32 SSISTPDR4 R/W H'FF50 1098 H'1F50 1098 32 SSIBLCNTSR4 R/W H'FF50 10A0 H'1F50 10A0 32 SSIBLCNT4 SSIBLNCNTSR4 R/W R/W H'FF50 10A8 H'FF50 10B0 H'1F50 10A8 H'1F50 10B0 32 32 SSIBLNCNT4 SSIDMMR5 R/W R/W H'FF50 10B8 H'FF50 10C0 H'1F50 10B8 H'1F50 10C0 32 32 Rev. 1.00 Nov. 22, 2007 Page 1521 of 1692 REJ09B0360-0100 Section 32 List of Registers Module SSI_DMAC1 Register Name RDMA transfer source address register 5 RDMA transfer word count register 5 WDMA transfer destination address register 5 WDMA transfer word count register 5 DMA control register 5 Transmit suspension block counter 5 Transmit suspension transfer data register 5 Block count source register 5 Block counter 5 n-times block transfer interrupt count source register 5 n-times block counter 5 DMA operation register 1 Interrupt status register 1 Abbreviation R/W SSIRDMADR5 R/W P4 Area Address* H'FF50 10C8 Area 7 Address* H'1F50 10C8 Access Size Remarks 32 SSIRDMCNTR5 R/W H'FF50 10D0 H'1F50 10D0 32 SSIWDMADR5 R/W H'FF50 10D8 H'1F50 10D8 32 SSIWDMCNTR5 R/W H'FF50 10E0 H'1F50 10E0 32 SSIDMCOR5 SSISTPBLCNT5 R/W R/W H'FF50 10E8 H'FF50 10F0 H'1F50 10E8 H'1F50 10F0 32 32 SSISTPDR5 R/W H'FF50 10F8 H'1F50 10F8 32 SSIBLCNTSR5 R/W H'FF50 1100 H'1F50 1100 32 SSIBLCNT5 SSIBLNCNTSR5 R/W R/W H'FF50 1108 H'FF50 1110 H'1F50 1108 H'1F50 1110 32 32 SSIBLNCNT5 SSIDMAOR1 R/W R/W H'FF50 1118 H'FF50 1180 H'1F50 1118 H'1F50 1180 32 32 SSIDMINTSR1 R/W H'FF50 1188 H'1F50 1188 32 Interrupt mask register 1 SSIDMINTMR1 R/W SSI_CH0 to 5 Control register 0 Status register 0 SSICR0 SSISR0 R/W R/W* R/W R R/W R/W* R/W R 8 8 H'FF50 1190 H'FF40 2000 H'FF40 2004 H'FF40 2008 H'FF40 200C H'FF40 3000 H'FF40 3004 H'FF40 3008 H'FF40 300C H'1F50 1190 H'1F40 2000 H'1F40 2004 H'1F40 2008 H'1F40 200C H'1F40 3000 H'1F40 3004 H'1F40 3008 H'1F40 300C 32 32 32 32 32 32 32 32 32 Transmit data register 0 SSITDR0 Receive data register 0 Control register 1 Status register 1 SSIRDR0 SSICR1 SSISR1 Transmit data register 1 SSITDR1 Receive data register 1 SSIRDR1 Rev. 1.00 Nov. 22, 2007 Page 1522 of 1692 REJ09B0360-0100 Section 32 List of Registers Module Register Name Abbreviation R/W SSICR2 SSISR2 R/W R/W* R/W R R/W 8 P4 Area Address* H'FF40 4000 H'FF40 4004 H'FF40 4008 H'FF40 400C H'FF50 2000 Area 7 Address* H'1F40 4000 H'1F40 4004 H'1F40 4008 H'1F40 400C H'1F50 2000 H'1F50 2004 H'1F50 2008 H'1F50 200C H'1F50 3000 H'1F50 3004 H'1F50 3008 H'1F50 300C H'1F50 4000 H'1F50 4004 H'1F50 4008 H'1F50 400C H'1EF0 0100* H'1EF0 0110* H'1EF0 0118* Access Size Remarks 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 SSI_CH0 to 5 Control register 2 Status register 2 Transmit data register 2 SSITDR2 Receive data register 2 Control register 3 Status register 3 SSIRDR2 SSICR3 SSISR3 R/W*8 H'FF50 2004 R/W R R/W R/W* R/W R R/W 8 Transmit data register 3 SSITDR3 Receive data register 3 Control register 4 Status register 4 SSIRDR3 SSICR4 SSISR4 H'FF50 2008 H'FF50 200C H'FF50 3000 H'FF50 3004 H'FF50 3008 H'FF50 300C H'FF50 4000 Transmit data register 4 SSITDR4 Receive data register 4 Control register 5 Status register 5 SSIRDR4 SSICR5 SSISR5 R/W*8 H'FF50 4004 R/W R R/W R/W R/W H'FF50 4008 H'FF50 400C H'FEF0 0100* H'FEF0 0110* H'FEF0 0118* Transmit data register 5 SSITDR5 Receive data register 5 EtherC EtherC mode register EtherC status register EtherC interrupt permission register Receive frame length register PHY interface register MAC address high register MAC address low register PHY status register Transmit retry over counter register Delayed collision detect counter register CDCR PSR TROCR MALR PIR MAHR RFLR SSIRDR5 ECMR ECSR ECSIPR R/W H'FEF0 0108* H'1EF0 0108* 32 R/W R/W H'FEF0 0120* H'FEF0 01C0* H'1EF0 0120* H'1EF0 01C0* 32 32 R/W H'FEF0 01C8* H'1EF0 01C8* 32 R R/W H'FEF0 0128* H'FEF0 01D0* H'1EF0 0128* H'1EF0 01D0* 32 32 R/W H'FEF0 01D4* H'1EF0 01D4* 32 Rev. 1.00 Nov. 22, 2007 Page 1523 of 1692 REJ09B0360-0100 Section 32 List of Registers Module EtherC Register Name Lost carrier counter register Carrier not detect counter register Abbreviation R/W LCCR R/W P4 Area Address* H'FEF0 01D8* Area 7 Address* H'1EF0 01D8* Access Size Remarks 32 CNDCR R/W H'FEF0 01DC* H'1EF0 01DC* 32 CRC error frame receive CEFCR counter register Frame receive error counter register Too-short frame receive TSFRCR counter register Too-long frame receive counter register Residual-bit frame receive counter register Multicast address frame MAFCR receive counter register IPG register IPGR RFCR TLFRCR FRECR R/W H'FEF0 01E4* H'1EF0 01E4* 32 R/W H'FEF0 01E8* H'1EF0 01E8* 32 R/W H'FEF0 01EC* H'1EF0 01EC* 32 R/W H'FEF0 01F0* H'1EF0 01F0* 32 R/W H'FEF0 01F4* H'1EF0 01F4* 32 R/W H'FEF0 01F8* H'1EF0 01F8* 32 R/W R/W H'FEF0 0150* H'FEF0 0154* H'1EF0 0150* H'1EF0 0154* 32 32 Automatic PAUSE frame APR register Manual PAUSE frame register Automatic PAUSE frame TPAUSER retransmit count register Random number generation counter upper limit setting register PAUSE Frame Receive Counter Register PAUSE frame retransmit TPAUSECR counter register Broadcast frame receive BCFRR count setting register RFCF RDMLR MPR R/W H'FEF0 0158* H'1EF0 0158* 32 R/W H'FEF0 0164* H'1EF0 0164* 32 R/W H'FEF0 0140* H'1EF0 0140* 32 R/W H'FEF0 0160* H'1EF0 0160* 32 R/W H'FEF0 0168* H'1EF0 0168* 32 R/W H'FEF0 016C* H'1EF0 016C* 32 Rev. 1.00 Nov. 22, 2007 Page 1524 of 1692 REJ09B0360-0100 Section 32 List of Registers Module E-DMAC Register Name E-DMAC mode register E-DMAC transmit request register E-DMAC receive request register Transmit descriptor list start address register Receive descriptor list start address register EtherC/E-DMAC status register EtherC/E-DMAC status interrupt permission register Transmit/receive status copy enable register Receive missed-frame counter register Abbreviation R/W EDMR EDTRR R/W R/W P4 Area Address* H'FEF0 0000* H'FEF0 0008* Area 7 Address* H'1EF0 0000* H'1EF0 0008* Access Size Remarks 32 32 EDRRR R/W H'FEF0 0010* H'1EF0 0010* 32 TDLAR R/W H'FEF0 0018* H'1EF0 0018* 32 RDLAR R/W H'FEF0 0020* H'1EF0 0020* 32 EESR R/W H'FEF0 0028* H'1EF0 0028* 32 EESIPR R/W H'FEF0 0030* H'1EF0 0030* 32 TRSCER R/W H'FEF0 0038* H'1EF0 0038* 32 RMFCR R H'FEF0 0040* H'1EF0 0040* 32 Transmit FIFO threshold TFTR register FIFO depth register Receiving method control register Transmit FIFO underrun TFUCR counter Receive FIFO overflow counter Receive buffer write address register Receive descriptor fetch RDFAR address register Transmit buffer read address register Transmit descriptor fetch address register TDFAR TBRAR RBWAR RFOCR FDR RMCR R/W H'FEF0 0048* H'1EF0 0048* 32 R/W R/W H'FEF0 0050* H'FEF0 0058* H'1EF0 0050* H'1EF0 0058* 32 32 R/W H'FEF0 0064* H'1EF0 0064* 32 R/W H'FEF0 0068* H'1EF0 0068* 32 R H'FEF0 00C8* H'1EF0 00C8* 32 R H'FEF0 00CC* H'1EF0 00CC* 32 R H'FEF0 00D4* H'1EF0 00D4* 32 R H'FEF0 00D8* H'1EF0 00D8* 32 Rev. 1.00 Nov. 22, 2007 Page 1525 of 1692 REJ09B0360-0100 Section 32 List of Registers Module E-DMAC Register Name Flow control start FIFO threshold setting register Receive data padding insert register Transmit interrupt setting register Independent output signal setting register Abbreviation R/W FCFTR R/W P4 Area Address* H'FEF0 0070* Area 7 Address* H'1EF0 0070* Access Size Remarks 32 RPADIR R/W H'FEF0 0078* H'1EF0 0078* 32 TRIMD R/W H'FEF0 007C* H'1EF0 007C* 32 IOSR R/W H'FEF0 006C* H'1EF0 006C* 32 USB System configuration control register CPU bus wait setting register System configuration status register Device state control register Test mode register DMA0-FIFO bus configuration register DMA1-FIFO bus configuration register CFIFO port register D0FIFO port register SYSCFG R/W H'FE40 0000 16 BUSWAIT R/W H'FE40 0002 16 SYSSTS R H'FE40 0004 16 DVSTCTR R/W H'FE40 0008 16 TESTMODE D0FBCFG R/W R/W H'FE40 000C H'FE40 0010 16 16 D1FBCFG R/W H'FE40 0012 16 CFIFO D0FIFO R/W R/W H'FE40 0014 H'FE40 0018 H'FE40 0180 8, 16, 32 8, 16, 32 D1FIFO port register D1FIFO R/W H'FE40 001C H'FE40 01C0 8, 16, 32 CFIFO port select register CFIFO port control register D0FIFO port select register D0FIFO port control register CFIFOSEL R/W H'FE40 0020 16 CFIFOCTR R/W H'FE40 0022 16 D0FIFOSEL R/W H'FE40 0028 16 D0FIFOCTR R/W H'FE40 002A 16 Rev. 1.00 Nov. 22, 2007 Page 1526 of 1692 REJ09B0360-0100 Section 32 List of Registers Module USB Register Name D1FIFO port select register D1FIFO port control register Abbreviation R/W D1FIFOSEL R/W P4 Area Address* H'FE40 002C Area 7 Address* Access Size Remarks 16 D1FIFOCTR R/W H'FE40 002E 16 Interrupt enable register INTENB0 0 Interrupt enable register INTENB1 1 BRDY interrupt enable register NRDY interrupt enable register BEMP interrupt enable register SOF output configuration register Interrupt status register 0 Interrupt status register 1 BRDY interrupt status register NRDY interrupt status register BEMP interrupt status register Frame number register FRMNUM BEMPSTS NRDYSTS BRDYSTS INTSTS1 INTSTS0 SOFCFG BEMPENB NRDYENB BRDYENB R/W H'FE40 0030 16 R/W H'FE40 0032 16 R/W H'FE40 0036 16 R/W H'FE40 0038 16 R/W H'FE40 003A 16 R/W H'FE40 003C 16 R/W H'FE40 0040 16 R/W H'FE40 0042 16 R/W H'FE40 0046 16 R/W H'FE40 0048 16 R/W H'FE40 004A 16 R/W R/W R R H'FE40 004C H'FE40 004E H'FE40 0050 H'FE40 0054 16 16 16 16 µFrame number register UFRMNUM USB address register USB request type register USB request value register USB request index register USBINDX USBVAL USBADDR USBREQ R H'FE40 0056 16 R H'FE40 0058 16 Rev. 1.00 Nov. 22, 2007 Page 1527 of 1692 REJ09B0360-0100 Section 32 List of Registers Module USB Register Name USB request length register DCP configuration register DCP maximum packet size register DCP control register Pipe window select register Pipe configuration register Pipe buffer setting register Pipe maximum packet size register Pipe cycle control register Pipe 1 control register Pipe 2 control register Pipe 3 control register Pipe 4 control register Pipe 5 control register Pipe 6 control register Pipe 7 control register Pipe 8 control register Pipe 9 control register Pipe 1 transaction counter enable register Pipe 1 transaction counter register Pipe 2 transaction counter enable register Pipe 2 transaction counter register Abbreviation R/W USBLENG R P4 Area Address* H'FE40 005A Area 7 Address* Access Size Remarks 16 DCPCFG R/W H'FE40 005C 16 DCPMAXP R/W H'FE40 005E 16 DCPCTR PIPESEL R/W R/W H'FE40 0060 H'FE40 0064 16 16 PIPECFG R/W H'FE40 0068 16 PIPEBUF R/W H'FE40 006A 16 PIPEMAXP R/W H'FE40 006C 16 PIPEPERI R/W H'FE40 006E 16 PIPE1CTR PIPE2CTR PIPE3CTR PIPE4CTR PIPE5CTR PIPE6CTR PIPE7CTR PIPE8CTR PIPE9CTR PIPE1TRE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'FE40 0070 H'FE40 0072 H'FE40 0074 H'FE40 0076 H'FE40 0078 H'FE40 007A H'FE40 007C H'FE40 007E H'FE40 0080 H'FE40 0090 16 16 16 16 16 16 16 16 16 16 PIPE1TRN R/W H'FE40 0092 16 PIPE2TRE R/W H'FE40 0094 16 PIPE2TRN R/W H'FE40 0096 16 Rev. 1.00 Nov. 22, 2007 Page 1528 of 1692 REJ09B0360-0100 Section 32 List of Registers Module USB Register Name Pipe 3 transaction counter enable register Pipe 3 transaction counter register Pipe 4 transaction counter enable register Pipe 4 transaction counter register Pipe 5 transaction counter enable register Pipe 5 transaction counter register Device address 0 configuration register Device address 1 configuration register Device address 2 configuration register Device address 3 configuration register Device address 4 configuration register Device address 5 configuration register Device address 6 configuration register Device address 7 configuration register Device address 8 configuration register Device address 9 configuration register Device address A configuration register Abbreviation R/W PIPE3TRE R/W P4 Area Address* H'FE40 0098 Area 7 Address* Access Size Remarks 16 PIPE3TRN R/W H'FE40 009A 16 PIPE4TRE R/W H'FE40 009C 16 PIPE4TRN R/W H'FE40 009E 16 PIPE5TRE R/W H'FE40 00A0 16 PIPE5TRN R/W H'FE40 00A2 16 DEVADD0 R/W H'FE40 00D0 16 DEVADD1 R/W H'FE40 00D2 16 DEVADD2 R/W H'FE40 00D4 16 DEVADD3 R/W H'FE40 00D6 16 DEVADD4 R/W H'FE40 00D8 16 DEVADD5 R/W H'FE40 00DA 16 DEVADD6 R/W H'FE40 00DC 16 DEVADD7 R/W H'FE40 00DE 16 DEVADD8 R/W H'FE40 00E0 16 DEVADD9 R/W H'FE40 00E2 16 DEVADDA R/W H'FE40 00E4 16 Rev. 1.00 Nov. 22, 2007 Page 1529 of 1692 REJ09B0360-0100 Section 32 List of Registers Module LCDC Register Name Palette data register 00 to FF LCDC input clock register LCDC module type register LCDC data format register LCDC data fetch start address register for upper display panel LCDC data fetch start address register for lower display panel LCDC fetch data line address offset register for display panel LCDC palette control register LCDC horizontal character number register LCDC horizontal synchronization signal register Abbreviation R/W LDPR00 to LDPRFF LDICKR R/W R/W P4 Area Address* Area 7 Address* Access Size Remarks H'FFE3 0000 to H'1FE3 0000 to 32 H'FFE3 03FC H'FFE3 0400 H'1FE3 03FC H'1FE3 0400 16 LDMTR R/W H'FFE3 0402 H'1FE3 0402 16 LDDFR R/W H'FFE3 0404 H'1FE3 0404 16 LDSARU R/W H'FFE3 0408 H'1FE3 0408 32 LDSARL R/W H'FFE3 040C H'1FE3 040C 32 LDLAOR R/W H'FFE3 0410 H'1FE3 0410 16 LDPALCR R/W H'FFE3 0412 H'1FE3 0412 16 LDHCNR R/W H'FFE3 0414 H'1FE3 0414 16 LDHSYNR R/W H'FFE3 0416 H'1FE3 0416 16 LCDC vertical displayed LDVDLNR line number register LCDC vertical total line number register LCDC vertical synchronization signal register LCDC AC modulation signal toggle line number register LDACLNR LDVSYNR LDVTLNR R/W H'FFE3 0418 H'1FE3 0418 16 R/W H'FFE3 041A H'1FE3 041A 16 R/W H'FFE3 041C H'1FE3 041C 16 R/W H'FFE3 041E H'1FE3 041E 16 Rev. 1.00 Nov. 22, 2007 Page 1530 of 1692 REJ09B0360-0100 Section 32 List of Registers Module LCDC Register Name LCDC interrupt control register LCDC power management mode register LCDC power supply sequence period register LCDC control register LCDC user specified interrupt control register LCDC user specified interrupt line number register LCDC memory access interval number register Abbreviation R/W LDINTR R/W P4 Area Address* H'FFE3 0420 Area 7 Address* H'1FE3 0420 Access Size Remarks 16 LDPMMR R/W H'FFE3 0424 H'1FE3 0424 16 LDPSPR R/W H'FFE3 0426 H'1FE3 0426 16 LDCNTR LDUINTR R/W R/W H'FFE3 0428 H'FFE3 0434 H'1FE3 0428 H'1FE3 0434 16 16 LDUINTLNR R/W H'FFE3 0436 H'1FE3 0436 16 LDLIRNR R/W H'FFE3 0440 H'1FE3 0440 16 VDC2 1 Graphics block control GRCMEN1 R/W H'FFEC 0000* H'1FEC 0000* 32/16/8 graphics block register Bus control register Reserved Reserved Reserved Reserved Graphic image base address register Graphic image area register Graphic image line offset register Graphic image start position register Reserved Reserved Reserved Reserved     R R R R H'FFEC 0318* H'FFEC 031C* H'FFEC 0320* H'FFEC 0324* H'1FEC 0318* H'1FEC 031C* H'1FEC 0320* H'1FEC 0324* 32/16/8 32/16/8 32/16/8 32/16/8 GROPDPHV1 R/W H'FFEC 0314* H'1FEC 0314* 32/16/8 GROPSOFST1 R/W H'FFEC 0310* H'1FEC 0310* 32/16/8 GROPSWH1 R/W H'FFEC 030C* H'1FEC 030C* 32/16/8 GRCBUSCNT1 R/W     GROPSADR1 R R R R R/W H'FFEC 0004* H'FFEC 0008* H'FFEC 000C* H'FFEC 0300* H'FFEC 0304* H'FFEC 0308* H'1FEC 0004* H'1FEC 0008* H'1FEC 000C* H'1FEC 0300* H'1FEC 0304* H'1FEC 0308* 32/16/8 32/16/8 32/16/8 32/16/8 32/16/8 32/16/8 Rev. 1.00 Nov. 22, 2007 Page 1531 of 1692 REJ09B0360-0100 Section 32 List of Registers Module VDC2 graphics block 1 VDC2 2 Register Name Reserved Abbreviation R/W  R P4 Area Address* H'FFEC 0328* H'FFEC 032C* Area 7 Address* H'1FEC 0328* H'1FEC 032C* Access Size Remarks 32/16/8 32/16/8 Color register for outside GROPBASERG R/W of graphic image area Graphics block control B1 GRCMEN2 R/W H'FFED 0000* H'1FED 0000* 32/16/8 graphics block register Bus control register Reserved Reserved Reserved Reserved Graphic image base address register Graphic image area register Graphic image line offset register Graphic image start position register α control area register α control area start position register α control register Chroma-key control register Chroma-key color register Color register for outside GROPBASERG R/W of graphic image area VDC2 3 Graphics block control B2 GRCMEN3 R/W H'FFEE 0000* H'1FEE 0000* 32/16/8 H'FFED 032C* H'1FED 032C* 32/16/8 GROPCRKY1_2 GRCBUSCNT2 R/W     GROPSADR2 R R R R R/W H'FFED 0004* H'FFED 0008* H'FFED 000C* H'FFED 0300* H'FFED 0304* H'FFED 0308* H'1FED 0004* H'1FED 0008* H'1FED 000C* H'1FED 0300* H'1FED 0304* H'1FED 0308* 32/16/8 32/16/8 32/16/8 32/16/8 32/16/8 32/16/8 GROPSWH2 R/W H'FFED 030C* H'1FED 030C* 32/16/8 GROPSOFST2 R/W H'FFED 0310* H'1FED 0310* 32/16/8 GROPDPHV2 R/W H'FFED 0314* H'1FED 0314* 32/16/8 GROPEWH2 R/W H'FFED 0318* H'FFED 031C* H'1FED 0318* H'1FED 031C* 32/16/8 32/16/8 GROPEDPHV2 R/W GROPEDPA2 GROPCRKY0_2 R/W R/W H'FFED 0320* H'FFED 0324* H'1FED 0320* H'1FED 0324* 32/16/8 32/16/8 R/W H'FFED 0328* H'1FED 0328* 32/16/8 graphics block register Bus control register Reserved Reserved Reserved GRCBUSCNT3 R/W    R R R H'FFEE 0004* H'FFEE 0008* H'FFEE 000C* H'FFEE 0300* H'1FEE 0004* H'1FEE 0008* H'1FEE 000C* H'1FEE 0300* 32/16/8 32/16/8 32/16/8 32/16/8 Rev. 1.00 Nov. 22, 2007 Page 1532 of 1692 REJ09B0360-0100 Section 32 List of Registers Module VDC2 graphics block 3 Register Name Reserved Graphic image base address register Graphic image area register Graphic image line offset register Graphic image start position register α control area register α control area start position register α control register Chroma-key control register Chroma-key color register Abbreviation R/W  GROPSADR3 R R/W P4 Area Address* H'FFEE 0304* H'FFEE 0308* Area 7 Address* H'1FEE 0304* H'1FEE 0308* Access Size Remarks 32/16/8 32/16/8 GROPSWH3 R/W H'FFEE 030C* H'1FEE 030C* 32/16/8 GROPSOFST3 R/W H'FFEE 0310* H'1FEE 0310* 32/16/8 GROPDPHV3 R/W H'FFEE 0314* H'1FEE 0314* 32/16/8 GROPEWH3 R/W H'FFEE 0318* H'FFEE 031C* H'1FEE 0318* H'1FEE 031C* 32/16/8 32/16/8 GROPEDPHV3 R/W GROPEDPA3 GROPCRKY0_3 R/W R/W H'FFEE 0320* H'FFEE 0324* H'1FEE 0320* H'1FEE 0324* 32/16/8 32/16/8 GROPCRKY1_3 R/W H'FFEE 0328* H'1FEE 0328* 32/16/8 Color register for outside GROPBASERGB3 R/W of graphic image area VDC2 4 Graphics block control GRCMEN4 R/W H'FFEE 032C* H'1FEE 032C* 32/16/8 H'FFEF 0000* H'1FEF 0000* 32/16/8 graphics block register Bus control register Reserved Reserved Reserved Reserved Graphic image base address register Graphic image area register Graphic image line offset register Graphic image start position register GROPDPHV4 R/W H'FFEF 0314* H'1FEF 0314* 32/16/8 GROPSOFST4 R/W H'FFEF 0310* H'1FEF 0310* 32/16/8 GROPSWH4 R/W H'FFEF 030C* H'1FEF 030C* 32/16/8 GRCBUSCNT4 R/W     GROPSADR4 R R R R R/W H'FFEF 0004* H'FFEF 0008* H'FFEF 000C* H'FFEF 0300* H'FFEF 0304* H'FFEF 0308* H'1FEF 0004* H'1FEF 0008* H'1FEF 000C* H'1FEF 0300* H'1FEF 0304* H'1FEF 0308* 32/16/8 32/16/8 32/16/8 32/16/8 32/16/8 32/16/8 Rev. 1.00 Nov. 22, 2007 Page 1533 of 1692 REJ09B0360-0100 Section 32 List of Registers Module VDC2 graphics block 4 Register Name α control area register α control area start position register α control register Chroma-key control register Chroma-key color register Abbreviation R/W GROPEWH4 R/W P4 Area Address* H'FFEF 0318* H'FFEF 031C* Area 7 Address* H'1FEF 0318* H'1FEF 031C* Access Size Remarks 32/16/8 32/16/8 GROPEDPHV4 R/W GROPEDPA4 GROPCRKY0_4 R/W R/W H'FFEF 0320* H'FFEF 0324* H'1FEF 0320* H'1FEF 0324* 32/16/8 32/16/8 GROPCRKY1_4 R/W H'FFEF 0328* H'1FEF 0328* 32/16/8 Color register for outside GROPBASERGB4 R/W of graphic image area VDC2 display control block SG mode register Interrupt output control register Sync signal control register External sync signal input timing control register Reserved  R R/W R/W EXTSYNCNT R/W SYNCNT R/W SGMODE SGINTCNT R/W R/W H'FFEF 032C* H'1FEF 032C* 32/16/8 H'FFEB 0000* H'FFEB 0004* H'1FEB 0000* H'1FEB 0004* 32/16/8 32/16/8 H'FFEB 0008* H'1FEB 0008* 32/16/8 H'FFEB 000C* H'1FEB 000C* 32/16/8 H'FFEB 0100* H'FFEB 0104* H'FFEB 0108* H'1FEB 0100* H'1FEB 0104* H'1FEB 0108* 32/16/8 32/16/8 32/16/8 Sync signal size register SYNSIZE Vertical sync signal timing control register Horizontal sync signal timing control register Gate clock signal timing CLSTIM control register Sampling start signal timing control register Gate control signal timing control register SGDE area start position register SGDE area size register SGDESIZE CDE chroma-key color register CDECRKY SGDESTART COMTIM SPLTIM HSYNCTIM VSYNCTIM R/W H'FFEB 010C* H'1FEB 010C* 32/16/8 R/W H'FFEB 0110* H'1FEB 0110* 32/16/8 R/W H'FFEB 0118* H'1FEB 0118* 32/16/8 R/W H'FFEB 011C* H'1FEB 011C* 32/16/8 R/W H'FFEB 0120* H'1FEB 0120* 32/16/8 R/W R/W H'FFEB 0124* H'FFEB 0128* H'1FEB 0124* H'1FEB 0128* 32/16/8 32/16/8 Rev. 1.00 Nov. 22, 2007 Page 1534 of 1692 REJ09B0360-0100 Section 32 List of Registers Module VDC2 display control block Register Name Reserved Abbreviation R/W  R P4 Area Address* H'FFEB 0148* Area 7 Address* H'1FEB 0148* Access Size Remarks 32/16/8 T-1004 control register T-1004 video start position register Reserved Reserved FLCTL T1004CNT T1004OFFSET R/W R/W H'FFEB 0200* H'FFEB 0204* H'1FEB 0200* H'1FEB 0204* 32/16/8 32/16/8   R R R/W R/W H'FFEB 0208* H'FFEB 020C* H'FFE9 0000 H'FFE9 0004 H'1FEB 0208* H'1FEB 020C* H'1FE9 0000 H'1FE9 0004 32/16/8 32/16/8 32 32 Common control register FLCMNCR Command control register Command code register FLCMCDR Address register Address register 2 Data register Data counter register Interrupt DMA control register Ready busy timeout setting register Ready busy timeout counter Data FIFO register FLDTFIFO FLBSYCNT FLBSYTMR FLADR FLADR2 FLDATAR FLDTCNTR FLINTDMACR FLCMDCR R/W R/W R/W R/W R/W R/W H'FFE9 0008 H'FFE9 000C H'FFE9 003C H'FFE9 0010 H'FFE9 0014 H'FFE9 0018 H'1FE9 0008 H'1FE9 000C H'1FE9 003C H'1FE9 0010 H'1FE9 0014 H'1FE9 0018 32 32 32 32 32 32 R/W H'FFE9 001C H'1FE9 001C 32 R H'FFE9 0020 H'1FE9 0020 32 R/W H'FFE9 0024/ H'FFE9 0050 H'1FE9 0024/ H'1FE9 0050 H'1FE9 0028/ H'1FE9 0060 H'1FE9 002C H'1FF3 0000 H'1FF3 0004 32 Control code FIFO register FLECFIFO R/W H'FFE9 0028/ H'FFE9 0060 32 Transfer control register FLTRCR SRC SRC input data register SRC output data register SRC input data control register SRC output data control SRCODCTRL register SRCIDCTRL SRCID SRCOD R/W R/W R H'FFE9 002C H'FFF3 0000 H'FFF3 0004 8 16, 32 16, 32 R/W H'FFF3 0008 H'1FF3 0008 16 R/W H'FFF3 000A H'1FF3 000A 16 Rev. 1.00 Nov. 22, 2007 Page 1535 of 1692 REJ09B0360-0100 Section 32 List of Registers Module SRC Register Name SRC control register SRC status register Abbreviation R/W SRCCTRL SRCSTAT R/W R/ (W)*9 P4 Area Address* H'FFF3 000C H'FFF3 000E Area 7 Address* H'1FF3 000C H'1FF3 000E Access Size Remarks 16 16 GPIO Port A control register Port B control register Port C control register Port D control register Port E control register Port F control register Port G control register Port H control register Port I control register Port J control register Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port G data register Port H data register Port I data register Port J data register Input-pin pull-up control register Pin select register A Pin select register B Pin select register C Pin select register D Pin select register E Pin select register F PTIO_A PTIO_B PTIO_C PTIO_D PTIO_E PTIO_F PTIO_G PTIO_H PTIO_I PTIO_J PTDAT_A PTDAT_B PTDAT_C PTDAT_D PTDAT_E PTDAT_F PTDAT_G PTDAT_H PTDAT_I PTDAT_J PTPUL_SPCL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'FFF1 0000* H'FFF1 0004* H'FFF1 0008* H'FFF1 000C* H'FFF1 0010* H'FFF1 0014* H'FFF1 0018* H'FFF1 001C* H'FFF1 0020* H'FFF1 0024* H'FFF1 0040* H'FFF1 0044* H'FFF1 0048* H'FFF1 004C* H'FFF1 0050* H'FFF1 0054* H'FFF1 0058* H'FFF1 005C* H'FFF1 0060* H'FFF1 0064* H'FFF1 00E0* H'1FF1 0000* H'1FF1 0004* H'1FF1 0008* H'1FF1 000C* H'1FF1 0010* H'1FF1 0014* H'1FF1 0018* H'1FF1 001C* H'1FF1 0020* H'1FF1 0024* H'1FF1 0040* H'1FF1 0044* H'1FF1 0048* H'1FF1 004C* H'1FF1 0050* H'1FF1 0054* H'1FF1 0058* H'1FF1 005C* H'1FF1 0060* H'1FF1 0064* H'1FF1 00E0* 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 PTSEL_A PTSEL_B PTSEL_C PTSEL_D PTSEL_E PTSEL_F R/W R/W R/W R/W R/W R/W H'FFF1 0080* H'FFF1 0084* H'FFF1 0088* H'FFF1 008C* H'FFF1 0090* H'FFF1 0094* H'1FF1 0080* H'1FF1 0084* H'1FF1 0088* H'1FF1 008C* H'1FF1 0090* H'1FF1 0094* 16*10 16*10 16*10 16*10 16*10 16*10 Rev. 1.00 Nov. 22, 2007 Page 1536 of 1692 REJ09B0360-0100 Section 32 List of Registers Module GPIO Register Name Pin select register G Pin select register H Pin select register I Pin select register J Pin select register K Pin select register P Pin select register R Pin select register S Hi-Z register A Hi-Z register B Special select register Abbreviation R/W PTSEL_G PTSEL_H PTSEL_I PTSEL_J PTSEL_K PTSEL_P PTSEL_R PTSEL_S PTHIZ_A PTHIZ_B PTSEL_SPCL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P4 Area Address* H'FFF1 0098* H'FFF1 009C* H'FFF1 00A0* H'FFF1 00A4* H'FFF1 00A8* H'FFF1 00AC* H'FFF1 00B0* H'FFF1 00B4* H'FFF1 00E8* H'FFF1 00EC* H'FFF1 00F0 H'FFC8 0020 H'FFC8 0030 H'FFC8 0038 H'FF20 0000 Area 7 Address* H'1FF1 0098* H'1FF1 009C* H'1FF1 00A0* H'1FF1 00A4* H'1FF1 00A8* H'1FF1 00AC* H'1FF1 00B0* H'1FF1 00B4* H'1FF1 00E8* H'1FF1 00EC* H'1FF1 00F0 H'1FC8 0020 H1FC8 0030 H'1FC8 0038 H'1F20 0000 Access Size Remarks 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 16*10 32 32 32 32 Power-down mode Standby control register STBCR Module stop register 0 Module stop register 1 MSTPCR0 MSTPCR1 CBR0 UBC Match condition setting register 0 Match operation setting register 0 Match address setting register 0 Match address mask setting register 0 Match condition setting register 1 Match operation setting register 1 Match address setting register 1 Match address mask setting register 1 Match data setting register 1 CRR0 R/W H'FF20 0004 H'1F20 0004 32 CAR0 R/W H'FF20 0008 H'1F20 0008 32 CAMR0 R/W H'FF20 000C H'1F20 000C 32 CBR1 R/W H'FF20 0020 H'1F20 0020 32 CRR1 R/W H'FF20 0024 H'1F20 0024 32 CAR1 R/W H'FF20 0028 H'1F20 0028 32 CAMR1 R/W H'FF20 002C H'1F20 002C 32 CDR1 R/W H'FF20 0030 H'1F20 0030 32 Rev. 1.00 Nov. 22, 2007 Page 1537 of 1692 REJ09B0360-0100 Section 32 List of Registers Module UBC Register Name Abbreviation R/W R/W P4 Area Address* H'FF20 0034 Area 7 Address* H'1F20 0034 Access Size Remarks 32 Match data mask setting CDMR1 register 1 Execution count break register 1 Channel match flag register Break control register CBCR CCMFR CETR1 R/W H'FF20 0038 H'1F20 0038 32 R/W H'FF20 0600 H'1F20 0600 32 R/W H'FF20 0620 H'1F20 0620 32 Notes: * The P4 area addresses shown here are the P4 area addresses in the virtual address space. The area 7 addresses should be accessed via the area 7 in the physical address space using the TLB. 1. Only 0 can be written to the HE and TE bits in CHCR after 1 is read from the bits to clear the flags. 2. Only 0 can be written to the AE and NMIF bits in DMAOR after 1 is read from the bits to clear the flags. 3. Do not access the registers with the access size not specified here. 4. Only 0 can be written to the registers to clear the flags. In addition, bits 15 to 8, 3, and 2 are read-only bits allowing no write-accesses. 5. Only 0 can be written to the registers to clear the flags. In addition, bits 15 to 1 are read-only bits allowing no write-accesses. 6. Only 0 can be written to bits 4 to 0 to clear the flags. 7. Only 0 can be written to bits 6 to 0 to clear the flags. 8. All the bits except bits 27 and 26 in the registers are read-only bits; bits 27 and 26 allow both read- and write- accesses. For details, refer to section 18.3.17, Status Registers 0 to 5 (SSISR0 to SSISR5). 9. Bits 15 to 3 are read-only bits. Only 0 can be written to bits 2 to 0 after 1 is read from the bits. 10. The registers can only be accessed in 16-bit units; be sure to access the registers with the specified access size. 11. For the standby control register, also refer to figure 9.1, Block Diagram of CPG. Rev. 1.00 Nov. 22, 2007 Page 1538 of 1692 REJ09B0360-0100 Section 32 List of Registers Module MCU Register Name Version control register Abbreviation R/W VCR R/W P4 Area Address H'FF80 0000 Area 7 Address Remarks Access (Initial Value) Size 32 H'0B04 0000 0000 0000 Memory interface mode register SDRAM control register MIM R/W H'FF80 0008 32 H'0000 0000 061A 0x40 SCR R/W H'FF80 0010 32 H'0000 0000 0000 0000 SDRAM timing register STR R/W H'FF80 0018 32 H'0000 0000 00FF FFE7 SDRAM row attribute register SDRAM mode register SDRA R/W H'FF80 0030 32 H'0000 0000 0000 0200 SDMR R R/W H'FFAx xxxx H'FF80 0200 32 32  H'0000 0000 0400 0000 Arbitration mode register AMR Linear-to-tiled memory address translation control register 0 Linear-to-tiled memory address translation area start address register 0 Linear-to-tiled memory address translation area start address mask register 0 Linear-to-tiled memory address translation control register 1 Linear-to-tiled memory address translation area start address register 1 LTC0 R/W H'FF80 0100 32 H'0000 0000 0000 0000 LTAD0 R/W H'FF80 0108 32 H'0000 0000 0000 0000 LTAM0 R/W H'FF80 0110 32 H'0000 0000 0000 0000 LTC1 R/W H'FF80 0118 32 H'0000 0000 0000 0000 LTAD1 R/W H'FF80 0120 32 H'0000 0000 0000 0000 Rev. 1.00 Nov. 22, 2007 Page 1539 of 1692 REJ09B0360-0100 Section 32 List of Registers Module MCU Register Name Linear-to-tiled memory address translation area start address mask register 1 Linear-to-tiled memory address translation control register 2 Linear-to-tiled memory address translation area start address register 2 Linear-to-tiled memory address translation area start address mask register 2 Linear-to-tiled memory address translation control register 3 Linear-to-tiled memory address translation area start address register 3 Linear-to-tiled memory address translation area start address mask register 3 Linear-to-tiled memory address translation control register 4 Linear-to-tiled memory address translation area start address register 4 Linear-to-tiled memory address translation area start address mask register 4 Linear-to-tiled memory address translation control register 5 Abbreviation R/W LTAM1 R/W P4 Area Address H'FF80 0128 Area 7 Address Remarks Access (Initial Value) Size 32 H'0000 0000 0000 0000 LTC2 R/W H'FF80 0130 32 H'0000 0000 0000 0000 LTAD2 R/W H'FF80 0138 32 H'0000 0000 0000 0000 LTAM2 R/W H'FF80 0140 32 H'0000 0000 0000 0000 LTC3 R/W H'FF80 0148 32 H'0000 0000 0000 0000 LTAD3 R/W H'FF80 0150 32 H'0000 0000 0000 0000 LTAM3 R/W H'FF80 0158 32 H'0000 0000 0000 0000 LTC4 R/W H'FF80 0160 32 H'0000 0000 0000 0000 LTAD4 R/W H'FF80 0168 32 H'0000 0000 0000 0000 LTAM4 R/W H'FF80 0170 32 H'0000 0000 0000 0000 LTC5 R/W H'FF80 0178 32 H'0000 0000 0000 0000 Rev. 1.00 Nov. 22, 2007 Page 1540 of 1692 REJ09B0360-0100 Section 32 List of Registers Module MCU Register Name Linear-to-tiled memory address translation area start address register 5 Linear-to-tiled memory address translation area start address mask register 5 Linear-to-tiled memory address translation control register 6 Linear-to-tiled memory address translation area start address register 6 Linear-to-tiled memory address translation area start address mask register 6 Linear-to-tiled memory address translation control register 7 Linear-to-tiled memory address translation area start address register 7 Linear-to-tiled memory address translation area start address mask register 7 Request mask setting register Bus control register Abbreviation R/W LTAD5 R/W P4 Area Address H'FF80 0180 Area 7 Address Remarks Access (Initial Value) Size 32 H'0000 0000 0000 0000 LTAM5 R/W H'FF80 0188 32 H'0000 0000 0000 0000 LTC6 R/W H'FF80 0190 32 H'0000 0000 0000 0000 LTAD6 R/W H'FF80 0198 32 H'0000 0000 0000 0000 LTAM6 R/W H'FF80 01A0 32 H'0000 0000 0000 0000 LTC7 R/W H'FF80 01A8 32 H'0000 0000 0000 0000 LTAD7 R/W H'FF80 01B0 32 H'0000 0000 0000 0000 LTAM7 R/W H'FF80 01B8 32 H'0000 0000 0000 0000 RQM R/W H'FF80 0218 32 H'0000 0000 0000 0000 BCR R/W H'FF80 1000 32 H'0000 0000 3800 0000 CS0 bus control register CS0BCR R/W H'FF80 2000 32 H'0000 0000 7777 7x80 Rev. 1.00 Nov. 22, 2007 Page 1541 of 1692 REJ09B0360-0100 Section 32 List of Registers Module MCU Register Name Abbreviation R/W R/W P4 Area Address H'FF80 2008 Area 7 Address Remarks Access (Initial Value) Size 32 H'0000 0000 7777 770F CS0 wait control register CS0WCR CS3 bus control register CS3BCR R/W H'FF80 2030 32 H'0000 0000 7777 7380 CS3 wait control register CS3WCR R/W H'FF80 2038 32 H'0000 0000 7777 770F Rev. 1.00 Nov. 22, 2007 Page 1542 of 1692 REJ09B0360-0100 Section 32 List of Registers Module ATAPI Register Name ATAPI status Abbreviation R/W ATAPI_STATU S R/W P4 Area Address H'FFF0 0084 Area 7 Address Register Access Size* 32 Remarks Interrupt enable ATAPI_INT_EN R/W ABLE H'FFF0 0088 32 PIO timing ATAPI_PIO_TI MING R/W H'FFF0 008C 32 Multiword DMA timing ATAPI_MULTI_ R/W TIMING H'FFF0 0090 32 Ultra DMA timing ATAPI_ULTRA_ R/W TIMING H'FFF0 0094 32 Descriptor table base address DMA start address ATAPI_DTB_A DR ATAPI_DMA_ START_ADR R/W H'FFF0 0098 32 R/W H'FFF0 009C 32 DMA transfer count ATAPI_DMA_ TRANS_CNT R/W H'FFF0 00A0 32 ATAPI control 2 ATAPI_ CONTROL2 R/W H'FFF0 00A4 32 Reserved Reserved ATAPI signal status Byte swap R R ATAPI_SIG_ST R ATAPI_BYTE_ SWAP R/W H'FFF0 00A8 H'FFF0 00AC H'FFF0 00B0 H'FFF0 00BC 32 32 32 32 Note: * The above registers should be accessed in longword units (32 bits); byte and word accesses are prohibited. Rev. 1.00 Nov. 22, 2007 Page 1543 of 1692 REJ09B0360-0100 Section 32 List of Registers Module G2D Register Name System control Status Status register clear Interrupt enable Interrupt command ID Return address 0 Return address 1 Abbreviation R/W SCLR SR SRCR IER ICIDR RTN0R RTN1R R/W R W R/W R R R R/W R/W P4 Area 2 Address* H'FFEA 0000 H'FFEA 0004 H'FFEA 0008 H'FFEA 000C H'FFEA 0010 H'FFEA 0040 H'FFEA 0044 H'FFEA 0048 H'FFEA 004C Area 7 2 Address* H'1FEA 0000 H'1FEA 0004 H'1FEA 0008 H'1FEA 000C H'1FEA 0010 H'1FEA 0040 H'1FEA 0044 H'1FEA 0048 H'1FEA 004C Access Remarks 1 Size (WPR)* 32 32 32 32 32 32 32 32 32 × × × O × O O × O Display list start address DLSAR 2-dimensional source area start address Rendering start address RSAR Work area start address WSAR Source stride Destination stride Endian conversion control Source transparent color STCR Destination transparent color Alpha value Color offset Rendering control Command status Current pointer Local offset System clipping area MAX User clipping area MIN User clipping area MAX Relative user clipping area MIN Relative user clipping area MAX RUCLMAR UCLMIR UCLMAR RUCLMIR ALPHR COFSR RCLR CSTR CURR LCOR SCLMAR DTCR SSTRR DSTRR ENDCVR SSAR R/W R/W R/W R/W R/W H'FFEA 0050 H'FFEA 0054 H'FFEA 0058 H'FFEA 005C H'FFEA 0060 H'1FEA 0050 H'1FEA 0054 H'1FEA 0058 H'1FEA 005C H'1FEA 0060 32 32 32 32 32 O O O O × R/W R/W H'FFEA 0080 H'FFEA 0084 H'1FEA 0080 H'1FEA 0084 32 32 O O R/W R/W R/W R R R R H'FFEA 0088 H'FFEA 008C H'FFEA 00C0 H'FFEA 00C4 H'FFEA 00C8 H'FFEA 00CC H'FFEA 00D0 H'1FEA 0088 H'1FEA 008C H'1FEA 00C0 H'1FEA 00C4 H'1FEA 00C8 H'1FEA 00CC H'1FEA 00D0 32 32 32 32 32 32 32 O O O × × × O R R R H'FFEA 00D4 H'FFEA 00D8 H'FFEA 00DC H'1FEA 00D4 H'1FEA 00D8 H'1FEA 00DC 32 32 32 O O O R H'FFEA 00E0 H'1FEA 00E0 32 O Rev. 1.00 Nov. 22, 2007 Page 1544 of 1692 REJ09B0360-0100 Section 32 List of Registers Module G2D Register Name Rendering control 2 Pattern offset Coordinate transformation control Matrix parameter A Matrix parameter B Matrix parameter C Matrix parameter D Matrix parameter E Matrix parameter F Matrix parameter G Matrix parameter H Matrix parameter I Coordinate transformation offset X Coordinate transformation offset Y Z clipping area MIN Z clipping area MAX Z saturation value MIN Abbreviation R/W RCL2R POFSR GTRCR R/W R/W R/W P4 Area 2 Address* H'FFEA 00F0 H'FFEA 00F8 H'FFEA 0100 Area 7 2 Address* H'1FEA 00F0 H'1FEA 00F8 H'1FEA 0100 Access Remarks 1 Size (WPR)* 32 32 32 O O O MTRAR MTRBR MTRCR MTRDR MTRER MTRFR MTRGR MTRHR MTRIR GTROFSXR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'FFEA 0104 H'FFEA 0108 H'FFEA 010C H'FFEA 0110 H'FFEA 0114 H'FFEA 0118 H'FFEA 011C H'FFEA 0120 H'FFEA 0124 H'FFEA 0128 H'1FEA 0104 H'1FEA 0108 H'1FEA 010C H'1FEA 0110 H'1FEA 0114 H'1FEA 0118 H'1FEA 011C H'1FEA 0120 H'1FEA 0124 H'1FEA 0128 32 32 32 32 32 32 32 32 32 32 O O O O O O O O O O GTROFSYR R/W H'FFEA 012C H'1FEA 012C 32 O ZCLPMINR ZCLPMAXR ZSATVMINR R/W R/W R/W H'FFEA 0130 H'FFEA 0134 H'FFEA 0138 H'1FEA 0130 H'1FEA 0134 H'1FEA 0138 32 32 32 O O O Notes: 1. O: ×: 2. WPR command setting Possible Impossible The P4 area addresses shown here are the P4 area addresses in the virtual address space. The area 7 addresses should be accessed via the area 7 in the physical address space using the TLB. If any address not specified here is written to, operation is not guaranteed. Rev. 1.00 Nov. 22, 2007 Page 1545 of 1692 REJ09B0360-0100 Section 32 List of Registers Module H-UDI Register Name Instruction register Abbreviation R/W SDIR R R/W   P4 Area 1 Address* H'FC11 0000 H'FC11 0018   Area 7 1 Address* H'1C11 0000 H'1C11 0018   Remarks Access (Initial 2 Value)* Size 16 16   H'0EFF H'0000  Undefined Interrupt source register SDINT Boundary scan register Bypass register SDBSR SDBPR Notes: 1. The P4 area addresses shown here are the P4 area addresses in the virtual address space. The area 7 addresses should be accessed via the area 7 in the physical address space using the TLB. 2. Registers are initialized when the TRST pin level is low or TAP is in the Test-LogicReset state. Rev. 1.00 Nov. 22, 2007 Page 1546 of 1692 REJ09B0360-0100 Section 32 List of Registers 32.2 Register States in Each Operation Mode Table 32.2 Register States in Each Operation Mode (1) Module Exception handling Register Abbreviation TRA EXPEVT INTEVT EXPMASK MMU PTEH PTEL TTB TEA MMUCR PTEA PASCR IRMCR Cache CCR QACR0 QACR1 RAMCR On-chip memory CPG RAMCR FRQCR PLLCR VDC2CLKCR DMAC SAR0 DAR0 TCR0 CHCR0 SAR1 DAR1 Power-on Reset Undefined H'0000 0000 Undefined H'0000 0000 Undefined Undefined Undefined Undefined H'0000 0000 H'0000 xxx0 H'0000 0000 H'0000 0000 H'0000 0000 Undefined Undefined H'0000 0000 H'0000 0000 H'x032 0044* H'0000 E001 H'0000 0080 Undefined Undefined Undefined H'4000 0000 Undefined Undefined 1 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1547 of 1692 REJ09B0360-0100 Section 32 List of Registers Module DMAC Register Abbreviation TCR1 CHCR1 SAR2 DAR2 TCR2 CHCR2 SAR3 DAR3 TCR3 CHCR3 DMAOR0 SAR4 DAR4 TCR4 CHCR4 SAR5 DAR5 TCR5 CHCR5 SARB0 DARB0 TCRB0 SARB1 DARB1 TCRB1 SARB2 DARB2 TCRB2 SARB3 DARB3 TCRB3 Power-on Reset Undefined H'4000 0000 Undefined Undefined Undefined H'4000 0000 Undefined Undefined Undefined H'4000 0000 H'0000 Undefined Undefined Undefined H'4000 0000 Undefined Undefined Undefined H'4000 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1548 of 1692 REJ09B0360-0100 Section 32 List of Registers Module DMAC Register Abbreviation DMARS0 DMARS1 DMARS2 Power-on Reset H'0000 H'0000 H'0000 H'0B04 0000 0000 0000 H'0000 0000 061A 0x40 H'0000 0000 0000 0000 H'0000 0000 00FF FFE7 H'0000 0000 0000 0200  H'0000 0000 0400 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained MCU VCR MIM SCR STR SDRA SDMR AMR LTC0 LTAD0 LTAM0 LTC1 LTAD1 LTAM1 LTC2 LTAD2 LTAM2 LTC3 LTAD3 LTAM3 LTC4 LTAD4 LTAM4 LTC5 LTAD5 LTAM5 LTC6 Rev. 1.00 Nov. 22, 2007 Page 1549 of 1692 REJ09B0360-0100 Section 32 List of Registers Module MCU Register Abbreviation LTAD6 LTAM6 LTC7 LTAD7 LTAM7 RQM BCR CS0BCR CS0WCR CS3BCR CS3WCR Power-on Reset H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 0000 0000 H'0000 0000 3800 0000 H'0000 0000 7777 7x80 H'0000 0000 7777 770F H'0000 0000 7777 7380 H'0000 0000 7777 770F H'x000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'FF00 0000 H'0000 0000 H'x000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained INTC ICR0 ICR1 INTPRI INTREQ INTMSK INTMSKCLR NMIFCR USERIMASK INT2PRI0 INT2PRI1 INT2PRI2 INT2PRI3 INT2PRI4 INT2PRI5 INT2PRI6 INT2PRI7 INT2PRI8 INT2PRI9 Rev. 1.00 Nov. 22, 2007 Page 1550 of 1692 REJ09B0360-0100 Section 32 List of Registers Module INTC Register Abbreviation INT2PRI10 INT2PRI11 INT2PRI12 INT2A0 INT2A01 INT2A1 INT2A11 INT2MSKR INT2MSKR1 INT2MSKCR INT2MSKCR1 INT2B0 INT2B2 INT2B3 INT2B4 INT2B5 INT2B6 INT2B7 INT2GPIC Power-on Reset H'0000 0000 H'0000 0000 H'0000 0000 H'xxxx xxxx H'xxxx xxxx H'0000 0000 H'0000 0000 H'FFFF FFFF H'FFFF FFFF H'0000 0000 H'0000 0000 H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'xxxx xxxx H'0000 0000 H'00 H'00 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained TMU TOCR TSTR0 TCOR0 TCNT0 TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 Rev. 1.00 Nov. 22, 2007 Page 1551 of 1692 REJ09B0360-0100 Section 32 List of Registers Module TMU Register Abbreviation TCR2 TCPR2 TSTR1 TCOR3 TCNT3 TCR3 TCOR4 TCNT4 TCR4 TCOR5 TCNT5 TCR5 Power-on Reset H'0000 H'xxxx xxxx H'00 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained SCIF SCSMR_0 SCBRR_0 SCSCR_0 SCFTDR_0 SCFSR_0 SCFRDR_0 SCFCR_0 SCFDR_0 SCSPTR_0 SCLSR_0 SCEMR_0 SCSMR_1 SCBRR_1 SCSCR_1 SCFTDR_1 SCFSR_1 SCFRDR_1 Rev. 1.00 Nov. 22, 2007 Page 1552 of 1692 REJ09B0360-0100 Section 32 List of Registers Module SCIF Register Abbreviation SCFCR_1 SCFDR_1 SCSPTR_1 SCLSR_1 SCEMR_1 SCSMR_2 SCBRR_2 SCSCR_2 SCFTDR_2 SCFSR_2 SCFRDR_2 SCFCR_2 SCFDR_2 SCSPTR_2 SCLSR_2 SCEMR_2 Power-on Reset H'0000 H'0000 H'0050 H'0000 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'0000 H'00 H'x0 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained IIC ICSCR ICMCR ICSSR ICMSR ICSIER ICMIER ICCCR ICSAR ICMAR ICRXD ICTXD Rev. 1.00 Nov. 22, 2007 Page 1553 of 1692 REJ09B0360-0100 Section 32 List of Registers Module ATAPI Register Abbreviation ATAPI_ CONTROL ATAPI_ STATUS ATAPI_INT_ ENABLE ATAPI_PIO_ TIMING ATAPI_MULTI_ TIMING ATAPI_ULTRA_ TIMING ATAPI_DTB_ ADR ATAPI_DMA_ START_ADR ATAPI_DMA_ TRANS_CNT ATAPI_ CONTROL2 ATAPI_SIG_ST ATAPI_BYTE_ SWAP Power-on Reset H'0000 0020 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 000x H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained SSI_DMAC0 SSIDMMR0 SSIRDMADR0 SSIRDMCNTR0 SSIWDMADR0 SSIWDMCNTR0 SSIDMCOR0 SSISTPBLCNT0 SSISTPDR0 Rev. 1.00 Nov. 22, 2007 Page 1554 of 1692 REJ09B0360-0100 Section 32 List of Registers Module SSI_DMAC0 Register Abbreviation SSIBLCNTSR0 SSIBLCNT0 SSIBLNCNTSR0 SSIBLNCNT0 SSIDMMR1 SSIRDMADR1 SSIRDMCNTR1 SSIWDMADR1 SSIWDMCNTR1 SSIDMCOR1 SSISTPBLCNT1 SSISTPDR1 SSIBLCNTSR1 SSIBLCNT1 SSIBLNCNTSR1 SSIBLNCNT1 SSIDMMR2 SSIRDMADR2 SSIRDMCNTR2 SSIWDMADR2 SSIWDMCNTR2 SSIDMCOR2 SSISTPBLCNT2 SSISTPDR2 Power-on Reset H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1555 of 1692 REJ09B0360-0100 Section 32 List of Registers Module SSI_DMAC0 Register Abbreviation SSIBLCNTSR2 SSIBLCNT2 SSIBLNCNTSR2 SSIBLNCNT2 SSIDMAOR0 SSIDMINTSR0 SSIDMINTMR0 Power-on Reset H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0101 0101 H'1F1F 1F1F H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained SSI_DMAC1 SSIDMMR3 SSIRDMADR3 SSIRDMCNTR3 SSIWDMADR3 SSIWDMCNTR3 SSIDMCOR3 SSISTPBLCNT3 SSISTPDR3 SSIBLCNTSR3 SSIBLCNT3 SSIBLNCNTSR3 SSIBLNCNT3 SSIDMMR4 SSIRDMADR4 SSIRDMCNTR4 SSIWDMADR4 SSIWDMCNTR4 Rev. 1.00 Nov. 22, 2007 Page 1556 of 1692 REJ09B0360-0100 Section 32 List of Registers Module SSI_DMAC1 Register Abbreviation SSIDMCOR4 SSISTPBLCNT4 SSISTPDR4 SSIBLCNTSR4 SSIBLCNT4 SSIBLNCNTSR4 SSIBLNCNT4 SSIDMMR5 SSIRDMADR5 SSIRDMCNTR5 SSIWDMADR5 SSIWDMCNTR5 SSIDMCOR5 SSISTPBLCNT5 SSISTPDR5 SSIBLCNTSR5 SSIBLCNT5 SSIBLNCNTSR5 SSIBLNCNT5 SSIDMAOR1 SSIDMINTSR1 SSIDMINTMR1 Power-on Reset H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0101 0101 H'1F1F 1F1F Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1557 of 1692 REJ09B0360-0100 Section 32 List of Registers Module SSI_CH0 to 5 Register Abbreviation SSICR0 SSISR0 SSITDR0 SSIRDR0 SSICR1 SISR1 SSITDR1 SSIRDR1 SSICR2 SSISR2 SSITDR2 SSIRDR2 SSICR3 SSISR3 SSITDR3 SSIRDR3 SSICR4 SSISR4 SITDR4 SSIRDR4 SSICR5 SSISR5 SSITDR5 SSIRDR5 Power-on Reset H'0000 0000 H'0210 A003 H'0000 0000 H'0000 0000 H'0000 0000 H'0210 A003 H'0000 0000 H'0000 0000 H'0000 0000 H'0210 A003 H'0000 0000 H'0000 0000 H'0000 0000 H'0210 A003 H'0000 0000 H'0000 0000 H'0000 0000 H'0210 A003 H'0000 0000 H'0000 0000 H'0000 0000 H'0210 A003 H'0000 0000 H'0000 0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1558 of 1692 REJ09B0360-0100 Section 32 List of Registers Module EtherC Register Abbreviation ECMR ECSR ECSIPR RFLR PIR MAHR MALR PSR TROCR CDCR LCCR CNDCR CEFCR FRECR TSFRCR TLFRCR RFCR MAFCR IPGR APR MPR TPAUSER BCFRR Power-on Reset H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 000x H'0000 0000 H'0000 0000 H'0000 000x H'0000 000x H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1559 of 1692 REJ09B0360-0100 Section 32 List of Registers Module EDMAC Register Abbreviation EDMR EDTRR EDRRR TDLAR RDLAR EESR EESIPR TRSCER RMFCR TFTR FDR RMCR TFUCR RFOCR RBWAR RDFAR TBRAR TDFAR FCFTR RPADIR TRIMD Power-on Reset H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0707 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0007 0007 H'0000 0000 H'0000 0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1560 of 1692 REJ09B0360-0100 Section 32 List of Registers Module USB Register Abbreviation SYSCFG BUSWAIT SYSSTS DVSTCTR TESTMODE D0FBCFG D1FBCFG CFIFO D0FIFO D1FIFO CFIFOSEL CFIFOCTR D0FIFOSEL D0FIFOCTR D1FIFOSEL D1FIFOCTR INTENB0 INTENB1 BRDYENB NRDYENB BEMPENB SOFCFG Power-on Reset H'0000 H'000F H'040x H'0000 H'0000 H'0000 H'0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1561 of 1692 REJ09B0360-0100 Section 32 List of Registers Module USB Register Abbreviation INTSTS0 INTSTS1 BRDYSTS NRDYSTS BEMPSTS FRMNUM UFRMNUM USBADDR USBREQ USBVAL USBINDX USBLENG DCPCFG DCPMAXP DCPCTR PIPESEL PIPECFG PIPEBUF PIPEMAXP PIPEPERI PIPE1CTR PIPE2CTR PIPE3CTR PIPE4CTR PIPE5CTR PIPE6CTR PIPE7CTR PIPE8CTR PIPE9CTR Power-on Reset H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0040 H'0040 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1562 of 1692 REJ09B0360-0100 Section 32 List of Registers Module USB Register Abbreviation PIPE1TRE PIPE1TRN PIPE2TRE PIPE2TRN PIPE3TRE PIPE3TRN PIPE4TRE PIPE4TRN PIPE5TRE PIPE5TRN DEVADD0 DEVADD1 DEVADD2 DEVADD3 DEVADD4 DEVADD5 DEVADD6 DEVADD7 DEVADD8 DEVADD9 DEVADDA Power-on Reset H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1563 of 1692 REJ09B0360-0100 Section 32 List of Registers Module LCDC Register Abbreviation LDPR00 to LDPRFF LDICKR LDMTR LDDFR LDSARU LDSARL LDLAOR LDPALCR LDHCNR LDHSYNR LDVDLNR LDVTLNR LDVSYNR LDACLNR LDINTR LDPMMR LDPSPR LDCNTR LDUINTR LDUINTLNR LDLIRNR Power-on Reset Undefined H'1101 H'0109 H'000C H'04000000 H'04000000 H'0280 H'0000 H'4F52 H'0050 H'01DF H'01DF H'01DF H'000C H'0000 H'0010 H'F60F H'0000 H'0000 H'004F H'0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1564 of 1692 REJ09B0360-0100 Section 32 List of Registers Module G2D Register Abbreviation SCLR SR SRCR IER ICIDR RTN0R RTN1R DLSAR SSAR RSAR WSAR SSTRR DSTRR ENDCVR STCR DTCR ALPHR COFSR RCLR CSTR CURR LCOR SCLMAR Power-on Reset H'8000 0000 Undefined H'0000 0000 H'0000 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined Undefined Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1565 of 1692 REJ09B0360-0100 Section 32 List of Registers Module G2D Register Abbreviation UCLMIR UCLMAR RUCLMIR RUCLMAR RCL2R POFSR GTRCR MTRAR MTRBR MTRCR MTRDR MTRER MTRFR MTRGR MTRHR MTRIR GTROFSXR GTROFSYR ZCLPMINR ZCLPMAXR ZSATVMINR Power-on Reset Undefined Undefined Undefined Undefined H'0000 4004 H'0000 0000 H'0000 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Rev. 1.00 Nov. 22, 2007 Page 1566 of 1692 REJ09B0360-0100 Section 32 List of Registers Module VDC2 graphics block 1 Register Abbreviation GRCMEN1 GRCBUSCNT1 GROPSADR1 GROPSWH1 GROPSOFST1 GROPDPHV1 Power-on Reset H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained GROPBASERGB1 H'0000 0000 VDC2 graphics block 2 GRCMEN2 GRCBUSCNT2 GROPSADR2 GROPSWH2 GROPSOFST2 GROPDPHV2 GROPEWH2 GROPEDPHV2 GROPEDPA2 GROPCRKY0_2 GROPCRKY1_2 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 GROPBASERGB2 H'0000 0000 Rev. 1.00 Nov. 22, 2007 Page 1567 of 1692 REJ09B0360-0100 Section 32 List of Registers Module VDC2 graphics block 3 Register Abbreviation GRCMEN3 GRCBUSCNT3 GROPSADR3 GROPSWH3 GROPSOFST3 GROPDPHV3 GROPEWH3 GROPEDPHV3 GROPEDPA3 GROPCRKY0_3 GROPCRKY1_3 Power-on Reset H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained GROPBASERGB3 H'0000 0000 VDC2 graphics block 4 GRCMEN4 GRCBUSCNT4 GROPSADR4 GROPSWH4 GROPSOFST4 GROPDPHV4 GROPEWH4 GROPEDPHV4 GROPEDPA4 GROPCRKY0_4 GROPCRKY1_4 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 GROPBASERGB4 H'0000 0000 Rev. 1.00 Nov. 22, 2007 Page 1568 of 1692 REJ09B0360-0100 Section 32 List of Registers Module VDC2 display control block Register Abbreviation SGMODE SGINTCNT SYNCNT EXTSYNCNT SYNSIZE VSYNCTIM HSYNCTIM CLSTIM SPLTIM COMTIM SGDESTART SGDESIZE CDECRKY T1004CNT T1004OFFSET Power-on Reset H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'020D 035A H'0000 0001 H'0000 000A H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained FLCTL FLCMNCR FLCMDCR FLCMCDR FLADR FLADR2 FLDATAR FLDTCNTR FLINTDMACR FLBSYTMR FLBSYCNT FLDTFIFO FLECFIFO FLTRCR Rev. 1.00 Nov. 22, 2007 Page 1569 of 1692 REJ09B0360-0100 Section 32 List of Registers Module SRC Register Abbreviation SRCID SRCOD SRCIDCTRL SRCODCTRL SRCCTRL SRCSTAT Power-on Reset H'0000 0000 H'0000 0000 H'0000 H'0000 H'0000 H'0002 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0002 H'AAAA H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained GPIO PTIO_A PTIO_B PTIO_C PTIO_D PTIO_E PTIO_F PTIO_G PTIO_H PTIO_I PTIO_J PTDAT_A PTDAT_B PTDAT_C PTDAT_D PTDAT_E PTDAT_F PTDAT_G PTDAT_H PTDAT_I PTDAT_J PTPUL_SPCL Rev. 1.00 Nov. 22, 2007 Page 1570 of 1692 REJ09B0360-0100 Section 32 List of Registers Module GPIO Register Abbreviation PTSEL_A PTSEL_B PTSEL_C PTSEL_D PTSEL_E PTSEL_F PTSEL_G PTSEL_H PTSEL_I PTSEL_J PTSEL_K PTSEL_P PTSEL_R PTSEL_S PTHIZ_A PTHIZ_B PTSEL_SPCL Power-on Reset H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 0000 H'0000 0000 H'0000 0000 H'2000 0000 H'0000 2000 Undefined Undefined H'2000 0000 H'0000 2000 Undefined Undefined Undefined Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Power-down mode*2 STBCR MSTPCR0 MSTPCR1 UBC CBR0 CRR0 CAR0 CAMR0 CBR1 CRR1 CAR1 CAMR1 CDR1 Rev. 1.00 Nov. 22, 2007 Page 1571 of 1692 REJ09B0360-0100 Section 32 List of Registers Module UBC Register Abbreviation CDMR1 CETR1 CCMFR CBCR Power-on Reset Undefined Undefined H'0000 0000 H'0000 0000 H'0EFF H'0000 Sleep Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained H-UDI SDIR SDINT Legend: O: Initialized : Retained Notes: 1. The initial value in the clock-operating mode that is selected according to the MODE0, MODE1, and MODE2 settings. 2. For the standby control register, also refer to figure 9.1, Block Diagram of CPG. Power-on Reset By RESET pin H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 By WDT/H-UDI Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Module WDT Register Abbreviation WDTST WDTCSR WDTBST WDTCNT WDTBCNT Rev. 1.00 Nov. 22, 2007 Page 1572 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Section 33 Electrical Characteristics 33.1 Absolute Maximum Ratings*1*2 Table 33.1 Absolute Maximum Ratings Item Power supply voltage (I/O) Power supply voltage (internal) Symbol V DDQ, VDDQ_USB Value –0.3 to 4.6 Unit V V VDD, VDD_PLL1, –0.3 to 1.7 VDD_PLL2, VDD_USB, UV12 VDDQA_USB VDDA_USB Vin Vbus Topr –0.3 to 4.6 –0.3 to 1.7 –0.3 to VDDQ + 0.3* –0.3 to 5.5 –20 to 85 (regular specifications) –40 to 85 (wide temperature specifications) 3 Power supply voltage (analog 3.3-V) Power supply voltage (analog 1.2-V) Input voltage Vbus input voltage Operating temperature V V V V °C Storage temperature Caution: 1 2 3 Tstg –55 to 125 °C Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Permanent damage to the LSI may result if all the VSS are not connected to GND. Do not exceed the maximum power supply voltage. Rev. 1.00 Nov. 22, 2007 Page 1573 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.2 Power-on/Power-off Sequence The sequences for turning on and off power supplies are shown below together with recommended values. 3.3 V power voltage 3.3 V minimum power voltage 1.2 V power voltage 1.2 V minimum power voltage GND tUNC Pins status undefined Normal operation period tUNC Pins status undefined 3.3 V power: VDDQ, VDDQ_USB, VDDQA_USB 1.2V power: VDD, VDD_PLL1, VDD_PLL2, VDD_USB, VDDA_USB, UV12 Figure 33.1 Power-on/Power-off Sequence Table 33.2 Recommended Time for Power-on/Power-off Sequence Item State undefined time Symbol tUNC Max. 100 Unit ms Note: The table shown above is the maximum values, so they represent guidelines rather than strict requirements. Either the 3.3-V power supply or the 1.2-V power does not matter to be turned on or turned off. An undefined time appears until either of the power supply, which turns on later, reaches above the minimum voltage and after it has reached below the minimum voltage. During these periods, pin and internal states become undefined. Design the system so that these undefined states do not cause an overall malfunction. Rev. 1.00 Nov. 22, 2007 Page 1574 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.3 DC Characteristics DC Characteristics [Common Items] Ta = –20 to 85°C, –40 to 85°C Symbol VDDQ, VDDQ _USB VDD, VDD_PLL1, VDD_PLL2, VDD_USB, UV12 VDDQA_USB VDDA_USB lDDQ + lDDQ_USB lDD + lDD_PLL1 + lDD_PLL2 + lDD_USB + UV12 Sleep mode lDDQ + lDDQ_USB lDD + lDD_PLL1 + lDD_PLL2 + lDD_USB + UV12 Refresh standby lDDQ + lDDQ_USB lDD + lDD_PLL1 + lDD_PLL2 + lDD_USB + UV12 Min. 3.0 1.15 Typ. 3.3 1.25 Max. 3.6 1.35 Unit V V Test Conditions Table 33.3 Conditions: Item Power supply voltage (I/O) Power supply voltage (Internal) Power supply voltage (analog 3.3-V) Power supply voltage (analog 1.2-V) Supply current Normal operation 3.0 1.15 3.3 1.25 3.6 1.35 150 850 V V mA mA Lck= 324 MHz SHck= Bck=108 MHz Pck= 54 MHz                     150 650 mA mA 15 450 mA mA Supply curren (USB)t Normal operation lDDQA_USB LDDA_USB lDDA_USB 15 20 600 600 mA mA µA µA Refresh standby lDDQA _USB Rev. 1.00 Nov. 22, 2007 Page 1575 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Table 33.4 DC Characteristics [Excluding the Pins Related to USB Transceiver and I2C ] Conditions: Ta = –20 to 85°C, –40 to 85°C Test Conditions VCCQ= 3.0 to 3.6 V Item Input voltage Symbol VIH PRESET, TRST, NMI, MODE8/FD7, MODE7/FD6, MODE5/FD5, MODE4/FD4, MODE3/FD3, MODE2/FD2, MODE1/FD1, MODE0/FD0, IRQ0/DTEND1, WDTOVF/IRQ1/AUDCK/DACK1, D44,IDEINT, MII_TXD2/AUDIO_CLK5/IDEINT_M/PD1, STATUS1/RTS2/PA7 STATUS0/CTS2/PA6, FCE/PA5, FRE/PA4, FEW/PA3, TXD2/PA2, RXD2/PA1, SCK2/PA0, A25/PB7/DREQ0/TRS0, A24/PB6/DACK0/CTS0, A23/PB5/DTEND0/RTS1, A22/PB4/CTS1, A21/PB3, A20/PB2, A19/PB1, A18/PB0, ASEBRKAK/BRKACK/TCLK/PC1, EXTAL, XIN Input pins other than above Min. Typ. VCCQ  × 0.9 Max. Unit VCCQ + V 0.3 2.0  VCCQ + 0.3 Rev. 1.00 Nov. 22, 2007 Page 1576 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Item Input voltage Symbol VIL PRESET, TRST, NMI, MODE8/FD7, MODE7/FD6, MODE5/FD5, MODE4/FD4, MODE3/FD3, MODE2/FD2, MODE1/FD1, MODE0/FD0, IRQ0/DTEND1, WDTOVF/IRQ1/AUDCK/DACK1, D44,IDEINT, MII_TXD2/AUDIO_CLK5/IDEINT_M/PD1, STATUS1/RTS2/PA7 STATUS0/CTS2/PA6, FCE/PA5, FRE/PA4, FEW/PA3, TXD2/PA2, RXD2/PA1, SCK2/PA0, A25/PB7/DREQ0/TRS0, A24/PB6/DACK0/CTS0, A23/PB5/DTEND0/RTS1, A22/PB4/CTS1, A21/PB3, A20/PB2, A19/PB1, A18/PB0, ASEBRKAK/BRKACK/TCLK/PC1, ESTAL, XIN Input pins other than above VIL |Iin | |Isti | Min. Typ. –0.3  Max. Unit VCCQ V × 0.1 Test Conditions VCCQ= 3.0 to 3.6 V –0.3  VCCQ V × 0.2 1.0 1.0 µA Vin = 0.5 to VCCQ – 0.5 V Input leakage current Three-state leakage current All input pins All input/output pins, output pins (off status)     Output voltage All output pins VOH 2.4   V VCCQ= 3.0 V lOH= 2 mA All output pins VOL   0.55 V VDDQ= 3.0 V IOL= 2 mA Pull-up resistance Pin capacitance All pins Others Rpull CL 20 60 180 10 kΩ pF   Note: Supply current values are the values measured when all of the output pins and pins are unloaded in the conditions; HVH (minimum) = VCCQ – 0.5 or VIL (maximum) = 0.5 V. Rev. 1.00 Nov. 22, 2007 Page 1577 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Table 33.5 DC Characteristics [Pins Related to I2C*] Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item Power supply voltage Input high voltage Input low voltage Output low voltage Output low permissible current Note: * Symbol VCCQ VIH VIL VOL IOL Min. 3.0 VCCQ × 0.7 –0.3   Typ. 3.3     Max. 3.6 VCCQ + 0.3 VCCQ × 0.3 0.4 10 Unit V V V V mA IOL = 3.0 mA Test Conditions Pins related to I2C: SCL, SDA (open-drain pins) Table 33.6 DC Characteristics [Pins Related to USB (1)] Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item Reference resistance Input high voltage (VBUS) Input low voltage (VBUS) Input high voltage (XIN) Input low voltage (XIN) Symbol RREF VIH VIL VIH VIL Min. 5.6 Ω±1% 4.02 0.0 VDDQ – 0.5 –0.3     5.25 1.0 VDDQ + 0.3 0.5 Typ. Max. Unit V V V V V Test Conditions Rev. 1.00 Nov. 22, 2007 Page 1578 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Table 33.7 DC Characteristics [Pins Related to USB (2) (for Full-Speed/High-Speed Common Items)] Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item DP pull-up resistance (when the function is selected) DP/DM pull-down resistance (when the host is selected) Symbol Rpu Min. 0.900 1.425 Rpd 14.25 Typ.    Max. 1.575 3.090 24.80 Unit kΩ kΩ kΩ Test Conditions In idle mode In transmit/receive mode Table 33.8 DC Characteristics [Pins Related to USB (3) (for Full Speed)] Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item Input high voltage Input low voltage Differential input sensitivity Differential common mode range Output high voltage Output low voltage Single-ended receiver threshold voltage Crossover voltage range Note: * Symbol VIH VIL VDI VCM VOH VOL VSE VCRS Min. 2.0  0.2 0.8 2.8 0.0 0.8 1.3 Typ.         Max.  0.8  2.5 3.6 0.3 2.0 2.0 Unit V V V V V V V V CL = 50 pF IOH = 5 mA IOL = 5 mA | (DP) – (DM) | Test Conditions Referring to the DP and DM pins Rev. 1.00 Nov. 22, 2007 Page 1579 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Table 33.9 DC Characteristics [Pins Related to USB (4) (for High Speed)] Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item Differential common mode range Symbol VHSDI Min. 0.15 100 –50 –10.0 360 –10.0 700 –900        150 500 10.0 440 10.0 1000 –500 Typ. Max. Unit V mV mV mV mV mV mV mV Test Conditions Squelch-detected threshold VHSSQ voltage (differential voltage) Common mode voltage range Idle state Output high voltage Output low voltage Chirp J output voltage (differential) Chirp K output voltage (differential) VHSCM VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK Note: Pins related to USB: DP, DM Table 33.10 DC Characteristics [Pins Related to USB (5) (for Low Speed)] Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item Input high voltage Input low voltage Symbol VLSOH VLSOL Min. 2.8  Typ.   Max.  0.3 Unit V V Test Conditions IOH= 200 µA IOL= 2 mA Note: Pins related to USB: DP, DM Rev. 1.00 Nov. 22, 2007 Page 1580 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Table 33.11 Output Permissible Current Value Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item Output low-level capacitance current Output low-level capacitance current (total) Symbol lOL Σ lOL Min.     Typ.     Max. 2 120 2 40 mA Unit mA Output high-level capacitance current – lOL Output high-level capacitance current ΣI– lOHI (total) Caution: To protect the LSI's reliability, do not exceed the output current values in table 33.11. 33.4 AC Characteristics Signals input to this LSI are basically handled as signals in synchronization with a clock. The setup and hold times for input pins must be followed. 33.4.1 Clock and Control Signal Timing Table 33.12 Clock and Control Signal Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item EXTAL clock input frequency* EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width 1 Symbol Min. fEX tEXcyc tEXL tEXH 24 30.8 7 7 Max. 32.4 42   Unit MHz ns ns ns Figure 33.2 Rev. 1.00 Nov. 22, 2007 Page 1581 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Item EXTAL clock input rise time EXTAL clock input fall time CLKOUT clock output* 2 Symbol Min. tEXr tEXf top tCLKOUTcyc tCLKOUTL tCLKOUTr tCLKOUTf tMDRS tMDRH TRESPW TOSC TTRSTRH   80 9.26 2 2   30 20 30 60 20 Max. 4 4 108 12.5   3 3      Unit ns ns MHz ns ns ns ns ns ms ns ms µs ns Figure 33.2 CLKOUT clock output cycle time CLKOUT clock output low-level pulse width 33.3 CLKOUT clock output high-level pulse width tCLKOUTH CLKOUT clock output rise time CLKOUT clock output fall time MDn reset set up time MDn reset hold time PRESET assert time Power-on oscillation settling time TRST reset hold time 33.5 33.4, 33.5 33.4 Notes: 1. The maximum frequency indicates 32.4 MHz when the crystal oscillator connects to EXTAL and XTAL. The tank circuit is required as the external circuit when the threedimensional overtone oscillator. 2. The maximum connection load capacitance to the CLOKOUT pin is 50 pF. tEXcyc tEXH tEXL EXTAL input VIH 1/2VCCQ VIH VIL tEXf VIL VIH 1/2VCCQ tEXr Note: When the clock is input on the EXTAL pin. Figure 33.2 EXTAL Clock Input Timing Rev. 1.00 Nov. 22, 2007 Page 1582 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics tCLKOUTcyc tCLKOUTH tCLKOUTL CLKOUT VOH 1/2VCCQ VOH VOL tCLKOUTf VOL VOH 1/2VCCQ tCLKOUTr Figure 33.3 CLKOUT Clock Output Timing (1) Power-on Oscillation settling time tOSC Internal clock VDD VDD min tRESPW PRESET tTRSTRH TRST CLKOUT Note: Oscillation settling time when the internal oscillator is used. Figure 33.4 Power-On Oscillation Settling Time Rev. 1.00 Nov. 22, 2007 Page 1583 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics tRESPW PRESET tMDRS MODEn tMDRH Figure 33.5 MODE Pin Setup / Hold Timing 33.4.2 Control Signal Timing Table 33.13 Control Signal Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item WDTOVF delay time STATSU0, STATUS1 delay time BREQ setup time BREQ hold time BACK delay time Bus 3-state delay time Bus buffer on time Symbol Min. tWOVD tSTD tBREQS tBREQH tBACKD tBOFF tBON   3 1.5    7 10 10 Max. tcyc + 9 tcyc + 10  Unit ns ns ns ns ns ns ns 33.7 Figure 33.6 Note: tcyc is a cycle time of CLKOUT clock. CLKOUT tSTD STATUS0 STATUS1 tWOVD WDTOVF tWOVD Figure 33.6 Pin Drive Timing in Standby Rev. 1.00 Nov. 22, 2007 Page 1584 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics CLKOUT tBREQS BREQ tBREQH BACK A25-0, CSn BS, R/W, RD, RAS, CAS, WEn, DQMLL, DQMLU, DQMUL, DQMUU tBACKD tBACKD tBREQH tBREQS tBOFF tBON Figure 33.7 Control Signal Timing Rev. 1.00 Nov. 22, 2007 Page 1585 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.4.3 Bus Timing Table 33.14 Bus Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item Address delay time BS delay time CSn delay time R/W delaytime RD delay time Read data setup time Read data hold time WEn delay time (falling edge)* WEn delay time Write data delay time RDY setup time RDY hold time RAS delay time CAS delay time CKE delay time DQM delay time Symbol Min. tAD tBSD tCSD tRWD tRSD tRDS tRDH tWEDF TWED1 tWDD tRDYS tRDYH tRASD tCASD tCKED tDQMD 1.0 1.0 1.0 1.0 1.0 3.0 1.5  1.0 1.0 3.0 1.5 1.0 1.0 1.0 1.0 Max. 7.0 7.0 7.0 7.0 7.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 33.12 to 33.23 33.9, 33.10 Figure 33.8 to 33.11   7.0 7.0 7.0   7.0 7.0 7.0 7.0 Note: This indicates the delay time for the CLKOUT rising-edge. Rev. 1.00 Nov. 22, 2007 Page 1586 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics T1 CLKOUT T2 tAD A25-A0 tAD tCSD tRWD tCSD CSn tRWD R/W tRSD RD Read D31-D0 WEn Write D31-D0 tRSD tRSD tRDS tRDH tWED1 tWEDF tWDD tWEDF tWDD tWDD tBSD BS tBSD RDY DACKn (Low-active) tDACD tDACD DTENDn (Low-active) tDTED tDTED Figure 33.8 Basic Bus Cycle in SRAM Bus Cycle (No Wait Cycle) Rev. 1.00 Nov. 22, 2007 Page 1587 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics T1 CLKOUT Tw T2 tAD A25-A0 tAD tCSD CSn tCSD tRWD R/W tRWD tRSD RD tRSD tRSD Read D31-D0 tRDS tWED1 WEn tRDH tWEDF tWEDF Write D31-D0 tWDD (write) tWDD tWDD tBSD BS tBSD tRDYS RDY tRDYH tDACD DACKn (Low-active) tDACD tDTED DTENDn (Low-active) tDTED Figure 33.9 Basic Bus Cycle in SRAM Bus Cycle (One Internal Wait Cycle) Rev. 1.00 Nov. 22, 2007 Page 1588 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics T1 CLKOUT Tw Twe T2 tAD A25-A0 tAD tCSD CSn tCSD tRWD R/W tRWD tRSD RD tRSD tRSD Read D31-D0 tRDS tWED1 WEn tRDH tWEDF tWEDF Write D31-D0 tWDD tWDD tWDD tBSD BS tBSD tRDYS RDY tRDYH tRDYS tRDYH tDACD DACKn (Low-active) tDACD DTENDn (Low-active) tDTED tDTED Figure 33.10 Basic Bus Cycle in SRAM Bus Cycle (Internal Wait Cycle + One External Wait Cycle) Rev. 1.00 Nov. 22, 2007 Page 1589 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics TS1 CLKOUT T1 T2 TH1 tAD A25 to A0 tAD tCSD CSn tCSD tRWD R/W tRWD tRSD RD Read D31 to D0 tRSD tRSD tRSD tRDS tRDH tWED1 WEn Write tWEDF tWEDF tWDD D31 to D0 tWDD tWDD tBSD BS tBSD RDY DACKn (Low-active) tDACD tDACD DTENDn (Low-active) tDTEND tDTEND Figure 33.11 Basic Bus Cycle in SRAM Bus Cycle (No Wait Cycle, Address Setup / Hold Time Insert, AnS= 1, AnH= 1) Rev. 1.00 Nov. 22, 2007 Page 1590 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Tr CLKOUT Trw Tc1 Tc2 Td1 Td2 Td3 Td4 tAD BANK BANK tAD tAD Row L tAD Precharge tAD tAD tAD Address Row tAD Col CSn tCSD tRWD tRASD tRASD tCASD tCSD tRWD R/W RAS tCASD tCASD CAS tDQMD DQMn tDQMD tRDS d0 tDQMD tRDH d1 d2 d3 D63 to D0 (Read) tBSD BS tBSD tBSD tCKED CKE DACKn (Low-active) tDACD tDACD tDACD DTENDn (Low-active) tDTED tDTED tDTED Figure 33.12 SRAM Bus Cycle in Bank Open Mode Read Bus Cycle (ACT-READ) (BOMODE[1:0]= 00, SCL[2:0]= 000, SRCD= 0, CAS Latency= 2cyc, IRCD= 2cyc) Rev. 1.00 Nov. 22, 2007 Page 1591 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Tpr CLKOUT Tpc Tr Trw Tc1 Tc2 Td1 Td2 Td3 Td4 tAD BANK BANK tAD tAD L Row tAD Precharge tAD L tAD tAD tAD Address Row tAD Col CSn tCSD tRWD tCSD tRWD tCSD tCSD R/W tRASD RAS tRASD tRASD tRASD tCASD CAS tCASD tDQMD tCASD tDQMD tRDS tRDH d0 d1 d2 d3 tDQMD DQMn D63 to D0 (Read) tBSD BS tBSD tBSD tCKED CKE DACKn (Low-active) DTENDn tDACD tDTED tDACD tDTED tDACD tDTED (Low-active) Figure 33.13 SRAM Bus Cycle in Bank Open Mode Pre-charge Read Bus Cycle (PRE-ACT-READ) (BOMODE[1:0]= 00, SRP[1:0]= 00, SCL[2:0]= 000, SRCD=0, IRP= 2cyc, CAS Latency= 2cyc, IRCD= 2cyc) Rev. 1.00 Nov. 22, 2007 Page 1592 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Tc1 CLKOUT Tc2 Td1 Td2 Td3 Td4 tAD BANK Row tAD tAD L tAD Precharge tAD Address Col tAD CSn tCSD tRWD tRASD tCSD R/W RAS tCASD CAS tCASD tDQMD DQMn tDQMD tRDS d0 D63 to D0 (Read) tRDH d1 d2 d3 tBSD BS tBSD tBSD tCKED CKE DACKn (Low-active) tDACD tDACD tDACD DTENDn (Low-active) tDTED tDTED tDTED Figure 33.14 SRAM Bus Cycle in Bank Open Mode Read Bus Cycle (Read) (BOMODE[1:0]= 00, SCL[2:0]= 000, SRCD=0, CAS Latency= 2cyc, IRCD= 2cyc) Rev. 1.00 Nov. 22, 2007 Page 1593 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Tr CLKOUT Trw Tc1 Tc2 Tc3 Tc4 tAD BANK BANK tAD tAD Row L tAD Precharge tAD tAD tCSD tAD Address Row tAD Col CSn tCSD tRWD tRASD tRASD tCASD tRWD tRWD R/W RAS tCASD tCASD CAS tDQMD DQMn tDQMD tWDD tWDD d0 d1 d2 d3 tDQMD D63 to D0 (Read) tBSD BS tBSD tBSD tCKED CKE DACKn (Low-active) tDACD tDACD tDACD DTENDn (Low-active) tDTED tDTED tDTED Figure 33.15 SRAM Bus Cycle in Bank Open Mode Write Bus Cycle (ACT-WRITE) (BOMODE[1:0]= 00, SRCD= 0, IRCD= 2cyc) Rev. 1.00 Nov. 22, 2007 Page 1594 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Tpr CLKOUT Tpc Tr Trw Tc1 Tc2 Tc3 Tc4 tAD BANK Bank tAD tAD L Row tAD Precharge tAD L tAD tAD tCSD tAD Address Row tAD Col tCSD CSn tCSD tCSD tRWD R/W tRWD tRASD tRASD tRASD tRWD tRWD tRASD RAS tCASD CAS tCASD tCASD tDQMD DQMn tDQMD tWDD d0 d1 d2 d3 tDQMD D63 to D0 (Write) tWDD tBSD tBSD tBSD BS tCKED CKE DACKn (Low-active) DTENDn (Low-active) tDACD tDTED tDACD tDTED tDACD tDTED Figure 33.16 SRAM Bus Cycle in Bank Open Mode Pre-charge Write Bus Cycle (PRE-ACT-SRITE) (BOMODE[1:0]= 00, SRP[1:0]= 00, SRCD=0, IRP= 2cyc, IRCD= 2cyc) Rev. 1.00 Nov. 22, 2007 Page 1595 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Tc1 CLKOUT Tc2 Tc3 Tc4 tAD BANK tAD tAD Precharge L tAD tAD Address Col tAD tCSD CSn tCSD tRWD R/W tRWD tRASD RAS tCASD CAS tCASD tDQMD DQMn tDQMD tWDD D63 to D0 (Write) d0 tWDD d1 d2 d3 BS tBSD tCKED tBSD CKE DACKn (Low-active) tDACD tDACD DTENDn (Low-active) tDTED tDTED Figure 33.17 SRAM Bus Cycle in Bank Open Mode Write Bus Cycle (WRITE) (BOMODE[1:0]= 00, SRCD= 0, IRCD= 2cyc) Rev. 1.00 Nov. 22, 2007 Page 1596 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Tr CLKOUT tAD BANK BANK tAD Precharge Row tAD Row tCSD Trw Tc1 Tc2 Td1 Td2 tAD tAD H tAD Col tAD tAD tCSD Address CSn tRWD R/W tRASD RAS tCASD CAS tDQMD DQMn tRDS D63 to D0 d0 tBSD tBSD tRDH d1 tBSD d2 d3 tDQMD tDQMD tCASD tCASD tRASD BS tCKED CKE DACKn (Low-active) DTENDn (Low-active) tDACD tDACD tDACD tDTED tDTED tDTED Figure 33.18 SRAM Bus Cycle in Bank Close Mode Read Bus Cycle (ACT-READA) (BOMODE[1:0]= 1, SCL[2:0]= 000, SRCD= 0, IRP= 2cyc, CAS Latency= 2cyc) Rev. 1.00 Nov. 22, 2007 Page 1597 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Tr CKIO Trw Tc1 Tc2 Tc3 Tc4 Tpc Tpc Tpc tAD BANK BANK tAD tAD Row H tAD Precharge tAD tAD tCSD tAD Address Row tAD Col CSn tCSD tRWD tRWD tRWD R/W tRASD RAS tRASD tCASD tCASD tCASD CAS tDQMD DQMn tDQMD tWDD tWDD d0 d1 d2 d3 tDQMD D63 to D0 (write) tBSD BS tBSD tBSD CKE tCKED tDACD tDTED tDACD tDTED tDACD tDTED DACKn (Low-active) DTENDn (Low-active) Figure 33.19 SRAM Bus Cycle in Bank Close Mode Write Bus Cycle (ACT-WRITEA) (BOMODE[1:0]= 00, SWR[1:0]= 00, SRP[1:0]= 00, SRCD= 0, IDAL= 4cyc, IRCD= 2cyc) Rev. 1.00 Nov. 22, 2007 Page 1598 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics TRp1 CLKOUT tAD BANK tAD H TRp2 tAD tAD Precharge Address tCSD CSn tRWD R/W tRASD RAS tCASD CAS tDQMD DQMn tWDD D63 to D0 tBSD BS tCKED tRASD tRWD tCSD CKE DACKn (Low-active) DTENDn (Low-active) tDACD tDTED Figure 33.20 SRAM Bus Cycle in Pre-charge Cycle (PALL) (SRP[1:0]= 00, IRP= 2cyc) Rev. 1.00 Nov. 22, 2007 Page 1599 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics TMr1 CLKOUT tAD BANK L tAD L tAD tCSD CSn tRWD R/W tRASD RAS tCASD CAS tDQMD DQMn tWDD D63 to D0 tBSD BS tCKED TMr2 tAD tAD Precharge tAD Address tCSD tRWD tRASD tCASD CKE DACKn (Low-active) DTENDn (Low-active) tDACD tDACD tDTED tDTED Figure 33.21 SRAM Bus Cycle in Mode Register Setting Cycle (MRS) Rev. 1.00 Nov. 22, 2007 Page 1600 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics TRf1 CLKOUT tAD BANK tAD TRf2 TRf3 TRf4 TRf5 TRf6 TRf7 TRf8 tAD tAD Precharge tAD Address tCSD CSn tRWD R/W tRASD RAS tCASD CAS tDQMD DQMn tWDD D63 to D0 tBSD BS tCKED tCASD tRASD tCSD tAD CKE DACKn (Low-active) DTENDn (Low-active) tDACD tDTED Figure 33.22 SRAM Bus Cycle in Auto Refresh Cycle (REF) (SRFC[2:0]= 000, IRC= 8cyc) Rev. 1.00 Nov. 22, 2007 Page 1601 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics TSRf CLKOUT tAD BANK tAD TRf1 TRf2 TRf3 TRf4 TRf5 TRf6 TRf7 TRf8 tAD tAD Precharge tAD Address tCSD CSn tRWD R/W tRASD RAS tCASD CAS tDQMD DQMn tWDD D63 to D0 tBSD BS tCKED tCKED tCKED tCASD tRASD tCSD tAD CKE DACKn (Low-active) DTENDn (Low-active) tDACD tDTED Figure 33.23 SRAM Bus Cycle in Refresh Cycle (SREF) Rev. 1.00 Nov. 22, 2007 Page 1602 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.4.4 INTC Module Signal Timing Table 33.15 INTC Module Signal Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item NMI pulse width (high) NMI pulse width (low) IRQ1, IRQ0 setup time IRQ1, IRQ0 hold time PINTn interrupt setup time PINTn interrupt hold time IRQOUT output delay time Symbol Min. tNMIH tNMIL tIRQS tTIRQH tGPIOS tGPIOH tIRQOD 5 5 8 3 15 8  Max.       13 Unit tcyc tcyc ns ns ns ns ns 33.25 Figure 33.24 Note Regular state, Sleep state Regular state, sleep state IRQ input IRQ input GPIO interrupt input GPO interrupt input IRQOUT output Note: tcyc is a cycle time of CLKOUT clock. tNMIH tNMIL NMI Figure 33.24 NMI Input Timing Rev. 1.00 Nov. 22, 2007 Page 1603 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics CLKOUT IRQn, PINTn tIRQS tGPIOS tIRQH tGPIOH IRQOUT tIRQOD Figure 33.25 IRQ, PINT Input, IRQOUT Output Timing Rev. 1.00 Nov. 22, 2007 Page 1604 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.4.5 DMAC Module Signal Timing Table 33.16 DMAC Module Signal Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Module DMAC Item DREQn setup time DREQn hold time DTENDn delay time DACKn delay time Symbol Min. tDRQS tDRQH tDTED tDACD 6 4 1.0 1.0 Max. Unit   8 8 ns ns ns ns 33.26, 33.8 to 33.23 Figure 33.26 CLKOUT tDRQH DREQ tDRQH tDRQS tDRQS DTEND, DACK tDTED tDACD Figure 33.26 DREQ/DTEND/DACK Timing 33.4.6 TMU Module Signal Timing Table 33.17 TMU Module Signal Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Module TMU Item Timer clock pulse width (high) Timer clock pulse width (low) Timer clock rising time Timer clock falling time Symbol Min. tTCLKWH tTCLKWL tTCLKr tTCLKf 4 4   Max. Unit   0.8 0.8 tPcyc tPcyc tPcyc tPcyc Figure 33.27 Note: tpcyc indicates the peripheral clock (Pck) cycle. Rev. 1.00 Nov. 22, 2007 Page 1605 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics TCLK tTCLKWH tTCLKWL tTCLKf tTCLKr Figure 33.27 TCLK Input Timing 33.4.7 IIC Module Signal Timing Table 33.18 I2C Module Signal Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item Symbol Min. Typ. Max. Unit Figure SCL frequency SCL, SDA input rise time SDA bus free time SCL start condition input hold time SCL retransmit start condition setup time tICYC tICF tICBF tICH tICS 0  1.3 0.6 0.6 0.6 100 0         400 300      0.9 kHz ns µs µs µs ns ns ns 33.28, 33.29 RP⋅CB= –9 257 × 10 to –9 275 × 10 [Ω⋅ pF] VPU= 3.3 V SDA stop condition setup tICST time SDA setup time SDA hold time tDAS tICDH Rev. 1.00 Nov. 22, 2007 Page 1606 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics P S tICBF Sr P SDA tICST tICF tICH tICS tDAS SCL tICDH tICF tICYC [Legend] S: Start condition P: Stop condition Sr: Start condition for retransmission Figure 33.28 I2C Timing This LSI VPU RP SDA SCL CB Figure 33.29 AC Characteristics Load Condition Rev. 1.00 Nov. 22, 2007 Page 1607 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.4.8 SCIF Module SignalTiming Table 33.19 SCIF Module Signal Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item Input clock cycle Clocked synchronous Asynchronous Input clock rising time Input clock falling time Input clock width Transfer data delay time (Clocked synchronous) Receive data setup time (Clocked synchronous) Receive data hold time (Clocked synchronous) tSCKr tSCKf tSCKW tTXD tRXS tRXH Symbol Min. tScyc 12 4   0.4  Max.   1.5 1.5 0.6 Unit tpcyc tpcyc tpcyc tpcyc tScyc 33.31 Figure 33.30 3 × tpcyc +15 tpcyc ns ns 4 × tpcyc +15  100  Note: tpcyc indicates the peripheral clock (ck) cycle. tSCKW SCK tSCKr tSCKf tScyc Figure 33.30 SCK Input Clock Timing tScyc SCK (Input/Output) tTXD TxDn (Data transmission) tRXS tRXH RxDn (Data reception) Figure 33.31 SCIF Input/Output Timing in Clocked Synchronous Mode Rev. 1.00 Nov. 22, 2007 Page 1608 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.4.9 SSI Module Signal Timing Table 33.20 SSI Module Signal Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item Output clock frequency Input clock frequency Clock high Clock low Clock rise time Delay Setup time Hold time AUDIO_CLK frequency Symbol tO tI tHC tLC tRC tDTR tSR tHTR fAUDIO Min. 160 160 40 40   20 10 3.072 Typ.          Max. 3364 3364   20 30   Unit ns ns ns ns ns ns ns ns Output (100 pF) Transmit Receive Receive 33.37 33.33, 33.34 33.35, 33.36 Remarks Output Input Bidirectional Figure 33.32 24.576 MHz tHC tLC tRC SSISCKn tI ,tO Figure 33.32 Clock Input/Output Timing Rev. 1.00 Nov. 22, 2007 Page 1609 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics SSISCKn tDTR SSIWSn, SSIDATAn tDTR Figure 33.33 SSI Transmit Timing (1) SSISCKn tDTR SSIWSn, SSIDATAn tDTR Figure 33.34 SSI Transmit Timing (2) SSISCKn tSR SSIWSn, SSIDATAn tHTR Figure 33.35 SSI Receive Timing (1) Rev. 1.00 Nov. 22, 2007 Page 1610 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics SSISCKn tSR SSIWSn, SSIDATAn tHTR Figure 33.36 SSI Receive Timing (2) fAUDIO AUDIO_CLKn Figure 33.37 AUDIO_CLK Timing Rev. 1.00 Nov. 22, 2007 Page 1611 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.4.10 ATAPI Interface Module Signal timing Table 33.21 ATAPI Interface Resister Access Timing in PIO Transmission Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Symbol and Item for Register Access in PIO Transmission (max/min) t0 t1 t2 t2i t3 t4 t5 t6 t6z t9 Cycle Time Address setup time IDEIORD/IDEIOWR pulse width 8-bit (min) (min) (min) Mode 0 ns 600 70 290  60 30 50 5 30 20 0 35 (max) (max) 1250 5 Mode 1 ns 383 50 290  45 20 35 5 30 15 0 35 1250 5 Mode 2 ns 330 30 290  30 15 20 5 30 10 0 35 1250 5 Mode 3 ns 180 30 80 70 30 10 20 5 30 10 0 35 1250 5 Mode 4 ns 120 25 70 25 20 10 20 5 30 10 0 35 1250 5 Figure 33.38 IDEIORD/IDEIOWR recovery time (min) IDEIOWR data setup time IDEIOWR data hold time IDEIORD data setup time IDEIORD data hold time IDEIORD three-state delay time Address hold time (min) (min) (min) (min) (max) (min) (min) tRD IDEIORDY read data valid time tA tB tC IDEIORDY setup time IDEIORDYpulse time IDEIORDY time from negate to high-impedance Rev. 1.00 Nov. 22, 2007 Page 1612 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Table 33.22 ATAPI Interface Data Transmission Timing in PIO Transmission Symbol ,Item and Conditions for Data Transfer in PIO (max/min) t0 t1 t2 t2i t3 t4 t5 t6 t6z t9 Cycle time Address setup time IDEIORD/IDEIOWR pulse width8-bit IDEIORD/IDEIOWR recovery time IDEIOWR data setup time IDEIOWR data hold time IDEIORD data setup time IDEIORD data hold time IDEIORD3 state delay time Address hold time (min) (min) (min) (min) (min) (min) (min) (min) (max) (min) (min) Mode 0 ns 600 70 290  60 30 50 5 30 20 0 35 (max) (max) 1250 5 Mode 1 ns 383 50 290  45 20 35 5 30 15 0 35 1250 5 Mode 2 ns 240 30 290  30 15 20 5 30 10 0 35 1250 5 Mode 3 ns 180 30 80 70 30 10 20 5 30 10 0 35 1250 5 Mode 4 ns 120 25 70 25 20 10 20 5 30 10 0 35 1250 5 Figure 33.38 tRD IDEIORDY read data valid time tA tB tC IDEIORDY setup time IDEIORDY pulse time Time form negate to highimpedance of IDEIORDY Rev. 1.00 Nov. 22, 2007 Page 1613 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Table 33.23 ATAPI Interface Multiword Transmission Timing Symbol and Item Multiword Transmission(max/min) t0 tD tE tF tG tH tI tJ tKR tKW tLR tLW tM tN tZ Cycle tome IDEIORD/IDEIOWR pulse width IDEIORD data access time IDEIORD data hold time IDEIORD/IDEIOWR data setup time IDEIOWR data hold time IODACK setup time IODACK hold time IDEIORD negate pulse width IDEIOWR negate pulse width IDEIORD IODREQ delay time IDEIOWR IODREQ delay time IDECS[1:0] setup time IDECS[1:0] hold time IODACK 3-state delay time (min) (min) (max) (min) (min) (min) (min) (min) (min) (min) (max) (max) (min) (min) (max) Mode 0 ns 480 215 150 5 100 20 0 20 50 215 120 40 50 15 20 Mode 1 ns 150 80 60 5 30 15 0 5 50 50 40 40 30 10 25 Mode 2 ns 120 70 50 5 20 10 0 5 25 25 35 35 25 10 25 33.39 33.41, 33.42 33.39 33.41, 33.42 33.40 to 33.42 33.40 to 33.42 33.41 Figure 33.40 to 33.42 33.39 to 33.42 Rev. 1.00 Nov. 22, 2007 Page 1614 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Table 33.24 ATAPI Interface Ultra-DMA Transmission Timing Mode 0 ns min 240 112 230 15 5 70 6.2 15 5 70 6.2 0 70 230 0 150 0 max Mode 1 ns min 160 73 153 10 5 48 6.2 10 5 48 6.2 0 48 200 150 0 max Mode 2 ns min 120 54 115 7 5 31 6.2 7 5 31 6.2 0 31 170 150 0 max Mode 3 ns min 90 39 86 7 5 20 6.2 7 5 20 6.2 0 20 130 100 0 max Mode 4 ns min 60 25 57 5 5 6.7 6.2 5 5 6.7 6.2 0 6.7 120 100 33.46, 33.47, 33.51, 33.52 33.43 33.43, 33.48 33.43 33.46 to 33.48 33.51, 33.52 33.46, 33.47, 33.51, 33.52 33.43, 33.48 10 20 0 55 60 20 55 60 33.43, 33.46, 33.47 33.46, 33.47 33.43 33.43, 33.48 33.45, 33.47, 33.50, 33.52 33.43, 33.44, 33.48, 33.49 max Figure 33.44 33.44, 33.49 Symbol for Ultra-DMA t2CYCTYP tCYC t2CYC tDS tDH tDVS tDVH tCS tCH tCVS tCVH tZFS tDZFS tFS tLI tMLI tUI tAZ tZAH tZAD tENV tRFS 20 0 10 20 0 20 70 75 20 0 10 20 0 20 70 70 20 0 10 20 0 20 70 60 20 0 10 20 0 20 20 0 Rev. 1.00 Nov. 22, 2007 Page 1615 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Mode 0 ns DMA tRP tIORDYZ tZIORDY tACK 0 20 min 160 20 max Mode 1 ns min 125 20 0 20 max Mode 2 ns min 100 20 0 20 max Mode 3 ns min 100 20 0 20 max Mode 4 ns min 100 20 0 20 33.46, 33.47, 33.51, 33.52 33.43, 33.48 33.43, 33.46 to 33.48, 33.51, 33.52 33.46, 33.51 max Figure tSS 50 50 50 50 50 Rev. 1.00 Nov. 22, 2007 Page 1616 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Table 33.25 Symbol for ATAPI Interface Ultra-DMA Transmission Timing Symbol t2CYCTYP tCYC t2CYC tDS tDH tDVS tDVH tCS tCH tCVS tCVH tZFS tDZFS tFS tLI tMLI tUI tAZ tZAH tZAD tENV tRFS tRP tIORDYZ tZIORDY tACK tSS Note Average cycle time (2 cycles) Cycle time Minimum cycle time (2 cycles) Data setup time (receive side) Data hold time (receive side) Data setup time (transfer side) Data hold time (transfer side) CRC data setup time (receive side) CRC data hold time (receive side) CRC setup time (transfer side) CRC hold time (transfer side) Setup time from the strove state to the drive state of the active signal (transfer side) Setup time from the drive state to the first strove state of the active signal (transfer side) Initial STROBE time Interlock time with restriction Minimum interlock time Interlock time without restriction Output release time Output delay time Output defined time (from release) Envelope time Final STROBE time Time till assert the STOP or negate the DMARQ Time till release the IORDY Time till drive the STROBE Time for DMACK setup/hold Time for STROBE STOP Rev. 1.00 Nov. 22, 2007 Page 1617 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Table 33.26 ATAPI Interface DIRECTION Timing Mode 0 ns Item or Symbol DIRECTION fall delay time in PIO write DIRECTION_WF DIRECTION rise delay time in PIO write DIRECTION_WR min 65 max 74 Mode 1 ns min 45 max 54 Mode 2 ns min 25 max 34 Mode 3 ns min 25 max 34 Mode 4 ns min 25 max 34 Figure 33.53 47 55 47 55 47 55 47 55 47 55 Multiword DMA data out -3 DIRECTION fall delay time tMDIRECTION_F Multiword DMA data-out 7 DIRECTION rise delay time tMDIRECTION_R 116 DIRECTION fall delay time in Ultra-DMA datain CRC transmission tUDIRECTION_F(CRC) DIRECTION rise delay 17 time in Ultra-DMA datain CRC transmission tUDIRECTION_R(CRC) DIRECTION fall delay 25 time in Ultra-DMA dataout tUDIRECTION_F DIRECTION rise delay 48 time in Ultra-DMA dataout tUDIRECTION_R Time from DIRECTION 9 fall to turning ON the IDED data bus tDON Time from IDED data bus OFF status to DIRECTION rise tDON tDOFF 6 5 -3 5 -3 5     33.55 15 7 15 7 15     124 76 84 56 64 46 54 36 44 33.57, 33.58 25 17 25 17 25 17 25 17 25 34 25 34 25 34 25 34 38 43 33.59 55 48 55 48 55 48 55 48 55 33.60, 33.61 33.53, 33.55, 33.57 to 33.59 15 9 15 9 15 9 15 18 22 14 6 14 6 14 6 14 6 14 33.53, 33.55, 33.57, 33.58, 33.60, 33.61 Rev. 1.00 Nov. 22, 2007 Page 1618 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics t0 IDECS[1:0] IDEA[2:0] t1 t2 t9 t2i IDEIOWR IDEIORD Write IDED[15:0] t3 t4 Read IDED[15:0] t5 With wait cycle IDEIORDY tA Without wait cycleI DEIORDY tC With wait cycle IDEIORDY tB tC tRD High-impedance High-impedance t6 t6z Figure 33.38 PIO Data Transmission In-between Devices Rev. 1.00 Nov. 22, 2007 Page 1619 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IDECS[1:0] tM IODREQ IODACK tl tD IDEIORD IDEIOWR tE Read IDED[15:0] tG tF Write IDED[15:0] tG tH Figure 33.39 Multiword DMA Data Transmission Start Rev. 1.00 Nov. 22, 2007 Page 1620 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IDECS[1:0] t0 IODREQ IODACK tD IDEIORD IDEIOWR tE Read IDED[15:0] tG Write IDED[15:0] tG tH tG tH tF tG tF tE tKR, tKW Figure 33.40 Multiword Data Transmission Rev. 1.00 Nov. 22, 2007 Page 1621 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IDECS[1:0] tN t0 IODREQ tLR, tLW IODACK tKR, tKW IDEIORD IDEIOWR tE Read IDED[15:0] tG Write IDED[15:0] tG tH tF tZ tD tJ Figure 33.41 End of Multiword Data Transmission from Device Rev. 1.00 Nov. 22, 2007 Page 1622 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IDECS[1:0] tN t0 IODREQ IODACK tKR, tKW IDEIORD IDEIOWR tE Read IDED[15:0] tG Write IDED[15:0] tG tH tF tZ tD tJ Figure 33.42 End of Multiword Data Transmission from Host Rev. 1.00 Nov. 22, 2007 Page 1623 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IODREQ (Device) tUI IODACK (Host) tACK (STOP) IDEIOWR (Host) tACK (HDMARDY) IDEIORD (Host) tZIORDY (DSTROBE) IDEIORDY (Device) tAZ Read IDED[15:0] tACK IDECS[1:0] IDEA[2:0] tZFS tDZFS tDVS tDVH tENV tZAD tFS tENV tZAD tFS Figure 33.43 Ultra-DMA Data In-burst Start Rev. 1.00 Nov. 22, 2007 Page 1624 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics t2CYC (t2CYCTYP) tCYC (DSTROBE) IDEIORDY (Device) tDVH Read IDED[15:0] (Device) tDVS tDVH tDVS tDVH tCYC t2CYC (DSTROBE) IDEIORDY (Host) tDH Read IDED[15:0] (Host) tDS tDH tDS tDH Figure 33.44 Ultra-DMA Data In-burst IODREQ (Device) IODACK (Host) tRP (STOP) IDEIOWR (Device) (HDMARDY) IDEIORD (Device) tRFS (DSTROBE) IDEIORDY (Device) Read IDED[15:0] Figure 33.45 Ultra-DMA Data In-burst from Host Pause Rev. 1.00 Nov. 22, 2007 Page 1625 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IODREQ (Device) tMLI IODACK (Host) tLI (STOP) IDEIOWR (Host) tLI (HDMARDY) IDEIORD (Host) tSS (DSTROBE) IDEIORDY (Device) tIORDYZ tLI tACK tACK tZAH tAZ tCVS tCVH Read IDED[15:0] CRC tACK IDECS[1:0] IDEA[2:0] Figure 33.46 End of Ultra-DMA Data In-burst from Device Rev. 1.00 Nov. 22, 2007 Page 1626 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IODREQ (Device) tLI tMLI IODACK (Host) tRP (STOP) IDEIOWR (Host) tZAH tAZ tACK tACK (HDMARDY) IDEIORD (Host) tRFS (DSTROBE) IDEIORDY (Device) tCVS Read IDED[15:0] tCVH tLI tMLI tIORDYZ CRC tACK IDECS[1:0] IDEA[2:0] Figure 33.47 End of Ultra-DMA Data In-burst from Host Rev. 1.00 Nov. 22, 2007 Page 1627 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IODREQ (Device) tUI IODACK (Host) tACK (STOP) IDEIOWR (Host) tZIORDY (DDMARDY) IDEIORDY (Device) tACK (HSTROBE) IDEIORD (Host) tDZFS tDVS Read IDED[15:0] tACK IDECS[1:0] IDEA[2:0] tDVH tLI tUI tENV Figure 33.48 Ultra-DMA Data Out-burst Start Rev. 1.00 Nov. 22, 2007 Page 1628 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics t2CYC tCYC (HSTROBE) IDEIORD (Host) tDVH Write IDED[15:0] (Host) tDVS tDVH tDVS tDVH tCYC t2CYC (HSTROBE) IDEIORD (Device) tDH Write IDED[15:0] (Device) tDS tDH tDS tDH Figure 33.49 Ultra-DMA Data Out-burst tRP IODREQ (Device) IODACK (Host) (STOP) IDEIOWR (Device) (DDMARDY) IDEIORDY (Device) tRFS (HSTROBE) IDEIORD (Device) Read IDED[15:0] (Host) Figure 33.50 Ultra-DMA Data Out-burst from Device Pause Rev. 1.00 Nov. 22, 2007 Page 1629 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics tLI IODREQ (Device) tMLI tLI IODACK (Host) tSS (STOP) IDEIOWR (Host) tIORDYZ (DDMARDY) IDEIORDY (Device) tLI tACK tACK (HSTROBE) IDEIORD (Host) tCVS Read IDED[15:0] (Host) tCVH CRC tACK IDECS[1:0] IDEA[2:0] Figure 33.51 End of Ultra-DMA Data Out-burst from Host Rev. 1.00 Nov. 22, 2007 Page 1630 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IODREQ (Device) IODACK (Host) tLI (STOP) IDEIOWR (Host) tRP tMLI tACK tIORDYZ (DDMARDY) IDEIORDY (Device) tRFS (HSTROBE) IDEIORD (Host) tCVS tCVH Read IDED[15:0] (Host) tLI tMLI tACK CRC tACK IDECS[1:0] IDEA[2:0] Figure 33.52 End of Ultra-DMA Data Out-burst from Device Rev. 1.00 Nov. 22, 2007 Page 1631 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IDECS[1:0] IDEA[2:0] (Out) IDEIOWR (Out) tDIRECTION_WF tDIRECTION_WR DIRECTION (Out) Write tDON IDED[15:0] (Out) Write tDOFF Figure 33.53 PIO Data Transmission (DIRECTIO) to Device IDECS[1:0] IDEA[2:0] (Out) IDEIORD (Out) DIRECTION (Out) Read IDED[15:0] (In) Read Figure 33.54 PIO Data Transmission (DIRECTIO) from Device Rev. 1.00 Nov. 22, 2007 Page 1632 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IDECS[1:0] IDEA[2:0] IODREQ IODACK IDEIOWR IDEIORD DIRECTION (Out) IDED[15:0] Read Read tMDIRECTION_F DIRECTION (Out) IDED[15:0] (Out) Write tDON Write tMDIRECTION_R tDOFF Figure 33.55 Multiword DMA Transmission (DIRECTION) Rev. 1.00 Nov. 22, 2007 Page 1633 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IODREQ IODACK (STOP) IDEIOWR (HDMARDY) IDEIORD (DSTROBE) IDEIORDY DIRECTION (Out) IDED[15:0] (In) IDECS[1:0] IDEA[2:0] Figure 33.56 Ultra-DMA Transmission Data In-burst Start(DIRECTION) Rev. 1.00 Nov. 22, 2007 Page 1634 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IODREQ IODACK (STOP) IDEIOWR (HDMARDY) IDEIORD (DSTROBE) IDEIORDY tUDIRECTION_R (CRC) tUDIRECTION_F (CRC) DIRECTION (Out) tDON tDOFF IDED[15:0] Data output IDECS[1:0] IDEA[2:0] Figure 33.57 End of Ultra-DMA Transmission Data In-burst from Device (DIRECTION) Rev. 1.00 Nov. 22, 2007 Page 1635 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IODREQ IODACK (STOP) IDEIOWR (HDMARDY) IDEIORD (DSTROBE) IDEIORDY tUDIRECTION_R (CRC) tUDIRECTION_F (CRC) DIRECTION (Out) tDON tDOFF IDED[15:0] Data output IDECS[1:0] IDEA[2:0] Figure 33.58 End of Ultra-DMA Transmission Data In-burst from Host (DIRECTION) Rev. 1.00 Nov. 22, 2007 Page 1636 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IODREQ IODACK (STOP) IDEIOWR (DDMARDY) IDEIORDY (HSTROBE) IDEIORD tUDIRECTION_F DIRECTION IDED[15:0] tDON IDECS[1:0] IDEA[2:0] Figure 33.59 Ultra-DMA Transmission Data Out-burst Start (DIRECTION) Rev. 1.00 Nov. 22, 2007 Page 1637 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IODREQ IODACK (STOP) IDEIOWR (DDMARDY) IDEIORDY (HSTROBE) IDEIORD tUDIRECTION_R DIRECTION tDOFF IDED[15:0] IDECS[1:0] IDEA[2:0] Figure 33.60 End of Ultra-DMA Transmission Data Out-burst from Host (DIRECTION) Rev. 1.00 Nov. 22, 2007 Page 1638 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics IODREQ IODACK (STOP) IDEIOWR (DDMARDY) IDEIORDY (HSTROBE) IDEIORD tUDIRECTION_R DIRECTION tDOFF IDED[15:0] IDECS[1:0] IDEA[2:0] Figure 33.61 End of Ultra-DMA Transmission Data Out-burst from Device (DIRECTION) Rev. 1.00 Nov. 22, 2007 Page 1639 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.4.11 USB Module Signal Timing Table 33.27 USB Module Clock Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item USB_CLK external input clock frequency (48 MHz) Clock riseing time Clock falling time Duty (tHIGH/tLOW) Symbol tFREQ tR48 tF48 tDUTY Min. 47.9   90 Max. 48.1 2 2 110 Unit MHz ns ns % Figure 33.62 tFREQ tHIGH 90 % 10 % tLOW USB_CLK (input) tR48 tF48 Figure 33.62 USB Clock Timing Table 33.28 USB Electrical Characteristics (for Full Speed) Item Transition time (rising)*2 Transition time (falling)*2 Rising/ falling time matching Symbol tR tF tRFM Min. 4 4 90 1.3 Max. 20 20 111 2.0 Unit ns ns % V Condition*1 CL= 50 pF CL= 50 pF (TR/TF)  Output signal crossover voltage VCRS Notes: The values are measured under the condition that the capacitor for edge control CEDGE = 47pF is connected to the serial resistor Rs = 45Ω. 1. The condition is that CL = 50pF unless otherwise specified. 2. Within 10 to 90% of the signal voltage. Rev. 1.00 Nov. 22, 2007 Page 1640 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Table 33.29 USB Electrical Characteristics (for Low Speed) Item Transition time (rising) Transition time (falling) Rising/ falling time matching Symbol tR tF tRFM Min. 75 75 80 1.3 Max. 300 300 125 2.0 Unit ns ns % V (TR/TF)  Condition Output signal crossover voltage VCRS Notes: The values are measured under the condition that the capacitor for edge control CEDGE = 47pF is connected to the serial resistor Rs = 22Ω.GPIO Signal Timing. * Within 10 to 90% of signal voltage. 33.4.12 GPIO Signal Timing Table 33.30 GPIO Signal Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item GPIO output delay time GPIO input setup time GPIO input hold time Symbol tIOPK tIOPS tIOPH Min.  17 Max. 17  Unit ns ns ns Figure 33.63 TCLKOUTcyc  CLKOUT tIOPD GPIO output tIOPS GPIO input tIOPH Figure 33.63 GPIO Timing Rev. 1.00 Nov. 22, 2007 Page 1641 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.4.13 H-UDI Module Signal Timing Table 33.31 H-UDI Module Signal Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Module H-UDI Item Input clock cycle Input clock pulse width (High) Input clock pulse width (Low) Input clock rise time Input clock fall time ASEBRKAK/BRKACK setup time ASEBRKAK/BRKACK hold time TDI/TMS setup time TDI/TMS hold time TDO data delay time ASEBRKAK/BRKACK pulse width Symbol tTCKcyc tTCKH tTCKL tTCKr tTCKf tASEBRKS tASEBRKH tTDIS tTDIH tTDO tPINBRK Min. 50 15 15   10 10 15 15 0 2 Max. Unit    10 10     15  ns ns ns ns ns tcyc tcyc ns ns ns tPcyc 33.67 33.66 33.65 Figure 33.64, 33.66 33.64 Notes: 1. tcyc indicates the CLKOUT clock cycle. 2. tpcyc indicates the peripheral clock (Pck) cycle. tTCKcyc tTCKH tTCKL VIH 1/2VCCQ tTCKr TCK 1/2VCCQ VIH VIH VIL tTCKf VIL Note: When the clock is input on the TCK pin. Figure 33.64 TCK Input Timing Rev. 1.00 Nov. 22, 2007 Page 1642 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics PRESET tASEBRKS ASEBRKAK/BRKACK tASEBRKH Figure 33.65 PRESET Hold Timing tTCKcyc TCK TDI TMS tTDIS tTDIH TDO tTDO Figure 33.66 H-UDI Data Transmission Timing tPINBRK ASEBRKAK/BRKACK Figure 33.67 ASEBRKAK/BRKACK Pin Break Timing Rev. 1.00 Nov. 22, 2007 Page 1643 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.4.14 EtherC Module Signal Timing Table 33.32 Ether Net Controller Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item TX-CLK cycle time TX-EN output delay time MII_TXD[3:0] output delay time CRS setup time CRS hold time COL setup time COL hold time RX-CLK cycle time RX-DV setup time RX-DV hold time MII_RXD[3:0] setup time MII_RXD[3:0] hold time RX-ER setup time RX-ER hold time MDIO setup time MDIO hold time MDIO output data hold time* WOL output delay time EXOUT output delay time Note: * Symbol tTcyc tTENd tMTDd tCRSs tCRSh tCOLs tCOLh tRcyc tRDVs tRDVh tMRDs tMRDh tRERs tRERh tMDIOs tMDIOh tMDIOdh tWOLd tEXOUTd Min. 40 1 1 10 10 10 10 40 10 10 10 10 10 10 10 10 5 1 1 Max.  20 20              18 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 33.73 33.74 33.75 33.72 33.71 33.70 33.69 Figure 33.68 Operate the internal register (PIR) in PHY block to meet the requirement of this specification. Rev. 1.00 Nov. 22, 2007 Page 1644 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics TX-CLK tTEND TX-EN tMTDD MII_TXD[3:0] Preamble SFD DATA CRC TX-ER tCRSS CRS tCRSH COL Figure 33.68 MII Transmission Timing (during Normal Operation) TX-CLK TX-EN Preamble JAM MII_TXD[3:0] TX-ER CRS tCOLS COL tCOLH Figure 33.69 MII Transmission Timing (in the Event of a Collision) Rev. 1.00 Nov. 22, 2007 Page 1645 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics RX-CLK tRDVS RX-DV tMRDS MII_RXD[3:0] Preamble SFD DATA CRC tRDVH tMRDH RX-ER Figure 33.70 MII Receive Timing (during Normal Operation) RX-CLK RX-DV MII_RXD[3:0] Preamble SFD DATA tRERS tRERH XXXX RX-ER Figure 33.71 MII Receive Timing (in the Event of a Collision) MDC tMDIOS MDIO tMDIOH Figure 33.72 MDIO Input Timing MDC tMDIODH MDIO Figure 33.73 MDIO Output Timing Rev. 1.00 Nov. 22, 2007 Page 1646 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics RX-CLK tWOLD WOL Figure 33.74 WOL Output Timing CLKOUT tEXOUTD EXOUT Figure 33.75 EXOUT Output Timing Rev. 1.00 Nov. 22, 2007 Page 1647 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.4.15 FLCTL Module Signal Timing Table 33.33 NAND Flush Memory Interface Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item Command output setup time Command output hold time Data output setup time Data output hold time Command address transmission time 1 Command address transmission time2 FEW cycle time FEW low pulse width FEW high pulse width Address ready/busy transmission time Ready/busy data read transmission time 1 Ready/busy data read transmission time 2 FRE cycle time FRE low pulse width FRE high pulse width Read data setup time Read data hold time Data write setup time time Command status read transmission time Command output off status read transmission time Status read setup time Note: Symbol tNCDS tNCDH tNDOS tNDOH tNCDAD1 tNCDAD2 tNWC tNWP tNWH tNADRB tNRBDR1 tNRBDR2 tNSCC tNSP tNSPH tNRDS tNRDH tNDWS tNCDSR tNCDFSR tNSTS Min. 2 × tfcyc –10 1.5 × tfcyc –5 0.5 × tfcyc –5 Max.    Unit ns ns ns ns ns ns ns ns ns 32 × tpcyc            ns ns ns ns ns ns ns ns ns ns ns ns 33.79 33.80 33.78, 33.80 33.78 33.78, 33.80 33.76, 33.77, 33.79, 33.80 33.76, 33.77 33.77 33.77, 33.79 33.76, 33.77, 33.79, 33.80 33.77, 33.79 33.77, 33.78 33.78 Figure 33.76, 33.80 0.5 × tfcyc –10  1.5 × tfcyc –10  2 × tfcyc –10 tfcyc –5 0.5 × tfcyc –5 0.5 × tfcyc –5  1.5 × tfcyc 32 × tpcyc tfcyc –5 0.5 × tfcyc –5 0.5 × tfcyc –5 14 0 32 × tpcyc 4 × tfcyc 3.5 × tfcyc 2.5 × tfcyc   tcyc indicates one cycle time of the FLCTL clock. Rev. 1.00 Nov. 22, 2007 Page 1648 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics FCE (Low) FCLE tNCDAD1 FALE tNCDS FWE (High) FRE tNDOS FD7 to 0 (High) FR/B tNDOH tNWP tNCDH Command Figure 33.76 NAND Flush Memory Command Issue Timing FCE (Low) FCLE tNWC FALE tNCDAD2 FWE (High) FRE tNDOS tNDOH tNDOS tNDOH tNDOS tNDOH FD7 to 0 (High) FR/B Address Address Address tNADRB tNWP tNWH tNWP tNWH tNWP tNCDAD1 Figure 33.77 NAND Flush Memory Address Issue Timing Rev. 1.00 Nov. 22, 2007 Page 1649 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics FCE (Low) FCLE (Low) FALE (High) FWE tNRBDR2 FRE tNRDS tNRDH tNRDS FD7 to 0 tNADRB FR/B tNRBDR1 Data tNRDS tNRDH Data tNSP tNSPH tNSP tNSP tNSCC Figure 33.78 NAND Flush Memory Data Read Timing FCE (Low) FCLE (Low) tNWC FALE tNDWS FWE (High) FRE tNDOS tNDOH tNDOS FD7 to 0 (High) FR/B Data tNDOS tNDOH Data tNWP tNWH tNWP tNWP Figure 33.79 NAND Flush Memory Data Write Timing Rev. 1.00 Nov. 22, 2007 Page 1650 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics FCE (Low) FCLE (Low) tNCDS FWE FRE tNDOS FD7 to 0 (High) FR/B tNDOH tNWP tNCDH tNCDSR tNSTS tNSP FALE tNCDFSR tNRDS tNRDH Command Status Figure 33.80 NAND Flush Memory Status Read Timing Rev. 1.00 Nov. 22, 2007 Page 1651 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.4.16 LCDC Module Signal Timing Table 33.34 LCDC Module Signal timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item LCD_CLK input clock frequency LCD_CLK input clock rise time LCD_CLK input clock fall time LCD_CLK input clock duty Clock (LCD_CL2) cycle time Symbol tFREQ tr tf tDUTY tCC tCLW tCT tDDdo tIDdo tHDdo tVDdo Min.    90 25 7 7  –3.5 –3.5 –3.5 –3.5 Max. 54 3 3 110    3 3 3 3 3 Unit MHz ns ns % ns ns ns ns ns ns ns ns 33.81 Figure Clock (LCD_CL2) high pulse width tCHW Clock (LCD_CL2) low pulse width Clock (LCD_CL2) transition time (rise/fall) Data (LCD_DATA) delay time Display permission (LCK_CL1) delay time Horizontal synchronized signal (LCD_CL1) delay time Vertical synchronized signal (LCD_FLM) delay time Rev. 1.00 Nov. 22, 2007 Page 1652 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics tCHW LCD_CL2 0.8Vcc 0.2Vcc tCLW tCT tCT tCC tDD LCD_DATA0 to 15 tDT 0.8VCCQ 0.2VCCQ tDT tID LCD_M_DISP tIT 0.8VCCQ 0.2VCCQ tIT tHD LCD_CL1 tHT 0.8VCCQ 0.2VCCQ tHT tVD LCD_FLM tVT 0.8VCCQ 0.2VCCQ tVT Figure 33.81 LCDC Module Signal Timing Rev. 1.00 Nov. 22, 2007 Page 1653 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.4.17 VDC2 Module Signal Timing Table 33.35 VDC2 Module Signal Timing Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35, Ta = –20 to 85°C, –40 to 85°C Item Symbol Min. 18.5 18.5 6 6   Typ.       Max. 158 158   3 5 Unit ns ns ns ns ns ns Note Output Input Input/ output Output (100 pF) Transmit 33.83, 33.84 Figure 33.82 Output clock frequency tO Input clock frequency Clock high Clock low Clock rise time tI tHC tLC tRC Delay Internal tDTRI synchronization mode External tDTRO synchronization mode Setup time Hold time tSR tHTR   20 ns 5 5     ns ns Receive Receive 33.85, 33.86 33.85 to 33.86 tHC tLC tRC DCLKIN DCLKOUT tI ,tO Figure 33.82 Clock Input/Output Timing Rev. 1.00 Nov. 22, 2007 Page 1654 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics DCLKIN (External synchronous mode) DCLKOUT (Internal synchronous mode) tDTRI/ tDTRO tDTRI/ tDTRO Output signal Figure 33.83 VDC2 Transmission Timing (1) DCLKIN (External synchronous mode) DCLKOUT (Internal synchronous mode) Output signal tTDTRI/ TDTRO tTDTRI/ TDTRO Figure 33.84 VDC2 Transmission Timing (2) DCLKIN tSR tHTR Input signal Figure 33.85 VDC2 Reception Timing (1) Rev. 1.00 Nov. 22, 2007 Page 1655 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics DCLKIN tSR tHTR Input signal Figure 33.86 VDC2 Reception Timing (2) Rev. 1.00 Nov. 22, 2007 Page 1656 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics 33.5 AC Characteristics Measurement Conditions AC characteristics measurement conditions as follows. V* 2 • Input pulse level:VssQ to V* • I/O signal reference level: • Input rise and fall times: 1 ns Note: * V:VDDQ (VDDQ = 3.0 to 3.6 V) IOL LSI output pin Output load switch reference voltage CL V VREF IOH Note: 1. CL is the total value that includes the capacitance of the measuring tools. The individual pins are set as 30 pF. 2. IOL = 3 mA (IIC pin) 2 mA (other than IIC pin) IOH = -2 mA Figure 33.87 Output Load Circuit Rev. 1.00 Nov. 22, 2007 Page 1657 of 1692 REJ09B0360-0100 Section 33 Electrical Characteristics Rev. 1.00 Nov. 22, 2007 Page 1658 of 1692 REJ09B0360-0100 Appendix Appendix A. CPU Operation Mode Register (CPUOPM) The CPUOPM is used to control the CPU operation mode. This register can be read from or written to the address H'FF2F0000 in P4 area or H'1F2F0000 in area 7 as 32-bit size. The write value to the reserved bits should be the initial value. The operation is not guaranteed if the write value is not the initial value. The CPUOPM register should be updated by the CPU store instruction not the access from SuperHyway bus master except CPU. After the CPUOPM is updated, read CPUOPM once, and execute one of the following two methods. 1. Execute a branch using the RTE instruction. 2. Execute the ICBI instruction for any address (including non-cacheable area). After one of these methods is executed, it is guaranteed that the CPU runs under the updated CPUOPM value. Bit: Initial value: R/W: 31  0 R 30  0 R 29  0 R 28  0 R 27  0 R 26  0 R 25  0 R 24  0 R 23  0 R 22  0 R 21  0 R 20  0 R 19  0 R 18  0 R 17  0 R 16  0 R Bit: Initial value: R/W: 15  0 R 14  13  12  11  10  9  8  7  1 R 6  5 RABD 4  3 INTMU 2  1  0  0 R 0 R 0 R 0 R 0 R 1 R 1 R 1 R 1 R/W 0 R 0 R/W 0 R 0 R 0 R Rev. 1.00 Nov. 22, 2007 Page 1659 of 1692 REJ09B0360-0100 Appendix Bit 31 to 6 5 Bit Name  RABD Initial Value R/W Description Reserved The write value must be the initial value. Speculative execution bit for subroutine return 0: Instruction fetch for subroutine return is issued speculatively. When this bit is set to 0, refer to appendix C, Speculative Execution for Subroutine Return. 1: Instruction fetch for subroutine return is not issued speculatively. H'000000F R 1 R/W 4 3  INTMU 0 0 R R/W Reserved The write value must be the initial value. Interrupt mode switch bit 0: SR.IMASK is not changed when an interrupt is accepted. 1: SR.IMASK is changed to the accepted interrupt level. 2 to 0  All 0 R Reserved The write value must be the initial value. Rev. 1.00 Nov. 22, 2007 Page 1660 of 1692 REJ09B0360-0100 Appendix B. Instruction Prefetching and Its Side Effects This LSI is provided with an internal buffer for holding pre-read instructions, and always performs pre-reading. Therefore, program code must not be located in the last 64-byte area of any memory space. If program code is located in these areas, a bus access for instruction prefetch may occur exceeding the memory areas boundary. A case in which this is a problem is shown below. Address : H'03FF FFF8 H'03FF FFFA H'03FF FFFC H'03FF FFFE H'4000 0000 H'4000 0002 Instruction : ADD R1,R4 JMP @R2 NOP NOP PC (Program Counter) Area 0 Area 1 Instruction prefetch address Figure B.1 Instruction Prefetch Figure B.1 presupposes a case in which the instruction (ADD) indicated by the program counter (PC) and the address H'04000002 instruction prefetch are executed simultaneously. It is also assumed that the program branches to an area other than area 1 after executing the following JMP instruction and delay slot instruction. In this case, a bus access (instruction prefetch) to area 1 may unintentionally occur from the programming flow. Instruction Prefetch Side Effects 1. It is possible that an external bus access caused by an instruction prefetch may result in misoperation of an external device, such as a FIFO, connected to the area concerned. 2. If there is no device to reply to an external bus request caused by an instruction prefetch, hangup will occur. Remedies 1. These illegal instruction fetches can be avoided by using the MMU. 2. The problem can be avoided by not locating program code in the last 64 bytes of any area. Rev. 1.00 Nov. 22, 2007 Page 1661 of 1692 REJ09B0360-0100 Appendix C. Speculative Execution for Subroutine Return The SH-4A has the mechanism to issue an instruction fetch speculatively when returning from subroutine. By issuing an instruction fetch speculatively, the execution cycles to return from subroutine may be shortened. This function is enabled by setting 0 to the bit 5 (RABD) of CPU Operation Mode register (CPUOPM). But this speculative instruction fetch may issue the access to the address that should not be accessed from the program. Therefore, a bus access to an unexpected area or an internal instruction address error may cause a problem. As for the effect of this bus access to unexpected memory area, refer to appendix B, Instruction Prefetching and Its Side Effects. Usage Condition: When the speculative execution for subroutine return is enabled, the RTS instruction should be used to return to the address set in PR by the JSR, BSR, or BSRF instructions. It can prevent the access to unexpected address and avoid the problem. Rev. 1.00 Nov. 22, 2007 Page 1662 of 1692 REJ09B0360-0100 Appendix D. Version Registers (PVR, PRR) The SH-4A has the read-only registers which show the version of a processor core, and the version of a product. By using the value of these registers, it becomes possible to be able to distinguish the version and product of a processor from software, and to realize the scalability of the high system. Note: The bit 7 to bit 0 of PVR register and the bit 3 to bit 0 of PRR register should be masked by the software. Table D.1 Register Configuration Abbr. PVR PRR R/W R R P4 Address H'FF000030 H'FF000044 Area 7 Address H'1F000030 H'1F000044 Size 32 32 Register Name Processor version register Product register Processor Version Register (PVR): Bit: 31 30 29 28 27 CHIP 26 25 24 23 22 21 20 19 18 17 16 VER 0 R 0 R 0 R 0 R 0 R 1 R 1 R 0 R 0 R 0 R 0 R Initial value: R/W: Bit: Initial value: R/W: 0 R 0 R 0 R 1 R 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 CUT 10 0 R 9 0 R 8 0 R 7   R 6  5  4  3   R 2  1  0  1 R  R  R  R  R  R  R Bit 31 to 24 23 to 16 Bit Name CHIP VER Initial Value H'10 H'30 R/W R R Description Processor Family The read value is always H'10 in the SH-4A. Major Version This value is changed when performing major enhancement of the architecture to the SH-4A. Minor Version This value is changed when performing minor enhancement of the architecture to the SH-4A. This value is undefined. It should be masked by software when using it. 15 to 8 CUT H'08 R 7 to 0 — Undefined R Rev. 1.00 Nov. 22, 2007 Page 1663 of 1692 REJ09B0360-0100 Appendix Product Register (PRR): Bit: Initial value: R/W: Bit: Initial value: R/W: 31 — 30 — 29 — 28 — 27 — 26 — 25 — 24 — 23 — 22 — 21 — 20 — 19 — 18 — 17 — 16 — 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 0 14 0 R 13 0 R 12 1 R 11 0 10 0 R 9 0 R 8 1 7 — 6 CUT 5 — 4 — R 3 — — 2 — 1 — 0 — Product — R — — — R R R R R R R R R Bit 31 to 16 Bit Name — Initial Value All 0 R/W R Description Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product. 15 to 8 Product H'11 R Major Version This value is changed when performing major enhancement of the product. 7 to 4 CUT Undefined R Minor Version This value is changed when performing minor enhancement of the product. 3 to 0 — Undefined R This value is undefined. It should be masked by software when using it. Rev. 1.00 Nov. 22, 2007 Page 1664 of 1692 REJ09B0360-0100 Appendix E. Pin State Pin States in Reset, Power-Down State, and Bus-Released State I/O XI XO O/IO/O IO/IO IO/IO IO/IO I/IO/O O/IO/O I/IO I/IO/O I/IO/O O/IO/O O/IO/O/IO Power-on Reset XI XO O I I I I O I I I O O O PI I O I O O I Refresh Standby XI XO K/G/K K/G K/G K/G I/G/K K/G/K I/G I/G/K I/G/K K/G/K K/K/K/G K/I/I/G PI I/G/I K/K/K/G K/G K/K/I/G K/G/IO K/G Sleep XI XO O/IO/O IO/IO IO/IO IO/IO I/IO/O O/IO/O I/IO I/IO/O I/IO/O O/IO/O O/IO/O/IO O/I/I/IO PI I/IO/I O/IO/O/IO IO/IO O/IO/I/IO O/IO/IO IO/IO Hi-Z Setting* XI XO Z/IO/Z Z/IO Z/IO Z/IO Z/IO/Z Z/IO/Z Z/IO Z/IO/Z Z/IO/Z Z/IO/Z Z/Z/Z/IO Z/Z/Z/IO PI Z/IO/Z Z/Z/Z/IO Z/IO Z/Z/Z/IO Z/IO/Z Z/IO Bus Release XI XO O/IO/O IO/IO IO/IO IO/IO I/IO/O O/IO/O I/IO I/IO/O I/IO/O O/IO/O O/IO/O/IO O/I/I/IO PI I/IO/I O/IO/O/IO IO/IO O/IO/I/IO O/IO/IO IO/IO Table E.1 BGA ball no. Pin Name B1 C1 D3 E3 F4 G4 D2 D1 F3 E2 E1 G3 F2 F1 H4 H3 G2 J4 G1 H2 J3 XIN XOUT WOL/PF2/IDEA0_M SSISCK2/PC3 SSIDATA2/PC2 SSIWS2/PC4 LNKSTA/PF3/ IDECS0_M EXOUT/PF4/ IDECS1_M AUDIO_CLK2/PC5 CRS/PD7/IDEA1_M COL/PE7/IDEA2_M TX_ER/PD6/ IDEIOWR_M MII_TXD3/SSIDATA5/ IODACK_M/PD0 MII_TXD2/AUDIO_CLK O/I/I/IO 5/IDEINT_M/PD1 MPMD I RX_ER/PE6/IODREQ_ I/IO/I M MII_TXD1/SSIWS5/ IDEIORD_M/PD2 SSIDATA3/PH4 O/IO/O/IO IO/IO MII_TXD0/SSISCK5/ID O/IO/I/IO EIORDY_M/ PD3 TX_EN/PD4/IDED0_M SSIWS3/PH6 O/IO/IO IO/IO Rev. 1.00 Nov. 22, 2007 Page 1665 of 1692 REJ09B0360-0100 Appendix BGA ball no. Pin Name H1 J2 J1 K3 K4 K2 K1 L3 L2 L4 L1 M2 M1 N1 M3 M4 N2 P1 N4 N3 P2 R1 P3 R2 P4 R3 I/O Power-on Reset I I I I I I I I I O I O I I I L I I L I I I I I O I Refresh Standby I/G/IO I/G/IO I/G/IO K/G I/O I/K/IO/G I/K/IO/G I/G I/K/IO/G K/I I/I/IO/G K/G/IO K/G/IO I/G K L/K/G K I/G H/K/G K K G/IO K G/IO K/G K Sleep I/IO/IO I/IO/IO I/IO/IO IO/IO I/O I/IO/IO/IO I/IO/IO/IO I/IO I/IO/IO/IO O/I I/I/IO/IO O/IO/IO IO/IO/IO I/IO IO H/IO/IO IO I/IO L/IO/IO IO IO IO/IO IO IO/IO O/IO IO Hi-Z Setting* Z/IO/Z Z/IO/Z Z/IO/Z Z/IO I/Z Z/Z/Z/IO Z/Z/Z/IO Z/IO Z/Z/Z/IO O/Z Z/Z/Z/IO Z/IO/Z Z/IO/Z Z/IO Z L/Z/IO Z Z/IO L/Z/IO Z Z IO/Z Z IO/Z Z/IO Z Bus Release I/IO/IO I/IO/IO I/IO/IO IO/IO I/O I/IO/IO/IO I/IO/IO/IO I/IO I/IO/IO/IO O/I I/I/IO/IO O/IO/IO IO/IO/IO I/IO IO H/IO/IO IO I/IO L/IO/IO IO IO IO/IO IO IO/IO O/IO IO TX_CLK/PD5/IDED15_ I/IO/IO M RX_CLK/PE5/IDED1_ M RX_DV/PE4/IDED14_ M SSISCK3/PH5 IRQ0/DTEND1 I/IO/IO I/IO/IO IO/IO I/O MII_RXD0/SSIWS4/IDE I/IO/IO/IO D2_M/PE3 MII_RXD1/SSISCK4/ID I/IO/IO/IO ED13_M/PE2 AUDIO_CLK3/PH7 I/IO MII_RXD2/SSIDATA4/I I/IO/IO/IO DED3_M/PE1 IRQOUT/DREQ1 O/I MII_RXD3/AUDIO_CLK I/I/IO/IO 4/IDED12_M/PE0 MDC/PF0/IDED4_M MDIO/PF1/IDED11_M AUDIO_CLK0/PC7 SSIWS0 STATUS1/RTS2/PA7 SSISCK0 AUDIO_CLK1/PC6 STATUS0/CTS2/PA6 SSIDATA0 SSISCK1 PJ7/IDED10_M SSIWS1 PJ6/IDED5_M FRE/PA4 SSIDATA1 O/IO/IO IO/IO/IO I/IO IO O/IO/IO IO I/IO O/IO/IO IO IO IO/IO IO IO/IO O/IO IO Rev. 1.00 Nov. 22, 2007 Page 1666 of 1692 REJ09B0360-0100 Appendix BGA ball no. Pin Name T1 T2 U1 U2 T3 R4 V1 V2 U3 T4 W1 V3 Y1 W2 V4 U4 W3 Y2 AA1 AB3 AB2 Y4 W5 AA3 Y5 AA4 W6 AA5 AB4 PJ5/IDED9_M PJ4/IDED6_M PJ2/IDED8_M PJ3/IDED7_M FWE/PA3 FCE/PA5 PJ1/IDERST_M PJ0/DIRECTION_M MODE7/FD6 FALE/PC0 MODE3/FD3 MODE5/FD5 TXD2/PA2 MODE2/FD2 MODE4/FD4 MODE8/FD7 MODE1/FD1 RXD2/PA1 SCK2/PA0 SDA SCL RXD1/AUDATA2 WDTOVF/IRQ1/AUDC K/DACK1 MODE0/FD0 RXD0/AUDATA0 TXD1/AUDATA3 TDO TXD0/AUDATA1 SCK1/FR/B I/O IO/IO IO/IO IO/IO IO/IO O/IO O/IO IO/O IO/O I/IO O/IO I/IO I/IO O/IO I/IO I/IO I/IO I/IO I/IO IO/IO IO IO I/IO O/I/IO/O I/IO I/IO O/IO O O/IO IO/I Power-on Reset I I I I O O I I Z O Z Z Z Z Z Z Z I I Z Z I O Z I Z Z Z I Refresh Standby G/IO G/IO G/IO G/IO K/G K/G G/K G/K -/K K/G -/K -/K K/G -/K -/K -/K -/K I/G K/G IO IO I/K O/I/K/O -/K I/K K/K O K/K K/I Sleep IO/IO IO/IO IO/IO IO/IO O/IO O/IO IO/O IO/O -/IO O/IO -/IO -/IO O/IO -/IO -/IO -/IO -/IO I/IO IO/IO IO IO I/IO O/I/IO/O -/IO I/IO O/IO O O/IO IO/I Hi-Z Setting* IO/Z IO/Z IO/Z IO/Z Z/IO Z/IO IO/Z IO/Z -/Z Z/IO -/Z -/Z Z/IO -/Z -/Z -/Z -/Z Z/IO Z/IO Z Z Z/IO O/I/IO/Z -/Z Z/IO Z/IO O Z/IO Z/Z Bus Release IO/IO IO/IO IO/IO IO/IO O/IO O/IO IO/O IO/O -/IO O/IO -/IO -/IO O/IO -/IO -/IO -/IO -/IO I/IO IO/IO IO IO I/IO O/I/IO/O -/IO I/IO O/IO O O/IO IO/I Rev. 1.00 Nov. 22, 2007 Page 1667 of 1692 REJ09B0360-0100 Appendix BGA ball no. Pin Name Y6 W7 AA6 AB5 AB6 Y8 AA8 TMS TRST TDI I/O I I I Power-on Reset PI PI PI I PI O O Refresh Standby PI PI PI K/K/K PI K/K/G K/K/K Sleep PI PI PI IO/IO/O PI O/O/IO O/IO/O Hi-Z Setting* PI PI PI Z/IO/Z PI Z/Z/IO Z/Z/Z Bus Release PI PI PI IO/IO/O PI O/O/IO O/IO/O SCK0/AUDSYNC/FCL IO/IO/O E TCK I LCD_VEP_WC/DR5/P O/O/IO H0 LCD_FLM/VSYNC/SP O/IO/O S/EX_VSYNC/BT_VSY NC LCD_CL1/HSYNC/SPL O/IO/O /EX_HSYNC/BT_HSY NC LCD_M_DISP/DE_C/D O/O/O E_H/BT_DE_C LCD_VCP_WC/DR4/P O/O/IO H1 LCD_CLK/DCLKIN I/I AB8 O K/K/K O/IO/O Z/Z/Z O/IO/O AA9 Y9 AB9 Y10 AA10 AB10 Y11 AA11 AB11 Y12 AA12 AB12 O O I O O O O O O O O O K/K/K K/K/G I/I K/K/G K/K/G K/K/G K/K/G K/K/G K/K/G K/K/G K/K/G K/K/K/G O/O/O O/O/IO I/I O/O/IO O/O/IO O/O/IO O/O/IO O/O/IO O/O/IO O/O/IO O/O/IO O/O/O/IO Z/Z/Z Z/Z/IO Z/Z Z/O/IO Z/O/IO Z/O/IO Z/O/IO Z/Z/IO Z/Z/IO Z/Z/IO Z/Z/IO Z/Z/Z/IO O/O/O O/O/IO I/I O/O/IO O/O/IO O/O/IO O/O/IO O/O/IO O/O/IO O/O/IO O/O/IO O/O/O/IO LCD_DATA15/DR3/PG O/O/IO 7 LCD_DATA14/DR2/PG O/O/IO 6 LCD_DATA13/DR1/PG O/O/IO 5 LCD_DATA12/DR0/PG O/O/IO 4 LCD_DATA11/DG5/PG O/O/IO 3 LCD_DATA10/DG4/PG O/O/IO 2 LCD_DATA9/DG3/PG1 O/O/IO LCD_DATA8/DG2/PG0 O/O/IO LCD_DATA7/DG1/BT_ O/O/O/IO DATA7/PI4 Rev. 1.00 Nov. 22, 2007 Page 1668 of 1692 REJ09B0360-0100 Appendix BGA ball no. Pin Name Y13 AA13 AB13 Y14 AA14 AB14 AA15 Y15 AB15 Y16 AB17 AA17 AA18 Y17 W17 Y19 AB21 AB22 Y20 Y22 W18 W21 V19 W22 I/O Power-on Refresh Reset Standby O O O O O O O O O I I I O O O I XI XO O I O A O O K/K/K/G K/K/K/G K/K/K/G K/K/K K/K/K K/K/K K/K/K K/K/G K/K/G G/K MI I K K K MI XI XO K I K A/I/G K/G/I/K K/G/O/K Sleep O/O/O/IO O/O/O/IO O/O/O/IO O/O/O O/O/O O/O/O O/O/O O/O/IO O/O/IO IO/O MI I O O O MI XI XO O I O IO/I/IO O/IO/I/IO O/IO/O/IO Hi-Z Setting* Z/Z/Z/IO Z/Z/Z/IO Z/Z/Z/IO Z/Z/Z Z/Z/Z Z/Z/Z Z/Z/Z Z/Z/IO Z/Z/IO IO/Z MI I O O O MI XI XO O I O IO/Z/IO O/IO/Z/Z O/IO/Z/Z Bus Release O/O/O/IO O/O/O/IO O/O/O/IO O/O/O O/O/O O/O/O O/O/O O/O/IO O/O/IO IO/O MI I O MZ MZ MI XI XO MZ I MZ IO/I/IO MZ/IO/I/IO MZ/IO/O/IO LCD_DATA6/DG0/BT_D O/O/O/IO ATA6/PI3 LCD_DATA5/DB5/BT_D O/O/O/IO ATA5/PI2 LCD_DATA4/DB4/BT_D O/O/O/IO ATA4/PI1 LCD_DATA3/DB3/BT_D O/O/O ATA3 LCD_DATA2/DB2/BT_D O/O/O ATA2 LCD_DATA1/DB1/BT_D O/O/O ATA1 LCD_DATA0/DB0/BT_D O/O/O ATA0 LCD_CL2/DE_V/PH3 O/O/IO LCD_DON/DCLKOUT/P O/O/IO H2 PI0/COM/CDE RDY NMI BACK RD CS3 BREQ EXTAL XTAL BS PRESET CS0 IO/O I I O O O I XI XO O I O ASEBRKAK/BRKACK/T O/I/IO CLK/PC1 A25/PB7/DREQ0/RTS0 O/IO/I/IO A24/PB6/DACK0/CTS0 O/IO/O/IO Rev. 1.00 Nov. 22, 2007 Page 1669 of 1692 REJ09B0360-0100 Appendix BGA ball no. Pin Name U19 V21 V20 U22 V22 U21 U20 T19 T20 T21 T22 R19 R20 R21 R22 P19 P20 P21 P22 N19 N22 N21 N20 M22 M21 M19 L22 M20 L21 K22 A17 A23/PB5/DTEND0/ RTS1 A21/PB3 A20/PB2 A22/PB4/CTS1 A19/PB1 A18/PB0 D15 D14 D1 D0 D13 D12 D3 D2 D11 D10 D5 D4 D9 D6 D7 D8 DQMLL DQMUL DQMUU D16 DQMLU D17 D18 I/O O O/IO/O/IO O/IO O/IO O/IO/IO O/IO O/IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O O IO O IO IO Power-on Refresh Reset Standby O O O O O O O PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ O O O PZ O PZ PZ K K/G/O/K K/G K/G K/G/K K/G K/G MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ K K K MZ K MZ MZ Sleep O O/IO/O/IO O/IO O/IO O/IO/IO O/IO O/IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O O IO O IO IO Hi-Z Setting* O O/IO/Z/Z O/IO O/IO O/IO/Z O/IO O/IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O O IO O IO IO Bus Release MZ MZ/IO/O/IO MZ/IO MZ/IO MZ/IO/IO MZ/IO MZ/IO MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ Rev. 1.00 Nov. 22, 2007 Page 1670 of 1692 REJ09B0360-0100 Appendix BGA ball no. K21 L19 L20 J22 J21 H22 K20 K19 G22 H21 J20 F22 G21 J19 H20 E22 F21 H19 D22 G20 E21 D21 F20 G19 C22 C21 B22 F19 E20 E19 Pin Name D19 D31 D30 D20 D21 D22 D28 D29 A15 D23 D26 A13 A16 D27 D24 A10 A14 D25 A4 A11 A5 R/W A8 A12 CKE RAS CLKOUT A9 A6 A7 I/O IO IO IO IO IO IO IO IO O IO IO O O IO IO O O IO O O O O O O O O O O O O Power-on Refresh Reset Standby PZ PZ PZ PZ PZ PZ PZ PZ O PZ PZ O O PZ PZ O O PZ O O O O O O O O O O O O MZ MZ MZ MZ MZ MZ MZ MZ K MZ MZ K K MZ MZ K K MZ K K K H K K K H C K K K Sleep IO IO IO IO IO IO IO IO O IO IO O O IO IO O O IO O O O O O O O O O O O O Hi-Z Setting* IO IO IO IO IO IO IO IO O IO IO O O IO IO O O IO O O O O O O O O O O O O Bus Release MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ MZ O MZ MZ MZ Rev. 1.00 Nov. 22, 2007 Page 1671 of 1692 REJ09B0360-0100 Appendix BGA ball no. D20 A21 B20 C19 D18 A20 B19 D17 C18 B18 A19 C17 D16 C16 A18 C15 D15 B17 B16 B15 A17 A16 D14 A15 C14 B14 A14 C13 B13 A13 Pin Name CAS CS1 CS2 A0 D47/IDECS0 A3 A1 D45/IODACK D46/IDECS1 D33/PF6 A2 D44/IDEINT D43/IDEIORDY D42/IDEIORD D32/PF7 D40/IDEIOWR D41/IODREQ D35/IDEA0 D37/IDEA1 D39/IDED14 D34/PF5 D36/IDEA2 D63/IDED1 D38/IDED15 D62/IDED0 WE2/DQM64UL WE0/DQM64LL D60/IDED2 WE3/DQM64UU WE1/DQM64LU I/O O O O O IO/O O O IO/O IO/O IO/IO O IO/I IO/I IO/O IO/IO IO/O IO/I IO/O IO/O IO/IO IO/IO IO/O IO/IO IO/IO IO/IO O/O O/O IO/IO O/O O/O Power-on Refresh Reset Standby O O O O PZ O O PZ PZ PZ O PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ O O PZ O O K K K K MZ/K K K MZ/K MZ/K MZ/G K MZ/I MZ/I MZ/K MZ/G MZ/K MZ/I MZ/K MZ/K MZ/IO MZ/G MZ/K MZ/IO MZ/IO MZ/IO K/K K/K MZ/IO K/K K/K Sleep O O O O IO/O O O IO/O IO/O IO/IO O IO/I IO/I IO/O IO/IO IO/O IO/I IO/O IO/O IO/IO IO/IO IO/O IO/IO IO/IO IO/IO O/O O/O IO/IO O/O O/O Hi-Z Setting* O O O O IO/Z O O IO/Z IO/Z IO/IO O IO/Z IO/Z IO/Z IO/IO IO/Z IO/Z IO/Z IO/Z IO/Z IO/IO IO/Z IO/Z IO/Z IO/Z O/O O/O IO/Z O/O O/O Bus Release MZ MZ MZ MZ MZ/O MZ MZ MZ/O MZ/O MZ/IO MZ MZ/I MZ/I MZ/O MZ/IO MZ/O MZ/I MZ/O MZ/O MZ/IO MZ/IO MZ/O MZ/IO MZ/IO MZ/IO MZ/MZ MZ/MZ MZ/IO MZ/MZ MZ/MZ Rev. 1.00 Nov. 22, 2007 Page 1672 of 1692 REJ09B0360-0100 Appendix BGA ball no. D13 A12 D12 C12 B12 B11 A11 C11 A10 B10 D11 C10 D10 A7 A6 B6 E8 Pin Name D61/IDED3 D48/IDED13 D59/IDED5 D58/IDED4 D49/IDED12 D51/IDED10 D50/IDED11 D56/IDED6 D52/IDED9 D53/IDED8 D57/IDED7 D54/IDERST D55/DIRECTION DM DP VBUS REFRIN I/O IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO IO/O IO/O AIO AIO AI AI Power-on Refresh Reset Standby PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ Z Z AI AI MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/K MZ/K Z Z AI AI Sleep IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO IO/IO IO/O IO/O AIO AIO AI AI Hi-Z Setting* IO/Z IO/Z IO/Z IO/Z IO/Z IO/Z IO/Z IO/Z IO/Z IO/Z IO/Z IO/Z IO/Z Z Z AI AI Bus Release MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/IO MZ/O MZ/O AIO AIO AI AI Note: * Indicated the pin states when setting the corresponding bit in the Hi-Z register A or B (PTHIZ_A or PTHIZ_B) in the GPIO to 1. Input Output Input/output XTAL input XTAL output Analog input Analog input/output High impedance Input and pulled up by an on-chip resistance High impedance and pulled up by an on-chip resistance High-level output Low-level output The state of a pin (both input and output) before transition to refresh standby mode is held. [Legend] I: O: IO: XI: XO: AI: AIO: Z: PI: PZ: H: L: K: Rev. 1.00 Nov. 22, 2007 Page 1673 of 1692 REJ09B0360-0100 Appendix Input buffer on, whether the on-chip pull-up resistance is on or off is depends on the corresponding register setting in the MCU. MZ: Input buffer off, output buffer off; whether the on-chip pull-up resistance is on or off is depends on the corresponding register setting in the MCU A: On-chip pull-up resistance is on. Input/output can be controlled by a register setting when MPMD is at a low level. Input when TRST is at the low level or MPMD is at the high level. C: Clock output or low level output: depends on a register setting in the CPG. G: Whether this is an input or output and the on-chip resistance is on or off is depends on register settings in the GPIO. GPI: Input buffer on, output buffer off; whether the on-chip resistance is on or off depends on register settings in the GPIO. GPZ: Input buffer off, output buffer off; whether the on-chip resistance is on or off depends on register settings in the GPIO. -: Invalid MI: Rev. 1.00 Nov. 22, 2007 Page 1674 of 1692 REJ09B0360-0100 Appendix F. Pin Treatment When Not in Use Treatment of Unused Pins Pin Name XIN XOUT WOL/PF2/IDEA0_M SSISCK2/PC3 SSIDATA2/PC2 SSIWS2/PC4 LNKSTA/PF3/IDECS0_M EXOUT/PF4/IDECS1_M AUDIO_CLK2/PC5 CRS/PD7/IDEA1_M COL/PE7/IDEA2_M TX_ER/PD6/IDEIOWR_M MII_TXD3/SSIDATA5/IODACK_M/PD0 MII_TXD2/AUDIO_CLK5/IDEINT_M/PD1 MPMD RX_ER/PE6/IODREQ_M MII_TXD1/SSIWS5/IDEIORD_M/PD2 SSIDATA3/PH4 MII_TXD0/SSISCK5/IDEIORDY_M/PD3 TX_EN/PD4/IDED0_M SSIWS3/PH6 TX_CLK/PD5/IDED15_M RX_CLK/PE5/IDED1_M RX_DV/PE4/IDED14_M SSISCK3/PH5 IRQ0/DTEND1 MII_RXD0/SSIWS4/IDED2_M/PE3 MII_RXD1/SSISCK4/IDED13_M/PE2 Treatment of Unused Pins*4 Pull-down Open Open Pull-up Pull-up Pull-up Pull-down Open Pull-up Pull-down Pull-down Open Open Open Pull-up*2 Pull-down Open Pull-up Open Open Pull-up Pull-down Pull-down Pull-down Pull-up Pull-up Pull-down Pull-down Table F.1 BGA ball no. B1 C1 D3 E3 F4 G4 D2 D1 F3 E2 E1 G3 F2 F1 H4 H3 G2 J4 G1 H2 J3 H1 J2 J1 K3 K4 K2 K1 Rev. 1.00 Nov. 22, 2007 Page 1675 of 1692 REJ09B0360-0100 Appendix BGA ball no. L3 L2 L4 L1 M2 M1 N1 M3 M4 N2 P1 N4 N3 P2 R1 P3 R2 P4 R3 T1 T2 U1 U2 T3 R4 V1 V2 U3 T4 W1 V3 Pin Name AUDIO_CLK3/PH7 MII_RXD2/SSIDATA4/IDED3_M/PE1 IRQOUT/DREQ1 MII_RXD3/AUDIO_CLK4/IDED12_M/PE0 MDC/PF0/IDED4_M MDIO/PF1/IDED11_M AUDIO_CLK0/PC7 SSIWS0 STATUS1/RTS2/PA7 SSISCK0 AUDIO_CLK1/PC6 STATUS0/CTS2/PA6 SSIDATA0 SSISCK1 PJ7/IDED10_M SSIWS1 PJ6/IDED5_M FRE/PA4 SSIDATA1 PJ5/IDED9_M PJ4/IDED6_M PJ2/IDED8_M PJ3/IDED7_M FWE/PA3 FCE/PA5 PJ1/IDERST_M PJ0/DIRECTION_M MODE7/FD6 FALE/PC0 MODE3/FD3 MODE5/FD5 Treatment of Unused Pins*4 Pull-up Pull-down Open Pull-down Open Pull-down Pull-up Pull-up Open Pull-up Pull-up Open Pull-up Pull-up Pull-up Pull-up Pull-up Open Pull-up Pull-up Pull-up Pull-up Pull-up Open Open Pull-up Pull-up Pull-down Open Must be used Must be used Rev. 1.00 Nov. 22, 2007 Page 1676 of 1692 REJ09B0360-0100 Appendix BGA ball no. Y1 W2 V4 U4 W3 Y2 AA1 AB3 AB2 Y4 W5 AA3 Y5 AA4 W6 AA5 AB4 Y6 W7 AA6 AB5 AB6 Y8 AA8 AB8 AA9 Y9 AB9 Y10 AA10 Pin Name TXD2/PA2 MODE2/FD2 MODE4/FD4 MODE8/FD7 MODE1/FD1 RXD2/PA1 SCK2/PA0 SDA SCL RXD1/AUDATA2 WDTOVF/IRQ1/AUDCK/DACK1 MODE0/FD0 RXD0/AUDATA0 TXD1/AUDATA3 TDO TXD0/AUDATA1 SCK1/FR/B TMS TRST TDI SCK0/AUDSYNC/FCLE TCK LCD_VEP_WC/DR5/PH0 Treatment of Unused Pins*4 Open Must be used Must be used Must be used Must be used Pull-up Pull-up Open Open Pull-up Open Must be used Pull-up Open Open*2 Open Pull-up Open*2 Connect to ground or PRESET*2*3 Open*2 Pull-up Open*2 Open LCD_FLM/VSYNC/SPS/EX_VSYNC/BT_VSYNC Open LCD_CL1/HSYNC/SPL/EX_HSYNC/BT_HSYNC Open LCD_M_DISP/DE_C/DE_H/BT_DE_C LCD_VCP_WC/DR4/PH1 LCD_CLK/DCLKIN LCD_DATA15/DR3/PG7 LCD_DATA14/DR2/PG6 Open Open Pull-up Open Open Rev. 1.00 Nov. 22, 2007 Page 1677 of 1692 REJ09B0360-0100 Appendix BGA ball no. AB10 Y11 AA11 AB11 Y12 AA12 AB12 Y13 AA13 AB13 Y14 AA14 AB14 AA15 Y15 AB15 Y16 AB17 AA17 AA18 Y17 W17 Y19 AB21 AB22 Y20 Y22 W18 W21 V19 W22 U19 Pin Name LCD_DATA13/DR1/PG5 LCD_DATA12/DR0/PG4 LCD_DATA11/DG5/PG3 LCD_DATA10/DG4/PG2 LCD_DATA9/DG3/PG1 LCD_DATA8/DG2/PG0 LCD_DATA7/DG1/BT_DATA7/PI4 LCD_DATA6/DG0/BT_DATA6/PI3 LCD_DATA5/DB5/BT_DATA5/PI2 LCD_DATA4/DB4/BT_DATA4/PI1 LCD_DATA3/DB3/BT_DATA3 LCD_DATA2/DB2/BT_DATA2 LCD_DATA1/DB1/BT_DATA1 LCD_DATA0/DB0/BT_DATA0 LCD_CL2/DE_V/PH3 LCD_DON/DCLKOUT/PH2 PI0/COM/CDE RDY NMI BACK RD CS3 BREQ EXTAL XTAL BS PRESET CS0 ASEBRKAK/BRKACK/TCLK/PC1 A25/PB7/DREQ0/RTS0 A24/PB6/DACK0/CTS0 A17 Treatment of Unused Pins*4 Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Pull-up Pull-down*1 Pull-up Open Open Open Pull-up Must be used Open Open Must be used Must be used Open*2 Open Open Open Rev. 1.00 Nov. 22, 2007 Page 1678 of 1692 REJ09B0360-0100 Appendix BGA ball no. V21 V20 U22 V22 U21 U20 T19 T20 T21 T22 R19 R20 R21 R22 P19 P20 P21 P22 N19 N22 N21 N20 M22 M21 M19 L22 M20 L21 K22 K21 L19 L20 Pin Name A23/PB5/DTEND0/RTS1 A21/PB3 A20/PB2 A22/PB4/CTS1 A19/PB1 A18/PB0 D15 D14 D1 D0 D13 D12 D3 D2 D11 D10 D5 D4 D9 D6 D7 D8 DQMLL DQMUL DQMUU D16 DQMLU D17 D18 D19 D31 D30 Treatment of Unused Pins*4 Open Open Open Open Open Open Open Open Must be used Must be used Open Open Must be used Must be used Open Open Must be used Must be used Open Must be used Must be used Open Open Open Open Open Open Open Open Open Open Open Rev. 1.00 Nov. 22, 2007 Page 1679 of 1692 REJ09B0360-0100 Appendix BGA ball no. J22 J21 H22 K20 K19 G22 H21 J20 F22 G21 J19 H20 E22 F21 H19 D22 G20 E21 D21 F20 G19 C22 C21 B22 F19 E20 E19 D20 A21 B20 C19 D18 Pin Name D20 D21 D22 D28 D29 A15 D23 D26 A13 A16 D27 D24 A10 A14 D25 A4 A11 A5 R/W A8 A12 CKE RAS CLKOUT A9 A6 A7 CAS CS1 CS2 A0 D47/IDECS0 Treatment of Unused Pins*4 Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Rev. 1.00 Nov. 22, 2007 Page 1680 of 1692 REJ09B0360-0100 Appendix BGA ball no. A20 B19 D17 C18 B18 A19 C17 D16 C16 A18 C15 D15 B17 B16 B15 A17 A16 D14 A15 C14 B14 A14 C13 B13 A13 D13 A12 D12 C12 B12 B11 Pin Name A3 A1 D45/IODACK D46/IDECS1 D33/PF6 A2 D44/IDEINT D43/IDEIORDY D42/IDEIORD D32/PF7 D40/IDEIOWR D41/IODREQ D35/IDEA0 D37/IDEA1 D39/IDED14 D34/PF5 D36/IDEA2 D63/IDED1 D38/IDED15 D62/IDED0 WE2/DQM64UL WE0/DQM64LL D60/IDED2 WE3/DQM64UU WE1/DQM64LU D61/IDED3 D48/IDED13 D59/IDED5 D58/IDED4 D49/IDED12 D51/IDED10 Treatment of Unused Pins*4 Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Rev. 1.00 Nov. 22, 2007 Page 1681 of 1692 REJ09B0360-0100 Appendix BGA ball no. A11 C11 A10 B10 D11 C10 D10 A7 A6 B6 E8 Pin Name D50/IDED11 D56/IDED6 D52/IDED9 D53/IDED8 D57/IDED7 D54/IDERST D55/DIRECTION DM DP VBUS REFRIN Treatment of Unused Pins*4 Open Open Open Open Open Open Open Open Open Open Open Notes: 1. This pin is pulled-up within the LSI after a power-on reset (initial state). Set the IPUP bit in BCR (MCU) to 1 to switch pulling-up of the RDY pin off. Pulling-up of the BREQ pin is also off when the IPUP bit is 1. So if the BREQ pin is in use, use a pull-up resistance on the board to pull the BREQ pin up. 2. When designing a board for use with an emulator, follow the directions for the emulator. 3. When not using emulator, the pin should be fixed to ground or connected to another pin which operates in the same manner as PRESET. However, since the TRST pin is pulled up within this LSI, a weak current flows when the pin is externally connected to ground pin. The value of the current is determined by a resistance of the pull-up MOS for the TRST pin. Although this current does not affect the operation of this LSI, it consumes power unnecessarily. 4. Treatment of pins if unused refers to the pin state after a power-on reset. Rev. 1.00 Nov. 22, 2007 Page 1682 of 1692 REJ09B0360-0100 Appendix G. Type Name Type name of the products Operating temperature Solder Ball range Composition PKG Code Table G.1 Model Name Catalog Number SDHI R5S77640N300BG R5S77640N300BG –20 to +85°C Lead free R5S77640P300BG R5S77640P300BG –40 to +85°C Lead free R5S77641N300BG R5S77641N300BG –20 to +85°C Lead free R5S77641P300BG R5S77641P300BG –40 to +85°C Lead free Note PRBG0404GA- Not A mounted PRBG0404GA- Not A mounted PRBG0404GA- Mounted* A PRBG0404GA- Mounted* A * This product mounts the SD host interface (SDHI). As regards the SD host interface (SDHI) information, a nondisclosure agreement needs to be entered into before release. Ask our sales representative details on this matter. Rev. 1.00 Nov. 22, 2007 Page 1683 of 1692 REJ09B0360-0100 Appendix H. Package Dimensions JEITA Package Code P-FBGA404-19x19-0.80 RENESAS Code PRBG0404GA-A Previous Code  MASS[Typ.] 1.1g D wS A wS B 4× v y1 S S A yS e ZD A AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 e A1 E Reference Symbol Dimension in Millimeters B D E v w A A1 ZE Min Nom 19 19 Max 0.15 0.2 1.9 0.35 0.45 0.4 0.8 0.5 0.55 0.08 0.1 0.2 0.45 e b x y y1 SD SE ZD ZE φb φ× M S A B 1.1 1.1 Figure H.1 Package Dimensions Rev. 1.00 Nov. 22, 2007 Page 1684 of 1692 REJ09B0360-0100 Index Numerics 10-Bit address format ............................. 576 7-Bit address format ............................... 575 Control Signal Timing .......................... 1584 Cycle-steal mode..................................... 393 D A Absolute Maximum Ratings ................. 1573 AC Characteristics ................................ 1581 AC Characteristics Measurement Conditions............................................. 1657 Address space identifier (ASID)............. 157 Address translation ................................. 156 Addressing modes..................................... 53 AND/NAND flash memory controller (FLCTL) ............................................... 1277 Arithmetic operation instructions ............. 61 ASID....................................................... 170 Auto-Reload Count Operation ................ 483 Auto-Request mode ................................ 384 Data address error ................................... 116 Data TLB miss exception................ 110, 192 Data TLB multiple hit exception ............ 192 Data TLB multiple-hit exception ............ 109 Data TLB protection violation exception......................................... 113, 194 DC Characteristics ................................ 1575 Delay slot .................................................. 51 Delayed branches ...................................... 51 Direct memory access controller (DMAC).................................................. 359 Dirty bit................................................... 172 Division by zero...................................... 144 DMAC Module Timing ........................ 1605 Double-precision floating-point extended registers...................................... 37 Double-precision floating-point registers..................................................... 37 Dual address mode.................................. 391 B Big endian................................................. 46 Block diagram........................................... 13 Branch instructions ................................... 65 Break detection and processing .............. 551 Burst mode.............................................. 395 Bus Timing ........................................... 1586 E ECC code .............................................. 1315 ECC error check.................................... 1315 Effective address....................................... 53 Electrical Characteristics....................... 1573 Equation for getting SCBRR value ......... 513 EtherC Module Signal Timing.............. 1644 Exception flow ........................................ 104 Exception handling ................................... 95 Exception/interrupt codes ....................... 102 Execution cycles ....................................... 85 Rev. 1.00 Nov. 22, 2007 Page 1685 of 1692 REJ09B0360-0100 C Cacheability bit....................................... 171 Caches..................................................... 207 Clock pulse generator (CPG).................. 245 Clock Timing........................................ 1581 Command access mode......................... 1308 Control registers ....................................... 32 External request mode ............................ 384 F Fixed mode ............................................. 388 Fixed-point transfer instructions............... 59 Floating-point control instructions ........... 70 Floating-point double-precision instructions ............................................... 69 Floating-point graphics acceleration instructions ............................................... 70 Floating-point registers....................... 33, 37 Floating-point single-precision instructions ............................................... 68 FPU error ................................................ 144 FPU exception ........................................ 125 FPU exception handling ......................... 145 FPU Exception sources........................... 144 G General FPU disable exception .............. 122 General FPU disable exceptions and slot FPU disable exceptions.................... 144 General illegal instruction exception ...... 120 General interrupt request ........................ 126 General purpose I/O (GPIO)................. 1337 General registers ....................................... 32 Geometric operation instructions............ 146 I2C bus interface (IIC)............................. 555 Inexact exception .................................... 144 Initial page write exception............. 112, 195 Input Capture Function ........................... 484 Instruction address error ......................... 118 Instruction execution state ........................ 47 Instruction fetch cycle break................. 1462 Instruction set............................................ 51 Instruction TLB miss exception...... 111, 190 Instruction TLB multiple hit exception......................................... 109, 189 Instruction TLB protection violation exception......................................... 115, 191 Intermittent mode.................................... 394 Interrupt controller (INTC) ..................... 409 Interrupt response time ........................... 465 Invalid operation ..................................... 144 IPG settings............................................. 745 IRQ interrupts ......................................... 455 Issue rates.................................................. 85 ITLB ....................................................... 173 ITLB address array ................................. 198 ITLB data array....................................... 199 L LCD controller (LCDC)........................ 1001 LCD module power-supply states......... 1048 Little endian .............................................. 46 Load-store architecture ............................. 51 Logic operation instructions ..................... 63 H H-UDI reset ............................................ 108 H-UDI-Related Pin Timing .................. 1648 M Magic packet........................................... 744 Memory management unit ...................... 149 Memory-mapped registers ........................ 45 MII registers.................................... 741, 742 Module standby mode........................... 1422 Multiple interrupts .................................. 464 I I/O Port Timing .................................... 1642 I2C bus data format ................................. 574 Rev. 1.00 Nov. 22, 2007 Page 1686 of 1692 REJ09B0360-0100 Multiple virtual memory mode ............... 156 N NMI (nonmaskable interrupt) ................. 126 NMI interrupt.......................................... 455 Notes on display-off mode (LCDC stopped) ................................... 1049 Pre-execution user break/post-execution user break................................................ 124 Privileged mode ........................................ 32 Processing modes...................................... 32 Programming model.................................. 31 Protection key data.................................. 171 R O On-chip module interrupts...................... 456 On-Chip peripheral module request mode ....................................................... 386 Operand access cycle break .................. 1464 Operation in asynchronous mode ........... 530 Operation in clocked synchronous mode ....................................................... 541 Output Addition Circuit........................ 1657 Overflow................................................. 144 Receive data sampling timing and receive margin (asynchronous mode) ..... 551 Receive descriptor................................... 791 Registers APR..................................................... 728 BEMPENB.......................................... 849 BEMPSTS........................................... 868 BRDYENB ......................................... 845 BRDYSTS .......................................... 864 BUSWAIT .......................................... 815 CAMR0............................................. 1454 CAMR1............................................. 1454 CAR0 ................................................ 1453 CAR1 ................................................ 1453 CBCR................................................ 1460 CBR0 ................................................ 1445 CBR1 ................................................ 1445 CCMFR............................................. 1459 CCR .................................................... 212 CDCR.................................................. 718 CDMR1............................................. 1457 CDR1 ................................................ 1456 CEFCR................................................ 721 CETR1 .............................................. 1458 CFIFO ................................................. 827 CFIFOCTR ......................................... 837 CFIFOSEL .......................................... 830 CHCR.................................................. 370 CPUOPM .......................................... 1659 CRR0 ................................................ 1451 CRR1 ................................................ 1451 Rev. 1.00 Nov. 22, 2007 Page 1687 of 1692 REJ09B0360-0100 P P0, P3, and U0 areas ............................... 153 P1 area .................................................... 154 P2 area .................................................... 154 P4 area .................................................... 154 Page size bits .......................................... 171 Pair single-precision data transfer instructions ............................................. 147 Physical address space............................ 155 Pin arrangement........................................ 14 Pipelining.................................................. 71 Power-Down mode ............................... 1411 Power-down state ..................................... 47 Power-on reset ........................................ 108 Power-on/Power-off Sequence ............. 1574 Power-supply control sequences........... 1044 PPN......................................................... 171 D0FBCFG........................................... 826 D0FIFO .............................................. 827 D0FIFOCTR....................................... 837 D0FIFOSEL ....................................... 830 D1FBCFG........................................... 826 D1FIFO .............................................. 827 D1FIFOCTR....................................... 837 D1FIFOSEL ....................................... 830 DAR.................................................... 367 DARB................................................. 368 DBR...................................................... 41 DCPCFG............................................. 879 DCPCTR............................................. 881 DCPMAXP......................................... 880 DEVADDn ......................................... 930 DMAOR0 ........................................... 378 DMARS.............................................. 381 DVSTCTR.......................................... 818 ECMR................................................. 705 ECSIPR .............................................. 711 ECSR .................................................. 709 EDMR ................................................ 753 EDRRR............................................... 755 EDTRR............................................... 754 EESIPR............................................... 763 EESR .................................................. 758 EXPEVT............................................... 97 FCETR................................................ 781 FDR .................................................... 772 FLADR............................................. 1291 FLADR2 ........................................... 1293 FLBSYCNT...................................... 1302 FLBSYTMR ..................................... 1301 FLCMCDR ....................................... 1290 FLCMDCR ....................................... 1287 FLCMNCR ....................................... 1284 FLDATAR........................................ 1295 FLDTCNTR ..................................... 1294 FLDTFIFO ....................................... 1303 FLECFIFO........................................ 1304 Rev. 1.00 Nov. 22, 2007 Page 1688 of 1692 REJ09B0360-0100 FLINTDMACR ................................ 1296 FLTRCR ........................................... 1305 FPSCR .......................................... 42, 139 FPUL................................................... 142 FRECR................................................ 722 FRMNUM........................................... 869 FRQCR ............................................... 251 GBR ...................................................... 41 GECMR .............................................. 734 ICCCR ................................................ 569 ICMAR ............................................... 569 ICMCR ............................................... 564 ICMIER .............................................. 568 ICMSR................................................ 566 ICR0.................................................... 419 ICR1.................................................... 421 ICRXD................................................ 571 ICSAR................................................. 563 ICSCR................................................. 558 ICSIER................................................ 562 ICSSR ................................................. 559 ICTXD ................................................ 571 INT2A0............................................... 432 INT2A01............................................. 434 INT2A1............................................... 436 INT2A11............................................. 438 INT2B ................................................. 448 INT2GPIC........................................... 453 INT2MSKCR...................................... 444 INT2MSKCR1.................................... 446 INT2MSKR ........................................ 440 INT2MSKR1 ...................................... 442 INT2PRI ............................................. 430 INTENB0............................................ 841 INTENB1............................................ 843 INTEVT................................................ 98 INTMSK0 ........................................... 424 INTMSKCLR0 ................................... 425 INTPRI ............................................... 422 INTREQ.............................................. 423 INTSTS0............................................. 852 INTSTS1............................................. 858 IOSR ................................................... 785 IRMCR ............................................... 168 LCCR.......................................... 719, 720 LDACLNR ....................................... 1024 LDCNTR .......................................... 1032 LDDFR ............................................. 1012 LDHCNR.......................................... 1019 LDHSYNR ....................................... 1020 LDICKR ........................................... 1007 LDINTR ........................................... 1025 LDLAOR.......................................... 1016 LDLIRNR......................................... 1036 LDMTR ............................................ 1009 LDPALCR ........................................ 1017 LDPMMR......................................... 1028 LDPR................................................ 1018 LDPSPR ........................................... 1030 LDSARL........................................... 1015 LDSARU .......................................... 1014 LDUINTLNR ................................... 1035 LDUINTR......................................... 1033 LDVDLNR ....................................... 1021 LDVSYNR ....................................... 1023 LDVTLNR........................................ 1022 MACH .................................................. 41 MACL................................................... 41 MAFCR .............................................. 726 MAHR ................................................ 713 MALR................................................. 714 MMUCR............................................. 162 MPR.................................................... 729 MSTPCR0 ........................................ 1415 MSTPCR1 ........................................ 1419 NMIFCR............................................. 426 NRDYENB......................................... 847 NRDYSTS .......................................... 866 PASCR ............................................... 167 PC ......................................................... 41 PFTCR ........................................ 732, 733 PIPEBUF ............................................ 899 PIPECFG ............................................ 892 PIPEMAXP......................................... 902 PIPEnCTR .......................................... 906 PIPEnTRE........................................... 926 PIPEnTRN .......................................... 928 PIPEPERI............................................ 904 PIPESEL ............................................. 891 PIR ...................................................... 712 PLLCR ................................................ 253 PR ......................................................... 41 PRR................................................... 1664 PSR ..................................................... 716 PTEH .................................................. 159 PTEL................................................... 160 PVR................................................... 1663 QACR0 ............................................... 214 QACR1 ............................................... 215 RAMCR ...................................... 216, 239 RBWAR.............................................. 777 RDFAR ............................................... 778 RDLAR............................................... 757 RFCR .................................................. 725 RFLR .................................................. 715 RFOCR ............................................... 776 RMCR................................................. 773 RMFCR............................................... 769 RPADIR.............................................. 783 SAR..................................................... 366 SARB .................................................. 367 SCBRR................................................ 513 SCEMR............................................... 526 SCFCR ................................................ 518 SCFDR................................................ 521 SCFRDR ............................................. 496 SCFSR ................................................ 505 SCFTDR ............................................. 497 SCLSR ................................................ 525 SCRSR ................................................ 496 Rev. 1.00 Nov. 22, 2007 Page 1689 of 1692 REJ09B0360-0100 SCSCR................................................ 501 SCSMR............................................... 498 SCSPTR.............................................. 522 SCTSR................................................ 497 SDBSR ............................................. 1485 SDINT .............................................. 1484 SDIR................................................. 1483 SGR ...................................................... 41 SOFCFG ............................................. 851 SPC....................................................... 41 SR ......................................................... 39 SRCCTRL ........................................ 1325 SRCID .............................................. 1320 SRCIDCTRL .................................... 1322 SRCOD............................................. 1321 SRCODCTRL................................... 1323 SRCSTAT......................................... 1328 SSR....................................................... 41 STBCR ............................................. 1414 SYSCFG ............................................. 811 SYSSTS.............................................. 816 TBRAR............................................... 779 TCNT.................................................. 477 TCOR ................................................. 477 TCPR2 ................................................ 480 TCR ............................................ 368, 478 TCRB.................................................. 369 TDFAR............................................... 780 TDLAR............................................... 756 TEA .................................................... 162 TESTMODE....................................... 823 TFTR .................................................. 770 TFUCR ............................................... 775 TLFRCR ............................................. 724 TOCR ................................................. 474 TPAUSER .................................. 730, 731 TRA ...................................................... 96 TRIMD ............................................... 784 TROCR............................................... 717 TRSCER ............................................. 766 Rev. 1.00 Nov. 22, 2007 Page 1690 of 1692 REJ09B0360-0100 TSFRCR ............................................. 723 TSTR................................................... 475 TTB..................................................... 161 UFRMNUM........................................ 872 USBADDR ......................................... 873 USBINDX........................................... 877 USBLENG .......................................... 878 USBREQ............................................. 874 USBVAL ............................................ 876 USERIMASK ..................................... 428 VBR ...................................................... 41 VDC2CLKCR..................................... 254 Relative priorities.................................... 102 Reset state ................................................. 47 Rounding................................................. 143 Round-robin mode .................................. 388 S Sampling rate converter (SRC) ............. 1317 SCIF interrupt sources ............................ 549 SCIF Module Timing............................ 1608 SDHI Module Timing ........................... 1641 Sector access mode ............................... 1311 Sending a break signal ............................ 551 Sequential break.................................... 1465 Serial communication interface with FIFO (SCIF)............................................ 489 Serial Sound Interface (SSI) ................... 619 Setting the display resolution................ 1044 Share status bit ........................................ 171 Shift instructions ....................................... 64 Sign-extended ........................................... 46 Single virtual memory mode................... 156 Single-precision floating-point extended.................................................... 37 Single-precision floating-point extended register matrix............................ 38 Single-precision floating-point registers..................................................... 37 Single-precision floating-point vector registers..................................................... 37 Sleep mode ........................................... 1420 Slot FPU disable exception..................... 123 Slot illegal instruction exception ............ 121 Software standby mode......................... 1421 SSI Module Timing .............................. 1609 STIF ModuleSignal Timing.................. 1652 System control instructions....................... 65 System registers........................................ 33 System registers related to FPU................ 33 U Unconditional trap .................................. 119 Underflow ............................................... 144 USB 2.0 host/function module (USB) .... 801 User break controller............................. 1441 User break operation ............................. 1461 User debugging interface ...................... 1477 User mode ................................................. 32 UTLB...................................................... 170 UTLB address array................................ 202 UTLB data array ..................................... 203 T T bit .......................................................... 52 TAP control .......................................... 1506 TCNT Count Timing .............................. 483 Timer Unit (TMU).................................. 469 Transceiver Timing............................... 1640 Transmit descriptor................................. 786 Types of exceptions ................................ 102 V Validity bit .............................................. 171 Vector addresses ..................................... 102 Video display controller (VDC2).......... 1221 Virtual address space .............................. 152 VPN ........................................................ 170 W Watchdog Timer and Reset................... 1425 Watchdog Timer Timing....................... 1605 Write-through bit .................................... 172 Rev. 1.00 Nov. 22, 2007 Page 1691 of 1692 REJ09B0360-0100 Rev. 1.00 Nov. 22, 2007 Page 1692 of 1692 REJ09B0360-0100 Renesas 32-Bit RISC Microcomputer Hardware Manual SH7764 Group Publication Date: Rev.1.00, Nov. 22, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.  2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: (21) 5877-1818, Fax: (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: (2) 796-3115, Fax: (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: 7955-9390, Fax: 7955-9510 Colophon 6.0 SH7764 Group Hardware Manual