SLG46722V-SKT

SLG46722 GreenPAK 3 Programmable Mixed Signal Array Personal Computers and Servers PC Peripherals Consumer Electronics Data Communications Equipment Handheld and Portable Electronics GPI 2 GPIO GPIO 17 GPIO 16 GPIO 3 15 GPIO GPIO 4 14 GPIO GPIO 5 13 GPIO GPIO 6 12 GPIO GPIO 7 11 GND 20 8 GPIO • • • • • 1 19 9 18 10 GPIO Applications VDD GPIO Logic & Mixed Signal Circuits Highly Versatile Macro Cells Read Back Protection (Read Lock) 1.8V (±5%) to 5V (±10%) Supply Operating Temperature Range: -40°C to 85°C RoHS Compliant / Halogen-Free 20-pin STQFN: 2 x 3 x 0.55 mm, 0.4 mm pitch GPIO • • • • • • • Pin Configuration GPIO Features STQFN-20 (Top View) Block Diagram Pin 1 VDD Pin 20 GPIO Pin 19 GPIO Pin 18 GPIO Counters/Delay Generators Pin 2 GPI Pin 17 GPIO D Flip Flops (DFF) / Latches CNT0 CNT1 CNT2 CNT3 DFF0 DFF1 DFF2 CNT4 CNT5 CNT6 CNT7 DFF3 DFF5 DFF6 Pin 16 GPIO Pin 15 GPIO Pin 3 GPIO Combination Function Macrocells Pin 4 GPIO 2-bit LUT2_0 or DFF4 Programmable Delay 3-bit LUT3_8 or Pipe Delay RC Oscillator Look Up Tables (LUTs) Pin 5 GPIO Pin 6 GPIO Pin 7 GPIO Silego Technology, Inc. 000-0046722-111 Pin 13 GPIO 2-bit LUT2_1 2-bit LUT2_2 3-bit LUT3_3 2-bit LUT2_4 2-bit LUT2_5 3-bit LUT3_0 3-bit LUT3_1 3-bit LUT3_2 3-bit LUT3_3 3-bit LUT3_4 3-bit LUT3_5 3-bit LUT3_6 3-bit LUT3_7 3-bit LUT3_9 4-bit LUT4_0 Pin 8 GPIO Pin 14 GPIO Pin 9 GPIO Additional Logic Functions FILTER_0 Pin 12 GPIO FILTER_1 Pin 10 GPIO Pin 11 GND Rev 1.11 Revised May 31, 2016 SLG46722 1.0 Overview The SLG46722 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macro cells of the SLG46722. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The macro cells in the device include the following: • • Fifteen Combinatorial Look Up Tables (LUTs) • Five 2-bit LUTs • Nine 3-bit LUTs • One 4-bit LUT Two Combination Function Macro cell • One Selectable FF/Latch or 2-bit LUT • One Selectable Pipe Delay or 3-bit LUT • Pipe Delay – 16 stage / 3 output Eight Counter / Delay Generators (CNT/DLY) • • • • • • One 14-bit delay/counter • One 14-bit delay/counter with external clock/reset • Four 8-bit delays/counters • Two 8-bit delays/counters with external clock/reset Six D Flip-Flop / Latches (DFF) Pipe Delay – 16 stage/3 output (Part of Combination Function Macrocell) Programmable Delay Additional Logic Functions – 2 Deglitch Filters RC Oscillator (RC OSC) • 000-0046722-111 Page 1 of 82 SLG46722 2.0 Pin Description 2.1 Functional and Programming Pin Description Pin # Pin Name Function Programming Function 1 VDD Power Supply Power Supply 2 GPI General Purpose Input VPP (Programming Voltage) 3 GPIO General Purpose I/O Reset 4 GPIO General Purpose I/O N/A 5 GPIO General Purpose I/O N/A 6 GPIO General Purpose I/O N/A 7 GPIO General Purpose I/O N/A 8 GPIO General Purpose I/O or POR Output N/A 9 GPIO General Purpose I/O N/A 10 GPIO General Purpose I/O N/A 11 GND Ground Ground 12 GPIO General Purpose I/O N/A 13 GPIO General Purpose I/O N/A 14 GPIO General Purpose I/O N/A 15 GPIO General Purpose I/O N/A 16 GPIO General Purpose I/O Programming Mode Control 17 GPIO General Purpose I/O Programming ID Pin 18 GPIO General Purpose I/O Programming SDIO Pin 19 GPIO General Purpose I/O Programming SRDWB Pin 20 GPIO General Purpose I/O or External Clock Programming SCL Pin 000-0046722-111 Page 2 of 82 SLG46722 3.0 User Programmability The SLG46722 is a user programmable device with One-Time-Programmable (OTP) memory elements that are able to construct combinatorial logic elements. Three of the I/O Pins provide a connection for the bit patterns into the OTP on board memory. A programming development kit allows the user the ability to create initial devices. Once the design is finalized, the programming code (.gpx file) is forwarded to Silego to integrate into a production process. 3URGXFW 'HILQLWLRQ &XVWRPHU&UHDWHVWKHLURZQGHVLJQLQ *UHHQ3$.'HVLJQHU (PDLO3URGXFW,GHD'HILQLWLRQ'UDZLQJRU 6FKHPDWLFWR*UHHQ3$.#VLOHJRFRP 3URJUDP(QJLQHHULQJ6DPSOHVZLWK *UHHQ3$.3URJUDPPHU 6LOHJR$SSOLFDWLRQV(QJLQHHUVZLOOUHYLHZGHVLJQ VSHFLILFDWLRQVZLWKFXVWRPHU &XVWRPHUYHULILHV*UHHQ3$. LQV\VWHPGHVLJQ 6DPSOHVDQG'HVLJQ &KDUDFWHUL]DWLRQ 5HSRUWVHQWWRFXVWRPHU *UHHQ3$.'HVLJQ DSSURYHG *UHHQ3$.'HVLJQ DSSURYHG (PDLOJS[ILOHWR *UHHQ3$.#VLOHJRFRP &XVWRPHUYHULILHV*UHHQ3$.GHVLJQ *UHHQ3$.'HVLJQ DSSURYHGLQV\VWHPWHVW &XVWRP*UHHQ3$.SDUW HQWHUVSURGXFWLRQ Figure 1. Steps to create a custom Silego GreenPAK device 000-0046722-111 Page 3 of 82 SLG46722 4.0 Ordering Information Part Number Type SLG46722V 20-pin STQFN SLG46722VTR 20-pin STQFN - Tape and Reel (3k units) 000-0046722-111 Page 4 of 82 SLG46722 5.0 Electrical Specifications 5.1 Absolute Maximum Conditions Parameter Min. Max. Unit Supply voltage on VDD relative to GND -0.5 7 V DC Input voltage GND - 0.5 VDD + 0.5 V Current at Input Pin -1.0 1.0 mA Storage Temperature Range -65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1300 -- V Moisture Sensitivity Level 1 5.2 Electrical Characteristics (1.8 V ±5% VDD) Symbol VDD TA VPP VIH VIL Parameter Min. Typ. Max. Unit Supply Voltage 1.71 1.80 1.89 V Operating Temperature -40 25 85 °C Programming Voltage HIGH-Level Input Voltage LOW-Level Input Voltage IIH HIGH-Level Input Current IIL LOW-Level Input Current VOH VOL IOH Condition/Note HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Output Current 000-0046722-111 7.25 7.50 7.75 V Logic Input 1.100 -- -- V Logic Input with Schmitt Trigger 1.270 -- -- V Low-Level Logic Input 0.980 -- -- V Logic Input -- -- 0.690 V Logic Input with Schmitt Trigger -- -- 0.440 V Low-Level Logic Input -- -- 0.520 V Logic Input Pins; VIN = 1.8 V -1.0 -- 1.0 A Logic Input Pins; VIN = 0 V -1.0 -- 1.0 A Push-Pull 1X, Open Drain PMOS 1X, IOH = 100 A 1.690 1.789 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 100 A 1.700 1.794 -- V Push-Pull 1X, IOL= 100 A -- 0.008 0.030 V Push-Pull 2X, IOL= 100 A -- 0.004 0.010 V Open Drain NMOS 1X, IOL= 100 A -- 0.005 0.020 V Open Drain NMOS 2X, IOL= 100 A -- 0.003 0.010 V Open Drain NMOS 4X, IOL= 100 A -- 0.003 0.004 V Push-Pull 1X, Open Drain PMOS 1X, VOH = VDD - 0.2 1.066 1.703 -- mA Push-Pull 1X, Open Drain PMOS 1X, VOH = VDD - 0.2 2.216 3.406 -- mA Page 5 of 82 SLG46722 Symbol IOL TSU PONTHR POFFTHR Parameter LOW-Level Output Current Condition/Note Min. Typ. Max. Unit Push-Pull 1X, VOL = 0.15 V 0.917 1.689 -- mA Push-Pull 2X, VOL = 0.15 V 1.834 3.378 -- mA Open Drain NMOS 1X, VOL = 0.15 V 1.375 2.534 -- mA Open Drain NMOS 2X, VOL = 0.15 V 2.750 5.068 -- mA Open Drain NMOS Super Drive, VOL = 0.15 V 5.500 10.136 -- mA -- 0.3 -- ms Startup Time from VDD rising past 1.35 V Power On Threshold VDD Level Required to Start Up the Chip 1.096 1.353 1.528 V Power Off Threshold VDD Level Required to Switch Off the Chip 0.759 0.933 1.125 V 000-0046722-111 Page 6 of 82 SLG46722 5.3 Electrical Characteristics (3.3V ±10% VDD) Symbol VDD TA VPP VIH VIL Parameter Min. Typ. Max. Unit Supply Voltage 3.0 3.3 3.6 V Operating Temperature -40 25 85 °C Programming Voltage HIGH-Level Input Voltage LOW-Level Input Voltage IIH HIGH-Level Input Current IIL LOW-Level Input Current VOH VOL IOH IOL TSU PONTHR POFFTHR Condition/Note HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Output Current LOW-Level Output Current 7.25 7.50 7.75 V Logic Input 1.780 -- -- V Logic Input with Schmitt Trigger 2.130 -- -- V Low-Level Logic Input 1.130 -- -- V Logic Input -- -- 1.210 V Logic Input with Schmitt Trigger -- -- 0.950 V Low-Level Logic Input -- -- 0.690 V Logic Input Pins; VIN = 3.3 V -1.0 -- 1.0 A Logic Input Pins; VIN = 0 V -1.0 -- 1.0 A Push-Pull 1X,Open Drain PMOS 1X, IOH = 3 mA 2.735 3.120 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 3 mA 2.870 3.210 -- V Push-Pull 1X, IOL= 3 mA -- 0.130 0.228 V Push-Pull 2X, IOL= 3 mA -- 0.060 0.108 V Open Drain NMOS 1X, IOL= 3 mA -- 0.080 0.147 V Open Drain NMOS 2X, IOL= 3 mA -- 0.040 0.080 V Open Drain NMOS 4X, IOL= 3 mA -- 0.027 0.034 V Push-Pull 1X, Open Drain PMOS 1X, VOH = 2.4 V 6.045 12.080 -- mA Push-Pull 2X, Open Drain PMOS 2X, VOH = 2.4 V 11.522 24.160 -- mA Push-Pull 1X, VOL = 0.4 V 4.875 8.244 -- mA Push-Pull 2X, VOL = 0.4 V 9.750 16.488 -- mA Open Drain NMOS 1X, VOL = 0.4 V 7.313 12.370 -- mA Open Drain NMOS 2X, VOL = 0.4 V 14.541 24.740 -- mA Open Drain NMOS Super Drive, VOL = 0.4 V 25.801 49.480 -- mA -- 0.3 -- ms Startup Time from VDD rising past 1.35 V Power On Threshold VDD Level Required to Start Up the Chip 1.096 1.353 1.528 V Power Off Threshold VDD Level Required to Switch Off the Chip 0.759 0.933 1.125 V 000-0046722-111 Page 7 of 82 SLG46722 5.4 Electrical Characteristics (5 V ±10% VDD) Symbol VDD TA VPP VIH VIL Parameter Min. Typ. Max. Unit Supply Voltage 4.5 5.0 5.5 V Operating Temperature -40 25 85 °C Programming Voltage HIGH-Level Input Voltage LOW-Level Input Voltage IIH HIGH-Level Input Current IIL LOW-Level Input Current VOH VOL IOH IOL TSU PONTHR POFFTHR Condition/Note HIGH-Level Output Voltage LOW-Level Output Voltage HIGH-Level Output Current LOW-Level Output Current 7.25 7.50 7.75 V Logic Input 2.640 -- -- V Logic Input with Schmitt Trigger 3.160 -- -- V Low-Level Logic Input 1.230 -- -- V Logic Input -- -- 1.840 V Logic Input with Schmitt Trigger -- -- 1.510 V Low-Level Logic Input -- -- 0.780 V Logic Input Pins; VIN = 5 V -1.0 -- 1.0 A Logic Input Pins; VIN = 0 V -1.0 -- 1.0 A Push-Pull 1X,Open Drain PMOS 1X, IOH = 5 mA 4.190 4.780 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 5 mA 4.320 4.890 -- V Push-Pull 1X, IOL= 5 mA -- 0.157 0.270 V Push-Pull 2X, IOL= 5 mA -- 0.076 0.130 V Open Drain NMOS 1X, IOL= 5 mA -- 0.102 0.180 V Open Drain NMOS 2X, IOL= 5 mA -- 0.051 0.110 V Open Drain NMOS 4X, IOL= 5 mA -- 0.035 0.045 V Push-Pull 1X, Open Drain PMOS 1X, VOH = 2.4 V 22.080 34.040 -- mA Push-Pull 2X, Open Drain PMOS 2X, VOH = 2.4 V 41.690 68.080 -- mA Push-Pull 1X, VOL = 0.4 V 7.215 11.580 -- mA Push-Pull 2X, VOL = 0.4 V 13.831 23.160 -- mA Open Drain NMOS 1X, VOL = 0.4 V 10.820 17.380 -- mA Open Drain NMOS 2X, VOL = 0.4 V 17.343 34.760 -- mA Open Drain NMOS Super Drive, VOL = 0.4 V 30.964 69.520 -- mA -- 0.3 -- ms Startup Time from VDD rising past 1.35 V Power On Threshold VDD Level Required to Start Up the Chip 1.096 1.353 1.528 V Power Off Threshold VDD Level Required to Switch Off the Chip 0.759 0.933 1.125 V 000-0046722-111 Page 8 of 82 SLG46722 5.5 IDD Estimator Table 1. Typical Current estimated for each block. Symbol Parameter I Current Note VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit Chip Quiescent 0.5 0.8 1.0 A OSC 25 kHz, predivide = 1 3.2 5.1 7.3 A OSC 25 kHz, predivide = 8 3.0 4.4 6.0 A OSC 2 MHz, predivide = 1 38.5 78.2 136.2 A OSC 2 MHz, predivide = 8 18.3 25.7 35.5 A 5.6 Timing Estimator Table 2. Typical Delay estimated for each block. Symbol Parameter tpd Delay tpd Delay tpd tpd VDD = 1.8 V Note VDD = 3.3V VDD = 5.0V Unit rising falling rising falling rising falling Digital Input without Schmitt Trigger 42 45 17 19 12 13 ns Digital Input with Schmitt Trigger 42 43 16 17 18 12 ns Delay Low Voltage Digital input 45 428 17 177 12 120 ns Delay Digital input-- PMOS 42 - 17 - 12 - ns tpd Delay Digital input-- NMOS - 80 - 27 - 18 ns tpd Delay Output enable from pin, OE Hi-Z to 1 53 - 21 - 15 - ns tpd Delay Output enable from pin, OE Hi-Z to 0 50 - 20 - 14 - ns tpd Delay LUT2bit(LATCH) 34 33 14 13 10 9 ns tpd Delay LATCH(LUT2bit) 30 34 14 13 10 9 ns tpd Delay LUT3bit(LATCH) 38 37 18 15 13 10 ns tpd Delay LATCH+nRESET(LUT3bit) 45 42 21 17 15 12 ns tpd Delay LUT4bit 28 33 14 13 10 9 ns tpd Delay LUT2bt 19 26 10 10 7 7 ns tpd Delay LUT3bit 28 34 14 13 10 9 ns tpd Delay CNT/DLY 40 38 18 15 13 11 ns tpd Delay P_DLY1C 380 377 166 163 123 120 ns tpd Delay P_DLY2C 720 718 314 312 233 231 ns tpd Delay P_DLY3C 1061 1060 462 460 343 341 ns tpd Delay P_DLY4C 1396 1400 609 609 451 451 ns tpd Delay Filter 200 200 78 78 53 53 ns tpd Delay ACMP (5mV across inputs) 3000 3000 2000 2000 2000 2000 ns tw width I/O with 1X push pull (min transmitted) 20 20 20 20 20 20 ns tw width filter (min transmitted) 150 150 55 55 35 35 ns 5.7 Typical Counter/Delay Offset Measurements Table 3. Typical Counter/Delay Offset Measurements. Parameter RC OSC Freq RC OSC Power offset 25kHz auto offset 2MHz auto 7 frequency settling time 25kHz auto 19 000-0046722-111 VDD = 1.8 V VDD = 3.3V VDD = 5.0V 19 Unit 12 s 4 4 s 14 12 s 14 Page 9 of 82 SLG46722 Table 3. Typical Counter/Delay Offset Measurements. Parameter RC OSC Freq RC OSC Power VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit frequency settling time 2MHz auto 14 14 14 s variable (CLK period) 25kHz forced 0-40 0-40 0-40 s variable (CLK period) 2MHz forced 0-0.5 0-0.5 0-0.5 s tpd (non-delayed edge) 25kHz/2MHz either 35 14 10 ns 000-0046722-111 Page 10 of 82 SLG46722 5.8 Expected Delays and Widths Table 4. Expected Delays and Widths for Programmable Delay (typical). Symbol Parameter Note time1 Width, 1 cell mode:(any)edge detect, edge detect output VDD = 1.8 V VDD = 3.3V VDD = 5.0V 325 150 110 Unit ns time1 Width, 2 cell mode:(any)edge detect, edge detect output 740 300 225 ns time1 Width, 3 cell mode:(any)edge detect, edge detect output 1020 450 340 ns time1 Width, 4 cell mode:(any)edge detect, edge detect output 1350 600 450 ns time2 Delay, 1 cell mode:(any)edge detect, edge detect output 44 18 14 ns time2 Delay, 2 cell mode:(any)edge detect, edge detect output 44 18 14 ns time2 Delay, 3 cell mode:(any)edge detect, edge detect output 44 18 14 ns time2 Delay, 4 cell mode:(any)edge detect, edge detect output 44 18 14 ns time1 Width, 1 cell mode: delayed (any)edge detect, delayed edge detect output 340 150 110 ns time1 Width, 2 cell mode: delayed (any)edge detect, delayed edge detect output 670 300 220 ns time1 Width, 3 cell mode: delayed (any)edge detect, delayed edge detect output 1000 450 335 ns time1 Width, 4 cell mode: delayed (any)edge detect, delayed edge detect output 1340 600 450 ns time2 Delay, 1 cell mode: delayed (any)edge detect, delayed edge detect output 570 220 140 ns time2 Delay, 2 cell mode: delayed (any)edge detect, delayed edge detect output 570 220 140 ns time2 Delay, 3 cell mode: delayed (any)edge detect, delayed edge detect output 570 220 140 ns time2 Delay, 4 cell mode: delayed (any)edge detect, delayed edge detect output 570 220 140 ns time2 Delay, 1 cell mode: both edge delay, edge detect output 382 375 126 ns time2 Delay, 2 cell mode: both edge delay, edge detect output 713 169 237 ns time2 Delay, 3 cell mode: both edge delay, edge detect output 1045 318 350 ns time2 Delay, 4 cell mode: both edge delay, edge detect output 1370 466 460 ns time2 Delay, 1 cell mode: both edge delay, delayed edge detect output 900 613 250 ns time2 Delay, 2 cell mode: both edge delay, delayed edge detect output 1250 520 360 ns time2 Delay, 3 cell mode: both edge delay, delayed edge detect output 1600 680 480 ns time2 Delay, 4 cell mode: both edge delay, delayed edge detect output 1900 815 600 ns 5.9 Typical Pulse Width Performance Table 5. Typical Pulse Width Performance. Parameter Filtered Pulse Width 000-0046722-111 VDD = 1.8 V VDD = 3.3V VDD = 5.0V < 150 < 55 < 35 Unit ns Page 11 of 82 SLG46722 6.0 Summary of Macro Cell Function 6.1 I/O Pins • • • • • Digital Input (low voltage or normal voltage, with or without Schmitt Trigger) Open Drain Outputs Push Pull Outputs 10 k/100 k/1 Mpull-up/pull-down resistors 40mA Open Drain Superdrive output 6.2 Connection Matrix • Digital matrix for circuit connections based on user design 6.3 Combinational Logic Look Up Tables (LUTs – 15 total) • • • Five 2-bit Lookup Tables Nine 3-bit Lookup Tables One 4-bit Lookup Tables 6.4 Combination Function Macrocell (2 total) • • One Selectable FF/Latch or 2-bit LUT One Selectable Pipe Delay or 3-bit LUT 6.5 Delays/Counters (8 total) • • • • One 14-bit delay/counter: Range 1-16384 clock cycles One 14-bit delay/counter with external clock/reset: Range 1-16384 clock cycles Four 8-bit delays/counters: Range 1-255 clock cycles Two 8-bit delays/counters with external clock/reset: Range 1-255 clock cycles 6.6 Digital Storage Elements (6 total) • Six D Flip-Flops or Latches 6.7 Pipe Delay (Part of Combination Function Macrocell) • • • 16 stage / 3 output One 1 stage fixed output Two 1-16 stage selectable outputs. 6.8 Programmable Delay • • 125 ns/250 ns/375 ns/500 ns @ 3.3 V Includes Edge Detection function 6.9 Additional Logic Functions (2 total) • Two Deglitch filter macro cells 6.10 RC Oscillator • • • 25 kHz and 2 MHz selectable frequency First stage divider (4): OSC/1, OSC/2, OSC/4, and OSC/8 Second stage divider (5): OSC/1, OSC/4, selectable (OSC/8, OSC/12, OSC/24, or OSC/64), OSC/3, and additional OSC/3 (from selectable output) 000-0046722-111 Page 12 of 82 SLG46722 7.0 I/O Pins The SLG46722 has a total of 18 multi-function I/O pins which can function as either a user defined Input or Output, as well as serving as a special function (such as outputting the voltage reference), or serving as a signal for programming of the on-chip Non Volatile Memory (NVM). Normal Mode pin definitions are as follows: • • • • • • • • • • • • • • • • • • Pin 2: general purpose input Pin 3: general purpose input or output Pin 4: general purpose input or output Pin 5: general purpose input or output Pin 6: general purpose input or output Pin 7: general purpose input or output Pin 8: general purpose input or output or POR output Pin 9: general purpose input or output Pin 10: general purpose input or output Pin 12: general purpose input or output Pin 13: general purpose input or output Pin 14: general purpose input or output Pin 15: general purpose input or output Pin 16: general purpose input or output Pin 17: general purpose input or output Pin 18: general purpose input or output Pin 19: general purpose input or output Pin 20: general purpose input or output or external clock Programming Mode pin definitions are as follows; • • • • • • • • Pin 1: Vdd power supply Pin 2: Vpp programming voltage Pin 11: ground Pin 16: programming mode control Pin 17: programming ID pin Pin 18: programming SDIO pin Pin 19: programming SRDWB pin Pin 20: programming SCL pin Of the 18 user defined I/O pins on the SLG46722, all but one of the pins (Pin 2) can serve as both digital input and digital output. Pin 2 can only serve as a digital input pin. 7.1 Input Modes Each I/O pin can be configured as a digital input pin with/without buffered Schmitt Trigger, or can also be configured as a low voltage digital input. 7.2 Output Modes Pins 3, 4,5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18, 19 and 20 can all be configured as digital output pins. 7.3 Pull Up/Down Resistors All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors are 10 k, 100 k and 1 M. In the case of Pin 2, the resistors are fixed to a pull-down configuration. In the case of all other I/O pins, the internal resistors can be configured as either pull-up or pull-downs. 000-0046722-111 Page 13 of 82 SLG46722 7.4 I/O Register Settings 7.4.1 PIN 2 Register Settings Table 6. PIN 2 Register Settings Signal Function Register Bit Address PIN 2 Mode Control 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved PIN 2 Pull Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor Register Definition 7.4.2 PIN 3 Register Settings Table 7. PIN 3 Register Settings Signal Function Register Bit Address PIN 3 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 3 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 3 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 3 Driver Strength Selection 0: 1X 1: 2X 000-0046722-111 Register Definition Page 14 of 82 SLG46722 7.4.3 PIN 4 Register Settings Table 8. PIN 4 Register Settings Signal Function Register Bit Address PIN 4 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 4 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 4 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 4 Driver Strength Selection 0: 1X 1: 2X Register Definition 7.4.4 PIN 5 Register Settings Table 9. PIN 5 Register Settings Signal Function Register Bit Address PIN 5 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 5 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 5 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 5 Driver Strength Selection 0: 1X 1: 2X 000-0046722-111 Register Definition Page 15 of 82 SLG46722 7.4.5 PIN 6 Register Settings Table 10. PIN 6 Register Settings Signal Function Register Bit Address PIN 6 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 6 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 6 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 6 Driver Strength Selection 0: 1X 1: 2X Register Definition 7.4.6 PIN 7 Register Settings Table 11. PIN 7 Register Settings Signal Function Register Bit Address PIN 7 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 7 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 7 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 7 Driver Strength Selection 0: 1X 1: 2X 000-0046722-111 Register Definition Page 16 of 82 SLG46722 7.4.7 PIN 8 Register Settings Table 12. PIN 8 Register Settings Signal Function Register Bit Address PIN 8 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 8 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 8 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 8 Driver Strength Selection 0: 1X 1: 2X Register Definition 7.4.8 PIN 9 Register Settings Table 13. PIN 9 Register Settings Signal Function Register Bit Address PIN 9 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 9 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 9 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 9 Driver Strength Selection 0: 1X 1: 2X 000-0046722-111 Register Definition Page 17 of 82 SLG46722 7.4.9 PIN 10 Register Settings Table 14. PIN 10 Register Settings Signal Function Register Bit Address Register Definition PIN 10 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 10 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 10 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 10 Driver Strength Selection 0: 1X 1: 2X PIN 10 Super Drive (4X, NMOS Open Drain) Selection 0: Super Drive Off 1: Super Drive On (if = ‘101’) 7.4.10 PIN 12 Register Settings Table 15. PIN 12 Register Settings Signal Function Register Bit Address Register Definition PIN 12 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 12 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 12 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 12 Driver Strength Selection 0: 1X 1: 2X PIN 12 Super Drive (4X, NMOS Open Drain) Selection 0: Super Drive Off 1: Super Drive On (if = ‘101’) 000-0046722-111 Page 18 of 82 SLG46722 7.4.11 PIN 13 Register Settings Table 16. PIN 13 Register Settings Signal Function Register Bit Address Register Definition PIN 13 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 13 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 13 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 13 Driver Strength Selection 0: 1X 1: 2X 7.4.12 PIN 14 Register Settings Table 17. PIN 14 Register Settings Signal Function Register Bit Address Register Definition PIN 14 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 14 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 14 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 14 Driver Strength Selection 0: 1X 1: 2X 000-0046722-111 Page 19 of 82 SLG46722 7.4.13 PIN 15 Register Settings Table 18. PIN 15 Register Settings Signal Function Register Bit Address Register Definition PIN 15 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 15 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 15 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 15 Driver Strength Selection 0: 1X 1: 2X 7.4.14 PIN 16 Register Settings Table 19. PIN 16 Register Settings Signal Function Register Bit Address Register Definition PIN 16 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 16 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 16 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 16 Driver Strength Selection 0: 1X 1: 2X 000-0046722-111 Page 20 of 82 SLG46722 7.4.15 PIN 17 Register Settings Table 20. PIN 17 Register Settings Signal Function Register Bit Address Register Definition PIN 17 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 17 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 17 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 17 Driver Strength Selection 0: 1X 1: 2X 7.4.16 PIN 18 Register Settings Table 21. PIN 18 Register Settings Signal Function Register Bit Address Register Definition PIN 18 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 18 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 18 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 18 Driver Strength Selection 0: 1X 1: 2X 000-0046722-111 Page 21 of 82 SLG46722 7.4.17 PIN 19 Register Settings Table 22. PIN 19 Register Settings Signal Function Register Bit Address Register Definition PIN 19 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 19 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 19 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 19 Driver Strength Selection 0: 1X 1: 2X 7.4.18 PIN 20 Register Settings Table 23. PIN 20 Register Settings Signal Function Register Bit Address Register Definition PIN 20 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved PIN 20 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 20 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor PIN 20 Driver Strength Selection 0: 1X 1: 2X 000-0046722-111 Page 22 of 82 SLG46722 7.5 GPI IO Structure 7.5.1 GPI IO Structure (for Pin 2) 10 k Floating 90 k S0 S1 S2 S3 900 k Res_sel[1:0] 00: floating 01: 10 k 10: 100 k 11: 1 M wosmt_en PAD Input Mode [1:0] 00: Digital In without Schmitt Trigger, wosmt_en=1 01: Digital In with Schmitt Trigger, smt_en=1 10: Low Voltage Digital In mode, lv_en = 1 11: Reserved smt_en lv_en Non-Schmitt Trigger Input Schmitt Trigger Input Digital In Low Voltage Input Figure 2. PIN 2 GPI IO Structure Diagram 000-0046722-111 Page 23 of 82 SLG46722 7.6 Register OE IO Structure 7.6.1 Register OE IO Structure (for Pins 3, 4, 5, 6, 7, 8, 9, 13, 14, 15, 16, 17, 18, 19, 20) Mode [2:0] 000: Digital In without Schmitt Trigger, wosmt_en=1, OE = 0 001: Digital In with Schmitt Trigger, smt_en=1, OE = 0 010: Low Voltage Digital In mode, lv_en = 1, OE = 0 011: Reserved 100: push-pull mode, pp_en=1, OE = 1 101: NMOS open drain mode, odn_en=1, OE = 1 110: PMOS open drain mode, odp_en=1, OE = 1 111: Reserved wosmt_en smt_en Non-Schmitt Trigger Input Schmitt Trigger Input lv_en Digital In Low Voltage Input odp_en Digital Out Digital Out S1 OE odn_en OE S0 2x_en 10 k pp_en Floating 90 k 900 k S0 S1 S2 S3 PAD pull_up_en odp_en Res_sel[1:0] 00: floating 01: 10 k 10: 100 k 11: 1 M Digital Out Digital Out OE OE 2x_en 2x_en odn_en pp_en Figure 3. Register OE IO Structure Diagram 000-0046722-111 Page 24 of 82 SLG46722 7.7 Register OE IO Structure with Super Driver 7.7.1 Register OE IO Structure with Super Driver (for Pins 10, 12) Mode [2:0] 000: Digital In without Schmitt Trigger, wosmt_en=1 001: Digital In with Schmitt Trigger, smt_en=1 010: Low Voltage Digital In mode, lv_en = 1 011: Reserved 100: push-pull mode, pp_en=1 101: NMOS open drain mode, odn_en=1 110: PMOS open drain mode, odp_en=1 111: Reserved wosmt_en smt_en lv_en Non-Schmitt Trigger Input Schmitt Trigger Input Digital In Low Voltage Input odp_en Digital Out Digital Out S1 OE odn_en OE S0 2x_en 10 k pp_en Floating 90 k 900 k S0 S1 S2 S3 PAD odp_en Res_sel[1:0] 00: floating 01: 10 k 10: 100 k 11: 1 M Digital Out Digital Out OE pull_up_en OE 2x_en 2x_en odn_en pp_en Digital Out OE 4x_en odn_en Figure 4. Register OE IO with Super Driver Structure Diagram 000-0046722-111 Page 25 of 82 SLG46722 8.0 Connection Matrix The Connection Matrix in the SLG46722 is used to create the internal routing for internal functions of the device once it is programmed. The registers are programmed from the one-time NVM cell during Test Mode Operation. All of the connection point for each logic cell within the SLG46722 has a specific digital bit code assigned to it that is either set to active “High” or inactive “Low” based on the design that is created. Once the 1024 register bits within the SLG46722 are programmed a fully custom circuit will be created. The Connection Matrix has 64 inputs and 95 outputs. Each of the 64 inputs to the Connection Matrix is hard-wired to a particular source macrocell, including I/O pins, LUTs, other digital resources and VDD and VSS. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines. For a complete list of the SLG46722’s register table, see Section 18.0 Appendix A - SLG46722 Register Definition. Matrix Input Signal Functions N VSS 0 Pin 2 Digital In 1 Pin 3 Digital In 2 Pin 4 Digital In 3 Resetb_core 62 VDD 63 Matrix Inputs Matrix Outputs N 0 1 2 93 Registers reg reg reg reg Function PIN3 Digital Output Source PIN4 Digital Output Source PIN5 Digital Output Source Input of Filter_1 Figure 5. Connection Matrix 000-0046722-111 Page 26 of 82 SLG46722 8.1 Matrix Input Table Table 24. Matrix Input Table Matrix Decode N Matrix Input Signal Function 5 4 3 2 1 0 0 VSS 0 0 0 0 0 0 1 pin2 digital Input 0 0 0 0 0 1 2 pin3 digital Input 0 0 0 0 1 0 3 pin4 digital Input 0 0 0 0 1 1 4 pin5 digital Input 0 0 0 1 0 0 5 pin6 digital Input 0 0 0 1 0 1 6 pin7 digital Input 0 0 0 1 1 0 7 pin8 digital Input 0 0 0 1 1 1 8 pin9 digital Input 0 0 1 0 0 0 9 pin10 digital Input 0 0 1 0 0 1 10 counter/delay_0 output 14 bit 0 0 1 0 1 0 11 counter/delay_1 output 14 bit w/ ext CK, reset 0 0 1 0 1 1 12 counter/delay_2 output 8 bit w/ ext CK, reset 0 0 1 1 0 0 13 counter/delay_3 output 8 bit w/ ext CK, reset 0 0 1 1 0 1 14 counter/delay_4 output 8 bit 0 0 1 1 1 0 15 counter/delay_5 output 8 bit 0 0 1 1 1 1 16 counter/delay_6 output 8 bit 0 1 0 0 0 0 17 counter/delay _7 output 14 bit 0 1 0 0 0 1 18 DFF/LATCH_0 Q output with resetb or setb 0 1 0 0 1 0 19 DFF/LATCH_0 nQ output with resetb or setb 0 1 0 0 1 1 20 DFF/LATCH_1 output with resetb or setb 0 1 0 1 0 0 21 DFF/LATCH_2 output with resetb or setb 0 1 0 1 0 1 22 DFF/LATCH_3 output with resetb or setb 0 1 0 1 1 0 23 DFF/LATCH_5 output 0 1 0 1 1 1 24 DFF/LATCH_6 output 0 1 1 0 0 0 25 LUT4_0 output 0 1 1 0 0 1 26 LUT3_0 output 0 1 1 0 1 0 27 LUT3_1 output 0 1 1 0 1 1 28 LUT3_2 output 0 1 1 1 0 0 29 LUT3_3 output 0 1 1 1 0 1 30 LUT3_4 output 0 1 1 1 1 0 31 LUT3_5 output 0 1 1 1 1 1 32 LUT3_6 output 1 0 0 0 0 0 33 LUT3_7 output 1 0 0 0 0 1 34 LUT3_8 output (1st stage pipe 1 delay output) 1 0 0 0 1 0 35 LUT3_9 output 1 0 0 0 1 1 36 LUT2_0 output (DFF/LATCH_4 output) 1 0 0 1 0 0 37 LUT2_1 output 1 0 0 1 0 1 000-0046722-111 Page 27 of 82 SLG46722 Table 24. Matrix Input Table Matrix Decode N Matrix Input Signal Function 5 4 3 2 1 0 38 LUT2_2 output 1 0 0 1 1 0 39 LUT2_3 output 1 0 0 1 1 1 40 LUT2_4 output 1 0 1 0 0 0 41 LUT2_5 output 1 0 1 0 0 1 42 pipe1 delay output0 1 0 1 0 1 0 43 pipe1 delay output1 1 0 1 0 1 1 44 Edge detect output 1 0 1 1 0 0 45 Programmable delay with edge detector 1 0 1 1 0 1 46 internal oscillator output 1 0 1 1 1 0 47 internal oscillator divided by 4 output 1 0 1 1 1 1 48 internal oscillator divided by 8, 12, 24, 64 output 1 1 0 0 0 0 49 internal oscillator divided by 3 output 1 1 0 0 0 1 50 pin12 digital Input 1 1 0 0 1 0 51 pin13 digital Input 1 1 0 0 1 1 52 pin14 digital Input 1 1 0 1 0 0 53 pin15 digital Input 1 1 0 1 0 1 54 pin16 digital Input 1 1 0 1 1 0 55 pin17 digital Input 1 1 0 1 1 1 56 pin18 digital Input 1 1 1 0 0 0 57 pin19 digital Input 1 1 1 0 0 1 58 pin20 digital Input 1 1 1 0 1 0 59 filter_0 output 1 1 1 0 1 1 60 matrix input divide by 3 1 1 1 1 0 0 61 filter_1 output 1 1 1 1 0 1 62 Reset_core as matrix input 1 1 1 1 1 0 63 VDD 1 1 1 1 1 1 000-0046722-111 Page 28 of 82 SLG46722 8.2 Matrix Output Table Table 25. Matrix Output Table Register Bit Address Matrix Output Signal Function Matrix Output Number reg Matrix Out: PIN3 Digital Output Source 0 reg Matrix Out: PIN4 Digital Output Source 1 reg Matrix Out: PIN5 Digital Output Source 2 reg Matrix Out: PIN6 Digital Output Source 3 reg Matrix Out: PIN7 Digital Output Source 4 reg Matrix Out: PIN8 Digital Output Source 5 reg Matrix Out: PIN9 Digital Output Source 6 reg Matrix Out: PIN10 Digital Output Source (Super Drive) 7 reg Matrix Out: Input for delay0 or Counter0 external clock 8 reg Matrix Out: Input for delay1 or counter1 reset input 9 reg Matrix Out: Input for Counter1 external clock or delay1 external clock 10 reg Matrix Out: Input for delay2 or counter2 reset input 11 reg Matrix Out: Input for Counter2 external clock or delay2 external clock 12 reg Matrix Out: Input for delay3 or counter3 reset input 13 reg Matrix Out: Input for Counter3 external clock or delay3 external clock 14 reg Matrix Out: Input for delay4 or Counter4 external clock 15 reg Matrix Out: Input for delay5 or Counter5 external clock 16 reg Matrix Out: Input for delay6 or Counter6 external clock 17 reg Matrix Out: Input for delay7 or Counter7 external clock 18 reg Matrix Out: Clock Input of DFF0 19 reg Matrix Out: Data Input of DFF0 20 reg Matrix Out: Resetb (Setb) of DFF0 21 reg Matrix Out: Clock Input of DFF1 22 reg Matrix Out: Data Input of DFF1 23 reg Matrix Out: Resetb (Setb) of DFF1 24 reg Matrix Out: Clock Input of DFF2 25 reg Matrix Out: Data Input of DFF2 26 reg Matrix Out: Resetb (Setb) of DFF2 27 reg Matrix Out: Clock Input of DFF3 28 reg Matrix Out: Data Input of DFF3 29 reg Matrix Out: Resetb (Setb) of DFF3 30 reg Matrix Out: Clock Input of DFF5 31 reg Matrix Out: Data Input of DFF5 32 reg Matrix Out: Clock Input of DFF6 33 reg Matrix Out: Data Input of DFF6 34 reg Matrix Out: In0 of LUT4_0 35 reg Matrix Out: In1 of LUT4_0 36 reg Matrix Out: In2 of LUT4_0 37 000-0046722-111 Page 29 of 82 SLG46722 Table 25. Matrix Output Table Register Bit Address Matrix Output Signal Function Matrix Output Number reg Matrix Out: In3 of LUT4_0 38 reg Matrix Out: In0 of LUT3_0 39 reg Matrix Out: In1 of LUT3_0 40 reg Matrix Out: In2 of LUT3_0 41 reg Matrix Out: In0 of LUT3_1 42 reg Matrix Out: In1 of LUT3_1 43 reg Matrix Out: In2 of LUT3_1 44 reg Matrix Out: In0 of LUT3_2 45 reg Matrix Out: In1 of LUT3_2 46 reg Matrix Out: In2 of LUT3_2 47 reg Matrix Out: In0 of LUT3_3 48 reg Matrix Out: In1 of LUT3_3 49 reg Matrix Out: In2 of LUT3_3 50 reg Matrix Out: In0 of LUT3_4 51 reg Matrix Out: In1 of LUT3_4 52 reg Matrix Out: In2 of LUT3_4 53 reg Matrix Out: In0 of LUT3_5 54 reg Matrix Out: In1 of LUT3_5 55 reg Matrix Out: In2 of LUT3_5 56 reg Matrix Out: In0 of LUT3_6 57 reg Matrix Out: In1 of LUT3_6 58 reg Matrix Out: In2 of LUT3_6 59 reg Matrix Out: In0 of LUT3_7 60 reg Matrix Out: In1 of LUT3_7 61 reg Matrix Out: In2 of LUT3_7 62 reg Matrix Out: In0 of LUT3_8 or Input of Pipe delay 63 reg Matrix Out: In1 of LUT3_8 or Resetb of Pipe delay 64 reg Matrix Out: In2 of LUT3_8 or Clock of Pipe delay 65 reg Matrix Out: In0 of LUT3_9 66 reg Matrix Out: In1 of LUT3_9 67 reg Matrix Out: In2 of LUT3_9 68 reg Matrix Out: In0 of LUT2_0 or Clock Input of DFF4 69 reg Matrix Out: In1 of LUT2_0 or Data Input of DFF4 70 reg Matrix Out: In0 of LUT2_1 71 reg Matrix Out: In1 of LUT2_1 72 reg Matrix Out: In0 of LUT2_2 73 reg Matrix Out: In1 of LUT2_2 74 reg Matrix Out: In0 of LUT2_3 75 reg Matrix Out: In1 of LUT2_3 76 000-0046722-111 Page 30 of 82 SLG46722 Table 25. Matrix Output Table Register Bit Address Matrix Output Signal Function Matrix Output Number reg Matrix Out: In0 of LUT2_4 77 reg Matrix Out: In1 of LUT2_4 78 reg Matrix Out: In0 of LUT2_5 79 reg Matrix Out: In1 of LUT2_5 80 reg Matrix Out: Input for programmable delay & edge detector 81 reg Matrix Out: Power down for osc 82 reg Matrix Out: Pin12 Digital Output Source (Super Drive) 83 reg Matrix Out: Pin13 Digital Output Source 84 reg Matrix Out: Pin14 Digital Output Source 85 reg Matrix Out: Pin15 Digital Output Source 86 reg Matrix Out: Pin16 Digital Output Source 87 reg Matrix Out: Pin17 Digital Output Source 88 reg Matrix Out: Pin18 Digital Output Source 89 reg Matrix Out: Pin19 Digital Output Source 90 reg Matrix Out: Pin20 Digital Output Source 91 reg Matrix Out: Input of filter_0 92 reg Matrix Out: Input of filter_1 93 reg Reserved 94 000-0046722-111 Page 31 of 82 SLG46722 9.0 Combinatorial Logic Combinatorial logic is supported via fifteen Lookup Tables (LUTs) within the SLG46722. There are five 2-bit LUTs, nine 3-bit LUTs, and one 4-bit LUT. The device also includes two Combination Function Macrocells that can be used as LUTs. For more details, please see Section 10.0 Combination Function Macro Cells. Inputs/Outputs for the fifteen LUTs are configured from the connection matrix with specific logic functions being defined by the state of NVM bits. The outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR). 9.1 2-Bit LUT The five 2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the connection matrix. reg From Connection Matrix Output From Connection Matrix Output reg IN0 To Connection Matrix Input 2-bit LUT1 From Connection Matrix Output From Connection Matrix Output IN1 From Connection Matrix Output OUT IN1 reg To Connection Matrix Input IN0 2-bit LUT3 To Connection Matrix Input 2-bit LUT2 OUT reg From Connection Matrix Output IN0 From Connection Matrix Output 2-bit LUT4 OUT From Connection Matrix Output IN1 To Connection Matrix Input IN0 OUT IN1 reg From Connection Matrix Output From Connection Matrix Output To Connection Matrix Input IN0 2-bit LUT5 OUT IN1 Figure 6. 2-bit LUTs 000-0046722-111 Page 32 of 82 SLG46722 Table 29. 2-bit LUT4 Truth Table. Table 26. 2-bit LUT1 Truth Table. IN1 IN0 OUT IN1 IN0 OUT 0 0 reg 0 0 reg 0 1 reg 0 1 reg 1 0 reg 1 0 reg 1 1 reg 1 1 reg Table 27. 2-bit LUT2 Truth Table. Table 30. 2-bit LUT5 Truth Table. IN1 IN0 OUT IN1 IN0 OUT 0 0 reg 0 0 reg 0 1 reg 0 1 reg 1 0 reg 1 0 reg 1 1 reg 1 1 reg Table 28. 2-bit LUT3 Truth Table. IN1 IN0 OUT 0 0 reg 0 1 reg 1 0 reg 1 1 reg Each 2-bit LUT uses a 4-bit register signal to define their output functions; 2-Bit LUT1 is defined by reg 2-Bit LUT2 is defined by reg 2-Bit LUT3 is defined by reg 2-Bit LUT4 is defined by reg 2-Bit LUT5 is defined by reg