SLG7NT408V
Ultra-small 7.8 mΩ, 4 A
Integrated Power Switch
General Description
Pin Configuration
The SLG7NT408V is a 7.8 mΩ 4 A single-channel load switch
that is able to switch 0.85 to 5 V power rails. The product is
packaged in an ultra-small 1.5 x 2.0 mm package.
• 1.5 x 2.0 mm FC-TDFN 8L package (2 fused pins for drain
and 2 fused pins for source)
• Logic level ON pin capable of supporting 0.85 V CMOS
Logic
• User selectable ramp rate with external capacitor
• 7.8 mΩ RDSONwhile supporting 4 A
• Two Over Current Protection Modes
• Short Circuit Current Limit
• Active Current Limit
• Over Temperature Protection
• Pb-Free / Halogen-Free / RoHS compliant
• Operating Temperature: -20 °C to 70°C
• Operating Voltage: 2.5 V to 5.5 V
1
ON
2
D
3
D
4
SLG7NT408V
Features
VDD
8
GND
7
CAP
6
S
5
S
8-pin FC-TDFN
(Top View)
Applications
• Notebook Power Rail Switching
• Tablet Power Rail Switching
• Smartphone Power Rail Switching
Block Diagram
4 A @ 7.8 mΩ
D
+2.5 to 5.5 V
CAP
S
Charge
Pump
Linear Ramp
Control
Over Current and
Over Temperature
Protection
ON
Silego Technology, Inc.
000-007NT408-101
CMOS Input
Rev 1.01
Revised September 9, 2015
SLG7NT408V
Pin Description
Pin #
Pin Name
Type
Pin Description
1
VDD
PWR
VDD power for load switch control (2.5 V to 5.5 V)
2
ON
Input
Turns MOSFET ON (4 MΩ pull down resistor)
CMOS input with VIL < 0.3 V, VIH > 0.85 V
3
D
MOSFET
Drain of Power MOSFET (fused with pin 4)
4
D
MOSFET
Drain of Power MOSFET (fused with pin 3)
5
S
MOSFET
Source of Power MOSFET (fused with pin 6)
6
S
MOSFET
Source of Power MOSFET (fused with pin 5)
7
CAP
Input
Capacitor for controlling power rail ramp rate
8
GND
GND
Ground
Ordering Information
Part Number
Type
Production Flow
SLG7NT408V
FC-TDFN 8L
Commercial, -20 °C to 70 °C
SLG7NT408VTR
FC-TDFN 8L (Tape and Reel)
Commercial, -20 °C to 70 °C
000-007NT408-101
Page 2 of 11
SLG7NT408V
Absolute Maximum Ratings
Parameter
VDD
TS
ESDHBM
WDIS
Description
Conditions
Min.
Typ.
Max.
Unit
--
--
7
V
-65
--
150
°C
2000
--
--
V
--
--
1
W
--
--
6
A
Power Supply
Storage Temperature
ESD Protection
Human Body Model
Package Power Dissipation
MOSFET IDSPK Peak Current from Drain to Source For no more than 1 ms with 1% duty cycle
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Electrical Characteristics
TA = -20 to 70 °C (unless otherwise stated)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VDD
Power Supply Voltage
-20 to 70°C
2.5
--
5.5
V
IDD
Power Supply Current (PIN 1)
when OFF
--
--
1
μA
when ON, No load
--
70
100
μA
Static Drain to Source
ON Resistance
TA 25°C @ 100 mA
--
7.8
8.5
mΩ
TA 70°C @ 100 mA
--
8.5
9.6
mΩ
IDS
Operating Current
VD = 1.0 V to 5.5 V
--
--
4
A
VD
Drain Voltage
0.85
--
VDD
V
0
300
500
μs
RDSON
TON_Delay
ON pin Delay Time
50% ON to Ramp Begin,
RL = 20 Ω, CL= 10 μF
Configurable 1
50% ON to 90% VS
TTotal_ON
Total Turn On Time
Example: CAP (PIN 7) = 4 nF, VDD =
VD = 5 V, Source_Cap = 10 μF,
RL = 20 Ω
--
Slew Rate
CAPSOURCE Source Cap
--
ms
Configurable 1
10% VS to 90% VS
TSLEWRATE
1.96
ms
V/ms
Example: CAP (PIN 7) = 4 nF, VDD =
VD = 5 V, Source_Cap = 10 μF,
RL = 20 Ω
--
3.0
--
V/ms
Source to GND
--
--
500
μF
ON_VIH
High Input Voltage on ON pin
0.85
--
VDD
V
ON_VIL
Low Input Voltage on ON pin
-0.3
0
0.3
V
Active Current Limit
MOSFET will automatically limit current when VS > 250 mV
--
6.0
--
A
Short Circuit Current Limit
MOSFET will automatically limit current when VS < 250 mV
--
--
0.5
A
ILIMIT
THERMON
Thermal shutoff turn-on temperature
--
125
--
°C
THERMOFF
Thermal shutoff turn-off temperature
--
100
--
°C
THERMTIME Thermal shutoff time
TOFF_Delay
TFALL
--
--
1
ms
OFF Delay Time
50% ON to VS Fall, VDD = VD = 5 V,
RL = 20 Ω, no CL
--
--
15
μs
VS Fall Time
90% VS to 10% VS, VDD = VD = 5 V,
RL = 20 Ω, no CL
--
TBD
--
μs
Notes:
1. Refer to table for configuration details.
000-007NT408-101
Page 3 of 11
SLG7NT408V
SLG7NT408V Turn ON
The normal power on sequence is first VDD, with VD only being applied after VDD is > 1 V, and then ON after VD is at least 90%
of final value. The normal power off sequence is the power on sequence in reverse.
If VDD and VD are turned on at the same time then it is possible that a voltage glitch will appear on VS before VDD achieves 1V
which is the VT of the main MOSFET. The size of the glitch is dependent on source and drain capacitance loading and the ramp
rate of VDD & VD.
SLG7NT408V Turn ON
The VS ramp follows a linear path, not an RC limitation provided the ramp is slow enough to not be current limited by load
capacitance.
SLG7NT408V Current Limiting
The SLG7NT408V has two forms of current limiting.
Standard Current Limiting Mode
Current is measured by mirroring the current through the main MOSFET. The mirrored current is then sent through a resistor
creating a voltage V(i) proportional to the MOSFET current. The V(i) is then compared with a Band Gap voltage V(BG). If V(i)
exceeds the Band Gap voltage then the voltage V(g) on the gate of the main MOSFET is reduced. The V(g) continues to drop
until V(i) < V(BG). This response is a closed loop response and is therefore very fast and current limits in less than a few
micro-seconds. There is no difference between peak or constant current limit.
Temperature Cutoff
However, as the V(g) drops the Rds(ON) of the main MOSFET will increase, thus limiting the current, but also increasing the
power dissipation of the IC. The IC is very small and cannot dissipate much power. Therefore, if a current limit condition is
sustained the IC will heat up. If the temperature exceeds approximately 120°C, then V(g) will be brought low completely shutting
off the main MOSFET. As the die cools the MOSFET will be turned back on at 100°C.
If the current limiting condition has not been mitigated then the die will again heat up to 120°C and the process will repeat.
Short Circuit Current Limiting Mode
When V(S) < 250 mV, which is the case if there is a solder bridge during the manufacturing process or a hard short on the power
rail, then the current is limited to approximately 500 mA. This current limit is accomplished in the same manner as the Standard
Current Limiting Mode with the exception that the current mirror is 15x greater. Because the current mirror is so much larger, a
15x smaller main MOSFET current is required to generate the same V(i). If V(S) rises above approximately 250 mV, then this
mode is automatically switched out.
000-007NT408-101
Page 4 of 11
SLG7NT408V
TTotal_ON vs. CAP @ VDD = 3.3 V
SLG7NT408V TTotal_ON: ON (50%) - VS (90%)
VDD = 3.3 V, TA = 25 °C. CL = 10 μF, IDS = 100 mA
6
5
Ttotal_on (ms)
4
VD = 1.5V
3
VD = 2.5V
VD = 3.3V
2
1
0
0
2000
4000
6000
8000
10000
12000
14000
16000
Cap (pf)
TTotal_ON vs. CAP @ VDD = 5.0 V
SLG7NT408V TTotal_ON: ON (50%) - VS (90%)
VDD = 5.0 V, TA = 25 °C. CL = 10 μF, IDS = 100 mA
6
5
Ttotal_on (ms)
4
VD = 1.50V
VD = 2.50V
3
VD = 3.30V
VD = 5.00V
2
1
0
0
2000
4000
6000
8000
10000
12000
14000
16000
Cap (pf)
000-007NT408-101
Page 5 of 11
SLG7NT408V
TSLEW vs. CAP @ VDD = 3.3 V
SLG7NT408V TSLEW: VS (10%) - VS (90%)
VDD = 3.3 V, TA = 25 °C. CL = 10 μF, IDS = 100 mA
15
14
13
12
11
10
V/ms
9
VD = 1.50V
8
VD = 2.50V
7
VD = 3.30V
6
5
4
3
2
1
0
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000 11000 12000 13000 14000 15000 16000
Cap (pf)
TSLEW vs. CAP @ VDD = 5.0 V
SLG7NT408V TSLEW: VS (10%) - VS (90%)
VDD = 5.0 V, TA = 25 °C. CL = 10 μF, IDS = 100 mA
15
14
13
12
11
10
V/ms
9
VD = 1.50V
8
VD = 2.50V
VD = 3.30V
7
VD = 5.00V
6
5
4
3
2
1
0
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000 11000 12000 13000 14000 15000 16000
Cap (pf)
000-007NT408-101
Page 6 of 11
SLG7NT408V
TTotal_ON, TON_Delay and Slew Rate Measurement
ON
50% ON
50% ON
TOFF_DELAY
90% VS
VS
90% VS
TON_DELAY
10% VS
10% VS
Slew Rate (V/ms)
TFALL
TTotal_ON
000-007NT408-101
Page 7 of 11
SLG7NT408V
Package Top Marking System Definition
Date Code + Revision
Pin 1 Identifier
000-007NT408-101
XXA
DDR
LL
Part Code + Assembly Site
Lot Traceability
Page 8 of 11
SLG7NT408V
Package Drawing and Dimensions
8 Lead TDFN Package 1.5 x 2.0 mm (Fused Lead)
JEDEC MO-252, Variation W2015D
Index Area (D/2 x E/2)
L
A1
1
e
8
b
(8X)
D
S
L1
L2
A2
A
E
Unit: mm
Symbol
A
A1
A2
b
D
E
000-007NT408-101
Min
0.70
0.005
0.15
0.15
1.95
1.45
Nom.
0.75
0.20
0.20
2.00
1.50
Max Symbol Min
Nom.
L
0.80
0.35
0.40
L1
0.060
0.515 0.565
0.135 0.185
L2
0.25
e
0.50 BSC
0.25
0.37 REF
S
2.05
1.55
Max
0.45
0.615
0.235
Page 9 of 11
SLG7NT408V
Tape and Reel Specifications
Max Units
Leader (min)
Nominal
Reel &
Package # of
Package Size
Hub Size
Length
Type
Pins
per Reel per Box
Pockets
[mm]
[mm]
[mm]
TDFN 8L
FC Green
8
1.5 x 2.0 x 0.75
3000
3000
178 / 60
100
400
Trailer (min)
Pockets
Length
[mm]
Tape
Width
[mm]
100
400
8
Part
Pitch
[mm]
4
Carrier Tape Drawing and Dimensions
Pocket BTM Pocket BTM
Package
Length
Width
Type
TDFN 8L
FC Green
Pocket
Depth
Index Hole
Pitch
Pocket
Pitch
Index Hole
Diameter
Index Hole Index Hole
to Tape
to Pocket Tape Width
Edge
Center
A0
B0
K0
P0
P1
D0
E
F
W
1.68
2.18
0.9
4
4
1.5
1.75
3.5
8
P0
D0
Y
E
W
F
Section Y-Y
Y
P1
A0
B0
CL
K0
Refer to EIA-481 specification
Recommended Reflow Soldering Profile
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 2.25 mm3 (nominal). More
information can be found at www.jedec.org.
000-007NT408-101
Page 10 of 11
SLG7NT408V
Revision History
Date
Version
9/9/2015
1.01
000-007NT408-101
Change
Updated Vd min = 0.85 V
Updated Conditions in Electrical Characteristics Table
Page 11 of 11
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