TBB1010_06

TBB1010 Twin Built in Biasing Circuit MOS FET IC VHF/VHF RF Amplifier REJ03G0844-0500 Rev.5.00 Aug 22, 2006 Features • • • • • Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space. High |yfs|=29mS × 2 Suitable for World Standard Tuner RF amplifier. Very useful for total tuner cost reduction. Withstanding to ESD; Built in ESD absorbing diode. Withstand up to 200 V at C = 200 pF, Rs = 0 conditions. • Provide mini mold packages; CMPAK-6 Outline RENESAS Package code: PTSP0006JA-A (Package name: CMPAK-6) 6 5 4 2 1 3 1. Drain(1) 2. Source 3. Drain(2) 4. Gate-1(2) 5. Gate-2 6. Gate-1(1) Notes: 1. Marking is “KM”. 2. TBB1010 is individual type number of RENESAS TWIN BBFET. Rev.5.00 Aug 22, 2006 page 1 of 7 TBB1010 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate1 to source voltage Gate2 to source voltage Symbol VDS VG1S VG2S Ratings 6 +6 -0 +6 -0 30 250 150 –55 to +150 Unit V V V mA mW °C °C Drain current ID Channel power dissipation Pch*3 Channel temperature Tch Storage temperature Tstg Notes: 3. Value on the glass epoxy board (50mm × 40mm × 1mm). Electrical Characteristics (Ta = 25°C) The below specification are applicable for FET1 and FET2 unit Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Gate2 to source cutoff voltage Drain current Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Power gain Noise figure Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS IG1SS IG2SS VG1S(off) VG2S(off) ID(op) |yfs| Ciss Coss Crss PG NF Min 6 +6 +6 — — 0.6 0.6 12 24 1.7 1.0 — 25 — Typ — — — — — — — 16 29 2.1 1.4 0.03 30 1.1 Max — — — +100 +100 1.1 1.1 20 — 2.5 1.8 0.05 — 1.8 Unit V V V nA nA V V mA mS pF pF pF dB dB Test conditions ID = 200 µA, VG1S = VG2S = 0 IG1 = +10 µA, VG2S = VDS = 0 IG2 = +10 µA, VG1S = VDS = 0 VG1S = +5 V, VG2S = VDS = 0 VG2S = +5 V, VG1S = VDS = 0 VDS = 5 V, VG2S = 4 V, ID = 100 µA VDS = 5 V, VG1S = 5 V, ID = 100 µA VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 120 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 120 kΩ, f = 1 kHz VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 120 kΩ f = 1 MHz VDS = VG1 = 5 V, VG2S = 4 V RG = 120 kΩ, f = 200 MHz Rev.5.00 Aug 22, 2006 page 2 of 7 TBB1010 Test Circuits • DC Biasing Circuit for Operating Characteristic Items (ID(op), |yfs|, Ciss, Coss, Crss, NF, PG) Measurment of FET1 RG VG1 Gate 1 Gate 2 Open VG2 ID VD A Drain Source Open Measurment of FET2 Gate 2 VG2 Open VG1 Gate 1 RG A Open Source Drain ID VD Rev.5.00 Aug 22, 2006 page 3 of 7 TBB1010 • Equivalent Circuit No.1 Drain(1) No.6 Gate-1(1) No.2 Source BBFET-(1) BBFET-(2) No.3 Drain(2) No.5 Gate-2 No.4 Gate-1(2) • 200 MHz Power Gain, Noise Figure Test Circuit VT 1000p VG2 1000p VT 1000p 47k Input (50 Ω) 1000p 36p L1 1000p 47k TWINBBFET L2 1000p 47k Output (50 Ω) 10p max 1000p 1SV70 RG 120k RFC 1SV70 1000p VD = VG1 Unit : Resistance (Ω) Capacitance (F) L1 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns L2 : φ1mm Enameled Copper Wire,Inside dia 10mm, 2Turns RFC : φ1mm Enameled Copper Wire,Inside dia 5mm, 2Turns Rev.5.00 Aug 22, 2006 page 4 of 7 TBB1010 Maximum Channel Power Dissipation Curve Channel Power Dissipation Pch* (mW) 400 25 G= 82 0k kΩ kΩ Ω Typical Output Characteristics VG2S = 4 V VG1 = VDS R 300 Drain Current ID (mA) 20 200 10 100 5 0 50 100 150 200 0 1 2 3 4 12 kΩ 0 15 Ω 0k 18 0 15 10 5 Ambient Temperature Ta (°C) * Value on the glass epoxy board (50mm × 40mm × 1mm) Drain to Source Voltage VDS (V) Drain Current vs. Gate1 Voltage 25 VDS = 5 V RG = 120 kΩ 4V Forward Transfer Admittance vs. Gate1 Voltage Forward Transfer Admittance |yfs| (mS) 50 VDS = 5 V RG = 120 kΩ 40 f = 1 kHz 30 4V Drain Current ID (mA) 20 15 3V 3V 10 2V 20 2V 5 VG2S = 1 V 10 VG2S = 1 V 0 1 2 3 4 5 0 1 2 3 4 5 Gate1 Voltage VG1 (V) Gate1 Voltage VG1 (V) Input Capacitance vs. Gate2 to Source Voltage 4 Drain Current vs. Gate Resistance 30 25 Input Capacitance Ciss (pF) Drain Current ID (mA) VDS = 5 V VG1 = 5 V VG2S = 4 V 3 20 15 10 5 0 10 2 VDS = 5 V VG1 = 5 V RG = 120 kΩ f = 1 MHz 0 1 2 3 4 1 0 20 50 100 200 500 1000 Gate Resistance RG (kΩ) Gate2 to Source Voltage VG2S (V) Rev.5.00 Aug 22, 2006 page 5 of 7 TBB1010 Power Gain vs. Gate Resistance 40 35 4 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 200 MHz Noise Figure vs. Gate Resistance Noise Figure NF (dB) 100 200 500 1000 Power Gain PG (dB) 3 30 25 20 15 10 10 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 200 MHz 20 50 2 1 0 10 20 50 100 200 500 1000 Gate Resistance RG (kΩ) Gate Resistance RG (kΩ) Gain Reduction vs. Gate2 to Source Voltage 50 Gain Reduction GR (dB) 40 VDS = VG1 = 5 V RG = 120 kΩ 30 20 10 0 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) Rev.5.00 Aug 22, 2006 page 6 of 7 TBB1010 Package Dimensions Package Name CMPAK-6 JEITA Package Code SC-88 RENESAS Code PTSP0006JA-A Previous Code CMPAK-6 / CMPAK-6V MASS[Typ.] 0.006g D e A Q c E HE LP L A xM A SA b L1 A3 e Reference Symbol Dimension in Millimeters A2 A yS b b1 c c1 A1 S e1 l1 b2 A-A Section Pattern of terminal position areas A A1 A2 A3 b b1 c c1 D E e HE L L1 LP x y b2 e1 l1 Q Min 0.8 0 0.8 0.15 0.1 1.8 1.15 2.0 0.3 0.1 0.2 Nom 0.9 0.25 0.22 0.2 0.13 0.11 2.0 1.25 0.65 2.1 Max 1.1 0.1 1.0 0.3 0.15 2.2 1.35 2.2 0.7 0.5 0.6 0.05 0.05 0.35 0.9 1.5 0.25 Ordering Information Part Name TBB1010KMTL-E Quantity 3000 Shipping Container φ 178 mm Reel, 8 mm Emboss Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.5.00 Aug 22, 2006 page 7 of 7 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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