TBB1017

TBB1017 Twin Built in Biasing Circuit MOS FET IC UHF/VHF RF Amplifier REJ03G1469-0100 Rev.1.00 Aug 07, 2006 Features • • • • • • • Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space. Very useful for total tuner cost reduction. Suitable for World Standard Tuner RF amplifier. High gain Low noise Low output capacitance Power supply voltage: 5 V Outline RENESAS Package code: PTSP0006JA-A (Package name: CMPAK-6) 5 4 6 2 1 3 1. Drain(1) 2. Source 3. Gate-1(1) 4. Gate-1(2) 5. Gate-2 6. Drain(2) Notes: 1. Marking is “SM“. 2. TBB1017 is individual type number of Renesas TWIN BBFET. Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate1 to source voltage Gate2 to source voltage Symbol VDS VG1S VG2S Ratings 6 +6 –0 +6 –0 30 250 150 –55 to +150 Unit V V V mA mW °C °C Drain current ID Channel power dissipation PchNote3 Channel temperature Tch Storage temperature Tstg Notes: 3. Value on the glass epoxy board (50mm × 40mm × 1mm). Rev.1.00 Aug 07, 2006 page 1 of 13 TBB1017 Electrical Characteristics • FET1 (Ta = 25°C) Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Gate2 to source cutoff voltage Drain current Forward transfer admittance Input capacitance Output capacitance Power gain Noise figure Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS IG1SS IG2SS VG1S(off) VG2S(off) ID(op) |yfs| Ciss Coss PG NF Min 6 +6 +6 — — 0.5 0.4 12 27 1.3 0.7 15 — Typ — — — — — 0.8 0.7 16 32 1.7 1.1 20 1.95 Max — — — +100 +100 1.1 1.0 20 38 2.1 1.5 25 2.7 Unit V V V nA nA V V mA mS pF pF dB dB Test Conditions ID = 200 µA, VG1S = VG2S = 0 IG1 = +10 µA, VG2S = VDS = 0 IG2 = +10 µA, VG1S = VDS = 0 VG1S = +5 V, VG2S = VDS = 0 VG2S = +5 V, VG1S = VDS = 0 VDS = 5 V, VG2S = 4 V, ID = 100 µA VDS = 5 V, VG1S = 5 V, ID = 100 µA VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 100 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V, f = 1 kHz, RG = 100 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V, f = 1 MHz, RG = 100 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 100 kΩ, f = 900 MHz • FET2 (Ta = 25°C) Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Gate2 to source cutoff voltage Drain current Forward transfer admittance Input capacitance Output capacitance Power gain Noise figure Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS IG1SS IG2SS VG1S(off) VG2S(off) ID(op) |yfs| Ciss Coss PG NF Min 6 +6 +6 — — 0.5 0.4 13 25 2.3 0.9 24 — Typ — — — — — 0.8 0.7 17 30 2.7 1.3 29 1.0 Max — — — +100 +100 1.1 1.0 21 35 3.1 1.7 34 1.6 Unit V V V nA nA V V mA mS pF pF dB dB Test Conditions ID = 200 µA, VG1s = VG2S = 0 IG1 = +10 µA, VG2S = VDS = 0 IG2 = +10 µA, VG1S = VDS = 0 VG1S = +5 V, VG2S = VDS = 0 VG2S = +5 V, VG1S = VDS = 0 VDS = 5 V, VG2S = 4 V, ID = 100 µA VDS = 5 V, VG1S = 5 V, ID = 100 µA VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 82 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V, f = 1 kHz, RG = 82 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V, f = 1 MHz, RG = 82 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 82 kΩ, f = 200 MHz Rev.1.00 Aug 07, 2006 page 2 of 13 TBB1017 DC Biasing Circuit for Operating Characteristic Items (ID(op), |yfs|, Ciss, Coss, NF, PG) • Measurement of FET1 Gate 2 VG2 Open Open ID VD A Drain Source Gate 1 RG VG1 • Measurement of FET2 VG2 Gate 2 Drain ID VD A Gate 1 RG VG1 Open Source Open Rev.1.00 Aug 07, 2006 page 3 of 13 TBB1017 900 MHz Power Gain, Noise Figure Test Circuit VG1 VG2 C4 C5 VD C6 R1 R2 C3 G2 R3 D L3 RFC Output (50 Ω) L4 Input (50 Ω) L1 L2 G1 S C1 C2 C1, C2 C3 C4 ~ C6 R1 R2 R3 : : : : : : Variable Capacitor (10 pF MAX) Disk Capacitor (1000 pF) Air Capacitor (1000 pF) 100 kΩ 47 kΩ 4.7 kΩ L1: 10 10 L2: 26 3 3 (φ 1 mm Copper wire) Unit: mm 8 21 L4: 29 10 7 7 10 L3: 18 RFC : φ1 mm Copper wire with enamel 4 turns inside dia 6 mm Rev.1.00 Aug 07, 2006 page 4 of 13 TBB1017 200 MHz Power Gain, Noise Figure Test Circuit VT 1000 p VG2 1000 p VT 1000 p 47 k Input (50 Ω) 1000 p 36 p L1 1000 p 47 k FET2 L2 1000 p 47 k Output (50 Ω) 10 p max 1000 p 1SV70 R1 1000 p V G1 1000 p VD Unit : Resistance (Ω) Capacitance (F) RFC 1SV70 R1 : 82 kΩ L1 : φ1 mm Enameled Copper Wire, Inside dia 10 mm, 2 Turns L2 : φ1 mm Enameled Copper Wire, Inside dia 10 mm, 2 Turns RFC : φ1 mm Enameled Copper Wire, Inside dia 5 mm, 2 Turns Rev.1.00 Aug 07, 2006 page 5 of 13 TBB1017 Main Characteristics • FET1 Maximum Channel Power Dissipation Curve Pch* (mW) 400 25 Typical Output Characteristics VG2S = 4 V VDS = VG1 20 68 kΩ 82 kΩ 300 Channel Power Dissipation ID (mA) 15 100 kΩ 120 kΩ 200 Drain Current 10 kΩ 150 kΩ 100 5 RG =1 80 0 50 100 150 200 0 0 1 2 3 4 5 Ambient Temperature Ta (°C) Drain to Source Voltage VDS (V) * Value on the glass epoxy board (50 mm × 40 mm × 1 mm) Drain Current vs. Gate1 Voltage Forward Transfer Admittance |yfs| (mS) 25 50 VDS = 5 V VG2S = 4 V RG = 100 kΩ Forward Transfer Admittance vs. Gate1 Voltage VDS = 5 V VG2S =4 V RG = 100 kΩ f = 1 kHz ID (mA) 20 40 4V 15 4V 3V 3V 2V 30 20 Drain Current 10 5 VG2S = 1 V 0 0 1 2 3 4 5 10 V G2S = 0 2V 1V 0 0 1 2 3 4 5 Gate1 Voltage VG1 (V) Gate1 Voltage VG1 (V) Drain Current vs. Gate Resistance 25 5 VDS = 5 V VG1 = 5 V VG2S = 4 V Input Capacitance vs. Gate2 to Source Voltage VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 1 MHz 20 Input Capacitance Ciss (pF) ID (mA) 4 15 3 Drain Current 10 2 5 1 0 10 0 100 1000 0 1 2 3 4 Gate Resistance RG (kΩ) Gate2 to Source Voltage VG2S (V) Rev.1.00 Aug 07, 2006 page 6 of 13 TBB1017 Power Gain vs. Gate Resistance 25 5 VDS = 5 V VG1 = 5 V VG2S = 5 V f = 900 MHz Noise Figure vs. Gate Resistance Noise Figure NF (dB) Power Gain PG (dB) 20 4 15 3 10 VDS = 5 V VG1 = 5 V VG2S = 5 V f = 900 MHz 2 5 1 0 10 100 1000 0 10 100 1000 Gate Resistance RG (kΩ) Power Gain vs. Gate2 to Source Voltage 25 20 VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 900 MHz Gate Resistance RG (kΩ) Noise Figure vs. Gate2 to Source Voltage 5 VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 900 MHz 15 Noise Figure NF (dB) 3 4 Power Gain PG (dB) 4 3 2 10 5 0 1 2 1 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) Gain Reduction vs. Gate2 to Source Voltage 40 Gate2 to Source Voltage VG2S (V) Gain Reduction GR (dB) 35 30 25 20 15 10 5 0 0 1 2 VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 900 MHz 3 4 Gate2 to Source Voltage VG2S (V) Rev.1.00 Aug 07, 2006 page 7 of 13 TBB1017 • FET2 Maximum Channel Power Dissipation Curve Pch* (mW) 400 Typical Output Characteristics 25 VG2S = 4 V VDS = VG1 56 kΩ 68 kΩ 82 kΩ ID (mA) 20 300 Channel Power Dissipation 15 200 Drain Current 100 kΩ 10 120 kΩ 150 kΩ 100 5 RG = 180 kΩ 0 0 50 100 150 200 0 1 2 3 4 5 Ambient Temperature Ta (°C) Drain to Source Voltage VDS (V) * Value on the glass epoxy board (50 mm × 40 mm × 1 mm) Drain Current vs. Gate1 Voltage 20 Forward Transfer Admittance vs. Gate1 Voltage Forward Transfer Admittance |yfs| (mS) 50 VDS = 5 V VG2S = 4 V RG = 82 kΩ f = 1 kHz ID (mA) 15 VDS = 5 V VG2S = 4 V RG = 82 kΩ 4V 40 4V 30 3V 20 2V VG2S = 1 V 0 1 2 3 4 5 Drain Current 10 2V 5 VG2S = 1 V 0 0 1 2 3 4 5 10 0 Gate1 Voltage VG1 (V) Gate1 Voltage VG1 (V) Drain Current vs. Gate Resistance 30 5 VDS = 5 V VG1 = 5 V VG2S = 4 V Input Capacitance vs. Gate2 to Source Voltage 25 Input Capacitance Ciss (pF) ID (mA) 4 20 3 Drain Current 15 2 VDS = 5 V VG1 = 5 V RG =82 kΩ f = 1 MHz 10 1 5 10 0 100 1000 0 1 2 3 4 Gate Resistance RG (kΩ) Gate2 to Source Voltage VG2S (V) Rev.1.00 Aug 07, 2006 page 8 of 13 TBB1017 Power Gain vs. Gate Resistance 35 3 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 200 MHz Noise Figure vs. Gate Resistance Noise Figure NF (dB) Power Gain PG (dB) 30 2 25 20 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 200 MHz 1 15 10 10 100 1000 0 10 100 1000 Gate Resistance RG (kΩ) Power Gain vs. Gate2 to Source Voltage 35 30 25 20 15 10 5 1 2 3 4 5 Gate Resistance RG (kΩ) Noise Figure vs. Gate2 to Source Voltage Noise Figure NF (dB) Power Gain PG (dB) 4 VDS =5 V VG1 =5 V RG =82 kΩ f = 200 MHz 3 2 VDS = 5 V VG1 = 5 V RG = 82 kΩ f = 200 MHz 1 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) Gain Reduction vs. Gate2 to Source Voltage 50 45 VDS = 5 V VG1 = 5 V RG = 82 kΩ f = 200 MHz Gate2 to Source Voltage VG2S (V) Gain Reduction GR (dB) 40 35 30 25 20 15 10 5 0 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) Rev.1.00 Aug 07, 2006 page 9 of 13 TBB1017 • FET1 S11 Parameter vs. Frequency .8 .6 .4 3 .2 4 5 10 0 .2 .4 .6 .8 1 1.5 2 3 45 –10 –.2 –5 –4 –3 –.4 –2 –.6 –.8 –1 –1.5 –120° –90° –60° 180° 0° 150° 30° 1 1.5 2 120° S21 Parameter vs. Frequency 90° Scale: 5 / div. 60° –150° –30° Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 100 kΩ 0.05 to 1.05 GHz (0.05 GHz step) Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 100 kΩ 0.05 to 1.05 GHz (0.05 GHz step) S12 Parameter vs. Frequency 90° 120° S22 Parameter vs. Frequency .8 .6 .4 3 1 1.5 2 30° .2 Scale: 0.05 / div. 60° 150° 4 5 10 180° 0° 0 .2 .4 .6 .8 1 1.5 2 3 45 –10 –.2 –150° –30° –.4 –2 –120° –90° –60° –.6 –.8 –1 –1.5 –5 –4 –3 Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 100 kΩ 0.05 to 1.05 GHz (0.05 GHz step) Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 100 kΩ 0.05 to 1.05 GHz (0.05 GHz step) Rev.1.00 Aug 07, 2006 page 10 of 13 TBB1017 • FET2 S11 Parameter vs. Frequency .8 .6 .4 3 .2 4 5 10 0 .2 .4 .6 .8 1 1.5 2 3 45 –10 –.2 –5 –4 –3 –.4 –2 –.6 –.8 –1 –1.5 –120° –90° –60° 180° 0° 150° 30° 1 1.5 2 120° S21 Parameter vs. Frequency 90° Scale: 5 / div. 60° –150° –30° Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 82 kΩ 0.05 to 1.05 GHz (0.05 GHz step) Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 82 kΩ 0.05 to 1.05 GHz (0.05 GHz step) S12 Parameter vs. Frequency 90° 120° S22 Parameter vs. Frequency .8 .6 .4 3 1 1.5 2 30° .2 Scale: 0.05 / div. 60° 150° 4 5 10 180° 0° 0 .2 .4 .6 .8 1 1.5 2 3 45 –10 –.2 –150° –30° –.4 –2 –120° –90° –60° –.6 –.8 –1 –1.5 –5 –4 –3 Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 82 kΩ 0.05 to 1.05 GHz (0.05 GHz step) Test condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 82 kΩ 0.05 to 1.05 GHz (0.05 GHz step) Rev.1.00 Aug 07, 2006 page 11 of 13 TBB1017 S parameter • FET1 (VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 100 kΩ, Zo = 50 Ω) Freq. (MHz) 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 S11 Mag 0.994 0.992 0.987 0.980 0.972 0.960 0.948 0.932 0.915 0.896 0.875 0.852 0.828 0.803 0.777 0.751 0.725 0.700 0.676 0.653 Deg –4.2 –8.8 –13.1 –17.6 –22.2 –26.9 –31.7 –36.8 –42.1 –47.7 –53.4 –59.5 –65.8 –72.4 –79.2 –86.4 –93.8 –101.4 –109.3 –117.2 Mag 2.97 2.97 2.97 2.97 2.97 2.96 2.97 2.96 2.95 2.94 2.93 2.92 2.89 2.85 2.81 2.77 2.71 2.66 2.59 2.52 S21 Deg 175.6 171.1 166.7 162.2 157.8 153.1 148.1 143.8 139.0 134.2 129.4 124.3 119.4 114.4 109.4 104.3 99.3 94.4 89.4 84.7 Mag 0.001 0.002 0.002 0.003 0.004 0.005 0.005 0.005 0.005 0.004 0.004 0.003 0.003 0.003 0.003 0.005 0.006 0.010 0.012 0.016 S12 Deg 74.5 89.6 81.5 81.6 77.8 76.9 73.8 72.9 69.4 73.3 73.7 78.4 83.8 113.5 151.7 169.5 176.7 176.0 179.6 177.3 Mag 0.999 0.998 0.997 0.996 0.994 0.993 0.992 0.988 0.983 0.981 0.979 0.974 0.973 0.970 0.969 0.968 0.966 0.967 0.966 0.968 S22 Deg –1.3 –2.8 –4.2 –5.6 –7.0 –8.3 –10.1 –11.0 –12.4 –13.6 –14.8 –16.2 –17.2 –18.5 –19.6 –20.7 –22.0 –22.9 –24.2 –25.3 • FET2 (VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 82 kΩ, Zo = 50 Ω) Freq (MHz) 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 S11 Mag 0.986 0.983 0.980 0.972 0.964 0.952 0.938 0.924 0.906 0.888 0.869 0.844 0.822 0.797 0.770 0.745 0.720 0.693 0.670 0.647 Deg –4.8 –10.1 –14.9 –20.0 –25.2 –30.4 –35.9 –41.6 –47.4 –53.7 –60.0 –66.6 –73.6 –80.6 –88.1 –95.9 –103.8 –112.2 –120.7 –130.1 Mag 2.96 2.96 2.96 2.95 2.96 2.96 2.96 2.95 2.95 2.93 2.92 2.90 2.88 2.85 2.80 2.76 2.71 2.65 2.58 2.51 S21 Deg 175.0 169.9 165.0 159.9 154.7 149.6 143.9 139.0 133.8 128.2 122.9 117.3 111.6 106.1 100.5 94.7 89.2 83.6 78.0 72.8 Mag 0.001 0.002 0.003 0.004 0.004 0.004 0.005 0.005 0.005 0.004 0.004 0.003 0.003 0.003 0.003 0.004 0.007 0.010 0.012 0.015 S12 Deg 109.6 93.5 77.5 73.2 72.4 69.1 70.2 67.3 66.2 64.6 65.8 71.3 79.4 109.7 139.9 159.6 166.6 166.5 168.6 165.0 Mag 0.999 0.997 0.997 0.994 0.993 0.991 0.990 0.986 0.981 0.980 0.976 0.972 0.971 0.968 0.966 0.965 0.963 0.964 0.963 0.965 S22 Deg –1.8 –4.0 –5.9 –8.0 –9.9 –11.9 –14.2 –15.7 –17.7 –19.5 –21.4 –23.3 –25.0 –26.9 –28.6 –30.3 –32.2 –33.7 –35.6 –37.3 Rev.1.00 Aug 07, 2006 page 12 of 13 TBB1017 Package Dimensions Package Name CMPAK-6 JEITA Package Code SC-88 RENESAS Code PTSP0006JA-A Previous Code CMPAK-6 / CMPAK-6V MASS[Typ.] 0.006g D e A Q c E HE LP L A xM A SA b L1 A3 e Reference Symbol Dimension in Millimeters A2 A yS b b1 c c1 A1 S e1 l1 b2 A-A Section Pattern of terminal position areas A A1 A2 A3 b b1 c c1 D E e HE L L1 LP x y b2 e1 l1 Q Min 0.8 0 0.8 0.15 0.1 1.8 1.15 2.0 0.3 0.1 0.2 Nom 0.9 0.25 0.22 0.2 0.13 0.11 2.0 1.25 0.65 2.1 Max 1.1 0.1 1.0 0.3 0.15 2.2 1.35 2.2 0.7 0.5 0.6 0.05 0.05 0.35 0.9 1.5 0.25 Ordering Information Part Name TBB1017SMTL-E Quantity 3000 pcs Shipping Container φ178 mm reel, 8 mm emboss taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.1.00 Aug 07, 2006 page 13 of 13 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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