TSE2002B3CNCG8

IDT Confidential ® Temperature Sensor with Integrated EEPROM for Memory Modules Advance Information* Features • • • • The TSE2002B3C digital temperature sensor with accuracy up to ±0.5°C was designed to target applications demanding highest level of temperature readout. The device also contains 256 Byte EEPROM for storage of vendor information and system configuration such as SPD for DIMM modules. The sensor and the EEPROM are fully compliant with JEDEC JC42.4 Component Specification. The digital temperature sensor comes with several user-programmable registers to provide maximum flexibility for temperature-sensing applications. The registers allow specifying critical, upper, and lower temperature limits as well as hysteresis settings. Both the limits and hysteresis values are used for communicating temperature events from the chip to the system. This communication is done using Event pin, which has an open-drain configuration. The user has the option of setting the Event pin polarity as either an active-low or active-high comparator output for thermostat operation, or as a temperature event interrupt output for microprocessor-based systems. - Meets strict SMBus spec of 25ms (min), 35ms (max) • • • • • • • • • • • • • • • • Memory Module DRAMs SMBus Chipset MCH Memory Bus Permanent and Reversible Software Write Protect Software Write Protection for the lower 128 bytes Byte and page write (up to 16 bytes) Self-time Write cycle Automatic address incrementing Organized as 1 block of 256 bytes (256x8) Typical Applications (for memory throttling) EVENT# Temperature Converted to Digital Data Sampling Rate of 100ms (max) Selectable 0, 1.5°C, 3°C, 6°C Hysteresis Programmable Resolution from 0.0625°C to 0.5°C Accuracy: – ±0.5°C/±1°C (typ./max.) from -20°C to +125°C Serial EEPROM Features Memory Module Temp Sensor Application CPU Timeout supported for Temp Sensor and EEPROM Timeout supported in all Modes – Active mode for Temp sensor and EEPROM – EEPROM in standby or Temp sensor in shutdown – EEPROM in standby and Temp sensor in shutdown Schmitt trigger and noise filtering on bus inputs 2-wire Serial Interface: 10-400 kHz I2C™ /SMBus™ Available Packages: DFN-8, TDFN-8 Temperature Sensor Features The sensor uses an industry standard 2-wire, I2C/SMBus serial interface, and allows up to eight devices to be controlled on the bus. The 2Kbit (256 Bytes) serial EEPROM memory in the part is organized as a single block. Half the bytes in memory locations 00h to 7Fh can be permanently locked with user defined or vendor defined information. The protected data could also contain system information such as access speed, size, and organization. The 128 bytes in addresses from 80h to FFh can be used for general purpose data storage. These addresses are not write-protected. Temperature Sensor + 256 Byte Serial EEPROM 256 Byte Serial EEPROM for SPD Single Supply: 3V to 3.6V Accurate timeout support Advance Information Description TSE2002B3C Data Sheet • • • • • Temperature sensor and EEPROM DIMM Modules (DDR2, DDR3) Servers, Laptops, Ultra-portables, PCs, etc. High end audio / video equipment Industrial temperature monitors Hard Disk Drives and Other PC Peripherals DRAMs IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 30 © 2010 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice May 12, 2010 DSC 7210/17 IDT Confidential Block Diagram: Temperature Sensor with EEPROM VDD Temperature Registers TUPPER TLOWER TChipset CRIT Resolution Temperature Sensor Up to 0.5°C accuracy Capability and ID Registers Configuration Registers Advance Information Temperature Range Accuracy MCH Event Feature Resolution Support Manufacturer ID Device ID ADC Resolution Hysteresis Event Status Event Polarity Event Mode Critical Event Only Clear Event Alarm Window Lock Shutdown Output Control Control Logic EVENT SCL SDA A0 A1 SMBus / I2C Interface A2 2Kb EEPROM with Write Protect GND 2 of 30 May 12, 2010 IDT Confidential Maximum Ratings Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings Symbol Parameter Min. Max. Units -65 150 °C TSTG Storage Temperature VIO Input or output range, SA0 -0.50 10 V Input or output range, other pins -0.50 4.3 V Supply Voltage -0.5 4.3 V VDDSPD This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. DC Characteristics Operating Conditions Symbol Parameter VDDSPD TA Min. Max. Units Supply Voltage 3.0 3.6 V Ambient operating temperature -20 125 °C 3 of 30 May 12, 2010 Advance Information DC and AC Parameters IDT Confidential AC Measurement Conditions Symbol CL Parameter Min. Load capacitance Max. Units 100 Input rise and fall times pF 50 ns Input levels 0.2*VDDSPD to 0.8*VDDSPD V Input and output timing reference levels 0.3*VDDSPD to 0.7*VDDSPD V Input Parameters for the TSE2002B3C Symbol Parameter1,2 Test Condition Min. Max. Units CIN Input capacitance (SDA) 8 pF CIN Input rise and fall times 6 ns ZEIL Ei (SA0,SA1,SA2) input impedance VIN< 0.3* VDDSPD 30 kΩ ZEIH Ei (SA0,SA1,SA2) input impedance VIN> 0.7* VDDSPD 800 kΩ tSP Pulse width ignored (input filter on SCL and SDA) Single glitch, f < 100 KHz 100 Single glitch, f> 100 KHz 50 ns 1.TA=25°C, f=400 kHz 2.Verified by design and characterization not necessarily tested on all devices 4 of 30 May 12, 2010 Advance Information AC Measurement I/O Waveform IDT Confidential Parameter Symbol Conditions Min. Max. Units Input Leakage Current (SCL, SDA) ILI VIN = VSSSPD or VDDSPD ±5 μA Output Leakage Current ILO VOUT = VSSSPD or VDDSPD, SDA in Hi-Z ±5 μA Supply Current, temp sensor converting, EEPROM write IDD VDDSPD = 3.3 V, fC = 100 kHz (rise/fall time < 30 ns) 2 mA Supply Current, temp sensor shut down, EEPROM write IDD1 VDDSPD = 3.3 V, fC = 100 kHz (rise/fall time < 30 ns) 1.5 mA Supply Current, temp sensor shut down, EEPROM read IDD2 VDDSPD = 3.3 V, fC = 100 kHz (rise/fall time < 30 ns) 0.5 mA Supply Current, temp sensor converting, EEPROM standby IDD3 VDDSPD = 3.3 V, fC = 100 kHz (rise/fall time < 30 ns) 0.5 mA Standby Supply Current IDD4 VIN = VSSSPD or VDDSPD, VDDSPD = 3.6 V 100 μA Input Low Voltage (SCL, SDA) VIL -0.5 0.3*VDDSPD V Input High Voltage (SCL, SDA) VIH 0.7* VDDSPD VDDSPD +1 V SA0 High Voltage VHV VHV - VDDSPD > 4.8 V 7 10 V Output Low Voltage VOL IOL = 2.1 mA, 3 V =< VDDSPD =< 3.6 V 0.4 V IOL = 0.7 mA, VDDSPD = 1.7 - 3.6 V 0.2 V __ V Input hysteresis VHYST VDDSPD> 2.2V 5 of 30 0.05*VDDSPD May 12, 2010 Advance Information DC Characteristics IDT Confidential AC Characteristics VDDSPD > 2.2 V Symbol Min. Max. Units Clock Frequency fSCL 10 400 kHz Clock Pulse Width High Time tHIGH 600 ns Clock Pulse Width Low Time 5 1300 ns Detect clock low timeout, Capabilities Register bit 6 =1 tLOW tTIMEOUT SDA Rise Time tR2 SDA Fall Time 2 tF 6 25 20 35 ms 300 ns 300 ns Data In Setup Time tSU:DAT 100 ns Data In Hold Time tHD:DI 0 ns Data Out Hold Time tHD:DAT 200 Start Condition Setup Time tSU:STA 1 600 ns Start Condition Hold Time tHD:STA 600 ns Stop Condition Setup Time tSU:STO 600 ns tBUF 1300 ns Time Between Stop Condition and Next Start Condition Write Time tW 900 10 ns ms 1. For a RESTART condition, or following a write cycle. 2. Guaranteed by design and characterization, not necessarily tested. 3. To avoid spurious START and STOP conditions, a minimum delay is placed between falling edge of SCL and the falling or rising edge of SDA. 4. The TSE2002B3C does not initiate clock stretching which is an optional I2C bus feature 5. Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds the value of tTIMEOUT,MIN. After the master in a transaction detects this condition, it must generate a stop condition within or after the current data byte in the transfer process. Devices that have detected this condition must reset their communication and be able to receive a new START condition no later than tTIMEOUT,MAX. Typical device examples include the host controller and embedded controller and most devices that can master the SMBus. Some devices do not contain a clock low drive circuit; this simple kind of device typically may reset its communications port after a start or stop condition. A timeout condition can only be ensured if the device that is forcing the timeout holds SCL low for tTIMEOUT,MAX or longer. 6. The temperature sensor family of devices are not required to support the SMBus ALERT function. 6 of 30 May 12, 2010 Advance Information Parameter IDT Confidential Temperature-to-Digital Conversion Performance Parameter Min Temperature Sensor Accuracy (exceeds JEDEC B-grade) Typ Max Unit ±0.5 ±1.0 °C Test Conditions1 -20°C < TA < 125°C 1. VDDSPDMIN < VDDSPD < VDDSPDMAX Temperature Conversion Time Resolution ADC Setting tCONV (typ) tCONV (Max) Unit 9 bit 100 ms 0.25°C (POR default) 10 bit 100 ms 0.125°C 11 bit 100 ms 0.0625°C 12 bit 100 ms Advance Information 0.5°C AC Waveforms 7 of 30 May 12, 2010 IDT Confidential Pin Assignment SA0 1 8 VDDSPD STBY SA1 2 7 EVENT SA2 3 6 SCL VSSSPD 4 5 SDA Pin Description Pin Name Definition 1 SA0 Select Address 0 2 SA1 Select Address 1 3 SA2 Select Address 2 4 VSSSPD 5 SDA Serial Data In 6 SCL Serial Clock In 7 EVENT Temperature Event Out 8 VDDSPD Supply Voltage Ground Pin Functional Descriptions Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to VDDSPD. (refer to the Maximum RL Value vs. Bus Capacitance figure on how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-ORed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to the most positive VDDSPD in the I2C chain. (refer to the Maximum RL Value vs. Bus Capacitance figure on how the value of the pull-up resistor can be calculated). 8 of 30 May 12, 2010 Advance Information Pin # IDT Confidential Select Address (SA0, SA1, SA2) These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Slave Address. In the end application, SA0, SA1 and SA2 must be directly (not through a pull-up or pull-down resistor) connected to VDDSPD or VSSSPD to establish the Slave Address. When these inputs are not connected, an internal pull-down circuitry makes (SA0, SA1, SA2) = (0, 0, 0). The SA0 input is used to detect the VHV voltage, when decoding an SWP or CWP instruction. Refer to the I2C Operating Modes table for decoding details. EVENT The TSE2002B3C EVENT pin is an open drain output that requires a pull-up to VDDSPD on the system motherboard or integrated into the master controller. The TSE2002B3C EVENT pin has three operating modes, depending on configuration settings and any current out-of-limit conditions. These modes are Interrupt, Comparator, or TCRIT Only. In Interrupt Mode the EVENT pin will remain asserted until it is released by writing a '1' to the “Clear Event” bit in the Status Register. The value to write is independent of the EVENT polarity bit. In Comparator Mode the EVENT pin will clear itself when the error condition that caused the pin to be asserted is removed. When the temperature is compared against the TCRIT limit, then this mode is always used. Finally, in the TCRIT Only Mode the EVENT pin will only be asserted if the measured temperature exceeds the TCRIT Limit. Once the pin has been asserted, it will remain asserted until the temperature drops below the TCRIT Limit minus the TCRIT hysteresis. The next figure illustrates the operation of the different modes over time and temperature. Systems that use the active high mode for EVENT must be wired point to point between the TSE2002B3C and the sensing controller. Wire-OR configurations should not be used with active high EVENT since any device pulling the EVENT signal low will mask the other devices on the bus. Also note that the normal state of EVENT in active high mode is a 0 which will continually draw power through the pull-up resistor. 9 of 30 May 12, 2010 Advance Information Maximum RL Value vs. Bus Capacitance (CBUS) for an I2C Bus IDT Confidential Advance Information EVENT Pin Mode Functionality Serial Communications The SPD section of the TSE2002B3C is a 2 Kbit serial EEPROM organized as a 256 byte memory. The device is able to lock permanently the data in the lower sector (from location 0x00 to 0x7F), designed specifically for use in DRAM DIMMs (Dual Inline Memory Modules) with Serial Presence Detect. All the information concerning the DRAM module configuration (such as its access speed, its size, its organization) can be kept write protected in the first half of the memory. Locking the lower sector of the SPD may be accomplished using one of two software write protection mechanisms. By sending the device a specific I2C sequence, the first 128 bytes of the memory become write protected, either permanently or resetable. The TSE2002B3C temperature sensor circuitry continuously monitors the temperature and updates the temperature data minimum of eight times per second. Temperature data is latched internally by the device and may be read by software from the bus host at any time. Internal registers are used to configure both the TS performance and response to over-temperature conditions. The device contains programmable high, low, and critical temperature limits. Finally, the device EVENT pin can be configured as active high or active low and can be configured to operate as an interrupt or as a comparator output. 10 of 30 May 12, 2010 IDT Confidential Device Diagram The TSE2002B3C behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and R/W# bit (as described in the I2C Operating Mode table), terminated by an acknowledge bit. The TSE2002B3C does not initiate clock stretching which is an optional I2C bus feature. In accordance with the I2C bus definition, the device uses three (3) built-in, 4-bit Device Type Identifier Codes (DTIC) and the state of SA0, SA1, and SA2 to generate an I2C Slave Address. The SPD memory may be accessed using a DTIC of (1010), and to perform the PSWP,CSWP, or PSWP operations a DTIC of (0110) is required. The TS registers are accessed using a DTIC of (0011). When writing data to the memory, the SPD inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Bus Master generated STOP condition after an Ack for WRITE, and after a NoAck for READ. The TS section of the device uses a pointer register to access all registers in the device. Additionally, all data transfers to and from this section of the device are performed as block read/ write operations. The data is transmitted/received as 2 bytes, Most Significant Byte (MSB) first, and terminated with a NoAck and STOP after the Least Significant byte (LSB). Data and address information is transmitted and received starting with the Most Significant Bit.first 11 of 30 May 12, 2010 Advance Information Device Interface IDT Confidential Advance Information I2C Bus Protocol Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Stop Condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the SPD into Standby mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle for the SPD. Neither of these conditions changes the operation of the TS section. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. 12 of 30 May 12, 2010 IDT Confidential No Acknowledge Bit (NACK) The no-acknowledge bit is used to indicate the completion of a block read operation, or an attempt to modify a write-protected register. The bus master releases Serial Data (SDA) after sending eight bits of data, and during the 9th clock pulse period, and does not pull Serial Data (SDA) Low. Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low. Memory Addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in the next table (on Serial Data (SDA), most significant bit first). Device Select Code Read/Write SPD Memory Device Type Identifier Select Address Signals b71 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 SA2 SA1 SA0 R/W# VSSSPD VSSSPD VHV 0 VSSSPD VDDSPD VHV 0 SA2 SA1 SA0 0 VSSSPD VSSSPD VHV 1 SA2 SA1 SA0 1 SA2 SA1 SA0 R/W# Set Write Protection (SWP) Clear Write Protection (CWP) Permanently Set Write Protection (PSWP)2 0 1 1 0 Read SWP Read PSWP 2 Read/Write Temperature Registers 0 0 1 1 R/W# Notes: 1. The most significant bit, b7, is sent first. 2. SA0, SA1, and SA2 are compared against the respective external pins on the TSE2002B3C. The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Select Address (SA2, SA1, SA0). To address the memory array, the 4-bit Device Type Identifier is 1010b; to access the write-protection settings, it is 0110b; and to access the Temperature Sensor settings is 0011b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (SA0, SA1, SA2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (SA0, SA1, SA2) inputs. The 8th bit is the Read/Write bit (R/W#). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the SPD Device Select code, the SPD section deselects itself from the bus, and goes into Standby mode. The I2C operating modes are shown in the following table. 13 of 30 May 12, 2010 Advance Information Memory Area Function IDT Confidential I2C Operating Modes Mode SPD Current Address Read SPD Random Address Read R/W# Bit Bytes 1 1 0 1 1 Initial Sequence START, Device Select, R/W# = 1 START, Device Select, R/W# = 0, Address reSTART, Device Select, R/W# = 1 SPD Sequential Read 1 >1 SPD Byte Write 0 1 START, Device Select, R/W# = 0, data, STOP SPD Page Write 0 < 16 START, Device Select, R/W# = 0, data, STOP TS Write 0 2 START, Device Select, R/W#=0, pointer, data, STOP TS Read 1 2 START, Device Select, R/W#=1, pointer, data, STOP Similar to Current or Random Address Read Device Reset and Initialization At Power-up (phase during which VDDSPD is lower than VDDSPDmin but increases continuously), the device will not respond to any instruction until VDDSPD has reached the Power On Reset threshold voltage (this threshold is lower than the minimum VDDSPD operating voltage defined in the DC AND AC PARAMETERS tables). Once VDDSPD has passed the POR threshold, the device is reset. The actual POR threshold voltage will be implementation dependent and is not defined in this document. The device is delivered with all bits in the EEPROM memory array set to ' 1' (each byte contains 0xFF). Prior to selecting the memory and issuing instructions, a valid and stable VDDSPD voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and for a Write instruction, until the completion of the internal write cycle (tW). At Power-down (phase during which VDDSPD decreases continuously), as soon as VDDSPD drops below the minimum operating voltage, the device stops responding to commands, and remains in reset until the POR threshold voltage is reached. 14 of 30 May 12, 2010 Advance Information In order to prevent inadvertent Write operations during Power-up, a Power-On Reset (POR) circuit is included. IDT Confidential Software Write Protect The TSE2002B3C has three software write-protection features, allowing the bottom half of the memory area (addresses 0x00 to 0x7F) to be temporarily or permanently write protected. Software write-protection is handled by three instructions: SWP: Set Write Protection CWP: Clear Write Protection PSWP: Permanently Set Write Protection The level of write-protection (set or cleared) that has been defined using these instructions, remains defined even after a power cycle. SWP and CWP If the software write-protection has been set with the SWP instruction, it can be cleared again with a CWP instruction. The two instructions (SWP and CWP) have the same format as a Byte Write instruction, but with a different Device Type Identifier (refer to the I2C Operating Modes table). Like the Byte Write instruction, it is followed by an address byte and a data byte, but in this case the contents are all “Don't Care” (refer to the Setting the Write Protection figure). Another difference is that the voltage, VHV, must be applied on the SA0 pin, and specific logical levels must be applied on the other two (SA1 and SA2, as shown in the I2C Operating Mode table). PSWP If the software write-protection has been set with the PSWP instruction, the first 128 bytes of the memory are permanently write-protected. This write-protection cannot be cleared by any instruction, or by power-cycling the device. Also, once the PSWP instruction has been successfully executed, the TSE2002B3C no longer acknowledges any instruction (with a Device Type Identifier of 0110) to access the write-protection settings. 15 of 30 May 12, 2010 Advance Information Result of Setting the Write Protection IDT Confidential Setting the Write Protection The status of software write protection can be determined using these instructions: Read SWP: Read Write Protection Status Read PSWP: Read Permanently Set Write Protection Status • • Read SWP The controller issues a Read SWP command. If Software Write Protection has not been set, the device replies to the data byte with an Ack. If Software Write Protection has been set, the device replies to the data byte with a NoAck. Read PSWP The controller issues a Read PSWP command. If Permanent Software Write Protection has not been set, the device replies to the data byte with an Ack. If Permanent Software Write Protection has been set, the device replies to the data byte with a NoAck Write Operations Following a Start condition the bus master sends a Device Select Code with the R/W# bit reset to 0. The device acknowledges this, as shown in the Write Mode Sequence in a Non-Write Protected Area figure, and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and the device does not respond to any requests. 16 of 30 May 12, 2010 Advance Information Reading Write Protection Status IDT Confidential Byte Write After the Device Select Code and the address byte, the bus master sends one data byte. If the addressed location is write-protected, the device replies to the data byte with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in the Write Mode Sequence in a Non-Write Protected Area figure above. Page Write The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as “roll-over” occurs. This should be avoided, as data starts to be over-written in an implementation dependent fashion. The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device. If the addressed location is write-protected, the device replies to the data byte with NoAck, and the locations are not modified. After each byte is transferred, the internal byte address counter is incremented. The transfer is terminated by the bus master generating a Stop condition. Write Cycle Polling Using ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tW) is shown in the AC Characteristic for TSE2002B3C table, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The polling sequence is shown in the following figure: Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). • • • 17 of 30 May 12, 2010 Advance Information Write Mode Sequences in a Non-Write Protected Area IDT Confidential Advance Information Write Cycle Polling Flowchart Using ACK Read Operations Read operations are performed independent of the software protection state. The device has an internal address counter which is incremented each time a byte is read. 18 of 30 May 12, 2010 IDT Confidential Advance Information Read Mode Sequences Random Address Read A dummy Write is first performed to load the address into this address counter (refer to the Read Mode Sequence figure) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the R/W# bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the R/W# bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in the Read Mode Sequence figure, without acknowledging the byte. 19 of 30 May 12, 2010 IDT Confidential Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition (refer to the Read Mode Sequence figure). The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter 'rolls-over', and the device continues to output data from memory address 0x00. Acknowledge in Read Mode For all Read commands to the SPD, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and returns to an idle state to await the next valid START condition. This has no effect on the TS operational status. Status Permanently Protected Instruction ACK Address ACK Data Byte ACK Write Cycle (tW) PSWP, SWP, or CWP NoACK Not Significant NoACK Not Significant NoACK No Page or byte write in lower 128 bytes ACK Address ACK Data ACK or NoACK1 Yes SWP NoACK Not Significant NoACK Not Significant NoACK No CWP ACK Not Significant ACK Not Significant ACK Yes PSWP ACK Not Significant ACK Not Significant ACK Yes Page or byte write in lower 128 bytes ACK Address ACK Data ACK or NoACK1 Yes PSWP, SWP, or CWP ACK Not Significant ACK Not Significant ACK Yes Page or byte write ACK Address ACK Data ACK Yes Protected with SWP Not Protected Note 1: Software must accept either return code. Acknowledge When Reading the Write Protection (Instructions with R/W# Bit=1) PSWP Status SWP Status Instruction ACK Address ACK Data Byte ACK Set X Read PSWP NoACK Not Significant NoACK Not Significant NoACK Not Set X Read PSWP ACK Not Significant NoACK Not Significant NoACK Set X Read SWP NoACK Not Significant NoACK Not Significant NoACK X Set Read SWP NoACK Not Significant NoACK Not Significant NoACK Not Set Not Set Read SWP ACK Not Significant NoACK Not Significant NoACK Note: X = Set or Not Set. Temperature Sensor (TS) Device Operation The TSE2002B3C Temperature Register Set is accessed though the I2C address 0011_bbb_R/W#. The “bbb” denotes the current state of SA2, SA1, and SA0. In the event SA0 is in the high voltage state, the device interprets the voltage as a logic '1' at the pin. The Temperature Register Set stores the temperature data, limits, and configuration values. All registers in the address space from 0x00 through 0x08 are 16-bit registers accessed through block read and write commands as detailed in the TS Write Operation section. 20 of 30 May 12, 2010 Advance Information Acknowledge When Writing Data or Defining Write Protection (Instructions with R/W# Bit=0) IDT Confidential TS Write Operations Writing to the TSE2002B3C Temperature Register Set is accomplished through a modified block write operation for two (2) data bytes. To maintain I2C compatibility, the 16 bit register is accessed through a pointer register, requiring the write sequence to include an address pointer in addition to the Slave address. This indicates the storage location for the next two bytes received. The next figure shows an entire write transaction on the bus. TS Register Write Operation Reading data from the TS may be accomplished in one of two ways: 1. If the location latched in the Pointer Register is correct (for normal operation it is expected the same address will be read repeatedly for temperature), the read sequence may consist of a Slave Address from the bus master followed by two bytes of data from the device; or 2. The pointer register is loaded with the correct register address, and the data is read. The sequence to preset the pointer register is shown in the Write to Pointer Register figure, and the preset pointer read is shown in the I2C Preset Pointer Register Word Read figure. If it is desired to read random address each cycle, the complete Pointer Write, Word Read sequence is shown in the I2C Pointer Write Register Word Read figure. I2 C The data byte has the most significant bit first. At the end of a read, this device can accept either Acknowledge (Ack) or No Acknowledge (No Ack) from the Master (No Acknowledge is typically used as a signal for the slave that the Master has read its last byte). 21 of 30 May 12, 2010 Advance Information TS Read Operations IDT Confidential I2C Write to Pointer Register Advance Information I2C Preset Pointer Register Word Read I2C Pointer Write Register Word Read TS Register Set Definition The register set address are shown in the Acknowledge When Writing Data or Defining Write Protection table. These values are used in the I2C operations as the “REG_PTR” as shown in previous three figures. 22 of 30 May 12, 2010 IDT Confidential Temperature Register Addresses R/W Name N/A W Address Pointer 00 R Capabilities 01 R/W Configuration 02 R/W 03 Function Default Address storage for subsequent operations N/A Indicates the functions and capabilities of the temperature sensor 004F Controls the operation of the temperature monitor 0000 High Limit Temperature High Limit 0000 R/W Low Limit Temperature Low Limit 0000 04 R/W TCRIT Limit Critical Temperature 0000 05 R Ambient Temperature Current Ambient temperature N/A 06 R Manufacturer ID PCI-SIG manufacturer ID 00B3 07 R Device/Revision Device ID and Revision number 2903 08 R/W Resolution Register Allows changing temperature sensor resolution 000F Capabilities Register The Capabilities Register indicates the supported features of the temperature sensor. Capabilities Register ADDR R/W 00 R B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default RFU RFU RFU RFU RFU RFU RFU RFU 004F EVSD TMOUT X RANGE ACC EVENT TRES[1:0] Bits 15 - Bit 8 – RFU; Reserved for future use. These bits will always read '0' and writing to them will have no affect. Bit 7- EVSD-EVENT with Shutdown action. ‘0’ - (default) The EVENT output freezes in its current state when entering shutdown. Upon exiting shutdown, the EVENT output remains in the previous state until the next thermal sample is taken, or possibly sooner if EVENT is programmed for comparator mode. ‘1’ The EVENT output is deasserted (not driven) when entering shutdown and remains deasserted upon exit from shutdown until the next thermal sample is taken, or possibly sooner if EVENT is programmed for comparator mode. Bit 6 - TMOUT – Bus timeout period for thermal sensor access during normal operation. Note that the TSE2002B3C supports timeout in both active and shutdown mode for temperature sensor and SPD (EEPROM) portions of the device. ‘0’ - Parameter tTIMEOUT is supported within the range of 10 to 60 ms. ‘1’ - (default) Parameter tTIMEOUT is supported within the range of 25 to 35 ms (SMBus compatible). Bit 5 - X – May be 0 or 1; applications must accept either code. (Default =0) Bits 4 - 3 – TRES[1:0]; Indicates the resolution of the temperature monitor as shown in the TRES Bit Decode table. (Default =01) 23 of 30 May 12, 2010 Advance Information ADDR IDT Confidential TRES Bit Decode TRES[1:0] Temperature Resolution 1 0 0 0 0.5°C (9-bit) 0 1 0.25°C (10-bit) (default) 1 0 0.125°C (11-bit) 1 1 0.0625°C (12-bit) Note: Refer to section Resolution Register on page 28. Bit 2 - RANGE; Indicates the supported temperature range. '0' - The temperature monitor clamps values lower than 0 °C. '1' (default) - The temperature monitor can read temperatures below 0 °C and sets the sign bit appropriately. '0' - The temperature monitor has ±2 °C accuracy of the active range (75 °C to 95 °C) and 3 °C accuracy over the entire operating range. '1' (default) - Bgrade. The temperature monitor has ±1 °C accuracy over the active range (75 °C to 95 °C) and 2°C accuracy over the monitoring range (40 °C to 125 °C) Bit 0 - EVENT; Indicates whether the temperature monitor supports interrupt capabilities '0'.-The device does not support interrupt capabilities. '1' (default); The device supports interrupt capabilities. Configuration Register Configuration Register ADDR 01 R/W R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 RFU RFU RFU RFU RFU TCRIT_ LOCK EVENT_ LOCK CLEAR EVENT_ STS EVENT_ CTRL B10/B2 B9/B1 HYST[1:0] TCRIT_ ONLY EVENT_ POL B8/B0 Default SHDN EVENT_ MODE 0000 The Configuration Register holds the control and status bits of the EVENT pin as well as general hysteresis on all limits. Bits 15 - 11 – RFU; Reserved for future use. These bits will always read '0' and writing to them will have no affect. For future compatibility, all RFU bits must be programmed as '0'. Bits 10 - 9 – HYST[1:0]; Control the hysteresis that is applied to all limits as shown in the HYST Bit Decode table that follows. This hysteresis applies to all limits when the temperature is dropping below the threshold so that once the temperature is above a given threshold, it must drop below the threshold minus the hysteresis in order to be flagged as an interrupt event. Note that hysteresis is also applied to EVENT pin functionality. When either of the lock bits is set, these bits cannot be altered. 24 of 30 May 12, 2010 Advance Information Bit 1 - ACC; Indicates the supported temperature accuracy. IDT Confidential HYST Bit Decode HYST[1:0] Hysteresis 1 0 0 0 Disable hysteresis (default) 0 1 1.5°C 1 0 3°C 1 1 6°C Bit 8 – SHDN-Shutdown. The thermal sensing device and A/D converters are disabled to save power, no events will be generated. When either of the lock bits is set, this bit cannot be set until unlocked. However it can be cleared at any time. When in shutdown mode, the TSE2002B3C still responds to commands normally, however bus timeout may or may not be supported in this mode. '0' (default); The temperature monitor is active and converting '1'; The temperature monitor is disabled and will not generate interrupts or update the temperature data. '0' (default; The TCRIT Limit Register can be updated normally. '1'; The TCRIT Limit Register is locked and cannot be updated. Once this bit has been set, it cannot be cleared until an internal power on reset. Bit 6 – EVENT_LOCK; Locks the High and Low Limit Registers from being updated. '0' (default); The High and Low Limit Registers can be updated normally. '1'; The High and Low Limit Registers are locked and cannot be updated. Once this bit has been set, it cannot be cleared until an internal power on reset. Bit 5 – CLEAR; Clears the EVENT pin when it has been asserted. This bit is write only and will always read '0'. '0'; does nothing '1'; The EVENT pin is released and will not be asserted until a new interrupt condition occurs. This bit is ignored if the device is operating in Comparator Mode. This bit is self clearing. Bit 4 – EVENT_STS; Indicates if the EVENT pin is asserted. This bit is read only. ‘0' (default); The EVENT pin is not asserted. '1'; The EVENT pin is being asserted by the device. Bit 3 – EVENT_CTRL; Masks the EVENT pin from generating an interrupt. If either of the lock bits are set (bit 7 and bit 6), then this bit cannot be altered. '0' (default); The EVENT pin is disabled and will not generate interrupts. '1'; The EVENT pin is enabled. Bit 2 – TCRIT_ONLY; Controls whether the EVENT pin will be asserted from a high / low out-of-limit condition. When the EVENT_LOCK bit is set, this bit cannot be altered. '0' (default); The EVENT pin will be asserted if the measured temperature is above the High Limit or below the Low Limit in addition to if the temperature is above the TCRIT Limit. '1'; The EVENT pin will only be asserted if the measured temperature is above the TCRIT Limit. Bit 1 – EVENT_POL; Controls the “active” state of the EVENT pin. The EVENT pin is driven to this state when it is asserted. 25 of 30 May 12, 2010 Advance Information Bit 7 – TCRIT_LOCK; Locks the TCRIT Limit Register from being updated. IDT Confidential '0' (default); The EVENT pin is active low. The “active” state of the pin will be logical '0'. '1'; The EVENT pin is active high. The “active” state of the pin will be logical '1'. Bit 0 – EVENT_MODE; Controls the behavior of the EVENT pin. The EVENT pin may function in either comparator or interrupt mode. '0'; The EVENT pin will function in comparator mode. '1'; The EVENT pin will function in interrupt mode. Temperature Register Value Definitions Temperatures in the High Limit Register, Low Limit Register, TCRIT Register, and Temperature Data Register are expressed in two's complement format. Bits B 12 through B2 for each of these registers are defined for all device resolutions as defined in the TRES field of the Capabilities Register, hence a 0.25°C minimum granularity is supported in all registers. Examples of valid settings and interpretation of temperature register bits: B15~B0 (binary) Value Units xxx0 0000 0010 11xx +2.75 °C xxx0 0000 0001 00xx +1.00 °C xxx0 0000 0000 01xx +0.25 °C xxx0 0000 0000 00xx 0 °C xxx1 1111 1111 11xx -0.25 °C xxx1 1111 1111 00xx -1.00 °C xxx1 1111 1101 01xx -2.75 °C The TRES field of the Capabilities Register optionally defines higher resolution devices. For compatibility and simplicity, this additional resolution affects only the Temperature Data Register but none of the Limit Registers. When higher resolution devices generate status or EVENT changes, only bits B12 through B2 are used in the comparison; however, all 11 bits (TRES[1-0] = 10) or all 12 bits (TRES[1-0] = 11) are visible in reads from the Temperature Data Register. When a lower resolution device is indicated in the Capabilities Register (TRES[1-0] = 00), the finest resolution supported is 0.5°C. When this is detected, bit 2 of all Limit Registers should be programmed to 0 to assure correct operation of the temperature comparators. High Limit Register The temperature limit registers (High, Low, and TCRIT) define the temperatures to be used by various on-chip comparators to determine device temperature status and thermal EVENTs. For future compatibility, unused bits “-” must be programmed as 0. High Limit Register ADDR R/W 02 R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 – – – Sign 128 64 32 16 8 4 2 1 0.5 0.25 – – Default 0000 The High Limit Register holds the High Limit for the nominal operating window. When the temperature rises above the High Limit, or drops below or equal to the High Limit, then the EVENT pin is asserted (if enabled). If the EVENT_LOCK bit is set as shown in the Configuration Register table), then this register becomes read-only. 26 of 30 May 12, 2010 Advance Information Temperature Register Coding Examples IDT Confidential Low Limit Register Low Limit Register ADDR R/W 03 R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 – – – Sign 128 64 32 16 8 4 2 1 0.5 0.25 – – Default 0000 The Low Limit Register holds the lower limit for the nominal operating window. When the temperature drops below the Low Limit or rises up to meet or exceed the Low Limit, then the EVENT pin is asserted (if enabled). If the EVENT_LOCK bit is set as shown in the Configuration Register, then this register becomes read-only. TCRIT Limit Register TCRIT Limit Register R/W 04 R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 – – – Sign 128 64 32 16 8 4 2 1 0.5 0.25 – – Default 0000 The TCRIT Limit Register holds the TCRIT Limit. If the temperature exceeds the limit, the EVENT pin will be asserted. It will remain asserted until the temperature drops below or equal to the limit minus hysteresis. If the TCRIT_LOCK bit is set as shown in the Configuration Register table, then this register becomes read-only. Temperature Data Register Temperature Data Register ADDR R/W 05 R B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 TCRIT HIGH LOW Sign 128 64 32 16 8 4 2 1 0.5 0.25* 0.125* 0.0625* Default N/A (0000) * Resolution defined based on value of TRES field of the Capabilities Register. Unused/unsupported bits will read as 0. The Temperature Data Register holds the 10-bit + sign data for the internal temperature measurement as well as the status bits indicating which error conditions, if any, are active. The encoding of bits B 12 through B0 is the same as for the temperature limit registers. Bit 15 – TCRIT; When set, the temperature is above the TCRIT Limit. This bit will remain set so long as the temperature is above TCRIT and will automatically clear once the temperature has dropped below the limit minus the hysteresis. Bit 14 – HIGH; When set, the temperature is above the High Limit. This bit will remain set so long as the temperature is above the HIGH limit. Once set, it will only be cleared when the temperature drops below or equal to the HIGH Limit minus the hysteresis. Bit 13 – LOW; When set, the temperature is below the Low Limit. This bit will remain set so long as the temperature is below the Low Limit minus the hysteresis. Once set, it will only be cleared when the temperature meets or exceeds the Low Limit. 27 of 30 May 12, 2010 Advance Information ADDR IDT Confidential Manufacturer ID Register Manufacturer ID Register ADDR R/W 06 R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 Default 00B3 The Manufacturer ID Register holds the PCI SIG number assigned to the specific manufacturer. Device ID/Revision Register Device ID/Revision Register R/W 07 R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 1 Default 2903 The upper byte of the Device ID / Revision Register stores a unique number indicating the TSE2002B3C from other devices. The lower byte holds the revision value. Resolution Register This register allows the user to change the resolution of the temperature sensor. The POR default resolution is 0.25°C. The resolution implemented via this register is also reflected in the capability register. Resolution Register ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default Value 08h R/W 0 0 0 0 0 0 0 0 000F 0 0 0 TRES[1] TRES[0] 1 1 1 Legend: Resolution bits 4-3 TRES[4:3] 00 = LSB = 0.5°C (register value = 0007) 01 = LSB = 0.25°C (register value = 000F) 10 = LSB = 0.125°C (register value = 0017) 11 = LSB = 0.0625°C (register value = 001F) Conversion times for each resolution are less than 100ms (worst case). Bits 0, 1, and 2 are used for test purposes and should only be set to ‘1’. Functions of bits [0:2] Bit 0 – gets mapped into bit 0 of capabilities register. Bit 1 – gets mapped into bit 1 of capabilities register. Bit 2 – gets mapped into bit 2 of capabilities register. 28 of 30 May 12, 2010 Advance Information ADDR IDT Confidential Use in a Memory Module In the Dual Inline Memory Module (DIMM) application, the TSE2002B3C is soldered directly onto the printed circuit module. The three Select Address inputs (SA0, SA1, SA2) must be connected to VSSSPD or VDDSPD directly (that is without using a pull-up or pull-down resistor) through the DIMM socket (as shown in the Unique Addressing table). The pull-up resistors needed for normal behavior of the I2C bus are connected on the I2C bus of the mother-board DIMM Position SA2 SA1 SA0 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 Note: 0 = VSSSPD, 1 = VDDSPD. The Event pin is expected to be used in a wire-OR configuration with a pull-up resistor to VDDSPD on the motherboard. In this configuration, EVENT should be programmed for the active low mode. Also note that comparator mode or TCRIT-only mode for EVENT on a wire-OR bus will show the combined results of all devices wired to the EVENT signal. Programming the TSE2002B3C The situations in which the TSE2002B3C is programmed can be considered under two headings: When the DIMM is isolated (not inserted on the PCB motherboard) When the DIMM is inserted on the PCB motherboard • • DIMM Isolated With specific programming equipment, it is possible to define the TSE2002B3C content, using Byte and Page Write instructions, and its write-protection using the SWP and CWP instructions. To issue the SWP and CWP instructions, the DIMM must be inserted in the application-specific slot where the SA0 signal can be driven to VHV during the whole instruction. This programming step is mainly intended for use by DIMM makers, whose end application manufacturers will want to clear this write-protection with the CWP on their own specific programming equipment, to modify the lower 128 Bytes, and finally to set permanently the write-protection with the PSWP instruction. DIMM Inserted in the Application Mother Board As the final application cannot drive the SA0 pin to VHV, the only possible action is to freeze the write-protection with the PSWP instruction. Refer to the Acknowledge When Writing Data or Defining Write Protection table on how the Ack bits can be used to identify the write-protection status. 29 of 30 May 12, 2010 Advance Information Unique Addressing of SPDs in DIMM Applications IDT Confidential Ordering Information TSE X X X XXX X Temp Voltage Range Rev. Package Shipping Carrier XXXX Device Type 8 Tape and Reel NCG - Green TDFN (2.0 x 3.0mm body, 0.75mm thick) NRG - Green DFN (2.0 x 3.0mm body, 0.90mm thick) 3 = (3 to 3.6V) B Temperature Accuracy Grade (±1.0°C Max) 2002 Temperature Sensor with EEPROM Example: TSE2002B3C NRG8 ® CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 30 of 30 for Tech Support: email: memorymodule-help@idt.com phone: 408-284-8208 May 12, 2010 Advance Information C