Datasheet
μPD44324185B
μPD44324365B
36M-BIT DDR II SRAM SEPARATE I/O
2-WORD BURST OPERATION
R10DS0037EJ0200
Rev.2.00
September 12, 2011
Description
The μPD44324185B is a 2,097,152-word by 18-bit and the μPD44324365B is a 1,048,576-word by 36-bit
synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS sixtransistor memory cell.
The μPD44324185B and μPD44324365B integrate unique synchronous peripheral circuitry and a burst
counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K
and K#. These products are suitable for application which require synchronous operation, high speed, low
voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply
• 165-pin PLASTIC BGA (15 x 17)
• HSTL interface
• PLL circuitry for wide output data valid window and future frequency scaling
• Separate independent read and write data ports
• DDR read or write operation initiated each cycle
• Pipelined double data rate operation
• Separate data input/output bus
• Two-tick burst for low DDR transaction size
• Two input clocks (K and K#) for precise DDR timing at clock rising edges only
• Two output clocks (C and C#) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
• User programmable impedance output (35 to 70 Ω)
• Fast clock cycle time : 3.3 ns (300 MHz), 3.5 ns (287 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 1 of 34
μPD44324185B, μPD44324365B
Ordering Information
Part No.
μPD44324185BF5-E33-FQ1-A
μPD44324185BF5-E35-FQ1-A
μPD44324185BF5-E40-FQ1-A
μPD44324185BF5-E50-FQ1-A
μPD44324365BF5-E33-FQ1-A
μPD44324365BF5-E35-FQ1-A
μPD44324365BF5-E40-FQ1-A
μPD44324365BF5-E50-FQ1-A
μPD44324185BF5-E33-FQ1
μPD44324185BF5-E35-FQ1
μPD44324185BF5-E40-FQ1
μPD44324185BF5-E50-FQ1
μPD44324365BF5-E33-FQ1
μPD44324365BF5-E35-FQ1
μPD44324365BF5-E40-FQ1
μPD44324365BF5-E50-FQ1
μPD44324185BF5-E33Y-FQ1-A
μPD44324185BF5-E35Y-FQ1-A
μPD44324185BF5-E40Y-FQ1-A
μPD44324185BF5-E50Y-FQ1-A
μPD44324365BF5-E33Y-FQ1-A
μPD44324365BF5-E35Y-FQ1-A
μPD44324365BF5-E40Y-FQ1-A
μPD44324365BF5-E50Y-FQ1-A
μPD44324185BF5-E33Y-FQ1
μPD44324185BF5-E35Y-FQ1
μPD44324185BF5-E40Y-FQ1
μPD44324185BF5-E50Y-FQ1
μPD44324365BF5-E33Y-FQ1
μPD44324365BF5-E35Y-FQ1
μPD44324365BF5-E40Y-FQ1
μPD44324365BF5-E50Y-FQ1
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Organization
(word x bit)
Cycle
time
Clock
frequency
Operating Ambient
Temperature
2M x 18
3.3ns
300MHz
Ta = 0 to 70°C
3.5ns
287MHz
4.0ns
250MHz
(15 x 17)
5.0ns
200MHz
Lead-free
1M x 36
2M x 18
1M x 36
2M x 18
1M x 36
2M x 18
1M x 36
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
5.0ns
200MHz
3.3ns
300MHz
Package
165-pin
PLASTIC BGA
Ta = 0 to 70°C
165-pin
3.5ns
287MHz
PLASTIC BGA
4.0ns
250MHz
(15 x 17)
5.0ns
200MHz
Lead
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
5.0ns
200MHz
Ta = −40 to 85°C
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
(15 x 17)
5.0ns
200MHz
Lead-free
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
5.0ns
200MHz
3.3ns
300MHz
165-pin
PLASTIC BGA
Ta = −40 to 85°C
165-pin
3.5ns
287MHz
PLASTIC BGA
4.0ns
250MHz
(15 x 17)
5.0ns
200MHz
Lead
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
5.0ns
200MHz
Page 2 of 34
μPD44324185B, μPD44324365B
Pin Arrangement
165-pin PLASTIC BGA (15 x 17)
(Top View)
[μPD44324185B]
2M x 18
1
2
3
4
5
6
7
8
9
10
11
A
CQ#
VSS/144M
A
R, W#
BW1#
K#
NC/288M
LD#
A
VSS/72M
CQ
B
NC
Q9
D9
A
NC
K
BW0#
A
NC
NC
Q8
C
NC
NC
D10
VSS
A
A
A
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
DLL#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
A
A
A
VSS
NC
NC
D1
P
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C#
A
A
A
TMS
TDI
A
D0 to D17
Q0 to Q17
LD#
R, W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
Remarks 1.
: Address inputs
: Data inputs
: Data outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
×××# indicates active LOW.
2.
Refer to Package Dimensions for the index mark.
3.
2A, 7A and 10A are expansion addresses : 10A for 72Mb
: 10A and 2A for 144Mb
: 10A, 2A and 7A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 3 of 34
μPD44324185B, μPD44324365B
Pin Arrangement
165-pin PLASTIC BGA (15 x 17)
(Top View)
[μPD44324365B]
1M x 36
1
2
3
4
5
6
7
8
9
10
11
R, W#
BW2#
K#
BW1#
LD#
A
VSS/144M
CQ
A
CQ#
B
Q27
Q18
D18
A
BW3#
K
BW0#
A
D17
Q17
Q8
C
D27
Q28
D19
VSS
A
A
A
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
DLL#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
A
A
A
VSS
Q10
D9
D1
P
Q35
D35
Q26
A
A
C
A
A
Q9
D0
Q0
R
TDO
TCK
A
A
A
C#
A
A
A
TMS
TDI
VSS/288M NC/72M
A
D0 to D35
Q0 to Q35
LD#
R, W#
BW0# to BW3#
K, K#
C, C#
CQ, CQ#
ZQ
Remarks 1.
: Address inputs
: Data inputs
: Data outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
DLL#
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
: PLL disable
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
×××# indicates active LOW.
2.
Refer to Package Dimensions for the index mark.
3.
2A, 3A and 10A are expansion addresses: 3A for 72Mb
: 3A and 10A for 144Mb
: 3A, 10A and 2A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 4 of 34
μPD44324185B, μPD44324365B
Pin Description
(1/2)
Symbol
Type
A
Input
D0 to Dxx
Input
Q0 to Qxx
Output
LD#
Input
R, W#
Input
BWx#
Input
K, K#
Input
C, C#
Input
Description
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of K. All transactions operate on a burst of two words (one
clock period of bus activity). These inputs are ignored when device is deselected, i.e., NOP
(LD# = HIGH).
Synchronous Data Inputs: Input data must meet setup and hold times around the rising
edges of K and K# during WRITE operations. See Pin Arrangement for ball site location of
individual signals.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K
and K# rising edges if C and C# are tied HIGH. Data is output in synchronization with C and
C# (or K and K#), depending on the LD# and R, W# command. See Pin Arrangement for
ball site location of individual signals.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined.
This definition includes address and read/write direction. All transactions operate on a burst
of 2 data (one clock period of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type
(READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W#
must meet the setup and hold times around the rising edge of K.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold times
around the rising edges of K and K# for each of the two rising edges comprising the WRITE
cycle. See Pin Arrangement for signal to data relationships.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge of
K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180
degrees out of phase with K. All synchronous inputs must meet setup and hold times around
the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output data.
The rising edge of C# is used as the output timing reference for first output data. The rising
edge of C is used as the output reference for second output data. Ideally, #C is 180 degrees
out of phase with C. When use of K and K# as the reference instead of C and C#, then fixed
C and C# to HIGH. Operation cannot be guaranteed unless C and C# are fixed to HIGH
(i.e. toggle of C and C#)
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 5 of 34
μPD44324185B, μPD44324365B
(2/2)
Symbol
CQ, CQ#
Type
Output
ZQ
Input
DLL#
Input
TMS
TDI
TCK
Input
Input
TDO
Output
VREF
−
VDD
Supply
VDDQ
Supply
VSS
NC
Supply
−
Description
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to
the synchronous data outputs and can be used as a data valid indication. These signals run
freely and do not stop when Q tristates. If C and C# are stopped (if K and K# are stopped in
the single clock mode), CQ and CQ# will also stop.
Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. Q, CQ and CQ# output impedance are set to 0.2 x RQ, where
RQ is a resistor from this bump to ground. The output impedance can be minimized by
directly connect ZQ to VDDQ. This pin cannot be connected directly to GND or left
unconnected. The output impedance is adjusted every 20 μs upon power-up to account for
drifts in supply voltage and temperature. After replacement for a resistor, the new output
impedance is reset by implementing power-on sequence.
PLL Disable: When debugging the system or board, the operation can be performed at a
clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# =
LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL# must
be HIGH and it can be connected to VDDQ through a 10 kΩ or less resistor.
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the
JTAG function is not used in the circuit.
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function
is not used in the circuit.
IEEE 1149.1 Test Output: 1.8 V I/O level.
When providing any external voltage to TDO signal, it is recommended to pull up to VDD.
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the
input buffers.
Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC
Characteristics for range.
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible.
See Recommended DC Operating Conditions and DC Characteristics for range.
Power Supply: Ground
No Connect: These signals are not connected internally.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 6 of 34
μPD44324185B, μPD44324365B
Block Diagram
[μPD44324185B]
20
ADDRESS
LD#
ADDRESS
R, W#
20
REGISTRY
& LOGIC
K
K#
R, W#
BW0#
LD#
36
OUTPUT
BUFFER
ARRAY
36
MUX
OUTPUT
SELECT
MEMORY
OUTPUT
REGISTER
& LOGIC
20
2 x 36
SENSE
AMPS
36
REGISTRY
WRITE
DRIVER
DATA
18
WRITE
REGISTER
BW1#
D0 to D17
18
Q0 to Q17
2
CQ,
CQ#
K
K
K#
K
C, C#
OR
K, K#
[μPD44324365B]
19
ADDRESS
LD#
ADDRESS
R, W#
19
REGISTRY
& LOGIC
K
K#
R, W#
72
OUTPUT
BUFFER
ARRAY
72
MUX
OUTPUT
SELECT
& LOGIC
MEMORY
OUTPUT
REGISTER
REGISTRY
19
2 x 72
SENSE
AMPS
36
72
WRITE
DRIVER
D0 to D35
DATA
WRITE
REGISTER
BW0#
BW1#
BW2#
BW3#
36
Q0 to Q35
2
CQ,
CQ#
LD#
K
K#
R10DS0037EJ0200 Rev.2.00
September 12, 2011
K
K
C, C#
OR
K, K#
Page 7 of 34
μPD44324185B, μPD44324365B
Power-On Sequence in DDR II SRAM
DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
The following timing charts show the recommended power-on sequence.
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and
VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-up.
The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD
and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during
power-down.
Power-On Sequence
Apply power and tie DLL# to HIGH.
- Apply VDD before VDDQ.
- Apply VDDQ before VREF or at the same time as VREF.
Provide stable clock for more than 20 μs to lock the PLL.
PLL Constraints
The PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified as
TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the PLL is
enabled, then the PLL may lock onto an undesired clock frequency.
Power-On Waveforms
VDD/VDDQ
VDD/VDDQ Stable (< ±0.1 V DC per 50 ns)
DLL#
Fix HIGH (or tied to VDDQ)
Clock
Unstable Clock
R10DS0037EJ0200 Rev.2.00
September 12, 2011
20 μs or more
Stable Clock
Normal Operation
Start
Page 8 of 34
μPD44324185B, μPD44324365B
Truth Table
Operation
WRITE cycle
LD# R, W#
L
L
CLK
D or Q
L→H
Data in
Load address, input write data on
Input data
D(A+0)
D(A+1)
consecutive K and K# rising edge
Input clock
K(t+1) ↑
K#(t+1) ↑
READ cycle
L
H
L→H
Data out
Load address, read data on
Output data
Q(A+0)
Q(A+1)
consecutive C and C# rising edge
Output clock
C#(t+1) ↑
C(t+2) ↑
NOP (No operation)
H
×
L→H
D = ×, Q = High-Z
Clock stop
×
×
Stopped
Previous state
Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 9 of 34
μPD44324185B, μPD44324365B
Byte Write Operation
[μPD44324185B]
Operation
K#
BW0#
BW1#
L→H
−
0
0
−
L→H
0
0
L→H
−
0
1
−
L→H
0
1
Write D9 to D17
L→H
−
1
0
−
L→H
1
0
Write nothing
L→H
−
1
1
−
L→H
1
1
Write D0 to D17
Write D0 to D8
K
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2.
Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[μPD44324365B]
Operation
K#
BW0#
BW1#
BW2#
BW3#
L→H
−
0
0
0
0
−
L→H
0
0
0
0
L→H
−
0
1
1
1
−
L→H
0
1
1
1
L→H
−
1
0
1
1
−
L→H
1
0
1
1
Write D18 to D26
L→H
−
1
1
0
1
−
L→H
1
1
0
1
Write D27 to D35
L→H
−
1
1
1
0
−
L→H
1
1
1
0
Write nothing
L→H
−
1
1
1
1
−
L→H
1
1
1
1
Write D0 to D35
Write D0 to D8
Write D9 to D17
K
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 10 of 34
μPD44324185B, μPD44324365B
Bus Cycle State Diagram
LOAD NEW
ADDRESS
Count = 0
Load, Count = 2
Load, Count = 2
Write
Read
READ DOUBLE
Count = Count + 2
WRITE DOUBLE
Count = Count + 2
NOP,
Count = 2
NOP,
Count = 2
Load
NOP
NOP
Power UP
Supply voltage provided
Remark State machine control timing sequence is controlled by K.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 11 of 34
μPD44324185B, μPD44324365B
Electrical Characteristics
Absolute Maximum Ratings
Parameter
Rating
Unit
VDD
−0.5 to +2.5
V
VDDQ
−0.5 to VDD
V
Input voltage
VIN
−0.5 to VDD+0.5 (2.5 V MAX.)
V
Input / Output voltage
VI/O
−0.5 to VDDQ+0.5 (2.5 V MAX.)
V
Operating ambient temperature
TA
0 to 70
°C
Supply voltage
Output supply voltage
Symbol
Conditions
(E** series)
−40 to 85
(E**Y series)
Storage temperature
−55 to +125
Tstg
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter
MIN.
TYP.
MAX.
Unit
VDD
1.7
1.8
1.9
V
Output supply voltage
VDDQ
1.4
VDD
V
1
Input HIGH voltage
VIH (DC)
VREF +0.1
VDDQ+0.3
V
1, 2
Input LOW voltage
VIL (DC)
−0.3
VREF −0.1
V
1, 2
Clock input voltage
VIN
−0.3
VDDQ+0.3
V
1, 2
Reference voltage
VREF
0.68
0.95
V
Supply voltage
Symbol
Conditions
Note
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH ≤ VDDQ +0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter
Symbol
Input HIGH voltage
VIH (AC)
Input LOW voltage
VIL (AC)
Conditions
MIN.
MAX.
VREF +0.2
VREF −0.2
Unit
Note
V
1
V
1
Note 1. Overshoot: VIH (AC) ≤ VDD +0.7 V (2.5 V MAX.) for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 12 of 34
μPD44324185B, μPD44324365B
DC Characteristics 1 (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
MAX.
x18
Unit Note
x36
Input leakage current
ILI
−2
+2
μA
I/O leakage current
ILO
−2
+2
μA
Operating supply current
IDD
(Read cycle / Write cycle)
Standby supply current
ISB1
(NOP)
Output HIGH voltage
530
600
II/O = 0 mA,
-E35
520
580
Cycle = MAX.
-E40
480
540
-E50
420
470
VIN ≤ VIL or VIN ≥ VIH,
-E33
400
420
II/O = 0 mA,
-E35
390
420
Cycle = MAX.
-E40
380
390
Inputs static
-E50
350
360
Note1
VOL(Low) IOL ≤ 0.1 mA
VOL
Notes 1.
2.
3.
4.
-E33
VOH(Low) |IOH| ≤ 0.1 mA
VOH
Output LOW voltage
VIN ≤ VIL or VIN ≥ VIH,
Note2
mA
mA
VDDQ−0.2
VDDQ
V
3, 4
VDDQ/2−0.12
VDDQ/2+0.12
V
3, 4
VSS
0.2
V
3, 4
VDDQ/2−0.12
VDDQ/2+0.12
V
3, 4
Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
AC load current is higher than the shown DC values.
HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 13 of 34
μPD44324185B, μPD44324365B
DC Characteristics 2 (TA = −40 to 85°C, VDD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
MAX.
x18
Unit Note
x36
Input leakage current
ILI
−2
+2
μA
I/O leakage current
ILO
−2
+2
μA
Operating supply current
IDD
(Read cycle / Write cycle)
Standby supply current
ISB1
(NOP)
Output HIGH voltage
680
760
II/O = 0 mA,
-E35Y
670
740
Cycle = MAX.
-E40Y
630
690
-E50Y
560
620
VIN ≤ VIL or VIN ≥ VIH,
-E33Y
530
550
II/O = 0 mA,
-E35Y
520
540
Cycle = MAX.
-E40Y
500
520
Inputs static
-E50Y
470
490
Note1
VOL(Low) IOL ≤ 0.1 mA
VOL
Notes 1.
2.
3.
4.
-E33Y
VOH(Low) |IOH| ≤ 0.1 mA
VOH
Output LOW voltage
VIN ≤ VIL or VIN ≥ VIH,
Note2
mA
mA
VDDQ−0.2
VDDQ
V
3, 4
VDDQ/2−0.12
VDDQ/2+0.12
V
3, 4
VSS
0.2
V
3, 4
VDDQ/2−0.12
VDDQ/2+0.12
V
3, 4
Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
AC load current is higher than the shown DC values.
HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 14 of 34
μPD44324185B, μPD44324365B
Capacitance (TA = 25°C, f = 1 MHz)
Parameter
Input capacitance
Symbol
Test conditions
MIN.
MAX.
Unit
CIN
VIN = 0 V
5
pF
CI/O
VI/O = 0 V
7
pF
Cclk
Vclk = 0 V
6
pF
(Address, Control)
Input / Output capacitance
(DQ, CQ, CQ#)
Clock Input capacitance
Remark These parameters are periodically sampled and not 100% tested.
Thermal Characteristics
Parameter
Thermal resistance
Symbol
θ ja
Substrate
4-layer
from junction to ambient air
8-layer
Thermal characterization parameter
Ψ jt
4-layer
from junction to the top center
of the package surface
Thermal resistance
8-layer
θ jc
Airflow
TYP.
Unit
0 m/s
21.2
°C/W
1 m/s
13.4
°C/W
0 m/s
20.2
°C/W
1 m/s
13.0
°C/W
0 m/s
0.02
°C/W
1 m/s
0.06
°C/W
0 m/s
0.02
°C/W
1 m/s
0.05
°C/W
2.58
°C/W
from junction to case
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 15 of 34
μPD44324185B, μPD44324365B
AC Characteristics (TA = 0 to 70°C or TA = −40 to 85°C, VDD = 1.8 ± 0.1 V)
AC Test Conditions (VDD = 1.8 ± 0.1 V, VDDQ = 1.4 V to VDD)
Input waveform (Rise / Fall time ≤ 0.3 ns)
1.25 V
0.75 V
Test Points
0.75 V
0.25 V
Output waveform
Test Points
VDDQ / 2
VDDQ / 2
Output load condition
Figure 1. External load at test
VDDQ / 2
0.75 V
50 Ω
VREF
ZO = 50 Ω
SRAM
250 Ω
ZQ
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 16 of 34
μPD44324185B, μPD44324365B
Read and Write Cycle
Parameter
Symbol
-E33,E33Y
(300 MHz)
-E35,E35Y
(287 MHz)
-E40,E40Y
(250 MHz)
-E50,E50Y
(200 MHz)
Unit
Note
8.4
ns
1
0.2
2
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock
Average Clock cycle time
(K, K#, C, C#)
Clock phase jitter (K, K#, C, C#)
Clock HIGH time (K, K#, C, C#)
Clock LOW time (K, K#, C, C#)
Clock HIGH to Clock# HIGH
(K → K#, C → C#)
Clock# HIGH to Clock HIGH
(K# → K, C# → C)
Clock to data clock
(K → C, K# → C#)
PLL lock time (K, C)
K static to PLL reset
TKHKH
3.3
8.4
3.5
0.2
8.4
4.0
5.0
TKC var
TKHKL
TKLKH
TKHK#H
1.32
1.32
1.49
1.5
1.5
1.7
1.6
1.6
1.8
2.0
2.0
2.2
ns
ns
ns
ns
TK#HKH
1.49
1.7
1.8
2.2
ns
TKHCH
0
TKC lock
TKC reset
20
30
1.45
0.2
8.4
0
1.65
0.2
0
1.8
0
2.3
ns
20
30
20
30
20
30
μs
ns
3
4
TCQHCQ#H 1.24
1.35
1.55
1.95
ns
5
TCQ#HCQH 1.24
1.35
1.55
1.95
ns
5
Output Times
CQ HIGH to CQ# HIGH
(CQ → CQ#)
CQ# HIGH to CQ HIGH
(CQ# → CQ)
C, C# HIGH to output valid
C, C# HIGH to output hold
C, C# HIGH to echo clock valid
C, C# HIGH to echo clock hold
CQ, CQ# HIGH to output valid
CQ, CQ# HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
TCHQV
TCHQX
TCHCQV
TCHCQX
TCQHQV
TCQHQX
TCHQZ
TCHQX1
0.45
−0.45
−0.45
−0.45
−0.45
ns
ns
ns
ns
ns
ns
ns
ns
TAVKH
TIVKH
0.4
0.4
0.5
0.5
0.5
0.5
0.6
0.6
ns
ns
7
7
TDVKH
0.3
0.35
0.35
0.4
ns
7
TKHAX
TKHIX
0.4
0.4
0.5
0.5
0.5
0.5
0.6
0.6
ns
ns
7
7
TKHDX
0.3
0.35
0.35
0.4
ns
7
−0.45
0.45
−0.45
0.45
−0.45
0.45
−0.45
0.27
−0.27
0.45
−0.45
0.45
−0.45
0.3
−0.3
0.45
0.45
−0.45
0.45
−0.45
0.3
−0.3
0.45
0.35
−0.35
0.45
0.45
6
6
Setup Times
Address valid to K rising edge
Synchronous load input (LD#),
read write input (R, W#) valid to
K rising edge
Data inputs and write data
select inputs (BWx#) valid to
K, K# rising edge
Hold Times
K rising edge to address hold
K rising edge to
synchronous load input (LD#),
read write input (R, W#) hold
K, K# rising edge to data inputs
and write data select inputs
(BWx#) hold
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 17 of 34
μPD44324185B, μPD44324365B
Notes 1.
When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock
cycle in this operation. The AC/DC characteristics cannot be guaranteed, however.
2.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
3.
VDD slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention.
PLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept NOP (LD# = HIGH) during these cycles.
4. K input is monitored for this operation. See below for the timing.
K
or
TKC reset
K
TKC reset
5. Guaranteed by design.
6. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
7. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold
times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5. VDDQ is 1.5 V DC.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 18 of 34
μPD44324185B, μPD44324365B
Read and Write Timing
NOP
READ
(burst of 2)
1
2
READ
(burst of 2)
3
WRITE
(burst of 2)
WRITE
(burst of 2)
4
5
READ
(burst of 2)
6
NOP
7
8
K
TKHKL
TKLKH
TKHKH
TKHK#H
TK#HKH
K#
LD#
TKHIX
TIVKH
R, W#
A0
Address
A1
A2
A4
A3
TDVKH
TKHDX
TAVKH TKHAX
Data in
Data out
Q00
Qx2
Q01
D20
D21
Q10
Q11
TCHQX1
TDVKH TKHDX
D30
D31
Q40
TCHQZ
TCHQX
TCQHQV
Q41
TCQHQX
TCHQX
TCHQV
TCHQV
CQ
TCHCQX
TCHCQV
TCQHCQ#H TCQ#HCQH
CQ#
TKHCH
TCHCQX
TCHCQV
C
TKHKL
TKLKH
TKHKH
TKHK#H TK#HKH
TKHCH
C#
Remarks 1. Q01 refers to output from address A0+0.
Q02 refers to output from the next internal burst address following A0, i.e., A0+1.
2. Outputs are disabled (high impedance) 2.5 clock cycles after the last READ (LD# = LOW, R, W# =
HIGH) is input in the sequences of [READ]-[NOP] and [READ]-[WRITE].
3. In this example, if address A4 = A3, data Q41 = D31 and Q42 = D32.
Write data is forwarded immediately as read results.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 19 of 34
μPD44324185B, μPD44324365B
Application Example
SRAM#1
ZQ
CQ#
CQ
DQ
SRAM
Controller
Vt
A
R=
250 Ω
...
SRAM#4
ZQ
CQ#
CQ
R=
250 Ω
DQ
LD# R, W# BWx# C/C# K/K#
A
LD# R, W# BWx# C/C# K/K#
R
Data IO
Address
R
LD#
Vt
R, W#
BW#
...
SRAM#1 CQ/CQ#
SRAM#4 CQ/CQ#
Vt
R
Vt
R
Source CLK/CLK#
Return CLK/CLK#
Vt
R
R = 50 Ω Vt = Vref
Remark AC Characteristics are defined at the condition of SRAM outputs, CQ, CQ# and DQ with termination.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 20 of 34
μPD44324185B, μPD44324365B
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
Pin assignments
Description
TCK
2R
TMS
10R
TDI
11R
Test Data Input. This is the input side of the serial registers placed between
TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP controller state machine and the instruction that is currently
loaded in the TAP instruction.
TDO
1R
Test Data Output. This is the output side of the serial registers placed between
TDI and TDO. Output changes in response to the falling edge of TCK.
Test Clock Input. All input are captured on the rising edge of TCK and all
outputs propagate from the falling edge of TCK.
Test Mode Select. This is the command input for the TAP controller state
machine.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
JTAG Input leakage current
ILI
0 V ≤ VIN ≤ VDD
−5.0
+5.0
μA
JTAG I/O leakage current
ILO
0 V ≤ VIN ≤ VDDQ,
−5.0
+5.0
μA
Outputs disabled
JTAG input HIGH voltage
VIH
1.3
VDD+0.3
V
JTAG input LOW voltage
VIL
−0.3
+0.5
V
JTAG output HIGH voltage
JTAG output LOW voltage
R10DS0037EJ0200 Rev.2.00
September 12, 2011
VOH1
| IOHC | = 100 μA
1.6
V
VOH2
| IOHT | = 2 mA
1.4
V
VOL1
IOLC = 100 μA
0.2
V
VOL2
IOLT = 2 mA
0.4
V
Page 21 of 34
μPD44324185B, μPD44324365B
JTAG AC Test Conditions
Input waveform (Rise / Fall time ≤ 1 ns)
1.8 V
0.9 V
Test Points
0.9 V
0.9 V
Test Points
0.9 V
0V
Output waveform
Output load
Figure 2. External load at test
VTT = 0.9 V
50 Ω
ZO = 50 Ω
TDO
20 pF
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 22 of 34
μPD44324185B, μPD44324365B
JTAG AC Characteristics (TA = 0 to 70°C)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Clock
Clock cycle time
tTHTH
50
ns
Clock frequency
fTF
Clock HIGH time
tTHTL
20
ns
Clock LOW time
tTLTH
20
ns
TCK LOW to TDO unknown
tTLOX
0
TCK LOW to TDO valid
tTLOV
20
MHz
Output time
ns
10
ns
Setup time
TMS setup time
tMVTH
5
ns
TDI valid to TCK HIGH
tDVTH
5
ns
tCS
5
ns
TMS hold time
tTHMX
5
ns
TCK HIGH to TDI invalid
tTHDX
5
ns
tCH
5
ns
Capture setup time
Hold time
Capture hold time
JTAG Timing Diagram
tTHTH
TCK
tMVTH
tTHTL
tTLTH
TMS
tTHMX
tDVTH
TDI
tTHDX
tTLOX
tTLOV
TDO
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 23 of 34
μPD44324185B, μPD44324365B
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller
when it is moved into the run-test/idle or the various data register state. The register can
be loaded when it is placed between the TDI and TDO pins. The instruction register is
automatically preloaded with the IDCODE instruction at power-up whenever the controller
is placed in test-logic-reset state.
Bypass register
The bypass register is a single bit register that can be placed between TDI and TDO. It
allows serial test data to be passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
ID register
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit
code when the controller is put in capture-DR state with the IDCODE command loaded in
the instruction register. The register is then placed between the TDI and TDO pins when
the controller is moved into shift-DR state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents
of the RAMs I/O ring when the controller is in capture-DR state and then is placed
between the TDI and TDO pins when the controller is moved to shift-DR state. Several
TAP instructions can be used to activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary
register location. The first column defines the bit’s position in the boundary register. The
second column is the name of the input or I/O at the bump and the third column is the
bump number.
Scan Register Definition (2)
Register name
Bit size
Unit
Instruction register
3
bit
Bypass register
1
bit
ID register
32
bit
Boundary register
109
bit
ID Register Definition
Part number
Organization
ID [31:28] vendor
revision no.
ID [27:12] part no.
ID [11:1] vendor
ID no.
ID [0] fix bit
μPD44324185B
2M x 18
XXXX
0000 0000 0100 0111
00000010000
1
μPD44324365B
1M x 36
XXXX
0000 0000 0100 1000
00000010000
1
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 24 of 34
μPD44324185B, μPD44324365B
SCAN Exit Order
Bit
Signal name
no.
x18
x36
Bump
Bit
Signal name
Bump
Bit
Signal name
ID
no.
x18
Bump
x36
ID
no.
x18
x36
ID
1
C#
6R
37
NC
D15
10D
73
NC
Q28
2C
2
C
6P
38
NC
Q15
9E
74
Q11
Q20
3E
3
A
6N
39
Q7
10C
75
D11
D20
2D
4
A
7P
40
D7
11D
76
NC
D29
2E
5
A
7N
41
NC
D16
9C
77
NC
Q29
1E
6
A
7R
42
NC
Q16
9D
78
Q12
Q21
2F
7
A
8R
43
Q8
11B
79
D12
D21
3F
8
A
8P
44
D8
11C
80
NC
D30
1G
9
A
9R
45
NC
D17
9B
81
NC
Q30
1F
10
Q0
11P
46
NC
Q17
10B
82
Q13
Q22
3G
11
D0
10P
47
CQ
11A
83
D13
D22
2G
12
NC
D9
10N
48
VSS
10A
84
DLL#
1H
13
NC
Q9
9P
49
A
9A
85
NC
D31
1J
14
Q1
10M
50
A
8B
86
NC
Q31
2J
15
D1
11N
51
A
7C
87
Q14
Q23
3K
16
NC
D10
9M
52
A
6C
88
D14
D23
3J
17
NC
Q10
9N
53
LD#
8A
89
NC
D32
2K
18
Q2
11L
54
NC
BW1#
7A
90
NC
Q32
1K
19
D2
11M
55
BW0#
BW0#
7B
91
Q15
Q24
2L
20
NC
D11
9L
56
K
6B
92
D15
D24
3L
21
NC
Q11
10L
57
K#
6A
93
NC
D33
1M
22
Q3
11K
58
NC
BW3#
5B
94
NC
Q33
1L
23
D3
10K
59
BW1#
BW2#
5A
95
Q16
Q25
3N
24
NC
D12
9J
60
R, W#
4A
96
D16
D25
3M
25
NC
Q12
9K
61
A
5C
97
NC
D34
1N
A
4B
98
NC
Q34
2M
3A
99
Q17
Q26
3P
26
Q4
10J
62
27
D4
11J
63
28
ZQ
11H
64
VSS
2A
100
D17
D26
2N
CQ#
1A
101
NC
D35
2P
NC
Q35
1P
A
NC
29
NC
D13
10G
65
30
NC
Q13
9G
66
Q9
Q18
2B
102
31
Q5
11F
67
D9
D18
3B
103
A
3R
32
D5
11G
68
NC
D27
1C
104
A
4R
33
NC
D14
9F
69
NC
Q27
1B
105
A
4P
34
NC
Q14
10F
70
Q10
Q19
3D
106
A
5P
35
Q6
11E
71
D10
D19
3C
107
A
5N
36
D6
10E
72
NC
D28
1D
108
A
5R
109
–
Internal
Remark Bump ID 10A of bit no. 48 and Bump ID 2A of bit no. 64 can also be used as NC.
The register always indicates LOW, however.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 25 of 34
μPD44324185B, μPD44324365B
JTAG Instructions
Instructions
Description
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested.
Boundary-scan register cells at output pins are used to apply test vectors, while those at
input pins capture test results. Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary scan register using the PRELOAD
instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on and
the PRELOAD data is driven onto the output pins.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the
controller is in capture-DR mode and places the ID register between the TDI and TDO pins
in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up
and any time the controller is placed in the test-logic-reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction register, the bypass register is
placed between TDI and TDO. This occurs when the TAP controller is moved to the shiftDR state. This allows the board level scan path to be shortened to facilitate testing of other
devices in the scan path.
SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the
SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP
controller into the capture-DR state loads the data in the RAMs input and DQ pins into the
boundary scan register. Because the RAM clock(s) are independent from the TAP clock
(TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample
metastable input will not harm the device, repeatable results cannot be expected. RAM
input signals must be stabilized for long enough to meet the TAPs input data capture setup
plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other
TAP operation except capturing the I/O ring contents into the boundary scan register.
Moving the controller to shift-DR state then places the boundary scan register between the
TDI and TDO pins.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM DQ pins are
forced to an inactive drive state (high impedance) and the boundary register is connected
between TDI and TDO when the TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2
IR1
IR0
Instruction
0
0
0
EXTEST
Note
0
0
1
IDCODE
0
1
0
SAMPLE-Z
1
0
1
1
RESERVED
2
1
0
0
SAMPLE / PRELOAD
1
0
1
RESERVED
2
1
1
0
RESERVED
2
1
1
1
BYPASS
Notes 1. TRISTATE all DQ pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
2. Do not use this instruction code because the vendor uses it to evaluate this product.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 26 of 34
μPD44324185B, μPD44324365B
Output Pin States of CQ, CQ# and Q
Instructions
Control-Register Status
Output Pin Status
CQ,CQ#
Q
0
Update
High-Z
1
Update
Update
0
SRAM
SRAM
1
SRAM
SRAM
SAMPLE-Z
0
High-Z
High-Z
1
High-Z
High-Z
SAMPLE
0
SRAM
SRAM
1
SRAM
SRAM
0
SRAM
SRAM
1
SRAM
SRAM
EXTEST
IDCODE
BYPASS
Remark The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Boundary Scan
Register
Register, bit no. 109).
CAPTURE
Register
There are three statuses:
Update : Contents of the “Update Register” are output to the
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (DDR Pad).
SRAM
Output
Update
Register
output pin (DDR Pad).
Update
High-Z :The output pin (DDR Pad) becomes high
impedance by controlling of the “High-Z JTAG
ctrl”.
The Control-Register status is set during Update-DR at the
DDR
Pad
SRAM
High-Z
SRAM
Output
Driver
EXTEST or SAMPLE instruction.
High-Z
JTAG ctrl
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 27 of 34
μPD44324185B, μPD44324365B
Boundary Scan Register Status of Output Pins CQ, CQ# and Q
Instructions
SRAM Status
Boundary Scan Register Status
CQ,CQ#
Q
READ (Low-Z)
Pad
Pad
NOP (High-Z)
Pad
Pad
READ (Low-Z)
−
−
NOP (High-Z)
−
−
SAMPLE-Z
READ (Low-Z)
Pad
Pad
NOP (High-Z)
Pad
Pad
SAMPLE
READ (Low-Z)
Internal
Internal
NOP (High-Z)
Internal
Pad
READ (Low-Z)
−
−
NOP (High-Z)
−
−
EXTEST
IDCODE
BYPASS
Remark The Boundary Scan Register statuses during execution each
Note
No definition
No definition
Boundary Scan
Register
instruction vary according to the instruction code and SRAM
CAPTURE
Register
operation mode.
There are two statuses:
Internal
Pad
: Contents of the output pin (DDR Pad) are captured
in the “CAPTURE Register” in the Boundary Scan
Update
Register
Pad
SRAM
Output
Register.
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
DDR
Pad
SRAM
Output
Driver
High-Z
JTAG ctrl
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 28 of 34
μPD44324185B, μPD44324365B
TAP Controller State Diagram
1
Test-Logic-Reset
0
1
0
1
1
Select-IR-Scan
Select-DR-Scan
Run-Test / Idle
0
0
1
1
Capture-IR
Capture-DR
0
0
0
Shift-DR
0
Shift-IR
1
1
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
0
Pause-IR
1
1
0
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
Update-IR
0
1
0
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open
but fix them to VDD via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected
also when the TAP controller is not used.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 29 of 34
New Instruction
μPD44324185B, μPD44324365B
Run-Test/Idle
Update-IR
Exit1-IR
Shift-IR
Exit2-IR
IDCODE
Pause-IR
Exit1-IR
Shift-IR
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Select-IR-Scan
Run-Test/Idle
Instruction
Register state
TDI
Controller
state
TMS
Test-Logic-Reset
TDO
Output Inactive
Select-DR-Scan
TCK
Test Logic Operation (Instruction Scan)
Capture-IR
Page 30 of 34
IDCODE
μPD44324185B, μPD44324365B
Test-Logic-Reset
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Update-DR
Exit1-DR
Shift-DR
Instruction
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Instruction
Register state
TDI
Controller
state
TMS
TCK
Test Logic (Data Scan)
Run-Test/Idle
TDO
Output Inactive
Select-DR-Scan
Page 31 of 34
μPD44324185B, μPD44324365B
Package Dimensions
165-PIN PLASTIC BGA(15x17)
w S B
E
ZD
ZE
B
11
10
9
8
7
6
5
4
3
2
1
A
D
R P N M L K J H G F E D C B A
INDEX MARK
w S A
A
y1
(UNIT:mm)
A2
S
S
y
e
S
b
x
A1
M
S AB
ITEM
D
DIMENSIONS
15.00±0.10
E
17.00±0.10
w
0.30
A
1.35±0.11
A1
0.37±0.05
A2
0.98
e
1.00
b
+0.10
0.50 0.05
x
0.10
y
0.15
y1
0.25
ZD
2.50
ZE
1.50
P165F5-100-FQ1-1
Renesas El ectronics Corporation 2010
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 32 of 34
μPD44324185B, μPD44324365B
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products.
Types of Surface Mount Devices
μPD44324185BF5-FQ1 : 165-pin PLASTIC BGA (15 x 17)
μPD44324365BF5-FQ1 : 165-pin PLASTIC BGA (15 x 17)
Quality Grade
• A quality grade of the products is “Standard”.
• Anti-radioactive design is not implemented in the products.
• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to
the ground and so forth.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 33 of 34
Revision History
Rev.
Date
1st edition
2nd edition
’08.03.01
’10.03.01
Rev.1.00
Rev.2.00
’10.09.10
’11.09.12
μPD44324185B , μPD44324365B
Description
Page
P14
P15
Throughout
Throughout
Summary
New Preliminary Data Sheet
DC Characteristics (Modification, Spec of IDD and ISB1)
Thermal Characteristics (Modification, Spec)
Preliminary Data Sheet → Data Sheet
Add Lead and the extended temperature operation product
All trademarks and registered trademarks are the property of their respective owners.
C - 34
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