Datasheet
μPD44324092B
μPD44324182B
μPD44324362B
36M-BIT DDR II SRAM
2-WORD BURST OPERATION
R10DS0036EJ0200
Rev.2.00
August 2, 2011
Description
The μPD44324092B is a 4,194,304-word by 9-bit, the μPD44324182B is a 2,097,152-word by 18-bit and the
μPD44324362B is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with
advanced CMOS technology using full CMOS six-transistor memory cell.
The μPD44324092B, μPD44324182B and μPD44324362B integrate unique synchronous peripheral circuitry
and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the
positive edge of K and K#. These products are suitable for application which require synchronous operation,
high speed, low voltage, high density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply
• 165-pin PLASTIC BGA (15 x 17)
• HSTL interface
• PLL circuitry for wide output data valid window and future frequency scaling
• Pipelined double data rate operation
• Common data input/output bus
• Two-tick burst for low DDR transaction size
• Two input clocks (K and K#) for precise DDR timing at clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
• User programmable impedance output (35 to 70 Ω)
• Fast clock cycle time : 3.3 ns (300 MHz), 3.5ns (287MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
R10DS0036EJ0100 Rev.2.00
August 2, 2011
Page 1 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Ordering Information (1/2)
Part No.
μPD44324092BF5-E33-FQ1-A
μPD44324092BF5-E35-FQ1-A
μPD44324092BF5-E40-FQ1-A
μPD44324092BF5-E50-FQ1-A
μPD44324182BF5-E33-FQ1-A
μPD44324182BF5-E35-FQ1-A
μPD44324182BF5-E40-FQ1-A
μPD44324182BF5-E50-FQ1-A
μPD44324362BF5-E33-FQ1-A
μPD44324362BF5-E35-FQ1-A
μPD44324362BF5-E40-FQ1-A
μPD44324362BF5-E50-FQ1-A
μPD44324092BF5-E33-FQ1
μPD44324092BF5-E35-FQ1
μPD44324092BF5-E40-FQ1
μPD44324092BF5-E50-FQ1
μPD44324182BF5-E33-FQ1
μPD44324182BF5-E35-FQ1
μPD44324182BF5-E40-FQ1
μPD44324182BF5-E50-FQ1
μPD44324362BF5-E33-FQ1
μPD44324362BF5-E35-FQ1
μPD44324362BF5-E40-FQ1
μPD44324362BF5-E50-FQ1
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Organization
(word x bit)
4M x 9
2M x 18
1M x 36
4M x 9
2M x 18
1M x 36
Cycle
time
Clock
frequency
Operating Ambient
Temperature
Ta = 0 to 70°C
Package
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
(15 x 17)
5.0ns
200MHz
Lead-free
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
5.0ns
200MHz
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
5.0ns
200MHz
3.3ns
300MHz
165-pin
PLASTIC BGA
Ta = 0 to 70°C
165-pin
3.5ns
287MHz
PLASTIC BGA
4.0ns
250MHz
(15 x 17)
5.0ns
200MHz
Lead
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
5.0ns
200MHz
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
5.0ns
200MHz
Page 2 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Ordering Information (2/2)
Part No.
μPD44324092BF5-E33Y-FQ1-A
μPD44324092BF5-E35Y-FQ1-A
μPD44324092BF5-E40Y-FQ1-A
μPD44324092BF5-E50Y-FQ1-A
μPD44324182BF5-E33Y-FQ1-A
μPD44324182BF5-E35Y-FQ1-A
μPD44324182BF5-E40Y-FQ1-A
μPD44324182BF5-E50Y-FQ1-A
μPD44324362BF5-E33Y-FQ1-A
μPD44324362BF5-E35Y-FQ1-A
μPD44324362BF5-E40Y-FQ1-A
μPD44324362BF5-E50Y-FQ1-A
μPD44324092BF5-E33Y-FQ1
μPD44324092BF5-E35Y-FQ1
μPD44324092BF5-E40Y-FQ1
μPD44324092BF5-E50Y-FQ1
μPD44324182BF5-E33Y-FQ1
μPD44324182BF5-E35Y-FQ1
μPD44324182BF5-E40Y-FQ1
μPD44324182BF5-E50Y-FQ1
μPD44324362BF5-E33Y-FQ1
μPD44324362BF5-E35Y-FQ1
μPD44324362BF5-E40Y-FQ1
μPD44324362BF5-E50Y-FQ1
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Organization
(word x bit)
4M x 9
2M x 18
1M x 36
4M x 9
2M x 18
1M x 36
Cycle
time
Clock
frequency
Operating Ambient
Temperature
Ta = −40 to 85°C
Package
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
(15 x 17)
5.0ns
200MHz
Lead-free
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
5.0ns
200MHz
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
5.0ns
200MHz
3.3ns
300MHz
165-pin
PLASTIC BGA
Ta = −40 to 85°C
165-pin
3.5ns
287MHz
PLASTIC BGA
4.0ns
250MHz
(15 x 17)
5.0ns
200MHz
Lead
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
5.0ns
200MHz
3.3ns
300MHz
3.5ns
287MHz
4.0ns
250MHz
5.0ns
200MHz
Page 3 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Pin Arrangement
165-pin PLASTIC BGA (15 x 17)
(Top View)
[μPD44324092B]
4M x 9
1
2
3
4
5
6
7
8
9
10
11
A
CQ#
VSS/72M
A
R, W#
NC
K#
NC/144M
LD#
A
A
CQ
B
NC
NC
NC
A
NC/288M
K
BW0#
A
NC
NC
DQ4
C
NC
NC
NC
VSS
A
A
A
VSS
NC
NC
NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ5
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ3
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ6
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DLL#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ2
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ7
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ1
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
N
NC
NC
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
DQ8
A
A
C
A
A
NC
NC
DQ0
R
TDO
TCK
A
A
A
C#
A
A
A
TMS
TDI
A
DQ0 to DQ8
LD#
R, W#
BW0#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
Remarks 1.
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
×××# indicates active LOW.
2.
Refer to Package Dimensions for the index mark.
3.
2A, 7A and 5B are expansion addresses : 2A for 72Mb
: 2A and 7A for 144Mb
: 2A, 7A and 5B for 288Mb
2A of this product can also be used as NC.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 4 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Pin Arrangement
165-pin PLASTIC BGA (15 x 17)
(Top View)
[μPD44324182B]
2M x 18
1
2
3
4
5
6
7
8
9
10
11
A
CQ#
VSS/72M
A
R, W#
BW1#
K#
NC/144M
LD#
A
A
CQ
B
NC
DQ9
NC
A
NC/288M
K
BW0#
A
NC
NC
DQ8
C
NC
NC
NC
VSS
A
A0
A
VSS
NC
DQ7
NC
D
NC
NC
DQ10
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ6
F
NC
DQ12
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DLL#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ4
NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ3
L
NC
DQ15
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
DQ1
NC
N
NC
NC
DQ16
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
DQ17
A
A
C
A
A
NC
NC
DQ0
R
TDO
TCK
A
A
A
C#
A
A
A
TMS
TDI
A0, A
DQ0 to DQ17
LD#
R, W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
Remarks 1.
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
×××# indicates active LOW.
2.
Refer to Package Dimensions for the index mark.
3.
2A, 7A and 5B are expansion addresses : 2A for 72Mb
: 2A and 7A for 144Mb
: 2A, 7A and 5B for 288Mb
2A of this product can also be used as NC.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 5 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Pin Arrangement
165-pin PLASTIC BGA (15 x 17)
(Top View)
[μPD44324362B]
1M x 36
1
2
3
4
5
6
7
8
9
10
11
A
CQ#
VSS/144M
A
R, W#
BW2#
K#
BW1#
LD#
A
VSS/72M
CQ
B
NC
DQ27
DQ18
A
BW3#
K
BW0#
A
NC
NC
DQ8
C
NC
NC
DQ28
VSS
A
A0
A
VSS
NC
DQ17
DQ7
D
NC
DQ29
DQ19
VSS
VSS
VSS
VSS
VSS
NC
NC
DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ14
H
DLL#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
DQ34
VSS
VSS
VSS
VSS
VSS
NC
DQ11
DQ1
N
NC
DQ35
DQ25
VSS
A
A
A
VSS
NC
NC
DQ10
P
NC
NC
DQ26
A
A
C
A
A
NC
DQ9
DQ0
R
TDO
TCK
A
A
A
C#
A
A
A
TMS
TDI
A0, A
DQ0 to DQ35
LD#
R, W#
BW0# to BW3#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
Remarks 1.
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
×××# indicates active LOW.
2.
Refer to Package Dimensions for the index mark.
3.
2A and 10A are expansion addresses : 10A for 72Mb
: 10A and 2A for 144Mb
2A and 10A of this product can also be used as NC.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 6 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Pin Description
(1/2)
Symbol
A0
A
Type
Input
DQ0 to
DQxx
Input/Output
LD#
Input
R, W#
Input
BWx#
Input
K, K#
Input
C, C#
Input
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Description
Synchronous Address Inputs: These inputs are registered and must meet the setup and
hold times around the rising edge of K. All transactions operate on a burst of two words
(one clock period of bus activity). A0 is used as the lowest order address bit permitting a
random starting address within the burst operation on x18 and x36 devices. These inputs
are ignored when device is deselected, i.e., NOP (LD# = HIGH).
Synchronous Data IOs: Input data must meet setup and hold times around the rising
edges of K and K#. Output data is synchronized to the respective C and C# data clocks
or to K and K# if C and C# are tied to HIGH.
x9 device uses DQ0 to DQ8.
x18 device uses DQ0 to DQ17.
x36 device uses DQ0 to DQ35.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be
defined. This definition includes address and read/write direction. All transactions operate
on a burst of 2 data (one clock period of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type
(READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W#
must meet the setup and hold times around the rising edge of K.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold
times around the rising edges of K and K# for each of the two rising edges comprising the
WRITE cycle. See Pin Arrangement for signal to data relationships.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge
of K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally
180 degrees out of phase with K. All synchronous inputs must meet setup and hold times
around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output
data. The rising edge of C# is used as the output timing reference for first output data.
The rising edge of C is used as the output reference for second output data. Ideally, C# is
180 degrees out of phase with C. When use of K and K# as the reference instead of C
and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and C#
are fixed to HIGH (i.e. toggle of C and C#)
Page 7 of 36
μPD44324092B, μPD44324182B, μPD44324362B
(2/2)
Symbol
Type
Description
CQ, CQ#
Output
ZQ
Input
DLL#
Input
TMS
TDI
TCK
Input
TDO
Output
VREF
−
VDD
Supply
VDDQ
Supply
VSS
Supply
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched
to the synchronous data outputs and can be used as a data valid indication. These signals
run freely and do not stop when DQ tristates. If C and C# are stopped (if K and K# are
stopped in the single clock mode), CQ and CQ# will also stop.
Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. DQ, CQ and CQ# output impedance are set to 0.2 x RQ,
where RQ is a resistor from this bump to ground. The output impedance can be
minimized by directly connect ZQ to VDDQ. This pin cannot be connected directly to GND
or left unconnected. The output impedance is adjusted every 20 μs upon power-up to
account for drifts in supply voltage and temperature. After replacement for a resistor, the
new output impedance is reset by implementing power-on sequence.
PLL Disable: When debugging the system or board, the operation can be performed at a
clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# =
LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL# must
be HIGH and it can be connected to VDDQ through a 10 kΩ or less resistor.
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the
JTAG function is not used in the circuit.
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG
function is not used in the circuit.
IEEE 1149.1 Test Output: 1.8 V I/O level.
When providing any external voltage to TDO signal, it is recommended to pull up to VDD.
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the
input buffers.
Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC
Characteristics for range.
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible.
See Recommended DC Operating Conditions and DC Characteristics for range.
Power Supply: Ground
NC
−
No Connect: These signals are not connected internally.
Input
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 8 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Block Diagram
CLK
Burst
Logic
A0
D0
A0'
Q0
R
Address
Register
Address
LD#
W#
E
Compare
C#
A0''
Write address
Register
K
E
Output control A0'''
Logic
A0'
/A0'
/A0'
Memory
Array
A0'
Sense Amps
CLK
WRITE Driver
A0'
K
Output Register
Input
Register
WRITE Register
E
C
0
ZQ
2 :1
MUX
1
Output Buffer
E
DQ
0
K#
E
Input
Register
1
A0'''
Output Enable
Register
C
R, W#
Register
R, W#`
E
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 9 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Power-On Sequence in DDR II SRAM
DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
The following timing charts show the recommended power-on sequence.
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and
VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-up.
The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD
and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during
power-down.
Power-On Sequence
Apply power and tie DLL# to HIGH.
- Apply VDD before VDDQ.
- Apply VDDQ before VREF or at the same time as VREF.
Provide stable clock for more than 20 μs to lock the PLL.
PLL Constraints
The PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified as
TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the PLL is
enabled, then the PLL may lock onto an undesired clock frequency.
Power-On Waveforms
VDD/VDDQ
VDD/VDDQ Stable (< ±0.1 V DC per 50 ns)
DLL#
Fix HIGH (or tied to VDDQ)
Clock
Unstable Clock
R10DS0036EJ0200 Rev.2.00
August 2, 2011
20 μs or more
Stable Clock
Normal Operation
Start
Page 10 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Burst Sequence
Linear Burst Sequence Table
[μPD44324182B, μPD44324362B]
A0
A0
External Address
0
1
1st Internal Burst Address
1
0
Truth Table
Operation
WRITE cycle
LD# R, W#
L
L
CLK
DQ
L→H
Data in
Load address, input write data on
Input data
D(A1)
D(A2)
consecutive K and K# rising edge
Input clock
K(t+1) ↑
K#(t+1) ↑
READ cycle
L
H
L→H
Data out
Load address, read data on
Output data
Q(A1)
Q(A2)
consecutive C and C# rising edge
Output clock
C#(t+1) ↑
C(t+2) ↑
NOP (No operation)
H
×
L→H
High-Z
Clock stop
×
×
Stopped
Previous state
Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst
address in accordance with the linear burst sequence.
7. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 11 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Byte Write Operation
[μPD44324092B]
Operation
Write DQ0 to DQ8
Write nothing
K
K#
BW0#
L→H
−
0
−
L→H
0
L→H
−
1
−
L→H
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[μPD44324182B]
Operation
Write DQ0 to DQ17
Write DQ0 to DQ8
Write DQ9 to DQ17
Write nothing
K
K#
BW0#
BW1#
L→H
−
0
0
−
L→H
0
0
L→H
−
0
1
−
L→H
0
1
L→H
−
1
0
−
L→H
1
0
L→H
−
1
1
−
L→H
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[μPD44324362B]
K
K#
BW0#
BW1#
BW2#
BW3#
Write DQ0 to DQ35
Operation
L→H
−
0
0
0
0
−
L→H
0
0
0
0
Write DQ0 to DQ8
L→H
−
0
1
1
1
−
L→H
0
1
1
1
Write DQ9 to DQ17
L→H
−
1
0
1
1
−
L→H
1
0
1
1
L→H
−
1
1
0
1
−
L→H
1
1
0
1
L→H
−
1
1
1
0
−
L→H
1
1
1
0
L→H
−
1
1
1
1
−
L→H
1
1
1
1
Write DQ18 to DQ26
Write DQ27 to DQ35
Write nothing
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 12 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Bus Cycle State Diagram
LOAD NEW
ADDRESS
Count = 0
Load, Count = 2
Load, Count = 2
Write
Read
READ DOUBLE
Count = Count + 2
WRITE DOUBLE
Count = Count + 2
NOP,
Count = 2
NOP,
Count = 2
Load
NOP
NOP
Power UP
Supply voltage provided
Remarks 1. A0 is internally advanced in accordance with the burst order table.
Bus cycle is terminated after burst count = 2.
2. State machine control timing sequence is controlled by K.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 13 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Electrical Characteristics
Absolute Maximum Ratings
Parameter
Rating
Unit
VDD
−0.5 to +2.5
V
VDDQ
−0.5 to VDD
V
Input voltage
VIN
−0.5 to VDD+0.5 (2.5 V MAX.)
V
Input / Output voltage
VI/O
−0.5 to VDDQ+0.5 (2.5 V MAX.)
V
Operating ambient temperature
TA
0 to 70
°C
Supply voltage
Output supply voltage
Symbol
Conditions
(E** series)
−40 to 85
(E**Y series)
Storage temperature
−55 to +125
Tstg
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter
MIN.
TYP.
MAX.
Unit
VDD
1.7
1.8
1.9
V
Output supply voltage
VDDQ
1.4
VDD
V
1
Input HIGH voltage
VIH (DC)
VREF +0.1
VDDQ+0.3
V
1, 2
Input LOW voltage
VIL (DC)
−0.3
VREF −0.1
V
1, 2
Clock input voltage
VIN
−0.3
VDDQ+0.3
V
1, 2
Reference voltage
VREF
0.68
0.95
V
Supply voltage
Symbol
Conditions
Note
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter
Symbol
Input HIGH voltage
VIH (AC)
Input LOW voltage
VIL (AC)
Conditions
MIN.
MAX.
VREF +0.2
VREF −0.2
Unit
Note
V
1
V
1
Note 1. Overshoot: VIH (AC) ≤ VDD +0.7 V (2.5 V MAX.) for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 14 of 36
μPD44324092B, μPD44324182B, μPD44324362B
DC Characteristics 1 (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
MAX.
x9
x18
Unit Note
x36
Input leakage current
ILI
−2
+2
μA
I/O leakage current
ILO
−2
+2
μA
Operating supply current
IDD
(Read cycle / Write cycle)
Standby supply current
ISB1
(NOP)
Output HIGH voltage
470
510
II/O = 0 mA,
-E35
430
460
500
Cycle = MAX.
-E40
410
430
470
-E50
380
390
420
VIN ≤ VIL or VIN ≥ VIH, -E33
390
410
430
II/O = 0 mA,
-E35
380
400
420
Cycle = MAX.
-E40
370
380
400
Inputs static
-E50
340
350
370
Note1
VOL(Low) IOL ≤ 0.1 mA
VOL
Notes 1.
2.
3.
4.
440
VOH(Low) |IOH| ≤ 0.1 mA
VOH
Output LOW voltage
VIN ≤ VIL or VIN ≥ VIH, -E33
Note2
mA
mA
VDDQ−0.2
VDDQ
V
3, 4
VDDQ/2−0.12
VDDQ/2+0.12
V
3, 4
VSS
0.2
V
3, 4
VDDQ/2−0.12
VDDQ/2+0.12
V
3, 4
Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
AC load current is higher than the shown DC values.
HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 15 of 36
μPD44324092B, μPD44324182B, μPD44324362B
DC Characteristics 2 (TA = −40 to 85°C, VDD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
MAX.
x9
x18
Unit Note
x36
Input leakage current
ILI
−2
+2
μA
I/O leakage current
ILO
−2
+2
μA
Operating supply current
IDD
(Read cycle / Write cycle)
Standby supply current
ISB1
(NOP)
Output HIGH voltage
600
640
II/O = 0 mA,
-E35Y
560
590
630
Cycle = MAX.
-E40Y
540
560
600
-E50Y
510
520
550
VIN ≤ VIL or VIN ≥ VIH, -E33Y
510
530
550
II/O = 0 mA,
-E35Y
500
520
540
Cycle = MAX.
-E40Y
490
500
520
Inputs static
-E50Y
460
470
490
Note1
VOL(Low) IOL ≤ 0.1 mA
VOL
Notes 1.
2.
3.
4.
570
VOH(Low) |IOH| ≤ 0.1 mA
VOH
Output LOW voltage
VIN ≤ VIL or VIN ≥ VIH, -E33Y
Note2
mA
mA
VDDQ−0.2
VDDQ
V
3, 4
VDDQ/2−0.12
VDDQ/2+0.12
V
3, 4
VSS
0.2
V
3, 4
VDDQ/2−0.12
VDDQ/2+0.12
V
3, 4
Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
AC load current is higher than the shown DC values.
HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 16 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Capacitance (TA = 25°C, f = 1 MHz)
Parameter
Input capacitance
Symbol
Test conditions
MIN.
MAX.
Unit
CIN
VIN = 0 V
5
pF
CI/O
VI/O = 0 V
7
pF
Cclk
Vclk = 0 V
6
pF
(Address, Control)
Input / Output capacitance
(DQ, CQ, CQ#)
Clock Input capacitance
Remark These parameters are periodically sampled and not 100% tested.
Thermal Characteristics
Parameter
Thermal resistance
Symbol
θ ja
Substrate
4-layer
from junction to ambient air
8-layer
Thermal characterization parameter
Ψ jt
4-layer
from junction to the top center
of the package surface
Thermal resistance
8-layer
θ jc
Airflow
TYP.
Unit
0 m/s
21.2
°C/W
1 m/s
13.4
°C/W
0 m/s
20.2
°C/W
1 m/s
13.0
°C/W
0 m/s
0.02
°C/W
1 m/s
0.06
°C/W
0 m/s
0.02
°C/W
1 m/s
0.05
°C/W
2.58
°C/W
from junction to case
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 17 of 36
μPD44324092B, μPD44324182B, μPD44324362B
AC Characteristics (TA = 0 to 70°C or TA = −40 to 85°C, VDD = 1.8 ± 0.1 V)
AC Test Conditions (VDD = 1.8 ± 0.1 V, VDDQ = 1.4 V to VDD)
Input waveform (Rise / Fall time ≤ 0.3 ns)
1.25 V
0.75 V
Test Points
0.75 V
0.25 V
Output waveform
Test Points
VDDQ / 2
VDDQ / 2
Output load condition
Figure 1. External load at test
VDDQ / 2
0.75 V
50 Ω
VREF
ZO = 50 Ω
SRAM
250 Ω
ZQ
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 18 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Read and Write Cycle
Parameter
Symbol
-E33, E33Y
(300 MHz)
-E35, E35Y
(287 MHz)
-E40, E40Y
(250 MHz)
-E50, E50Y
(200 MHz)
Unit
Note
8.4
ns
1
0.2
2
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock
Average Clock cycle time
(K, K#, C, C#)
Clock phase jitter (K, K#, C, C#)
Clock HIGH time (K, K#, C, C#)
Clock LOW time (K, K#, C, C#)
Clock HIGH to Clock# HIGH
(K → K#, C → C#)
Clock# HIGH to Clock HIGH
(K# → K, C# → C)
Clock to data clock
(K → C, K# → C#)
PLL lock time (K, C)
K static to PLL reset
TKHKH
3.3
8.4
3.5
0.2
8.4
4.0
5.0
TKC var
TKHKL
TKLKH
TKHK#H
1.32
1.32
1.49
1.5
1.5
1.7
1.6
1.6
1.8
2.0
2.0
2.2
ns
ns
ns
ns
TK#HKH
1.49
1.7
1.8
2.2
ns
TKHCH
0
TKC lock
TKC reset
20
30
1.45
0.2
8.4
0
1.65
0.2
0
1.8
0
2.3
ns
20
30
20
30
20
30
μs
ns
3
4
TCQHCQ#H 1.24
1.35
1.55
1.95
ns
5
TCQ#HCQH 1.24
1.35
1.55
1.95
ns
5
Output Times
CQ HIGH to CQ# HIGH
(CQ → CQ#)
CQ# HIGH to CQ HIGH
(CQ# → CQ)
C, C# HIGH to output valid
C, C# HIGH to output hold
C, C# HIGH to echo clock valid
C, C# HIGH to echo clock hold
CQ, CQ# HIGH to output valid
CQ, CQ# HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
TCHQV
TCHQX
TCHCQV
TCHCQX
TCQHQV
TCQHQX
TCHQZ
TCHQX1
0.45
−0.45
−0.45
−0.45
−0.45
ns
ns
ns
ns
ns
ns
ns
ns
TAVKH
TIVKH
0.4
0.4
0.5
0.5
0.5
0.5
0.6
0.6
ns
ns
7
7
TDVKH
0.3
0.35
0.35
0.4
ns
7
TKHAX
TKHIX
0.4
0.4
0.5
0.5
0.5
0.5
0.6
0.6
ns
ns
7
7
TKHDX
0.3
0.35
0.35
0.4
ns
7
−0.45
0.45
−0.45
0.45
−0.45
0.45
−0.45
0.27
−0.27
0.45
−0.45
0.45
−0.45
0.3
−0.3
0.45
0.45
−0.45
0.45
−0.45
0.3
−0.3
0.45
0.35
−0.35
0.45
0.45
6
6
Setup Times
Address valid to K rising edge
Synchronous load input (LD#),
read write input (R, W#) valid to
K rising edge
Data inputs and write data
select inputs (BWx#) valid to
K, K# rising edge
Hold Times
K rising edge to address hold
K rising edge to
synchronous load input (LD#),
read write input (R, W#) hold
K, K# rising edge to data inputs
and write data select inputs
(BWx#) hold
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 19 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Notes 1.
When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock
cycle in this operation. The AC/DC characteristics cannot be guaranteed, however.
2.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
3.
VDD slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention.
PLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept NOP (LD# = HIGH) during these cycles.
4. K input is monitored for this operation. See below for the timing.
K
or
TKC reset
K
TKC reset
5. Guaranteed by design.
6. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
7. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold
times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5. VDDQ is 1.5 V DC.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 20 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Read and Write Timing
NOP
READ
(burst of 2)
1
2
NOP
READ
(burst of 2)
3
READ
WRITE
WRITE
(burst of 2) (burst of 2) (burst of 2)
NOP
4
5
6
7
8
A2
A3
A4
9
10
TKHKH
K
TKHKL TKLKH
TKHK#H
TK#HKH
K#
LD#
TIVKH
TKHIX
R, W#
TAVKH TKHAX
A0
Address
A1
TKHDX
TKHDX
TDVKH
TDVKH
DQ
Qx2
Q00
TCHQX1
TKHCH
TKHCH
Q01
Q10
D20
Q11
D21
D30
D31
Q40
Q41
TCQHQX
TCHQX
TCHQZ
TCHQV
TCHQV
TCQHQV
TCHQX
CQ
TCHCQX
TCHCQV
TCQHCQ#H TCQ#HCQH
CQ#
TCHCQX
TCHCQV
C
TKHKL TKLKH TKHKH TKHK#H TK#HKH
C#
Remarks 1. Q01 refers to output from address A0.
Q02 refers to output from the next internal burst address following A0, etc.
2. Outputs are disabled (high impedance) 2.5 clock cycles after the last READ (LD# = LOW, R, W# =
HIGH) is input in the sequences of [READ]-[NOP].
3. The second NOP cycle at the cycle “5” is not necessary for correct device operation;
however, at high clock frequencies it may be required to prevent bus contention.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 21 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Application Example
SRAM#1
ZQ
CQ#
CQ
DQ
SRAM
Controller
Vt
A
R=
250 Ω
...
SRAM#4
ZQ
CQ#
CQ
R=
250 Ω
DQ
LD# R, W# BWx# C/C# K/K#
A
LD# R, W# BWx# C/C# K/K#
R
Data IO
Address
R
LD#
Vt
R, W#
BW#
...
SRAM#1 CQ/CQ#
SRAM#4 CQ/CQ#
Vt
R
Vt
R
Source CLK/CLK#
Return CLK/CLK#
Vt
R
R = 50 Ω Vt = Vref
Remark AC Characteristics are defined at the condition of SRAM outputs, CQ, CQ# and DQ with termination.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 22 of 36
μPD44324092B, μPD44324182B, μPD44324362B
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
Pin assignments
Description
TCK
2R
TMS
10R
TDI
11R
Test Data Input. This is the input side of the serial registers placed between
TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP controller state machine and the instruction that is currently
loaded in the TAP instruction.
TDO
1R
Test Data Output. This is the output side of the serial registers placed between
TDI and TDO. Output changes in response to the falling edge of TCK.
Test Clock Input. All input are captured on the rising edge of TCK and all
outputs propagate from the falling edge of TCK.
Test Mode Select. This is the command input for the TAP controller state
machine.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
JTAG Input leakage current
ILI
0 V ≤ VIN ≤ VDD
−5.0
+5.0
μA
JTAG I/O leakage current
ILO
0 V ≤ VIN ≤ VDDQ,
−5.0
+5.0
μA
Outputs disabled
JTAG input HIGH voltage
VIH
1.3
VDD+0.3
V
JTAG input LOW voltage
VIL
−0.3
+0.5
V
JTAG output HIGH voltage
JTAG output LOW voltage
R10DS0036EJ0200 Rev.2.00
August 2, 2011
VOH1
| IOHC | = 100 μA
1.6
V
VOH2
| IOHT | = 2 mA
1.4
V
VOL1
IOLC = 100 μA
0.2
V
VOL2
IOLT = 2 mA
0.4
V
Page 23 of 36
μPD44324092B, μPD44324182B, μPD44324362B
JTAG AC Test Conditions
Input waveform (Rise / Fall time ≤ 1 ns)
1.8 V
0.9 V
Test Points
0.9 V
0.9 V
Test Points
0.9 V
0V
Output waveform
Output load
Figure 2. External load at test
VTT = 0.9 V
50 Ω
ZO = 50 Ω
TDO
20 pF
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 24 of 36
μPD44324092B, μPD44324182B, μPD44324362B
JTAG AC Characteristics (TA = 0 to 70°C)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Clock
Clock cycle time
tTHTH
50
ns
Clock frequency
fTF
Clock HIGH time
tTHTL
20
ns
Clock LOW time
tTLTH
20
ns
TCK LOW to TDO unknown
tTLOX
0
TCK LOW to TDO valid
tTLOV
20
MHz
Output time
ns
10
ns
Setup time
TMS setup time
tMVTH
5
ns
TDI valid to TCK HIGH
tDVTH
5
ns
tCS
5
ns
TMS hold time
tTHMX
5
ns
TCK HIGH to TDI invalid
tTHDX
5
ns
tCH
5
ns
Capture setup time
Hold time
Capture hold time
JTAG Timing Diagram
tTHTH
TCK
tMVTH
tTHTL
tTLTH
TMS
tTHMX
tDVTH
TDI
tTHDX
tTLOX
tTLOV
TDO
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 25 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller
when it is moved into the run-test/idle or the various data register state. The register can
be loaded when it is placed between the TDI and TDO pins. The instruction register is
automatically preloaded with the IDCODE instruction at power-up whenever the controller
is placed in test-logic-reset state.
Bypass register
The bypass register is a single bit register that can be placed between TDI and TDO. It
allows serial test data to be passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
ID register
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit
code when the controller is put in capture-DR state with the IDCODE command loaded in
the instruction register. The register is then placed between the TDI and TDO pins when
the controller is moved into shift-DR state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents
of the RAMs I/O ring when the controller is in capture-DR state and then is placed
between the TDI and TDO pins when the controller is moved to shift-DR state. Several
TAP instructions can be used to activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary
register location. The first column defines the bit’s position in the boundary register. The
second column is the name of the input or I/O at the bump and the third column is the
bump number.
Scan Register Definition (2)
Register name
Bit size
Unit
Instruction register
3
bit
Bypass register
1
bit
ID register
32
bit
Boundary register
109
bit
ID Register Definition
Part number
Organization
ID [31:28] vendor
revision no.
ID [27:12] part no.
ID [11:1] vendor
ID no.
ID [0] fix bit
μPD44324092B
4M x 9
XXXX
0000 0000 0011 1110
00000010000
1
μPD44324182B
2M x 18
XXXX
0000 0000 0011 1111
00000010000
1
μPD44324362B
1M x 36
XXXX
0000 0000 0100 0000
00000010000
1
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 26 of 36
μPD44324092B, μPD44324182B, μPD44324362B
SCAN Exit Order
Bit
no.
Signal name
x9
x18
x36
Bump
Bit
ID
no.
Signal name
x9
x18
x36
Bump
Bit
ID
no.
Signal name
x9
x18
x36
Bump
ID
1
C#
6R
37
NC
10D
73
NC
2C
2
C
6P
38
NC
9E
74
DQ5 DQ11 DQ20
3E
3
A
6N
39
NC
DQ7 DQ17 10C
75
NC
2D
4
A
7P
40
NC
NC DQ16 11D
76
NC
2E
5
A
7N
41
NC
9C
77
NC
1E
6
A
7R
42
NC
9D
78
NC
7
A
8R
43
DQ4 DQ8 DQ8
11B
79
NC
8
A
8P
44
11C
80
NC
1G
9
A
9R
45
NC
9B
81
NC
1F
10
DQ0
11P
46
NC
10B
82
DQ6 DQ13 DQ22
3G
10P
47
CQ
11A
83
10A
84
DLL#
1H
11
NC
NC
DQ9
NC
A
NC
A
DQ7
VSS
NC
NC
DQ29
DQ12 DQ30
NC
NC
DQ21
DQ31
2F
3F
2G
12
NC
10N
48
13
NC
9P
49
A
9A
85
NC
1J
NC
2J
14
NC
DQ1 DQ11 10M
50
A
8B
86
15
NC
NC DQ10 11N
51
A
7C
87
NC
16
NC
9M
52
6C
88
NC
17
NC
9N
53
LD#
8A
89
NC
2K
18
DQ1 DQ2 DQ2
11L
54
NC BW1#
7A
90
NC
1K
DQ1 11M
55
BW0#
7B
91
DQ7 DQ15 DQ33
2L
19
NC
NC
A
NC
A0
A0
NC
9L
56
K
6B
92
21
NC
10L
57
K#
6A
93
NC
1M
11K
58
NC
NC BW3#
5B
94
NC
1L
NC DQ12 10K
59
NC BW1# BW2#
5A
95
NC
24
NC
9J
60
R, W#
4A
96
NC
25
NC
9K
61
A
5C
97
NC
1N
DQ2 DQ4 DQ13 10J
62
A
4B
98
NC
2M
11J
63
A
3A
99
DQ8 DQ17 DQ26
3P
23
NC
26
27
NC
DQ3 DQ3
NC
DQ4
DQ16 DQ25
NC
3M
11H
64
VSS
2A
100
29
NC
10G
65
CQ#
1A
101
NC
2P
30
NC
9G
66
NC
DQ9 DQ27
2B
102
NC
1P
11F
67
NC
NC DQ18
3B
103
A
3R
NC DQ14 11G
68
NC
1C
104
A
4R
33
NC
9F
69
NC
1B
105
A
4P
34
NC
10F
70
NC DQ10 DQ19
3D
106
A
5P
35
DQ3 DQ6 DQ6
11E
71
NC
NC DQ28
3C
107
A
5N
NC DQ15 10E
72
NC
1D
108
A
5R
109
–
Internal
32
NC
36
NC
DQ5 DQ5
DQ35
3N
ZQ
NC
NC
DQ34
3L
28
31
NC
DQ24
3J
NC
NC
NC
DQ32
3K
20
22
NC
DQ14 DQ23
2N
Remark Bump ID 10A of bit no. 48 can also be used as NC if the product is x36.
Bump ID 2A of bit no. 64 can also be used as NC.
The register always indicates LOW, however.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 27 of 36
μPD44324092B, μPD44324182B, μPD44324362B
JTAG Instructions
Instructions
Description
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested.
Boundary-scan register cells at output pins are used to apply test vectors, while those at
input pins capture test results. Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary scan register using the PRELOAD
instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on and
the PRELOAD data is driven onto the output pins.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the
controller is in capture-DR mode and places the ID register between the TDI and TDO pins
in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up
and any time the controller is placed in the test-logic-reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction register, the bypass register is
placed between TDI and TDO. This occurs when the TAP controller is moved to the shiftDR state. This allows the board level scan path to be shortened to facilitate testing of other
devices in the scan path.
SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the
SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP
controller into the capture-DR state loads the data in the RAMs input and DQ pins into the
boundary scan register. Because the RAM clock(s) are independent from the TAP clock
(TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample
metastable input will not harm the device, repeatable results cannot be expected. RAM
input signals must be stabilized for long enough to meet the TAPs input data capture setup
plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other
TAP operation except capturing the I/O ring contents into the boundary scan register.
Moving the controller to shift-DR state then places the boundary scan register between the
TDI and TDO pins.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM DQ pins are
forced to an inactive drive state (high impedance) and the boundary register is connected
between TDI and TDO when the TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2
IR1
IR0
Instruction
0
0
0
EXTEST
Note
0
0
1
IDCODE
0
1
0
SAMPLE-Z
1
0
1
1
RESERVED
2
1
0
0
SAMPLE / PRELOAD
1
0
1
RESERVED
2
1
1
0
RESERVED
2
1
1
1
BYPASS
Notes 1. TRISTATE all DQ pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
2. Do not use this instruction code because the vendor uses it to evaluate this product.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 28 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Output Pin States of CQ, CQ# and DQ
Instructions
Control-Register Status
Output Pin Status
CQ,CQ#
DQ
0
Update
High-Z
1
Update
Update
0
SRAM
SRAM
1
SRAM
SRAM
SAMPLE-Z
0
High-Z
High-Z
1
High-Z
High-Z
SAMPLE
0
SRAM
SRAM
1
SRAM
SRAM
0
SRAM
SRAM
1
SRAM
SRAM
EXTEST
IDCODE
BYPASS
Remark The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Boundary Scan
Register
Register, bit no. 109).
CAPTURE
Register
There are three statuses:
Update : Contents of the “Update Register” are output to the
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (DDR Pad).
SRAM
Output
Update
Register
output pin (DDR Pad).
Update
High-Z :The output pin (DDR Pad) becomes high
impedance by controlling of the “High-Z JTAG
ctrl”.
The Control-Register status is set during Update-DR at the
DDR
Pad
SRAM
High-Z
SRAM
Output
Driver
EXTEST or SAMPLE instruction.
High-Z
JTAG ctrl
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 29 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Boundary Scan Register Status of Output Pins CQ, CQ# and DQ
Instructions
SRAM Status
Boundary Scan Register Status
CQ,CQ#
DQ
READ (Low-Z)
Pad
Pad
NOP (High-Z)
Pad
Pad
READ (Low-Z)
−
−
NOP (High-Z)
−
−
SAMPLE-Z
READ (Low-Z)
Pad
Pad
NOP (High-Z)
Pad
Pad
SAMPLE
READ (Low-Z)
Internal
Internal
NOP (High-Z)
Internal
Pad
READ (Low-Z)
−
−
NOP (High-Z)
−
−
EXTEST
IDCODE
BYPASS
Remark The Boundary Scan Register statuses during execution each
Note
No definition
No definition
Boundary Scan
Register
instruction vary according to the instruction code and SRAM
operation mode.
CAPTURE
Register
There are two statuses:
Internal
Pad
: Contents of the output pin (DDR Pad) are captured
in the “CAPTURE Register” in the Boundary Scan
Update
Register
Pad
SRAM
Output
Register.
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
DDR
Pad
SRAM
Output
Driver
High-Z
JTAG ctrl
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 30 of 36
μPD44324092B, μPD44324182B, μPD44324362B
TAP Controller State Diagram
1
Test-Logic-Reset
0
1
0
1
1
Select-IR-Scan
Select-DR-Scan
Run-Test / Idle
0
0
1
1
Capture-IR
Capture-DR
0
0
0
Shift-DR
0
Shift-IR
1
1
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
0
Pause-IR
1
1
0
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
Update-IR
0
1
0
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open
but fix them to VDD via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected
also when the TAP controller is not used.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 31 of 36
New Instruction
μPD44324092B, μPD44324182B, μPD44324362B
Run-Test/Idle
Update-IR
Exit1-IR
Shift-IR
Exit2-IR
IDCODE
Pause-IR
Exit1-IR
Shift-IR
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Select-IR-Scan
Run-Test/Idle
Instruction
Register state
TDI
Controller
state
TMS
Test-Logic-Reset
TDO
Output Inactive
Select-DR-Scan
TCK
Test Logic Operation (Instruction Scan)
Capture-IR
Page 32 of 36
IDCODE
μPD44324092B, μPD44324182B, μPD44324362B
Test-Logic-Reset
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Update-DR
Exit1-DR
Shift-DR
Instruction
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Instruction
Register state
TDI
Controller
state
TMS
TCK
Test Logic (Data Scan)
Run-Test/Idle
TDO
Output Inactive
Select-DR-Scan
Page 33 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Package Dimensions
165-PIN PLASTIC BGA(15x17)
w S B
E
ZD
ZE
B
11
10
9
8
7
6
5
4
3
2
1
A
D
R P N M L K J H G F E D C B A
INDEX MARK
w S A
A
y1
(UNIT:mm)
A2
S
S
y
e
S
b
x
A1
M
S AB
ITEM
D
DIMENSIONS
15.00±0.10
E
17.00±0.10
w
0.30
A
1.35±0.11
A1
0.37±0.05
A2
0.98
e
1.00
b
+0.10
0.50 0.05
x
0.10
y
0.15
y1
0.25
ZD
2.50
ZE
1.50
P165F5-100-FQ1-1
Renesas El ectronics Corporation 2010
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 34 of 36
μPD44324092B, μPD44324182B, μPD44324362B
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products.
Types of Surface Mount Devices
μPD44324092BF5-FQ1 : 165-pin PLASTIC BGA (15 x 17)
μPD44324182BF5-FQ1 : 165-pin PLASTIC BGA (15 x 17)
μPD44324362BF5-FQ1 : 165-pin PLASTIC BGA (15 x 17)
Quality Grade
• A quality grade of the products is “Standard”.
• Anti-radioactive design is not implemented in the products.
• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to
the ground and so forth.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 35 of 36
Revision History
Rev.
Date
1st edition
2nd edition
’08.03.01
’10.03.01
Rev.1.00
Rev.2.00
’10.09.10
’11.08.02
μPD44324092B, μPD44324182B, μPD44324362B
Description
Page
P14
P15
Throughout
Throughout
Summary
New Preliminary Data Sheet
DC Characteristics (Modification, Spec of IDD and ISB1)
Thermal Characteristics (Modification, Spec)
Preliminary Data Sheet → Data Sheet
Add Lead and the extended temperature operation product
All trademarks and registered trademarks are the property of their respective owners.
C - 36
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