User’s Manual
32
V850ES/JG3-H, V850ES/JH3-H
User’s Manual: Hardware
RENESAS MCU
V850ES/Jx3-H Microcontrollers
V850ES/JG3-H
V850ES/JH3-H
μPD70F3760
μPD70F3765
μPD70F3761
μPD70F3766
μPD70F3762
μPD70F3767
μPD70F3770
μPD70F3771
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.5.10
Mar, 2014
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of
third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No
license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of
Renesas Electronics or others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration,
modification, copy or otherwise misappropriation of Renesas Electronics product.
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human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property
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6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(2012.4)
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
How to Use This Manual
Readers
This manual is intended for users who wish to understand the functions of the
V850ES/JG3-H and V850ES/JH3-H and design application systems using the
V850ES/JG3-H and V850ES/JH3-H.
Purpose
This manual is intended to give users an understanding of the hardware functions of the
V850ES/JG3-H and V850ES/JH3-H shown in the Organization below.
Organization
The manual of these products is divided into two volumes: Hardware (this volume) and
Architecture (V850ES Architecture User’s Manual).
Hardware
How to Read This Manual
Architecture
• Pin functions
• Data types
• CPU function
• Register set
• On-chip peripheral functions
• Instruction format and instruction set
• Flash memory programming
• Interrupts and exceptions
• Electrical specifications
• Pipeline operation
It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To understand the overall functions of the V850ES/JG3-H and V850ES/JH3-H
→ Read this manual according to the CONTENTS.
To find the details of a register where the name is known
→ Use APPENDIX C REGISTER INDEX.
Register format
→ The name of the bit whose number is in angle brackets () in the figure of the register
format of each register is defined as a reserved word in the device file.
To understand the details of an instruction function
→ Refer to the V850ES Architecture User’s Manual available separately.
To know the electrical specifications of the V850ES/JG3-H and V850ES/JH3-H
→ Refer to the CHAPTER 33 ELECTRICAL SPECIFICATIONS.
The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note with
caution that if “xxx.yyy” is described as is in a program, however, the compiler/assembler
cannot recognize it correctly.
The mark shows major revised points. The revised points can be easily searched
by copying an “” in the PDF file and specifying it in the “Find what: ” field.
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representation:
xxx (overscore over pin or signal name)
Memory map address:
Higher addresses on the top and lower addresses on the
Note:
Footnote for item marked with Note in the text
bottom
Caution:
Information requiring particular attention
Remark:
Supplementary information
Numeric representation:
Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Prefix indicating power of 2
(address space, memory
capacity):
K (kilo): 210 = 1,024
M (mega): 220 = 1,0242
G (giga): 230 = 1,0243
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
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Document No.
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U15943E
V850ES/JG3-H, V850ES/JH3-H Hardware User’s Manual
This manual
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IECUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany.
MINICUBE is a registered trademark of Renesas Electronics Corporation in Japan and Germany or a trademark in
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Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United
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PC/AT is a trademark of International Business Machines Corporation.
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Table of Contents
CHAPTER 1 INTRODUCTION................................................................................................................. 19
1.1 General ...................................................................................................................................... 19
1.2 Features .................................................................................................................................... 22
1.3 Application Fields .................................................................................................................... 24
1.4 Ordering Information ............................................................................................................... 24
1.5 Pin Configuration (Top View).................................................................................................. 25
1.6 Function Block Configuration................................................................................................. 28
1.6.1 Internal block diagram.....................................................................................................................28
1.6.2 Internal units ...................................................................................................................................30
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 33
2.1 List of Pin Functions................................................................................................................ 33
2.2 Pin States .................................................................................................................................. 47
2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins.......... 48
2.4 Cautions .................................................................................................................................... 53
CHAPTER 3 CPU FUNCTION ................................................................................................................ 54
3.1 Features .................................................................................................................................... 54
3.2 CPU Register Set...................................................................................................................... 55
3.2.1 Program register set .......................................................................................................................56
3.2.2 System register set .........................................................................................................................57
3.3
Operation Modes ...................................................................................................................... 63
3.3.1 Specifying operation mode..............................................................................................................63
3.4
Address Space ......................................................................................................................... 64
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
CPU address space ........................................................................................................................64
Wraparound of CPU address space ...............................................................................................65
Memory map ...................................................................................................................................66
Areas ..............................................................................................................................................68
Recommended use of address space.............................................................................................74
Peripheral I/O registers ...................................................................................................................77
Programmable peripheral I/O registers ...........................................................................................91
Special registers .............................................................................................................................92
Cautions..........................................................................................................................................96
CHAPTER 4 PORT FUNCTIONS ......................................................................................................... 100
4.1 Features .................................................................................................................................. 100
4.2 Basic Port Configuration....................................................................................................... 100
4.3 Port Configuration ................................................................................................................. 102
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
4.3.13
4.3.14
4.4
4.5
Port 0 ............................................................................................................................................108
Port 1 ............................................................................................................................................113
Port 2 (V850ES/JH3-H only) .........................................................................................................114
Port 3 ............................................................................................................................................118
Port 4 ............................................................................................................................................123
Port 5 ............................................................................................................................................126
Port 6 ............................................................................................................................................133
Port 7 ............................................................................................................................................137
Port 9 ............................................................................................................................................139
Port CM.........................................................................................................................................149
Port CS (V850ES/JH3-H only) ......................................................................................................152
Port CT .........................................................................................................................................154
Port DH (V850ES/JH3-H only) ......................................................................................................157
Port DL..........................................................................................................................................159
Port Register Settings When Alternate Function Is Used.................................................. 161
Cautions .................................................................................................................................. 172
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
Cautions on setting port pins.........................................................................................................172
Cautions on bit manipulation instruction for port n register (Pn)....................................................175
Cautions on on-chip debug pins (V850ES/JG3-H only) ................................................................176
Cautions on P56/INTP05/DRST pin..............................................................................................176
Cautions on P10, P11, and P53 pins when power is turned on ....................................................176
Hysteresis characteristics .............................................................................................................176
CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 177
5.1 Features .................................................................................................................................. 177
5.2 Bus Control Pins .................................................................................................................... 178
5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed ....................179
5.2.2 Pin status in each operation mode................................................................................................179
5.3
5.4
Memory Block Function ........................................................................................................ 180
Bus Access ............................................................................................................................. 181
5.4.1 Number of clocks for access .........................................................................................................181
5.4.2 Bus size setting function ...............................................................................................................181
5.4.3 Access by bus size .......................................................................................................................182
5.5
Wait Function.......................................................................................................................... 189
5.5.1
5.5.2
5.5.3
5.5.4
5.6
5.7
Programmable wait function..........................................................................................................189
External wait function....................................................................................................................190
Relationship between programmable wait and external wait.........................................................191
Programmable address wait function ............................................................................................192
Idle State Insertion Function................................................................................................. 193
Bus Hold Function (V850ES/JH3-H only)............................................................................. 194
5.7.1 Functional outline..........................................................................................................................194
5.7.2 Bus hold procedure.......................................................................................................................195
5.7.3 Operation in power save mode .....................................................................................................195
5.8
5.9
Bus Priority ............................................................................................................................. 196
Bus Timing.............................................................................................................................. 197
CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 200
6.1 Overview ................................................................................................................................. 200
6.2 Configuration.......................................................................................................................... 201
6.3 Registers ................................................................................................................................. 203
6.4 Operation ................................................................................................................................ 208
6.4.1 Operation of each clock ................................................................................................................208
6.4.2 Clock output function ....................................................................................................................208
6.5
PLL Function .......................................................................................................................... 209
6.5.1 Overview .......................................................................................................................................209
6.5.2 Registers.......................................................................................................................................209
6.5.3 Usage ...........................................................................................................................................212
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA).............................................................. 213
7.1 Overview ................................................................................................................................. 213
7.2 Functions ................................................................................................................................ 213
7.3 Configuration.......................................................................................................................... 214
7.3.1 Pin configuration ...........................................................................................................................216
7.4
7.5
Registers ................................................................................................................................. 217
Operation ................................................................................................................................ 234
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.6
Interval timer mode (TAAmMD2 to TAAmMD0 bits = 000) ...........................................................240
External event count mode (TAAnMD2 to TAAnMD0 bits = 001)..................................................250
External trigger pulse output mode (TAAnMD2 to TAAnMD0 bits = 010) .....................................258
One-shot pulse output mode (TAAnMD2 to TAAnMD0 bits = 011) ...............................................270
PWM output mode (TAAnMD2 to TAAnMD0 bits = 100) ..............................................................277
Free-running timer mode (TAAnMD2 to TAAnMD0 bits = 101).....................................................286
Pulse width measurement mode (TAAnMD2 to TAAnMD0 bits = 110) .........................................303
Timer output operations ................................................................................................................308
Timer-Tuned Operation Function ......................................................................................... 309
7.6.1 Free-running timer mode (during timer-tuned operation) ..............................................................311
7.6.2 PWM output mode (during timer-tuned operation) ........................................................................318
7.7
Simultaneous-Start Function ................................................................................................ 320
7.7.1 PWM output mode (simultaneous-start operation) ........................................................................321
7.8 Cascade Connection.............................................................................................................. 323
7.9 Selector Function ................................................................................................................... 328
7.10 Cautions .................................................................................................................................. 329
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB).............................................................. 330
8.1 Overview ................................................................................................................................. 330
8.2 Functions ................................................................................................................................ 330
8.3 Configuration.......................................................................................................................... 331
8.4 Registers ................................................................................................................................. 334
8.5 Operation ................................................................................................................................ 351
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
8.6
8.7
Interval timer mode (TABnMD2 to TABnMD0 bits = 000) .............................................................352
External event count mode (TABnMD2 to TABnMD0 bits = 001)..................................................361
External trigger pulse output mode (TABnMD2 to TABnMD0 bits = 010) .....................................370
One-shot pulse output mode (TABnMD2 to TABnMD0 bits = 011) ...............................................383
PWM output mode (TABnMD2 to TABnMD0 bits = 100) ..............................................................392
Free-running timer mode (TABnMD2 to TABnMD0 bits = 101).....................................................403
Pulse width measurement mode (TABnMD2 to TABnMD0 bits = 110) .........................................423
Triangular wave PWM mode (TABnMD2 to TABnMD0 bits = 111) ...............................................429
Timer output operations ................................................................................................................431
Timer-Tuned Operation Function/Simultaneous-Start Function ...................................... 432
Cautions .................................................................................................................................. 433
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT) ................................................................. 434
9.1 Overview ................................................................................................................................. 434
9.2 Functions ................................................................................................................................ 434
9.3 Configuration.......................................................................................................................... 435
9.3.1 Pin configuration ...........................................................................................................................438
9.4
9.5
9.6
Registers ................................................................................................................................. 439
Timer Output Operations....................................................................................................... 460
Operation ................................................................................................................................ 461
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
9.6.6
9.6.7
9.6.8
9.6.9
9.6.10
Interval timer mode (TT0MD3 to TT0MD0 bits = 0000).................................................................469
External event count mode (TT0MD3 to TT0MD0 bits = 0001).....................................................479
External trigger pulse output mode (TT0MD3 to TT0MD0 bits = 0010).........................................489
One-shot pulse output mode (TT0MD3 to TT0MD0 bits = 0011) ..................................................502
PWM output mode (TT0MD3 to TT0MD0 bits = 0100)..................................................................509
Free-running timer mode (TT0MD3 to TT0MD0 bits = 0101) ........................................................518
Pulse width measurement mode (TT0MD3 to TT0MD0 bits = 0110) ............................................534
Triangular-wave PWM output mode (TT0MD3 to TT0MD0 bits = 0111) .......................................540
Encoder count function .................................................................................................................542
Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000) .........................................................558
CHAPTER 10 16-BIT INTERVAL TIMER M (TMM) .......................................................................... 566
10.1 Overview ................................................................................................................................. 566
10.2 Configuration.......................................................................................................................... 567
10.3 Registers ................................................................................................................................. 569
10.4 Operation ................................................................................................................................ 571
10.4.1 Interval timer mode .......................................................................................................................571
10.4.2 Cautions........................................................................................................................................575
CHAPTER 11 MOTOR CONTROL FUNCTION .................................................................................. 576
11.1 Functional Overview .............................................................................................................. 576
11.2 Configuration.......................................................................................................................... 577
11.3 Control Registers ................................................................................................................... 581
11.4 Operation ................................................................................................................................ 591
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.4.6
System outline ..............................................................................................................................591
Dead-time control (generation of negative-phase wave signal).....................................................596
Interrupt culling function ................................................................................................................603
Operation to rewrite register with transfer function........................................................................610
TAA4 tuning operation for A/D conversion start trigger signal output............................................628
A/D conversion start trigger output function ..................................................................................631
CHAPTER 12 REAL-TIME COUNTER................................................................................................. 636
12.1 Functions ................................................................................................................................ 636
12.2 Configuration.......................................................................................................................... 637
12.2.1 Pin configuration ...........................................................................................................................639
12.2.2 Interrupt functions .........................................................................................................................639
12.3 Registers ................................................................................................................................. 640
12.4 Operation ................................................................................................................................ 655
12.4.1
12.4.2
12.4.3
12.4.4
12.4.5
12.4.6
12.4.7
12.4.8
12.4.9
Initial settings ................................................................................................................................655
Rewriting each counter during the real-time counter operation .....................................................656
Reading each counter during the real-time counter operation.......................................................657
Changing INTRTC0 interrupt setting during the real-time counter operation ................................658
Changing INTRTC1 interrupt setting during the real-time counter operation ................................659
Initial INTRTC2 interrupt settings ..................................................................................................660
Changing INTRTC2 interrupt setting during the real-time counter operation ................................661
Initializing real-time counter ..........................................................................................................662
Watch error correction example of real-time counter ....................................................................663
CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2 ................................................................... 667
13.1 Functions ................................................................................................................................ 667
13.2 Configuration.......................................................................................................................... 668
13.3 Registers ................................................................................................................................. 669
13.4 Operation ................................................................................................................................ 671
CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO)................................................................... 672
14.1 Function .................................................................................................................................. 672
14.2 Configuration.......................................................................................................................... 673
14.3 Registers ................................................................................................................................. 675
14.4 Operation ................................................................................................................................ 677
14.5 Usage....................................................................................................................................... 678
14.6 Cautions .................................................................................................................................. 678
CHAPTER 15 A/D CONVERTER ......................................................................................................... 679
15.1 Overview ................................................................................................................................. 679
15.2 Functions ................................................................................................................................ 679
15.3 Configuration.......................................................................................................................... 680
15.4 Registers ................................................................................................................................. 683
15.5 Operation ................................................................................................................................ 694
15.5.1
15.5.2
15.5.3
15.5.4
15.5.5
Basic operation .............................................................................................................................694
Conversion operation timing .........................................................................................................695
Trigger mode.................................................................................................................................696
Operation mode ............................................................................................................................698
Power-fail compare mode .............................................................................................................702
15.6 Cautions .................................................................................................................................. 707
15.7 How to Read A/D Converter Characteristics Table ............................................................ 711
CHAPTER 16 D/A CONVERTER ......................................................................................................... 715
16.1 Functions ................................................................................................................................ 715
16.2 Configuration.......................................................................................................................... 715
16.3 Registers ................................................................................................................................. 716
16.4 Operation ................................................................................................................................ 718
16.4.1 Operation in normal mode.............................................................................................................718
16.4.2 Operation in real-time output mode...............................................................................................718
16.4.3 Cautions........................................................................................................................................719
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) ............................................. 720
17.1 Features .................................................................................................................................. 720
17.2 Configuration.......................................................................................................................... 721
17.3 Mode Switching Between UARTC and Other Serial Interfaces ......................................... 723
17.3.1
17.3.2
17.3.3
17.3.4
17.3.5
Mode switching between UARTC0 and CSIF4 .............................................................................723
Mode switching between UARTC1 and I2C02 ...............................................................................724
Mode switching between UARTC2 and CSIF3 .............................................................................725
Mode switching between UARTC3, I2C00 and CAN0....................................................................726
Mode switching between UARTC4, CSIF0, and I2C01 ..................................................................727
17.4 Registers ................................................................................................................................. 728
17.5 Interrupt Request Signals ..................................................................................................... 738
17.6 Operation ................................................................................................................................ 739
17.6.1 Data format ...................................................................................................................................739
17.6.2 SBF transmission/reception format ...............................................................................................741
17.6.3 SBF transmission..........................................................................................................................743
17.6.4 SBF reception ...............................................................................................................................744
17.6.5 UART transmission .......................................................................................................................745
17.6.6 Continuous transmission procedure..............................................................................................746
17.6.7 UART reception ............................................................................................................................748
17.6.8 Reception errors ...........................................................................................................................749
17.6.9 Parity types and operations...........................................................................................................751
17.6.10 Receive data noise filter ...........................................................................................................752
17.7 Dedicated Baud Rate Generator........................................................................................... 753
17.8 Cautions .................................................................................................................................. 761
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF) .................................................... 762
18.1 Mode Switching of CSIF and Other Serial Interfaces ......................................................... 762
18.1.1 CSIF4 and UARTC0 mode switching ............................................................................................762
18.1.2 CSIF0, UARTC4, and I2C01 mode switching ................................................................................763
18.1.3 CSIF3 and UARTC2 mode switching ............................................................................................764
18.2
18.3
18.4
18.5
18.6
Features .................................................................................................................................. 765
Configuration.......................................................................................................................... 766
Registers ................................................................................................................................. 769
Interrupt Request Signals ..................................................................................................... 776
Operation ................................................................................................................................ 777
18.6.1 Single transfer mode (master mode, transmission mode).............................................................777
18.6.2 Single transfer mode (master mode, reception mode) ..................................................................779
18.6.3 Single transfer mode (master mode, transmission/reception mode) .............................................781
18.6.4 Single transfer mode (slave mode, transmission mode) ...............................................................783
18.6.5 Single transfer mode (slave mode, reception mode).....................................................................785
18.6.6 Single transfer mode (slave mode, transmission/reception mode)................................................787
18.6.7 Continuous transfer mode (master mode, transmission mode).....................................................789
18.6.8 Continuous transfer mode (master mode, reception mode) ..........................................................791
18.6.9 Continuous transfer mode (master mode, transmission/reception mode) .....................................794
18.6.10 Continuous transfer mode (slave mode, transmission mode) ..................................................798
18.6.11 Continuous transfer mode (slave mode, reception mode)........................................................800
18.6.12 Continuous transfer mode (slave mode, transmission/reception mode)...................................803
18.6.13 Reception error ........................................................................................................................807
18.6.14 Clock timing..............................................................................................................................808
18.7 Output Pins ............................................................................................................................. 810
18.8 Baud Rate Generator ............................................................................................................. 811
18.8.1 Baud rate generation ....................................................................................................................812
18.9 Cautions .................................................................................................................................. 813
CHAPTER 19 I2C BUS .......................................................................................................................... 814
19.1 Mode Switching of I2C Bus and Other Serial Interfaces..................................................... 814
19.1.1 UARTC3 and I2C00 mode switching .............................................................................................814
19.1.2 UARTC4, CSIF0, and I2C01 mode switching ................................................................................815
19.1.3 UARTC1 and I2C02 mode switching .............................................................................................816
19.2
19.3
19.4
19.5
Features .................................................................................................................................. 817
Configuration.......................................................................................................................... 818
Registers ................................................................................................................................. 822
I2C Bus Mode Functions ........................................................................................................ 837
19.5.1 Pin configuration ...........................................................................................................................837
19.6 I2C Bus Definitions and Control Methods ............................................................................ 838
19.6.1
19.6.2
19.6.3
19.6.4
19.6.5
19.6.6
19.6.7
Start condition ...............................................................................................................................838
Addresses .....................................................................................................................................839
Transfer direction specification .....................................................................................................840
ACK ..............................................................................................................................................841
Stop condition ...............................................................................................................................842
Wait state......................................................................................................................................843
Wait state cancellation method .....................................................................................................845
19.7 I2C Interrupt Request Signals (INTIICn)................................................................................ 846
19.7.1
19.7.2
19.7.3
19.7.4
19.7.5
19.7.6
Master device operation................................................................................................................846
Slave device operation (when receiving slave address data (address match)) .............................849
Slave device operation (when receiving extension code)..............................................................853
Operation without communication.................................................................................................857
Arbitration loss operation (operation as slave after arbitration loss)..............................................857
Operation when arbitration loss occurs (no communication after arbitration loss) ........................859
19.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control ........................ 866
19.9 Address Match Detection Method ........................................................................................ 868
19.10 Error Detection ....................................................................................................................... 868
19.11 Extension Code ...................................................................................................................... 868
19.12 Arbitration ............................................................................................................................... 869
19.13 Wakeup Function ................................................................................................................... 870
19.14 Communication Reservation ................................................................................................ 871
19.14.1
19.14.2
When communication reservation function is enabled (IICFn.IICRSVn bit = 0)........................871
When communication reservation function is disabled (IICFn.IICRSVn bit = 1) .......................875
19.15 Cautions .................................................................................................................................. 876
19.16 Communication Operations .................................................................................................. 877
19.16.1
19.16.2
19.16.3
Master operation in single master system ................................................................................878
Master operation in multimaster system...................................................................................879
Slave operation ........................................................................................................................882
19.17 Timing of Data Communication ............................................................................................ 885
CHAPTER 20 CAN CONTROLLER ..................................................................................................... 892
20.1 Overview ................................................................................................................................. 892
20.1.1 Features........................................................................................................................................892
20.1.2 Overview of functions....................................................................................................................893
20.1.3 Configuration.................................................................................................................................894
20.2 CAN Protocol .......................................................................................................................... 895
20.2.1
20.2.2
20.2.3
20.2.4
20.2.5
Frame format ................................................................................................................................895
Frame types ..................................................................................................................................896
Data frame and remote frame .......................................................................................................896
Error frame....................................................................................................................................904
Overload frame .............................................................................................................................905
20.3 Functions ................................................................................................................................ 906
20.3.1
20.3.2
20.3.3
20.3.4
20.3.5
20.3.6
Determining bus priority ................................................................................................................906
Bit stuffing .....................................................................................................................................906
Multi masters.................................................................................................................................906
Multi cast.......................................................................................................................................906
CAN sleep mode/CAN stop mode function ...................................................................................907
Error control function.....................................................................................................................907
20.3.7 Baud rate control function .............................................................................................................914
20.4 Connection with Target System ........................................................................................... 918
20.5 Internal Registers of CAN Controller ................................................................................... 919
20.5.1 CAN controller configuration .........................................................................................................919
20.5.2 Register access type.....................................................................................................................920
20.5.3 Register bit configuration ..............................................................................................................937
20.6 Registers ................................................................................................................................. 941
20.7 Bit Set/Clear Function............................................................................................................ 977
20.8 CAN Controller Initialization ................................................................................................. 979
20.8.1
20.8.2
20.8.3
20.8.4
20.8.5
Initialization of CAN module ..........................................................................................................979
Initialization of message buffer......................................................................................................979
Redefinition of message buffer .....................................................................................................979
Transition from initialization mode to operation mode ...................................................................980
Resetting error counter C0ERC of CAN module ...........................................................................981
20.9 Message Reception................................................................................................................ 982
20.9.1
20.9.2
20.9.3
20.9.4
20.9.5
20.9.6
Message reception........................................................................................................................982
Reading reception data .................................................................................................................983
Receive history list function...........................................................................................................984
Mask function................................................................................................................................986
Multi buffer receive block function.................................................................................................988
Remote frame reception................................................................................................................989
20.10 Message Transmission.......................................................................................................... 990
20.10.1
20.10.2
20.10.3
20.10.4
20.10.5
Message transmission..............................................................................................................990
Transmit history list function.....................................................................................................992
Automatic block transmission (ABT) ........................................................................................994
Transmission abort process .....................................................................................................996
Remote frame transmission .....................................................................................................997
20.11 Power Saving Modes ............................................................................................................. 998
20.11.1
20.11.2
20.11.3
CAN sleep mode ......................................................................................................................998
CAN stop mode......................................................................................................................1000
Example of using power saving modes ..................................................................................1001
20.12 Interrupt Function ................................................................................................................ 1002
20.13 Diagnosis Functions and Special Operational Modes ..................................................... 1003
20.13.1
20.13.2
20.13.3
20.13.4
Receive-only mode ................................................................................................................1003
Single-shot mode ...................................................................................................................1004
Self-test mode ........................................................................................................................1005
Transmission/reception operation in each operation mode ....................................................1006
20.14 Time Stamp Function........................................................................................................... 1007
20.14.1
Time stamp function...............................................................................................................1007
20.15 Baud Rate Settings .............................................................................................................. 1009
20.15.1
20.15.2
Bit rate setting conditions .......................................................................................................1009
Representative examples of baud rate settings .....................................................................1013
20.16 Operation of CAN Controller............................................................................................... 1017
CHAPTER 21 USB FUNCTION CONTROLLER (USBF) ................................................................ 1043
21.1 Overview ............................................................................................................................... 1043
21.2 Configuration........................................................................................................................ 1044
21.2.1 Block diagram .............................................................................................................................1044
21.2.2 USB memory map.......................................................................................................................1045
21.3 External Circuit Configuration ............................................................................................ 1046
21.3.1 Outline ........................................................................................................................................1046
21.3.2 Connection configuration ............................................................................................................1047
21.4 Cautions ................................................................................................................................ 1049
21.5 Requests ............................................................................................................................... 1050
21.5.1 Automatic requests .....................................................................................................................1050
21.5.2 Other requests ............................................................................................................................1057
21.6 Register Configuration ........................................................................................................ 1058
21.6.1 USB control registers ..................................................................................................................1058
21.6.2 USB function controller register list .............................................................................................1060
21.6.3 EPC control registers ..................................................................................................................1076
21.6.4 Data hold registers......................................................................................................................1128
21.6.5 EPC request data registers .........................................................................................................1151
21.6.6 Bridge register.............................................................................................................................1166
21.6.7 DMA register ...............................................................................................................................1170
21.6.8 Bulk-in register ............................................................................................................................1174
21.6.9 Bulk-out register..........................................................................................................................1175
21.6.10 Peripheral control registers ....................................................................................................1177
21.7 STALL Handshake or No Handshake................................................................................. 1181
21.8 Register Values in Specific Status ..................................................................................... 1182
21.9 FW Processing ..................................................................................................................... 1184
21.9.1
21.9.2
21.9.3
21.9.4
21.9.5
21.9.6
21.9.7
Initialization processing ...............................................................................................................1186
Interrupt servicing .......................................................................................................................1189
USB main processing .................................................................................................................1190
Suspend/Resume processing .....................................................................................................1216
Processing after power application .............................................................................................1219
Receiving data for bulk transfer (OUT) in DMA mode .................................................................1222
Transmitting data for bulk transfer (IN) in DMA mode.................................................................1227
CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) ................................................................. 1232
22.1 Features ................................................................................................................................ 1232
22.2 Configuration........................................................................................................................ 1233
22.3 Registers ............................................................................................................................... 1234
22.4 Transfer Targets................................................................................................................... 1243
22.5 Transfer Modes .................................................................................................................... 1243
22.6 Transfer Types ..................................................................................................................... 1244
22.7 DMA Channel Priorities ....................................................................................................... 1245
22.8 Time Related to DMA Transfer............................................................................................ 1245
22.9 DMA Transfer Start Factors ................................................................................................ 1246
22.10 DMA Abort Factors .............................................................................................................. 1247
22.11 End of DMA Transfer ........................................................................................................... 1247
22.12 Operation Timing.................................................................................................................. 1247
22.13 Cautions ................................................................................................................................ 1251
CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................. 1256
23.1 Features ................................................................................................................................ 1256
23.2 Non-Maskable Interrupts ..................................................................................................... 1267
23.2.1 Operation ....................................................................................................................................1269
23.2.2 Restore .......................................................................................................................................1270
23.2.3 NP flag ........................................................................................................................................1271
23.3 Maskable Interrupts ............................................................................................................. 1272
23.3.1
23.3.2
23.3.3
23.3.4
23.3.5
23.3.6
23.3.7
23.3.8
Operation ....................................................................................................................................1272
Restore .......................................................................................................................................1274
Priorities of maskable interrupts..................................................................................................1275
Interrupt control register (xxICn) .................................................................................................1279
Interrupt mask registers 0 to 5 (IMR0 to IMR5) ...........................................................................1283
In-service priority register (ISPR) ................................................................................................1285
ID flag .........................................................................................................................................1286
Watchdog timer mode register 2 (WDTM2).................................................................................1286
23.4 Software Exception.............................................................................................................. 1287
23.4.1 Operation ....................................................................................................................................1287
23.4.2 Restore .......................................................................................................................................1288
23.4.3 EP flag ........................................................................................................................................1289
23.5 Exception Trap ..................................................................................................................... 1290
23.5.1 Illegal opcode..............................................................................................................................1290
23.5.2 Debug trap ..................................................................................................................................1292
23.6 External Interrupt Request Input Pins (NMI and INTP00 to INTP18)............................... 1294
23.6.1 Noise elimination.........................................................................................................................1294
23.6.2 Edge detection ............................................................................................................................1294
23.7 Interrupt Acknowledge Time of CPU.................................................................................. 1302
23.8 Periods in Which Interrupts Are Not Acknowledged by CPU ......................................... 1303
23.9 Cautions ................................................................................................................................ 1303
CHAPTER 24 KEY INTERRUPT FUNCTION ................................................................................... 1304
24.1 Function ................................................................................................................................ 1304
24.2 Register ................................................................................................................................. 1305
24.3 Cautions ................................................................................................................................ 1305
CHAPTER 25 STANDBY FUNCTION ................................................................................................ 1306
25.1 Overview ............................................................................................................................... 1306
25.2 Registers ............................................................................................................................... 1308
25.3 HALT Mode ........................................................................................................................... 1311
25.3.1 Setting and operation status .......................................................................................................1311
25.3.2 Releasing HALT mode ................................................................................................................1311
25.4 IDLE1 Mode........................................................................................................................... 1313
25.4.1 Setting and operation status .......................................................................................................1313
25.4.2 Releasing IDLE1 mode ...............................................................................................................1314
25.5 IDLE2 Mode........................................................................................................................... 1316
25.5.1 Setting and operation status .......................................................................................................1316
25.5.2 Releasing IDLE2 mode ...............................................................................................................1317
25.5.3 Securing setup time when releasing IDLE2 mode.......................................................................1319
25.6 STOP Mode ........................................................................................................................... 1320
25.6.1 Setting and operation status .......................................................................................................1320
25.6.2 Releasing STOP mode ...............................................................................................................1320
25.6.3 Securing oscillation stabilization time when releasing STOP mode ............................................1323
25.7 Subclock Operation Mode................................................................................................... 1324
25.7.1 Setting and operation status .......................................................................................................1324
25.7.2 Releasing subclock operation mode ...........................................................................................1324
25.8 Sub-IDLE Mode..................................................................................................................... 1326
25.8.1 Setting and operation status .......................................................................................................1326
25.8.2 Releasing sub-IDLE mode ..........................................................................................................1326
CHAPTER 26 RESET FUNCTIONS ................................................................................................... 1328
26.1 Overview ............................................................................................................................... 1328
26.2 Registers to Check Reset Source ...................................................................................... 1329
26.3 Operation .............................................................................................................................. 1330
26.3.1
26.3.2
26.3.3
26.3.4
26.3.5
Reset operation via RESET pin ..................................................................................................1330
Reset operation by watchdog timer 2..........................................................................................1332
Reset operation by low-voltage detector .....................................................................................1334
Operation after reset release ......................................................................................................1335
Reset function operation flow......................................................................................................1336
CHAPTER 27 CLOCK MONITOR ...................................................................................................... 1337
27.1 Functions .............................................................................................................................. 1337
27.2 Configuration........................................................................................................................ 1337
27.3 Register ................................................................................................................................. 1338
27.4 Operation .............................................................................................................................. 1339
CHAPTER 28 LOW-VOLTAGE DETECTOR (LVI) ........................................................................... 1342
28.1 Functions .............................................................................................................................. 1342
28.2 Configuration........................................................................................................................ 1342
28.3 Registers ............................................................................................................................... 1343
28.4 Operation .............................................................................................................................. 1345
28.4.1 To use for internal reset signal....................................................................................................1345
28.4.2 To use for interrupt......................................................................................................................1346
28.5 RAM Retention Voltage Detection Operation.................................................................... 1346
CHAPTER 29 CRC FUNCTION.......................................................................................................... 1348
29.1 Functions .............................................................................................................................. 1348
29.2 Configuration........................................................................................................................ 1348
29.3 Registers ............................................................................................................................... 1349
29.4 Operation .............................................................................................................................. 1350
29.5 Usage Method....................................................................................................................... 1351
CHAPTER 30 REGULATOR ............................................................................................................... 1353
30.1 Overview ............................................................................................................................... 1353
30.2 Operation .............................................................................................................................. 1354
CHAPTER 31 FLASH MEMORY ........................................................................................................ 1355
31.1 Features ................................................................................................................................ 1355
31.2 Memory Configuration......................................................................................................... 1356
31.3 Functional Overview ............................................................................................................ 1357
31.4 Rewriting by Dedicated Flash Programmer ...................................................................... 1360
31.4.1
31.4.2
31.4.3
31.4.4
31.4.5
31.4.6
Programming environment..........................................................................................................1360
Communication mode .................................................................................................................1361
Flash memory control .................................................................................................................1375
Selection of communication mode ..............................................................................................1376
Communication commands.........................................................................................................1377
Pin connection ............................................................................................................................1378
31.5 Rewriting by Self Programming.......................................................................................... 1382
31.5.1
31.5.2
31.5.3
31.5.4
31.5.5
31.5.6
Overview .....................................................................................................................................1382
Features......................................................................................................................................1383
Standard self programming flow .................................................................................................1384
Flash functions............................................................................................................................1385
Pin processing ............................................................................................................................1385
Internal resources used...............................................................................................................1386
31.6 Creating ROM code to place order for previously written product ................................ 1387
31.6.1 Procedure for using ROM code to place an order .......................................................................1387
CHAPTER 32 ON-CHIP DEBUG FUNCTION ................................................................................... 1388
32.1 Debugging with DCU ........................................................................................................... 1389
32.1.1
32.1.2
32.1.3
32.1.4
32.1.5
32.1.6
Connection circuit example ........................................................................................................1389
Interface signals .........................................................................................................................1389
Maskable functions.....................................................................................................................1391
Register......................................................................................................................................1391
Operation ...................................................................................................................................1393
Cautions .....................................................................................................................................1393
32.2 Debugging Without Using DCU .......................................................................................... 1394
32.2.1
32.2.2
32.2.3
32.2.4
Circuit connection examples.......................................................................................................1394
Maskable functions.....................................................................................................................1397
Securement of user resources ...................................................................................................1398
Cautions .....................................................................................................................................1405
32.3 ROM Security Function........................................................................................................ 1406
32.3.1 Security ID..................................................................................................................................1406
32.3.2 Setting ........................................................................................................................................1407
CHAPTER 33 ELECTRICAL SPECIFICATIONS ............................................................................... 1409
33.1 Absolute Maximum Ratings ................................................................................................ 1409
33.2 Capacitance .......................................................................................................................... 1411
33.3 Operating Conditions .......................................................................................................... 1411
33.4 Oscillator Characteristics.................................................................................................... 1412
33.4.1 Main clock oscillator characteristics ............................................................................................1412
33.4.2 Subclock oscillator characteristics ..............................................................................................1414
33.4.3 PLL characteristics......................................................................................................................1416
33.4.4 Internal oscillator characteristics .................................................................................................1416
33.5 DC Characteristics ............................................................................................................... 1417
33.5.1 I/O level.......................................................................................................................................1417
33.5.2 Supply current.............................................................................................................................1419
33.6 Data Retention Characteristics........................................................................................... 1420
33.7 AC Characteristics ............................................................................................................... 1421
33.7.1 CLKOUT output timing................................................................................................................1422
33.7.2 Bus timing ...................................................................................................................................1423
33.8 Basic Operation.................................................................................................................... 1430
33.9 Flash Memory Programming Characteristics ................................................................... 1443
CHAPTER 34 PACKAGE DRAWINGS .............................................................................................. 1445
CHAPTER 35 RECOMMENDED SOLDERING CONDITIONS......................................................... 1447
APPENDIX A DEVELOPMENT TOOLS............................................................................................. 1449
A.1 Software Package ................................................................................................................ 1451
A.2 Language Processing Software ......................................................................................... 1451
A.3 Control Software .................................................................................................................. 1451
A.4 Debugging Tools (Hardware) .............................................................................................. 1452
A.4.1 When using IECUBE QB-V850ESJX3H......................................................................................1452
A.4.2 When using MINICUBE QB-V850MINI .......................................................................................1455
A.4.3 When using MINICUBE2 QB-MINI2............................................................................................1456
A.5 Debugging Tools (Software) ............................................................................................... 1456
A.6 Embedded Software............................................................................................................. 1457
A.7 Flash Memory Writing Tools ............................................................................................... 1457
APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/Jx3-H AND V850ES/Jx3 ............... 1458
APPENDIX C REGISTER INDEX ....................................................................................................... 1459
APPENDIX D INSTRUCTION SET LIST ........................................................................................... 1496
D.1 Conventions.......................................................................................................................... 1496
D.2 Instruction Set (in Alphabetical Order) .............................................................................. 1499
APPENDIX E REVISION HISTORY..................................................................................................... 1506
E.1 Major Revisions in This Edition.......................................................................................... 1506
E.2 Revision History of Preceding Editions............................................................................. 1507
R01UH0042EJ0510
Rev.5.10
Mar 25, 2014
V850ES/JG3-H, V850ES/JH3-H
RENESAS MCU
CHAPTER 1 INTRODUCTION
The V850ES/JG3-H and V850ES/JH3-H are products in the low-power series of Renesas Electronics’ V850 single-chip
microcontrollers designed for real-time control applications.
1.1
General
The V850ES/JG3-H and V850ES/JH3-H are 32-bit single-chip microcontrollers that use the V850ES CPU core and
incorporate peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, a D/A converter, a
DMA controller, CAN, and a USB function controller.
In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/JG3-H and
V850ES/JH3-H feature multiply instructions realized by a hardware multiplier, saturated operation instructions, and bit
manipulation instructions.
Table 1-1 lists the products of the V850ES/JG3-H, and Table 1-2 lists the products of the V850ES/JH3-H.
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 19 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 1 INTRODUCTION
Table 1-1. V850ES/JG3-H Product List
Generic Name
V850ES/JG3-H
Part Number
μPD70F3760
μPD70F3761
μPD70F3762
μPD70F3770
256 KB
384 KB
512 KB
256 KB
40 KB
48 KB
56 KB
40 KB
Internal
memory
Flash memory
Memory
space
Logical space
64 MB
External memory area
64 KB
RAM
Note 1
External bus interface
Address data bus: 16
Multiplexed bus
General-purpose register
32 bits × 32 registers
Clock
(PLL mode: fX = 3 to 6 MHz, fXX = 24 to 48 MHz (multiplied by 8)
Clock through mode: fX = 3 to 6 MHz (internal: fXX = 3 to 6 MHz)
Main clock
Subclock
fXT = 32.768 kHz
Internal oscillator
fR = 220 kHz (TYP.)
Minimum instruction
execution time
20.8 ns (main clock (fXX) = 48 MHz)
I/O port (5 V tolerant)
I/O: 77 (22)
Timer
16-bit TAA
6 channels (including 1 channel used only for interval function)
16-bit TAB
2 channels
16-bit TMM
4 channels
16-bit TMT
1 channel
Motor control
1 channel (functions with combination of TAA and TAB; includes Hi-Z output control function)
Watch timer
1 channel (RTC)
WDT
1 channel
Real-time output function
6 bits × 1 channel
10-bit A/D converter
12 channels
8-bit D/A converter
2 channels
Serial interface CSIF/UARTC
2 channels
2 channels
2 channels
2 channels
CSIF/UARTC/I C
1 channel
1 channel
1 channel
1 channel
CSIF
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
1 channel
2
2
UARTC/I C
UARTC/I C/CAN
−
−
−
1 channel
USB function
1 channel
1 channel
1 channel
1 channel
2
DMA controller
Interrupt source
4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory)
External
Notes 2, 3
Internal
Power save function
17 (17)
17 (17)
17 (17)
17 (17)
69
69
69
73
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
Reset source
RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
On-chip debugging
MINICUBE®, MINICUBE2 supported
Operating power supply voltage
2.85 to 3.6 V
Operating ambient temperature
−40 to +85°C
Package
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
Notes 1. Including 8 KB of data-only RAM area.
2. The figures in parentheses indicate the number of external interrupts that can release STOP mode.
3. Including NMI.
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 20 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 1 INTRODUCTION
Table 1-2. V850ES/JH3-H Product List
Generic Name
V850ES/JH3-H
Part Number
μPD70F3765
μPD70F3766
μPD70F3767
μPD70F3771
256 KB
384 KB
512 KB
256 KB
40 KB
48 KB
56 KB
40 KB
Internal
memory
Flash memory
Memory
space
Logical space
64 MB
External memory area
13 MB
RAM
Note 1
External bus interface
Address bus: 24
Address data bus: 16
Separate bus output function/Multiplexed bus
General-purpose register
32 bits × 32 registers
Clock
Main clock
(PLL mode: fX = 3 to 6 MHz, fXX = 24 to 48 MHz (multiplied by 8)
Clock through mode: fX = 3 to 6 MHz (internal: fXX = 3 to 6 MHz)
Subclock
fXT = 32.768 kHz
Internal oscillator
fR = 220 kHz (TYP.)
Minimum instruction
execution time
20.8 ns (main clock (fXX) = 48 MHz)
I/O port (5 V tolerant)
I/O: 96 (25)
Timer
16-bit TAA
6 channels (including 1 channel used only for interval function)
16-bit TAB
2 channels
16-bit TMM
4 channels
16-bit TMT
1 channel
Motor control
1 channel (functions with combination of TAA and TAB; includes Hi-Z output control function)
Watch timer
1 channel (RTC)
WDT
1 channel
Real-time output function
6 bits × 1 channel
10-bit A/D converter
12 channels
8-bit D/A converter
2 channels
Serial interface CSIF/UARTC
2 channels
2 channels
2 channels
2 channels
CSIF/UARTC/I C
1 channel
1 channel
1 channel
1 channel
CSIF
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
1 channel
2
2
UARTC/I C
UARTC/I C/CAN
−
−
−
1 channel
USB function
1 channel
1 channel
1 channel
1 channel
2
DMA controller
Interrupt source
4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory)
External
Notes 2, 3
Internal
20 (20)
69
69
69
73
Power save function
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
Reset source
RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI)
On-chip debugging
MINICUBE, MINICUBE2 supported
Operating power supply voltage
2.85 to 3.6 V
Operating ambient temperature
−40 to +85°C
Package
128-pin plastic LQFP (fine pitch) (14 × 20 mm)
Notes 1. Including 8 KB of data-only RAM area.
2. The figures in parentheses indicate the number of external interrupts that can release STOP mode.
3. Including NMI.
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V850ES/JG3-H, V850ES/JH3-H
1.2
CHAPTER 1 INTRODUCTION
Features
{ Minimum instruction execution time: 20.8 ns (main clock (fXX) = 48 MHz: VDD = 2.85 to 3.6 V)
30.5 μs (subclock (fXT) = 32.768 kHz)
{ General-purpose registers:
32 bits × 32 registers
{ CPU features:
Signed multiplication (16 × 16 → 32): 1 or 2 clocks
Signed multiplication (32 × 32 → 64): 1 to 5 clocks
Saturated operations (overflow and underflow detection functions included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
{ Memory space:
64 MB of linear address space (for programs and data)
External expansion: Up to 16 MB (including 1 MB used as internal ROM/RAM space)
• Internal memory:
RAM:
40/48/56 KB (see Table 1-1 and Table 1-2)
Flash memory: 256/384/512 KB (see Table 1-1 and Table 1-2)
• External bus interface: Separate bus output function/multiplexed bus output selectable
(Only a multiplexed bus is available in the V850ES/JG3-H)
8/16-bit data bus sizing function
Wait function
• Programmable wait function
• External wait function
Idle state function
Bus hold function
{ Interrupts and exceptions:
Internal
V850ES/JG3-H
V850ES/JH3-H
Non-maskable
Maskable
Total
Non-maskable
Maskable
Total
μPD70F3760
1
68
69
1
16
17
μPD70F3761
1
68
69
1
16
17
μPD70F3762
1
68
69
1
16
17
μPD70F3770
1
72
73
1
16
17
μPD70F3765
1
68
69
1
19
20
μPD70F3766
1
68
69
1
19
20
μPD70F3767
1
68
69
1
19
20
μPD70F3771
1
72
73
1
19
20
Software exceptions:
32 sources
Exception trap:
2 sources
{ I/O lines:
External
I/O ports:
77 (V850ES/JG3-H)
96 (V850ES/JH3-H)
{ Timer function:
16-bit interval timer M (TMM):
4 channels
16-bit timer/event counter AA (TAA):
6 channels
16-bit timer/event counter AB (TAB):
2 channels
16-bit timer/event counter T (TMT):
1 channel
Motor control function (timers used: TAB1, TAA4)
6-phase PWM function with dead-time function of 16-bit accuracy
High-impedance output control function
A/D trigger generation by timer-tuned operation function
Arbitrary cycle setting function
Arbitrary dead-time setting function
Real-time counter (RTC):
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1 channel
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V850ES/JG3-H, V850ES/JH3-H
CHAPTER 1 INTRODUCTION
Watchdog timer:
1 channel
{ Real-time output port:
6 bits × 1 channel
{ Serial interface:
Asynchronous serial interface C (UARTC)
3-wire variable-length serial interface F (CSIF)
I2C bus interface (I2C)
CAN interface
USB function interface
UARTC/CSIF:
2 channels
UARTC/CSIF/I2C: 1 channel
UARTC/I2CNote:
2 channels
CSIF:
2 channels
USB function:
1 channel
Note In the μPD70F3770 and 70F3771, one channel is shared with CAN.
{ A/D converter:
10-bit resolution: 12 channels
{ D/A converter:
8-bit resolution: 2 channels
{ DMA controller:
4 channels
{ DCU (debug control unit):
JTAG interface
{ Clock generator:
Main clock or subclock operation:
7-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
Clock-through mode/PLL mode selectable
{ Internal oscillation clock:
220 kHz (TYP.)
{ Power-save functions:
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
{ Package:
100-pin plastic LQFP (fine pitch) (14 × 14) (V850ES/JG3-H)
128-pin plastic LQFP (fine pitch) (14 × 20) (V850ES/JH3-H)
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Mar 25, 2014
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V850ES/JG3-H, V850ES/JH3-H
1.3
CHAPTER 1 INTRODUCTION
Application Fields
Equipment requiring a USB interface such as home audio systems, printers, and scanners.
1.4
Ordering Information
• V850ES/JG3-H
Part Number
Package
Internal Flash Memory
μPD70F3760GC-UEU-AX
μPD70F3761GC-UEU-AX
μPD70F3762GC-UEU-AX
μPD70F3770GC-UEU-AX
100-pin plastic LQFP (fine pitch) (14 × 14)
256 KB
100-pin plastic LQFP (fine pitch) (14 × 14)
384 KB
100-pin plastic LQFP (fine pitch) (14 × 14)
512 KB
100-pin plastic LQFP (fine pitch) (14 × 14)
256 KB
Part Number
Package
Internal Flash Memory
μPD70F3765GF-GAT-AX
μPD70F3766GF-GAT-AX
μPD70F3767GF-GAT-AX
μPD70F3771GC-GAT-AX
128-pin plastic LQFP (fine pitch) (14 × 20)
256 KB
128-pin plastic LQFP (fine pitch) (14 × 20)
384 KB
128-pin plastic LQFP (fine pitch) (14 × 20)
512 KB
100-pin plastic LQFP (fine pitch) (14 × 20)
256 KB
• V850ES/JH3-H
Remark
The V850ES/JG3-H and V850ES/JH3-H are lead-free products.
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Mar 25, 2014
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V850ES/JG3-H, V850ES/JH3-H
1.5
CHAPTER 1 INTRODUCTION
Pin Configuration (Top View)
• V850ES/JH3-H
100-pin plastic LQFP (fine pitch) (14 × 14)
μPD70F3761GC-UEU-AX
μPD70F3762GC-UEU-AX
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P710/ANI10
P711/ANI11
PDL15/AD15
PDL14/AD14
PDL13/AD13
PDL12/AD12
PDL11/AD11
PDL10/AD10
PDL9/AD9
PDL8/AD8
EVDD
VSS
PDL7/AD7
PDL6/AD6
PDL5/AD5/FLMD1
μPD70F3760GC-UEU-AX
μPD70F3770GC-UEU-AX
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PDL4/AD4
PDL3/AD3
PDL2/AD2
PDL1/AD1
PDL0/AD0
P65/TOAB1B3/EVTAB1/CS3
P64/TOAB1T3/TIAB13/TOAB13/CS2
P63/TOAB1B2/TRGAB1/CS0
P62/TOAB1T2/TIAB12/TOAB12/ASTB
P61/TOAB1B1/TIAB10/TOAB10/RD
P60/TOAB1T1/TIAB11/TOAB11/WAIT
PCM1/CLKOUT
EVDD
VSS
REGCNote 4
VDD
PCT1/WR1
PCT0/WR0
P915/TIAA50/TOAA50/INTP18
P914/TIAA51/TOAA51/INTP17
P913/TOAB1OFF/INTP16
P912/SCKF3
P911/SOF3/RXDC2/INTP15
P910/SIF3/TXDC2/INTP14
P99/SCKF1/INTP13
P31/RXDC0/SIF4/INTP08
P32/ASCKC0/SCKF4/TIAA00/TOAA00
P33/TIAA01/TOAA01/RTCDIV/RTCCL
P34/TIAA10/TOAA10/TOAA1OFF/INTP09
P35/TIAA11/TOAA11/RTC1HZ
P36/TXDC3/SCL00(CTXD0Note 3)/UDMARQ0
P37/RXDC3/SDA00(CRXD0Note 3)UDMAAK0
VSS
EVDD
P50/TIAB01/KR0/TOAB01/RTP00/UDMARQ1
P51/TIAB02/KR1/TOAB02/RTP01/UDMAAK1
P52/TIAB03/KR2/TOAB03/RTP02/DDI
P53/SIF2/TIAB00/KR3/TOAB00/RTP03/DDO
P54/SOF2/KR4/RTP04/DCK
P55/SCKF2/KR5/RTP05/DMS
P56/INTP05/DRST
P90/KR6/TXDC1/SDA02
P91/KR7/RXDC1/SCL02
P92/TENC01/TIT01/TOT01
P93/TECR0/TIT00/TOT00
P94/TIAA31/TOAA31/TENC00/EVTT0
P95/TIAA30/TOAA30
P96/TIAA21/TOAA21/INTP11
P97/SIF1/TIAA20/TOAA20
P98/SOF1/INTP12
AVREF0
AVSS
P10/ANO0
P11/ANO1
AVREF1
P02/NMI
P03/INTP02/ADTRG/UCLK
FLMD0Note 1
VDD
REGCNote 2
VSS
X1
X2
RESET
XT1
XT2
UDMF
UDPF
UVDD
P04/INTP03
P05/INTP04
P40/SIF0/TXDC4/SDA01
P41/SOF0/RXDC4/SCL01
P42/SCKF0/INTP10
P30/TXDC0/SOF4/INTP07
Notes 1. Connect this pin to VSS in the normal mode.
2. Connect the REGC pin to VSS via a 4.7 μF (recommended value) capacitor.
3. μPD703770 only
4. Connect the REGC pin to VSS via a 4.7 μF (recommended value) capacitor.
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Mar 25, 2014
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V850ES/JG3-H, V850ES/JH3-H
CHAPTER 1 INTRODUCTION
• V850ES/JH3-H
128-pin plastic LQFP (fine pitch) (14 × 20)
μPD70F3766GF-GAT-AX
μPD70F3767GF-GAT-AX
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P710/ANI10
P711/ANI11
PCS3/CS3
PDL15/AD15
PDL14/AD14
PDL13/AD13
PDL12/AD12
PDL11/AD11
PDL10/AD10
PDL9/AD9
PDL8/AD8
EVDD
VSS
PDL7/AD7
PDL6/AD6
PDL5/AD5/FLMD1
μPD70F3765GF-GAT-AX
μPD70F3771GF-GAT-AX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PDL4/AD4
PDL3/AD3
PDL2/AD2
PDL1/AD1
PDL0/AD0
PCS2/CS2
PCS0/CS0
P65/TOAB1B3/EVTAB1
P64/TOAB1T3/TIAB13/TOAB13
P63/TOAB1B2/TRGAB1
P62/TOAB1T2/TIAB12/TOAB12
P61/TOAB1B1/TIAB10/TOAB10
P60/TOAB1T1/TIAB11/TOAB11
PCM0/WAIT
PCT6/ASTB
PCT4/RD
PCM1/CLKOUT
EVDD
VSS
REGCNote 4
VDD
PDH7/A23
PDH6/A22
PDH5/A21
PDH4/A20
PCT1/WR1
PCT0/WR0
PDH3/A19
PDH2/A18
PDH1/A17
PDH0/A16
P915/TIAA50/TOAA50/INTP18/A15
P914/TIAA51/TOAA51/INTP17/A14
P913/TOAB1OFF/INTP16/A13
P912/SCKF3/A12
P911/SOF3/RXDC2/INTP15/A11
P910/SIF3/TXDC2/INTP14/A10
P99/SCKF1/INTP13/A9
P32/ASCKC0/SCKF4/TIAA00/TOAA00
P33/TIAA01/TOAA01/RTCDIV/RTCCL
P34/TIAA10/TOAA10/TOAA1OFF/INTP09
P35/TIAA11/TOAA11/RTC1HZ
P36/TXDC3/SCL00(/CTXD0Note 3)/UDMARQ0
P37/RXDC3/SDA00(/CRXD0Note 3)/UDMAAK0
VSS
EVDD
P50/TIAB01/KR0/TOAB01/RTP00/UDMARQ1
P51/TIAB02/KR1/TOAB02/RTP01/UDMAAK1
DDI
DDO
DCK
DMS
DRST
P90/KR6/TXDC1/SDA02/A0
P91/KR7/RXDC1/SCL02/A1
P92/TENC01/TIT01/TOT01/A2
P93/TECR0/TIT00/TOT00/A3
P94/TIAA31/TOAA31/TENC00/EVTT0/A4
P95/TIAA30/TOAA30/A5
VSS
EVDD
P96/TIAA21/TOAA21/INTP11/A6
P97/SIF1/TIAA20/TOAA20/A7
P98/SOF1/INTP12/A8
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AVREF0
AVSS
P10/ANO0
P11/ANO1
AVREF1
P02/NMI
P03/INTP02/ADTRG/UCLK
P00/INTP00
P01/INTP01
PCM2/HLDAK
PCM3/HLDRQ
FLMD0Note 1
VDD
REGCNote 2
VSS
X1
X2
RESET
XT1
XT2
UDMF
UDPF
UVDD
NC
NC
P04/INTP03
P05/INTP04
P25/INTP06
P40/SIF0/TXDC4/SDA01
P41/SOF0/RXDC4/SCL01
P42/SCKF0/INTP10
P20/TIAB03/KR2/TOAB03/RTP02
P21/SIF2/TIAB00/KR3/TOAB00/RTP03
P22/SOF2/KR4/RTP04
P23/SCKF2/KR5/RTP05
P24/INTP05
P30/TXDC0/SOF4/INTP07
P31/RXDC0/SIF4/INTP08
Notes 1. Connect this pin to VSS in the normal mode.
2. Connect the REGC pin to VSS via a 4.7 μF (recommended value) capacitor.
3. μPD703770 only
4. Connect the REGC pin to VSS via a 4.7 μF (recommended value) capacitor.
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Mar 25, 2014
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V850ES/JG3-H, V850ES/JH3-H
CHAPTER 1 INTRODUCTION
Pin names
Address bus
A0 to A23:
Address/data bus
AD0 to AD15:
A/D trigger input
ADTRG:
Analog input
ANI0 to ANI11:
Analog output
ANO0, ANO1:
Asynchronous serial clock
ASCKC0:
Address strobe
ASTB:
Analog reference voltage
AVREF0, AVREF1:
Grand for analog pin
AVSS:
Clock output
CLKOUT:
CAN receive data
CRXD0:
Chip select
CS0, CS2, CS3:
CAN transmit data
CTXD0:
Debug clock
DCK:
Debug data input
DDI:
Debug data output
DDO:
Debug mode select
DMS:
Debug reset
DRST:
Power supply for external pin
EVDD:
Timer event count input
EVTT0, EVTAB1:
Flash programming mode
FLMD0, FLMD1:
Hold acknowledge
HLDAK:
Hold request
HLDRQ:
INTP00 to INTP18: External interrupt input
Key return
KR0 to KR7:
Non-maskable interrupt request
NMI:
Non-connection
NC:
Port 0
P00 to P05:
Port 1
P10, P11:
Port 2
P20 to P25:
Port 3
P30 to P37:
Port 4
P40 to P42:
Port 5
P50 to P56:
Port 6
P60 to P65
Port 7
P70 to P711:
Port 9
P90 to P915:
Port CM
PCM0 to PCM3:
PCS0, PCS2, PCS3: Port CS
Port CT
PCT0, PCT1,
PCT4, PCT6:
Port DH
PDH0 to PDH7:
Port DL
PDL0 to PDL15:
Read strobe
RD:
Regulator control
REGC:
Reset
RESET:
RTC1HZ, RTCCL,
Real-time counter clock output
RTCDIV:
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
RTP00 to RTP05:
RXDC0 to RXDC4:
SCKF0 to SCKF4:
SCL00 to SCL02:
SDA00 to SDA02:
SIF0 to SIB4:
SOF0 to SOF4:
TECR0:
TENC00, TENC01:
TIAA00, TIAA01,
TIAA10, TIAA11,
TIAA20, TIAA21,
TIAA30, TIAA31,
TIAA50, TIAA51,
TIAB00 to TIAB03,
TIAB10, TIAB13,
TIT00, TIT01:
TOAA00, TOAA01,
TOAA10, TOAA11,
TOAA20, TOAA21,
TOAA30, TOAA31,
TOAA50 to TOAA51,
TOAB00 to TOAB03,
TOAB10 to TOAB13,
TOAB1B1 to TOAB1B3,
TOAB1T1 to TOAB1T3,
TOT00, TOT01:
TOAA1OFF,
TOAB1OFF:
TRGAB1:
TXDC0 to TXDC4:
UCLK:
UDMAAK0,
UDMAAK1:
UDMARQ0,
UDMARQ1:
UDMF:
UDPF:
UVDD:
VDD:
VSS:
WAIT:
WR0:
WR1:
X1, X2:
XT1, XT2:
Real-time output port
Receive data
Serial clock
Serial clock
Serial data
Serial input
Serial output
Timer encoder clear input
Timer encoder input
Timer input
Timer output
Timer output off
Timer trigger input
Transmit data
USB clock
DMA acknowledge for external USB
DMA request for external USB
USB data I/O (−) function
USB data I/O (+) function
Power supply for external USB
Power supply
Ground
External wait input
Lower byte write strobe
Upper byte write strobe
Crystal for main clock
Crystal for subclock
Page 27 of 1513
V850ES/JG3-H, V850ES/JH3-H
1.6
CHAPTER 1 INTRODUCTION
Function Block Configuration
1.6.1
Internal block diagram
• V850ES/JG3-H
16-bit timer/
counter AB:
2 ch
TOT00, TOT01
PC
RAM
32-bit barrel
shifter
Note 2
System
register
Instruction
queue
ASTB
Multiplier
16 × 16 → 32
RD
BCU
WAIT
WR0, WR1
ALU
General-purpose
registers 32 bits × 32
CS0, CS2, CS3
DMAC
AD0 to AD15
16-bit timer/
counter AA:
6 ch
16-bit timer/
counter T:
1 ch
WDT
RTC1HZ
RTCCL
RTCDIV
RTC
RTP00 to RTP05
RTO
Ports
CLKOUT
CRC
16-bit interval
timer M:
4 ch
TECR0, TENC00, TENC01,
EVTT0, TIT00, TIT01
Note 1
CLM
TIAA00 to TIAA30, TIAA50,
TIAA01 to TIAA31, TIAA51,
TOAA1OFF
TOAA00 to TOAA30, TOAA50,
TOAA01 to TOAA31, TOAA51
CPU
Internal
oscillator
TIAB00 to TIAB03,
TIAB10 to TIAB13,
EVTAB1,
TRGAB1,
TOAB1OFF
TOAB00 to TOAB03,
TOAB10 to TOAB13
TOAB1T1 to TOAB1T3,
TOAB1B1 to TOAB1B3
Flash memory
INTC
CG
CG
PCM1
PCT0, PCT1
PDL0 to PDL15
P90 to P915
P70 to P711
P60 to P65
P50 to P56
P40 to P42
P30 to P37
P10, P11
P02 to P05
NMI
INTP02 to INTP05,
INTP07 to INTP18
PLL
XT1
XT2
X1
X2
RESET
LVI
VDD
Regulator
VSS
REGC
FLMD0
FLMD1
SIF0 to SIF4
SOF0 to SOF4
SCKF0 to SCKF4
CSIF:
5 ch
RXDC0 to RXDC4
TXDC0 to TXDC4
ASCKC0
UARTC:
5 ch
SDA00 to SDA02
SCL00 to SCL02
I2C0: 3 ch
UDMF
UDPF
CRXD0
CTXD0
EVDD, UVDD
A/D
converter
USB function
CAN
: 1 ch
DRST
DMS
D/A
converter
Note 3
ANI0 to ANI11
ADTRG
AVREF0
AVSS
Key return
function
AVREF1
ANO0, ANO1
DCU
DDI
DCK
DDO
KR0 to KR7
Notes 1. μPD70F3760, 70F3770: 256 KB
μPD70F3761:
μPD70F3762:
2. μPD70F3760, 70F3770:
μPD70F3761:
μPD70F3762:
3. μPD70F3770 only
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
384 KB
512 KB
40 KB (Including a data only RAM: 8 KB)
48 KB (Including a data only RAM: 8 KB)
56 KB (Including a data only RAM: 8 KB)
Page 28 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 1 INTRODUCTION
• V850ES/JH3-H
Flash memory
TIAA00 to TIAA30, TIAA50,
TIAA01 to TIAA31, TIAA51,
TOAA1OFF
TOAA00 to TOAA30, TOAA50,
TOAA01 to TOAA31, TOAA51
PC
RAM
32-bit barrel
shifter
Note 2
System
register
HLDAK
16-bit timer/
counter AB:
2 ch
16-bit timer/
counter AA:
6 ch
16-bit timer/
counter T:
1 ch
WDT
RTC1HZ
RTCCL
RTCDIV
RTC
RTP00 to RTP05
RTO
CSIF:
5 ch
RXDC0 to RXDC4
TXDC0 to TXDC4
ASCKC0
UARTC:
5 ch
SDA00 to SDA02
SCL00 to SCL02
I2C: 3 ch
CRXD0
CTXD0
ALU
ASTB
RD
WAIT
WR0, WR1
CS0, CS2, CS3
A0 to A23
DMAC:
4 ch
AD0 to AD15
Ports
CLKOUT
CG
CG
PLL
XT1
XT2
X1
X2
RESET
LVI
VDD
Regulator
VSS
REGC
FLMD0
FLMD1
SIF0 to SIF4
SOF0 to SOF4
SCKF0 to SCKF4
UDMF
UDPF
BCU
PCM0 to PCM3
PCS0, PCS2, PCS3
PCT0, PCT1, PCT4, PCT6
PDH0 to PDH7
PDL0 to PDL15
P90 to P915
P70 to P711
P60 to P65
P50, P51
P40 to P42
P30 to P37
P20 to P25
P10, P11
P00 to P05
TOT00, TOT01
HLDRQ
Multiplier
16 × 16 → 32
General-purpose
registers 32 bits × 32
16-bit interval
timer M:
4 ch
TECR0, TENC00, TENC01,
EVTT0, TIT00, TIT01
Instruction
queue
Note 1
CRC
TIAB00 to TIAB03,
TIAB10 to TIAB13,
EVTAB1,
TRGAB1,
TOAB1OFF
TOAB00 to TOAB03,
TOAB10 to TOAB13
TOAB1T1 to TOAB1T3,
TOAB1B1 to TOAB1B3
CPU
INTC
Internal
oscillator
NMI
INTP00 to INTP18
USB
function
Note 3
CAN
: 1 ch
EVDD, UVDD
CLM
A/D
converter
ANI0 to ANI11
ADTRG
AVREF0
AVSS
DRST
DMS
D/A
converter
Key return
function
AVREF1
ANO0, ANO1
DCU
DDI
DCK
DDO
KR0 to KR7
Notes 1. μPD70F3765, 70F3771: 256 KB
μPD70F3766:
μPD70F3767:
2. μPD70F3765, 70F3771:
μPD70F3766:
μPD70F3767:
3. μPD70F3771 only
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
384 KB
512 KB
40 KB (Including a data only RAM: 8 KB)
48 KB (Including a data only RAM: 8 KB)
56 KB (Including a data only RAM: 8 KB)
Page 29 of 1513
V850ES/JG3-H, V850ES/JH3-H
1.6.2
CHAPTER 1 INTRODUCTION
Internal units
(1) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic
operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits)
contribute to faster complex processing.
(2) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU
generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an
instruction queue.
(3) Flash memory (ROM)
This is a 512/384/256 KB flash memory mapped to addresses 0000000H to 007FFFFH/0000000H to
005FFFFH/0000000H to 003FFFFH. It can be accessed from the CPU in one clock during instruction fetch.
(4) RAM
This is a 48/40/32 KB RAM mapped to addresses 3FF3000H to 3FFEFFFH/3FF5000H to 3FFEFFFH/3FF7000H to
3FFEFFFH. It can be accessed from the CPU in one clock during data access. An 8 KB data-only RAM is
incorporated at addresses 00280000H to 002FFFFFH.
(5) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP18) from on-chip peripheral hardware and
external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed
servicing control can be performed.
(6) Clock generator (CG)
A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (fX)
and subclock frequency (fXT), respectively. There are two modes: In the clock-through mode, fX is used as the main
clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 8.
The CPU clock frequency (fCPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT.
(7) Internal oscillator
An internal oscillator is provided on chip. The oscillation frequency is 220 kHz (TYP). The internal oscillator
supplies the clock for watchdog timer 2 and timer M.
(8) Timer/counter
Six-channel 16-bit timer/event counter AA (TAA), two-channel 16-bit timer/event counter AB (TAB), one-channel 16bit timer/event counter T (TMT), and four-channel 16-bit interval timer M (TMM) are provided on chip. The motor
control function can be realized using TAB1 and TAA4 in combination.
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Page 30 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 1 INTRODUCTION
(9) Real-time counter (for watch)
The real-time counter counts the reference time (one second) for watch counting based on the subclock (32.768
kHz) or main clock. This can simultaneously be used as the interval timer based on the main clock. Hardware
counters dedicated to year, month, day of week, day, hour, minute, and second are provided, and can count up to
99 years.
(10) Watchdog timer 2
A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc.
The internal oscillation clock, the main clock, or the subclock can be selected as the source clock.
Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal
(WDT2RES) after an overflow occurs.
(11) Serial interface
The V850ES/JG3-H and V850ES/JH3-H include three kinds of serial interfaces (asynchronous serial interface C
(UARTC), 3-wire variable-length serial interface F (CSIF), and an I2C bus interface (I2C)), a CAN controller
(CAN)Note, and a USB function controller (USBF).
UARTC transfers data via the TXDC0 to TXDC2 pins and RXDC0 to RXDC2 pins.
CSIF transfers data via the SOF0 to SOF4 pins, SIF0 to SIF4 pins, and SCKF0 to SCKF4 pins.
In the case of I2C, data is transferred via the SDA00 to SDA02 and SCL00 to SCL02 pins.
Note
CAN
transfers data via the CRXD0Note and CTXD0Note pins.
USBF transfers data via the UDMF and UDPF pins.
Note μPD70F3770, 70F3771 only
(12) A/D converter
This 10-bit A/D converter includes 12 analog input pins.
Conversion is performed using the successive
approximation method.
(13) D/A converter
A two-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip.
(14) DMA controller
A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM, on-chip
peripheral I/O devices, and external memory in response to interrupt requests sent by on-chip peripheral I/O
devices.
(15) Key interrupt function
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8
channels).
(16) Real-time output function
The real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer compare
register match signal.
(17) CRC function
A CRC operation circuit that generates a 16-bit CRC (Cyclic Redundancy Check) code upon setting of 8-bit data
is provided on-chip.
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 31 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 1 INTRODUCTION
(18) DCU (debug control unit)
An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is provided.
Switching between the normal port function and on-chip debugging function is done with the control pin input
level and the OCDM register.
(19) Ports
The following general-purpose port functions and control pin functions are available.
• V850ES/JG3-H
Port
I/O
Alternate Function
P0
4-bit I/O
NMI, external interrupt, A/D converter trigger, serial interface
P1
2-bit I/O
D/A converter analog output
P3
10-bit I/O
External interrupt, real-time counter, serial interface, timer I/O
P4
3-bit I/O
Serial interface, external interrupt
P5
7-bit I/O
Timer I/O, serial interface, real-time output, key interrupt input, debug I/O
P6
6-bit I/O
External bus control signal, timer I/O, external bus control signal
P7
12-bit I/O
A/D converter analog input
P9
16-bit I/O
Serial interface, key interrupt input, timer I/O, external interrupt
PCM
1-bit I/O
External bus control signal
PCT
2-bit I/O
External bus control signal
PDL
16-bit I/O
External address/data bus
• V850ES/JH3-H
Port
I/O
Alternate Function
P0
6-bit I/O
NMI, external interrupt, A/D converter trigger, serial interface
P1
2-bit I/O
D/A converter analog output
P2
6-bit I/O
Timer I/O, real-time output, key interrupt input, serial interface
P3
10-bit I/O
External interrupt, real-time counter, serial interface, timer I/O
P4
3-bit I/O
Serial interface, external interrupt
P5
2-bit I/O
Timer I/O, real-time output, key interrupt input
P6
6-bit I/O
External bus control signal, timer I/O
P7
12-bit I/O
A/D converter analog input
P9
16-bit I/O
External address bus, serial interface, key interrupt input, timer I/O, external interrupt
PCM
4-bit I/O
External bus control signal
PCS
3-bit I/O
External bus control signal
PCT
4-bit I/O
External bus control signal
PDH
8-bit I/O
External address bus
PDL
16-bit I/O
External address/data bus
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 32 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 2 PIN FUNCTIONS
CHAPTER 2 PIN FUNCTIONS
2.1
List of Pin Functions
The names and functions of the pins of the V850ES/JG3-H and V850ES/JH3-H are described below.
There are four types of pin I/O buffer power supplies: AVREF0, AVREF1, EVDD, and UVDD. The relationship between these
power supplies and the pins is described below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply
Corresponding Pins
V850ES/JG3-H
V850ES/JH3-H
AVREF0
Port 7
Port 7
AVREF1
Port 1
Port 1
EVDD
RESET, ports 0, 3 to 6, 9, CM, CT, DL
RESET, ports 0, 2 to 6, 9, CM, CS, CT, DH, DL
UVDD
UDPF, UDMF
UDPF, UDMF
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Page 33 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 2 PIN FUNCTIONS
(1) Port pins
(1/4)
Pin Name
I/O
Function
Alternate Function
Pin No.
JG3-H JH3-H
I/O
P00
Port 0
6-bit I/O port (V850ES/JH3-H)
P01
4-bit I/O port (V850ES/JG3-H)
P02
INTP00
−
8
INTP01
−
9
NMI
6
6
INTP02/ADTRG/UCLK
7
7
P04
INTP03
20
26
P05
INTP04
21
27
ANO0
3
3
ANO1
4
4
TIAB03/KR2/TOAB03/RTP02
−
32
SIF2/TIAB00/KR3/TOAB00/RTP03
−
33
SOF2/KR4/RTP04
−
34
P23
SCKF2/KR5/RTP05
−
35
P24
INTP05
−
36
P25
INTP06
−
28
TXDC0/SOF4/INTP07
25
37
RXDC0/SIF4/INTP08
26
38
ASCKC0/SCKF4/TIAA00/TOAA00
27
39
P33
TIAA01/TOAA01/RTCDIV/RTCCL
28
40
P34
TIAA10/TOAA10/TOAA1OFF/INTP09
29
41
P35
TIAA11/TOAA11/RTC1HZ
30
42
P36
TXDC3/SCL00/CTXD0
Note
P37
RXDC3/SDA00/CRXD0
Input/output can be specified in 1-bit units.
P03
5 V tolerant.
I/O
P10
Port 1
2-bit I/O port
P11
Input/output can be specified in 1-bit units.
P20
I/O
Port 2
6-bit I/O port
P21
Input/output can be specified in 1-bit units.
P22
5 V tolerant.
P30
I/O
Port 3
8-bit I/O port
P31
Input/output can be specified in 1-bit units.
P32
5 V tolerant.
P40
I/O
Port 4
3-bit I/O port
P41
Input/output can be specified in 1-bit units.
P42
5 V tolerant.
P50
I/O
P51
Port 5
31
43
32
44
SIF0/TXDC4/SDA01
22
29
SOF0/RXDC4/SCL01
23
30
SCKF0/INTP10
24
31
TIAB01/KR0/TOAB01/RTP00
35
47
36
48
TIAB03/KR2/TOAB03/RTP02/DDI
37
−
SIF2/TIAB00/KR3/TOAB00
38
−
−
/UDMAAK0
2-bit I/O port (V850ES/JH3-H)
/UDMARQ1
7-bit I/O port (V850ES/JG3-H)
TIAB02/KR1/TOAB02/RTP01
Input/output can be specified in 1-bit units.
/UDMAAK1
5 V tolerant.
P52
/UDMARQ0
Note
P53
/RTP03/DDO
P54
SOF2/KR4/RTP04/DCK
39
P55
SCKF2/KR5/RTP05/DMS
40
−
P56
INTP05/DRST
41
−
Note
μPD70F3770, 70F3771 only
Remark
JG3-H: V850ES/JG3-H, JH3-H: V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 34 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 2 PIN FUNCTIONS
(2/4)
Pin Name
I/O
Function
Alternate Function
Pin No.
JG3-H JH3-H
P60
I/O
P61
Port 6
6-bit I/O port
Input/output can be specified in 1-bit units.
P62
P63
P64
P65
TOAB1T1/TOAB11/TIAB11/WAIT
65
−
TOAB1T1/TOAB11/TIAB11
−
90
TOAB1B1/TIAB10/TOAB10/RD
66
−
TOAB1B1/TIAB10/TOAB10
−
91
TOAB1T2/TOAB12/TIAB12/ASTB
67
−
TOAB1T2/TOAB12/TIAB12
−
92
TOAB1B2/TRGAB1/CS0
68
−
TOAB1B2/TRGAB1
−
93
TOAB1T3/TOAB13/TIAB13/CS2
69
−
TOAB1T3/TOAB13/TIAB13
−
94
TOAB1B3/EVTAB1/CS3
70
−
−
95
ANI0
100
128
ANI1
99
127
ANI2
98
126
P73
ANI3
97
125
P74
ANI4
96
124
P75
ANI5
95
123
P76
ANI6
94
122
P77
ANI7
93
121
P78
ANI8
92
120
P79
ANI9
91
119
P710
ANI10
90
118
TOAB1B3/EVTAB1
P70
I/O
P71
P72
Port 7
12-bit I/O port
Input/output can be specified in 1-bit units.
P711
P90
P91
I/O
Port 9
16-bit I/O port
Input/output can be specified in 1-bit units.
P92
P93
P94
P95
P96
P97
Remark
ANI11
89
117
KR6/TXDC1/SDA02
42
−
KR6/TXDC1/SDA02/A0
−
54
KR7/RXDC1/SCL02
43
−
KR7/RXDC1/SCL02/A1
−
55
TENC01/TIT01/TOT01
44
−
TENC01/TIT01/TOT01/A2
−
56
TECR0/TIT00/TOT00
45
−
TECR0/TIT00/TOT00/A3
−
57
TIAA31/TOAA31/TENC00/EVTT0
46
−
TIAA31/TOAA31/TENC00/EVTT0/A4
−
58
TIAA30/TOAA30
47
−
TIAA30/TOAA30/A5
−
59
TIAA21/TOAA21/INTP11
48
−
TIAA21/TOAA21/INTP11/A6
−
62
SIF1/TIAA20/TOAA20
49
−
SIF1/TIAA20/TOAA20/A7
−
63
JG3-H: V850ES/JG3-H, JH3-H: V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 35 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 2 PIN FUNCTIONS
(3/4)
Pin Name
I/O
Function
Alternate Function
Pin No.
JG3-H JH3-H
P98
I/O
Port 9
16-bit I/O port
Input/output can be specified in 1-bit units.
P99
P910
P911
P912
P913
P914
P915
PCM0
I/O
Port CM
4-bit I/O port (V850ES/JH3-H)
PCM1
1-bit I/O port (V850ES/JG3-H)
SOF1/INTP12
50
−
SOF1/INTP12/A8
−
64
SCKF1/INTP13
51
−
SCKF1/INTP13/A9
−
65
SIF3/TXDC2/INTP14
52
−
SIF3/TXDC2/INTP14/A10
−
66
SOF3/RXDC2/INTP15
53
−
SOF3/RXDC2/INTP15/A11
−
67
SCKF3
54
−
SCKF3/A12
−
68
TOAB1OFF/INTP16
55
−
TOAB1OFF/INTP16/A13
−
69
TIAA51/TOAA51/INTP17
56
−
TIAA51/TOAA51/INTP17/A14
−
70
TIAA50/TOAA50/INTP18
57
−
TIAA50/TOAA50/INTP18/A15
−
71
WAIT
−
89
CLKOUT
64
86
HLDAK
−
10
HLDRQ
−
11
CS0
−
96
CS2
−
97
CS3
−
116
WR0
58
76
WR1
59
77
RD
−
87
ASTB
−
88
A16
−
72
A17
−
73
A18
−
74
PDH3
A19
−
75
PDH4
A20
−
78
PDH5
A21
−
79
PDH6
A22
−
80
PDH7
A23
−
81
PCM2
Input/output can be specified in 1-bit units.
PCM3
PCS0
I/O
3-bit I/O port
PCS2
Input/output can be specified in 1-bit units.
PCS3
PCT0
Port CS
I/O
Port CT
4-bit I/O port (V850ES/JH3-H)
PCT1
2-bit I/O port (V850ES/JG3-H)
PCT4
Input/output can be specified in 1-bit units.
PCT6
PDH0
PDH1
PDH2
Remark
I/O
Port DH
8-bit I/O port
Input/output can be specified in 1-bit units.
JG3-H: V850ES/JG3-H, JH3-H: V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 36 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 2 PIN FUNCTIONS
(4/4)
Pin Name
I/O
Function
Alternate Function
Pin No.
JG3-H JH3-H
PDL0
I/O
Port DL
AD0
71
98
AD1
72
99
AD2
73
100
PDL3
AD3
74
101
PDL4
AD4
75
102
PDL5
AD5/FLMD1
76
103
PDL6
AD6
77
104
PDL7
AD7
78
105
PDL8
AD8
81
108
PDL9
AD9
82
109
PDL10
AD10
83
110
PDL11
AD11
84
111
PDL12
AD12
85
112
PDL13
AD13
86
113
PDL14
AD14
87
114
PDL15
AD15
88
115
PDL1
PDL2
Remark
16-bit I/O port
Input/output can be specified in 1-bit units.
JG3-H: V850ES/JG3-H, JH3-H: V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 37 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 2 PIN FUNCTIONS
(2) Non-port Pins
(1/9)
Pin Name
I/O
Function
Alternate Function
Pin No.
JG3-H JH3-H
A0
Output
Address bus for external memory
(when using separate bus output function)
P90/KR6/TXDC1/SDA02
−
54
P91/KR7/RXDC1/SCL02
−
55
A2
P92/TENC01/TIT01/TOT01
−
56
A3
P93/TECR00/TIT00/TOT00
−
57
A4
P94/TIAA31/TOAA31/TENC0/EVTT0
−
58
A5
P95/TIAA30/TOAA30
−
59
A6
P96/TIAA21/TOAA21/INTP11
−
62
A7
P97/SIF1/TIAA20/TOAA20
−
63
A8
P98/SOF1/INTP12
−
64
A9
P99/SCKF1/INTP13
−
65
A10
P910/SIF3/TXDC2/INTP14
−
66
A11
P911/SOF3/RXDC2/INTP15
−
67
A12
P912/SCKF3
−
68
A13
P913/TOAB1OFF/INTP16
−
69
A14
P914/TIAA51/TOAA51/INTP17
−
70
A15
P915/TIAA50/TOAA50/INTP18
−
71
A16
PDH0
−
72
A17
PDH1
−
73
A18
PDH2
−
74
A19
PDH3
−
75
A20
PDH4
−
78
A21
PDH5
−
79
A22
PDH6
−
80
A23
PDH7
−
81
PDL0
71
98
AD1
PDL1
72
99
AD2
PDL2
73
100
AD3
PDL3
74
101
AD4
PDL4
75
102
AD5
PDL5/FLMD1
76
103
AD6
PDL6
77
104
AD7
PDL7
78
105
AD8
PDL8
81
108
AD9
PDL9
82
109
AD10
PDL10
83
110
AD11
PDL11
84
111
AD12
PDL12
85
112
AD13
PDL13
86
113
AD14
PDL14
87
114
AD15
PDL15
88
115
P03/INTP02/UCLK
7
7
A1
AD0
ADTRG
Remark
I/O
Input
Address/data bus for external memory
External trigger input for A/D converter
JG3-H: V850ES/JG3-H, JH3-H: V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 38 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 2 PIN FUNCTIONS
(2/9)
Pin Name
I/O
Function
Alternate Function
Pin No.
JG3-H JH3-H
ANI0
P70
100
128
ANI1
P71
99
127
ANI2
P72
98
126
ANI3
P73
97
125
ANI4
P74
96
124
ANI5
P75
95
123
ANI6
P76
94
122
ANI7
P77
93
121
ANI8
P78
92
120
ANI9
P79
91
119
ANI10
P710
90
118
ANI11
P711
89
117
P10
3
3
Input
ANO0
Output
Analog voltage input for A/D converter
Analog voltage output for D/A converter
ANO1
ASCKC0
Input
P11
4
4
UARTC0 baud rate clock input. 5 V tolerant.
P32/SCKF4/TIAA00/TOAA00
27
39
P62/TOAB1T2/TIAB12/TOAB12
67
−
PCT6
ASTB
Output
Address strobe signal for external memory
−
88
AVREF0
−
Reference voltage input for A/D
converter/positive power supply for port 7
−
1
1
AVREF1
−
Reference voltage input for D/A
converter/positive power supply for port 1
−
5
5
AVSS
−
Ground potential for A/D and D/A converters
−
2
2
CLKOUT
CRXD0
Note
Output
Input
Internal system clock output
PCM1
64
86
CAN receive data input. 5 V tolerant.
P37/RXDC3/SDA00/UDMAAK0
32
44
68
−
CS0
Output
Chip select output
P63/TOAB1B2/TRGAB1
PCS0
−
96
CS2
Output
Chip select output
P64/TOAB1T3/TIAB13/TOAB13
69
−
PCS2
−
97
CS3
Output
Chip select output
P65/TOAB1B3/EVTAB1
70
−
PCS3
−
116
CTXD0
Note
DCK
Output
Input
CAN transmit data output. 5 V tolerant.
P36/TXDC3/SCL00/UDMARQ0
31
43
Clock input for on-chip debugging
P54/SOF2/KR4/RTP04
39
−
−
51
−
5 V tolerant
DDI
Input
37
−
−
−
49
Data output for on-chip debugging
In the on-chip debug mode, high-level output is
forcibly set. 5 V tolerant.
P53/SIF2/TIAB00/KR3/TOAB00/RTP03
38
−
−
−
50
Mode select signal input for on-chip debugging
P55/SCKF2/KR5/RTP05
40
−
−
52
Data input for on-chip debugging
P52/TIAB03/KR2/TOAB03/RTP02
5 V tolerant
DDO
Output
DMS
Input
−
5 V tolerant
DRST
Input
Reset signal input for on-chip debugging
5 V tolerant
Note
P56/INTP05
−
41
−
−
53
μPD70F3770, 70F3771 only
Remark
JG3-H: V850ES/JG3-H, JH3-H: V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 39 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 2 PIN FUNCTIONS
(3/9)
Pin Name
I/O
Function
Alternate Function
Pin No.
JG3-H JH3-H
EVDD
−
−
Positive power supply for external devices
(same potential as VDD)
EVTT0
EVTAB1
Input
Input
FLMD0
Input
FLMD1
Input
HLDAK
Output
34, 63, 46, 61,
80
85,107
P94/TIAA31/TOAA31/TENC00
46
−
P94/TIAA31/TOAA31/TENC00/A4
−
58
P65/TOAB1B3/CS3
70
−
P65/TOAB1B3
−
95
8
12
PDL5/AD5
76
103
Bus hold acknowledge output
PCM2
−
10
External event count input of TMT0
External event count input of TAB1
−
Flash memory programming mode setting pin
HLDRQ
Input
Bus hold request input
PCM3
−
11
INTP00
Input
External interrupt request input
P00
−
8
(maskable, analog noise elimination)
P01
−
9
P03/ADTRG/UCLK
7
7
P04
20
26
P05
21
27
P56/DRST
41
−
P24
−
36
INTP01
INTP02
INTP03
INTP04
Analog noise elimination or digital noise
elimination selectable for INTP02 pin
5 V tolerant (INTP00 to INTP05, INTP07 to
INTP10)
INTP05
INTP06
P25
−
28
INTP07
P30/TXDC0/SOF4
25
37
INTP08
P31/RXDC0/SIF4
26
38
INTP09
P34/TIAA10/TOAA10/TOAA1OFF
29
41
INTP10
P42/SCKF0
24
31
INTP11
P96/TIAA21/TOAA21/A6
−
62
P96/TIAA21/TOAA21
48
−
P98/SOF1
50
−
P98/SOF1/A8
−
64
P99/SCKF1
51
−
P99/SCKF1/A9
−
65
P910/SIF3/TXDC2
52
−
P910/SIF3/TXDC2/A10
−
66
P911/SOF3/RXDC2
53
−
P911/SOF3/RXDC2/A11
−
67
P913/TOAB1OFF
55
−
P913/TOAB1OFF/A13
−
69
P914/TIAA51/TOAA51
56
−
P914/TIAA51/TOAA51/A14
−
70
P915/TIAA50/TOAA50
57
−
P915/TIAA50/TOAA50/A15
−
71
INTP12
INTP13
INTP14
INTP15
INTP16
INTP17
INTP18
Remark
JG3-H: V850ES/JG3-H, JH3-H: V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 40 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 2 PIN FUNCTIONS
(4/9)
Pin Name
I/O
Function
Alternate Function
Pin No.
JG3-H JH3-H
Key interrupt input. (on-chip analog noise
P50/TIAB01/TOAB01/RTP00
eliminator)
/UDMARQ1
5 V tolerant (KR0 to KR5)
P51/TIAB02/TOAB02/RTP01
35
47
36
48
P52/TIAB03/TOAB03/RTP02/DDI
37
−
P20/TIAB03/TOAB03/RTP02
−
32
P53/SIF2/TIAB00/TOAB00/RTP03/DDO
38
−
P21/SIF2/TIAB00/TOAB00/RTP03
−
33
KR4
P54/SOF2/RTP04/DCK
39
−
P22/SOF2/RTP04
−
34
KR5
P55/SCKF2/RTP05/DMS
40
−
P23/SCKF2/RTP05
−
35
P90/TXDC1/SDA02
42
−
P90/TXDC1/SDA02/A0
−
54
P91/RXDC1/SCL02
43
−
P91/RXDC1/SCL02/A1
−
55
P02
6
6
KR0
Input
KR1
/UDMARQ1
KR2
KR3
KR6
KR7
NMI
Input
External interrupt input.
(non-maskable, analog noise elimination)
5 V tolerant
NC
−
RD
Output
REGC
−
−
24, 25
P61/TOAB1B1/TIAB10/TOAB10
−
66
−
PCT4
−
87
−
10, 61
14, 83
−
14
18
P35/TIAA11/TOAA11
30
42
P33/TIAA01/TOAA01/RTCDIV
28
40
P33/TIAA01/TOAA01/RTCCL
28
40
Non-Connection (Leave open.)
Read strobe signal output for external memory
Connection of regulator output stabilization
capacitance (4.7 μF: recommended value)
RESET
Input
RTC1HZ
Output
System reset input
Real-time counter correction clock (1 Hz) output.
5 V tolerant.
RTCCL
Output
Real-time counter clock (32 kHz primary
oscillation) output. 5 V tolerant.
RTCDIV
Output
Real-time counter clock (32 kHz division) output.
5 V tolerant.
RTP00
RTP01
RTP02
Output
Real-time output port
P50/TIAB01/KR0/TOAB01/UDMARQ1
35
47
N-ch open-drain output selectable
P51/TIAB02/KR1/TOAB02/UDMAAK1
36
48
P52/TIAB03/KR2/TOAB03/DDI
37
−
P20/TIAB03/KR2/TOAB03
−
32
P53/SIF2/TIAB00/KR3/TOAB00/DDO
38
−
P21/SIF2/TIAB00/KR3/TOAB00
−
33
P54/SOF2/KR4/DCK
39
−
P22/SOF2/KR4
−
34
P55/SCKF2/KR5/DMS
40
−
P23/SCKF2/KR5
−
35
5 V tolerant
RTP03
RTP04
RTP05
Remark
JG3-H: V850ES/JG3-H, JH3-H: V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 41 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 2 PIN FUNCTIONS
(5/9)
Pin Name
I/O
Function
Alternate Function
Pin No.
JG3-H JH3-H
RXDC0
Input
RXDC1
Serial receive data input (UARTC0 to UARTC4)
P31/SIF4/INTP08
26
5 V tolerant
P91/KR7/SCL02
43
−
P91/KR7/SCL02/A1
−
55
P911/SOF3/INTP15
53
−
−
67
32
44
RXDC2
P911/SOF3/INTP15/A11
Note
RXDC3
P37/SDA00/CRXD0
RXDC4
SCKF0
I/O
SCKF1
Serial clock I/O (CSIF0 to CSIF4)
N-ch open-drain output selectable
5 V tolerant (SCKF0, SCKF2, SCKF4)
SCKF2
SCKF3
SCKF4
SCL00
/UDMAAK0
P41/SOF0/SCL01
23
30
P42/INTP10
24
31
P99/INTP13
51
−
P99/INTP13/A9
−
65
P55/KR5/RTP05/DMS
40
−
P23/KR5/RTP05
−
35
P912
54
−
P912/A12
−
68
27
39
31
43
P32/ASCKC0/TIAA00/TOAA00
2
2
38
Note
P36/TXDC3/CTXD0
SCL01
Serial clock I/O (I C00 to I C02)
N-ch open-drain output selectable
P41/SOF0/RXDC4
23
30
SCL02
5 V tolerant (SCL00, SCL01)
P91/KR7/RXDC1
43
−
−
55
I/O
/UDMARQ0
P91/KR7/RXDC1/A1
SDA00
I/O
SDA01
2
2
Serial transmit/receive data I/O (I C00 to I C02)
N-ch open-drain output selectable
5 V tolerant (SDA00, SDA01)
SDA02
32
44
P40/SIF0/TXDC4
/UDMAAK0
22
29
P90/KR6/TXDC1
42
−
P90/KR6/TXDC1/A0
−
54
Serial receive data input (CSIF0 to CSIF4)
P40/TXDC4/SDA01
22
29
5 V tolerant (SIF0, SIF2, SIF4)
P97/TIAA20/TOAA20
49
−
P97/TIAA20/TOAA20/A7
−
63
SIF2
P53/TIAB00/KR3/TOAB00/RTP03/DDO
38
−
P21/TIAB00/KR3/TOAB00/RTP03
−
33
SIF3
P910/TXDC2/INTP14
52
−
P910/TXDC2/INTP14/A10
−
66
P31/RXDC0/INTP08
26
38
P41/RXDC4/SCL01
23
30
P98/INTP12
50
−
P98/INTP12/A8
−
64
P54/KR4/RTP04/DCK
39
−
P22/KR4/RTP04
−
34
P911/RXDC2/INTP15
53
−
P911/RXDC2/INTP15/A11
−
67
P30/TXDC0/INTP07
25
37
SIF0
Input
P37/RXDC3/CRXD0
Note
SIF1
SIF4
SOF0
SOF1
Output
Serial transmit data output (CSIF0 to CSIF4)
N-ch open-drain output selectable
5 V tolerant (SOF0, SOF2, SOF4)
SOF2
SOF3
SOF4
Note μPD70F3770, 70F3771 only
Remark
JG3-H: V850ES/JG3-H, JH3-H: V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 42 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 2 PIN FUNCTIONS
(6/9)
Pin Name
I/O
Function
Alternate Function
Pin No.
JG3-H JH3-H
TECR0
Input
TENC00
TMT0 encoder clear input
TMT0 encoder input
TENC01
TIAA00
Input
External event count input/capture trigger
P93/TIT00/TOT00
45
−
P93/TIT00/TOT00/A3
−
57
P94/TIAA31/TOAA31/EVTT0
46
−
P94/TIAA31/TOAA31/EVTT0/A4
−
58
P92/TIT01/TOT01
44
−
P92/TIT01/TOT01/A2
−
56
P32/ASCKC0/SCKF4/TOAA00
27
39
input/external trigger input (TAA0). 5 V tolerant
TIAA01
Capture trigger input (TAA0). 5 V tolerant.
P33/TOAA01/RTCDIV/RTCCL
28
40
TIAA10
External event count input/capture trigger
P34/TOAA10/TOAA1OFF/INTP09
29
41
input/external trigger input (TAA1). 5 V tolerant.
TIAA11
Capture trigger input (TAA1). 5 V tolerant.
P35/TOAA11/RTC1HZ
30
42
TIAA20
External event count input/capture trigger
P97/SIF1/TOAA20
49
−
input/external trigger input (TAA2)
P97/SIF1/TOAA20/A7
−
63
Capture trigger input (TAA2)
P96/TOAA21/INTP11
48
−
P96/TOAA21/INTP11/A6
−
62
External event count input/capture trigger
P95/TOAA30
47
−
input/external trigger input (TAA3)
P95/TOAA30/A5
−
59
TIAA31
Capture trigger input (TAA3)
P94/TOAA31/TENC00/EVTT0
46
−
P94/TOAA31/TENC00/EVTT0/A4
−
58
TIAA50
External event count input/capture trigger
P915/TOAA50/INTP18
57
−
input/external trigger input (TAA5)
P915/TOAA50/INTP18/A15
−
71
Capture trigger input (TAA5)
P914/TOAA51/INTP17
56
−
P914/TOAA51/INTP17/A14
−
70
External event count input/capture trigger
P53/SIF2/KR3/TOAB00/RTP03/DDO
38
−
input/external trigger input (TAB0). 5 V tolerant.
P21/SIF2/KR3/TOAB00/RTP03
−
33
TIAB01
Capture trigger input (TAB0)
P50/KR0/TOAB01/RTP00/UDMARQ1
35
47
TIAB02
5 V tolerant
P51/KR1/TOAB02/RTP01/UDMAAK1
36
48
P52/KR2/TOAB03/RTP02/DDI
37
−
TIAA21
TIAA30
TIAA51
TIAB00
Input
TIAB03
TIAB10
Input
P20/KR2/TOAB03/RTP02
−
32
Capture trigger input (TAB1)
P61/TOAB1B1/TOAB10/RD
66
−
5 V tolerant
P61/TOAB1B1/TOAB10
−
91
P60/TOAB1T1/TOAB11/WAIT
65
−
P60/TOAB1T1/TOAB11
−
90
P62/TOAB1T2/TOAB12/ASTB
67
−
P62/TOAB1T2/TOAB12
−
92
P64/TOAB1T3/TOAB13/CS2
69
−
P64/TOAB1T3/TOAB13
−
94
TIAB11
TIAB12
TIAB13
Remark
JG3-H: V850ES/JG3-H, JH3-H: V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 43 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 2 PIN FUNCTIONS
(7/9)
Pin Name
I/O
Function
Alternate Function
Pin No.
JG3-H JH3-H
TIT00
Input
TIT01
Input
Output
TOAA00
TOAA01
P93/TECR0/TOT00
45
−
P93/TECR0/TOT00/A3
−
57
P92/TENC01/TOT01
44
−
P92/TENC01/TOT01/A2
−
56
Timer output (TAA0)
P32/ASCKC0/SCKF4/TIAA00
27
39
N-ch open-drain output selectable
P33/TIAA01/RTCDIV/RTCCL
28
40
TMT0 external trigger input/capture trigger input
TMT0 capture trigger input
5 V tolerant.
TOAA10
Timer output (TAA1)
P34/TIAA10/TOAA1OFF/INTP09
29
41
TOAA11
N-ch open-drain output selectable
P35/TIAA11/RTC1HZ
30
42
P34/TIAA10/TOAA10/INTP09
29
41
P97/SIF1/TIAA20
49
−
P97/SIF1/TIAA20/A7
−
63
P96/TIAA21/INTP11
48
−
P96/TIAA21/INTP11/A6
−
62
Timer output (TAA3)
P95/TIAA30
47
−
N-ch open-drain output selectable
P95/TIAA30/A5
−
59
P94/TIAA31/TENC00/EVTT0
46
−
P94/TIAA31/TENC00/EVTT0/A4
−
58
Timer output (TAA5)
P915/TIAA50/INTP18
57
−
N-ch open-drain output selectable
P915/TIAA50/INTP18/A15
−
71
P914/TIAA51/INTP17
56
−
P914/TIAA51/INTP17/A14
−
70
Timer output (TAB0)
P53/SIF2/TIAB00/KR3/RTP03/DDO
38
−
N-ch open-drain output selectable
P21/SIF2/TIAB00/KR3/RTP03
−
33
5 V tolerant.
TOAA1OFF
Input
TAA1 high-impedance output control signal input
5 V tolerant.
TOAA20
Output
Timer output (TAA2)
N-ch open-drain output selectable
TOAA21
TOAA30
TOAA31
TOAA50
TOAA51
TOAB00
Output
5 V tolerant.
TOAB01
P50/TIAB01/KR0/RTP00/UDMARQ1
35
47
TOAB02
P51/TIAB02/KR1/RTP01/UDMAAK1
36
48
TOAB03
P52/TIAB03/KR2/RTP02/DDI
37
−
P20/TIAB03/KR2/RTP02
−
32
TAB1 high-impedance output control signal input
P913/INTP16
55
−
5 V tolerant.
P913/INTP16/A13
−
69
Timer output (TAB1)
P61/TOAB1B1/TIAB10/RD
66
−
N-ch open-drain output selectable
P61/TOAB1B1/TIAB10
−
91
P60/TOAB1T1/TIAB11/WAIT
65
−
P60/TOAB1T1/TIAB11
−
90
TOAB12
P62/TOAB1T2/TIAB12/ASTB
67
−
P62/TOAB1T2/TIAB12
−
92
TOAB13
P64/TOAB1T3/TIAB13/CS2
69
−
P64/TOAB1T3/TIAB13
−
94
TOAB1OFF
TOAB10
TOAB11
Remark
Input
Output
5 V tolerant.
JG3-H: V850ES/JG3-H, JH3-H: V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 44 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 2 PIN FUNCTIONS
(8/9)
Pin Name
I/O
Function
Alternate Function
Pin No.
JG3-H JH3-H
TOAB1B1
Output
Pulse signal output for 6-phase PWM low-arm of
P61/TIAB10/TOAB10/RD
66
−
TAB1
P61/TIAB10/TOAB10
−
91
P63/TRGAB1/CS0
68
−
P63/TRGAB1
−
93
P65/EVTAB1/CS3
70
−
P65/EVTAB1
−
95
Pulse signal output for 6-phase PWM high-arm
P60/TOAB11/TIAB11/WAIT
65
−
of TAB1
P60/TIAB11/TOAB11
−
90
TOAB1B2
TOAB1B3
TOAB1T1
Output
TOAB1T2
TOAB1T3
TOT00
Output
TMT0 timer output
TOT01
TRGAB1
Input
TXDC0
Output
TXDC1
External trigger input of TAB1
P62/TIAB12/TOAB12/ASTB
67
−
P62/TIAB12/TOAB12
−
92
P64/TOAB13/TIAB13/CS2
69
−
P64/TIAB13/TOAB13
−
94
P93/TECR0/TIT00
45
−
P93/TECR0/TIT00/A3
−
57
P92/TENC01/TIT01
44
−
P92/TENC01/TIT01/A2
−
56
P63/TOAB1B2/CS0
68
−
P63/TOAB1B2
−
93
37
Serial transmit data output (UARTC0 to
P30/SOF4/INTP07
25
UARTC4)
P90/KR6/SDA02
42
P90/KR6/SDA02/A0
−
54
P910/SIF3/INTP14
52
−
−
66
31
43
22
29
7
7
32
44
N-ch open-drain output selectable
5 V tolerant (TXDC0, TXDC3, TXDC4)
TXDC2
P910/SIF3/INTP14/A10
TXDC3
P36/SCL00/CTXD0
TXDC4
P40/SIF0/SDA01
UCLK
Input
UDMAAK0
Output
UDMAAK1
UDMARQ0
Input
UDMARQ1
UDMF
I/O
UDPF
USB clock signal input. 5 V tolerant.
DMA acknowledge for USB. 5 V tolerant.
Note
/UDMARQ0
P03/INTP02/ADTRG
P37/RXDC3/SDA00/CRXD0
Note
DMA acknowledge for USB. 5 V tolerant.
P51/TIAB02/KR1/TOAB02/RTP01
36
48
DMA request for USB. 5 V tolerant.
P36/TXDC3/SCL00/CTXD0
31
43
DMA request for USB. 5 V tolerant.
P50/TIAB01/KR0/TOAB01/RTP00
35
47
Note
USB data I/O (−) function
−
17
21
USB data I/O (+) function
−
18
22
UVDD
−
3.3 V Positive power supply for USB
−
19
23
VDD
−
Positive power supply pin for internal unit
−
9, 60
13, 82
VSS
−
Ground potential for internal unit
−
11, 33
15, 45
62, 79
60, 84
106
Note μPD70F3770, 70F3771 only
Remark
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CHAPTER 2 PIN FUNCTIONS
(9/9)
Pin Name
I/O
Function
Alternate Function
Pin No.
JG3-H JH3-H
WAIT
WR0
Input
Output
WR1
X1
Input
X2
−
XT1
Input
XT2
−
Remark
P60/TOAB1T1/TIAB11/TOAB11
65
−
PCM0
−
89
Write strobe for external memory (lower 8 bits)
PCT0
58
76
Write strove for external memory (higher 8 bits)
PCT1
59
77
−
12
16
−
13
17
External wait input
Connection of resonator for main clock
Connection of resonator for subclock
−
15
19
−
16
20
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2.2
CHAPTER 2 PIN FUNCTIONS
Pin States
The operation states of pins in the various operation modes are described below.
Table 2-2. Pin Operation States in Various Modes
Pin Name
When Power
During
Is Turned
Note 1
On
Reset
Mode
STOP
IDLE1,
HALT
Note 2
(Other than
IDLE2,
Mode
Note 2
Idle State
Note
Bus Hold
3
Sub-IDLE
When Power
Mode
Note 2
Is Turned
On)
DRST
Pull down
Pull down
Note
Held
Held
Held
Held
Held
Held
Held
Hi-Z
Held
Held
Hi-Z
Hi-Z
Held
Hi-Z
−
−
−
−
−
Operating
L
L
Operating
Operating
H
H
H
Hi-Z
4
P10/ANO0, P11/ANO1
AD0 to AD15
Undefined
Hi-Z
Note 5
Hi-Z
Hi-Z
Note 5
Notes 6, 7
Notes 6,
Undefined
A0 to A15
8
Undefined
A16 to A21
Note
6
WAIT
CLKOUT
Note 6
WR0, WR1
H
RD
ASTB
Operating
HLDAK
Note 6
L
−
−
−
Operating
Held
Held
Held
Held
HLDRQ
Other port pins
Hi-Z
Hi-Z
Held
Notes 1. Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower limit)
when the power is turned on.
2. Operates while alternate functions are operating.
3. The state of the pins in the idle state inserted after the T3 state is shown.
4. Pulled down during external reset. During internal reset by the watchdog timer or clock monitor, etc., the state
of this pin differs according to the OCDM.OCDM0 bit setting.
5. The bus control pins function alternately as port pins, so they are initialized to the input mode (port mode).
6. Operates even in the HALT mode, during DMA operation.
7. In separate bus output function:
Hi-Z
In multiplexed bus mode: Undefined
8. In separate bus output function
Remark
Hi-Z: High impedance
Held: The state during the immediately preceding external bus cycle is held.
L:
Low-level output
H:
High-level output
−:
Input without sampling (not acknowledged)
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2.3
CHAPTER 2 PIN FUNCTIONS
Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins
Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (1/4)
Pin
Alternate Function
P00
P01
I/O Circuit
Recommended Connection
JG3-H JH3-H
Type
Name
10-D
INTP00
Input:
INTP01
Independently connect to EVDD or VSS
−
√
via a resistor.
−
√
√
√
Output: Leave open.
P02
NMI
P03
INTP02/ADTRG/UCLK
√
√
P04
INTP03
√
√
P05
INTP04
P10
ANO0
P11
12-D
Input:
ANO1
√
√
Independently connect to AVREF1 or
√
√
AVSS via a resistor.
√
√
Independently connect to EVDD or VSS
−
√
via a resistor.
−
√
−
√
Output: Leave open.
P20
P21
TIAB03/KR2/TOAB03/RTP02
10-D
Input:
SIF2/TIAB00/KR3/TOAB00/RTP03
Output: Leave open.
P22
SOF2/KR4/RTP04
P23
SCKF2/KR5/RTP05
−
√
P24
INTP05
−
√
P25
INTP06
−
√
P30
TXDC0/SOF4/INTP07
Independently connect to EVDD or VSS
√
√
P31
RXDC0/SIF4/INTP08
via a resistor.
√
√
√
√
10-D
Input:
Output: Leave open.
P32
ASCKC0/SCKF4/TIAA00/TOAA00
P33
TIAA01/TOAA01/RTCDIV/RTCCL
√
√
P34
TIAA10/TOAA10/TOAA1OFF/INTP09
√
√
P35
TIAA11/TOAA11/RTC1HZ
√
√
√
√
√
√
Independently connect to EVDD or VSS
√
√
via a resistor.
√
√
√
√
Independently connect to EVDD or VSS
√
√
via a resistor.
√
√
√
−
P36
P37
TXDC3/SCL00/CTXD0
Note
RXDC3/SDA00/CRXD0
P40
SIF0/TXDC4/SDA01
P41
SOF0/RXDC4/SCL01
/UDMARQ0
Note
/UDMAAK0
P42
SCKF0/INTP10
P50
TIAB01/KR0/TOAB01/RTP00/UDMARQ1
P51
10-D
Input:
Output: Leave open.
10-D
Input:
TIAB02/KR1/TOAB02/RTP01/UDMAAK1
Output: Leave open.
P52
TIAB03/KR2/TOAB03/RTP02/DDI
P53
SIF2/TIAB00/KR3/TOAB00/RTP03/DDO
√
−
P54
SOF2/KR4/RTP04/DCK
√
−
√
−
√
−
P55
SCKF2/KR5/RTP05/DMS
P56
INTP05/DRST
10-N
Input:
Independently connect to VSS via a
resistor. Fixing to VDD level is
prohibited.
Output: Leave open.
Internally pull-down after reset by
RESET pin.
Note μPD70F3770, 70F3771 only
Remark
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CHAPTER 2 PIN FUNCTIONS
Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (2/4)
Pin
Name
P60
Alternate Function
TOAB1T1/TIAB11/TOAB11/WAIT
I/O Circuit
Type
10-D
P62
P63
P64
P65
Input:
Independently connect to EVDD or VSS
via a resistor.
Output: Leave open.
JG3-H JH3-H
√
−
−
√
TOAB1B1/TIAB10/TOAB10/RD
√
−
TOAB1B1/TIAB10/TOAB10
−
√
TOAB1T2/TIAB12/TOAB12/ASTB
√
−
TOAB1T2/TIAB12/TOAB12
−
√
TOAB1B2/TRGAB1/CS0
√
−
TOAB1B2/TRGAB1
−
√
TOAB1T3/TIAB13/TOAB13/CS2
√
−
TOAB1T3/TIAB13/TOAB13
−
√
TOAB1B3/EVTAB1/CS3
√
−
TOAB1B3/EVTAB1
−
√
TOAB1T1/TIAB11/TOAB11
P61
Recommended Connection
P70 to
P711
ANI0 to ANI11
11-G
Input:
Independently connect to AVREF0 or
AVSS via a resistor.
Output: Leave open.
√
√
P90
KR6/TXDC1/SDA02
10-D
Input:
Independently connect to EVDD or VSS
via a resistor.
Output: Leave open.
√
−
−
√
KR6/TXDC1/SDA02/A0
P91
P92
P93
P94
P95
P96
P97
P98
P99
P910
P911
P912
Remark
KR7/RXDC1/SCL02
√
−
KR7/RXDC1/SCL02/A1
−
√
TENC01/TIT01/TOT01
√
−
TENC01/TIT01/TOT01/A2
−
√
TECR0/TIT00/TOT00
√
−
TECR0/TIT00/TOT00/A3
−
√
TIAA31/TOAA31/TENC00/EVTT0
√
−
TIAA31/TOAA31/TENC00/EVTT0/A4
−
√
TIAA30/TOAA30
√
−
TIAA30/TOAA30/A5
−
√
TIAA21/TOAA21/INTP11
√
−
TIAA21/TOAA21/INTP11/A6
−
√
SIF1/TIAA20/TOAA20
√
−
SIF1/TIAA20/TOAA20/A7
−
√
SOF1/INTP12
√
−
SOF1/INTP12/A8
−
√
SCKF1/INTP13
√
−
SCKF1/INTP13/A9
−
√
SIF3/TXDC2/INTP14
√
−
SIF3/TXDC2/INTP14/A10
−
√
SOF3/RXDC2/INTP15
√
−
SOF3/RXDC2/INTP15/A11
−
√
SCKF3
√
−
SCKF3/A12
−
√
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CHAPTER 2 PIN FUNCTIONS
Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (3/4)
Pin
Alternate Function
Name
P913
I/O Circuit
Recommended Connection
Independently connect to EVDD or VSS
√
−
via a resistor.
−
√
TIAA51/TOAA51/INTP17
√
−
TIAA51/TOAA51/INTP17/A14
−
√
TIAA50/TOAA50/INTP18
√
−
TIAA50/TOAA50/INTP18/A15
−
√
Independently connect to EVDD or VSS
−
√
via a resistor.
√
√
−
√
TOAB1OFF/INTP16
10-D
Input:
TOAB1OFF/INTP16/A13
Output: Leave open.
P914
P915
PCM0
PCM1
WAIT
HLDAK
PCM3
HLDRQ
PCS0
CS0
Input:
Output: Leave open.
5
Input:
CS2
PCS3
CS3
PCT0
WR0
PCT1
5
CLKOUT
PCM2
PCS2
JG3-H JH3-H
Type
RD
PCT6
ASTB
√
−
√
via a resistor.
−
√
−
√
Independently connect to EVDD or VSS
√
√
via a resistor.
√
√
−
√
−
√
−
√
√
√
√
√
√
√
Output: Leave open.
5
Input:
WR1
PCT4
−
Independently connect to EVDD or VSS
Output: Leave open.
PDH0 to A16 to A23
5
Input:
PDH7
Independently connect to EVDD or VSS
via a resistor.
Output: Leave open.
PDL0 to AD0 to AD4
5
PDL4
PDL5
Input:
Independently connect to EVDD or VSS
via a resistor.
Output: Leave open.
AD5/FLMD1
PDL6 to AD6 to AD15
PDL15
AVREF0
−
−
Always connect to power supply. (The same
√
√
√
√
√
√
AVREF1
−
−
applies during standby.)
AVSS
−
−
Always directly connect to ground. (The same
applies during standby.)
DCK
−
−
Always connect to power supply. (The same
−
√
−
√
DDI
−
−
applies during standby.)
DDO
−
−
Leave open.
−
√
DMS
−
−
Always connect to power supply. (The same
−
√
−
√
√
√
√
√
applies during standby.)
DRST
−
−
Always directly connect to ground. (The same
applies during standby.)
EVDD
−
−
Always connect to power supply. (The same
applies during standby.)
FLMD0
Remark
−
−
Directly connect to VSS in other than flash mode.
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CHAPTER 2 PIN FUNCTIONS
Table 2-3. Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (4/4)
Pin
Alternate Function
Name
I/O Circuit
Recommended Connection
JG3-H JH3-H
Type
REGC
−
−
Connect to regulator output stabilization capacitor.
√
√
RESET
−
2
−
√
√
UDMF
−
−
Always directly connect to ground via a resistor.
√
√
UDPF
−
−
Always directly connect to ground. (The same
√
√
√
√
√
√
√
√
applies during standby.)
UVDD
−
−
Always connect to power supply. (The same
applies during standby.)
VDD
−
−
Always connect to power supply. (The same
applies during standby.)
VSS
−
−
Always directly connect to ground. (The same
applies during standby.)
X1
−
−
−
√
√
X2
−
−
−
√
√
XT1
−
16-C
Connect to VSS via a resistor.
√
√
XT2
−
16-C
Leave open.
√
√
NC
−
−
Leave open.
−
√
Remark
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuits
Type 11-G
Type 2
AVREF0
Data
IN
P-ch
IN/OUT
Output
disable
N-ch
Schmitt-triggered input with hysteresis characteristics
AVSS
EVDD
Data
P-ch
VREF0
(Threshold voltage)
IN/OUT
Output
disable
P-ch
Comparator
+
_
Type 5
N-ch
N-ch
AVSS
Input enable
Type 12-D
VSS
AVREF1
Input
enable
Type 10-D
EVDD
Data
P-ch
Output
disable
N-ch
IN/OUT
AVSS
Data
P-ch
Input
enable
IN/OUT
Open drain
N-ch
Output
disable
Note
N-ch
VSS
Type 16-C
Feedback cut-off
Input
enable
P-ch
Type 10-N
EVDD
Data
P-ch
IN/OUT
Open drain
XT1
XT2
N-ch
Output
disable
Note
Input
enable
P-ch
Analog output
OCDM0 bit
VSS
N-ch
Note Hysteresis characteristics are not available in port mode.
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2.4
CHAPTER 2 PIN FUNCTIONS
Cautions
When the power is turned on, the following pins may output an undefined level temporarily even during reset.
• P10/ANO0 pin
• P11/ANO1 pin
• DDO pin (V850ES/JH3-H only)
• P53/SIF2/TIAB00/KR3/TOAB00/RTP03/DDO pin (V850ES/JG3-H only)
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CHAPTER 3 CPU FUNCTION
CHAPTER 3 CPU FUNCTION
The CPU of the V850ES/JG3-H and V850ES/JH3-H is based on RISC architecture and executes almost all instructions
with one clock by using a 5-stage pipeline.
3.1
Features
Minimum instruction execution time: 20.8 ns (operating with main clock (fXX) of 48 MHz: VDD = 2.85 to 3.6 V)
30.5 μs (operating with subclock (fXT) of 32.768 kHz)
Memory space
Program (physical address) space: 64 MB linear
Data (logical address) space:
4 GB linear
General-purpose registers: 32 bits × 32 registers
Internal 32-bit architecture
5-stage pipeline control
Multiplication/division instruction
Saturation operation instruction
32-bit shift instruction: 1 clock
Load/store instruction with long/short format
Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
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3.2
CHAPTER 3 CPU FUNCTION
CPU Register Set
The registers of the V850ES/JG3-H and V850ES/JH3-H can be classified into two types: general-purpose program
registers and dedicated system registers. All the registers are 32 bits wide.
For details, refer to the V850ES Architecture User’s Manual.
(1) Program register set
31
r0
(2) System register set
0
31
0
(Zero register)
EIPC
(Interrupt status saving register)
(Assembler-reserved register)
EIPSW
(Interrupt status saving register)
r3
(Stack pointer (SP))
FEPC
(NMI status saving register)
r4
(Global pointer (GP))
FEPSW (NMI status saving register)
r5
(Text pointer (TP))
r1
r2
r6
ECR
(Interrupt source register)
PSW
(Program status word)
CTPC
(CALLT execution status saving register)
r7
r8
r9
r10
r11
CTPSW (CALLT execution status saving register)
r12
r13
DBPC
r14
(Exception/debug trap status saving register)
DBPSW (Exception/debug trap status saving register)
r15
r16
CTBP
r17
(CALLT base pointer)
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
(Element pointer (EP))
r31
(Link pointer (LP))
31
PC
0
(Program counter)
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3.2.1
CHAPTER 3 CPU FUNCTION
Program register set
The program registers include general-purpose registers and a program counter.
(1) General-purpose registers (r0 to r31)
Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data
variable or an address variable.
However, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used.
r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the SLD and
SST instructions as a base pointer when these instructions access the memory. r1, r3 to r5, and r31 are implicitly
used by the assembler and C compiler. When using these registers, save their contents for protection, and then
restore the contents after using the registers. r2 is sometimes used by the real-time OS. If the real-time OS does
not use r2, it can be used as a register for variables.
Table 3-1. Program Registers
Name
Usage
Operation
r0
Zero register
Always holds 0.
r1
Assembler-reserved register
Used as working register to create 32-bit immediate data
r2
Register for address/data variable (if real-time OS does not use r2)
r3
Stack pointer
Used to create a stack frame when a function is called
r4
Global pointer
Used to access a global variable in the data area
r5
Text pointer
Used as register that indicates the beginning of a text area (area
where program codes are located)
r6 to r29
Register for address/data variable
r30
Element pointer
Used as base pointer to access memory
r31
Link pointer
Used when the compiler calls a function
PC
Program counter
Holds the instruction address during program execution
Remark
For further details on the r1, r3 to r5, and r31 that are used in the assembler and C compiler, refer to the
CA850 (C Compiler Package) Assembly Language User’s Manual.
(2) Program counter (PC)
The program counter holds the instruction address during program execution. The lower 32 bits of this register are
valid. Bits 31 to 26 are fixed to 0. A carry from bit 25 to 26 is ignored even if it occurs.
Bit 0 is fixed to 0. This means that execution cannot branch to an odd address.
31
PC
26 25
Fixed to 0
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1 0
Instruction address during program execution
0
Default value
00000000H
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3.2.2
CHAPTER 3 CPU FUNCTION
System register set
The system registers control the status of the CPU and hold interrupt information.
These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the
system register numbers listed below.
Table 3-2. System Register Numbers
System
System Register Name
Register
Operand Specification
LDSR Instruction STSR Instruction
Number
Note 1
0
Interrupt status saving register (EIPC)
1
Interrupt status saving register (EIPSW)
Note 1
Note 1
2
NMI status saving register (FEPC)
√
√
√
√
√
√
3
NMI status saving register (FEPSW)
√
√
4
Interrupt source register (ECR)
×
√
5
Program status word (PSW)
√
√
Reserved for future function expansion (operation is not guaranteed if these
×
×
√
√
6 to 15
Note 1
registers are accessed)
16
CALLT execution status saving register (CTPC)
17
CALLT execution status saving register (CTPSW)
√
√
Exception/debug trap status saving register (DBPC)
√
Note 2
19
Exception/debug trap status saving register (DBPSW)
√
Note 2
20
CALLT base pointer (CTBP)
√
√
Reserved for future function expansion (operation is not guaranteed if these
×
×
18
21 to 31
√
Note 2
√
Note 2
registers are accessed)
Notes 1. Because only one set of these registers is available, the contents of these registers must be saved by
program if multiple interrupts are enabled.
2. These registers can be accessed only during the interval between the execution of the DBTRAP instruction
or illegal opcode and DBRET instruction execution.
Caution
Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when
execution is returned to the main routine by the RETI instruction after interrupt servicing (this is
because bit 0 of the PC is fixed to 0). Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0).
Remark
√: Can be accessed
×: Access prohibited
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CHAPTER 3 CPU FUNCTION
(1) Interrupt status saving registers (EIPC and EIPSW)
EIPC and EIPSW are used to save the status when an interrupt occurs.
If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC,
and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI
status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
The address of the instruction next to the instruction under execution, except some instructions (see 23.8 Periods
in Which Interrupts Are Not Acknowledged by CPU), is saved to EIPC when a software exception or a maskable
interrupt occurs.
The current contents of the PSW are saved to EIPSW.
Because only one set of interrupt status saving registers is available, the contents of these registers must be saved
by program when multiple interrupts are enabled.
Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved for future function expansion (these bits are always
fixed to 0).
The value of EIPC is restored to the PC and the value of EIPSW to the PSW by the RETI instruction.
31
EIPC
0 0 0 0 0 0
31
EIPSW
26 25
0
Default value
0xxxxxxxH
(x: Undefined)
(Contents of saved PC)
8 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0
(Contents of
saved PSW)
Default value
000000xxH
(x: Undefined)
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CHAPTER 3 CPU FUNCTION
(2) NMI status saving registers (FEPC and FEPSW)
FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs.
If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status
word (PSW) are saved to FEPSW.
The address of the instruction next to the one of the instruction under execution, except some instructions, is saved
to FEPC when an NMI occurs.
The current contents of the PSW are saved to FEPSW.
Because only one set of NMI status saving registers is available, the contents of these registers must be saved by
program when multiple interrupts are enabled.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these bits are always
fixed to 0).
The value of FEPC is restored to the PC and the value of FEPSW to the PSW by the RETI instruction.
31
FEPC
26 25
0 0 0 0 0 0
0
31
FEPSW
Default value
0xxxxxxxH
(x: Undefined)
(Contents of saved PC)
8 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Default value
000000xxH
(x: Undefined)
(Contents of
saved PSW)
(3) Interrupt source register (ECR)
The interrupt source register (ECR) holds the source of an exception or interrupt if an exception or interrupt occurs.
This register holds the exception code of each interrupt source. Because this register is a read-only register, data
cannot be written to this register using the LDSR instruction.
31
16 15
ECR
Bit position
FECC
Bit name
0
EICC
Meaning
31 to 16
FECC
Exception code of non-maskable interrupt (NMI)
15 to 0
EICC
Exception code of exception or maskable interrupt
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Default value
00000000H
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CHAPTER 3 CPU FUNCTION
(4) Program status word (PSW)
The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction
execution) and the status of the CPU.
If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated
immediately after completion of LDSR instruction execution. However if the ID flag is set to 1, interrupt requests will
not be acknowledged while the LDSR instruction is being executed.
Bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0).
(1/2)
31
8 7 6 5 4 3 2 1 0
PSW
NP EP ID SAT CY OV S Z
RFU
Bit position
Flag name
Default value
00000020H
Meaning
31 to 8
RFU
Reserved field. Fixed to 0.
7
NP
Indicates that a non-maskable interrupt (NMI) is being serviced. This bit is set to 1 when an
NMI request is acknowledged, disabling multiple interrupts.
0: NMI is not being serviced.
1: NMI is being serviced.
6
Indicates that an exception is being processed. This bit is set to 1 when an exception occurs.
EP
Even if this bit is set, interrupt requests are acknowledged.
0: Exception is not being processed.
1: Exception is being processed.
5
Indicates whether a maskable interrupt can be acknowledged.
ID
0: Interrupt enabled
1: Interrupt disabled
4
Note
SAT
Indicates that the result of a saturation operation has overflowed and is saturated. Because
this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is
saturated, and is not cleared to 0 even if the subsequent operation result is not saturated.
Use the LDSR instruction to clear this bit. This flag is neither set to 1 nor cleared to 0 by
execution of an arithmetic operation instruction.
0: Not saturated
1: Saturated
3
Indicates whether a carry or a borrow occurs as a result of an operation.
CY
0: Carry or borrow does not occur.
1: Carry or borrow occurs.
2
OV
Note
Indicates whether an overflow occurs during operation.
0: Overflow does not occur.
1: Overflow occurs.
1
S
Note
Indicates whether the result of an operation is negative.
0: The result is positive or 0.
1: The result is negative.
0
Z
Indicates whether the result of an operation is 0.
0: The result is not 0.
1: The result is 0.
Remark
Also read Note on the next page.
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(2/2)
Note The result of the operation that has performed saturation processing is determined by the contents of the
OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is
performed.
Status of Operation Result
Result of Operation of
Flag Status
SAT
OV
S
Saturation Processing
Maximum positive value is exceeded
1
1
0
7FFFFFFFH
Maximum negative value is exceeded
1
1
1
80000000H
Positive (maximum value is not exceeded)
Holds value
0
0
Operation result itself
Negative (maximum value is not exceeded)
before operation
1
(5) CALLT execution status saving registers (CTPC and CTPSW)
CTPC and CTPSW are CALLT execution status saving registers.
When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and those
of the program status word (PSW) are saved to CTPSW.
The contents saved to CTPC are the address of the instruction next to CALLT.
The current contents of the PSW are saved to CTPSW.
Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved for future function expansion (fixed to 0).
31
CTPC
0 0 0 0 0 0
31
CTPSW
26 25
0
Default value
0xxxxxxxH
(x: Undefined)
(Saved PC contents)
8 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0
(Saved PSW
contents)
Default value
000000xxH
(x: Undefined)
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CHAPTER 3 CPU FUNCTION
(6) Exception/debug trap status saving registers (DBPC and DBPSW)
DBPC and DBPSW are exception/debug trap status registers.
If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those
of the program status word (PSW) are saved to DBPSW.
The contents to be saved to DBPC are the address of the instruction next to the one that is being executed when
an exception trap or debug trap occurs.
The current contents of the PSW are saved to DBPSW.
This register can be read or written only during the interval between the execution of the DBTRAP instruction or
illegal opcode and the DBRET instruction.
Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (fixed to 0).
The value of DBPC is restored to the PC and the value of DBPSW to the PSW by the DBRET instruction.
31
DBPC
26 25
0 0 0 0 0 0
0
31
DBPSW
Default value
0xxxxxxxH
(x: Undefined)
(Saved PC contents)
8 7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Default value
000000xxH
(x: Undefined)
(Saved PSW
contents)
(7) CALLT base pointer (CTBP)
The CALLT base pointer (CTBP) is used to specify a table address or generate a target address (bit 0 is fixed to 0).
Bits 31 to 26 of this register are reserved for future function expansion (fixed to 0).
31
CTBP
26 25
0 0 0 0 0 0
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0
(Base address)
0
Default value
0xxxxxxxH
(x: Undefined)
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3.3
CHAPTER 3 CPU FUNCTION
Operation Modes
The V850ES/JG3-H and V850ES/JH3-H have the following operation modes.
(1) Normal operation mode
In this mode, each pin related to the bus interface is set to the port mode after system reset has been released.
Execution branches to the reset entry address of the internal ROM, and then instruction processing is started.
(2) Flash memory programming mode
In this mode, the internal flash memory can be programmed by using a flash programmer.
(3) On-chip debug mode
The V850ES/JG3-H and V850ES/JH3-H are provided with an on-chip debug function that employs the JTAG (Joint
Test Action Group) communication specifications.
For details, see CHAPTER 32 ON-CHIP DEBUG FUNCTION.
3.3.1
Specifying operation mode
Specify the operation mode by using the FLMD0 and FLMD1 pins.
In the normal mode, make sure that a low level is input to the FLMD0 pin when reset is released.
In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash
programmer is connected, but it must be input from an external circuit in the self-programming mode.
Operation When Reset Is Released
Operation Mode After Reset
FLMD0
FLMD1
L
×
Normal operation mode
H
L
Flash memory programming mode
H
H
Setting prohibited
Remark
L: Low-level input
H: High-level input
×: Don’t care
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3.4
3.4.1
CHAPTER 3 CPU FUNCTION
Address Space
CPU address space
For instruction addressing, up to a combined total of 16 MB of external memory area and internal ROM area, plus an
internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand addressing
(data access), up to 4 GB of a linear address space (data space) is supported. The 4 GB address space, however, is
viewed as 64 images of a 64 MB physical address space. This means that the same 64 MB physical address space is
accessed regardless of the value of bits 31 to 26.
Figure 3-1. Image on Address Space
Image 63
4 GB
Data space
Peripheral I/O area
Program space
Image 1
Use-prohibited area
Internal RAM area
Internal RAM area
Use-prohibited area
64 MB
Use-prohibited area
64 MB
Image 0
External memory area
External memory area
Internal ROM area
(external memory area)
16 MB
Internal ROM area
(external memory area)
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CHAPTER 3 CPU FUNCTION
Wraparound of CPU address space
(1) Program space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The
higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation.
Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are
contiguous addresses. That the highest address and the lowest address of the program space are contiguous in
this way is called wraparound.
Caution
Because the 4 KB area of addresses 03FFF000H to 03FFFFFFH is an on-chip peripheral I/O area,
instructions cannot be fetched from this area. Therefore, do not execute an operation in which
the result of a branch address calculation affects this area.
00000001H
Program space
00000000H
(+) direction
(−) direction
03FFFFFFH
03FFFFFEH
Program space
(2) Data space
The result of an operand address calculation operation that exceeds 32 bits is ignored.
Therefore, the highest address of the data space, FFFFFFFFH, and the lowest address, 00000000H, are
contiguous, and wraparound occurs at the boundary of these addresses.
00000001H
Data space
00000000H
(+) direction
(−) direction
FFFFFFFFH
FFFFFFFEH
Data space
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3.4.3
CHAPTER 3 CPU FUNCTION
Memory map
The areas shown below are reserved in the V850ES/JG3-H and V850ES/JH3-H.
Figure 3-2. Data Memory Map (Physical Addresses)
03FFFFFFH
On-chip peripheral I/O area
(4 KB)
(80 KB)
03FEC000H
03FEBFFFH
03FFFFFFH
03FFF000H
03FFEFFFH
Internal RAM area
(60 KB)
Use prohibited
Note 2
Use prohibited
03FF0000H
03FEFFFFH
03FEF000H
03FEEFFFH
Programmable peripheral
I/O areaNote 3 or
use prohibitedNote 4
01000000H
00FFFFFFH
03FEC000H
003FFFFFH
Use prohibited
External memory area
(8 MB)
03000000H
02FFFFFFH
CS3
Data-only RAM area
(8 KB)
00280000H
0027FFFFH
Use prohibited
00250000H
0024FFFFH
00800000H
007FFFFFH
USB function area
External memory area
(4 MB)
00200000H
CS2
00400000H
003FFFFFH
00200000H
001FFFFFH
001FFFFFH
External memory area
(2 MB)
(2 MB)
00000000H
CS1Note 1
CS0
External memory area
(1 MB)
Internal ROM areaNote 5
(1 MB)
00100000H
000FFFFFH
00000000H
Notes 1. CS1 is not provided as an external signal of the V850ES/Jx3-H; it is used internally as a chip select
signal for the USB.
2. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because they overlap an on-chip
peripheral I/O area.
3. The programmable peripheral I/O area is seen as 256 MB areas in the 4 GB address space.
4. In on-chip CAN controller products, addresses 03FEC000H to 03FEEFFFH are assigned to
addresses 03FEC000H to 03FECBFFH as a programmable peripheral I/O area. In other products,
use of this area is prohibited.
5. This area is used as an external memory area when data write access to this area is executed.
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Figure 3-3. Program Memory Map
03FFFFFFH
03FFF000H
03FFEFFFH
Use prohibited
(program fetch prohibited area)
Internal RAM area (60 KB)
03FF0000H
03FEFFFFH
Use prohibited
(program fetch prohibited area)
01000000H
00FFFFFFH
External memory area
(14 MB)
00200000H
001FFFFFH
00100000H
000FFFFFH
00000000H
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External memory area
(1 MB)
Internal ROM area
(1 MB)
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3.4.4
CHAPTER 3 CPU FUNCTION
Areas
(1) Internal ROM area
Up to 1 MB is reserved as an internal ROM area.
(a) Internal ROM (256 KB)
256 KB are allocated to addresses 00000000H to 0003FFFFH in the following products.
Accessing addresses 00040000H to 000FFFFFH is prohibited.
• μPD70F3760, 70F3770, 70F3765, 70F3771
Figure 3-4. Internal ROM Area (256 KB)
000FFFFFH
Access-prohibited
area
00040000H
0003FFFFH
Internal ROM
(256 KB)
00000000H
(b) Internal ROM (384 KB)
384 KB are allocated to addresses 00000000H to 0005FFFFH in the following products.
Accessing addresses 00060000H to 000FFFFFH is prohibited.
• μPD70F3761, 70F3766
Figure 3-5. Internal ROM Area (384 KB)
000FFFFFH
Access-prohibited
area
00060000H
0005FFFFH
Internal ROM
(384 KB)
00000000H
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CHAPTER 3 CPU FUNCTION
(c) Internal ROM (512 KB)
512 KB are allocated to addresses 00000000H to 0007FFFFH in the following products.
Accessing addresses 00080000H to 000FFFFFH is prohibited.
• μPD70F3762, 70F3767
Figure 3-6. Internal ROM Area (512 KB)
000FFFFFH
Access-prohibited
area
00080000H
0007FFFFH
Internal ROM
(512 KB)
00000000H
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CHAPTER 3 CPU FUNCTION
(2) Internal RAM area
Up to 60 KB are reserved as the internal RAM area.
The V850ES/JG3-H and V850ES/JH3-H include a data-only RAM of 8 KB in addition to the internal RAM.
The RAM capacity of V850ES/JG3-H and V850ES/JH3-H is as follows.
Table 3-3 RAM area
Generic Name
V850ES/JG3-H
V850ES/JH3-H
Product Name
Internal RAM
Data-only RAM
Total RAM
μPD70F3760, 70F3770
32 KB
μPD70F3761
40 KB
48 KB
μPD70F3762
48 KB
56 KB
μPD70F3765, 70F3771
32 KB
40 KB
μPD70F3766
40 KB
48 KB
μPD70F3767
48 KB
56KB
8 KB
40 KB
(a) Internal RAM (32 KB)
32 KB are allocated to addresses 03FF7000H to 03FFEFFFH in the following products.
Accessing addresses 03FF0000H to 03FF6FFFH is prohibited.
• μPD70F3760, 70F3770, 70F3765, 70F3771
Figure 3-7. Internal RAM Area (32 KB)
Physical address space
Logical address space
03FFEFFFH
FFFFEFFFH
Internal RAM
(32 KB)
03FF7000H
03FF6FFFH
FFFF7000H
FFFF6FFFH
Access-prohibited
area
03FF0000H
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FFFF0000H
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CHAPTER 3 CPU FUNCTION
(b) Internal RAM (40 KB)
40 KB are allocated to addresses 03FF5000H to 03FFEFFFH in the following products.
Accessing addresses 03FF0000H to 03FF4FFFH is prohibited.
• μPD70F3761, 70F3766
Figure 3-8. Internal RAM Area (40 KB)
Physical address space
Logical address space
FFFFEFFFH
03FFEFFFH
Internal RAM
(40 KB)
03FF5000H
03FF4FFFH
FFFF5000H
FFFF4FFFH
Access-prohibited
area
03FF0000H
FFFF0000H
(c) Internal RAM (48 KB)
48 KB are allocated to addresses 03FF3000H to 03FFEFFFH in the following products.
Accessing addresses 03FF0000H to 03FF2FFFH is prohibited.
• μPD70F3762, 70F3767
Figure 3-9. Internal RAM Area (48 KB)
Physical address space
Logical address space
FFFFEFFFH
03FFEFFFH
Internal RAM
(48 KB)
03FF3000H
03FF2FFFH
03FF0000H
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FFFF3000H
FFFF2FFFH
FFFF0000H
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CHAPTER 3 CPU FUNCTION
(d) Data-only RAM (8 KB)
A data-only RAM of 8 KB is allocated to addresses 00280000H to 00281FFFH in the V850ES/JG3-H and
V850ES/JH3-H.
Figure 3-10. Data-Only RAM Area (8 KB)
Logical address space
Access-prohibited
area
00282000H
00281FFFH
Data-only RAM
(8 KB)
Access-prohibited
area
Caution
00280000H
0027FFFFH
If using the data-only RAM area, the following two register setting are needed.
• Select the clock that be possible to supply the data-only RAM in the USB clock select register
(UCKSEL) (refer to 21.6.1(1))
• Set the data-only RAM operation to be enable in the USB function select register (UHCKMSK)
(refer to 21.6.1(3)) (UHCKMSK.UHMSK bit = 0)
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(3) On-chip peripheral I/O area
4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area.
Figure 3-11. On-Chip Peripheral I/O Area
Physical address space
Logical address space
03FFFFFFH
FFFFFFFFH
On-chip peripheral I/O area
(4 KB)
03FFF000H
FFFFF000H
Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the on-chip
peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area.
Cautions 1. When a register is accessed in word units, a word area is accessed twice in halfword units in
the order of lower area and higher area, with the lower 2 bits of the address ignored.
2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits
are undefined when the register is read, and data is written to the lower 8 bits.
3. Addresses not defined as registers are reserved for future expansion.
The operation is
undefined and not guaranteed when these addresses are accessed.
4. The internal ROM/RAM area and on-chip peripheral I/O area are assigned to successive
addresses.
When accessing the internal ROM/RAM area by incrementing or decrementing addresses
using a pointer operation or such, be careful not to access the on-chip peripheral I/O area by
mistakenly extending over the internal ROM/RAM area boundary.
(4) External memory area
13 MB (00100000H to 001FFFFFH, 00400000H to 00FFFFFFH) are allocated as the external memory area. For
details, see CHAPTER 5 BUS CONTROL FUNCTION.
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3.4.5
CHAPTER 3 CPU FUNCTION
Recommended use of address space
The architecture of the V850ES/JG3-H and V850ES/JH3-H requires that a register that serves as a pointer be secured
for address generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can
be directly accessed by an instruction for operand data. Because the number of general-purpose registers that can be
used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer
value is changed, as many general-purpose registers as possible can be secured for variables, and the program size can
be reduced.
(1) Program space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid.
Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H
unconditionally corresponds to the memory map.
To use the internal RAM area as the program space, access the following addresses.
Caution
If a branch instruction is at the upper limit of the internal RAM area, a prefetch operation (invalid
fetch) straddling the on-chip peripheral I/O area does not occur.
RAM Size
Access Address
48 KB
03FF3000H to 03FFEFFFH
40 KB
03FF5000H to 03FFEFFFH
32 KB
03FF7000H to 03FFEFFFH
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(2) Data space
With the V850ES/JG3-H and V850ES/JH3-H, it seems that there are sixty-four 64 MB address spaces on the 4 GB
CPU address space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and
allocated as an address.
(a) Application example of wraparound
If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32
KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can be
addressed by one pointer.
The zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers
dedicated to pointers.
Example: μPD70F3767
0007FFFFH
00007FFFH
Internal ROM area
32 KB
On-chip peripheral
I/O area
4 KB
Internal RAM area
28 KB
(R = ) 0 0 0 0 0 0 0 0 H
FFFFF000H
FFFFEFFFH
FFFF8000H
FFFF3000H
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Figure 3-12. Recommended Memory Map
Program space
Data space
FFFFFFFFH
On-chip
peripheral I/O
FFFFF000H
FFFFEFFFH
Internal RAM
FFFFFFFFH
FFFF0000H
FFFEFFFFH
On-chip
peripheral I/O
FFFFF000H
FFFFEFFFH
Internal RAM
FFFF3000H
FFFF2FFFH
FFFF0000H
FFFEFFFFH
04000000H
03FFFFFFH
Use prohibited
03FFF000H
03FFEFFFH
Internal RAM
Use prohibited
03FF3000H
03FF2FFFH
03FF0000H
03FEFFFFH
Use prohibited
Program space
64 MB
External
memory
01000000H
00FFFFFFH
00100000H
000FFFFFH
Internal ROM
00000000H
External
memory
00100000H
000FFFFFH
00080000H
0007FFFFH
00000000H
Remarks 1.
Internal ROM
Internal ROM
indicates the recommended area.
2. This figure is the recommended memory map of the μPD70F3767.
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3.4.6
CHAPTER 3 CPU FUNCTION
Peripheral I/O registers
(1/14)
Address
Function Register Name
Symbol
R/W Manipulatable Bits Default Value
1
FFFFF004H
Port DL register
8
√
R/W
PDL
16
0000H
FFFFF004H
Port DL register L
PDLL
√
√
00H
FFFFF005H
Port DL register H
PDLH
√
√
00H
PDH
Note 2
√
√
00H
PCS
Note 2
√
√
00H
Note 1
FFFFF006H
Port DH register
Note 2
FFFFF008H
Port CS register
Note 2
FFFFF00AH
Port CT register
PCT
√
√
00H
FFFFF00CH
Port CM register
PCM
√
√
00H
FFFFF024H
Port DL mode register
PMDL
Port DL mode register L
PMDLL
√
√
FFFFF024H
Note 1
Note 1
Note 1
Note 1
√
FFFFH
FFH
√
√
FFH
FFFFF026H
Port DH mode register
Note 2
PMDH
Note 2
√
√
FFH
FFFFF028H
Port CS mode register
Note 2
PMCS
Note 2
√
√
FFH
FFFFF02AH
Port CT mode register
PMCT
√
√
FFH
FFFFF02CH
Port CM mode register
PMCM
√
√
FFH
√
√
FFFFF025H
FFFFF044H
FFFFF044H
FFFFF045H
Port DL mode register H
PMDLH
Port DL mode control register
PMCDL
Port DL mode control register L
PMCDLL
Port DL mode control register H
Port DH mode control register
FFFFF048H
Port CS mode control register
FFFFF04AH
Port CT mode control register
FFFFF04CH
Port CM mode control register
Note 2
√
0000H
00H
√
√
00H
PMCDH
Note 2
√
√
00H
PMCCS
Note 2
PMCDLH
Note 2
FFFFF046H
√
√
00H
PMCCT
√
√
00H
PMCCM
√
√
00H
FFFFF064H
Peripheral I/O area select control register
BPC
√
0000H
FFFFF066H
Bus size configuration register
BSC
√
5555H
Note 3
Note 3
Note 1
Note 1
√
FFFFF06EH
System wait control register
VSWC
FFFFF080H
DMA source address register 0L
DSA0L
√
Undefined
FFFFF082H
DMA source address register 0H
DSA0H
√
Undefined
FFFFF084H
DMA destination address register 0L
DDA0L
√
Undefined
FFFFF086H
DMA destination address register 0H
DDA0H
√
Undefined
FFFFF088H
DMA source address register 1L
DSA1L
√
Undefined
FFFFF08AH
DMA source address register 1H
DSA1H
√
Undefined
FFFFF08CH
DMA destination address register 1L
DDA1L
√
Undefined
FFFFF08EH
DMA destination address register 1H
DDA1H
√
Undefined
FFFFF090H
DMA source address register 2L
DSA2L
√
Undefined
FFFFF092H
DMA source address register 2H
DSA2H
√
Undefined
FFFFF094H
DMA destination address register 2L
DDA2L
√
Undefined
FFFFF096H
DMA destination address register 2H
DDA2H
√
Undefined
FFFFF098H
DMA source address register 3L
DSA3L
√
Undefined
FFFFF09AH
DMA source address register 3H
DSA3H
√
Undefined
FFFFF09CH
DMA destination address register 3L
DDA3L
√
Undefined
Notes 1
77H
The output latch is 00H or 0000H. When these registers are in the input mode, the pin statuses are read.
2. V850ES/JH3-H only
3. μPD70F3770, 70F3771 only
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 77 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 3 CPU FUNCTION
(2/14)
Address
Function Register Name
Symbol
R/W
Manipulatable Bits Default Value
1
8
16
√
Undefined
DBC0
√
Undefined
DBC1
√
Undefined
DMA transfer count register 2
DBC2
√
Undefined
FFFFF0C6H
DMA transfer count register 3
DBC3
√
Undefined
FFFFF0D0H
DMA addressing control register 0
DADC0
√
0000H
FFFFF0D2H
DMA addressing control register 1
DADC1
√
0000H
FFFFF0D4H
DMA addressing control register 2
DADC2
√
0000H
FFFFF0D6H
DMA addressing control register 3
DADC3
√
0000H
FFFFF0E0H
DMA channel control register 0
DCHC0
√
√
00H
FFFFF0E2H
DMA channel control register 1
DCHC1
√
√
00H
FFFFF0E4H
DMA channel control register 2
DCHC2
√
√
00H
√
√
FFFFF09EH
DMA destination address register 3H
DDA3H
FFFFF0C0H
DMA transfer count register 0
FFFFF0C2H
DMA transfer count register 1
FFFFF0C4H
R/W
FFFFF0E6H
DMA channel control register 3
DCHC3
FFFFF100H
Interrupt mask register 0
IMR0
FFFFF100H
Interrupt mask register 0L
IMR0L
√
√
FFFFF101H
Interrupt mask register 0H
IMR0H
√
√
Interrupt mask register 1
IMR1
FFFFF102H
00H
√
FFFFH
FFH
FFH
√
FFFFH
FFFFF102H
Interrupt mask register 1L
IMR1L
√
√
FFH
FFFFF103H
Interrupt mask register 1H
IMR1H
√
√
FFH
Interrupt mask register 2
IMR2
FFFFF104H
√
FFFFH
FFFFF104H
Interrupt mask register 2L
IMR2L
√
√
FFH
FFFFF105H
Interrupt mask register 2H
IMR2H
√
√
FFH
Interrupt mask register 3
IMR3
FFFFF106H
√
FFFFH
FFFFF106H
Interrupt mask register 3L
IMR3L
√
√
FFH
FFFFF107H
Interrupt mask register 3H
IMR3H
√
√
FFH
FFFFF108H
√
Interrupt mask register 4
IMR4
FFFFF108H
Interrupt mask register 4L
IMR4L
√
√
FFH
FFFFF109H
Interrupt mask register 4H
IMR4H
√
√
FFH
FFFFF10AH
√
FFFFH
Interrupt mask register 5
IMR5
FFFFF10AH
Interrupt mask register 5L
IMR5L
√
√
FFFFH
FFH
FFFFF10BH
Interrupt mask register 5H
IMR5H
√
√
FFH
FFFFF110H
Interrupt control register
LVIIC
√
√
47H
FFFFF112H
Interrupt control register
PIC00
√
√
47H
FFFFF114H
Interrupt control register
PIC01
√
√
47H
FFFFF116H
Interrupt control register
PIC02
√
√
47H
FFFFF118H
Interrupt control register
PIC03
√
√
47H
FFFFF11AH
Interrupt control register
PIC04
√
√
47H
FFFFF11CH
Interrupt control register
PIC05
√
√
47H
FFFFF11EH
Interrupt control register
PIC06
√
√
47H
FFFFF120H
Interrupt control register
PIC07
√
√
47H
FFFFF122H
Interrupt control register
PIC08
√
√
47H
FFFFF124H
Interrupt control register
PIC09
√
√
47H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 78 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 3 CPU FUNCTION
(3/14)
Address
Function Register Name
Symbol
R/W
Manipulatable Bits Default Value
1
8
√
√
47H
PIC11
√
√
47H
Interrupt control register
PIC12
√
√
47H
FFFFF12CH
Interrupt control register
PIC13
√
√
47H
FFFFF12EH
Interrupt control register
PIC14
√
√
47H
FFFFF130H
Interrupt control register
PIC15
√
√
47H
FFFFF132H
Interrupt control register
PIC16
√
√
47H
FFFFF134H
Interrupt control register
PIC17
√
√
47H
FFFFF136H
Interrupt control register
PIC18
√
√
47H
FFFFF138H
Interrupt control register
TAB0OVIC
√
√
47H
FFFFF13AH
Interrupt control register
TAB0CCIC0
√
√
47H
FFFFF13CH
Interrupt control register
TAB0CCIC1
√
√
47H
FFFFF13EH
Interrupt control register
TAB0CCIC2
√
√
47H
FFFFF140H
Interrupt control register
TAB0CCIC3
√
√
47H
FFFFF142H
Interrupt control register
TAB1OVIC
√
√
47H
FFFFF144H
Interrupt control register
TAB1CCIC0
√
√
47H
FFFFF146H
Interrupt control register
TAB1CCIC1
√
√
47H
FFFFF148H
Interrupt control register
TAB1CCIC2
√
√
47H
FFFFF126H
Interrupt control register
PIC10
FFFFF128H
Interrupt control register
FFFFF12AH
R/W
16
FFFFF14AH
Interrupt control register
TAB1CCIC3
√
√
47H
FFFFF14CH
Interrupt control register
TT0OVIC
√
√
47H
FFFFF14EH
Interrupt control register
TT0CCIC0
√
√
47H
FFFFF150H
Interrupt control register
TT0CCIC1
√
√
47H
FFFFF152H
Interrupt control register
TT0IECIC
√
√
47H
FFFFF154H
Interrupt control register
TAA0OVIC
√
√
47H
FFFFF156H
Interrupt control register
TAA0CCIC0
√
√
47H
FFFFF158H
Interrupt control register
TAA0CCIC1
√
√
47H
FFFFF15AH
Interrupt control register
TAA1OVIC
√
√
47H
FFFFF15CH
Interrupt control register
TAA1CCIC0
√
√
47H
FFFFF15EH
Interrupt control register
TAA1CCIC1
√
√
47H
FFFFF160H
Interrupt control register
TAA2OVIC
√
√
47H
FFFFF162H
Interrupt control register
TAA2CCIC0
√
√
47H
FFFFF164H
Interrupt control register
TAA2CCIC1
√
√
47H
FFFFF166H
Interrupt control register
TAA3OVIC
√
√
47H
FFFFF168H
Interrupt control register
TAA3CCIC0
√
√
47H
FFFFF16AH
Interrupt control register
TAA3CCIC1
√
√
47H
FFFFF16CH
Interrupt control register
TAA4OVIC
√
√
47H
FFFFF16EH
Interrupt control register
TAA4CCIC0
√
√
47H
FFFFF170H
Interrupt control register
TAA4CCIC1
√
√
47H
FFFFF172H
Interrupt control register
TAA5OVIC
√
√
47H
FFFFF174H
Interrupt control register
TAA5CCIC0
√
√
47H
FFFFF176H
Interrupt control register
TAA5CCIC1
√
√
47H
FFFFF178H
Interrupt control register
TM0EQIC0
√
√
47H
FFFFF17AH
Interrupt control register
TM1EQIC0
√
√
47H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 79 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 3 CPU FUNCTION
(4/14)
Address
Function Register Name
Symbol
R/W
R/W
Manipulatable Bits Default Value
1
8
√
√
47H
TM3EQIC0
√
√
47H
CF0RIC/IICIC1
√
√
47H
Interrupt control register
CF0TIC
√
√
47H
Interrupt control register
CF1RIC
√
√
47H
Interrupt control register
CF1TIC
√
√
47H
FFFFF17CH
Interrupt control register
TM2EQIC0
FFFFF17EH
Interrupt control register
FFFFF180H
Interrupt control register
FFFFF182H
FFFFF184H
FFFFF186H
16
FFFFF188H
Interrupt control register
CF2RIC
√
√
47H
FFFFF18AH
Interrupt control register
CF2TIC
√
√
47H
FFFFF18CH
Interrupt control register
CF3RIC
√
√
47H
FFFFF18EH
Interrupt control register
CF3TIC
√
√
47H
FFFFF190H
Interrupt control register
CF4RIC
√
√
47H
FFFFF192H
Interrupt control register
CF4TIC
√
√
47H
FFFFF194H
Interrupt control register
UC0RIC
√
√
47H
FFFFF196H
Interrupt control register
UC0TIC
√
√
47H
FFFFF198H
Interrupt control register
UC1RIC/IICIC2
√
√
47H
FFFFF19AH
Interrupt control register
UC1TIC
√
√
47H
FFFFF19CH
Interrupt control register
UC2RIC
√
√
47H
FFFFF19EH
Interrupt control register
UC2TIC
√
√
47H
FFFFF1A0H
Interrupt control register
UC3RIC/IICIC0
√
√
47H
FFFFF1A2H
Interrupt control register
UC3TIC
√
√
47H
FFFFF1A4H
Interrupt control register
UC4RIC
√
√
47H
FFFFF1A6H
Interrupt control register
UC4TIC
√
√
47H
FFFFF1A8H
Interrupt control register
ADIC
√
√
47H
FFFFF1AAH
Interrupt control register
DMAIC0
√
√
47H
FFFFF1ACH
Interrupt control register
DMAIC1
√
√
47H
FFFFF1AEH
Interrupt control register
DMAIC2
√
√
47H
FFFFF1B0H
Interrupt control register
DMAIC3
√
√
47H
FFFFF1B2H
Interrupt control register
KRIC
√
√
47H
FFFFF1B4H
Interrupt control register
RTC0IC
√
√
47H
FFFFF1B6H
Interrupt control register
RTC1IC
√
√
47H
FFFFF1B8H
Interrupt control register
RTC2IC
√
√
47H
√
√
47H
√
√
47H
Note
√
√
47H
Note
√
√
47H
Note
FFFFF1BAH
Interrupt control register
ERRIC0n
FFFFF1BCH
Interrupt control register
WUPIC0
FFFFF1BEH
Interrupt control register
RECIC0
FFFFF1C0H
Interrupt control register
TRXIC0
Note
FFFFF1C8H
Interrupt control register
UFIC0
√
√
47H
FFFFF1CAH
Interrupt control register
UFIC1
√
√
47H
FFFFF1FAH
In-service priority register
ISPR
√
√
00H
FFFFF1FCH
Command register
PRCMD
FFFFF1FEH
Power save control register
PSC
FFFFF200H
A/D converter mode register 0
FFFFF201H
A/D converter mode register 1
R
√
Undefined
√
√
00H
ADA0M0
√
√
00H
ADA0M1
√
√
00H
W
R/W
Note μPD70F3770, 70F3771 only
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 80 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 3 CPU FUNCTION
(5/14)
Address
Function Register Name
Symbol
R/W Manipulatable Bits Default Value
1
8
16
√
√
00H
FFFFF202H
A/D converter channel specification register
ADA0S
FFFFF203H
A/D converter mode register 2
ADA0M2
√
√
00H
FFFFF204H
Power-fail compare mode register
ADA0PFM
√
√
00H
FFFFF205H
Power-fail compare threshold value register
ADA0PFT
√
√
FFFFF210H
A/D conversion result register 0
ADA0CR0
A/D conversion result register 0H
ADA0CR0H
FFFFF211H
FFFFF212H
FFFFF213H
FFFFF214H
FFFFF215H
FFFFF216H
FFFFF217H
FFFFF218H
FFFFF219H
FFFFF21AH
FFFFF21BH
FFFFF21CH
FFFFF21DH
FFFFF21EH
FFFFF21FH
FFFFF220H
FFFFF221H
FFFFF222H
FFFFF223H
FFFFF224H
FFFFF225H
FFFFF226H
A/D conversion result register 1
ADA0CR1
A/D conversion result register 1H
ADA0CR1H
A/D conversion result register 2
ADA0CR2
A/D conversion result register 2H
ADA0CR2H
A/D conversion result register 3
ADA0CR3
A/D conversion result register 3H
ADA0CR3H
A/D conversion result register 4
ADA0CR4
A/D conversion result register 4H
ADA0CR4H
A/D conversion result register 5
ADA0CR5
A/D conversion result register 5H
ADA0CR5H
A/D conversion result register 6
ADA0CR6
A/D conversion result register 6H
ADA0CR6H
A/D conversion result register 7
ADA0CR7
A/D conversion result register 7H
ADA0CR7H
A/D conversion result register 8
ADA0CR8
A/D conversion result register 8H
ADA0CR8H
A/D conversion result register 9
ADA0CR9
A/D conversion result register 9H
ADA0CR9H
A/D conversion result register 10
ADA0CR10
A/D conversion result register 10H
ADA0CR10H
R/W
00H
√
R
√
Undefined
Undefined
√
√
Undefined
Undefined
√
√
Undefined
Undefined
√
√
Undefined
Undefined
√
√
Undefined
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
Undefined
√
√
Undefined
Undefined
√
A/D conversion result register 11
ADA0CR11
A/D conversion result register 11H
ADA0CR11H
FFFFF280H
D/A conversion value setting register 0
DA0CS0
FFFFF281H
D/A conversion value setting register 1
DA0CS1
FFFFF282H
D/A converter mode register
DA0M
FFFFF300H
Key return mode register
FFFFF308H
Selector operation control register 0
FFFFF310H
CRC input register
CRCIN
FFFFF312H
CRC data register
CRCD
FFFFF320H
Prescaler mode register 1
PRSM1
FFFFF321H
Prescaler compare register 1
PRSCM1
FFFFF324H
Prescaler mode register 2
PRSM2
FFFFF325H
Prescaler compare register 2
PRSCM2
FFFFF328H
Prescaler mode register 3
PRSM3
FFFFF329H
Prescaler compare register 3
PRSCM3
√
00H
FFFFF340H
IIC division clock select register 0
OCKS0
√
00H
FFFFF344H
IIC division clock select register 1
OCKS1
√
00H
FFFFF227H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Undefined
√
Undefined
√
00H
√
00H
√
√
00H
KRM
√
√
00H
SELCNT0
√
√
00H
R/W
√
00H
√
√
√
√
0000H
√
00H
√
00H
√
00H
√
00H
√
00H
Page 81 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 3 CPU FUNCTION
(6/14)
Address
Function Register Name
Symbol
R/W Manipulatable Bits Default Value
1
8
16
√
√
00H
√
√
00H
√
√
00H
Note 1
FFFFF400H
Port 0 register
P0
FFFFF402H
Port 1 register
P1
FFFFF404H
Port 2 register
FFFFF406H
Port 3 register
P3
√
√
00H
FFFFF408H
Port 4 register
P4
√
√
00H
FFFFF40AH
Port 5 register
P5
√
√
00H
FFFFF40CH
Port 6 register
P6
√
√
00H
FFFFF40EH
Port 7 register L
P7L
√
√
00H
FFFFF40FH
Port 7 register H
P7H
√
√
00H
FFFFF412H
Port 9 register
P9
FFFFF412H
Port 9 register L
P9L
√
√
00H
FFFFF413H
Port 9 register H
P9H
√
√
00H
FFFFF420H
Port 0 mode register
PM0
√
√
FFH
FFFFF422H
Port 1 mode register
PM1
√
√
FFH
Note 2
P2
R/W
Note 2
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
√
0000H
Note 1
Note 1
FFFFF424H
Port 2 mode register
PM2
√
√
FFH
FFFFF426H
Port 3 mode register
PM3
√
√
FFH
FFFFF428H
Port 4 mode register
PM4
√
√
FFH
FFFFF42AH
Port 5 mode register
PM5
√
√
FFH
FFFFF42CH
Port 6 mode register
PM6
√
√
FFH
FFFFF42EH
Port 7 mode register L
PM7L
√
√
FFH
FFFFF42FH
Port 7 mode register H
PM7H
√
√
FFH
√
√
FFFFF432H
Note 2
Note 2
√
FFFFH
Port 9 mode register
PM9
FFFFF432H
Port 9 mode register L
PM9L
FFFFF433H
Port 9 mode register H
PM9H
√
√
FFH
PMC0
√
√
00H
√
√
00H
FFH
FFFFF440H
Port 0 mode control register
FFFFF444H
Port 2 mode control register
FFFFF446H
Port 3 mode control register
PMC3
√
√
00H
FFFFF448H
Port 4 mode control register
PMC4
√
√
00H
FFFFF44AH
Port 5 mode control register
PMC5
√
√
00H
FFFFF44CH
Port 6 mode control register
PMC6
√
√
00H
FFFFF452H
Note 2
PMC2
Note 2
√
0000H
Port 9 mode control register
PMC9
FFFFF452H
Port 9 mode control register L
PMC9L
√
√
00H
FFFFF453H
Port 9 mode control register H
PMC9H
√
√
00H
PFC0
√
√
00H
√
√
00H
FFFFF460H
Port 0 function control register
Note 2
FFFFF464H
Port 2 function control register
FFFFF466H
Port 3 function control register
PFC3
√
√
00H
FFFFF468H
Port 4 function control register
PFC4
√
√
00H
FFFFF46AH
Port 5 function control register
PFC5
√
√
00H
FFFFF46CH
Port 6 function control register
PFC6
√
√
00H
Notes 1
PFC2
Note 2
Note 1
The output latch is 00H or 0000H. When these registers are input, the pin statuses are read.
2. V850ES/JH3-H only
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 82 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 3 CPU FUNCTION
(7/14)
Address
Function Register Name
Symbol
R/W Manipulatable Bits Default Value
1
FFFFF472H
Port 9 function control register
PFC9
8
16
√
R/W
0000H
FFFFF472H
Port 9 function control register L
PFC9L
√
√
00H
FFFFF473H
Port 9 function control register H
PFC9H
√
√
00H
Data wait control register 0
DWC0
√
7777H
FFFFF488H
Address wait control register
AWC
√
FFFFH
FFFFF48AH
Bus cycle control register
BCC
√
AAAAH
FFFFF540H
TAB0 control register 0
TAB0CTL0
FFFFF541H
TAB0 control register 1
TAB0CTL1
√
√
00H
FFFFF542H
TAB0 I/O control register 0
TAB0IOC0
√
√
00H
FFFFF543H
TAB0 I/O control register 1
TAB0IOC1
√
√
00H
FFFFF544H
TAB0 I/O control register 2
TAB0IOC2
√
√
00H
FFFFF545H
TAB0 option register 0
TAB0OPT0
√
√
00H
FFFFF546H
TAB0 capture/compare register 0
TAB0CCR0
√
0000H
FFFFF548H
TAB0 capture/compare register 1
TAB0CCR1
√
0000H
FFFFF54AH
TAB0 capture/compare register 2
TAB0CCR2
√
0000H
FFFFF54CH
TAB0 capture/compare register 3
TAB0CCR3
√
0000H
FFFFF54EH
TAB0 counter read buffer register
TAB0CNT
R
√
0000H
R/W
FFFFF484H
√
√
00H
FFFFF550H
TAB0 I/O control register 4
TAB0IOC4
√
√
00H
FFFFF560H
TAB1 control register 0
TAB1CTL0
√
√
00H
FFFFF561H
TAB1 control register 1
TAB1CTL1
√
√
00H
FFFFF562H
TAB1 I/O control register 0
TAB1IOC0
√
√
00H
FFFFF563H
TAB1 I/O control register 1
TAB1IOC1
√
√
00H
FFFFF564H
TAB1 I/O control register 2
TAB1IOC2
√
√
00H
FFFFF565H
TAB1 option register 0
TAB1OPT0
√
√
00H
FFFFF566H
TAB1 capture/compare register 0
TAB1CCR0
√
0000H
FFFFF568H
TAB1 capture/compare register 1
TAB1CCR1
√
0000H
FFFFF56AH
TAB1 capture/compare register 2
TAB1CCR2
√
0000H
FFFFF56CH
TAB1 capture/compare register 3
TAB1CCR3
√
0000H
FFFFF56EH
TAB1 counter read buffer register
TAB1CNT
R
√
0000H
FFFFF570H
TAB1 I/O control register 4
TAB1IOC4
R/W
FFFFF580H
TAB1 option register 1
FFFFF581H
TAB1 option register 2
FFFFF582H
TAB1 I/O control register 3
FFFFF584H
TAB1 dead time compare register 1
TAB1DTC
FFFFF590H
High impedance output control register 0
FFFFF591H
FFFFF600H
FFFFF601H
TMT0 control register 1
√
√
00H
TAB1OPT1
√
√
00H
TAB1OPT2
√
√
00H
TAB1IOC3
√
√
A8H
HZACTL0
√
√
00H
High impedance output control register 1
HZACTL1
√
√
00H
TMT0 control register 0
TT0CTL0
√
√
00H
TT0CTL1
√
√
00H
√
0000H
FFFFF602H
TMT0 control register 2
TT0CTL2
√
√
00H
FFFFF603H
TMT0I/O control register 0
TT0IOC0
√
√
00H
FFFFF604H
TMT0I/O control register 1
TT0IOC1
√
√
00H
FFFFF605H
TMT0I/O control register 2
TT0IOC2
√
√
00H
FFFFF606H
TMT0I/O control register 3
TT0IOC3
√
√
00H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 83 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 3 CPU FUNCTION
(8/14)
Address
Function Register Name
Symbol
R/W Manipulatable Bits Default Value
1
8
√
√
00H
TT0OPT1
√
√
00H
TMT0 option register 2
TT0OPT2
√
√
TMT0 capture/compare register 0
TT0CCR0
FFFFF607H
TMT0 option register 0
TT0OPT0
FFFFF608H
TMT0 option register 1
FFFFF609H
FFFFF60AH
R/W
16
00H
√
0000H
FFFFF60CH
TMT0 capture/compare register 1
TT0CCR1
√
0000H
FFFFF60EH
TMT0 counter read buffer register
TT0CNT
R
√
0000H
FFFFF610H
TMT0 counter write register
TT0TCW
R/W
√
0000H
FFFFF630H
TAA0 control register 0
TAA0CTL0
√
√
00H
FFFFF631H
TAA0 control register 1
TAA0CTL1
√
√
00H
FFFFF632H
TAA0 I/O control register 0
TAA0IOC0
√
√
00H
FFFFF633H
TAA0 I/O control register 1
TAA0IOC1
√
√
00H
FFFFF634H
TAA0 I/O control register 2
TAA0IOC2
√
√
00H
FFFFF635H
TAA0 option register 0
TAA0OPT0
√
√
FFFFF636H
TAA0 capture/compare register 0
TAA0CCR0
√
0000H
FFFFF638H
TAA0 capture/compare register 1
TAA0CCR1
√
0000H
FFFFF63AH
TAA0 counter read buffer register
TAA0CNT
R
√
0000H
FFFFF63CH
TAA0 I/O control register 4
TAA0IOC4
R/W
FFFFF63DH
TAA0 option register 1
FFFFF640H
TAA1 control register 0
FFFFF641H
00H
√
√
00H
TAA0OPT1
√
√
00H
TAA1CTL0
√
√
00H
TAA1 control register 1
TAA1CTL1
√
√
00H
FFFFF642H
TAA1 I/O control register 0
TAA1IOC0
√
√
00H
FFFFF643H
TAA1 I/O control register 1
TAA1IOC1
√
√
00H
FFFFF644H
TAA1 I/O control register 2
TAA1IOC2
√
√
00H
FFFFF645H
TAA1 option register 0
TAA1OPT0
√
√
00H
FFFFF646H
TAA1 capture/compare register 0
TAA1CCR0
FFFFF648H
TAA1 capture/compare register 1
TAA1CCR1
FFFFF64AH
TAA1 counter read buffer register
TAA1CNT
R
R/W
√
0000H
√
0000H
√
0000H
FFFFF64CH
TAA1 I/O control register 4
TAA1IOC4
√
√
00H
FFFFF650H
TAA2 control register 0
TAA2CTL0
√
√
00H
FFFFF651H
TAA2 control register 1
TAA2CTL1
√
√
00H
FFFFF652H
TAA2 I/O control register 0
TAA2IOC0
√
√
00H
FFFFF653H
TAA2 I/O control register 1
TAA2IOC1
√
√
00H
FFFFF654H
TAA2 I/O control register 2
TAA2IOC2
√
√
00H
FFFFF655H
TAA2 option register 0
TAA2OPT0
√
√
FFFFF656H
TAA2 capture/compare register 0
TAA2CCR0
FFFFF658H
TAA2 capture/compare register 1
TAA2CCR1
FFFFF65AH
TAA2 counter read buffer register
TAA2CNT
R
FFFFF65CH
TAA2 I/O control register 4
TAA2IOC4
R/W
FFFFF65DH
TAA2 option register 1
FFFFF660H
TAA3 control register 0
FFFFF661H
FFFFF662H
FFFFF663H
00H
√
0000H
√
0000H
√
0000H
√
√
00H
TAA2OPT1
√
√
00H
TAA3CTL0
√
√
00H
TAA3 control register 1
TAA3CTL1
√
√
00H
TAA3 I/O control register 0
TAA3IOC0
√
√
00H
TAA3 I/O control register 1
TAA3IOC1
√
√
00H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 84 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 3 CPU FUNCTION
(9/14)
Address
Symbol
R/W
TAA3 I/O control register 2
TAA3IOC2
R/W
FFFFF665H
TAA3 option register 0
TAA3OPT0
FFFFF666H
TAA3 capture/compare register 0
TAA3CCR0
√
0000H
FFFFF668H
TAA3 capture/compare register 1
TAA3CCR1
√
0000H
FFFFF66AH
TAA3 counter read buffer register
TAA3CNT
R
FFFFF66CH
TAA3 I/O control register4
TAA3IOC4
R/W
FFFFF670H
TAA4 control register 0
FFFFF671H
TAA4 control register 1
FFFFF676H
TAA4 capture compare register 0
TAA4CCR0
FFFFF664H
Function Register Name
Manipulatable Bits Default Value
1
8
√
√
√
√
16
00H
00H
√
0000H
√
√
00H
TAA4CTL0
√
√
00H
TAA4CTL1
√
√
00H
√
0000H
√
0000H
√
0000H
FFFFF678H
TAA4 capture compare register 1
TAA4CCR1
FFFFF67AH
TAA4 counter read buffer register
TAA4CNT
R
FFFFF680H
TAA5 control register 0
TAA5CTL0
R/W
√
√
00H
FFFFF681H
TAA5 control register 1
TAA5CTL1
√
√
00H
FFFFF682H
TAA5 I/O control register 0
TAA5IOC0
√
√
00H
FFFFF683H
TAA5 I/O control register 1
TAA5IOC1
√
√
00H
FFFFF684H
TAA5 I/O control register 2
TAA5IOC2
√
√
00H
FFFFF685H
TAA5 option register 0
TAA5OPT0
√
√
00H
FFFFF686H
TAA5 capture/compare register 0
TAA5CCR0
√
0000H
FFFFF688H
TAA5 capture/compare register 1
TAA5CCR1
√
0000H
FFFFF68AH
TAA5 counter read buffer register
TAA5CNT
R
FFFFF68CH
TAA5 I/O control register 4
TAA5IOC4
R/W
FFFFF6C0H
Oscillation stabilization time select register
√
√
0000H
√
00H
OSTS
√
06H
FFFFF6C1H
PLL lockup time specification register
PLLS
√
03H
FFFFF6D0H
Watchdog timer mode register 2
WDTM2
√
67H
FFFFF6D1H
Watchdog timer enable register
WDTE
√
9AH
FFFFF6E0H
Real-time output buffer register 0L
RTBL0
√
√
00H
FFFFF6E2H
Real-time output buffer register 0H
RTBH0
√
√
00H
FFFFF6E4H
Real-time output port mode register 0
RTPM0
√
√
00H
FFFFF6E5H
Real-time output port control register 0
RTPC0
√
√
00H
FFFFF700H
Port 0 function control expansion register
PFCE0
√
√
00H
FFFFF704H
Port 2 function control expansion register
PFCE2
√
√
00H
FFFFF706H
Port 3 function control expansion register
PFCE3
√
√
00H
Note
Note
FFFFF708H
Port 4 function control expansion register
PFCE4
√
√
00H
FFFFF70AH
Port 5 function control expansion register
PFCE5
√
√
00H
FFFFF70CH
Port 6 function control expansion register
PFCE6
√
√
00H
FFFFF712H
√
Port 9 function control expansion register
PFCE9
FFFFF712H
Port 9 function control expansion register L
PFCE9L
√
√
0000H
00H
FFFFF713H
Port 2 function control expansion register H
PFCE9H
√
√
00H
FFFFF724H
TAA noise elimination control register
TANFC
√
√
00H
FFFFF726H
TMT noise elimination control register
TTNFC
√
√
00H
FFFFF728H
Noise elimination control register
INTNFC
√
√
00H
FFFFF802H
System status register
SYS
√
√
00H
Note V850ES/JH3-H only
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 85 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 3 CPU FUNCTION
(10/14)
Address
Function Register Name
Symbol
R/W Manipulatable Bits Default Value
1
8
√
√
00H
DTFR0
√
√
00H
DMA trigger factor register 1
DTFR1
√
√
00H
DMA trigger factor register 2
DTFR2
√
√
00H
Power save mode register
PSMR
√
√
00H
Clock control register
CKC
√
√
0AH
FFFFF824H
Lock register
LOCKR
R
√
√
00H
FFFFF828H
Processor clock control register
PCC
R/W
√
√
03H
FFFFF82CH
PLL control register
PLLCTL
√
√
01H
FFFFF82EH
CPU operation clock status register
CCLS
R
√
√
00H
FFFFF870H
Clock monitor mode register
CLM
R/W
√
√
00H
FFFFF888H
Reset source flag register
RESF
√
√
00H
FFFFF890H
Low-voltage detection register
LVIM
√
√
00H
FFFFF892H
Internal RAM data status register
RAMS
√
√
01H
FFFFF8B0H
Prescaler mode register 0
PRSM0
√
√
00H
FFFFF8B1H
Prescaler compare register 0
PRSCM0
√
00H
√
01H
FFFFF80CH
Internal oscillation mode register
RCM
FFFFF810H
DMA trigger factor register 0
FFFFF812H
FFFFF814H
FFFFF820H
FFFFF822H
Note
Note
√
√
16
FFFFF9FCH
On-chip debug mode register
FFFFFA00H
UARTC0 control register 0
UC0CTL0
√
10H
FFFFFA01H
UARTC0 control register 1
UC0CTL1
√
00H
FFFFFA02H
UARTC0 control register 2
UC0CTL2
√
FFH
FFFFFA03H
UARTC0 option control register 0
UC0OPT0
√
√
14H
FFFFFA04H
UARTC0 status register
UC0STR
√
√
00H
FFFFFA06H
UARTC0 receive data register
UC0RX
UARTC0 receive data register L
UC0RXL
UARTC0 transmit data register
UC0TX
UARTC0 transmit data register L
UC0TXL
FFFFFA0AH
UARTC0 option control register 1
UC0OPT1
√
FFFFFA10H
UARTC1 control register 0
UC1CTL0
√
√
10H
FFFFFA11H
UARTC1 control register 1
UC1CTL1
√
00H
FFFFFA12H
UARTC1 control register 2
UC1CTL2
√
FFH
FFFFFA13H
UARTC1 option control register 0
UC1OPT0
√
√
14H
FFFFFA14H
UARTC1 status register
UC1STR
√
√
00H
FFFFFA16H
UARTC1 receive data register
UC1RX
UARTC1 receive data register L
UC1RXL
UARTC1 transmit data register
UC1TX
FFFFFA06H
FFFFFA08H
FFFFFA08H
FFFFFA16H
FFFFFA18H
FFFFFA18H
OCDM
R/W
√
R
√
√
FFH
√
R/W
01FFH
01FFH
√
FFH
√
00H
√
R
√
FFH
√
R/W
01FFH
01FFH
√
FFH
√
00H
UARTC1 transmit data register L
UC1TXL
FFFFFA1AH
UARTC1 option control register 1
UC1OPT1
√
FFFFFA20H
UARTC2 control register 0
UC2CTL0
√
√
10H
FFFFFA21H
UARTC2 control register 1
UC2CTL1
√
00H
FFFFFA22H
UARTC2 control register 2
UC2CTL2
√
FFH
FFFFFA23H
UARTC2 option control register 0
UC2OPT0
√
14H
√
Note V850ES/JG3-H only
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 86 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 3 CPU FUNCTION
(11/14)
Address
Function Register Name
Symbol
FFFFFA24H
UARTC2 status register
UC2STR
FFFFFA26H
UARTC2 receive data register
UC2RX
UARTC2 receive data register L
UC2RXL
UARTC2 transmit data register
UC2TX
FFFFFA26H
FFFFFA28H
R/W Manipulatable Bits Default Value
R/W
1
8
√
√
16
00H
√
R
√
FFH
√
R/W
01FFH
01FFH
UARTC2 transmit data register L
UC2TXL
√
FFH
FFFFFA2AH
UARTC2 option control register 1
UC2OPT1
√
√
00H
FFFFFA30H
UARTC3 control register 0
UC3CTL0
√
√
10H
FFFFFA31H
UARTC3 control register 1
UC3CTL1
√
00H
FFFFFA32H
UARTC3 control register 2
UC3CTL2
√
FFH
FFFFFA33H
UARTC3 option control register 0
UC3OPT0
√
√
14H
FFFFFA34H
UARTC3 status register
UC3STR
√
√
00H
FFFFFA36H
UARTC3 receive data register
UC3RX
UARTC3 receive data register L
UC3RXL
UARTC3 transmit data register
UC3TX
FFFFFA28H
FFFFFA36H
FFFFFA38H
R
√
01FFH
√
01FFH
√
R/W
FFH
UARTC3 transmit data register L
UC3TXL
√
FFH
FFFFFA3AH
UARTC3 option control register 1
UC3OPT1
√
√
00H
FFFFFA40H
UARTC4 control register 0
UC4CTL0
√
√
10H
FFFFFA41H
UARTC4 control register 1
UC4CTL1
√
00H
FFFFFA42H
UARTC4 control register 2
UC4CTL2
√
FFH
FFFFFA43H
UARTC4 option control register 0
UC4OPT0
√
√
14H
FFFFFA44H
UARTC4 status register
UC4STR
√
√
00H
FFFFFA46H
UARTC4 receive data register
UC4RX
UARTC4 receive data register L
UC4RXL
UARTC4 transmit data register
UC4TX
FFFFFA38H
FFFFFA46H
FFFFFA48H
√
R
√
FFH
√
R/W
01FFH
01FFH
UARTC4 transmit data register L
UC4TXL
√
FFH
FFFFFA4AH
UARTC4 option control register 1
UC4OPT1
√
√
00H
FFFFFA80H
TMM0 control register 0
TM0CTL0
√
√
FFFFFA84H
TMM0 compare register 0
TM0CMP0
FFFFFA90H
TMM1 control register 0
TM1CTL0
FFFFFA94H
TMM1 compare register 0
TM1CMP0
FFFFFAA0H
TMM2 control register 0
TM2CTL0
FFFFFAA4H
TMM2 compare register 0
TM2CMP0
FFFFFAB0H
TMM3 control register 0
TM3CTL0
FFFFFAB4H
TMM3 compare register 0
TM3CMP0
FFFFFAD0H
Sub-count register
RC1SUBC
FFFFFAD2H
Second count register
RC1SEC
FFFFFAD3H
Minute count register
FFFFFAD4H
FFFFFAD5H
FFFFFA48H
00H
√
√
√
√
√
00H
√
√
0000H
00H
√
0000H
√
0000H
√
0000H
√
R
0000H
00H
√
00H
RC1MIN
√
00H
Hour count register
RC1HOUR
√
12H
Week count register
RC1WEEK
√
00H
FFFFFAD6H
Day count register
RC1DAY
√
01H
FFFFFAD7H
Month count register
RC1MONTH
√
01H
FFFFFAD8H
Year count register
RC1YEAR
√
00H
FFFFFAD9H
Time error correction register
RC1SUBU
√
00H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
R/W
√
Page 87 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 3 CPU FUNCTION
(12/14)
Address
Function Register Name
Symbol
R/W Manipulatable Bits Default Value
1
8
16
√
00H
√
12H
√
00H
√
√
00H
RC1CC1
√
√
00H
RC1CC2
√
√
00H
RC1CC3
√
√
00H
R/W
FFFFFADAH
Alarm minute set register
RC1ALM
FFFFFADBH
Alarm time set register
RC1ALH
FFFFFADCH
Alarm week set register
RC1ALW
√
FFFFFADDH
RTC control register 0
RC1CC0
FFFFFADEH
RTC control register 1
FFFFFADFH
RTC control register 2
FFFFFAE0H
RTC control register 3
√
√
00H
√
√
00H
INTF3
√
√
00H
INTF4
√
√
00H
√
√
00H
INTF9L
√
√
00H
External interrupt falling edge specification register 9H INTF9H
√
√
00H
FFFFFC20H
External interrupt rising edge specification register 0
INTR0
√
√
00H
FFFFFC24H
External interrupt rising edge specification register 2
Note 1
INTR2
√
√
00H
FFFFFC26H
External interrupt rising edge specification register 3
INTR3
√
√
00H
FFFFFC28H
External interrupt rising edge specification register 4
INTR4
√
√
00H
FFFFFC2AH
Note 2
External interrupt rising edge specification register 5
INTR5
√
√
00H
FFFFFC32H
External interrupt rising edge specification register 9
INTR9
FFFFFC00H
External interrupt falling edge specification register 0
INTF0
FFFFFC04H
External interrupt falling edge specification register 2
Note 1
INTF2
FFFFFC06H
External interrupt falling edge specification register 3
FFFFFC08H
External interrupt falling edge specification register 4
FFFFFC0AH
Note 2
External interrupt falling edge specification register 5
INTF5
FFFFFC12H
External interrupt falling edge specification register 9
INTF9
FFFFFC12H
External interrupt falling edge specification register 9L
FFFFFC13H
Note 1
Note 2
√
Note 1
Note 2
√
0000H
0000H
FFFFFC32H
External interrupt rising edge specification register 9H INTR9H
√
√
00H
FFFFFC33H
External interrupt rising edge specification register 9L
INTR9L
√
√
00H
FFFFFC60H
Port 0 function register
PF0
FFFFFC64H
Port 2 function register
PF2
FFFFFC66H
Port 3 function register
FFFFFC68H
Port 4 function register
FFFFFC6AH
√
√
00H
√
√
00H
PF3
√
√
00H
PF4
√
√
00H
Port 5 function register
PF5
√
√
00H
FFFFFC72H
Port 9 function register L
PF9L
√
√
00H
FFFFFD00H
CSIF0 control register 0
CF0CTL0
√
√
01H
FFFFFD01H
CSIF0 control register 1
CF0CTL1
√
√
00H
FFFFFD02H
CSIF0 control register 2
CF0CTL2
√
00H
FFFFFD03H
CSIF0 status register
CF0STR
√
00H
FFFFFD04H
CSIF0 receive data register
CF0RX
CSIF0 receive data register L
CF0RXL
CSIF0 transmit data register
CF0TX
FFFFFD04H
FFFFFD06H
Note 1
Note 1
√
√
R
√
00H
√
R/W
0000H
0000H
CSIF0 transmit data register L
CF0TXL
√
00H
FFFFFD10H
CSIF1 control register 0
CF1CTL0
√
√
01H
FFFFFD11H
CSIF1 control register 1
CF1CTL1
√
√
00H
FFFFFD12H
CSIF1 control register 2
CF1CTL2
√
00H
FFFFFD13H
CSIF1 status register
CF1STR
√
00H
FFFFFD06H
√
Notes 1. V850ES/JH3-H only
2. V850ES/JG3-H only
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Address
Function Register Name
Symbol
R/W Manipulatable Bits Default Value
1
FFFFFD14H
FFFFFD14H
FFFFFD16H
CSIF1 receive data register
CF1RX
CSIF1 receive data register L
CF1RXL
CSIF1 transmit data register
CF1TX
8
16
√
R
√
00H
√
R/W
0000H
0000H
CSIF1 transmit data register L
CF1TXL
√
00H
FFFFFD20H
CSIF2 control register 0
CF2CTL0
√
√
01H
FFFFFD21H
CSIF2 control register 1
CF2CTL1
√
√
00H
FFFFFD22H
CSIF2 control register 2
CF2CTL2
√
00H
FFFFFD23H
CSIF2 status register
CF2STR
√
√
00H
FFFFFD16H
FFFFFD24H
FFFFFD24H
FFFFFD26H
CSIF2 receive data register
CF2RX
CSIF2 receive data register L
CF2RXL
CSIF2 transmit data register
CF2TX
CSIF2 transmit data register L
CF2TXL
FFFFFD30H
CSIF3 control register 0
CF3CTL0
FFFFFD31H
CSIF3 control register 1
CF3CTL1
FFFFFD32H
CSIF3 control register 2
CF3CTL2
FFFFFD33H
CSIF3 status register
CF3STR
FFFFFD34H
CSIF3 receive data register
CF3RX
FFFFFD26H
FFFFFD34H
FFFFFD36H
CSIF3 receive data register L
CF3RXL
CSIF3 transmit data register
CF3TX
√
R
√
00H
√
R/W
0000H
0000H
√
00H
√
√
01H
√
√
00H
√
00H
√
√
00H
√
R
√
00H
√
R/W
0000H
0000H
CSIF3 transmit data register L
CF3TXL
√
00H
FFFFFD40H
CSIF4 control register 0
CF4CTL0
√
√
01H
FFFFFD41H
CSIF4 control register 1
CF4CTL1
√
√
00H
FFFFFD42H
CSIF4 control register 2
CF4CTL2
√
00H
FFFFFD43H
CSIF4 status register
CF4STR
√
√
00H
FFFFFD36H
FFFFFD44H
FFFFFD44H
FFFFFD46H
CSIF4 receive data register
CF4RX
CSIF4 receive data register L
CF4RXL
√
R
√
0000H
00H
√
CSIF4 transmit data register
CF4TX
CSIF4 transmit data register L
CF4TXL
√
00H
FFFFFD80H
IIC shift register 0
IIC0
√
00H
FFFFFD82H
IIC control register 0
IICC0
√
00H
FFFFFD83H
Slave address register 0
SVA0
√
00H
FFFFFD46H
R/W
√
0000H
FFFFFD84H
IIC clock select register 0
IICCL0
√
√
00H
FFFFFD85H
IIC function expansion register 0
IICX0
√
√
00H
FFFFFD86H
IIC status register 0
IICS0
R
√
√
00H
FFFFFD8AH
IIC flag register 0
IICF0
R/W
√
√
00H
FFFFFD90H
IIC shift register 1
IIC1
√
00H
FFFFFD92H
IIC control register 1
IICC1
√
00H
FFFFFD93H
Slave address register 1
SVA1
√
00H
√
FFFFFD94H
IIC clock select register 1
IICCL1
√
√
00H
FFFFFD95H
IIC function expansion register 1
IICX1
√
√
00H
FFFFFD96H
IIC status register 1
IICS1
R
√
√
00H
FFFFFD9AH
IIC flag register 1
IICF1
R/W
√
FFFFFDA0H
IIC shift register 2
IIC2
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00H
√
00H
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CHAPTER 3 CPU FUNCTION
(14/14)
Address
FFFFFDA2H
Function Register Name
Symbol
R/W Manipulatable Bits Default Value
R/W
IIC control register 2
IICC2
FFFFFDA3H
Slave address register 2
SVA2
FFFFFDA4H
IIC clock select register 2
IICCL2
FFFFFDA5H
IIC function expansion register 2
IICX2
FFFFFDA6H
IIC status register 2
IICS2
R
FFFFFDAAH
IIC flag register 2
IICF2
R/W
FFFFFF40H
USB clock selection register
FFFFFF41H
USB function control register
8
√
√
16
00H
√
00H
√
√
00H
√
√
00H
√
√
00H
√
√
00H
UCKSEL
√
√
00H
UFCKMSK
√
√
03H
√
√
03H
√
00H
FFFFFF42H
USB function selection register
UHCKMSK
FFFFFF60H
External DMA request enable register
EXDRQEN
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3.4.7
CHAPTER 3 CPU FUNCTION
Programmable peripheral I/O registers
The BPC register is used to select the programmable peripheral I/O register area.
The BPC register is valid only μPD70F3770, 70F3771.
(1) Peripheral I/O area select control register (BPC)
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
After reset: 0000H
BPC
15
14
PA15
0
PA15
13
Address: FFFFF064H
12
11
10
9
8
7
6
5
4
3
2
1
0
PA13 PA12 PA11 PA10 PA09 PA08 PA07 PA06 PA05 PA04 PA03 PA02 PA01 PA00
Allows/does not allow use of programmable peripheral I/O area.
0
Do not allow use of programmable peripheral I/O area.
1
Allow use of programmable peripheral I/O area.
PA13 to
PA00
Caution
R/W
Set address of programmable peripheral I/O area. (correspond to A27 to
A14)
If the PA15 bit is set to 1, be sure to set the BPC register to 8FFBH.
If the PA15 bit is set to 0, be sure to set the BPC register to 0000H.
For the list of programmable peripheral I/O registers, refer to Table 20-16 Register Access Type.
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CHAPTER 3 CPU FUNCTION
Special registers
Special registers are registers that are protected from being written with illegal data due to a program loop. The
V850ES/JG3-H and V850ES/JH3-H have the following eight special registers.
• Power save control register (PSC)
• Clock control register (CKC)
• Processor clock control register (PCC)
• Clock monitor mode register (CLM)
• Reset source flag register (RESF)
• Low-voltage detection register (LVIM)
• Internal RAM data status register (RAMS)
• On-chip debug mode register (OCDM) (V850ES/JG3-H only)
In addition, the PRCDM register is provided to protect against a write access to the special registers so that the
application system does not inadvertently stop due to a program loop. A write access to the special registers is made in a
specific sequence, and an illegal store operation is reported to the SYS register.
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CHAPTER 3 CPU FUNCTION
(1) Setting data to special registers
Set data to the special registers in the following sequence.
Disable DMA operation.
Prepare data to be set to the special register in a general-purpose register.
Write the data prepared in to the PRCMD register.
Write the setting data to the special register (by using the following instructions).
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
( to Insert NOP instructions (5 instructions).)Note
Enable DMA operation if necessary.
[Example] With PSC register (setting standby mode)
ST.B r11, PSMR[r0]
CLR1 0, DCHCn[r0]
; Set PSMR register (setting IDLE1, IDLE2, and STOP modes).
; Disable DMA operation. n = 0 to 3
MOV0x02, r10
ST.B r10, PRCMD[r0] ; Write PRCMD register.
ST.B r10, PSC[r0]
; Set PSC register.
Note
NOP
; Dummy instruction
NOPNote
; Dummy instruction
Note
; Dummy instruction
NOPNote
; Dummy instruction
NOP
NOP
Note
; Dummy instruction
SET1 0, DCHCn[r0]
; Enable DMA operation. n = 0 to 3
(next instruction)
There is no special sequence to read a special register.
Note Five NOP instructions or more must be inserted immediately after setting the IDLE1 mode, IDLE2 mode, or
STOP mode (by setting the PSC.STP bit to 1).
Cautions 1. When a store instruction is executed to store data in the command register, interrupts are not
acknowledged. This is because it is assumed that steps and above are performed by
successive store instructions. If another instruction is placed between and , and if an
interrupt is acknowledged by that instruction, the above sequence may not be established,
causing malfunction.
2. Although dummy data is written to the PRCMD register, use the same general-purpose
register used to set the special register ( in Example) to write data to the PRCMD register
( in Example). The same applies when a general-purpose register is used for addressing.
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CHAPTER 3 CPU FUNCTION
(2) Command register (PRCMD)
The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system
from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access
to a special register is valid after data has been written in advance to the PRCMD register. In this way, the value of
the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write
access.
The PRCMD register is write-only, in 8-bit units (undefined data is read when this register is read).
After reset: Undefined
PRCMD
W
Address: FFFFF1FCH
7
6
5
4
3
2
1
0
REG7
REG6
REG5
REG4
REG3
REG2
REG1
REG0
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CHAPTER 3 CPU FUNCTION
(3) System status register (SYS)
Status flags that indicate the operation status of the overall system are allocated to this register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address: FFFFF802H
< >
SYS
0
0
0
PRERR
0
0
0
0
PRERR
Detects protection error
0
Protection error did not occur
1
Protection error occurred
The PRERR flag operates under the following conditions.
(a) Set condition (PRERR flag = 1)
(i) When data is written to a special register without writing anything to the PRCMD register (when is
executed without executing in 3.4.8 (1) Setting data to special registers)
(ii) When data is written to an on-chip peripheral I/O register other than a special register (including execution
of a bit manipulation instruction) after writing data to the PRCMD register (if in 3.4.8 (1) Setting data
to special registers is not the setting of a special register)
Remark
Even if an on-chip peripheral I/O register is read (except by a bit manipulation instruction) between
an operation to write the PRCMD register and an operation to write a special register, the PRERR
flag is not set, and the set data can be written to the special register.
(b) Clear condition (PRERR flag = 0)
(i) When 0 is written to the PRERR flag
(ii) When the system is reset
Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register,
immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0 (the
write access takes precedence).
2. If data is written to the PRCMD register, which is not a special register, immediately after a
write access to the PRCMD register, the PRERR bit is set to 1.
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3.4.9
CHAPTER 3 CPU FUNCTION
Cautions
(1) Registers to be set first
Be sure to set the following registers first when using the V850ES/JG3-H and V850ES/JH3-H.
• System wait control register (VSWC)
• On-chip debug mode register (OCDM) (V850ES/JG3-H only)
• Watchdog timer mode register 2 (WDTM2)
After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
When using the external bus, set each pin to the alternate-function bus control pin mode by using the port-related
registers after setting the above registers.
(a) System wait control register (VSWC)
The VSWC register controls wait of bus access to the on-chip peripheral I/O registers.
Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). The V850ES/JG3H and V850ES/JH3-H require wait cycles according to the operating frequency. Set the following value to the
VSWC register in accordance with the frequency used.
The VSWC register can be read or written in 8-bit units.
Reset sets this register to 77H.
After reset: 77H
R/W
Address: FFFFF06EH
VSWC
Operating Frequency (fCPU)
Set Value of VSWC
Number of Waits
fCPU < 16.6 MHz
00H
0 (no waits)
16.6 MHz ≤ fCPU < 25 MHz
01H
1
25 MHz ≤ fCPU < 33.3 MHz
11H
2
33.3 MHz ≤ fCPU ≤ 48 MHz
12H
3
(b) On-chip debug mode register (OCDM) (V850ES/JG3-H only)
For details, see CHAPTER 32 ON-CHIP DEBUG FUNCTION.
(c) Watchdog timer mode register 2 (WDTM2)
The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2.
Watchdog timer 2 automatically starts in the reset mode after reset is released. Write the WDTM2 register to
activate this operation.
For details, see CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2.
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CHAPTER 3 CPU FUNCTION
(2) Accessing specific on-chip peripheral I/O registers
This product has two types of internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.
The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and an
access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is a
possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is
accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next instruction
but enters the wait status. If this wait status occurs, the number of clocks required to execute an instruction
increases by the number of wait clocks shown below.
This must be taken into consideration if real-time processing is required.
When specific on-chip peripheral I/O registers are accessed, more wait states may be required in addition to the
wait states set by the VSWC register.
The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks) at this
time are shown below.
(1/2)
Peripheral Function
Register Name
Access
k
16-bit timer/event counter AA (TAA)
TAAnCNT
Read
1 or 2
(n = 0 to 5, m = 0 to 3, 5)
TAAnCCR0, TAAnCCR1
Write
• 1st access: No wait
• Continuous write: 0 to 3
TAAmIOC4
Read
1 or 2
Write
• 1st access: No wait
• Continuous write: 0 to 3
Read
1 or 2
16-bit timer/event counter AB (TAB)
TABnCNT
Read
1 or 2
(n = 0, 1)
TABnCCR0 to TABnCCR3
Write
• 1st access: No wait
• Continuous write: 0 to 3
TABnIOC4
Read
1 or 2
Write
• 1st access: No wait
• Continuous write: 0 to 3
Motor control
TAB0OPT1
Read
1 or 2
Write
• 1st access: No wait
• Continuous write: 0 to 3
TAB0DTC
Write
• 1st access: No wait
• Continuous write: 0 to 3
TMT
TT0CNT
Read
1 or 2
TT0TCR0, TT0TCR1
Write
• 1st access: No wait
• Continuous write: 0 to 3
Watchdog timer 2 (WDT2)
WDTM2
Read
1 or 2
Write
3
(when WDT2 operating)
Real-time output function (RTO)
RTBL0, RTBH0
Write
1
(RTPC0.RTPOE0 bit = 0)
A/D converter
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Read
1 or 2
ADA0CR0 to ADA0CR11
Read
1 or 2
ADA0CR0H to ADA0CR11H
Read
1 or 2
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CHAPTER 3 CPU FUNCTION
(2/2)
Peripheral Function
2
2
Register Name
Access
k
I C00 to I C02
IICS0 to IICS2
Read
1
CRC
CRCD
Write
1
CAN controller
C0GMABT,
Read/Write
fXX/fCANMOD + 1) / (2 + j) (MIN.)
(m = 0 to 31, a = 1 to 4)
C0GMABTD,
Note
Note
(2 × fXX/fCANMOD + 1) / (2 + j) (MAX.)
C0MASKaL, C0MASKaH,
C0LEC,
C0INFO,
C0ERC,
C0IE,
C0INTS,
C0BRP,
C0BTR,
C0TS
C0GMCTRL,
Read/Write
C0GMCS,
Note
(fXX/fCAN + 1) / (2 + j) (MIN.)
(2 × fXX/fCAN + 1) / (2 + j) (MAX.)
Note
C0CTRL
C0RGPT,
Write
Note
(fXX/fCANMOD + 1) / (2 + j) (MIN.)
Note
(2 × fXX/fCANMOD + 1) / (2 + j) (MAX.)
C0TGPT
Read
(3 × fXX/fCANMOD + 1) / (2 + j) (MIN.)
Note
Note
(4 × fXX/fCANMOD + 1) / (2 + j) (MAX.)
C0LIPT,
Read
Note
C0LOPT
C0MCTRLm
(3 × fXX/fCANMOD + 1) / (2 + j) (MIN.)
(4 × fXX/fCANMOD + 1) / (2 + j) (MAX.)
Write
Note
(4 × fXX/fCAN + 1) / (2 + j) (MIN.)
(5 × fXX/fCAN + 1) / (2 + j) (MAX.)
Read
Write (8 bits)
Note
Note
(4 × fXX/fCANMOD + 1) / (2 + j) (MIN.)
Note
Note
C0MDATA1m, C0MDATA23m,
C0MDATA2m, C0MDATA3m,
Note
(3 × fXX/fCAN + 1) / (2 + j) (MIN.)
(4 × fXX/fCAN + 1) / (2 + j) (MAX.)
C0MDATA01m, C0MDATA0m,
Note
(5 × fXX/fCANMOD + 1) / (2 + j) (MAX.)
Write (16 bits)
C0MDATA45m, C0MDATA4m,
(2 × fXX/fCANMOD + 1) / (2 + j) (MIN.)
Note
Note
(3 × fXX/fCANMOD + 1) / (2 + j) (MAX.)
C0MDATA5m, C0MDATA67m,
C0MDATA6m, C0MDATA7m,
Read (8/16 bits)
C0MDLCm,
(3 × fXX/fCANMOD + 1) / (2 + j) (MIN.)
Note
Note
(4 × fXX/fCANMOD + 1) / (2 + j) (MAX.)
C0MCONFm,
C0MIDLm,
C0MIDHm
Number of clocks necessary for access = 3 + i + j + (2 + j) × k
Note Digits below the decimal point are rounded up.
Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is generated,
it can only be cleared by a reset.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
Remark
i:
Values (0) of higher 4 bits of VSWC register
j:
Values (0 or 1) of lower 4 bits of VSWC register
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CHAPTER 3 CPU FUNCTION
(3) Restriction on conflict between sld instruction and interrupt request
(a) Description
If a conflict occurs between the decode operation of an instruction in immediately before the sld instruction
following an instruction in and an interrupt request before the instruction in is complete, the execution
result of the instruction in may not be stored in a register.
Instruction
• ld instruction:
ld.b, ld.h, ld.w, ld.bu, ld.hu
• sld instruction:
sld.b, sld.h, sld.w, sld.bu, sld.hu
• Multiplication instruction: mul, mulh, mulhi, mulu
Instruction
mov
reg1,
reg2
satadd
reg1,
reg2
and
reg1,
reg2
add
reg1,
satsub
reg2
reg2
satadd imm5,
or reg1, reg2
xor
reg2
subr
reg2
reg1,
reg1,
tst reg1, reg2
reg2
add
cmp
imm5,
reg1,
imm5,
reg2
sar
reg2
reg1,
reg2
cmp
imm5,
reg1,
reg1,
sub
reg1,
reg2
reg2
shr
reg2
mulh
satsubr reg1,
reg2
not
imm5,
reg2
shl
imm5,
reg2
reg2
ld.w [r11], r10
•
•
•
If the decode operation of the mov instruction immediately before the sld
instruction and an interrupt request conflict before execution of the ld instruction
is complete, the execution result of instruction may not be stored in a register.
mov r10, r28
sld.w 0x28, r10
(b) Countermeasure
When compiler (CA850) is used
Use CA850 Ver. 2.61 or later because generation of the corresponding instruction sequence can be
automatically suppressed.
For assembler
When executing the sld instruction immediately after instruction , avoid the above operation using
either of the following methods.
• Insert a nop instruction immediately before the sld instruction.
• Do not use the same register as the sld instruction destination register in the above instruction
executed immediately before the sld instruction.
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CHAPTER 4 PORT FUNCTIONS
CHAPTER 4 PORT FUNCTIONS
4.1
Features
{ I/O ports
• V850ES/JG3-H: 77
5 V tolerant/N-ch open-drain output selectable: 22
• V850ES/JH3-H: 96
5 V tolerant/N-ch open-drain output selectable: 25
{ Input/output specifiable in 1-bit units
4.2
Basic Port Configuration
The V850ES/JG3-H features a total of 77 I/O ports consisting of ports 0, 1, 3 to 7, 9, CM, CT, and DL.
The V850ES/JH3-H features a total of 96 I/O ports consisting of ports 0 to 7, 9, CM, CS, CT, DH, and DL.
The port configuration is shown below.
Table 4-1. I/O Buffer Power Supplies for Pins (V850ES/JG3-H)
Power Supply
Corresponding Pins
AVREF0
Port 7
AVREF1
Port 1
EVDD
RESET, ports 0, 3 to 6, 9, CM, CT, DL
Table 4-2. I/O Buffer Power Supplies for Pins (V850ES/JH3-H)
Power Supply
Corresponding Pins
AVREF0
Port 7
AVREF1
Port 1
EVDD
RESET, ports 0, 2 to 6, 9, CM, CS, CT, DH, DL
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CHAPTER 4 PORT FUNCTIONS
Figure 4-1. Port Configuration Diagram (V850ES/JG3-H)
Port 0
P02
P03
P04
P05
P10
Port 1
P11
P60
Port 6
P65
P70
Port 7
P711
P90
P30
Port 3
Port 9
P915
P37
PCM1
Port CM
P42
PCT0
PCT1
Port CT
P50
PDL0
P56
PDL15
P40
Port 4
Port DL
Port 5
Caution Ports 0, 3 to 5 are 5 V tolerant.
Figure 4-2. Port Configuration Diagram (V850ES/JH3-H)
P00
P90
P05
P915
P10
PCM0
Port 0
Port 1
Port 9
P20
Port 2
P25
P30
Port 3
P37
P40
Port 4
Port 5
Port CM
P11
PCM3
PCS0
PCS2
PCS3
Port CS
PCT0
PCT1
PCT4
PCT6
Port CT
P42
PDH0
P50
P51
PDH7
P60
PDL0
P65
PDL15
Port 6
Port DH
Port DL
P70
Port 7
P711
Caution Ports 0, 2, 3 to 5 are 5 V tolerant.
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CHAPTER 4 PORT FUNCTIONS
Port Configuration
Table 4-3. Port Configuration (V850ES/JG3-H)
Item
Configuration
Control register
Port n mode register (PMn: n = 0, 1, 3 to 7, 9, CM, CT, DL)
Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM, CT, DL)
Port n function control register (PFCn: n = 0, 3 to 6, 9)
Port n function control expansion register (PFCEn: n = 4 to 6, 9)
Port n function register (PFn: n = 0, 3 to 5, 9)
Ports
I/O: 77
Table 4-4. Port Configuration (V850ES/JH3-H)
Item
Control register
Configuration
Port n mode register (PMn: n = 0 to 7, 9, CM, CS, CT, DH, DL)
Port n mode control register (PMCn: n = 0, 2 to 6, 9, CM, CS, CT, DH, DL)
Port n function control register (PFCn: n = 0, 2 to 6, 9)
Port n function control expansion register (PFCEn: n = 4 to 6, 9)
Port n function register (PFn: n = 0, 2 to 5, 9)
Ports
I/O: 96
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(1) Port n register (Pn)
Data is input from or output to an external device by writing or reading the Pn register.
The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins.
Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units.
After reset: 00H (output latch)
Pn
R/W
7
6
5
7
3
2
1
0
Pn7
Pn6
Pn5
Pn4
Pn3
Pn2
Pn1
Pn0
Pnm
Control of output data (in output mode)
0
Outputs 0.
1
Outputs 1.
Data is written to or read from the Pn register as follows, regardless of the setting of the PMCn register.
Table 4-5. Writing/Reading Pn Register
Setting of PMn Register
Writing to Pn Register
Note
Output mode
Data is written to the output latch
(PMnm = 0)
In the port mode (PMCn = 0), the contents of the output
.
Reading from Pn Register
The value of the output latch is read.
latch are output from the pins.
Input mode
Data is written to the output latch.
(PMnm = 1)
The pin status is not affected
Note
The pin status is read.
.
Note The value written to the output latch is retained until a new value is written to the output latch.
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(2) Port n mode register (PMn)
The PMn register specifies the input or output mode of the corresponding port pin.
Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit
units.
After reset: FFH
PMn
PMn7
R/W
PMn6
PMn5
PMnm
PMn4
PMn3
PMn2
PMn1
PMn0
Control of input/output mode
0
Output mode
1
Input mode
(3) Port n mode control register (PMCn)
The PMCn register specifies the port mode or alternate function.
Each bit of this register corresponds to one pin of port n, and the mode of the port can be specified in 1-bit units.
After reset: 00H
PMCn
PMCn7
R/W
PMCn6
PMCnm
PMCn5
PMCn4
PMCn2
PMCn1
PMCn0
Specification of operation mode
0
Port mode
1
Alternate-function mode
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CHAPTER 4 PORT FUNCTIONS
(4) Port n function control register (PFCn)
The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions.
Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in
1-bit units.
After reset: 00H
PFCn
PFCn7
R/W
PFCn6
PFCn5
PFCnm
PFCn4
PFCn3
PFCn2
PFCn1
PFCn0
Specification of alternate function
0
Alternate function 1
1
Alternate function 2
(5) Port n function control expansion register (PFCEn)
The PFCEn register specifies the alternate function of a port pin to be used if the pin has three or more alternate
functions.
Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in
1-bit units.
After reset: 00H
PFCEn
PFCn
R/W
PFCEn7 PFCEn6
PFCEn5 PFCEn4
PFCEn3 PFCEn2
PFCEn1
PFCEn0
PFCn7
PFCn6
PFCn5
PFCn3
PFCn1
PFCn0
PFCEnm
PFCnm
0
0
Alternate function 1
0
1
Alternate function 2
1
0
Alternate function 3
1
1
Alternate function 4
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PFCn2
Specification of alternate function
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(6) Port n function register (PFn)
The PFn register specifies normal output or N-ch open-drain output.
Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in 1bit units.
After reset: 00H
PFn
PFn7
PFnmNote
PFn6
R/W
PFn5
PFn4
PFn3
PFn2
PFn1
PFn0
Control of normal output/N-ch open-drain output
0
Normal output (CMOS output)
1
N-ch open-drain output
Note The PFnm bit of the PFn register is valid only when the PMnm bit of the PMn register is 0 (when the
output mode is specified) in port mode (PMCnm bit = 0). When the PMnm bit is 1 (when the input mode
is specified), the set value of the PFn register is invalid.
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(7) Port setting
Set a port as illustrated below.
Figure 4-3. Setting of Each Register and Pin Function
Port mode
Output mode
“0”
PMn register
Input mode
“1”
Alternate function
(when two alternate
functions are available)
“0”
“0”
Alternate function 1
PFCn register
Alternate function 2
PMCn register
“1”
Alternate function
(when three or more alternate
functions are available)
“1”
Alternate function 1
(a)
Alternate function 2
(b)
PFCn register
(c)
PFCEn register
Alternate function 3
(d)
Alternate function 4
Remark
(a)
(b)
(c)
(d)
PFCEnm
PFCnm
0
0
1
1
0
1
0
1
Set the alternate functions in the following sequence.
Set the PFCn and PFCEn registers.
Set the PMCn register.
Set the INTRn or INTFn register (to specify an external interrupt pin).
If the PMCn register is set first, an unintended function may be set while the PFCn and PFCEn
registers are being set.
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CHAPTER 4 PORT FUNCTIONS
Port 0
Port 0 is 4-bit (V850ES/JG3-H)/6-bit (V850ES/JH3-H) port for which I/O settings can be controlled in 1-bit units.
Port 0 includes the following alternate-function pins.
Table 4-6. Port 0 Alternate-Function Pins
Pin Name
Pin No.
Alternate-Function Pin Name
V850ES/
V850ES/
JG3-H
JH3-H
I/O
P00
−
8
INTP00
Input
P01
−
9
INTP01
Input
P02
6
6
NMI
Input
P03
7
7
INTP02/ADTRG/UCLK
Input
P04
20
26
INTP03
Input
P05
21
27
INTP04
Input
Caution
Remark
Selectable as N-ch open-drain output
The P00 to P05 pins have hysteresis characteristics in the input mode of the alternate function, but
do not have hysteresis characteristics in the port mode.
(1) Port 0 register (P0)
(a) V850ES/JG3-H
After reset: 00H (output latch)
P0
R/W
Address: FFFFF400H
7
6
5
4
3
2
1
0
0
0
P05
P04
P03
P02
0
0
P0n
Output data control (in output mode) (n = 2 to 5)
0
Outputs 0.
1
Outputs 1.
(b) V850ES/JH3-H
After reset: 00H (output latch)
P0
R/W
Address: FFFFF400H
7
6
5
4
3
2
1
0
0
0
P05
P04
P03
P02
P01
P00
P0n
Output data control (in output mode) (n = 2 to 5)
0
Outputs 0.
1
Outputs 1.
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(2) Port 0 mode register (PM0)
(a) V850ES/JG3-H
After reset: FFH
PM0
R/W
Address: FFFFF420H
7
6
5
4
3
2
1
0
1
1
PM05
PM04
PM03
PM02
1
1
PM0n
I/O mode control (n = 2 to 5)
0
Output mode
1
Input mode
(b) V850ES/JH3-H
After reset: FFH
PM0
R/W
Address: FFFFF420H
7
6
5
4
3
2
1
0
1
1
PM05
PM04
PM03
PM02
PM01
PM00
PM0n
I/O mode control (n = 0 to 5)
0
Output mode
1
Input mode
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(3) Port 0 mode control register (PMC0)
(1/2)
(a) V850ES/JG3-H
After reset: 00H
PMC0
R/W
Address: FFFFF440H
7
6
5
4
3
2
1
0
0
0
PMC05
PMC04
PMC03
PMC02
0
0
PMC05
Specification of P05 pin operation mode
0
I/O port
1
INTP04 input
PMC04
Specification of P04 pin operation mode
0
I/O port
1
INTP03 input
PMC03
Specification of P03 pin operation mode
0
I/O port
1
INTP02 input/ADTRG input/UCLK input
PMC02
Specification of P02 pin operation mode
0
I/O port
1
NMI input
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(2/2)
(b) V850ES/JH3-H
After reset: 00H
PMC0
R/W
Address: FFFFF440H
7
6
5
4
3
2
1
0
0
0
PMC05
PMC04
PMC03
PMC02
PMC01
PMC00
PMC05
Specification of P05 pin operation mode
0
I/O port
1
INTP04 input
PMC04
Specification of P04 pin operation mode
0
I/O port
1
INTP03 input
PMC03
Specification of P03 pin operation mode
0
I/O port
1
INTP02 input/ADTRG input/UCLK input
PMC02
Specification of P02 pin operation mode
0
I/O port
1
NMI input
PMC01
Specification of P01 pin operation mode
0
I/O port
1
INTP01 input
PMC00
Specification of P00 pin operation mode
0
I/O port
1
INTP00 input
(4) Port 0 function control register (PFC0)
After reset: 00H
PFC0
Remark
R/W
Address: FFFFF460H
7
6
5
4
3
2
1
0
0
0
0
0
PFC03
0
0
0
For details of alternate function specification, see 4.3.1 (6) Port 0 alternate function
specifications.
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(5) Port 0 function control expansion register (PFCE0)
After reset: 00H
PFCE0
Remark
R/W
Address: FFFFF700H
7
6
5
4
3
2
1
0
0
0
0
0
PFCE03
0
0
0
For details of alternate function specification, see 4.3.1 (6) Port 0 alternate function
specifications.
(6) Port 0 alternate function specifications
PFCE03
PFC03
Specification of P03 pin alternate function
0
0
INTP02 input
0
1
ADTRG input
1
0
UCLK input
1
1
Setting prohibited
(7) Port 0 function register (PF0)
(a) V850ES/JG3-H
After reset: 00H
PF0
R/W
Address: FFFFFC60H
7
6
5
4
3
2
1
0
0
0
PF05
PF04
PF03
PF02
0
0
PF0n
Control of normal output or N-ch open-drain output (n = 2-5)
0
Normal output
1
N-ch open-drain output
(b) V850ES/JH3-H
After reset: 00H
PF0
R/W
Address: FFFFFC60H
7
6
5
4
3
2
1
0
0
0
PF05
PF04
PF03
PF02
PF01
PF00
PF0n
Control of normal output or N-ch open-drain output (n = 0 to 5)
0
Normal output
1
N-ch open-drain output
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CHAPTER 4 PORT FUNCTIONS
Port 1
Port 1 is a 2-bit port for which I/O settings can be controlled in 1-bit units.
Port 1 includes the following alternate-function pins.
Table 4-7. Port 1 Alternate-Function Pins
Pin Name
Pin No.
Alternate-Function Pin Name
V850ES/
V850ES/
JG3-H
JH3-H
I/O
P10
3
3
ANO0
Output
P11
4
4
ANO1
Output
Caution
Remark
−
When the power is turned on, the P10 and P11 pins may output an undefined level temporarily even
during reset.
(1) Port 1 register (P1)
After reset: 00H (output latch)
P1
Address: FFFFF402H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
P11
P10
P1n
Caution
R/W
Output data control (in output mode) (n = 0, 1)
0
Outputs 0.
1
Outputs 1.
Do not read or write the P1 register during D/A conversion (see 16.4.3 Cautions).
(2) Port 1 mode register (PM1)
After reset: FFH
PM1
R/W
Address: FFFFF422H
7
6
5
4
3
2
1
0
1
1
1
1
1
1
PM11
PM10
PM1n
I/O mode control (n = 0, 1)
0
Output mode
1
Input mode
Cautions 1. When using P1n as the alternate function (ANOn pin output), set the PM1n bit
to 1.
2. When using one of the PM10 and PM11 pins as an I/O port and the other as a
D/A output pin, do so in an application where the port I/O level does not change
during D/A output.
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CHAPTER 4 PORT FUNCTIONS
Port 2 (V850ES/JH3-H only)
Port 2 is a 6-bit port for which I/O settings can be controlled in 1-bit units.
Port 2 includes the following alternate-function pins.
Table 4-8. Port 2 Alternate-Function Pins
Pin Name
Pin No.
Alternate-Function Pin Name
V850ES/
V850ES/
JG3-H
JH3-H
I/O
P20
−
32
TIAB03/KR2/TOAB03/RTP02
I/O
P21
−
33
SIF2/KR3/TIAB00/TOAB00
I/O
Remark
Selectable as N-ch open-drain output
/RTP03
P22
−
34
SOF2/KR4/RTP04
I/O
P23
−
35
SCKF2/KR5/RTP05
I/O
P24
−
36
INTP05
Input
P25
−
28
INTP06
Input
Caution
The P20 to P25 pins have hysteresis characteristics in the input mode of the alternate-function pin,
but do not have the hysteresis characteristics in the port mode.
(1) Port 2 register (P2)
After reset: 00H (output latch)
P2
R/W
Address: FFFFF404H
7
6
5
4
3
2
1
0
0
0
P25
P24
P23
P22
P21
P20
P2n
Output data control (in output mode) (n = 0 to 5)
0
Outputs 0.
1
Outputs 1.
(2) Port 2 mode register (PM2)
After reset: FFH
PM2
R/W
Address: FFFFF424H
7
6
5
4
3
2
1
0
1
1
PM25
PM24
PM23
PM22
PM21
PM20
PM2n
I/O mode control (n = 0 to 5)
0
Output mode
1
Input mode
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(3) Port 2 mode control register (PMC2)
After reset: 00H
PMC2
R/W
Address: FFFFF444H
7
6
5
4
3
2
1
0
0
0
PMC25
PMC24
PMC23
PMC22
PMC21
PMC20
PMC25
Specification of P25 pin operation mode
0
I/O port
1
INTP06 input
PMC24
Specification of P24 pin operation mode
0
I/O port
1
INTP05 input
PMC23
Specification of P23 pin operation mode
0
I/O port
1
SCKF2 I/O/KR5 input/RTP05 output
PMC22
Specification of P22 pin operation mode
0
I/O port
1
SOF2 output/KR4 input/RTP04 output
PMC21
Specification of P21 pin operation mode
0
I/O port
1
SIF2 output/KR3 input/TIAB00 input/TOAB00 output/RTP03 output
PMC20
Specification of P20 pin operation mode
0
I/O port
1
TIAB03 input/KR2 input/TOAB03 output/RTP02 output
(4) Port 2 function control register (PFC2)
After reset: 00H
PFC2
Remark
R/W
Address: FFFFF464H
7
6
5
4
3
2
1
0
0
0
0
0
PFC23
PFC22
PFC21
PFC20
For details of alternate function specification, see 4.3.3 (6) Port 2 alternate function
specifications.
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CHAPTER 4 PORT FUNCTIONS
(5) Port 2 function control expansion register (PFCE2)
After reset: 00H
PFCE2
Remark
R/W
Address: FFFFF704H
7
6
5
4
3
0
0
0
0
PFCE23
2
1
0
PFCE22 PFCE21 PFCE20
For details of alternate function specification, see 4.3.3 (6) Port 2 alternate function
specifications.
(6) Port 2 alternate function specifications
PFCE23
PFC23
Specification of P23 pin alternate function
0
0
SCKF2 I/O
0
1
KR5 input
1
0
RTP05 output
1
1
Setting prohibited
PFCE22
PFC22
0
0
SOF2 output
0
1
KR4 input
1
0
RTP04 output
1
1
Setting prohibited
PFCE21
PFC21
0
0
SIF2 input
0
1
KR3 input/TIAB00 input
Specification of P22 pin alternate function
Specification of P21 pin alternate function
1
0
TOAB00 output
1
1
RTP03 output
Note
Note KR3 and TIAB00 are alternate functions. When using the pin as the TIAB00 pin, disable the KR3 pin key
return detection, which is the alternate function (clear the KRM.KRM3 bit to 0). Also, when using the pin
as the KRn pin, disable TIAB00 pin edge detection, which is the alternate function (TAB0IOC1.TAB0TIG0,
TAB0TIG1 bit = 00 B, TAB0IOC2 register = 00H).
PFCE20
PFC20
0
0
TIAB03 input/KR02 input
0
1
KR2 input
1
0
TOAB03 output
1
1
Setting prohibited
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CHAPTER 4 PORT FUNCTIONS
(7) Port 2 function register (PF2)
After reset: 00H
PF2
R/W
Address: FFFFFC64H
7
6
5
4
3
2
1
0
0
0
PF25
PF24
PF23
PF22
PF21
PF20
PF2n
Control of normal output or N-ch open-drain output (n = 0 to 5)
0
Normal output
1
N-ch open-drain output
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CHAPTER 4 PORT FUNCTIONS
Port 3
Port 3 is a 10-bit port that controls I/O in 1-bit units.
Port 3 includes the following alternate-function pins.
Table 4-9. Port 3 Alternate-Function Pins
Pin Name
Pin No.
Alternate-Function Pin Name
V850ES/
V850ES/
JG3-H
JH3-H
I/O
Selectable as N-ch open-drain output
P30
25
37
TXDC0/SOF4/INTP07
I/O
P31
26
38
RXDC0/SIF4/INTP08
Input
P32
27
39
ASCKC0/SCKF4/TIAA00/TOAA00
I/O
P33
28
40
TIAA01/TOAA01/RTCDIV/RTCCL
I/O
P34
29
41
TIAA10/TOAA10/TOAA1OFF/INTP09
I/O
P35
30
42
TIAA11/TOAA11/RTC1HZ
I/O
Note
P36
31
43
TXDC3/SCL00/CTXD0
P37
32
44
RXDC3/SDA00/CRXD0
/UDMARQ0
Note
/UDMAAK0
Remark
I/O
I/O
Note μPD70F3770, 70F3771 only
Caution
The P30 to P37 pins have hysteresis characteristics in the input mode of the alternate-function pin,
but do not have the hysteresis characteristics in the port mode.
(1) Port 3 register (P3)
After reset: 00H (output latch)
P3
R/W
Address: FFFFF406H
7
6
5
4
3
2
1
0
P37
P36
P35
P34
P33
P32
P31
P30
P3n
Output data control (in output mode) (n = 0 to 7)
0
Outputs 0.
1
Outputs 1.
(2) Port 3 mode register (PM3)
After reset: FFH
PM3
R/W
Address: FFFFF426H
7
6
5
4
3
2
1
0
PM37
PM36
PM35
PM34
PM33
PM32
PM31
PM30
PM3n
I/O mode control (n = 0 to 7)
0
Output mode
1
Input mode
(3) Port 3 mode control register (PMC3)
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After reset: 00H
PMC3
PMC37
CHAPTER 4 PORT FUNCTIONS
R/W
PMC36
PMC37
Address: FFFFF446H
PMC35
PMC34
PMC33
PMC32
PMC31
PMC30
Specification of P37 pin operation mode
0
I/O port
1
RXDC3 input/SDA00 I/O/CRXD inputNote/UDMAAK0 output
PMC36
Specification of P36 pin operation mode
0
I/O port
1
TXDC3 output/SCL00 I/O/CTXD0 outputNote/UDMARQ0 input
PMC35
Specification of P35 pin operation mode
0
I/O port
1
TIAA11 input/TOAA11 output/RTC1HZ output
PMC34
Specification of P34 pin operation mode
0
I/O port
1
TIAA10 input/TOAA10 output/TOAA1OFF input/INTP09 input
PMC33
Specification of P33 pin operation mode
0
I/O port
1
TIAA01 input/TOAA01 output/RTCDIV output/RTCCL output
PMC32
Specification of P32 pin operation mode
0
I/O port
1
ASCKA0 input/SCKF4 I/O/TIAA00 input/TOAA00 output
PMC31
Specification of P31 pin operation mode
0
I/O port
1
RXDC0 input/SIF4 input/INTP08 input
PMC30
Specification of P30 pin operation mode
0
I/O port
1
TXDC0 output/SOF4 output/INTP07 input
Note μPD70F3770, 70F3771 only
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(4) Port 3 function control register (PFC3)
After reset: 00H
PFC3
Remark
PFC37
R/W
Address: FFFFF466H
PFC36
PFC35
PFC34
PFC33
PFC32
PFC31
PFC30
For details of alternate function specification, see 4.3.4 (6) Port 3 alternate function
specifications.
(5) Port 3 function control expansion register (PFCE3)
After reset: 00H
PFCE3
Remark
R/W
Address: FFFFF706H
PFCE37 PFCE36
PFCE35 PFCE34
PFCE33 PFCE32
PFCE31
PFCE30
For details of alternate function specification, see 4.3.4 (6) Port 3 alternate function
specifications.
(6) Port 3 alternate function specifications
PFCE37
PFC37
Specification of P37 pin alternate function
0
0
RXDC3 input
0
1
SDA00 I/O
1
0
CRXD0 input
1
1
UDMAAK0 output
Note
Note μPD70F3770, 70F3771 only
PFCE36
PFC36
Specification of P36 pin alternate function
0
0
TXDC3 output
0
1
SCL00 I/O
1
0
CTXD0 output
1
1
UDMARQ0 input
Note
Note μPD70F3770, 70F3771 only
PFCE35
PFC35
0
0
TIAA11 input
0
1
TOAA11 output
1
0
RTC1HZ output
1
1
Setting prohibited
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CHAPTER 4 PORT FUNCTIONS
PFCE34
PFC34
Specification of P34 pin alternate function
0
0
TIAA10 input
0
1
TOAA10 output
1
0
TOAA1OFF input/INTP09 input
1
1
Setting prohibited
Note
Note TOAA1OFF and INTP09 are alternate functions. When using the pin as the TOAA1OFF pin, disable
INTP09 pin edge detection, which is the alternate function. Also, when using the pin as the INTP09 pin,
stop the high-impedance output controller.
PFCE33
PFC33
Specification of P33 pin alternate function
0
0
TIAA01 iput
0
1
TOAA01 output
1
0
RTCDIV output
1
1
RTCCL output
PFCE32
PFC32
0
0
ASCKC0 input
0
1
SCKF4 I/O
1
0
TIAA00 input
1
1
TOAA00 output
PFCE31
PFC31
Specification of P32 pin alternate function
Specification of P31 pin alternate function
0
0
RXDC0 input
0
1
SIF4 input
1
0
INTP08 input
1
1
Setting prohibited
PFCE30
PFC30
0
0
TXDC0 output
0
1
SOF4 output
1
0
INTP07 input
1
1
Setting prohibited
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CHAPTER 4 PORT FUNCTIONS
(7) Port 3 function register (PF3)
After reset: 00H
PF3
PF37
PF3n
R/W
Address:
PF36
PF35
FFFFFC66H
PF34
PF32
PF31
PF30
Control of normal output or N-ch open-drain output (n = 0 to 7)
0
Normal output (CMOS output)
1
N-ch open-drain output
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4.3.5
CHAPTER 4 PORT FUNCTIONS
Port 4
Port 4 is a 3-bit port that controls I/O in 1-bit units.
Port 4 includes the following alternate-function pins.
Table 4-10. Port 4 Alternate-Function Pins
Pin Name
Pin No.
Alternate-Function Pin Name
V850ES/
V850ES/
JG3-H
JH3-H
I/O
P40
22
29
SIF0/TXDC4/SDA01
I/O
P41
23
30
SOF0/RXDC4/SCL01
I/O
P42
24
31
SCKF0/INTP10
I/O
Caution
Remark
Selectable as N-ch open-drain output
The P40 to P42 pins have hysteresis characteristics in the input mode of the alternate-function pin,
but do not have the hysteresis characteristics in the port mode.
(1) Port 4 register (P4)
After reset: 00H (output latch)
P4
0
0
R/W
0
P4n
Address: FFFFF408H
0
0
P42
P41
P40
Output data control (in output mode) (n = 0 to 2)
0
Outputs 0.
1
Outputs 1.
(2) Port 4 mode register (PM4)
After reset: FFH
PM4
1
R/W
Address: FFFFF428H
1
PM4n
1
1
PM42
PM41
PM40
I/O mode control (n = 0 to 2)
0
Output mode
1
Input mode
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CHAPTER 4 PORT FUNCTIONS
(3) Port 4 mode control register (PMC4)
After reset: 00H
PMC4
0
R/W
Address: FFFFF448H
0
0
PMC42
0
0
PMC42
PMC41
PMC40
Specification of P42 pin operation mode
0
I/O port
1
SCKF0 I/O/INTP10 input
PMC41
Specification of P41 pin operation mode
0
I/O port
1
SOF0 output/RXDC4 input/SCL01 I/O
PMC40
Specification of P40 pin operation mode
0
I/O port
1
SIF0 input/TXDC4 output/SDA01 I/O
(4) Port 4 function control register (PFC4)
After reset: 00H
PFC4
Remark
0
R/W
0
Address: FFFFF468H
0
0
0
PFC42
PFC41
PFC40
For details of alternate function specification, see 4.3.5 (6) Port 4 alternate function
specifications.
(5) Port 4 function control expansion register (PFCE4)
After reset: 00H
PFCE4
Remark
0
R/W
0
Address: FFFFF708H
0
0
0
0
PFCE41
PFCE40
For details of alternate function specification, see 4.3.5 (6) Port 4 alternate function
specifications.
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(6) Port 4 alternate function specifications
PFC42
Specification of P42 pin alternate function
0
SCKF0 I/O
1
INTP10 input
PFCE41
PFC41
Specification of P41 pin alternate function
0
0
SOF0 output
0
1
RXDC4 input
1
0
SCL01 I/O
1
1
Setting prohibited
PFCE40
PFC40
0
0
SIF0 input
0
1
TXDC4 output
1
0
SDA01 I/O
1
1
Setting prohibited
Specification of P40 pin alternate function
(7) Port 4 function register (PF4)
After reset: 00H
PF4
0
PF4n
R/W
0
Address: FFFFFC68H
0
0
PF42
PF41
PF40
Control of normal output or N-ch open-drain output (n = 0 to 2)
0
Normal output (CMOS output)
1
N-ch open-drain output
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4.3.6
CHAPTER 4 PORT FUNCTIONS
Port 5
Port 5 is 6-bit (V850ES/JG3-H)/2-bit (V850ES/JH3-H) port that controls I/O in 1-bit units.
Port 5 includes the following alternate-function pins.
Table 4-11. Port 5 Alternate-Function Pins
Pin Name
P50
Pin No.
V850ES/
V850ES/
JG3-H
JH3-H
35
47
Alternate-Function Pin Name
TIAB01/KR0/TOAB01/RTP00
I/O
I/O
Remark
Selectable as N-ch open-drain output
/UDMARQ1
P51
36
48
TIAB02/KR1/TOAB02/RTP01
I/O
/UDMAAK1
P52
37
−
TIAB03/KR2/TOAB13/RTP02
/DDI
P53
38
−
I/O
Note
SIF2/TIAB00/KR3/TOAB10
I/O
Note
/RTP03/DDO
P54
P55
P56
39
−
40
−
41
−
SOF2/KR4/RTP04/DCK
Note
SCKF2/KR5/RTP05/DMS
Note
INTP05/DRST
Note
I/O
I/O
Input
Note The DDI, DDO, DCK, DMS, and DRST pins are used for on-chip debugging.
If on-chip debugging is not used, fix the P05/INTP02/DRST pin to low level between when the reset by the
RESET pin is released and when the OCDM.OCDM0 bit is cleared (0).
For details, see 4.5.3 Cautions on on-chip debug pins.
Cautions 1. When the power is turned on, the P53 pin may output an undefined level temporarily even during
reset.
2. The P50 to P56 pins have hysteresis characteristics in the input mode of the alternate-function
pin, but do not have the hysteresis characteristics in the port mode.
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(1) Port 5 register (P5)
(a) V850ES/JG3-H
After reset: 00H (output latch)
P5
0
P56
P5n
R/W
P55
Address: FFFFF40AH
P54
P53
P52
P51
P50
Output data control (in output mode) (n = 0 to 6)
0
Outputs 0.
1
Outputs 1.
(b) V850ES/JH3-H
After reset: 00H (output latch)
P5
0
0
P5n
0
Address: FFFFF40AH
0
0
0
P51
P50
Output data control (in output mode) (n = 0, 1)
0
Outputs 0.
1
Outputs 1.
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CHAPTER 4 PORT FUNCTIONS
(2) Port 5 mode register (PM5)
(a) V850ES/JG3-H
After reset: FFH
R/W
PM5
PM56
1
Address: FFFFF42AH
PM55
PM5n
PM54
PM53
PM52
PM51
PM50
PM51
PM50
I/O mode control (n = 0 to 6)
0
Output mode
1
Input mode
(b) V850ES/JH3-H
After reset: FFH
PM5
1
R/W
Address: FFFFF42AH
1
PM5n
1
1
1
I/O mode control (n = 0, 1)
0
Output mode
1
Input mode
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CHAPTER 4 PORT FUNCTIONS
(3) Port 5 mode control register (PMC5)
(a) V850ES/JG3-H
After reset: 00H
PMC5
0
R/W
PMC56
Address: FFFFF44AH
PMC55
PMC56
PMC54
PMC53
PMC52
PMC51
PMC50
Specification of P56 pin operation mode
0
I/O port
1
INTP05 input
PMC55
Specification of P55 pin operation mode
0
I/O port
1
SCKF2 I/O/KR5 input/RTP05 output
PMC54
Specification of P54 pin operation mode
0
I/O port
1
SOF2 output/KR4 input/RTP04 output
PMC53
Specification of P53 pin operation mode
0
I/O port
1
SIF2 input/KR3 input/TIAB00 input/TOAB00 output/RTP03 output
PMC52
Specification of P52 pin operation mode
0
I/O port
1
TIAB03 input/KR2 input/TOAB03 output/RTP02 output
PMC51
Specification of P51 pin operation mode
0
I/O port
1
TIAB02 input/KR1 input/TOAB02 output/RTP01 output/UDMAAK1 output
PMC50
Specification of P50 pin operation mode
0
I/O port
1
TIAB01 input/KR0 input/TOAB01 output/RTP00 output/UDMARQ1 input
(b) V850ES/JH3-H
After reset: 00H
PMC5
0
R/W
0
PMC51
Address: FFFFF44AH
0
0
0
0
PMC51
PMC50
Specification of P51 pin operation mode
0
I/O port
1
TIAB02 input/KR1 input/TOAB02 output/RTP01 output/UDMAAK1 output
PMC50
Specification of P50 pin operation mode
0
I/O port
1
TIAB01 input/KR0 input/TOAB01 output/RTP00 output/UDMARQ1 input
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(4) Port 5 function control register (PFC5)
(a) V850ES/JG3-H
After reset: 00H
PFC5
R/W
0
Address: FFFFF46AH
0
PFC55
PFC54
PFC53
PFC52
PFC51
PFC50
0
0
PFC51
PFC50
(b) V850ES/JH3-H
After reset: 00H
PFC5
Remark
R/W
0
Address: FFFFF46AH
0
0
0
For details of alternate function specification, see 4.3.6 (6) Port 5 alternate function
specifications.
(5) Port 5 function control expansion register (PFCE5)
(a) V850ES/JG3-H
After reset: 00H
PFCE5
R/W
0
Address: FFFFF70AH
0
PFCE55 PFCE54
PFCE53 PFCE52
PFCE51
PFCE50
PFCE51
PFCE50
(b) V850ES/JH3-H
After reset: 00H
PFCE5
Remark
R/W
0
Address: FFFFF70AH
0
0
0
0
0
For details of alternate function specification, see 4.3.6 (6) Port 5 alternate function
specifications.
(6) Port 5 alternate function specifications
PFCE55
Note 1
PFC55
Note 1
Specification of P55 pin alternate function
0
0
SCKF2 I/O
0
1
KR5 input
1
0
RTP05 output
1
1
Setting prohibited
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PFCE54
Note 1
PFC54
CHAPTER 4 PORT FUNCTIONS
Note 1
Specification of P54 pin alternate function
0
0
SOF2 output
0
1
KR4 input
1
0
RTP04 output
1
1
Setting prohibited
PFCE53
Note 1
PFC53
Note 1
Specification of P53 pin alternate function
0
0
SIF2 input
0
1
TIAB00 input/KR3
1
0
TOAB00 output
1
1
RTP03 output
PFCE52
Note1
PFC52
Note1
Note 2
0
TIAB03 input/KR2
0
1
TOAB03 output
1
0
RTP02 output
1
1
Setting prohibited
PFCE51
PFC51
0
0
TIAB02 input/KR1
0
1
TOAB02 output
1
0
RTP01 output
1
1
UDMAAK1 output
PFCE50
PFC50
0
0
TIAB01 input/KR0
0
1
TOAB01 output
1
0
RTP00 output
1
1
UDMARQ1 input
Note 2
Note 1
input
Specification of P52 pin alternate function
0
Note 1
Note 1
input
Specification of P51 pin alternate function
Note 2
input
Specification of P50 pin alternate function
Note 2
input
Notes 1. V850ES/JG3-H only
2. KRn and TIAB0m are alternate functions. When using the pin as the TIAB0m pin, disable KRn pin key
return detection, which is the alternate function (clear the KRM.KRMn bit to 0). Also, when using the
pin as the KRn pin, disable TIAB0m pin edge detection, which is the alternate function (n = 0 to 3, m =
0 to 3).
Pin Name
Use as TIAB0m Pin
Using as KRn Pin
KR0/TIAB01
KRM.KRM0 bit = 0
TAB0IOC1.TAB0TIG2, TAB0TIG3 bits = 0
KR1/TIAB02
KRM.KRM1 bit = 0
TAB0IOC1.TAB0TIG4, TAB0TIG5 bits = 0
KR2/TIAB03
KRM.KRM2 bit = 0
TAB0IOC1.TAB0TIG6, TAB0TIG7 bits = 0
KR3/TIAB00
KRM.KRM3 bit = 0
TAB0IOC1.TAB0TIG0, TAB0TIG1 bits = 0
TAB0IOC2.TAB0EES0, TAB0EES1 bits = 0
TAB0IOC2.TAB0ETS0, TAB0ETS1 bits = 0
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(7) Port 5 function register (PF5)
(a) V850ES/JG3-H
After reset: 00H
PF5
0
R/W
Address: FFFFFC6AH
PF56
PF5n
PF55
PF54
PF53
PF52
PF51
PF50
Control of normal output or N-ch open-drain output (n = 0 to 6)
0
Normal output (CMOS output)
1
N-ch open-drain output
(b) V850ES/JH3-H
After reset: 00H
PF5
0
PF5n
R/W
0
Address: FFFFFC6AH
0
0
0
PF51
PF50
Control of normal output or N-ch open-drain output (n = 0, 1)
0
Normal output (CMOS output)
1
N-ch open-drain output
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4.3.7
CHAPTER 4 PORT FUNCTIONS
Port 6
Port 6 is a 6-bit port for which I/O settings can be controlled in 1-bit units.
Port 6 includes the following alternate-function pins.
Table 4-12. Port 6 Alternate-Function Pins
Pin Name
P60
Pin No.
Alternate-Function Pin Name
V850ES/
V850ES/
JG3-H
JH3-H
65
90
TOAB1T1/TOAB11/TIAB11
I/O
Remark
−
I/O
Note
/WAIT
P61
66
91
TOAB1B1/TOAB10/TIAB10
I/O
Note
/RD
P62
67
92
TOAB1T2/TOAB12/TIAB12
/ASTB
I/O
Note
P63
68
93
TOAB1B2/TRGAB1/CS0
Note
I/O
P64
69
94
TOAB1T3/TOAB13/TIAB13
I/O
Note
/CS2
P65
70
95
TOAB1B3/EVTAB1/CS3
Note
I/O
Note V850ES/JG3-H only
Caution
The P60 to P65 pins have hysteresis characteristics in the input mode of the alternate-function pin,
but do not have the hysteresis characteristics in the port mode.
(1) Port 6 register (P6)
After reset: 00H (output latch)
P6
0
0
P6n
P65
Address: FFFFF40CH
P64
P63
P62
P61
P60
Output data control (in output mode) (n = 0 to 5)
0
Outputs 0.
1
Outputs 1.
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CHAPTER 4 PORT FUNCTIONS
(2) Port 6 mode register (PM6)
After reset: FFH
PM6
1
R/W
Address: FFFFF42CH
1
PM65
PM6n
PM64
PM63
PM62
PM61
PM60
Output data control (in output mode) (n = 0 to 5)
0
Output mode
1
Input mode
(3) Port 6 mode control register (PMC6)
After reset: 00H
PMC6
0
R/W
0
PMC65
Address: FFFFF44CH
PMC65
PMC64
PMC63
PMC62
PMC61
PMC60
Specification of P65 pin operation mode
0
I/O port
1
TOAB1B3 output/EVTAB1 input/CS3 outputNote
PMC64
Specification of P64 pin operation mode
0
I/O port
1
TOAB1T3 output/TOAB13 output/TIAB13 input/CS2 outputNote
PMC63
Specification of P63 pin operation mode
0
I/O port
1
TOAB1B2 output/TRGAB1 input/CS0 outputNote
PMC62
Specification of P62 pin operation mode
0
I/O port
1
TOAB1T2 output/TOAB12 output/TIAB12 output/ASTB outputNote
PMC61
Specification of P61 pin operation mode
0
I/O port
1
TOAB1B1 output/TIAB10 input/TOAB10 output/RD outputNote
PMC60
Specification of P60 pin operation mode
0
I/O port
1
TOAB1T1 output/TOAB11 output/TIAB11 input/WAIT outputNote
Note V850ES/JG3-H only
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CHAPTER 4 PORT FUNCTIONS
(4) Port 6 function control register (PFC6)
After reset: 00H
PFC6
Remark
0
R/W
Address: FFFFF46CH
0
PFC65
PFC64
PFC63
PFC62
PFC61
PFC60
For details of alternate function specification, see 4.3.7 (6) Port 6 alternate function
specifications.
(5) Port 6 function control expansion register (PFCE6)
(a) V850ES/JG3-H
After reset: 00H
PFCE6
0
R/W
Address: FFFFF70CH
0
PFCE65 PFCE64
PFCE63 PFCE62
PFCE61
PFCE60
PFCE61
0
(b) V850ES/JH3-H
After reset: 00H
PFCE6
Remark
0
R/W
Address: FFFFF70CH
0
0
0
0
0
For details of alternate function specification, see 4.3.7 (6) Port 6 alternate function
specifications.
(6) Port 6 alternate function specifications
PFCE65
Note
PFC65
Specification of P65 pin alternate function
0
0
TOAB1B3 output
0
1
EVTAB1 input
1
0
CS3 output
1
1
Setting prohibited
PFCE64
Note
Note
PFC64
Note
Specification of P64 pin alternate function
0
0
TOAB1T3 output/TOAB13 output
0
1
TIAB13 input
1
0
CS2 output
1
1
Setting prohibited
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Note
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PFCE63
Note
CHAPTER 4 PORT FUNCTIONS
PFC63
Specification of P63 pin alternate function
0
0
TOAB1B2 output
0
1
TRGAB1 input
1
0
CS0 output
1
1
Setting prohibited
PFCE62
Note
Note
PFC62
Note
Specification of P62 pin alternate function
0
0
TOAB1T2 output/TOAB12 output
0
1
TIAB12 input
1
0
ASTB output
1
1
Setting prohibited
PFCE61
PFC61
0
0
TOAB1B1 output
0
1
TIAB10 input
1
0
TOAB10 output
1
1
RD output (V850ES/JG3-H)
Note
Note
Specification of P61 pin alternate function
Setting prohibited (V850ES/JH3-H)
PFCE60
Note
PFC60
Specification of P60 pin alternate function
0
0
TOAB1T1 output/TOAB11 output
0
1
TIAB11 input
1
0
WAIT output
1
1
Setting prohibited
Note
Note
Note V850ES/JG3-H only
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4.3.8
CHAPTER 4 PORT FUNCTIONS
Port 7
Port 7 is a 12-bit port for which I/O settings can be controlled in 1-bit units.
Port 7 includes the following alternate-function pins.
Table 4-13. Port 7 Alternate-Function Pins
Pin Name
Pin No.
Alternate-Function Pin Name
V850ES/
V850ES/
JG3-H
JH3-H
I/O
P70
100
128
ANI0
Input
P71
99
127
ANI1
Input
P72
98
126
ANI2
Input
P73
97
125
ANI3
Input
P74
96
124
ANI4
Input
P77
95
123
ANI5
Input
P76
94
122
ANI6
Input
P77
93
121
ANI7
Input
P78
92
120
ANI8
Input
P79
91
119
ANI9
Input
P710
90
118
ANI10
Input
P711
89
117
ANI11
Input
Remark
−
(1) Port 7 register H, port 7 register L (P7H, P7L)
After reset: 00H (output latch)
R/W
Address: P7L FFFFF40EH, P7H FFFFF40FH
P7H
0
0
0
0
P711
P710
P79
P78
P7L
P77
P76
P75
P74
P73
P72
P71
P70
P7n
Caution
Output data control (in output mode) (n = 0 to 11)
0
Outputs 0.
1
Outputs 1.
Do not read or write the P7H and P7L registers during A/D conversion (see 15.6 (4)
Alternate I/O).
Remark
These registers cannot be accessed in 16-bit units as the P7 register. They can be read
or written in 8-bit or 1-bit units as the P7H and P7L registers.
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(2) Port 7 mode register H, port 7 mode register L (PM7H, PM7L)
After reset: FFH
R/W
Address: PM7L FFFFF42EH, PM7H FFFFF42FH
PM7H
1
1
1
1
PM711
PM710
PM79
PM78
PM7L
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
PM7n
Caution
Remark
I/O mode control (n = 0 to 11)
0
Output mode
1
Input mode
When using the P7n pin as its alternate function (ANIn pin), set the PM7n bit to 1.
These registers cannot be accessed in 16-bit units as the PM7 register. They can be
read or written in 8-bit or 1-bit units as the PM7H and PM7L registers.
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4.3.9
CHAPTER 4 PORT FUNCTIONS
Port 9
Port 9 is a 16-bit port for which I/O settings can be controlled in 1-bit units.
Port 9 includes the following alternate-function pins.
Table 4-14. Port 9 Alternate-Function Pins
Pin Name
P90
P91
P92
Pin No.
V850ES/
V850ES/
JG3-H
JH3-H
42
43
44
54
55
56
Alternate-Function Pin Name
Note
KR6/TXDC1/SDA02/A0
I/O
I/O
Note
KR7/RXDC1/SCL02/A1
TENC01/TIT01/TOT01/A2
I/O
Note
P93
45
57
TECR0/TIT00/TOT00/A3
I/O
P94
46
58
TIAA31/TOAA31/TENC00
I/O
P95
47
59
TIAA30/TOAA30/A5
Note
I/O
48
62
TIAA21/TOAA21/INTP11/A6
P97
49
63
SIF1/TIAA20/TOAA20/A7
P99
P910
P911
P912
P913
50
51
52
53
54
55
64
65
66
Note
Note
SOF1/INTP12/A8
I/O
I/O
Note
I/O
Note
SCKF1/INTP13/A9
I/O
Note
SIF3/TXDC2/INTP14/A10
I/O
Note
67
SOF3/RXDC2/INTP15/A11
I/O
68
Note
I/O
69
−
Note
P96
P98
Selectable as N-ch open-drain output
I/O
Note
/EVTT0/A4
Remark
SCKF3/A12
TOAB1OFF/INTP16/A13
Note
I/O
P914
56
70
TIAA51/TOAA51/INTP17/A14
Note
P915
57
71
TIAA50/TOAA50/INTP18/A15
Note
I/O
I/O
Note V850ES/JH3-H only
Caution
The P90 to P915 pins have hysteresis characteristics in the input mode of the alternate-function pin,
but do not have the hysteresis characteristics in the port mode.
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(1) Port 9 register (P9)
After reset: 0000H (output latch)
R/W
Address: P9 FFFFF412H,
P9L FFFFF412H, P9H FFFFF413H
15
14
13
12
11
10
9
8
P9 (P9H)
P915
P914
P913
P912
P911
P910
P99
P98
(P9L)
P97
P96
P95
P94
P93
P92
P91
P90
P9n
Output data control (in output mode) (n = 0 to 15)
0
Outputs 0.
1
Outputs 1.
Remarks 1. The P9 register can be read or written in 16-bit units.
However, when using the higher 8 bits of the P9 register as the P9H register and the
lower 8 bits as the P9L register, they can be read or written in 8-bit or 1-bit units.
2. To read/write bits 8 to 15 of the P9 register in 8-bit or 1-bit units, specify them as bits
0 to 7 of the P9H register.
(2) Port 9 mode register (PM9)
After reset: FFFFH
PM9 (PM9H)
(PM9L)
R/W
Address: PM9 FFFFF432H,
PM9L FFFFF432H, PM9H FFFFF433H
15
14
13
12
11
10
9
8
PM915
PM914
PM913
PM912
PM911
PM910
PM99
PM98
PM97
PM96
PM95
PM94
PM93
PM92
PM91
PM90
PM9n
I/O mode control (in output mode) (n = 0 to 15)
0
Output mode
1
Input mode
Remarks 1. The PM9 register can be read or written in 16-bit units.
However, when using the higher 8 bits of the PM9 register as the PM9H register and
the lower 8 bits as the PM9L register, they can be read or written in 8-bit and 1-bit
units.
2. To read/write bits 8 to 15 of the PM9 register in 8-bit or 1-bit units, specify them as
bits 0 to 7 of the PM9H register.
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CHAPTER 4 PORT FUNCTIONS
(3) Port 9 mode control register (PMC9)
(1/2)
After reset: 0000H
R/W
15
PMC9 (PMC9H)
(PMC9L)
14
Address: PMC9 FFFFF452H,
PMC9L FFFFF452H, PMC9H FFFFF453H
9
8
PMC915 PMC914 PMC913 PMC912 PMC911 PMC910
PMC99
PMC98
PMC97
PMC91
PMC90
PMC96
PMC915
13
PMC95
12
PMC94
11
PMC93
10
PMC92
Specification of P915 pin operation mode
0
I/O port
1
TIAA50 input/TOAA50 output/INTP18 input/A15 outputNote
PMC914
Specification of P914 pin operation mode
0
I/O port
1
TIAA51 input/TOAA51 output/INTP17 input/A14 outputNote
PMC913
Specification of P913 pin operation mode
0
I/O port
1
TOAB1OFF input/INTP16 input/A13 output
PMC912
Note
Specification of P912 pin operation mode
0
I/O port
1
SCKF3 I/O/A12 outputNote
PMC911
Specification of P911 pin operation mode
0
I/O port
1
SOF3 output/RXDC2 input/INTP15 input/A11 outputNote
PMC910
Specification of P910 pin operation mode
0
I/O port
1
SIF3 input/TXDC2 output/INTP14 input/A10 output
PMC99
Note
Specification of P99 pin operation mode
0
I/O port
1
SCKF1 I/O/INTP13 input/A9 outputNote
PMC98
Specification of P98 pin operation mode
0
I/O port
1
SOF1 output/INTP12 input/A8 output
Note
Note V850ES/JH3-H only
Remarks 1. The PMC9 register can be read or written in 16-bit units.
However, when using the higher 8 bits of the PMC9 register as the PMC9H register and
the lower 8 bits as the PMC9L register, they can be read or written in 8-bit or 1-bit units.
2. To read/write bits 8 to 15 of the PMC9 register in 8-bit or 1-bit units, specify them as bits 0
to 7 of the PMC9H register.
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CHAPTER 4 PORT FUNCTIONS
(2/2)
PMC97
Specification of P97 pin operation mode
0
I/O port
1
SIF1 input/TIAA20 input/TOAA20 output/A7 output
PMC96
Note
Specification of P96 pin operation mode
0
I/O port
1
TIAA21 input/TOAA21 output/INTP11 input/A6 output
PMC95
Note
Specification of P95 pin operation mode
0
I/O port
1
TIAA30 input/TOAA30 output/A5 output
PMC94
Note
Specification of P94 pin operation mode
0
I/O port
1
TIAA31 input/TOAA31 output/TENC00 input/EVTT0 input/A4 output
PMC93
Note
Specification of P93 pin operation mode
0
I/O port
1
TECR0 input/TIT00 input/TOT00 output/A3 output
PMC92
Note
Specification of P92 pin operation mode
0
I/O port
1
TENC01 input/TIT01 input/TOT01 output/A2 output
PMC91
Note
Specification of P91 pin operation mode
0
I/O port
1
KR7 input/RXDC1 input/SCL02 I/O/A1 output
PMC90
Note
Specification of P90 pin operation mode
0
I/O port
1
KR6 input/TXDC1 output/SDA02 I/O/A0 output
Note
Note V850ES/JH3-H only
Caution
When using the A0 to A15 pins as the alternate functions of the P90 to P915 pins,
be sure to set all 16 bits of the PMC9 register to FFFFH at once (V850ES/JH3-H
only).
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CHAPTER 4 PORT FUNCTIONS
(4) Port 9 function control register (PFC9)
Caution
When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for
all 16 bits at once after setting the PFC9 register to the FCDFH and PFCE9 register to CFFFH
(V850ES/JH3-H only).
(a) V850ES/JG3-H
After reset: 0000H
PFC9 (PFC9H)
(PFC9L)
R/W
Address:
PFC9 FFFFF472H,
PFC9L FFFFF472H, PFC9H FFFFF473H
15
14
13
12
PFC915
PFC914
0
0
PFC97
PFC96
PFC95
PFC94
9
8
PFC911 PFC910
11
10
PFC99
PFC98
PFC93
PFC91
PFC90
PFC92
(b) V850ES/JH3-H
After reset: 0000H
PFC9 (PFC9H)
(PFC9L)
R/W
Address: PFC9 FFFFF472H,
PFC9L FFFFF472H, PFC9H FFFFF473H
15
14
13
12
11
10
9
8
PFC915
PFC914
PFC913
PFC912
PFC911
PFC910
PFC99
PFC98
PFC97
PFC96
PFC95
PFC94
PFC93
PFC92
PFC91
PFC90
Remarks 1. For details of alternate function specification, see 4.3.9 (6) Port 9 alternate function
specifications.
2. The PFC9 register can be read or written in 16-bit units.
However, when using the higher 8 bits of the PFC9 register as the PFC9H register
and the lower 8 bits as the PFC9L register, they can be read or written in 8-bit or 1-bit
units.
3. To read/write bits 8 to 15 of the PFC9 register in 8-bit or 1-bit units, specify them as
bits 0 to 7 of the PFC9H register.
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CHAPTER 4 PORT FUNCTIONS
(5) Port 9 function control expansion register (PFCE9)
Caution
When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for
all 16 bits at once after setting the PFC9 register to FCDFH and the PFCE9 register to CFFFH
(V850ES/JH3-H only).
(a) V850ES/JG3-H
After reset: 0000H
15
R/W
14
PFCE9 (PFCE9H) PFCE915 PFCE914
(PFCE9L)
PFCE97 PFCE96
Address: PFCE9 FFFFF712H,
PFCE9L FFFFF712H, PFCE9H FFFFF713H
13
12
9
8
0
0
PFCE911 PFCE910
11
10
0
0
0
PFCE94
PFCE93 PFCE92
PFCE91
PFCE90
(b) V850ES/JH3-H
After reset: 0000H
15
R/W
14
PFCE9 (PFCE9H) PFCE915 PFCE914
(PFCE9L)
PFCE97 PFCE96
Address: PFCE9 FFFFF712H,
PFCE9L FFFFF712H, PFCE9H FFFFF713H
13
12
0
0
PFCE95 PFCE94
11
10
9
8
PFCE911 PFCE910 PFCE99
PFCE98
PFCE93 PFCE92
PFCE90
PFCE91
Remarks 1. For details of alternate function specification, see 4.3.9 (6) Port 9 alternate function
specifications.
2. The PFCE9 register can be read or written in 16-bit units.
However, when using the higher 8 bits of the PFCE9 register as the PFCE9H register
and the lower 8 bits as the PFCE9L register, they can be read or written in 8-bit or 1bit units.
3. To read/write bits 8 to 15 of the PFCE9 register in 8-bit or 1-bit units, specify them as
bits 0 to 7 of the PFCE9H register.
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CHAPTER 4 PORT FUNCTIONS
(6) Port 9 alternate function specifications
PFCE915
PFC915
Specification of P915 pin alternate function
0
0
TIAA50 input
0
1
TOAA50 output
1
0
INTP18 input
1
1
Setting prohibited (V850ES/JG3-H)
A15 output (V850ES/JH3-H)
PFCE914
PFC914
Specification of P914 pin alternate function
0
0
TIAA51 input
0
1
TOAA51 output
1
0
INTP17 input
1
1
Setting prohibited (V850ES/JG3-H)
A14 output (V850ES/JH3-H)
PFC913
Note
Specification of P913 pin alternate function
0
TOAB1OFF input/INTP16 input
1
A13 output
PFC912
Note
Note
Specification of P912 pin alternate function
0
SCKF3 I/O
1
A12 output
Note
PFCE911
PFC911
Specification of P911 pin alternate function
0
0
SOF3 output
0
1
RXDC2 input
1
0
INTP15 input
1
1
Setting prohibited (V850ES/JG3-H)
A11 output (V850ES/JH3-H)
PFCE910
PFC910
Specification of P910 pin alternate function
0
0
SIF3 input
0
1
TXDC2 output
1
0
INTP14 input
1
1
Setting prohibited (V850ES/JG3-H)
A10 output (V850ES/JH3-H)
PFCE99
Note
PFC99
Specification of P99 pin alternate function
0
0
SCKF1 I/O
0
1
INTP13 input
1
0
A9 output
1
1
Setting prohibited
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Note
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PFCE98
Note
CHAPTER 4 PORT FUNCTIONS
PFC98
Specification of P98 pin alternate function
0
0
SOF1 output
0
1
INTP12 input
1
0
A8 output
1
1
Setting prohibited
PFCE97
PFC97
0
0
SIF1 input
0
1
TIAA20 input
1
0
TOAA20 output
1
1
Setting prohibited (V850ES/JG3-H)
Note
Note
Specification of P97 pin alternate function
A7 output (V850ES/JH3-H)
PFCE96
PFC96
0
0
Specification of P96 pin alternate function
TIAA21 input
0
1
TOAA21 output
1
0
INTP11 input
1
1
Setting prohibited (V850ES/JG3-H)
A6 output (V850ES/JH3-H)
PFCE95
Note
PFC95
Specification of P95 pin alternate function
0
0
TIAA30 input
0
1
TOAA30 output
1
0
A5 output
1
1
Setting prohibited
PFCE94
PFC94
0
0
TIAA31 input
0
1
TOAA31 output
1
0
TENC00 input/EVTT0 input
1
1
Setting prohibited (V850ES/JG3-H)
Note
Note
Specification of P94 pin alternate function
A4 output (V850ES/JH3-H)
PFCE93
PFC93
Specification of P93 pin alternate function
0
0
TECR0 input
0
1
TIT00 input
1
0
TOT00 output
1
1
Setting prohibited (V850ES/JG3-H)
A3 output (V850ES/JH3-H)
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PFCE92
PFC92
Specification of P92 pin alternate function
0
0
TENC01 input
0
1
TIT01 input
1
0
TOT01 output
1
1
Setting prohibited (V850ES/JG3-H)
A2 output (V850ES/JH3-H)
PFCE91
PFC91
Specification of P91 pin alternate function
0
0
KR7 input
0
1
RXDC1 input
1
0
SCL02 I/O
1
1
Setting prohibited (V850ES/JG3-H)
A1 output (V850ES/JH3-H)
PFCE90
PFC90
Specification of P90 pin alternate function
0
0
KR6 input
0
1
TXDC1 output
1
0
SDA02 I/O
1
1
Setting prohibited (V850ES/JG3-H)
A0 output (V850ES/JH3-H)
Note V850ES/JH3-H only
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(7) Port 9 function register (PF9)
After reset: 0000H
R/W
Address: PF9 FFFFFC72H,
PF9L FFFFFC72H
15
14
13
12
11
10
9
8
PF9
0
0
0
0
0
0
0
0
(PF9L)
0
0
0
0
0
0
PF91
PF90
PF9n
Caution
Control of normal output or N-ch open-drain output (n = 0, 1)
0
Normal output (CMOS output)
1
N-ch open-drain output
When output pins P90, P91 are pulled up to EVDD or higher, be sure to set the PF9n
bit to 1.
Remark
The PF9 register can be read or written in 16-bit units.
However, when using the higher 8 bits of the PF9 register as the PF9H register and the
lower 8 bits as the PF9L register, they can be read or written in 8-bit or 1-bit units.
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CHAPTER 4 PORT FUNCTIONS
4.3.10 Port CM
Port CM is 1-bit (V850ES/JG3-H)/4-bit (V850ES/JH3-H) port for which I/O settings can be controlled in 1-bit units.
Port CM includes the following alternate-function pins.
Table 4-15. Port CM Alternate-Function Pins
Pin Name
Pin No.
Alternate-Function Pin Name
V850ES/
V850ES/
JG3-H
JH3-H
I/O
Remark
−
PCM0
−
89
WAIT
Input
PCM1
64
86
CLKOUT
Output
PCM2
−
10
HLDAK
Output
PCM3
−
11
HLDRQ
Input
(1) Port CM register (PCM)
(a) V850ES/JG3-H
After reset: 00H (output latch)
R/W
PCM
0
0
0
PCM1
Address: FFFFF00CH
0
0
0
PCM1
0
Output data control (in output mode)
0
Outputs 0.
1
Outputs 1.
(b) V850ES/JH3-H
After reset: 00H (output latch)
R/W
PCM
0
0
0
PCMn
0
PCM3
PCM2
PCM1
PCM0
Output data control (in output mode) (n = 0 to 3)
0
Outputs 0.
1
Outputs 1.
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CHAPTER 4 PORT FUNCTIONS
(2) Port CM mode register (PMCM)
(a) V850ES/JG3-H
After reset: FFH
PMCM
1
R/W
Address: FFFFF02CH
1
1
1
PMCM1
1
1
PMCM1
1
PMCM2
PMCM1
PMCM0
I/O mode control
0
Output mode
1
Input mode
(b) V850ES/JH3-H
After reset: FFH
PMCM
1
R/W
Address: FFFFF02CH
1
PMCMn
1
PMCM3
I/O mode control (n = 0 to 3)
0
Output mode
1
Input mode
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CHAPTER 4 PORT FUNCTIONS
(3) Port CM mode control register (PMCCM)
(a) V850ES/JG3-H
After reset: 00H
PMCCM
0
R/W
Address: FFFFF04CH
0
0
PMCCM1
0
0
0
PMCCM1
0
Specification of PCM1 pin operation mode
0
I/O port
1
CLKOUT output
(b) V850ES/JH3-H
After reset: 00H
PMCCM
0
R/W
Address: FFFFF04CH
0
PMCCM3
0
PMCCM3 PMCCM2 PMCCM1 PMCCM0
Specification of PCM3 pin operation mode
0
I/O port
1
HLDRQ input
PMCCM2
Specification of PCM2 pin operation mode
0
I/O port
1
HLDAK output
PMCCM1
Specification of PCM1 pin operation mode
0
I/O port
1
CLKOUT output
PMCCM0
Specification of PCM0 pin operation mode
0
I/O port
1
WAIT input
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CHAPTER 4 PORT FUNCTIONS
4.3.11 Port CS (V850ES/JH3-H only)
Port CS is a 3-bit port for which I/O settings can be controlled in 1-bit units.
Port CS includes the following alternate-function pins.
Table 4-16. Port CM Alternate-Function Pins
Pin Name
Pin No.
Alternate-Function Pin Name
V850ES/
V850ES/
JG3-H
JH3-H
I/O
PCS0
−
96
CS0
Output
PCS2
−
97
CS2
Output
PCS3
−
116
CS3
Output
Remark
−
(1) Port CS register (PCS)
After reset: 00H (output latch)
R/W
PCS
0
0
0
PCSn
Address: FFFFF008H
0
PCS3
PCS2
0
PCS0
Output data control (in output mode) (n = 0, 2, 3)
0
Outputs 0.
1
Outputs 1.
(2) Port CS mode register (PMCS)
After reset: FFH
PMCS
1
R/W
Address: FFFFF028H
1
PMCSn
1
PMCS3
PMCS2
1
PMCS0
I/O mode control (n = 0, 2, 3)
0
Output mode
1
Input mode
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CHAPTER 4 PORT FUNCTIONS
(3) Port CS mode control register (PMCCS)
After reset: 00H
PMCCS
0
R/W
Address: FFFFF048H
0
PMCCS3
0
PMCCS3 PMCCS2
0
PMCCS0
Specification of PCS3 pin operation mode
0
I/O port
1
CS3 output
PMCCS2
Specification of PCS2 pin operation mode
0
I/O port
1
CS2 output
PMCCS0
Specification of PCS0 pin operation mode
0
I/O port
1
CS0 output
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CHAPTER 4 PORT FUNCTIONS
4.3.12 Port CT
Port CT is a 2-bit (V850ES/JG3-H)/4-bit (V850ES/JH3-H) port for which I/O settings can be controlled in 1-bit units.
Port CT includes the following alternate-function pins.
Table 4-17. Port CT Alternate-Function Pins
Pin Name
Pin No.
Alternate-Function Pin Name
V850ES/
V850ES/
JG3-H
JH3-H
I/O
PCT0
58
76
WR0
Output
PCT1
59
77
WR1
Output
PCT4
−
87
RD
Output
PCT6
−
88
ASTB
Output
Remark
−
(1) Port CT register (PCT)
(a) V850ES/JG3-H
After reset: 00H (output latch)
PCT
0
0
PCTn
R/W
0
Address: FFFFF00AH
0
0
0
PCT1
PCT0
Output data control (in output mode) (n = 0, 1)
0
Outputs 0.
1
Outputs 1.
(b) V850ES/JH3-H
After reset: 00H (output latch)
PCT
0
PCT6
PCMn
Address: FFFFF00AH
0
PCT4
0
0
PCT1
PCT0
Output data control (in output mode) (n = 0, 1, 4, 6)
0
Outputs 0.
1
Outputs 1.
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CHAPTER 4 PORT FUNCTIONS
(2) Port CT mode register (PMCT)
(a) V850ES/JG3-H
After reset: FFH
PMCT
1
R/W
Address: FFFFF02AH
1
1
PMCTn
1
1
1
PMCT1
PMCT0
PMCT1
PMCT0
I/O mode control (n = 0, 1)
0
Output mode
1
Input mode
(b) V850ES/JH3-H
After reset: FFH
PMCT
1
R/W
Address: FFFFF02AH
PMCT6
PMCTn
PMCT4
1
1
I/O mode control (n = 0, 1, 4, 6)
0
Output mode
1
Input mode
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CHAPTER 4 PORT FUNCTIONS
(3) Port CT mode control register (PMCCT)
(a) V850ES/JG3-H
After reset: 00H
PMCCT
0
R/W
Address: FFFFF04AH
0
0
PMCCT1
0
0
0
PMCCT1 PMCCT0
Specification of PCT1 pin operation mode
0
I/O port
1
WR1 output
PMCCT0
Specification of PCT0 pin operation mode
0
I/O port
1
WR0 output
(b) V850ES/JH3-H
After reset: 00H
PMCCT
0
R/W
Address: FFFFF04AH
PMCCT6
PMCCT6
PMCCT4
0
0
PMCCT1 PMCCT0
Specification of PCT6 pin operation mode
0
I/O port
1
ASTB output
PMCCT4
Specification of PCT4 pin operation mode
0
I/O port
1
RD output
PMCCT1
Specification of PCT1 pin operation mode
0
I/O port
1
WR1 output
PMCCT0
Specification of PCT0 pin operation mode
0
I/O port
1
WR0 output
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CHAPTER 4 PORT FUNCTIONS
4.3.13 Port DH (V850ES/JH3-H only)
Port DH is an 8-bit port for which I/O settings can be controlled in 1-bit units.
Port DH includes the following alternate-function pins.
Table 4-18. Port DH Alternate-Function Pins
Pin Name
Pin No.
V850ES/
V850ES/
JG3-H
JH3-H
Alternate-Function Pin Name
I/O
PDH0
−
72
A16
Output
PDH1
−
73
A17
Output
PDH2
−
74
A18
Output
PDH3
−
75
A19
Output
PDH4
−
78
A20
Output
PDH5
−
79
A21
Output
PDH6
−
80
A22
Output
PDH7
−
81
A23
Output
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Remark
−
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V850ES/JG3-H, V850ES/JH3-H
CHAPTER 4 PORT FUNCTIONS
(1) Port DH register (PDH)
After reset: 00H (output latch)
PDH
PDH7
R/W
PDH6
PDH5
PDHn
Address: FFFFF006H
PDH4
PDH3
PDH2
PDH1
PDH0
Output data control (in output mode) (n = 0 to 7)
0
Outputs 0.
1
Outputs 1.
(2) Port DH mode register (PMDH)
After reset: FFH
PMDH
PMDH7
R/W
Address: FFFFF026H
PMDH6
PMDH5
PMDHn
PMDH4
PMDH3
PMDH2
PMDH1
PMDH0
I/O mode control (n = 0, 7)
0
Output mode
1
Input mode
(3) Port DH mode control register (PMCDH)
After reset: 00H
PMCDH
R/W
Address: FFFFF046H
PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0
PMCDHn
Specification of PDHn pin operation mode (n = 0 to 7)
0
I/O port
1
Am output (Address bus) (m = 16 to 23)
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CHAPTER 4 PORT FUNCTIONS
4.3.14 Port DL
Port DL is a 16-bit port for which I/O settings can be controlled in 1-bit units.
Port DL includes the following alternate-function pins.
Table 4-19. Port DL Alternate-Function Pins
Pin Name
Pin No.
V850ES/
V850ES/
JG3-H
JH3-H
Alternate-Function Pin Name
I/O
PDL0
71
98
AD0
I/O
PDL1
72
99
AD1
I/O
PDL2
73
100
AD2
I/O
PDL3
74
101
AD3
I/O
PDL4
75
102
AD4
Remark
−
I/O
Note
PDL5
78
103
AD5/FLMD1
I/O
PDL6
79
104
AD6
I/O
PDL7
80
105
AD7
I/O
PDL8
81
108
AD8
I/O
PDL9
82
109
AD9
I/O
PDL10
83
110
AD10
I/O
PDL11
84
111
AD11
I/O
PDL12
85
112
AD12
I/O
PDL13
86
113
AD13
I/O
PDL14
87
114
AD14
I/O
PDL15
88
115
AD15
I/O
Note Since this pin is set in the flash memory programming mode, it does not need to be manipulated with the port
control register. For details, see CHAPTER 31 FLASH MEMORY.
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V850ES/JG3-H, V850ES/JH3-H
CHAPTER 4 PORT FUNCTIONS
(1) Port DL register (PDL)
After reset: 0000H (output latch)
R/W
Address: PDL FFFFF004H,
PDLL FFFFF004H, PDLH FFFFF005H
15
14
13
12
11
10
9
8
PDL (PDLH)
PDL15
PDL14
PDL13
PDL12
PDL11
PDL10
PDL9
PDL8
(PDLL)
PDL7
PDL6
PDL5
PDL4
PDL3
PDL2
PDL1
PDL0
PDLn
Output data control (in output mode) (n = 0 to 15)
0
Outputs 0.
1
Outputs 1.
Remarks 1. The PDL register can be read or written in 16-bit units.
However, when using the higher 8 bits of the PDL register as the PDLH register and
the lower 8 bits as the PDLL register, they can be read or written in 8-bit or 1-bit units.
2. To read/write bits 8 to 15 of the PDL register in 8-bit or 1-bit units, specify them as
bits 0 to 7 of the PDLH register.
(2) Port DL mode register (PMDL)
After reset: FFFFH
15
PMDL (PMDLH)
(PMDLL)
R/W
Address:
14
9
8
PMDL15 PMDL14 PMDL13 PMDL12 PMDL11 PMDL10
PMDL9
PMDL8
PMDL7
PMDL1
PMDL0
PMDL6
13
PMDL FFFFF024H,
PMDLL FFFFF024H, PMDLH FFFFF025H
PMDL5
PMDLn
12
PMDL4
11
PMDL3
10
PMDL2
I/O mode control (n = 0 to 15)
0
Output mode
1
Input mode
Remarks 1. The PMDL register can be read or written in 16-bit units.
However, when using the higher 8 bits of the PMDL register as the PMDLH register
and the lower 8 bits as the PMDLL register, they can be read or written in 8-bit or 1-bit
units.
2. To read/write bits 8 to 15 of the PMDL register in 8-bit or 1-bit units, specify them as
bits 0 to 7 of the PMDLH register.
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V850ES/JG3-H, V850ES/JH3-H
CHAPTER 4 PORT FUNCTIONS
(3) Port DL mode control register (PMCDL)
After reset: 0000H
15
R/W
14
Address: PMCDL FFFFF044H,
PMCDLL FFFFF044H, PMCDLH FFFFF045H
13
12
11
10
9
8
PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8
(PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0
PMCDLn
Specification of PDLn pin operation mode (n = 0 to 15)
0
I/O port
1
ADn I/O (address/data bus I/O)
Remarks 1. The PMCDL register can be read or written in 16-bit units.
However, when using the higher 8 bits of the PMCDL register as the PMCDLH
register and the lower 8 bits as the PMCDLL register, they can be read or written in
8-bit or 1-bit units.
2. To read/write bits 8 to 15 of the PMCDL register in 8-bit or 1-bit units, specify them
as bits 0 to 7 of the PMCDLH register.
4.4
Port Register Settings When Alternate Function Is Used
Table 4-20 shows the port register settings when each port is used for an alternate function. When using a port pin as
an alternate-function pin, refer to the description of each pin.
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Page 161 of 1513
Pin Name
Alternate Function
Name
I/O
Pnx Bit of
PMnx Bit of
PMCnx Bit of
PFCEnx Bit of
PFCnx Bit of
Other Bits
Pn Register
PMn Register
PMCn Register
PFCEn Register
PFCn Register
(Registers)
P00Note 1
INTP00
Input
P00 = Setting not required
PM00 = Setting not required PMC00 = 1
−
−
P01Note 1
INTP01
Input
P01 = Setting not required
PM01 = Setting not required PMC01 = 1
−
−
P02
NMI
Input
P02 = Setting not required
PM02 = Setting not required PMC02 = 1
−
P03
INTP02
Input
P03 = Setting not required
PM03 = Setting not required PMC03 = 1
PFCE03 = 0
PFC03 = 0
P04
−
ADTRG
Input
P03 = Setting not required
PM03 = Setting not required PMC03 = 1
PFCE03 = 0
PFC03 = 1
UCLK
Input
P03 = Setting not required
PM03 = Setting not required PMC03 = 1
PFCE03 = 1
PFC03 = 0
INTP03
Input
P04 = Setting not required
PM04 = Setting not required PMC04 = 1
−
−
−
−
−
−
P05
INTP04
Input
P05 = Setting not required
PM05 = Setting not required PMC05 = 1
P10
ANO0
Output
P10 = Setting not required
PM10 = 1
−
P11
ANO1
Output
P11 = Setting not required
PM11 = 1
−
P20Note 1
TIAB03
Input
P20 = Setting not required
PM20 = Setting not required PMC20 = 1
PFCE20 = 0
PFC20 = 0
KR2
Input
P20 = Setting not required
PM20 = Setting not required PMC20 = 1
PFCE20 = 0
PFC20 = 0
TOAB03
Output
P20 = Setting not required
PM20 = Setting not required PMC20 = 1
PFCE20 = 0
PFC20 = 1
RTP02
Output
P20 = Setting not required
PM20 = Setting not required PMC20 = 1
PFCE20 = 1
PFC20 = 0
SIF2
Input
P21 = Setting not required
PM21 = Setting not required PMC21= 1
PFCE21 = 0
PFC21 = 0
KR3Note 2
Input
P21 = Setting not required
PM21 = Setting not required PMC21= 1
PFCE21 = 0
PFC21 = 1
TIAB00
Input
P21 = Setting not required
PM21 = Setting not required PMC21= 1
PFCE21 = 0
PFC21 = 1
TOAB00
Output
P21 = Setting not required
PM21 = Setting not required PMC21= 1
PFCE21 = 1
PFC21 = 0
RTP03
Output
P21 = Setting not required
PM21 = Setting not required PMC21= 1
PFCE21 = 1
PFC21 = 1
Note 1
P21
Note 2
−
−
2. The KR3 pin and TIAB00 pin are alternate-function pins. When using this pin as the TIAB00 pin, do not use the alternate function KR3 pin. Similarly, when using
this pin as the KR3 pin, do not use the TIAB00 pin.
When the power is turned on, the P10 and P11 pins may output an undefined level temporarily even during reset.
Page 162 of 1513
CHAPTER 4 PORT FUNCTIONS
Notes 1. V850ES/JH3-H only
Caution
V850ES/JG3-H, V850ES/JH3-H
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Table 4-20. Using Port Pin as Alternate-Function Pin (1/10)
Pin Name
Alternate Function
Name
P22Note
P23Note
P24Note
I/O
Pnx Bit of
PMnx Bit of
PMCnx Bit of
PFCEnx Bit of
PFCnx Bit of
Other Bits
Pn Register
PMn Register
PMCn Register
PFCEn Register
PFCn Register
(Registers)
SOF2
Output
P22 = Setting not required
PM22 = Setting not required PMC22= 1
PFCE22 = 0
PFC22 = 0
KR4
Input
P22 = Setting not required
PM22 = Setting not required PMC22= 1
PFCE22 = 0
PFC22 = 1
RTP04
Output
P22 = Setting not required
PM22 = Setting not required PMC22= 1
PFCE22 = 1
PFC22 = 0
SCKF2
I/O
P23 = Setting not required
PM23 = Setting not required PMC23= 1
PFCE23 = 0
PFC23 = 0
KR5
Input
P23 = Setting not required
PM23 = Setting not required PMC23= 1
PFCE23 = 0
PFC23 = 1
RTP05
Output
P23 = Setting not required
PM23 = Setting not required PMC23= 1
PFCE23 = 1
PFC23 = 0
INTP05
Input
P24 = Setting not required
PM24 = Setting not required PMC24= 1
−
−
P25
INTP06
Input
P25 = Setting not required
PM25 = Setting not required PMC25= 1
−
P30
TXDC0
Output
P30 = Setting not required
PM30 = Setting not required PMC30 = 1
PFCE30 = 0
PFC30 = 0
Note
P31
P32
P33
−
Output
P30 = Setting not required
PM30 = Setting not required PMC30 = 1
PFCE30 = 0
PFC30 = 1
Input
P30 = Setting not required
PM30 = Setting not required PMC30 = 1
PFCE30 = 1
PFC30 = 0
RXDC0
Input
P31 = Setting not required
PM31 = Setting not required PMC31 = 1
PFCE31 = 0
PFC31 = 0
SIF4
Input
P31 = Setting not required
PM31 = Setting not required PMC31 = 1
PFCE31 = 0
PFC31 = 1
INTP08
Input
P31 = Setting not required
PM31 = Setting not required PMC31 = 1
PFCE31 = 1
PFC31 = 0
ASCKC0
Input
P32 = Setting not required
PM32 = Setting not required PMC32 = 1
PFCE32 = 0
PFC32 = 0
SCKF4
I/O
P32 = Setting not required
PM32 = Setting not required PMC32 = 1
PFCE32 = 0
PFC32 = 1
TIAA00
Input
P32 = Setting not required
PM32 = Setting not required PMC32 = 1
PFCE32 = 1
PFC32 = 0
TOAA00
Output
P32 = Setting not required
PM32 = Setting not required PMC32 = 1
PFCE32 = 1
PFC32 = 1
TIAA01
Input
P33 = Setting not required
PM33 = Setting not required PMC33 = 1
PFCE33 = 0
PFC33 = 0
TOAA01
Output
P33 = Setting not required
PM33 = Setting not required PMC33 = 1
PFCE33 = 0
PFC33 = 1
RTCDIV
Output
P33 = Setting not required
PM33 = Setting not required PMC33 = 1
PFCE33 = 1
PFC33 = 0
RTCCL
Output
P33 = Setting not required
PM33 = Setting not required PMC33 = 1
PFCE33 = 1
PFC33 = 1
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CHAPTER 4 PORT FUNCTIONS
SOF4
INTP07
Note V850ES/JH3-H only
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
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Table 4-20. Using Port Pin as Alternate-Function Pin (2/10)
Pin Name
Alternate Function
Name
P34
I/O
P40
P41
PFCnx Bit of
Other Bits
PFCn Register
(Registers)
Input
P34 = Setting not required
PM34 = Setting not required PMC34 = 1
PFCE34 = 0
PFC34 = 0
P34 = Setting not required
PM34 = Setting not required PMC34 = 1
PFCE34 = 0
PFC34 = 1
Input
P34 = Setting not required
PM34 = Setting not required PMC34 = 1
PFCE34 = 1
PFC34 = 0
Input
P34 = Setting not required
PM34 = Setting not required PMC34 = 1
PFCE34 = 1
PFC34 = 0
TIAA11
Input
P35 = Setting not required
PM35 = Setting not required PMC35 = 1
PFCE35 = 0
PFC35 = 0
TOAA11
Output
P35 = Setting not required
PM35 = Setting not required PMC35 = 1
PFCE35 = 0
PFC35 = 1
RTC1HZ
Output
P35 = Setting not required
PM35 = Setting not required PMC35 = 1
PFCE35 = 1
PFC35 = 0
TXDC3
Output
P36 = Setting not required
PM36 = Setting not required PMC36 = 1
PFCE36 = 0
PFC36 = 0
SCL00
I/O
P36 = Setting not required
PM36 = Setting not required PMC36 = 1
PFCE36 = 0
PFC36 = 1
Note 1
CTXD0
Output
P36 = Setting not required
PM36 = Setting not required PMC36 = 1
PFCE36 = 1
PFC36 = 0
UDMARQ0
Input
P36 = Setting not required
PM36 = Setting not required PMC36 = 1
PFCE36 = 1
PFC36 = 1
RXDC3
Input
P37 = Setting not required
PM37 = Setting not required PMC37 = 1
PFCE37 = 0
PFC37 = 0
SDA00
I/O
P37 = Setting not required
PM37 = Setting not required PMC37 = 1
PFCE37 = 0
PFC37 = 1
CRXD0Note 2
Input
P37 = Setting not required
PM37 = Setting not required PMC37 = 1
PFCE37 = 1
PFC37 = 0
UDMAAK0
Output
P37 = Setting not required
PM37 = Setting not required PMC37 = 1
PFCE37 = 1
PFC37 = 1
SIF0
Input
P40 = Setting not required
PM40 = Setting not required PMC40 = 1
PFCE40 = 0
PFC40 = 0
TXDC4
Output
P40 = Setting not required
PM40 = Setting not required PMC40 = 1
PFCE40 = 0
PFC40 = 1
SDA01
I/O
P40 = Setting not required
PM40 = Setting not required PMC40 = 1
PFCE40 = 1
PFC40 = 0
SOF0
Output
P41 = Setting not required
PM41 = Setting not required PMC41 = 1
PFCE41 = 0
PFC41 = 0
RXDC4
Input
P41 = Setting not required
PM41 = Setting not required PMC41 = 1
PFCE41 = 0
PFC41 = 1
SCL01
I/O
P41 = Setting not required
PM41 = Setting not required PMC41 = 1
PFCE41 = 1
PFC41 = 0
SCKF0
I/O
P42 = Setting not required
PM42 = Setting not required PMC42 = 1
−
PFC42 = 0
INTP10
Input
P42 = Setting not required
PM42 = Setting not required PMC42 = 1
−
PFC42 = 1
PF36 (PF3) = 1
PF37 (PF3) = 1
PF40 (PF4) = 0
PF41 (PF4) = 0
Notes 1. The TOAA1OFF pin and INTP09 pin are alternate-function pins. When using this pin as the TOAA1OFF pin, disable edge detection of the INTP09 pin, which is the
alternate function (set to INTF3.INTF34 = 0, INTR3.INTR34 = 0). Similarly, when using this pin as the INTP09 pin, be sure to stop the high impedance output
circuit.
Page 164 of 1513
2. μPD70F3770, 70F3771 only
CHAPTER 4 PORT FUNCTIONS
P42
PFCEnx Bit of
PFCEn Register
Output
Note 2
P37
PMCnx Bit of
PMCn Register
TOAA10
TOAA1OFF
P36
PMnx Bit of
PMn Register
TIAA10
INTP09Note 1
P35
Pnx Bit of
Pn Register
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Table 4-20. Using Port Pin as Alternate-Function Pin (3/10)
Pin Name
Alternate Function
Name
P50
P51
P52Note
Note
P53
I/O
Pnx Bit of
PMnx Bit of
PMCnx Bit of
PFCEnx Bit of
PFCnx Bit of
Other Bits
Pn Register
PMn Register
PMCn Register
PFCEn Register
PFCn Register
(Registers)
TIAB01
Input
P50 = Setting not required
PM50 = Setting not required PMC50 = 1
PFCE50 = 0
PFC50 = 0
KRM0 (KRM)= 0
KR0
Input
P50 = Setting not required
PM50 = Setting not required PMC50 = 1
PFCE50 = 0
PFC50 = 0
TAB0TIG2, TAB0TIG3 (TAB0IOC1) = 0
TOAB01
Output
P50 = Setting not required
PM50 = Setting not required PMC50 = 1
PFCE50 = 0
PFC50 = 1
RTP00
Output
P50 = Setting not required
PM50 = Setting not required PMC50 = 1
PFCE50 = 1
PFC50 = 0
UDMARQ1
Input
P50 = Setting not required
PM50 = Setting not required PMC50 = 1
PFCE50 = 1
PFC50 = 1
TIAB02
Input
P51 = Setting not required
PM51 = Setting not required PMC51 = 1
PFCE51 = 0
PFC51 = 0
KRM1 (KRM) = 0
KR1
Input
P51 = Setting not required
PM51 = Setting not required PMC51 = 1
PFCE51 = 0
PFC51 = 0
TAB0TIG4, TAB0TIG5 (TAB0IOC1) = 0
TOAB02
Output
P51 = Setting not required
PM51 = Setting not required PMC51 = 1
PFCE51 = 0
PFC51 = 1
RTP01
Output
P51 = Setting not required
PM51 = Setting not required PMC51 = 1
PFCE51 = 1
PFC51 = 0
UDMAAK1
Output
P51 = Setting not required
PM51 = Setting not required PMC51 = 1
PFCE51 = 1
PFC51 = 1
TIAB03
Input
P52 = Setting not required
PM52 = Setting not required PMC52 = 1
PFCE52 = 0
PFC52 = 0
KRM2 (KRM) = 0
KR2
Input
P52 = Setting not required
PM52 = Setting not required PMC52 = 1
PFCE52 = 0
PFC52 = 0
TAB0TIG6, TAB0TIG7 (TAB0I0C1) = 0
TOAB03
Output
P52 = Setting not required
PM52 = Setting not required PMC52 = 1
PFCE52 = 0
PFC52 = 1
RTP02
Output
P52 = Setting not required
PM52 = Setting not required PMC52 = 1
PFCE52 = 1
PFC52 = 0
SIF2
Input
P53 = Setting not required
PM53 = Setting not required PMC53 = 1
PFCE53 = 0
PFC53 = 0
TIAB00
Input
P53 = Setting not required
PM53 = Setting not required PMC53 = 1
PFCE53 = 0
PFC53 = 1
KR3
Input
P53 = Setting not required
PM53 = Setting not required PMC53 = 1
PFCE53 = 0
PFC53 = 1
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Table 4-20. Using Port Pin as Alternate-Function Pin (4/10)
KRM3 (KRM) = 0
TAB0TIG0, TAB0TIG1 (TAB0IOC1) = 0,
TAB0EES0, TAB0EES1 (TAB0IOC2) = 0,
TAB0ETS0, TAB0ETS1 (TAB0IOC2) = 0
P54
Output
P53 = Setting not required
PM53 = Setting not required PMC53 = 1
PFCE53 = 1
PFC53 = 0
RTP03
Output
P53 = Setting not required
PM53 = Setting not required PMC53 = 1
PFCE53 = 1
PFC53 = 1
SOF2
Output
P54 = Setting not required
PM54 = Setting not required PMC54 = 1
PFCE54 = 0
PFC54 = 0
KR4
Input
P54 = Setting not required
PM54 = Setting not required PMC54 = 1
PFCE54 = 0
PFC54 = 1
RTP04
Output
P54 = Setting not required
PM54 = Setting not required PMC54 = 1
PFCE54 = 1
PFC54 = 0
Note V850ES/JG3-H only
Page 165 of 1513
CHAPTER 4 PORT FUNCTIONS
Note
TOAB00
Pin Name
Alternate Function
Name
P55Note
P60
P61
P62
P64
PMnx Bit of
PMCnx Bit of
PFCEnx Bit of
PFCnx Bit of
Other Bits
PMn Register
PMCn Register
PFCEn Register
PFCn Register
(Registers)
I/O
P55 = Setting not required
PM55 = Setting not required PMC55 = 1
PFCE55 = 0
PFC55 = 0
KR5
Input
P55 = Setting not required
PM55 = Setting not required PMC55 = 1
PFCE55 = 0
PFC55 = 1
RTP05
Output
P55 = Setting not required
PM55 = Setting not required PMC55 = 1
PFCE55 = 1
PFC55 = 0
TOAB1T1
Output
P60 = Setting not required
PM60 = Setting not required PMC60 = 1
PFCE60 = 0Note
PFC60 = 0
TOAB11
Output
P60 = Setting not required
PM60 = Setting not required PMC60 = 1
PFCE60 = 0Note
PFC60 = 0
TIAB11
Input
P60 = Setting not required
PM60 = Setting not required PMC60 = 1
PFCE60 = 0Note
PFC60 = 1
WAITNote
Output
P60 = Setting not required
PM60 = Setting not required PMC60 = 1
PFCE60 = 1Note
PFC60 = 0
TOAB1B1
Output
P61 = Setting not required
PM61 = Setting not required PMC61 = 1
PFCE61 = 0
PFC61 = 0
TIAB10
Input
P61 = Setting not required
PM61 = Setting not required PMC61 = 1
PFCE61 = 0
PFC61 = 1
TOAB10
Output
P61 = Setting not required
PM61 = Setting not required PMC61 = 1
PFCE61 = 1
PFC61 = 0
RDNote
Output
P61 = Setting not required
PM61 = Setting not required PMC61 = 1
PFCE61 = 1
PFC61 = 1
Note
TOAB1T2
Output
P62 = Setting not required
PM62 = Setting not required PMC62 = 1
PFCE62 = 0
PFC62 = 0
TOAB12
Output
P62 = Setting not required
PM62 = Setting not required PMC62 = 1
PFCE62 = 0Note
PFC62 = 0
TIAB12
Input
P62 = Setting not required
PM62 = Setting not required PMC62 = 1
PFCE62 = 0Note
PFC62 = 1
Note
ASTB
Output
P62 = Setting not required
PM62 = Setting not required PMC62 = 1
PFCE62 = 1
PFC62 = 0
TOAB1B2
Output
P63 = Setting not required
PM63 = Setting not required PMC63 = 1
PFCE63 = 0Note
PFC63 = 0
Note
TRGAB1
Input
P63 = Setting not required
PM63 = Setting not required PMC63 = 1
PFCE63 = 0
PFC63 = 1
CS0Note
Output
P63 = Setting not required
PM63 = Setting not required PMC63 = 1
PFCE63 = 1Note
PFC63 = 0
Note
Output
P64 = Setting not required
PM64 = Setting not required PMC64 = 1
PFCE64 = 0
PFC64 = 0
TOAB13
Output
P64 = Setting not required
PM64 = Setting not required PMC64 = 1
PFCE64 = 0Note
PFC64 = 0
TIAB13
Input
P64 = Setting not required
PM64 = Setting not required PMC64 = 1
PFCE64 = 0Note
PFC64 = 1
Note
CS2
Output
P64 = Setting not required
PM64 = Setting not required PMC64 = 1
PFCE64 = 1
PFC64 = 0
TOAB1B3
Output
P65 = Setting not required
PM65 = Setting not required PMC65 = 1
PFCE65 = 0Note
PFC63 = 0
Note
EVTAB1
Input
P65 = Setting not required
PM65 = Setting not required PMC65 = 1
PFCE65 = 0
PFC65 = 1
CS3Note
Output
P65 = Setting not required
PM65 = Setting not required PMC65 = 1
PFCE65 = 1Note
PFC65 = 0
Note V850ES/JG3-H only
Page 166 of 1513
CHAPTER 4 PORT FUNCTIONS
TOAB1T3
Note
P65
Pnx Bit of
Pn Register
SCKF2
Note
P63
I/O
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Table 4-20. Using Port Pin as Alternate-Function Pin (5/10)
Pin Name
Alternate Function
Name
I/O
Pnx Bit of
PMnx Bit of
PMCnx Bit of
PFCEnx Bit of
PFCnx Bit of
Other Bits
Pn Register
PMn Register
PMCn Register
PFCEn Register
PFCn Register
(Registers)
P70
ANI0
Input
P70 = Setting not required
PM70 = 1
−
−
−
P71
ANI1
Input
P71 = Setting not required
PM71 = 1
−
−
−
P72
ANI2
Input
P72 = Setting not required
PM72 = 1
−
−
−
P73
ANI3
Input
P73 = Setting not required
PM73 = 1
−
−
−
P74
ANI4
Input
P74 = Setting not required
PM74 = 1
−
−
−
P75
ANI5
Input
P75 = Setting not required
PM75 = 1
−
−
−
P76
ANI6
Input
P76 = Setting not required
PM76 = 1
−
−
−
P77
ANI7
Input
P77 = Setting not required
PM77 = 1
−
−
−
P78
ANI8
Input
P78 = Setting not required
PM78 = 1
−
−
−
P79
ANI9
Input
P79 = Setting not required
PM79 = 1
−
−
−
P710
ANI10
Input
P710 = Setting not required
PM710 = 1
−
−
−
−
−
−
P711
ANI11
Input
P711 = Setting not required
PM711 = 1
P90
KR6
Input
P90 = Setting not required
PM90 = Setting not required PMC90 = 1
PFCE90 = 0
PFC90 = 0
TXDC1
Output
P90 = Setting not required
PM90 = Setting not required PMC90 = 1
PFCE90 = 0
PFC90 = 1
P91
SDA02
I/O
P90 = Setting not required
PM90 = Setting not required PMC90 = 1
PFCE90 = 1
PFC90 = 0
PF90 (PF9) = 1
A0Note 1
Output
P90 = Setting not required
PM90 = Setting not required PMC90 = 1
PFCE90 = 1
PFC90 = 1
Note 2
KR7
Input
P91 = Setting not required
PM91 = Setting not required PMC91 = 1
PFCE91 = 0
PFC91 = 0
RXDC1
Input
P91 = Setting not required
PM91 = Setting not required PMC91 = 1
PFCE91 = 0
PFC91 = 1
SCL02
I/O
P91 = Setting not required
PM91 = Setting not required PMC91 = 1
PFCE91 = 1
PFC91 = 0
PF91 (PF9) = 1
A1Note 1
Output
P91 = Setting not required
PM91 = Setting not required PMC91 = 1
PFCE91 = 1
PFC91 = 1
Note 2
TENC01
Input
P92 = Setting not required
PM92 = Setting not required PMC92 = 1
PFCE92 = 0
PFC92 = 0
TIT01
Input
P92 = Setting not required
PM92 = Setting not required PMC92 = 1
PFCE92 = 0
PFC92 = 1
TOT01
Output
P92 = Setting not required
PM92 = Setting not required PMC92 = 1
PFCE92 = 1
PFC92 = 0
Output
P92 = Setting not required
PM92 = Setting not required PMC92 = 1
PFCE92 = 1
PFC92 = 1
Note 1
A2
Notes 1. V850ES/JH3-H only
2. When using as the A0 to A15 pins, be sure to set all 16 bits of the PMC9 register to FFFFH at once.
Note 2
Page 167 of 1513
CHAPTER 4 PORT FUNCTIONS
P92
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Table 4-20. Using Port Pin as Alternate-Function Pin (6/10)
Pin Name
Alternate Function
Name
P93
P94
P95
P96
P97
Pnx Bit of
PMnx Bit of
PMCnx Bit of
PFCEnx Bit of
PFCnx Bit of
Other Bits
Pn Register
PMn Register
PMCn Register
PFCEn Register
PFCn Register
(Registers)
TECR0
Input
P93 = Setting not required
PM93 = Setting not required PMC93 = 1
PFCE93 = 0
PFC93 = 0
TIT00
Input
P93 = Setting not required
PM93 = Setting not required PMC93 = 1
PFCE93 = 0
PFC93 = 1
TOT00
Output
P93 = Setting not required
PM93 = Setting not required PMC93 = 1
PFCE93 = 1
PFC93 = 0
A3Note 1
Output
P93 = Setting not required
PM93 = Setting not required PMC93 = 1
PFCE93 = 1
PFC93 = 1
TIAA31
Input
P94 = Setting not required
PM94 = Setting not required PMC94 = 1
PFCE94 = 0
PFC94 = 0
TOAA31
Output
P94 = Setting not required
PM94 = Setting not required PMC94 = 1
PFCE94 = 0
PFC94 = 1
TENC00
Input
P94 = Setting not required
PM94 = Setting not required PMC94 = 1
PFCE94 = 1
PFC94 = 0
EVTT0
Input
P94 = Setting not required
PM94 = Setting not required PMC94 = 1
PFCE94 = 1
PFC94 = 0
A4Note 1
Output
P94 = Setting not required
PM94 = Setting not required PMC94 = 1
PFCE94 = 1
PFC94 = 1
TIAA30
Input
P95 = Setting not required
PM95 = Setting not required PMC95 = 1
PFCE95 = 0
PFC95 = 0
TOAA30
Output
P95 = Setting not required
PM95 = Setting not required PMC95 = 1
PFCE95 = 0
PFC95 = 1
Note 1
A5
Output
P95 = Setting not required
PM95 = Setting not required PMC95 = 1
PFCE95 = 1
PFC95 = 0
TIAA21
Input
P96 = Setting not required
PM96 = Setting not required PMC96 = 1
PFCE96 = 0
PFC96 = 0
TOAA21
Output
P96 = Setting not required
PM96 = Setting not required PMC96 = 1
PFCE96 = 1
PFC96 = 1
INTP11
Input
P96 = Setting not required
PM96 = Setting not required PMC96 = 1
PFCE96 = 1
PFC96 = 0
A6Note 1
Output
P96 = Setting not required
PM96 = Setting not required PMC96 = 1
PFCE96 = 1
PFC96 = 1
SIF1
Input
P97 = Setting not required
PM97 = Setting not required PMC97 = 1
PFCE97 = 0
PFC97 = 0
TIAA20
Input
P97 = Setting not required
PM97 = Setting not required PMC97 = 1
PFCE97 = 0
PFC97 = 1
TOAA20
Output
P97 = Setting not required
PM97 = Setting not required PMC97 = 1
PFCE97 = 1
PFC97 = 0
A7Note 1
Output
P97 = Setting not required
PM97 = Setting not required PMC97 = 1
PFCE97 = 1
PFC97 = 1
SOF1
Output
P98 = Setting not required
PM98 = Setting not required PMC98 = 1
PFCE98 = 0
PFC98 = 0
INTP12
Input
P98 = Setting not required
PM98 = Setting not required PMC98 = 1
PFCE98 = 0
PFC98 = 1
A8Note 1
Output
P98 = Setting not required
PM98 = Setting not required PMC98 = 1
PFCE98 = 1
PFC98 = 0
Notes 1. V850ES/JH3-H only
2. When using as the A0 to A15 pins, be sure to set all 16 bits of the PMC9 register to FFFFH at once.
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Page 168 of 1513
CHAPTER 4 PORT FUNCTIONS
P98
I/O
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Table 4-20. Using Port Pin as Alternate-Function Pin (7/10)
Pin Name
Alternate Function
Name
P99
P911
P912
P913
P914
PMnx Bit of
PMCnx Bit of
PFCEnx Bit of
PFCnx Bit of
Other Bits
PMn Register
PMCn Register
PFCEn Register
PFCn Register
(Registers)
I/O
P99 = Setting not required
PM99 = Setting not required PMC99 = 1
PFCE99 = 0
PFC99 = 0
INTP13
Input
P99 = Setting not required
PM99 = Setting not required PMC99 = 1
PFCE99 = 0
PFC99 = 1
A9
Output
P99 = Setting not required
PM99 = Setting not required PMC99 = 1
PFCE99 = 1
PFC99 = 0
SIF3
Input
P910 = Setting not required
PM910 = Setting not required PMC910 = 1
PFCE910 = 0
PFC910 = 0
TXDC2
Output
P910 = Setting not required
PM910 = Setting not required PMC910 = 1
PFCE910 = 0
PFC910 = 1
INTP14
Input
P910 = Setting not required
PM910 = Setting not required PMC910 = 1
PFCE910 = 1
PFC910 = 0
A10Note 1
Output
P910 = Setting not required
PM910 = Setting not required PMC910 = 1
PFCE910 = 1
PFC910 = 1
SOF3
Output
P911 = Setting not required
PM911 = Setting not required
PMC911 = 1
PFCE911 = 0
PFC911 = 0
RXDC2
Input
P911 = Setting not required
PM911 = Setting not required
PMC911 = 1
PFCE911 = 0
PFC911 = 1
INTP15
Input
P911 = Setting not required
PM911 = Setting not required
PMC911 = 1
PFCE911 = 1
PFC911 = 0
A11Note 1
Output
P911 = Setting not required
PM911 = Setting not required
PMC911 = 1
PFCE911 = 1
PFC911 = 1
SCKF3
I/O
P912 = Setting not required
PM912 = Setting not required PMC912 = 1
−
PFC912 = 0
A12Note 1
Output
P912 = Setting not required
PM912 = Setting not required PMC912 = 1
−
PFC912 = 1
TOAB1OFF Input
P913 = Setting not required
PM913 = Setting not required PMC913 = 1
−
PFC913 = 0
INTP16
Input
P913 = Setting not required
PM913 = Setting not required PMC913 = 1
−
PFC913 = 0
A13Note 1
Output
P913 = Setting not required
PM913 = Setting not required PMC913 = 1
−
PFC913 = 1
TIAA51
Input
P914 = Setting not required
PM914 = Setting not required PMC914 = 1
PFCE914 = 0
PFC914 = 0
TOAA51
Output
P914 = Setting not required
PM914 = Setting not required PMC914 = 1
PFCE914 = 0
PFC914 = 1
INTP17
Input
P914 = Setting not required
PM914 = Setting not required PMC914 = 1
PFCE914 = 1
PFC914 = 0
A14Note 1
Output
P914 = Setting not required
PM914 = Setting not required PMC914 = 1
PFCE914 = 1
PFC914 = 1
TIAA50
Input
P915 = Setting not required
PM915 = Setting not required PMC915 = 1
PFCE915 = 0
PFC915 = 0
TOP50
Output
P915 = Setting not required
PM915 = Setting not required PMC915 = 1
PFCE915 = 0
PFC915 = 1
INTP18
Input
P915 = Setting not required
PM915 = Setting not required PMC915 = 1
PFCE915 = 1
PFC915 = 0
Output
P915 = Setting not required
PM915 = Setting not required PMC915 = 1
PFCE915 = 1
PFC915 = 1
Note 1
A15
Notes 1. V850ES/JH3-H only
2. When using as the A0 to A15 pins, be sure to set all 16 bits of the PMC9 register to FFFFH at once.
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Page 169 of 1513
CHAPTER 4 PORT FUNCTIONS
P915
Pnx Bit of
Pn Register
SCKF1
Note 1
P910
I/O
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Table 4-20. Using Port Pin as Alternate-Function Pin (8/10)
Pin Name
Alternate Function
Name
I/O
PCM0
WAITNote
Input
PCM1
CLKOUT
Output
Pnx Bit of
PMnx Bit of
PMCnx Bit of
PFCEnx Bit of
PFCnx Bit of
Other Bits
Pn Register
PMn Register
PMCn Register
PFCEn Register
PFCn Register
(Registers)
PCM0 = Setting not required PMCM0 = Setting not required PMCCM0 = 1
−
−
PCM1 = Setting not required PMCM1 = Setting not required PMCCM1 = 1
−
−
HLDAK
Output
PCM2 = Setting not required PMCM2 = Setting not required PMCCM2 = 1
−
−
PCM3
HLDRQNote
Input
PCM3 = Setting not required PMCM3 = Setting not required PMCCM3 = 1
−
−
PCS0
CS0Note
Output
PCS0 = Setting not required PMCS0 = Setting not required PMCCS0 = 1
−
−
PCS2
CS2Note
Output
PCS2 = Setting not required PMCS2 = Setting not required PMCCS2 = 1
−
−
PCS3
CS3Note
Output
PCS3 = Setting not required PMCS3 = Setting not required PMCCS3 = 1
−
−
PCT0
WR0
Output
PCT0 = Setting not required PMCT0 = Setting not required PMCCT0 = 1
−
−
PCT1
WR1
Output
PCT1 = Setting not required PMCT1 = Setting not required PMCCT1 = 1
−
−
PCT4
Note
RD
Output
PCT4 = Setting not required PMCT4 = Setting not required PMCCT4 = 1
−
−
PCT6
ASTBNote
Output
PCT6 = Setting not required PMCT6 = Setting not required PMCCT6 = 1
−
−
PDH0
A16
Output
PDH0 = Setting not required PMDH0 = Setting not required PMCDH0 = 1
−
−
PDH1
A17
Output
PDH1 = Setting not required PMDH1 = Setting not required PMCDH1 = 1
−
−
PDH2
A18
Output
PDH2 = Setting not required PMDH2 = Setting not required PMCDH2 = 1
−
−
PDH3
A19
Output
PDH3 = Setting not required PMDH3 = Setting not required PMCDH3 = 1
−
−
PDH4
A20
Output
PDH4 = Setting not required PMDH4 = Setting not required PMCDH4 = 1
−
−
PDH5
A21
Output
PDH5 = Setting not required PMDH5 = Setting not required PMCDH5 = 1
−
−
PDL0
AD0
I/O
PDL0 = Setting not required PMDL0 = Setting not required PMCDL0 = 1
−
−
PDL1
AD1
I/O
PDL1 = Setting not required PMDL1 = Setting not required PMCDL1 = 1
−
−
PDL2
AD2
I/O
PDL2 = Setting not required PMDL2 = Setting not required PMCDL2 = 1
−
−
PDL3
AD3
I/O
PDL3 = Setting not required PMDL3 = Setting not required PMCDL3 = 1
−
−
PDL4
AD4
I/O
PDL4 = Setting not required PMDL4 = Setting not required PMCDL4 = 1
−
−
Note V850ES/JH3-H only
Page 170 of 1513
CHAPTER 4 PORT FUNCTIONS
PCM2
Note
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Table 4-20. Using Port Pin as Alternate-Function Pin (9/10)
Pin Name
Alternate Function
Name
I/O
Pnx Bit of
PMnx Bit of
PMCnx Bit of
PFCEnx Bit of
PFCnx Bit of
Other Bits
Pn Register
PMn Register
PMCn Register
PFCEn Register
PFCn Register
(Registers)
AD5
I/O
PDL5 = Setting not required
PMDL5 = Setting not required
PMCDL5 = 1
−
−
FLMD1Note
Input
PDL5 = Setting not required
PMDL5 = Setting not required
PMCDL5 = Setting not required
−
−
PDL6
AD6
I/O
PDL6 = Setting not required
PMDL6 = Setting not required
PMCDL6 = 1
−
−
PDL7
AD7
I/O
PDL7 = Setting not required
PMDL7 = Setting not required
PMCDL7 = 1
−
−
PDL8
AD8
I/O
PDL8 = Setting not required
PMDL8 = Setting not required
PMCDL8 = 1
−
−
PDL9
AD9
I/O
PDL9 = Setting not required
PMDL9 = Setting not required
PMCDL9 = 1
−
−
PDL10
AD10
I/O
PDL10 = Setting not required PMDL10 = Setting not required PMCDL10 = 1
−
−
PDL5
PDL11
AD11
I/O
PDL11 = Setting not required PMDL11 = Setting not required PMCDL11 = 1
−
−
PDL12
AD12
I/O
PDL12 = Setting not required PMDL12 = Setting not required PMCDL12 = 1
−
−
PDL13
AD13
I/O
PDL13 = Setting not required PMDL13 = Setting not required PMCDL13 = 1
−
−
PDL14
AD14
I/O
PDL14 = Setting not required PMDL14 = Setting not required PMCDL14 = 1
−
−
PDL15
AD15
I/O
PDL15 = Setting not required PMDL15 = Setting not required PMCDL15 = 1
−
−
Note Since this pin is set in the flash memory programming mode, it does not need to be manipulated using the port control register.
V850ES/JG3-H, V850ES/JH3-H
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Table 4-20. Using Port Pin as Alternate-Function Pin (10/10)
For details, see CHAPTER 31
FLASH MEMORY.
CHAPTER 4 PORT FUNCTIONS
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4.5
4.5.1
CHAPTER 4 PORT FUNCTIONS
Cautions
Cautions on setting port pins
(1) In the V850ES/JG3-H and V850ES/JH3-H, the general-purpose port functions share pins with several peripheral
function I/O pins. Switch between the general-purpose port (port mode) and the peripheral function I/O pin
(alternate-function mode) by setting the PMCn register. Note the following cautions with regards to this register
setting sequence.
(a) Cautions on switching from port mode to alternate-function mode
Switch from the port mode to alternate-function mode in the following order.
Set the PFn registerNote 1:
N-ch open-drain setting
Set the PFCn and PFCEn registers:
Alternate-function selection
Set the corresponding bit of the PMCn register to 1: Switch to alternate-function mode
Set the INTRn and INTFn registersNote 2:
External interrupt setting
If the PMCn register is set first, note that unexpected operations may occur at that moment or depending on
the change of the pin states in accordance with the setting of the PFn, PFCn, and PFCEn registers.
A concrete example is shown in [Example] below.
Notes 1. N-ch open-drain output pin only
2. Only when the external interrupt function is selected
Caution
Regardless of the port mode/alternate-function mode, the Pn register is read and written as
follows.
• Pn register read: Read the port output latch value (when PMn.PMnm bit = 0), or read the
pin states (PMn.PMnm bit = 1).
• Pn register write: Write to the port output latch
[Example] SCL01 pin setting example
The SCL01 pin is used alternately as the P41/SOF0 pin. Select the valid pin function using the
PMC4, PFC4, and PF4 registers.
PMC41 Bit
PFC41 Bit
PF41 Bit
Valid Pin Function
0
don’t care
1
P41 (in output port mode, N-ch open-drain output)
1
0
1
SOF0 output (N-ch open-drain output)
1
1
SCL01 I/O (N-ch open-drain output)
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CHAPTER 4 PORT FUNCTIONS
The setting procedure that may cause malfunction on switching from the P41 pin to the SCL01 pin
is shown below.
Setting Procedure
Setting Contents
Initial value
Pin State
Pin Level
Port mode (input)
Hi-Z
SOF0 output
Low level (high level depending on the
(PMC41 bit = 0,
PFC41 bit = 0,
PF41 bit = 0)
PMC41 bit ← 1
CSIF0 setting)
PFC41 bit ← 1
SCL01 I/O
High level (CMOS output)
PF41 bit ← 1
SCL01 I/O
Hi-Z (N-ch open-drain output)
In , I2C communication may be affected since the alternate-function SOF0 output is output to the
pin. In the CMOS output period of or , unnecessary current may be generated.
(b) Cautions on alternate-function mode (input)
The signal input to the alternate-function block is low level when the PMCn.PMCnm bit is 0 due to the AND
output of the PMCn register set value and the pin level. Thus, depending on the port setting and alternatefunction operation enable timing, unexpected operations may occur. Therefore, switch between the port mode
and alternate-function mode in the following sequence.
• To switch from port mode to alternate-function mode (input)
Set the pins to the alternate-function mode using the PMCn register and then enable the alternate-function
operation.
• To switch from alternate-function mode (input) to port mode
Stop the alternate-function operation and then switch the pins to the port mode.
Concrete examples are shown in [Example 1] and [Example 2].
[Example 1] Switching from general-purpose port (P02) to external interrupt pin (NMI)
When the P02/NMI pin is pulled up as shown in Figure 4-4 and the rising edge is specified by the
NMI pin edge detection setting, even though a high level is input continuously to the NMI pin
when switching from the P02 pin to the an NMI pin (PMC02 bit = 0 → 1), this is detected as a
rising edge as if a low level changed to a high level, and an NMI interrupt occurs.
To avoid this, set the NMI pin’s valid edge after switching from the P02 pin to the NMI pin.
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CHAPTER 4 PORT FUNCTIONS
Figure 4-4. Example of Switching from P02 to NMI (Incorrect)
7
6
5
4
3
2
1
0
0→1
PMC0
3V
PMC0m bit = 0: Port mode
PMC0m bit = 1: Alternate-function mode
NMI interrupt occurrence
Rising
edge
detector
P02/NMI
PMC02 bit = 0: Low level
↓
PMC02 bit = 1: High level
Remark
m = 2 to 6
[Example 2] Switching from external pin (NMI) to general-purpose port (P02)
When the P02/NMI pin is pulled up as shown in Figure 4-5 and the falling edge is specified by
the NMI pin edge detection setting, even though a high level is input continuously to the NMI pin
when switching from the NMI pin to the P02 pin (PMC02 bit = 1 → 0), this is detected as a falling
edge as if a high level changed to a low level, and an NMI interrupt occurs.
To avoid this, set the NMI pin edge detection as “No edge detected” before switching to the P02
pin.
Figure 4-5. Example of Switching from NMI to P02 (Incorrect)
7
6
5
4
3
2
1
0
1→0
PMC0
3V
PMC0m bit = 0: Port mode
PMC0m bit = 1: Alternate-function mode
NMI interrupt occurrence Falling
edge
detector
P02/NMI
PMC02 bit = 1: High level
↓
PMC02 bit = 0: Low level
Remark
m = 2 to 6
(2) In port mode, the PFn.PFnm bit is valid only in the output mode (PMn.PMnm bit = 0). In the input mode (PMnm bit
= 1), the value of the PFnm bit is not reflected in the buffer.
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4.5.2
CHAPTER 4 PORT FUNCTIONS
Cautions on bit manipulation instruction for port n register (Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of
the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
When the P90 pin is an output port, the P91 to P97 pins are input ports (all pin statuses are high level),
and the value of the port latch is 00H, if the output of the P90 pin is changed from low level to high level
via a bit manipulation instruction, the value of the port latch is FFH.
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are
the output latch and pin status, respectively.
A bit manipulation instruction is executed in the following order in the V850ES/JG3-H and V850ES/JH3H.
The Pn register is read in 8-bit units.
The targeted bit is manipulated.
The Pn register is written in 8-bit units.
In step , the value of the output latch (0) of the P90 pin, which is an output port, is read, while the pin
statuses of the P91 to P97 pins, which are input ports, are read. If the pin statuses of the P91 to P97
pins are high level at this time, the read value is FEH.
The value is changed to FFH by the manipulation in .
FFH is written to the output latch by the manipulation in .
Figure 4-6. Bit Manipulation Instruction (P90 Pin)
Bit manipulation
instruction
(set1 0, P9L[r0])
is executed for
P90 bit.
P90
Low-level output
P91 to P97
P90
High-level output
P91 to P97
Pin status: High level
Pin status: High level
Port 9L latch
0
0
Port 9L latch
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit manipulation instruction for P90 bit
P9L register is read in 8-bit units.
• In the case of P90, an output port, the value of the port latch (0) is read.
• In the case of P91 to P97, input ports, the pin status (1) is read.
Set (1) P90 bit.
Write the results of to the output latch of P9L register in 8-bit units.
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4.5.3
CHAPTER 4 PORT FUNCTIONS
Cautions on on-chip debug pins (V850ES/JG3-H only)
The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins.
After reset by the RESET pin, the P56/INTP05/DRST pin is initialized to function as an on-chip debug pin (DRST). If a
high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can
be used.
The following action must be taken if on-chip debugging is not used.
• Clear the OCDM0 bit of the OCDM register (special register) (0)
At this time, fix the P56/INTP05/DRST pin to low level from when reset by the RESET pin is released until the above
action is taken.
If a high level is input to the DRST pin before the above action is taken, it may cause a malfunction (CPU deadlock).
Handle the P56 pin with the utmost care.
Caution
After reset by the WDT2RES signal, clock monitor (CLM), or low-voltage detector (LVI), the
P56/INTP05/DRST pin is not initialized to function as an on-chip debug pin (DRST). The OCDM
register holds the current value.
4.5.4
Cautions on P56/INTP05/DRST pin
The P56/INTP05/DRST pin has an internal pull-down resistor (30 kΩ TYP.). After a reset by the RESET pin, a pulldown resistor is connected. The pull-down resistor is disconnected when the OCDM0 bit is cleared (0).
4.5.5
Cautions on P10, P11, and P53 pins when power is turned on
When the power is turned on, the following pins may output an undefined level temporarily even during reset.
• P10/ANO0 pin
• P11/ANO1 pin
• P53/SIF2/TIAB00/KR3/TOAB00/RTP03/DDO pin (V850ES/JG3-H only)
4.5.6
Hysteresis characteristics
In port mode, the following port pins do not have hysteresis characteristics.
P00 to P05
P20 to P25
P30 to P37
P40 to P42
P50 to P56
P60 to P65
P90 to P915
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CHAPTER 5 BUS CONTROL FUNCTION
CHAPTER 5 BUS CONTROL FUNCTION
The V850ES/JG3-H and V850ES/JH3-H are provided with an external bus interface function by which external
memories such as ROM and RAM, and I/O can be connected.
5.1
Features
Output is selectable from multiplexed bus output with a minimum of 3 bus cycles and separate bus output function
(V850ES/JH3-H only; the V850ES/JG3-H only supports the multiplexed bus.)
8-bit/16-bit data bus selectable
Wait function
• Programmable wait function of up to 7 states
• External wait function using WAIT pin
Idle state function
Bus hold function
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5.2
CHAPTER 5 BUS CONTROL FUNCTION
Bus Control Pins
The pins used to connect an external device are listed in the table below.
Table 5-1. V850ES/JH3-H Bus Control Pins (Multiplexed Bus)
Bus Control Pin
Alternate-Function Pin
I/O
AD0 to AD15
PDL0 to PDL15
I/O
A16 to A23
PDH0 to PDH7
Output
WAIT
PCM0
Function
Address/data bus
Address bus
Input
External wait control
CLKOUT
PCM1
Output
Internal system clock
WR0, WR1
PCT0, PCT1
Output
Write strobe signal
RD
PCT4
Output
Read strobe signal
ASTB
PCT6
Output
Address strobe signal
HLDRQ
PCM3
Input
HLDAK
PCM2
Output
CS0, CS2, CS3
PCS0, PCS2, PCS3
Output
Bus hold control
Chip select
Table 5-2. V850ES/JH3-H Bus Control Pins (Separate Bus Output Function)
Bus Control Pin
Alternate-Function Pin
I/O
I/O
Function
AD0 to AD15
PDL0 to PDL15
Data bus
A0 to A15
P90 to P915
Output
Address bus
A16 to A23
PDH0 to PDH7
Output
Address bus
WAIT
PCM0
Input
External wait control
CLKOUT
PCM1
Output
Internal system clock
WR0, WR1
PCT0, PCT1
Output
Write strobe signal
RD
PCT4
Output
Read strobe signal
HLDRQ
PCM3
Input
HLDAK
PCM2
Output
CS0, CS2, CS3
PCS0, PCS2, PCS3
Output
Bus hold control
Chip select
Table 5-3. V850ES/JG3-H Bus Control Pins (Multiplexed Bus)
Bus Control Pin
AD0 to AD15
Alternate-Function Pin
PDL0 to PDL15
I/O
I/O
Function
Address/data bus
WAIT
PCM0
Input
External wait control
CLKOUT
PCM1
Output
Internal system clock
WR0, WR1
PCT0, PCT1
Output
Write strobe signal
RD
P61
Output
Read strobe signal
ASTB
P62
Output
Address strobe signal
CS0, CS2, CS3
P63, P64, P65
Output
Chip select
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5.2.1
CHAPTER 5 BUS CONTROL FUNCTION
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed
When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows.
Table 5-4. Pin Statuses When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
Bus Control Pin
Separate Bus Output Function
Internal ROM/RAM
Address/data bus
Undefined
Peripheral I/O
Multiplexed Bus Mode
Internal ROM/RAM
Undefined
Undefined
Undefined (Address
Undefined
Peripheral I/O
Undefined
(AD15 to AD0)
Address bus
Undefined
(A23 to A16)
Address bus
output during access)
Undefined
(A15 to A0)
Control signal
Caution
Undefined (Address
Undefined
output during access)
Inactive
Inactive
Undefined (Address
output during access)
Undefined (Address
output during access)
Inactive
Inactive
When a write access is performed to the internal ROM area, address, data, and control signals are
activated in the same way as access to the external memory area.
5.2.2
Pin status in each operation mode
For the pin status of the V850ES/JG3-H and V850ES/JH3-H in each operation mode, see 2.2 Pin States.
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5.3
CHAPTER 5 BUS CONTROL FUNCTION
Memory Block Function
The 16 MB external memory space is divided into memory blocks of 2 MB, 4 MB, and 8 MB from the lowest of the
memory space.
The programmable wait function and bus cycle operation mode for each of these blocks can be
independently controlled in one-block units.
Figure 5-1. Data Memory Map: Physical Address
03FFFFFFH
On-chip peripheral
I/O area (4 KB)
(80 KB)
03FFFFFFH
03FFF000H
03FFEFFFH
03FEC000H
03FEBFFFH
Internal RAM area
(60 KB)
Use prohibited
Note 2
Use prohibited
Programmable peripheral
I/O areaNote 3
or use prohibitedNote 4
01000000H
00FFFFFFH
03FF0000H
03FEFFFFH
03FEF000H
03FEEFFFH
03FEC000H
003FFFFFH
Use prohibited
External memory area
(8 MB)
00300000H
002FFFFFH
CS3
Data-only RAM area
00280000H
0027FFFFH
Use prohibited
00250000H
0024FFFFH
00800000H
007FFFFFH
USB function area
External memory area
(4 MB)
00200000H
CS2
00400000H
003FFFFFH
00200000H
001FFFFFH
001FFFFFH
External memory area
(2 MB)
(2 MB)
Note 1
(CS1
CS0
)
External memory area
(1 MB)
00100000H
000FFFFFH
Internal ROM areaNote 5
(1 MB)
00000000H
00000000H
Notes 1. CS1 is not provided as an external signal of the V850ES/Jx3-H; it is used internally as a chip select
signal for the USB.
2. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because these addresses are in the
same area as the on-chip peripheral I/O area.
3. Only the programmable peripheral I/O area is seen as images of 256 MB each in the 4 GB address
space.
4. In the CAN controller version, addresses 03FEC000H to 03FEEFFFH are assigned as a
programmable peripheral I/O area in addresses 03FEC000H to 03FECBFFH. Use of these
addresses in a version without a CAN controller is prohibited.
5. This area is an external memory area in the case of a data write access.
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5.4
5.4.1
CHAPTER 5 BUS CONTROL FUNCTION
Bus Access
Number of clocks for access
The following table shows the number of basic clocks required for accessing each resource.
Area (Bus Width)
Internal ROM (32 Bits)
Internal RAM (32 Bits)
Bus Cycle Type
External Memory (16 Bits)
Multiplexed
Instruction fetch (normal access)
1
Instruction fetch (branch)
3
Operand data access
5
Note 2
3+n
Note 1
3+n
1
2
Note 1
Separate
1
3+n
Notes 1. V850ES/JH3-H only
2. Increases by 1 if a conflict with a data access occurs.
Remark
5.4.2
Unit: Clocks/access
Bus size setting function
Each external memory area selected by memory block CSn can be set by using the BSC register. However, the bus
size can be set to 8 bits and 16 bits only.
The external memory area of the V850ES/JG3-H and V850ES/JH3-H is selected by memory blocks CS0, CS2, and
CS3.
(1) Bus size configuration register (BSC)
The BSC register can be read or written in 16-bit units.
Reset sets this register to 5555H.
Caution
Write to the BSC register after reset, and then do not change the set values. Also, do not access
an external memory area until the initial settings of the BSC register are complete.
After reset: 5555H
BSC
R/W
14
13
12
11
10
9
8
0
1
0
1
0
1
0
1
7
6
5
4
3
2
1
0
0
BS30
0
BS20
0
1
0
BS00
CS3
BSn0
Caution
Address: FFFFF066H
15
CS2
CS0
Data bus width of memory block CSn space (n = 0, 2, 3)
0
8 bits
1
16 bits
Be sure to set bits 14, 12, 10, 8, and 2 to “1”, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to “0”.
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5.4.3
CHAPTER 5 BUS CONTROL FUNCTION
Access by bus size
The V850ES/JG3-H and V850ES/JH3-H access the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32bit units. The bus size is as follows.
• The bus size of the on-chip peripheral I/O is fixed to 16 bits.
• The bus size of the external memory is selectable from 8 bits or 16 bits (by using the BSC register).
The operation when each of the above is accessed is described below. All data is accessed starting from the lower side.
The V850ES/JG3-H and V850ES/JH3-H support only the little-endian format.
Figure 5-2. Little-Endian Address in Word
31
24 23
16 15
8 7
0
000BH
000AH
0009H
0008H
0007H
0006H
0005H
0004H
0003H
0002H
0001H
0000H
(1) Data space
The V850ES/JG3-H and V850ES/JH3-H have an address misalign function.
With this function, data can be placed at all addresses, regardless of the format of the data (word data or halfword
data). However, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least
twice, causing the bus efficiency to drop.
(a) Halfword-length data access
A byte-length bus cycle is generated twice if the least significant bit of the address is 1.
(b) Word-length data access
(i) A byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if
the least significant bit of the address is 1.
(ii) A halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10.
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(2) Byte access (8 bits)
(a) 16-bit data bus width
Access to even address (2n)
Access to odd address (2n + 1)
Address
Address
15
15
7
8
7
7
8
7
0
0
0
0
2n + 1
2n
Byte data
External data
bus
Byte data
External data
bus
(b) 8-bit data bus width
Access to even address (2n)
Access to odd address (2n + 1)
Address
Address
7
7
0
0
7
7
0
0
2n + 1
2n
Byte data
External data
bus
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External data
bus
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CHAPTER 5 BUS CONTROL FUNCTION
(3) Halfword access (16 bits)
(a) 16-bit data bus width
Access to even address (2n)
Access to odd address (2n + 1)
First access
Address
15
15
Address
2n + 1
8
7
8
7
15
15
8
7
8
7
Address
15
15
8
7
8
7
2n + 1
2n
0
Second access
2n + 2
2n
0
0
Halfword data External data
bus
0
Halfword data
0
External data
bus
0
Halfword data
External data
bus
(b) 8-bit data bus width
Access to even address (2n)
First access
15
Access to odd address (2n + 1)
15
Address
8
7
7
0
0
15
Address
8
7
7
0
0
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Halfword data External data
bus
Second access
15
Address
8
7
7
0
0
2n + 1
2n
Halfword data External data
bus
First access
Second access
Address
8
7
7
0
0
2n + 2
2n + 1
Halfword data External data Halfword data External data
bus
bus
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CHAPTER 5 BUS CONTROL FUNCTION
(4) Word access (32 bits)
(a) 16-bit data bus width (1/2)
Access to address (4n)
First access
Second access
31
31
24
23
24
23
Address
16
15
15
8
7
8
7
0
0
Address
16
15
15
8
7
8
7
0
0
4n + 1
4n + 3
4n
Word data External data
bus
4n + 2
Word data External data
bus
Access to address (4n + 1)
First access
Second access
Third access
31
31
31
24
23
24
23
24
23
Address
16
15
15
8
7
0
Address
16
15
15
8
7
8
7
8
7
0
0
0
4n + 1
Address
16
15
15
8
7
8
7
0
0
4n + 3
4n + 2
Word data External data
bus
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bus
4n + 4
Word data External data
bus
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CHAPTER 5 BUS CONTROL FUNCTION
(a) 16-bit data bus width (2/2)
Access to address (4n + 2)
First access
Second access
31
31
24
23
24
23
Address
16
15
15
8
7
8
7
Address
16
15
15
8
7
8
7
4n + 3
4n + 5
4n + 2
0
0
4n + 4
0
Word data External data
bus
0
Word data External data
bus
Access to address (4n + 3)
First access
Second access
Third access
31
31
31
24
23
24
23
24
23
Address
16
15
15
8
7
0
Address
16
15
15
8
7
8
7
8
7
0
0
0
4n + 3
Address
16
15
15
8
7
8
7
0
0
4n + 5
4n + 4
Word data External data
bus
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bus
4n + 6
Word data External data
bus
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CHAPTER 5 BUS CONTROL FUNCTION
(b) 8-bit data bus width (1/2)
Access to address (4n)
First access
Second access
Third access
Fourth access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
Address
8
7
7
0
0
Address
8
7
7
0
0
4n
Word data External data
bus
Address
8
7
7
0
0
4n + 1
Word data External data
bus
Address
8
7
7
0
0
4n + 2
Word data External data
bus
4n + 3
Word data External data
bus
Access to address (4n + 1)
First access
Second access
Third access
Fourth access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
8
7
7
0
0
Address
8
7
7
0
0
4n + 1
Word data External data
bus
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Address
8
7
7
0
0
4n + 2
Word data External data
bus
Address
8
7
7
0
0
4n + 3
Word data External data
bus
Address
4n + 4
Word data External data
bus
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CHAPTER 5 BUS CONTROL FUNCTION
(b) 8-bit data bus width (2/2)
Access to address (4n + 2)
First access
Second access
Third access
Fourth access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
8
7
Address
7
4n + 2
0
0
Word data External data
bus
Address
8
7
7
4n + 3
0
0
Word data External data
bus
8
7
Address
7
4n + 4
0
0
Word data External data
bus
8
7
Address
7
4n + 5
0
0
Word data External data
bus
Access to address (4n + 3)
First access
Second access
Third access
Fourth access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
Address
8
7
7
0
0
Address
8
7
7
0
0
4n + 3
Word data External data
bus
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Address
8
7
7
0
0
4n + 4
Word data External data
bus
Address
8
7
7
0
0
4n + 5
Word data External data
bus
4n + 6
Word data External data
bus
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5.5
5.5.1
CHAPTER 5 BUS CONTROL FUNCTION
Wait Function
Programmable wait function
(1) Data wait control register 0 (DWC0)
To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle
that is executed for each CS space.
The number of wait states can be programmed by using the DWC0 register. Immediately after system reset, 7 data
wait states are inserted for all the blocks.
The DWC0 register can be read or written in 16-bit units.
Reset sets this register to 7777H.
Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are
always accessed without a wait state. The on-chip peripheral I/O area is also not subject to
programmable wait, and only wait control from each peripheral function is performed.
2. Write to the DWC0 register after reset, and then do not change the set values. Also, do not
access an external memory area until the initial settings of the DWC0 register are complete.
After reset: 7777H
R/W
Address: FFFFF484H
15
14
13
12
11
10
9
8
0
DW32
DW31
DW30
0
DW22
DW21
DW20
7
6
4
3
2
1
0
0
DW02
DW01
DW00
DWC0
CS2
CS3
0
DW12
5
Note
Note
DW11
Note
DW10
CS0
Note
Number of wait states inserted in
CSn space (n = 0 to 3)
DWn2
DWn1
DWn0
0
0
0
None
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
The DW12 to DW10 bits set wait of access to the USB function area.
It is recommended to set the DW12 to DW10 bits to 001B (1 wait).
Caution
Be sure to clear bits 15, 11, 7, and 3 to “0”.
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5.5.2
CHAPTER 5 BUS CONTROL FUNCTION
External wait function
To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be
inserted in the bus cycle by using the external wait pin (WAIT).
When the P60Note 1 or PCM0Note 2 pin is set to its alternate function, the external wait function is enabled.
Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the
external wait function, in the same manner as the programmable wait function.
The WAIT signal can be input asynchronously to CLKOUT, and is sampled at the falling edge of the clock in the T2 and
TW states of the bus cycle. it is sampled at the rising edge of the clock immediately after the T1 and TW states of the bus
cycle. If the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted
at all.
Notes 1. V850ES/JG3-H
2. V850ES/JH3-H
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5.5.3
CHAPTER 5 BUS CONTROL FUNCTION
Relationship between programmable wait and external wait
Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the
programmable wait and the wait cycles controlled by the WAIT pin.
Programmable wait
Wait control
Wait via WAIT pin
For example, if the timing of the programmable wait and the WAIT pin signal is as illustrated below, three wait states will
be inserted in the bus cycle.
Figure 5-3. Inserting Wait Example
T1
T2
TW
TW
TW
T3
CLKOUT
WAIT pin
Wait via WAIT pin
Programmable wait
Wait control
Remark
The circles indicate the sampling timing.
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5.5.4
CHAPTER 5 BUS CONTROL FUNCTION
Programmable address wait function
Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address
wait insertion is set for each chip select area (CS0, CS2, CS3).
If an address setup wait is inserted, it seems that the high-clock period of the T1 state is extended by 1 clock. If an
address-hold wait is inserted, it seems that the low-clock period of the T1 state is extended by 1 clock.
(1) Address wait control register (AWC)
The AWC register can be read or written in 16-bit units.
Reset sets this register to FFFFH.
Cautions 1. Address-setup wait and address-hold wait cycles are not inserted when the internal ROM area,
internal RAM area, and on-chip peripheral I/O areas are accessed.
2. Write to the AWC register after reset, and then do not change the set values. Also, do not
access an external memory area until the initial settings of the AWC register are complete.
After reset: FFFFH
AWC
R/W
Address: FFFFF488H
15
14
13
12
11
10
9
8
1
1
1
1
1
1
1
1
7
6
5
4
3
1
0
AHW0
ASW0
AHW3
ASW3
AHW2
CS3
AHW1
Note
ASW1
CS2
CS0
Specifies insertion of address-hold wait (n = 0 to 3)
AHWn
0
Not inserted
1
Inserted
Specifies insertion of address-setup wait (n = 0 to 3)
ASWn
Note
ASW2
2
Note
0
Not inserted
1
Inserted
It is recommended to clear the AHW1 bit and the ASW1 bit to 0.
Caution
Be sure to set bits 15 to 8 to “1”.
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5.6
CHAPTER 5 BUS CONTROL FUNCTION
Idle State Insertion Function
To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle
that is executed for each space selected by the chip select. By inserting an idle state, the data output float delay time of
the memory can be secured during read access (an idle state cannot be inserted during write access).
Whether the idle state is to be inserted can be programmed by using the BCC register.
An idle state is inserted for all the areas immediately after system reset.
(1) Bus cycle control register (BCC)
The BCC register can be read or written in 16-bit units.
Reset sets this register to AAAAH.
Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle state
insertion.
2. Write to the BCC register after reset, and then do not change the set values. Also, do not
access an external memory area until the initial settings of the BCC register are complete.
After reset: AAAAH
BCC
R/W
Address: FFFFF48AH
15
14
13
12
11
10
9
8
1
0
1
0
1
0
1
0
7
6
5
4
3
2
1
0
0
BC01
0
BC31
0
BC21
CS3
0
BC11
Note
CS2
CS0
Specifies insertion of idle state (n = 0 to 3)
BCn1
0
Not inserted
1
Inserted
Note It is recommended to clear the BC11 bit to 0.
Caution
Be sure to set bits 15, 13, 11, and 9 to “1”, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to “0”.
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5.7
5.7.1
CHAPTER 5 BUS CONTROL FUNCTION
Bus Hold Function (V850ES/JH3-H only)
Functional outline
The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to their alternate function.
When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the
external address/data bus goes into a high-impedance state and is released (bus hold status). If the request for the bus
mastership is cleared and the HLDRQ pin is deasserted (high level), driving these pins is started again.
During the bus hold period, execution of the program in the internal ROM and internal RAM is continued until an onchip peripheral I/O register or the external memory is accessed.
The bus hold status is indicated by assertion of the HLDAK pin (low level). The bus hold function enables the
configuration of multi-processor type systems in which two or more bus masters exist.
Note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing function or
a bit manipulation instruction.
Status
Data Bus
Access Type
Timing at Which Bus Hold Request
Is Not Acknowledged
Width
CPU bus lock
16 bits
Word access to even address
Between first and second access
Word access to odd address
Between first and second access
Between second and third access
8 bits
Halfword access to odd address
Between first and second access
Word access
Between first and second access
Between second and third access
Between third and fourth access
Halfword access
Read-modify-write access of bit
manipulation instruction
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−
Between first and second access
−
Between read access and write
access
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5.7.2
CHAPTER 5 BUS CONTROL FUNCTION
Bus hold procedure
The bus hold status transition procedure is shown below.
HLDRQ = 0 acknowledged
All bus cycle start requests inhibited
Normal status
End of current bus cycle
Shift to bus idle status
HLDAK = 0
Bus hold status
HLDRQ = 1 acknowledged
HLDAK = 1
Bus cycle start request inhibition released
Bus cycle starts
Normal status
HLDRQ (input)
HLDAK (output)
5.7.3
Operation in power save mode
Because the internal system clock is stopped in the STOP, IDLE1, and IDLE2 modes, the bus hold status is not entered
even if the HLDRQ pin is asserted.
In the HALT mode, the HLDAK pin is asserted as soon as the HLDRQ pin has been asserted, and the bus hold status is
entered. When the HLDRQ pin is later deasserted, the HLDAK pin is also deasserted, and the bus hold status is cleared.
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5.8
CHAPTER 5 BUS CONTROL FUNCTION
Bus Priority
Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are
executed in the external bus cycle.
Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch (branch), and
instruction fetch (successive).
An instruction fetch may be inserted between the read access and write access in a read-modify-write access.
If an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between
accesses due to bus size limitations.
Table 5-5. Bus Priority
Priority
High
Low
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External Bus Cycle
Bus Master
Bus hold
External device
DMA transfer
DMAC
Operand data access
CPU
Instruction fetch (branch)
CPU
Instruction fetch (successive)
CPU
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V850ES/JG3-H, V850ES/JH3-H
5.9
CHAPTER 5 BUS CONTROL FUNCTION
Bus Timing
Figure 5-4. Multiplexed Bus/Separate Bus Output Function Read Timing (Bus Size: 16 Bits, 16-Bit Access)
T1
T2
T3
T1
T2
TW
TW
T3
TI
T1
CLKOUT
A23 to A0Note 1
A1
A2
A3
D2
A3
ASTB
CS3, CS2, CS0Note 2
WAIT
AD15 to AD0
A1
A2
D1
RD
Programmable External
wait
wait
8-bit Access
Idle state
Odd Address Even Address
AD15 to AD8
Active
Hi-Z
AD7 to AD0
Hi-Z
Active
Notes 1. V850ES/JH3-H only
2. Only the CS space subject to access is active.
Remark
The broken lines indicate high impedance.
Figure 5-5. Multiplexed Bus/Separate Bus Output Function Read Timing (Bus Size: 8 Bits)
T1
T2
T3
T1
T2
TW
TW
T3
TI
T1
CLKOUT
A23 to A0Note 1,
AD15 to AD8
A1
A2
A3
D2
A3
ASTB
CS3, CS2, CS0Note 2
WAIT
AD7 to AD0
A1
D1
A2
RD
Programmable External
wait
wait
Idle state
Notes 1. V850ES/JH3-H only
2. Only the CS space subject to access is active.
Remark
The broken lines indicate high impedance.
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CHAPTER 5 BUS CONTROL FUNCTION
Figure 5-6. Multiplexed Bus/Separate Bus Output Function Write Timing (Bus Size: 16 Bits, 16-Bit Access)
T1
T2
T3
T1
T2
TW
TW
T3
T1
CLKOUT
A23 to A0Note 1
A1
A2
A3
D2
A3
ASTB
CS3, CS2, CS0Note 2
WAIT
A1
AD15 to AD0
WR1, WR0
11
D1
A2
11
00
8-bit Access
11
Programmable External
wait
wait
Odd Address Even Address
AD15 to AD8
Active
Hi-Z
AD7 to AD0
Undefined
Active
WR1, WR0
01
10
11
00
Notes 1. V850ES/JH3-H only
2. Only the CS space subject to access is active.
Figure 5-7. Multiplexed Bus/Separate Bus Output Function Write Timing (Bus Size: 8 Bits)
T1
T2
T3
T1
T2
TW
TW
T3
T1
CLKOUT
A23 to A0Note 1,
AD15 to AD8
A1
A2
A3
D2
A3
ASTB
CS3, CS2, CS0Note 2
WAIT
AD7 to AD0
WR1, WR0
A1
11
D1
10
A2
11
11
10
11
Programmable External
wait
wait
Notes 1. V850ES/JH3-H only
2. Only the CS space subject to access is active.
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CHAPTER 5 BUS CONTROL FUNCTION
Figure 5-8. Multiplexed Bus/Separate Bus Output Function Hold Timing (Bus Size: 16 Bits, 16-Bit Access)
(V850ES/JH3-H only)
T1
T2
T3
TINote 1
TH
TH
TH
TH
TINote 1
T1
T2
T3
CLKOUT
HLDRQ
HLDAK
A23 to A0
A1
AD15 to AD0
A1
Undefined
Undefined
D1
Undefined
Undefined
1111
1111
A2
A2
D2
ASTB
RD
CS3, CS2, CS0Note 2
Notes 1. This idle state (TI) does not depend on the BCC register settings.
2. Only the CS space subject to access is active.
Remarks 1.
2.
See Table 2-2 for the pin statuses in the bus hold mode.
The broken lines indicate high impedance.
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CHAPTER 6 CLOCK GENERATION FUNCTION
CHAPTER 6 CLOCK GENERATION FUNCTION
6.1
Overview
The following clock generation functions are available.
Main clock oscillator
• In clock-through mode
fX = 3.0 to 6.0 MHz (fXX = 3.0 to 6.0 MHz)
• In PLL mode
fX = 3.0 to 6.0 MHz (×8: fXX = 24 to 48 MHz)
Subclock oscillator
• fXT = 32.768 kHz
Multiply (×8) function by PLL (Phase Locked Loop)
• Clock-through mode/PLL mode selectable
Internal oscillator
• fR = 220 kHz (TYP.)
Internal system clock generation
• 7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
Peripheral clock generation
Clock output function
Remark fX:
Main clock oscillation frequency
fXX: Main clock frequency
fXT: Subclock frequency
fR:
Internal oscillation clock frequency
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6.2
CHAPTER 6 CLOCK GENERATION FUNCTION
Configuration
Figure 6-1. Clock Generator
FRC bit
XT1
Subclock
oscillator
XT2
fXT
fXT
RTC clock,
WDT clock
Prescaler 3
PLL
Main clock
oscillator
stop control
IDLE mode
IDLE fXX
control
CK2 to CK0
bits
Prescaler 2
fXX/32
fXX/16
fXX/8
fXX/4
fXX/2
fXX
STOP mode
SELPLL bit
Internal
oscillator
fR
HALT
mode
Selector
Main clock
oscillator
fX
CLS, CK3
bits
Selector
X2
PLLON
bit
Selector
X1
IDLE
control
Selector
MFRC
bit
RTC clock
HALT fCPU
control
1/8 divider
fCLK
CPU clock
Internal
system clock
WDT clock,
TMM clock
RSTOP bit
Port CM
CLKOUT
UCLK
Remark
Prescaler 1
Selector
UCKSEL
bit
fX:
Main clock oscillation frequency
fXX:
Main clock frequency
Peripheral clock
USB clock
fCLK: Internal system clock frequency
fXT:
Subclock frequency
fCPU: CPU clock frequency
fR:
Internal oscillation clock frequency
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CHAPTER 6 CLOCK GENERATION FUNCTION
(1) Main clock oscillator
The main clock oscillator oscillates the following frequencies (fX).
• In clock-through mode
fX = 3.0 to 6.0 MHz
• In PLL mode
fX = 3.0 to 6.0 MHz (×8)
(2) Subclock oscillator
The sub-resonator oscillates a frequency of 32.768 kHz (fXT).
(3) Main clock oscillator stop control
This circuit generates a control signal that stops oscillation of the main clock oscillator.
Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only when
the PCC.CLS bit = 1).
(4) Internal oscillator
Oscillates a frequency (fR) of 220 kHz (TYP.).
(5) Prescaler 1
This prescaler generates the clock (fXX to fXX/1,024) to be supplied to the following on-chip peripheral functions:
TAA, TAB, TMM, TMT, CSIF, UARTC, I2C, CAN, ADC, DAC, WDT2
(6) Prescaler 2
This circuit divides the main clock (fXX).
The clock generated by prescaler 2 (fXX to fXX/32) is supplied to the selector that generates the CPU clock (fCPU)
and internal system clock (fCLK).
fCLK is the clock supplied to the INTC, ROM, and RAM blocks, and can be output from the CLKOUT pin.
(7) Prescaler 3
This circuit divides the clock generated by the main clock oscillator (fX) to a specific frequency (32.768 kHz) and
supplies that clock to the real-time counter (RTC) block.
(8) PLL
This circuit multiplies the clock generated by the main clock oscillator (fX) by 8.
It operates in two modes: clock-through mode in which fX is output as is, and PLL mode in which a multiplied clock
is output. These modes can be selected by using the PLLCTL.SELPLL bit.
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6.3
CHAPTER 6 CLOCK GENERATION FUNCTION
Registers
(1) Processor clock control register (PCC)
The PCC register is a special register.
Data can be written to this register only in combination of specific
sequences (see 3.4.8 Special registers).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 03H.
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After reset: 03H
CHAPTER 6 CLOCK GENERATION FUNCTION
R/W
Address: FFFFF828H
< >
< >
PCC
FRC
MCK
MFRC
FRC
Note
CLS
< >
CK3
CK2
CK1
CK0
Use of subclock on-chip feedback resistor
0
Used
1
Not used
MCK
Main clock oscillator control
0
Oscillation enabled
1
Oscillation stopped
• Even if the MCK bit is set (1) while the system is operating with the main clock as
the CPU clock, the operation of the main clock does not stop. It stops after the
CPU clock has been changed to the subclock.
• Before setting the MCK bit from 0 to 1, stop the on-chip peripheral functions
operating with the main clock.
• When the main clock is stopped and the device is operating with the subclock,
clear (0) the MCK bit and secure the oscillation stabilization time by software
before switching the CPU clock to the main clock or operating the on-chip
peripheral functions.
MFRC
Use of main clock on-chip feedback resistor
0
Used
1
Not used
CLSNote
Status of CPU clock (fCPU)
0
Main clock operation
1
Subclock operation
CK3
CK2
CK1
CK0
Clock selection (fCLK/fCPU)
0
0
0
0
fXX
0
0
0
1
fXX/2
0
0
1
0
fXX/4
0
0
1
1
fXX/8
0
1
0
0
fXX/16
0
1
0
1
fXX/32
0
1
1
×
Setting prohibited
1
×
×
×
fXT
Note The CLS bit is a read-only bit.
Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being
output.
2. Use a bit manipulation instruction to manipulate the CK3 bit.
When using an 8-bit
manipulation instruction, do not change the set values of the CK2 to CK0 bits.
Remark
×: don't care
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CHAPTER 6 CLOCK GENERATION FUNCTION
(a) Example of setting main clock operation → subclock operation
CK3 bit ← 1:
Use of a bit manipulation instruction is recommended. Do not change the CK2 to
CK0 bits.
Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following
time after the CK3 bit is set until subclock operation is started.
Max.: 1/fXT (1/subclock frequency)
MCK bit ← 1:
Set the MCK bit to 1 only when stopping the main clock.
Cautions 1. When stopping the main clock, stop the PLL. Also stop the operations of the on-chip
peripheral functions operating with the main clock.
2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the
conditions are satisfied, then change to the subclock operation mode.
Internal system clock (fCLK) > Subclock (fXT: 32.768 kHz) × 4
Remark
Internal system clock (fCLK): Clock generated from the main clock (fXX) by setting the CK2 to CK0
bits
[Description example]
_DMA_DISABLE:
clrl
0, DCHCn[r0]
-- DMA operation disabled. n = 0 to 3
_SET_SUB_RUN :
st.b
r0, PRCMD[r0]
set1
3, PCC[r0]
-- CK3 bit ← 1
_CHECK_CLS :
tst1
4, PCC[r0]
bz
_CHECK_CLS
-- Wait until subclock operation starts.
_STOP_MAIN_CLOCK :
st.b
r0, PRCMD[r0]
set1
6, PCC[r0]
-- MCK bit ← 1, main clock is stopped.
_DMA_ENABLE:
setl
Remark
0, DCHCn[r0]
-- DMA operation enabled. n = 0 to 3
The description above is simply an example. Note that in above, the CLS bit is read in a closed
loop.
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(b) Example of setting subclock operation → main clock operation
MCK bit ← 0:
Main clock starts oscillating
Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses.
CK3 bit ← 0:
Use of a bit manipulation instruction is recommended. Do not change the CK2
to CK0 bits.
Main clock operation:
It takes the following time after the CK3 bit is set until main clock operation is
started.
Max.: 1/fXT (1/subclock frequency)
Therefore, insert one NOP instruction immediately after setting the CK3 bit to 0
or read the CLS bit to check if main clock operation has started.
Caution Enable operation of the on-chip peripheral functions operating with the main clock only after
the oscillation of the main clock stabilizes. If their operations are enabled before the lapse of
the oscillation stabilization time, a malfunction may occur.
[Description example]
_DMA_DISABLE:
clrl
0, DCHCn[r0]
-- DMA operation disabled. n = 0 to 3
_START_MAIN_OSC :
st.b
r0, PRCMD[r0]
-- Release of protection of special registers
clr1
6, PCC[r0]
-- Main clock starts oscillating.
0x55, r0, r11
-- Wait for oscillation stabilization time.
movea
_WAIT_OST :
nop
nop
nop
addi
-1, r11, r11
cmp
r0, r11
bne
_WAIT_OST
st.b
clr1
r0, PRCMD[r0]
3, PCC[r0]
-- CK3 ← 0
_CHECK_CLS :
tst1
4, PCC[r0]
bnz
_CHECK_CLS
-- Wait until main clock operation starts.
_DMA_ENABLE:
setl
Remark
0, DCHCn[r0]
-- DMA operation enabled. n = 0 to 3
The description above is simply an example. Note that in above, the CLS bit is read in a closed
loop.
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(2) Internal oscillation mode register (RCM)
The RCM register is an 8-bit register that sets the operation mode of the internal oscillator.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address: FFFFF80CH
< >
RCM
0
0
0
RSTOP
0
0
0
0
RSTOP
Oscillation/stop of internal oscillator
0
Internal oscillator oscillation
1
Internal oscillator stopped
Cautions 1. The internal oscillator cannot be stopped while the CPU is operating on the internal
oscillation clock (CCLS.CCLSF bit = 1). Do not set the RSTOP bit to 1.
2. The internal oscillator oscillates if the CCLS.CCLSF bit is set to 1 (when WDT overflow
occurs during oscillation stabilization) even when the RSTOP bit is set to 1. At this time,
the RSTOP bit remains being set to 1.
(3) CPU operation clock status register (CCLS)
The CCLS register indicates the status of the CPU operation clock.
This register is read-only, in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00HNote
CCLS
0
R
Address: FFFFF82EH
0
CCLSF
0
0
0
0
0
CCLSF
CPU operation clock status
0
Operating on main clock (fX) or subclock (fXT).
1
Operating on internal oscillation clock (fR).
Note If WDT overflow occurs during oscillation stabilization after a reset is released, the CCLSF bit is set
to 1 and the reset value is 01H.
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6.4
6.4.1
CHAPTER 6 CLOCK GENERATION FUNCTION
Operation
Operation of each clock
The following table shows the operation status of each clock.
Table 6-1. Operation Status of Each Clock
Register Setting and
PCC Register
Operation Status
CLK Bit = 0, MCK Bit = 0
During
Reset
During
Oscillation
HALT
Mode
Stabilization
Target Clock
IDLE1,
IDLE2
Mode
CLS Bit = 1,
MCK Bit = 0
STOP
Mode
CLS Bit = 1,
MCK Bit = 1
Subclock Sub-IDLE Subclock Sub-IDLE
Mode
Mode
Mode
Mode
Time Count
Main clock oscillator (fX)
×
×
×
×
Subclock oscillator (fXT)
×
×
×
×
×
×
×
×
×
×
Note
×
×
Peripheral clock (fXX to fXX/1,024)
×
×
×
×
WT clock (main)
×
CPU clock (fCPU)
×
Internal system clock (fCLK)
×
Main clock (in PLL mode, fXX)
×
×
×
×
×
×
×
×
×
×
×
×
WT clock (sub)
WDT2 clock (internal oscillation)
×
WDT2 clock (main)
×
×
×
×
×
WDT2 clock (sub)
Note Lockup time
Remark
: Operable
×: Stopped
6.4.2
Clock output function
The clock output function is used to output the internal system clock (fCLK) from the CLKOUT pin.
The internal system clock (fCLK) is selected by using the PCC.CK3 to PCC.CK0 bits.
The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the control
register of port CM.
The status of the CLKOUT pin is the same as the internal system clock in Table 6-1 and the pin can output the clock
when it is in the operable status. It outputs a low level in the stopped status. However, the CLKOUT pin is in the port
mode (PCM1 pin: input mode) after reset and until it is set in the output mode. Therefore, the status of the pin is Hi-Z.
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6.5
6.5.1
CHAPTER 6 CLOCK GENERATION FUNCTION
PLL Function
Overview
In the V850ES/JG3-H and V850ES/JH3-H, an operating clock that is 8 times higher than the oscillation frequency
output by the PLL function or the clock-through mode can be selected as the operating clock of the CPU and on-chip
peripheral functions.
When PLL function is used (×8): Input clock = 3.0 to 6.0 MHz (output: 24 to 48 MHz)
Clock-through mode:
6.5.2
Input clock = 3.0 to 6.0 MHz (output: 3.0 to 6.0 MHz)
Registers
(1) PLL control register (PLLCTL)
The PLLCTL register is an 8-bit register that controls the PLL function.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
After reset: 01H
PLLCTL
0
R/W
Address: FFFFF82CH
0
0
0
PLLON
0
0
< >
< >
SELPLL
PLLON
PLL operation stop register
0
PLL stopped
1
PLL operating
(After PLL operation starts, a lockup time is required for frequency stabilization)
SELPLL
CPU operation clock selection register
0
Clock-through mode
1
PLL mode
Cautions 1. When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0 (clockthrough mode).
2. The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If not
(unlocked), "0" is written to the SELPLL bit if data is written to it.
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(2) Clock control register (CKC)
The CKC register is a special register. Data can be written to this register only in a combination of specific
sequence (see 3.4.8 Special registers).
The CKC register controls the internal system clock in the PLL mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 0AH.
After reset: 0AH
CKC
0
R/W
0
CKDIV0
Caution 1.
Address: FFFFF822H
0
0
1
0
1
CKDIV0
Internal system clock (fXX) in PLL mode
0
Setting prohibited
1
fXX = 8 × fX (fX = 3.0 to 6.0 MHz)
Be sure to set the CKC register to 0BH. When setting this register to a value other than
0BH or leaving it set to its initial value without setting it to 0BH, enabling PLL operation
(PLLCTL.SELPLL = 1) is prohibited.
2.
Remark
Be sure to set bits 3 and 1 to ‘‘1’’ and clear bits 7 to 4 and 2 to ‘‘0’’.
Both the CPU clock and peripheral clock are divided by the CKC register, but only the CPU clock is
divided by the PCC register.
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CHAPTER 6 CLOCK GENERATION FUNCTION
(3) Lock register (LOCKR)
Phase lock occurs at a given frequency following power application or immediately after the STOP mode is
released, and the time required for stabilization is the lockup time (frequency stabilization time). This state until
stabilization is called the lockup status, and the stabilized state is called the locked status.
The LOCKR register includes a LOCK bit that reflects the PLL frequency stabilization status.
This register is read-only, in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R
Address: FFFFF824H
< >
LOCKR
0
0
0
LOCK
0
0
0
0
LOCK
PLL lock status check
0
Locked status
1
Unlocked status
Caution The LOCK register does not reflect the lock status of the PLL in real time. The set/clear
conditions are as follows.
[Set conditions]
• Upon system resetNote
• In IDLE2 or STOP mode
• Upon setting of PLL stop (clearing of PLLCTL.PLLON bit to 0)
• Upon stopping main clock and using CPU with subclock (setting of PCC.CK3 bit to 1 and setting of
PCC.MCK bit to 1)
Note This register is set to 01H by reset and cleared to 00H after the reset has been released and the
oscillation stabilization time has elapsed.
[Clear conditions]
• Upon overflow of oscillation stabilization time following reset release (OSTS register default time (see 25.2
(3) Oscillation stabilization time select register (OSTS)))
• Upon oscillation stabilization timer overflow (time set by OSTS register) following STOP mode release,
when the STOP mode was set in the PLL operating status
• Upon PLL lockup time timer overflow (time set by PLLS register) when the PLLCTL.PLLON bit is changed
from 0 to 1
• After the setup time inserted upon release of the IDLE2 mode is released (time set by the OSTS register)
when the IDLE2 mode is set during PLL operation.
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(4) PLL lockup time specification register (PLLS)
The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed
from 0 to 1.
This register can be read or written in 8-bit units.
Reset sets this register to 03H.
After reset: 03H
R/W
Address: FFFFF6C1H
0
0
PLLS1
PLLS0
0
0
210/fX
0
1
211/fX
1
0
212/fX
1
1
213/fX (default value)
PLLS
0
0
0
0
PLLS1
PLLS0
Selection of PLL lockup time
Cautions 1. Set so that the lockup time is 800 μs or longer.
2. Do not change the PLLS register setting during the lockup period.
6.5.3
Usage
(1) When PLL is used
• After the reset signal has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default
mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1).
• To enable PLL operation, first set the PLLON bit to 1, and then set the SELPLL bit to 1 after the LOCKR.LOCK
bit = 0. To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8 clocks or more, and then
stop the PLL (PLLON bit = 0).
• The PLL stops during transition to the IDLE2 or STOP mode regardless of the setting and is restored from the
IDLE2 or STOP mode to the status before transition. The time required for restoration is as follows.
(a) When transiting to the IDLE2 or STOP mode from the clock through mode
• STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer.
• IDLE2 mode: Set the OSTS register so that the setup time is 350 μs (min.) or longer.
(b) When transiting to the IDLE 2 or STOP mode while remaining in the PLL operation mode
• STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer.
• IDLE2 mode: Set the OSTS register so that the setup time is 800 μs (min.) or longer.
When transiting to the IDLE1 mode, the PLL does not stop. Stop the PLL if necessary.
(2) When PLL is not used
• The clock-through mode (SELPLL bit = 0) is selected after the reset signal has been released, but the PLL is
operating (PLLON bit = 1) and must therefore be stopped (PLLON bit = 0).
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Timer AA (TAA) is 16-bit timer/event counter.
The V850ES/JG3-H and V850ES/JH3-H have TAA0 to TAA5.
7.1
Overview
An overview of TAAn is shown below.
• Clock selection:
8 ways
• Capture/trigger input pins:
2
• External event count input pinsNote:
1
• External trigger input pinNote:
1
• Timer/counter:
1
• Capture/compare registers:
2
(32-bit capture timer function available by using a cascade connection of TAA0 and TAA1, TAA2 and TAA3.)
• Capture/compare match interrupt request signals: 2
• Timer output pins:
2
Note External event count input pins and external trigger input pins are alternately used as capture/trigger input pins
(TIAAm0).
Remark
7.2
n = 0 to 5, m = 0 to 3, 5
Functions
TAAn has the following functions.
• Interval timer
• External event counter
• External trigger pulse output
• One-shot pulse output
• PWM output
• Free-running timer
• Pulse width measurement
• Timer-tuned function
• Simultaneous-start function
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Configuration
TAAn includes the following hardware.
Table 7-1. Configuration of TAAn
Item
Configuration
Registers
16-bit counter
TAAn capture/compare registers 0, 1 (TAAnCCR0, TAAnCCR1)
TAAn counter read buffer register (TAAnCNT)
CCR0, CCR1 buffer registers
TAAn control registers 0, 1 (TAAnCTL0, TAAnCTL1)
TAAm I/O control registers 0 to 2, 4 (TAAmIOC0 to TAAmIOC2, TAAmIOC4)
TAAm option registers 0, 1 (TAAmOPT0, TAAmOPT1)
TAA noise elimination control register (TANFC)
Timer inputs
Note 1
2 (TIAAm0
Note 1
Timer outputs
Notes1.
Note 2
, TIAAm1 pins)
2 (TOAAm0, TOAAm1 pins)
When using the functions of the TIAAm0, TIAAm1, TOAAm0, and TOAAm1 pins, see Table 4-20
Using Port Pin as Alternate-Function Pin.
2.
The TIAAm0 pin functions alternately as a capture trigger input signal, external event count input
signal, and external trigger input signal.
Remark
n = 0 to 5, m = 0 to 3, 5
Figure 7-1. Block Diagram of TAAn
Internal bus
Selector
TAAnCNT
Clear
TIAAm1
Edge
detector
CCR0
buffer
register
TIAAm0
INTTAAnOV
16-bit counter
Output
controller
Selector
Note
fXX
fXX/2
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
fXX/128
CCR1
buffer
register
TOAAm0
TOAAm1
INTTAAnCC0
INTTAAnCC1
TAAnCCR0
TAAnCCR1
Internal bus
Note TAA2, TAA3, TAA5: fXX/2, fXX/4, fXX/8, fXX/16, fXX/64, fXX/256, fXX/512, fXX/1024.
Remark
fXX: Main clock frequency
n = 0 to 5, m = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(1) 16-bit counter
This 16-bit counter can count internal clocks or external events.
The count value of this counter can be read by using the TAAnCNT register.
When the TAAnCTL0.TAAnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TAAnCNT register is read at
this time, 0000H is read.
Reset sets the TAAnCE bit to 0. Therefore, the 16-bit counter is set to FFFFH.
(2) CCR0 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TAAnCCR0 register is used as a compare register, the value written to the TAAnCCR0 register is
transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0
buffer register, a compare match interrupt request signal (INTTAAnCC0) is generated.
The CCR0 buffer register cannot be read or written directly.
Reset clears the TAAnCCR0 register to 0000H. Therefore, the CCR0 buffer register is cleared to 0000H.
(3) CCR1 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TAAnCCR1 register is used as a compare register, the value written to the TAAnCCR1 register is
transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1
buffer register, a compare match interrupt request signal (INTTAAnCC1) is generated.
The CCR1 buffer register cannot be read or written directly.
Reset clears the TAAnCCR1 register to 0000H. Therefore, the CCR1 buffer register is cleared to 0000H.
(4) Edge detector
This circuit detects the valid edges input to the TIAAm0 and TIAAm1 pins. No edge, rising edge, falling edge, or
both the rising and falling edges can be selected as the valid edge by using the TAAmIOC1 and TAAmIOC2
registers.
(5) Output controller
This circuit controls the output of the TOAAm0 and TOAAm1 pins. The outputs of the TOAAm0 and TOAAm1 pins
are controlled by the TAAmIOC0 register.
(6) Selector
This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can
be selected as the count clock.
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7.3.1
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Pin configuration
The timer inputs and outputs that configure TAAn are shared with the following ports. The port functions must be set
when using each pin (see Table 4-20 When Using Port Pins as Alternate-Function Pins).
Table 7-2 Pin Configuration
Channel
TAA0
TAA1
TAA2
TAA3
Port
Timer AA Input
P32
TIAA00
P33
TIAA01
P34
TIAA10
P35
TIAA11
P97
TIAA20
P96
TIAA21
P95
TIAA30
P94
TIAA31
Note 1
Note 1
Note 1
Note 1
−
TAA4
−
TAA5
P915
TIAA50
P914
TIAA51
Timer AA Output
TOAA00
ASCK0/SCKF4
TOAA01
RTCDIV/RTCCL
TOAA10
TOAA1OFF/INTP09
TOAA11
RTC1HZ
TOAA20
SIF1/A7
TOAA21
INTP11/A6
TOAA30
A5
TOAA31
TENC00/EVTT0/A4
Note 2
Note 2
Note 2
Note 2
−
−
−
−
Note 1
Other Alternate Function
−
−
TOAA50
INTP18/A15
Note 2
TOAA51
INTP17/A14
Note 2
Notes 1. The TAAm0 pin functions alternately as a capture trigger input function, external event input function, and
external trigger input function.
2. V850ES/JH3-H only
Remark
TAA4 has neither timer inputs nor outputs. Consequently, only the interval timer function can use TAA4 by
itself. However, the 6-phase PWM output function can be achieved by using TAA4 together with TAB1.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Registers
The registers that control TAAn are as follows.
• TAAn control register 0 (TAAnCTL0)
• TAAn control register 1 (TAAnCTL1)
• TAAn I/O control register 0 (TAAmIOC0)
• TAAn I/O control register 1 (TAAmIOC1)
• TAAn I/O control register 2 (TAAmIOC2)
• TAAn I/O control register 4 (TAAmIOC4)
• TAAn option register 0 (TAAmOPT0)
• TAAn option register 1 (TAAmOPT1)
• TAAn capture/compare register 0 (TAAnCCR0)
• TAAn capture/compare register 1 (TAAnCCR1)
• TAAn counter read buffer register (TAAnCNT)
• TAA noise elimination control register (TANFC)
Remarks 1. When using the functions of the TIAAm0, TIAAm1, TOAAm0, and TOAAm1 pins, see Table 4-20 Using
Port Pin as Alternate-Function Pin.
2. n = 0 to 5, m = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(1) TAAn control register 0 (TAAnCTL0)
The TAAnCTL0 register is an 8-bit register that controls the operation of TAAn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The same value can always be written to the TAAnCTL0 register by software.
After reset: 00H
R/W
Address:
TAA0CTL0 FFFFF630H, TAA1CTL0 FFFFF640H,
TAA2CTL0 FFFFF650H, TAA3CTL0 FFFFF660H,
TAA4CTL0 FFFFF670H, TAA5CTL0 FFFFF680H
TAAnCTL0
7
6
5
4
3
TAAnCE
0
0
0
0
2
1
0
TAAnCKS2 TAAnCKS1 TAAnCKS0
(n = 0 to 5)
TAAnCE
TAAn operation control
0
TAAn operation disabled (TAAn reset asynchronouslyNote ).
1
TAAn operation enabled. TAAn operation started.
TAAnCKS2 TAAnCKS1 TAAnCKS0
Internal count clock selection
n = 0, 1, 4
n = 2, 3, 5
0
0
0
fXX
(20.8 ns)
fXX/2
(41.7 ns)
0
0
1
fXX/2
(41.7 ns)
fXX/4
(83.3 ns)
0
1
0
fXX/4
(83.3 ns)
fXX/8
(166.7 ns)
0
1
1
fXX/8
(166.7 ns)
fXX/16
(333.3 ns)
1
0
0
fXX/16
(333.3 ns)
fXX/64
(1.3333 μ s)
1
0
1
fXX/32
(666.7 ns)
fXX/256
(5.3333 μ s)
1
1
0
fXX/64
(1.3333 μ s)
fXX/512
(10.6667 μ s)
1
1
1
fXX/128 (2.6667 μs)
fXX/1024 (21.3333 μ s)
Note TAAnOPT0.TAAnOVF bit, 16-bit counter, timer output (TOAAn0, TOAAn1 pins)
Cautions 1. Set the TAAnCKS2 to TAAnCKS0 bits when the TAAnCE bit = 0.
When the value of the TAAnCE bit is changed from 0 to 1, the
TAAnCKS2 to TAAnCKS0 bits can be set simultaneously.
2. Be sure to set bits 3 to 6 to “0”.
Remark
fXX: Main clock frequency
The values in parentheses indicate the cycles when fXX = 48 MHz.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(2) TAAn control register 1 (TAAnCTL1)
The TAAnCTL1 register is an 8-bit register that controls the operation of TAAn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(1/2)
After reset: 00H
R/W
Address:
TAA0CTL1 FFFFF631H, TAA1CTL1 FFFFF641H,
TAA2CTL1 FFFFF651H, TAA3CTL1 FFFFF661H,
TAA4CTL1 FFFFF671H, TAA5CTL1 FFFFF681H
7
TAA0CTL1
TAA1CTL1
TAA2CTL1
6
5
4
TAA0SYE TAA0EST TAA0EEETAA0SYM
0
TAA1EST TAA1EEE
2
1
0
TAA0MD2 TAA0MD1 TAA0MD0
0
TAA1MD2 TAA1MD1 TAA1MD0
0
TAA2MD2 TAA2MD1 TAA2MD0
0
0
TAA3MD2 TAA3MD1 TAA3MD0
0
TAA2SYE TAA2EST TAA2EEETAA2SYM
TAA3EST TAA3EEE
3
0
TAA3CTL1
0
TAA4CTL1
TAA4SYE
TAA4SYM
0
TAA4MD2 TAA4MD1 TAA4MD0
TAA5CTL1
TAA5SYE TAA5EST TAA5EEETAA5SYM
0
TAA5MD2 TAA5MD1 TAA5MD0
0
0
TAAmSYETAAmSYM
Tuned operation mode enable control (m = 0, 2, 4, 5)
0
0
Independent operation mode (asynchronous operation mode)
0
1
Setting prohibited
1
0
Tuned-operation function (specification of slave operation)
1
1
Simultaneous-start function (specification of slave timer)
These bits can be set only for the slave timer (setting them for the master timer is
prohibited).
The relationship between the master timer and slave timer is as follows.
Master timer
Slave timer
TAA1
TAA0
TAA3
TAA2
TAB0
TAA5
TAB1
TAA4
For the tuned-operation function, see 7.6 Timer-Tuned Operation Function.
For the simultaneous-start function, see 7.7 Simultaneous-Start Function.
TAAnEST
Software trigger control (n = 0 to 3, 5)
0
−
1
Generates a valid signal for external trigger input.
• In one-shot pulse output mode:
A one-shot pulse is output with writing 1 to the TAAnEST bit as the trigger.
• In external trigger pulse output mode:
A PWM waveform is output with writing 1 to the TAAnEST bit as the trigger.
Cautions 1. The TAAnEST bit is valid only in the external trigger pulse output
mode or one-shot pulse output mode. In any other mode, writing 1
to this bit is ignored.
2. Be sure to clear the sections of the TAAnCTL1 register of each
channel, where 0 is specified, to 0.
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(2/2)
TAAmEEE
Count clock selection
0
Disables operation with external event count input.
(Performs counting with the count clock selected by the
TAAmCTL0.TAAmCK0 to TAAmCK2 bits.)
1
Enables operation with external event count input.
(Performs counting at every valid edge of the external event count input
signal.)
The TAAmEEE bit selects whether counting is performed with the internal count
clock or the valid edge of the external event count input.
TAAnMD2 TAAnMD1 TAAnMD0
Timer mode selection
0
0
0
Interval timer mode
0
0
1
External event count mode
0
1
0
External trigger pulse output mode
0
1
1
One-shot pulse output mode
1
0
0
PWM output mode
1
0
1
Free-running timer mode
1
1
0
Pulse width measurement mode
1
1
1
Setting prohibited
Cautions 1. External event count input is selected in the external event count mode
regardless of the value of the TAAmEEE bit.
2. Set the TAAmEEE and TAAmMD2 to TAAmMD0 bits when the
TAAmCTL0.TAAmCE bit = 0. (The same value can be written when the
TAAmCE bit = 1.)
The operation is not guaranteed when rewriting is
performed with the TAAmCE bit = 1.
If rewriting was mistakenly
performed, clear the TAAnCE bit to 0 and then set the bits again (m = 0 to
3, 5).
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(3) TAAn I/O control register 0 (TAAnIOC0)
The TAAnIOC0 register is an 8-bit register that controls the timer output (TOAAn0, TOAAn1 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address:
TAA0IOC0 FFFFF632H, TAA1IOC0 FFFFF642H,
TAA2IOC0 FFFFF652H, TAA3IOC0 FFFFF662H,
TAA5IOC0 FFFFF682H
TAAnIOC0
7
6
5
4
0
0
0
0
3
2
1
0
TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0
(n = 0 to 3, 5)
TOAAn1 pin output level settingNote
TAAnOL1
0
TOAAn1 pin output starts at high level
1
TOAAn1 pin output starts at low level
TAAnOE1
TOAAn1 pin output setting
0
Timer output disabled
• When TAAnOL1 bit = 0: Low level is output from the TOAAn1 pin
• When TAAnOL1 bit = 1: High level is output from the TOAAn1 pin
1
Timer output enabled (a square wave is output from the TOAAn1 pin).
TOAAn0 pin output level settingNote
TAAnOL0
0
TOAAn0 pin output starts at high level
1
TOAAn0 pin output starts at low level
TAAnOE0
TOAAn0 pin output setting
0
Timer output disabled
• When TAAnOL0 bit = 0: Low level is output from the TOAAn0 pin
• When TAAnOL0 bit = 1: High level is output from the TOAAn0 pin
1
Timer output enabled (a square wave is output from the TOAAn0 pin).
Note The output level of the timer output pin (TOAAnm) specified by the
TAAnOLm bit is shown below.
• When TAAnOLm bit = 0
• When TAAnOLm bit = 1
16-bit counter
16-bit counter
TAAnCE bit
TAAnCE bit
TOAAnm pin output
TOAAnm pin output
Cautions 1. Rewrite the TAAnOL1, TAAnOE1, TAAnOL0, and TAAnOE0
bits when the TAAnCTL0.TAAnCE bit = 0. (The same value
can be written when the TAAnCE bit = 1.) If rewriting was
mistakenly performed, clear the TAAnCE bit to 0 and then
set the bits again.
2. Even if the TAAnOLm bit is manipulated when the TAAnCE
and TAAnOEm bits are 0, the TOAAnm pin output level
varies.
Remark
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(4) TAAn I/O control register 1 (TAAnIOC1)
The TAAnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIAAn0,
TIAAn1 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address:
TAA0IOC1 FFFFF633H, TAA1IOC1 FFFFF643H,
TAA2IOC1 FFFFF653H, TAA3IOC1 FFFFF663H,
TAA5IOC1 FFFFF683H
TAAnIOC1
7
6
5
4
0
0
0
0
3
2
0
1
TAAnIS3 TAAnIS2 TAAnIS1 TAAnIS0
(n = 0 to 3, 5)
TAAnIS3 TAAnIS2
Capture trigger input signal (TIAAn1 pin) valid edge setting
0
0
No edge detection (capture operation invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
TAAnIS1 TAAnIS0
Capture trigger input signal (TIAAn0 pin) valid edge setting
0
0
No edge detection (capture operation invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
Cautions 1.
Rewrite
the
TAAnIS3
to
TAAnCTL0.TAAnCE bit = 0.
TAAnIS0
bits
when
the
(The same value can be
written when the TAAnCE bit = 1.)
If rewriting was
mistakenly performed, clear the TAAnCE bit to 0 and then
set the bits again.
2.
The TAAnIS3 to TAAnIS0 bits are valid only in the freerunning timer mode and the pulse width measurement
mode.
In all other modes, a capture operation is not
performed.
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(5) TAAn I/O control register 2 (TAAnIOC2)
The TAAnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal
(TIAAn0 pin) and external trigger input signal (TIAAn0 pin).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address:
TAA0IOC2 FFFFF634H, TAA1IOC2 FFFFF644H,
TAA2IOC2 FFFFF654H, TAA3IOC2 FFFFF664H.
TAA5IOC2 FFFFF684H
TAAnIOC2
(n = 0 to 3, 5)
7
6
5
4
0
0
0
0
3
2
1
0
TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0
TAAnEES1 TAAnEES0 External event count input signal (TIAAn0 pin) valid edge setting
0
0
No edge detection (external event count invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
TAAnETS1 TAAnETS0
External trigger input signal (TIAAn0 pin) valid edge setting
0
0
No edge detection (external trigger invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
Cautions 1. Rewrite the TAAnEES1, TAAnEES0, TAAnETS1, and
TAAnETS0 bits when the TAAnCTL0.TAAnCE bit = 0. (The
same value can be written when the TAAnCE bit = 1.) If
rewriting was mistakenly performed, clear the TAAnCE bit
to 0 and then set the bits again.
2. The TAAnEES1 and TAAnEES0 bits are valid only when
the TAAnCTL1.TAAnEEE bit = 1 or when the external
event
count
mode
(TAAnCTL1.TAAnMD2
to
TAAnCTL1.TAAnMD0 bits = 001) has been set.
3. The TAAnETS1 and TAAnETS0 bits are valid only when
the
external
trigger
pulse
output
mode
(TAAnCTL1.TAAnMD2 to TAAnCTL1.TAAnMD0 bits = 010)
or the one-shot pulse output mode (TAAnCTL1.TAAnMD2
to TAAnCTL1.TAAnMD0 = 011) is set.
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(6) TAAn I/O control register 4 (TAAnIOC4)
The TAAnIOC4 register is an 8-bit register that controls the timer output.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H. This register is not reset by stopping the timer operation (TAAnCTL0.TAAnCE = 0).
Cautions 1. Accessing the TAAnIOC4 register is prohibited in the following statuses. For details, see 3.4.9
(2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
2. The TAAnIOC4 register can be set only in the interval timer mode and free-running timer mode.
Be sure to set the TAAnIOC4 register to 00H in all other modes (for details of the mode setting,
see 7.4 (2) TAAn control register 1 (TAAnCTL1)). The TAAnIOC4 register setting is invalid if the
TAAnCCR0 and TAAnCCR1 registers are set to the capture function, even if the free-running
timer mode is set.
After reset: 00H
R/W
Address:
TAA0IOC4 FFFFF63CH, TAA1IOC4 FFFFF64CH,
TAA2IOC4 FFFFF65CH, TAA3IOC4 FFFFF66CH,
TAA5IOC4 FFFFF68CH
TAAnIOC4
7
6
5
4
0
0
0
0
3
2
1
0
TAAnOS1 TAAnOR1 TAAnOS0 TAAnOR0
(n = 0 to 3, 5)
Toggle control of TIAAn1 pin
TAAnOS1 TAAnOR1
0
0
No request. Normal toggle operation.
0
1
Reset request
Fix to inactive level upon next match between value of 16-bit
counter and value of TAAnCCR1 register.
1
0
Set request
Fix to active level upon next match between value of 16-bit
counter and value of TAAnCCR1 register.
1
1
Keep request
Keep current output level.
TAAnOS0 TAAnOR0
Toggle control of TIAAn0
0
0
No request. Normal toggle operation.
0
1
Reset request
Fix to inactive level upon next match between value of 16-bit
counter and value of TAAnCCR0 register.
1
0
Set request
Fix to active level upon next match between value of 16-bit
counter and value of TAAnCCR0 register.
1
1
Keep request
Keep current output level.
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(7) TAAn option register 0 (TAAnOPT0)
The TAAnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address:
TAA0OPT0 FFFFF635H, TAA1OPT0 FFFFF645H,
TAA2OPT0 FFFFF655H, TAA3OPT0 FFFFF665H,
TAA5OPT0 FFFFF685H
TAAnOPT0
7
6
0
0
5
4
TAAnCCS1TAAnCCS0
3
2
1
0
0
0
0
TAAnOVF
(n = 0 to 3, 5)
TAAnCCS1
TAAnCCR1 register capture/compare selection
0
Compare register selected
1
Capture register selected
The TAAnCCS1 bit setting is valid only in the free-running timer mode.
TAAnCCS0
TAAnCCR0 register capture/compare selection
0
Compare register selected
1
Capture register selected
The TAAnCCS0 bit setting is valid only in the free-running timer mode.
TAAnOVF
TAAn overflow detection flag
Set (1)
Overflow occurred
Reset (0)
0 written to TAAnOVF bit or TAAnCTL0.TAAnCE bit = 0
• The TAAnOVF bit is set to 1 when the 16-bit counter count value overflows from
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
• An interrupt request signal (INTTAAnOV) is generated at the same time that the
TAAnOVF bit is set to 1. The INTTAAnOV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
• The TAAnOVF bit is not cleared even when the TAAnOVF bit or the TAAnOPT0
register are read when the TAAnOVF bit = 1.
• The TAAnOVF bit can be both read and written, but the TAAnOVF bit cannot be
set to 1 by software. Writing 1 has no influence on the operation of TAAn.
Cautions 1. Rewrite the TAAnCCS1 and TAAnCCS0 bits when the
TAAnCE bit = 0. (The same value can be written when the
TAAnCE bit = 1.) If rewriting was mistakenly performed,
clear the TAAnCE bit to 0 and then set the bits again.
2. Be sure to set bits 1 to 3, 6, and 7 to “0”.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(8) TAAn option register 1 (TAAnOPT1)
The TAAnOPT1 register is an 8-bit register that controls the 32-bit capture function realized by a cascade
connection.
Rewriting this register is prohibited while the timer is operating (TAAnCTL0.TAAnCE = 1).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
TAAnOPT1
R/W
Address:
TAA0OPT1 FFFFF63DH, TAA2OPT1 FFFFF65DH
7
6
5
4
3
2
1
0
TAAnCSE
0
0
0
0
0
0
0
(n = 0, 2)
TAAnCSE
Cascade control
0
Individual operation or operation as lower side of cascade function
1
Operation as higher side of cascade function
Cautions 1. Cascade connection and timer-tuned operation cannot be
used together. Be sure to set TAAnCTL1.TAAnSYE to 0 for
a cascade connection.
2. For a cascade connection, set the free-running timer
mode and use the TAAnCCR0 and TAAnCCR1 registers as
capture registers.
For details of cascade connection, see 7.8
Cascade
Connection.
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(9) TAAn capture/compare register 0 (TAAnCCR0)
The TAAnCCR0 register can be used as a capture register or a compare register depending on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
depending on the setting of the TAAnOPT0.TAAnCCS0 bit. In the pulse width measurement mode, the TAAnCCR0
register can be used only as a capture register. In any other mode, this register can be used only as a compare
register.
The TAAnCCR0 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution
Accessing the TAAnCCR0 register is prohibited in the following statuses. For details, see 3.4.9
(2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
After reset: 0000H
R/W
Address:
TAA0CCR0 FFFFF636H, TAA1CCR0 FFFFF646H,
TAA2CCR0 FFFFF656H, TAA3CCR0 FFFFF666H,
TAA4CCR0 FFFFF676H, TAA5CCR0 FFFFF686H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TAAnCCR0
(n = 0 to 5)
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(a) Function as compare register
The TAAnCCR0 register can be rewritten even when the TAAnCTL0.TAAnCE bit = 1.
The set value of the TAAnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal
(INTTAAnCC0) is generated. If TOAAn0 pin output is enabled at this time, the output of the TOAAn0 pin is
inverted.
When the TAAnCCR0 register is used as a cycle register in the interval timer mode, external event count mode,
external trigger pulse output mode, one-shot pulse output mode, or PWM output mode, the value of the 16-bit
counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register.
(b) Function as capture register
When the TAAnCCR0 register is used as a capture register in the free-running timer mode, the count value of
the 16-bit counter is stored in the TAAnCCR0 register if the valid edge of the capture trigger input pin (TIAAn0
pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the
TAAnCCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin
(TIAAn0) is detected.
Even if the capture operation and reading the TAAnCCR0 register conflict, the correct value of the TAAnCCR0
register can be read.
The following table shows the functions of the capture/compare register in each mode, and how to write data to the
compare register.
Table 7-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
Capture/Compare Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(10) TAAn capture/compare register 1 (TAAnCCR1)
The TAAnCCR1 register can be used as a capture register or a compare register depending on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
depending on the setting of the TAAnOPT0.TAAnCCS1 bit.
In the pulse width measurement mode, the
TAAnCCR1 register can be used only as a capture register. In any other mode, this register can be used only as a
compare register.
The TAAnCCR1 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution
Accessing the TAAnCCR1 register is prohibited in the following statuses. For details, see 3.4.9
(2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
After reset: 0000H
R/W
Address:
TAA0CCR1 FFFFF638H, TAA1CCR1 FFFFF648H,
TAA2CCR1 FFFFF658H, TAA3CCR1 FFFFF668H,
TAA4CCR1 FFFFF678H, TAA5CCR1 FFFFF688H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TAAnCCR1
(n = 0 to 5)
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(a) Function as compare register
The TAAnCCR1 register can be rewritten even when the TAAnCTL0.TAAnCE bit = 1.
The set value of the TAAnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal
(INTTAAnCC1) is generated. If TOAAn1 pin output is enabled at this time, the output of the TOAAn1 pin is
inverted.
(b) Function as capture register
When the TAAnCCR1 register is used as a capture register in the free-running timer mode, the count value of
the 16-bit counter is stored in the TAAnCCR1 register if the valid edge of the capture trigger input pin (TIAAn1
pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the
TAAnCCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin
(TIAAn1) is detected.
Even if the capture operation and reading the TAAnCCR1 register conflict, the correct value of the TAAnCCR1
register can be read.
The following table shows the functions of the capture/compare register in each mode, and how to write data to the
compare register.
Table 7-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
Capture/Compare Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(11) TAAn counter read buffer register (TAAnCNT)
The TAAnCNT register is a read buffer register that can read the count value of the 16-bit counter.
If this register is read when the TAAnCTL0.TAAnCE bit = 1, the count value of the 16-bit timer can be read.
This register is read-only, in 16-bit units.
The value of the TAAnCNT register is cleared to 0000H when the TAAnCE bit = 0. If the TAAnCNT register is read
at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read.
Reset clears the TAAnCE bit to 0. Therefore, the value of the TAAnCNT register is cleared to 0000H.
Caution
Accessing the TAAnCNT register is prohibited in the following statuses. For details, see 3.4.9 (2)
Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
After reset: 0000H
R
Address:
TAA0CNT FFFFF63AH, TAA1CNT FFFFF64AH,
TAA2CNT FFFFF65AH, TAA3CNT FFFFF66AH,
TAA4CNT FFFFF67AH, TAA5CNT FFFFF68AH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TAAnCNT
(n = 0 to 5)
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(12) Noise elimination control register (TANFC)
Digital noise elimination can be selected for the TIAAn0 and TIAAn1 pins. The noise elimination setting is selected
using the TANFC register.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among fXX
and fXX/4. Sampling is performed 3 times.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution
Time equal to the sampling clock × 3 clocks is required until the digital noise eliminator is
initialized after the sampling clock has been changed. If the valid edge of TIAAn0 and TIAAn1 is
input after the sampling clock has been changed and before the time of the sampling clock × 3
clocks passes, therefore, an interrupt request signal may be generated. Therefore, when using
the external trigger function, the external event function, and the capture trigger function of TAA,
enable TAA operation after the time of the sampling clock × 3 clocks has elapsed.
Remark
n = 0 to 3, 5
After reset: 00H
TANFC
R/W
TANFEN
0
TANFEN
Address: FFFFF724H
0
0
0
0
0
TANFC0
Setting of digital noise elimination
0
Does not perform digital noise elimination
1
Performs digital noise elimination
TANFC0
Digital sampling clock
0
fXX
1
fXX/4
Remarks 1.
Since sampling is performed 3 times, the noise width for reliably eliminating
noise is 2 sampling clocks.
2.
In the case of noise with a width smaller than 2 sampling clocks, an
interrupt request signal is generated if noise synchronized with the
sampling clock is input.
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A timing example of noise elimination performed by the timer AA input pin digital filter is shown Figure 7-2.
Figure 7-2. Example of Digital Noise Elimination Timing
Noise elimination clock
Input signal
Sampling
3 times
Sampling
3 times
1 clock
1 clock
2 clocks
2 clocks
3 clocks
3 clocks
Internal signal
Remark
If there are two or fewer noise elimination clocks while the TIAAn0 or TIAAn1 input signal is high
level (or low level), that input signal is eliminated as noise. If it is sampled three times or more,
the edge is detected as a valid input (n = 0 to 3, 5).
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7.5
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Operation
TAAn can perform the following operations.
Operation
Interval timer mode
External event count mode
Note 1
External trigger pulse output mode
One-shot pulse output mode
Note 2
Note 2
PWM output mode
Free-running timer mode
Pulse width measurement mode
Note 2
TAAnCTL1.TAAmEST Bit
TIAAn0 Pin
Capture/Compare
Compare Register
(Software Trigger Bit)
(External Trigger Input)
Register Setting
Write
Invalid
Invalid
Compare only
Anytime write
Invalid
Invalid
Compare only
Anytime write
Valid
Valid
Compare only
Batch write
Valid
Valid
Compare only
Anytime write
Invalid
Invalid
Compare only
Batch write
Invalid
Invalid
Switching enabled
Anytime write
Invalid
Invalid
Capture only
Not applicable
Notes 1. To use the external event count mode, specify that the valid edge of the TIAAn0 pin capture trigger input is not
detected (by clearing the TAAnIOC1.TAAnIS1 and TAAnIOC1.TAAnIS0 bits to “00”).
2. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement
mode, select the internal clock as the count clock (by clearing the TAAnCTL1.TAAnEEE bit to 0).
Remark
n = 0 to 3, 5
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(1) Anytime write and batch write
With TAAn, the TAAnCCR0 and TAAnCCR1 registers can be rewritten during timer operation (TAAnCTL0.TAAnCE
bit = 1), but the write method (anytime write, batch write) of the CCR0 and CCR1 buffer registers differs depending
on the mode.
(a) Anytime write
In this mode, data is transferred at any time from the TAAnCCR0 and TAAnCCR1 registers to the CCR0 and
CCR1 buffer registers during timer operation.
Figure 7-3. Example of Basic Anytime Write Operation Flowchart (Interval Timer Mode of TAA0)
START
Initial settings
• Set values to TAACCRn register
• Timer operation enable
(TAA0CE bit = 1)
→ Transfer values of TAA0CCRn
register to CCRn buffer
register
TAA0CCRn register rewrite
→ Transfer to CCRn buffer register
Timer operation
• Match between 16-bit counter
and CCR1 buffer registerNote
• Match between 16-bit counter
and CCR0 buffer register
• 16-bit counter clear & start
INTTAA0CC1 signal output
INTTAA0CC0 signal output
Note The 16-bit counter is not cleared upon a match between the 16-bit counter value
and the CCR1 buffer register value. It is cleared upon a match between the 16-bit
counter value and the CCR0 buffer register value.
Remark
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Figure 7-4. Example of Anytime Write Timing (Interval Timer Mode of TAA0)
TAA0CE bit = 1
D01
FFFFH
D01
D02
16-bit counter
D11
D11
D12
D12
0000H
D01
TAA0CCR0 register
CCR0 buffer register
0000H
D01
D11
TAA0CCR1 register
CCR1 buffer register
D02
0000H
D02
D12
D11
D12
INTTAA0C0 signal
INTTAA0CC1 signal
Remark
D01, D02: Set values of TAA0CCR0 register
D11, D12: Set values of TAA0CCR1 register
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(b) Batch write
In this mode, data is transferred all at once from the TAAnCCR0 and TAAnCCR1 registers to the CCR0 and
CCR1 buffer registers during timer operation. This data is transferred upon a match between the value of the
CCR0 buffer register and the value of the 16-bit counter. Transfer is enabled by writing to the TAAnCCR1
register. Whether to enable or disable the next transfer timing is controlled by writing or not writing to the
TAAnCCR1 register.
In order for the set value when the TAAnCCR0 and TAAnCCR1 registers are rewritten to become the 16-bit
counter comparison value (in other words, in order for this value to be transferred to the CCR0 and CCR1
buffer registers), it is necessary to rewrite the TAAnCCR0 register and then write to the TAAnCCR1 register
before the 16-bit counter value and the CCR0 buffer register value match. Therefore, the values of the
TAAnCCR0 and TAAnCCR1 registers are transferred to the CCR0 and CCR1 buffer registers upon a match
between the count value of the 16-bit counter and the value of the CCR0 buffer register. Thus even when
wishing only to rewrite the value of the TAAnCCR0 register, also write the same value (same as preset value of
the TAAnCCR1 register) to the TAAnCCR1 register.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Figure 7-5. Example of Basic Batch Write Operation Flowchart (PWM Output Mode of TAA0)
START
Initial settings
• Set values to TAA0CCRn register
• Enable timer operation (TAA0CE
bit = 1)
→ Transfer values of TAA0CCRn
register to CCRn buffer
register
TAA0CCR0 register rewrite
TAA0CCR1 register rewrite
Timer operation
• Match between 16-bit counter
and CCR1 buffer registerNote
• Match between 16-bit counter
and CCR0 buffer register
• 16-bit counter clear & start
• Transfer of values of TAA0CCRn
register to CCRn buffer register
Batch write enable
INTTAA0CC1 signal output
INTTAA0CC0 signal output
Note The 16-bit counter is not cleared upon a match between the 16-bit counter value and the CCR1
buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0
buffer register value.
Caution
Writing to the TAA0CCR1 register includes enabling of batch write. Thus, rewrite the
TAA0CCR1 register after rewriting the TAA0CCR0 register.
Remark
n = 0, 1
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Figure 7-6. Timing of Batch Write (Interval Timer Mode of TAA0)
TAA0CE bit = 1
D01
FFFFH
D02
D11
D12
16-bit counter
D03
D02
D12
D12
D12
0000H
D01
TAA0CCR0 register
CCR0 buffer register
0000H
TAA0CCR1 register
CCR1 buffer register
D02
D01
D11
0000H
D03
D02
Note 1
Note 2 D12
D11
D12
Note 1
Note 1
Same value write
D12
Note 3
D03
D12
Note 1
INTTAA0CC0 signal
INTTAA0CC1 signal
TOAA00 pin output
TOAA01 pin output
Notes 1. Because the TAA0CCR1 register was not rewritten, D03 is not transferred.
2. Because the TAA0CCR1 register has been written (D12), data is transferred to the CCR1
buffer register upon a match between the value of the 16-bit counter and the value of the
TAA0CCR0 register (D01).
3. Because the TAA0CCR1 register has been written (D12), data is transferred to the CCR1
buffer register upon a match between the value of the 16-bit counter and the value of the
TAA0CCR0 register (D02).
Remark
D01, D02, D03: Set values of TAA0CCR0 register
D11, D12:
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Interval timer mode (TAAmMD2 to TAAmMD0 bits = 000)
In the interval timer mode, an interrupt request signal (INTTAAnCC0) is generated at any interval if the
TAAnCTL0.TAAnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOAAn0
pin.
Usually, the TAAnCCR1 register is not used in the interval timer mode.
Figure 7-7. Configuration of Interval Timer
Clear
Count clock
selection
Output
controller
16-bit counter
Match signal
TAAnCE bit
TOAAm0 pin
INTTAAnCC0 signal
CCR0 buffer register
TAAnCCR0 register
Remark
m = 0 to 3, 5
n = 0 to 5
Figure 7-8. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
D0
D0
D0
D0
0000H
TAAnCE bit
TAAnCCR0 register
D0
TOAAm0 pin output
INTTAAnCC0 signal
Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1)
Remark
m = 0 to 3, 5
n = 0 to 5
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When the TAAnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
with the count clock, and the counter starts counting. At this time, the output of the TOAAn0 pin is inverted. Additionally,
the set value of the TAAnCCR0 register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, the output of the TOAAn0 pin is inverted, and a compare match interrupt request signal (INTTAAnCC0) is
generated.
The interval can be calculated by the following expression.
Interval = (Set value of TAAnCCR0 register + 1) × Count clock cycle
Remark
m = 0 to 3, 5
n = 0 to 5
Figure 7-9. Register Settings for Interval Timer Mode Operation (1/2)
(a) TAAn control register 0 (TAAnCTL0)
TAAnCE
TAAnCTL0
TAAnCKS2 TAAnCKS1 TAAnCKS0
0/1
0
0
0
0
0/1
0/1
0/1
Select count clock
0: Stops counting
1: Enables counting
(b) TAAn control register 1 (TAAnCTL1)
TAmEST TAAmEEE
TAAnCTL1
0
0
0/1Note
TAAnMD2 TAAnMD1 TAAnMD0
0
0
0
0
0
0, 0, 0:
Interval timer mode
0: Operates on count clock
selected by TAAmCKS0
to TAAmCKS2 bits
1: Counts with external
event count input signal
Note
This bit can be set to 1 only when the interrupt request signals (INTTAAmCC0 and INTTAAmCC1)
are masked by the interrupt mask flags (TAAmCCMK0 and TAAmCCMK1) and timer output
(TOAAm1) is performed. However, set the TAAmCCR0 and TAAmCCR1 registers to the same value
(see 7.5.1 (2) (d) Operation of TAAnCCR1 register).
Remark
m = 0 to 3, 5
n = 0 to 5
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Figure 7-9. Register Settings for Interval Timer Mode Operation (2/2)
(c) TAAm I/O control register 0 (TAAmIOC0)
TAAmOL1 TAAmOE1TAAmOL0 TAAmOE0
TAAmIOC0
0
0
0
0
0/1
0/1
0/1
0/1
0: Disables TOAAm0 pin output
1: Enables TOAAm0 pin output
Setting of output level with
operation of TOAAm0 pin disabled
0: Low level
1: High level
0: Disables TOAAm1 pin output
1: Enables TOAAm1 pin output
Setting of output level with
operation of TOAAm1 pin disabled
0: Low level
1: High level
(d) TAAn counter read buffer register (TAAnCNT)
By reading the TAAnCNT register, the count value of the 16-bit counter can be read.
(e) TAAn capture/compare register 0 (TAAnCCR0)
If the TAAnCCR0 register is set to D0, the interval is as follows.
Interval = (D0 + 1) × Count clock cycle
(f) TAAn capture/compare register 1 (TAAnCCR1)
Usually, the TAAnCCR1 register is not used in the interval timer mode. However, the set value of
the TAAnCCR1 register is transferred to the CCR1 buffer register. A compare match interrupt
request signal (INTTAAnCC1) is generated when the count value of the 16-bit counter matches
the value of the CCR1 buffer register.
Therefore, mask the interrupt request by using the corresponding interrupt mask flag
(TAAnCCMK1).
Remarks 1.
TAAm I/O control register 1 (TAAmIOC1), TAAm I/O control register 2 (TAAmIOC2),
and TAAm option register 0 (TAAmOPT0) are not used in the interval timer mode.
2.
m = 0 to 3, 5
n = 0 to 5
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(1) Interval timer mode operation flow
Figure 7-10. Software Processing Flow in Interval Timer Mode
FFFFH
D0
16-bit counter
D0
D0
0000H
TAAnCE bit
TAAnCCR0 register
D0
TOAAm0 pin output
INTTAAnCC0 signal
Count operation start flow
START
Register initial setting
TAAnCTL0 register
(TAAnCKS0 to TAAnCKS2 bits),
TAAnCTL1 register,
TAAmIOC0 register,
TAAnCCR0 register
TAAnCE bit = 1
Initial setting of these registers is performed
before setting the TAAnCE bit to 1.
The TAAnCKS0 to TAAnCKS2 bits can be
set at the same time when counting has
been started (TAAnCE bit = 1).
Count operation stop flow
TAAnCE bit = 0
The counter is initialized and counting is
stopped by clearing the TAAnCE bit to 0.
STOP
Remark
m = 0 to 3, 5
n = 0 to 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(2) Interval timer mode operation timing
(a) Operation if TAAnCCR0 register is set to 0000H
If the TAAnCCR0 register is set to 0000H, the INTTAAnCC0 signal is generated at each count clock
subsequent to the first count clock, and the output of the TOAAm0 pin is inverted.
The value of the 16-bit counter is always 0000H.
Count clock
16-bit counter
FFFFH
0000H
0000H
0000H
0000H
TAAnCE bit
TAAnCCR0 register
0000H
TOAAm0 pin output
INTTAAnCC0 signal
Interval time
Count clock cycle
Remark
Interval time
Count clock cycle
m = 0 to 3, 5
n = 0 to 5
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(b) Operation if TAAnCCR0 register is set to FFFFH
If the TAAnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to
0000H in synchronization with the next count-up timing. The INTTAAnCC0 signal is generated and the output
of the TOAAm0 pin is inverted. At this time, an overflow interrupt request signal (INTTAAnOV) is not generated,
nor is the overflow flag (TAAmOPT0.TAAmOVF bit) set to 1.
FFFFH
16-bit counter
0000H
TAAnCE bit
TAAnCCR0 register
FFFFH
TOAAm0 pin output
INTTAAnCC0 signal
Interval time
Interval time
Interval time
10000H ×
10000H ×
10000H ×
count clock cycle count clock cycle count clock cycle
Remark
m = 0 to 3, 5
n = 0 to 5
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(c) Notes on rewriting TAAnCCR0 register
To change the value of the TAAnCCR0 register to a smaller value, stop counting once and then change the set
value.
If the value of the TAAnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
D1
D1
16-bit counter
D2
D2
D2
0000H
TAAnCE bit
D1
TAAnCCR0 register
TAAnOL0 bit
D2
L
TOAAm0 pin output
INTTAAnCC0 signal
Interval time (1)
Remarks 1.
Interval time (NG)
Interval
time (2)
Interval time (1): (D1 + 1) × Count clock cycle
Interval time (NG):
(10000H + D2 + 1) × Count clock cycle
Interval time (2): (D2 + 1) × Count clock cycle
2.
m = 0 to 3, 5
n = 0 to 5
If the value of the TAAnCCR0 register is changed from D1 to D2 while the count value is greater than D2 but
less than D1, the count value is transferred to the CCR0 buffer register as soon as the TAAnCCR0 register has
been rewritten. Consequently, the value of the 16-bit counter that is compared is D2.
Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows,
and then counts up again from 0000H.
When the count value matches D2, the INTTAAnCC0 signal is
generated and the output of the TOAAm0 pin is inverted.
Therefore, the INTTAAnCC0 signal may not be generated at the interval time “(D1 + 1) × Count clock cycle” or
“(D2 + 1) × Count clock cycle” as originally expected, but may be generated at an interval of “(10000H + D2 + 1)
× Count clock period”.
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(d) Operation of TAAnCCR1 register
Figure 7-11. Configuration of TAAnCCR1 Register
TAAnCCR1 register
CCR1 buffer register
Output
controller
Match signal
TOAAn1 pin
INTTAAnCC1 signal
Clear
Count clock
selection
16-bit counter
Match signal
TAAnCE bit
Output
controller
TOAAn0 pin
INTTAAnCC0 signal
CCR0 buffer register
TAAnCCR0 register
Remark
n = 0 to 3, 5
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If the set value of the TAAnCCR1 register is less than the set value of the TAAnCCR0 register, the
INTTAAnCC1 signal is generated once per cycle. At the same time, the output of the TOAAn1 pin is inverted.
The TOAAn1 pin outputs a square wave with the same cycle as that output by the TOAAn0 pin.
Figure 7-12. Timing Chart When D01 ≥ D11
FFFFH
D01
16-bit counter
D11
D01
D11
D01
D11
D01
D11
0000H
TAAnCE bit
TAAnCCR0 register
D01
TOAAn0 pin output
INTTAAnCC0 signal
TAAnCCR1 register
D11
TOAAn1 pin output
INTTAAnCC1 signal
Remark
n = 0 to 3, 5
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If the set value of the TAAnCCR1 register is greater than the set value of the TAAnCCR0 register, the count
value of the 16-bit counter does not match the value of the TAAnCCR1 register.
Consequently, the
INTTAAnCC1 signal is not generated, nor is the output of the TOAAn1 pin changed.
Figure 7-13. Timing Chart When D01 < D11
FFFFH
D01
D01
D01
D01
16-bit counter
0000H
TAAnCE bit
TAAnCCR0 register
D01
TOAAn0 pin output
INTTAAnCC0 signal
D11
TAAnCCR1 register
TOAAn1 pin output
INTTAAnCC1 signal
Remark
L
n = 0 to 3, 5
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7.5.2
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
External event count mode (TAAnMD2 to TAAnMD0 bits = 001)
In the external event count mode, the valid edge of the external event count input is counted when the
TAAnCTL0.TAAnCE bit is set to 1, and an interrupt request signal (INTTAAnCC0) is generated each time the specified
number of edges have been counted. The TOAAn0 pin cannot be used.
Usually, the TAAnCCR1 register is not used in the external event count mode.
Figure 7-14. Configuration in External Event Count Mode
Clear
TIAAn0 pin
(external event
count input)
Edge
detector
16-bit counter
Match signal
TAAnCE bit
INTTAAnCC0 signal
CCR0 buffer register
TAAnCCR0 register
Remark
n = 0 to 3, 5
Figure 7-15. Basic Timing in External Event Count Mode
FFFFH
D0
16-bit counter
D0
D0
0000H
16-bit counter
TAAnCE bit
External event
count input
(TIAAn0 pin input)
TAAnCCR0 register
TAAnCCR0 register
D0
D0 − 1
D0
0000
0001
D0
INTTAAnCC0 signal
INTTAAnCC0 signal
External
event
count
interval
(D0 + 1)
Remarks 1.
External
event
count
interval
(D0 + 1)
External
event
count
interval
(D0 + 1)
This figure shows the basic timing when the rising edge is specified as the valid edge
of the external event count input.
2.
n = 0 to 3, 5
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When the TAAnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts
each time the valid edge of external event count input is detected. Additionally, the set value of the TAAnCCR0 register is
transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, and a compare match interrupt request signal (INTTAAnCC0) is generated.
The INTTAAnCC0 signal is generated each time the valid edge of the external event count input has been detected (set
value of TAAnCCR0 register + 1) times.
Figure 7-16. Register Setting for Operation in External Event Count Mode (1/2)
(a) TAAn control register 0 (TAAnCTL0)
TAAnCE
TAAnCTL0
0/1
TAAnCKS2 TAAnCKS1 TAAnCKS0
0
0
0
0
0
0
0
0: Stops counting
1: Enables counting
(b) TAAn control register 1 (TAAnCTL1)
TAAnEST TAAnEEE
TAAnCTL1
0
0
0
TAAnMD2 TAAnMD1 TAAnMD0
0
0
0
0
1
0, 0, 1:
External event count mode
(c) TAAn I/O control register 0 (TAAnIOC0)
TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0
TAAnIOC0
0
0
0
0
0
0
0
0
0: Disables TOAAn0 pin output
0: Disables TOAAn1 pin output
(d) TAAn I/O control register 2 (TAAnIOC2)
TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0
TAAnIOC2
0
0
0
0
0/1
0/1
0
0
Select valid edge of
external event count input
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Figure 7-16. Register Setting for Operation in External Event Count Mode (2/2)
(e) TAAn counter read buffer register (TAAnCNT)
The count value of the 16-bit counter can be read by reading the TAAnCNT register.
(f) TAAn capture/compare register 0 (TAAnCCR0)
If D0 is set to the TAAnCCR0 register, the counter is cleared and a compare match interrupt
request signal (INTTAAnCC0) is generated when the number of external event counts reaches
(D0 + 1).
(g) TAAn capture/compare register 1 (TAAnCCR1)
Usually, the TAAnCCR1 register is not used in the external event count mode. However, the set
value of the TAAnCCR1 register is transferred to the CCR1 buffer register. When the count value
of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt
request signal (INTTAAnCC1) is generated.
Therefore, mask the interrupt signal by using the interrupt mask flag (TAAnCCMK1).
Caution
When an external clock is used as the count clock, the external clock can be input only from
the TIAAn0 pin. At this time, set the TAAnIOC1.TAAnIS1 and TAAnIOC1.TAAnIS0 bits to 00
(capture trigger input (TIAAn0 pin): no edge detection).
Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are
not used in the external event count mode.
2. n = 0 to 3, 5
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(1) External event count mode operation flow
Figure 7-17. Flow of Software Processing in External Event Count Mode
FFFFH
D0
16-bit counter
D0
D0
0000H
TAAnCE bit
TAAnCCR0 register
D0
INTTAAnCC0 signal
Count operation start flow
START
Register initial setting
TAAnCTL0 register
(TAAnCKS0 to TAAnCKS2 bits),
TAAnCTL1 register,
TAAnIOC0 register,
TAAnIOC2 register,
TAAnCCR0 register
TAAnCE bit = 1
Initial setting of these registers
is performed before setting the
TAAnCE bit to 1.
The TAAnCKS0 to TAAnCKS2 bits can
be set at the same time when counting
has been started (TAAnCE bit = 1).
Count operation stop flow
TAAnCE bit = 0
The counter is initialized and counting
is stopped by clearing the TAAnCE bit to 0.
STOP
Remark
n = 0 to 3, 5
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(2) Operation timing in external event count mode
Cautions 1. In the external event count mode, do not set the TAAnCCR0 register to 0000H.
2. In the external event count mode, use of the timer output is disabled. If performing timer
output using external event count input, set the interval timer mode, and select the operation
of the count clock to be enabled by the external event count input (TAAnCTL1.TAAnMD2 to
TAAnCTL1.TAAnMD0 bits = 000, TAAnCTL1.TAAnEEE bit = 1).
(a) Operation if TAAnCCR0 register is set to FFFFH
If the TAAnCCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the
external event count signal has been detected. The 16-bit counter is cleared to 0000H in synchronization with
the next count-up timing, and the INTTAAnCC0 signal is generated. At this time, the TAAnOPT0.TAAnOVF bit
is not set.
FFFFH
16-bit counter
0000H
TAAnCE bit
TAAnCCR0 register
FFFFH
INTTAAnCC0 signal
External event
count signal
interval
Remark
External event
count signal
interval
External event
count signal
interval
n = 0 to 3, 5
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(b) Notes on rewriting the TAAnCCR0 register
To change the value of the TAAnCCR0 register to a smaller value, stop counting once and then change the set
value.
If the value of the TAAnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
D1
16-bit counter
D1
D2
D2
D2
0000H
TAAnCE bit
D1
TAAnCCR0 register
D2
INTTAAnCC0 signal
External event
count signal
interval (1)
(D1 + 1)
Remark
External event count signal
interval (NG)
(10000H + D2 + 1)
External event
count signal
interval (2)
(D2 + 1)
n = 0 to 3, 5
If the value of the TAAnCCR0 register is changed from D1 to D2 while the count value is greater than D2 but
less than D1, the count value is transferred to the CCR0 buffer register as soon as the TAAnCCR0 register has
been rewritten. Consequently, the value that is compared with the 16-bit counter is D2.
Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows,
and then counts up again from 0000H.
When the count value matches D2, the INTTAAnCC0 signal is
generated.
Therefore, the INTTAAnCC0 signal may not be generated at the valid edge count of “(D1 + 1) times” or “(D2 + 1)
times” as originally expected, but may be generated at the valid edge count of “(10000H + D2 + 1) times”.
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(c) Operation of TAAnCCR1 register
Figure 7-18. Configuration of TAAnCCR1 Register
TAAnCCR1 register
CCR1 buffer register
Match signal
INTTAAnCC1 signal
Clear
Edge
detector
TIAAn0 pin
16-bit counter
Match signal
TAAnCE bit
INTTAAnCC0 signal
CCR0 buffer register
TAAnCCR0 register
Remark
n = 0 to 3, 5
If the set value of the TAAnCCR1 register is smaller than the set value of the TAAnCCR0 register, the
INTTAAnCC1 signal is generated once per cycle.
Figure 7-19. Timing Chart When D01 ≥ D11
FFFFH
D01
16-bit counter
D11
D01
D11
D01
D11
D01
D11
0000H
TAAnCE bit
TAAnCCR0 register
D01
INTTAAnCC0 signal
TAAnCCR1 register
D11
INTTAAnCC1 signal
Remark
n = 0 to 3, 5
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If the set value of the TAAnCCR1 register is greater than the set value of the TAAnCCR0 register, the
INTTAAnCC1 signal is not generated because the count value of the 16-bit counter and the value of the
TAAnCCR1 register do not match.
Figure 7-20. Timing Chart When D01 < D11
FFFFH
D01
D01
D01
D01
16-bit counter
0000H
TAAnCE bit
TAAnCCR0 register
D01
INTTAAnCC0 signal
D11
TAAnCCR1 register
INTTAAnCC1 signal
Remark
L
n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
External trigger pulse output mode (TAAnMD2 to TAAnMD0 bits = 010)
In the external trigger pulse output mode, 16-bit timer/event counter AA waits for a trigger when the TAAnCTL0.TAAnCE
bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter AA starts
counting, and outputs a PWM waveform from the TOAAn1 pin.
Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software
trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOAAn0 pin.
Figure 7-21. Configuration in External Trigger Pulse Output Mode
TAAnCCR1 register
Edge
detector
TIAAn0 pin
Transfer
CCR1 buffer register
Software trigger
generation
Output
S
controller
R (RS-FF)
Match signal
TOAAn1 pin
INTTAAnCC1 signal
Clear
Count
clock
selection
Count
start
control
16-bit counter
Output
controller
Match signal
TAAnCE bit
TOAAn0 pin
INTTAAnCC0 signal
CCR0 buffer register
Transfer
TAAnCCR0 register
Remark
n = 0 to 3, 5
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Figure 7-22. Basic Timing in External Trigger Pulse Output Mode
FFFFH
D0
D1
16-bit counter
D0
D0
D1
D1
D0
D1
0000H
TAAnCE bit
External trigger input
(TIAAn0 pin input)
D0
TAAnCCR0 register
INTTAAnCC0 signal
TOAAn0 pin output
(only when software
trigger is used)
D1
TAAnCCR1 register
INTTAAnCC1 signal
TOAAn1 pin output
Wait Active level
for width (D1)
trigger
Cycle (D0 + 1)
Active level
width (D1)
Cycle (D0 + 1)
Active level
width (D1)
Cycle (D0 + 1)
16-bit timer/event counter AA waits for a trigger when the TAAnCE bit is set to 1. When the trigger is generated, the 16bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the
TOAAn1 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted.
(The output of the TOAAn0 pin is inverted. The TOAAn1 pin outputs a high level regardless of the status (high/low) when a
trigger occurs.)
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TAAnCCR1 register) × Count clock cycle
Cycle = (Set value of TAAnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TAAnCCR1 register)/(Set value of TAAnCCR0 register + 1)
The compare match request signal INTTAAnCC0 is generated the next time the 16-bit counter counts after its count
value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H at the same time. The
compare match interrupt request signal INTTAAnCC1 is generated when the count value of the 16-bit counter matches the
value of the CCR1 buffer register.
The value set to the TAAnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H.
The valid edge of an external trigger input signal, or setting the software trigger (TAAnCTL1.TAAnEST bit) to 1 is used
as the trigger.
Remark
n = 0 to 3, 5
m = 0, 1
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Figure 7-23. Setting of Registers in External Trigger Pulse Output Mode (1/2)
(a) TAAn control register 0 (TAAnCTL0)
TAAnCE
TAAnCTL0
TAAnCKS2 TAAnCKS1 TAAnCKS0
0/1
0
0
0
0
0/1
0/1
0/1
Select count clock
0: Stops counting
1: Enables counting
(b) TAAn control register 1 (TAAnCTL1)
TAAnEST TAAnEEE
TAAnCTL1
0
0/1
TAAnMD2 TAAnMD1 TAAnMD0
0
0
0
0
1
0
0, 1, 0:
External trigger pulse
output mode
Generates software trigger
when 1 is written
(c) TAAn I/O control register 0 (TAAnIOC0)
TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0
TAAnIOC0
0
0
0
0
0/1
0/1
0/1Note
0/1Note
0: Disables TOAAn0 pin output
1: Enables TOAAn0 pin output
Sets output level while operation
of TOAAn0 pin is disabled
0: Low level
1: High level
0: Disables TOAAn1 pin output
1: Enables TOAAn1 pin output
Specifies active level of
TOAAn1 pin output
0: Active-high
1: Active-low
• When TAAnOL1 bit = 0
• When TAAnOL1 bit = 1
16-bit counter
16-bit counter
TOAAn1 pin output
TOAAn1 pin output
Note
Clear this bit to 0 when the TOAAn0 pin is not used in the external trigger pulse output
mode.
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Figure 7-23. Setting of Registers in External Trigger Pulse Output Mode (2/2)
(d) TAAn I/O control register 2 (TAAnIOC2)
TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0
TAAnIOC2
0
0
0
0
0
0
0/1
0/1
Select valid edge of
external trigger input
(e) TAAn counter read buffer register (TAAnCNT)
The value of the 16-bit counter can be read by reading the TAAnCNT register.
(f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1)
If D0 is set to the TAAnCCR0 register and D1 to the TAAnCCR1 register, the cycle and active level of
the PWM waveform are as follows.
Cycle = (D0 + 1) × Count clock cycle
Active level width = D1 × Count clock cycle
Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are
not used in the external trigger pulse output mode.
2. n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(1) Operation flow in external trigger pulse output mode
Figure 7-24. Software Processing Flow in External Trigger Pulse Output Mode (1/2)
FFFFH
D01
16-bit counter
D00
D10
D00
D10
D01
D01
D11
D10
D11
D00
D10
0000H
TAAnCE bit
External trigger input
(TIAAn0 pin input)
TAAnCCR0 register
D00
CCR0 buffer register
D01
D00
D00
D01
D00
INTTAAnCC0 signal
TOAAn0 pin output
(only when software
trigger is used)
D10
TAAnCCR1 register
D10
D11
D10
CCR1 buffer register
D10
D10
D11
D10
INTTAAnCC1 signal
TOAAn1 pin output
Remark
n = 0 to 3, 5
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Figure 7-24. Software Processing Flow in External Trigger Pulse Output Mode (2/2)
Count operation start flow
TAAnCCR0, TAAnCCR1 register
setting change flow
START
Setting of TAAnCCR1 register
Register initial setting
TAAnCTL0 register
(TAAnCKS0 to TAAnCKS2 bits),
TAAnCTL1 register,
TAAnIOC0 register,
TAAnIOC2 register,
TAAnCCR0 register,
TAAnCCR1 register
TAAnCE bit = 1
Initial setting of these
registers is performed
before setting the
TAAnCE bit to 1.
Only writing of the TAAnCCR1
register must be performed when
the set duty factor is changed.
When the counter is cleared after
setting, the value of the
TAAnCCRm register is transferred
to the CCRm buffer register.
TAAnCCR0, TAAnCCR1 register
setting change flow
The TAAnCKS0 to
TAAnCKS2 bits can be
set at the same time
when counting is enabled
(TAAnCE bit = 1).
Trigger wait status
Setting of TAAnCCR0 register
When the counter is
cleared after setting,
the values of the TAAnCCRm
register are transferred to
the CCRm buffer register
in a batch.
Setting of TAAnCCR1 register
TAAnCCR0 and TAAnCCR1 register
setting change flow
Setting of TAAnCCR0 register
Setting of TAAnCCR1 register
Remark
Count operation stop flow
TAAnCCR1 register write
processing is necessary
only when the set
cycle is changed.
TAAnCE bit = 0
When the counter is
cleared after setting,
the values of the
TAAnCCRm register are
transferred to the CCRm
buffer register in a batch.
STOP
Counting is stopped.
n = 0 to 3, 5
m = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(2) External trigger pulse output mode operation timing
(a) Note on changing pulse width during operation
To change the PWM waveform while the counter is operating, write the TAAnCCR1 register last.
Rewrite the TAAnCCRm register after writing the TAAnCCR1 register after the INTTAAnCC0 signal is detected.
FFFFH
D01
16-bit counter
D00
D10
D00
D10
D00
D10
D11
D01
D11
0000H
TAAnCE bit
External trigger input
(TIAAn0 pin input)
TAAnCCR0 register
CCR0 buffer register
D00
D01
D00
D01
INTTAAnCC0 signal
TOAAn0 pin output
(only when software
trigger is used)
TAAnCCR1 register
CCR1 buffer register
D10
D10
D11
D11
INTTAAnCC1 signal
TOAAn1 pin output
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In order to transfer data from the TAAnCCRm register to the CCRm buffer register, the TAAnCCR1 register
must be written.
To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the
TAAnCCR0 register and then set the active level width to the TAAnCCR1 register.
To change only the cycle of the PWM waveform, first set the cycle to the TAAnCCR0 register, and then write
the same value to the TAAnCCR1 register.
To change only the active level width (duty factor) of the PWM waveform, only the TAAnCCR1 register has to
be set.
After data is written to the TAAnCCR1 register, the value written to the TAAnCCRm register is transferred to the
CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared
with the 16-bit counter.
To write the TAAnCCR0 or TAAnCCR1 register again after writing the TAAnCCR1 register once, do so after the
INTTAAnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined
because the timing of transferring data from the TAAnCCRm register to the CCRm buffer register conflicts with
writing the TAAnCCRm register.
Remark
n = 0 to 3, 5
m = 0, 1
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(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TAAnCCR1 register to 0000H. If the set value of the TAAnCCR0 register is
FFFFH, the INTTAAnCC1 signal is generated periodically.
Count clock
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0001
D0 − 1
D0
0000
TAAnCE bit
TAAnCCR0 register
D0
D0
D0
TAAnCCR1 register
0000H
0000H
0000H
INTTAAnCC0 signal
INTTAAnCC1 signal
TOAAn1 pin output
Remark
n = 0 to 3, 5
To output a 100% waveform, set a value of (set value of TAAnCCR0 register + 1) to the TAAnCCR1 register. If
the set value of the TAAnCCR0 register is FFFFH, 100% output cannot be produced.
Count clock
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0001
D0 − 1
D0
0000
TAAnCE bit
TAAnCCR0 register
D0
D0
D0
TAAnCCR1 register
D0 + 1
D0 + 1
D0 + 1
INTTAAnCC0 signal
INTTAAnCC1 signal
TOAAn1 pin output
Remark
n = 0 to 3, 5
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(c) Conflict between trigger detection and match with TAAnCCR1 register
If the trigger is detected immediately after the INTTAAnCC1 signal is generated, the 16-bit counter is cleared to
0000H at the same time, the output signal of the TOAAn1 pin is asserted, and the counter continues counting.
Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter
FFFF
D1 − 1
0000
0000
External trigger input
(TIAAn0 pin input)
D1
TAAnCCR1 register
INTTAAnCC1 signal
TOAAn1 pin output
Shortened
Remark
n = 0 to 3, 5
If the trigger is detected immediately before the INTTAAnCC1 signal is generated, the INTTAAnCC1 signal is
not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the
TOAAn1 pin remains active. Consequently, the active period of the PWM waveform is extended.
16-bit counter
FFFF
0000
D1 − 2
0000
0001
D1 − 1
D1
External trigger input
(TIAAn0 pin input)
TAAnCCR1 register
D1
INTTAAnCC1 signal
TOAAn1 pin output
Extended
Remark
n = 0 to 3, 5
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(d) Conflict between trigger detection and match with TAAnCCR0 register
If the trigger is detected immediately after the INTTAAnCC0 signal is generated, the 16-bit counter is cleared to
0000H again and continues counting up. Therefore, the active period of the TOAAn1 pin is extended by the
time from generation of the INTTAAnCC0 signal to trigger detection.
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0000
External trigger input
(TIAAn0 pin input)
D0
TAAnCCR0 register
INTTAAnCC0 signal
TOAAn1 pin output
Extended
Remark
n = 0 to 3, 5
If the trigger is detected immediately before the INTTAAnCC0 signal is generated, the INTTAAnCC0 signal is
not generated. The 16-bit counter is cleared to 0000H, the TOAAn1 pin is asserted, and the counter continues
counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0001
External trigger input
(TIAAn0 pin input)
TAAnCCR0 register
D0
INTTAAnCC0 signal
TOAAn1 pin output
Shortened
Remark
n = 0 to 3, 5
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(e) Generation timing of compare match interrupt request signal (INTTAAnCC1)
The timing of generation of the INTTAAnCC1 signal in the external trigger pulse output mode differs from the
timing of other INTTAAnCC1 signals; the INTTAAnCC1 signal in the external trigger pulse output mode is
generated when the count value of the 16-bit counter matches the value of the TAAnCCR1 register.
Count clock
16-bit counter
TAAnCCR1 register
D1 − 2
D1 − 1
D1
D1 + 1
D1 + 2
D1
TOAAn1 pin output
INTTAAnCC1 signal
Remark
n = 0 to 3, 5
Usually, the INTTAAnCC1 signal is generated in synchronization with the next count-up, after the count value of
the 16-bit counter matches the value of the TAAnCCR1 register.
In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing
is changed to match the timing of changing the output signal of the TOAAn1 pin.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
One-shot pulse output mode (TAAnMD2 to TAAnMD0 bits = 011)
In the one-shot pulse output mode, 16-bit timer/event counter AA waits for a trigger when the TAAnCTL0.TAAnCE bit is
set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter AA starts counting, and
outputs a one-shot pulse from the TOAAn1 pin.
Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software trigger
is used, the TOAAn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the
counter is stopped (waiting for a trigger).
Figure 7-25. Configuration in One-Shot Pulse Output Mode
TAAnCCR1 register
Edge
detector
TIAAn0 pin
Transfer
Output
S
controller
R (RS-FF)
CCR1 buffer register
Software trigger
generation
Match signal
TOAAn1 pin
INTTAAnCC1 signal
Clear
Count clock
selection
Count start
control
Output
S
controller
R (RS-FF)
16-bit counter
Match signal
TAAnCE bit
TOAAn0 pin
INTTAAnCC0 signal
CCR0 buffer register
Transfer
TAAnCCR0 register
Remark
n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Figure 7-26. Basic Timing in One-Shot Pulse Output Mode
FFFFH
D0
16-bit counter
D1
D0
D1
D0
D1
0000H
TAAnCE bit
External trigger input
(TIAAn0 pin input)
D0
TAAnCCR0 register
INTTAAnCC0 signal
TOAAn0 pin output
(only when software
trigger is used)
TAAnCCR1 register
D1
INTTAAnCC1 signal
TOAAn1 pin output
Delay
(D1)
Active
level width
(D0 − D1 + 1)
Delay
(D1)
Delay
Active
level width
(D1)
(D0 − D1 + 1)
Active
level width
(D0 − D1 + 1)
When the TAAnCE bit is set to 1, 16-bit timer/event counter AA waits for a trigger. When the trigger is generated, the
16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOAAn1 pin. After
the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is
generated again while the one-shot pulse is being output, it is ignored.
The output delay period and active level width of the one-shot pulse can be calculated as follows.
Output delay period = (Set value of TAAnCCR1 register) × Count clock cycle
Active level width = (Set value of TAAnCCR0 register − Set value of TAAnCCR1 register + 1) × Count clock cycle
The compare match interrupt request signal INTTAAnCC0 is generated when the 16-bit counter counts after its count
value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTAAnCC1 is
generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register.
The valid edge of an external trigger input or setting the software trigger (TAAnCTL1.TAAnEST bit) to 1 is used as the
trigger.
Remark
n = 0 to 3, 5
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Figure 7-27. Register Setting for Operation in One-Shot Pulse Output Mode (1/2)
(a) TAAn control register 0 (TAAnCTL0)
TAAnCE
TAAnCTL0
TAAnCKS2 TAAnCKS1 TAAnCKS0
0/1
0
0
0
0
0/1
0/1
0/1
Select count clock
0: Stops counting
1: Enables counting
(b) TAAn control register 1 (TAAnCTL1)
TAAnEST TAAnEEE
TAAnCTL1
0
0/1
0
TAAnMD2 TAAnMD1 TAAnMD0
0
0
0
1
1
0, 1, 1:
One-shot pulse output mode
Generates software trigger
when 1 is written
(c) TAAn I/O control register 0 (TAAnIOC0)
TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0
TAAnIOC0
0
0
0
0
0/1
0/1
0/1Note
0/1Note
0: Disables TOAAn0 pin output
1: Enables TOAAn0 pin output
Sets output level while operation
of TOAAn0 pin is disabled
0: Low level
1: High level
0: Disables TOAAn1 pin output
1: Enables TOAAn1 pin output
Specifies active level of
TOAAn1 pin output
0: Active-high
1: Active-low
• When TAAnOL1 bit = 0
• When TAAnOL1 bit = 1
16-bit counter
16-bit counter
TOAAn1 pin output
TOAAn1 pin output
Note Clear this bit to 0 when the TOAAn0 pin is not used in the one-shot pulse output mode.
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Figure 7-27. Register Setting for Operation in One-Shot Pulse Output Mode (2/2)
(d) TAAn I/O control register 2 (TAAnIOC2)
TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0
TAAnIOC2
0
0
0
0
0
0
0/1
0/1
Select valid edge of
external trigger input
(e) TAAn counter read buffer register (TAAnCNT)
The value of the 16-bit counter can be read by reading the TAAnCNT register.
(f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1)
If D0 is set to the TAAnCCR0 register and D1 to the TAAnCCR1 register, the active level width and output
delay period of the one-shot pulse are as follows.
Active level width = (D0 − D1 + 1) × Count clock cycle
Output delay period = (D1) × Count clock cycle
Caution
One-shot pulses are not output even in the one-shot pulse output mode, if the set
value of the TAAnCCR1 register is greater than the set value of the TAAnCCR0 register.
Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are not
used in the one-shot pulse output mode.
2. n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(1) Operation flow in one-shot pulse output mode
Figure 7-28. Software Processing Flow in One-Shot Pulse Output Mode
FFFFH
D00
D01
16-bit counter
D10
D11
0000H
TAAnCE bit
External trigger input
(TIAAn0 pin input)
TAAnCCR0 register
D00
D01
D10
D11
INTTAAnCC0 signal
TAAnCCR1 register
INTTAAnCC1 signal
TOAAn1 pin output
Count operation start flow
TAAnCCR0, TAAnCCR1 register setting change flow
START
Setting of TAAnCCR0,
TAAnCCR1 registers
Register initial setting
TAAnCTL0 register
(TAAnCKS0 to TAAnCKS2 bits),
TAAnCTL1 register,
TAAnIOC0 register,
TAAnIOC2 register,
TAAnCCR0 register,
TAAnCCR1 register
TAAnCE bit = 1
Remark
Initial setting of these
registers is performed
before setting the
TAAnCE bit to 1.
As rewriting the
TAAnCCRm register
immediately forwards
to the CCRm buffer
register, rewriting
immediately after
the generation of the
INTTAAnCCR0 signal
is recommended.
Count operation stop flow
The TAAnCKS0 to
TAAnCKS2 bits can be
set at the same time
when counting has been
started (TAAnCE bit = 1).
Trigger wait status
TAAnCE bit = 0
Count operation is
stopped
STOP
n = 0 to 3, 5
m = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(2) Operation timing in one-shot pulse output mode
(a) Note on rewriting TAAnCCRm register
To change the set value of the TAAnCCRm register to a smaller value, stop counting once, and then change
the set value.
If the value of the TAAnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
D00
16-bit counter
D00
D10
D10
D00
D10
D01
D11
0000H
TAAnCE bit
External trigger input
(TIAAn0 pin input)
D00
TAAnCCR0 register
D01
INTTAAnCC0 signal
TOAAn0 pin output
(only when software
trigger is used)
TAAnCCR1 register
D10
D11
INTTAAnCC1 signal
TOAAn1 pin output
Delay
(D10)
Active level width
(D00 − D10 + 1)
Delay
(D10)
Active level width
(D00 − D10 + 1)
Delay
(10000H + D11)
Active level width
(D01 − D11 + 1)
When the TAAnCCR0 register is rewritten from D00 to D01 and the TAAnCCR1 register from D10 to D11 where
D00 > D01 and D10 > D11, if the TAAnCCR1 register is rewritten when the count value of the 16-bit counter is
greater than D11 and less than D10 and if the TAAnCCR0 register is rewritten when the count value is greater
than D01 and less than D00, each set value is reflected as soon as the register has been rewritten and
compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H.
When the count value matches D11, the counter generates the INTTAAnCC1 signal and asserts the TOAAn1
pin.
When the count value matches D01, the counter generates the INTTAAnCC0 signal, deasserts the
TOAAn1 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the oneshot pulse that is originally expected.
Remark
n = 0 to 3, 5
m = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(b) Generation timing of compare match interrupt request signal (INTTAAnCC1)
The generation timing of the INTTAAnCC1 signal in the one-shot pulse output mode is different from other
INTTAAnCC1 signals; the INTTAAnCC1 signal in the one-shot pulse output mode is generated when the count
value of the 16-bit counter matches the value of the TAAnCCR1 register.
Count clock
16-bit counter
D1 − 2
D1 − 1
TAAnCCR1 register
D1
D1 + 1
D1 + 2
D1
TOAAn1 pin output
INTTAAnCC1 signal
Remark
n = 0 to 3, 5
Usually, the INTTAAnCC1 signal is generated the next time the 16-bit counter counts after its count value
matches the value of the TAAnCCR1 register.
In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is
changed to match the change timing of the TOAAn1 pin.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
PWM output mode (TAAnMD2 to TAAnMD0 bits = 100)
In the PWM output mode, a PWM waveform is output from the TOAAn1 pin when the TAAnCTL0.TAAnCE bit is set to 1.
In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOAAn0 pin.
Figure 7-29. Configuration in PWM Output Mode
TAAnCCR1 register
Transfer
Output
S
controller
R (RS-FF)
CCR1 buffer register
Match signal
TOAAn1 pin
INTTAAnCC1 signal
Clear
Count
clock
selection
16-bit counter
Output
controller
Match signal
TAAnCE bit
TOAAn0 pin
INTTAAnCC0 signal
CCR0 buffer register
Transfer
TAAnCCR0 register
Remark
n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Figure 7-30. Basic Timing in PWM Output Mode
FFFFH
D01
16-bit counter
D00
D10
D00
D10
D00
D10
D11
D01
D11
0000H
TAAnCE bit
TAAnCCR0 register
D00
CCR0 buffer register
D01
D00
D01
INTTAAnCC0 signal
TOAAn0 pin output
D10
TAAnCCR1 register
D11
D10
CCR1 buffer register
D11
INTTAAnCC1 signal
TOAAn1 pin output
Active period
(D10)
Cycle
(D00 + 1)
Inactive period
(D00 − D10 + 1)
When the TAAnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
PWM waveform from the TOAAn1 pin.
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TAAnCCR1 register) × Count clock cycle
Cycle = (Set value of TAAnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TAAnCCR1 register)/(Set value of TAAnCCR0 register + 1)
The PWM waveform can be changed by rewriting the TAAnCCRm register while the counter is operating. The newly
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the
16-bit counter is cleared to 0000H.
The compare match interrupt request signal INTTAAnCC0 is generated the next time the 16-bit counter counts after its
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal INTTAAnCC1 is generated when the count value of the 16-bit counter matches the value of
the CCR1 buffer register.
The value set to the TAAnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H.
Remark
n = 0 to 3, 5
m = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Figure 7-31. Setting of Registers in PWM Output Mode (1/2)
(a) TAAn control register 0 (TAAnCTL0)
TAAnCE
TAAnCTL0
TAAnCKS2 TAAnCKS1 TAAnCKS0
0/1
0
0
0
0
0/1
0/1
0/1
Select count clockNote 1
0: Stops counting
1: Enables counting
(b) TAAn control register 1 (TAAnCTL1)
TAAnEST TAAnEEE
TAAnCTL1
0
0
TAAnMD2 TAAnMD1 TAAnMD0
0/1
0
0
1
0
0
1, 0, 0:
PWM output mode
0: Operates on count clock
selected by TAAnCKS0 to
TAAnCKS2 bits
1: Counts external event
input signal
(c) TAAn I/O control register 0 (TAAnIOC0)
TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0
TAAnIOC0
0
0
0
0
0/1
0/1
0/1Note 2
0/1Note 2
0: Disables TOAAn0 pin output
1: Enables TOAAn0 pin output
Sets output level while operation
of TOAAn0 pin is disabled
0: Low level
1: High level
0: Disables TOAAn1 pin output
1: Enables TOAAn1 pin output
Specifies active level of
TOAAn1 pin output
0: Active-high
1: Active-low
• When TAAnOL1 bit = 0
• When TAAnOL1 bit = 1
16-bit counter
16-bit counter
TOAAn1 pin output
TOAAn1 pin output
Notes 1. The setting is invalid when the TAAnCTL1.TAAnEEE bit = 1.
2. Clear this bit to 0 when the TOAAn0 pin is not used in the PWM output mode.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Figure 7-31. Setting of Registers in PWM Output Mode (2/2)
(d) TAAn I/O control register 2 (TAAnIOC2)
TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0
TAAnIOC2
0
0
0
0
0/1
0/1
0
0
Select valid edge of
external event count input.
(e) TAAn counter read buffer register (TAAnCNT)
The value of the 16-bit counter can be read by reading the TAAnCNT register.
(f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1)
If D0 is set to the TAAnCCR0 register and D1 to the TAAnCCR1 register, the cycle and active level of the
PWM waveform are as follows.
Cycle = (D0 + 1) × Count clock cycle
Active level width = D1 × Count clock cycle
Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are not
used in the PWM output mode.
2. n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(1) Operation flow in PWM output mode
Figure 7-32. Software Processing Flow in PWM Output Mode (1/2)
FFFFH
D01
16-bit counter
D00
D01
D00
D10
D10
D01
D11
D11
D10
D00
D10
0000H
TAAnCE bit
TAAnCCR0 register
D00
CCR0 buffer register
D01
D00
D00
D01
D00
INTTAAnCC0 signal
TOAAn0 pin output
D10
TAAnCCR1 register
D10
D10
CCR1 buffer register
D11
D10
D10
D11
D10
INTTAAnCC1 signal
TOAAn1 pin output
Remark
n = 0 to 3, 5
m = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Figure 7-32. Software Processing Flow in PWM Output Mode (2/2)
Count operation start flow
TAAnCCR0, TAAnCCR1 register
setting change flow
START
Setting of TAAnCCR1 register
Register initial setting
TAAnCTL0 register
(TAAnCKS0 to TAAnCKS2 bits),
TAAnCTL1 register,
TAAnIOC0 register,
TAAnIOC2 register,
TAAnCCR0 register,
TAAnCCR1 register
TAAnCE bit = 1
Initial setting of these
registers is performed
before setting the
TAAnCE bit to 1.
Only writing of the TAAnCCR1
register must be performed
when only the set duty factor is
changed. When the counter is
cleared after setting, the
value of compare register m
is transferred to the CCRm
buffer register.
TAAnCCR0, TAAnCCR1 register
setting change flow
The TAAnCKS0 to
TAAnCKS2 bits can be
set at the same time
when counting is enabled
(TAAnCE bit = 1).
Setting of TAAnCCR0 register
When the counter is
cleared after setting,
the values of compare
register m are transferred
to the CCRm buffer register
in a batch.
Setting of TAAnCCR1 register
TAAnCCR0, TAAnCCR1 register
setting change flow
Setting of TAAnCCR0 register
Setting of TAAnCCR1 register
Remark
Count operation stop flow
TAAnCCR1 write
processing is necessary
even if only the set cycle
is changed.
When the counter is
cleared after setting,
the values of the
TAAnCCRm register are
transferred to the CCRm
buffer register in a batch.
TAAnCE bit = 0
Counting is stopped.
STOP
n = 0 to 3, 5
m = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(2) PWM output mode operation timing
(a) Changing pulse width during operation
To change the PWM waveform while the counter is operating, write the TAAnCCR1 register last.
Rewrite the TAAnCCRm register after writing the TAAnCCR1 register after the INTTAAnCC1 signal is detected.
FFFFH
D01
16-bit counter
D00
D10
D00
D10
D00
D10
D01
D11
D11
0000H
TAAnCE bit
TAAnCCR0 register
D00
D01
CCR0 buffer register
TAAnCCR1 register
D00
D10
CCR1 buffer register
D01
D11
D10
D11
TOAAn1 pin output
INTTAAnCC0 signal
To transfer data from the TAAnCCRm register to the CCRm buffer register, the TAAnCCR1 register must be
written.
To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the
TAAnCCR0 register and then set the active level to the TAAnCCR1 register.
To change only the cycle of the PWM waveform, first set the cycle to the TAAnCCR0 register, and then write
the same value to the TAAnCCR1 register.
To change only the active level width (duty factor) of the PWM waveform, only the TAAnCCR1 register has to
be set.
After data is written to the TAAnCCR1 register, the value written to the TAAnCCRm register is transferred to the
CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared
with the 16-bit counter.
To write the TAAnCCR0 or TAAnCCR1 register again after writing the TAAnCCR1 register once, do so after the
INTTAAnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined
because the timing of transferring data from the TAAnCCRm register to the CCRm buffer register conflicts with
writing the TAAnCCRm register.
Remark
n = 0 to 3, 5
m = 0, 1
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(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TAAnCCR1 register to 0000H. If the set value of the TAAnCCR0 register is
FFFFH, the INTTAAnCC1 signal is generated periodically.
Count clock
16-bit counter
FFFF
0000
D00 − 1
D00
0000
0001
D00 − 1
D00
0000
TAAnCE bit
TAAnCCR0 register
D00
D00
D00
TAAnCCR1 register
0000H
0000H
0000H
INTTAAnCC0 signal
INTTAAnCC1 signal
TOAAn1 pin output
Remark
n = 0 to 3, 5
To output a 100% waveform, set a value of (set value of TAAnCCR0 register + 1) to the TAAnCCR1 register. If
the set value of the TAAnCCR0 register is FFFFH, 100% output cannot be produced.
Count clock
16-bit counter
FFFF
0000
D00 − 1
D00
0000
0001
D00 − 1
D00
0000
TAAnCE bit
TAAnCCR0 register
D00
D00
D00
TAAnCCR1 register
D00 + 1
D00 + 1
D00 + 1
INTTAAnCC0 signal
INTTAAnCC1 signal
TOAAn1 pin output
Remark
n = 0 to 3, 5
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(c) Generation timing of compare match interrupt request signal (INTTAAnCC1)
The timing of generation of the INTTAAnCC1 signal in the PWM output mode differs from the timing of other
INTTAAnCC1 signals; the INTTAAnCC1 signal in the PWM output mode is generated when the count value of
the 16-bit counter matches the value of the TAAnCCR1 register.
Count clock
16-bit counter
TAAnCCR1 register
D1 − 2
D1 − 1
D1
D1 + 1
D1 + 2
D1
TOAAn1 pin output
INTTAAnCC1 signal
Remark
n = 0 to 3, 5
Usually, the INTTAAnCC1 signal is generated in synchronization with the next count-up after the count value of
the 16-bit counter matches the value of the TAAnCCR1 register.
In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed to
match the change timing of the output signal of the TOAAn1 pin.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Free-running timer mode (TAAnMD2 to TAAnMD0 bits = 101)
In the free-running timer mode, 16-bit timer/event counter AA starts counting when the TAAnCTL0.TAAnCE bit is set to
1. At this time, the TAAnCCRm register can be used as a compare register or a capture register, depending on the setting
of the TAAnOPT0.TAAnCCS0 and TAAnOPT0.TAAnCCS1 bits.
Figure 7-33. Configuration in Free-Running Timer Mode
TAAnCCR1 register
(compare)
TAAnCCR0 register
(compare)
Output
controller
TOAAn1 pin output
Output
controller
TOAAn0 pin output
TAAnCCS0, TAAnCCS1 bits
(capture/compare selection)
Internal count clock
TIAAn0 pin
(external event
count input/
capture
trigger input)
Edge
detector
Count
clock
selection
0
TAAnCE bit
Remark
INTTAAnCC1 signal
1
Edge
detector
0
TAAnCCR0 register
(capture)
TIAAn1 pin
(capture
trigger input)
INTTAAnOV signal
16-bit counter
INTTAAnCC0 signal
1
Edge
detector
TAAnCCR1 register
(capture)
n = 0 to 3, 5
m = 0, 1
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When the TAAnCE bit is set to 1, 16-bit timer/event counter AA starts counting, and the output signals of the TOAAn0
and TOAAn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TAAnCCRm
register, a compare match interrupt request signal (INTTAAnCCm) is generated, and the output signal of the TOAAnm pin
is inverted.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTAAnOV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR
instruction by software.
The TAAnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at
that time, and compared with the count value.
Figure 7-34. Basic Timing in Free-Running Timer Mode (Compare Function)
FFFFH
D00
D00
D01
16-bit counter
D10
D10
D11
D01
D11
D11
0000H
TAAnCE bit
TAAnCCR0 register
D00
D01
INTTAAnCC0 signal
TOAAn0 pin output
TAAnCCR1 register
D10
D11
INTTAAnCC1 signal
TOAAn1 pin output
INTTAAnOV signal
TAAnOVF bit
Cleared to 0 by
CLR instruction
Remark
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
n = 0 to 3, 5
m = 0, 1
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When the TAAnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIAAnm pin is
detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, and a capture interrupt request signal
(INTTAAnCCm) is generated.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTAAnOV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR
instruction by software.
Figure 7-35. Basic Timing in Free-Running Timer Mode (Capture Function)
FFFFH
D10
D00
16-bit counter
D11
D12
D13
D01
D02
D03
0000H
TAAnCE bit
TIAAn0 pin input
TAAnCCR0 register
D00
D01
D02
D03
INTTAAnCC0 signal
TIAAn1 pin input
TAAnCCR1 register
D10
D11
D12
D13
INTTAAnCC1 signal
INTTAAnOV signal
TAAnOVF bit
Cleared to 0 by
CLR instruction
Remark
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
n = 0 to 3, 5
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Figure 7-36. Register Setting in Free-Running Timer Mode (1/2)
(a) TAAn control register 0 (TAAnCTL0)
TAAnCE
TAAnCTL0
0/1
TAAnCKS2 TAAnCKS1 TAAnCKS0
0
0
0
0
0/1
0/1
0/1
Select count clockNote
0: Stops counting
1: Enables counting
Note The setting is invalid when the TAAnCTL1.TAAnEEE bit = 1
(b) TAAn control register 1 (TAAnCTL1)
TAAnEST TAAnEEE
TAAnCTL1
0
0
0/1
TAAnMD2 TAAnMD1 TAAnMD0
0
0
1
0
1
1, 0, 1:
Free-running mode
0: Operates with count clock
selected by TAAnCKS0 to
TAAnCKS2 bits
1: Counts on external
event count input signal
(c) TAAn I/O control register 0 (TAAnIOC0)
TAAnOL1 TAAnOE1 TAAnOL0 TAAnOE0
TAAnIOC0
0
0
0
0
0/1
0/1
0/1
0/1
0: Disables TOAAn0 pin output
1: Enables TOAAn0 pin output
Sets output level with operation
of TOAAn0 pin disabled
0: Low level
1: High level
0: Disables TOAAn1 pin output
1: Enables TOAAn1 pin output
Sets output level with operation
of TOAAn1 pin disabled
0: Low level
1: High level
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Figure 7-36. Register Setting in Free-Running Timer Mode (2/2)
(d) TAAn I/O control register 1 (TAAnIOC1)
TAAnIS3 TAAnIS2 TAAnIS1 TAAnIS0
TAAnIOC1
0
0
0
0
0/1
0/1
0/1
0/1
Select valid edge
of TIAAn0 pin input
Select valid edge
of TIAAn1 pin input
(e) TAAn I/O control register 2 (TAAnIOC2)
TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0
TAAnIOC2
0
0
0
0
0/1
0/1
0
0
Select valid edge of
external event count input
(f) TAAn option register 0 (TAAnOPT0)
TAAnCCS1 TAAnCCS0
TAAnOPT0
0
0
0/1
0/1
TAAnOVF
0
0
0
0/1
Overflow flag
Specifies if TAAnCCR0
register functions as
capture or compare register
Specifies if TAAnCCR1
register functions as
capture or compare register
(g) TAAn counter read buffer register (TAAnCNT)
The value of the 16-bit counter can be read by reading the TAAnCNT register.
(h) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1)
These registers function as capture registers or compare registers depending on the setting of the
TAAnOPT0.TAAnCCSm bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIAAnm pin is detected.
When the registers function as compare registers and when Dm is set to the TAAnCCRm register, the
INTTAAnCCm signal is generated when the counter reaches (Dm + 1), and the output signal of the
TOAAnm pin is inverted.
Remark
n = 0 to 3, 5
m = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(1) Operation flow in free-running timer mode
(a) When using capture/compare register as compare register
Figure 7-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2)
FFFFH
D00
D00
D01
16-bit counter
D10
D10
D01
D11
D11
D11
0000H
TAAnCE bit
TAAnCCR0 register
D00
D01
Set value changed
INTTAAnCC0 signal
TOAAn0 pin output
D10
TAAnCCR1 register
D11
Set value changed
INTTAAnCC1 signal
TOAAn1 pin output
INTTAAnOV signal
TAAnOVF bit
Cleared to 0 by
CLR instruction
Remark
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Figure 7-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2)
Count operation start flow
START
Register initial setting
TAAnCTL0 register
(TAAnCKS0 to TAAnCKS2 bits),
TAAnCTL1 register,
TAAnIOC0 register,
TAAnIOC2 register,
TAAnOPT0 register,
TAAnCCR0 register,
TAAnCCR1 register
TAAnCE bit = 1
Initial setting of these registers
is performed before setting the
TAAnCE bit to 1.
The TAAnCKS0 to TAAnCKS2 bits
can be set at the same time
when counting has been started
(TAAnCE bit = 1).
Overflow flag clear flow
Read TAAnOPT0 register
(check overflow flag).
TAAnOVF bit = 1
NO
YES
Execute instruction to clear
TAAnOVF bit (CLR TAAnOVF).
Count operation stop flow
TAAnCE bit = 0
Counter is initialized and
counting is stopped by
clearing TAAnCE bit to 0.
STOP
Remark
n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(b) When using capture/compare register as capture register
Figure 7-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2)
FFFFH
D10
D00
D11
D12
D01
16-bit counter
D02
D03
0000H
TAAnCE bit
TIAAn0 pin input
TAAnCCR0 register
0000
D00
D01
D02
D03
0000
INTTAAnCC0 signal
TIAAn1 pin input
0000
TAAnCCR1 register
D10
D11
D12
0000
INTTAAnCC1 signal
INTTAAnOV signal
TAAnOVF bit
Remark
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Figure 7-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2)
Count operation start flow
START
Register initial setting
TAAnCTL0 register
(TAAnCKS0 to TAAnCKS2 bits),
TAAnCTL1 register,
TAAnIOC1 register,
TAAnOPT0 register
TAAnCE bit = 1
Initial setting of these registers
is performed before setting the
TAAnCE bit to 1.
The TAAnCKS0 to TAAnCKS2 bits can
be set at the same time when counting
has been started (TAAnCE bit = 1).
Overflow flag clear flow
Read TAAnOPT0 register
(check overflow flag).
TAAnOVF bit = 1
NO
YES
Execute instruction to clear
TAAnOVF bit (CLR TAAnOVF).
Count operation stop flow
TAAnCE bit = 0
Counter is initialized and
counting is stopped by
clearing TAAnCE bit to 0.
STOP
Remark
n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(2) Operation timing in free-running timer mode
(a) Interval operation with TAAnCCRm register used as compare register
When 16-bit timer/event counter AA is used as an interval timer with the TAAnCCRm register used as a
compare register, software processing is necessary for setting a comparison value to generate the next
interrupt request signal each time the INTTAAnCCm signal has been detected.
FFFFH
D02
D10
D00
D11
16-bit counter
D03
D12
D01
D13
0000H
D04
TAAnCE bit
TAAnCCR0 register
D00
D01
D02
D03
D04
D05
INTTAAnCC0 signal
TOAAn0 pin output
Interval period Interval period Interval period Interval period Interval period
(D00 + 1)
(10000H +
(D02 − D01)
(10000H +
(10000H +
D01 − D00)
D03 − D02)
D04 − D03)
TAAnCCR1 register
D10
D11
D12
D13
D14
INTTAAnCC1 signal
TOAAn1 pin output
Interval period Interval period Interval period Interval period
(D10 + 1)
(10000H +
(10000H +
(10000H +
D11 − D10)
D12 − D11)
D13 − D12)
When performing an interval operation in the free-running timer mode, two intervals can be set with one
channel.
To perform the interval operation, the value of the corresponding TAAnCCRm register must be re-set in the
interrupt servicing that is executed when the INTTAAnCCm signal is detected.
The set value for re-setting the TAAnCCRm register can be calculated by the following expression, where “Dm”
is the interval period.
Compare register default value: Dm − 1
Value set to compare register second and subsequent times: Previous set value + Dm
(If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the
register.)
Remark
m = 0, 1
n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(b) Pulse width measurement with TAAnCCRm used as capture register
When pulse width measurement is performed with the TAAnCCRm register used as a capture register,
software processing is necessary for reading the capture register each time the INTTAAnCCm signal has been
detected and for calculating the interval.
FFFFH
D02
D10
D00
D11
16-bit counter
D03
D12
D01
D13
0000H
D04
TAAnCE bit
TIAAn0 pin input
TAAnCCR0 register
0000H
D00
D01
D02
D03
D04
INTTAAnCC0 signal
Pulse interval Pulse interval Pulse interval Pulse interval Pulse interval
(D00)
(10000H +
(D02 − D01)
(10000H +
(10000H +
D01 − D00)
D03 − D02)
D04 − D03)
TIAAn1 pin input
TAAnCCR1 register
0000H
D10
D11
D12
D13
INTTAAnCC1 signal
Pulse interval Pulse interval Pulse interval Pulse interval
(D10)
(10000H +
(10000H +
(10000H +
D11 − D10)
D12 − D11)
D13 − D12)
INTTAAnOV signal
TAAnOVF bit
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
When executing pulse width measurement in the free-running timer mode, two pulse widths can be measured
with one channel.
To measure a pulse width, the pulse width can be calculated by reading the value of the TAAnCCRm register in
synchronization with the INTTAAnCCm signal, and calculating the difference between the read value and the
previously read value.
Remark
m = 0, 1
n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(c) Processing of overflow when two capture registers are used
Care must be exercised in processing the overflow flag when two capture registers are used. First, an example
of incorrect processing is shown below.
Example of incorrect processing when two capture registers are used
FFFFH
D11
D10
16-bit counter
D01
D00
0000H
TAAnCE bit
TIAAn0 pin input
TAAnCCR0 register
D01
D00
TIAAn1 pin input
D11
D10
TAAnCCR1 register
INTTAAnOV signal
TAAnOVF bit
The following problem may occur when two pulse widths are measured in the free-running timer mode.
Read the TAAnCCR0 register (setting of the default value of the TIAAn0 pin input).
Read the TAAnCCR1 register (setting of the default value of the TIAAn1 pin input).
Read the TAAnCCR0 register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 − D00).
Read the TAAnCCR1 register.
Read the overflow flag. Because the flag is cleared in , 0 is read.
Because the overflow flag is 0, the pulse width can be calculated by (D11 − D10) (incorrect).
When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other
capture register may not obtain the correct pulse width.
Use software when using two capture registers. An example of how to use software is shown below.
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(1/2)
Example when two capture registers are used (using overflow interrupt)
FFFFH
D11
D10
16-bit counter
D01
D00
0000H
TAAnCE bit
INTTAAnOV signal
TAAnOVF bit
TAAnOVF0 flagNote
TIAAn0 pin input
D01
D00
TAAnCCR0 register
TAAnOVF1 flagNote
TIAAn1 pin input
D11
D10
TAAnCCR1 register
Note The TAAnOVF0 and TAAnOVF1 flags are set on the internal RAM by software.
Read the TAAnCCR0 register (setting of the default value of the TIAAn0 pin input).
Read the TAAnCCR1 register (setting of the default value of the TIAAn1 pin input).
An overflow occurs. Set the TAAnOVF0 and TAAnOVF1 flags to 1 in the overflow interrupt servicing,
and clear the overflow flag to 0.
Read the TAAnCCR0 register.
Read the TAAnOVF0 flag. If the TAAnOVF0 flag is 1, clear it to 0.
Because the TAAnOVF0 flag is 1, the pulse width can be calculated by (10000H + D01 − D00).
Read the TAAnCCR1 register.
Read the TAAnOVF1 flag. If the TAAnOVF1 flag is 1, clear it to 0 (the TAAnOVF0 flag is cleared in
, and the TAAnOVF1 flag remains 1).
Because the TAAnOVF1 flag is 1, the pulse width can be calculated by (10000H + D11 − D10)
(correct).
Same as
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(2/2)
Example when two capture registers are used (without using overflow interrupt)
FFFFH
D11
D10
16-bit counter
D01
D00
0000H
TAAnCE bit
INTTAAnOV signal
TAAnOVF bit
TAAnOVF0 flagNote
TIAAn0 pin input
D01
D00
TAAnCCR0 register
TAAnOVF1 flagNote
TIAAn1 pin input
D11
D10
TAAnCCR1 register
Note The TAAnOVF0 and TAAnOVF1 flags are set on the internal RAM by software.
Read the TAAnCCR0 register (setting of the default value of the TIAAn0 pin input).
Read the TAAnCCR1 register (setting of the default value of the TIAAn1 pin input).
An overflow occurs. Nothing is done by software.
Read the TAAnCCR0 register.
Read the overflow flag. If the overflow flag is 1, set only the TAAnOVF1 flag to 1, and clear the
overflow flag to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 − D00).
Read the TAAnCCR1 register.
Read the overflow flag. Because the overflow flag is cleared in , 0 is read.
Read the TAAnOVF1 flag. If the TAAnOVF1 flag is 1, clear it to 0.
Because the TAAnOVF1 flag is 1, the pulse width can be calculated by (10000H + D11 − D10)
(correct).
Same as
Remark
n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(d) Processing of overflow if capture trigger interval is long
If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow
may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is
shown below.
Example of incorrect processing when capture trigger interval is long
FFFFH
Dm0
16-bit counter
Dm1
0000H
TAAnCE bit
TIAAnm pin input
TAAnCCRm register
Dm0
Dm1
INTTAAnOV signal
TAAnOVF bit
1 cycle of 16-bit counter
Pulse width
The following problem may occur when a long pulse width is measured in the free-running timer mode.
Read the TAAnCCRm register (setting of the default value of the TIAAnm pin input).
An overflow occurs. Nothing is done by software.
An overflow occurs a second time. Nothing is done by software.
Read the TAAnCCRm register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + Dm1 − Dm0)
(incorrect).
Actually, the pulse width must be (20000H + Dm1 − Dm0) because an overflow occurs twice.
If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be
obtained.
If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use
software. An example of how to use software is shown next.
Remark
m = 0, 1
n = 0 to 3, 5
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Example when capture trigger interval is long
FFFFH
Dm0
16-bit counter
Dm1
0000H
TAAnCE bit
TIAAnm pin input
TAAnCCRm register
Dm0
Dm1
INTTAAnOV signal
TAAnOVF bit
Overflow
counterNote
0H
1H
2H
0H
1 cycle of 16-bit counter
Pulse width
Note The overflow counter is set arbitrarily by software on the internal RAM.
Read the TAAnCCRm register (setting of the default value of the TIAAnm pin input).
An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow
interrupt servicing.
An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to
0 in the overflow interrupt servicing.
Read the TAAnCCRm register.
Read the overflow counter.
→ When the overflow counter is “N”, the pulse width can be calculated by (N × 10000H + Dm1 –
Dm0).
In this example, the pulse width is (20000H + Dm1 – Dm0) because an overflow occurs twice.
Clear the overflow counter (0H).
Remark
m = 0, 1
n = 0 to 3, 5
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(e) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TAAnOVF bit to 0 with the CLR instruction and by writing
8-bit data (bit 0 is 0) to the TAAnOPT0 register. To accurately detect an overflow, read the TAAnOVF bit when it
is 1, and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting)
Overflow
set signal
(iii) Operation to clear to 0 (without conflict with setting)
Overflow
set signal
L
L
0 write signal
0 write signal
Register
access signal
Overflow flag
(TAAnOVF bit)
Read
Write
Overflow flag
(TAAnOVF bit)
(ii) Operation to write 0 (conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
Overflow
set signal
0 write signal
Overflow flag
(TAAnOVF bit)
Overflow
set signal
0 write signal
Register
access signal
Overflow flag
(TAAnOVF bit)
Remark
Read
Write
H
n = 0 to 3, 5
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of the overflow
may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has
occurred even when an overflow has actually occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to
0 with the CLR instruction, the overflow flag remains set (1) even after execution of the clear instruction.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Pulse width measurement mode (TAAnMD2 to TAAnMD0 bits = 110)
In the pulse width measurement mode, 16-bit timer/event counter AA starts counting when the TAAnCTL0.TAAnCE bit
is set to 1. Each time the valid edge input to the TIAAnm pin has been detected, the count value of the 16-bit counter is
stored in the TAAnCCRm register, and the 16-bit counter is cleared to 0000H.
The interval of the valid edge can be measured by reading the TAAnCCRm register after a capture interrupt request
signal (INTTAAnCCm) occurs.
Select either the TIAAn0 or TIAAn1 pin as the capture trigger input pin. Specify “No edge detection” for the unused pins
by using the TAAnIOC1 register.
When an external clock is used as the count clock, measure the pulse width of the TIAAn1 pin because the external
clock is fixed to the TIAAn0 pin. At this time, clear the TAAnIOC1.TAAnIS1 and TAAnIOC1.TAAnIS0 bits to 00 (capture
trigger input (TIAAn0 pin): No edge detection).
Figure 7-39. Configuration in Pulse Width Measurement Mode
Clear
Count
clock
selection
16-bit counter
INTTAAnOV signal
INTTAAnCC0 signal
TAAnCE bit
TIAAn0 pin
(capture
trigger input)
Edge
detector
TIAAn1 pin
(capture
trigger input)
Edge
detector
Remark
INTTAAnCC1 signal
TAAnCCR0 register
(capture)
TAAnCCR1 register
(capture)
n = 0 to 3, 5
m = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Figure 7-40. Basic Timing in Pulse Width Measurement Mode
FFFFH
16-bit counter
0000H
TAAnCE bit
TIAAnm pin input
TAAnCCRm register
0000H
D0
D1
D2
D3
INTTAAnCCm signal
INTTAAnOV signal
TAAnOVF bit
Remark
Cleared to 0 by
CLR instruction
n = 0 to 3, 5
m = 0, 1
When the TAAnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIAAnm pin is
later detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, the 16-bit counter is cleared to
0000H, and a capture interrupt request signal (INTTAAnCCm) is generated.
The pulse width is calculated as follows.
Pulse width = Captured value × Count clock cycle
If the valid edge is not input to the TIAAnm pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt
request signal (INTTAAnOV) is generated at the next count clock, and the counter is cleared to 0000H and continues
counting. At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by
executing the CLR instruction via software.
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Pulse width = (10000H × TAAnOVF bit set (1) count + Captured value) × Count clock cycle
Remark
n = 0 to 3, 5
m = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Figure 7-41. Register Setting in Pulse Width Measurement Mode
(a) TAAn control register 0 (TAAnCTL0)
TAAnCE
TAAnCTL0
0/1
TAAnCKS2 TAAnCKS1 TAAnCKS0
0
0
0
0
0/1
0/1
0/1
Select count clock
0: Stops counting
1: Enables counting
(b) TAAn control register 1 (TAAnCTL1)
TAAnEST TAAnEEE
TAAnCTL1
0
0
0
TAAnMD2 TAAnMD1 TAAnMD0
0
0
1
1
0
1, 1, 0:
Pulse width measurement
mode
(c) TAAn I/O control register 1 (TAAnIOC1)
TAAnIS3 TAAnIS2 TAAnIS1 TAAnIS0
TAAnIOC1
0
0
0
0
0/1
0/1
0/1
0/1
Select valid edge
of TIAAn0 pin input
Select valid edge
of TIAAn1 pin input
(d) TAAn option register 0 (TAAnOPT0)
TAAnCCS1 TAAnCCS0
TAAnOPT0
0
0
0
0
TAAnOVF
0
0
0
0/1
Overflow flag
(e) TAAn counter read buffer register (TAAnCNT)
The value of the 16-bit counter can be read by reading the TAAnCNT register.
(f) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1)
These registers store the count value of the 16-bit counter when the valid edge input to the TIAAnm pin is
detected.
Remarks 1. TAAn I/O control register 0 (TAAnIOC0), and TAAn I/O control register 2 (TAAnIOC2) are not
used in the pulse width measurement mode.
2. m = 0, 1
n = 0 to 3, 5
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(1) Operation flow in pulse width measurement mode
Figure 7-42. Software Processing Flow in Pulse Width Measurement Mode
FFFFH
16-bit counter
0000H
TAAnCE bit
TIAAn0 pin input
0000H
TAAnCCR0 register
D0
D1
D2
0000H
INTTAAnCC0 signal
Count operation start flow
START
Register initial setting
TAAnCTL0 register
(TAAnCKS0 to TAAnCKS2 bits),
TAAnCTL1 register,
TAAnIOC1 register,
TAAnOPT0 register
Set TAAnCTL0 register
(TAAnCE bit = 1)
Initial setting of these registers
is performed before setting the
TAAnCE bit to 1.
The TAAnCKS0 to TAAnCKS2 bits can
be set at the same time when counting
has been started (TAAnCE bit = 1).
Count operation stop flow
TAAnCE bit = 0
The counter is initialized and counting
is stopped by clearing the TAAnCE bit to 0.
STOP
Remark
n = 0 to 3, 5
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(2) Operation timing in pulse width measurement mode
(a) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TAAnOVF bit to 0 with the CLR instruction and by writing
8-bit data (bit 0 is 0) to the TAAnOPT0 register. To accurately detect an overflow, read the TAAnOVF bit when it
is 1, and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting)
Overflow
set signal
(iii) Operation to clear to 0 (without conflict with setting)
Overflow
set signal
L
L
0 write signal
0 write signal
Register
access signal
Overflow flag
(TAAnOVF bit)
Read
Write
Overflow flag
(TAAnOVF bit)
(ii) Operation to write 0 (conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
Overflow
set signal
0 write signal
Overflow flag
(TAAnOVF bit)
Overflow
set signal
0 write signal
Register
access signal
Overflow flag
(TAAnOVF bit)
Remark
Read
Write
H
n = 0 to 3, 5
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of the overflow
may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has
occurred even when an overflow has actually occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to
0 with the CLR instruction, the overflow flag remains set (1) even after execution of the clear instruction.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Timer output operations
The following table shows the operations and output levels of the TOAAn0 and TOAAn1 pins.
Table 7-5. Timer Output Control in Each Mode
Operation Mode
TOAAn1 Pin
TOAAn0 Pin
Interval timer mode
Square wave output
External event count mode
Square wave output
External trigger pulse output mode
External trigger pulse output
One-shot pulse output mode
One-shot pulse output
PWM output mode
PWM output
Free-running timer mode
Square wave output (only when compare function is used)
Square wave output
−
Pulse width measurement mode
Remark
−
n = 0 to 3, 5
Table 7-6. Truth Table of TOAAn0 and TOAAn1 Pins Under Control of Timer Output Control Bits
TAAnIOC0.TAAnOLm Bit TAAnIOC0.TAAnOEm Bit
0
TAAnCTL0.TAAnCE Bit
Level of TOAAnm Pin
0
×
Low-level output
1
0
Low-level output
1
Low level immediately before counting, high
level after counting is started
1
0
×
High-level output
1
0
High-level output
1
High level immediately before counting, low level
after counting is started
Remark
n = 0 to 3, 5
m = 0, 1
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7.6
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Timer-Tuned Operation Function
Timer AA and timer AB have a timer-tuned operation function.
The timer-tuned operation function is used to tune the internal timers of the V850ES/JG3-H and V850ES/JH3-H, so that
the number of capture or compare registers of the slave timer (the number of timer outputs and the number of compare
match interrupts of the slave timer) can be added to the master timer. The timers that can be tuned are listed in Table 7-7.
Table 7-7. Tuned-Operation Mode of Timers
Master Timer
Slave Timer
TAA1
TAA0
TAA3
TAA2
TAB0
TAA5
The tuned-operation function has the following modes.
• PWM output mode
• Free-running timer mode
Figure 7-43 shows an example where individual operation and tuned operation of TAA0 (as the master timer) and TAA1
(as the slave timer) are performed in PWM output mode.
Figure 7-43. Differences Between Individual Operation and Tuned Operation Using TAA0 and TAA1
Individual operation
Tuned operation
TAA1 (master) + TAA0 (slave)
TAA1
16-bit timer/counter
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
TOAA10 (square
waveform output)
TOAA11 (PWM output)
TAA0
16-bit capture/compare
TOAA10 (square
waveform output)
TOAA11 (PWM output)
16-bit capture/compare
TOAA01 (PWM output)
16-bit capture/compare
TOAA01 (PWM output)
16-bit capture/compare
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
TOAA00 (squarewaveform output)
TOAA01 (PWM output)
Two PWM outputs are available when PWM
is operated separately with each timer.
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PWM is operated in tuned-operation mode.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Table 7-8 show the timer modes that can be used in the tuned-operation mode and Table 7-9 shows the differences of
the timer output functions between individual operation and tuned operation (√: Settable, ×: Not settable).
Table 7-8. Timer Modes Usable in Tuned-Operation Mode
Master Timer
Slave Timer
Free-Running Timer Mode
PWM Mode
TAA1
TAA0
√
√
TAA3
TAA2
√
√
TAB0
TAA5
√
√
Table 7-9. Timer Output Functions
Tuned
Channel
Ch0
Timer
TAA1
(master)
TAA0
(slave)
Ch1
TAA3
(master)
TAA2
(slave)
Ch2
TAB0
(master)
TAA5
(slave)
Remark
Pin
Free-Running Timer Mode
PWM Mode
Individual Operation
Tuned Operation
Individual Operation
Tuned Operation
TOAA10
PPG
←
Toggle
←
TOAA11
PPG
←
PWM
←
TOAA00
PGP
←
Toggle
PWM
TOAA01
PPG
←
PWM
←
TOAA30
PPG
←
Toggle
←
TOAA31
PPG
←
PWM
←
TOAA20
PPG
←
Toggle
PWM
TOAA21
PPG
←
PWM
←
TOAB00
PPG
←
Toggle
←
TOAB01 to TOAB03
PPG
←
PWM
←
TOAA50
PPG
←
Toggle
PWM
TOAA51
PPG
←
PWM
←
The timing of transmitting data from the compare register of the buffer register is as follows.
• PPG:
CPU write timing
• Toggle, PWM, triangular wave PWM: Timing at which timer counter and compare register match TOAAn0
and TOABm0
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Free-running timer mode (during timer-tuned operation)
This section explains the free-running timer mode of the timer-tuned operation. For the combination of timer-tuned
operations, see Table 7-7. In this section, an example of timer-tuned operation using TAA1 and TAA0 is shown.
(i) Selecting capture/compare registers
When the free-running timer mode of the timer-tuned operation is used with TAA1 and TAA0 connected to each
other, the two capture/compare registers of TAA1 and two capture/compare registers of TAA0 can be used in
combination.
How the capture and compare registers are combined is not restricted and can be selected by using the
TAAnCCSn bit of the master or slave timer. When the compare register is selected, the set value of the
compare register can be rewritten during operation and the rewriting method is anytime write (n = 0, 1).
(ii) Overflow
If the counter overflows, an overflow interrupt (INTTAA1OV) of the master timer is generated and the overflow
flag (TAA1OVF) is set to “1”.
The overflow interrupt (INTTAA0OV) and overflow flag (TAA0OVF) of the slave timer do not operate and are
always at the low level.
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(1) Settings in free-running timer mode (compare function)
[Initial settings]
Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled)
Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled)
[Initial settings of master timer (TAA1)]
• TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 101 (setting of free-running timer mode)
• TAA1OPT0.TAA1CCS1 and TAA1OPT0.TAA1CCS0 = 00 (setting of capture/compare select bit to
“compare”.)
• TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any))
• TAA1CCR1 and TAA1CCR0 registers are set.
[Initial settings of slave timer (TAA0)]
• TAA0CTL1.TAA0SYE = 1 (setting of timer-tuned operation)
• TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 101 (setting of free-running timer mode)
• TAA0OPT0.TAA0CCS1 and TAA0OPT0.TAA0CCS0 = 00 (setting of capture/compare select bit to
“compare”.)
• TAA0CCR0 and TAA0CCR1 registers are set.
Remark
The initial settings of the master timer and slave timer may be performed in any order.
[Starting counting]
Set TAA1CTL0.TAA1CE of the master timer to 1.
Start counting.
Changing the setting of the register during operation
• The compare register can be rewritten (anytime write).
[End condition]
• Set TAA1CTL0.TAA1CE of the master timer to 0.
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Figure 7-44. Example of Timing in Free-Running Mode (Compare Function)
FFFFH
D01
D01
D00
D00
TAA1
16-bit counter
D11
D11
D10
D10
0000H
TAA1CE
TAA1CCR0
D10
TAA1CCR1
D11
TAA0CCR0
D00
TAA0CCR1
D01
INTTAA1CC0
INTTAA1CC1
INTTAA0CC0
INTTAA0CC1
INTTAA1OV
TAA1OVF
TAA1OVF write clear (0)
TOAA10
TOAA11
TOAA00
TOAA01
INTTAA0OV
L
TAA0OVF
L
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(2) Settings in free-running timer mode (capture function)
[Initial settings]
Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled)
Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled)
[Initial settings of master timer (TAA1)]
• TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 101 (setting of free-running timer mode)
• TAA1OPT0.TAA1CCS1 and TAA1OPT0.TAA1CCS0 = 11 (setting of capture/compare select bit to “capture”.)
• TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any))
• TAA1IOC1.TAA1IS3 to TAA1IOC1.TAA1IS0 (specification of valid edge of capture trigger)
[Initial settings of slave timer (TAA0)]
• TAA0CTL1.TAA0SYE = 1 (setting of timer-tuned operation)
• TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 101 (setting of free-running timer mode)
• TAA0OPT0.TAA0CCS1 and TAA0OPT0.TAA0CCS0 = 11 (setting of capture/compare select bit to “capture”.)
• TAA0IOC1.TAA0IS3 to TAA0IOC1.TAA0IS0 (specification of valid edge of capture trigger)
Remark
The initial settings of the master timer and slave timer may be performed in any order.
[Starting counting]
Set TAA1CTL0.TAA1CE of the master timer to 1.
Start counting.
[End condition]
• Set TAA1CTL0.TAA1CE of the master timer to 0.
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Figure 7-45. Example of Timing in Free-Running Mode (Capture Function)
FFFFH
D011
D110
D001
D000
TAA1
16-bit counter
D111
D110
D100
D101
0000H
TAA1CE
TIAA10
TIAA11
TIAA00
TIAA01
TAA1CCR0
TAA1CCR1
0000
0000
TAA0CCR0
D110
0000
TAA0CCR1
D101
D100
0000
D101
D110
D111
D000
D001
D010
D011
INTTAA1CC0
INTTAA1CC1
INTTAA0CC0
INTTAA0CC1
INTTAA1OV
TAA1OVF
INTTAA0OV
L
TAA0OVF
L
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
(3) Settings in free-running timer mode (capture/compare used together)
An example of using TAA0 as a capture register and TAA1 as a compare register is shown below.
[Initial settings]
Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled)
Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled)
[Initial settings of master timer (TAA1)]
• TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 101 (setting of free-running timer mode)
• TAA1OPT0.TAA1CCS1 and TAA1OPT0.TAA1CCS0 = 11 (setting of capture/compare select bit to “capture”.)
• TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any))
• TAA1.TAA0IS3 to TAA1.TAA1IS0 (specification of valid edge of capture trigger)
[Initial settings of slave timer (TAA0)]
• TAA0CTL1.TAA0SYE = 1 (setting of timer-tuned operation)
• TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 101 (setting of free-running timer mode)
• TAA0OPT0.TAA0CCS1 and TAA0OPT0.TAA0CCS0 = 00 (setting of capture/compare select bit to
“compare”.)
• TAA0CCR0 and TAA0CCR1 registers are set.
Remark
The initial settings of the master timer and slave timer may be performed in any order.
[Starting counting]
Set TAA1CTL0.TAA1CE of the master timer to 1.
Start counting.
[End condition]
• Set TAA1CTL0.TAA1CE of the master timer to 0.
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Figure 7-46. Example of Timing in Free-Running Mode (Capture/Compare Used Together)
FFFFH
D100
D010
D010
TAA1
16-bit counter
D000
D000
D111
D110
0000H
TAA1CE
TIAA10
TIAA11
0000
TAA1CCR0
TAA1CCR1
0000
D000
D111
D110
TAA0CCR0
0000
D000
TAA0CCR1
0000
D010
INTTAA1CC0
INTTAA1CC1
INTTAA0CC0
INTTAA0CC1
INTTAA1OV
TAA1OVF
TAA1OVF write clear (0)
TOAA00
TOAA01
INTTAA0OV
L
TAA0OVF
L
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7.6.2
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
PWM output mode (during timer-tuned operation)
This section explains the PWM output mode of timer-tuned operation. For combinations of timer-tuned operations, see
Table 7-7. This section presents an example of a timer-tuned operation with TAB0 and TAA5.
The TAB0CCR0 register of the master timer (TAB0) is used as a compare register for cycle, and the TAB0CCR1,
TAB0CCR2, and TAB0CCR3 registers of the master timer (TAB0) and the TAA5CCR0 and TAA5CCR1 registers of the
slave timer (TAA5) are used as compare registers for duty.
The compare registers can be rewritten during operation and the rewriting method is batch writing.
Batch writing is enabled when the TAB0CCR1 register of the master timer (TAB0) is written, and all the compare
registers of the master and slave timers are rewritten or the same value is written to them when an interrupt, which is
generated if the value of the TAB0CCR0 register of the master timer (TAB0) matches the value of the timer counter, is
generated.
(1) Settings in PWM output mode
[Initials setting]
Master timer: TAB0CTL0.TAB0CE = 0 (operation disabled)
Slave timer: TAA5CTL0.TAA5CE = 0 (operation disabled)
[Initial settings of master timer (TAB0)]
• TAB0CTL1.TAB0MD2 to TAB0CTL1.TAB0MD0 = 100 (setting of PWM output mode)
• TAB0OPT0.TAB0CCS3 to TAB0OPT0.TAB0CCS0 = 0000 (setting of capture/compare select bit to
“compare”.)
• TAB0CCR0, TAB0CCR1, TAB0CCR2, and TAB0CCR3 registers are set.
[Initial settings of slave timer (TAA5)]
• TAA5CTL1.TAA5SYE = 1 (setting of timer-tuned operation)
• TAA5CTL1.TAA5MD2 to TAA5CTL1.TAA5MD0 = 101 (setting of free-running timer mode)
• TAA5OPT0.TAA5CCS1 and TAA5OPT0.TAA5CCS0 = 00 (setting of capture/compare select bit to
“compare”.)
• TAA5CCR0 and TAA5CCR1 registers are set.
Remark
The initial settings of the master timer and slave timer may be performed in any order.
[Starting counting]
Set TAB0CTL0.TAB0CE of the master timer to 1.
Start counting.
Changing the setting of the register during operation
• The compare register can be rewritten (batch rewrite).
[End condition]
• Set TAB0CTL0.TAB0CE of the master timer to 0.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
[Batch write]
In the PWM output mode, the next batch write is enabled by writing the TAB0CCR1 register of the master timer
(TAB0). After all the compare registers that must be rewritten have been rewritten, therefore, the TAB0CCR1
register of the master timer (TAB0) must be written.
Batch writing is executed when the value of the timer counter matches the value of the compare register for cycle
(TAB0CCR0).
If the TAB0CCR1 register of the master timer (TAB0) is not written, batch writing is not enabled even if any other
compare register is rewritten. Consequently, the value of the compare registers is not rewritten even when the
value of the timer counter matches the value of the compare register for cycle (TAB0CCR0).
Figure 7-47. Timing Example of Tuned PWM Function (TAB0, TAA5)
FFFFH
D00
D50
D50
D40
D40
TAB0
16-bit counter
D00
D30
D30
D20
D20
D10
D10
0000H
TAB0CE bit
TAB0CCR0 register
D00
TAB0CCR1 register
D10
TAB0CCR0 register
D20
TAB0CCR1 register
D30
TAA5CCR0 register
D40
TAA5CCR1 register
D50
INTTAB0CC0
match interrupt
INTTAB0CC1
match interrupt
INTTAB0CC2
match interrupt
INTTAB0CC3
match interrupt
INTTAA5CC0
match interrupt
INTTAA5CC1
match interrupt
TOAB00 pin output
TOAB01 pin output
TOAB02 pin output
TOAB03 pin output
TOAA50 pin output
TOAA51 pin output
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7.7
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Simultaneous-Start Function
Timer AA and timer AB have a timer-tuned operation function.
By using the simultaneous-start function, a timer operation in which the operation start timing and count up timing of the
master timer and slave timer are synchronized can be performed.
Only the PWM output mode can be used in the simultaneous-start function.
The combinations of timers that can use the simultaneous-start function are listed in Table 7-10.
Table 7-10. Timer Simultaneous-Start Function
Master Timer
Slave Timer
TAA1
TAA0
TAA3
TAA2
TAB0
TAA5
Figure 7-48 shows an example where individual operation and simultaneous-start operation of TAA0 (as the master
timer) and TAA1 (as the slave timer) are performed in PWM output mode.
Figure 7-48. Differences Between Individual Operation and Simultaneous-Start Operation Using TAA1 and TAA0
Individual operation
Simultaneous-start operation
TAA1 (master)
TAA1
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
16-bit timer/counter
TOAA10 (square
waveform output)
TOAA11 (PWM output)
TAA0
16-bit capture/compare
16-bit capture/compare
TAA0 (slave)
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
Simultaneous-start signal
16-bit timer/counter
TOAA00 (square
waveform output)
TOAA01 (PWM output)
If PWM operates separately with each timer,
the 16-bit counter starts and the PWM output
starts at a different timing for each timer.
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TOAA10 (square
waveform output)
TOAA11 (PWM output)
16-bit capture/compare
16-bit capture/compare
TOAA00 (square
waveform output)
TOAA01 (PWM output)
With the simultaneous-start function, PWM
output operates with the count start timing and
the count clock of both timers being synchronized.
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7.7.1
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
PWM output mode (simultaneous-start operation)
In this section, the operation of the simultaneous-start function is shown, where TAA1 is used as the master timer and
TAA0 is used as the slave timer.
The master timer (TAA1) and slave timer (TAA0) start operating at the same time when the TAA1CTL0.TAA0CE bit of
master timer is set to 1. The slave timer operates by the count clock supplied from the master timer (TAA1). After the
slave timer starts operating, however, the 16-bit counter of the slave timer (TAA0) is not cleared even if the 16-bit counter
of the master timer (TAA1) is cleared to 0000H upon a match between the 16-bit counter value of the master timer (TAA1)
and the TAA1CCR0 register value, because each timer operates individually.
In the same manner, if the compare register value of the master timer (TAA1) is rewritten by batch writing, the compare
register of the slave timer is not affected.
[Initial settings]
Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled)
Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled)
[Initial settings of master timer (TAA1)]
• TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 100 (setting of PMW output mode)
• TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any))
• TAA1CCR1, TAA1CCR0 (specification of valid edge of capture trigger)
• TAA1IOC0 (specification of valid edge of capture trigger)
[Initial settings of slave timer (TAA0)]
• TAA0CTL1.TAA0SYE = 1, TAA0SYM = 1 (simultaneous-start operation)
• TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 100 (setting of PMW output mode)
• TAA0CCR0, TAA1CCR1 (specification of valid edge of capture trigger)
• TAA0IOC0 (specification of valid edge of capture trigger)
Remark
The initial settings of the master timer and slave timer may be performed in any order.
[Starting counting]
Set TAA1CTL0.TAA1CE of the master timer to 1.
Start counting.
Changing the setting of the register during operation
• The compare register can be rewritten (anytime write).
[End condition]
• Set TAA1CTL0.TAA0CE of the master timer to 0.
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Figure 7-49. Timing Example of Simultaneous-Start Function (TAA1: Master, TAA0: Slave)
FFFFH
D11
TAA1
16-bit counter
D11
D10
D10
0000H
FFFFH
TAA0
16-bit counter
D01
D00
D01
D00
D01
D00
0000H
TAA1CE bit
TAA1CCR0 register
D10
TAA1CCR1 register
D11
INTTAA1CC0 interrupt
INTTAA1CC1 interrupt
TOAA10 pin output
TOAA11 pin output
TAA0CCR0 register
D00
TAA0CCR1 register
D01
INTTAA0CC0 interrupt
INTTAA0CC1 interrupt
TOAA00 pin output
TOAA01 pin output
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7.8
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Cascade Connection
This section explains an operation of connecting two channels of TAA in cascade to form a 32-bit capture timer.
For cascade connection, the free-running timer mode must be set and all the capture/compare registers must be set as
capture registers (TAA0CCSn = 1).
Combinations of TAA channels that can be connected in cascade are shown in the following table.
Table 7-11. Cascade Connection of TAA
Lower Timer (Master Timer)
Higher Timer (Slave Timer)
TAA1
TAA0
TAA3
TAA2
In the following example, TAA1 is used as the lower timer (master timer) and TAA0 is used as the higher timer (slave
timer) to use them as a 32-bit capture timer by cascade connection.
Figure 7-50. Cascade Connection Example
[Lower timer TAA1]
Capture signal 1
(TIAA11)
[Higher timer TAA0]
Lower capture interrupt 1
(INTTAA1CC1)
Edge
detection
Higher capture register 1
(TAA0CCR1)
Lower capture register 1
(TAA1CCR1)
Count
clock
selection
Lower timer counter
Operation enable
bit (TAA1CE)
FFFFH
detection
signal
Lower capture register 0
(TAA1CCR0)
Capture signal 0
(TIAA10)
Higher timer counter
Higher capture register 0
(TAA0CCR0)
Edge
detection
Lower capture interrupt 0
(INTTAA1CC0)
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Lower overflow interrupt
(INTTAA1OV)
Higher overflow interrupt
(INTTAA0OV)
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The operation of each pin and signal when TAA1 and TAA0 are connected in cascade is shown below.
Table 7-12. Status in Cascade Connection
Name
TIAA10 pin input
Higher/Lower
Lower
Function
Capture input 0
Operation
The value of the lower timer counter is stored in the
TAA1CCR0 register and the value of the higher timer
counter is stored in the TAA0CCR0 register when the
valid edge of this input is detected.
TIAA11 pin input
Lower
Capture input 1
The value of the lower timer counter is stored in the
TAA1CCR1 register and the value of the higher timer
counter is stored in the TAA0CCR1 register when the
valid edge of this input is detected.
INTTAA1CCR0 interrupt signal
Lower
Capture interrupt 0
This interrupt is generated when the valid edge of the
TIAA10 pin is detected.
INTTAA1CCR1 interrupt signal
Lower
Capture interrupt 1
This interrupt is generated when the valid edge of the
TIAA11 pin is detected.
INTTAA1OV interrupt signal
Lower
Overflow interrupt
This interrupt is generated when an overflow of the
lower timer counter is detected.
TIAA00 pin input
Higher
Capture input 0
Does not operate.
TIAA01 pin input
Higher
Capture input 1
Does not operate.
INTTAA0CCR0 interrupt signal
Higher
Capture interrupt 0
Does not operate.
INTTAA0CCR1 interrupt signal
Higher
Capture interrupt 1
Does not operate.
INTTAA0OV interrupt signal
Higher
Overflow interrupt
This interrupt is generated when an overflow of the
higher timer counter is detected.
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Figure 7-51. Operation Flow in Cascade Connection of TAA1 and TAA0 (1/2)
FFFFFFFFH
D1a1b
D0e0f
D1c1d
D0a0b
32-bit counter
D0g0h
D1e1f
D0c0d
00000000H
Operation enable bit
(TAA1CE)
TIAA10 input
Lower capture register 0
(TAA1CCR0)
0000
D 0b
D 0d
D 0f
D 0h
0000H
Higher capture register 0
(TAA0CCR0)
0000
D 0a
D 0c
D 0e
D 0g
0000H
Lower capture interrupt 0
(INTTAA1CC0)
Pulse interval Pulse interval Pulse interval
D0c0d − D0a0b D0e0f − D0c0d D0g0h − D0c0d
TIAA11 input
Lower capture register 1
(TAA1CCR1)
0000
D 1b
D1d
D 1f
0000H
Higher capture register 1
(TAA0CCR1)
0000
D 1a
D1c
D 1e
0000H
Lower capture interrupt 1
(INTTAA1CC1)
Pulse interval Pulse interval
D1c1d − D1a1b
D1e1f − D1c1d
Overflow interrupt
(INTTAA0OV)
Overflow flag
(TAA0OVF)
Cleared to 0 by
CLR instruction
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CLR instruction
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Figure 7-51. Operation Flow in Cascade Connection of TAA1 and TAA0 (2/2)
Capture 1 read flow
Count operation start flow
START
INTTAA0CCR1 generated?
Register initial setting
[Lower timer: TAA1]
TAA1CTL0 register
(TAA1CKS0 to TAA1CKS2 bits),
TAA1CTL1 register,
TAA1IOC1 register,
TAA1IOC2 register,
TAA1OPT0 register
[Higher timer: TAA0]
TAA0CTL1 register,
TAA0IOC1 register,
TAA0OPT0 register,
TAA0OPT1 register
TAA1CE bit = 1
Perform initial setting
of these registers
before TAA1CE bit = 1.
NO
YES
Executing instruction that clears
TAA0CCIC1.TAA0CCIF1 bit
(CLR TAA0CCIF1)
Reading TAA1CCR1 and
TAA0CCR1 registers
(reading capture register 0)
TAA1CKS0 to TAA1CKS2 bits
can be set as soon as counting
operation starts
(TAA1CE bit = 1).
TAA0CCIF1 = 0?
NO
YES
Calculating pulse interval
(Captured value − Previously
captured value)
Capture 0 read flow
Overflow flag clear flow
INTTAA0CCR0 generated?
NO
YES
Reading TAA0OPT0 register
(checking overflow flag)
Executing instruction that clears
TAA0CCIC0.TAA0CCIF0 bit
(CLR TAA0CCIF0)
Reading TAA1CCR0 and
TAA0CCR0 registers
(reading capture register 0)
TAA0OVF bit = 1
NO
YES
TAA1CCIF0 = 0?
NO
Executing instruction that clears
TAA0OVF bit (CLR TAA0OVF)
YES
Calculating pulse interval
(Captured value − Previously
captured value)
Count operation stop flow
TAA1CE bit = 0
Counter is initialized by
stopping counting operation
(TAA1CE bit = 0).
STOP
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Figure 7-52. Example of Basic Timing When TAA1 and TAA0 Are Connected in Cascade
FFFFFFFFH
D1a1b
D0e0f
D1c1d
D0a0b
32-bit counter
D0g0h
D1e1f
D0c0d
D0i0j
D1g1h
00000000H
Operation enable bit
(TAA1CE)
TIAA10 input
Lower capture register 0
(TAA1CCR0)
0000
D 0b
D 0d
D 0f
D 0h
D 0j
Higher capture register 0
(TAA0CCR0)
0000
D 0a
D 0c
D 0e
D 0g
D 0i
Lower capture interrupt 0
(INTTAA1CC0)
Pulse interval Pulse interval Pulse interval Pulse interval
D0c0d − D0a0b D0e0f − D0c0d D0g0h − D0c0d
D0i0j − D0g0h
TIAA11 input
Lower capture register 1
(TAA1CCR1)
0000
D 1b
D1d
D 1f
D 1h
Higher capture register 1
(TAA0CCR1)
0000
D 1a
D1c
D 1e
D 1g
Capture interrupt 1
(INTTAA1CC1)
Pulse interval Pulse interval Pulse interval
D1c1d − D1a1b
D1e1f − D1c1d
D1g1h − D1c1d
Overflow interrupt
(INTTAA0OV)
Overflow flag
(TAA0OVF)
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
The counting operation is started when the TAA1CTL.TAA1CE bit is set to 1 and the count clock is supplied.
When the valid edge input to the TIAA10 pin is detected, the count value is stored in the capture register 0
(TAA1CCR0 and TAA0CCR0), and capture interrupt 0 signal (INTTAA1CC0) is issued.
The timer counter continues the counting operation in synchronization with the count clock. When it counts
up to FFFFFFFFH, the overflow interrupt (INTTAA0OV) is generated at the next clock and the overflow flag
(TAA0OVF) is set to 1. The timer counter is cleared to 00000000H and continues counting up.
The overflow flag (TAA0OVF) is cleared by an instruction issued from the CPU that writes “0” to it.
Because the free-running timer mode is set, the timer counter cannot be cleared by detection of the valid
edge input to the TIAA10 pin.
Using TOAA10 output is prohibited because it alternately functions as the TIAA10 input.
Capture register 1 (TAA1CCR1 and TAA0CCR1) also operates in the same manner.
If the lower timer counter (TAA1) overflows, an overflow interrupt (TAA1OVF) is generated. However, it is
recommended to mask this interrupt because it cannot be used as an overflow interrupt of the 32-bit counter.
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7.9
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Selector Function
In the V850ES/JG3-H and V850ES/JH3-H, the alternate-function pins of ports or peripheral I/O (TAA1, TAB0, UARTC0,
or UARTC1) signals can be selected as the capture trigger input of TAA1 and TAB0.
If the signal input from the UARTCn pin is selected by the selector function when RXDCn is used, baud rate errors of
the LIN reception transfer rate of UARTCn can be calculated (n = 0, 1).
(1) Selector operation control register 0 (SELCNT0)
The SELCNT0 register is an 8-bit register that selects the capture trigger for CAN0, TAA1, and TAB0.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
SELCNT0
R/W
Address: FFFFF308H
7
6
5
4
3
2
1
0
0
0
0
ISEL4
ISEL3
0
0
ISEL0Note
ISEL4
Selection of TIAA11 capture trigger input signal
0
TIAA11 (alternately functions as P35) pin
1
RXDC1 (alternately functions as P91) pin
ISEL3
Selection of TIAA10 capture trigger input signal
0
TIAA10 (alternately functions as P34) pin
1
RXDC0 (alternately functions as P31) pin
ISEL0Note
Selection of TIAB02 capture trigger input signal
0
TIAB02 (alternately functions as P51) pin
1
CAN0 TSOUT signal
Note μPD70F3770 and 70F3771 only
Cautions 1. To set the ISEL4, ISEL3, and ISEL0 bits to 1, set the corresponding function pin to
the capture input mode.
2. Set the ISEL4, ISEL3, and ISEL0 bits when the operation of TAA1, TAB0, and
UARTC0, UARTC1, and CAN0 are stopped.
3. Be sure to set bits 7 to 5, 2, and 1 to “0”.
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7.10 Cautions
(1) Capture operation
When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be
captured in the TAAnCCR0 and TAAnCCR1 registers if the capture trigger is input immediately after the TAAnCE bit
is set to 1.
(a) Free-running timer mode
FFFFH
16-bit counter
0000H
Count clock
Sampling clock (fXX)
TAAnCCR0 register
0000H
FFFFH
0001H
TAAnCE bit
TIAAn0 pin input
Capture
trigger input
Capture
trigger input
(b) Pulse width measurement mode
FFFFH
16-bit counter
0000H
Count clock
Sampling clock (fXX)
TAAnCCR0 register
0000H
FFFFH
0002H
TAAnCE bit
TIAAn0 pin input
Capture
trigger input
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trigger input
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Timer AB (TAB) is a 16-bit timer/event counter.
The V850ES/JG3-H and V850ES/JH3-H have TAB0 and TAB1.
8.1
Overview
An outline of TABn is shown below.
• Clock selection: 8 ways
• Capture/trigger input pins: 4
• External event count input pins: 1
• External trigger input pins: 1
• Timer counters: 1
• Capture/compare registers: 4
• Capture/compare match interrupt request signals: 4
• Timer output pins: 4
Remark
8.2
n = 0, 1
Functions
TABn has the following functions.
• Interval timer
• External event counter
• External trigger pulse output
• One-shot pulse output
• PWM output
• Free-running timer
• Pulse width measurement
• Triangular wave PWM output
• Timer-tuned operation function
• Simultaneous-start function
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Configuration
TABn includes the following hardware.
Table 8-1. Configuration of TABn
Item
Configuration
16-bit counter
Registers
TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
TABn counter read buffer register (TABnCNT)
CCR0 to CCR3 buffer registers
TABn control registers 0, 1 (TABnCTL0, TABnCTL1)
TABn I/O control registers 0 to 2 (TABnIOC0 to TABnIOC2, TABnIOC4)
TABn option register 0 (TABnOPT0)
Timer inputs
Note 2
Note 2
Timer outputs
4 (TIABn0
Note 1
to TIABn3 pins)
4 (TOABn0 to TOABn3 pins)
Notes 1. When using the functions of the TIABn0 to TIABn3 and TOABn0 to TOABn3 pins, see Table 4-20
Using Port Pin as Alternate-Function Pin.
2. The TIAB00 pin functions alternately as a capture trigger input signal, external event count input
signal, and external trigger input signal.
Figure 8-1. Block Diagram of TABn
Internal bus
Selector
TABnCNT
Clear
CCR0
buffer
register
TIABn1
TIABn2
TIABn3
Edge detector
TIABn0
Note
INTTABnOV
16-bit counter
Output
controller
Selector
fXX
fXX/2
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
fXX/128
CCR1
buffer
register
CCR2
buffer
register
TABnCCR0
CCR3
buffer
register
TABnCCR1
TOABn0
TOABn1
TOABn2
TOABn3
INTTABnCC0
INTTABnCC1
INTTABnCC2
INTTABnCC3
TABnCCR2
TABnCCR3
Internal bus
Note TAB1: EVTAB1 pin and TRGAB1 pin
Remarks 1. fXX: Main clock frequency
2. n = 0, 1
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(1) 16-bit counter
This 16-bit counter can count internal clocks or external events.
The count value of this counter can be read by using the TABnCNT register.
When the TABnCTL0.TABnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TABnCNT register is read at
this time, 0000H is read.
Reset sets the TABnCE bit to 0. Therefore, the 16-bit counter is set to FFFFH.
(2) CCR0 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TABnCCR0 register is used as a compare register, the value written to the TABnCCR0 register is
transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0
buffer register, a compare match interrupt request signal (INTTABnCC0) is generated.
The CCR0 buffer register cannot be read or written directly.
The CCR0 buffer register is cleared to 0000H after reset, as the TABnCCR0 register is cleared to 0000H.
(3) CCR1 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TABnCCR1 register is used as a compare register, the value written to the TABnCCR1 register is
transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1
buffer register, a compare match interrupt request signal (INTTABnCC1) is generated.
The CCR1 buffer register cannot be read or written directly.
The CCR1 buffer register is cleared to 0000H after reset, as the TABnCCR1 register is cleared to 0000H.
(4) CCR2 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TABnCCR2 register is used as a compare register, the value written to the TABnCCR2 register is
transferred to the CCR2 buffer register. When the count value of the 16-bit counter matches the value of the CCR2
buffer register, a compare match interrupt request signal (INTTABnCC2) is generated.
The CCR2 buffer register cannot be read or written directly.
The CCR2 buffer register is cleared to 0000H after reset, as the TABnCCR2 register is cleared to 0000H.
(5) CCR3 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TABnCCR3 register is used as a compare register, the value written to the TABnCCR3 register is
transferred to the CCR3 buffer register. When the count value of the 16-bit counter matches the value of the CCR3
buffer register, a compare match interrupt request signal (INTTABnCC3) is generated.
The CCR3 buffer register cannot be read or written directly.
The CCR3 buffer register is cleared to 0000H after reset, as the TABnCCR3 register is cleared to 0000H.
(6) Edge detector
This circuit detects the valid edges input to the TIABn0 to TIABn3 pins. No edge, rising edge, falling edge, or both
the rising and falling edges can be selected as the valid edge by using the TABnIOC1 and TABnIOC2 registers.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(7) Output controller
This circuit controls the output of the TOABn0 to TOABn3 pins. The output controller is controlled by the TABnIOC0
register.
(8) Selector
This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can
be selected as the count clock.
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8.4
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Registers
The registers that control TABn are as follows.
• TABn control register 0 (TABnCTL0)
• TABn control register 1 (TABnCTL1)
• TABn I/O control register 0 (TABnIOC0)
• TABn I/O control register 1 (TABnIOC1)
• TABn I/O control register 2 (TABnIOC2)
• TABn I/O control register 4 (TABnIOC4)
• TABn option register 0 (TABnOPT0)
• TABn capture/compare register 0 (TABnCCR0)
• TABn capture/compare register 1 (TABnCCR1)
• TABn capture/compare register 2 (TABnCCR2)
• TABn capture/compare register 3 (TABnCCR3)
• TABn counter read buffer register (TABnCNT)
Remarks 1. When using the functions of the TIABn0 to TIABn3 and TOABn0 to TOABn3 pins, see Table 4-20 Using
Port Pin as Alternate-Function Pin.
2. n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(1) TABn control register 0 (TABnCTL0)
The TABnCTL0 register is an 8-bit register that controls the operation of TABn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Software can be used to always write the same value to the TABnCTL0 register.
After reset: 00H
TABnCTL0
R/W
Address:
TAB0CTL0 FFFFF540H, TAB1CTL0 FFFFF560H
7
6
5
4
3
TABnCE
0
0
0
0
2
1
0
TABnCKS2 TABnCKS1 TABnCKS0
(n = 0, 1)
TABnCE
TABn operation control
0
TABn operation disabled (TABn reset asynchronouslyNote).
1
TABn operation enabled. TABn operation started.
Internal count clock selection
TABnCKS2 TABnCKS1 TABnCKS0
0
0
0
fXX
0
0
1
fXX/2
0
1
0
fXX/4
0
1
1
fXX/8
1
0
0
fXX/16
1
0
1
fXX/32
1
1
0
fXX/64
1
1
1
fXX/128
Note TABnOPT0.TABnOVF bit, 16-bit counter, timer output (TOABn0 to TOABn3 pins)
Cautions 1. Set the TABnCKS2 to TABnCKS0 bits when the TABnCE bit = 0.
When the value of the TABnCE bit is changed from 0 to 1, the
TABnCKS2 to TABnCKS0 bits can be set simultaneously.
2. Be sure to set bits 3 to 6 to “0”.
Remark
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(2) TABn control register 1 (TABnCTL1)
The TABnCTL1 register is an 8-bit register that controls the operation of TABn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
7
TABnCTL1
(n = 0, 1)
0
R/W
6
Address: TAB0CTL1 FFFFF541H, TAB1CTL1 FFFFF561H
5
TABnEST TABnEEE
4
3
0
0
2
TABnEST
Software trigger control
0
−
1
1
0
TABnMD2 TABnMD1 TABnMD0
Generate a valid signal for external trigger input.
• In one-shot pulse output mode: A one-shot pulse is output with writing
1 to the TABnEST bit as the trigger.
• In external trigger pulse output mode: A PWM waveform is output with
writing 1 to the TABnEST bit as
the trigger.
Count clock selection
TABnEEE
0
Disable operation with external event count input.
(Perform counting with the count clock selected by the
TABnCTL0.TABnCK0 to TABnCTL0.TABnCK2 bits.)
1
Enable operation with external event count input.
(Perform counting at the valid edge of the external event count input
signal.)
The TABnEEE bit selects whether counting is performed with the internal count
clock or the valid edge of the external event count input.
TABnMD2 TABnMD1 TABnMD0
Timer mode selection
0
0
0
Interval timer mode
0
0
1
External event count mode
0
1
0
External trigger pulse output mode
0
1
1
One-shot pulse output mode
1
0
0
PWM output mode
1
0
1
Free-running timer mode
1
1
0
Pulse width measurement mode
1
1
1
Triangular wave PWM mode
Cautions 1. The TABnEST bit is valid only in the external trigger pulse output mode or
one-shot pulse output mode. In any other mode, writing 1 to this bit is
ignored.
2. Be sure to set bits 3, 4, and 7 to “0”.
3. External event count input is selected in the external event count mode
regardless of the value of the TABnEEE bit.
4. Set the TABnEEE and TABnMD2 to TABnMD0 bits when the
TABnCTL0.TABnCE bit = 0. (The same value can be written when the
TABnCE bit = 1.) The operation is not guaranteed when rewriting is
performed with the TABnCE bit = 1. If rewriting was mistakenly
performed, clear the TABnCE bit to 0 and then set the bits again.
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(3) TABn I/O control register 0 (TABnIOC0)
The TABnIOC0 register is an 8-bit register that controls the timer output (TOABn0 to TOABn3 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
6
7
TABnIOC0
Address:
TAB0IOC0 FFFFF542H, TAB1IOC0 FFFFF562H
5
4
3
2
1
0
TABnOL3 TABnOE3 TABnOL2 TABnOE2 TABnOL1 TABnOE1 TABnOL0 TABnOE0
(n = 0, 1)
TOABnm pin output level setting (m = 0 to 3)Note
TABnOLm
0
TOABnm pin high level start
1
TOABnm pin low level start
TOABnm pin output setting (m = 0 to 3)
TABnOEm
0
Timer output disabled
• When TABnOLm bit = 0: Low level is output from the TOABnm pin
• When TABnOLm bit = 1: High level is output from the TOABnm pin
1
Timer output enabled (a square wave is output from the TOABnm pin).
Note The output level of the timer output pin (TOABnm) specified by the
TABnOLm bit is shown below.
• When TABnOLm bit = 0
• When TABnOLm bit = 1
16-bit counter
16-bit counter
TABnCE bit
TABnCE bit
TOABnm output pin
TOABnm output pin
Cautions 1.
Rewrite the TABnOLm and TABnOEm bits when the
TABnCTL0.TABnCE bit = 0. (The same value can be written
when the TABnCE bit = 1.)
If rewriting was mistakenly
performed, clear the TABnCE bit to 0 and then set the bits
again.
2. Even if the TABnOLm bit is manipulated when the TABnCE
and TABnOEm bits are 0, the TOABnm pin output level varies.
Remark
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(4) TABn I/O control register 1 (TABnIOC1)
The TABnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIABn0
to TIABn3 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
7
R/W
Address:
6
5
TAB0IOC1 FFFFF543H, TAB1IOC1 FFFFF563H
4
3
2
1
0
TABnIOC1 TABnIS7 TABnIS6 TABnIS5 TABnIS4 TABnIS3 TABnIS2 TABnIS1 TABnIS0
(n = 0, 1)
TABnIS7 TABnIS6
Capture trigger input signal (TIABn3 pin) valid edge setting
0
0
No edge detection (capture operation invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
TABnIS5 TABnIS4 Capture trigger input signal (TIABn2 pin) valid edge detection
0
0
No edge detection (capture operation invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
TABnIS3 TABnIS2
Capture trigger input signal (TIABn1 pin) valid edge setting
0
0
No edge detection (capture operation invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
TABnIS1 TABnIS0
Capture trigger input signal (TIABn0 pin) valid edge setting
0
0
No edge detection (capture operation invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
Cautions 1. Rewrite
the
TABnIS7
to
TABnCTL0.TABnCE bit = 0.
TABnIS0
bits
when
the
(The same value can be
written when the TABnCE bit = 1.)
If rewriting was
mistakenly performed, clear the TABnCE bit to 0 and then
set the bits again.
2. The TABnIS7 to TABnIS0 bits are valid only in the freerunning timer mode and the pulse width measurement
mode.
In all other modes, a capture operation is not
possible.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(5) TABn I/O control register 2 (TABnIOC2)
The TABnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal
(TIAB00/EVTAB1 pin) and external trigger input signal (TIAB00/TRGAB1 pin).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
TABnIOC2
R/W
Address:
TAB0IOC2 FFFFF544H, TAB1IOC2 FFFFF564H
7
6
5
4
0
0
0
0
3
2
1
0
TABnEES1 TABnEES0 TABnETS1 TABnETS0
(n = 0, 1)
TABnEES1 TABnEES0 External event count input signal (TIAB00/EVTAB1 pin) valid edge setting
0
0
No edge detection (external event count invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
TABnETS1 TABnETS0 External trigger input signal (TIAB00/TRGAB1 pin) valid edge setting
0
0
No edge detection (external trigger invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
Cautions 1. Rewrite the TABnEES1, TABnEES0, TABnETS1, and
TABnETS0 bits when the TABnCTL0.TABnCE bit = 0. (The
same value can be written when the TABnCE bit = 1.) If
rewriting was mistakenly performed, clear the TABnCE bit
to 0 and then set the bits again.
2. The TABnEES1 and TABnEES0 bits are valid only when the
TABnCTL1.TABnEEE bit = 1 or when the external event
count mode (TABnCTL1.TABnMD2 to TABnCTL1.TABnMD0
bits = 001) has been set.
3. The TABnETS1 and TABnETS0 bits are valid only when the
external trigger pulse output mode (TABnCTL1.TABnMD2
to TABnCTL1.TABnMD0 bits = 010) or the one-shot pulse
output
mode
(TABnCTL1.TABnMD2
to
TABnCTL1.TABnMD0 = 011) is set.
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(6) TABn I/O control register 4 (TABnIOC4)
The TABnIOC4 register is an 8-bit register that controls the timer output.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H. This register is not reset by stopping the timer operation (TABnCTL0.TABnCE = 0).
Cautions 1. Accessing the TABnIOC4 register is prohibited in the following statuses. For details, see 3.4.9
(2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock
2. The TABnIOC4 register can be set only in the interval timer mode and free-running timer mode.
Be sure to set the TABnIOC4 register to 00H in all other modes (for details of the mode setting,
see 8.4 (2) TABn control register 1 (TABnCTL1)). Even in free-running timer mode, if the
TABnCCR0 to TABnCCR3 registers are set to the capture function, the setting of the
TABnIOC4 register becomes invalid.
After reset: 00H
7
TABnIOC4
(n = 0, 1)
R/W
6
Address:
TAB0IOC4 FFFFF550H, TAB1IOC4 FFFFF570H
5
4
3
2
1
0
TABnOS3 TABnOR3 TABnOS2 TABnOR2 TABnOS1 TABnOR1 TABnOS0 TABnOR0
TABnOSm TABnORm
Toggle control of TOABnm pin (m = 0 to 3)
0
0
No request. Normal toggle operation.
0
1
Reset request
Fix to inactive level upon next match between value of 16-bit
counter and value of TAAnCCRm register.
1
0
Set request
Fix to active level upon next match between value of 16-bit
counter and value of TAAnCCRm register.
1
1
Keep request
Keep the current output level.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(7) TABn option register 0 (TABnOPT0)
The TABnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address:
6
7
5
TAB0OPT0 FFFFF545H, TAB1OPT0 FFFFF565H
4
TABnOPT0 TABnCCS3 TABnCCS2 TABnCCS1 TABnCCS0
3
0
2
1
Note
TAB1CMS
0
TABnCUF TABnOVF
(n = 0, 1)
TABnCCSm
TABnCCRm register capture/compare selection
0
Compare register selected
1
Capture register selected
The TABnCCSm bit setting is valid only in the free-running timer mode.
TABnOVF
TABn overflow detection
Set (1)
Overflow occurred
Reset (0)
TABnOVF bit 0 written or TABnCTL0.TABnCE bit = 0
• The TABnOVF bit is set to 1 when the 16-bit counter count value overflows from
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
• An interrupt request signal (INTTABnOV) is generated at the same time that the
TABnOVF bit is set to 1. The INTTABnOV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
• The TABnOVF bit is not cleared even when the TABnOVF bit or the TABnOPT0
register are read when the TABnOVF bit = 1.
• The TABnOVF bit can be both read and written, but the TABnOVF bit cannot be
set to 1 by software. Writing 1 has no effect on the operation of TABn.
Note The TAB1CMS bit is used for the motor control function. For details,
see CHAPTER 11 MOTOR CONTROL FUNCTION.
Cautions 1. Rewrite the TABnCCS3 to TABnCCS0 bits when the
TABnCTL0.TABnCE bit = 0.
(The same value can be
written when the TABnCE bit = 1.)
If rewriting was
mistakenly performed, clear the TABnCE bit to 0 and then
set the bits again.
2. Be sure to set bit 3 to “0”.
When the motor control
function is not used, be sure to also set bit 2 to “0”.
Remark
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(8) TABn capture/compare register 0 (TABnCCR0)
The TABnCCR0 register can be used as a capture register or a compare register depending on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
according to the setting of the TABnOPT0.TABnCCS0 bit. In the pulse width measurement mode, the TABnCCR0
register can be used only as a capture register. In any other mode, this register can be used only as a compare
register.
The TABnCCR0 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution
Accessing the TABnCCR0 register is prohibited in the following statuses. For details, see 3.4.9
(2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock
After reset: 0000H
15
14
R/W
13
12
Address:
11
10
TAB0CCR0 FFFFF546H, TAB1CCR0 FFFFF566H
9
8
7
6
5
4
3
2
1
0
TABnCCR0
(n = 0, 1)
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(a) Function as compare register
The TABnCCR0 register can be rewritten even when the TABnCTL0.TABnCE bit = 1.
The set value of the TABnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal
(INTTABnCC0) is generated. If TOABn0 pin output is enabled at this time, the output of the TOABn0 pin is
inverted.
When the TABnCCR0 register is used as a cycle register in the interval timer mode, external event count mode,
external trigger pulse output mode, one-shot pulse output mode, PWM output mode, or triangular wave PWM
mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer
register.
(b) Function as capture register
When the TABnCCR0 register is used as a capture register in the free-running timer mode, the count value of
the 16-bit counter is stored in the TABnCCR0 register if the valid edge of the capture trigger input pin (TIABn0
pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the
TABnCCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin
(TIABn0 pin) is detected.
Even if the capture operation and reading the TABnCCR0 register conflict, the correct value of the TABnCCR0
register can be read.
Remark
n = 0, 1
The following table shows the functions of the capture/compare register in each mode, and how to write data to the
compare register.
Table 8-2. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
Capture/Compare Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
−
Triangular wave PWM mode
Compare register
Batch write
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(9) TABn capture/compare register 1 (TABnCCR1)
The TABnCCR1 register can be used as a capture register or a compare register depending on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
according to the setting of the TABnOPT0.TABnCCS1 bit. In the pulse width measurement mode, the TABnCCR1
register can be used only as a capture register. In any other mode, this register can be used only as a compare
register.
The TABnCCR1 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution
Accessing the TABnCCR1 register is prohibited in the following statuses. For details, see 3.4.9
(2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock
After reset: 0000H
15
14
R/W
13
12
Address:
11
10
TAB0CCR1 FFFFF548H, TAB1CCR1 FFFFF568H
9
8
7
6
5
4
3
2
1
0
TABnCCR1
(n = 0, 1)
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(a) Function as compare register
The TABnCCR1 register can be rewritten even when the TABnCTL0.TABnCE bit = 1.
The set value of the TABnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal
(INTTABnCC1) is generated. If TOABn1 pin output is enabled at this time, the output of the TOABn1 pin is
inverted.
(b) Function as capture register
When the TABnCCR1 register is used as a capture register in the free-running timer mode, the count value of
the 16-bit counter is stored in the TABnCCR1 register if the valid edge of the capture trigger input pin (TIABn1
pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the
TABnCCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin
(TIABn1 pin) is detected.
Even if the capture operation and reading the TABnCCR1 register conflict, the correct value of the TABnCCR1
register can be read.
Remark
n = 0, 1
The following table shows the functions of the capture/compare register in each mode, and how to write data to the
compare register.
Table 8-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
Capture/Compare Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
−
Triangular wave PWM mode
Compare register
Batch write
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(10) TABn capture/compare register 2 (TABnCCR2)
The TABnCCR2 register can be used as a capture register or a compare register depending on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
according to the setting of the TABnOPT0.TABnCCS2 bit. In the pulse width measurement mode, the TABnCCR2
register can be used only as a capture register. In any other mode, this register can be used only as a compare
register.
The TABnCCR2 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution
Accessing the TABnCCR2 register is prohibited in the following statuses. For details, see 3.4.9
(2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
After reset: 0000H
15
14
R/W
13
12
Address:
11
10
TAB0CCR2 FFFFF54AH, TAB1CCR2 FFFFF56AH
9
8
7
6
5
4
3
2
1
0
TABnCCR2
(n = 0, 1)
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(a) Function as compare register
The TABnCCR2 register can be rewritten even when the TABnCTL0.TABnCE bit = 1.
The set value of the TABnCCR2 register is transferred to the CCR2 buffer register. When the value of the 16bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal
(INTTABnCC2) is generated. If TOABn2 pin output is enabled at this time, the output of the TOABn2 pin is
inverted.
(b) Function as capture register
When the TABnCCR2 register is used as a capture register in the free-running timer mode, the count value of
the 16-bit counter is stored in the TABnCCR2 register if the valid edge of the capture trigger input pin (TIABn2
pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the
TABnCCR2 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin
(TIABn2 pin) is detected.
Even if the capture operation and reading the TABnCCR2 register conflict, the correct value of the TABnCCR2
register can be read.
Remark
n = 0, 1
The following table shows the functions of the capture/compare register in each mode, and how to write data to the
compare register.
Table 8-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
Capture/Compare Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
−
Triangular wave PWM mode
Compare register
Batch write
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(11) TABn capture/compare register 3 (TABnCCR3)
The TABnCCR3 register can be used as a capture register or a compare register depending on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
according to the setting of the TABnOPT0.TABnCCS3 bit. In the pulse width measurement mode, the TABnCCR3
register can be used only as a capture register. In any other mode, this register can be used only as a compare
register.
The TABnCCR3 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution
Accessing the TABnCCR3 register is prohibited in the following statuses. For details, see 3.4.9
(2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
After reset: 0000H
15
14
R/W
13
12
Address:
11
10
TAB0CCR3 FFFFF54CH, TAB1CCR3 FFFFF56CH
9
8
7
6
5
4
3
2
1
0
TABnCCR3
(n = 0, 1)
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(a) Function as compare register
The TABnCCR3 register can be rewritten even when the TABnCTL0.TABnCE bit = 1.
The set value of the TABnCCR3 register is transferred to the CCR3 buffer register. When the value of the 16bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal
(INTTABnCC3) is generated. If TOABn3 pin output is enabled at this time, the output of the TOABn3 pin is
inverted.
(b) Function as capture register
When the TABnCCR3 register is used as a capture register in the free-running timer mode, the count value of
the 16-bit counter is stored in the TABnCCR3 register if the valid edge of the capture trigger input pin (TIABn3
pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the
TABnCCR3 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin
(TIABn3 pin) is detected.
Even if the capture operation and reading the TABnCCR3 register conflict, the correct value of the TABnCCR3
register can be read.
Remark
n = 0, 1
The following table shows the functions of the capture/compare register in each mode, and how to write data to the
compare register.
Table 8-5. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
Capture/Compare Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
−
Triangular wave PWM mode
Compare register
Batch write
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(12) TABn counter read buffer register (TABnCNT)
The TABnCNT register is a read buffer register that can read the count value of the 16-bit counter.
If this register is read when the TABnCTL0.TABnCE bit = 1, the count value of the 16-bit timer can be read.
This register is read-only in 16-bit units.
The value of the TABnCNT register is cleared to 0000H when the TABnCE bit = 0. If the TABnCNT register is read
at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read.
The value of the TABnCNT register is cleared to 0000H after reset, as the TABnCE bit is cleared to 0.
Caution
Accessing the TABnCNT register is prohibited in the following statuses. For details, see 3.4.9 (2)
Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
After reset: 0000H
15
14
R/W
13
12
Address:
11
10
TAB0CCR0 FFFFF546H, TAB1CCR0 FFFFF566H
9
8
7
6
5
4
3
2
1
0
TABnCCR0
(n = 0, 1)
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8.5
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Operation
TABn can perform the following operations.
Operation
Interval timer mode
External event count mode
Note 1
External trigger pulse output mode
One-shot pulse output mode
Note 2
Note 2
PWM output mode
Free-running timer mode
Pulse width measurement mode
Note 2
Triangular wave PWM mode
TABnCTL1.TABnEST Bit
TIABn0 Pin
Capture/Compare
Compare Register
(Software Trigger Bit)
(External Trigger Input)
Register Setting
Write
Invalid
Invalid
Compare only
Anytime write
Invalid
Invalid
Compare only
Anytime write
Valid
Valid
Compare only
Batch write
Valid
Valid
Compare only
Anytime write
Invalid
Invalid
Compare only
Batch write
Invalid
Invalid
Switching enabled
Anytime write
Invalid
Invalid
Capture only
Not applicable
Invalid
Invalid
Compare only
Batch write
Notes 1. To use the external event count mode, specify that the valid edge of the TIABn0 pin capture trigger input is
not detected (by clearing the TABnIOC1.TABnIS1 and TABnIOC1.TABnIS0 bits to “00”).
2. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width
measurement mode, select the internal clock as the count clock (by clearing the TABnCTL1.TABnEEE bit to
0).
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Interval timer mode (TABnMD2 to TABnMD0 bits = 000)
In the interval timer mode, an interrupt request signal (INTTABnCC0) is generated at the specified interval if the
TABnCTL0.TABnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOABn0
pin.
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the interval timer mode.
Figure 8-2. Configuration of Interval Timer
Clear
Count clock
selection
Output
controller
16-bit counter
Match signal
TABnCE bit
TOABn0 pin
INTTABnCC0 signal
CCR0 buffer register
TABnCCR0 register
Remark
n = 0, 1
Figure 8-3. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
D0
D0
D0
D0
0000H
TABnCE bit
TABnCCR0 register
D0
TOABn0 pin output
INTTABnCC0 signal
Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1)
Remark
n = 0, 1
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When the TABnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
with the count clock, and the counter starts counting. At this time, the output of the TOABn0 pin is inverted. Additionally,
the set value of the TABnCCR0 register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, the output of the TOABn0 pin is inverted, and a compare match interrupt request signal (INTTABnCC0) is
generated.
The interval can be calculated by the following expression.
Interval = (Set value of TABnCCR0 register + 1) × Count clock cycle
Figure 8-4. Register Setting for Interval Timer Mode Operation (1/2)
(a) TABn control register 0 (TABnCTL0)
TABnCE
CTL0
0/1
TABnCKS2 TABnCKS1 TABnCKS0
0
0
0
0
0/1
0/1
0/1
Select count clock
0: Stop counting
1: Enable counting
(b) TABn control register 1 (TABnCTL1)
TABnSYE TABnEST TABnEEE
CTL1
0
0
Note
0/1
TABnMD2 TABnMD1 TABnMD0
0
0
0
0
0
0, 0, 0:
Interval timer mode
0: Operate on count
clock selected by bits
TABnCKS0 to TABnCKS2
1: Count with external
event count input signal
Note
This bit can be set to 1 only when the interrupt request signals (INTTABnCC0 and INTTABnCCk) are
masked by the interrupt mask flags (TABnCCMK0 to TABnCCMKk) and the timer output (TOABnk) is
performed at the same time. However, the TABnCCR0 and TABnCCRk registers must be set to the
same value (see 8.5.1 (2) (d) Operation of TABnCCR1 to TABnCCR3 registers) (k = 1 to 3).
Remark
n = 0, 1
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Figure 8-4. Register Setting for Interval Timer Mode Operation (2/2)
(c) TABn I/O control register 0 (TABnIOC0)
TABnOL3 TABnOE3 TABnOL2 TABnOE2 TABnOL1 TABnOE1 TABnOL0 TABnOE0
TABnIOC0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0: Disable TOABn0 pin output
1: Enable TOABn0 pin output
Setting of output level with
operation of TOABn0 pin disabled
0: Low level
1: High level
0: Disable TOABn1 pin output
1: Enable TOABn1 pin output
Setting of output level with
operation of TOABn1 pin disabled
0: Low level
1: High level
0: Disable TOABn2 pin output
1: Enable TOABn2 pin output
Setting of output level with
operation of TOABn2 pin disabled
0: Low level
1: High level
0: Disable TOABn3 pin output
1: Enable TOABn3 pin output
Setting of output level with
operation of TOABn3 pin disabled
0: Low level
1: High level
(d) TABn counter read buffer register (TABnCNT)
By reading the TABnCNT register, the count value of the 16-bit counter can be read.
(e) TABn capture/compare register 0 (TABnCCR0)
If the TABnCCR0 register is set to D0, the interval is as follows.
Interval = (D0 + 1) × Count clock cycle
(f) TABn capture/compare registers 1 to 3 (TABnCCR1 to TABnCCR3)
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the interval timer mode. However, the set
value of the TABnCCR1 to TABnCCR3 registers is transferred to the CCR1 to CCR3 buffer
registers. The compare match interrupt request signals (INTTABnCCR1 to INTTABnCCR3) are
generated when the count value of the 16-bit counter matches the value of the CCR1 to CCR3
buffer registers.
Therefore, mask the interrupt requests by using the corresponding interrupt mask flags (TABnCCMK1 to
TABnCCMK3).
Remarks 1. TABn I/O control register 1 (TABnIOC1), TABn I/O control register 2 (TABnIOC2), and
TABn option register 0 (TABnOPT0) are not used in the interval timer mode.
2. n = 0, 1
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(1) Interval timer mode operation flow
Figure 8-5. Software Processing Flow in Interval Timer Mode
FFFFH
D0
16-bit counter
D0
D0
0000H
TABnCE bit
TABnCCR0 register
D0
TOABn0 pin output
INTTABnCC0 signal
Count operation start flow
START
Register initial setting
TABnCTL0 register
(TABnCKS0 to TABnCKS2 bits)
TABnCTL1 register,
TABnIOC0 register,
TABnCCR0 register
TABnCE bit = 1
The initial setting of these registers is performed
before setting the TABnCE bit to 1.
The TABnCKS0 to TABnCKS2 bits can be
set at the same time when counting has
been started (TABnCE bit = 1).
Count operation stop flow
TABnCE bit = 0
The counter is initialized and counting is
stopped by clearing the TABnCE bit to 0.
STOP
Remark
n = 0, 1
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(2) Interval timer mode operation timing
(a) Operation if TABnCCR0 register is set to 0000H
If the TABnCCR0 register is set to 0000H, the INTTABnCC0 signal is generated at each count clock
subsequent to the first count clock, and the output of the TOABn0 pin is inverted.
The value of the 16-bit counter is always 0000H.
Count clock
16-bit counter
FFFFH
0000H
0000H
0000H
0000H
TABnCE bit
TABnCCR0 register
0000H
TOABn0 pin output
INTTABnCC0 signal
Interval time
Count clock cycle
Remark
Interval time
Count clock cycle
n = 0, 1
(b) Operation if TABnCCR0 register is set to FFFFH
If the TABnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to
0000H in synchronization with the next count-up timing. The INTTABnCC0 signal is generated and the output
of the TOABn0 pin is inverted. At this time, an overflow interrupt request signal (INTTABnOV) is not generated,
nor is the overflow flag (TABnOPT0.TABnOVF bit) set to 1.
FFFFH
16-bit counter
0000H
TABnCE bit
TABnCCR0 register
FFFFH
TOABn0 pin output
INTTABnCC0 signal
Interval time
Interval time
Interval time
10000H ×
10000H ×
10000H ×
count clock cycle count clock cycle count clock cycle
Remark
n = 0, 1
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(c) Notes on rewriting TABnCCR0 register
To change the value of the TABnCCR0 register to a smaller value, stop counting once and then change the set
value.
If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
D1
D1
16-bit counter
D2
D2
D2
0000H
TABnCE bit
D1
TABnCCR0 register
TABnOL0 bit
D2
L
TOABn0 pin output
INTTABnCC0 signal
Interval time (1)
Interval time (NG)
Interval
time (2)
Remarks 1. Interval time (1): (D1 + 1) × Count clock cycle
Interval time (NG):
(10000H + D2 + 1) × Count clock cycle
Interval time (2): (D2 + 1) × Count clock cycle
2. n = 0, 1
If the value of the TABnCCR0 register is changed from D1 to D2 while the count value is greater than D2 but
less than D1, the count value is transferred to the CCR0 buffer register as soon as the TABnCCR0 register has
been rewritten. Consequently, the value of the 16-bit counter that is compared is D2.
Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows,
and then counts up again from 0000H.
When the count value matches D2, the INTTABnCC0 signal is
generated and the output of the TOABn0 pin is inverted.
Therefore, the INTTABnCC0 signal may not be generated at the interval time “(D1 + 1) × Count clock cycle” or
“(D2 + 1) × Count clock cycle” originally expected, but may be generated at an interval of “(10000H + D2 + 1) ×
Count clock period”.
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(d) Operation of TABnCCR1 to TABnCCR3 registers
Figure 8-6. Configuration of TABnCCR1 to TABnCCR3 Registers
TABnCCR1
register
CCR1 buffer
register
Output
controller
Match signal
TOABn1 pin
INTTABnCC1 signal
TABnCCR2
register
Output
controller
CCR2 buffer
register
Match signal
TOABn2 pin
INTTABnCC2 signal
TABnCCR3
register
CCR3 buffer
register
Output
controller
Match signal
TOABn3 pin
INTTABnCC3 signal
Clear
Count
clock
selection
16-bit counter
Match signal
TABnCE bit
Output
controller
TOABn0 pin
INTTABnCC0 signal
CCR0 buffer register
TABnCCR0 register
Remark
n = 0, 1
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If the set value of the TABnCCRk register is less than the set value of the TABnCCR0 register, the
INTTABnCCk signal is generated once per cycle. At the same time, the output of the TOABnk pin is inverted.
The TOABnk pin outputs a square wave with the same cycle as that output by the TOABn0 pin.
Remark
k = 1 to 3,
n = 0, 1
Figure 8-7. Timing Chart When D01 ≥ Dk1
FFFFH
16-bit counter
D01
D31
D11
D21
D01
D31
D11
D21
D01
D31
D11
D21
D01
D31
D11
D21
0000H
TABnCE bit
TABnCCR0 register
D01
TOABn0 pin output
INTTABnCC0 signal
TABnCCR1 register
D11
TOABn1 pin output
INTTABnCC1 signal
TABnCCR2 register
D21
TOABn2 pin output
INTTABnCC2 signal
TABnCCR3 register
D31
TOABn3 pin output
INTTABnCC3 signal
Remark
n = 0, 1
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If the set value of the TABnCCRk register is greater than the set value of the TABnCCR0 register, the count
value of the 16-bit counter does not match the value of the TABnCCRk register.
Consequently, the
INTTABnCCk signal is not generated, nor is the output of the TOABnk pin changed.
Remark
k = 1 to 3,
n = 0, 1
Figure 8-8. Timing Chart When D01 < Dk1
FFFFH
D01
D01
D01
D01
16-bit counter
0000H
TABnCE bit
D01
TABnCCR0 register
TOABn0 pin output
INTTABnCC0 signal
TABnCCR1 register
D11
TOABn1 pin output
INTTABnCC1 signal
L
D21
TABnCCR2 register
TOABn2 pin output
INTTABnCC2 signal
L
D31
TABnCCR3 register
TOABn3 pin output
INTTABnCC3 signal
Remark
L
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
External event count mode (TABnMD2 to TABnMD0 bits = 001)
In the external event count mode, the valid edge of the external event count input is counted when the
TABnCTL0.TABnCE bit is set to 1, and an interrupt request signal (INTTABnCC0) is generated each time the specified
number of edges have been counted. The TOABn0 pin cannot be used.
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the external event count mode.
Figure 8-9. Configuration in External Event Count Mode
Clear
TIAB00 pinNote
(external event
count input)
Edge
detector
16-bit counter
Match signal
TABnCE bit
INTTABnCC0 signal
CCR0 buffer register
TABnCCR0 register
Note
TAB1: EVTAB1 pin
Figure 8-10. Basic Timing in External Event Count Mode
FFFFH
D0
16-bit counter
D0
D0
0000H
16-bit counter
TABnCE bit
External event
count input
(TIAB00 pin input)Note
TABnCCR0 register
TABnCCR0 register
D0
D0
0000
0001
D0
INTTABnCC0 signal
INTTABnCC0 signal
External
event
count
interval
(D0 + 1)
Note
D0 − 1
External
event
count
interval
(D0 + 1)
External
event
count
interval
(D0 + 1)
TAB1: EVTAB1 pin
Remark
This figure shows the basic timing when the rising edge is specified as the valid edge of the
external event count input.
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When the TABnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts
each time the valid edge of the external event count input is detected. Additionally, the set value of the TABnCCR0 register
is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, and a compare match interrupt request signal (INTTABnCC0) is generated.
The INTTABnCC0 signal is generated each time the valid edge of the external event count input has been detected (set
value of TABnCCR0 register + 1) times.
Figure 8-11. Register Setting for Operation in External Event Count Mode (1/2)
(a) TABn control register 0 (TABnCTL0)
TABnCE
TABnCTL0
TABnCKS2 TABnCKS1 TABnCKS0
0/1
0
0
0
0
0
0
0
0: Stop counting
1: Enable counting
(b) TABn control register 1 (TABnCTL1)
TABnSYE TABnEST TABnEEE
TABnCTL1
0
0
TABnMD2 TABnMD1 TABnMD0
0
0
0
0
0
1
0, 0, 1:
External event count mode
(c) TABn I/O control register 0 (TABnIOC0)
TABnOL3 TABnOE3 TABnOL2 TABnOE2 TABnOL1 TABnOE1 TABnOL0 TABnOE0
TABnIOC0
0
0
0
0
0
0
0
0
0: Disable TOABn0 pin output
0: Disable TOABn1 pin output
0: Disable TOABn2 pin output
0: Disable TOABn3 pin output
(d) TABn I/O control register 2 (TABnIOC2)
TABnEES1 TABnEES0 TABnETS1 TABnETS0
TABnIOC2
0
0
0
0
0/1
0/1
0
0
Select valid edge
of external event
count input
Remark
n = 0, 1
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Figure 8-11. Register Setting for Operation in External Event Count Mode (2/2)
(e) TABn counter read buffer register (TABnCNT)
The count value of the 16-bit counter can be read by reading the TABnCNT register.
(f) TABn capture/compare register 0 (TABnCCR0)
If D0 is set to the TABnCCR0 register, the counter is cleared and a compare match interrupt request
signal (INTTABnCC0) is generated when the number of external event counts reaches (D0 + 1).
(g) TABn capture/compare registers 1 to 3 (TABnCCR1 to TABnCCR3)
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the external event count mode. However,
the set value of the TABnCCR1 to TABnCCR3 registers are transferred to the CCR1 to CCR3
buffer registers. When the count value of the 16-bit counter matches the value of the CCR1 to
CCR3 buffer registers, compare match interrupt request signals (INTTABnCC1 to INTTABnCC3)
are generated.
Therefore, mask the interrupt signals by using the interrupt mask flags (TABnCCMK1 to TABnCCMK3).
Caution
For TAB0, when an external clock is used as the count clock, the external clock can be input
only from the TIAB00 pin. At this time, set the TAB0IOC1.TAB0IS1 and TAB0IOC1.TAB0IS0
bits to 00 (capture trigger input (TIAB00 pin): no edge detection).
Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are
not used in the external event count mode.
2. n = 0, 1
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(1) External event count mode operation flow
Figure 8-12. Flow of Software Processing in External Event Count Mode
FFFFH
D0
16-bit counter
D0
D0
0000H
TABnCE bit
TABnCCR0 register
D0
INTTABnCC0 signal
Count operation start flow
START
Register initial setting
TABnCTL0 register
(TABnCKS0 to TABnCKS2 bits)
TABnCTL1 register,
TABnIOC0 register,
TABnIOC2 register,
TABnCCR0 register
TABnCE bit = 1
The initial setting of these registers
is performed before setting the
TABnCE bit to 1.
The TABnCKS0 to TABnCKS2 bits can
be set at the same time when counting
has been started (TABnCE bit = 1).
Count operation stop flow
TABnCE bit = 0
The counter is initialized and counting
is stopped by clearing the TABnCE bit to 0.
STOP
Remark
n = 0, 1
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(2) Operation timing in external event count mode
Cautions 1. In the external event count mode, do not set the TABnCCR0 register to 0000H.
2. In the external event count mode, use of the timer output is disabled. If performing timer
output using external event count input, set the interval timer mode, and select the operation
enabled by the external event count input for the count clock (TABnCTL1.TABnMD2 to
TABnCTL1.TABnMD0 bits = 000, TABnCTL1.TABnEEE bit = 1).
(a) Operation if TABnCCR0 register is set to FFFFH
If the TABnCCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the
external event count signal has been detected. The 16-bit counter is cleared to 0000H in synchronization with
the next count-up timing, and the INTTABnCC0 signal is generated. At this time, the TABnOPT0.TABnOVF bit
is not set.
FFFFH
16-bit counter
0000H
TABnCE bit
TABnCCR0 register
FFFFH
INTTABnCC0 signal
External event
count signal
interval
Remark
External event
count signal
interval
External event
count signal
interval
n = 0, 1
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(b) Notes on rewriting the TABnCCR0 register
To change the value of the TABnCCR0 register to a smaller value, stop counting once and then change the set
value.
If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
D1
16-bit counter
D1
D2
D2
D2
0000H
TABnCE bit
D1
TABnCCR0 register
D2
INTTABnCC0 signal
External event
count signal
interval (1)
(D1 + 1)
Remark
External event count signal
interval (NG)
(10000H + D2 + 1)
External event
count signal
interval (2)
(D2 + 1)
n = 0, 1
If the value of the TABnCCR0 register is changed from D1 to D2 while the count value is greater than D2 but
less than D1, the count value is transferred to the CCR0 buffer register as soon as the TABnCCR0 register has
been rewritten. Consequently, the value that is compared with the 16-bit counter is D2.
Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows,
and then counts up again from 0000H.
When the count value matches D2, the INTTABnCC0 signal is
generated.
Therefore, the INTTABnCC0 signal may not be generated at the valid edge count of “(D1 + 1) times” or “(D2 + 1)
times” originally expected, but may be generated at the valid edge count of “(10000H + D2 + 1) times”.
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(c) Operation of TABnCCR1 to TABnCCR3 registers
Figure 8-13. Configuration of TABnCCR1 to TABnCCR3 Registers
TABnCCR1
register
CCR1 buffer
register
Match signal
INTTABnCC1 signal
TABnCCR2
register
CCR2 buffer
register
Match signal
INTTABnCC2 signal
TABnCCR3
register
CCR3 buffer
register
Match signal
INTTABnCC3 signal
Clear
Edge
detector
TIAB00 pinNote
16-bit counter
Match signal
TABnCE bit
INTTABnCC0 signal
CCR0 buffer register
TABnCCR0 register
Note
TAB1: EVTAB1 pin
Remark
n = 0, 1
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If the set value of the TABnCCRk register is smaller than the set value of the TABnCCR0 register, the
INTTABnCCk signal is generated once per cycle.
Remark
k = 1 to 3,
n = 0, 1
Figure 8-14. Timing Chart When D01 ≥ Dk1
FFFFH
16-bit counter
D01
D31
D11
D21
D01
D31
D11
D21
D01
D31
D11
D21
D01
D31
D11
D21
0000H
TABnCE bit
TABnCCR0 register
D01
INTTABnCC0 signal
TABnCCR1 register
D11
INTTABnCC1 signal
TABnCCR2 register
D21
INTTABnCC2 signal
TABnCCR3 register
D31
INTTABnCC3 signal
Remark
n = 0, 1
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If the set value of the TABnCCRk register is greater than the set value of the TABnCCR0 register, the
INTTABnCCk signal is not generated because the count value of the 16-bit counter and the value of the
TABnCCRk register do not match.
Remark
k = 1 to 3,
n = 0, 1
Figure 8-15. Timing Chart When D01 < Dk1
FFFFH
D01
D01
D01
D01
16-bit counter
0000H
TABnCE bit
D01
TABnCCR0 register
INTTABnCC0 signal
TABnCCR1 register
INTTABnCC1 signal
D11
L
TABnCCR2 register
INTTABnCC2 signal
D21
L
TABnCCR3 register
INTTABnCC3 signal
Remark
D31
L
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
External trigger pulse output mode (TABnMD2 to TABnMD0 bits = 010)
In the external trigger pulse output mode, TABn waits for a trigger when the TABnCTL0.TABnCE bit is set to 1. When
the valid edge of the external trigger input signal is detected, TABn starts counting, and outputs a PWM waveform from the
TOABn1 to TOABn3 pins.
Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software
trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOABn0 pin.
Figure 8-16. Configuration in External Trigger Pulse Output Mode
TABnCCR1
register
Transfer
Output
S
controller
R (RS-FF)
CCR1 buffer
register
Match signal
TOABn1 pin
INTTABnCC1 signal
TABnCCR2
register
Transfer
S Output
R controller
CCR2 buffer
register
Match signal
TOABn2 pin
INTTABnCC2 signal
TABnCCR3
register
Transfer
Edge
detector
TIAB00 pinNote
CCR3 buffer
register
Software trigger
generation
Output
S
controller
R (RS-FF)
Match signal
TOABn3 pin
INTTABnCC3 signal
Clear
Count
clock
selection
Count
start
control
16-bit counter
Output
controller
Match signal
TABnCE bit
TOABn0 pin
INTTABnCC0 signal
CCR0 buffer register
Transfer
TABnCCR0 register
Note
TAB1: TRGAB1 pin
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Figure 8-17. Basic Timing in External Trigger Pulse Output Mode
FFFFH
D0
D3
D3
D2
16-bit counter
D0
D3
D2
D1
D0
D3
D2
D1
D1
D1
D0
D2
D1
0000H
TABnCE bit
External trigger input
(TIAB00 pin input)Note
TABnCCR0 register
D0
INTTABnCC0 signal
TOABn0 pin output
(only when software
trigger is used)
D1
TABnCCR1 register
INTTABnCC1 signal
TOABn1 pin output
Active level
width
(D1)
Active level
width
(D1)
Active level Active level
width
width
(D1)
(D1)
TABnCCR2 register
Active level
width
(D1)
D2
INTTABnCC2 signal
TOABn2 pin output
Active level
width (D2)
Active level
width (D2)
TABnCCR3 register
Active level
width (D2)
D3
INTTABnCC3 signal
TOABn3 pin output
Active level
width (D3)
Wait Cycle (D0 + 1)
for trigger
Note
Active level
width (D3)
Cycle (D0 + 1)
Active level
width (D3)
Cycle (D0 + 1)
TAB1: TRGAB1 pin
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
TABn waits for a trigger when the TABnCE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared
from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOABnk pin. If the trigger
is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the
TOABn0 pin is inverted. The TOABnk pin outputs a high level regardless of the status (high/low) when a trigger is
generated.)
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TABnCCRk register) × Count clock cycle
Cycle = (Set value of TABnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TABnCCRk register)/(Set value of TABnCCR0 register + 1)
The compare match request signal (INTTABnCC0) is generated when the 16-bit counter counts up next time after its
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal (INTTABnCCk) is generated when the count value of the 16-bit counter matches the value
of the CCRk buffer register.
The value set to the TABnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H.
The valid edge of the external trigger input signal or setting the software trigger (TABnCTL1.TABnEST bit) to 1 is used
as the trigger.
Remark
k = 1 to 3,
m = 0 to 3,
n = 0, 1
Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (1/3)
(a) TABn control register 0 (TABnCTL0)
TABnCE
TABnCTL0
0/1
TABnCKS2 TABnCKS1 TABnCKS0
0
0
0
0
0/1
0/1
0/1
Select count clockNote
0: Stop counting
1: Enable counting
Note
The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
Remark
n = 0, 1
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Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (2/3)
(b) TABn control register 1 (TABnCTL1)
TABnSYE TABnEST TABnEEE
TABnCTL1
0
0/1
TABnMD2 TABnMD1 TABnMD0
0/1
0
0
0
1
0
0, 1, 0:
External trigger pulse
output mode
0: Operate on count clock
selected by TABnCKS0 to
TABnCKS2 bits
1: Count by external event
input signal
Generate software trigger
when 1 is written
(c) TABn I/O control register 0 (TABnIOC0)
TABnOL3 TABnOE3 TABnOL2 TABnOE2 TABnOL1 TABnOE1 TABnOL0 TABnOE0
TABnIOC0
0/1
0/1
0/1
0/1
0/1
0/1
0/1Note
0/1Note
0: Disable TOABn0 pin output
1: Enable TOABn0 pin output
Setting of output level while
operation of TOABn0 pin is disabled
0: Low level
1: High level
0: Disable TOABn1 pin output
1: Enable TOABn1 pin output
Specification of active level
of TOABn1 pin output
0: Active-high
1: Active-low
0: Disable TOABn2 pin output
1: Enable TOABn2 pin output
Specification of active level
of TOABn2 pin output
0: Active-high
1: Active-low
0: Disable TOABn3 pin output
1: Enable TOABn3 pin output
Specification of active level
of TOABn3 pin output
0: Active-high
1: Active-low
• When TABnOLk bit = 0
• When TABnOLk bit = 1
16-bit counter
16-bit counter
TOABnk pin output
TOABnk pin output
Note
Clear this bit to 0 when the TOABn0 pin is not used in the external trigger pulse output mode.
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (3/3)
(d) TABn I/O control register 2 (TABnIOC2)
TABnEES1 TABnEES0 TABnETS1 TABnETS0
TABnIOC2
0
0
0
0
0/1
0/1
0/1
0/1
Select valid edge of
external trigger input
Select valid edge of
external event count input
(e) TABn counter read buffer register (TABnCNT)
The value of the 16-bit counter can be read by reading the TABnCNT register.
(f) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
If D0 is set to the TABnCCR0 register, D1 to the TABnCCR1 register, D2 to the TABnCCR2 register, and D3 to
the TABnCCR3 register, the cycle and active level of the PWM waveform are as follows.
Cycle = (D0 + 1) × Count clock cycle
TOABn1 pin PWM waveform active level width = D1 × Count clock cycle
TOABn2 pin PWM waveform active level width = D2 × Count clock cycle
TOABn3 pin PWM waveform active level width = D3 × Count clock cycle
Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are
not used in the external trigger pulse output mode.
2. Updating TABn capture/compare register 2 (TABnCCR2) and TABn capture/compare
register 3 (TABnCCR3) is enabled by writing TABn capture/compare register 1
(TABnCCR1).
3. n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(1) Operation flow in external trigger pulse output mode
Figure 8-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2)
FFFFH
D01
D00
16-bit counter
D30
D10
D20
D00
D31
D21
D31
D21
D11
D11
D00
D00
D31
D21
D30
D20
D10
D10
D00
D31
D21
D11
0000H
TABnCE bit
External trigger input
(TIAB00 pin input)Note
TABnCCR0 register
D00
CCR0 buffer register
D01
D00
D00
D01
D00
INTTABnCC0 signal
TOABn0 pin output
(only when software
trigger is used)
D10
TABnCCR1 register
D11
D10
CCR1 buffer register
D11
D10
D11
D11
D10
D10
D11
D10
D11
INTTABnCC1 signal
TOABn1 pin output
TABnCCR2 register
D20
CCR2 buffer register
D20
D21
D20
D21
D21
D20
D21
INTTABnCC2 signal
TOABn2 pin output
TABnCCR3 register
D30
CCR3 buffer register
D30
D31
D30
D31
D31
D30
D31
INTTABnCC3 signal
TOABn3 pin output
Note
TAB1: TRGAB1 pin
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Figure 8-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2)
Count operation start flow
START
Register initial setting
TABnCTL0 register
(TABnCKS0 to TABnCKS2
bits),
TABnCTL1 register,
TABnIOC0 register,
TABnIOC2 register,
TABnCCR0 to TABnCCR3
registers
TABnCE bit = 1
TABnCCR1 to TABnCCR3 register
setting change flow
Setting of TABnCCR2,
TABnCCR3 registers
The initial setting of these
registers is performed
before setting the
TABnCE bit to 1.
The TABnCKS0 to
TABnCKS2 bits can be
set at the same time
when counting is
enabled (TABnCE bit = 1).
Trigger wait status
Setting of TABnCCR1 register
TABnCCR2, TABnCCR3 register
setting change flow
Setting of TABnCCR2,
TABnCCR3 registers
Setting of TABnCCR1 register
TABnCCR0 to TABnCCR3 register
setting change flow
Setting of TABnCCR0, TABnCCR2,
and TABnCCR3 registers
Setting of TABnCCR1 register
Writing the TABnCCR1
register must be performed
after writing the TABnCCR0,
TABnCCR2, and TABnCCR3
registers.
When the counter is cleared
after setting, the value
of the TABnCCRm register is
transferred to the CCRm buffer
registers.
Setting of TABnCCR0 register
Setting of TABnCCR1 register
Remark
When the counter is
cleared after setting,
the value of the TABnCCRm
register is transferred to
the CCRm buffer register.
Writing the same value to the
TABnCCR1 register is necessary
only when the set duty factor of
the TOABn2 and TOABn3 pin
outputs is changed.
When the counter is cleared
after setting, the value of the
TABnCCRm register is
transferred to the CCRm buffer
register.
TABnCCR1 register setting change flow
Setting of TABnCCR1 register
TABnCCR0 register setting change flow
Writing the same value to
the TABnCCR1 register is
necessary only when the
set cycle is changed.
Writing the TABnCCR1
register must be performed
only when the set duty factor is
changed after writing the
TABnCCR2 and TABnCCR3
registers.
When the counter is cleared
after setting, the value of the
TABnCCRm register is transferred
to the CCRm buffer register.
The TABnCCR1 register only needs
to be written, only when the set duty
factor of the TOABn1 pin output is
changed.
When the counter is cleared after
setting, the value of the TABnCCRm
register is transferred to the CCRm
buffer register.
Count operation stop flow
TABnCE bit = 0
Counting is stopped.
STOP
m = 0 to 3,
n = 0, 1
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(2) External trigger pulse output mode operation timing
(a) Note on changing pulse width during operation
To change the PWM waveform while the counter is operating, write the TABnCCR1 register last.
Rewrite the TABnCCRk register after writing the TABnCCR1 register after the INTTABnCC0 signal is detected.
FFFFH
16-bit counter
0000H
D01
D00
D30
D20
D10
D00
D30
D20
D10
D00
D30
D20
D10
D01
D31
D21
D31
D21
D11
D11
TABnCE bit
External trigger input
(TIAB00 pin input)Note
TABnCCR0 register
D00
D01
D00
CCR0 buffer register
D01
INTTABnCC0 signal
TOABn0 pin output
(only when software
trigger is used)
D10
TABnCCR1 register
D11
D10
CCR1 buffer register
D11
INTTABnCC1 signal
TOABn1 pin output
TABnCCR2 register
D20
D21
D20
CCR2 buffer register
D21
INTTABnCC2 signal
TOABn2 pin output
TABnCCR3 register
CCR3 buffer register
D30
D31
D30
D31
INTTABnCC3 signal
TOABn3 pin output
Note
TAB1: TRGAB1 pin
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
To transfer data from the TABnCCRm register to the CCRm buffer register, the TABnCCR1 register must be
written.
To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the
TABnCCR0 register, set the active level width to the TABnCCR2 and TABnCCR3 registers, and then set the
active level to the TABnCCR1 register.
To change only the cycle of the PWM waveform, first set the cycle to the TABnCCR0 register, and then write
the same value to the TABnCCR1 register.
To change only the active level width (duty factor) of the PWM waveform, first set the active level to the
TABnCCR2 and TABnCCR3 registers and then set the active level to the TABnCCR1 register.
To change only the active level width (duty factor) of the PWM waveform output by the TOABn1 pin, only the
TABnCCR1 register has to be set.
To change only the active level width (duty factor) of the PWM waveform output by the TOABn2 and TOABn3
pins, first set the active level width to the TABnCCR2 and TABnCCR3 registers, and then write the same value
to the TABnCCR1 register.
After data is written to the TABnCCR1 register, the value written to the TABnCCRm register is transferred to the
CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value to be
compared with the 16-bit counter.
To write the TABnCCR0 to TABnCCR3 registers again after writing the TABnCCR1 register once, do so after
the INTTABnCC0 signal is generated.
Otherwise, the value of the CCRm buffer register may become
undefined because the timing of transferring data from the TABnCCRm register to the CCRm buffer register
conflicts with writing the TABnCCRm register.
Remark
m = 0 to 3,
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TABnCCRk register to 0000H. If the set value of the TABnCCR0 register is
FFFFH, the INTTABnCCk signal is generated periodically.
Count clock
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0001
D0 − 1
D0
0000
TABnCE bit
TABnCCR0 register
D0
D0
D0
TABnCCRk register
0000H
0000H
0000H
INTTABnCC0 signal
INTTABnCCk signal
TOABnk pin output
Remark
L
k = 1 to 3,
n = 0, 1
To output a 100% waveform, set a value of “set value of TABnCCR0 register + 1” to the TABnCCRk register. If
the set value of the TABnCCR0 register is FFFFH, 100% output cannot be produced.
Count clock
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0001
D0 − 1
D0
0000
TABnCE bit
TABnCCR0 register
D0
D0
D0
TABnCCRk register
D0 + 1
D0 + 1
D0 + 1
INTTABnCC0 signal
INTTABnCCk signal
TOABnk pin output
Remark
k = 1 to 3,
n = 0, 1
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(c) Conflict between trigger detection and match with CCRk buffer register
If the trigger is detected immediately after the INTTABnCCk signal is generated, the 16-bit counter is
immediately cleared to 0000H, the output signal of the TOABnk pin is asserted, and the counter continues
counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter
FFFF
Dk − 1
0000
Dk
0000
External trigger input
(TIAB00 pin input)Note
Dk
CCRk buffer register
INTTABnCCk signal
TOABnk pin output
Shortened
Note
TAB1: TRGAB1 pin
Remark
k = 1 to 3,
n = 0, 1
If the trigger is detected immediately before the INTTABnCCk signal is generated, the INTTABnCCk signal is
not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the
TOABnk pin remains active. Consequently, the active period of the PWM waveform is extended.
16-bit counter
FFFF
0000
Dk − 2
0000
0001
Dk − 1
Dk
External trigger input
(TIAB00 pin input)Note
CCRk buffer register
Dk
INTTABnCCk signal
TOABnk pin output
Extended
Note
TAB1: TRGAB1 pin
Remark
k = 1 to 3,
n = 0, 1
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(d) Conflict between trigger detection and match with CCR0 buffer register
If the trigger is detected immediately after the INTTABnCC0 signal is generated, the 16-bit counter is cleared to
0000H and continues counting up. Therefore, the active period of the TOABnk pin is extended by time from
generation of the INTTABnCC0 signal to trigger detection.
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0000
External trigger input
(TIAB00 pin input)Note
D0
CCR0 buffer register
INTTABnCC0 signal
TOABnk pin output
Extended
Note
TAB1: TRGAB1 pin
Remark
k = 1 to 3,
n = 0, 1
If the trigger is detected immediately before the INTTABnCC0 signal is generated, the INTTABnCC0 signal is
not generated. The 16-bit counter is cleared to 0000H, the TOABnk pin is asserted, and the counter continues
counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0001
External trigger input
(TIAB00 pin input)Note
CCR0 buffer register
D0
INTTABnCC0 signal
TOABnk pin output
Shortened
Note
TAB1: TRGAB1 pin
Remark
k = 1 to 3,
n = 0, 1
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(e) Generation timing of compare match interrupt request signal (INTTABnCCk)
The timing of generation of the INTTABnCCk signal in the external trigger pulse output mode differs from the
timing of other INTTABnCCk signals; the INTTABnCCk signal is generated when the count value of the 16-bit
counter matches the value of the CCRk buffer register.
Count clock
16-bit counter
CCRk buffer register
Dk − 2
Dk − 1
Dk
Dk + 1
Dk + 2
Dk
TOABnk pin output
INTTABnCCk signal
Remark
k = 1 to 3,
n = 0, 1
Usually, the INTTABnCCk signal is generated in synchronization with the next count-up after the count value of
the 16-bit counter matches the value of the CCRk buffer register.
In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing
is changed to match the timing of changing the output signal of the TOABnk pin.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
One-shot pulse output mode (TABnMD2 to TABnMD0 bits = 011)
In the one-shot pulse output mode, TABn waits for a trigger when the TABnCTL0.TABnCE bit is set to 1. When the valid
edge of the external trigger input is detected, TABn starts counting, and outputs a one-shot pulse from the TOABn1 to
TOABn3 pins.
Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software trigger
is used, the TOABn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the
counter is stopped (waiting for a trigger).
Figure 8-20. Configuration in One-Shot Pulse Output Mode
TABnCCR1
register
Transfer
Output
S
controller
R (RS-FF)
CCR1 buffer
register
Match signal
TOABn1 pin
INTTABnCC1 signal
TABnCCR2
register
Transfer
Output
S
controller
R (RS-FF)
CCR2 buffer
register
Match signal
TOABn2 pin
INTTABnCC2 signal
TABnCCR3
register
Transfer
Edge
detector
TIAB00 pinNote
S Output
controller
R
(RS-FF)
CCR3 buffer
register
Software trigger
generation
Match signal
TOABn3 pin
INTTABnCC3 signal
Clear
Count clock
selection
Count start
control
S Output
controller
R
(RS-FF)
16-bit counter
Match signal
TABnCE bit
TOABn0 pin
INTTABnCC0 signal
CCR0 buffer register
Transfer
TABnCCR0 register
Note TAB1: TRGAB1 pin
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Figure 8-21. Basic Timing in One-Shot Pulse Output Mode
FFFFH
D0
D0
D3
16-bit counter
D0
D3
D2
D3
D2
D1
D2
D1
D1
0000H
TABnCE bit
External trigger input
(TIAB00 pin input)Note
D0
TABnCCR0 register
INTTABnCC0 signal
TOABn0 pin output
(only when software
trigger is used)
TABnCCR1 register
D1
INTTABnCC1 signal
TOABn1 pin output
Delay
(D1)
Active
level width
(D0 − D1 + 1)
TABnCCR2 register
Delay
(D1)
Active
level width
(D0 − D1 + 1)
Delay
(D1)
Active
level width
(D0 − D1 + 1)
D2
INTTABnCC2 signal
TOABn2 pin output
Delay
(D2)
TABnCCR3 register
Active
level width
(D0 − D2 + 1)
Delay
(D2)
Active
level width
(D0 − D2 + 1)
Delay
(D2)
Active
level width
(D0 − D2 + 1)
D3
INTTABnCC3 signal
TOABn3 pin output
Delay
(D3)
Active
level width
(D0 − D3 + 1)
Delay
(D3)
Active
level width
(D0 − D3 + 1)
Delay
(D3)
Active
level width
(D0 − D3 + 1)
Note TAB1: TRGAB1 pin
Remark
n = 0, 1
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When the TABnCE bit is set to 1, TABn waits for a trigger. When the trigger is generated, the 16-bit counter is cleared
from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOABnk pin. After the one-shot pulse is
output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is generated again while the
one-shot pulse is being output, it is ignored.
The output delay period and active level width of the one-shot pulse can be calculated as follows.
Output delay period = (Set value of TABnCCRk register) × Count clock cycle
Active level width = (Set value of TABnCCR0 register − Set value of TABnCCRk register + 1) × Count clock cycle
The compare match interrupt request signal INTTABnCC0 is generated when the 16-bit counter counts up after its
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal (INTTABnCCk) is
generated when the count value of the 16-bit counter matches the value of the CCRk buffer register.
The valid edge of the external trigger input or setting the software trigger (TABnCTL1.TABnEST bit) to 1 is used as the
trigger.
Remark
k = 1 to 3,
n = 0, 1
Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (1/3)
(a) TABn control register 0 (TABnCTL0)
TABnCE
TABnCTL0
0/1
TABnCKS2 TABnCKS1 TABnCKS0
0
0
0
0
0/1
0/1
0/1
Select count clockNote
0: Stop counting
1: Enable counting
(b) TABn control register 1 (TABnCTL1)
TABnSYE TABnEST TABnEEE
TABnCTL1
0
0/1
0/1
TABnMD2 TABnMD1 TABnMD0
0
0
0
1
1
0, 1, 1:
One-shot pulse output mode
0: Operate on count clock
selected by TABnCKS0 to
TABnCKS2 bits
1: Count by external event
count input signal
Generate software trigger
when 1 is written
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
Remark
n = 0, 1
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Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (2/3)
(c) TABn I/O control register 0 (TABnIOC0)
TABnOL3 TABnOE3 TABnOL2 TABnOE2 TABnOL1 TABnOE1 TABnOL0 TABnOE0
TABnIOC0
0/1
0/1
0/1
0/1
0/1
0/1
0/1Note
0/1Note
0: Disable TOABn0 pin output
1: Enable TOABn0 pin output
Setting of output level while
operation of TOABn0 pin is disabled
0: Low level
1: High level
0: Disable TOABn1 pin output
1: Enable TOABn1 pin output
Specification of active level
of TOABn1 pin output
0: Active-high
1: Active-low
0: Disable TOABn2 pin output
1: Enable TOABn2 pin output
Specification of active level
of TOABn2 pin output
0: Active-high
1: Active-low
0: Disable TOABn3 pin output
1: Enable TOABn3 pin output
Specification of active level
of TOABn3 pin output
0: Active-high
1: Active-low
• When TABnOLk bit = 0
• When TABnOLk bit = 1
16-bit counter
16-bit counter
TOABnk pin output
TOABnk pin output
(d) TABn I/O control register 2 (TABnIOC2)
TABnEES1 TABnEES0 TABnETS1 TABnETS0
TABnIOC2
0
0
0
0
0/1
0/1
0/1
0/1
Select valid edge of
external trigger input
Select valid edge of
external event count input
(e) TABn counter read buffer register (TABnCNT)
The value of the 16-bit counter can be read by reading the TABnCNT register.
Note Clear this bit to 0 when the TOABn0 pin is not used in the one-shot pulse output mode.
Remark
n = 0, 1
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Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (3/3)
(f) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
If D0 is set to the TABnCCR0 register and Dk to the TABnCCRk register, the active level width and output
delay period of the one-shot pulse are as follows.
Active level width = (D0 − Dk + 1) × Count clock cycle
Output delay period = (Dk) × Count clock cycle
Caution
One-shot pulses are not output even in the one-shot pulse output mode, if the set
value of the TABnCCRk register is greater than that value of the TABnCCR0 register.
Remarks 1.
TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are not
used in the one-shot pulse output mode.
2.
k = 1 to 3,
n = 0, 1
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(1) Operation flow in one-shot pulse output mode
Figure 8-23. Software Processing Flow in One-Shot Pulse Output Mode (1/2)
FFFFH
D00
D01
D30
16-bit counter
D31
D20
D10
D11
D21
0000H
TABnCE bit
External trigger input
(TIAB00 pin input)Note
TABnCCR0 register
D00
D01
D10
D11
INTTABnCC0 signal
TOABn0 pin output
(only when software
trigger is used)
TABnCCR1 register
INTTABnCC1 signal
TOABn1 pin output
TABnCCR2 register
D20
D21
INTTABnCC2 signal
TOABn2 pin output
TABnCCR3 register
D30
D31
INTTABnCC3 signal
TOABn3 pin output
Note TAB1: TRGAB1 pin
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Figure 8-23. Software Processing Flow in One-Shot Pulse Output Mode (2/2)
Count operation start flow
TABnCCR0 to TABnCCR3 register setting change flow
START
Setting of TABnCCR0 to
TABnCCR3 registers
Register initial setting
TABnCTL0 register
(TABnCKS0 to TABnCKS2 bits),
TABnCTL1 register,
TABnIOC0 register,
TABnIOC2 register,
TABnCCR0 to TABnCCR3 registers
TABnCE bit = 1
The initial setting of these
registers is performed
before setting the
TABnCE bit to 1.
As rewriting the
TABnCCRm register
immediately sends the
data to the CCRm
buffer register, rewriting
immediately after
the generation of the
INTTABnCCR0 signal
is recommended.
Count operation stop flow
The TABnCKS0 to
TABnCKS2 bits can be
set at the same time
when counting has been
started (TABnCE bit = 1).
Trigger wait status
TABnCE bit = 0
Count operation is
stopped
STOP
Remark
m = 0 to 3,
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(2) Operation timing in one-shot pulse output mode
(a) Notes on rewriting TABnCCRm register
To change the set value of the TABnCCRm register to a smaller value, stop counting once, and then change
the set value.
If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
D00
D00
D01
16-bit counter
Dk0
D01
Dk0
Dk1
Dk1
0000H
TABnCE bit
External trigger input
(TIAB00 pin input)Note
TABnCCR0 register
D00
D01
INTTABnCC0 signal
TOABn0 pin output
(only when software
trigger is used)
TABnCCRk register
Dk0
Dk1
INTTABnCCk signal
TOABnk pin output
Delay
(Dk0)
Active level width
(D00 − Dk0 + 1)
Delay
(10000H + Dk1)
Delay
(Dk1)
Active level width
(D01 − Dk1 + 1)
Active level width
(D01 − Dk1 + 1)
Note TAB1: TRGAB1 pin
When the TABnCCR0 register is rewritten from D00 to D01 and the TABnCCRk register from Dk0 to Dk1 where
D00 > D01 and Dk0 > Dk1, if the TABnCCRk register is rewritten when the count value of the 16-bit counter is
greater than Dk1 and less than Dk0 and if the TABnCCR0 register is rewritten when the count value is greater
than D01 and less than D00, each set value is reflected as soon as the register has been rewritten and
compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H.
When the count value matches Dk1, the counter generates the INTTABnCCk signal and asserts the TOABnk
pin.
When the count value matches D01, the counter generates the INTTABnCC0 signal, deasserts the
TOABnk pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the oneshot pulse that is originally expected.
Remark
k = 1 to 3,
n = 0, 1
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(b) Generation timing of compare match interrupt request signal (INTTABnCCk)
The generation timing of the INTTABnCCk signal in the one-shot pulse output mode is different from other
INTTABnCCk signals; the INTTABnCCk signal is generated when the count value of the 16-bit counter matches
the value of the TABnCCRk register.
Count clock
16-bit counter
Dk − 2
Dk − 1
TABnCCRk register
Dk
Dk + 1
Dk + 2
Dk
TOABnk pin output
INTTABnCCk signal
Usually, the INTTABnCCk signal is generated when the 16-bit counter counts up next time after its count value
matches the value of the TABnCCRk register.
In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is
changed to match the change timing of the TOABnk pin.
Remark
k = 1 to 3,
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
PWM output mode (TABnMD2 to TABnMD0 bits = 100)
In the PWM output mode, a PWM waveform is output from the TOABn1 to TOABn3 pins when the TABnCTL0.TABnCE
bit is set to 1.
In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOABn0 pin.
Figure 8-24. Configuration in PWM Output Mode
TABnCCR1
register
Transfer
Output
S
controller
R (RS-FF)
CCR1 buffer
register
Match signal
TOABn1 pin
INTTABnCC1 signal
TABnCCR2
register
Transfer
S Output
controller
R
(RS-FF)
CCR2 buffer
register
Match signal
TOABn2 pin
INTTABnCC2 signal
TABnCCR3
register
Transfer
CCR3 buffer
register
Output
S
controller
R (RS-FF)
Match signal
TOABn3 pin
INTTABnCC3 signal
Clear
Count
clock
selection
16-bit counter
Output
controller
Match signal
TABnCE bit
TOABn0 pin
INTTABnCC0 signal
CCR0 buffer register
Transfer
TABnCCR0 register
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Figure 8-25. Basic Timing in PWM Output Mode
FFFFH
D3
16-bit counter
D1
D0
D3
D0
D3
D2
D2
D0
D3
D2
D1
D0
D2
D1
D1
0000H
TABnCE bit
D0
TABnCCR0 register
INTTABnCC0 signal
TOABn0 pin output
TABnCCR1 register
D1
INTTABnCC1 signal
TOABn1 pin output
Active
level width
(D1)
Active
level width
(D1)
Active
level width
(D1)
TABnCCR2 register
Active
level width
(D1)
D2
INTTABnCC2 signal
TOABn2 pin output
Active
level width
(D2)
Active
level width
(D2)
TABnCCR3 register
Active
level width
(D2)
Active
level width
(D2)
D3
INTTABnCC3 signal
TOABn3 pin output
Active level
width (D3)
Cycle (D0 + 1)
Remark
Active level
width (D3)
Cycle (D0 + 1)
Active level
width (D3)
Cycle (D0 + 1)
Active level
width (D3)
Cycle (D0 + 1)
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
When the TABnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
PWM waveform from the TOABnk pin.
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TABnCCRk register) × Count clock cycle
Cycle = (Set value of TABnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TABnCCRk register)/(Set value of TABnCCR0 register + 1)
The PWM waveform can be changed by rewriting the TABnCCRm register while the counter is operating. The newly
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the
16-bit counter is cleared to 0000H.
The compare match interrupt request signal (INTTABnCC0) is generated when the 16-bit counter counts up next time
after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal (INTTABnCCk) is generated when the count value of the 16-bit counter matches
the value of the CCRk buffer register.
Remark
k = 1 to 3,
m = 0 to 3,
n = 0, 1
Figure 8-26. Setting of Registers in PWM Output Mode (1/3)
(a) TABn control register 0 (TABnCTL0)
TABnCE
TABnCTL0
0/1
TABnCKS2 TABnCKS1 TABnCKS0
0
0
0
0
0/1
0/1
0/1
Select count clockNote
0: Stop counting
1: Enable counting
(b) TABn control register 1 (TABnCTL1)
TABnSYE TABnEST TABnEEE
TABnCTL1
0
0
0/1
TABnMD2 TABnMD1 TABnMD0
0
0
1
0
0
1, 0, 0:
PWM output mode
0: Operate on count clock
selected by TABnCKS0 to
TABnCKS2 bits
1: Count by external event
count input signal
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
Remark
n = 0, 1
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Figure 8-26. Setting of Registers in PWM Output Mode (2/3)
(c) TABn I/O control register 0 (TABnIOC0)
TABnOL3 TABnOE3 TABnOL2 TABnOE2 TABnOL1 TABnOE1 TABnOL0 TABnOE0
TABnIOC0
0/1
0/1
0/1
0/1
0/1
0/1
0/1Note
0/1Note
0: Disable TOABn0 pin output
1: Enable TOABn0 pin output
Setting of output level while
operation of TOABn0 pin is disabled
0: Low level
1: High level
0: Disable TOABn1 pin output
1: Enable TOABn1 pin output
Specification of active level of
TOABn1 pin output
0: Active-high
1: Active-low
0: Disable TOABn2 pin output
1: Enable TOABn2 pin output
Specification of active level
of TOABn2 pin output
0: Active-high
1: Active-low
0: Disable TOABn3 pin output
1: Enable TOABn3 pin output
Specification of active level
of TOABn3 pin output
0: Active-high
1: Active-low
• When TABnOLk bit = 0
• When TABnOLk bit = 1
16-bit counter
16-bit counter
TOABnk pin output
TOABnk pin output
(d) TABn I/O control register 2 (TABnIOC2)
TABnEES1 TABnEES0 TABnETS1 TABnETS0
TABnIOC2
0
0
0
0
0/1
0/1
0
0
Select valid edge
of external event
count input.
(e) TABn counter read buffer register (TABnCNT)
The value of the 16-bit counter can be read by reading the TABnCNT register.
Note Clear this bit to 0 when the TOABn0 pin is not used in the PWM output mode.
Remark
n = 0, 1
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Figure 8-26. Register Setting in PWM Output Mode (3/3)
(f) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
If D0 is set to the TABnCCR0 register and Dk to the TABnCCRk register, the cycle and active level of the
PWM waveform are as follows.
Cycle = (D0 + 1) × Count clock cycle
Active level width = Dk × Count clock cycle
Remarks 1.
TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are not
used in the PWM output mode.
2.
Updating TABn capture/compare register 2 (TABnCCR2) and TABn capture/compare register
3 (TABnCCR3) is enabled by writing TABn capture/compare register 1 (TABnCCR1).
3.
n = 0, 1
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(1) Operation flow in PWM output mode
Figure 8-27. Software Processing Flow in PWM Output Mode (1/2)
FFFFH
D01
D00
16-bit counter
D30
D10
D20
D00
D31
D21
D31
D21
D11
D11
D00
D00
D31
D21
D30
D20
D10
D10
D00
D31
D21
D11
0000H
TABnCE bit
TABnCCR0 register
D00
CCR0 buffer register
D01
D00
D00
D01
D00
INTTABnCC0 signal
TOABn0 pin output
TABnCCR1 register
D10
CCR1 buffer register
D11
D10
D11
D10
D11
D11
D10
D10
D11
D10
D11
INTTABnCC1 signal
TOABn1 pin output
TABnCCR2 register
D20
CCR2 buffer register
D20
D21
D20
D21
D21
D20
D21
INTTABnCC2 signal
TOABn2 pin output
TABnCCR3 register
D30
CCR3 buffer register
D30
D31
D30
D31
D31
D30
D31
INTTABnCC3 signal
TOABn3 pin output
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Figure 8-27. Software Processing Flow in PWM Output Mode (2/2)
Count operation start flow
START
Register initial setting
TABnCTL0 register
(TABnCKS0 to TABnCKS2
bits),
TABnCTL1 register,
TABnIOC0 register,
TABnIOC2 register,
TABnCCR0 to TABnCCR3
registers
TABnCE bit = 1
TABnCCR1 to TABnCCR3 register
setting change flow
Setting of TABnCCR2,
TABnCCR3 registers
The initial setting of these
registers is performed
before setting the
TABnCE bit to 1.
The TABnCKS0 to
TABnCKS2 bits can be
set at the same time
when counting is
enabled (TABnCE bit = 1).
Setting of TABnCCR1 register
TABnCCR2, TABnCCR3 register
setting change flow
Setting of TABnCCR2,
TABnCCR3 registers
Setting of TABnCCR1 register
TABnCCR0 to TABnCCR3 register
setting change flow
Setting of TABnCCR0, TABnCCR2,
and TABnCCR3 registers
Setting of TABnCCR1 register
Writing the TABnCCR1
register must be performed
after writing the TABnCCR0,
TABnCCR2, and TABnCCR3
registers.
When the counter is cleared
after setting, the value
of the TABnCCRm register is
transferred to the CCRm buffer
registers.
Writing the TABnCCR1 register
must be performed only when
the set duty factor is changed
after writing the TABnCCR2 and
TABnCCR3 registers.
When the counter is cleared after
setting, the value of the
TABnCCRm register is transferred
to the CCRm buffer register.
Writing the same value to the
TABnCCR1 register is necessary
only when the set duty factor of
TOABn2 and TOABn3 pin
outputs is changed.
When the counter is
cleared after setting,
the value of the TABnCCRm
register is transferred to
the CCRm buffer register.
TABnCCR1 register setting change flow
Setting of TABnCCR1 register
The TABnCCR1 register only needs
to be written, only when the set duty
factor is changed.
When the counter is cleared after
setting, the value of the TABnCCRm
register is transferred to the CCRm
buffer register.
TABnCCR0 register setting change flow
Setting of TABnCCR0 register
Setting of TABnCCR1 register
Remark
Writing the same value
to TABnCCR1 is
necessary only when the
set cycle is changed.
When the counter is
cleared after setting, the
value of the TABnCCRm
register is transferred to
the CCRm buffer register.
Count operation stop flow
TABnCE bit = 0
Counting is stopped.
STOP
k = 1 to 3,
m = 0 to 3,
n = 0, 1
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(2) PWM output mode operation timing
(a) Changing pulse width during operation
To change the PWM waveform while the counter is operating, write the TABnCCR1 register last.
Rewrite the TABnCCRk register after writing the TABnCCR1 register after the INTTABnCC1 signal is detected.
FFFFH
16-bit counter
0000H
D01
D00
D30
D20
D10
D00
D30
D20
D10
D00
D30
D20
D10
D01
D31
D21
D31
D21
D11
D11
TABnCE bit
TABnCCR0 register
D00
D01
D00
CCR0 buffer register
D01
INTTABnCC0 signal
TOABn0 pin output
D10
TABnCCR1 register
CCR1 buffer register
D11
D10
D11
INTTABnCC1 signal
TOABn1 pin output
TABnCCR2 register
CCR2 buffer register
D20
D21
D20
D21
INTTABnCC2 signal
TOABn2 pin output
TABnCCR3 register
CCR3 buffer register
D30
D30
D31
D31
INTTABnCC3 signal
TOABn3 pin output
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
To transfer data from the TABnCCRm register to the CCRm buffer register, the TABnCCR1 register must be
written.
To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the
TABnCCR0 register, set the active level width to the TABnCCR2 and TABnCCR3 registers, and then set the
active level width to the TABnCCR1 register.
To change only the cycle of the PWM waveform, first set the cycle to the TABnCCR0 register, and then write
the same value to the TABnCCR1 register.
To change only the active level width (duty factor) of the PWM wave, first set the active level to the TABnCCR2
and TABnCCR3 registers, and then set the active level to the TABnCCR1 register.
To change only the active level width (duty factor) of the PWM waveform output by the TOABn1 pin, only the
TABnCCR1 register has to be set.
To change only the active level width (duty factor) of the PWM waveform output by the TOABn2 and TOABn3
pins, first set the active level width to the TABnCCR2 and TABnCCR3 registers, and then write the same value
to the TABnCCR1 register.
After the TABnCCR1 register is written, the value written to the TABnCCRm register is transferred to the CCRm
buffer register in synchronization with the timing of clearing the 16-bit counter, and is used as the value to be
compared with the value of the 16-bit counter.
To write the TABnCCR0 to TABnCCR3 registers again after writing the TABnCCR1 register once, do so after
the INTTABnCC0 signal is generated.
Otherwise, the value of the CCRm buffer register may become
undefined because the timing of transferring data from the TABnCCRm register to the CCRm buffer register
conflicts with writing the TABnCCRm register.
Remark
m = 0 to 3,
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TABnCCRk register to 0000H. If the set value of the TABnCCR0 register is
FFFFH, the INTTABnCCk signal is generated periodically.
Count clock
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0001
D0 − 1
D0
0000
TABnCE bit
TABnCCR0 register
D0
D0
D0
TABnCCRk register
0000H
0000H
0000H
INTTABnCC0 signal
INTTABnCCk signal
TOABnk pin output
Remark
L
k = 1 to 3,
n = 0, 1
To output a 100% waveform, set a value of “set value of TABnCCR0 register + 1” to the TABnCCRk register. If
the set value of the TABnCCR0 register is FFFFH, 100% output cannot be produced.
Count clock
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0001
D0 − 1
D0
0000
TABnCE bit
TABnCCR0 register
D0
D0
D0
TABnCCRk register
D0 + 1
D0 + 1
D0 + 1
INTTABnCC0 signal
INTTABnCCk signal
TOABnk pin output
Remark
k = 1 to 3,
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(c) Generation timing of compare match interrupt request signal (INTTABnCCk)
The timing of generation of the INTTABnCCk signal in the PWM output mode differs from the timing of other
INTTABnCCk signals; the INTTABnCCk signal is generated when the count value of the 16-bit counter matches
the value of the TABnCCRk register.
Count clock
16-bit counter
CCRk buffer register
Dk − 2
Dk − 1
Dk
Dk + 1
Dk + 2
Dk
TOABnk pin output
INTTABnCCk signal
Remark
k = 1 to 3,
n = 0, 1
Usually, the INTTABnCCk signal is generated in synchronization with the next counting up after the count value
of the 16-bit counter matches the value of the TABnCCRk register.
In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed to
match the change timing of the output signal of the TOABnk pin.
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8.5.6
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Free-running timer mode (TABnMD2 to TABnMD0 bits = 101)
In the free-running timer mode, TABn starts counting when the TABnCTL0.TABnCE bit is set to 1. At this time, the
TABnCCRm register can be used as a compare register or a capture register, according to the setting of the
TABnOPT0.TABnCCS0 and TABnOPT0.TABnCCS1 bits.
Remark
m = 0 to 3,
n = 0, 1
Figure 8-28. Configuration in Free-Running Timer Mode
TABnCCR3
register
(compare)
TABnCCR2
register
(compare)
TABnCCR1
register
(compare)
TABnCCR0
register
(compare)
Internal count clock
TIAB00 pin
(external event
count inputNote/
capture
trigger input)
TIABn1 pin
(capture
trigger input)
TIABn2 pin
(capture
trigger input)
TIABn3 pin
(capture
trigger input)
Edge
detector
Output
controller
TOABn3 pin output
Output
controller
TOABn2 pin output
Output
controller
TOABn1 pin output
Output
controller
TOABn0 pin output
TABnCCS0,
TABnCCS1 bits
(capture/compare
selection)
Count
clock
selection
INTTABnOV signal
16-bit counter
TABnCE
bit
0
Edge
detector
INTTABnCC3 signal
1
TABnCCR0
register
(capture)
0
INTTABnCC2 signal
1
Edge
detector
0
TABnCCR1
register
(capture)
Edge
detector
INTTABnCC1 signal
1
0
1
INTTABnCC0 signal
TABnCCR2
register
(capture)
Edge
detector
TABnCCR3
register
(capture)
Note TAB1: EVTAB1 pin
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
When the TABnCE bit is set to 1, TABn starts counting, and the output signals of the TOABn0 to TOABn3 pins are
inverted. When the count value of the 16-bit counter subsequently matches the set value of the TABnCCRm register, a
compare match interrupt request signal (INTTABnCCm) is generated, and the output signal of the TOABnm pin is inverted.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTABnOV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TABnOPT0.TABnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR
instruction by software.
The TABnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at
that time, and compared with the count value.
Remark
m = 0 to 3,
n = 0, 1
Figure 8-29. Basic Timing in Free-Running Timer Mode (Compare Function)
FFFFH
16-bit counter
D00
D30
D00
D30
D20
D01
D31
D20
D10
D11
D21
D11
D01
D31
D21
D11
0000H
TABnCE bit
D00
TABnCCR0 register
D01
INTTABnCC0 signal
TOABn0 pin output
TABnCCR1 register
D10
D11
INTTABnCC1 signal
TOABn1 pin output
TABnCCR2 register
D20
D21
INTTABnCC2 signal
TOABn2 pin output
TABnCCR3 register
D30
D31
INTTABnCC3 signal
TOABn3 pin output
INTTABnOV signal
TABnOVF bit
Cleared to 0 by
CLR instruction
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Cleared to 0 by Cleared to 0 by
CLR instruction CLR instruction
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
When the TABnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIABnm pin is
detected, the count value of the 16-bit counter is stored in the TABnCCRm register, and a capture interrupt request signal
(INTTABnCCm) is generated.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTABnOV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TABnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction
by software.
Remark
m = 0 to 3,
n = 0, 1
Figure 8-30. Basic Timing in Free-Running Timer Mode (Capture Function)
FFFFH
16-bit counter
D10
D30
D31
D21
D00
D20
D32
D22
D23
D33
D11
D02
D12
D01
D13
D03
0000H
TABnCE bit
TIABn0 pin input
TABnCCR0 register
0000
D00
D01
D02
D03
INTTABnCC0 signal
TIABn1 pin input
TABnCCR1 register
0000
D10
D11
D12
D13
INTTABnCC1 signal
TIABn2 pin input
TABnCCR2 register
0000
D20
D21
D22
D23
INTTABnCC2 signal
TIABn3 pin input
TABnCCR3 register
0000
D30
D31
D32
D33
INTTABnCC3 signal
INTTABnOV signal
TABnOVF bit
Cleared to 0 by
CLR instruction
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Cleared to 0 by Cleared to 0 by
CLR instruction CLR instruction
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Figure 8-31. Register Setting in Free-Running Timer Mode (1/3)
(a) TABn control register 0 (TABnCTL0)
TABnCE
TABnCTL0
0/1
TABnCKS2 TABnCKS1 TABnCKS0
0
0
0
0
0/1
0/1
0/1
Select count clockNote
0: Stop counting
1: Enable counting
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1
(b) TABn control register 1 (TABnCTL1)
TABnSYE TABnEST TABnEEE
TABnCTL1
0
0
0/1
TABnMD2 TABnMD1 TABnMD0
0
0
1
0
1
1, 0, 1:
Free-running mode
0: Operate with count
clock selected by
TABnCKS0 to TABnCKS2 bits
1: Count by external
event count input signal
(c) TABn I/O control register 0 (TABnIOC0)
TABnOL3 TABnOE3 TABnOL2 TABnOE2 TABnOL1 TABnOE1 TABnOL0 TABnOE0
TABnIOC0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0: Disable TOABn0 pin output
1: Enable TOABn0 pin output
Setting of output level with
operation of TOABn0 pin disabled
0: Low level
1: High level
0: Disable TOABn1 pin output
1: Enable TOABn1 pin output
Setting of output level with
operation of TOABn1 pin
disabled
0: Low level
1: High level
0: Disable TOABn2 pin output
1: Enable TOABn2 pin output
Setting of output level with
operation of TOABn2 pin
disabled
0: Low level
1: High level
0: Disable TOABn3 pin output
1: Enable TOABn3 pin output
Setting of output level with
operation of TOABn3 pin
disabled
0: Low level
1: High level
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Figure 8-31. Register Setting in Free-Running Timer Mode (2/3)
(d) TABn I/O control register 1 (TABnIOC1)
TABnIS7 TABnIS6 TABnIS5 TABnIS4 TABnIS3 TABnIS2 TABnIS1 TABnIS0
TABnIOC1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
Select valid edge
of TIABn0 pin input
Select valid edge
of TIABn1 pin input
Select valid edge
of TIABn2 pin input
Select valid edge
of TIABn3 pin input
(e) TABn I/O control register 2 (TABnIOC2)
TABnEES1 TABnEES0 TABnETS1 TABnETS0
TABnIOC2
0
0
0
0
0/1
0/1
0
0
Select valid edge of
external event count input
(f) TABn option register 0 (TABnOPT0)
TABnCCS3 TABnCCS2 TABnCCS1 TABnCCS0
TABnOPT0
0/1
0/1
0/1
0/1
TABnOVF
0
0
0
0/1
Overflow flag
Specifies if TABnCCR0
register functions as
capture or compare register
Specifies if TABnCCR1
register functions as
capture or compare register
Specifies if TABnCCR2
register functions as
capture or compare register
Specifies if TABnCCR3
register functions as
capture or compare register
(g) TABn counter read buffer register (TABnCNT)
The value of the 16-bit counter can be read by reading the TABnCNT register.
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Figure 8-31. Register Setting in Free-Running Timer Mode (3/3)
(h) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
These registers function as capture registers or compare registers according to the setting of the
TABnOPT0.TABnCCSm bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIABnm pin is detected.
When the registers function as compare registers and when Dm is set to the TABnCCRm register, the
INTTABnCCm signal is generated when the counter reaches (Dm + 1), and the output signal of the
TOABnm pin is inverted.
Remark
m = 0 to 3,
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(1) Operation flow in free-running timer mode
(a) When using capture/compare register as compare register
Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2)
FFFFH
D21
D00
D30
D20
16-bit counter
D21
D00
D30
D20
D10
D01
D31
D10
D11
D01
D31
D11
D11
0000H
TABnCE bit
TABnCCR0 register
D00
D01
Set value changed
INTTABnCC0 signal
TOABn0 pin output
D10
TABnCCR1 register
D11
Set value changed
INTTABnCC1 signal
TOABn1 pin output
TABnCCR2 register
D21
D20
Set value changed
INTTABnCC2 signal
TOABn2 pin output
TABnCCR3 register
D31
D30
Set value changed
INTTABnCC3 signal
TOABn3 pin output
INTTABnOV signal
TABnOVF bit
Cleared to 0 by
CLR instruction
Remark
Cleared to 0 by Cleared to 0 by
CLR instruction CLR instruction
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2)
Count operation start flow
START
Register initial setting
TABnCTL0 register
(TABnCKS0 to TABnCKS2 bits),
TABnCTL1 register,
TABnIOC0 register,
TABnIOC2 register,
TABnOPT0 register,
TABnCCR0 to TABnCCR3
registers
TABnCE bit = 1
The initial setting of these registers
is performed before setting the
TABnCE bit to 1.
The TABnCKS0 to TABnCKS2 bits
can be set at the same time
when counting has been started
(TABnCE bit = 1).
Overflow flag clear flow
Read TABnOPT0 register
(check overflow flag).
TABnOVF bit = 1
NO
YES
Execute instruction to clear
TABnOVF bit (CLR TABnOVF).
Count operation stop flow
TABnCE bit = 0
The counter is initialized and
counting is stopped by
clearing the TABnCE bit to 0.
STOP
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(b) When using capture/compare register as capture register
Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2)
FFFFH
D10
D30
D31
D21
D00
D20
16-bit counter
D32
D22
D23
D33
D11
D02
D12
D01
D13
D03
0000H
TABnCE bit
TIABn0 pin input
TABnCCR0 register
0000
D00
D01
D02
D03
0000
INTTABnCC0 signal
TIABn1 pin input
TABnCCR1 register
0000
D10
0000
D20
D11
D12
0000
D13
INTTABnCC1 signal
TIABn2 pin input
TABnCCR2 register
D21
D22
D23
0000
INTTABnCC2 signal
TIABn3 pin input
TABnCCR3 register
0000
D30
D31
D32
0000
D33
INTTABnCC3 signal
INTTABnOV signal
TABnOVF bit
Cleared to 0 by
CLR instruction
Remark
Cleared to 0 by Cleared to 0 by
CLR instruction CLR instruction
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2)
Count operation start flow
START
Register initial setting
TABnCTL0 register
(TABnCKS0 to TABnCKS2 bits),
TABnCTL1 register,
TABnIOC1 register,
TABnOPT0 register
TABnCE bit = 1
The initial setting of these registers
is performed before setting the
TABnCE bit to 1.
The TABnCKS0 to TABnCKS2 bits can
be set at the same time when counting
has been started (TABnCE bit = 1).
Overflow flag clear flow
Read TABnOPT0 register
(check overflow flag).
TABnOVF bit = 1
NO
YES
Execute instruction to clear
TABnOVF bit (CLR TABnOVF).
Count operation stop flow
TABnCE bit = 0
The counter is initialized and
counting is stopped by
clearing the TABnCE bit to 0.
STOP
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(2) Operation timing in free-running timer mode
(a) Interval operation with compare register
When TABn is used as an interval timer with the TABnCCRm register used as a compare register, software
processing is necessary for setting a comparison value to generate the next interrupt request signal each time
the INTTABnCCm signal has been detected.
FFFFH
D01
D11
D30
D04
D13
D31
D22
D03
D20
D10
16-bit counter
D12
D00
D23
D02
D21
0000H
TABnCE bit
TABnCCR0 register
D00
D01
D02
D03
D04
D05
INTTABnCC0 signal
TOABn0 pin output
Interval period Interval period Interval period Interval period Interval period
(D00 + 1)
(D01 − D00)
(10000H +
(D03 − D02)
(D04 − D03)
D02 − D01)
TABnCCR1 register
D10
D11
D12
D13
D14
INTTABnCC1 signal
TOABn1 pin output
Interval period
(D10 + 1)
TABnCCR2 register
Interval period
Interval period
Interval period
(D11 − D10) (10000H + D12 − D11) (D13 − D12)
D20
D21
D22
D23
INTTABnCC2 signal
TOABn2 pin output
Interval period
Interval period
Interval period
Interval period
(D20 + 1)
(10000H + D21 − D20) (D22 − D21) (10000H + D23 − D22)
TABnCCR3 register
D30
D31
D32
INTTABnCC3 signal
TOABn3 pin output
Interval period
(D30 + 1)
Remark
Interval period
(10000H + D31 − D30)
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
When performing an interval operation in the free-running timer mode, four intervals can be set with one
channel.
To perform the interval operation, the value of the corresponding TABnCCRm register must be re-set in the
interrupt servicing that is executed when the INTTABnCCm signal is detected.
The set value for re-setting the TABnCCRm register can be calculated by the following expression, where “Dm”
is the interval period.
Compare register default value: Dm − 1
Value set to compare register second and subsequent times: Previous set value + Dm
(If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the
register.)
Remark
m = 0 to 3,
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(b) Pulse width measurement with capture register
When pulse width measurement is performed with the TABnCCRm register used as a capture register,
software processing is necessary for reading the capture register each time the INTTABnCCm signal has been
detected and for calculating an interval.
FFFFH
16-bit counter
D10
D30
D31
D21
D00
D20
D13
D32
D23
D33
D11
D02
D12
D01
D22
D03
0000H
TABnCE bit
TIABn0 pin input
0000
TABnCCR0 register
D00
D01
D02
Pulse interval
(10000H +
D02 − D01)
Pulse interval
(10000H +
D03 − D02)
D03
INTTABnCC0 signal
Pulse interval Pulse interval
(D00 + 1)
(10000H +
D01 − D00)
TIABn1 pin input
TABnCCR1 register
0000
D10
D11
D12
D13
INTTABnCC1 signal
Pulse interval Pulse interval Pulse interval Pulse interval
(10000H +
(D13 − D12)
(D10 + 1)
(10000H +
D12 − D11)
D11 − D10)
TIABn2 pin input
TABnCCR2 register
0000
D21
D20
D22
D23
INTTABnCC2 signal
Pulse interval
(D20 + 1)
Pulse interval
(10000H +
D21 − D20)
Pulse interval
(20000H +
D22 − D21)
Pulse interval
(D23 − D22)
D31
D32
TIABn3 pin input
TABnCCR3 register
0000
D30
D33
INTTABnCC3 signal
Pulse interval Pulse interval
(D30 + 1)
(10000H +
D31 − D30)
Pulse interval
(10000H +
D32 − D31)
Pulse interval
(10000H +
D33 − D32)
INTTABnOV signal
TABnOVF bit
Cleared to 0 by
CLR instruction
Remark
Cleared to 0 by Cleared to 0 by
CLR instruction CLR instruction
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
When executing pulse width measurement in the free-running timer mode, four pulse widths can be measured
with one channel.
To measure a pulse width, the pulse width can be calculated by reading the value of the TABnCCRm register in
synchronization with the INTTABnCCm signal, and calculating the difference between the value read this time
and the previously read value.
Remark
m = 0 to 3,
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(c) Processing of overflow when two or more capture registers are used
Care must be exercised in processing the overflow flag when two or more capture registers are used. First, an
example of incorrect processing is shown below.
Example of incorrect processing when two or more capture registers are used
FFFFH
D11
D10
16-bit counter
D01
D00
0000H
TABnCE bit
TIABn0 pin input
TABnCCR0 register
D01
D00
TIABn1 pin input
D11
D10
TABnCCR1 register
INTTABnOV signal
TABnOVF bit
The following problem may occur when two pulse widths are measured in the free-running timer mode.
Read the TABnCCR0 register (setting of the default value of the TIABn0 pin input).
Read the TABnCCR1 register (setting of the default value of the TIABn1 pin input).
Read the TABnCCR0 register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 − D00).
Read the TABnCCR1 register.
Read the overflow flag. Because the flag is cleared in , 0 is read.
Because the overflow flag is 0, the pulse width can be calculated by (D11 − D10) (incorrect).
Remark
n = 0, 1
When two or more capture registers are used, and if the overflow flag is cleared to 0 by one capture register,
the other capture register may not obtain the correct pulse width.
Use software when using two or more capture registers. An example of how to use software is shown below.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
(1/2)
Example when two capture registers are used (using overflow interrupt)
FFFFH
D11
D10
16-bit counter
D01
D00
0000H
TABnCE bit
INTTABnOV signal
TABnOVF bit
TABnOVF0 flagNote
TIABn0 pin input
D01
D00
TABnCCR0 register
TABnOVF1 flagNote
TIABn1 pin input
D11
D10
TABnCCR1 register
Note The TABnOVF0 and TABnOVF1 flags are set in the internal RAM by software.
Read the TABnCCR0 register (setting of the default value of the TIABn0 pin input).
Read the TABnCCR1 register (setting of the default value of the TIABn1 pin input).
An overflow occurs. Set the TABnOVF0 and TABnOVF1 flags to 1 in the overflow interrupt servicing,
and clear the overflow flag to 0.
Read the TABnCCR0 register.
Read the TABnOVF0 flag. If the TABnOVF0 flag is 1, clear it to 0.
Because the TABnOVF0 flag is 1, the pulse width can be calculated by (10000H + D01 − D00).
Read the TABnCCR1 register.
Read the TABnOVF1 flag. If the TABnOVF1 flag is 1, clear it to 0 (the TABnOVF0 flag is cleared in
, and the TABnOVF1 flag remains 1).
Because the TABnOVF1 flag is 1, the pulse width can be calculated by (10000H + D11 − D10)
(correct).
Same as
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(2/2)
Example when two capture registers are used (without using overflow interrupt)
FFFFH
D11
D10
16-bit counter
D01
D00
0000H
TABnCE bit
INTTABnOV signal
TABnOVF bit
TABnOVF0 flagNote
TIABn0 pin input
D01
D00
TABnCCR0 register
TABnOVF1 flagNote
TIABn1 pin input
D11
D10
TABnCCR1 register
Note The TABnOVF0 and TABnOVF1 flags are set in the internal RAM by software.
Read the TABnCCR0 register (setting of the default value of the TIABn0 pin input).
Read the TABnCCR1 register (setting of the default value of the TIABn1 pin input).
An overflow occurs. Nothing is done by software.
Read the TABnCCR0 register.
Read the overflow flag. If the overflow flag is 1, set only the TABnOVF1 flag to 1, and clear the
overflow flag to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 − D00).
Read the TABnCCR1 register.
Read the overflow flag. Because the overflow flag is cleared in , 0 is read.
Read the TABnOVF1 flag. If the TABnOVF1 flag is 1, clear it to 0.
Because the TABnOVF1 flag is 1, the pulse width can be calculated by (10000H + D11 − D10)
(correct).
Same as
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(d) Processing of overflow if capture trigger interval is long
If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow
may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is
shown below.
Example of incorrect processing when capture trigger interval is long
FFFFH
Dm0
16-bit counter
Dm1
0000H
TABnCE bit
TIABnm pin input
TABnCCRm register
Dm0
Dm1
INTTABnOV signal
TABnOVF bit
1 cycle of 16-bit counter
Pulse width
The following problem may occur when a long pulse width is measured in the free-running timer mode.
Read the TABnCCRm register (setting of the default value of the TIABnm pin input).
An overflow occurs. Nothing is done by software.
An overflow occurs a second time. Nothing is done by software.
Read the TABnCCRm register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + Dm1 − Dm0)
(incorrect).
Actually, the pulse width must be (20000H + Dm1 − Dm0) because an overflow occurs twice.
Remark
m = 0 to 3,
n = 0, 1
If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be
obtained.
If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use
software. An example of how to use software is shown next.
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Example when capture trigger interval is long
FFFFH
Dm0
16-bit counter
Dm1
0000H
TABnCE bit
TIABnm pin input
TABnCCRm register
Dm0
Dm1
INTTABnOV signal
TABnOVF bit
Overflow counterNote
0H
1H
2H
0H
1 cycle of 16-bit counter
Pulse width
Note The overflow counter is set arbitrarily by software in the internal RAM.
Read the TABnCCRm register (setting of the default value of the TIABnm pin input).
An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow
interrupt servicing.
An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to
0 in the overflow interrupt servicing.
Read the TABnCCRm register.
Read the overflow counter.
When the overflow counter is “N”, the pulse width can be calculated by (N × 10000H + Dm1 – Dm0).
In this example, the pulse width is (20000H + Dm1 – Dm0) because an overflow occurs twice.
Clear the overflow counter (0H).
Remark
m = 0 to 3,
n = 0, 1
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(e) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TABnOVF bit to 0 with the CLR instruction and by writing
8-bit data (bit 0 is 0) to the TABnOPT0 register. To accurately detect an overflow, read the TABnOVF bit when it
is 1, and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting)
Overflow
set signal
L
0 write signal
Overflow flag
(TABnOVF bit)
(iii) Operation to clear to 0 (without conflict with setting)
Overflow
set signal
L
0 write signal
Register
access signal
Read
Write
Overflow flag
(TABnOVF bit)
(ii) Operation to write 0 (conflict with setting)
Overflow
set signal
0 write signal
Overflow flag
(TABnOVF bit)
(iv) Operation to clear to 0 (conflict with setting)
Overflow
set signal
0 write signal
Register
access signal
Overflow flag
(TABnOVF bit)
Remark
Read
Write
H
n = 0, 1
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set overflow information may
be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred
even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to
0 with the CLR instruction, the overflow flag remains set even after execution of the CLR instruction.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Pulse width measurement mode (TABnMD2 to TABnMD0 bits = 110)
In the pulse width measurement mode, TABn starts counting when the TABnCTL0.TABnCE bit is set to 1. Each time
the valid edge input to the TIABnm pin has been detected, the count value of the 16-bit counter is stored in the
TABnCCRm register, and the 16-bit counter is cleared to 0000H.
The interval of the valid edge can be measured by reading the TABnCCRm register after a capture interrupt request
signal (INTTABnCCm) occurs.
Select one of the TIABn0 to TIABn3 pins as the capture trigger input pin. Specify “No edge detected” for the unused
pins by using the TABnIOC1 register.
When an external clock is used as the count clock, measure the pulse width of the TIAB0k pin because the external
clock is fixed to the TIAB00 pin. At this time, clear the TAB0IOC1.TAB0IS1 and TAB0IOC1.TAB0IS0 bits to 00 (capture
trigger input (TIAB00 pin): No edge detected).
For TAB1, the external clock is input from the EVTAB1 pin, and the pulse width can be measured by using the TIAB10
to TIAB13 pins.
Remark
m = 0 to 3,
n = 0, 1
k = 1 to 3
Figure 8-34. Configuration in Pulse Width Measurement Mode
Internal count clock
TIAB00 pin
(external event
count inputNote/
capture
trigger input)
Edge
detector
Count
clock
selection
Clear
16-bit counter
TABnCE
bit
Edge
detector
INTTABnCC0 signal
TABnCCR0
register
(capture)
TIABn1 pin
(capture
trigger input)
INTTABnOV signal
INTTABnCC1 signal
Edge
detector
TABnCCR1
register
(capture)
TIABn2 pin
(capture
trigger input)
INTTABnCC2 signal
INTTABnCC3 signal
Edge
detector
TABnCCR2
register
(capture)
TIABn3 pin
(capture
trigger input)
Edge
detector
TABnCCR3
register
(capture)
Note TAB1: EVTAB1 pin
Remark
n = 0, 1
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Figure 8-35. Basic Timing in Pulse Width Measurement Mode
FFFFH
16-bit counter
0000H
TABnCE bit
TIABnm pin input
TABnCCRm register
0000H
D0
D1
D2
D3
INTTABnCCm signal
INTTABnOV signal
TABnOVF bit
Remark
Cleared to 0 by
CLR instruction
m = 0 to 3,
n = 0, 1
When the TABnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIABnm pin is
later detected, the count value of the 16-bit counter is stored in the TABnCCRm register, the 16-bit counter is cleared to
0000H, and a capture interrupt request signal (INTTABnCCm) is generated.
The pulse width is calculated as follows.
Pulse width = Captured value × Count clock cycle
If the valid edge is not input to the TIABnm pin even when the 16-bit counter has counted up to FFFFH, an overflow
interrupt request signal (INTTABnOV) is generated at the next count clock, and the counter is cleared to 0000H and
continues counting. At this time, the overflow flag (TABnOPT0.TABnOVF bit) is also set to 1. Clear the overflow flag to 0
by executing the CLR instruction via software.
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Pulse width = (10000H × TABnOVF bit setting (1) count + Captured value) × Count clock cycle
Remark
m = 0 to 3,
n = 0, 1
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Figure 8-36. Register Setting in Pulse Width Measurement Mode (1/2)
(a) TABn control register 0 (TABnCTL0)
TABnCE
TABnCTL0
0/1
TABnCKS2 TABnCKS1 TABnCKS0
0
0
0
0
0/1
0/1
0/1
Select count clockNote
0: Stop counting
1: Enable counting
Note The setting is invalid when the TABnEEE bit = 1.
(b) TABn control register 1 (TABnCTL1)
TABnMD2 TABnMD1 TABnMD0
TABnEST TABnEEE
TABnCTL1
0
0
0/1
0
0
1
1
0
1, 1, 0:
Pulse width measurement mode
0: Operate on count clock
selected by TABnCKS0 to
TABnCKS2 bits
1: Count by external event
count input signal
(c) TABn I/O control register 1 (TABnIOC1)
TABnIS7 TABnIS6 TABnIS5 TABnIS4 TABnIS3 TABnIS2 TABnIS1 TABnIS0
TABnIOC1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
Select valid edge
of TIABn0 pin input
Select valid edge
of TIABn1 pin input
Select valid edge
of TIABn2 pin input
Select valid edge
of TIABn3 pin input
(d) TABn I/O control register 2 (TABnIOC2)
TABnEES1 TABnEES0 TABnETS1 TABnETS0
TABnIOC2
0
0
0
0
0/1
0/1
0
0
Select valid edge of
external event count input
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Figure 8-36. Register Setting in Pulse Width Measurement Mode (2/2)
(e) TABn option register 0 (TABnOPT0)
TABnOVF
TABnCCS3 TABnCCS2 TABnCCS1 TABnCCS0
TABnOPT0
0
0
0
0
0
0
0
0/1
Overflow flag
(f) TABn counter read buffer register (TABnCNT)
The value of the 16-bit counter can be read by reading the TABnCNT register.
(g) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
These registers store the count value of the 16-bit counter when the valid edge input to the TIABnm pin is
detected.
Remarks 1.
2.
TABn I/O control register 0 (TABnIOC0) is not used in the pulse width measurement mode.
m = 0 to 3,
n = 0, 1
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(1) Operation flow in pulse width measurement mode
Figure 8-37. Software Processing Flow in Pulse Width Measurement Mode
FFFFH
16-bit counter
0000H
TABnCE bit
TIABn0 pin input
0000H
TABnCCR0 register
D0
D1
D2
0000H
INTTABnCC0 signal
Count operation start flow
START
Register initial setting
TABnCTL0 register
(TABnCKS0 to TABnCKS2 bits),
TABnCTL1 register,
TABnIOC1 register,
TABnIOC2 register,
TABnOPT0 register
Set TABnCTL0 register
(TABnCE bit = 1)
The initial setting of these registers
is performed before setting the
TABnCE bit to 1.
The TABnCKS0 to TABnCKS2 bits can
be set at the same time when counting
has been started (TABnCE bit = 1).
Count operation stop flow
TABnCE bit = 0
The counter is initialized and counting
is stopped by clearing the TABnCE bit to 0.
STOP
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(2) Operation timing in pulse width measurement mode
(a) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TABnOVF bit to 0 with the CLR instruction and by writing
8-bit data (bit 0 is 0) to the TABnOPT0 register. To accurately detect an overflow, read the TABnOVF bit when it
is 1, and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting)
Overflow
set signal
L
0 write signal
Overflow flag
(TABnOVF bit)
(iii) Operation to clear to 0 (without conflict with setting)
Overflow
set signal
L
0 write signal
Register
access signal
Read
Write
Overflow flag
(TABnOVF bit)
(ii) Operation to write 0 (conflict with setting)
Overflow
set signal
0 write signal
Overflow flag
(TABnOVF bit)
(iv) Operation to clear to 0 (conflict with setting)
Overflow
set signal
0 write signal
Register
access signal
Overflow flag
(TABnOVF bit)
Remark
Read
Write
H
n = 0, 1
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set overflow information may
be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred
even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to
0 with the CLR instruction, the overflow flag remains set even after execution of the CLR instruction.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Triangular wave PWM mode (TABnMD2 to TABnMD0 bits = 111)
In the triangular wave PWM mode, TABn capture/compare register k (TABnCCRk) is used to set the duty factor, and
TABn capture/compare register 0 (TABnCCR0) is used to set the cycle.
By using these four registers and operating the timer, triangular wave PWM with a variable cycle is output.
The value of the TABnCCRm register can be rewritten when TABnCE = 1.
To stop timer AB, clear TABnCE to 0. The PWM waveform is output from the TOABnk pin. The TOABn0 pin produces a
toggle output when the value of the 16-bit counter matches the value of the TABnCCR0 register and when the counter
underflows.
Caution
In the PWM mode, the capture function of the TABnCCRm register cannot be used because this
register can be used only as a compare register.
Remark
n = 0, 1, m = 0 to 3, k = 1 to 3
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Figure 8-38. Timing of Basic Operation in Triangular Wave PWM Mode
(TABnOE0 = 1, TABnOE1 = 1, TABnOE2 = 1, TABnOE3 = 1,
TABnOL0 = 0, TABnOL1 = 0, TABnOL2 = 0, TABnOL3 = 0)
TABnCE = 1
FFFFH
D00
16-bit
counter
D30
D20
D10
D00
D30
D30
D00
D30
D20 D20
D10
D30
D20 D20
D10
TABnCCR0 0000H
D00
TABnCCR1 0000H
D10
TABnCCR2 0000H
D20
TABnCCR3 0000H
D30
D30
D20
INTTABnCC0
match interrupt
INTTABnCC1
match interrupt
INTTABnCC2
match interrupt
INTTABnCC3
match interrupt
INTTABnOV
TOABn0
TOABn1
TOABn2
TOABn3
Remark
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Timer output operations
The following table shows the operations and output levels of the TOABn0 to TOABn3 pins.
Table 8-6. Timer Output Control in Each Mode
Operation Mode
TOABn0 Pin
Interval timer mode
Square wave output
External event count mode
Square wave output
External trigger pulse output mode
Square wave output
One-shot pulse output mode
PWM output mode
Free-running timer mode
TOABn1 Pin
TOABn2 Pin
TOABn3 Pin
−
External trigger pulse
External trigger pulse
External trigger pulse
output
output
output
One-shot pulse
One-shot pulse
One-shot pulse
output
output
output
PWM output
PWM output
PWM output
Square wave output (only when compare function is used)
−
Pulse width measurement mode
Triangular wave PWM output mode
Square wave output
Triangular PWM
Triangular PWM
Triangular PWM
output
output
output
Table 8-7. Truth Table of TOABn0 to TOABn3 Pins Under Control of Timer Output Control Bits
TABnIOC0.TABnOLm Bit
TABnIOC0.TABnOEm Bit
TABnCTL0.TABnCE Bit
Level of TOABnm Pin
0
0
×
Low-level output
1
0
Low-level output
1
Low level immediately before counting,
0
×
High-level output
1
0
High-level output
1
High level immediately before counting, low
high level after counting is started
1
level after counting is started
Remark
m = 0 to 3,
n = 0, 1
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Timer-Tuned Operation Function/Simultaneous-Start Function
Timer AA and timer AB have a timer-tuned operation function/simultaneous-start function.
The timers that can be synchronized are listed in Table 8-8.
Table 8-8. Timer-Tuned Operation Mode
Master Timer
Slave Timer
TAA1
TAA0
TAA3
TAA2
TAB0
TAA5
For details of the timer-tuned operation function, see 7.6 Timer-Tuned Operation Function, and for details of the
simultaneous-start function, see 7.7 Simultaneous-Start Function.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Cautions
(1) Capture operation
When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be
captured in the TABnCCR0, TABnCCR1, TABnCCR2, and TABnCCR3 registers if the capture trigger is input
immediately after the TABnCE bit is set to 1.
(a) Free-running timer mode
FFFFH
16-bit counter
0000H
Count clock
Sampling clock (fXX)
TABnCCR0 register
0000H
FFFFH
0001H
TABnCE bit
TIABn0 pin input
Capture
trigger input
Capture
trigger input
(b) Pulse width measurement mode
FFFFH
16-bit counter
0000H
Count clock
Sampling clock (fXX)
TABnCCR0 register 0000H
FFFFH
0002H
TABnCE bit
TIABn0 pin input
Capture
trigger input
Remark
Capture
trigger input
n = 0, 1
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Timer T (TMT) is a 16-bit timer/event counter.
An encoder count function and other functions are added to timer AA (TAA). However, TMT does not have a function to
operate with an external event count input when it operates in the interval timer mode.
The V850ES/JG3-H and V850ES/JH3-H have one TMT channel.
9.1
Overview
An overview of TMT0 is given below.
• Clock selection:
8 types
• Capture trigger input pins (TIT00, TIT01):
2
• External event count input pin (EVTT0):
1
• Encoder input pins (TENC00, TENC01):
2
• Encoder clear input pin (TECR0):
1
• External trigger input pinNote:
1
• Timer counter:
1
• Capture/compare registers:
2
• Capture/compare match interrupt request signals: 2
• Timer output pins:
2
Note The external trigger input pin and external event count input pin (EVTT0) are shared with an encoder input pin
(TENC00).
9.2
Functions
The functions of TMT0 are shown below.
• Interval timer
• External event counter
• External trigger pulse output
• One-shot pulse output
• PWM output
• Free-running timer
• Pulse width measurement
• Triangular-wave PWM output
• Encoder count
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Configuration
TMT0 includes the following hardware.
Table 9-1. Configuration of TMT0
Item
Registers
Configuration
16-bit counter × 1
TMT0 capture/compare registers 0, 1 (TT0CCR0, TT0CCR1)
TMT0 counter read buffer register (TT0CNT)
TMT0 counter write register (TT0TCW)
CCR0, CCR1 buffer registers
TMT0 control registers 0, 1 (TT0CTL0, TT0CTL1)
TMT0 control registers 2 (TT0CTL2)
TMT0 I/O control registers 0 to 3 (TT0IOC0 to TT0IOC3)
TMT0 option register 0 (TT0OPT0)
TMT0 option register 1 (TT0OPT1)
TMT noise elimination control register (TTNFC)
Timer input
• TIT00, TIT01 (capture trigger input pins)
• EVTT0/TENC00 (external event input/encoder 0 input pin)
Note
• TENC01 (encoder 1 input pin)
• TENCR0 (encoder clear input pin)
Timer output
TOT00, TOT01
Note Shared with the external trigger input function
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Figure 9-1. Block Diagram of TMT0
Internal bus
Counter
control
Edge detection/
Noise eliminator
EVTT0/TENC00Note
Edge detection/
Noise eliminator
TENC01
Edge detection/
Noise eliminator
TIT00
Edge detection/
Noise eliminator
TIT01
Edge detection/
Noise eliminator
fXX
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
Selector
TECR0
TT0TCW
INTTT0OV
16-bit counter
Clear
Output
controller
fXX
fXX/2
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
fXX/128
Selector
TT0CNT
CCR0
buffer
register
CCR1
buffer
register
TT0CCR0
TOT00
TOT01
INTTT0CC0
INTTT0CC1
TT0CCR1
INTTT0EC
Sampling
clock
Internal bus
Note Shared with the external trigger input function
Remark
fXX: Peripheral clock
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(1) 16-bit counter
This 16-bit counter can count internal clocks or external events.
The count value of this counter can be read by using the TT0CNT register.
When the TT0CTL0.TT0CE bit = 0, the value of the 16-bit counter is FFFFH. If the TT0CNT register is read at this
time, 0000H is read.
Reset sets the TT0CE bit to 0.
(2) CCR0 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TT0CCR0 register is used as a compare register, the value written to the TT0CCR0 register is
transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0
buffer register, a compare match interrupt request signal (INTTTCC00) is generated.
The CCR0 buffer register cannot be read or written directly.
The CCR0 buffer register is set to 0000H after reset, and the TT0CCR0 register is set to 0000H.
(3) CCR1 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TT0CCR1 register is used as a compare register, the value written to the TT0CCR1 register is
transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1
buffer register, a compare match interrupt request signal (INTTTCC01) is generated.
The CCR1 buffer register cannot be read or written directly.
The CCR1 buffer register is set to 0000H after reset, and the TT0CCR1 register is set to 0000H.
(4) Edge detector
This circuit detects the valid edges input to the TIT00, TIT01, EVTT0/TENC00, TENC01, and TECR0 pins. No edge,
rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the
TT0IOC1, TT0IOC2, and TT0IOC3 registers.
(5) Output controller
This circuit controls the output of the TOT00 and TOT01 pins via the TT0IOC0 register.
(6) Selector
This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can
be selected as the count clock.
(7) Counter control
The count operation is controlled by the timer mode selected by the TT0CTL1 register.
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9.3.1
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Pin configuration
The timer inputs and outputs that configure TMT0 are shared with the following ports. The port functions must be set
when using each pin (see Table 4-20 Using Port Pin as Alternate-Function Pin).
Table 9-2. Pin Configuration
Port
Timer Input Pin
Timer Output
Other Alternate Function
Note 1
P92
TIT01 (capture trigger input 1)
TENC01 (encoder input)
TOT01
A2
P93
TIT00 (capture trigger input 0)
TECR0 (encoder clear input)
TOT00
A3
P94
EVTT0/TENC00
Note 2
−
−
Note 1
−
Notes 1. V850ES/JH3-H only
2. The external event count input (EVTT0), encoder input (TENC00), and external trigger input are shared in a
state that cannot be controlled by using the port functions. To use each function, set them by using the
TT0IOC2 and TT0IOC3 registers after setting their corresponding ports.
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9.4
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Registers
(1) TMT0 control register 0 (TT0CTL0)
The TT0CTL0 register is an 8-bit register that controls the operation of TMT0.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The same value can always be written to the TT0CTL0 register by software.
After reset: 00H
TT0CTL0
R/W
Address: FFFF600H
6
5
4
3
TT0CE
0
0
0
0
TT0CE
2
1
0
TT0CKS2 TT0CKS1 TT0CKS0
TMT0 operation control
0
TMT0 operation disabled (TMT0 reset asynchronouslyNote)
1
TMT0 operation enabled. TMT0 operation start
Internal count clock selection
TT0CKS2 TT0CKS1 TT0CKS0
0
0
0
fXX
0
0
1
fXX/2
0
1
0
fXX/4
0
1
1
fXX/8
1
0
0
fXX/16
1
0
1
fXX/32
1
1
0
fXX/64
1
1
1
fXX/128
Note The TT0OPT0.TT0OVF bit and 16-bit counter are reset simultaneously.
Moreover, timer outputs (TOT00 and TOT01) are reset at the same time as the
16-bit counter.
Cautions 1. Set the TT0CKS2 to TT0CKS0 bits when the TT0CE bit = 0.
When the value of the TT0CE bit is changed from 0 to 1, the TT0CKS2
to TT0CKS0 bits can be set simultaneously.
2. Be sure to set bits 3 to 6 to “0”.
Remark
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(2) TMT0 control register 1 (TT0CTL1)
The TT0CTL1 register is an 8-bit register that controls the TMT0 operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(1/2)
After reset: 00H
TT0CTL1
R/W
Address: FFFFF601H
7
6
5
4
0
TT0EST
TT0EEE
0
3
1
0
Software trigger control
TT0EST
−
0
1
2
TT0MD3 TT0MD2 TT0MD1 TT0MD0
Generates a valid signal for external trigger input.
• In one-shot pulse output mode: A one-shot pulse is output with writing
1 to the TT0EST bit as the trigger.
• In external trigger pulse output mode: A PWM waveform is output with
writing 1 to the TT0EST bit as the trigger.
The read value of the TT0EST bit is always 0.
TT0EEE
Count clock selection
0
Disables operation with external event count input (EVTT0 pin).
(Performs counting with the count clock selected by the
TT0CTL0.TT0CKS0 to TT0CTL0.TT0CKS2 bits.)
1
Enables operation with external event count input (EVTT0 pin).
(Performs counting at every valid edge of the external event count input
signal (EVTT0 pin).)
The TT0EEE bit selects whether counting is performed with the internal count clock
or the valid edge of the external event count input.
TT0MD3 TT0MD2 TT0MD1 TT0MD0
0
0
0
0
Interval timer mode
0
0
0
1
External event count mode
0
0
1
0
External trigger pulse output mode
0
0
1
1
One-shot pulse output mode
0
1
0
0
PWM output mode
0
1
0
1
Free-running timer mode
0
1
1
0
Pulse width measurement mode
0
1
1
1
Triangular-wave PWM output mode
1
0
0
0
Encoder compare mode
Other than above
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Setting prohibited
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(2/2)
Cautions 1. The TT0EST bit is valid only in the external trigger pulse output mode or one-shot pulse
output mode. In any other mode, writing 1 to this bit is ignored.
2. The TT0EEE bit is valid only in the interval timer mode, external trigger pulse output mode,
one-shot pulse output mode, PWM output mode, free-running timer mode, pulse width
measurement mode, or triangular-wave PWM output mode. In any other mode, writing 1 to
this bit is ignored.
3. External event count input (EVTT0) or encoder inputs (TENC00, TENC01) is selected in the
external event count mode or encoder compare mode regardless of the value of the
TT0EEE bit.
4. Set the TT0EEE and TT0MD3 to TT0MD0 bits when the TT0CTL0.TT0CE bit = 0. (The same
value can be written when the TT0CE bit = 1.) The operation is not guaranteed when
rewriting is performed with the TT0CE bit = 1. If rewriting was mistakenly performed, clear
the TT0CE bit to 0 and then set the bits again.
5. Be sure to set bits 4 and 7 to “0”.
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(3) TMT0 control register 2 (TT0CTL2)
The TT0CTL2 register is an 8-bit register that controls the encoder count function operation.
The TT0CTL2 register is valid only in the encoder compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution
For details of each bit of the TT0CTL2 register, see 9.6.9 (5) Controlling bits of TT0CTL2 register.
(1/2)
After reset: 00H
7
TT0CTL2
TT0ECC
R/W
6
0
Address: FFFFF602H
5
4
0
3
2
1
0
TT0LDE TT0ECM1 TT0ECM0 TT0UDS1 TT0UDS0
TT0ECC
Encoder counter control
0
Normal operation
1
Holds count value of 16-bit counter when TT0CTL0.TT0CE bit = 0.
TT0LDE
Transfer setting to 16-bit counter
0
Disables transfer of set value of TT0CCR0 to 16-bit counter in case of underflow.
1
Enables transfer of set value of TT0CCR0 to 16-bit counter in case of underflow.
TT0ECM1
Control of encoder clear operation 1
0
The 16-bit counter is not cleared to 0000H when its count value matches
value of CCR1 register.
1
The 16-bit counter is cleared to 0000H when the count after a match between
the 16-bit counter count value and CCR1 register value is a down-count
TT0ECM0
0
Control of encoder clear operation 0
The 16-bit counter is not cleared to 0000H when its count value matches
value of CCR0 register.
1
The 16-bit counter is cleared to 0000H when the count after a match between
the 16-bit counter count value and CCR0 register value is an up-count
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(2/2)
Up/down count selection
TT0UDS1 TT0UDS0
0
0
When valid edge of TENC00 input is detected
Counts down when TENC01 = high level.
Counts up when TENC01 = low level.
0
1
1
0
Counts up when valid edge of TENC00 input is detected.
Counts down when valid edge of TENC01 input is detected.
Counts down when rising edge of TENC00 input is detected.
Counts up when falling edge of TENC00 input is detected.
However, count operation is performed only when
TENC01 = low level.
1
1
Both rising and falling edges of TENC00 and TENC01 are
detected. Count operation is automatically identified by
combination of edge detection and level detection.
Cautions 1. The TT0ECC bit is valid only in the encoder compare mode. In any other
mode, writing “1” to this bit is ignored.
If the TT0CTL0.TT0CE bit is cleared to 0 while the TT0ECC bit = 1, the
values of the timer/counter and capture registers (TT0CCR0 and
TT0CCR1), and the TT0OPT1, TT0EUF, TT0EOF, and TT0ESF flags are
retained.
If the TT0CE bit is set from 0 to 1 when the TT0ECC bit = 1, the value of the
TT0TCW register is not transferred to the 16-bit counter.
2. The TT0LDE bit is valid only when the TT0ECM1 and TT0ECM0 bits = 00,
01. Writing “1” to this bit is ignored when the TT0ECM1 and TT0ECM0 bits
= 10, 11.
3. The edge detection of the TENC00 and TENC01 inputs specified by the
TT0IOC3.TT0EIS1 and TT0IOC3.TT0EIS0 bits is invalid and fixed to both
the rising and falling edges when the TT0UDS1 and TT0UDS0 bits = 10, 11.
4. Set the TT0LDE, TT0ECM1, TT0ECM0, TT0UDS1, and TT0UDS0 bits when
the TT0CTL0.TT0CE bit = 0 (the same value can be written to these bits
when the TT0CE bit = 1). If the value of these bits is changed when the
TT0CE bit = 1, the operation cannot be guaranteed. If it is changed by
mistake, clear the TT0CE bit and then set the correct value.
5. Be sure to set bits 5 and 6 to “0”.
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(4) TMT0 I/O control register 0 (TT0IOC0)
The TT0IOC0 register is an 8-bit register that controls the timer output (TOT00, TOT01 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
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After reset: 00H
TT0IOC0
R/W
Address: FFFFF603H
7
6
5
4
0
0
0
0
3
TT0OL1 TT0OE1
1
TT0OL0
TT0OE0
TOT01 pin output level settingNote
TT0OL1
0
TOT01 pin starts output at high level.
1
TOT01 pin starts output at low level.
TT0OE1
TOT01 pin output setting
0
Timer output prohibited
• Low level is output from the TOT01 pin when the TT0OL1 bit = 0.
• High level is output from the TOT01 pin when the TT0OL1 bit = 1.
1
Timer output enabled (A pulse is output from the TOT01 pin.)
TOT00 pin output level settingNote
TT0OL0
0
TOT00 pin starts output at high level.
1
TOT00 pin starts output at low level.
TT0OE0
TOT00 pin output setting
0
Timer output prohibited
• Low level is output from the TOT00 pin when the TT0OL0 bit = 0.
• High level is output from the TOT00 pin when the TT0OL0 bit = 1.
1
Timer output enabled (A pulse is output from the TOT00 pin.)
Note The output level of the timer output pins (TOT00 and TOT01) specified by the
TT0OLn bit is shown below (n = 0, 1).
• When TT0OLn bit = 0
• When TT0OLn bit = 1
16-bit counter
16-bit counter
TT0CE bit
TT0CE bit
TOT0n pin output
TOT0n pin output
Cautions 1. If the setting of the TT0IOC0 register is changed when TOT00 and
TOT01 outputs are set for the port mode, the output of the pins
change. Set the port in the input mode and make the port go into a
high-impedance state, noting changes in the pin status.
2. Rewrite the TT0OL1, TT0OE1, TT0OL0, and TT0OE0 bits when the
TT0CTL0.TT0CE bit = 0. (The same value can be written when the
TT0CE bit = 1.)
If rewriting was mistakenly performed, clear the
TT0CE bit to 0 and then set the bits again.
3. Even if the TT0OL0 or TT0OL1 bit is manipulated when the TT0CE,
TT0OE0, and TT0OE1 bits are 0, the output level of the TOT00 and
TOT01 pins changes.
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(5) TMT0 I/O control register 1 (TT0IOC1)
The TT0IOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals (TIT00,
TIT01 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address: FFFFF604H
7
6
5
4
3
2
1
0
0
0
0
0
TT0IS3
TT0IS2
TT0IS1
TT0IS0
TT0IS3
TT0IS2
0
0
No edge detection (capture operation invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
TT0IS1
TT0IS0
0
0
No edge detection (capture operation invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
TT0IOC1
Capture trigger input signal (TIT01 pin) valid edge setting
Capture trigger input signal (TIT00 pin) valid edge setting
Cautions 1. Rewrite the TT0IS3 to TT0IS0 bits when the TT0CTL0.TT0CE bit = 0.
(The same value can be written when the TT0CE bit = 1.) If rewriting
was mistakenly performed, clear the TT0CE bit to 0 and then set the
bits again.
2. The TT0IS3 and TT0IS2 bits are valid only in the free-running timer
mode (only when the TT0OPT0.TT0CCS1 bit = 1) and the pulse width
measurement mode. In all other modes, a capture operation is not
performed.
The TT0IS1 and TT0IS0 bits are valid only in the free-running timer
mode (only when the TT0OPT0. TT0CCS0 bit = 1) and the pulse width
measurement mode. In all other modes, a capture operation is not
performed.
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(6) TMT0 I/O control register 2 (TT0IOC2)
The TT0IOC2 register is an 8-bit register that controls the valid edge for the external event count input signal
(EVTT0 pin) and external trigger input signal (EVTT0 pin).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
TT0IOC2
R/W
Address: FFFFF605H
7
6
5
4
0
0
0
0
3
2
1
0
TT0EES1 TT0EES0 TT0ETS1 TT0ETS0
TT0EES1 TT0EES0 External event count input signal (EVTT0 pin) valid edge setting
0
0
No edge detection (external event count invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
TT0ETS1 TT0ETS0
External trigger input signal (EVTT0 pin) valid edge setting
0
0
No edge detection (external trigger invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
Cautions 1. Rewrite the TT0EES1, TT0EES0, TT0ETS1, and TT0ETS0 bits when the
TT0CTL0.TT0CE bit = 0. (The same value can be written when the
TT0CE bit = 1.)
If rewriting was mistakenly performed, clear the
TT0CE bit to 0 and then set the bits again.
2. The
TT0EES1
and
TT0EES0
bits
are
valid
only
when
the
TT0CTL1.TT0EEE bit = 1 or when the external event count mode (the
TT0CTL1.TT0MD3 to TT0CTL1.TT0MD0 bits = 0001) has been set.
3. The TT0ETS1 and TT0ETS0 bits are valid only in the external trigger
pulse mode or one-shot pulse output mode.
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(7) TMT0 I/O control register 3 (TT0IOC3)
The TT0IOC3 register is an 8-bit register that controls the encoder clear function operation.
The TT0IOC3 register is valid only in the encoder compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(1/2)
After reset: 00H
7
TT0IOC3
R/W
Address: FFFFF606H
6
5
TT0SCE TT0ZCL
4
3
2
1
0
TT0BCL TT0ACL TT0ECS1 TT0ECS0 TT0EIS1 TT0EIS0
TT0SCE
Encoder clear selection
0
Clears 16-bit counter on detection of edge of encoder clear signal (TECR0 pin).
1
Clears 16-bit counter on detection of clear level condition of the TENC00,
TENC01, and TECR0 pins.
• Clears the 16-bit counter to 0000H when the valid edge of TECR0 pin specified by
the TT0ECS1 and TT0ECS0 bits is detected when the TT0SCE bit = 0.
• Clears the 16-bit counter to 0000H when the clear level conditions of the TT0ZCL,
TT0BCL, and TT0ACL bits match the input levels of the TECR0, TENC01, and
TENC00 pins when TT0SCE bit = 1.
• Setting of the TT0ZCL, TT0BCL, and TT0ACL bits is valid and that of the
TT0ECS1 and TT0ECS0 bits is invalid when the TT0SCE bit = 1.
An encoder clear interrupt request signal (INTTTI0EC) is not generated.
• Setting of the TT0ZCL, TT0BCL, and TT0ACL bits is invalid and setting of
the TT0ECS1 and TT0ECS0 bits is valid when the TT0SCE bit = 0.
The INTTTI0EC signal is generated when the valid edge specified by the TT0ECS1
and TT0ECS0 bits is detected.
• Be sure to set the TT0CTL2.TT0UDS1 and TT0CTL2.TT0UDS0 bits to 10 or 11
when the TT0SCE bit = 1.
Operation is not guaranteed if the TT0UDS1 and TT0UDS0 bits = 00 or 01 and
the TT0SCE bit = 1.
TT0ZCL
Clear level selection of encoder clear signal (TECR0 pin)
0
Clears low level of the TECR0 pin.
1
Clears high level of the TECR0 pin.
Setting of the TT0ZCL bit is valid only when the TT0SCE bit = 1.
TT0BCL
Clear level selection of encoder input signal (TENC01 pin)
0
Clears low level of the TENC01 pin.
1
Clears high level of the TENC01 pin.
Setting of the TT0BCL bit is valid only when the TT0SCE bit = 1.
TT0ACL
Clear level selection of encoder input signal (TENC00 pin)
0
Clears low level of the TENC00 pin.
1
Clears high level of the TENC00 pin.
Setting of the TT0ACL bit is valid only when the TT0SCE bit = 1.
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(2/2)
TT0ECS1 TT0ECS0
Valid edge setting of encoder clear signal (TECR0 pin)
0
0
Detects no edge (clearing encoder is invalid).
0
1
Detects rising edge.
1
0
Detects falling edge.
1
1
Detects both edges.
TT0EIS1 TT0EIS0
Valid edge setting of encoder input signals (TENC00, TENC01 pins)
0
0
Detects no edge (inputting encoder is invalid).
0
1
Detects rising edge.
1
0
Detects falling edge.
1
1
Detects both edges.
Cautions 1. Rewrite the TT0SCE, TT0ZCL, TT0BCL, TT0ACL, TT0ECS1, TT0ECS0,
TT0EIS1, and TT0EIS0 bits when the TT0CTL0.TT0CE bit = 0. (The same
value can be written to these bits when the TT0CE bit = 1.) If rewriting was
mistakenly performed, clear the TT0CE bit to 0 and then set these bits
again.
2. The TT0ECS1 and TT0ECS0 bits are valid only when the TT0SCE bit = 0
and the encoder compare mode is set.
3. The TT0EIS1 and TT0EIS0 bits are valid only when the TT0CTL2.TT0UDS1
and TT0CTL2.TT0UDS0 bits = 00 or 01.
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(8) TMT0 option register 0 (TT0OPT0)
The TT0OPT0 register is an 8-bit register that sets the capture/compare operation and detects overflows.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
TT0OPT0
R/W
Address: FFFFF607H
7
6
0
0
5
4
TT0CCS1 TT0CCS0
TT0CCS1
3
2
1
0
0
0
TT0OVF
TT0CCR1 register capture/compare selection
0
Selected as compare register
1
Selected as capture register (cleared by the TT0CTL0.TT0CE bit = 0)
The TT0CCS1 bit setting is valid only in the free-running timer mode.
TT0CCS0
TT0CCR0 register capture/compare selection
0
Selected as compare register
1
Selected as capture register (cleared by the TT0CTL0.TT0CE bit = 0)
The TT0CCS0 bit setting is valid only in the free-running timer mode.
TT0OVF
TMT0 overflow detection flag
Set (1)
Overflow occurred
Reset (0)
0 written to TT0OVF bit or TT0CTL0.TT0CE bit = 0
• The TT0OVF bit is set to 1 when the 16-bit counter value overflows from FFFFH
to 0000H in the free-running timer mode or the pulse width measurement mode.
• An overflow interrupt request signal (INTTT0OV) is generated when the TT0OVF
bit is set to 1. The INTTT0OV signal is not generated in modes other than the
free-running timer mode and the pulse width measurement mode.
• The TT0OVF bit is not cleared to 0 even when the TT0OVF bit or the TT0OPT0
register are read when the TT0OVF bit = 1.
• Before clearing the TT0OVF bit to 0 after generation of the INTTT0OV signal, be
sure to confirm (by reading) that the TT0OVF bit is set to 1.
• The TT0OVF bit can be both read and written, but the TT0OVF bit cannot be set
to 1 by software. Writing 1 has no effect on the operation of TMT0.
Cautions 1. Rewrite the TT0CCS1 and TT0CCS0 bits when the TT0CE bit = 0. (The
same value can be written when the TT0CE bit = 1.) If rewriting was
mistakenly performed, clear the TT0CE bit to 0 and then set these bits
again.
2. Be sure to set bits 1 to 3, 6, and 7 to “0”.
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(9) TMT0 option register 1 (TT0OPT1)
The TT0OPT1 register is an 8-bit register that detects overflows, underflows, and count-up/down operations of the
encoder count function.
The TT0OPT1 register is valid only in the encoder compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
This register can be rewritten even when the TT0CTL0.TT0CE bit = 1.
(1/2)
After reset: 00H
TT0OPT1
R/W
Address: FFFFF608H
7
6
5
4
3
0
0
0
0
0
TT0EUF
Set (1)
TT0EUF TT0EOF
TT0ESF
TMT0 underflow detection flag
Underflow occurs.
Reset (0) Cleared by writing to TT0EUF bit or when TT0CTL0.TT0CE bit = 0
• The TT0EUF bit is set to 1 when the 16-bit counter underflows from 0000H to
FFFFH in the encoder compare mode.
• When the TT0CTL2.TT0LDE bit = 1, the TT0EUF bit is set to 1 when the value of
the 16-bit counter is changed from 0000H to the set value of the TT0CCR0 register.
• An overflow interrupt request signal (INTTTOV0) is generated as soon as the
TT0EUF bit is set to 1.
• The TT0EUF bit is not cleared to 0 even if the TT0EUF bit or TT0OPT1 register
is read when the TT0EUF bit = 1.
• The status of the TT0EUF bit is retained even if the TT0CTL0.TT0CE bit is cleared
to 0 when the TT0CTL2.TT0ECC bit = 1.
• Before clearing the TT0EUF bit to 0 after the INTTTOV0 signal is generated, be
sure to confirm (read) that the TT0EUF bit is set to 1.
• The TT0EUF bit can be read or written, but it cannot be set to 1 by software.
Setting this bit to 1 does not affect the operation of TMT0.
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(2/2)
TT0EOF
Set (1)
Overflow detection flag for TMT0 encoder function
Overflow occurs.
Reset (0) Cleared by writing 0 to the TT0EOF bit or when the TT0CTL0.TT0CE
bit = 0
• The TT0EOF bit is set to 1 when the 16-bit counter overflows from FFFFH to
0000H in the encoder compare mode.
• As soon as the TT0EOF bit has been set to 1, an overflow interrupt request signal
(INTTTOV0) is generated. At this time, the TT0OPT0.TT0OVF bit is not set to 1.
• The TT0EOF bit is not cleared to 0 even if the TT0EOF bit or TT0OPT1 register
is read when the TT0EOF bit = 1.
• The status of the TT0EOF bit is retained even if the TT0CTL0.TT0CE bit is cleared
to 0 when the TT0CTL2.TT0ECC bit = 1.
• Before clearing the TT0EOF bit to 0 after the INTTTOV0 signal is generated, be
sure to confirm (read) that the TT0EOF bit is set to 1.
• The TT0EOF bit can be read or written, but it cannot be set to 1 by software.
Writing 1 to this bit does not affect the operation of TMT0.
TT0ESF
TMT0 count-up/-down operation status detection flag
0
TMT0 is counting up.
1
TMT0 is counting down.
• This bit is cleared to 0 if the TT0CTL0.TT0CE bit = 0 when the
TT0CTL2.TT0ECC bit = 0.
• The status of the TT0ESF bit is retained even if the TT0CE bit = 0 when the
TT0ECC bit = 1.
Caution
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(10) TMT0 capture/compare register 0 (TT0CCR0)
The TT0CCR0 register is a 16-bit register that can be used as a capture register or compare register depending
on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
depending on the setting of the TT0OPT0.TT0CCS0 bit. In the pulse width measurement mode, the TT0CCR0
register can be used only as a capture register. In any other mode, this register can be used only as a compare
register.
The TT0CCR0 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
After reset: 0000H
15
14
R/W
13
12
Address: FFFFF60AH
11
10
9
8
7
6
5
4
3
2
1
0
TT0CCR0
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(a) Function as compare register
The TT0CCR0 register can be rewritten even when the TT0CTL0.TT0CE bit = 1.
The set value of the TT0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit
counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTT0CC0)
is generated. If TOT00 pin output is enabled at this time, the output of the TOT00 pin is inverted.
When the TT0CCR0 register is used as a cycle register in the interval timer mode, or when the TT0CCR0
register is used as a cycle register in the external event count mode, external trigger pulse output mode, oneshot pulse output mode, PWM output mode, triangular-wave PWM output mode, or encoder compare mode,
the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer
register.
The compare register is not cleared by setting the TT0CTL0.TT0CE bit to 0.
(b) Function as capture register
In the free-running timer mode (when the TT0CCR0 register is used as a capture register), the count value of
the 16-bit counter is stored in the TT0CCR0 register if the valid edge of the capture trigger input pin (TIT00 pin)
is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the
TT0CCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin
(TIT00 pin) is detected.
Even if the capture operation and reading the TT0CCR0 register conflict, the correct value of the TT0CCR0
register can be read.
The capture register is cleared by setting the TT0CTL0.TT0CE bit to 0.
The following table shows the functions of the capture/compare register in each mode, and how to write data to the
compare register.
Table 9-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
TT0CCR0 Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
Note
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
None
Triangular-wave WPM output
Compare register
Batch write
Encoder compare
Compare register
Anytime write
Note
Note
Note Writing to the TT0CCR1 register is the trigger.
Remark For anytime write and batch write, see 9.6 (2) Anytime write and batch write.
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(11) TMT0 capture/compare register 1 (TT0CCR1)
The TT0CCR1 register is a 16-bit register that can be used as a capture register or compare register depending
on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
depending on the setting of the TT0OPT0.TT0CCS1 bit. In the pulse width measurement mode, the TT0CCR1
register can be used only as a capture register. In any other mode, this register can be used only as a compare
register.
The TT0CCR1 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
After reset: 0000H
15
14
R/W
13
12
Address: FFFFFF60CH
11
10
9
8
7
6
5
4
3
2
1
0
TT0CCR1
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(a) Function as compare register
The TT0CCR1 register can be rewritten even when the TT0CTL0.TT0CE bit = 1.
The set value of the TT0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit
counter matches the value of the CCR1 buffer register, a compare match interrupt request signal
(INTTT0CC01) is generated. If TOT01 pin output is enabled at this time, the output of the TOT01 pin is inverted.
The compare register is not cleared by setting the TT0CTL0.TT0CE bit to 0.
(b) Function as capture register
In the free-running timer mode (when the TT0CCR1 register is used as a capture register), the count value of
the 16-bit counter is stored in the TT0CCR1 register if the valid edge of the capture trigger input pin (TIT01 pin)
is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the
TT0CCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin
(TIT01 pin) is detected.
Even if the capture operation and reading the TT0CCR1 register conflict, the correct value of the TT0CCR1
register can be read.
The capture register is cleared by setting the TT0CTL0.TT0CE bit to 0.
The following table shows the functions of the capture/compare register in each mode, and how to write data to the
compare register.
Table 9-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
TT0CCR1 Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
None
Triangular-wave PWM output
Compare register
Batch write
Encoder compare
Compare register
Anytime write
Note
Note
Note
Note Writing to the TT0CCR1 register is the trigger.
Remark For anytime write and batch write, see 9.6 (2) Anytime write and batch write.
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(12) TMT0 counter write register (TT0TCW)
The TT0TCW register is used to set the initial value of the 16-bit counter.
The TT0TCW register is valid only in the encoder compare mode.
This register can be read or written in 16-bit units.
Rewrite the TT0TCW register when the TT0CTL0.TT0CE bit = 0.
The value of the TT0TCW register is transferred to the 16-bit counter when the TT0CE bit is set (1).
Reset sets this register to 0000H.
After reset: 0000H
15
14
R/W
13
Address: FFFFF610H
11
12
10
9
8
7
6
5
4
3
2
1
0
TT0TCW
(13) TMT0 counter read buffer register (TT0CNT)
The TT0CNT register is a read buffer register that can read the count value of the 16-bit counter.
If this register is read when the TT0CTL0.TT0CE bit = 1, the count value of the 16-bit timer can be read.
This register is read-only, in 16-bit units.
The value of the TT0CNT register is set to 0000H when the TT0CTL2.TT0ECC and TT0CE bits = 0. If the
TT0CNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. The
TT0CNT register is not set to 0000H but the previous value is read when the TT0ECC bit = 1 and TT0CE bit = 0.
The TT0ECC and TT0CE bits are set to 0 after reset, and the value of the TT0CNT register is set to 0000H.
After reset: 0000H
15
14
R
13
Address: FFFFFF60EH
12
11
10
9
8
7
6
5
4
3
2
1
0
TT0CNT
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(14) Noise elimination control register (TTNFC)
Digital noise elimination can be selected for the TIT00, TIT01, TENC01, TECR0, and EVTT00 pins. The noise
elimination settings are performed using the TTNFC register.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among fXX,
fXX/4, fXX/8, fXX/16, fXX/32, and fXX/64. Sampling is performed 3 times.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution
Time equal to the sampling clock × 3 clocks is required until the digital noise eliminator is
initialized after the sampling clock has been changed. If the valid edge of the TIT00, TIT01,
TENC01, TECR0, and EVTT00 pins is input after the sampling clock has been changed and
before the time of the sampling clock × 3 clocks passes, therefore, an interrupt request signal
may be generated.
Therefore, when using the external trigger function, the external event
function, the capture trigger function, and the encoder function of TMT, enable TMT operation
after the sampling clock × 3 clocks have elapsed.
After reset: 00H
TTNFC
TTNFEN
R/W
Address: FFFFF726H
0
0
TTNFEN
0
0
TTNFC2 TTNFC1 TTNFC0
Settings of digital noise elimination
0
Digital noise elimination not executed
1
Digital noise elimination executed
TTNFC2 TTNFC1 TTNFC0
Digital sampling clock
0
0
0
fXX
0
0
1
fXX/4
0
1
0
fXX/8
0
1
1
fXX/16
1
0
0
fXX/32
1
0
1
fXX/64
Other than above
Setting prohibited
Remarks 1. Since sampling is performed three times, the noise width for reliably
eliminating noise is 2 sampling clocks.
2. In the case of noise with a width smaller than 2 sampling clocks, an
interrupt request signal is generated if noise synchronized with the
sampling clock is input.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
A timing example of noise elimination performed by the timer T input pin digital filter is shown Figure 9-2.
Figure 9-2. Example of Digital Noise Elimination Timing
Noise elimination clock
Input signal
Sampling
3 times
Sampling
3 times
1 clock
1 clock
2 clocks
2 clocks
3 clocks
3 clocks
Internal signal
Remark
If there are two or fewer noise elimination clocks while the TIT00, TIT01, TENC01, TECR0, and
EVTT00 input signals are high level (or low level), the input signal is eliminated as noise. If it is
sampled three times or more, the edge is detected as a valid input.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Timer Output Operations
The following table shows the operations and output levels of the TOT00 and TOT01 pins.
Table 9-5. Timer Output Control in Each Mode
Operation Mode
TOT01 Pin
TOT00 Pin
Interval timer mode
Square wave output
External event count mode
None
External trigger pulse output mode
External trigger pulse output
One-shot pulse output mode
One-shot pulse output
PWM output mode
PWM output
Free-running timer mode
Square wave output (only when compare function is used)
Pulse width measurement mode
None
Triangular-wave PWM output mode
Triangular-wave PWM output
Encoder compare mode
None
Square wave output
Table 9-6. Truth Table of TOT00 and TOT01 Pins Under Control of Timer Output Control Bits
TT0IOC0.TT0OLn Bit
TT0IOC0.TT0OEn Bit
TT0CTL0.TT0CE Bit
0
0
×
1
Level of TOT0n Pin
Low-level output
0
Low-level output
1
Low level immediately before counting, high
level after counting is started
1
0
×
High-level output
1
0
High-level output
1
High level immediately before counting, low level
after counting is started
Remark
n = 0, 1
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Operation
The functions of TMT0 that can be implemented differ from one channel to another. The functions of each channel are
shown below.
Table 9-7. TMT0 Specifications in Each Mode
Operation
TT0CTL1.TT0EST Bit
EVTT0 Pin
Capture/Compare
Compare Register
(Software Trigger Bit)
(External Trigger Input)
Register Setting
Write Method
Interval timer mode
Invalid
Invalid
Compare only
Anytime write
External event count mode
Invalid
Invalid
Compare only
Anytime write
External trigger pulse output mode
Valid
Valid
Compare only
Batch write
One-shot pulse output mode
Valid
Valid
Compare only
Anytime write
PWM output mode
Invalid
Invalid
Compare only
Batch write
Free-running timer mode
Invalid
Invalid
Switchable
Anytime write
Pulse width measurement mode
Invalid
Invalid
Capture only
Not applicable
Triangular-wave PWM output mode
Invalid
Invalid
Compare only
Batch write
Encoder compare mode
Invalid
Invalid
Compare only
Anytime write
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(1) Basic counter operation
This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation
in each mode.
(a) Count start operation
• Encoder compare mode
A count operation is controlled by TENC00 and TENC01 phases.
The 16-bit counter initial setting is performed by transferring the set value of the TT0TCW register to the 16bit counter and the count operation is started. (When the TT0CTL2.TT0ECC bit = 0, the TT0TCW register set
value is transferred to the 16-bit counter at the timing when the TT0CTL0.TT0CE bit changes from 0 to 1.)
• Triangular-wave PWM mode
The 16-bit counter starts counting from the initial value FFFFH.
It counts up FFFFH, 0000H, 0001H, 0002H, 0003H, and so on.
Following the count-up operation, the counter counts down upon a match between the 16-bit count value and
the CCR0 buffer register.
• Mode other than above
The 16-bit counter starts counting from the initial value FFFFH.
It counts up FFFFH, 0000H, 0001H, 0002H, 0003H, and so on.
(b) Clear operation
The 16-bit counter is cleared to 0000H when its value matches the value of the compare register, when its
value is captured, when the edge of the encoder clear signal is detected, and when the clear level condition of
the TENC00, TENC01, and TECR0 pins is detected. The count operation from FFFFH to 0000H that takes
place immediately after the counter has started counting or when the counter overflows is not a clear operation.
Therefore, the INTTT0CC0 and INTTT0CC1 interrupt signals are not generated.
(c) Overflow operation
The 16-bit counter overflows when it counts up from FFFFH to 0000H in the free-running mode, pulse width
measurement mode, and encoder compare mode. If the counter overflows in the free-running mode and pulse
width measurement mode, the TT0OPT0.TT0OVF bit is set to 1 and an interrupt request signal (INTTT0OV) is
generated.
If the counter overflows in the encoder compare mode, the TT0OPT1.TT0EOF bit is set to 1 and an interrupt
request signal (INTTT0OV) is generated.
Note that the INTTT0OV signal is not generated under the following conditions.
• Immediately after a count operation has been started
• If the counter value matches the compare value FFFFH and is cleared
• When FFFFH is captured and cleared to 0000H in the pulse width measurement mode
Caution
After the overflow interrupt request signal (INTTT0OV) has been generated, be sure to check
that the overflow flag (TT0OVF, TT0EOF bits) is set to 1.
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(d) Count value hold operation
The value of the 16-bit counter is held by the TT0CTL2.TT0ECC bit in the encoder compare mode. The value
of the 16-bit counter is reset to FFFFH when the TT0ECC bit = 0 and TT0CTL0.TT0CE bit = 0. When the
TT0CE bit is next set to 1, the set value of the TT0TCW register is transferred to the 16-bit counter and a count
operation is performed.
If the TT0ECC bit = 1 and TT0CE bit = 0, the value of the 16-bit counter is held. When the TT0CE bit is next
set to 1, the counter resumes the count operation from the held value.
(e) Counter read operation during count operation
The value of the 16-bit counter of TMT0 can be read by using the TT0CNT register during the count operation.
When the TT0CTL0.TT0CE bit = 1, the value of the 16-bit counter can be read by reading the TT0CNT register.
If the TT0CNT register is read when the TT0CTL2.TT0ECC bit = 0 and TT0CE bit = 0, however, it is 0000H.
The held value of the TT0CNT register is read if the register is read when the TT0ECC bit = 1 and TT0CE bit =
0.
(f) Underflow operation
A 16-bit counter underflow occurs at the timing when the 16-bit counter value changes from 0000H to FFFFH
in the encoder compare mode. When an underflow occurs, the TT0OPT1.TT0EUF bit is set to 1 and an
interrupt request signal (INTTT0OV) is generated.
(g) Interrupt operation
TMT0 generates the following four types of interrupt request signals.
• INTTT0CC0 interrupt:
This signal functions as a match interrupt request signal of the CCR0 buffer register
and as a capture interrupt request signal to the TT0CCR0 register.
• INTTT0CC1 interrupt:
This signal functions as a match interrupt request signal of the CCR1 buffer register
and as a capture interrupt request signal to the TT0CCR1 register.
• INTTT0OV interrupt:
This signal functions as an overflow interrupt request signal.
• INTTT0EC interrupt:
This signal functions as a valid edge detection interrupt request signal of the
encoder clear input (TECR0 pin).
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(2) Anytime write and batch write
The TT0CCR0 and TT0CCR1 registers in TMT0 can be rewritten during timer operation (TT0CTL0.TT0CE bit = 1),
but the write method (anytime write, batch write) of the CCR0 and CCR1 buffer registers differs depending on the
mode.
(a) Anytime write
In this mode, data is transferred at any time from the TT0CCR0 and TT0CCR1 registers to the CCR0 and
CCR1 buffer registers during timer operation (n = 0, 1).
Figure 9-3. Flowchart of Basic Operation for Anytime Write
START
Initial settings
• Set values to TT0CCRn register
• Timer operation enable
(TT0CE bit = 1)
→ Transfer values of TT0CCRn
register to CCRn buffer
register
TTnCCRn register rewrite
→ Transfer to CCRn buffer register
Timer operation
• Match between 16-bit counter
and CCR1 buffer registerNote
• Match between 16-bit counter
and CCR0 buffer register
• 16-bit counter clear & start
IINTTT0CC1 signal output
IINTTT0CC0 signal output
Note The 16-bit counter is not cleared upon a match between the 16-bit counter value
and the CCR1 buffer register value. It is cleared upon a match between the 16-bit
counter value and the CCR0 buffer register value.
Remarks 1. The above flowchart illustrates an example of the operation in the interval
timer mode.
2. n = 0, 1
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Figure 9-4. Timing of Anytime Write
TT0CE bit = 1
D01
FFFFH
D01
D02
16-bit counter
D11
D11
D12
D12
0000H
D01
TT0CCR0 register
CCR0 buffer register
0000H
D01
D11
TT0CCR1 register
CCR1 buffer register
D02
0000H
D02
D12
D11
D12
INTTT0CC0 signal
INTTT0CC1 signal
Remarks 1. D01, D02: Set values of TT0CCR0 register
D11, D12: Set values of TT0CCR1 register
2. The above timing chart illustrates an example of the operation in the interval timer
mode.
3. n = 0, 1
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(b) Batch write
In this mode, data is transferred all at once from the TT0CCR0 and TT0CCR1 registers to the CCR0 and CCR1
buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0
buffer register and the value of the 16-bit counter. Transfer is enabled by writing to the TT0CCR1 register.
Whether to enable or disable the next transfer timing is controlled by writing or not writing to the TT0CCR1
register.
In order for the set value when the TT0CCR0 and TT0CCR1 registers are rewritten to become the 16-bit
counter comparison value (in other words, in order for this value to be transferred to the CCR0 and CCR1
buffer registers), it is necessary to rewrite the TT0CCR0 register and then write to the TT0CCR1 register before
the 16-bit counter value and the CCR0 buffer register value match. Therefore, the values of the TT0CCR0 and
TT0CCR1 registers are transferred to the CCR0 and CCR1 buffer registers upon a match between the count
value of the 16-bit counter and the value of the CCR0 buffer register. Thus even when wishing only to rewrite
the value of the TT0CCR0 register, also write the same value (same as preset value of the TT0CCR1 register)
to the TT0CCR1 register.
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Figure 9-5. Flowchart of Basic Operation for Batch Write
START
Initial settings
• Set values to TT0CCRn register
• Timer operation enable (TT0CE
bit = 1)
→ Transfer values of TT0CCRn
register to CCRn buffer
register
TT0CCR0 register rewrite
TT0CCR1 register rewrite
Timer operation
• Match between 16-bit counter
and CCR1 buffer registerNote
• Match between 16-bit counter
and CCR0 buffer register
• 16-bit counter clear & start
• Transfer of values of TT0CCRn
register to CCRn buffer register
Batch write enable
INTTT0CC1 signal output
INTTT0CC0 signal output
Note The 16-bit counter is not cleared upon a match between the 16-bit counter value and the CCR1
buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0
buffer register value.
Caution
Writing to the TT0CCR1 register includes enabling of batch write. Thus, rewrite the
TT0CCR1 register after rewriting the TT0CCR0 register.
Remark
The above flowchart illustrates an example of the operation in the PWM output mode.
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Figure 9-6. Timing of Batch Write
TT0CE bit = 1
D01
FFFFH
D02
D11
D12
16-bit counter
D03
D02
D12
D12
D12
0000H
TT0CCR0 register
D01
CCR0 buffer register 0000H
TT0CCR1 register
D02
D01
D11
CCR1 buffer register 0000H
D03
D02
Note 1
Note 2 D12
D11
D12
Note 1
Note 1
Same value write
D12
Note 3
D03
D12
Note 1
INTTT0CC0 signal
INTTT0CC1 signal
TOT00 pin output
TOT01 pin output
Notes 1. Because the TT0CCR1 register was not rewritten, D03 is not transferred.
2. Because the TT0CCR1 register has been written (D12), data is transferred to the CCR1
buffer register upon a match between the value of the 16-bit counter and the value of the
TT0CCR0 register (D01).
3. Because the TT0CCR1 register has been written (D12), data is transferred to the CCR1
buffer register upon a match between the value of the 16-bit counter and the value of the
TT0CCR0 register (D02).
Remarks 1. D01, D02, D03: Set values of TT0CCR0 register
D11, D12:
Set values of TT0CCR1 register
2. The above timing chart illustrates the operation in the PWM output mode as an example.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Interval timer mode (TT0MD3 to TT0MD0 bits = 0000)
In the interval timer mode, an interrupt request signal (INTTT0CC0) is generated at the interval set by the TT0CCR0
register if the TT0CTL0.TT0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from
the TOT00 pin.
The TT0CCR1 register is not used in the interval timer mode. However, the set value of the TT0CCR1 register is
transferred to the CCR1 buffer register, and when the count value of the 16-bit counter matches the value of the CCR1
buffer register, a compare match interrupt request signal (INTTT0CC1) is generated. In addition, a square wave, which is
inverted when the INTTT0CC1 signal is generated, can be output from the TOT01 pin.
The value of the TT0CCR0 and TT0CCR1 registers can be rewritten even while the timer is operating.
Figure 9-7. Configuration of Interval Timer
Clear
Count clock
selection
Output
controller
16-bit counter
Match signal
TT0CE bit
TOT00 pin
INTTT0CC0 signal
CCR0 buffer register
TT0CCR0 register
Figure 9-8. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
D0
D0
D0
D0
0000H
TT0CE bit
TT0CCR0 register
D0
TOT00 pin output
INTTT0CC0 signal
Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1)
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When the TT0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with
the count clock, and the counter starts counting. At this time, the output of the TOT00 pin is inverted. Additionally, the set
value of the TT0CCR0 register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, the output of the TOT00 pin is inverted, and a compare match interrupt request signal (INTTT0CC0) is
generated.
The interval can be calculated by the following expression.
Interval = (Set value of TT0CCR0 register + 1) × Count clock cycle
Figure 9-9. Register Setting for Interval Timer Mode Operation (1/2)
(a) TMT0 control register 0 (TT0CTL0)
TT0CE
TT0CTL0
0/1
TT0CKS2 TT0CKS1 TT0CKS0
0
0
0
0
0/1
0/1
0/1
Select count clock
0: Stops counting
1: Enables counting
(b) TMT0 control register 1 (TT0CTL1)
TT0EST TT0EEE
TT0CTL1
0
0
0
TT0MD3
0
0
TT0MD2 TT0MD1 TT0MD0
0
0
0
0, 0, 0, 0:
Interval timer mode
(c) TMT0 I/O control register 0 (TT0IOC0)
TT0IOC0
0
0
0
0
TT0OL1
TT0OE1
TT0OL0
TT0OE0
0/1
0/1
0/1
0/1
0: Disables TOT00 pin output
1: Enables TOT00 pin output
Setting of TOT00 pin output
level before count operation
0: Low level
1: High level
0: Disables TOT01 pin output
1: Enables TOT01 pin output
Setting of TOT01 pin output
level before count operation
0: Low level
1: High level
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Figure 9-9. Register Setting for Interval Timer Mode Operation (2/2)
(d) TMT0 counter read buffer register (TT0CNT)
By reading the TT0CNT register, the count value of the 16-bit counter can be read.
(e) TMT0 capture/compare register 0 (TT0CCR0)
If the TT0CCR0 register is set to D0, the interval is as follows.
Interval = (D0 + 1) × Count clock cycle
(f) TMT0 capture/compare register 1 (TT0CCR1)
The TT0CCR1 register is not used in the interval timer mode. However, the set value of the TT0CCR1
register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches
the value of the CCR1 buffer register, the TOT01 pin output is inverted and a compare match interrupt
request signal (INTTT0CC1) is generated.
By setting this register to the same value as the value set in the TT0CCR0 register, a square wave with a
duty factor of 50% can be output from the TOT01 pin.
When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH. Also mask the
register by the interrupt mask flag (TT0CCIC1.TT0CCMK1).
Remark
TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control
register 2 (TT0IOC2), TMT0 I/O control register 3 (TT0IOC3), TMT0 option register 0
(TT0OPT0), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW)
are not used in the interval timer mode.
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(1) Interval timer mode operation flow
Figure 9-10. Software Processing Flow in Interval Timer Mode
FFFFH
D0
16-bit counter
D0
D0
0000H
TT0CE bit
TT0CCR0 register
D0
TOT00 pin output
INTTT0CC0 signal
Count operation start flow
START
Register initial setting
TT0CTL0 register
(TT0CKS0 to TT0CKS2 bits)
TT0CTL1 register,
TT0IOC0 register,
TT0CCR0 register
TT0CE bit = 1
Initial setting of these registers is performed
before setting the TT0CE bit to 1.
The TT0CKS0 to TT0CKS2 bits can be
set at the same time as when counting
starts (TT0CE bit = 1).
Count operation stop flow
TT0CE bit = 0
The counter is initialized and counting is
stopped by clearing the TT0CE bit to 0.
The output level of the TOT00 pin is as
specified by the TT0IOC0 register.
STOP
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(2) Interval timer mode operation timing
(a) Operation if TT0CCR0 register is set to 0000H
If the TT0CCR0 register is set to 0000H, the INTTT0CC0 signal is generated at each count clock, and the
output of the TOT00 pin is inverted.
The value of the 16-bit counter is always 0000H.
Count clock
16-bit counter
FFFFH
0000H
0000H
0000H
0000H
TT0CE bit
TT0CCR0 register
0000H
TOT00 pin output
INTTT0CC0 signal
Interval time
Interval time
Interval time
Count clock cycle Count clock cycle Count clock cycle
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(b) Operation if TT0CCR0 register is set to FFFFH
If the TT0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to
0000H in synchronization with the next count-up timing. The INTTT0CC0 signal is generated and the output of
the TOT00 pin is inverted. At this time, an overflow interrupt request signal (INTTT0OV) is not generated, nor is
the overflow flag (TT0OPT0.TT0OVF bit) set to 1.
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
FFFFH
TOT00 pin output
INTTT0CC0 signal
Interval time
Interval time
Interval time
10000H ×
10000H ×
10000H ×
count clock cycle count clock cycle count clock cycle
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(c) Notes on rewriting TT0CCR0 register
If the value of the TT0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow. When an overflow may occur, stop counting and then change the set value.
FFFFH
D1
D1
16-bit counter
D2
D2
D2
0000H
TT0CE bit
D1
TT0CCR0 register
TT0OL0 bit
D2
L
TOT00 pin output
INTTT0CC0 signal
Interval time (1)
Remark
Interval time (1):
Interval time (NG)
Interval
time (2)
(D1 + 1) × Count clock cycle
Interval time (NG): (10000H + D2 + 1) × Count clock cycle
Interval time (2):
(D2 + 1) × Count clock cycle
If the value of the TT0CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less
than D1, the count value is transferred to the CCR0 buffer register as soon as the TT0CCR0 register has been
rewritten. Consequently, the value of the 16-bit counter that is compared is D2.
Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows,
and then counts up again from 0000H. When the count value matches D2, the INTTT0CC0 signal is generated
and the output of the TOT00 pin is inverted.
Therefore, the INTTT0CC0 signal may not be generated at the interval time “(D1 + 1) × Count clock cycle” or
“(D2 + 1) × Count clock cycle” as originally expected, but may be generated at an interval of “(10000H + D2 + 1)
× Count clock cycle”.
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(d) Operation of TT0CCR1 register
Figure 9-11. Configuration of TT0CCR1 Register
TT0CCR1 register
CCR1 buffer register
Output
controller
Match signal
TOT01 pin
INTTT0CC1 signal
Clear
Count clock
selection
16-bit counter
Match signal
TT0CE bit
Output
controller
TOT00 pin
INTTT0CC0 signal
CCR0 buffer register
TT0CCR0 register
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When the TT0CCR1 register is set to the same value as the TT0CCR0 register, the INTTT0CC0 signal is
generated at the same timing as the INTTT0CC1 signal and the TOT01 pin output is inverted. In other words, a
square wave can be output from the TOT01 pin.
The following shows the operation when the TT0CCR1 register is set to other than the value set in the
TT0CCR0 register.
If the set value of the TT0CCR1 register is less than the set value of the TT0CCR0 register, the INTTT0CC1
signal is generated once per cycle. At the same time, the output of the TOT01 pin is inverted.
The TOT01 pin outputs a square wave after outputting a short-width pulse.
Figure 9-12. Timing Chart When D01 ≥ D11
FFFFH
D01
16-bit counter
D11
D01
D11
D01
D11
D01
D11
0000H
TT0CE bit
TT0CCR0 register
D01
TOT00 pin output
INTTT0CC0 signal
TT0CCR1 register
D11
TOT01 pin output
INTTT0CC1 signal
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If the set value of the TT0CCR1 register is greater than the set value of the TT0CCR0 register, the count value
of the 16-bit counter does not match the value of the TT0CCR1 register. Consequently, the INTTT0CC1 signal
is not generated, nor is the output of the TOT01 pin changed.
When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH.
Figure 9-13. Timing Chart When D01 < D11
FFFFH
D01
D01
D01
D01
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
D01
TOT00 pin output
INTTT0CC0 signal
D11
TT0CCR1 register
TOT01 pin output
INTTT0CC1 signal
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
External event count mode (TT0MD3 to TT0MD0 bits = 0001)
In the external event count mode, the valid edge of the external event count input (EVTT0) is counted when the
TT0CTL0.TT0CE bit is set to 1, and an interrupt request signal (INTTT0CC0) is generated each time the number of edges
set by the TT0CCR0 register have been counted. The TOT00 and TOT01 pins cannot be used.
The TT0CCR1 register is not used in the external event count mode.
Figure 9-14. Configuration in External Event Count Mode
Clear
EVTT0 pin
(external event
count input)
Edge
detectorNote
16-bit counter
Match signal
TT0CE bit
INTTT0CC0 signal
CCR0 buffer register
TT0CCR0 register
Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.
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Figure 9-15. Basic Timing in External Event Count Mode
FFFFH
D0
16-bit counter
D0
D0
0000H
16-bit counter
TT0CE bit
External event
count input
(EVTT0 pin input)
TT0CCR0 register
TT0CCR0 register
D0
D0
0000
0001
D0
INTTT0CC0 signal
INTTT0CC0 signal
External
event
count
(D0 + 1)
Remark
D0 − 1
External
event
count
(D0 + 1)
External
event
count
(D0 + 1)
This figure shows the basic timing when the rising edge is specified as the valid edge of the
external event count input.
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When the TT0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts
each time the valid edge of external event count input is detected. Additionally, the set value of the TT0CCR0 register is
transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, and a compare match interrupt request signal (INTTT0CC0) is generated.
The INTTT0CC0 signal is generated each time the valid edge of the external event count input has been detected
“value set to TT0CCR0 register + 1” times.
Figure 9-16. Register Setting for Operation in External Event Count Mode (1/2)
(a) TMT0 control register 0 (TT0CTL0)
TT0CE
TT0CTL0
0/1
TT0CKS2 TT0CKS1 TT0CKS0
0
0
0
0
0
0
0
0: Stops counting
1: Enables counting
(b) TMT0 control register 1 (TT0CTL1)
TT0EST TT0EEE
TT0CTL1
0
0
0
TT0MD3 TT0MD2 TT0MD1 TT0MD0
0
0
0
0
1
0, 0, 0, 1:
External event count mode
(c) TMT0 I/O control register 2 (TT0IOC2)
TT0EES1 TT0EES0 TT0ETS1 TT0ETS0
TT0IOC2
0
0
0
0
0/1
0/1
0
0
Select valid edge
of external event
count input (EVTT0 pin)
(d) TMT0 counter read buffer register (TT0CNT)
The count value of the 16-bit counter can be read by reading the TT0CNT register.
(e) TMT0 capture/compare register 0 (TT0CCR0)
If the TT0CCR0 register is set to D0, the count is cleared when the number of external events has reached
(D0 + 1) and the compare match interrupt request signal (INTTT0CC0) is generated.
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Figure 9-16. Register Setting for Operation in External Event Count Mode (2/2)
(f) TMT0 capture/compare register 1 (TT0CCR1)
The TT0CCR1 register is not used in the external event count mode. However, the set value of the
TT0CCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter
matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTT0CC1) is
generated.
When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH. Also mask the
register by the interrupt mask flag (TT0CCIC1.TT0CCMK1).
Remark
TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 0 (TT0IOC0), TMT0 I/O control
register 1 (TT0IOC1), TMT0 I/O control register 3 (TT0IOC3), TMT0 option register 0
(TT0OPT0), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are
not used in the external event count mode.
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(1) External event count mode operation flow
Figure 9-17. Software Processing Flow in External Event Count Mode
FFFFH
D0
16-bit counter
D0
D0
0000H
TT0CE bit
TT0CCR0 register
D0
INTTT0CC0 signal
Count operation start flow
START
Register initial setting
TT0CTL1 register,
TT0IOC2 register,
TT0CCR0, TT0CCR1 registers
Initial setting of these registers
is performed before setting the
TT0CE bit to 1.
TT0CE bit = 1
Count operation stop flow
TT0CE bit = 0
The counter is initialized and counting
is stopped by clearing the TT0CE bit to 0.
STOP
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(2) Operation timing in external event count mode
(a) Operation if TT0CCR0 register is set to 0000H
When the TT0CCR0 register is set to 0000H, the 16-bit counter is repeatedly cleared to 0000H and generates
the INTTT0CC0 signal each time it has detected the valid edge of the external event count signal and its value
has matched that of the CCR0 buffer register.
The value of the 16-bit counter is always 0000H.
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
0000H
INTTT0CC0 signal
INTTT0CC0 signal is generated each time the 16-bit
counter counts the valid edge of the external event count input.
(b) Operation if TT0CCR0 register is set to FFFFH
If the TT0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH each time the valid edge of
the external event count signal has been detected. The 16-bit counter is cleared to 0000H in synchronization
with the next count-up timing, and the INTTT0CC0 signal is generated. At this time, the TT0OPT0.TT0OVF bit
is not set.
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
FFFFH
INTTT0CC0 signal
External event
count: 10000H
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(c) Operation with TT0CCR0 set to FFFFH and TT0CCR1 register to 0000H
When the TT0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH each time it has detected
the valid edge of the external event count signal. The counter is then cleared to 0000H in synchronization with
the next count-up timing and the INTTT0CC0 signal is generated. At this time, the TT0OPT0.TT0OVF bit is not
set.
If the TT0CCR1 register is set to 0000H, the INTTT0CC1 signal is generated when the 16-bit counter is cleared
to 0000H.
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
FFFFH
INTTT0CC0 signal
TT0CCR1 register
0000H
INTTT0CC1 signal
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(d) Notes on rewriting TT0CCR0 register
If the value of the TT0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow. When an overflow may occur, stop counting once and then change the set value.
FFFFH
D1
16-bit counter
D1
D2
D2
D2
0000H
TT0CE bit
TT0CCR0 register
D1
D2
INTTT0CC0 signal
External event
count (1):
(D1 + 1)
External event count (NG): External event
(10000H + D2 + 1)
count (2):
(D2 + 1)
If the value of the TT0CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less
than D1, the count value is transferred to the CCR0 buffer register as soon as the TT0CCR0 register has been
rewritten. Consequently, the value that is compared with the 16-bit counter is D2.
Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows,
and then counts up again from 0000H. When the count value matches D2, the INTTT0CC0 signal is generated.
Therefore, the INTTT0CC0 signal may not be generated at the valid edge count of “(D1 + 1) times” or “(D2 + 1)
times” as originally expected, but may be generated at the valid edge count of “(10000H + D2 + 1) times”.
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(e) Operation of TT0CCR1 register
Figure 9-18. Configuration of TT0CCR1 Register
TT0CCR1 register
CCR1 buffer register
Match signal
INTTT0CC1 signal
Clear
EVTT0 pin
(external event
count input)
Edge
detectorNote
16-bit counter
Match signal
TT0CE bit
INTTT0CC0 signal
CCR0 buffer register
TT0CCR0 register
Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.
If the set value of the TT0CCR1 register is smaller than the set value of the TT0CCR0 register, the INTTT0CC1
signal is generated once per cycle.
Figure 9-19. Timing Chart When D01 ≥ D11
FFFFH
D01
16-bit counter
D11
D01
D11
D01
D11
D01
D11
0000H
TT0CE bit
TT0CCR0 register
D01
INTTT0CC0 signal
TT0CCR1 register
D11
INTTT0CC1 signal
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
If the set value of the TT0CCR1 register is greater than the set value of the TT0CCR0 register, the INTTT0CC1
signal is not generated because the count value of the 16-bit counter and the value of the TT0CCR1 register
do not match.
When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH.
Figure 9-20. Timing Chart When D01 < D11
FFFFH
D01
D01
D01
D01
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
D01
INTTT0CC0 signal
D11
TT0CCR1 register
INTTT0CC1 signal
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9.6.3
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
External trigger pulse output mode (TT0MD3 to TT0MD0 bits = 0010)
In the external trigger pulse output mode, 16-bit timer/event counter T waits for a trigger when the TT0CTL0.TT0CE bit
is set to 1. When the valid edge of an external trigger input (EVTT0) is detected, 16-bit timer/event counter T starts
counting, and outputs a PWM waveform from the TOT01 pin.
Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software
trigger, a square wave that has the set value of the TT0CCR0 register + 1 as half its cycle can also be output from the
TOT00 pin.
Figure 9-21. Configuration in External Trigger Pulse Output Mode
Edge
detectorNote 2
EVTT0 pinNote 1
(external
trigger input/
external event
count input)
TT0CCR1 register
Transfer
Software trigger
generation
Edge
detectorNote 3
Internal count clock
Output
S
controller
R
(RS-FF)
CCR1 buffer register
Match signal
Count
clock
selection
TOT01 pin
INTTT0CC1 signal
Clear
Count
start
control
16-bit counter
Output
controller
Match signal
TT0CE bit
TOT00 pin
INTTT0CC0 signal
CCR0 buffer register
Transfer
TT0CCR0 register
Notes 1. Since the external trigger input pin and external event count input pin are the same alternatefunction pin, the external event count input function cannot be used.
2. Edge detector for external trigger input.
Set by the TT0IOC2.TT0ETS1 and TT0IOC2.TT0ETS0 bits.
3. Edge detector for external event count input.
Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.
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Figure 9-22. Basic Timing in External Trigger Pulse Output Mode
FFFFH
D0
16-bit counter
D1
D0
D0
D1
D0
D1
D1
0000H
TT0CE bit
External trigger input
(EVTT0 pin input)
TT0CCR0 register
D0
INTTT0CC0 signal
TOT00 pin output
D1
TT0CCR1 register
INTTT0CC1 signal
TOT01 pin output
Wait Active level
for width (D1)
trigger
Cycle (D0 + 1)
Active level
width (D1)
Cycle (D0 + 1)
Active level
width (D1)
Cycle (D0 + 1)
16-bit timer/event counter T waits for a trigger when the TT0CE bit is set to 1. When the trigger is generated, the 16-bit
counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOT01
pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The
output of the TOT00 pin is inverted. The TOT01 pin outputs a high level regardless of the status (high/low) when a trigger
occurs.)
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TT0CCR1 register) × Count clock cycle
Cycle = (Set value of TT0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TT0CCR1 register)/(Set value of TT0CCR0 register + 1)
The compare match request signal (INTTT0CC0) is generated the next time the 16-bit counter counts after its count
value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match
interrupt request signal (INTTT0CC1) is generated when the count value of the 16-bit counter matches the value of the
CCR1 buffer register.
The value set to the TT0CCRn register is transferred to the CCRn buffer register when the count value of the 16-bit
counter matches the value of the CCRn buffer register and the 16-bit counter is cleared to 0000H.
The valid edge of an external trigger input (EVTT0), or setting the software trigger (TT0CTL1.TT0EST bit) to 1 is used
as the trigger (n = 0, 1).
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Figure 9-23. Setting of Registers in External Trigger Pulse Output Mode (1/2)
(a) TMT0 control register 0 (TT0CTL0)
TT0CE
TT0CTL0
TT0CKS2 TT0CKS1 TT0CKS0
0/1
0
0
0
0
0/1
0/1
0/1
Select count clock
0: Stops counting
1: Enables counting
Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1.
(b) TMT0 control register 1 (TT0CTL1)
TT0EST TT0EEE
TT0CTL1
0
0/1
0
TT0MD3
0
0
TT0MD2 TT0MD1 TT0MD0
0
1
0
0, 0, 1, 0:
External trigger pulse
output mode
Generates software trigger
when 1 is written
(c) TMT0 I/O control register 0 (TT0IOC0)
TT0IOC0
0
0
0
0
TT0OL1
TT0OE1
TT0OL0
TT0OE0
0/1
0/1
0/1
0/1
0: Disables TOT00 pin output
1: Enables TOT00 pin output
Setting of TOT00 pin output level
while waiting for external trigger
0: Low level
1: High level
0: Disables TOT01 pin output
1: Enables TOT01 pin output
Setting of TOT01 pin output level
while waiting for external trigger
0: Low level
1: High level
• When TT0OL1 bit = 0
• When TT0OL1 bit = 1
16-bit counter
16-bit counter
TOT01 pin output
TOT01 pin output
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Figure 9-23. Setting of Registers in External Trigger Pulse Output Mode (2/2)
(d) TMT0 I/O control register 2 (TT0IOC2)
TT0EES1 TT0EES0 TT0ETS1 TT0ETS0
TT0IOC2
0
0
0
0
0
0
0/1
0/1
Select valid edge of external
trigger input (EVTT0 pin)Note
Note Set the valid edge selection of the unused alternate external input signals to “No edge detection”.
(e) TMT0 counter read buffer register (TT0CNT)
The value of the 16-bit counter can be read by reading the TT0CNT register.
(f) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1)
If D0 is set to the TT0CCR0 register and D1 to the TT0CCR1 register, the cycle and active level of the PWM
waveform are as follows.
Cycle = (D0 + 1) × Count clock cycle
Active level width = D1 × Count clock cycle
Remark
TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control
register 3 (TT0IOC3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1 (TT0OPT1),
and TMT0 counter write register (TT0TCW) are not used in the external trigger pulse output
mode.
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(1) Operation flow in external trigger pulse output mode
Figure 9-24. Software Processing Flow in External Trigger Pulse Output Mode (1/2)
FFFFH
D01
16-bit counter
D00
D10
D00
D10
D01
D01
D11
D10
D11
D00
D10
0000H
TT0CE bit
External trigger input
(EVTT0 pin input)
TT0CCR0 register
D00
CCR0 buffer register
D01
D00
D00
D01
D00
INTTT0CC0 signal
TOT00 pin output
D10
TT0CCR1 register
D10
D11
D10
CCR1 buffer register
D10
D10
D11
D10
INTTT0CC1 signal
TOT01 pin output
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Figure 9-24. Software Processing Flow in External Trigger Pulse Output Mode (2/2)
Count operation start flow
TT0CCR0, TT0CCR1 register
setting change flow
START
Setting of TT0CCR1 register
Register initial setting
TT0CTL0 register
(TT0CKS0 to TT0CKS2 bits)
TT0CTL1 register,
TT0IOC0 register,
TT0IOC2 register,
TT0CCR0 register,
TT0CCR1 register
TT0CE bit = 1
Initial setting of these
registers is performed
before setting the
TT0CE bit to 1.
Writing of the TT0CCR1 register
must be performed when only
the set duty factor is changed.
When the counter is cleared after
setting, the value of the
TT0CCRn register is transferred
to the CCRn buffer register.
TT0CCR0, TT0CCR1 register
setting change flow
The TT0CKS0 to
TT0CKS2 bits can be
set at the same time
as when counting is
enabled (TT0CE bit = 1).
Trigger wait status.
Setting of TT0CCR0 register
When the counter is
cleared after setting,
the value of the TT0CCRn
register is transferred to
the CCRn buffer register.
Setting of TT0CCR1 register
TT0CCR0 and TT0CCR1 register
setting change flow
Setting of TT0CCR0 register
Setting of TT0CCR1 register
Remark
Count operation stop flow
Writing the same value
(same as preset value of
the TT0CCR1 register)
to the TT0CCR1 register
is necessary only when
the set cycle is changed.
When the counter is
cleared after setting,
the values of the TT0CCRn
register are transferred to
the CCRn buffer register
in a batch.
TT0CE bit = 0
Counting is stopped.
STOP
n = 0, 1
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(2) External trigger pulse output mode operation timing
(a) Note on changing pulse width during operation
To change the PWM waveform while the counter is operating, write the TT0CCR1 register last.
Rewrite the TT0CCRn register after writing the TT0CCR1 register after the INTTT0CC0 signal is detected.
FFFFH
D01
16-bit counter
D00
D10
D00
D10
D00
D10
D11
D01
D11
0000H
TT0CE bit
External trigger input
(EVTT0 pin input)
TT0CCR0 register
CCR0 buffer register
D00
D01
D00
D01
INTTT0CC0 signal
TOT00 pin output
TT0CCR1 register
CCR1 buffer register
D10
D10
D11
D11
INTTT0CC1 signal
TOT01 pin output
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In order to transfer data from the TT0CCRn register to the CCRn buffer register, the TT0CCR1 register must be
written.
To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the
TT0CCR0 register and then set the active level width to the TT0CCR1 register.
To change only the cycle of the PWM waveform, first set the cycle to the TT0CCR0 register, and then write the
same value (same as preset value of the TT0CCR1 register) to the TT0CCR1 register.
To change only the active level width (duty factor) of the PWM waveform, only the TT0CCR1 register has to be
set.
After data is written to the TT0CCR1 register, the value written to the TT0CCRn register is transferred to the
CCRn buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared
with the 16-bit counter.
To write the TT0CCR0 or TT0CCR1 register again after writing the TT0CCR1 register once, do so after the
INTTT0CC0 signal is generated. Otherwise, the value of the CCRn buffer register may become undefined
because the timing of transferring data from the TT0CCRn register to the CCRn buffer register conflicts with
writing the TT0CCRn register.
Remark
n = 0, 1
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(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TT0CCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the
INTTT0CC0 and INTTT0CC1 signals are generated after a match between the count value of the 16-bit
counter and the value of the CCR0 buffer register.
Count clock
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0001
D0 − 1
D0
0000
TT0CE bit
External trigger input
(EVTT0 pin input)
TT0CCR0 register
D0
D0
D0
TT0CCR1 register
0000H
0000H
0000H
Note
Note
Note
Note
INTTT0CC0 signal
INTTT0CC1 signal
TOT01 pin output
L
Note The timing is actually delayed by one operating clock (fXX).
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To output a 100% waveform, set a value of (set value of TT0CCR0 register + 1) to the TT0CCR1 register. If the
set value of the TT0CCR0 register is FFFFH, 100% output cannot be produced.
Count clock
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0001
D0 − 1
D0
0000
TT0CE bit
External trigger input
(EVTT0 pin input)
TT0CCR0 register
D0
D0
D0
TT0CCR1 register
D0 + 1
D0 + 1
D0 + 1
Note
Note
INTTT0CC0 signal
INTTT0CC1 signal
TOT01 pin output
Note The timing is actually delayed by one operating clock (fXX).
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(c) Conflict between trigger detection and match with CCR1 buffer register
If the trigger is detected immediately after the INTTT0CC1 signal is generated, the 16-bit counter is
immediately cleared to 0000H, the TOT01 pin is asserted, and the counter continues counting. Consequently,
the inactive period of the PWM waveform is shortened.
16-bit counter
FFFF
D1 − 1
0000
0000
External trigger input
(EVTT0 pin input)
D1
CCR1 buffer register
INTTT0CC1 signal
TOT01 pin output
Shortened
If the trigger is detected immediately before the INTTT0CC1 signal is generated, the INTTT0CC1 signal is not
generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the TOT01
pin remains active. Consequently, the active period of the PWM waveform is extended.
16-bit counter
FFFF
0000
D1 − 2
0000
0001
D1 − 1
D1
External trigger input
(EVTT0 pin input)
CCR1 buffer register
D1
INTTT0CC1 signal
TOT01 pin output
Extended
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(d) Conflict between trigger detection and match with CCR0 buffer register
If the trigger is detected immediately after the INTTT0CC0 signal is generated, the 16-bit counter is cleared to
0000H and continues counting up again from that point. Therefore, the active period of the TOT01 pin is
extended by the time from generation of the INTTT0CC0 signal to trigger detection.
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0000
External trigger input
(EVTT0 pin input)
D0
CCR0 buffer register
INTTT0CC0 signal
TOT01 pin output
Extended
If the trigger is detected immediately before the INTTT0CC0 signal is generated, the INTTT0CC0 signal is not
generated. The 16-bit counter is cleared to 0000H, the TOT01 pin is asserted, and the counter continues
counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter
FFFF
0000
D0 − 1
D0
0000
0001
External trigger input
(EVTT0 pin input)
CCR0 buffer register
D0
INTTT0CC0 signal
TOT01 pin output
Shortened
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(e) Generation timing of compare match interrupt request signal (INTTT0CC1)
The timing of generating the INTTT0CC1 signal in the external trigger pulse output mode differs from the timing
of generating INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of
the 16-bit counter matches the value of the TT0CCR1 register.
Count clock
16-bit counter
D1 − 2
D1 − 1
D1
TT0CCR1 register
TOT01 pin output
INTTT0CC1 signal
D1 + 1
D1 + 2
D1
Note
Note
Note The timing is actually delayed by one operating clock (fXX).
Usually, the INTTT0CC1 signal is generated in synchronization with the next count-up, after the count value of
the 16-bit counter matches the value of the TT0CCR1 register.
In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing
is changed to match the timing when the output signal of the TOT01 pin changes.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
One-shot pulse output mode (TT0MD3 to TT0MD0 bits = 0011)
In the one-shot pulse output mode, 16-bit timer/event counter T waits for a trigger when the TT0CTL0.TT0CE bit is set
to 1. When the valid edge of an external trigger input (EVTT0) is detected, 16-bit timer/event counter T starts counting,
and outputs a one-shot pulse from the TOT01 pin.
Instead of the external trigger input (EVTT0), a software trigger can also be generated to output the pulse. When the
software trigger is used, the TOT00 pin outputs the active level while the 16-bit counter is counting, and the inactive level
when the counter is stopped (waiting for a trigger).
Figure 9-25. Configuration in One-Shot Pulse Output Mode
Edge
detectorNote 2
EVTT0 pinNote 1
(external
trigger input/
external event
count input)
TT0CCR1 register
Transfer
Software trigger
generation
Edge
detectorNote 3
Internal count clock
Output
S
controller
R
(RS-FF)
CCR1 buffer register
Match signal
Count
clock
selection
TOT01 pin
INTTT0CC1 signal
Clear
Count
start
control
Output
S
controller
R (RS-FF)
16-bit counter
Match signal
TT0CE bit
TOT00 pin
INTTT0CC0 signal
CCR0 buffer register
Transfer
TT0CCR0 register
Notes 1. Because the external trigger input pin (EVTT0) and external event count input pin (EVTT0) are
the same alternate-function pin, the external trigger input pin (EVTT0) cannot be used.
2. Edge detector for external trigger input.
Set by the TT0IOC2.TT0ETS1 and TT0IOC2.TT0ETS0 bits.
3. Edge detector for external event count input.
Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.
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Figure 9-26. Basic Timing in One-Shot Pulse Output Mode
FFFFH
D0
16-bit counter
D1
D0
D1
D0
D1
0000H
TT0CE bit
External trigger input
(EVTT0 pin input)
D0
TT0CCR0 register
INTTT0CC0 signal
TOT00 pin output
D1
TT0CCR1 register
INTTT0CC1 signal
TOT01 pin output
Delay
(D1)
Active
level width
(D0 − D1 + 1)
Delay
(D1)
Active
Delay
level width (D1)
(D0 − D1 + 1)
Active
level width
(D0 − D1 + 1)
When the TT0CE bit is set to 1, 16-bit timer/event counter T waits for a trigger. When the trigger is generated, the 16-bit
counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOT01 pin. After the oneshot pulse is output, the 16-bit counter is cleared to 0000H, stops counting, and waits for a trigger. When the trigger is
generated again, the 16-bit counter starts counting from 0000H. If a trigger is generated again while the one-shot pulse is
being output, it is ignored.
The output delay period and active level width of the one-shot pulse can be calculated as follows.
Output delay period = (Set value of TT0CCR1 register) × Count clock cycle
Active level width = (Set value of TT0CCR0 register − Set value of TT0CCR1 register + 1) × Count clock cycle
The compare match interrupt request signal (INTTT0CC0) is generated the next time the 16-bit counter counts after its
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal (INTTT0CC1) is
generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register.
The valid edge of an external trigger input (EVTT0 pin) or setting the software trigger (TT0CTL1.TT0EST bit) to 1 is
used as the trigger.
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Figure 9-27. Setting of Registers in One-Shot Pulse Output Mode (1/2)
(a) TMT0 control register 0 (TT0CTL0)
TT0CE
TT0CTL0
TT0CKS2 TT0CKS1 TT0CKS0
0/1
0
0
0
0
0/1
0/1
0/1
Select count clock
0: Stops counting
1: Enables counting
(b) TMT0 control register 1 (TT0CTL1)
TT0EST
TT0CTL1
0
0/1
TT0EEE
0
TT0MD3
0
0
TT0MD2 TT0MD1 TT0MD0
0
1
1
0, 0, 1, 1:
One-shot pulse output mode
Generates software trigger
when 1 is written
(c) TMT0 I/O control register 0 (TT0IOC0)
TT0IOC0
0
0
0
0
TT0OL1
TT0OE1
TT0OL0
TT0OE0
0/1
0/1
0/1
0/1
0: Disables TOT00 pin output
1: Enables TOT00 pin output
Setting of TOT00 pin output level
while waiting for external trigger
0: Low level
1: High level
0: Disables TOT01 pin output
1: Enables TOT01 pin output
Setting of TOT01 pin output level
while waiting for external trigger
0: Low level
1: High level
• When TT0OL1 bit = 0
• When TT0OL1 bit = 1
16-bit counter
16-bit counter
TOT01 pin output
TOT01 pin output
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Figure 9-27. Setting of Registers in One-Shot Pulse Output Mode (2/2)
(d) TMT0 I/O control register 2 (TT0IOC2)
TT0EES1 TT0EES0 TT0ETS1 TT0ETS0
TT0IOC2
0
0
0
0
0
0
0/1
0/1
Select valid edge of external
trigger input (EVTT0 pin)Note
Note Set the valid edge selection of the unused alternate external input signals to “No edge
detection”.
(e) TMT0 counter read buffer register (TT0CNT)
The value of the 16-bit counter can be read by reading the TT0CNT register.
(f) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1)
If D0 is set to the TT0CCR0 register and D1 to the TT0CCR1 register, the active level width and output
delay period of the one-shot pulse are as follows.
Active level width = (D0 − D1 + 1) × Count clock cycle
Output delay period = D1 × Count clock cycle
Remark
TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control
register 3 (TT0IOC3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1 (TT0OPT1),
and TMT0 counter write register (TT0TCW) are not used in the one-shot pulse output mode.
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(1) Operation flow in one-shot pulse output mode
Figure 9-28. Software Processing Flow in One-Shot Pulse Output Mode
FFFFH
D00
16-bit counter
D01
D10
D11
0000H
TT0CE bit
External trigger input
(EVTT0 pin input)
TT0CCR0 register
D00
D01
D10
D11
INTTT0CC0 signal
TT0CCR1 register
INTTT0CC1 signal
TOT01 pin output
Count operation start flow
Count operation stop flow
TT0CE bit = 0
START
Register initial setting
TT0CTL0 register
(TT0CKS0 to TT0CKS2 bits)
TT0CTL1 register,
TT0IOC0 register,
TT0IOC2 register,
TT0CCR0 register,
TT0CCR1 register
TT0CE bit = 1
Initial setting of these
registers is performed
before setting the
TT0CE bit to 1.
Count operation is stopped
STOP
The TT0CKS0 to
TT0CKS2 bits can be
set at the same time
as when counting starts
(TT0CE bit = 1).
Trigger wait status
TT0CCR0, TT0CCR1 register setting change flow
Setting of TT0CCR0, TT0CCR1
registers
Remark
As rewriting the
TT0CCRn register
immediately forwards
to the CCRn buffer
register, rewriting
immediately after
the generation of the
INTTT0CC0 signal
is recommended.
n = 0, 1
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(2) Operation timing in one-shot pulse output mode
(a) Note on rewriting TT0CCRn register
If the value of the TT0CCRn register is rewritten to a smaller value during counting, the 16-bit counter may
overflow. When an overflow may occur, stop counting and then change the set value.
Remark
n = 0, 1
FFFFH
D00
16-bit counter
D00
D10
D10
D00
D10
D01
D11
0000H
TT0CE bit
External trigger input
(EVTT0 pin input)
D00
TT0CCR0 register
D01
INTTT0CC0 signal
TOT00 pin output
D10
TT0CCR1 register
D11
INTTT0CC1 signal
TOT01 pin output
Delay
(D10)
Delay
(D10)
Active level width
(D00 − D10 + 1)
Active level width
(D00 − D10 + 1)
Delay
(10000H + D11)
Active level width
(D01 − D11 + 1)
When the TT0CCR0 register is rewritten from D00 to D01 and the TT0CCR1 register from D10 to D11 where D00 >
D01 and D10 > D11, if the TT0CCR1 register is rewritten when the count value of the 16-bit counter is greater
than D11 and less than D10 and if the TT0CCR0 register is rewritten when the count value is greater than D01
and less than D00, each set value is reflected as soon as the register has been rewritten and compared with the
count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value
matches D11, the counter generates the INTTT0CC1 signal and asserts the TOT01 pin. When the count value
matches D01, the counter generates the INTTT0CC0 signal, deasserts the TOT01 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the oneshot pulse that is originally expected.
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(b) Generation timing of compare match interrupt request signal (INTTT0CC1)
The generation timing of the INTTT0CC1 signal in the one-shot pulse output mode is different from
INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of the 16-bit
counter matches the value of the TT0CCR1 register.
Count clock
16-bit counter
D1 − 2
D1 − 1
D1
TT0CCR1 register
TOT01 pin output
INTTT0CC1 signal
D1 + 1
D1 + 2
D1
Note
Note
Note The timing is actually delayed by one operating clock (fXX).
Usually, the INTTT0CC1 signal is generated the next time the 16-bit counter counts up after its count value
matches the value of the TT0CCR1 register.
In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is
changed to match the timing the output signal of the TOT01 pin changes.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
PWM output mode (TT0MD3 to TT0MD0 bits = 0100)
In the PWM output mode, a PWM waveform is output from the TOT01 pin when the TT0CTL0.TT0CE bit is set to 1.
In addition, a square wave with the set value of the TT0CCR0 register + 1 as half its cycle is output from the TOT00 pin.
Figure 9-29. Configuration in PWM Output Mode
TT0CCR1 register
Transfer
Output
S
controller
R (RS-FF)
CCR1 buffer register
Match signal
Internal count clock
EVTT0 pin
(external event
count input)
Edge
detectorNote
INTTT0CC1 signal
Clear
Count
clock
selection
16-bit counter
Output
controller
Match signal
TT0CE bit
TOT01 pin
TOT00 pin
INTTT0CC0 signal
CCR0 buffer register
Transfer
TT0CCR0 register
Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.
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Figure 9-30. Basic Timing in PWM Output Mode
FFFFH
D01
16-bit counter
D00
D10
D00
D10
D00
D10
D11
D01
D11
0000H
TT0CE bit
TT0CCR0 register
CCR0 buffer register
D00
D01
D00
D01
INTTT0CC0 signal
TOT00 pin output
TT0CCR1 register
CCR1 buffer register
D10
D11
D10
D11
INTTT0CC1 signal
TOT01 pin output
Active period Cycle
(D10)
(D00 + 1)
Inactive period
(D00 - D10 + 1)
When the TT0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
PWM waveform from the TOT01 pin.
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TT0CCR1 register) × Count clock cycle
Cycle = (Set value of TT0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TT0CCR1 register)/(Set value of TT0CCR0 register + 1)
The PWM waveform can be changed by rewriting the TT0CCRn register while the counter is operating. The newly
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the
16-bit counter is cleared to 0000H.
The compare match interrupt request signal (INTTT0CC0) is generated the next time the 16-bit counter counts after its
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal (INTTT0CC1) is generated when the count value of the 16-bit counter matches the value of
the CCR1 buffer register.
The value set to the TT0CCRn register is transferred to the CCRn buffer register when the count value of the 16-bit
counter matches the value of the CCRn buffer register and the 16-bit counter is cleared to 0000H.
Remark
n = 0, 1
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Figure 9-31. Setting of Registers in PWM Output Mode (1/2)
(a) TMT0 control register 0 (TT0CTL0)
TT0CE
TT0CTL0
TT0CKS2 TT0CKS1 TT0CKS0
0/1
0
0
0
0
0/1
0/1
0/1
Select count clockNote
0: Stops counting
1: Enables counting
Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1.
(b) TMT0 control register 1 (TT0CTL1)
TT0MD3 TT0MD2 TT0MD1 TT0MD0
TT0EST TT0EEE
TT0CTL1
0
0
0/1
0
0
1
0
0
0, 1, 0, 0:
PWM output mode
0: Operates on count clock
selected by TT0CKS0 to
TT0CKS2 bits
1: Counts with external event
count input signal
(c) TMT0 I/O control register 0 (TT0IOC0)
TT0IOC0
0
0
0
0
TT0OL1
TT0OE1
TT0OL0
TT0OE0
0/1
0/1
0/1
0/1
0: Disables TOT00 pin output
1: Enables TOT00 pin output
Setting of TOT00 pin output
level before count operation
0: Low level
1: High level
0: Disables TOT01 pin output
1: Enables TOT01 pin output
Setting of TOT01 pin output
level before count operation
0: Low level
1: High level
• When TT0OL1 bit = 0
• When TT0OL1 bit = 1
16-bit counter
16-bit counter
TOT01 pin output
TOT01 pin output
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Figure 9-31. Register Setting in PWM Output Mode (2/2)
(d) TMT0 I/O control register 2 (TT0IOC2)
TT0EES1 TT0EES0 TT0ETS1 TT0ETS0
TT0IOC2
0
0
0
0
0/1
0/1
0
0
Select valid edge
of external event
count input (EVTT0 pin).
(e) TMT0 counter read buffer register (TT0CNT)
The value of the 16-bit counter can be read by reading the TT0CNT register.
(f) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1)
If D0 is set to the TT0CCR0 register and D1 to the TT0CCR1 register, the cycle and active level of the
PWM waveform are as follows.
Cycle = (D0 + 1) × Count clock cycle
Active level width = D1 × Count clock cycle
Remark
TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control
register 3 (TT0CTL3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1
(TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the PWM output
mode.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(1) Operation flow in PWM output mode
Figure 9-32. Software Processing Flow in PWM Output Mode (1/2)
FFFFH
D01
16-bit counter
D00
D01
D00
D10
D10
D01
D11
D11
D10
D00
D10
0000H
TT0CE bit
TT0CCR0 register
D00
CCR0 buffer register
D01
D00
D00
D01
D00
INTTT0CC0 signal
TOT00 pin output
D10
TT0CCR1 register
D10
D10
CCR1 buffer register
D11
D10
D10
D11
D10
INTTT0CC1 signal
TOT01 pin output
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Figure 9-32. Software Processing Flow in PWM Output Mode (2/2)
Count operation start flow
TT0CCR0, TT0CCR1 register
setting change flow (duty only)
START
Setting of TT0CCR1 register
Register initial setting
TT0CTL0 register
(TT0CKS0 to TT0CKS2 bits)
TT0CTL1 register,
TT0IOC0 register,
TT0IOC2 register,
TT0CCR0 register,
TT0CCR1 register
TT0CE bit = 1
Initial setting of these
registers is performed
before setting the
TT0CE bit to 1.
Only writing of the TT0CCR1
register must be performed
when the set duty factor is
changed. When the counter is
cleared after setting, the
value of compare register n
is transferred to the CCRn
buffer register.
TT0CCR0, TT0CCR1 register
setting change flow (cycle and duty)
The TT0CKS0 to
TT0CKS2 bits can be
set at the same time
as when counting is
enabled (TT0CE bit = 1).
Setting of TT0CCR0 register
When the counter is
cleared after setting,
the values of compare
register n are transferred
to the CCRn buffer register
in a batch.
Setting of TT0CCR1 register
TT0CCR0, TT0CCR1 register
setting change flow (cycle only)
Setting of TT0CCR0 register
Setting of TT0CCR1 register
Remark
Count operation stop flow
Writing the same value
(same as preset value of
the TT0CCR1 register)
to the TT0CCR1 register
is necessary only when
the set cycle is changed.
When the counter is
cleared after setting,
the value of the TT0CCRn
register is transferred to the
CCRn buffer register.
TT0CE bit = 0
Counting is stopped.
STOP
n = 0, 1
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(2) PWM output mode operation timing
(a) Changing pulse width during operation
To change the PWM waveform while the counter is operating, write the TT0CCR1 register last.
Rewrite the TT0CCRn register after writing the TT0CCR1 register after the INTTT0CC1 signal is detected.
FFFFH
D01
16-bit counter
D00
D10
D00
D10
D00
D10
D11
D01
D11
0000H
TT0CE bit
TT0CCR0 register
CCR0 buffer register
TT0CCR1 register
CCR1 buffer register
D00
D01
D00
D10
D10
D01
D11
D11
TOT01 pin output
INTTT0CC0 signal
To transfer data from the TT0CCRn register to the CCRn buffer register, the TT0CCR1 register must be written.
To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TT0CCR0
register and then set the active level width to the TT0CCR1 register.
To change only the cycle of the PWM waveform, first set the cycle to the TT0CCR0 register, and then write the
same value (same as preset value of the TT0CCR1 register) to the TT0CCR1 register.
To change only the active level width (duty factor) of the PWM waveform, only the TT0CCR1 register has to be
set.
After data is written to the TT0CCR1 register, the value written to the TT0CCRn register is transferred to the
CCRn buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared
with the 16-bit counter.
To write the TT0CCR0 or TT0CCR1 register again after writing the TT0CCR1 register once, do so after the
INTTT0CC0 signal is generated. Otherwise, the value of the CCRn buffer register may become undefined
because the timing of transferring data from the TT0CCRn register to the CCRn buffer register conflicts with
writing the TT0CCRn register.
Remark
n = 0, 1
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TT0CCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the
INTTT0CC0 and INTTT0CC1 signals are generated after a match between the count value of the 16-bit
counter and the value of the CCR0 buffer register.
Count clock
16-bit counter
FFFF
0000
D00 − 1
D00
0000
0001
D00 − 1
D00
0000
TT0CE bit
TT0CCR0 register
D00
D00
D00
TT0CCR1 register
0000H
0000H
0000H
Note
Note
Note
Note
INTTT0CC0 signal
INTTT0CC1 signal
TOT01 pin output
L
Note The timing is actually delayed by one operating clock (fXX).
To output a 100% waveform, set a value of (set value of TT0CCR0 register + 1) to the TT0CCR1 register. If the
set value of the TT0CCR0 register is FFFFH, 100% output cannot be produced.
Count clock
16-bit counter
FFFF
0000
D00 − 1
D00
0000
0001
D00 − 1
D00
0000
TT0CE bit
TT0CCR0 register
D00
D00
D00
TT0CCR1 register
D00 + 1
D00 + 1
D00 + 1
Note
Note
INTTT0CC0 signal
INTTT0CC1 signal
TOT01 pin output
Note The timing is actually delayed by one operating clock (fXX).
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(c) Generation timing of compare match interrupt request signal (INTTT0CC1)
The timing of generation of the INTTT0CC1 signal in the PWM output mode differs from the timing of
INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of the 16-bit
counter matches the value of the TT0CCR1 register.
Count clock
16-bit counter
D1 − 2
D1 − 1
D1
TT0CCR1 register
TOT01 pin output
INTTT0CC1 signal
D1 + 1
D1 + 2
D1
Note
Note
Note The timing is actually delayed by one operating clock (fXX).
Usually, the INTTT0CC1 signal is generated in synchronization with the next count-up after the count value of
the 16-bit counter matches the value of the TT0CCR1 register.
In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed to
match the timing at which the output signal of the TOT01 pin changes.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Free-running timer mode (TT0MD3 to TT0MD0 bits = 0101)
In the free-running timer mode, 16-bit timer/event counter T starts counting when the TT0CTL0.TT0CE bit is set to 1. At
this time, the TT0CCR0 and TT0CCR1 registers can be used as compare registers or capture registers, depending on the
setting of the TT0OPT0.TT0CCS0 and TT0OPT0.TT0CCS1 bits.
Figure 9-33. Configuration in Free-Running Timer Mode
TT0CCR1 register
(compare)
TT0CCR0 register
(capture)
Output
controller
TOT01 pinNote 1 output
Output
controller
TOT00 pinNote 1 output
TT0CCS0, TT0CCS1 bits
(capture/compare selection)
Internal count clock
EVTT0 pin
(external event
count input)
Note 1
TIT00 pin
(capture
trigger input)
TIT01 pinNote 1
(capture
trigger input)
Edge
detectorNote 2
Count
clock
selection
INTTT0OV signal
16-bit counter
0
TT0CE bit
INTTT0CC1 signal
1
Edge
detectorNote 3
0
TT0CCR0 register
(capture)
INTTT0CC0 signal
1
Edge
detectorNote 4
TT0CCR1 register
(compare)
Notes 1. Because the capture trigger input pins (TIT00, TIT01) and timer output pins (TOT00, TOT01)
are the same alternate-function pins, two functions cannot be used at the same time.
2. Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.
3. Set by the TT0IOC1.TT0IS1 and TT0IOC1.TT0IS0 bits.
4. Set by the TT0IOC1.TT0IS3 and TT0IOC1.TT0IS2 bits.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
• Compare operation
When the TT0CE bit is set to 1, 16-bit timer/event counter T starts counting, and the output signal of the TOT0n pin is
inverted. When the count value of the 16-bit counter later matches the set value of the TT0CCRn register, a compare
match interrupt request signal (INTTT0CCn) is generated, and the output signal of the TOT0n pin is inverted.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTT0OV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Confirm that the overflow flag is set
to 1 and then clear it to 0 by executing the CLR instruction via software.
The TT0CCRn register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at
that time by anytime write, and compared with the count value.
Figure 9-34. Basic Timing in Free-Running Timer Mode (Compare Function)
FFFFH
D00
D00
D01
16-bit counter
D10
D10
D11
D01
D11
D11
0000H
TT0CE bit
TT0CCR0 register
D00
D01
INTTT0CC0 signal
TOT00 pin output
TT0CCR1 register
D10
D11
INTTT0CC1 signal
TOT01 pin output
INTTT0OV signal
TT0OVF bit
Cleared to 0 by
CLR instruction
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Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
• Capture operation
When the TT0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIT0n pin is
detected, the count value of the 16-bit counter is stored in the TT0CCRn register, and a capture interrupt request
signal (INTTT0CCn) is generated.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTT0OV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Confirm that the overflow flag is set
to 1 and then clear it to 0 by executing the CLR instruction via software.
Figure 9-35. Basic Timing in Free-Running Timer Mode (Capture Function)
FFFFH
D10
D00
16-bit counter
D11
D12
D13
D01
D02
D03
0000H
TT0CE bit
TIT00 pin input
TT0CCR0 register
D00
D01
D02
D03
INTTT0CC0 signal
TIT01 pin input
TT0CCR1 register
D10
D11
D12
D13
INTTT0CC1 signal
INTTT0OV signal
TT0OVF bit
Cleared to 0 by
CLR instruction
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Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Figure 9-36. Register Setting in Free-Running Timer Mode (1/2)
(a) TMT0 control register 0 (TT0CTL0)
TT0CE
TT0CTL0
TT0CKS2 TT0CKS1 TT0CKS0
0/1
0
0
0
0
0/1
0/1
0/1
Select count clockNote
0: Stops counting
1: Enables counting
Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1
(b) TMT0 control register 1 (TT0CTL1)
TT0EST TT0EEE
TT0CTL1
0
0
TT0MD3 TT0MD2 TT0MD1 TT0MD0
0/1
0
0
1
0
1
0, 1, 0, 1:
Free-running timer mode
0: Operates with count
clock selected by
TT0CKS0 to TT0CKS2 bits
1: Counts on external
event count input signal
(c) TMT0 I/O control register 0 (TT0IOC0)
TT0IOC0
0
0
0
TT0OL1
TT0OE1
TT0OL0
TT0OE0
0/1
0/1
0/1
0/1
0
0: Disables TOT00 pin output
1: Enables TOT00 pin output
Setting of TOT00 pin output
level before count operation
0: Low level
1: High level
0: Disables TOT01 pin output
1: Enables TOT01 pin output
Setting of TOT01 pin output
level before count operation
0: Low level
1: High level
(d) TMT0 I/O control register 1 (TT0IOC1)
TT0IOC1
0
0
0
0
TT0IS3
TT0IS2
TT0IS1
TT0IS0
0/1
0/1
0/1
0/1
Select valid edge
of TIT00 pin input
Select valid edge
of TIT01 pin input
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Figure 9-36. Register Setting in Free-Running Timer Mode (2/2)
(e) TMT0 I/O control register 2 (TT0IOC2)
TT0EES1 TT0EES0 TT0ETS1 TT0ETS0
TT0IOC2
0
0
0
0
0/1
0/1
0
0
Select valid edge of
external event count
input (EVTT0 pin)
(f) TMT0 option register 0 (TT0OPT0)
TT0CCS1 TT0CCS0
TT0OPT0
0
0
0/1
0/1
TT0OVF
0
0
0
0/1
Overflow flag
Specifies if TT0CCR0
register functions as
capture or compare register
0: Compare register
1: Capture register
Specifies if TT0CCR1
register functions as
capture or compare register
0: Compare register
1: Capture register
(g) TMT0 counter read buffer register (TT0CNT)
The value of the 16-bit counter can be read by reading the TT0CNT register.
(h) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1)
These registers function as capture registers or compare registers depending on the setting of the
TT0OPT0.TT0CCSn bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIT0n pin is detected.
When the registers function as compare registers and when Da is set to the TT0CCRn register, the
INTTT0CCn signal is generated when the counter reaches (Da + 1), and the output signals of the
TOT00 and TOT01 pins are inverted.
Remark
n = 0, 1
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(1) Operation flow in free-running timer mode
(a) When using capture/compare register as compare register
Figure 9-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2)
FFFFH
D00
D00
D01
16-bit counter
D10
D10
D11
D01
D11
D11
0000H
TT0CE bit
TT0CCR0 register
D00
D01
INTTT0CC0 signal
TOT00 pin output
D10
TT0CCR1 register
D11
INTTT0CC1 signal
TOT01 pin output
INTTT0OV signal
TT0OVF bit
Cleared to 0 by
CLR instruction
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Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Figure 9-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2)
Count operation start flow
START
Register initial setting
TT0CTL0 register
(TT0CKS0 to TT0CKS2 bits)
TT0CTL1 register,
TT0IOC0 register,
TT0IOC2 register,
TT0OPT0 register,
TT0CCR0 register,
TT0CCR1 register
Initial setting of these registers
is performed before setting the
TT0CE bit to 1.
The TT0CKS0 to TT0CKS2 bits
can be set at the same time
as when counting starts
(TT0CE bit = 1).
TT0CE bit = 1
Overflow flag clear flow
Read TT0OPT0 register
(check overflow flag).
TT0OVF bit = 1
No
Yes
Execute instruction to clear
TT0OVF bit (CLR TT0OVF).
Count operation stop flow
TT0CE bit = 0
Counter is initialized and
counting is stopped by
clearing TT0CE bit to 0.
STOP
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(b) When using capture/compare register as capture register
Figure 9-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2)
FFFFH
D10
D00
D11
D12
D01
16-bit counter
D02
D03
0000H
TT0CE bit
TIT00 pin input
TT0CCR0 register
0000
D00
D01
D02
D03
0000
INTTT0CC0 signal
TIT01 pin input
0000
TT0CCR1 register
D10
D11
D12
0000
INTTT0CC1 signal
INTTT0OV signal
TT0OVF bit
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Figure 9-38. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2)
Count operation start flow
START
Register initial setting
TT0CTL0 register
(TT0CKS0 to TT0CKS2 bits)
TT0CTL1 register,
TT0IOC1 register,
TT0OPT0 register
Initial setting of these registers
is performed before setting the
TT0CE bit to 1.
The TT0CKS0 to TT0CKS2 bits can
be set at the same time as when counting
starts (TT0CE bit = 1).
TT0CE bit = 1
Overflow flag clear flow
Read TT0OPT0 register
(check overflow flag).
TT0OVF bit = 1
No
Yes
Execute instruction to clear
TT0OVF bit (CLR TT0OVF).
Count operation stop flow
TT0CE bit = 0
Counter is initialized and
counting is stopped by
clearing TT0CE bit to 0.
STOP
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(2) Operation timing in free-running timer mode
(a) Interval operation with compare register
When 16-bit timer/event counter T is used as an interval timer with the TT0CCRn register used as a compare
register, software processing is necessary for setting a comparison value to generate the next interrupt request
signal each time the INTTT0CCn signal has been detected.
FFFFH
D02
D10
D00
D11
16-bit counter
D03
D12
D01
D13
0000H
D04
TT0CE bit
TT0CCR0 register
D00
D01
D02
D03
D04
D05
INTTT0CC0 signal
TOT00 pin output
Interval period Interval period Interval period Interval period Interval period
(D00 + 1)
(10000H +
(D02 − D01)
(10000H +
(10000H +
D01 − D00)
D03 − D02)
D04 − D03)
TT0CCR1 register
D10
D11
D12
D13
D14
INTTT0CC1 signal
TOT01 pin output
Interval period Interval period Interval period Interval period
(D10 + 1)
(10000H +
(10000H +
(10000H +
D11 − D10)
D12 − D11)
D13 − D12)
When performing an interval operation in the free-running timer mode, two intervals can be set with one
channel.
To perform the interval operation, the value of the corresponding TT0CCRn register must be re-set in the
interrupt servicing that is executed when the INTTT0CCn signal is detected.
The set value for re-setting the TT0CCRn register can be calculated by the following expression, where “Da” is
the interval period.
Compare register default value: Da − 1
Value set to compare register second and subsequent time: Previous set value + Da
(If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the
register.)
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(b) Pulse width measurement with capture register
When pulse width measurement is performed with the TT0CCRn register used as a capture register, software
processing is necessary for reading the capture register each time the INTTT0CCn signal has been detected
and for calculating an interval.
FFFFH
D02
D10
D00
D11
16-bit counter
D03
D12
D01
D13
0000H
D04
TT0CE bit
TIT00 pin input
TT0CCR0 register
0000H
D00
D01
D02
D03
D04
INTTT0CC0 signal
Pulse interval Pulse interval Pulse interval Pulse interval Pulse interval
(D00)
(10000H +
(10000H +
(D02 − D01)
(10000H +
D01 - D00)
D03 − D02)
D04 − D03)
TIT01 pin input
TT0CCR1 register
0000H
D10
D11
D12
D13
INTTT0CC1 signal
Pulse interval Pulse interval Pulse interval Pulse interval
(D10)
(10000H +
(10000H +
(10000H +
D11 − D10)
D12 − D11)
D13 − D12)
INTTT0OV signal
TT0OVF bit
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
When executing pulse width measurement in the free-running timer mode, two pulse widths can be measured
with one channel.
To measure a pulse width, the pulse width can be calculated by reading the value of the TT0CCRn register in
synchronization with the INTTT0CCn signal, and calculating the difference between the read value and the
previously read value.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(c) Processing of overflow when two capture registers are used
Care must be exercised in processing the overflow flag when two capture registers are used. First, an example
of incorrect processing is shown below.
Example of incorrect processing when two capture registers are used
FFFFH
D11
D10
16-bit counter
D01
D00
0000H
TT0CE bit
TIT00 pin input
TT0CCR0 register
D01
D00
TIT01 pin input
D11
D10
TT0CCR1 register
INTTT0OV signal
TT0OVF bit
The following problem may occur when two pulse widths are measured in the free-running timer mode.
Read the TT0CCR0 register (setting of the default value of the TIT00 pin input).
Read the TT0CCR1 register (setting of the default value of the TIT01 pin input).
Read the TT0CCR0 register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 − D00).
Read the TT0CCR1 register.
Read the overflow flag. Because the flag is cleared in , 0 is read.
Because the overflow flag is 0, the pulse width can be calculated by (D11 − D10) (incorrect).
When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other
capture register may not obtain the correct pulse width.
Use software when using two capture registers. An example of how to use software is shown below.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(1/2)
Example when two capture registers are used (using overflow interrupt)
FFFFH
D11
D10
16-bit counter
D01
D00
0000H
TT0CE bit
INTTT0OV signal
TT0OVF bit
TT0OVF0 flagNote
TIT00 pin input
D01
D00
TT0CCR0 register
TT0OVF1 flagNote
TIT01 pin input
D11
D10
TT0CCR1 register
Note The TT0OVF0 and TT0OVF1 flags are set on the internal RAM by software.
Read the TT0CCR0 register (setting of the default value of the TIT00 pin input).
Read the TT0CCR1 register (setting of the default value of the TIT01 pin input).
An overflow occurs. Set the TT0OVF0 and TT0OVF1 flags to 1 in the overflow interrupt servicing,
and clear the overflow flag to 0.
Read the TT0CCR0 register.
Read the TT0OVF0 flag. If the TT0OVF0 flag is 1, clear it to 0.
Because the TT0OVF0 flag is 1, the pulse width can be calculated by (10000H + D01 − D00).
Read the TT0CCR1 register.
Read the TT0OVF1 flag. If the TT0OVF1 flag is 1, clear it to 0 (the TT0OVF0 flag is cleared in
, and the TT0OVF1 flag remains 1).
Because the TT0OVF1 flag is 1, the pulse width can be calculated by (10000H + D11 − D10)
(correct).
Same as
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(2/2)
Example when two capture registers are used (without using overflow interrupt)
FFFFH
D11
D10
16-bit counter
D01
D00
0000H
TT0CE bit
INTTT0OV signal
TT0OVF bit
TT0OVF0 flagNote
TIT00 pin input
D01
D00
TT0CCR0 register
TT0OVF1 flagNote
TIT01 pin input
D11
D10
TT0CCR1 register
Note The TT0OVF0 and TT0OVF1 flags are set on the internal RAM by software.
Read the TT0CCR0 register (setting of the default value of the TIT00 pin input).
Read the TT0CCR1 register (setting of the default value of the TIT01 pin input).
An overflow occurs. Nothing is done by software.
Read the TT0CCR0 register.
Read the overflow flag. If the overflow flag is 1, set only the TT0OVF1 flag to 1, and clear the
overflow flag to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 − D00).
Read the TT0CCR1 register.
Read the overflow flag. Because the overflow flag is cleared in , 0 is read.
Read the TT0OVF1 flag. If the TT0OVF1 flag is 1, clear it to 0.
Because the TT0OVF1 flag is 1, the pulse width can be calculated by (10000H + D11 − D10)
(correct).
Same as
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(d) Processing of overflow if capture trigger interval is long
If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow
may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is
shown below.
Example of incorrect processing when capture trigger interval is long
FFFFH
Da0
16-bit counter
Da1
0000H
TT0CE bit
TIT0n pin input
TT0CCRn register
Da0
Da1
INTTT0OV signal
TT0OVF bit
1 cycle of 16-bit counter
Pulse width
The following problem may occur when long pulse width is measured in the free-running timer mode.
Read the TT0CCRn register (setting of the default value of the TIT0n pin input).
An overflow occurs. Nothing is done by software.
An overflow occurs a second time. Nothing is done by software.
Read the TT0CCRn register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + Da1 − Da0)
(incorrect).
Actually, the pulse width must be (20000H + Da1 − Da0) because an overflow occurs twice.
Remark
n = 0, 1
If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be
obtained.
If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use
software. An example of how to use software is shown next.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Example when capture trigger interval is long
FFFFH
Da0
16-bit counter
Da1
0000H
TT0CE bit
TIT0n pin input
TT0CCRn register
Da0
Da1
INTTT0OV signal
TT0OVF bit
Overflow
counterNote
0H
1H
2H
0H
1 cycle of 16-bit counter
Pulse width
Note The overflow counter is set arbitrarily by software on the internal RAM.
Read the TT0CCRn register (setting of the default value of the TIT0n pin input).
An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the
overflow interrupt servicing.
An overflow occurs a second time. Increment the overflow counter and clear the overflow flag to 0
in the overflow interrupt servicing.
Read the TT0CCRn register.
Read the overflow counter.
→ When the overflow counter is “N”, the pulse width can be calculated by (N × 10000H + Da1 –
Da0).
In this example, the pulse width is (20000H + Da1 – Da0) because an overflow occurs twice.
Clear the overflow counter (0H).
Remark
n = 0, 1
(e) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TT0OVF bit to 0 with the CLR instruction after reading the
TT0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TT0OPT0 register after reading the TT0OVF
bit when it is 1.
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9.6.7
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Pulse width measurement mode (TT0MD3 to TT0MD0 bits = 0110)
In the pulse width measurement mode, 16-bit timer/event counter T starts counting when the TT0CTL0.TT0CE bit is set
to 1. Each time the valid edge input to the TIT0n pin has been detected, the count value of the 16-bit counter is stored in
the TT0CCRn register, and the 16-bit counter is cleared to 0000H.
The interval of the valid edge can be measured by reading the TT0CCRn register after a capture interrupt request
signal (INTTT0CCn) occurs.
As shown in Figure 9-39, select either the TIT00 or TIT01 pin as the capture trigger input pin and set the unused pins to
“No edge detection” by using the TT0IOC1 register.
Figure 9-39. Configuration in Pulse Width Measurement Mode
Clear
Internal count clock
EVTT0 pin
(external event
count input)
Edge
detectorNote 1
Count
clock
selection
16-bit counter
INTTT0OV signal
INTTT0CC0 signal
TT0CE bit
TIT00 pin
(capture
trigger input)
Edge
detectorNote 2
TIT01 pin
(capture
trigger input)
Edge
detectorNote 3
INTTT0CC1 signal
TT0CCR0 register
(capture)
TT0CCR1 register
(capture)
Notes 1. Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.
2. Set by the TT0IOC1.TT0IS1 and TT0IOC1.TT0IS0 bits.
3. Set by the TT0IOC1.TT0IS3 and TT0IOC1.TT0IS2 bits.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Figure 9-40. Basic Timing in Pulse Width Measurement Mode
FFFFH
16-bit counter
0000H
TT0CE bit
TIT0n pin input
TT0CCRn register
0000H
D0
D1
D2
D3
INTTT0CCn signal
INTTT0OV signal
TT0OVF bit
Remark
Cleared to 0 by
CLR instruction
n = 0, 1
When the TT0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIT0n pin is later
detected, the count value of the 16-bit counter is stored in the TT0CCRn register, the 16-bit counter is cleared to 0000H,
and a capture interrupt request signal (INTTT0CCn) is generated.
The pulse width is calculated as follows.
Pulse width = Captured value × Count clock cycle
If the valid edge is not input to the TIT0n pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt
request signal (INTTT0OV) is generated at the next count clock, and the counter is cleared to 0000H and continues
counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing
the CLR instruction via software.
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Pulse width = (10000H × TT0OVF bit set (1) count + Captured value) × Count clock cycle
Remark
n = 0, 1
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Figure 9-41. Register Setting in Pulse Width Measurement Mode (1/2)
(a) TMT0 control register 0 (TT0CTL0)
TT0CE
TT0CTL0
0/1
TT0CKS2 TT0CKS1 TT0CKS0
0
0
0
0
0/1
0/1
0/1
Select count clockNote
0: Stops counting
1: Enables counting
Note Setting is invalid when the TT0CTL1.TT0EEE bit = 1.
(b) TMT0 control register 1 (TT0CTL1)
TT0EST TT0EEE
TT0CTL1
0
0
0/1
TT0MD3 TT0MD2 TT0MD1 TT0MD0
0
0
1
1
0
0, 1, 1, 0:
Pulse width measurement mode
0: Operates with count
clock selected by
TT0CKS0 to TT0CKS2 bits
1: Counts on external
event count input signal
(c) TMT0 I/O control register 1 (TT0IOC1)
TT0IOC1
0
0
0
0
TT0IS3
TT0IS2
TT0IS1
TT0IS0
0/1
0/1
0/1
0/1
Select valid edge
of TIT00 pin input
Select valid edge
of TIT01 pin input
(d) TMT0 I/O control register 2 (TT0IOC2)
TT0EES1 TT0EES0 TT0ETS1 TT0ETS0
TT0IOC2
0
0
0
0
0/1
0/1
0
0
Select valid edge of
external event count
input (EVTT0 pin)
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Figure 9-41. Register Setting in Pulse Width Measurement Mode (2/2)
(e) TMT0 option register 0 (TT0OPT0)
TT0CCS1 TT0CCS0
TT0OPT0
0
0
0
0
TT0OVF
0
0
0
0/1
Overflow flag
(f) TMT0 counter read buffer register (TT0CNT)
The value of the 16-bit counter can be read by reading the TT0CNT register.
(g) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1)
These registers store the count value of the 16-bit counter when the valid edge input to the TIT00 and
TIT01 pins is detected.
Remark
TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 0 (TT0IOC0), TMT0 I/O control
register 3 (TT0IOC3), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register
(TT0TCW) are not used in the pulse width measurement mode.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(1) Operation flow in pulse width measurement mode
Figure 9-42. Software Processing Flow in Pulse Width Measurement Mode
FFFFH
16-bit counter
0000H
TT0CE bit
TIT00 pin input
TT0CCR0 register
0000H
D0
D1
D2
0000H
INTTT0CC0 signal
Count operation start flow
START
Register initial setting
TT0CTL0 register
(TT0CKS0 to TT0CKS2 bits),
TT0CTL1 register,
TT0IOC1 register,
TT0IOC2 register,
TT0OPT0 register
TT0CE bit = 1
Initial setting of these registers
is performed before setting the
TT0CE bit to 1.
The TT0CKS0 to TT0CKS2 bits can
be set at the same time as when counting
starts (TT0CE bit = 1).
Count operation stop flow
TT0CE bit = 0
The counter is initialized and counting
is stopped by clearing the TT0CE bit to 0.
STOP
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
(2) Operation timing in pulse width measurement mode
(a) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TT0OVF bit to 0 with the CLR instruction after reading the
TT0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TT0OPT0 register after reading the TT0OVF
bit when it is 1.
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9.6.8
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Triangular-wave PWM output mode (TT0MD3 to TT0MD0 bits = 0111)
In the triangular-wave PWM output mode, a triangular-wave PWM waveform is output from the TOT01 pin when the
TT0CTL0.TT0CE bit is set to 1.
A PWM waveform that is inverted when the count value of the 16-bit counter matches the value of the CCR0 buffer
register and when the 16-bit counter is set to 0000H is output from the TOT00 pin.
Figure 9-43. Configuration in Triangular-Wave PWM Output Mode
TT0CCR1 register
Transfer
Output
S
controller
R (RS-FF)
CCR1 buffer register
Match signal
Internal count clock
EVTT0 pin
(external event
count input)
Edge
detectorNote
INTTT0CC1 signal
Clear
Count
clock
selection
16-bit counter
Output
controller
Match signal
TT0CE bit
TOT01 pin
TOT00 pin
INTTT0CC0 signal
CCR0 buffer register
Transfer
TT0CCR0 register
Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Figure 9-44. Basic Timing in Triangular-Wave PWM Output Mode
FFFFH
D02
D00
D01
16-bit counter
D10
D11
D10
D12
D12
D11
0000H
TT0CE bit
TT0CCR0 register
D00
CCR0 buffer register
D01
D02
D00
D01
D02
INTTT0CC0 signal
TOT00 pin output
TT0CCR1 register
CCR1 buffer register
D10
D11
D10
D12
D11
D12
INTTT0CC1 signal
TOT01 pin output
INTTT0OV signal
The 16-bit counter is cleared from FFFFH and 0000H and starts counting when the TT0CE bit is set to 1. The triangular
PWM waveform is output from the TOT01 pin.
In the triangular-wave PWM output mode, the counter counts up or down. When the 16-bit counter reaches 0000H
while it is counting down, an overflow interrupt request signal (INTTT0OV) is generated.
At this time, the
TT0OPT0.TT0OVF bit is not set to 1. If the count value of the 16-bit counter matches the value of the CCR0 buffer register
while the counter is counting up, a compare match interrupt request signal (INTTT0CC0) is generated.
The counting direction is changed from up to down when the value of the 16-bit counter matches that of the CCR0
buffer register, and from down to up when the counter is cleared to 0000H.
The PWM waveform can be changed by rewriting the TT0CCRn register during operation. To change the PWM
waveform during operation, write the TT0CCR1 register last.
The cycle of the triangular PWM waveform is set by the TT0CCR0 register and its duty factor is set by the TT0CCR1
register. Set a value to the TT0CCR0 register in a range of “0 ≤ TT0CCR0 ≤ FFFEH”. The rewritten value is reflected
when the 16-bit counter reaches 0000H while it is counting down.
Even when changing only the cycle of the PWM waveform, first set a period to the TT0CCR0 register, and then write
the same value (value same as that set to the TT0CCR1 register) to the TT0CCR1 register.
To transfer data from the TT0CCRn register to the CCRn buffer register, the data must be written to the TT0CCR1
register (n = 0, 1).
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Encoder count function
The encoder count function includes an encoder compare mode (see 9.6.10 Encoder compare mode (TT0MD3 to
TT0MD0 bits = 1000)).
Mode
Encoder compare mode
TT0CCR0 Register
Compare only
TT0CCR1 Register
Compare only
(1) Count-up/-down control
Counting up or down by the 16-bit counter is controlled by the phase of input encoder signals (TENC00 and
TENC01) and settings of the TT0CTL2.TT0UDS1 and TT0CTL2.TT0UDS0 bits.
When the encoder count function is used, the internal count clock and external event count input (EVTT0) cannot
be used. Set the TT0CTL0.TT0CKS2 to TT0CTL0.TT0CKS0 bits to 000 and the TT0CTL1.TT0EEE bit to 0.
(2) Setting initial value of 16-bit counter
The initial count value set to the TT0TCW register when the TT0CTL2.TT0ECC bit = 0 is transferred to the 16-bit
counter immediately after the counter starts its operation (TT0CTL0.TT0CE bit = 0 → 1), and the counter starts the
operation after it detects the valid edge of the encoder input signal (TENC00 or TENC01).
(3) Basic operation
The TT0CCRn register generates a compare match interrupt request signal (INTTT0CCn) when the count value of
the 16-bit counter matches the value of the CCRn buffer register.
(4) Clear operation
The 16-bit counter is cleared when the following conditions are satisfied in the encoder compare mode.
• When the value of the 16-bit counter matches the value of the compare register (the TT0CTL2.TT0ECM1 and
TT0CTL2.TT0ECM0 bits are set)
• When the edge of the encoder clear input signal (TECR0) is detected (the TT0ECS1 and TT0ECS0 bits are set
when the TT0IOC3.TT0SCE bit = 0)
• When the clear level condition of the TENC00, TENC01, and TECR0 pins is detected (the TT0ZCL, TT0BCL, and
TT0ACL bits are set when the TT0SCE bit = 1)
Remark
n = 0, 1
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(5) Controlling bits of TT0CTL2 register
The setting of the TT0CTL2 register in the encoder compare mode is shown below.
Table 9-8. Setting of TT0CTL2 Register
Mode
TT0UDS1,
TT0ECM1 Bit
TT0ECM0 Bit
TT0LDE Bit
Counter Clear
Transfer to
TT0UDS0 Bits
()
()
()
(Target Compare
Counter
()
Encoder compare
mode
Can be set to 00,
Register)
0
0
−
0
01, 10, or 11.
1
0
1
Possible
TT0CCR0
1
1
−
−
Possible
0
Invalid
TT0CCR1
−
1
Invalid
TT0CCR0,
−
Note
TT0CCR1
Note The counter can operate in a range from 0000H to the set value of the TT0CCR0 register.
(a) Outline of each bit
The TT0UDS1 and TT0UDS0 bits identify the counting direction (up or down) of the 16-bit counter by the
phase input from the encoder input pin (TENC00 or TENC01).
The TT0ECM1 and TT0ECM0 bits control clearing of the 16-bit counter when its count value matches the
value of the CCR0 or CCR1 buffer register.
The TT0LDE bit controls a function to transfer the set value of the TT0CCR0 register to the 16-bit counter
when the counter underflows. The TT0LDE bit is valid only when the TT0ECM1 and TT0ECM0 bits are 00
and 01, respectively. It is invalid when these bits are set to any other values.
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(b) Detailed explanation of each bit
TT0UDS1 and TT0UDS0 bits: Count-up/-down selection
Whether the 16-bit counter is counting up or down is identified by the phase input from the TENC00 or
TENC01 pin and depending on the settings of the TT0UDS1 and TT0UDS0 bits. These bits are valid
only in the encoder compare mode.
• When TT0UDS1 and TT0UDS0 bits = 00
TENC00 Pin
Rising edge
TENC01 Pin
Count Operation
High level
Count down
Low level
Count up
Falling edge
Both edges
Rising edge
Falling edge
Both edges
Remark
Detecting the edge of the TENC00 pin is specified by the TT0IOC3.TT0EIS1 and TT0EIS0
bits.
Figure 9-45. Operation Example (When Valid Edge of TENC00 Pin Is Specified to Be Rising Edge
and No Edge Is Specified as Valid Edge of TENC01 Pin)
TENC00
TENC01
16-bit counter
0007H
0006H
0005H
Count down
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0004H
0005H
0006H
0007H
Count up
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• When TT0UDS1 and TT0UDS0 bits = 01
TENC00 Pin
Low level
TENC01 Pin
Count Operation
Count down
Rising edge
Falling edge
Both edges
High level
Rising edge
Falling edge
Both edges
Rising edge
High level
Count up
Falling edge
Both edges
Rising edge
Low level
Falling edge
Both edges
Counter does not perform count
Simultaneous input to TENC00 and TENC01 pins
operation but holds value immediately
before.
Remark
Detecting the edges of the TENC00 and TENC01 pins is specified by the
TT0IOC3.TT0EIS1 and TT0IOC3.TT0EIS0 bits.
Figure 9-46. Operation Example (When Rising Edge Is Specified as Valid Edges of TENC00 and TENC01 Pins)
TENC00
TENC01
16-bit counter
0006H
0007H
Count up
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0008H
Value held
0007H
0006H
0005H
Count down
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• When TT0UDS1 and TT0UDS0 bits = 10
TENC00 Pin
Low level
TENC01 Pin
Falling edge
Count Operation
Counter does not perform count
operation but holds value immediately
before.
Rising edge
Low level
Count down
High level
Rising edge
Counter does not perform count
Falling edge
High level
operation but holds value immediately
before.
Rising edge
High level
Falling edge
Falling edge
Low level
Count up
Low level
Rising edge
Counter does not perform count
operation but holds value immediately
Rising edge
before.
Falling edge
Rising edge
Falling edge
Count down
Falling edge
Caution
Count up
Specification of the valid edges of the TENC00 and TENC01 pins is invalid.
Figure 9-47. Operation Example (Count Operation When Valid Edges of TENC00 and TENC01 Pins do not Overlap)
TENC00
TENC01
16-bit counter
0007H
0006H 0005H 0006H 0005H 0006H 0005H 0006H
Count down
Count Count Count Count
up down up down
0007H
Count up
Figure 9-48. Operation Example (Count Operation When Valid Edges of TENC00 and TENC01 Pins Overlap)
TENC00
TENC01
16-bit counter
0007H
Count down
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0006H
Value held
0005H 0006H
Count
down
0007H
Count up
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• When TT0UDS1 and TT0UDS0 bits = 11
TENC00 Pin
TENC01 Pin
Low level
Falling edge
Rising edge
Low level
High level
Rising edge
Falling edge
High level
Count Operation
Count down
Rising edge
Count up
High level
Falling edge
Falling edge
Low level
Low level
Rising edge
Counter does not perform count
Simultaneous input to TENC00 and TENC01 pins
operation but holds value immediately
before.
Caution
Specification of the valid edges of the TENC00 and TENC01 pins is invalid.
Figure 9-49. Operation Example (Count Operation When Valid Edges of TENC00 and TENC01 Pins do not Overlap)
TENC00
TENC01
16-bit counter
0003H 0004H 0005H 0006H 0007H 0008H 0009H
000AH
Count up
0009H 0008H 0007H 0006H 0005H
Count down
Figure 9-50. Operation Example (Count Operation When Valid Edges of TENC00 and TENC01 Pins Overlap)
TENC00
TENC01
16-bit counter
0003H 0004H
Count up
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0005H
Value
held
0006H 0007H
0008H
Count up
0007H 0006H
Count down
0005H
0006H
Value Count
held
up
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
TT0ECM1 and TT0ECM0 bits: Timer/counter clear function upon match of the compare register
The 16-bit counter performs its count operation in accordance with the set value of the TT0ECM1 and
TT0ECM0 bits when the count value of the counter matches the value of the CCRn buffer register.
• When TT0ECM1 and TT0ECM0 bits = 00
The 16-bit counter is not cleared when its count value matches the value of the CCRn buffer register.
• When TT0ECM1 and TT0ECM0 bits = 01
The 16-bit counter performs a count operation under the following condition when its count value
matches the value of the CCR0 buffer register.
Next Count Operation
Description
Count up
16-bit counter is cleared to 0000H.
Count down
Count value of 16-bit counter is counted down.
• When TT0ECM1 and TT0ECM0 bits = 10
The 16-bit counter performs a count operation under the following condition when its count value
matches the value of the CCR1 buffer register.
Next Count Operation
Description
Count up
Count value of 16-bit counter is counted up.
Count down
16-bit counter is cleared to 0000H.
• When TT0ECM1 and TT0ECM0 bits = 11
The 16-bit counter performs a count operation under the following condition when its count value
matches the value of the CCR0 buffer register.
Next Count Operation
Description
Count up
16-bit counter is cleared to 0000H.
Count down
Count value of 16-bit counter is counted down.
The 16-bit counter performs a count operation under the following condition when its count value
matches the value of the CCR1 buffer register.
Next Count Operation
Description
Count up
Count value of 16-bit counter is counted up.
Count down
16-bit counter is cleared to 0000H.
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TT0LDE bit: Transfer function of the set value of the TT0CCR0 register to the 16-bit counter when the
counter underflows
When the TT0LDE bit = 1, the set value of the TT0CCR0 register can be transferred to the 16-bit counter
when the counter underflows.
The TT0LDE bit is valid only in the encoder compare mode.
• Count operation in range from 0000H to set value of the TT0CCR0 register
If the 16-bit counter performs a count operation when the TT0LDE bit = 1 and TT0ECM1 and TT0ECM0
bits = 01, and when the count value of the counter matches the set value of the CCR0 buffer register
when the TT0ECM0 bit = 1, the 16-bit counter is cleared to 0000H if the next count operation is
counting up.
If the 16-bit counter underflows when the TT0LDE bit = 1, the set value of the TT0CCR0 register is
transferred to the counter.
Therefore, the counter can operate in a range from 0000H to the set value of the TT0CCR0 register in
which the upper-limit count value is the set value of the TT0CCR0 register and the lower-limit value is
0000H.
Figure 9-51. Operation Example (Count Operation in Range from 0000H to Set Value of TT0CCR0 Register)
Count value of 16-bit counter
matches value of CCR0 buffer register.
Set value of TT0CCR0 register
is transferred to 16-bit counter.
Set value of TT0CCR0 register (N)
16-bit counter
0000H
16-bit counter is
cleared to 0000H.
Count up
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16-bit counter
underflows.
Count down
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Figure 9-52. Operation Timing (Count Operation in Range from 0000H to Set Value of TT0CCR0 Register)
Peripheral clock
Count
timing signal
TT0ESF bit
H = down counting
0002H
TT0CNT register
0001H
0000H
N
N−1
N
TT0CCR0 register
INTTT0CC0 signal
TT0EOF bit
L
TT0EUF bit
INTTT0OV signal
Remark
TT0ESF bit: Bit 0 of TMT0 option register 1 (TT0OPT1)
TT0EOF bit: Bit 1 of TMT0 option register 1 (TT0OPT1)
TT0EUF bit: Bit 2 of TMT0 option register 1 (TT0OPT1)
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(6) Function to clear counter to 0000H by encoder clear signal (TECR0 pin)
The 16-bit counter can be cleared to 0000H by the input signal of the TECR0 pin in two ways which are selected by
the TT0IOC3.TT0SCE bit.
The TT0SCE bit also controls, depending on its setting, the TT0IOC3.TT0ZCL,
TT0IOC3.TT0BCL, TT0IOC3.TT0ACL, TT0IOC3.TT0ESC1, and TT0IOC3.TT0ECS0 bits.
The counter can be cleared by the methods described below only in the encoder compare mode.
Table 9-9. Relationship Between TT0SCE Bit and TT0ZCL, TT0BCL, TT0ACL, TT0ECS1, and TT0ECS0 Bits
Clearing Method
TT0SCE Bit
TT0ZCL Bit
TT0BCL Bit
TT0ACL Bit
TT0ECS1, TT0ECS0 Bits
0
Invalid
Invalid
Invalid
Valid
1
Valid
Valid
Valid
Invalid
(a) Clearing method : By detecting edge of encoder clear signal (TECR0 pin) (TT0SCE bit = 0)
When the TT0SCE bit = 0, the 16-bit counter is cleared to 0000H in synchronization with the peripheral clock if
the valid edge of the TECR0 pin specified by the TT0ECS1 and TT0ECS0 bits is detected. At this time, an
encoder clear interrupt request signal (INTTT0EC) is generated. When the TT0SCE bit = 0, the settings of the
TT0ZCL, TT0BCL, and TT0ACL bits is invalid.
Figure 9-53. Operation Example (When TT0SCE Bit = 0, TT0ECS1 and TT0ECS0 Bits = 01, and TT0UDS1 and
TT0UDS0 Bits = 11)
Encoder input
(TENC00 pin input)
Encoder input
(TENC01 pin input)
Encoder clear input
(TECR0 pin input)
Peripheral clock
TT0CNT register
N
N+1
0000H
0001H
0002H
Count
timing signal
INTTT0EC
interrupt
Counter clear
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(b) Clearing method : By detecting clear level condition of the TENC00, TENC01, and TECR0 pins
(TT0SCE bit = 1)
When the TT0SCE bit = 1, the 16-bit counter is cleared to 0000H if the clear level condition of the TECR0,
TENC00, or TENC01 pin specified by the TT0ZCL, TT0BCL, and TT0ACL bits is detected. At this time, the
encoder clear interrupt request signal (INTTT0EC) is not generated.
The settings of the TT0ECS1 and
TT0ECS0 bits is invalid when the TT0SCE bit = 1.
Table 9-10. 16-bit Counter Clearing Condition When TT0SCE Bit = 1
Clear Level Condition Setting
Input Level of Encoder Pin
TT0ZCL Bit
TT0BCL Bit
TT0ACL Bit
TECR0 Pin
TENC01 Pin
TENC00 Pin
0
0
0
L
L
L
0
0
1
L
L
H
Caution
0
1
0
L
H
L
0
1
1
L
H
H
1
0
0
H
L
L
1
0
1
H
L
H
1
1
0
H
H
L
1
1
1
H
H
H
The 16-bit counter is cleared to 0000H when the clear level condition of the TT0ZCL, TT0BCL, and
TT0ACL bits match the input level of the TECR0, TENC01, or TENC00 pin.
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Figure 9-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and
TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (1/3)
(i) If inputting the high level to the TECR0 pin lags behind inputting the low level to the TENC01 pin
while the counter is counting up, the counter is cleared after it counts up.
Encoder input
(TENC00 pin input)
H
Encoder input
(TENC01 pin input)
L
Encoder clear input
(TECR0 pin input)
H
Peripheral clock
Clear signal
N
TT0CNT register
N+1
0000H
Count timing
signal
N + 1 (when TT0CCR0 register is set to N + 1)
TT0CCR0 register
INTTT0CC0 signal
Compare match interrupt request signal is not generated.
TT0CCR1 register
0000H (when TT0CCR1 register is set to 0000H)
INTTT0CC1 signal
TT0CCR0 register
N (when TT0CCR0 register is set to N)
INTTT0CC0 signal
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Figure 9-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and
TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (2/3)
(ii) If the high level is input to the TECR0 pin at the same time as the low level is input to the TECN01 pin
while the counter is counting up, the counter is cleared without counting up.
Encoder input
(TENC00 pin input)
H
Encoder input
(TENC01 pin input)
L
Encoder clear input
(TECR0 pin input)
H
Peripheral clock
Clear signal
TT0CNT register
N
0000H
Count
timing signal
(iii) If the high level is input to the TECR0 pin earlier than the low level is input to the TENC01 pin while
the counter is counting up, the counter is cleared without counting up.
Encoder input
(TENC00 pin input)
H
Encoder input
(TENC01 pin input)
L
Encoder clear input
(TECR0 pin input)
H
Peripheral clock
Clear signal
TT0CNT register
N
0000H
Count
timing signal
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Figure 9-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and
TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (3/3)
(iv) If the high level is input to the TECR0 pin later than the low level is input to the TENC01 pin while the
counter is counting up, the counter is cleared after it counts up.
Encoder input
(TENC00 pin input)
H
Encoder input
(TENC01 pin input)
L
Encoder clear input
(TECR0 pin input)
H
Peripheral clock
Clear signal
N
TT0CNT register
N−1
0000H
Count
timing signal
N − 1 (when TT0CCR0 register is set to N − 1)
TT0CCR0 register
INTTT0CC0 signal
Compare match interrupt request signal is not generated.
TT0CCR1 register
0000H (when TT0CCR1 register is set to 0000H)
INTTT0CC1 signal
TT0CCR0 register
N (when TT0CCR0 register is set to N)
INTTT0CC0 signal
If the counter is cleared in this way, a miscount does not occur even if inputting the signal to the TECR0 pin is
late, because the clear level condition of the TECR0, TENC01, and TENC00 pins is set and the 16-bit counter
is cleared to 0000H when the clear level condition is detected.
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(7) Notes on using encoder count function
(a) If compare match interrupt is not generated immediately after operation is started
If a value which is the same as that of the TT0TCW register is set to the TT0CCR0 or TT0CCR1 register and
the counter operation is started when the TT0CTL2.TT0ECC bit = 0, and if the count value (TT0TCW) of the
16-bit counter matches the value of the CCRn buffer register immediately after the start of the operation, the
match is masked and the compare match interrupt request signal (INTTT0CCn) is not generated (n = 0, 1). In
addition, the 16-bit counter is not cleared to 0000H by setting the TT0CTL2.TT0ECM1 and
TT0CTL2.TT0ECM0 bits.
Count clock
TT0CE bit
Peripheral clock
Count
timing signal
Count
up/down signal
H = Count down
TT0CNT register
TT0CCR1 register
INTTT0CC1 signal
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FFFFH
16-bit counter is not cleared.
TT0TCW
TT0TCW − 1
TT0TCW
Match does not occur.
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(b) If overflow does not occur immediately after start of operation
If the count operation is resumed when the TT0CTL2.TT0ECC bit = 1, the 16-bit counter does not overflow if its
count value that has been held is FFFFH and if the next count operation is counting up.
After the counter starts operating and counts up from a count value (value of TT0TCW register = FFFFH), the
counter overflows from FFFFH to 0000H. However, detection of the overflow is masked, the overflow flag
(TT0EOF) is not set, and the overflow interrupt request signal (INTTT0OV) is not generated.
Count clock
TT0CE bit
Peripheral clock
Count
timing signal
Count
up/down signal
L = Count up
TT0ECC bit H
TT0CNT register
TT0TCW register
INTTT0OV signal
Hold
FFFFH
TT0TCW = FFFFH
0000H
FFFFH
Overflow does
not occur.
TT0EOF bit
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9.6.10 Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000)
In the encoder compare mode, the encoder is controlled by using both the TT0CCR0 and TT0CCR1 registers as
compare registers and the input pins for encoder count function (TENC00, TENC01, and TECR0).
In this mode, the 16-bit counter can be cleared to 0000H in three ways: when the count value of the counter matches
the value of the CCRn buffer register (compare match interrupt request signal (INTTT0CCn) is generated), when the edge
of the encoder clear input (TECR0 pin) is detected, and when the clear level condition of TENC00, TENC01, and TECR0
pins is detected.
When the 16-bit counter underflows, the set value of the TT0CCR0 register can be transferred to the counter.
(1) Encoder compare mode operation flow
Figure 9-55. Encoder Compare Mode Operation Flow
START
Register initial setting
TT0CTL1 register
(TT0MD3 to TT0MD0 bits),
TT0CTL2 register
(TT0LDE, TT0ECM1, TT0ECM0,
TT0UDS1, TT0UDS0 bits),
TT0IOC3 register
(TT0SCE, TT0ZCL, TT0ACL,
TT0BCL, TT0ECS1, TT0ECS0,
TT0EIS1, TT0EIS0 bits),
TT0CCR0, TT0CCR1 registers,
TT0TCW register
TT0CE bit = 1
Encoder compare mode operation processing
Operation end?
: See Figure 9-56 Encoder Compare Mode Operation Processing.
No
Yes
TT0CE bit = 0
END
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Figure 9-56. Encoder Compare Mode Operation Processing
A
Valid edge of TENC00,
TENC01 detected?
No
Yes
Count down
Which count operation?
Count up
TT0ECM0 = 1?
(TT0CTL2)
No
Yes
Count value matches
CCR0 register value?
TT0ECM1 = 1?
(TT0CTL2)
No
Yes
No
Yes
Count value matches
CCR1 register value?
No
Yes
16-bit counter cleared
and started.
INTTT0CC0 signal generated.
16-bit counter cleared
and started.
INTTT0CC1 signal generated.
TT0LDE = 1?
(TT0CTL2)
No
Yes
Underflow?
No
Yes
TT0CCR0 set value
transferred to 16-bit counter.
INTTT0CC0 signal generated.
TT0SCE = 1?
(TT0IOC3)
No
Yes
Clear level condition of
TENC00, TENC01, and TECR0
pins detected?
Yes
16-bit counter cleared
and started.
No
TECR0 edge detected?
No
Yes
16-bit counter cleared
and started.
INTTIEC0 signal generated.
A
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(2) Encoder compare mode operation timing
(a) Basic timing 1
[Register setting conditions]
• TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 01
The 16-bit counter is cleared to 0000H when its count value matches the value of the CCR0 buffer register.
• TT0CTL2.TT0LDE bit = 1
The set value of the TT0CCR0 register is transferred to the 16-bit counter when it overflows.
• TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT0ECS1 and TT0IOC3.TT0ECS0 bits = 00
Specification of clearing the 16-bit counter when the edge of the encoder clear input signal (TECR0 pin) is
detected (no edge specified)
FFFFH
CM01
TT0CNT register
CM12
CM00
CM00
CM02
CM03 CM03
Clear
Transfer
CM11
Clear
0000H
TT0CCR0 register
CCR0 buffer register
CM00
CM01
CM00
CM01
Clear
CM02
CM03
CM02
CM03
INTTT0CC0 signal
TT0CCR1 register
CCR1 buffer register
CM10
CM10
CM11
CM11
CM12
CM12
INTTT0CC1 signal
TT0ESF bit
INTTT0OV signal
TT0EOF bit L
TT0EUF bit
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When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is
transferred to the counter and the 16-bit counter starts operating.
When the count value of the counter matches the value of the CCR0 buffer register, the compare match
interrupt request signal (INTTT0CC0) is generated. Because the TT0ECM0 bit = 1, the 16-bit counter is
cleared to 0000H if the next count operation is counting up.
When the count value of the 16-bit counter matches the value of the CCR1 buffer register, the compare match
interrupt request signal (INTTT0CC1) is generated. Because the TT0ECM1 bit = 0, the 16-bit counter is not
cleared to 0000H when its value matches that of the CCR1 buffer register.
When the TT0LDE bit = 1 and TT0ECM0 bit = 1, the counter can operate in a range from 0000H to the set
value of the TT0CCR0 register.
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(b) Basic timing 2
[Register setting condition]
• TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 00
The 16-bit counter is not cleared even when its count value matches the value of the CCRn buffer register (a
= 0, 1).
• TT0CTL2.TT0LDE bit = 0
The set value of the TT0CCR0 register is not transferred to the 16-bit counter after the counter underflows.
• TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT0ECS1 and TT0IOC3.TT0ECS0 bits = 00
Specification of clearing the 16-bit counter when the edge of the encoder clear input signal (TECR0 pin) is
detected (no edge specified)
Underflow
FFFFH
Overflow
CM10
CM02
CM12
TT0CNT register
CM01
CM00
CM00
CM01
CM11
0000H
TT0CCR0 register
CCR0 buffer register
CM00
CM01
CM00
CM02
CM01
CM02
INTTT0CC0 signal
TT0CCR1 register
CCR1 buffer register
CM10
CM10
CM11
CM11
CM12
CM12
INTTT0CC1 signal
TT0ESF bit
INTTT0OV signal
TT0EOF bit
TT0EUF bit
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When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is
transferred to the 16-bit counter and the counter starts operating.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match
interrupt request signal (INTTT0CC0) is generated.
When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match
interrupt request signal (INTTT0CC1) is generated.
The 16-bit counter is not cleared to 0000H even when its count value matches the value of the CCRn buffer
register because the TT0ECM1 and TT0ECM0 bits = 00 (n = 0, 1).
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(c) Basic timing 3
[Register setting condition]
• TT0CTL2.TT0ECM1 and TT0CTL2.TT0ECM0 bits = 11
The count value of the 16-bit counter is cleared to 0000H when its value matches the value of the CCR0
buffer register.
The count value of the 16-bit counter is cleared to 0000H when its value matches the value of the CCR1
buffer register.
• Setting of the TT0CTL2.TT0LDE bit is invalid.
• TT0IOC3.TT0SCE bit = 0, and TT0IOC3.TT0ECS1 and TT0IOC3.TT0ECS0 bits = 00
Specification of clearing the 16-bit counter when the edge of the encoder clear input signal (TECR0 pin) is
detected (no edge specified)
Underflow
FFFFH
Underflow
Overflow
Underflow
CM01
CM01
CM02
TT0CNT register
CM11
CM00
CM10
Clear
Clear
Clear
CM12
Clear
0000H
TT0CCR0 register
CCR0 buffer register
CM12
CM00
CM01
CM00
CM02
CM01
CM02
INTTT0CC0 signal
TT0CCR1 register
CCR1 buffer register
CM10
CM10
CM11
CM11
CM12
CM12
INTTT0CC1 signal
TT0ESF bit
INTTT0OV signal
TT0EOF bit
TT0EUF bit
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CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
When the 16-bit counter starts operating (TT0CE bit = 0 → 1), the set value of the TT0TCW register is
transferred to the 16-bit counter and the counter starts operating.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match
interrupt request signal (INTTT0CC0) is generated. At this time, the 16-bit counter is cleared to 0000H if the
next count operation is counting up.
When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match
interrupt request signal (INTTT0CC1) is generated. At this time, the 16-bit counter is cleared to 0000H if the
next count operation is counting down.
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CHAPTER 10 16-BIT INTERVAL TIMER M (TMM)
CHAPTER 10 16-BIT INTERVAL TIMER M (TMM)
The V850ES/JG3-H and V850ES/JH3-H have four TMM channels (TMMn).
10.1 Overview
TMMn has the following features.
• Interval function
• 8 clocks selectable
• 16-bit counter × 1
(The 16-bit counter cannot be read during timer count operation.)
• Compare register × 1
(The compare register cannot be written during timer counter operation.)
• Compare match interrupt × 1
TMMn supports only the clear & start mode. The free-running timer mode is not supported.
Remark
n = 0 to 3
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10.2 Configuration
TMMn includes the following hardware.
Table 10-1. Configuration of TMMn
Item
Configuration
Timer register
16-bit counter
Register
TMMn compare register 0 (TMnCMP0)
Control register
TMMn control register 0 (TMnCTL0)
Figure 10-1. Block Diagram of TMMn
Internal bus
TMnCTL0
TMnCE TMnCKS2 TMnCKS1TMnCKS0
TMnCMP0
Match
Selector
Note
fXX/2
fXX/4
fXX/8
fXX/16
fXX/64
fXX/256
fXX/512
fXX/1024
Controller
16-bit counter
INTTMnEQ0
Clear
Note In TMM0, fXX, fXX/2, fXX/4, fXX/64, fXX/512, fXX/1024, fR, fXT
Remark
fXX:
Main clock frequency
fR:
Internal oscillation clock frequency
fXT:
Subclock frequency
n = 0 to 3
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(1) 16-bit counter
This is a 16-bit counter that counts the internal clock.
The 16-bit counter cannot be read or written.
(2) TMMn compare register 0 (TMnCMP0)
The TMnCMP0 register is a 16-bit compare register.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Software can be used to always write the same value to the TMnCMP0 register.
Rewriting the TMnCMP0 register is prohibited when the TMnCTL0.TMnCE bit = 1.
After reset: 0000H
R/W
Address: TM0CMP0 FFFFFA84H, TM1CMP0 FFFFFA94H,
TM2CMP0 FFFFFAA4H, TM3CMP0 FFFFFAB4H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TMnCMP0
(n = 0 to 3)
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10.3 Registers
(1) TMMn control register (TMnCTL0)
The TMnCTL0 register is an 8-bit register that controls the TMMn operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Software can be used to always write the same value to the TMnCTL0 register.
Remark
n = 0 to 3
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CHAPTER 10 16-BIT INTERVAL TIMER M (TMM)
After reset: 00H
R/W
Address: TM0CTL0 FFFFFA80H, TM1CTL0 FFFFFA90H,
TM2CTL0 FFFFFAA0H, TM3CTL0 FFFFFAB0H
6
TMnCTL0
TMnCE
5
0
4
0
3
0
2
0
1
0
TMnCKS2 TMnCKS1 TMnCKS0
(n = 0 to 3)
TMnCE
Internal clock operation enable/disable specification
0
TMMn operation disabled (16-bit counter reset asynchronously).
Operation clock application stopped.
1
TMMn operation enabled. Operation clock application started. TMMn
operation started.
Internal clock control and internal circuit reset for TMMn are performed asynchronously
using the TMnCE bit. When the TMnCE bit is cleared to 0, the internal clock of TMMn
is disabled (fixed to low level) and 16-bit counter is reset asynchronously.
(m = 0)
TMmCKS2 TMmCKS1 TMmCKS0
Count clock selection
fXX = 48 MHz fXX = 32 MHz fXX = 24 MHz
0
0
0
fXX
20.8 ns
31.3 ns
41.7 ns
0
0
1
fXX/2
41.7 ns
62.5 ns
83.3 ns
0
1
0
fXX/4
83.3 ns
125 ns
167 ns
0
1
1
fXX/64
1.33 μ s
2.00 μ s
2.67 μ s
1
0
0
fXX/512
10.7 μ s
16.0 μ s
21.3 μ s
1
0
1
fXX/1024
21.3 μ s
32.0 μ s
42.7 μ s
1
1
0
fR/8
36.4 μ s
36.4 μ s
36.4 μ s
1
1
1
fXT
30.5 μ s
30.5 μ s
30.5 μ s
(m = 1 to 3)
TMmCKS2 TMmCKS1 TMmCKS0
Count clock selection
fXX = 48 MHz fXX = 32 MHz fXX = 24 MHz
0
0
0
fXX/2
41.7 ns
62.5 ns
83.3 ns
0
0
1
fXX/4
83.3 ns
125 ns
167 ns
0
1
0
fXX/8
167 ns
250 ns
333 ns
0
1
1
fXX/16
333 ns
500 ns
667 ns
1
0
0
fXX/64
1.33 μ s
2.00 μ s
2.67 μ s
1
0
1
fXX/256
5.33 μ s
8.00 μ s
10.7 μ s
1
1
0
fXX/512
10.7 μ s
16.0 μ s
21.3 μ s
1
1
1
fXX/1024
21.3 μ s
32.0 μ s
42.7 μ s
Cautions 1. Set the TMnCKS2 to TMnCKS0 bits when the TMnCE bit = 0.
When changing the value of TMnCE from 0 to 1, it is not possible to set
the value of the TMnCKS2 to TMnCKS0 bits simultaneously.
2. Be sure to clear bits 3 to 6 to “0”.
Remark
fXX: Main clock frequency
fR: Internal oscillation clock frequency
fXT: Subclock frequency
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CHAPTER 10 16-BIT INTERVAL TIMER M (TMM)
10.4 Operation
Caution
Do not set the TMnCMP0 register to FFFFH.
10.4.1 Interval timer mode
In the interval timer mode, an interrupt request signal (INTTMnEQ0) is generated at the specified interval if the
TMnCTL0.TMnCE bit is set to 1.
Figure 10-2. Configuration of Interval Timer
Clear
Count clock
selection
INTTMnEQ0 signal
16-bit counter
Match signal
TMnCE bit
Remark
TMnCMP0 register
n = 0 to 3
Figure 10-3. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
D
D
D
D
0000H
TMnCE bit
TMnCMP0 register
D
INTTMnEQ0 signal
Interval (D + 1)
Remark
Interval (D + 1)
Interval (D + 1)
Interval (D + 1)
n = 0 to 3
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CHAPTER 10 16-BIT INTERVAL TIMER M (TMM)
When the TMnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with
the count clock, and the counter starts counting.
When the count value of the 16-bit counter matches the value of the TMnCMP0 register, the 16-bit counter is cleared to
0000H and a compare match interrupt request signal (INTTMnEQ0) is generated.
The interval can be calculated by the following expression.
Interval = (Set value of TMnCMP0 register + 1) × Count clock cycle
Figure 10-4. Register Setting for Interval Timer Mode Operation
(a) TMMn control register 0 (TMnCTL0)
TMnCE
TMnCTL0
0/1
TMnCKS2 TMnCKS1 TMnCKS0
0
0
0
0
0/1
0/1
0/1
Select count clock
0: Stop counting
1: Enable counting
(b) TMMn compare register 0 (TMnCMP0)
If the TMnCMP0 register is set to D, the interval is as follows.
Interval = (D + 1) × Count clock cycle
Remark
n = 0 to 3
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CHAPTER 10 16-BIT INTERVAL TIMER M (TMM)
(1) Interval timer mode operation flow
Figure 10-5. Software Processing Flow in Interval Timer Mode
FFFFH
D
16-bit counter
D
D
0000H
TMnCE bit
TMnCMP0 register
D
INTTMnEQ0 signal
Count operation start flow
START
Register initial setting
TMnCTL0 register
(TMnCKS0 to TMnCKS2 bits)
TMnCMP0 register
TMnCE bit = 1
The initial setting of these registers is performed
before setting the TMnCE bit to 1.
The TMnCKS0 to TMnCKS2 bits cannot be set
at the same time when counting has been started
(TMnCE bit = 1).
Count operation stop flow
TMnCE bit = 0
The counter is initialized and counting is
stopped by clearing the TMnCE bit to 0.
STOP
Remark
n = 0 to 3
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(2) Interval timer mode operation timing
Caution
Do not set the TMnCMP0 register to FFFFH.
(a) Operation if TMnCMP0 register is set to 0000H
If the TMnCMP0 register is set to 0000H, the INTTMnEQ0 signal is generated at each count clock.
The value of the 16-bit counter is always 0000H.
Count clock
16-bit counter
FFFFH
0000H
0000H
0000H
0000H
TMnCE bit
TMnCMP0 register
0000H
INTTMnEQ0 signal
Interval time
Count clock cycle
Remark
Interval time
Count clock cycle
n = 0 to 3
(b) Operation if TMnCMP0 register is set to N
If the TMnCMP0 register is set to N, the 16-bit counter counts up to N. The counter is cleared to 0000H in
synchronization with the next count-up timing and the INTTMnEQ0 signal is generated.
FFFFH
N
16-bit counter
0000H
TMnCE bit
TMnCMP0 register
N
INTTMnEQ0 signal
Interval time
(N + 1) ×
count clock cycle
Remark
Interval time
(N + 1) ×
count clock cycle
Interval time
(N + 1) ×
count clock cycle
n = 0 to 3
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10.4.2 Cautions
(1) It takes the 16-bit counter up to the following time to start counting after the TMnCTL0.TMnCE bit is set to 1,
depending on the count clock selected.
(n = 0)
Selected Count Clock
Maximum Time Before Counting Start
fXX
2/fXX
fXX/2
3/fXX
fXX/4
6/fXX
fXX/64
128/fXX
fXX/512
1024/fXX
fXX/1024
2048/fXX
fR/8
16/fR
fXT
2/fXT
(n = 1 to 3)
Selected Count Clock
Maximum Time Before Counting Start
fXX/2
4/fXX
fXX/4
6/fXX
fXX/8
12/fXX
fXX16
32/fXX
fXX/64
128/fXX
fXX/256
512/fXX
fXX/512
1024/fXX
fXX/1024
2048/fXX
(2) Rewriting the TMnCMP0 and TMnCTL0 registers is prohibited while TMMn is operating.
If these registers are rewritten while the TMnCE bit is 1, the operation cannot be guaranteed.
If they are rewritten by mistake, clear the TMnCTL0.TMnCE bit to 0, and re-set the registers.
Remark
n = 0 to 3
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CHAPTER 11 MOTOR CONTROL FUNCTION
CHAPTER 11 MOTOR CONTROL FUNCTION
11.1 Functional Overview
Timer AB1 (TAB1) and the TMQ0 option (TMQOP0) can be used as an inverter function that controls a motor. It
performs a tuning operation with timer AA4 (TAA4) and A/D conversion of the A/D converter can be started when the value
of TAB1 matches the value of TAA4. The following operations can be performed as motor control functions.
• 6-phase PWM output function with 16-bit accuracy
• Timer tuning operation function (tunable with TAA4)
• Cycle setting function (cycle can be changed during operation of crest or valley interrupt)
• Compare register rewriting: Anytime rewrite, batch rewrite, or intermittent rewrite (selectable during TAB1 operation)
• Interrupt and transfer culling functions
• Dead-time setting function
• A/D trigger timing function of the A/D converter
• 0% output and 100% output available
• 0% output and 100% output selectable by crest interrupt and valley interrupt
• Forcible output stop function
• When valid edge detected by external pin input (TOAB1OFF, TOAA1OFF)
• When main clock oscillation stop detected by clock monitor function
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CHAPTER 11 MOTOR CONTROL FUNCTION
11.2 Configuration
The motor control function consists of the following hardware.
Item
Configuration
Timer register
Dead-time counters
Compare register
TAB1 dead-time compare register (TAB1DTC register)
Control registers
TAB1 option register 1 (TAB1OPT1)
TAB1 option register 2 (TAB1OPT2)
TAB1 I/O control register 3 (TAB1IOC3)
High-impedance output control register 0 (HZA0CTL0)
High-impedance output control register 1 (HZA0CTL1)
• 6-phase PWM output can be produced with dead time by using the output of TAB1 (TOAB11, TOAB12, TOAB13).
• The output level of the 6-phase PWM output can be set individually.
• The 16-bit timer/counter of TAB1 counts up/down triangular waves. When the timer/counter underflows and when a
cycle match occurs, an interrupt is generated. Interrupt generation, however, can be suppressed up to 31 times.
• TAA4 can execute counting at the same time as TAB1 (timer tuning operation function). TAA4 can be set in three
ways as it can generate an A/D trigger source (TABTADT0) and two types of interrupts: a TAB1 underflow interrupt
(INTTAB1OV) and a cycle match interrupt (INTTAB1CC0).
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CHAPTER 11 MOTOR CONTROL FUNCTION
Figure 11-1. Block Diagram of Motor Control
TOAB10
TAB1
• Carrier
• 3-phase PWM
generation
TAA4
• A/D trigger
generation in
synchronization
with TAB1
TOAB1T1
TMQ option
• 6-phase PWM
generation with
dead time from
3-phase PWM
• Culling control
• A/D trigger selection
TOAB1B1
TOAB1T2
TOAB1B2
TOAB1T3
TAA1
TOAB1B3
• PWM generation
TOAA11
High-impedance
output
controller
Crest interrupt
(INTTAB1CC0)
INTC
• Interrupt control
Valley interrupt
(INTTAB1OV)
Noise
elimination
INTP16/TOAB1OFF
Noise
elimination
INTP09/TOAA1OFF
A/D trigger of A/D converter
Edge detection
Edge detection
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CHAPTER 11 MOTOR CONTROL FUNCTION
Figure 11-2. TMQ1 Option
Internal bus
TOAB10
TABnDTC
(10-bit dead-time value)
TAB1
Channel 1
TOAB10
TOAB11Note
(internal
signal)
Clear
Edge
detection
Dead-time counter 1
(10 bits)
High-impedance
output controller
Positive
phase
F/F
Level
control
Active setting
Output control
Negative
phase
F/F
Level
control
Active setting
Output control
TOAB1T1
TOAB1B1
TOAB1T2
Channel 2
TOAB12Note
(internal
signal)
TOAB13Note
(internal
signal)
TOAB1B2
TOAB1T3
Channel 3
TOAB1B3
Interrupt culling circuit
INTC
INTTAB1OV_BASE
INTTAB1OV
INTTAB1CC0
Counter
Mask
control
Mask count buffer
Crest/valley interrupt
selection
Culling enable
Number of masks
TABTICCn0
TABTIOVn
A/D trigger
generator 1
A/D converter
A/D trigger selection
(TAB1OPT2 register)
Up/down selection
TAA4
TABTADT0
INTTAA4CC0
INTTAA4CC1
Note TOAB11, TOAB12, and TOAB13 function alternately as output pins.
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CHAPTER 11 MOTOR CONTROL FUNCTION
(1) TAB1 dead-time compare register (TAB1DTC)
The TAB1DTC register is a 10-bit compare register that specifies the dead-time value.
Rewriting this register is prohibited when the TAB1CTL0.TAB1CE bit = 1.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution
When generating a dead-time period, set the TAB1DTC register to 1 or higher.
Note, when the operation is stopped (TAB1CTL0.TAB1CE bit = 0), a dead-time period is not
generated, so the output levels of the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3 pins are
in their default states. Therefore, for the protection of the system, take measures such as making
the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3 pins go into a high-impedance state before
stopping operation, or setting the output levels of the pins before switching port modes.
When a dead-time period is not needed, set the TAB1DTC register to 0.
After reset: 0000H
R/W
10
15
TAB1DTC
Address: FFFFF584H
000000
9
0
TAB1DTC9 to TAB1DTC0
(2) Dead-time counters 1 to 3
The dead-time counters are 10-bit counters that count dead time.
These counters are cleared or count up at the rising or falling edge of the TOAB1m output signal of TAB1, and are
cleared or stopped when their count value matches the value of the TAB1DTC register. The count clock of these
counters is the same as that set by the TAB1CTL0.TAB1CKS2 to TAB1CTL0.TAB1CKS0 bits of TAB1.
Remarks 1. The operation differs when the TAB1OPT2.TAB1DTM bit = 1. For details, see 11.4.2 (4) Automatic
dead-time width narrowing function (TAB1OPT2.TAB1DTM bit = 1).
2. m = 1 to 3
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11.3 Control Registers
(1) TAB1 option register 1 (TAB1OPT1)
The TAB1OPT1 register is an 8-bit register that controls the interrupt request signal generated by the timer Q option
function.
This register can be rewritten when the TAB1CTL0.TAB1CE bit is 1.
Two rewrite modes (batch write mode and anytime write mode) can be selected, depending on the setting of the
TAB1OPT0.TAB1CMS bit.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
TAB1OPT1
Address: FFFFF580H
5
4
3
2
1
0
TAB1ICE TAB1IOE
0
TAB1ID4 TAB1ID3 TAB1ID2 TAB1ID1 TAB1ID0
TAB1ICE
Crest interrupt (INTTAB1CC0 signal) enable
0
Do not use INTTAB1CC0 signal (do not use it as count signal for interrupt
culling).
1
Use INTTAB1CC0 signal (use it as count signal for interrupt culling).
TAB1IOE
Valley interrupt (INTTAB1OV signal) enable
0
Do not use INTTAB1OV signal (do not use it as count signal for interrupt
culling).
1
Use INTTAB1OV signal (use it as count signal for interrupt culling).
TAB1ID4 TAB1ID3 TAB1ID2 TAB1ID1 TAB1ID0
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Number of times of interrupt
0
0
0
0
0
Not culled (all interrupts are output)
0
0
0
0
1
1 masked (one of two interrupts is output)
0
0
0
1
0
2 masked (one of three interrupts is output)
0
0
0
1
1
3 masked (one of four interrupts is output)
:
:
:
:
:
1
1
1
0
0
28 masked (one of 29 interrupts is output)
1
1
1
0
1
29 masked (one of 30 interrupts is output)
1
1
1
1
0
30 masked (one of 31 interrupts is output)
1
1
1
1
1
31 masked (one of 32 interrupts is output)
:
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(2) TAB1 option register 2 (TAB1OPT2)
The TAB1OPT2 register is an 8-bit register that controls the timer Q option function.
This register can be rewritten when the TAB1CTL0.TAB1CE bit is 1. However, rewriting the TAB1DTM bit is
prohibited when the TAB1CE bit is 1. The same value can be rewritten.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(1/2)
After reset: 00H
R/W
Address: FFFFF581H
TAB1OPT2
TAB1RDE TAB1DTM TAB1ATM3 TAB1ATM2 TAB1AT3 TAB1AT2 TAB1AT1 TAB1AT0
TAB1RDE
Transfer culling enable
0
Do not cull transfer (transfer timing is generated every time at crest
and valley).
1
Cull transfer at the same interval as interrupt culling set by the TAB1OPT1
register.
TAB1DTM
Dead-time counter operation mode selection (m = 1 to 3)
0
The dead-time counter counts up normally and, if TOAB1m output of
TAB1 is at a narrow interval (TOAB1m output width < dead-time width),
the dead-time counter is cleared and counts up again.
1
The dead-time counter counts up normally and, if TOAB1m output of
TAB1 is at a narrow interval (TOAB1m output width < dead-time width),
the dead-time counter counts down and the dead-time control width is
automatically narrowed.
Rewriting the TAB1DTM bit is disabled during timer operation. If it is rewritten by
mistake, stop the timer operation by clearing the TAB1CE bit to 0, and re-set the
TAB1DTM bit.
Cautions 1. When using interrupt culling (the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits are
set to other than 00000), be sure to set the TAB1RDE bit to 1.
This means that interrupts and transfers are generated at the same timing. Interrupts
and transfers, cannot be set separately. If interrupts and transfers are set separately
(TAB1RDE bit = 0), transfers are not performed normally.
2. When generating a dead-time period, set the TAB1DTC register to 1 or higher.
Note, when the operation is stopped (TAB1CTL0.TAB1CE bit = 0), a dead-time period is
not generated, so the output levels of the TOAB1T1 to TOAB1T3 and TOAB1B1 to
TOAB1B3 pins are in their default states. Therefore, for the protection of the system,
take measures such as making the TOAB1T1 to TOAB1T3 and TOAB1B1 to TOAB1B3
pins go into a high-impedance state before stopping operation, or setting the output
levels of the pins before switching port modes.
When a dead-time period is not needed, set the TAB1DTC register to 0.
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(2/2)
TAB1ATM3
TAB1ATM3 mode selection
0
Output A/D trigger signal (TABTADT0) for INTTAA4CC1 interrupt while
dead-time counter is counting up.
1
Output A/D trigger signal (TABTADT0) for INTTAA4CC1 interrupt while
dead-time counter is counting down.
TAB1ATM2
TAB1ATM2 mode selection
0
Output A/D trigger signal (TABTADT0) for INTTAA4CC0 interrupt while
dead-time counter is counting up.
1
Output A/D trigger signal (TABTADT0) for INTTAA4CC0 interrupt while
dead-time counter is counting down.
TAB1AT3Note
A/D trigger output control 3
0
Disable output of A/D trigger signal (TABTADT0) for INTTAA4CC1 interrupt.
1
Enable output of A/D trigger signal (TABTADT0) for INTRAA4CC1 interrupt.
TAB1AT2Note
A/D trigger output control 2
0
Disable output of A/D trigger signal (TABTADT0) for INTTAA4CC0 interrupt.
1
Enable output of A/D trigger signal (TABTADT0) for INTTAA4CC0 interrupt.
TAB1AT1Note
A/D trigger output control 1
0
Disable output of A/D trigger signal (TABTADT0) for INTTAB1CC0
(crest interrupt).
1
Enable output of A/D trigger signal (TABTADT0) for INTTAB1CC0
(crest interrupt).
TAB1AT0Note
A/D trigger output control 0
0
Disable output of A/D trigger signal (TABTADT0) for INTTAB1OV
(valley interrupt).
1
Enable output of A/D trigger signal (TABTADT0) for INTTAB1OV
(valley interrupt).
Note For the setting of the TAB1AT3 to TAB1AT0 bits, see CHAPTER 15 A/D CONVERTER.
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(3) TAB1 I/O control register 3 (TAB1IOC3)
The TAB1IOC3 register is an 8-bit register that controls the output of the timer Q option function.
To output from the TOAB1Tm pin, set the TAB1IOC0.TAB1OEm bit to 1 and then set the TAB1IOC3 register.
The TAB1IOC3 register can be rewritten only when the TAB1CTL0.TAB1CE bit is 0.
Rewriting each bit of the TAB1IOC3 register is prohibited when the TAB1CTL0.TAB1CE bit is 1; however the same
value can be rewritten to each bit of the TAB1IOC3 register when the TAB1CTL0.TAB1CE bit is 1.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to A8H.
Caution
Set the TAB1IOC3 register to the reset value (A8H) when the timer is used in a mode other than
the 6-phase PWM output mode.
Remarks 1. Set the output level of the TOAB1Tm pin by using the TAB1IOC0 register.
2. m = 1 to 3
After reset: A8H
R/W
Address: FFFFF582H
TAB1IOC3
TAB1OLB3 TAB1OEB3 TAB1OLB2 TAB1OEB2 TAB1OLB1TAB1OEB1
TAB1OLBm
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0
0
Setting of TOAB1Bm pin output level (m = 1 to 3)
0
Disable inversion of output of TOAB1Bm pin
1
Enable inversion of output of TOAB1Bm pin
TAB1OEBm
1
0
TOAB1Bm pin output (m = 1 to 3)
0
Disable TOAB1Bm pin output.
• When TAB1OLBm bit = 0, low level is output from TOAB1Bm pin.
• When TAB1OLBm bit = 1, high level is output from TOAB1Bm pin.
1
Enable TOAB1Bm pin output.
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(a) Output from TOAB1Tm and TOAB1Bm pins
The TOAB1Tm pin output is controlled by the TAB1IOC0.TAB1OLm and TAB1IOC0.TAB1OEm bits. The
TOAB1Bm pin output is controlled by the TAB1IOC3.TAB1OLBm and TAB1IOC3.TAB1OEBm bits.
The timer output with each setting in the 6-phase PWM output mode is shown below.
Figure 11-3. Output Control of TOAB1Tm and TOAB1Bm Pins (Without Dead Time)
16-bit
counter
TAB1OEm bit = 0, TAB1OLm bit = 0 (status after reset)
TAB1OEBm bit = 0, TAB1OLBm bit = 1 (status after reset)
TOAB1Tm
pin output
Fixed to low-level output
TOAB1Bm
pin output
Fixed to high-level output
TAB1OEm bit = 1, TAB1OLm bit = 0 (positive-phase output)
TAB1OEBm bit = 1, TAB1OLBm bit = 1 (negative-phase output)
TOAB1Tm
pin output
TOAB1Bm
pin output
TAB1OEm bit = 1, TAB1OLm bit = 0 (positive-phase output)
TAB1OEBm bit = 1, TAB1OLBm bit = 0 (positive-phase output)
TOAB1Tm
pin output
TOAB1Bm
pin output
TAB1OEm bit = 1, TAB1OLm bit = 1 (negative-phase output)
TAB1OEBm bit = 1, TAB1OLBm bit = 1 (negative-phase output)
TOAB1Tm
pin output
TOAB1Bm
pin output
Remark
m = 1 to 3
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Table 11-1. TOAB1Tm Pin Output
TAB1OLm Bit
TAB1OEm Bit
TAB1CE Bit
0
0
x
Low-level output
1
0
Low-level output
1
TOAB1Tm positive-phase output
0
x
High-level output
1
0
High-level output
1
TOAB1Tm negative-phase output
1
Remark
TOAB1Tm Pin Output
m = 1 to 3
Table 11-2. TOAB1Bm Pin Output
TAB1OLBm Bit
TAB1OEBm Bit
0
1
Remark
TAB1CE Bit
TOAB1Bm Pin Output
0
x
Low-level output
1
0
Low-level output
1
TOAB1Bm positive-phase output
0
x
High-level output
1
0
High-level output
1
TOAB1Bm negative-phase output
m = 1 to 3
(6) High-impedance output control registers 0, 1 (HZA0CTL0, HZA0CTL1)
The HZA0CTL0 and HZA0CTL1 registers are 8-bit registers that control the high-impedance state of the output
buffer.
These registers can be read or written in 8-bit or 1-bit units. However, the HZA0DCFn bit is a read-only bit and
cannot be written.
16-bit access is not possible.
Reset sets these registers to 00H.
Software can be used to always write the same value to the HZA0CTLn register.
The relationship between detection factor and the control registers is shown below.
Pins Subject to High-Impedance Control
High-Impedance Control Factor
Control Register
External Pin
When TOAB1T1 to TOAB1T3 are output
TOAB1OFF/INTP16
HZA0CTL0
TOAA1OFF/INTP09
HZA0CTL1
When TOAB1B1 to TOAB1B3 are output
When TOAA11 is output
Caution
High impedance control is performed only when the target port is specified as a target pin in the
above table.
Remark
n = 0, 1
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(1/2)
After reset: 00H
R/W
HZA0CTLn
Address: HZA0CTL0 FFFFF590H, HZA0CTL1 FFFFF591H
5
4
HZA0DCEn HZA0DCMn HZA0DCNn HZA0DCPn HZA0DCTn HZA0DCCn
1
0
HZA0DCFn
(n = 0, 1)
High-impedance output control
HZA0DCEn
0
Disable high-impedance output control operation. Pins can function as
output pins.
1
Enable high-impedance output control operation.
Condition of clearing high-impedance state by HZA0DCCn bit
HZA0DCMn
0
Setting of the HZA0DCCn bit is valid regardless of the external pin input.
1
Setting of the HZA0DCCn bit is invalid while the external pin input holds a
level detected as abnormal (active level).
Rewrite the HZA0DCMn bit when the HZA0DCEn bit = 0.
HZA0DCNn HZA0DCPn
External pin input edge specification
0
0
No valid edge (setting the HZA0DCFn bit by external pin input
is prohibited).
0
1
Rising edge of the external pin is valid
(abnormality is detected by rising edge input).
1
0
Falling edge of the external pin is valid
(abnormality is detected by falling edge input).
1
1
Setting prohibited
• Rewrite the HZA0DCNn and HZA0DCPn bits when the HZA0DCEn bit is 0.
• For the valid edge specification of the interrupts of the INTP09 and INTP16 pins,
see 23.6.2 (3) External interrupt falling, rising edge specification register 3
(INTR3, INTF3) and (6) External interrupt falling, rising edge specification
register 9H (INTR9, INTF9).
• For the edge specification of the external pins, begin with the TOAB1OFF and
TOAA1OFF pins. Then, perform edge specification for the external pins other than
the TOAB1OFF and TOAA1OFF pins. Otherwise, an undefined edge may be
detected when the edge for the TOAB1OFF and TOAA1OFF pins is specified.
• High-impedance output control is performed when the valid edge is input after the
operation is enabled (by setting HZA0DCEn bit to 1). If the external pin is at
the active level when the operation is enabled, therefore, high-impedance output
control is not performed.
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(2/2)
High-impedance output trigger bit
HZA0DCTn
0
No operation
1
Pins are made to go into a high-impedance state by software and the
HZA0DCFn bit is set to 1.
• If an edge indicating abnormality is input to the external pin (which is detected
according to the setting of the HZA0DCNn and HZA0DCPn bits), the HZA0DCTn
bit is invalid even if it is set to 1.
• The HZA0DCTn bit is always 0 when it is read because it is a software-triggered
bit.
• The HZA0DCTn bit is invalid even if it is set to 1 when the HZA0DCEn bit = 0.
• Simultaneously setting the HZA0DCTn and HZA0DCCn bits to 1 is prohibited.
HZA0DCCn
High-impedance output control clear bit
0
No operation
1
Pins that have gone into a high-impedance state are output-enabled by
software and the HZA0DCFn bit is cleared to 0.
• Pins can function as output pins when the HZA0DCM bit = 0, regardless of the
status of the external pin.
• If an edge indicating abnormality is input to the external pin (which is set by the
HZA0DCNn and HZA0DCPn bits) when the HZA0DCM bit = 1, the HZA0DCCn
bit is invalid even if it is set to 1.
• The HZA0DCCn bit is always 0 when it is read.
• The HZA0DCCn bit is invalid even if it is set to 1 when the HZA0DCEn bit = 0.
• Simultaneously setting the HZA0DCTn and HZA0DCCn bits to 1 is prohibited.
HZA0DCFn
High-impedance output status flag
Clear (0)
Indicates that output of the pin is enabled.
• This bit is cleared to 0 when the HZA0DCEn bit = 0.
• This bit is cleared to 0 when the HZA0DCCn bit = 1.
Set (1)
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Indicates that the pin goes into a high-impedance state.
• This bit is set to 1 when the HZA0DCTn bit = 1.
• This bit is set to 1 when an edge indicating abnormality is input to the
external pin (which is detected according to the setting of the
HZA0DCNn and HZA0DCPn bits).
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Figure 11-4. High-Impedance Output Controller Configuration
TOAA1OFF/
INTP09
Analog
filter
TOAB1OFF/
INTP16
Analog
filter
Edge detection
INTP16
Edge detection
INTP09
HZA0CTL1
X2
Main
oscillator
TOAA11
TMQOP
TOAB1B1
HZA0CTL0
PLL
X1
TAA1
Clock monitor
circuit
TOAB1T1
TOAB1B2
TOAB1T2
TOAB1B3
TOAB1T3
Remark
Also see Figures 11-1 and 11-2.
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(a) Setting procedure
(i) Setting of high-impedance control operation
Set the HZA0DCMn, HZA0DCNn, and HZA0DCPn bits.
Set the HZA0DCEn bit to 1 (enable high-impedance control).
(ii) Changing setting after enabling high-impedance control operation
Clear the HZA0DCEn bit to 0 (to stop the high-impedance control operation).
Change the setting of the HZA0DCMn, HZA0DCNn, and HZA0DCPn bits.
Set the HZA0DCEn bit to 1 (to enable the high-impedance control operation again).
(iii) Resuming output when pins are in high-impedance state
If the HZA0DCMn bit is 1, set the HZA0DCCn bit to 1 to clear the high-impedance state after the valid
edge of the external pin is detected. However, the high-impedance state cannot be cleared unless this bit
is set while the input level of the external pin is inactive.
Set the HZA0DCCn bit to 1 (command signal to clear the high-impedance state).
Read the HZA0DCFn bit and check the flag status.
Return to if the HZA0DCFn bit is 1. The input level of the external pin must be checked.
The pin can function as an output pin if the HZA0DCFn bit is 0.
(iv) Making pin go into high-impedance state by software
The HZA0DCTn bit must be set to 1 by software to make the pin go into a high-impedance state while the
input level of the external pin is inactive. The following procedure is an example in which the setting is not
dependent upon the setting of the HZA0DCMn bit.
Set the HZA0DCTn bit to 1 (high-impedance output command).
Read the HZA0DCFn bit to check the flag status.
Return to if the HZA0DCFn bit is 0. The input level of the external pin must be checked.
The pin is in a high-impedance state if the HZA0DCFn bit is 1.
However, if the external pin is not used with the HZA0DCPn bit and HZA0DCNn bit cleared to 0, the pin
goes into a high-impedance state when the HZA0DCTn bit is set to 1.
Remark
n = 0, 1
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11.4 Operation
11.4.1 System outline
(1) Outline of 6-phase PWM output
The 6-phase PWM output mode is used to generate a 6-phase PWM output wave, by using the timer AB1 (TAB1)
and the TMQ option (TMQOPA) in combination.
The 6-phase PWM output mode is enabled by setting the TAB1CTL1.TAB1MD2 to TAB1CTL1.TAB1MD0 bits of
TAB1 to “111”.
One 16-bit counter and four 16-bit compare registers of TAB1 are used to generate a basic 3-phase wave.
The functions of the compare registers are as follows.
TAA4 can perform a tuning operation with TAB1 to generate a conversion trigger source for the A/D converter.
Compare Register
Function
Settable Range
TAB1CCR0 register
Setting of cycle
0002H ≤ m ≤ FFFEH
TAB1CCR1 register
Specifying output width of phase U
0000H ≤ i ≤ m + 1
TAB1CCR2 register
Specifying output width of phase V
0000H ≤ j ≤ m + 1
TAB1CCR3 register
Specifying output width of phase W
0000H ≤ k ≤ m + 1
Remark
m = Set value of TAB1CCR0 register
i = Set value of TAB1CCR1 register
j = Set value of TAB1CCR2 register
k = Set value of TAB1CCR3 register
A dead-time interval is generated from the basic 3-phase wave generated by using three 10-bit dead-time counters
and one compare register to create a wave with a reverse phase to that of the basic 3-phase wave. Then a 6phase PWM output wave (U, U, V, V, W, and W) is generated.
The 16-bit counter for generating the basic 3-phase wave counts up or down. After the operation has been started,
this counter counts up. When its count value matches the cycle set to the TAB1CCR0 register, the counter starts
counting down. When the count value matches 0001H, the counter counts up again. This means that a value two
times higher than the value set to the TAB1CCR0 register + 1 is the carrier cycle.
10-bit dead-time counters 1 to 3, which generate the dead-time interval, count up. Therefore, the value set to the
TAB1 dead-time compare register (TAB1DTC) is used as a dead-time value as is. Because three counters are
used, dead time can be generated independently in phases U, V, and W. However, because there is only one
register that specifies a dead-time value (TAB1DTC), the same dead-time value is used in all three phases.
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Figure 11-5. Outline of 6-Phase PWM Output Mode
16-bit counter
A/D trigger
generator
Up/down selection
INTTAB1OV_BASE
Interrupt
culling circuit
0001H
Dead-time counter 1
TAB1CCR1 register (phase U output data)
TOAB12
(internal signal)Note
Dead-time counter 2
TAB1CCR2 register (phase V output data)
TOAB13
(internal signal)Note
INTTAB1CC0 signal
(crest interrupt)
TOAB10 pin
output
TAB1CCR0 register (carrier cycle)
TOAB11
(internal signal)Note
INTTAB1OV signal
(valley interrupt)
Dead-time counter 3
TAB1CCR3 register (phase W output data)
TOT1
TOAB1T1 pin
output (U)
TOB1
TOAB1B1 pin
output (U)
TOT2
TOAB1T2 pin
output (V)
TOB2
TOAB1B2 pin
output (V)
TOT3
TOAB1T3 pin
output (W)
TOB3
TOAB1B3 pin
output (W)
TAB1DTC register
(dead-time value)
Note TOAB11, TOAB12, and TOAB13 function alternately as output pins.
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Figure 11-6. Timing Chart of 6-Phase PWM Output Mode
M+1
k
16-bit
counter
j
i
0000H
TAB1CCR0
register
TAB1CCR1
register
TAB1CCR2
register
TAB1CCR3
register
M+1
k
k
j
k
j
i
j
i
i
M (carrier data)
i (phase U data)
j (phase V data)
k (phase W data)
TOAB11 signal
(internal signal)
TOAB12 signal
(internal signal)
TOAB13 signal
(internal signal)
Carrier cycle = (M + 1) × 2
Basic phase U output width = (M + 1 - i) ´ 2
Basic phase V output width = (M + 1 − j) × 2
TAB1DTC
register
Basic phase W output width = (M + 1 − k) × 2
N (dead-time value)
Dead-time
counter 1
Dead-time
counter 2
Dead-time
counter 3
TOAB10
pin output
TOAB1T1
pin output (U)
TOAB1B1
pin output (U)
TOAB1T2
pin output (V)
TOAB1B2
pin output (V)
TOAB1T3
pin output (W)
TOAB1B3
pin output (W)
Phase U output width = (M + 1 − i) × 2 − N
Phase U output width = (M + 1 − i) × 2 + N
Phase V output width = (M + 1 − j) × 2 − N
Phase V output width = (M + 1 − j) × 2 + N
Phase W output width = (M + 1 − k) × 2 − N
Phase W output width = (M + 1 − k) × 2 + N
Dead-time width = N
Cautions 1. Set the value “M” of the TAB1CCR0 register in a range of 0002H ≤ M ≤ FFFEH in the 6-phase
PWM output mode.
2. Only a value of up to “M + 1” can be set to the TAB1CCR1, TAB1CCR2, and TAB1CCR3
registers.
3. The output is 100% if “0000H” is set to the TAB1CCR1, TAB1CCR2, and TAB1CCR3
registers. The output is 0% if “M + 1” is set to the TAB1CCR1, TAB1CCR2, and TAB1CCR3
registers.
The output (duty 50%) rises at the crest (M + 1) of the 16-bit counter and falls at the valley
(0000H) if “M + 2” or higher is set to the TAB1CCR1, TAB1CCR2, and TAB1CCR3 registers.
4. If the operation value of an equation (such as (M + 1 – i) × 2 – N) of the output width of
phases U, V, and W is 0 or lower, it is converged to 0 (100% output). If the operation value is
higher than “(M + 1) × 2”, it is converged to (M + 1) × 2 (0% output).
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(2) Interrupt requests
Two types of interrupt requests are available: the INTTAB1CC0 (crest interrupt) signal and INTTAB1OV (valley
interrupt) signal.
The INTTAB1CC0 and INTTAB1OV signals can be culled by using the TAB1OPT1 register.
For details of culling interrupts, see 11.4.3 Interrupt culling function.
• INTTAB1CC0 (crest interrupt) signal: An interrupt signal indicating a match between the value of the 16-bit
counter that counts up and the value of the TAB1CCR0 register
• INTTAB1OV (valley interrupt) signal: An interrupt signal indicating a match between the value of the 16-bit
counter that counts down and the value 0001H
(3) Rewriting registers during timer operation
The following registers have a buffer register and can be rewritten in the anytime rewrite mode, batch rewrite mode,
or intermittent batch rewrite mode.
Related Unit
Register
TAA1 capture/compare register 0 (TAA1CCR0)
Timer AA1
TAA1 capture/compare register 1 (TAA1CCR1)
TAB1 capture/compare register 0 (TAB1CCR0)
Timer AB1
TAB1 capture/compare register 1 (TAB1CCR1)
TAB1 capture/compare register 2 (TAB1CCR2)
TAB1 capture/compare register 3 (TAB1CCR3)
Timer Q1 option
TAB1 option register 1 (TAB1OPT1)
For details of the transfer function of the compare register, see 11.4.4 Operation to rewrite register with transfer
function.
(4) Counting-up/down operation of 16-bit counter
The operation status of the 16-bit counter can be checked by using the TAB1CUF bit of TAB1 option register 0
(TAB1OPT0).
Status of TAB1CUF Bit
Status of 16-Bit Counter
Range of 16-Bit Counter Value
TAB1CUF bit = 0
Counting up
0000H − m
TAB1CUF bit = 1
Counting down
(m + 1) − 0001H
Remark
m = Set value of TAB1CCR0 register
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Figure 11-7. Interrupt and Up/Down Flag
M+1
k
16-bit
counter
j
i
0000H
TAB1CCR0
register
TAB1CCR1
register
TAB1CCR2
register
TAB1CCR3
register
TOAB10
pin output
TOAB1T1
pin output (U)
TOAB1B1
pin output (U)
TOAB1T2
pin output (V)
TOAB1B2
pin output (V)
TOAB1T3
pin output (W)
TOAB1B3
pin output (W)
M+1
k
k
j
j
i
i
k
j
i
M (carrier data)
i (phase U data)
j (phase V data)
k (phase W data)
INTTAB1CC0
(crest interrupt)
INTTAB1OV
(valley interrupt)
TAB1CUF
(up/down flag)
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11.4.2 Dead-time control (generation of negative-phase wave signal)
(1) Dead-time control mechanism
In the 6-phase PWM output mode, compare registers 1 to 3 (TAB1CCR1, TAB1CCR2, and TAB1CCR3) are used to
set the duty factor, and compare register 0 (TAB1CCR0) is used to set the cycle. By setting these four registers
and by starting the operation of TAB1, three types of PWM output waves (basic 3-phase waves) with a variable duty
factor are generated. These three PWM output waves are input to the timer Q option unit (TMQOP) and their
inverted signal with dead-time is created to generate three sets of (six) PWM waves.
The TMQOP unit consists of three 10-bit counters (dead-time counters 1 to 3) that operate in synchronization with
the count clock of TAB1, and a TAB1 dead-time compare register (TAB1DTC) that specifies dead time. If “a” is set
to the TAB1DTC register, the dead-time value is “a”, and interval “a” is created between a positive-phase wave and
a negative-phase wave.
Figure 11-8. PWM Output Wave with Dead Time (1)
(a) When dead time is inserted (TAB1DTC register = a)
16-bit
counter
TOAB1m signal
(internal signal)
Dead-time
counter m
TOAB1Tm
pin output
TOAB1Bm
pin output
a
a
(b) No dead time (TAB1DTC register = 000H)
16-bit
counter
TOAB1m signal
(internal signal)
Dead-time
counter m
TOAB1Tm
pin output
0000H
TOAB1Bm
pin output
0
Remark
0
m = 1 to 3
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(2) PWM output of 0%/100%
The V850ES/V850ES/JG3-H and V850ES/JH3-H are capable of 0% wave output and 100% wave output for PWM
output.
A low level is continuously output from the TOAB1Tm pin as the 0% wave output. A high level is continuously
output from the TOAB1Tm pin as the 100% wave output.
A 0% wave is output by setting the TAB1CCRm register to “M + 1” when the TAB1CCR0 register = M.
A 100% wave is output by setting the TAB1CCRm register to “0000H”.
Rewriting the TAB1CCRm register is enabled while the timer is operating, and 0% wave output or 100% wave
output can be selected at the point of the crest interrupt (INTTAB1CC0) and valley interrupt (INTTAB1OV).
Remark
m = 1 to 3
Figure 11-9. 0% PWM Output Waveform (With Dead Time)
16-bit
counter
i
i
TAB1CCR0
register
i
i
M
TAB1CCR1
register
CCR1
buffer register
i
i
M+1
i
0000H
i
M+1
i
TOAB1T1
pin output
M+1
i
M+1
0% output
i
i
0% output
TOAB1B1
pin output
Forced timing
of timer output
0% output is selected by the valley interrupt (without a match with the 16-bit counter).
The valley interrupt forcibly lowers the timer output. This produces the 0% output.
0% output is canceled by the crest interrupt (without a match with the 16-bit counter).
The crest interrupt forcibly raises the timer output. This cancels the 0% output.
0% output is selected by the crest interrupt (with a match with the 16-bit counter).
The crest interrupt forcibly raises the timer output, but lowering the timer output takes precedence when
the value of the TAB1CCRm register matches the value of the 16-bit counter. As a result, the 0% wave is
output.
0% output is canceled by the valley interrupt (without a match with the 16-bit counter).
The valley interrupt forcibly lowers the timer output. This cancels the 0% output.
Remarks 1.
means forcible raising and means forcible lowering.
2. m = 1 to 3
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Figure 11-10. 100% PWM Output Waveform (With Dead Time)
16-bit
counter
i
i
i
TAB1CCR0
register
i
i
M
TAB1CCR1
register
CCR1
buffer register
i
0000H
i
0000H
i
0000H
TOAB1T1
pin output
TOAB1B1
pin output
Forced timing
of timer output
0000H
i
0000H
i
100%
output
i
i
100%
output
100% output is selected by the valley interrupt (with a match with the 16-bit counter).
The valley interrupt forcibly lowers the timer output, but raising the timer output takes precedence when
the value of the TAB1CCRm register matches the value of the 16-bit counter. As a result, the 100% output
is produced.
100% output is canceled by the valley interrupt (without a match with the 16-bit counter).
The valley interrupt forcibly lowers the timer output. This cancels the 100% output.
100% output is selected by the crest interrupt (without a match with the 16-bit counter).
The crest interrupt forcibly raises the timer output. This produces the 100% output.
100% output is canceled by the crest interrupt (without a match with the 16-bit counter).
The crest interrupt forcibly raises the timer output. This cancels the 100% output.
Remarks 1.
means forcible raising and means forcible lowering.
2. m = 1 to 3
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Figure 11-11. PWM Output Waveform from 0% to 100% and from 100% to 0% (With Dead Time)
16-bit
counter
TAB1CCR0
register
M
TAB1CCR1
register
CCR1
buffer register
0000H
0000H
0000H
TOAB1T1
pin output
TOAB1B1
pin output
M+1
M+1
0000H
M+1
100%
output
0000H
M+1
0000H
0% output
0000H
0% output
100%
output
100%
output
Forced timing
of timer output
The valley interrupt selects 100% ←→ 0% or 0% ←→ 100% output.
Output can be selected from 100% ←→ 0% or 0% ←→ 100% immediately after the timer has been
started.
The crest interrupt selects 100% ←→ 0% output.
The crest interrupt selects 100% → 0% output by using the timer output forcible raising function and by a
match between the 16-bit counter value and the TAB1CCR0 register value.
(3) Output waveform in vicinity of 0% and 100% output
If an interrupt is generated because the value of the 16-bit counter matches the value of the compare register while
dead time is being counted, the dead-time counter is cleared and starts its count operation again.
The output waveform of dead-time control in the vicinity of 0% and 100% output is shown below.
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Figure 11-12. PWM Output Waveform with Dead Time (2)
(a) 0% output (TAB1CCRm register = M + 1, TAB1CCR0 register = M, TAB1DTC register = a)
16-bit
counter
0000H
L
TOAB1m signal
(internal signal)
Dead-time
counter m
TOAB1Tm
pin output
TOAB1Bm
pin output
000H (dead-time counter m does not count)
L
H
(b) In vicinity of 0% output (TAB1CCRm register = i ≥ M + 1 − a/2, TAB1CCR0 register = M, TAB1DTC register = a)
16-bit
counter
0000H
TOAB1m signal
(internal signal)
Dead-time
counter m 000H
Dead-time counter is cleared and counts again
TOAB1Tm
pin output
TOAB1Bm
pin output
L
Negative-phase output width: (M + 1 − i) × 2 + a
(e.g., output width is 2 + a where TAB1CCRm register = M)
(c) In vicinity of 100% output (TAB1CCRm register = i ≤ a/2, TAB1CCR0 register = M, TAB1DTC register = a)
16-bit
counter
0000H
TOAB1m signal
(internal signal)
Dead-time
counter m 000H
TOAB1Tm
pin output
Counter is cleared and counts again
TOAB1Bm
pin output
Positive-phase output width: (M + 1 − i) × 2 − a)
(e.g., output width is 2 − a where TAB1CCRm register = 0001H.)
(d) 100% output (TAB1CCRm register = 0000H, TAB1CCR0 register = M, TAB1DTC register = a)
16-bit
counter
0000H
TOAB1m signal
(internal signal)
Dead-time
counter m
000H (dead-time counter m does not count)
TOAB1Tm
pin output
TOAB1Bm
pin output
Remark
m = 1 to 3
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(4) Automatic dead-time width narrowing function (TAB1OPT2.TAB1DTM bit = 1)
The dead-time width can be automatically narrowed in the vicinity of 0% output or 100% output by setting the
TAB1OPT2.TAB1DTM bit to 1.
By setting the TAB1DTM bit to 1, the dead-time counter is not cleared, but starts down counting if the TOAB1m
(internal signal) output of timer AB changes during dead-time counting.
The following timing chart shows the operation of the dead-time counter when the TAB1DTM bit is set to 1.
Figure 11-13. Operation of Dead-Time Counter m (1)
(a) In vicinity of 0% output
(TAB1CCRm register = i ≥ M + 1 − a/2, TAB1CCR0 register = M, TAB1DTC register = a)
16-bit
counter
0000H
TOAB1m signal
(internal signal)
Dead-time
counter m 000H
Dead-time counter m starts counting down
TOAB1Tm
pin output
TOAB1Bm
pin output
Negative-phase wave output width: (M + 1 − i) × 4
(e.g., output width is 4 where TAB1CCRm = M)
(b) In vicinity of 100% output (TAB1CCRm register = i ≤ a/2, TAB1CCR0 register = M, TAB1DTC register = a)
16-bit
counter
0000H
TOAB1m signal
(internal signal)
Dead-time
counter m
000H
TOAB1Tm
pin output
Dead-time counter m starts counting down
TOAB1Bm
pin output
Note
Positive-phase wave output width: (M + 1 − i) × 2 − (i × 2)
(e.g., output width is M × 2 − 2 where TAB1CCRm = 0001H)
Note The output width of the first wave differs from that of the second and subsequent waves immediately
after the TAB1CTL0.TAB1CE bit has been set. The first wave is shorter than the second wave because
the dead time is fully counted.
Remark
m = 1 to 3
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(5) Dead-time control in case of incorrect setting
Usually, the TOAB1m (internal signal) output of TAB1 changes only once during dead-time counting, only in the
vicinity of 0% and 100% output. This section shows an example where the TAB1CCR0 register (carrier cycle) and
TAB1DTC register (dead-time value) are incorrectly set. If these registers are incorrectly set, the TOAB1m (internal
signal) output of TAB1 changes twice or three times during dead-time counting. The following flowchart shows the
6-phase PWM output wave in this case.
Figure 11-14. Operation of Dead-Time Counter m (2)
(a) When TAB1OPT2.TAB1DTM bit = 0, TAB1CCR0 register = 0006H, TAB1DTC register = 000FH,
TAB1CCRm register = 0004H
16-bit
counter
TOAB1m signal
(internal signal)
Dead-time
counter m
001H 002H 003H 004H 005H 006H 001H 002H 003H 004H 005H 006H 007H 008H 009H 00AH 00BH 00CH 00DH 00EH 00FH
000H
000H
001H
TOAB1Tm
pin output
TOAB1Bm
pin output
Counter cleared
Counter is not cleared but continues counting
(b) When TAB1OPT2.TAB1DTM bit = 1, TAB1CCR0 register = 0006H, TAB1DTC register = 000FH,
TAB1CCRm register = 0002H
16-bit
counter
TOAB1m signal
(internal signal)
Dead-time
counter m
000H
001H 002H 003H 004H 005H 006H 007H 008H 009H 00AH 009H 008H 007H 006H 005H 004H 003H 002H 001H
000H
001H 002H 003H 004H 003H 002H 001H
TOAB1Tm
pin output
TOAB1Bm
pin output
Starts counting
down.
Remark
Output does not change
and dead-time counter m
continues counting down
m = 1 to 3
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11.4.3 Interrupt culling function
• The interrupts to be culled are INTTAB1CC0 (crest interrupt) and INTTAB1OV (valley interrupt).
• The TAB1OPT1.TAB1ICE bit is used to enable output of the INTTAB1CC0 interrupt and the number of times the
interrupt is to be culled.
• The TAB1OPT1.TAB1IOE bit is used to enable output of the INTTAB1OV interrupt and the number of times the
interrupt is to be culled.
• The TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits are used to specify the number of counts by which a specified
interrupt is to be culled. The interrupt is masked for the duration of the specified number of counts and is generated
at the next interrupt timing.
• The TAB1OPT2.TAB1RDE bit is used to specify whether transfer is to be culled or not.
If it is specified that transfer is to be culled, transfer is executed at the same timing as the interrupt output after culling.
If it is specified that transfer is not to be culled, transfer is executed at the transfer timing after the TAB1CCR1 register
has been written.
• The TAB1OPT0.TAB1CMS bit is used to specify whether the registers with a transfer function are batch rewritten or
anytime rewritten.
The values of the registers are updated in synchronization with transfer when the TAB1CMS bit is 0. When the
TAB1CMS bit is 1, the values of the registers are immediately updated when a new value is written to the registers.
Transfer is performed from the TAB1CCRm register to the CCRm buffer register in synchronization with the interrupt
culling timing.
Cautions 1. When using the interrupt culling function in the batch rewrite mode (transfer mode), execute the
function in the intermittent batch rewrite mode (transfer culling mode).
2. The interrupt is generated at the timing after culling.
Remark
m = 1 to 3
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(1) Interrupt culling operation
Figure 11-15. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1,
TAB1OPT2.TAB1RDE Bit = 1 (Crest/Valley Interrupt Output)
16-bit
counter
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001 (1 mask)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00010 (2 masks)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00011 (3 masks)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00100 (4 masks)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00101 (5 masks)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00110 (6 masks)
INTTAB1CC0 signal
INTTAB1OV signal
Remark
: Culled interrupt
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Figure 11-16. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 0,
TAB1OPT2.TAB1RDE Bit = 1 (Crest Interrupt Output)
16-bit
counter
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001 (1 mask)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00010 (2 masks)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00011 (3 masks)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00100 (4 masks)
INTTAB1CC0 signal
INTTAB1OV signal
Remark
: Culled interrupt
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Figure 11-17. Interrupt Culling Operation When TAB1OPT1.TAB1ICE Bit = 0, TAB1OPT1.TAB1IOE Bit = 1,
TAB1OPT2.TAB1RDE Bit = 1 (Valley Interrupt Output)
16-bit
counter
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00000 (not culled)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001 (1 mask)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00010 (2 masks)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00011 (3 masks)
INTTAB1CC0 signal
INTTAB1OV signal
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00100 (4 masks)
INTTAB1CC0 signal
INTTAB1OV signal
Remark
: Culled interrupt
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(2) To alternately output crest interrupt (INTTAB1CC0) and valley interrupt (INTTAB1OV)
To alternately output the crest and valley interrupts, set both the TAB1OPT1.TAB1ICE and TAB1OPT1.TAB1IOE
bits to 1.
Figure 11-18. Crest/Valley Interrupt Output
(a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.TAB1RDE bit = 1 (with transfer culling control)
16-bit
counter
INTTAB1CC0
signal
INTTAB1OV
signal
TAB1ID4 to TAB1ID0 bits
TAB1ID4 to TAB1ID0 bits
(slave bit)
00100
00010
Transfer
00100
00010
Timing of rewriting transfer
culling count from 2 to 4
Remarks 1. Transfer is performed at the culled interrupt output timing. The other transfer timing is ignored.
2.
: Culled interrupt
(b) TAB1CMS bit = 1, TAB1RDE bit = 0 or 1 (without transfer control)
16-bit
counter
INTTAB1CC0
signal
INTTAB1OV
signal
TAB1ID4 to TAB1ID0 bits
TAB1ID4 to TAB1ID0 bits
(slave bit)
00010
00100
Reflected immediately
00100
00010
Timing of rewriting transfer
culling count from 2 to 4
Remarks 1. Rewriting is reflected immediately. The transfer timing is ignored.
2.
: Culled interrupt
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(3) To output only crest interrupt (INTTAB1CC0)
Set the TAB1OPT1.TAB1ICE bit to 1 and clear the TAB1OPT1.TAB1IOE bit to 0.
Figure 11-19. Crest Interrupt Output
(a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.TAB1RDE bit = 1 (with transfer culling control)
16-bit
counter
INTTAB1CC0
signal
INTTAB1OV
signal
L
TAB1ID4 to TAB1ID0 bits
00011
00010
Transfer
TAB1ID4 to TAB1ID0 bits
(slave bit)
00011
00010
Timing of rewriting transfer
culling count from 2 to 3
Remarks 1. Transfer is performed at the culled interrupt output timing. The other transfer timing is ignored.
2.
: Culled interrupt
(b) TAB1CMS bit = 1, TAB1RDE bit = 0 or 1 (without transfer control)
16-bit
counter
INTTAB1CC0
signal
INTTAB1OV
signal
L
TAB1ID4 to TAB1ID0 bits
00010
TAB1ID4 to TAB1ID0 bits
(slave bit)
00010
00011
Reflected immediately
00011
Timing of rewriting transfer
culling count from 2 to 3
Remarks 1. Rewriting is reflected immediately. The transfer timing is ignored.
2.
: Culled interrupt
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(4) To output only valley interrupt (INTTAB1OV)
Clear the TAB1OPT1.TAB1ICE bit to 0 and set the TAB1IOE bit to 1.
Figure 11-20. Valley Interrupt Output
(a) TAB1OPT0.TAB1CMS bit = 0, TAB1OPT2.TAB1RDE bit = 1 (with transfer culling control)
16-bit
counter
INTTAB1CC0
signal
INTTAB1OV
signal
L
TAB1ID4 to TAB1ID0 bits
00011
00010
Transfer
TAB1ID4 to TAB1ID0 bits
(slave bit)
00011
00010
Timing of rewriting transfer
culling count from 2 to 3
Remarks 1. Transfer is performed at the culled interrupt output timing. The other transfer timing is ignored.
2.
: Culled interrupt
(b) TAB1CMS bit = 1, TAB1RDE bit = 0 or 1 (without transfer control)
16-bit
counter
INTTAB1CC0
signal
INTTAB1OV
signal
L
TAB1ID4 to TAB1ID0 bits
00010
TAB1ID4 to TAB1ID0 bits
(slave bit)
00010
00011
Reflected immediately
00011
Timing of rewriting transfer
culling count from 2 to 3
Remarks 1. Rewriting is reflected immediately. The transfer timing is ignored.
2.
: Culled interrupt
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11.4.4 Operation to rewrite register with transfer function
The following seven registers are provided with a transfer function and are used to control a motor. Each of the
registers has a buffer register.
• TAB1CCR0: Register that specifies the cycle of the 16-bit counter (TAB)
• TAB1CCR1: Register that specifies the duty factor of TOAB1T1 (U) and TOAB1B1 (U)
• TAB1CCR2: Register that specifies the duty factor of TOAB1T2 (V) and TOAB1B2 (V)
• TAB1CCR3: Register that specifies the duty factor of TOAB1T3 (W) and TOAB1B3 (W)
• TAB1OPT1: Register that specifies the culling of interrupts
• TAA4CCR0: Register that specifies the A/D conversion start trigger generation timing (TAA4 during tuning operation)
• TAA4CCR1: Register that specifies the A/D conversion start trigger generation timing (TAA4 during tuning operation)
The following three rewrite modes are provided in the registers with a transfer function.
• Anytime rewrite mode
This mode is set by setting the TAB1OPT0.TAB1CMS bit to 1. The specification of the TAB1OPT2.TAB1RDE bit is
ignored.
In this mode, each compare register is updated independently, and the value of the compare register is updated as
soon as a new value is written to it.
• Batch rewrite mode (transfer mode)
This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0, the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits
to 00000, and the TAB1OPT2.TAB1RDE bit to 0.
When data is written to the TAB1CCR1 register, data in the seven registers are transferred to the buffer register all at
once at the next transfer timing. Unless the TAB1CCR1 register is rewritten, the transfer operation is not performed
even if the other six registers are rewritten.
The transfer timing is the timing of each crest (match between the 16-bit counter value and TAB1CCR0 register value)
and valley (match between the 16-bit counter value and 0001H) regardless of the interrupt.
• Intermittent batch rewrite mode (transfer culling mode)
This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0 and setting the TAB1OPT2.TAB1RDE bit to 1.
When data is written to the TAB1CCR1 register, data from the seven registers is transferred to the buffer register all at
once at the next transfer timing. Unless the TAB1CCR1 register is rewritten, the transfer operation is not performed
even if the other six registers are rewritten.
If interrupt culling is specified by the TAB1OPT1 register, the transfer timing is also culled as the interrupts are culled,
and data from the seven registers is transferred all at once at the culled timing of the crest interrupt (match between
the 16-bit counter value and TAB1CCR0 register value) or valley interrupt (match between the 16-bit counter value
and 0001H).
For details of the interrupt culling function, see 11.4.3 Interrupt culling function.
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(1) Anytime rewrite mode
This mode is set by setting the TAB1OPT0.TAB1CMS bit to 1. The setting of the TAB1OPT2.TAB1RDE bit is
ignored.
In this mode, the value written to each register with a transfer function is immediately transferred to an internal
buffer register and compared with the value of the counter. If a register with transfer function is rewritten in this
mode after the count value of the 16-bit counter matches the value of the TAB1CCRm register, the rewritten value
is not reflected because the next match is ignored after the first match has occurred. If the register is rewritten
during counting up, the new register value becomes valid after the counter has started counting down.
Figure 11-21. Timing of Reflecting Rewritten Value
Operating clock
(fXX/2)
TAB1CCR0
register
b
CCR0 buffer
register
b
a
a
Note
Note After the register (TAB1CCR0, TAB1CCR2, TAB1CCR3, TAB1OPT1, TAA4CCR0, or TAA4CCR1) has
been written, the written value is transferred to an internal buffer register after four clocks of the operating
clock. However, the value of the TAB1CCR1 register is transferred after 5 clocks.
(a) Rewriting TAB1CCR0 register
Even if the TAB1CCR0 register is rewritten in the anytime rewrite mode, the new value may not be reflected in
some cases.
Figure 11-22. Example of Rewriting TAB1CCR0 Register
16-bit
counter
Rewriting during period (rewriting during counting up)
If the newly rewritten value is greater than the value of the 16-bit counter, there is no problem because it will
match the value of the 16-bit counter. If the new value is less than the value of the 16-bit counter, it will not
match the value of the counter. As a result, the 16-bit counter overflows and continues counting up from
0000H until it matches the register value again, and the correct PWM waveform is not output.
Rewriting during period (rewriting during counting down)
A match with the value of the 16-bit counter is ignored during counting down. Therefore, the rewritten period
value is reflected as the match point starting from counting up in the next cycle.
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(b) Rewriting TAB1CCRm register
Figure 11-24 shows the timing of rewriting before the value of the 16-bit counter matches the value of the
TAB1CCRm register ( in Figure 11-23), and Figure 11-25 shows the timing of rewriting after the value of the
16-bit counter matches the value of the TAB1CCRm register ( in Figure 11-23).
Figure 11-23. Basic Operation of 16-Bit Counter and TAB1CCRm Register
(a) Basic figure
i
16-bit
counter
i
i
TAB1CCRm
register
i
i
Remarks 1. i = Set value of TAB1CCRm register
2. m = 1 to 3
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Figure 11-24. Example of Rewriting TAB1CCR1 to TAB1CCR3 Registers (Rewriting Before Match Occurs)
(a)
If the TAB1CCRm register is rewritten before its value matches the value of the 16-bit counter, the register value
will match the value of the 16-bit counter after the register has been rewritten. Consequently, the new register
value is immediately reflected.
i
16-bit
counter
TAB1CCRm
register
CCRm buffer
register
TOAB1Tm
pin output
k
k
k
i
k
i
k
(b)
If a value less than the value of the 16-bit counter (greater if the counter is counting down) is written to the
TAB1CCRm register, the output waveform is as follows because the register value does not match the counter
value.
16-bit
counter
TAB1CCRm
register
CCRm buffer
register
TOAB1Tm
pin output
r
i
r
i
r
i
r
r
If the register value does not match the counter value, the TOAB1Tm pin output does not change. Even if the
value of the 16-bit counter does not match the value of the TAB1CCRm register, the TOAB1Tm pin output
always changes to the high level if the crest interrupt occurs and to the low level if the valley interrupt occurs.
This is a function provided for 0% output and 100% output.
For details, see 11.4.2 (2) PWM output of 0%/100%.
Remarks 1. i, r, k = Set values of TAB1CCRm register
2. m = 1 to 3
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Figure 11-25. Example of Rewriting TAB1CCR1 to TAB1CCR3 Registers (Rewriting After Match Occurs)
16-bit
counter
TAB1CCRm
register
CCRm buffer
register
i
i
k
k
i
k
k
i
TOAB1Tm
pin output
INTTAB1CCm
signal
k
Matching of the count value of the 16-bit counter and the value of the TAB1CCRm register as a result of
rewriting the register is ignored after a match signal has been generated, and the PWM output does not
change.
Even if the PWM output does not change, the interrupt generated upon a match between the 16-bit
counter value and the TAB1CCRm register value (INTTAB1CCm) is output.
The next match between the 16-bit counter and TAB1CCRm register is valid after the counter has changed
its counting direction to up or down, and the PWM output changes.
If the TAB1CCRm register is rewritten after its value matches the value of the 16-bit counter, the next match is
ignored after the first match occurs and the rewritten value is not reflected in the TOAB1Tm pin output. If the
register is rewritten while the counter is counting down, the match that occurs after the counter starts counting
down is valid (the match that occurs after the counter has started counting up is valid if the register is rewritten
while the counter is counting up).
Remarks 1. i, r, k = Set value of TAB1CCRm register
2. m = 1 to 3
(c) Rewriting TAB1OPT1 register
The interrupt culling counter is cleared when the TAB1OPT1 register is written. When the interrupt culling
counter has been cleared, the measured number of times the interrupt has occurred is discarded.
Consequently, the interrupt generation interval is temporarily extended.
To avoid this operation, rewrite the TAB1OPT1 register in the intermittent batch rewrite mode (transfer culling
mode).
For details of rewriting the TAB1OPT1 register, see 11.4.3 Interrupt culling function.
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(2) Batch rewrite mode (transfer mode)
This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0, the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0
bits to 00000, and the TAB1OPT2.TAB1RDE bit to 0.
In this mode, the values written to each compare register are transferred to the internal buffer register all at once at
the transfer timing and compared with the counter value.
(a) Rewriting procedure
If data is written to the TAB1CCR1 register, the values set to the TAB1CCR0 to TAB1CCR3, TAB1OPT1,
TAA4CCR0, and TAA4CCR1 registers are transferred all at once to the internal buffer register at the next
transfer timing. Therefore, write to the TAB1CCR1 register last. Writing to the register is prohibited after the
TAB1CCR1 register has been written and before the transfer timing is generated (until the crest (match
between the 16-bit counter value and TAB1CCR0 register value) or the valley (match between the 16-bit
counter value and 0001H)). The operation procedure is as follows.
Rewriting the TAB1CCR0, TAB1CCR2, TAB1CCR3, TAB1OPT1, TAA4CCR0, and TAA4CCR1 registers
Do not rewrite registers that do not have to be rewritten.
Rewriting the TAB1CCR1 register
Rewrite the same value to the register even when it is not necessary to rewrite the TAB1CCR1 register.
Holding the next rewriting pending until the transfer timing is generated
Rewrite the register next time after the INTTAB1OV or INTTAB1CC0 interrupt has occurred.
Return to .
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Figure 11-26. Basic Operation in Batch Mode
16-bit counter
(TAB1)
Transfer
timing
TAB1CCR0
register
CCR0 buffer
register
TAB1CCR1
register
CCR1 buffer
register
TAB1CCR2
register
CCR2 buffer
register
TAB1CCR3
register
CCR3 buffer
register
TAB1OPT1
register
OPT1 buffer
register
&
INTTAB1OV signal
INTTAB1CC0 signal
16-bit counter
(TAA4)
Transfer
timing
TAA4CCR0
register
CCR0 buffer
register
TAA4CCR1
register
CCR1 buffer
register
[Operation of TAB1]
Write the TAB1CCR1 register
The target timing is the first transfer timing after a write to the TAB1CCR1 register.
The values are transferred all at once at the transfer timing.
[Operation of TAA4]
Write the TAB1CCR1 register
The target timing is the first transfer timing after a write to the TAB1CCR1 register.
The values are transferred all at once at the transfer timing.
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(b) Rewriting TAB1CCR0 register
When rewriting the TAB1CCR0 register in the batch rewrite mode, the output waveform differs depending on
whether transfer occurs at the crest (match between the 16-bit counter value and TAB1CCR0 register value) or
at the valley (match between the 16-bit counter value and 0001H). Usually, it is recommended to rewrite the
TAB1CCR0 register while the 16-bit counter is counting down, and transfer the register value at the transfer
timing of the crest timing.
Figure 11-28 shows an example of rewriting the TAB1CCR0 register while the 16-bit counter is counting up
(during period in Figure 11-27). Figure 11-29 shows an example of rewriting the TAB1CCR0 register while
the counter is counting down (during period in Figure 11-27).
Figure 11-27. Basic Operation of 16-Bit Counter
16-bit
counter
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The transfer timing in Figure 11-28 is at the point where the crest timing occurs. While the 16-bit counter is
counting down, the cycle changes and an asymmetrical triangular wave is output. Because the cycle changes,
rewrite the duty factor (voltage data value).
Figure 11-28. Example of Rewriting TAB1CCR0 Register (During Counting Up)
(a) M > N
M
16-bit
counter
Transfer
timing
TAB1CCR0
register
CCR0 buffer
register
TAB1CCR1
register
CCR1 buffer
register
TOAB1T1
pin output
INTTAB1CC0
signal
INTTAB1OV
signal
N+1
k
i
k
k
k
k
k
N+1
N
M
N
M
0000H
i
k
k
i
0000H
(b) M < N
N+1
N+1
M
16-bit
counter
Transfer
timing
TAB1CCR0
register
CCR0 buffer
register
TAB1CCR1
register
CCR1 buffer
register
i
k
N
M
N
M
0000H
i
0000H
k
k
i
k
TOAB1T1
pin output
INTTAB1CC0
signal
INTTAB1OV
signal
Remarks 1. If transfer (match between the value of the 16-bit counter and the value of the CCR0 buffer
register) occurs in the 6-phase PWM output mode, the value of the TAB1CCR0 register plus 1 is
loaded to the 16-bit counter. In this way, the expected wave can be output even if the cycle value
is changed at the transfer timing of the crest (match between the 16-bit counter value and the
TAB1CCR0 register value) timing.
2. M: Value of CCR0 buffer register before rewriting
N: Value of CCR0 buffer register after rewriting
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Figure 11-29. Example of Rewriting TAB1CCR0 Register (During Counting Down)
M+1
16-bit
counter
i
i
k
N+1
k
k
k
Transfer
timing
TAB1CCR0
register
CCR0 buffer
register
TAB1CCR1
register
CCR1 buffer
register
N
M
M
0000H
k
i
0000H
N
i
k
TOAB1T1
pin output
INTTAB1CC0
signal
INTTAB1OV
signal
Because the next transfer timing is at the point of the valley (match between the 16-bit counter value and
0001H), the cycle value changes from the next cycle and output of a symmetrical triangular wave is
maintained. Because the cycle changes, rewrite the duty value (voltage data value) as required.
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(c) Rewriting TAB1CCRm register
Figure 11-30. Example of Rewriting TAB1CCRm Register
16-bit
counter
r
i
r
k
Transfer
timing
TAB1CCRm
register
CCRm buffer
register
TOAB1Tm
register
INTTAB1CCm
signal
i
0000H
r
k
i
r
k
Rewriting during period (rewriting during counting up)
Because the TAB1CCRm register value is transferred at the transfer timing of the crest (match between the
16-bit counter value and TAB1CCRm register value), an asymmetrical triangular wave is output.
Rewriting during period (rewriting during counting down)
Because the TAB1CCRm register value is transferred at the transfer timing of the valley (match between the
16-bit counter value and 0001H), a symmetrical triangular wave is output.
Remark
m = 1 to 3
(d) Transferring TAB1OPT1 register value
Do not set the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits to other than 00000. When using the interrupt
culling function, rewrite the TAB1OPT1 register in the intermittent batch rewrite mode (transfer culling mode).
For details of rewriting the TAB1OPT1 register, see 11.4.3 Interrupt culling function.
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(3) Intermittent batch rewrite mode (transfer culling mode)
This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0 and setting the TAB1OPT2.TAB1RDE bit to 1.
In this mode, the values written to each compare register are transferred to the internal buffer register all at once
after the culled transfer timing and compared with the counter value. The transfer timing is the timing at which an
interrupt is generated (INTTAB1CC0, INTTAB1OV) by interrupt culling.
For details of the interrupt culling function, see 11.4.3 Interrupt culling function.
(a) Rewriting procedure
If data is written to the TAB1CCR1 register, the data of the TAB1CCR0 to TAB1CCR3, TAB1OPT1, TAA4CCR0,
and TAA4CCR1 registers are transferred all at once to the internal buffer register at the next transfer timing.
Therefore, write to the TAB1CCR1 register last. Writing to the register is prohibited after the TAB1CCR1
register has been written until the transfer timing is generated (until the INTTAB1OV or INTTAB1CC0 interrupt
occurs). The operation procedure is as follows.
Rewrite the TAB1CCR0, TAB1CCR2, TAB1CCR3, TAB1OPT1, TAA4CCR0, and TAA4CCR1 registers.
Do not rewrite registers that do not have to be rewritten.
Rewrite the TAB1CCR1 register.
Rewrite the same value to the register even when it is not necessary to rewrite the TAB1CCR1 register.
Hold the next rewriting pending until the transfer timing is generated.
Perform the next rewrite after the INTTAB1OV or INTTAB1CC0 interrupt has occurred.
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Figure 11-31. Basic Operation in Intermittent Batch Rewrite Mode
16-bit counter
(TAB1)
Transfer
timing
TAB1CCR0
register
CCR0 buffer
register
TAB1CCR1
register
&
CCR1 buffer
register
TAB1CCR2
register
CCR2 buffer
register
TAB1CCR3
register
CCR3 buffer
register
TAB1OPT1
register
OPT1 buffer
register
INTTAB1OV signal
INTTAB1CC0 signal
16-bit counter
(TAA4)
Transfer
timing
TAA4CCR0
register
CCR0 buffer
register
TAA4CCR1
register
CCR1 buffer
register
[TAB1 operation]
Write the TAB1CCR1 register.
Rewrite the register at the transfer timing that is generated after the TAB1CCR1 register has been
rewritten.
The registers are transferred all at once at the transfer timing.
The transfer timing is also culled as the interrupts are culled.
[TAA4 operation]
Write the TAB1CCR1 register.
Rewrite the register at the transfer timing that is generated after the TAB1CCR1 register has been
rewritten.
The registers are transferred all at once at the transfer timing.
The transfer timing is also culled as the interrupts are culled.
Remark
This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 1, TAB1OPT1.TAB1IOE bit =
1, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001.
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(b) Rewriting TAB1CCR0 register
When rewriting the TAB1CCR0 register in the intermittent batch mode, the output waveform differs depending
on where the occurrence of the crest or valley interrupt is specified by the interrupt culling setting. The
following figure illustrates the change of the output waveform when interrupts are culled.
Figure 11-32. Rewriting TAB1CCR0 Register (When Crest Interrupt Is Set)
M
16-bit
counter
i
i
N+1
i
k
k
k
k
Transfer
timing
TAB1CCR0
register
N
M
CCR0 buffer
register
TAB1CCR1
register
i
CCR1 buffer
register
N
M
0000H
0000H
k
i
k
TOAB1T1
pin output
INTTAB1CC0
signal
INTTAB1OV
signal
L
The transfer timing is generated when the crest interrupt occurs, the cycle of counting up and counting down
changes, and an asymmetrical triangular wave is output.
Remarks 1. This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 1, TAB1OPT1.TAB1IOE
bit = 0, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001.
2.
: Culled interrupt
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Figure 11-33. Rewriting TAB1CCR0 Register (When Valley Interrupt Is Set)
M+1
16-bit
counter
M+1
i
i
i
i
k
N+1
k
Transfer
timing
TAB1CCR0
register
N
M
CCR0 buffer
register
TAB1CCR1
register
i
CCR1 buffer
register
N
M
0000H
0000H
k
i
k
TOAB1T1
pin output
INTTAB1CC0
signal
L
INTTAB1OV
signal
The transfer timing is generated when the valley interrupt occurs, the cycle of counting up becomes same as
cycle of counting down, and a symmetrical triangular wave is output.
Remarks 1. This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 0, TAB1OPT1.TAB1IOE
bit = 1, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001.
2.
: Culled interrupt
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(c) Rewriting TAB1CCR1 to TAB1CCR3 registers
• Transfer at crest when crest interrupt is set
Because the register is transferred at the transfer timing of the crest interrupt, an asymmetrical triangular
wave is output.
Figure 11-34. Rewriting TAB1CCR1 Register (TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 0,
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00001)
16-bit
counter
i
i
i
k
Transfer
timing
TAB1CCR1
register
i
CCR1 buffer
register
r
k
i
k
TOAB1T1
pin output
INTTAB1CC0
signal
INTTAB1OV
signal
Transfer at
crest interrupt
Remark
: Culled interrupt
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• Transfer at valley when valley interrupt is set
Because the register is transferred at the transfer timing of the valley interrupt, a symmetrical triangular wave
is output.
Figure 11-35. Rewriting TAB1CCR1 Register (TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1,
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00001)
16-bit
counter
i
i
k
k
Transfer
timing
TAB1CCR1
register
i
CCR1 buffer
register
r
k
i
k
r
TOAB1T1
pin output
INTTAB1CC0
signal
INTTAB1OV
signal
Transfer at
valley interrupt
Remark
Transfer at
valley interrupt
: Culled interrupt
(d) Rewriting TAB1OPT1 register
Because a new interrupt culling value is transferred when the value of the interrupt culling counter matches the
value of the 16-bit counter, the next interrupt and those that follow occur at the set interval.
For details of rewriting the TAB1OPT1 register, see 11.4.3 Interrupt culling function.
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(4) Rewriting TAB1OPT0.TAB1CMS bit
The TAB1CMS bit can select the anytime rewrite mode and batch rewrite mode. This bit can be rewritten during
timer operation (when TAB1CTL0.TAB1CE bit = 1). However, the operation and caution illustrated in Figure 11-36
are necessary.
If the TAB1CCR1 register is written when the TAB1CMS bit is cleared to 0, a transfer request signal (internal signal)
is set.
When the transfer request signal is set, the register is transferred at the next transfer timing, and the transfer
request signal is cleared. This transfer request signal is also cleared when the TAB1CMS bit is set to 1.
Figure 11-36. Rewriting TAB1CMS Bit
16-bit
counter
Transfer
timing
TAB1CCR1
register
CCR1 buffer
register
Write signal of
TAB1CCR1
Transfer
request signal
k
i
0000H
r
i
TAB1CMS bit
s
r
Clear
s
Clear
If the TAB1CCR1 register is rewritten when the TAB1CMS bit is 0, the transfer request signal is set.
If the TAB1CMS bit is set to 1 in this status, the transfer request signal is cleared.
The register is not transferred because the TAB1CMS bit is set to 1 and the transfer request signal is
cleared.
The transfer request signal is not set even if the TAB1CCR1 register is written when the TAB1CMS bit is 1.
The transfer request signal is not set even if the TAB1CCR1 register is written when the TAB1CMS bit is 1,
so even if the TAB1CMS bit is cleared to 0, transfer does not occur at the subsequent transfer timing.
The transfer request signal is set if the TAB1CCR1 register is written when the TAB1CMS bit is 0.
Transfer is performed at the subsequent transfer timing and the transfer request signal is cleared.
Once transfer has been performed, the transfer request signal is cleared. Therefore, transfer is not
performed at the next transfer timing.
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11.4.5 TAA4 tuning operation for A/D conversion start trigger signal output
This section explains the tuning operation of TAA4 and TAB1 in the 6-phase PWM output mode.
In the 6-phase PWM output mode, the tuning operation is performed with TAB1 serving as the master and TAA4 as a
slave. The conversion start trigger signal of the A/D converter can be set as the A/D conversion start trigger source by the
INTTAA4CC0 and INTTAA4CC1 signals of TAA4 and the INTTAB1OV and INTTAB1CC0 signals of TAB1.
(1) Tuning operation starting procedure
The TAA4 and TAB1 registers should be set using the following procedure to perform the tuning operation.
(a) Setting of TAA4 register (stop the operations of TAB1 and TAA4 (by clearing the TAB1CTL0.TAB1CE bit
and TAA4CTL0.TAA4CE bit to 0)).
• Set the TAA4CTL1 register to 85H (set the tuning operation slave mode and free-running timer mode).
• Clear the TAA4OPT0 register to 00H (select the compare register).
• Set an appropriate value to the TAA4CCR0 and TAA4CCR1 registers (set the default value for comparison
for starting the operation).
(b) Setting of TAB1 register
• Set the TAB1CTL1 register to 07H (master mode and 6-phase PWM output mode).
• Set an appropriate value to the TAB1IOC0 register (set the output mode of TOAB1T1 to TOAB1T3).
However, clear the TAB1OL0 bit to 0 and set the TAB1OE0 bit to 1 (enable positive phase output). Unless
this setting is made, the crest interrupt (INTTAB1CC0) and valley interrupt (INTTAB1OV) do not occur.
Consequently, the conversion start trigger signal of the A/D converter is not correctly generated.
• Set the TAB1IOC1 and TAB1IOC2 registers to 00H (the TIAB10 to TIAB13, EVTB1, and TRGB1 pins of TAB1
are not used).
• Clear the TAB1OPT0 register to 00H (select the compare register).
• Set an appropriate value to the TAB1CCR0 to TAB1CCR3 registers (set the default value for comparison for
starting the operation).
• Set the TAB1CTL0 register to 0xH (clear the TAB1CE bit to 0 and set the operating clock of TAB1).
• The operating clock of TAB1 set by the TAB1CTL0 register is also supplied to TAA4, and the count
operation is performed at the same timing. The operating clock of TAA4 set by the TAA4CTL0 register is
ignored.
(c) Setting of TMQOP (TMQ option) register
• Set an appropriate value to the TAB1OPT1 and TAB1OPT2 registers.
• Set an appropriate value to the TAB1IOC3 register (set TOAB1B1 to TOAB1B3 in the output mode).
• Set an appropriate value to the TAB1DTC register (set the default value for comparison for starting the
operation).
(d) Setting of alternate function
• Set the port to alternate function mode using the port control mode setting.
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(e) Set the TAA4CE bit to 1 and set the TAB1CE bit to 1 immediately after that to start the 6-phase PWM
output operation
Rewriting the TAB1CTL0, TAB1CTL1, TAB1IOC1, TAB1IOC2, TAA4CTL0, and TAA4CTL1 registers is prohibited
during operation. The operation and the PWM output waveform are not guaranteed if any of these registers is
rewritten during operation. However, rewriting the TAB1CTL0.TAB1CE bit to clear it is permitted. Manipulating
(reading/writing) the other TAB1, TAA4, and TMQ option registers is prohibited until the TAA4CTL0.TAA4CE bit
is set to 1 and then the TAB1CE bit is set to 1.
(2) Tuning operation clearing procedure
To clear the tuning operation and exit the 6-phase PWM output mode, set the TAA4 and TAB1 registers using the
following procedure.
Clear the TAB1CTL0.TAB1CE bit to 0 and stop the timer operation.
Clear the TAA4CTL0.TAA4CE bit to 0 so that TAA4 can be separated.
Stop the timer output by using the TAB1IOC0 register.
Clear the TAA4CTL1.TAA4SYE bit to 0 to clear the tuning operation.
Caution
Manipulating (reading/writing) the other TAB1, TAA4, and TMQ option registers is prohibited until
the TAB1CE bit is set to 1 and then the TAA4CE bit is set to 1.
(3) When not tuning TAA4
When the match interrupt signal of TAA4 is not necessary as the conversion trigger source that starts the A/D
converter, TAA4 can be used independently as a separate timer without being tuned. In this case, the match
interrupt signal of TAA4 cannot be used as a trigger source to start A/D conversion in the 6-phase PWM output
mode. Therefore, fix the TAB1OPT2.TAB1AT0 to TAB1OPT2.TAB1AT3 bits to 0.
The other control bits can be used in the same manner as when TAA4 is tuned.
If TAA4 is not tuned, the compare registers (TAA4CCR0 and TAA4CCR1) of TAA4 are not affected by the setting of
the TAB1OPT0.TAB1CMS and TAB1OPT2.TAB1RDE bit. For the initialization procedure when TAA4 is not tuned,
see (b) to (e) in 11.4.5 (1) Tuning operation starting procedure. (a) is not necessary because it is a step used to
set TAA4 for the tuning operation.
(4) Basic operation of TAA4 during tuning operation
The 16-bit counter of TAA4 only counts up. The 16-bit counter is cleared by the set cycle value of the TAB1CCR0
register and starts counting from 0000H again. The count value of this counter is the same as the value of the 16bit counter of TAB1 when it counts up. However, it is not the same when the 16-bit counter of TAA4 counts down.
• When TAB1 counts up (same value)
16-bit counter of TAB1: 0000H → M (counting up)
16-bit counter of TAA4: 0000H → M (counting up)
• When TAB1 counts down (not same value)
16-bit counter of TAB1: M + 1 → 0001H (counting down)
16-bit counter of TAA4: 0000H → M (counting up)
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Figure 11-37. TAA4 During Tuning Operation
M+1
16-bit
counter
of TAB1
TAB1CCR0
register
TAB1CCR1
register
TAB1CCR2
register
TAB1CCR3
register
k
M+1
k
j
k
j
k
j
i
i
j
i
i
M (carrier data)
i (phase U data)
j (phase V data)
k (phase W data)
TOAB0T1
pin output (U)
TOAB1B1
pin output (U)
TOAB1T2
pin output (V)
TOAB1B2
pin output (V)
TOAB1T3
pin output (W)
TOAB1B3
pin output (W)
M
M
r
16-bit
counter
of TAA4
TAA4CCR0
register
TAA4CCR1
register
s
M
r
s
r
s
r
s
s (A/D conversion start trigger timing 2)
r (A/D conversion start trigger timing 3)
INTTAA4CC0
signal
INTTAA4CC1
signal
TABTADT0
signal
Note
Note
Note The TABTADT0 signal is masked by the TAB1OPT2.TAB1ATM2 and TAB1OPT2.TAB1ATM3 bits.
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11.4.6 A/D conversion start trigger output function
The V850ES/JG3-H and V850ES/JH3-H have a function to select four trigger sources (INTTAB1OV, INTTAB1CC0,
INTTAA4CC0, INTTAA4CC1) to generate the A/D conversion start trigger signal (TABTADT0).
The trigger sources are specified by the TAB1OPT2.TAB1AT0 to TAB1OPT2.TAB1AT3 bits.
• TAB1AT0 bit = 1:
A/D conversion start trigger signal generated when INTTAB1OV (counter underflow) occurs.
• TAB1AT1 bit = 1:
A/D conversion start trigger signal generated when INTTAB1CC0 (cycle match) occurs.
• TAB1AT2 bit = 1:
A/D conversion start trigger signal generated when INTTAA4CC0 (match of TAA4CCR0 register of TAA4 during
tuning operation) occurs.
• TAB1AT3 bit = 1:
A/D conversion start trigger signal generated when INTTAA4CC1 (match of TAA4CCR1 register of TAA4 during
tuning operation) occurs.
The A/D conversion start trigger signals selected by the TAB1AT0 to TAB1AT3 bits are ORed and output. Therefore, two
or more trigger sources can be specified at the same time.
The INTTAB1OV and INTTAB1CC0 signals selected by the TAB1AT0 and TAB1AT1 bits are culled interrupt signals.
Therefore, these signals are output after the interrupts have been culled and, unless interrupt output is enabled (by the
TAB1OPT1.TAB1ICE and TAB1OPT1.TAB1IOE bits), the A/D conversion start trigger signal is not output.
The trigger sources (INTTAA4CC0 and INTTAA4CC1) from TAA4 have a function to mask the A/D conversion start
trigger signal depending on the count-up/count-down status of the 16-bit counter, if so set by the TAB1AT2 and TAB1AT3
bits.
• TAB1ATM2 bit: Corresponds to the TAB1AT2 bit and controls INTTAA4CC0 (match interrupt signal) of TAA4.
• TAB1ATM2 bit = 0: The A/D conversion start trigger signal is output when the 16-bit counter counts up
(TAB1OPT0.TAB1CUF bit = 0), and the A/D conversion start trigger signal is not output when
the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 1).
• TAB1ATM2 bit = 1: The A/D conversion start trigger signal is output when the 16-bit counter counts up
(TAB1OPT0.TAB1CUF bit = 1), and the A/D conversion start trigger signal is not output when
the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 0).
• TAB1ATM3 bit: Corresponds to the TAB1AT3 bit and controls INTTAA4CC1 (match interrupt signal) of TAA4.
• TAB1ATM3 bit = 0: The A/D conversion start trigger signal is output when the 16-bit counter counts up
(TAB1OPT0.TAB1CUF bit = 0), and the A/D conversion start trigger signal is not output when
the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 1).
• TAB1ATM3 bit = 1: The A/D conversion start trigger signal is output when the 16-bit counter counts up
(TAB1OPT0.TAB1CUF bit = 1), and the A/D conversion start trigger signal is not output when
the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 0).
The TAB1ATM3, TAB1ATM2, and TAB1AT3 to TAB1AT0 bits can be rewritten while the timer is operating. If the bit that
sets the A/D conversion start trigger signal is rewritten while the timer is operating, the new setting is immediately reflected
in the output status of the A/D conversion start trigger signal. These control bits do not have a transfer function and can be
used only in the anytime rewrite mode.
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Cautions 1. The A/D conversion start trigger signal output that is set by the TAB1AT2 and TAB1AT3 bits can be
used only when TAA4 is performing a tuning operation as the slave timer of TAB1. If TAB1 and
TAA4 are not performing a tuning operation, or if a mode other than the 6-phase PWM output
mode is used, the output cannot be guaranteed.
2. The TAB1 signal output is internally used to identify whether the 16-bit counter is counting up or
down. Therefore, enable TOAB10 pin output by clearing the TAB1IOC0.TAB1OL0 bit to 0 and
setting the TAB1IOC0.TAB1OE0 bit to 1.
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Figure 11-38. Example of A/D Conversion Start Trigger (TABTADT0) Signal Output
(TAB1OPT1.TAB1ICE Bit = 1, TAB1OPT1.TAB1IOE Bit = 1,
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00000: Without Interrupt Culling)
16-bit
counter
INTTAB1CC0 signal
INTTAB1OV signal
INTTAA4CC0 signal
INTTAA4CC1 signal
TAB1CUF bit
TAB1AT3 to TAB1AT0 bits = 0001 (INTTAB1OV signal output)
TABTADT0 signal
TAB1AT3 to TAB1AT0 bits = 0010 (INTTAB1CC0 signal output)
TABTADT0 signal
TAB1AT3 to TAB1AT0 bits = 0100, TAB1ATM2 bit = 0 (INTTAA4CC0 signal output during counting up)
TABTADT0 signal
TAB1AT3 to TAB1AT0 bits = 0100, TAB1ATM2 bit = 1 (INTTAA4CC0 signal output during counting down)
TABTADT0 signal
TAB1AT3 to TAB1AT0 bits = 1000, TAB1ATM3 bit = 0 (INTTAA4CC1 signal output during counting up)
TABTADT0 signal
TAB1AT3 to TAB1AT0 bits = 1000, TAB1ATM3 bit = 1 (INTTAA4CC1 signal output during counting down)
TABTADT0 signal
TAB1AT3 to TAB1AT0 bits = 0011 (setting to output A/D conversion start trigger signal when both crest and valley interrupts occur)
TABTADT0 signal
TAB1AT3 to TAB1AT0 bits = 1100, TAB1ATM3 bit = 1, TAB1ATM2 bit = 0 (INTTAA4CC0 and INTTAA4CC1 signals ORed for output.
Setting to output A/D conversion start trigger signal when match interrupt of TAA4 occurs when counter is counting up or down)
TABTADT0 signal
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Figure 11-39. Example of A/D Conversion Start Trigger (TABTADT0) Signal Output
(TAB1OPT1.TAB1ICE Bit = 0, TAB1OPT1.TAB1IOE Bit = 1,
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00010: With Interrupt Culling) (1)
16-bit
counter
INTTAB1CC0 signal
L
INTTAB1OV signal
TAB1AT3 to TAB1AT0 bits = 0011 (both INTTAB1CC0 and INTTAB1OV signals are selected but
crest interrupt (INTTAB1CC0) is not output because interrupt culling is not specified)
TABTADT0 signal
Remark
: Culled interrupt
Figure 11-40. Example of A/D Conversion Start Trigger (TABTADT0) Signal Output
(TAB1OPT1.TAB1ICE Bit = 0, TAB1OPT1.TAB1IOE Bit = 1,
TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 Bits = 00010: With Interrupt Culling) (2)
16-bit
counter
INTTAB1CC0 signal
L
INTTAB1OV signal
INTAA4CC0 signal
INTAA4CC1 signal
TAB1CUF bit
TAB1AT3 to TAB1AT0 bits = 0101, TAB1ATM2 bit = 1
TABTADT0 signal
Caution
Remark
The INTTAB1CC0 signal is culled but the INTTAA4CC0 signal is not.
: Culled interrupt
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(1) Operation under boundary condition (operation when 16-bit counter matches INTTAA4CC0 signal)
Table 11-3. Operation When TAB1CCR0 Register = M, TAB1AT2 Bit = 1, TAB1ATM2 Bit = 0
(Counting Up Period Selected)
Value of TAA4CCR0
Value of 16-Bit
Value of 16-Bit
Status of 16-Bit
TABTADT0 Signal Output
Register
Counter of TAB1
Counter of TAA4
Counter of TAB1
by INTTAA4CC0 Signal
0000H
0000H
0000H
−
Output
0000H
M+1
0000H
−
Not output
0001H
0001H
0001H
Count-up
Output
0001H
M
0001H
Count-down
Not output
M
M
M
Count-up
Output
M
0001H
M
Count-down
Not output
Table 11-4. Operation When TAB1CCR0 Register = M, TAB1AT2 Bit = 1, TAB1ATM2 Bit = 1
(Counting Down Period Selected)
Value of TAA4CCR0
Value of 16-Bit
Value of 16-Bit
Status of 16-Bit
TABTADT0 Signal Output
Register
Counter of TAB1
Counter of TAA4
Counter of TAB1
by INTTAA4CC0 Signal
0000H
0000H
0000H
−
Not output
0000H
M+1
0000H
−
Output
0001H
0001H
0001H
Count-up
Not output
0001H
M
0001H
Count-down
Output
M
M
M
Count-up
Not output
M
0001H
M
Count-down
Output
Caution The TAA4CCRm register enables the setting of “0” to “M” when the TAB1CCR0 register = M. Setting a
value of “M + 1” or higher is prohibited.
If a value of “M + 1” or higher is set, the 16-bit counter of TAA4 is cleared by “M”. Therefore, the
TABTADT0 signal is not output.
Remark
m = 0, 1
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CHAPTER 12 REAL-TIME COUNTER
CHAPTER 12 REAL-TIME COUNTER
12.1 Functions
The real-time counter (RTC) has the following features.
• Counting up to 99 years using year, month, day-of-week, day, hour, minute, and second sub-counters provided
• Year, month, day-of-week, day, hour, minute, and second counter display using BCD codesNote 1
• Alarm interrupt function
• Constant-period interrupt function (period: 1 month to 0.5 second)
• Interval interrupt function (period: 1.95 ms to 125 ms)
• Pin output function of 1 Hz
• Pin output function of 32.768 kHz
• Pin output function of 512 Hz or 16.384 kHz
• Watch error correction function
• Subclock operation or main clock operationNote 2 selectable
Notes 1. A BCD (binary coded decimal) code expresses each digit of a decimal number in 4-bit binary format.
2. Use the baud rate generator dedicated to the real-time counter to divide the main clock frequency to 32.768
kHz for use.
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12.2 Configuration
The real-time counter includes the following hardware.
Table 12-1. Configuration of Real-Time Counter
Item
Control registers
Configuration
Real-time counter control register 0 (RC1CC0)
Real-time counter control register 1 (RC1CC1)
Real-time counter control register 2 (RC1CC2)
Real-time counter control register 3 (RC1CC3)
Sub-count register (RC1SUBC)
Second count register (RC1SEC)
Minute count register (RC1MIN)
Hour count register (RC1HOUR)
Day count register (RC1DAY)
Day-of-week count register (RC1WEEK)
Month count register (RC1MONTH)
Year count register (RC1YEAR)
Watch error correction register (RC1SUBU)
Alarm minute register (RC1ALM)
Alarm hour register (RC1ALH)
Alarm week register (RC1ALW)
Prescaler mode register 0 (PRSM0)
Prescaler compare register 0 (PRSCM0)
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CHAPTER 12 REAL-TIME COUNTER
Figure 12-1. Block Diagram of Real-Time Counter
CLOE1
RTC1HZ
Hour
alarm
Minute
alarm
Day-of-week
alarm
Selector
INTRTC1
Count clock
= 32.768 kHz
Selector
fBRGNote
fXT
1 minute
Second
counter
(7-bit)
Sub-counter
(16-bit)
1 hour
Minute
counter
(7-bit)
1 month
1 day
Day
counter
(3-bit)
Hour
counter
(6-bit)
INTRTC0
Day-of week
counter
(3-bit)
Month
counter
(5-bit)
Year
counter
(8-bit)
Count enable/
disable circuit
Second
counter
write buffer
Minute
counter
write buffer
Hour
counter
write buffer
Day
counter
write buffer
Week
counter
write buffer
Month
counter
write buffer
Year
counter
write buffer
ICT2 to ICT0
fXT/26
fXT/2
INTRTC2
CKDIV
Selector
fXT/211
fXT/210
fXT/29
fXT/28
fXT/27
fXT/26
RINTE
Selector
12-bit counter
fXT/212
CLOE2
RTCDIV
CLOE0
RTCCL
Note For detail of fBRG, refer to 12.3 (17) Prescaler mode register 0 (PRSM0) and 12.3 (18) Prescaler compare
register 0 (PRSCM0).
Remark
fBRG:
Real-time counter count clock frequency
fXT:
Subclock frequency
INTRTC0: Real-time counter fixed-cycle interrupt signal
INTRTC1: Real-time counter alarm match interrupt signal
INTRTC2: Real-time counter interval interrupt signal
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12.2.1 Pin configuration
The RTC outputs included in the real-time counter are alternatively used as shown in Table 12-2. The port function
must be set when using each pin (see Table 4-20 Using Port Pin as Alternate-Function Pin).
Table 12-2. Pin Configuration
Port
Pin Number
RTC Output
Other Alternate Function
V850ES/JG3-H
V850ES/JH3-H
30
42
P35
RTC1HZ
TIAA11/TOAA11
28
40
P33
RTCDIV
TIAA01/TOAA01/RTCCL
28
40
P33
RTCCL
TIAA01/TOAA01/RTCDIV
12.2.2 Interrupt functions
The RTC includes the following three types of interrupt signals.
(1) INTRTC0
A fixed-cycle interrupt signal is generated every 0.5 second, second, minute, hour, day, or month.
(2) INTRTC1
Alarm interrupt signal
(3) INTRTC2
An interval interrupt signal of a cycle of fXT/26, fXT/27, fXT/28, fXT/29, fXT/210, fXT/211, or fXT/212 is generated.
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12.3 Registers
The real-time counter is controlled by the following 18 registers.
(1) Real-time counter control register 0 (RC1CC0)
The RC1CC0 register selects the real-time counter input clock.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
7
RC1CC0
R/W
6
RC1PWR RC1CKS
Address: FFFFFADDH
5
4
0
RC1PWR
0
3
2
1
0
0
0
0
0
Real-time counter operation control
0
Stops real-time counter operation.
1
Enables real-time counter operation.
RC1CKS
Operation clock selection
0
Selects fXT as operation clock.
1
Selects fBRG as operation clock.
Cautions 1. Follow the description in 12.4.8 Initializing real-time counter when stopping (RC1PWR =
1 → 0) the real-time counter while it is operating.
2. The RC1CKS bit can be rewritten only when the real-time counter is stopped (RC1PWR
bit = 0). Furthermore, rewriting the RC1CKS bit at the same time as setting the RC1PWR
bit from 0 to 1 is prohibited.
(2) Real-time counter control register 1 (RC1CC1)
The RC1CC1 register is an 8-bit register that starts or stops the real-time counter, controls the RTCCL and
RTC1HZ pins, selects the 12-hour or 24-hour system, and sets the fixed-cycle interrupt function.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
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After reset: 00H
7
RC1CC1
RTCE
CHAPTER 12 REAL-TIME COUNTER
R/W
6
0
Address: FFFFFADEH
5
3
2
1
0
AMPM
CT2
CT1
CT0
4
CLOE1
RCTE
CLOE0
Control of operation of each counter
0
Stops counter operation.
1
Enables counter operation.
CLOE1
RTC1HZ pin output control
0
Disables RTC1HZ pin output (1 Hz)
1
Enables RTC1HZ pin output (1 Hz)
CLOE0
RTCCL pin output control
0
Disables RTCCL pin output (32.768 kHz)
1
Enables RTCCL pin output (32.768 kHz)
AMPM
12-hour system/24-hour system selection
0
12-hour system (a.m. and p.m. are displayed.)
1
24-hour system
CT2
CT1
CT0
0
0
0
Does not use fixed-cycle interrupts
0
0
1
Once in 0.5 second (synchronous with second count-up)
0
1
0
Once in 1 second (simultaneous with second count-up)
0
1
1
Once in 1 minute (every minute at 00 seconds)
1
0
0
Once in 1 hour (every hour at 00 minutes 00 seconds)
1
0
1
Once in 1 day (every day at 00 hours 00 minutes 00 seconds)
1
1
×
Once in 1 month (one day every month at 00 hours
00 minutes 00 seconds a.m.)
Fixed-cycle interrupt (INTRTC0) selection
Cautions 1. Writing 0 to the RTCE bit while the RTCE bit is 1 is prohibited. Clear the RTCE bit by
clearing the RC1PWR bit according to 12.4.8 Initializing real-time counter.
2. The RTC1HZ output operates as follows when the CLOE1 bit setting is changed.
• When changed from 0 to 1: The RTC1HZ output outputs a 1 Hz pulse after two clocks
(2 x 32.768 kHz) or less.
• When changed from 1 to 0: The RTC1HZ output is stopped (fixed to low level) after
two clocks (2 x 32.768 kHz) or less.
3. See 12.4.1 Initial settings and 12.4.2 Rewriting each counter during the real-time counter
operation for setting or changing the AMPM bit.
Furthermore, re-set the RC1HOUR
register when the AMPM bit is rewritten.
4. See 12.4.4 Changing INTRTC0 interrupt setting during the real-time counter operation
when rewriting the CT2 to CT0 bits while the real-time counter operates (RC1PWR bit =
1).
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(3) Real-time counter control register 2 (RC1CC2)
The RC1CC2 register is an 8-bit register that controls the alarm interrupt function and waiting of counters.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
7
RC1CC2
WALE
WALE
R/W
6
0
Address: FFFFFADFH
5
4
0
0
3
2
1
0
0
0
RWST
RWAIT
Alarm interrupt (INTRTC1) operation control
0
Does not generate interrupt upon alarm match.
1
Generates interrupt upon alarm match.
RWST
Real-time counter wait state
0
Counter operating
1
Counting up of second to year counters stopped
(Reading and writing of counter values enabled)
This is a status flag indicating whether the RWAIT bit setting is valid.
Read or write counter values after confirming that the RWST bit is 1.
RWAIT
Real-time counter wait control
0
Sets counter operation.
1
Stops count operation of second to year counters.
(Counter value read/write mode)
This bit controls the operation of the counters.
Be sure to write 1 to this bit when reading or writing counter values.
If the RC1SUBC register overflows while the RWAIT bit is 1, the overflow
information is retained internally and the RC1SEC register is counted up after two
clocks or less after 0 is written to the RWAIT bit.
However, if the second counter value is rewritten while the RWAIT bit is 1, the
retained overflow information is discarded.
Cautions 1. See 12.4.5 Changing INTRTC1 interrupt setting during the real-time counter operation
when rewriting the WALE bit while the real-time counter operates (RC1PWR bit = 1).
2. Confirm that the RWST bit is set to 1 when reading or writing each counter value.
3. The RWST bit does not become 0 while each counter is being written, even if the RWAIT
bit is set to 0. It becomes 0 when writing to each counter is completed.
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CHAPTER 12 REAL-TIME COUNTER
(4) Real-time counter control register 3 (RC1CC3)
The RC1CC3 register is an 8-bit register that controls the interval interrupt function and RTCDIV pin.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
7
RC1CC3
RINTE
R/W
6
CLOE2
Address: FFFFFAE0H
5
4
CKDIV
RINTE
0
3
2
1
0
0
ICT2
ICT1
ICT0
Interval interrupt (INTRTC2) control
0
Does not generate interval interrupt.
1
Generates interval interrupt.
CLOE2
RTCDIV pin output control
0
Disables RTCDIV pin output.
1
Enables RTCDIV pin output.
CKDIV
RTCDIV pin output frequency selection
0
Outputs 512 Hz (1.95 ms) from RTCDIV pin.
1
Outputs 16.384 kHz (0.061 ms) from RTCDIV pin.
ICT2
ICT1
Interval interrupt (INTRTC2) selection
ICT0
6
0
0
0
2 /fXT (1.953125 ms)
0
0
1
27/fXT (3.90625 ms)
0
1
0
28/fXT (7.8125 ms)
0
1
1
29/fXT (15.625 ms)
1
0
0
210/fXT (31.25 ms)
1
0
1
211/fXT (62.5 ms)
1
1
×
212/fXT (125 ms)
Cautions 1. See 12.4.7 Changing INTRTC2 interrupt setting during the real-time counter operation
when rewriting the RINTE bit during real-time counter operation (RC1PWR bit = 1).
2. The RTCDIV output operates as follows when the CLOE2 bit setting is changed.
• When changed from 0 to 1: A pulse set by the CKDIV bit is output after two clocks (2 x
32.768 kHz) or less.
• When changed from 1 to 0: Output of the RTCDIV output is stopped after two clocks (2
x 32.768 kHz) or less (fixed to low level).
3. See 12.4.7 Changing INTRTC2 interrupt setting during the real-time counter operation
when rewriting the ICT2 to ICT0 bits while the real-time counter operates (RC1PWR bit =
1).
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CHAPTER 12 REAL-TIME COUNTER
(5) Sub-count register (RC1SUBC)
The RC1SUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter.
It takes a value of 0000H to 7FFFH and counts one second with a clock of 32.768 kHz.
This register is read-only, in 16-bit units.
Reset sets this register to 0000H.
Cautions 1 When a correction is made by using the RC1SUBU register, the value may become 8000H
or more.
2. This register is also cleared by writing to the second count register.
3. The value read from this register is not guaranteed if it is read during operation, because a
changing value is read.
After reset: 0000H
14
15
R
13
12
Address:
11
10
FFFFFAD0H
9
8
7
6
5
4
3
2
1
0
RC1SUBC
(6) Second count register (RC1SEC)
The RC1SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of
seconds.
It counts up when the sub-counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 x 32.768 kHz)
later. Set a decimal value of 00 to 59 to this register in BCD code.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution
Setting the RC1SEC register to values other than 00 to 59 is prohibited.
Remark
See 12.4.1 Initial settings, 12.4.2 Rewriting each counter during real-time counter operation, and
12.4.3 Reading each counter during real-time counter operation when reading or writing the
RC1SEC register.
After reset: 00H
RC1SEC
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R/W
Address: FFFFFAD2H
0
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CHAPTER 12 REAL-TIME COUNTER
(7) Minute count register (RC1MIN)
The RC1MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of
minutes.
It counts up when the second counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later.
Set a decimal value of 00 to 59 to this register in BCD code.
This register can be read or written 8-bit units.
Reset sets this register to 00H.
Caution
Remark
Setting a value other than 00 to 59 to the RC1MIN register is prohibited.
See 12.4.1 Initial settings, 12.4.2 Rewriting each counter during real-time counter operation, and
12.4.3 Reading each counter during real-time counter operation when reading or writing the
RC1MIN register.
After reset: 00H
RC1MIN
R/W
Address: FFFFFAD3H
0
(8) Hour count register (RC1HOUR)
The RC1HOUR register is an 8-bit register that takes a value of 0 to 23 or 1 to 12 (decimal) and indicates the count
value of hours.
It counts up when the minute counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later.
Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code.
This register can be read or written 8-bit units.
Reset sets this register to 12H.
However, the value of this register is 00H if the AMPM bit is set to 1 after reset.
Cautions 1. Bit 5 of the RC1HOUR register indicates a.m. (0) or p.m. (1) if AMPM = 0 (if the 12-hour
system is selected).
2. Setting a value other than 01 to 12, 21 to 32 (AMPM bit= 0), or 00 to 23 (AMPM bit = 1) to
the RC1HOUR register is prohibited.
Remark
See 12.4.1 Initial settings, 12.4.2 Rewriting each counter during real-time counter operation, and
12.4.3 Reading each counter during real-time counter operation when reading or writing the
RC1HOUR register.
After reset: 12H
RC1HOUR
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0
R/W
Address: FFFFFAD4H
0
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CHAPTER 12 REAL-TIME COUNTER
Table 12-3 shows the relationship among the AMPM bit setting value, RC1HOUR register value, and time.
Table 12-3. Time Digit Display
12-Hour Display (AMPM Bit = 0)
24-Hour Display (AMPM Bit = 1)
Time
Time
RC1HOUR Register Value
RC1HOUR Register Value
0:00 a.m.
12 H
0:00
00H
1:00 a.m.
01 H
1:00
01 H
2:00 a.m.
02 H
2:00
02 H
3:00 a.m.
03 H
3:00
03 H
4:00 a.m.
04 H
4:00
04 H
5:00 a.m.
05 H
5:00
05 H
6:00 a.m.
06 H
6:00
06 H
7:00 a.m.
07 H
7:00
07 H
8:00 a.m.
08 H
8:00
08 H
9:00 a.m.
09 H
9:00
09 H
10:00 a.m.
10 H
10:00
10 H
11:00 a.m.
11 H
11:00
11 H
0:00 p.m.
32 H
12:00
12 H
1:00 p.m.
21 H
13:00
13 H
2:00 p.m.
22 H
14:00
14 H
3 :00 p.m.
23 H
15:00
15 H
4:00 p.m.
24 H
16:00
16 H
5:00 p.m.
25 H
17:00
17 H
6:00 p.m.
26 H
18:00
18 H
7:00 p.m.
27 H
19:00
19 H
8:00 p.m.
28 H
20:00
20 H
9:00 p.m.
29 H
21:00
21 H
10:00 p.m.
30 H
22:00
22 H
11:00 p.m.
31 H
23:00
23 H
The RC1HOUR register value is displayed in 12 hour-format if the AMPM bit is 0 and in 24-hour format when the
AMPM bit is 1.
In 12-hour display, a.m. or p.m. is indicated by the fifth bit of RCHOUR: 0 indicating before noon (a.m.) and 1
indicating noon or afternoon (p.m.).
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CHAPTER 12 REAL-TIME COUNTER
(9) Day count register (RC1DAY)
The RC1DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of
days.
It counts up when the hour counter overflows.
This counter counts as follows.
• 01 to 31 (January, March, May, July, August, October, December)
• 01 to 30 (April, June, September, November)
• 01 to 29 (February in leap year)
• 01 to 28 (February in normal year)
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 x 32.768 kHz)
later. Set a decimal value of 00 to 31 to this register in BCD code.
This register can be read or written in 8-bit units.
Reset sets this register to 01H.
Caution
Setting a value other than 01 to 31 to the RC1DAY register is prohibited. Setting a value outside
the above-mentioned count range, such as “February 30” is also prohibited.
Remark
See 12.4.1 Initial settings, 12.4.2 Rewriting each counter during the real-time counter operation,
and 12.4.3 Reading each counter during the real-time counter operation when reading or writing the
RC1DAY register.
After reset: 01H
RC1DAY
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0
R/W
Address: FFFFFAD6H
0
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CHAPTER 12 REAL-TIME COUNTER
(10) Day-of-week count register (RC1WEEK)
The RC1WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the day-of-week
count value.
It counts up in synchronization with the day counter.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 x 32.768 kHz)
later. Set a decimal value of 00 to 06 to this register in BCD code. If a value outside this range is set, the register
value returns to the normal value after 1 period.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
After reset: 00H
RC1WEEK
0
R/W
0
Address: FFFFFAD5H
0
0
0
Cautions 1. Setting a value other than 00 to 06 to the RC1WEEK register is prohibited.
2. Values corresponding to the month count register and day count register are not
automatically stored to the day-of-week register.
Be sure to set as follows after rest release.
Remark
Day of Week
RC1WEEK
Sunday
00H
Monday
01H
Tuesday
02H
Wednesday
03H
Thursday
04H
Friday
05H
Saturday
06H
See 12.4.1 Initial settings, 12.4.2 Rewriting each counter during real-time counter operation, and
12.4.3 Reading each counter during real-time counter operation when reading or writing the
RC1WEEK register.
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CHAPTER 12 REAL-TIME COUNTER
(11) Month count register (RC1MONTH)
The RC1MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value
of months.
It counts up when the day counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 x 32.768 kHz)
later. Set a decimal value of 01 to 12 to this register in BCD code.
This register can be read or written in 8-bit units.
Reset sets this register to 01H.
Caution
Setting a value other than 01 to 12 to the RC1MONTH register is prohibited.
Remark
See 12.4.1 Initial settings, 12.4.2 Rewriting each counter during the real-time counter operation,
and 12.4.3 Reading each counter during the real-time counter operation when reading or writing
the RC1MONTH register.
After reset: 01H
RC1MONTH
R/W
0
0
Address: FFFFFAD7H
0
(12) Year count register (RC1YEAR)
The RC1YEAR register is an 8-bit register that takes a value of 0 to 99 (decimal) and indicates the count value of
years.
It counts up when the month counter overflows.
Values 00, 04, 08, …, 92, and 96 indicate a leap year.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (2 x 32.768 kHz)
later. Set a decimal value of 00 to 99 to this register in BCD code.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution
Setting a value other than 00 to 99 to the RC1YEAR register is prohibited.
Remark
See 12.4.1 Initial settings, 12.4.2 Rewriting each counter during the real-time counter operation,
and 12.4.3 Reading each counter during the real-time counter operation when reading or writing
the RC1YEAR register.
After reset: 00H
R/W
Address: FFFFFAD8H
RC1YEAR
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CHAPTER 12 REAL-TIME COUNTER
(13) Watch error correction register (RC1SUBU)
The RC1SUBU register (8-bit) can be used to correct the watch with high accuracy when the watch is early or late,
by changing the value (reference value: 7FFFH) overflowing from the sub-count register (RSUBC) to the second
counter register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Remarks 1. The RC1SUBU register can be rewritten only when the real-time counter is set to its initial values.
Be sure to see 12.4.1 Initial settings.
2. See 12.4.9 Watch error correction example of real-time counter for details of watch error
correction.
After reset: 00H
RC1SUBU
R/W
Address: FFFFFAD9H
7
6
5
4
3
2
1
0
DEV
F6
F5
F4
F3
F2
F1
F0
DEV
Setting of watch error correction timing
0
Corrects watch errors when RC1SEC (second counter) is at 00, 20, or
40 seconds (every 20 seconds).
1
Corrects watch errors when RC1SEC (second counter) is at 00 seconds
(every 60 seconds).
F6
Setting of watch error correction value
0
Increments the RC1SUBC count value by the value set using the F5 to
F0 bits (positive correction).
Expression for calculating increment value:
(Setting value of F5 to F0 bits − 1) × 2
1
Decrements the RC1SUBC count value by the value set using the F5 to
F0 bits (negative correction).
Expression for calculating decrement value:
(Inverted value of setting value of F5 to F0 bits + 1) × 2
If the F6 to F0 bit values are {1/0, 0, 0, 0, 0, 0, 1/0}, watch error correction is not
performed.
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CHAPTER 12 REAL-TIME COUNTER
(14) Alarm minute setting register (RC1ALM)
The RC1ALM register (8-bit) is used to set minutes of alarm.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution
Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set,
the alarm is not detected.
After reset: 00H
RC1ALM
R/W
Address: FFFFFADAH
0
(15) Alarm hour setting register (RC1ALH)
The RC1ALH register (8-bit) is used to set hours of alarm.
This register can be read or written in 8-bit units.
Reset sets this register to 12H.
Cautions 1. Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a value
outside the range is set, the alarm is not detected.
2. Bit 5 of the RC1ALH register indicates a.m. (0) or p.m. (1) if the AMPM bit = 0 (12-hour
system) is selected.
After reset: 12H
RC1ALH
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0
R/W
Address: FFFFFADBH
0
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CHAPTER 12 REAL-TIME COUNTER
(16) Alarm day-of-week setting register (RC1ALW)
The RC1ALW register is used to set the day-of-week of the alarm.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution
See 12.4.5 Changing INTRTC1 interrupt setting during the real-time counter operation when
rewriting the RC1ALW register while the real-time counter operates (RC1PWR bit = 1).
After apply power to RVDD: 00H
RC1ALW
0
RC1ALWn
R/W
Address: FFFFFADCH
RC1ALW6 RC1ALW5 RC1ALW4 RC1ALW3 RC1ALW2 RC1ALW1 RC1ALW0
Alarm interrupt day-of-week bit (n = 0 to 6)
0
Does not generate alarm interrupt if RC1WEEK = nH.
1
Generates an alarm interrupt if the time specified by using the RC1ALM
and RC1ALH registers is reached while RC1WEEK is set to nH.
Remark The relationship between the day-of-week and the RC1WEEK register is described below.
Day of Week
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RC1WEEK
Sunday
00H
Monday
01H
Tuesday
02H
Wednesday
03H
Thursday
04H
Friday
05H
Saturday
06H
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CHAPTER 12 REAL-TIME COUNTER
(a) Alarm interrupt setting examples (RC1ALM, RC1ALH, and RC1ALW setting examples)
Tables 12-4 and 12-5 show setting examples if Sunday is RC1WEEK = 00, Monday is RC1WEEK = 01,
Tuesday is RC1WEEK = 02, ···, and Saturday is RC1WEEK = 06.
Table 12-4. Alarm Setting Example if AMPM = 0 (RC1HOUR Register 12-Hour Display)
Register
RC1ALW
RC1ALH
RC1ALM
01H
07H
00H
Alarm Setting Time
Sunday, 7:00 a.m.
Sunday/Monday, 00:15 p.m.
03H
32H
15H
Monday/Tuesday/Friday, 5:30 p.m.
26H
25H
30H
Everyday, 10:45 p.m.
7FH
30H
45H
Table 12-5. Alarm Setting Example if AMPM = 1 (RC1HOUR Register 24-Hour Display)
Register
RC1ALW
RC1ALH
RC1ALM
Sunday, 7:00
01H
07H
00H
Sunday/Monday, 12:15
03H
12H
15H
Monday/Tuesday/Friday, 17:30
26H
17H
30H
Everyday, 22:45
7FH
22H
45H
Alarm Setting Time
(17) Prescaler mode register 0 (PRSM0)
The PRSM0 register (8-bit) controls the generation of the real time counter count clock (fBRG).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset : 00H
R/W
Address : FFFFF8B0H
< >
PRSM0
0
0
0
BGCE0
0
0
BGCS01 BGCS00
Main clock operation enable
0
Disabled
1
Enabled
BGCS01 BGCS00
Cautions 1.
BGCE0
Selection of real time counter source clock(fBGCS)
5 MHz
4 MHz
0
0
fX
200 ns
250 ns
0
1
fX/2
400 ns
500 ns
1
0
fX/4
800 ns
1 μs
1
1
fX/8
1.6 μs
2 μs
Do not change the values of the BGCS00 and BGCS01 bits during real time
counteroperation.
2.
Set the PRSM0 register before setting the BGCE0 bit to 1.
3.
Set the PRSM0 and PRSCM0 registers according to the main clock frequency that is used
so as to obtain an fBRG frequency of 32.768 kHz.
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CHAPTER 12 REAL-TIME COUNTER
(18) Prescaler compare register 0 (PRSCM0)
The PRSCM0 register is an 8-bit compare register.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
After reset: 00H
PRSCM0
R/W
Address: FFFFF8B1H
PRSCM07 PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00
Cautions 1. Do not rewrite the PRSCM0 register during real time counter operation.
2. Set the PRSCM0 register before setting the PRSM0.BGCE0 bit to 1.
3. Set the PRSM0 and PRSCM0 registers according to the main clock frequency that is used
so as to obtain an fBRG frequency of 32.768 kHz.
The calculation for fBRG is shown below.
fBRG = fBGCS/2N
Remark
fBGCS:
Watch timer source clock set by the PRSM0 register
N:
Set value of the PRSCM0 register = 1 to 256
However, N = 256 when the PRSCM0 register is set to 00H.
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CHAPTER 12 REAL-TIME COUNTER
12.4 Operation
12.4.1 Initial settings
The initial settings are set when operating the watch function and performing a fixed-cycle interrupt operation.
Figure 12-2. Initial Setting Procedure
Start
RC1CC0.RC1PWR bit = 0
Setting RC1CKS
RC1CC0.RC1PWR bit = 1
Setting AMPM and CT2 to CT0
Setting RC1SUBU
Selects real-time counter (RTC) operation clock.
Enables real-time counter (RTC) internal clock operation.
Selects 12-hour system or 24-hour system and interrupt (INTRTC0).
Sets watch error correction.
Setting RC1SEC
(Clearing RC1SUBC)
Setting RC1MIN
Setting RC1HOUR
Setting RC1WEEK
Setting RC1DAY
Setting RC1MONTH
Setting RC1YEAR
Sets each count register.
Clearing interrupt IF flag
Clears interrupt request flag (RTC0IF)
Clearing interrupt MK flag
Clears interrupt mask flag (RTC0MK)
RC1CC1.RTCE bit = 1
No
Stops counter operation.
Starts counter operation.
INTRTC = 1?
Yes
Reading counter
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12.4.2 Rewriting each counter during the real-time counter operation
Set as follows when rewriting each counter (RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH,
RC1YEAR) during the real-time counter operation (RC1PWR = 1, RTCE = 1).
Figure 12-3. Rewriting Each Counter During The real-time counter Operation
Start
No
RWST = 0?
Checks whether previous writing to
RC1SEC to RC1YEAR counters is completed.
Yes
RWAIT = 1
No
RWST = 1?Note
Stops RC1SEC to RC1YEAR counters.
Counter value write mode
Checks counter wait status.
Yes
Setting AMPM
Writing RC1SEC
Writing RC1MIN
Writing RC1HOUR
Writing RC1WEEK
Writing RC1DAY
Writing RC1MONTH
Setting RC1YEAR
RWAIT = 0
Selects watch counter display method.
Writes to each count register.
Sets RC1SEC to RC1YEAR counter operation.
End
Note Be sure to confirm that RWST = 0 before setting STOP mode.
Caution
Complete the series of operations for setting RWAIT to 1 to clearing RWAIT to 0 within 1
second.
If RWAIT = 1 is set, the operation of RC1SEC to RC1YEAR is stopped. If a carry occurs from
RC1SUBC while RWAIT = 1, one carry can be internally retained. However, if two or more
carries occur, the number of carries cannot be retained.
Remark
RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, and RC1YEAR may berewrite
in any sequence.
All the registers do not have to be set and only some registers may be read.
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CHAPTER 12 REAL-TIME COUNTER
12.4.3 Reading each counter during the real-time counter operation
Set as follows when reading each counter (RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH,
RC1YEAR) during real-time counter operation (RC1PWR = 1).
Figure 12-4. Reading Each Counter During The real-time counter Operation
Start
No
RC1CC2.RWST bit = 0?
Checks whether previous writing to RC1SEC to
RC1YEAR is completed.
Yes
No
RC1CC2.RWAIT bit = 1
Stops RC1SEC to RC1YEAR counters.
Counter value write/read mode
RC1CC2.RWST bit = 1?Note
Checks counter wait status.
Yes
Reading RC1SEC
Reading RC1MIN
Reading RC1HOUR
Reading RC1WEEK
Reading RC1DAY
Reading RC1MONTH
Setting RC1YEAR
Reads each count register.
RC1CC2.RWAIT bit = 0
Sets RC1SEC to RC1YEAR counter operation.
End
Note Be sure to confirm that RWST = 0 before setting STOP mode.
Caution
Complete the series of operations for setting RWAIT to 1 to clearing RWAIT to 0 within 1
second.
If RWAIT = 1 is set, the operation of RC1SEC to RC1YEAR is stopped. If a carry occurs from
RC1SUBC while RWAIT = 1, one carry can be internally retained. However, if two or more
carries occur, the number of carries cannot be retained.
Remark
RC1SEC, RC1MIN, RC1HOUR, RC1WEEK, RC1DAY, RC1MONTH, and RC1YEAR may be read
in any sequence.
All the registers do not have to be set and only some registers may be read.
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CHAPTER 12 REAL-TIME COUNTER
12.4.4 Changing INTRTC0 interrupt setting during the real-time counter operation
If the setting of the INTRTC0 interrupt (fixed-cycle interrupt) signal is changed while the real-time counter clock
operates (PC1PWR = 1), the INTRCT0 interrupt waveform may include whiskers and unintended signals may be output.
Set as follows when changing the setting of the INTRTC0 interrupt signal during the real-time counter operation (RC1PWR
= 1, RTCE = 1), in order to mask the whiskers.
Figure 12-5. Changing INTRTC0 Interrupt Setting During The real-time counter Operation
Start
Setting RTC0MK bit
Setting RC1CC1.CT2 to
RC1CC1.CT0
Clearing RTC0IF flag
Clearing RTC0MK flag
Masks INTRTC0 interrupt signal.
Changes INTRTC0 interrupt signal setting.
Clears interrupt request flag.
Unmasks INTRTC0 interrupt signal.
End
Remark
See 23.3.4 Interrupt control register (xxICn) for details of the RTC0IF and RTC0MK bits.
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CHAPTER 12 REAL-TIME COUNTER
12.4.5 Changing INTRTC1 interrupt setting during the real-time counter operation
If the setting of the INTRTC1 interrupt (alarm interrupt) signal is changed while the real-time counter clock operates
(RC1PWR = 1), the INTRCT1 interrupt waveform may include whiskers and unintended signals may be output. Set as
follows when changing the setting of the INTRTC1 interrupt signal during the real-time counter operation (PC1PWR = 1,
RTCE = 1), in order to mask the whiskers.
Figure 12-6. Changing INTRTC1 Interrupt Setting During The real-time counter Operation
Start
Setting RTC1MK bit
RC1CC2.WALE bit = 0
Setting RC1ALM
Setting RC1ALH
Setting RC1ALW
Masks interrupt signal (INTRTC1).
Disables alarm interrupt.
Sets alarm minute register.
Sets alarm hour register
Sets alarm day-of-week register
Clearing RTC1IF flag
Clears interrupt pending bit.
Clearing RTC1MK flag
Unmasks interrupt signal (INTRTC1).
RC1CC2.WALE bit = 1
Enables alarm interrupt.
End
Remark
See 23.3.4 Interrupt control register (xxICn) for details of the RTC1IF and RTC1MK bits.
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CHAPTER 12 REAL-TIME COUNTER
12.4.6 Initial INTRTC2 interrupt settings
Set as follows to set the INTRTC1 interrupt (interval interrupt).
Figure 12-7. INTRTC2 Interrupt Setting
Start
RC1CC0.RC1PWR = 1
Setting RC1CC3.ICT2 to
RC1CC3.ICT0
RC1CC3.RINTE = 1
Enables counter operation.
Selects INTRTC2 (interval) interrupt interval.
Enables INTRTC2 (interval) interrupt.
End
Caution
Set and simultaneously or set first. Unintended waveform interrupts may occur
if is set first.
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CHAPTER 12 REAL-TIME COUNTER
12.4.7 Changing INTRTC2 interrupt setting during the real-time counter operation
If the setting of the INTRTC2 interrupt (interval interrupt) is changed while the real-time counter clock operates
(PC1PWR = 1), the INTRCT2 interrupt waveform may include whiskers and unintended signals may be output. Set as
follows when changing the setting of the INTRTC2 interrupt signal during the real-time counter operation (PC1PWR = 1,
RTCE = 1), in order to mask the whiskers.
Figure 12-8. Changing INTRTC2 Interrupt Setting During The real-time counter Operation
Start
Setting RTC2MK bit
RC1CC3.RINTE = 1
Setting RC1CC3.ICT2 to
RC1CC3.ICT0
Clearing RTC2IF flag
Clearing RTC2MK flag
Masks interrupt signal (INTRTC2).
Enables INTRTC2 (interval) interrupt.
Selects INTRTC2 (interval) interrupt interval.
Clears interrupt pending bit.
Unmasks interrupt signal (INTRTC2).
End
Remark
See 23.3.4 Interrupt control register (xxICn) for details of the RTC2IF and RTC2MK bits.
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CHAPTER 12 REAL-TIME COUNTER
12.4.8 Initializing real-time counter
The procedure for initializing the real-time counter is shown below.
Figure 12-9. Initializing Real-Time Counter
Start
Setting RTCnMK bit
Masks interrupt signal (INTRTCn)
RC1CC3.CLOE2 bit = 0
RTCDIV interrupt disable processing
RC1CC1.CLOE1 bit = 0
RC1CC1.CLOE0 bit = 0
RTC1HZ interrupt disable processing
RTCCL interrupt disable processing
RC1CC0.RC1PWR bit = 0
Initializes real-time counter (RTC).
Clearing RTCnIF flag
Clearing RTCnMK flag
Clears interrupt request bit.
Unmasks interrupt signal (INTRTCn).
End
Remarks 1. See 23.3.4 Interrupt control register (xxICn) for details of the RTCnIF and RTCnMK bits.
2. n = 0 to 2
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CHAPTER 12 REAL-TIME COUNTER
12.4.9 Watch error correction example of real-time counter
The watch error correction function corrects deviation in the oscillation frequency of a resonator connected to the
V850ES/Jx3-H.
Deviation, here, refers to steady-state deviation, which is deviation in the frequency when the resonator is designed.
Next, the timing chart when an error has occurred in the input clock intended to be 32.768 kHz but a 32.7681 kHz
resonator has been connected when designing the system, and the RC1SUBC and RC1SEC count operations to correct
the error are shown below.
Figure 12-10. Watch Error Correction Example
Watch count(32.768 kHz)
RTCCLK
(32.768 kHz)
RC1SUBC
7FFFH 0000H
0000H
7FFFH 0000H
7FFFH 0000H
7FFFH 0000H
7FFFH
20 secondsNote 1
00
RC1SEC
01
20
19
Watch count
(32.7681 kHz/no error correction)
RTCCLK
(32.7681 kHz)
RC1SUBC
0000H
7FFFH 0000H
7FFFH 0000H
7FFFH 0000H
7FFFH
19.99994 secondsNote 2
19
01
00
RC1SEC
20
Watch count
(32.7681 kHz/error correction(DEV bit = 0, F6 bit = 0, F5 to F0 bit = 000010))
RTCCLK
(32.7681 kHz)
2 count numbers are added.
RC1SUBC
0000H
7FFFH 8000H 8001H 0000H
2 count numbers are added.
7FFFH 0000H
7FFFH 0000H
7FFFH 0000H
7FFFH 8000H 8001H
20 secondsNote 3
RC1SEC
00
01
19
20
Notes 1. The RC1SEC counter counts 20 seconds every 32,768 cycles (0000H to 7FFFH) of the 32.768 kHz
clock.
2. When 32,768 cycles (0000H to 7FFFH) of the 32.7681 kHz clock are input, the time counted by the
RC1SEC counter is calculated as follows: 32,768/3,268.1 ≅ 0.999997 seconds
If this counting continues 20 times, the time is calculated as follows: (32,768/32,768.1) x 20 ≅ 19.99994
seconds, which causes an error of 0.00006 seconds.
3. To precisely count 20 seconds by using a 32.7681 kHz clock, clear the DEV and F6 bits to 0 and set the
F5 to F0 bits to 2H (000010B) in the RC1SUBU register. As a result, two additional cycles are counted
every 20 seconds (when the RC1SEC counter count is 00, 20, and 40 seconds), so that the number of
cycles counted at these points is not 32,768, but 32,770 (0000H to 8001H), which is exactly 20 seconds.
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CHAPTER 12 REAL-TIME COUNTER
As shown in Figure 12-10, the watch can be accurately counted by incrementing the RC1SUBC count value, if a
positive error faster than 32.768 kHz occurs at the resonator. Similarly, if a negative error slower than 32.768 kHz occurs
at the resonator, the watch can be accurately counted by decrementing the RC1SUBC count value.
The RC1SUBC correction value is determined by using the RC1SUBU.F6 to RC1SUBU.F0 bits.
The F6 bit is used to determine whether to increment or decrement RC1SUBC and the F5 to F0 bits to determine the
RC1SUBC value.
(1) Incrementing the RC1SUBC count value
The RC1SUBC count value is incremented by the value set using the F5 to F0 bits, by setting the F6 bit to 0.
Expression for calculating the increment value: (F5 to F0 bit value − 1) × 2
[Example of incrementing the RC1SUBC count value: F6 bit = 0]
If 15H (010101B) is set to the F5 to F0 bits
(15H − 1) × 2 = 40 (increments the RC1SUBC count value by 40)
RC1SUBC count value = 32,768 + 40 = 32,808
(2) Decrementing the RC1SUBC count value
The RC1SUBC count value is decremented by an inverted value of the value set using the F5 to F0 bits, by setting
the F6 bit to 1.
Expression for calculating the decrement value: (Inverted value of F5 to F0 bit value + 1) × 2
[Example of decrementing the RC1SUBC count value: F6 bit = 1]
If 15H (010101B) is set to the F5 to F0 bits
Inverted data of 15H (010101B) = 2AH (101010B)
(2AH + 1) × 2 = 86 (decrements the RC1SUBC count value by 86)
RC1SUBC count value = 32,768 − 86 = 32,682
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CHAPTER 12 REAL-TIME COUNTER
(3) DEV bit
The DEV bit determines when the setting by the F6 to F0 bits is enabled.
The value set by the F6 to F0 bits is reflected upon the next timing, but not to the RC1SUBC count value every time.
Table 12-6. DVE Bit Setting
DEV Bit Value
Timing of Reflecting Value to RC1SUBC
0
When RC1SEC is 00, 20, or 40 seconds.
1
When RC1SEC is 00 seconds.
[Example when 0010101B is set to F6 to F0 bits]
• If the DEV bit is 0
The RC1SUBC count value is 32,808 at 00, 20, or 40 seconds.
Otherwise, it is 32,768.
• IF DEV bit is 1
The RC1SUBC count value is 32,808 at 00 seconds.
Otherwise, it is 32,768.
As described above, the RC1SUBC count value is corrected every 20 seconds or 60 seconds, instead of every
second, in order to match the RC1SUBC count value with the deviation width of the resonator.
The range in which the resonator frequency can be actually corrected is shown below.
• If the DEV bit is 0: 32.76180000 kHz to 32.77420000 kHz
• If the DEV bit is 1: 32.76593333 kHz to 32.77006667 kHz
The range in which the frequency can be corrected when the DEV bit is 0 is three times wider than when the DEV
bit is 1.
However, the accuracy of setting the frequency when the DEV bit is 1 is three times that when the DEV bit is 0.
Tables 12-7 and 12-8 show the setting values of the DEV, and F6 to F0 bits, and the corresponding frequencies that
can be corrected.
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CHAPTER 12 REAL-TIME COUNTER
Table 12-7. Range of Frequencies That Can Be Corrected When DEV Bit = 0
F6
F5 to F0
RC1SUBC Correction Value
Frequency of Connected Clock
(Including Steady-State Deviation)
0
000000
No correction
−
0
000001
No correction
−
0
000010
Increments RC1SUBC count value by 2 once every 20 seconds
32.76810000 kHz
0
000011
Increments RC1SUBC count value by 4 once every 20 seconds
32.76820000 kHz
0
000100
Increments RC1SUBC count value by 6 once every 20 seconds
..
.
.
32.76830000 kHz
0
111011
Increments RC1SUBC count value by 120 once every 20 seconds
32.77400000 kHz
0
111110
Increments RC1SUBC count value by 122 once every 20 seconds
32.77410000 kHz
32.77420000 kHz (upper limit)
0
111111
Increments RC1SUBC count value by 124 once every 20 seconds
1
000000
No correction
−
1
000001
No correction
−
1
000010
Decrements RC1SUBC count value by 124 once every 20 seconds
32.76180000 kHz (lower limit)
1
000011
Decrements RC1SUBC count value by 122 once every 20 seconds
32.76190000 kHz
1
000100
Decrements RC1SUBC count value by 120 once every 20 seconds
.
..
.
32.76200000 kHz
1
11011
Decrements RC1SUBC count value by 6 once every 20 seconds
32.76770000 kHz
1
11110
Decrements RC1SUBC count value by 4 once every 20 seconds
32.76780000 kHz
1
11111
Decrements RC1SUBC count value by 2 once every 20 seconds
32.76790000 kHz
Table 12-8. Range of Frequencies That Can Be Corrected When DEV Bit = 1
F6
F5 to F0
RC1SUBC Correction Value
Frequency of Connected Clock
(Including Steady-State Deviation)
0
000000
No correction
−
0
000001
No correction
−
0
000010
Increments RC1SUBC count value by 2 once every 60 seconds
32.76803333 kHz
0
000011
Increments RC1SUBC count value by 4 once every 60 seconds
32.76806667 kHz
0
000100
Increments RC1SUBC count value by 6 once every 60 seconds
.
..
.
32.76810000 kHz
0
111011
Increments RC1SUBC count value by 120 once every 60 seconds
32.77000000 kHz
0
111110
Increments RC1SUBC count value by 122 once every 60 seconds
32.77003333 kHz
32.77006667 kHz (upper limit)
0
111111
Increments RC1SUBC count value by 124 once every 60 seconds
1
000000
No correction
−
1
000001
No correction
−
1
000010
Decrements RC1SUBC count value by 124 once every 60 seconds
32.76593333 kHz (lower limit)
1
000011
Decrements RC1SUBC count value by 122 once every 60 seconds
32.76596667 kHz
1
000100
Decrements RC1SUBC count value by 120 once every 60 seconds
..
.
.
32.76600000 kHz
1
11011
Decrements RC1SUBC count value by 6 once every 60 seconds
32.76790000 kHz
1
11110
Decrements RC1SUBC count value by 4 once every 60 seconds
32.76793333 kHz
1
11111
Decrements RC1SUBC count value by 2 once every 60 seconds
32.76796667 kHz
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CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2
CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2
13.1 Functions
Watchdog timer 2 has the following functions.
• Default-start watchdog timerNote 1
→ Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal)
→ Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of
INTWDT2 signal)Note 2
• Input from main clock, internal oscillation clock, and subclock selectable as the source clock
Notes 1. Watchdog timer 2 automatically starts in the reset mode following reset release.
When watchdog timer 2 is not used, either stop its operation before reset is executed via this function, or
clear watchdog timer 2 once and stop it within the next interval time.
Also, write to the WDTM2 register for verification purposes once, even if the default settings (reset mode,
interval time: fR/219) do not need to be changed.
2. For the non-maskable interrupt servicing due to a non-maskable interrupt request signal (INTWDT2), see
23.2.2 (2) From INTWDT2 signal.
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CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2
13.2 Configuration
The following shows the block diagram of watchdog timer 2.
Figure 13-1. Block Diagram of Watchdog Timer 2
fXX/2
10
fXT
fR/23
Clock
input
controller
16-bit
counter
2
Watchdog timer enable
register (WDTE)
fXX/219 to fXX/226,
fXT/29 to fXT/216,
fR/212 to fR/219
Selector
3
Clear
0
Output
controller
INTWDT2
WDT2RES
(internal reset signal)
3
WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
Watchdog timer mode
register 2 (WDTM2)
Internal bus
Remark
fXX:
Main clock frequency
fXT:
Subclock frequency
fR:
Internal oscillation clock frequency
INTWDT2:
Non-maskable interrupt request signal from watchdog timer 2
WDTRES2: Watchdog timer 2 reset signal
Watchdog timer 2 includes the following hardware.
Table 13-1. Configuration of Watchdog Timer 2
Item
Control registers
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Configuration
Watchdog timer mode register 2 (WDTM2)
Watchdog timer enable register (WDTE)
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CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2
13.3 Registers
(1) Watchdog timer mode register 2 (WDTM2)
The WDTM2 register sets the overflow time and operation clock of watchdog timer 2.
This register can be read or written in 8-bit units. This register can be read any number of times, but it can be
written only once following reset release.
Reset sets this register to 67H.
Caution
Accessing the WDTM2 register is prohibited in the following statuses. For details, see 3.4.9 (2)
Accessing specific on-chip peripheral I/O registers.
• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock
After reset: 67H
WDTM2
R/W
Address: FFFFF6D0H
0
WDM21
WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
WDM21
WDM20
0
0
Stops operation
0
1
Non-maskable interrupt request mode
(generation of INTWDT2 signal)
1
–
Reset mode (generation of WDT2RES signal)
Selection of operation mode of watchdog timer 2
Cautions 1. For details of the WDCS20 to WDCS24 bits, see Table 13-2 Watchdog Timer 2 Clock
Selection.
2. Although watchdog timer 2 can be stopped just by stopping operation of the internal
oscillator, clear the WDTM2 register to 00H to securely stop the timer (to avoid selection of
the main clock or subclock due to an erroneous write operation).
3. If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly generated
and the counter is reset.
4. To intentionally generate an overflow signal, write data to the WDTM2 register twice, or
write a value other than “ACH” to the WDTE register once.
However, when the operation of watchdog timer 2 is set to be stopped, an overflow signal
is not generated even if data is written to the WDTM2 register twice, or a value other than
“ACH” is written to the WDTE register once.
5. To stop the operation of watchdog timer 2, set the RCM.RSTOP bit to 1 (to stop the
internal oscillator) and write 00H in the WDTM2 register. If the RCM.RSTOP bit cannot be
set to 1, set the WDCS23 bit to 1 (2n/fXX is selected and the clock can be stopped in the
IDLE1, IDLW2, sub-IDLE, and subclock operation modes).
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CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2
Table 13-2. Watchdog Timer 2 Clock Selection
WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Selected Clock
100 kHz (MIN.)
220 kHz (TYP.)
400 kHz (MAX.)
12
41.0 ms
18.6 ms
10.2 ms
13
81.9 ms
37.2 ms
20.5 ms
14
163.8 ms
74.5 ms
41.0 ms
15
327.7 ms
148.9 ms
81.9 ms
16
655.4 ms
297.9 ms
163.8 ms
17
1,310.7 ms
595.8 ms
327.7 ms
18
2 /fR
2 /fR
2 /fR
2 /fR
2 /fR
2 /fR
0
0
1
1
0
2 /fR
2,621.4 ms
1191.6 ms
655.4 ms
0
0
1
1
1
2 /fR (Default value) 5,242.9 ms
2383.1 ms
1,310.7 ms
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
19
fXX = 24 MHz
fXX = 32 MHz
fXX = 48 MHz
19
21.8 ms
16.4 ms
10.9 ms
20
43.7 ms
32.8 ms
21.8 ms
21
87.4 ms
65.5 ms
43.7 ms
22
174.8 ms
131.1 ms
87.4 ms
23
349.5 ms
262.1 ms
174.8 ms
24
699.1 ms
524.3 ms
349.5 ms
25
1398.1 ms
1048.6 ms
699.1 ms
26
2796.2 ms
2097.2 ms
1398.1 ms
2 /fXX
2 /fXX
2 /fXX
2 /fXX
0
1
1
0
0
2 /fXX
0
1
1
0
1
2 /fXX
0
0
1
1
1
1
1
1
0
1
2 /fXX
2 /fXX
fXT = 32.768 kHz
1
1
×
×
0
0
0
0
0
1
9
15.625 ms
10
31.25 ms
11
62.5 ms
12
125 ms
13
250 ms
14
500 ms
15
1,000 ms
16
2,000 ms
2 /fXT
2 /fXT
1
×
0
1
0
2 /fXT
1
×
0
1
1
2 /fXT
1
1
1
1
×
×
×
×
1
1
1
1
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0
0
1
1
0
1
0
1
2 /fXT
2 /fXT
2 /fXT
2 /fXT
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CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2
(2) Watchdog timer enable register (WDTE)
The counter of watchdog timer 2 is cleared and counting restarted by writing “ACH” to the WDTE register.
The WDTE register can be read or written in 8-bit units.
Reset sets this register to 9AH.
After reset: 9AH
R/W
Address: FFFFF6D1H
WDTE
Cautions 1. When a value other than “ACH” is written to the WDTE register, an overflow signal is
forcibly output.
2. When a 1-bit memory manipulation instruction is executed for the WDTE register, an
overflow signal is forcibly output.
3. To intentionally generate an overflow signal, write a value other than “ACH” to the WDTE
register once, or write data to the WDTM2 register twice.
However, when the operation of watchdog timer 2 is set to be stopped, an overflow signal is
not generated even if data is written to the WDTM2 register twice, or a value other than
“ACH” is written to the WDTE register once.
4. The read value of the WDTE register is “9AH” (which differs from written value “ACH”).
13.4 Operation
Watchdog timer 2 automatically starts in the reset mode following reset release.
The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write the
operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction. After this,
the operation of watchdog timer 2 cannot be stopped.
The WDTM2.WDCS24 to WDTM2.WDCS20 bits are used to select the watchdog timer 2 loop detection time interval.
Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again. After
the count operation has started, write ACH to WDTE within the loop detection time interval.
If the time interval expires without ACH being written to the WDTE register, a reset signal (WDT2RES) or a nonmaskable interrupt request signal (INTWDT2) is generated, depending on the set values of the WDTM2.WDM21 and
WDTM2.WDM20 bits.
When the WDTM2.WDM21 bit is set to 1 (reset mode), if a WDT overflow occurs during oscillation stabilization after a
reset or standby is released, no internal reset will occur and the CPU clock will switch to the internal oscillation clock.
To not use watchdog timer 2, write 00H to the WDTM2 register.
For the non-maskable interrupt servicing while the non-maskable interrupt request mode is set, see 23.2.2 (2) From
INTWDT2 signal.
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CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO)
CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO)
14.1 Function
The real-time output function transfers the data preset to the RTBL0 and RTBH0 registers to the output latches via
hardware and outputs the data to an external device, at the same time as a timer interrupt occurs. The pins through which
the data is output to an external device constitute a port called the real-time output (RTO) port.
Because signals without jitter can be output by using RTO, it is suitable for controlling a stepper motor.
In the V850ES/JG3-H and V850ES/JH3-H, one 6-bit real-time output port channel is provided.
The real-time output port can be set to the port mode or real-time output port mode in 1-bit units.
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14.2 Configuration
The block diagram of RTO is shown below.
Internal bus
Figure 14-1. Block Diagram of RTO
Real-time output
buffer register 0H
(RTBH0)
Real-time output
latch 0H
2
Real-time output
buffer register 0L
(RTBL0)
Real-time output
latch 0L
4
RTP04,
RTP05
RTP00 to
RTP03
INTTAA0CC0
Transfer trigger (H)
Selector
INTTAA5CC0
Transfer trigger (L)
INTTAA4CC0
2
RTPOE0 RTPEG0 BYTE0
EXTR0
Real-time output port control
register 0 (RTPC0)
4
RTPM05 RTPM04 RTPM03 RTPM02 RTPM01 RTPM00
Real-time output port mode
register 0 (RTPM0)
RTO includes the following hardware.
Table 14-1. Configuration of RTO
Item
Configuration
Registers
Real-time output buffer registers 0L, 0H (RTBL0, RTBH0)
Control registers
Real-time output port mode register 0 (RTPM0)
Real-time output port control register 0 (RTPC0)
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CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO)
(1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0)
The RTBL0 and RTBH0 registers are 4-bit registers that hold output data in advance.
These registers are each mapped to independent addresses in the peripheral I/O register area.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
If an operation mode of 4 bits × 1 channel or 2 bits × 1 channel is specified (RTPC0.BYTE0 bit = 0), data can be
individually set to the RTBL0 and RTBH0 registers. The data of both these registers can be read at once by
specifying the address of either of these registers.
If an operation mode of 6 bits × 1 channel is specified (BYTE0 bit = 1), 8-bit data can be set to both the RTBL0 and
RTBH0 registers by writing the data to either of these registers. Moreover, the data of both these registers can be
read at once by specifying the address of either of these registers.
Table 14-2 shows the operation when the RTBL0 and RTBH0 registers are manipulated.
After reset: 00H
R/W
Address: RTBL0 FFFFF6E0H, RTBH0 FFFFF6E2H
RTBL0
RTBH0
RTBL03
0
0
RTBL02
RTBL01
RTBL00
RTBH05 RTBH04
Cautions 1. When writing to bits 6 and 7 of the RTBH0 register, always set 0.
2. Accessing the RTBL0 and RTBH0 registers is prohibited in the following
statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O
registers.
• When the CPU operates on the subclock and the main clock oscillation is
stopped
• When the CPU operates on the internal oscillation clock
Table 14-2. Operation During Manipulation of RTBL0 and RTBH0 Registers
Operation Mode
Register to Be
Manipulated
Read
Higher 4 Bits
Write
Lower 4 Bits
Higher 4 Bits
Note
Lower 4 Bits
4 bits × 1 channel,
2 bits × 1 channel
RTBL0
RTBH0
RTBL0
Invalid
RTBL0
RTBH0
RTBH0
RTBL0
RTBH0
Invalid
6 bits × 1 channel
RTBL0
RTBH0
RTBL0
RTBH0
RTBL0
RTBH0
RTBH0
RTBL0
RTBH0
RTBL0
Note After setting the real-time output port, set output data to the RTBL0 and RTBH0 registers by the time a real-time
output trigger is generated.
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CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO)
14.3 Registers
RTO is controlled using the following two registers.
• Real-time output port mode register 0 (RTPM0)
• Real-time output port control register 0 (RTPC0)
(1) Real-time output port mode register 0 (RTPM0)
The RTPM0 register selects the real-time output port mode or port mode in 1-bit units.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
RTPM0
R/W
0
0
RTPM0m
Address: RTPM0 FFFFF6E4H
RTPM05 RTPM04 RTPM03 RTPM02 RTPM01 RTPM00
Control of real-time output port (m = 0 to 5)
0
Real-time output disabled
1
Real-time output enabled
Cautions 1. By enabling the real-time output operation (RTPC0.RTPOE0 bit = 1), the bits
enabled for real-time output among the RTP00 to RTP05 signals perform realtime output, and the bits set to port mode output 0.
2. If real-time output is disabled (RTPOE0 bit = 0), the real-time output pins
(RTP00 to RTP05) all output 0, regardless of the RTPM0 register setting.
3. In order to use this register for the real-time output pins (RTP00 to RTP05), set
these pins as real-time output port pins using the PMC and PFC registers.
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CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO)
(2) Real-time output port control register 0 (RTPC0)
The RTPC0 register is a register that sets the operation mode and output trigger of the real-time output port.
The relationship between the operation mode and output trigger of the real-time output port is as shown in Table
14-3.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address: FFFFF6E5H
< >
RTPC0
RTPOE0 RTPEG0
BYTE0
RTPOE0
0
0
0
0
Control of real-time output operation
0
Disables operation
1
Enables operation
Note 1
Valid edge of INTTP0CC0 signal
RTPEG0
0
Falling edgeNote 2
1
Rising edge
BYTE0
EXTR0
Specification of channel configuration for real-time output
0
4 bits × 1 channels, 2 bits × 1 channels
1
6 bits × 1 channels
Notes 1. When the real-time output operation is disabled (RTPOE0 bit = 0), all real-time output
pins (RTP00 to RTP05) output “0”.
2. The INTTAA0CC0 signal is output for 1 clock of the count clock selected by TAA0.
Caution Set the RTPEG0, BYTE0, and EXTR0 bits only when the RTPOE0 bit = 0.
Table 14-3. Operation Modes and Output Triggers of Real-Time Output Port
BYTE0
EXTR0
0
0
1
1
0
1
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Operation Mode
4 bits × 1 channel,
2 bits × 1 channel
6 bits × 1 channel
RTBH0 (RTP04, RTP05)
RTBL0 (RTP00 to RTP03)
INTTAA5CC0
INTTAA4CC0
INTTAA4CC0
INTTAA0CC0
INTTAA4CC0
INTTAA0CC0
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CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO)
14.4 Operation
If the real-time output operation is enabled by setting the RTPC0.RTPOE0 bit to 1, the data of the RTBH0 and RTBL0
registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger
(set by the RTPC0.EXTR0 and RTPC0.BYTE0 bits). Of the transferred data, only the data of the bits for which real-time
output is enabled by the RTPM0 register is output from the RTP00 to RTP05 bits. The bits for which real-time output is
disabled by the RTPM0 register output 0.
If the real-time output operation is disabled by clearing the RTPOE0 bit to 0, the RTP00 to RTP05 signals output 0
regardless of the setting of the RTPM0 register.
Figure 14-2. Example of Operation Timing of RTO0 (When EXTR0 Bit = 0, BYTE0 Bit = 0)
INTTAA5CC0 (internal)
INTTAA4CC0 (internal)
CPU operation
A
B
RTBH0 D01
RTBL0
RT output latch 0 (H)
RT output latch 0 (L)
A
B
D02
A
B
D03
D11
D13
D02
D11
B
D04
D12
D01
A
D14
D03
D12
D04
D13
D14
A: Software processing by INTTAA5CC0 interrupt request (RTBH0 write)
B: Software processing by INTTAA4CC0 interrupt request (RTBL0 write)
Remark
For the operation during standby, see CHAPTER 25 STANDBY FUNCTION.
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CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO)
14.5 Usage
(1) Disable real-time output.
Clear the RTPC0.RTPOE0 bit to 0.
(2) Perform initialization as follows.
• Set the alternate-function pins of port 2 or port 5
After setting the PFC2.PFC2m bit and PFCE2.PFCE2m bit to the RTO pin, set the PMC2.PMC2m bit to 1 (m = 0
to 3).
After setting the PFC5.PFC5m bit and PFCE5.PFCE5m bit to the RTO pin, set the PMC5.PMC5m bit to 1 (m = 0
to 5).
• Specify the real-time output port mode or port mode in 1-bit units.
Set the RTPM0 register.
• Channel configuration: Select the trigger and valid edge.
Set the RTPC0.EXTR0, RTPC0.BYTE0, and RTPC0.RTPEG0 bits.
• Set the initial values to the RTBH0 and RTBL0 registersNote 1.
(3) Enable real-time output.
Set the RTPOE0 bit = 1.
(4) Set the next output value to the RTBH0 and RTBL0 registers by the time the selected transfer trigger is
generatedNote 2.
(5) Sequentially set the next real-time output value to the RTBH0 and RTBL0 registers via interrupt servicing
corresponding to the selected trigger.
Notes 1. If the RTBH0 and RTBL0 registers are written when the RTPOE0 bit = 0, that value is transferred to
real-time output latches 0H and 0L.
2.
Even if the RTBH0 and RTBL0 registers are written when the RTPOE0 bit = 1, data is not transferred to
real-time output latches 0H and 0L.
14.6 Cautions
(1) Prevent the following conflicts by software.
• Conflict between real-time output disable/enable switching (RTPOE0 bit) and the selected real-time output
trigger.
• Conflict between writing to the RTBH0 and RTBL0 registers in the real-time output enabled status and the
selected real-time output trigger.
(2) Before performing initialization, disable real-time output (RTPOE0 bit = 0).
(3) Once real-time output has been disabled (RTPOE0 bit = 0), be sure to initialize the RTBH0 and RTBL0 registers
before enabling real-time output again (RTPOE0 bit = 0 → 1).
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CHAPTER 15 A/D CONVERTER
CHAPTER 15 A/D CONVERTER
15.1 Overview
The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 12
analog input signal channels (ANI0 to ANI11).
The A/D converter has the following features.
{ 10-bit resolution
{ 12 channels
{ Successive approximation method
{ Operating voltage: AVREF0 = 3.0 to 3.6 V
{ Analog input voltage: 0 V to AVREF0
{ The following functions are provided as operation modes.
• Continuous select mode
• Continuous scan mode
• One-shot select mode
• One-shot scan mode
{ The following functions are provided as trigger modes.
• Software trigger mode
• External trigger mode (external, 1)
• Timer trigger mode
{ Power-fail monitor function (conversion result compare function)
15.2 Functions
(1) 10-bit resolution A/D conversion
An analog input channel is selected from ANI0 to ANI11, and an A/D conversion operation is repeated at a
resolution of 10 bits. Each time A/D conversion has been completed, an interrupt request signal (INTAD) is
generated.
(2) Power-fail detection function
This function is used to detect a drop in the battery voltage. The result of A/D conversion (the value of the
ADA0CRnH register) is compared with the value of the ADA0PFT register, and the INTAD signal is generated only
when a specified comparison condition is satisfied (n = 0 to 11).
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15.3 Configuration
The block diagram of the A/D converter is shown below.
Figure 15-1. Block Diagram of A/D Converter
AVREF0
ANI0
ANI1
ANI2
:
:
:
:
:
ANI11
Selector
Sample & hold circuit
ADA0CE bit
Voltage comparator
&
Compare voltage
generation DAC
ADA0CE bit
AVSS
SAR
ADA0TMD1 bit
ADA0TMD0 bit
INTAD
INTTAA2CC1
TQTADTONote
Edge
ADTRG
detection
Selector
INTTAA2CC0
Controller
ADA0CR0
ADA0CR1
ADA0CR2
:
:
ADA0CR10
ADA0ETS0 bit
ADA0ETS1 bit
ADA0M0
Controller
ADA0PFE bit
ADA0PFC bit
ADA0M1
ADA0M2
ADA0S
ADA0CR11
Voltage
comparator
ADA0PFT ADA0PFM
Internal bus
Note The timer trigger signal from 6-phase PWM output circuit (TMQOP)
The A/D converter includes the following hardware.
Table 15-1. Configuration of A/D Converter
Item
Configuration
Analog inputs
12 channels (ANI0 to ANI11 pins)
Registers
Successive approximation register (SAR)
A/D conversion result registers 0 to 11 (ADA0CR0 to ADA0CR11)
A/D conversion result registers 0H to 11H (ADCR0H to ADCR11H): Only higher 8 bits
can be read
Control registers
A/D converter mode registers 0 to 2 (ADA0M0 to ADA0M2)
A/D converter channel specification register 0 (ADA0S)
Power fail compare mode register (ADA0PFM)
Power fail compare threshold value register (ADA0PFT)
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CHAPTER 15 A/D CONVERTER
(1) Successive approximation register (SAR)
The SAR compares the voltage value of the analog input signal with the output voltage of the compare voltage
generation DAC (compare voltage), and holds the comparison result starting from the most significant bit (MSB).
When the comparison result has been held down to the least significant bit (LSB) (i.e., when A/D conversion is
complete), the contents of the SAR are transferred to the ADA0CRn register.
Remark
n = 0 to 11
(2) A/D conversion result register n (ADA0CRn), A/D conversion result register nH (ADA0CRnH)
The ADA0CRn register is a 16-bit register that stores the A/D conversion result. ADA0ARn consist of 12 registers
and the A/D conversion result is stored in the 10 higher bits of the AD0CRn register corresponding to analog input.
(The lower 6 bits are fixed to 0.)
(3) A/D converter mode register 0 (ADA0M0)
This register specifies the operation mode and controls the conversion operation by the A/D converter.
(4) A/D converter mode register 1 (ADA0M1)
This register sets the conversion time of the analog input signal to be converted.
(5) A/D converter mode register 2 (ADA0M2)
This register sets the hardware trigger mode.
(6) A/D converter channel specification register (ADA0S)
This register sets the input port that inputs the analog voltage to be converted.
(7) Power-fail compare mode register (ADA0PFM)
This register sets the power-fail monitor mode.
(8) Power-fail compare threshold value register (ADA0PFT)
The ADA0PFT register sets the threshold value that is compared with the value of A/D conversion result register nH
(ADA0CRnH).
The 8-bit data set to the ADA0PFT register is compared with the higher 8 bits of the A/D conversion result register
(ADA0CRnH).
(9) Controller
The controller compares the result of the A/D conversion (the value of the ADA0CRnH register) with the value of the
ADA0PFT register when A/D conversion is completed or when the power-fail detection function is used, and
generates the INTAD signal only when a specified comparison condition is satisfied.
(10) Sample & hold circuit
The sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the
sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage during
A/D conversion.
(11) Voltage comparator
The voltage comparator compares a voltage value that has been sampled and held with the output voltage of the
compare voltage generation DAC.
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(12) Compare voltage generation DAC
This compare voltage generation DAC is connected between AVREF0 and AVSS and generates a voltage for
comparison with the analog input signal.
(13) ANI0 to ANI11 pins
These are analog input pins for the 12 A/D converter channels and are used to input analog signals to be
converted into digital signals. Pins other than the one selected as the analog input by the ADA0S register can be
used as input port pins.
Caution
Make sure that the voltages input to the ANI0 to ANI11 pins do not exceed the rated values. In
particular if a voltage of AVREF0 or higher is input to a channel, the conversion value of that
channel becomes undefined, and the conversion values of the other channels may also be
affected.
(14) AVREF0 pin
This is the pin used to input the reference voltage of the A/D converter. Always make the potential at this pin the
same as that at the VDD pin even when the A/D converter is not used.
The signals input to the ANI0 to ANI11 pins are converted to digital signals based on the voltage applied between
the AVREF0 and AVSS pins.
(15) AVSS pin
This is the ground potential pin of the A/D converter. Always make the potential at this pin the same as that at the
VSS pin even when the A/D converter is not used.
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CHAPTER 15 A/D CONVERTER
15.4 Registers
The A/D converter is controlled by the following registers.
• A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2)
• A/D converter channel specification register 0 (ADA0S)
• Power-fail compare mode register (ADA0PFM)
The following registers are also used.
• A/D conversion result register n (ADA0CRn)
• A/D conversion result register nH (ADA0CRnH)
• Power-fail compare threshold value register (ADA0PFT)
(1) A/D converter mode register 0 (ADA0M0)
The ADA0M0 register is an 8-bit register that specifies the operation mode and controls conversion operations.
This register can be read or written in 8-bit or 1-bit units. However, the ADA0EF bit is read-only.
Reset sets this register to 00H.
(1/2)
After reset: 00H
R/W
Address: FFFFF200H
< >
< >
ADA0M0
ADA0CE
0
ADA0MD1 ADA0MD0 ADA0ETS1 ADA0ETS0 ADA0TMD
ADA0EF
A/D conversion control
ADA0CE
0
Stops A/D conversion
1
Enables A/D conversion
ADA0MD1 ADA0MD0
Specification of A/D converter operation mode
0
0
Continuous select mode
0
1
Continuous scan mode
1
0
One-shot select mode
1
1
One-shot scan mode
ADA0ETS1 ADA0ETS0 Specification of external trigger (ADTRG pin) input valid edge
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0
0
No edge detection
0
1
Falling edge detection
1
0
Rising edge detection
1
1
Detection of both rising and falling edges
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CHAPTER 15 A/D CONVERTER
(2/2)
Trigger mode specification
ADA0TMD
0
Software trigger mode
1
External trigger mode/timer trigger mode
A/D converter status display
ADA0EF
0
A/D conversion stopped
1
A/D conversion in progress
Cautions 1. Accessing the ADA0M0 register is prohibited in the following statuses. For details,
see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock
2. A write operation to bit 0 is ignored.
3. Changing the ADA0M1.ADA0FR2 to ADA0M1.ADA0FR0 bits is prohibited while A/D
conversion is enabled (ADA0CE bit = 1).
4. In the following modes, write data to the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or
ADA0PFT registers while A/D conversion is stopped (ADA0CE bit = 0), and then enable
the A/D conversion operation (ADA0CE bit = 1).
• Normal conversion mode
• One-shot select mode/one-shot scan mode in high-speed conversion mode
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers are written in other
modes during A/D conversion (ADA0EF bit = 1), the following will be performed
according to the mode.
• In software trigger mode
A/D conversion is stopped and started again from the beginning.
• In hardware trigger mode
A/D conversion is stopped, and the trigger standby status is set.
5. To select the external trigger mode/timer trigger mode (ADA0TMD bit = 1), set the highspeed conversion mode (ADA0M1.ADA0HS1 bit = 1). Do not input a trigger during
stabilization time that is inserted once after the A/D conversion operation is enabled
(ADA0CE bit = 1).
6. When not using the A/D converter, stop the operation by setting the ADA0CE bit to 0 to
reduce the power consumption.
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(2) A/D converter mode register 1 (ADA0M1)
The ADA0M1 register is an 8-bit register that specifies the conversion time.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this bit to 00H.
After reset: 00H
ADA0M1
ADA0HS1
R/W
0
Address: FFFFF201H
0
0
ADA0FR3 ADA0FR2 ADA0FR1 ADA0FR0
ADA0HS1 Specification of normal conversion mode/high-speed mode (A/D conversion time)
0
Normal conversion mode
1
High-speed conversion mode
Cautions 1. Changing the ADA0M1 register is prohibited while A/D conversion is enabled
(ADA0M0.ADA0CE bit = 1).
2. To select the external trigger mode/timer trigger mode (ADA0M0.ADA0TMD bit = 1), set
the high-speed conversion mode (ADA0HS1 bit = 1). Do not input a trigger during the
stabilization time that is inserted once after the A/D conversion operation is enabled
(ADA0CE bit = 1).
3. Be sure to clear bits 6 to 4 to “0”.
Remark
For A/D conversion time setting examples, see Tables 15-2 and 15-3.
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Table 15-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0)
ADA0FR3 to
ADA0FR0
Bits
Stabilization Time
48 MHz
32 MHz
24 MHz
+ Conversion Time + Wait Time
0000
26/fXX + 52/fXX + 54/fXX
Setting prohibited
Setting prohibited
5.50 μs
0001
52/fXX + 104/fXX + 106/fXX
5.46 μs
8.19 μs
Setting prohibited
0010
78/fXX + 156/fXX + 158/fXX
8.17 μs
Setting prohibited
Setting prohibited
0011
100/fXX + 208/fXX + 210/fXX
Setting prohibited
Setting prohibited
Setting prohibited
0100
100/fXX + 260/fXX + 262/fXX
Setting prohibited
Setting prohibited
Setting prohibited
0101
100/fxx + 312/fxx + 314/fXX
Setting prohibited
Setting prohibited
Setting prohibited
0110
100/fxx + 364/fxx + 366/fXX
Setting prohibited
Setting prohibited
Setting prohibited
0111
100/fXX + 416/fXX + 418/fXX
Setting prohibited
Setting prohibited
Setting prohibited
1000
100/fXX + 468/fXX + 470/fXX
Setting prohibited
Setting prohibited
Setting prohibited
1001
100/fXX + 520/fXX + 522/fXX
Setting prohibited
Setting prohibited
Setting prohibited
1010
100/fXX + 572/fXX + 574/fXX
Setting prohibited
Setting prohibited
Setting prohibited
1011
100/fXX + 624/fXX + 626/fXX
Setting prohibited
Setting prohibited
Setting prohibited
1100
100/fXX + 676/fXX + 678/fXX
Setting prohibited
Setting prohibited
Setting prohibited
1101
100/fXX + 728/fXX + 730/fXX
Setting prohibited
Setting prohibited
Setting prohibited
1110
100/fXX + 780/fXX + 782/fXX
Setting prohibited
Setting prohibited
Setting prohibited
1111
100/fXX + 832/fXX + 834/fXX
Setting prohibited
Setting prohibited
Setting prohibited
Other than above
Remark
A/D Conversion Time
Setting prohibited
Stabilization time:
A/D converter setup time (1 μs or longer)
Conversion time:
Actual A/D conversion time (2.17 to 9.75 μs)
Wait time:
Wait time inserted before the next conversion
fXX:
Main clock frequency
In the normal conversion mode, the conversion is started after the stabilization time elapses after the
ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.17 to 9.75
μs). Operation is stopped after the conversion ends and the A/D conversion end interrupt request signal
(INTAD) is generated after the wait time elapses.
Because the conversion operation is stopped during the wait time, operating current can be reduced.
Cautions 1. Set as 2.17 μs ≤ conversion time ≤ 9.75 μs.
2. During A/D conversion, if the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT
registers are written or a trigger is input, reconversion is carried out. However, if the
stabilization time end timing conflicts with writing to these registers, or if the stabilization
time end timing conflicts with the trigger input, a stabilization time of 64 clocks is
reinserted.
If a conflict occurs again with the reinserted stabilization time end timing, the stabilization
time is reinserted. Therefore do not set the trigger input interval and control register write
interval to 64 clocks or lower.
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Table 15-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1)
ADA0FR3 to
ADA0FR0
Bits
A/D Conversion Time
Conversion Time
48 MHz
24 MHz
0000
52/fXX (+26/fXX)
Setting prohibited
Setting prohibited
2.17 μs
0001
104/fXX (+52/fXX)
2.17 μs
3.25 μs
4.33 μs
0010
156/fXX (+78/fXX)
3.25 μs
4.88 μs
6.50 μs
0011
208/fXX (+100/fXX)
4.33 μs
6.50 μs
8.67 μs
0100
260/fXX (+100/fXX)
5.42 μs
8.13 μs
Setting prohibited
0101
312/fXX (+100/fXX)
6.50 μs
9.75 μs
Setting prohibited
0110
364/fXX (+100/fXX)
7.58 μs
Setting prohibited
Setting prohibited
0111
416/fXX (+100/fXX)
8.67 μs
Setting prohibited
Setting prohibited
1000
468/fXX (+100/fXX)
9.75 μs
Setting prohibited
Setting prohibited
1001
520/fXX (+100/fXX)
Setting prohibited
Setting prohibited
Setting prohibited
1010
572/fXX (+100/fXX)
Setting prohibited
Setting prohibited
Setting prohibited
1011
624/fXX (+100/fXX)
Setting prohibited
Setting prohibited
Setting prohibited
1100
676/fXX (+100/fXX)
Setting prohibited
Setting prohibited
Setting prohibited
1101
728/fXX (+100/fXX)
Setting prohibited
Setting prohibited
Setting prohibited
1110
780/fXX (+100/fXX)
Setting prohibited
Setting prohibited
Setting prohibited
1111
832/fXX (+100/fXX)
Setting prohibited
Setting prohibited
Setting prohibited
Other than above
Remark
32 MHz
(+ Stabilization Time)
Setting prohibited
Stabilization time:
A/D converter setup time (1 μs or longer)
Conversion time:
Actual A/D conversion time (2.17 to 9.75 μs)
fXX:
Main clock frequency
In the high-speed conversion mode, the conversion is started after the stabilization time elapses after the
ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.17 to 9.75
μs). The A/D conversion end interrupt request signal (INTAD) is generated immediately after the conversion
ends.
In continuous conversion mode, the stabilization time is inserted only before the first conversion, and not
inserted after the second conversion (the A/D converter remains running).
Cautions 1. Set as 2.17 μs ≤ conversion time ≤ 9.75 μs.
2. In the high-speed conversion mode, rewriting of the ADA0M0, ADA0M2, ADA0S, ADA0PFM,
and ADA0PFT registers and trigger input are prohibited during the stabilization time.
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(3) A/D converter mode register 2 (ADA0M2)
The ADA0M2 register specifies the hardware trigger mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
ADA0M2
R/W
Address: FFFFF203H
7
6
5
4
3
2
0
0
0
0
0
0
ADA0TMD1 ADA0TMD0
1
0
ADA0TMD1 ADA0TMD0
Specification of hardware trigger mode
0
0
External trigger mode (when ADTRG pin valid edge is detected)
0
1
Timer trigger mode 0
(when INTTAA2CC0 interrupt request is generated)
1
0
Timer trigger mode 1
(when INTTAA2CC1 interrupt request is generated)
1
1
Timer trigger mode 2 (TQTADT0 signal)
Cautions 1. In the following modes, write data to the ADA0M2 register while A/D conversion is
stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation
(ADA0CE bit = 1).
• Normal conversion mode
• One-shot select mode/one-shot scan mode in high-speed conversion mode
2. Be sure to clear bits 7 to 2 to “0”.
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(4) Analog input channel specification register 0 (ADA0S)
The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
ADA0S
0
R/W
0
Address: FFFFF202H
0
0
ADA0S3 ADA0S2 ADA0S1 ADA0S0
ADA0S3 ADA0S2 ADA0S1 ADA0S0
Select mode
Scan mode
0
0
0
0
ANI0
ANI0
0
0
0
1
ANI1
ANI0, ANI1
0
0
1
0
ANI2
ANI0 to ANI2
0
0
1
1
ANI3
ANI0 to ANI3
0
1
0
0
ANI4
ANI0 to ANI4
0
1
0
1
ANI5
ANI0 to ANI5
0
1
1
0
ANI6
ANI0 to ANI6
0
1
1
1
ANI7
ANI0 to ANI7
1
0
0
0
ANI8
ANI0 to ANI8
1
0
0
1
ANI9
ANI0 to ANI9
1
0
1
0
ANI10
ANI0 to ANI10
1
0
1
1
ANI11
ANI0 to ANI11
Cautions 1. In the following modes, write data to the ADA0S register while A/D conversion is
stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation
(ADA0CE bit = 1).
• Normal conversion mode
• One-shot select mode/one-shot scan mode in high-speed conversion mode
2. Be sure to clear bits 7 to 4 to “0”.
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(5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH)
The ADA0CRn and ADA0CRnH registers store the A/D conversion results.
These registers are read-only, in 16-bit or 8-bit units. However, the ADA0CRn register is used for 16-bit access and
the ADA0CRnH register for 8-bit access. The 10 bits of the conversion result are read to the higher 10 bits of the
ADA0CRn register, and 0 is read to the lower 6 bits. The higher 8 bits of the conversion result are read to the
ADA0CRnH register.
Caution Accessing the ADA0CRn and ADA0CRnH registers is prohibited in the following statuses.
For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock
After reset: Undefined
R
Address: ADA0CR0 FFFFF210H, ADA0CR1 FFFFF212H,
ADA0CR2 FFFFF214H, ADA0CR3 FFFFF216H,
ADA0CR4 FFFFF218H, ADA0CR5 FFFFF21AH,
ADA0CR6 FFFFF21CH, ADA0CR7 FFFFF21EH,
ADA0CR8 FFFFF220H, ADA0CR9 FFFFF222H,
ADA0CR10 FFFFF224H, ADA0CR11 FFFFF226H
ADA0CRn
(n = 0 to 11)
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
After reset: Undefined
R
0
0
0
0
0
0
Address: ADA0CR0H FFFFF211H, ADA0CR1H FFFFF213H,
ADA0CR2H FFFFF215H, ADA0CR3H FFFFF217H,
ADA0CR4H FFFFF219H, ADA0CR5H FFFFF21BH,
ADA0CR6H FFFFF21DH, ADA0CR7H FFFFF21FH,
ADA0CR8H FFFFF221H, ADA0CR9H FFFFF223H,
ADA0CR10H FFFFF225H, ADA0CR11H FFFFF227H
ADA0CRnH
7
6
5
4
3
2
1
0
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
(n = 0 to 11)
Caution
A write operation to the ADA0M0 and ADA0S registers may cause the contents of the
ADA0CRn register to become undefined. After the conversion, read the conversion result
before writing to the ADA0M0 and ADA0S registers. Correct conversion results may not
be read at a timing other than the above.
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The relationship between the analog voltage input to the analog input pins (ANI0 to ANI11) and the A/D conversion
result (ADA0CRn register) is as follows.
SAR = INT (
VIN
AVREF0
× 1,024 + 0.5)
ADA0CRNote = SAR × 64
Or,
(SAR − 0.5) ×
AVREF0
1,024
≤ VIN < (SAR + 0.5) ×
AVREF0
1,024
INT( ):
Function that returns the integer of the value in ( )
VIN:
Analog input voltage
AVREF0:
AVREF0 pin voltage
ADA0CR: Value of ADA0CRn register
Note The lower 6 bits of the ADA0CRn register are fixed to 0.
The following shows the relationship between the analog input voltage and the A/D conversion results.
Figure 15-2. Relationship Between Analog Input Voltage and A/D Conversion Results
ADA0CRn
SAR
A/D conversion results
1,023
FFC0H
1,022
FF80H
1,021
FF40H
3
00C0H
2
0080H
1
0040H
0
0000H
1
1
3
2
5
3
2,048 1,024 2,048 1,024 2,048 1,024
2,043 1,022 2,045 1,023 2,047 1
2,048 1,024 2,048 1,024 2,048
Input voltage/AVREF0
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(6) Power-fail compare mode register (ADA0PFM)
The ADA0PFM register is an 8-bit register that sets the power-fail compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
ADA0PFM
Address: FFFFF204H
6
ADA0PFE ADA0PFC
ADA0PFE
5
4
3
2
1
0
0
0
0
0
0
0
Selection of power-fail compare enable/disable
0
Power-fail compare disabled
1
Power-fail compare enabled
ADA0PFC
Selection of power-fail compare mode
0
Generates an interrupt request signal (INTAD) when ADA0CRnH ≥ ADA0PFT
1
Generates an interrupt request signal (INTAD) when ADA0CRnH < ADA0PFT
Cautions 1. In the select mode, the 8-bit data set to the ADA0PFT register is compared with the
value of the ADA0CRnH register specified by the ADA0S register. If the result matches
the condition specified by the ADA0PFC bit, the conversion result is stored in the
ADA0CRn register and the INTAD signal is generated. If it does not match, however,
the interrupt signal is not generated.
2. In the scan mode, the 8-bit data set to the ADA0PFT register is compared with the
contents of the ADA0CR0H register. If the result matches the condition specified by
the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register and the
INTAD signal is generated. If it does not match, however, the INTAD signal is not
generated. Regardless of the comparison result, the scan operation is continued and
the conversion result is stored in the ADA0CRn register until the scan operation is
completed. However, the INTAD signal is not generated after the scan operation has
been completed.
3. In the following modes, write data to the ADA0PFM register while A/D conversion is
stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation
(ADA0CE bit = 1).
• Normal conversion mode
• One-shot select mode/one-shot scan mode in high-speed conversion mode
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(7) Power-fail compare threshold value register (ADA0PFT)
The ADA0PFT register sets the compare value in the power-fail compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
7
6
Address: FFFFF205H
5
4
3
2
1
0
ADA0PFT
Caution
In the following modes, write data to the ADA0PFT register while A/D conversion is
stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation
(ADA0CE bit = 1).
• Normal conversion mode
• One-shot select mode/one-shot scan mode in high-speed conversion mode
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15.5 Operation
15.5.1 Basic operation
Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0,
ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is
started in the software trigger mode and the A/D converter waits for a trigger in the external or timer trigger mode.
When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the sample
& hold circuit.
When the sample & hold circuit samples the input channel for a specific time, it enters the hold status, and holds
the input analog voltage until A/D conversion is complete.
Set bit 9 of the successive approximation register (SAR), and set the compare voltage generation DAC to (1/2)
AVREF0.
The voltage difference between the voltage of the compare voltage generation DAC and the analog input voltage
is compared by the voltage comparator. If the analog input voltage is higher than (1/2) AVREF0, the MSB of the
SAR remains set. If it is lower than (1/2) AVREF0, the MSB is reset.
Next, bit 8 of the SAR is automatically set and the next comparison is started. Depending on the value of bit 9, to
which a result has been already set, the compare voltage generation DAC is selected as follows.
• Bit 9 = 1: (3/4) AVREF0
• Bit 9 = 0: (1/4) AVREF0
This compare voltage and the analog input voltage are compared and, depending on the result, bit 8 is
manipulated as follows.
Analog input voltage ≥ Compare voltage: Bit 8 = 1
Analog input voltage ≤ Compare voltage: Bit 8 = 0
This comparison is continued to bit 0 of the SAR.
When comparison of the 10 bits is complete, the valid digital result remains in the SAR, and is then transferred to
and stored in the ADA0CRn register. After that, an A/D conversion end interrupt request signal (INTAD) is
generated.
In one-shot select mode, conversion is stoppedNote. In one-shot scan mode, conversion is stopped after scanning
Note
once
. In continuous select mode, repeat steps to until the ADA0M0.ADA0CE bit is cleared to 0. In
continuous scan mode, repeat steps to for each channel.
Note In the external trigger mode, timer trigger mode 0, or timer trigger mode 1, the trigger standby status is
entered.
Remark
The trigger standby status means the status after the stabilization time has elapsed.
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15.5.2 Conversion operation timing
Figure 15-3. Conversion Operation Timing (Continuous Conversion)
(1) Operation in normal conversion mode (ADA0HS1 bit = 0)
ADA0M0.ADA0CE bit
First conversion
Setup
Processing state
Sampling
Second conversion
A/D conversion
Wait
Conversion time
Wait time
Setup
Sampling
INTAD signal
Stabilization
time
2/fXX (MAX.)
Sampling
time
0.5/fXX
(2) Operation in high-speed conversion mode (ADA0HS1 bit = 1)
ADA0M0.ADA0CE bit
First conversion
Setup
Processing state
Sampling
Second conversion
A/D conversion
Sampling
A/D conversion
INTAD signal
Stabilization
time
2/fXX (MAX.)
Remark
Conversion time
Sampling
time
0.5/fXX
The above timings are applicable when a trigger is generated within the stabilization time. If a
trigger is generated after the stabilization time has elapsed, a trigger response time is inserted.
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15.5.3 Trigger mode
The timing of starting the conversion operation is specified by setting the trigger mode. The trigger mode includes the
software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and
external trigger mode. The ADA0M0.ADA0TMD bit is used to set the trigger mode. The hardware trigger modes are set
by the ADA0M2.ADA0TMD1 and ADA0M2.ADA0TMD0 bits.
(1) Software trigger mode
When the ADA0M0.ADA0CE bit is set to 1, the signal of the analog input pin (ANI0 to ANI11 pin) specified by the
ADA0S register is converted. When conversion is complete, the result is stored in the ADA0CRn register. At the
same time, the A/D conversion end interrupt request signal (INTAD) is generated.
If the operation mode specified by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits is the continuous
select/scan mode, the next conversion is repeated, unless the ADA0CE bit is cleared to 0 after completion of the
conversion. Conversion is performed once and ends if the operation mode is the one-shot select/scan mode.
When conversion is started, the ADA0M0.ADA0EF bit is set to 1 (indicating that conversion is in progress).
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the conversion is
aborted and started again from the beginning. However, writing to these registers is prohibited in the normal
conversion mode and one-shot select mode/one-shot scan mode in the high-speed conversion mode.
(2) External trigger mode
In this mode, converting the signal of the analog input pin (ANI0 to ANI11) specified by the ADA0S register is
started when an external trigger is input (to the ADTRG pin). Which edge of the external trigger is to be detected
(i.e., the rising edge, falling edge, or both rising and falling edges) can be specified by using the
ADA0M0.ADA0ETS1 and ADA0M0.ATA0ETS0 bits. When the ADA0CE bit is set to 1, the A/D converter waits for
the trigger, and starts conversion after the external trigger has been input.
When conversion is completed, the result of conversion is stored in the ADA0CRn register, regardless of whether
the continuous select, continuous scan, one-shot select, or one-shot scan mode is set as the operation mode by
the ADA0MD1 and ADA0MD0 bits. At the same time, the INTAD signal is generated, and the A/D converter waits
for the trigger again.
When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the A/D
converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is stopped).
If the valid trigger is input during the conversion operation, the conversion is aborted and started again from the
beginning.
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during the conversion operation, the
conversion is aborted, and the A/D converter waits for the trigger again. However, writing to these registers is
prohibited in the one-shot select mode/one-shot scan mode.
Caution
To select the external trigger mode, set the high-speed conversion mode. Do not input a trigger
during the stabilization time that is inserted once after the A/D conversion operation is enabled
(ADA0M0.ADA0CE bit = 1).
Remark
The trigger standby status means the status after the stabilization time has elapsed.
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(3) Timer trigger mode
In this mode, converting the signal of the analog input pin (ANI0 to ANI11) specified by the ADA0S register is
started by the compare match interrupt request signal (INTTAA2CC0 or INTTAA2CC1) of the capture/compare
register connected to the timer. The INTTAA2CC0 or INTTAA2CC1 signal is selected by the ADA0TMD1 and
ADA0TMD0 bits, and conversion is started at the rising edge of the specified compare match interrupt request
signal. When the ADA0CE bit is set to 1, the A/D converter waits for a trigger, and starts conversion when the
compare match interrupt request signal of the timer is input.
When conversion is completed, regardless of whether the continuous select, continuous scan, one-shot select, or
one-shot scan mode is set as the operation mode by the ADA0MD1 and ADA0MD0 bits, the result of the conversion
is stored in the ADA0CRn register. At the same time, the INTAD signal is generated, and the A/D converter waits
for the trigger again.
When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the A/D
converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is stopped).
If the valid trigger is input during the conversion operation, the conversion is aborted and started again from the
beginning.
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the conversion is
stopped and the A/D converter waits for the trigger again. However, writing to these registers is prohibited in the
one-shot select mode/one-shot scan mode.
Caution
To select the timer trigger mode, set the high-speed conversion mode. Do not input a trigger
during the stabilization time that is inserted once after the A/D conversion operation is enabled
(ADA0M0.ADA0CE bit = 1).
Remark
The trigger standby status means the status after the stabilization time has elapsed.
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15.5.4 Operation mode
Four operation modes are available as the modes in which to set the ANI0 to ANI11 pins: continuous select mode,
continuous scan mode, one-shot select mode, and one-shot scan mode.
The operation mode is selected by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits.
(1) Continuous select mode
In this mode, the voltage of one analog input pin selected by the ADA0S register is continuously converted into a
digital value.
The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an
analog input pin corresponds to an ADA0CRn register on a one-to-one basis. Each time A/D conversion is
completed, the A/D conversion end interrupt request signal (INTAD) is generated. After completion of conversion,
the next conversion is started, unless the ADA0M0.ADA0CE bit is cleared to 0 (n = 0 to 11).
Figure 15-4. Timing Example of Continuous Select Mode Operation (ADA0S Register = 01H)
ANI1
Data 4
Data 1
Data 1
(ANI1)
A/D conversion
Data 2
Data 3
Data 2
(ANI1)
Data 3
(ANI1)
Data 1
(ANI1)
ADA0CR1
Data 2
(ANI1)
Data 4
(ANI1)
Data 3
(ANI1)
Data 5
Data 5
(ANI1)
Data 4
(ANI1)
Data 6
Data 7
Data 6
(ANI1)
Data 7
(ANI1)
Data 6
(ANI1)
INTAD
Conversion start
Set ADA0CE bit = 1
Conversion start
Set ADA0CE bit = 1
(2) Continuous scan mode
In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S
register, and their values are continuously converted into digital values.
The result of each conversion is stored in the ADA0CRn register corresponding to the analog input pin. When
conversion of the analog input pin specified by the ADA0S register is complete, the INTAD signal is generated, and
A/D conversion is started again from the ANI0 pin, unless the ADA0CE bit is cleared to 0 (n = 0 to 11).
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Figure 15-5. Timing Example of Continuous Scan Mode Operation (ADA0S Register = 03H)
(a) Timing example
ANI0
Data 1
Data 5
ANI1
Data 6
Data 2
Data 7
Data 3
ANI2
ANI3
Data 4
Data 1
(ANI0)
A/D conversion
Data 2
(ANI1)
Data 1
(ANI0)
ADA0CRn
Data 3
(ANI2)
Data 2
(ANI1)
Data 4
(ANI3)
Data 3
(ANI2)
Data 5
(ANI0)
Data 4
(ANI3)
Data 6
(ANI1)
Data 5
(ANI0)
Data 7
(ANI2)
Data 6
(ANI1)
INTAD
Conversion start
Set ADA0CE bit = 1
(b) Block diagram
Analog input pin
ADA0CRn register
ANI0
ADA0CR0
ANI1
ADA0CR1
ANI2
ADA0CR2
ANI3
A/D converter
ADA0CR3
ANI4
ADA0CR4
ANI5
.
.
.
.
ADA0CR5
.
.
.
ANI9
ADA0CR9
ANI10
ADA0CR10
ANI11
ADA0CR11
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(3) One-shot select mode
In this mode, the voltage of one analog input pin specified by the ADA0S register is converted into a digital value
only once.
The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an
analog input pin and an ADA0CRn register correspond on a one-to-one basis. When A/D conversion has been
completed once, the INTAD signal is generated. The A/D conversion operation is stopped after it has been
completed (n = 0 to 11).
Figure 15-6. Timing Example of One-Shot Select Mode Operation (ADA0S Register = 01H)
ANI1
Data 4
Data 1
Data 2
Data 3
Data 1
(ANI1)
A/D conversion
Data 5
Data 6
Data 7
Data 6
(ANI1)
Data 1
(ANI1)
ADA0CR1
Data 6
(ANI1)
INTAD
Conversion end
Conversion start
Set ADA0CE bit = 1
Conversion end
Conversion start
Set ADA0CE bit = 1
(4) One-shot scan mode
In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S
register, and their values are converted into digital values .
Each conversion result is stored in the ADA0CRn register corresponding to the analog input pin. When conversion
of the analog input pin specified by the ADA0S register is complete, the INTAD signal is generated. A/D conversion
is stopped after it has been completed (n = 0 to 11).
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Figure 15-7. Timing Example of One-Shot Scan Mode Operation (ADA0S Register = 03H)
(a) Timing example
ANI0
Data 1
ANI1
Data 2
Data 3
ANI2
ANI3
Data 4
Data 1
(ANI0)
A/D conversion
Data 2
(ANI1)
Data 1
(ANI0)
ADA0CRn
Data 3
(ANI2)
Data 2
(ANI1)
Data 4
(ANI3)
Data 3
(ANI2)
Data 4
(ANI3)
INTAD
Conversion end
Conversion start
Set ADA0CE bit = 1
(b) Block diagram
Analog input pin
ADA0CRn register
ANI0
ADA0CR0
ANI1
ADA0CR1
ANI2
ADA0CR2
ANI3
A/D converter
ADA0CR3
ANI4
ADA0CR4
ANI5
.
.
.
.
ADA0CR5
.
.
.
ANI9
ADA0CR9
ANI10
ADA0CR10
ANI11
ADA0CR11
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15.5.5 Power-fail compare mode
The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT
registers.
• When the ADA0PFM.ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed (normal
use of the A/D converter).
• When the ADA0PFE bit = 1 and when the ADA0PFM.ADA0PFC bit = 0, the value of the ADA0CRnH register is
compared with the value of the ADA0PFT register when conversion is completed, and the INTAD signal is generated
only if ADA0CRnH ≥ ADA0PFT.
• When the ADA0PFE bit = 1 and when the ADA0PFC bit = 1, the value of the ADA0CRnH register is compared with
the value of the ADA0PFT register when conversion is completed, and the INTAD signal is generated only if
ADA0CRnH < ADA0PFT.
Remark
n = 0 to 11
In the power-fail compare mode, four modes are available as modes in which to set the ANI0 to ANI11 pins: continuous
select mode, continuous scan mode, one-shot select mode, and one-shot scan mode.
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(1) Continuous select mode
In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is
compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition
set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is
generated. If it does not match, the conversion result is stored in the ADA0CRn register, and the INTAD signal is
not generated. After completion of the first conversion, the next conversion is started, unless the ADA0M0.ADA0CE
bit is cleared to 0 (n = 0 to 11).
Figure 15-8. Timing Example of Continuous Select Mode Operation
(When Power-Fail Comparison Is Made: ADA0S Register = 01H)
ANI1
Data 4
Data 1
Data 1
(ANI1)
A/D conversion
ADA0CR1
Data 2
Data 3
Data 2
(ANI1)
Data 3
(ANI1)
Data 4
(ANI1)
Data 1
(ANI1)
Data 2
(ANI1)
Data 3
(ANI1)
ADA0PFT
unmatch
ADA0PFT
unmatch
ADA0PFT
match
Data 5
Data 5
(ANI1)
Data 4
(ANI1)
Data 6
Data 7
Data 6
(ANI1)
Data 7
(ANI1)
Data 6
(ANI1)
INTAD
Conversion start
Set ADA0CE bit = 1
ADA0PFT
ADA0PFT
match
match
Conversion start
Set ADA0CE bit = 1
(2) Continuous scan mode
In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0 pin
to the pin specified by the ADA0S register are stored, and the set value of the ADA0CR0H register of channel 0 is
compared with the value of the ADA0PFT register. If the result of power-fail comparison matches the condition set
by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register, and the INTAD signal is generated. If
it does not match, the conversion result is stored in the ADA0CR0 register, and the INTAD signal is not generated.
After the result of the first conversion has been stored in the ADA0CR0 register, the results of sequentially
converting the voltages on the analog input pins up to the pin specified by the ADA0S register are continuously
stored. After completion of conversion, the next conversion is started from the ANI0 pin again, unless the ADA0CE
bit is cleared to 0.
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CHAPTER 15 A/D CONVERTER
Figure 15-9. Timing Example of Continuous Scan Mode Operation
(When Power-Fail Comparison Is Made: ADA0S Register = 03H)
(a) Timing example
ANI0
Data 1
Data 5
ANI1
Data 6
Data 2
Data 7
Data 3
ANI2
ANI3
Data 4
Data 1
(ANI0)
A/D conversion
Data 2
(ANI1)
Data 1
(ANI0)
ADA0CRn
Data 3
(ANI2)
Data 2
(ANI1)
Data 4
(ANI3)
Data 3
(ANI2)
Data 5
(ANI0)
Data 4
(ANI3)
Data 6
(ANI1)
Data 5
(ANI0)
Data 7
(ANI2)
Data 6
(ANI1)
INTAD
ADA0PFT
match
ADA0PFT
unmatch
Conversion start
Set ADA0CE bit = 1
(b) Block diagram
Analog input pin
ADA0CRn register
ANI0
ADA0CR0
ANI1
ADA0CR1
ANI2
ADA0CR2
ANI3
A/D converter
ADA0CR3
ANI4
ADA0CR4
ANI5
.
.
.
.
ADA0CR5
.
.
.
ANI9
ADA0CR9
ANI10
ADA0CR10
ANI11
ADA0CR11
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(3) One-shot select mode
In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is
compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition
set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is
generated. If it does not match, the conversion result is stored in the ADA0CRn register, and the INTAD signal is
not generated. Conversion is stopped after it has been completed.
Figure 15-10. Timing Example of One-Shot Select Mode Operation
(When Power-Fail Comparison Is Made: ADA0S Register = 01H)
ANI1
Data 4
Data 1
Data 2
Data 1
(ANI1)
A/D conversion
Data 5
Data 6
Data 7
Data 6
(ANI1)
Data 1
(ANI1)
ADA0CR1
Data 3
Data 6
(ANI1)
INTAD
ADA0PFT unmatch
Conversion end
Conversion start
Set ADA0CE bit = 1
ADA0PFT match
Conversion end
Conversion start
Set ADA0CE bit = 1
(4) One-shot scan mode
In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0 pin
to the pin specified by the ADA0S register are stored, and the set value of the ADA0CR0H register of channel 0 is
compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition
set by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register and the INTAD signal is generated.
If it does not match, the conversion result is stored in the ADA0CR0 register, and the INTAD0 signal is not
generated.
After the result of the first conversion has been stored in the ADA0CR0 register, the results of
converting the signals on the analog input pins specified by the ADA0S register are sequentially stored. The
conversion is stopped after it has been completed.
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CHAPTER 15 A/D CONVERTER
Figure 15-11. Timing Example of One-Shot Scan Mode Operation
(When Power-Fail Comparison Is Made: ADA0S Register = 03H)
(a) Timing example
ANI0
Data 1
ANI1
Data 2
Data 3
ANI2
ANI3
Data 4
Data 1
(ANI0)
A/D conversion
Data 2
(ANI1)
Data 1
(ANI0)
ADA0CRn
Data 3
(ANI2)
Data 2
(ANI1)
Data 4
(ANI3)
Data 3
(ANI2)
Data 4
(ANI3)
INTAD
Conversion start
Set ADA0CE bit = 1
ADA0PFT
match
Conversion end
(b) Block diagram
Analog input pin
ADA0CRn register
ANI0
ADA0CR0
ANI1
ADA0CR1
ANI2
ADA0CR2
ANI3
A/D converter
ADA0CR3
ANI4
ADA0CR4
ANI5
.
.
.
.
ADA0CR5
.
.
.
ANI9
ADA0CR9
ANI10
ADA0CR10
ANI11
ADA0CR11
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CHAPTER 15 A/D CONVERTER
15.6 Cautions
(1) When A/D converter is not used
When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0M0.ADA0CE bit
to 0.
(2) Input range of ANI0 to ANI11 pins
Input the voltage within the specified range to the ANI0 to ANI11 pins. If a voltage equal to or higher than AVREF0 or
equal to or lower than AVSS (even within the range of the absolute maximum ratings) is input to any of these pins,
the conversion value of that channel is undefined, and the conversion value of the other channels may also be
affected.
(3) Countermeasures against noise
To maintain the 10-bit resolution, the ANI0 to ANI11 pins must be effectively protected from noise. The effect of
noise increases as the output impedance of the analog input source becomes higher.
To lower the noise,
connecting an external capacitor as shown in Figure 15-12 is recommended.
Figure 15-12. Processing of Analog Input Pin
Clamp with a diode with a low VF (0.3 V or less)
if noise equal to or higher than AVREF0 or equal
to or lower than AVSS may be generated.
VDD
AVREF0
ANI0 to ANI11
AVSS
VSS
(4) Alternate I/O
The analog input pins (ANI0 to ANI11) function alternately as port pins. When selecting one of the ANI0 to ANI11
pins to execute A/D conversion, do not execute an instruction to read an input port or write to an output port during
conversion as the conversion resolution may drop.
Also the conversion resolution may drop at the pins set as output port pins during A/D conversion if the output
current fluctuates due to the effect of the external circuit connected to the port pins.
If a digital pulse is applied to a pin adjacent to the pin whose input signal is being converted, the A/D conversion
value may not be as expected due to the effect of coupling noise. Therefore, do not apply a pulse to a pin adjacent
to the pin undergoing A/D conversion.
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(5) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the
analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected
analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the
ADA0S register is rewritten. If the ADIF flag is read immediately after the ADA0S register is rewritten, the ADIF flag
may be set even though the A/D conversion of the newly selected analog input pin has not been completed. When
A/D conversion is stopped, clear the ADIF flag before resuming conversion.
Figure 15-13. Generation Timing of A/D Conversion End Interrupt Request
ADA0S rewriting
(ANIn conversion start)
ADA0S rewriting
(ANIm conversion start)
ANIn
A/D conversion
ADIF is set, but ANIm
conversion does not end
ANIn
ADA0CRn
ANIn
ANIm
ANIm
ANIn
ANIm
ANIm
INTAD
Remark
n = 0 to 11
m = 0 to 11
(6) Internal equivalent circuit
The following shows the equivalent circuit of the analog input block.
Figure 15-14. Internal Equivalent Circuit of ANIn Pin
RIN
ANIn
CIN
RIN
CIN
14 kΩ
8.4 pF
Remarks 1. The above values are reference values.
2. n = 0 to 11
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(7) AVREF0 pin
(a) The AVREF0 pin is used as the power supply pin of the A/D converter and also supplies power to the alternatefunction ports. In an application where a backup power supply is used, be sure to supply the same potential as
VDD to the AVREF0 pin as shown in Figure 15-15.
(b) The AVREF0 pin is also used as the reference voltage pin of the A/D converter. If the source supplying power to
the AVREF0 pin has a high impedance or if the power supply has a low current supply capability, the reference
voltage may fluctuate due to the current that flows during conversion (especially, immediately after the
conversion operation enable bit ADA0CE has been set to 1). As a result, the conversion accuracy may drop.
To avoid this, it is recommended to connect a capacitor across the AVREF0 and AVSS pins to suppress the
reference voltage fluctuation as shown in Figure 15-15.
(c) If the source supplying power to the AVREF0 pin has a high DC resistance (for example, because of insertion of
a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped,
because of a voltage drop caused by the A/D conversion current.
Figure 15-15. AVREF0 Pin Processing Example
Note
AVREF0
Main power supply
AVSS
Note Parasitic inductance
(8) Reading ADA0CRn register
When the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written, the contents of the ADA0CRn
register may be undefined. Read the conversion result after completion of conversion and before writing to the
ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register.
Also, when an external/timer trigger is
acknowledged, the contents of the ADA0CRn register may be undefined.
Read the conversion result after
completion of conversion and before the next external/timer trigger is acknowledged. The correct conversion result
may not be read at a timing different from the above.
(9) External trigger mode
When using the external trigger mode, the input trigger during A/D conversion will not be acknowledged.
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(10) Standby mode
Because the A/D converter stops operating in the STOP mode, the conversion results are invalid, so power
consumption can be reduced. Operations are resumed after the STOP mode is released, but the A/D conversion
results after the STOP mode is released are invalid. When using the A/D converter after the STOP mode is
released, clear the ADA0M0.ADA0CE bit to 0 before setting the STOP mode or after releasing the STOP mode,
then set the ADA0CE bit to 1 after releasing the STOP mode.
In the IDLE1, IDLE2, or subclock operation mode, operation continues.
To lower the power consumption,
therefore, clear the ADA0M0.ADA0CE bit to 0. In the IDLE1 and IDLE2 modes, since the analog input voltage
value cannot be retained, the A/D conversion results after the IDLE1 and IDLE2 modes are released are invalid.
The results of conversions before the IDLE1 and IDLE2 modes were set are valid.
(11) High-speed conversion mode
In the high-speed conversion mode, rewriting the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT
registers and trigger input during the stabilization time are prohibited.
(12) A/D conversion time
The A/D conversion time is the total of the stabilization time, conversion time, wait time, and trigger response time
(for details of these times, refer to Table 15-2 Conversion Time Selection in Normal Conversion Mode
(ADA0HS1 Bit = 0) and Table 15-3 Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1
Bit = 1)).
During A/D conversion in the normal conversion mode, if the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and
ADA0PFT registers are written or a trigger is input, reconversion is carried out. However, if the stabilization time
end timing conflicts with writing to these registers, or if the stabilization time end timing conflicts with the trigger
input, a stabilization time of 64 clocks is reinserted.
If a conflict occurs again with the reinserted stabilization time end timing, the stabilization time is reinserted.
Therefore do not set the trigger input interval and control register write interval to 64 clocks or lower.
(13) Variation of A/D conversion results
The results of A/D conversion may vary due to a fluctuation in the supply voltage or the effect of noise. To reduce
this variation, take countermeasures with the program such as averaging the A/D conversion results.
(14) A/D conversion result hysteresis characteristics
The successive comparison type A/D converter holds the analog input voltage in the internal sample & hold
capacitor and then performs A/D conversion. After A/D conversion has finished, the analog input voltage remains
in the internal sample & hold capacitor. As a result, the following phenomena may occur.
• When the same channel is used for A/D conversions, if the voltage is higher or lower than the previous A/D
conversion, then hysteresis characteristics may appear in which the conversion result is affected by the
previous value. Thus, even if the conversion is performed at the same potential, the result may vary.
• When switching the analog input channel, hysteresis characteristics may appear in which the conversion result
is affected by the previous channel value. This is because one A/D converter is used for the A/D conversions.
Thus, even if the conversion is performed at the same potential, the result may vary.
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15.7 How to Read A/D Converter Characteristics Table
This section describes the terms related to the A/D converter.
(1) Resolution
The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital
output is called 1 LSB (least significant bit). The ratio of 1 LSB to the full scale is expressed as %FSR (full-scale
range). %FSR is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be
expressed as follows, independently of the resolution.
1%FSR = (Maximum value of convertible analog input voltage – Minimum value of convertible analog
input voltage)/100
= (AVREF0 − 0)/100
= AVREF0/100
When the resolution is 10 bits, 1 LSB is as follows:
1 LSB = 1/210 = 1/1,024
= 0.098%FSR
The accuracy is determined by the overall error, independently of the resolution.
(2) Overall error
This is the maximum value of the difference between an actually measured value and a theoretical value.
It is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors.
The overall error in the characteristics table does not include the quantization error.
Figure 15-16. Overall Error
1......1
Digital output
Ideal line
Overall error
0......0
0
AVREF0
Analog input
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(3) Quantization error
This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because
the A/D converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, a quantization
error is unavoidable.
This error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or differential
linearity error in the characteristics table.
Figure 15-17. Quantization Error
Digital output
1......1
1/2 LSB
Quantization error
1/2 LSB
0......0
0
AVREF0
Analog input
(4) Zero-scale error
This is the difference between the actually measured analog input voltage and its theoretical value when the digital
output changes from 0…000 to 0…001 (1/2 LSB).
Figure 15-18. Zero-Scale Error
Digital output (lower 3 bits)
111
Ideal line
100
Zero-scale error
011
010
001
000
−1
0
1
2
3
AVREF0
Analog input (LSB)
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(5) Full-scale error
This is the difference between the actually measured analog input voltage and its theoretical value when the digital
output changes from 1…110 to 1…111 (full scale − 3/2 LSB).
Figure 15-19. Full-Scale Error
Digital output (lower 3 bits)
Full-scale error
111
100
011
010
000
0
AVREF0 − 3 AVREF0 − 2 AVREF0 − 1 AVREF0
Analog input (LSB)
(6) Differential linearity error
Ideally, the width to output a specific code is 1 LSB. This error indicates the difference between the actually
measured value and its theoretical value when a specific code is output. This indicates the basic characteristics of
the A/D conversion when the voltage applied to the analog input pins of the same channel is consistently increased
bit by bit from AVSS to AVREF0. When the input voltage is increased or decreased, or when two or more channels
are used, see 15.7 (2) Overall error.
Figure 15-20. Differential Linearity Error
1......1
Digital output
Ideal width of 1 LSB
Differential
linearity error
0......0
AVREF0
Analog input
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(7) Integral linearity error
This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It
indicates the maximum value of the difference between the actually measured value and its theoretical value where
the zero-scale error and full-scale error are 0.
Figure 15-21. Integral Linearity Error
1......1
Digital output
Ideal line
Integral
linearity error
0......0
0
AVREF0
Analog input
(8) Conversion time
This is the time required to obtain a digital output after each trigger has been generated.
The conversion time in the characteristics table includes the sampling time.
(9) Sampling time
This is the time for which the analog switch is ON to load an analog voltage to the sample & hold circuit.
Figure 15-22. Sampling Time
Sampling time
Conversion time
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CHAPTER 16 D/A CONVERTER
CHAPTER 16 D/A CONVERTER
16.1 Functions
The D/A converter has the following functions.
8-bit resolution × 2 channels (DA0CS0, DA0CS1)
R-2R ladder method
Settling time: 3 μs max. (when AVREF1 is 3.0 to 3.6 V and external load is 20 pF)
Analog output voltage: AVREF1 × m/256 (m = 0 to 255; value set to DA0CSn register)
Operation modes: Normal mode, real-time output mode
Remark
n = 0, 1
16.2 Configuration
The D/A converter configuration is shown below.
Figure 16-1. Block Diagram of D/A Converter
DACS0 register write
DA0M.DAMD0 bit
DACS0 register
INTTAA2CC0 signal
ANO0 pin
DA0M.DACE0 bit
AVREF1 pin
Selector
AVSS pin
ANO1 pin
Selector
DA0M.DACE1 bit
DACS1 register write
DA0M.DAMD1 bit
INTTAA3CC0 signal
DACS1 register
Cautions 1. DAC0 and DAC1 share the AVREF1 pin.
2. DAC0 and DAC1 share the AVSS pin. The AVSS pin is also shared by the A/D converter.
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The D/A converter includes the following hardware.
Table 16-1. Configuration of D/A Converter
Item
Configuration
D/A converter mode register (DA0M)
Control registers
D/A conversion value setting registers 0, 1 (DA0CS0, DA0CS1)
16.3 Registers
The registers that control the D/A converter are as follows.
• D/A converter mode register (DA0M)
• D/A conversion value setting registers 0, 1 (DA0CS0, DA0CS1)
(1) D/A converter mode register (DA0M)
The DA0M register controls the operation of the D/A converter.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address: FFFFF282H
< >
DA0M
0
DA0CEn
0
DA0CE1 DA0CE0
0
0
DA0MD1 DA0MD0
Control of D/A converter operation enable/disable (n = 0, 1)
0
Disables operation
1
Enables operation
DA0MDn
< >
Selection of D/A converter operation mode (n = 0, 1)
0
Normal mode
1
Real-time output modeNote
Note The output trigger in the real-time output mode (DA0MDn bit = 1) is as follows.
• When n = 0: INTTAA2CC0 signal (see CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA))
• When n = 1: INTTAA3CC0 signal (see CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA))
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CHAPTER 16 D/A CONVERTER
(2) D/A conversion value setting registers 0, 1 (DA0CS0, DA0CS1)
The DA0CS0 and DA0CS1 registers set the analog voltage value output to the ANO0 and ANO1 pins.
These registers can be read or written in 8-bit units.
Reset sets these registers to 00H.
After reset: 00H
DA0CSn
Caution
R/W
Address: DA0CS0 FFFFF280H, DA0CS1 FFFFF281H
DA0CSn7 DA0CSn6 DA0CSn5 DA0CSn4 DA0CSn3 DA0CSn2 DA0CSn1 DA0CSn0
In the real-time output mode (DA0M.DA0MDn bit = 1), set the DA0CSn register before the
INTTAA2CC0/INTTAA3CC0 signals are generated.
D/A conversion starts when the
INTTAA2CC0/INTTAA3CC0 signals are generated.
Remark
n = 0, 1
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CHAPTER 16 D/A CONVERTER
16.4 Operation
16.4.1 Operation in normal mode
D/A conversion is performed using a write operation to the DA0CSn register as the trigger.
The setting method is described below.
Set the DA0M.DA0MDn bit to 0 (normal mode).
Set the analog voltage value to be output to the ANOn pin to the DA0CSn register.
Steps and above constitute the initial settings.
Set the DA0M.DA0CEn bit to 1 (D/A conversion enable).
D/A conversion starts when this setting is performed.
To perform subsequent D/A conversions, write to the DA0CSn register.
The previous D/A conversion result is held until the next D/A conversion is performed.
Remarks 1. For the alternate-function pin settings, see Table 4-20 Using Port Pins as Alternate-Function Pins.
2. n = 0, 1
16.4.2 Operation in real-time output mode
D/A conversion is performed using the interrupt request signals (INTTAA2CC0 and INTTAA3CC0) of TAA2 and TAA3
as triggers.
The setting method is described below.
Set the DA0M.DA0MDn bit to 1 (real-time output mode).
Set the analog voltage value to be output to the ANOn pin to the DA0CSn register.
Set the DA0M.DA0CEn bit to 1 (D/A conversion enable).
Steps to above constitute the initial settings.
Operate TAA2 and TAA3.
D/A conversion starts when the INTTAA2CC0 and INTTAA3CC0 signals are generated.
After that, the value set in DA0CSn register is output every time the INTTAA2CC0 and INTTAA3CC0 signals are
generated.
Remarks 1. The output values of the ANO0 and ANO1 pins up to above are undefined.
2. For the output values of the ANO0 and ANO1 pins in the HALT, IDLE1, IDLE2, and STOP modes, see
CHAPTER 21 STANDBY FUNCTION.
3. For the alternate-function pin settings, see Table 4-20 Using Port Pins as Alternate-Function Pins.
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CHAPTER 16 D/A CONVERTER
16.4.3 Cautions
Observe the following cautions when using the D/A converter of the V850ES/JG3-H and V850ES/JH3-H.
(1) Do not change the set value of the DA0CSn register while the trigger signal is being issued in the real-time output
mode.
(2) Before changing the operation mode, be sure to clear the DA0M.DA0CEn bit to 0.
(3) When using one of the P10/AN00 and P11/AN01 pins as an I/O port and the other as a D/A output pin, do so in an
application where the port I/O level does not change during D/A output.
(4) Make sure that AVREF0 = VDD = AVREF1 = 3.0 to 3.6 V. If this range is exceeded, the operation is not guaranteed.
(5) Apply power to AVREF1 at the same timing as AVREF0.
(6) No current can be output from the ANOn pin (n = 0, 1) because the output impedance of the D/A converter is high.
When connecting a resistor of 2 MΩ or less, insert a JFET input operational amplifier between the resistor and the
ANOn pin.
Figure 16-2. External Pin Connection Example
−
Output
ANOn
+
AVREF0
AVSS
AVREF1
JFET input
operational amplifier
0.1 μF
10 μ F
0.1 μF
10 μ F
VDD
(7) Because the D/A converter stops operating in the STOP mode, the ANO0 and ANO1 pins go into a high-impedance
state, and the power consumption can be reduced.
In the IDLE1, IDLE2, or subclock operation mode, however, operation continues. To lower the power consumption,
therefore, clear the DA0M.DA0CEn bit to 0.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
The V850ES/JG3-H and V850ES/JH3-H have a 5-channel UARTC.
17.1 Features
{ Transfer rate: 300 bps to 3 Mbps (using internal system clock of 24 MHz and dedicated baud rate generator)
{ Full-duplex communication: Internal UARTCn receive data register (UCnRX)
Internal UARTCn transmit data register (UCnTX)
{ 2-pin configuration:
TXDCn: Transmit data output pin
RXDCn: Receive data input pin
{ Reception error detection function
• Parity error
• Framing error
• Overrun error
{ Interrupt sources: 2 types
• Reception completion interrupt (INTUCnR):
This interrupt occurs upon transfer of receive data from the receive
shift register to the receive data register after serial transfer is
complete, in the reception enabled status.
• Transmission enable interrupt (INTUCnT):
This interrupt occurs upon transfer of transmit data from the
transmit data register to the transmit shift register in the
transmission enabled status.
{ Character length: 7 to 9 bits
{ Parity function: Odd, even, 0, none
{ Transmission stop bit: 1, 2 bits
{ On-chip dedicated baud rate generator
{ MSB-/LSB-first transfer selectable
{ Transmit/receive data inverted input/output possible
{ SBF (Sync Break Field) transmission in the LIN (Local Interconnect Network) communication format
• 13 to 20 bits selectable for the SBF transmission
• Recognition of 11 bits or more possible for SBF reception
• SBF reception flag provided
Remark
n = 0 to 4
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.2 Configuration
The block diagram of the UARTCn is shown below.
Figure 17-1. Block Diagram of Asynchronous Serial Interface Cn
Internal bus
INTUCnT
INTUCnR
UCnRX
Reception unit
Transmission
unit
UCnTX
Receive
shift register
Reception
controller
Transmission
controller
Transmit
shift register
Filter
Baud rate
generator
Baud rate
generator
Selector
RXDCn
Clock
selector
Selector
fXX to fXX/210
ASCKC0Note
TXDCn
UCnCTL1
UCnCTL2
UCnCTL0
UCnSTR
UCnOPT0
Internal bus
Note UARTC0 only
Remarks 1. n = 0 to 4
2. For the configuration of the baud rate generator, see Figure 17-19.
UARTCn includes the following hardware.
Table 17-1. Configuration of UARTCn
Item
Registers
Configuration
UARTCn control register 0 (UCnCTL0)
UARTCn control register 1 (UCnCTL1)
UARTCn control register 2 (UCnCTL2)
UARTCn option control register 0 (UCnOPT0)
UARTCn option control register 1 (UCnOPT1)
UARTCn status register (UCnSTR)
UARTCn receive shift register
UARTCn receive data register (UCnRX)
UARTCn transmit shift register
UARTCn transmit data register (UCnTX)
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
(1) UARTCn control register 0 (UCnCTL0)
The UCnCTL0 register is an 8-bit register used to specify the UARTCn operation.
(2) UARTCn control register 1 (UCnCTL1)
The UCnCTL1 register is an 8-bit register used to select the input clock for the UARTCn.
(3) UARTCn control register 2 (UCnCTL2)
The UCnCTL2 register is an 8-bit register used to control the baud rate for the UARTCn.
(4) UARTCn option control register 0 (UCnOPT0)
The UCnOPT0 register is an 8-bit register used to control serial transfer for the UARTCn.
(5) UARTCn option control register 1 (UCnOPT1)
The UCnOPT1 register is an 8-bit register used to control 9-bit length serial transfer for the UARTCn.
(6) UARTCn status register (UCnSTR)
The UCnSTRn register consists of flags indicating the error contents when a reception error occurs. Each one of
the reception error flags is set (to 1) upon occurrence of a reception error.
(7) UARTCn receive shift register
This is a shift register used to convert the serial data input to the RXDCn pin into parallel data. Upon reception of 1
byte of data and detection of the stop bit, the receive data is transferred to the UCnRX register.
This register cannot be manipulated directly.
(8) UARTCn receive data register (UCnRX)
The UCnRX register is an 8-bit register that holds receive data. When 7 characters are received, 0 is stored in the
most significant bit (when data is received with the LSB first).
In the reception enabled status, receive data is transferred from the UARTCn receive shift register to the UCnRX
register in synchronization with the completion of shift-in processing of 1 frame.
Transfer to the UCnRX register also causes the reception completion interrupt request signal (INTUCnR) to be
output.
(9) UARTCn transmit shift register
The transmit shift register is a shift register used to convert the parallel data transferred from the UCnTX register
into serial data.
When 1 byte of data is transferred from the UCnTX register, the shift register data is output from the TXDCn pin.
This register cannot be manipulated directly.
(10) UARTCn transmit data register (UCnTX)
The UCnTX register is an 8-bit transmit data buffer. Transmission starts when transmit data is written to the UCnTX
register. When data can be written to the UCnTX register (when data of one frame is transferred from the UCnTX
register to the UARTCn transmit shift register), the transmission enable interrupt request signal (INTUCnT) is
generated.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.3 Mode Switching Between UARTC and Other Serial Interfaces
17.3.1 Mode switching between UARTC0 and CSIF4
In the V850ES/JG3-H and V850ES/JH3-H, CSIF4 and UARTC0 share the same pins and therefore cannot be used
simultaneously. Set UARTC0 in advance, using the PMC3 and PFC3 registers, before use.
Caution
The transmit/receive operation of CSIF4 and UARTC0 is not guaranteed if these functions are
switched during transmission or reception. Be sure to disable the one that is not used.
Figure 17-2. CSIF4 and UARTC0 Mode Switch Settings
After reset: 00H
PMC3
PMC37
After reset: 00H
PFC3
PFC37
After reset: 00H
PFCE3
R/W
PMC36
R/W
PFC36
R/W
PFCE37 PFCE36
Address: FFFFF446H
PMC35
PMC34
PMC33
PMC32
PMC31
PMC30
PFC33
PFC32
PFC31
PFC30
PFCE31
PFCE30
Address: FFFFF466H
PFC35
PFC34
Address: FFFFF706H
PFCE35 PFCE34
PFCE33 PFCE32
PMC32
PFCE32
PFC32
0
×
×
Port I/O mode
1
0
0
ASCKC0 (UARTC0)
1
0
1
SCKF4 (CSIF4)
PMC31
PFCE31
PFC31
Operation mode
Operation mode
0
×
×
Port I/O mode
1
0
0
RXDC0 (UARTC)
1
0
1
SIF4 (CSIF4)
PMC30
PFCE30
PFC30
0
×
×
Port I/O mode
1
0
0
TXDC0 (UARTC)
1
0
1
SOF4 (CSIF4)
Remark
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.3.2 Mode switching between UARTC1 and I2C02
In the V850ES/JG3-H and V850ES/JH3-H, UARTC1 and I2C02 share the same pins and therefore cannot be used
simultaneously. Set UARTC1 in advance, using the PMC9, PFC9 and PFCE9 registers, before use.
Caution
The transmit/receive operation of UARTC1 and I2C02 is not guaranteed if these functions are
switched during transmission or reception. Be sure to disable the one that is not used.
Figure 17-3. UARTC1 and I2C02 Mode Switch Settings
After reset: 0000H
15
PMC9
9
8
PMC99
PMC98
PMC97
PMC91
PMC90
9
8
PMC96
R/W
13
PMC95
12
PMC94
11
10
PMC93
PMC92
Address: FFFFF472H, FFFFF473H
15
14
PFC915
PFC914
PFC913 PFC912
PFC911 PFC910
PFC99
PFC98
PFC97
PFC96
PFC95
PFC93
PFC91
PFC90
9
8
After reset: 0000H
15
PFCE9
14
Address: FFFFF452H, FFFFF453H
PMC915 PMC914 PMC913 PMC912 PMC911 PMC910
After reset: 0000H
PFC9
R/W
R/W
14
PFCE915 PFCE914
PFCE97 PFCE96
PMC91
PFCE91
13
12
PFC94
11
10
Address: FFFFF712H, FFFFF713H
13
12
0
0
PFCE95 PFCE94
11
10
PFCE911 PFCE910 PFCE99
PFCE98
PFCE93 PFCE92
PFCE90
PFC91
×
×
Port I/O mode
1
0
1
TXDC1 (UARTC1)
1
1
0
SDA02 (I2C02)
PMC90
PFCE90
PFC90
0
×
×
Port I/O mode
1
0
1
RXDC1 (UARTC1)
1
1
0
SCL02 (I2C02)
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Operation mode
0
Remark
PFC92
Operation mode
× = don’t care
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.3.3 Mode switching between UARTC2 and CSIF3
In the V850ES/JG3-H and V850ES/JH3-H, UARTC2 and CSIF3 share of the same pin and therefore cannot be used
simultaneously. Set UARTC2 in advance, using the PMC9, PFC9 and PFCE9 registers, before use.
Caution
The transmit/receive operation of UARTC2 and CSIF3 is not guaranteed if these functions are
switched during transmission or reception. Be sure to disable the one that is not used.
Figure 17-4. UARTC2 and CSIF3 Mode Switch Settings
After reset: 0000H
15
PMC9
8
PMC915 PMC914 PMC913 PMC912 PMC911 PMC910
PMC99
PMC98
PMC97
PMC91
PMC90
9
8
PMC96
R/W
13
PMC95
12
PMC94
11
10
PMC93
PMC92
Address: FFFFF472H, FFFFF473H
15
14
PFC915
PFC914
PFC913 PFC912
PFC911 PFC910
PFC99
PFC98
PFC97
PFC96
PFC95
PFC93
PFC91
PFC90
9
8
After reset: 0000H
15
PFCE9
14
Address: FFFFF452H, FFFFF453H
9
After reset: 0000H
PFC9
R/W
R/W
14
PFCE915 PFCE914
PFCE97 PFCE96
13
12
PFC94
11
10
Address: FFFFF712H, FFFFF713H
13
12
0
0
PFCE95 PFCE94
11
10
PFCE911 PFCE910 PFCE99
PFCE98
PFCE93 PFCE92
PFCE90
PMC91
PFCE91
PFC91
0
×
×
Port I/O mode
1
0
1
TXDC1 (UARTC1)
1
1
0
SDA02 (I2C02)
PMC90
PFCE90
PFC90
0
×
×
Port I/O mode
1
0
1
RXDC1 (UARTC1)
1
1
0
SCL02 (I2C02)
Remark
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PFCE91
Operation mode
Operation mode
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.3.4 Mode switching between UARTC3, I2C00 and CAN0
In the V850ES/JG3-H and V850ES/JH3-H, UARTC3, I2C00, and CAN0 (μPD70F3770, 70F3771 only) share the same
pins and therefore cannot be used simultaneously. Set UARTC3 in advance, using the PMC3, PFC3 and PFCE3 registers,
before use.
Caution
The transmit/receive operation of UARTC3, I2C00, and CAN0 (μPD70F3770, 70F3771 only) is not
guaranteed if these functions are switched during transmission or reception. Be sure to disable the
one that is not used.
Figure 17-5. UARTC3, I2C00, and CAN0 Mode Switch Settings
After reset: 00H
PMC3
PMC37
After reset: 00H
PFC3
PFC37
After reset: 00H
PFCE3
R/W
PMC36
R/W
PFC36
R/W
Address: FFFFF446H
PMC35
PMC34
PMC33
PMC32
PMC31
PMC30
PFC33
PFC32
PFC31
PFC30
PFCE31
PFCE30
Address: FFFFF466H
PFC35
PFC34
Address: FFFFF706H
PFCE37 PFCE36
PFCE35 PFCE34
PFCE33 PFCE32
PMC37
PFCE37
PFC37
0
×
×
Port I/O mode
1
0
0
RXDC3 (UARTC3)
1
0
1
SDA00 (I2C00)
1
1
0
CRXD0 (CAN0)
PMC36
PFCE36
PFC36
0
×
×
Port I/O mode
1
0
0
TXDC3 (UARTC3)
1
0
1
SCL00 (I2C00)
1
1
0
CTXD0 (CAN0)
Operation mode
Note
Operation mode
Note
Note μPD70F3770, 70F3771 only
Remark
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.3.5 Mode switching between UARTC4, CSIF0, and I2C01
In the V850ES/JG3-H and V850ES/JH3-H, UARTC4, CSIF0, and I2C01 share the same pin and therefore cannot be
used simultaneously. Set UARTC4 in advance, using the PMC4, PFC4, and PMCE4 registers, before use.
Caution
The transmit/receive operation of UARTC4, CSIF0, and I2C01 is not guaranteed if these functions are
switched during transmission or reception. Be sure to disable the one that is not used.
Figure 17-6. UARTC4, CSIF0 and I2C01 Mode Switch Settings
After reset: 00H
PMC4
0
After reset: 00H
0
PFC4
After reset: 00H
R/W
0
R/W
0
R/W
Address: FFFFF448H
0
0
0
PMC42
PMC41
PMC40
0
PFC42
PFC41
PFC40
0
0
PFCE41
PFCE40
Address: FFFFF468H
0
0
Address: FFFFF708H
0
0
0
PMC41
PFCE41
PFC41
0
×
×
Port I/O mode
1
0
0
SOF0 (CSIF0)
1
0
1
RXDC4 (UARTC4)
1
1
0
SCL01 (I2C01)
PMC40
PFCE40
PFC40
0
×
×
Port I/O mode
1
0
0
SIF0 (CSIF0)
1
0
1
TXDC4 (UARTC4)
1
1
0
SDA01 (I2C01)
PFCE4
Remark
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0
Operation mode
Operation mode
× = don’t care
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.4 Registers
(1) UARTCn control register 0 (UCnCTL0)
The UCnCTL0 register is an 8-bit register that controls the UARTCn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 10H.
(1/2)
After reset: 10H
R/W
Address: UC0CTL0 FFFFFA00H, UC1CTL0 FFFFFA10H,
UC2CTL0 FFFFFA20H, UC3CTL0 FFFFFA30H,
UC4CTL0 FFFFFA40H
UCnCTL0
UCnPWR UCnTXE UCnRXE UCnDIR
3
2
UCnPS1 UCnPS0
1
0
UCnCL
UCnSL
(n = 0 to 4)
UCnPWR
UCRTCn operation control
0
Disable UCRTCn operation (UCRTCn reset asynchronously)
1
Enable UCRTCn operation
The UARTCn operation is controlled by the UCnPWR bit. The TXDCn pin output
is fixed to high level by clearing the UCnPWR bit to 0 (fixed to low level if
UCnOPT0.UCnTDL bit = 1).
UCnTXE
Transmission operation enable
0
Disable transmission operation
1
Enable transmission operation
• To start transmission, set the UCnPWR bit to 1 and then set the UCnTXE bit to 1.
To stop transmission, clear the UCnTXE bit to 0 and then UCnPWR bit to 0.
• To initialize the transmission unit, clear the UCnTXE bit to 0, wait for two cycles of
the base clock, and then set the UCnTXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 17.7 (1) (a) Base clock).
UCnRXE
Reception operation enable
0
Disable reception operation
1
Enable reception operation
• To start reception, set the UCnPWR bit to 1 and then set the UCnRXE bit to 1.
To stop reception, clear the UCnRXE bit to 0 and then UCnPWR bit to 0.
• To initialize the reception unit, clear the UCnRXE bit to 0, wait for two periods of
the base clock, and then set the UCnRXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 17.7 (1) (a) Base clock).
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(2/2)
UCnDIR
Transfer direction selection
0
MSB-first transfer
1
LSB-first transfer
• This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit =
the UCnRXE bit = 0.
• When transmission and reception are performed in the LIN format, set the UCnDIR
bit to 1.
UCnPS1 UCnPS0 Parity selection during transmission Parity selection during reception
0
0
No parity output
Reception with no parity
0
1
0 parity output
Reception with 0 parity
1
0
Odd parity output
Odd parity check
1
1
Even parity output
Even parity check
• This register is rewritten only when the UCnPWR bit = 0 or the UCnTXE bit = the
UCnRXE bit = 0.
• If “Reception with 0 parity” is selected during reception, a parity check is not performed.
Therefore, the UCnSTR.UCnPE bit is not set.
• When transmission and reception are performed in the LIN format, clear the
UCnPS1 and UCnPS0 bits to 00.
UCnCL
Specification of data character length of 1 frame of transmit/receive data
0
7 bits
1
8 bits
• This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit =
the UCnRXE bit = 0.
• When transmission and reception are performed in the LIN format, set the UCnCL
bit to 1.
UCnSL
Specification of length of stop bit for transmit data
0
1 bit
1
2 bits
This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit =
the UCnRXE bit = 0.
Remark
For details of parity, see 17.6.9 Parity types and operations.
(2) UARTCn control register 1 (UCnCTL1)
For details, see 17.7 (2) UARTCn control register 1 (UCnCTL1).
(3) UARTCn control register 2 (UCnCTL2)
For details, see 17.7 (3) UARTCn control register 2 (UCnCTL2).
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
(4) UARTCn option control register 0 (UCnOPT0)
The UCnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTCn register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 14H.
(1/2)
After reset: 14H
R/W
Address: UC0OPT0 FFFFFA03H, UC1OPT0 FFFFFA13H,
UC2OPT0 FFFFFA23H, UC3OPT0 FFFFFA33H,
UC4OPT0 FFFFFA43H
UCnOPT0
6
5
4
3
2
1
0
UCnSRF UCnSRT UCnSTT UCnSLS2 UCnSLS1 UCnSLS0 UCnTDL UCnRDL
(n = 0 to 4)
UCnSRF
SBF reception flag
0
When the UCnCTL0.UCnPWR bit = UCnCTL0.UCnRXE bit = 0 are set, or
upon normal end of SBF reception.
1
During SBF reception
• SBF (Sync Brake Field) reception is judged during LIN communication.
• The UCnSRF bit is held at 1 when an SBF reception error occurs, and then SBF
reception is started again.
• The UCnSRF bit is a read-only bit.
UCnSRT
SBF reception trigger
−
0
1
SBF reception trigger
• This is the SBF reception trigger bit during LIN communication, and when read,
“0” is always read. For SBF reception, set the UCnSRT bit (to 1) to enable SBF
reception.
• Set the UCnSRT bit after setting the UCnPWR bit = UCnRXE bit = 1.
UCnSTT
SBF transmission trigger
−
0
1
SBF transmission trigger
• This is the SBF transmission trigger bit during LIN communication, and when read,
“0” is always read.
• Set the UCnSTT bit after setting the UCnPWR bit = UCnTXE bit = 1.
Caution
Do not set the UCnSRT and UCnSTT bits (to 1) during SBF reception (UCnSRF bit = 1).
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
(2/2)
UCnSLS2 UCnSLS1 UCnSLS0
SBF transmission length selection
1
0
1
13-bit output (reset value)
1
1
0
14-bit output
1
1
1
15-bit output
0
0
0
16-bit output
0
0
1
17-bit output
0
1
0
18-bit output
0
1
1
19-bit output
1
0
0
20-bit output
This register can be set when the UCnPWR bit = 0 or when the UCnTXE bit = 0.
UCnTDL
Transmit data level bit
0
Normal output of transfer data
1
Inverted output of transfer data
• The output level of the TXDCn pin can be inverted using the UCnTDL bit.
• This register can be set when the UCnPWR bit = 0 or when the UCnTXE bit = 0.
UCnRDL
Receive data level bit
0
Normal input of transfer data
1
Inverted input of transfer data
• The input level of the RXDCn pin can be inverted using the UCnRDL bit.
• This register can be set when the UCnPWR bit = 0 or the UCnRXE bit = 0.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
(5) UARTCn option control register 1 (UCnOPT1)
The UCnOPT1 register is an 8-bit register that controls the serial transfer operation of UARTCn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution
Set the UCnEBE bit while the operation of UARTC is disabled (UCnCTL0.UCnPWR = 0).
After reset: 00H
R/W
Address: UC0OPT1 FFFFFA0AH, UC1OPT1 FFFFFA1AH,
UC2OPT1 FFFFFA2AH, UC3OPT1 FFFFFA3AH,
UC4OPT1 FFFFFA4AH
UCnOPT1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
UCnEBE
(n = 0 to 4)
UCnEBE
Extension bit enable/disable
0
Extension-bit operation is prohibited. Transmission/reception is performed
in the data length set by the UCnCTL0.UCnCL bit.
1
Extension-bit operation enabled. Transmission/reception can be
performed in 9-bit character length.
• When setting the UCnEBE bit to 1, and transmitting in 9-bit data length, be sure to
set the following. If this setting is not performed, the setting of UCnEBE bit is invalid.
• UCnCTL0.UCnPS1, UCnPS0 = 00 (no parity)
• CnCTL0.UCnCL = 1 (8-bit character length)
• If transmitting or receiving in the LIN communication format, set the UCnEBE to 0.
The following shows the relationship between the register setting value and the data format.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Table 17-2. Relationship Between Register Setting and Data Format
Register Setting
Data Format
UCnCTL0
UCnOPT1
D0 to D6
D7
D8
D9
D10
Data
Stop
−
−
−
UCnCL
UCnPS1
UCnPS0
UCnSL
UCnEBE
0
0
0
0
0
0
Other than 00
Data
Parity
Stop
−
−
1
0
0
Data
Data
Stop
−
−
1
Other than 00
Data
Data
Parity
Stop
−
0
0
Data
Stop
Stop
−
−
0
1
0
0
Other than 00
Data
Parity
Stop
Stop
−
1
0
0
Data
Data
Stop
Stop
−
1
Other than 00
Data
Data
Parity
Stop
Stop
0
0
Data
Stop
−
−
−
0
Other than 00
Data
Parity
Stop
−
−
1
0
0
Data
Data
Data
Stop
−
1
Other than 00
Data
Data
Parity
Stop
−
0
0
Data
Stop
Stop
−
−
0
0
0
1
1
1
0
Other than 00
Data
Parity
Stop
Stop
−
1
0
0
Data
Data
Data
Stop
Stop
1
Other than 00
Data
Data
Parity
Stop
Stop
Remark
Data: Data bit
Stop: Stop bit
Parity: Parity bit
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
(6) UARTCn status register (UCnSTR)
The UCnSTR register is an 8-bit register that displays the UARTCn transfer status and reception error contents.
This register can be read or written in 8-bit or 1-bit units, but the UCnTSF bit is a read-only bit, while the UCnPE,
UCnFE, and UCnOVE bits can both be read and written. However, these bits can only be cleared by writing 0; they
cannot be set by writing 1 (even if 1 is written to them, the value is retained).
The initialization conditions are shown below.
Register/Bit
UCnSTR register
Initialization Conditions
• Reset
• UCnCTL0.UCnPWR = 0
UCnTSF bit
• UCnCTL0.UCnTXE = 0
UCnPE, UCnFE, UCnOVE bits
• 0 write
• UCnCTL0.UCnRXE = 0
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After reset: 00H
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
R/W
Address: UC0STR FFFFFA04H, UC1STR FFFFFA14H,
UC2STR FFFFFA24H, UC3STR FFFFFA34H,
UC4STR FFFFFA44H
UCnSTR
6
5
4
3
UCnTSF
0
0
0
0
UCnPE
UCnFE
UCnOVE
(n = 0 to 4)
UCnTSF
Transfer status flag
0
• When the UCnPWR bit = 0 or the UCnTXE bit = 0 has been set.
• When, following transfer completion, there was no next data transfer
from UCnTX register
1
Write to UCnTX register
The UCnTSF bit is always 1 when performing continuous transmission. When
initializing the transmission unit, check that the UCnTSF bit = 0 before performing
initialization. The transmit data is not guaranteed when initialization is performed
while the UCnTSF bit = 1.
UCnPE
Parity error flag
0
• When the UCnPWR bit = 0 or the UCnRXE bit = 0 has been set.
• When 0 has been written
1
When parity of data and parity bit do not match during reception.
• The operation of the UCnPE bit is controlled by the settings of the
UCnCTL0.UCnPS1 and UCnCTL0.UCnPS0 bits.
• The UCnPE bit can be read and written, but it can only be cleared by writing 0 to it, and
it cannot be set by writing 1 to it. When 1 is written to this bit, the value is retained.
UCnFE
Framing error flag
0
• When the UCnPWR bit = 0 or the UCnRXE bit = 0 has been set
• When 0 has been written
1
When no stop bit is detected during reception
• Only the first bit of the receive data stop bits is checked, regardless of the value
of the UCnCTL0.UCnSL bit.
• The UCnFE bit can be both read and written, but it can only be cleared by
writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit,
the value is retained.
UCnOVE
Overrun error flag
0
• When the UCnPWR bit = 0 or the UCnRXE bit = 0 has been set.
• When 0 has been written
1
When receive data has been set to the UCnRX register and the next
receive operation is completed before that receive data has been read
• When an overrun error occurs, the data is discarded without the next receive data
being written to the receive buffer.
• The UCnOVE bit can be both read and written, but it can only be cleared by writing
0 to it. When 1 is written to this bit, the value is retained.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
(7) UARTCn receive data register L (UCnRXL) and UARTCn receive data register (UCnRX)
The UCnRXL and UCnRX register are an 8- bit or 9-bit buffer register that stores parallel data converted by the
receive shift register.
The data stored in the receive shift register is transferred to the UCnRXL and UCnRX register upon completion of
reception of 1 byte of data.
During LSB-first reception when the data length has been specified as 7 bits, the receive data is transferred to bits
6 to 0 of the UCnRXL register and the MSB always becomes 0. During MSB-first reception, the receive data is
transferred to bits 7 to 1 of the UCnRXL register and the LSB always becomes 0.
When an overrun error (UCnOVE) occurs, the receive data at this time is not transferred to the UCnRXL and
UCnRX register and is discarded.
The access unit or reset value differs depending on the character length.
• Character length 7/8-bit (UCnOPT1.UCnEBE = 0)
This register is read-only, in 8-bit units.
Reset or UCnCTL0.UCnPWR bit = 0 sets this register to FFH.
• Character length 9-bit (UCnOPT1.UCnEBE = 0)
This register is read-only, in 16-bit units.
Reset or UCnCTL0.UCnPWR bit = 0 sets this register to 01FFH.
(a) Character length 7/8-bit (UCnOPT1.UCnEBE = 0)
After reset: FFH
R
Address: UC0RXL FFFFFA06H, UC1RXL FFFFFA16H,
UC2RXL FFFFFA26H, UC3RXL FFFFFA36H,
UC4RXL FFFFFA46H
6
7
5
4
3
2
1
0
UCnRXL
(n = 0 to 4)
(b) Character length 9-bit (UCnOPT1.UCnEBE = 1)
After reset: 01FFH
R
Address: UC0RX FFFFFA06H, UC1RX FFFFFA16H,
UC2RX FFFFFA26H, UC3RX FFFFFA36H,
UC4RX FFFFFA46H
15
14
13
12
11
10
9
0
0
0
0
0
0
0
UCnRX
(n = 0 to 4)
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
(8) UARTCn transmit data register L (UCnTXL), UARTCn transmit data register (UCnTX)
The UCnTXL and UCnTX register is an 8-bit or 9-bit register used to set transmit data.
During LSB-first transmission when the data length has been specified as 7 bits, the transmit data is transferred to
bits 6 to 0 of the UCnRX register. During MSB-first transmission, the receive data is transferred to bits 7 to 1 of the
UCnRX register.
The access unit or reset value differs depending on the character length.
• Character length 7/8-bit (UCnOPT1.UCnEBE = 0)
This register can be read or written in 8-bit units.
Reset sets this register to FFH.
• Character length 9-bit (UCnOPT1.UCnEBE = 0)
This register can be read or written in 16-bit units.
Reset sets this register to 01FFH.
Cautions 1. In the transmission operation enable status (UCnPWR = 1 and UCnTXE = 1), Writing to the
UCnTXL, UCnTX register, as operate as trigger of transmission star, if writing the value of as
soon as before and save value, before the INTUCnT interrupt is occurred, the same data is
transferred at twice.
2. Data writing for consecutive transmission, after be generated the INTUCnT interrupt.
If writing the next data before the INTUCnT interrupt is occurred, transmission start
processing and source of conflict writing the UCnTXL, UCnTX register, unexpected
operations may occur.
3. If perform to write the UCnTXL, UCnTXLin the disable transmission operation register, can not
be used as transmission start trigger. Consequently, even if transmission enable status after
perform to write the UCnTXL, UCnTX register in the disable transmission
operation
status, can not be started transmission.
(a) Character length 7/8-bit (UCnOPT1.UCnEBE = 0)
After reset: FFH
R/W
Address: UC0TXL FFFFFA08H, UC1TXL FFFFFA18H,
UC2TXL FFFFFA28H, UC3TXL FFFFFA38H,
UC4TXL FFFFFA48H
6
7
5
4
3
2
1
0
UCnTXL
(n = 0 to 4)
(b) Character length 9-bit (UCnOPT1.UCnEBE = 1)
After reset: 01FFH
R/W
Address: UC0TX FFFFFA08H, UC1TX FFFFFA18H,
UC2TX FFFFFA28H, UC3TX FFFFFA38H,
UC4TX FFFFFA48H
15
14
13
12
11
10
9
0
0
0
0
0
0
0
UCnTX
(n = 0 to 4)
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.5 Interrupt Request Signals
The following two interrupt request signals are generated from UARTCn.
• Reception completion interrupt request signal (INTUCnR)
• Transmission enable interrupt request signal (INTUCnT)
The default priority for these two interrupt request signals is reception completion interrupt request signal then
transmission enable interrupt request signal.
Table 17-3. Interrupts and Their Default Priorities
Interrupt
Priority
Reception complete
High
Transmission enable
Low
(1) Reception completion interrupt request signal (INTUCnR)
A reception completion interrupt request signal is output when data is shifted into the receive shift register and
transferred to the UCnRX register in the reception enabled status.
A reception completion interrupt request signal is also output when a reception error occurs. Therefore, when a
reception completion interrupt request signal is acknowledged and the data is read, read the UCnSTR register and
check that the reception result is not an error.
No reception completion interrupt request signal is generated in the reception disabled status.
(2) Transmission enable interrupt request signal (INTUCnT)
If transmit data is transferred from the UCnTX register to the UARTCn transmit shift register with transmission
enabled, the transmission enable interrupt request signal is generated.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.6 Operation
17.6.1 Data format
Full-duplex serial data reception and transmission is performed.
As shown in Figure 17-7, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and
stop bit(s).
Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and
specification of MSB/LSB-first transfer are performed using the UCnCTL0 register.
Moreover, control of UART output/inverted output for the TXDCn bit is performed using the UCnOPT0.UCnTDL bit.
• Start bit..................1 bit
• Character bits ........7 bits/8 bits
• Parity bit ................Even parity/odd parity/0 parity/no parity
• Stop bit ..................1 bit/2 bits
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Figure 17-7. UARTC Transmit/Receive Data Format
(a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H
1 data frame
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
bit
bit
(b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H
1 data frame
Start
bit
D7
D6
D5
D4
D3
D2
D1
D0
Parity Stop
bit
bit
(c) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H, TXDCn inversion
1 data frame
Start
bit
D7
D6
D5
D4
D3
D2
D1
D0
Parity Stop
bit
bit
(d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H
1 data frame
Start
bit
D0
D1
D2
D3
D4
D5
D6
Parity Stop
bit
bit
Stop
bit
(e) 8-bit data length, LSB first, no parity, 1 stop bit, transfer data: 87H
1 data frame
Start
bit
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D1
D2
D3
D4
D5
D6
D7
Stop
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.6.2 SBF transmission/reception format
The V850ES/JG3-H and V850ES/JH3-H have an SBF (Sync Break Field) transmission/reception control function to
enable use of the LIN function.
Remark
LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol
intended to aid the cost reduction of an automotive network.
LIN communication is single-master communication, and up to 15 slaves can be connected to one master.
The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN
master via the LIN network.
Normally, the LIN master is connected to a network such as CAN (Controller Area Network).
In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that
complies with ISO9141.
In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and
corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is
±15% or less.
Figures 17-8 and 17-9 outline the transmission and reception manipulations of LIN.
Figure 17-8. LIN Transmission Manipulation Outline
Sync
break
field
Sync
field
Note 2
13 bits
55H
transmission
Wake-up
signal
frame
DATA
field
DATA
field
Check
SUM
field
Data
transmission
Data
transmission
Data
transmission
Identifier
field
LIN
bus
Note 3
8 bits
Note 1
Data
transmission
TXDCn (output)
SBF transmissionNote 4
INTUCnT
interrupt
Notes 1. The interval between each field is controlled by software.
2. SBF output is performed by hardware.
The output width is the bit length set by the
UCnOPT0.UCnSLS2 to UCnOPT0.UCnSLS0 bits.
required,
such
adjustments
can
be
If even finer output width adjustments are
performed
using
the
UCnCTL2.UCnBRS7
to
UCnCTL2.UCnBRS0 bits.
3. 80H transfer in the 8-bit mode is substituted for the wakeup signal frame.
4. A transmission enable interrupt request signal (INTUCnT) is output at the start of each transmission.
The INTUCnT signal is also output at the start of each SBF transmission.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Figure 17-9. LIN Reception Manipulation Outline
Wake-up
signal
frame
Sync
break
field
Sync
field
Identifier
field
DATA
field
Note 2
13 bits
SF reception
ID reception
Data
transmission
DATA
field
Check
SUM
field
LIN
bus
RXDCn (input)
SBF
reception
Enable
Disable
Data
Note 5
transmission Data transmission
Note 3
Reception interrupt (INTUCnR)
Note 1
Edge detection
Note 4
Capture timer
Disable
Enable
Notes 1. The wakeup signal is sent by the pin edge detector, UARTCn is enabled, and the SBF reception
mode is set.
2. The receive operation is performed until detection of the stop bit. Upon detection of SBF reception
of 11 or more bits, normal SBF reception end is judged, and an interrupt signal is output. Upon
detection of SBF reception of less than 11 bits, an SBF reception error is judged, no interrupt signal
is output, and the mode returns to the SBF reception mode.
3. If SBF reception ends normally, an interrupt request signal is output. The timer is enabled by an SBF
reception
completion
interrupt.
Moreover,
error
detection
for
the
UCnSTR.UCnOVE,
UCnSTR.UCnPE, and UCnSTR.UCnFE bits is suppressed and UART communication error detection
processing and UARTCn receive shift register and data transfer of the UCnRX register are not
performed. The UARTCn receive shift register holds the initial value, FFH.
4. The RXDCn pin is connected to TI (capture input) of the timer, the transfer rate is calculated, and the
baud rate error is calculated. The value of the UCnCTL2 register obtained by correcting the baud
rate error after dropping UARTC enable is set again, causing the status to become the reception
status.
5. Check-sum field distinctions are made by software. UARTCn is initialized following CSF reception,
and the processing for setting the SBF reception mode again is performed by software.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.6.3 SBF transmission
When the UCnCTL0.UCnPWR bit = UCnCTL0.UCnTXE bit = 1, the transmission enabled status is entered, and SBF
transmission is started by setting (to 1) the SBF transmission trigger (UCnOPT0.UCnSTT bit).
Thereafter, a low level the width of bits 13 to 20 specified by the UCnOPT0.UCnSLS2 to UCnOPT0.UCnSLS0 bits is
output. A transmission enable interrupt request signal (INTUCnT) is generated upon SBF transmission start. Following the
end of SBF transmission, the UCnSTT bit is automatically cleared. Thereafter, the UART transmission mode is restored.
Transmission is suspended until the data to be transmitted next is written to the UCnTX register, or until the SBF
transmission trigger (UCnSTT bit) is set.
Figure 17-10. SBF Transmission
TXDCn
1
2
3
4
5
6
7
8
9
10
11
12
13
Stop
bit
INTUCnT
interrupt
Setting of UCnSTT bit
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.6.4 SBF reception
The reception wait status is entered by setting the UCnCTL0.UCnPWR bit to 1 and then setting the UCnCTL0.UCnRXE
bit to 1.
The SBF reception wait status is set by setting the SBF reception trigger (UCnOPT0.UCnSRT bit) to 1.
In the SBF reception wait status, similarly to the UART reception wait status, the RXDCn pin is monitored and start bit
detection is performed.
Following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate.
When a stop bit is received, if the SBF width is 11 or more bits, normal processing is judged and a reception completion
interrupt request signal (INTUCnR) is output. The UCnOPT0.UCnSRF bit is automatically cleared and SBF reception ends.
Error detection for the UCnSTR.UCnOVE, UCnSTR.UCnPE, and UCnSTR.UCnFE bits is suppressed and UART
communication error detection processing is not performed. Moreover, data transfer of the UARTCn reception shift
register and UCnRX register is not performed and FFH, the initial value, is held. If the SBF width is 10 or fewer bits,
reception is terminated as error processing without outputting an interrupt, and the SBF reception mode is returned to.
The UCnSRF bit is not cleared at this time.
Cautions 1. If SBF is transmitted during a data reception, a framing error occurs.
2. Do not set the SBF reception trigger bit (UCnSRT) and SBF transmission trigger bit (UCnSTT) to 1
during an SBF reception (UCnSRF = 1).
Figure 17-11. SBF Reception
(a) Normal SBF reception (detection of stop bit in more than 10.5 bits)
RXDCn
1
2
3
4
5
6
7
8
9
10
11
11.5
UCnSRF
INTUCnR
interrupt
(b) SBF reception error (detection of stop bit in 10.5 or fewer bits)
RXDCn
1
2
3
4
5
6
7
8
9
10
10.5
UCnSRF
INTUCnR
interrupt
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.6.5 UART transmission
A high level is output to the TXDCn pin by setting the UCnCTL0.UCnPWR bit to 1.
Next, the transmission enabled status is set by setting the UCnCTL0.UCnTXE bit to 1, and transmission is started by
writing transmit data to the UCnTX register. The start bit, parity bit, and stop bit are automatically added.
Since the CTS (transmit enable signal) input pin is not provided in UARTCn, use a port to check that reception is
enabled at the transmit destination.
The data in the UCnTX register is transferred to the UARTCn transmit shift register upon the start of the transmit
operation.
A transmission enable interrupt request signal (INTUCnT) is generated upon completion of transmission of the data of
the UCnTX register to the UARTCn transmit shift register, and thereafter the contents of the UARTCn transmit shift register
are output to the TXDCn pin.
Write of the next transmit data to the UCnTX register is enabled after the INTUCnT signal is generated.
Figure 17-12. UART Transmission
TXDCn
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
bit
bit
INTUCnT
Remark
LSB first
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.6.6 Continuous transmission procedure
UARTCn can write the next transmit data to the UCnTX register when the UARTCn transmit shift register starts the shift
operation. The transmit timing of the UARTCn transmit shift register can be judged from the transmission enable interrupt
request signal (INTUCnT). An efficient communication rate is realized by writing the data to be transmitted next to the
UCnTX register during transfer.
Caution
When initializing transmissions during the execution of continuous transmissions, make sure that
the UCnSTR.UCnTSF bit is 0, then perform the initialization. Transmit data that is initialized when the
UCnTSF bit is 1 cannot be guaranteed.
Figure 17-13. Continuous Transmission Processing Flow
Start
Register settings
UCnTX write
Occurrence of transmission
interrupt?
No
Yes
Required number of
writes performed?
No
Yes
End
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Figure 17-14. Continuous Transmission Operation Timing
(a) Transmission start
Start
TXDCn
UCnTX
Data (1)
Parity
Stop
Data (1)
Transmission
shift register
Start
Data (2)
Parity
Data (2)
Stop
Start
Data (3)
Data (2)
Data (1)
INTUCnT
UCnTSF
(b) Transmission end
TXDCn
Parity
UCnTX
Transmission
shift register
Stop
Start
Data (n – 1)
Parity
Data (n – 1)
Stop
Start
Data (n)
Parity Stop
Data (n)
Data (n – 1)
Data (n)
FF
INTUCnT
UCnTSF
UCnPWR or UCnTXE bit
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.6.7 UART reception
The reception wait status is set by setting the UCnCTL0.UCnPWR bit to 1 and then setting the UCnCTL0.UCnRXE bit
to 1. In the reception wait status, the RXDCn pin is monitored and start bit detection is performed.
Start bit detection is performed using a two-step detection routine.
First the rising edge of the RXDCn pin is detected and sampling is started at the falling edge. The start bit is
recognized if the RXDCn pin is low level at the start bit sampling point. After a start bit has been recognized, the receive
operation starts, and serial data is saved to the UARTCn receive shift register according to the set baud rate.
When the reception completion interrupt request signal (INTUCnR) is output upon reception of the stop bit, the data of
the UARTCn receive shift register is written to the UCnRX register. However, if an overrun error (UCnSTR.UCnOVE bit)
occurs, the receive data at this time is not written to the UCnRX register and is discarded.
Even if a parity error (UCnSTR.UCnPE bit) or a framing error (UCnSTR.UCnFE bit) occurs during reception, reception
continues until the reception position of the first stop bit, and INTUCnR is output following reception completion.
Figure 17-15. UART Reception
RXDCn
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
bit
bit
INTUCnR
UCnRX
Cautions 1. Be sure to read the UCnRX register even when a reception error occurs. If the UCnRX register is
not read, an overrun error occurs during reception of the next data, and reception errors continue
occurring indefinitely.
2. The operation during reception is performed assuming that there is only one stop bit. A second
stop bit is ignored.
3. When reception is completed, read the UCnRX register after the reception completion interrupt
request signal (INTUCnR) has been generated, and clear the UCnPWR or UCnRXE bit to 0. If the
UCnPWR or UCnRXE bit is cleared to 0 before the INTUCnR signal is generated, the read value of
the UCnRX register cannot be guaranteed.
4. If receive completion processing (INTUCnR signal generation) of UARTCn and the UCnPWR bit =
0 or UCnRXE bit = 0 conflict, the INTUCnR signal may be generated in spite of these being no data
stored in the UCnRX register.
To complete reception without waiting for the INTUCnR signal to be generated, be sure to set (1)
the interrupt mask flag (UCnRMK) of the interrupt control register (UCnRIC), clear (0) the UCnPWR
bit or UCnRXE bit, and then clear the interrupt request flag (UCnRIF) of the UCnRIC register.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.6.8 Reception errors
Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception
result error flags are set in the UCnSTR register and a reception completion interrupt request signal (INTUCnR) is output
when an error occurs.
It is possible to ascertain which error occurred during reception by reading the contents of the UCnSTR register.
Clear the reception error flag by writing 0 to it after reading it.
Figure 17-16. Receive Data Read Flow
START
INTUCnR signal
generated?
No
Yes
Read UCnRX register
Read UCnSTR register
No
Error occurs?
Yes
Error processing
END
Caution
When an INTUCnR signal is generated, the UCnSTR register must be read to check for errors.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
• Reception error causes
Error Flag
Reception Error
Cause
UCnPE
Parity error
Received parity bit does not match the setting
UCnFE
Framing error
Stop bit not detected
UCnOVE
Overrun error
Reception of next data completed before data was read from receive buffer
When reception errors occur, perform the following procedures depending upon the kind of error.
• Parity error
If false data is received due to problems such as noise in the reception line, discard the received data and retransmit.
• Framing error
A baud rate error may have occurred between the reception side and transmission side or the start bit may have
been erroneously detected. Since this is a fatal error for the communication format, check the operation stop in the
transmission side, perform initialization processing each other, and then start the communication again.
• Overrun error
Since the next reception is completed before reading receive data, 1 frame of data is discarded. If this data was
needed, do a retransmission.
Caution
If a receive error interrupt occurs during continuous reception, read the contents of the UCnSTR
register must be read before the next reception is completed, then perform error processing.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.6.9 Parity types and operations
Caution
When using the LIN function, fix the UCnCTL0.UCnPS1 and UCnCTL0.UCnPS0 bits to 00.
The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the
transmission side and the reception side.
In the case of even parity and odd parity, it is possible to detect odd-count bit errors. In the case of 0 parity and no
parity, errors cannot be detected.
(a) Even parity
(i) During transmission
The number of bits whose value is “1” among the transmit data, including the parity bit, is controlled so as to be
an even number. The parity bit values are as follows.
• Odd number of bits whose value is “1” among transmit data: 1
• Even number of bits whose value is “1” among transmit data: 0
(ii) During reception
The number of bits whose value is “1” among the reception data, including the parity bit, is counted, and if it is
an odd number, a parity error is output.
(b) Odd parity
(i) During transmission
Opposite to even parity, the number of bits whose value is “1” among the transmit data, including the parity bit,
is controlled so that it is an odd number. The parity bit values are as follows.
• Odd number of bits whose value is “1” among transmit data: 0
• Even number of bits whose value is “1” among transmit data: 1
(ii) During reception
The number of bits whose value is “1” among the receive data, including the parity bit, is counted, and if it is an
even number, a parity error is output.
(c) 0 parity
During transmission, the parity bit is always made 0, regardless of the transmit data.
During reception, parity bit check is not performed. Therefore, no parity error occurs, regardless of whether the
parity bit is 0 or 1.
(d) No parity
No parity bit is added to the transmit data.
Reception is performed assuming that there is no parity bit. No parity error occurs since there is no parity bit.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.6.10 Receive data noise filter
This filter samples the RXDCn pin using the base clock of the prescaler output.
When the same sampling value is read twice, the match detector output changes and the RXDCn signal is sampled as
the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit
(see Figure 17-18). See 17.7 (1) (a) Base clock regarding the base clock.
Moreover, since the circuit is as shown in Figure 17-17, the processing that goes on within the receive operation is
delayed by 3 clocks in relation to the external signal status.
Figure 17-17. Noise Filter Circuit
Base clock (fUCLK)
RXDCn
In
Q
Internal signal A
In
Q
Internal signal B
In
Match
detector
Q
Internal signal C
LD_EN
Figure 17-18. Timing of RXDCn Signal Judged as Noise
Base clock
RXDCn (input)
Internal signal A
Internal signal B
Match
Mismatch
(judged as noise)
Match
Mismatch
(judged as noise)
Internal signal C
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.7 Dedicated Baud Rate Generator
The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and
generates a serial clock during transmission and reception with UARTCn. Regarding the serial clock, a dedicated baud
rate generator output can be selected for each channel.
There is an 8-bit counter for transmission and another one for reception.
(1) Baud rate generator configuration
Figure 17-19. Configuration of Baud Rate Generator
UCnPWR
fXX/2
fXX/4
UCnPWR, UCnTXEn bits
(or UCnRXE bit)
fXX/8
fXX/16
fXX/32
fXX/64
fXX/128
fXX/256
fXX/512
fXX/1024
fXX/2048
ASCKC0Note
Selector
8-bit counter
fUCLK
Match detector
UCnCTL1:
UCnCKS3 to UCnCKS0
1/2
Baud rate
UCnCTL2:
UCnBRS7 to UCnBRS0
Note Only UARTC0 is valid; setting UARTC1 and UARTC4 is prohibited.
Remarks 1. n = 0 to 4
2. fXX:
Main clock frequency
fUCLK: Base clock frequency
(a) Base clock
When the UCnCTL0.UCnPWR bit is 1, the clock selected by the UCnCTL1.UCnCKS3 to UCnCTL1.UCnCKS0
bits is supplied to the 8-bit counter. This clock is called the base clock (fUCLK).
(b) Serial clock generation
A serial clock can be generated by setting the UCnCTL1 register and the UCnCTL2 register (n = 0 to 4).
The base clock is selected by UCnCTL1.UCnCKS3 to UCnCTL1.UCnCKS0 bits.
The frequency division value for the 8-bit counter can be set using the UCnCTL2.UCnBRS7 to
UCnCTL2.UCnBRS0 bits.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
(2) UARTCn control register 1 (UCnCTL1)
The UCnCTL1 register is an 8-bit register that selects the UARTCn base clock.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution
Clear the UCnCTL0.UCnPWR bit to 0 before rewriting the UCnCTL1 register.
After reset: 00H
R/W
Address: UC0CTL1 FFFFFA01H, UC1CTL1 FFFFFA11H,
UC2CTL1 FFFFFA21H, UC3CTL1 FFFFFA31H,
UC4CTL1 FFFFFA41H
UCnCTL1
7
6
5
4
0
0
0
0
3
2
1
0
UCnCKS3UCnCKS2 UCnCKS1 UCnCKS0
(n = 0 to 4)
UCnCKS3 UCnCKS2 UCnCKS1UCnCKS0
Base clock (fUCLK) selection
0
0
0
0
fXX/2
0
0
0
1
fXX/4
0
0
1
0
fXX/8
0
0
1
1
fXX/16
0
1
0
0
fXX/32
0
1
0
1
fXX/64
0
1
1
0
fXX/128
0
1
1
1
fXX/256
1
0
0
0
fXX/512
1
0
0
1
fXX/1,024
1
0
1
0
fXX/2,048
1
0
1
1
External clockNote (ASCKC0 pin)
Other than above
Setting prohibited
Note Only UARTC0 is valid; setting UARTC1 to UARTC4 is prohibited.
Remark
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
(3) UARTCn control register 2 (UCnCTL2)
The UCnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTCn.
This register can be read or written in 8-bit units.
Reset sets this register to FFH.
Caution
Clear the UCnCTL0.UCnPWR bit to 0 or clear the UCnTXE and UCnRXE bits to 00 before rewriting
the UCnCTL2 register.
After reset FFH
R/W
Address: UC0CTL2 FFFFFA02H, UC1CTL2 FFFFFA12H,
UC2CTL2 FFFFFA22H, UC3CTL2 FFFFFA32H,
UC4CTL2 FFFFFA42H
6
7
UCnCTL2
5
4
3
2
1
0
UCnBRS7 UCnBRS6 UCnBRS5UCnBRS4 UCnBRS3UCnBRS2 UCnBRS1 UCnBRS0
(n = 0 to 4)
UCn
BRS7
UCn
BRS6
UCn
BRS5
UCn
BRS4
UCn
BRS3
UCn
BRS2
UCn
BRS1
UCn Default
BRS0
(k)
Serial
clock
0
0
0
0
0
0
×
×
×
0
0
0
0
0
1
0
0
4
fUCLK/4
0
0
0
0
0
1
0
1
5
fUCLK/5
0
0
0
0
0
1
1
0
6
fUCLK/6
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
0
0
252
fUCLK/252
1
1
1
1
1
1
0
1
253
fUCLK/253
1
1
1
1
1
1
1
0
254
fUCLK/254
1
1
1
1
1
1
1
1
255
fUCLK/255
Setting
prohibited
Remark fUCLK: Clock frequency selected by the UCnCTL1.UCnCKS3 to
UCnCTL1.UCnCKS0 bits
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
(4) Baud rate
The baud rate is obtained by the following equation.
Baud rate =
fUCLK
[bps]
2×k
When using the internal clock, the equation will be as follows (when using the ASCKC0 pin as clock at
UARTC0, calculate using the above equation).
Baud rate =
fXX
m+1
2
Remark
×k
[bps]
fUCLK = Frequency of base clock selected by the UCnCTL1.UCnCKS3 to UCnCTL1.UCnCKS0 bits
fXX: Main clock frequency
m = Value set using the UCnCTL1.UCnCKS3 to UCnCTL1.UCnCKS0 bits (m = 0 to 10)
k = Value set using the UCnCTL2.UCnBRS7 to UCnCTL2.UCnBRS0 bits (k = 4 to 255)
The baud rate error is obtained by the following equation.
Error (%) =
=
Actual baud rate (baud rate with error)
Target baud rate (correct baud rate)
fUCLK
2 × k × Target baud rate
− 1 × 100 [%]
− 1 × 100 [%]
When using the internal clock, the equation will be as follows (when using the ASCKC0 pin input as the
clock for UARTC0, calculate the baud rate error using the above equation).
fXX
Error (%) =
m+1
2
× k × Target baud rate
− 1 × 100 [%]
Cautions 1. The baud rate error during transmission must be within the error tolerance on the
receiving side.
2. The baud rate error during reception must satisfy the range indicated in (5) Allowable
baud rate range during reception.
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
To set the baud rate, perform the following calculation for setting the UCnCTL1 and UCnCTL2 registers (when
using internal clock).
Set k to fxx/2/(2 × target baud rate) and m to 0.
If k is 256 or greater (k ≥ 256), reduce k to half (k/2) and increment m by 1 (m + 1).
Repeat Step until k becomes less than 256 (k < 256).
Round off the first decimal point of k to the nearest whole number.
If k becomes 256 after round-off, perform Step again to set k to 128.
Set the value of m to UCnCTL1 register and the value of k to the UCnCTL2 register.
Example: When fXX = 48 MHz and target baud rate = 153,600 bps
k = 480,000,000/2/(2 × 153,600) = 78.125…, m = 0
, k = 78.125… < 256, m = 0
Set value of UCnCTL2 register: k = 78 = 4EH, set value of UCnCTL1 register: m = 0
Actual baud rate = 48,000,000/2/(2 × 78)
= 153,846 [bps]
Baud rate error
= {48,000,000/2/(2 × 78 × 153,600) − 1} × 100
= 0.160 [%]
The representative examples of baud rate settings are shown below.
Table 17-4. Baud Rate Generator Setting Data
Baud Rate
(bps)
fXX = 48 MHz
UCnCTL1 UCnCTL2
fXX = 32 MHz
ERR (%)
UCnCTL1 UCnCTL2
fXX = 24 MHz
ERR (%)
UCnCTL1
UCnCTL2
ERR (%)
300
08H
9CH
0.16
07H
D0H
0.16
07H
9CH
−2.3
600
07H
9CH
0.16
06H
D0H
0.16
06H
9CH
0.16
1,200
06H
9CH
0.16
05H
D0H
0.16
05H
9CH
0.16
2,400
05H
9CH
0.16
04H
D0H
0.16
04H
9CH
0.16
4,800
04H
9CH
0.16
03H
D0H
0.16
03H
9CH
0.16
9,600
03H
9CH
0.16
02H
D0H
0.16
02H
9CH
0.16
19,200
02H
9CH
0.16
01H
D0H
0.16
01H
9CH
0.16
31,250
01H
C0H
0.00
01H
80H
0.00
00H
C0H
0.00
38,400
01H
9CH
0.16
00H
D0H
0.16
00H
9CH
0.16
76,800
00H
9CH
0.16
00H
68H
0.16
00H
4EH
0.16
153,600
00H
4EH
0.16
00H
34H
0.16
00H
27H
0.16
312,500
00H
26H
1.05
00H
1AH
−1.54
00H
13H
1.05
625,000
00H
13H
1.05
00H
0DH
−1.54
00H
0AH
−4.00
1,000,000
00H
0CH
0.00
00H
08H
0.00
00H
06H
0.00
1,250,000
00H
0AH
00H
05H
−4.00
2,000,000
00H
06H
2,500,000
00H
05H
3,000,000
00H
04H
Remark
fXX:
−4.00 Setting prohibited
0.00
00H
04H
0.00 Setting prohibited
−4.00 Setting prohibited
0.00
Main clock frequency
ERR: Baud rate error (%)
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
(5) Allowable baud rate range during reception
The baud rate error range at the destination that is allowable during reception is shown below.
Caution
The baud rate error during reception must be set within the allowable error range using the
following equation.
Figure 17-20. Allowable Baud Rate Range During Reception
Latch timing
UARTCn
transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FL
1 data frame (11 × FL)
Minimum
allowable
transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmin
Maximum
allowable
transfer rate
Start bit
Bit 0
Bit 1
Parity bit
Bit 7
Stop bit
FLmax
Remark
n = 0 to 4
As shown in Figure 17-20, the receive data latch timing is determined by the counter set using the UCnCTL2
register following start bit detection. The transmit data can be normally received if up to the last data (stop bit) can
be received in time for this latch timing.
When this is applied to 11-bit reception, the following is the theoretical result.
FL = (Brate)−1
Brate: UARTCn baud rate (n = 0 to 4)
k:
Set value of UCnCTL2.UCnBRS7 to UCnCTL2.UCnBRS0 bits (n = 0 to 4)
FL:
1-bit data length
Latch timing margin: 2 clocks
Minimum allowable transfer rate: FLmin = 11 × FL −
k−2
2k
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× FL =
21k + 2
FL
2k
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Therefore, the maximum baud rate that can be received by the destination is as follows.
BRmax = (FLmin/11)−1 =
22k
Brate
21k + 2
Similarly, obtaining the following maximum allowable transfer rate yields the following.
10
k+2
× FLmax = 11 × FL −
2×k
11
FLmax =
21k − 2
× FL =
21k − 2
2×k
FL
FL × 11
20 k
Therefore, the minimum baud rate that can be received by the destination is as follows.
BRmin = (FLmax/11)−1 =
20k
21k − 2
Brate
Obtaining the allowable baud rate error for UARTCn and the destination from the above-described equations for
obtaining the minimum and maximum baud rate values yields the following.
Table 17-5. Maximum/Minimum Allowable Baud Rate Error
Division Ratio (k)
Maximum Allowable Baud Rate Error
Minimum Allowable Baud Rate Error
4
+2.32%
−2.43%
8
+3.52%
−3.61%
20
+4.26%
−4.30%
50
+4.56%
−4.58%
100
+4.66%
−4.67%
255
+4.72%
−4.72%
Remarks 1. The reception accuracy depends on the bit count in 1 frame, the input clock
frequency, and the division ratio (k). The higher the input clock frequency and
the larger the division ratio (k), the higher the accuracy.
2. k: Set value of UCnCTL2.UCnBRS7 to UCnCTL2.UCnBRS0 bits (n = 0 to 4)
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
(6) Transfer rate during continuous transmission
During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks
longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no
influence on the transfer result.
Figure 17-21. Transfer Rate During Continuous Transfer
Start bit of 2nd byte
1 data frame
Start bit
FL
Bit 0
Bit 1
Bit 7
FL
FL
FL
Parity bit
FL
Stop bit
FLstp
Start bit
FL
Bit 0
FL
The following equation can be obtained assuming 1 bit data length: FL; stop bit length: FLstp; and base clock
frequency: fUCLK.
FLstp = FL + 2/fUCLK
Therefore, the transfer rate during continuous transmission is as follows.
Transfer rate = 11 × FL + (2/fUCLK)
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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
17.8 Cautions
(1) When the clock supply to UARTCn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation stops
with each register retaining the value it had immediately before the clock supply was stopped. The TXDCn pin
output also holds and outputs the value it had immediately before the clock supply was stopped. However, the
operation is not guaranteed after the clock supply is resumed. Therefore, after the clock supply is resumed, the
circuits should be initialized by setting the UCnCTL0.UCnPWR, UCnCTL0.UCnRXEn, and UCnCTL0.UCnTXEn
bits to 000.
(2) The RXDC1 and KR7 pins must not be used at the same time. To use the RXDC1 pin, do not use the KR7 pin. To
use the KR7 pin, do not use the RXDC1 pin (it is recommended to set the PFC91 bit to 1 and clear PFCE91 bit to
0).
(3) Start up the UARTCn in the following sequence.
Set the UCnCTL0.UCnPWR bit to 1.
Set the ports.
Set the UCnCTL0.UCnTXE bit to 1, UCnCTL0.UCnRXE bit to 1.
(4) Stop the UARTCn in the following sequence.
Set the UCnCTL0.UCnTXE bit to 0, UCnCTL0.UCnRXE bit to 0.
Set the ports and set the UCnCTL0.UCnPWR bit to 0 (it is not a problem if port setting is not changed).
(5) In transmit mode (UCnCTL0.UCnPWR bit = 1 and UCnCTL0.UCnTXE bit = 1), do not overwrite the same value to
the UCnTX register by software because transmission starts by writing to this register. To transmit the same value
continuously, overwrite the same value.
(6) In continuous transmission, the communication rate from the stop bit to the next start bit is extended 2 base clocks
more than usual. However, the reception side initializes the timing by detecting the start bit, so the reception result
is not affected.
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.1 Mode Switching of CSIF and Other Serial Interfaces
18.1.1 CSIF4 and UARTC0 mode switching
In the V850ES/JG3-H and V850ES/JH3-H, CSIF4 and UARTC0 share the same pins and therefore cannot be used
simultaneously. To use CSIF4, the use of CSIF4 must be set in advance, using the PMC3, PFC3 and PFCE3 registers.
Caution
The transmit/receive operation of CSIF4 and UARTC0 is not guaranteed if these functions are
switched during transmission or reception. Be sure to disable the one that is not used.
Figure 18-1. CSIF4 and UARTC0 Mode Switch Settings
After reset: 00H
PMC3
PMC37
After reset: 00H
PFC3
Address: FFFFF446H
PMC36
R/W
PMC35
PMC34
PMC33
PMC32
PMC31
PMC30
Address: FFFFF466H
7
6
5
4
3
2
1
0
PFC37
PFC36
PFC35
PFC34
PFC33
PFC32
PFC31
PFC30
PFCE31
PFCE30
After reset: 00H
PFCE3
R/W
R/W
PFCE37 PFCE36
Address: FFFFF706H
PFCE35 PFCE34
PFCE33 PFCE32
PMC32
PFCE32
PFC32
0
×
×
Port I/O mode
1
0
0
ASCKC0
1
0
1
SCKF4
PMC3n
PFC3n
0
×
Port I/O mode
1
0
UARTC0 mode
1
1
CSIF4 mode
Operation mode
Operation mode
Remarks 1. n = 0, 1
2. × = don’t care
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
2
18.1.2 CSIF0, UARTC4, and I C01 mode switching
In the V850ES/JG3-H and V850ES/JH3-H, CSIF0, UARTC4, and I2C01 share the same pins and therefore cannot be
used simultaneously. Switching among CSIF0, UARTC4, and I2C01 must be set in advance, using the PMC4, PFC4, and
PFCE4 registers.
Caution
The transmit/receive operation of CSIF0, UARTC4, and I2C01 is not guaranteed if these functions are
switched during transmission or reception. Be sure to disable the one that is not used.
Figure 18-2. CSIF0, UARTC4, and I2C01 Mode Switch Settings
After reset: 00H
PMC4
R/W
0
After reset: 00H
PFC4
0
R/W
0
0
0
PMC42
PMC41
PMC40
Address: FFFFF468H
7
6
5
4
3
2
1
0
0
0
0
0
0
PFC42
PFC41
PFC40
0
0
PFCE41
PFCE40
After reset: 00H
PFCE4
Address: FFFFF448H
R/W
Address: FFFFF708H
0
0
0
PMC4n
PFCE4n
PFC4n
0
Operation mode
0
×
×
Port I/O mode
1
0
0
CSIF0 mode
1
0
1
UARTC4 mode
1
1
0
I2C01 mode
Remarks 1. n = 0, 1
2. × = don’t care
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.1.3 CSIF3 and UARTC2 mode switching
In the V850ES/JG3-H and V850ES/JH3-H, CSIF3 and UARTC2 share the same pins and therefore cannot be used
simultaneously. Switching between CSIF3 and UARTC2 must be set in advance, using the PMC9, PFC9 and PFCE9
registers.
Caution
The transmit/receive operation of CSIF3 and UARTC2 is not guaranteed if these functions are
switched during transmission or reception. Be sure to disable the one that is not used.
Figure 18-3. CSIF3 and UARTC2 Mode Switch Settings
After reset: 0000H
15
PMC9
9
8
PMC99
PMC98
PMC97
PMC91
PMC90
14
9
8
PMC96
R/W
13
PMC95
12
PMC94
11
10
PMC93
PMC92
Address: FFFFF472H, FFFFF473H
15
14
PFC915
PFC914
PFC913 PFC912
PFC911 PFC910
PFC99
PFC98
PFC97
PFC96
PFC95
PFC93
PFC91
PFC90
9
8
After reset: 0000H
15
PFCE9
Address: FFFFF452H, FFFFF453H
PMC915 PMC914 PMC913 PMC912 PMC911 PMC910
After reset: 0000H
PFC9
R/W
R/W
13
PFC94
11
10
PFC92
Address: FFFFF712H, FFFFF713H
14
PFCE915 PFCE914
PFCE97 PFCE96
12
13
12
0
0
PFCE95 PFCE94
11
10
PFCE911 PFCE910 PFCE99
PFCE98
PFCE93 PFCE92
PFCE90
PFCE91
Operation mode
PMC91n PFCE91n PFC91n
0
×
×
Port I/O mode
1
0
0
CSIF3 mode
1
0
1
UARTC2 mode
Remarks 1. n = 0, 1
2. × = don’t care
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.2 Features
{ Transfer rate: 12 Mbps max. (fXX = 48 MHz, using internal clock, master mode: CSIF3)
8 Mbps (fXX = 48 MHz, using internal clock, master mode: CSIF0 to CSIF2, CSIF4)
{ Master mode and slave mode selectable
{ 8-bit to 16-bit transfer, 3-wire serial interface
{ Interrupt request signals (INTCFnT, INTCFnR)
{ Serial clock and data phase switchable
{ Transfer data length selectable in 1-bit units between 8 and 16 bits
{ Transfer data MSB-first/LSB-first switchable
{ 3-wire transfer SOFn:
SIFn:
Serial data output
Serial data input
SCKFn: Serial clock I/O
{ Transmission mode, reception mode, and transmission/reception mode specifiable
Remark
n = 0 to 4
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18.3 Configuration
The following shows the block diagram of CSIFn.
Figure 18-4. Block Diagram of CSIFn
Internal bus
CFnCTL1
CFnCTL0
CFnCTL2
CFnSTR
INTCFnT
Note
fXX/3
fXX/4
fXX/6
fXX/8
fXX/32
fXX/64
Selector
Controller
fCCLK
INTCFnR
Phase control
fBRGm
CFnTX
SCKFn
SO latch
SIFn
Shift register
Phase
control
SOFn
CFnRX
Note For CSIF3: fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXX/64
Remark
fCCLK:
Communication clock
fXX:
Main clock frequency
fBRGm:
Count clock of the baud rate generator
n = 0 to 4
m = 1 (n = 0, 1)
m = 2 (n = 2, 3)
m = 3 (n = 4)
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CSIFn includes the following hardware.
Table 18-1. Configuration of CSIFn
Item
Configuration
CSIFn receive data register (CFnRX)
Registers
CSIFn transmit data register (CFnTX)
CSIFn control register 0 (CFnCTL0)
CSIFn control register 1 (CFnCTL1)
CSIFn control register 2 (CFnCTL2)
CSIFn status register (CFnSTR)
(1) CSIFn receive data register (CFnRX)
The CFnRX register is a 16-bit buffer register that holds receive data.
This register is read-only, in 16-bit units.
The receive operation is started by reading the CFnRX register in the reception enabled status.
If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CFnRXL
register.
Reset sets this register to 0000H.
In addition to reset input, the CFnRX register can be initialized by clearing (to 0) the CFnPWR bit of the CFnCTL0
register.
After reset: 0000H
R
Address: CF0RX FFFFFD04H, CF1RX FFFFFD14H,
CF2RX FFFFFD24H, CF3RX FFFFFD34H,
CF4RX FFFFFD44H
CFnRX
(n = 0 to 4)
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(2) CSIFn transmit data register (CFnTX)
The CFnTX register is a 16-bit buffer register used to write the CSIFn transfer data.
This register can be read or written in 16-bit units.
The transmit operation is started by writing data to the CFnTX register in the transmission enabled status.
If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CFnTXL register.
Reset sets this register to 0000H.
After reset 0000H
R/W
Address: CF0TX FFFFFD06H, CF1TX FFFFFD16H,
CF2TX FFFFFD26H, CF3TX FFFFFD36H,
CF4TX FFFFFD46H
CFnTX
(n = 0 to 4)
Remark
The communication start conditions are shown below.
Transmission mode (CFnTXE bit = 1, CFnRXE bit = 0):
Write to CFnTX register
Transmission/reception mode (CFnTXE bit = 1, CFnRXE bit = 1): Write to CFnTX register
Reception mode (CFnTXE bit = 0, CFnRXE bit = 1):
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.4 Registers
The following registers are used to control CSIFn.
• CSIFn control register 0 (CFnCTL0)
• CSIFn control register 1 (CFnCTL1)
• CSIFn control register 2 (CFnCTL2)
• CSIFn status register (CFnSTR)
(1) CSIFn control register 0 (CFnCTL0)
CFnCTL0 is a register that controls the CSIFn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
(1/3)
After reset: 01H
R/W
Address: CF0CTL0 FFFFFD00H, CF1CTL0 FFFFFD10H,
CF2CTL0 FFFFFD20H, CF3CTL0 FFFFFD30H,
CF4CTL0 FFFFFD40H
< >
CFnCTL0
< >
< >
< >
< >
CFnPWR CFnTXENote CFnRXENote CFnDIRNote
0
0
CFnTMSNote CFnSCE
(n = 0 to 4)
CFnPWR
Specification of CSIFn operation disable/enable
0
Disables CSIFn operation and resets the CFnSTR register
1
Enables CSIFn operation
• The CFnPWR bit controls the CSIFn operation and resets the internal circuit.
CFnTXENote
Specification of transmit operation disable/enable
0
Disables transmit operation
1
Enables transmit operation
• The SOFn output is low level when the CFnTXE bit is 0.
CFnRXENote
Specification of receive operation disable/enable
0
Disables receive operation
1
Enables receive operation
• No reception completion interrupt is output even when the prescribed data is
transferred, and the receive data (CFnRX register) is not updated, because the
receive operation is disabled by clearing the CFnRXE bit to 0.
Note These bits can only be rewritten when the CFnPWR bit = 0.
However, CFnPWR bit = 1 can also be set at the same time as
rewriting these bits.
Caution
To forcibly suspend transmission/reception, clear the CFnPWR
bit to 0 instead of the CFnRXE and CFnTXE bits.
At this time, the clock output is stopped.
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(2/3)
CFnDIRNote
Specification of transfer direction mode (MSB/LSB)
0
MSB-first transfer
1
LSB-first transfer
CFnTMSNote
Transfer mode specification
0
Single transfer mode
1
Continuous transfer mode
[In single transfer mode]
The reception completion interrupt (INTCFnR) occurs when communication is
complete.
Even if transmission is enabled (CFnTXE bit = 1), the transmission enable interrupt
(INTCFnT) does not occur.
If the next transmit data is written during communication (CFnSTR.CFnTSF bit =
1), it is ignored and the next communication is not started. Also, if reception-only
communication is set (CFnTXE bit = 0, CFnRXE bit = 1), the next communication
is not started even if the receive data is read during communication (CFnSTR.
CFnTSF bit = 1).
[In continuous transfer mode]
The continuous transmission is enabled by writing the next transmit data during
communication (CFnSTR.CFnTSF bit = 1).
Writing the next transmission data is enabled after a transmission enable interrupt
(INTCFnT) occurs.
If reception-only communication is set (CFnTXE bit = 0, CFnRXE bit = 1) in the
continuous transfer mode, the next reception is started immediately after a
reception completion interrupt (INTCFnR), regardless of the read operation of the
CFnRX register.
Therefore, immediately read the receive data from the CFnRX register. If this read
operation is delayed, an overrun error (CFnOVE bit = 1) occurs.
Note These bits can only be rewritten when the CFnPWR bit = 0. However, the CFnPWR
can be set to 1 at the same time as these bits are rewritten.
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(3/3)
CFnSCE
Specification of start transfer disable/enable
0
Communication start trigger invalid
1
Communication start trigger valid
• In master mode
This bit enables or disables the communication start trigger.
(a) In single transmission or transmission/reception mode, or continuous
transmission or continuous transmission/reception mode
A communication operation can be started by writing data to the CFnTX
register when the CFnSCE bit is 1.
Set the CFnSCE bit to 1.
(b) In single reception mode
Disable starting the next receive operation by clearing the CFnSCE bit to 0
before reading the last receive data, because a receive operation is started by
reading receive data (CFnRX register)Note 1.
(c) In continuous reception mode
Clear the CFnSCE bit to 0 one communication clock before reception of the
last data is completed to disable the start of reception after the last data is
receivedNote 2.
• In slave mode
This bit enables or disables the communication start trigger.
Set the CFnSCE bit to 1.
[Usage of CFnSCE bit]
• In single reception mode
When reception of the last data is completed by INTCFnR interrupt
servicing, clear the CFnSCE bit to 0 before reading the CFnRX register.
After confirming the CFnSTR.CFnTSF bit = 0, clear the CFnRXE bit to 0 to
disable reception.
To continue reception, set the CFnSCE bit to 1 to start the next reception
by dummy-reading the CFnRX register.
• In continuous reception mode
Clear the CFnSCE bit to 0 during reception of the last data by INTCFnR
interrupt servicing.
Read the CFnRX register.
Read the last reception data by reading the CFnRX register after
acknowledging the CFnTIR interrupt.
After confirming the CFnSTR.CFnTSF bit = 0, clear the CFnRXE bit to 0 to
disable reception.
To continue reception, set the CFnSCE bit to 1 to wait for the next reception
by dummy-reading the CFnRX register.
Notes 1. If the CFnSCE bit is read while it is 1, the next communication operation is started.
2. The CFnSCE bit is not cleared to 0 one communication clock before the completion
of the last data reception, the next communication operation is automatically
started.
Caution
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(2) CSIFn control register 1 (CFnCTL1)
CFnCTL1 is an 8-bit register that controls the CSIFn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution
The CFnCTL1 register can be rewritten only when the CFnCTL0.CFnPWR bit = 0.
After reset: 00H
R/W
Address: CF0CTL1 FFFFFD01H, CF1CTL1 FFFFFD11H,
CF2CTL1 FFFFFD21H, CF3CTL1 FFFFFD31H,
CF4CTL1 FFFFFD41H
CFnCTL1
0
0
CFnCKP CFnDAP CFnCKS2 CFnCKS1 CFnCKS0
0
(n = 0 to 4)
Specification of data transmission/
reception timing in relation to SCKFn
CFnCKP CFnDAP
0
Communication
type 1
0
SCKFn (I/O)
D7
SOFn (output)
D6
D5
D4
D3
D2
D1
D0
SIFn capture
0
Communication
type 2
1
SCKFn (I/O)
SOFn (output)
D7
D6
D5
D4
D3
D2
D1
D0
SIFn capture
1
Communication
type 3
0
SCKFn (I/O)
D7
SOFn (output)
D6
D5
D4
D3
D2
D1
D0
SIFn capture
1
Communication
type 4
1
SCKFn (I/O)
SOFn (output)
D7
D6
D5
D4
D3
D2
D1
D0
SIFn capture
CFnCKS2 CFnCKS1 CFnCKS0
Mode
Communication clock (fCCLK)
n = 3Note 2
n = 0 to 2, 4Note 1
0
0
0
fXX/3
fXX/2
Master mode
0
0
1
fXX/4
fXX/4
Master mode
0
1
0
fXX/6
fXX/8
Master mode
0
1
1
fXX/8
fXX/16
Master mode
1
0
0
fXX/32
fXX/32
Master mode
1
0
1
fXX/64
fXX/64
Master mode
1
1
0
fBRGm
Master mode
1
1
1
External clock (SCKFn)
Slave mode
Notes 1. Set the communication clock (fCCLK) to 8 MHz or lower (master/slave mode).
2. Set the communication clock (fCCLK) to 12 MHz or lower (master mode) and 8
MHz or lower (master/slave mode).
Remark
When n = 0, 1, m = 1
When n = 2, 3, m = 2
When n = 4, m = 3
For details of fBRGm, see 18.8 Baud Rate Generator.
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(3) CSIFn control register 2 (CFnCTL2)
CFnCTL2 is an 8-bit register that controls the number of CSIFn serial transfer bits.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution
The CFnCTL2 register can be rewritten only when the CFnCTL0.CFnPWR bit = 0 or when both the
CFnTXE and CFnRXE bits = 0.
After reset: 00H
R/W
Address: CF0CTL2 FFFFFD02H, CF1CTL2 FFFFFD12H,
CF2CTL2 FFFFFD22H, CF3CTL2 FFFFFD32H,
CF4CTL2 FFFFFD42H
CFnCTL2
0
0
0
0
CFnCL3 CFnCL2
CFnCL1
CFnCL0
(n = 0 to 4)
CFnCL3
CFnCL2 CFnCL1
CFnCL0
Serial register bit length
0
0
0
0
8 bits
0
0
0
1
9 bits
0
0
1
0
10 bits
0
0
1
1
11 bits
0
1
0
0
12 bits
0
1
0
1
13 bits
0
1
1
0
14 bits
0
1
1
1
15 bits
1
×
×
×
16 bits
Remarks 1. If the number of transfer bits is other than 8 or 16, prepare and
use data stuffed from the LSB of the CFnTX and CFnRX
registers.
2. ×: don’t care
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(a) Transfer data length change function
The CSIFn transfer data length can be set in 1-bit units between 8 and 16 bits using the CFnCTL2.CFnCL3 to
CFnCTL2.CFnCL0 bits.
When the transfer bit length is set to a value other than 16 bits, set the data to the CFnTX or CFnRX register
starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB. Any data can be set for
the higher bits that are not used, but the receive data becomes 0 following serial transfer.
(i) Transfer bit length = 10 bits, MSB first
SOFn
SIFn
15
10
9
0
Insertion of 0
(ii) Transfer bit length = 12 bits, LSB first
SIFn
15
12
SOFn
11
0
Insertion of 0
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(4) CSIFn status register (CFnSTR)
CFnSTR is an 8-bit register that displays the CSIFn status.
This register can be read or written in 8-bit or 1-bit units, but the CFnTSF flag is read-only.
Reset sets this register to 00H.
In addition to reset input, the CFnSTR register can be initialized by clearing (0) the CFnCTL0.CFnPWR bit.
After reset: 00H
R/W
Address: CF0STR FFFFFD03H, CF1STR FFFFFD13H,
CF2STR FFFFFD23H, CF3STR FFFFFD33H,
CF4STR FFFFFD43H
< >
< >
CFnSTR
CFnTSF
0
0
0
0
0
0
CFnOVE
(n = 0 to 4)
CFnTSF
Communication status flag
0
Communication stopped
1
Communicating
• During transmission, this register is set when data is prepared in the CFnTX
register, and during reception, it is set when a dummy read of the CFnRX register
is performed.
When transfer ends, this flag is cleared to 0 at the last edge of the clock.
CFnOVE
Overrun error flag
0
No overrun
1
Overrun
• An overrun error occurs when the next reception is completed without the CPU
reading the value of the receive buffer, upon completion of the receive operation.
The CFnOVE flag displays the overrun error occurrence status in this case.
• The CFnOVE bit is valid also in the single transfer mode. Therefore, when only
using transmission, note the following.
• Do not check the CFnOVE flag.
• Read this bit even if reading the reception data is not required.
• The CFnOVE flag is cleared by writing 0 to it. It cannot be set even by writing 1 to it.
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18.5 Interrupt Request Signals
CSIFn can generate the following two types of interrupt request signals.
• Reception completion interrupt request signal (INTCFnR)
• Transmission enable interrupt request signal (INTCFnT)
Of these two interrupt request signals, the reception completion interrupt request signal has the higher priority by
default, and the priority of the transmission enable interrupt request signal is lower.
Table 18-2. Interrupts and Their Default Priority
Interrupt
Priority
Reception complete
High
Transmission enable
Low
(1) Reception completion interrupt request signal (INTCFnR)
When receive data is transferred to the CFnRX register while reception is enabled, the reception completion
interrupt request signal is generated.
This interrupt request signal can also be generated if an overrun error occurs.
When the reception completion interrupt request signal is acknowledged and the data is read, read the CFnSTR
register to check that the result of reception is not an error.
In the single transfer mode, the INTCFnR interrupt request signal is generated upon completion of transmission,
even when only transmission is executed.
(2) Transmission enable interrupt request signal (INTCFnT)
In the continuous transmission or continuous transmission/reception mode, transmit data is transferred from the
CFnTX register and, as soon as writing to CFnTX has been enabled, the transmission enable interrupt request
signal is generated.
In the single transmission and single transmission/reception modes, the INTCFnT interrupt is not generated.
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18.6 Operation
18.6.1 Single transfer mode (master mode, transmission mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length =
8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
(1) Operation flow
START
(1), (2), (3)
CFnCTL1 register ← 00H
CFnCTL2 register ← 00H
CFnCTL0 register ← C1H
(4)
Write CFnTX register
(5)
Start transmission
(6)
INTCFnR interrupt
generated?
No
Yes
Transmission
completed?
No (7)
Yes
(8)
CFnCTL0 ← 00H
END
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4
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(2) Operation timing
CFnTSF bit
INTCFnR signal
SCKFn pin
SOFn pin
Bit 7
(1)
(2)
(3)
(4)
Bit 6
Bit 5
Bit 4
Bit 3
(5)
Bit 2
Bit 1
Bit 0
(6)
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(7)
Bit 0
(8)
(1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) =
fXX/2 or fXX/3, and master mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C1H to the CFnCTL0 register, and select the transmission mode and MSB first at the same time
as enabling the operation of the communication clock (fCCLK).
(4) Set the CFnSTR.CFnTSF bit to 1 by writing the transmit data to the CFnTX register, and start
transmission.
(5) When transmission is started, output the serial clock to the SCKFn pin, and output the transmit data
from the SOFn pin in synchronization with the serial clock.
(6) When transmission of the transfer data length set with the CFnCTL2 register is completiond, stop the
serial clock output and transmit data output, generate the reception completion interrupt request signal
(INTCFnR) at the last edge of the serial clock, and clear the CFnTSF bit to 0.
(7) To continue transmission, start the next transmission by writing the transmit data to the CFnTX register
again after the INTCFnR signal is generated.
(8) To end transmission, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnTXE bit = 0.
Remark
n = 0 to 4
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18.6.2 Single transfer mode (master mode, reception mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length =
8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
(1) Operation flow
START
(1), (2), (3)
CFnCTL1 register ← 00H
CFnCTL2 register ← 00H
CFnCTL0 register ← A1H
(4)
CFnRX register
dummy read
(5)
Start reception
(6)
INTCFnR interrupt
generated?
No
Yes
Reception completed?
Yes
(8)
CFnSCE bit = 0
(CFnCTL0)
(9)
Read CFnRX register
(10)
CFnCTL0 register ← 00H
No (7)
Read CFnRX register
END
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4
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(2) Operation timing
CFnTSF bit
INTCFnR signal
SCKFn pin
SIFn pin
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SIFn pin capture
timing
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) =
fXX/2 or fXX/3, and master mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A1H to the CFnCTL0 register, and select the reception mode and MSB first at the same time as
enabling the operation of the communication clock (fCCLK).
(4) Set the CFnSTR.CFnTSF bit to 1 by performing a dummy read of the CFnRX register, and start
reception.
(5) When reception is started, output the serial clock to the SCKFn pin, and capture the receive data of the
SIFn pin in synchronization with the serial clock.
(6) When reception of the transfer data length set with the CFnCTL2 register is completed, stop the serial
clock output and data capturing, generate the reception completion interrupt request signal (INTCFnR)
at the last edge of the serial clock, and clear the CFnTSF bit to 0.
(7) To continue reception, read the CFnRX register while keeping the CFnCTL0.CFnSCE bit = 1 after the
INTCFnR signal is generated.
(8) To read the CFnRX register without starting the next reception, write the CFnSCE bit = 0.
(9) Read the CFnRX register.
(10) To end reception, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit = 0.
Remark
n = 0 to 4
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18.6.3 Single transfer mode (master mode, transmission/reception mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length =
8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
(1) Operation flow
START
(1), (2), (3)
CFnCTL1 register ← 07H
CFnCTL2 register ← 00H
CFnCTL0 register ← E1H
(4)
Write CFnTX register
(5)
Start transmission/reception
(6)
INTCFnR interrupt
generated?
No
Yes
(7), (9)
Read CFnRX register
Transmission/reception
completed?
No (8)
Yes
(10)
CFnCTL0 ← 00H
END
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4
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(2) Operation timing
CFnTSF bit
INTCFnR signal
SCKFn pin
SOFn pin
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
SIFn pin
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
SIFn pin capture
timing
(1)
(2)
(3)
(4)
(5)
(6) (7) (8)
(9)(10)
(1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) =
fXX/2 or fXX/3, and master mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E1H to the CFnCTL0 register, and select the transmission/reception mode and MSB first at the
same time as enabling the operation of the communication clock (fCCLK).
(4) Set the CFnSTR.CFnTSF bit to 1 by writing the transmit data to the CFnTX register, and start
transmission/reception.
(5) When transmission/reception is started, output the serial clock to the SCKFn pin, output the transmit
data to the SOFn pin in synchronization with the serial clock, and capture the receive data of the SIFn
pin.
(6) When transmission/reception of the transfer data length set by the CFnCTL2 register is completed,
stop the serial clock output, transmit data output, and data capturing, generate the reception
completion interrupt request signal (INTCFnR) at the last edge of the serial clock, and clear the
CFnTSF bit to 0.
(7) Read the CFnRX register.
(8) To continue transmission/reception, write the transmit data to the CFnTX register again.
(9) Read the CFnRX register.
(10) To end transmission/reception, write CFnCTL0.CFnPWR bit = 0, CFnCTL0.CFnTXE bit = 0, and
CFnCTL0.CFnRXE bit = 0.
Remark
n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.6.4 Single transfer mode (slave mode, transmission mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer
data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
(1) Operation flow
START
(1), (2), (3)
CFnCTL1 register ← 07H
CFnCTL2 register ← 00H
CFnCTL0 register ← C1H
(4)
Write CFnTX register
(4)
SCKFn pin input
started?
No
Yes
(5)
Start transmission
(6)
INTCFnR interrupt
generated?
No
Yes
Transmission
completed?
No (7)
Yes
(8)
CFnCTL0 ← 00H
END
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4
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(2) Operation timing
CFnTSF bit
INTCFnR signal
SCKFn pin
SOFn pin
Bit 7
(1)
(2)
(3)
(4)
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
(5)
Bit 0
(6)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(7)
Bit 0
(8)
(1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) =
external clock (SCKFn), and slave mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C1H to the CFnCTL0 register, and select the transmission mode and MSB first at the same time
as enabling the operation of the communication clock (fCCLK).
(4) The CFnSTR.CFnTSF bit is set to 1 by writing the transmit data to the CFnTX register, and the device
waits for a serial clock input.
(5) When a serial clock is input, output the transmit data from the SOFn pin in synchronization with the
serial clock.
(6) When transmission of the transfer data length set with the CFnCTL2 register is completed, stop the
serial clock input and transmit data output, generate the reception completion interrupt request signal
(INTCFnR) at the last edge of the serial clock, and clear the CFnTSF bit to 0.
(7) To continue transmission, write the transmit data to the CFnTX register again after the INTCFnR signal
is generated, and wait for a serial clock input.
(8) To end transmission, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnTXE bit = 0.
Remark
n = 0 to 4
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18.6.5 Single transfer mode (slave mode, reception mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer
data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
(1) Operation flow
START
(1), (2), (3)
CFnCTL1 register ← 07H
CFnCTL2 register ← 00H
CFnCTL0 register ← A1H
(4)
CFnRX register
dummy read
(4)
SCKFn pin input
started?
No
Yes
(5)
Start reception
(6)
INTCFnR interrupt
generated?
No
Yes
(6)
Reception completed?
Yes
(8)
CFnSCE bit = 0
(CFnCTL0)
(9)
Read CFnRX register
(10)
CFnCTL0 register ← 00H
No (7)
Read CFnRX register
END
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4
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(2) Operation timing
CFnTSF bit
INTCFnR signal
SCKFn pin
SIFn pin
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SIFn pin capture
timing
(4)
(1)
(2)
(3)
(5)
(6)
(7)
(8)
(9)
(10)
(1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) =
external clock (SCKFn), and slave mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A1H to the CFnCTL0 register, and select the reception mode and MSB first at the same time as
enabling the operation of the communication clock (fCCLK).
(4) The CFnSTR.CFnTSF bit is set to 1 by performing a dummy read of the CFnRX register, and the
device waits for a serial clock input.
(5) When a serial clock is input, capture the receive data of the SIFn pin in synchronization with the serial
clock.
(6) When reception of the transfer data length set with the CFnCTL2 register is completed, stop the serial
clock input and data capturing, generate the reception completion interrupt request signal (INTCFnR)
at the last edge of the serial clock, and clear the CFnTSF bit to 0.
(7) To continue reception, read the CFnRX register while keeping the CFnCTL0.CFnSCE bit = 1 after the
INTCFnR signal is generated, and wait for a serial clock input.
(8) To end reception, write the CFnSCE bit = 0.
(9) Read the CFnRX register.
(10) To end reception, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit = 0.
Remark
n = 0 to 4
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18.6.6 Single transfer mode (slave mode, transmission/reception mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer
data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
(1) Operation flow
START
(1), (2), (3)
CFnCTL1 register ← 07H
CFnCTL2 register ← 00H
CFnCTL0 register ← E1H
(4)
Write CFnTX register
(4)
SCKFn pin input
started?
No
Yes
(5)
Start transmission/reception
(6)
INTCFnR interrupt
generated?
No
Yes
(7), (9)
Read CFnRX register
Transmission/reception
completed?
No (8)
Yes
(10)
CFnCTL0 ← 00H
END
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4
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(2) Operation timing
CFnTSF bit
INTCFnR signal
SCKFn pin
SOFn pin
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SIFn pin
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SIFn pin capture
timing
(1)
(2)
(3)
(4)
(5)
(6) (7) (8)
(9)(10)
(1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) =
external clock (SCKFn), and slave mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E1H to the CFnCTL0 register, and select the transmission/reception mode and MSB first at the
same time as enabling the operation of the communication clock (fCCLK).
(4) The CFnSTR.CFnTSF bit is set to 1 by writing the transmit data to the CFnTX register, and the device
waits for a serial clock input.
(5) When a serial clock is input, output the transmit data to the SOFn pin in synchronization with the serial
clock, and capture the receive data of the SIFn pin.
(6) When transmission/reception of the transfer data length set with the CFnCTL2 register is completed,
stop the serial clock input, transmit data output, and data capturing, generate the reception completion
interrupt request signal (INTCFnR) at the last edge of the serial clock, and clear the CFnTSF bit to 0.
(7) Read the CFnRX register.
(8) To continue transmission/reception, write the transmit data to the CFnTX register again, and wait for a
serial clock input.
(9) Read the CFnRX register.
(10) To end transmission/reception, write CFnCTL0.CFnPWR bit = 0, CFnCTL0.CFnTXE bit = 0, and
CFnCTL0.CFnRXE bit = 0.
Remark
n = 0 to 4
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18.6.7 Continuous transfer mode (master mode, transmission mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length =
8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
(1) Operation flow
START
(1), (2), (3)
(4), (8)
CFnCTL1 register ← 00H
CFnCTL2 register ← 00H
CFnCTL0 register ← C3H
Write CFnTX register
(5)
Start transmission
(6), (9)
INTCFnT interrupt
generated?
No
Yes
Transmission
completed?
No (7)
Yes
(10)
CFnTSF bit = 0?
(CFnSTR register)
No
Yes
(11)
CFnCTL0 ← 00H
END
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4
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(2) Operation timing
CFnTSF bit
INTCFnT signal
INTCFnR signal
L
SCKFn pin
SOFn pin
Bit 7
(1)
(2)
(3)
(4)
(5)
Bit 6
(6)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(7)
Bit 0 Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
(8) (9)
(10)
(11)
(1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) =
fXX/2 or fXX/3, and master mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C3H to the CFnCTL0 register, and select the transmission mode, MSB first, and continuous
transfer mode at the same time as enabling the operation of the communication clock (fCCLK).
(4) Set the CFnSTR.CFnTSF bit to 1 by writing the transmit data to the CFnTX register, and start
transmission.
(5) When transmission is started, output the serial clock to the SCKFn pin, and output the transmit data
from the SOFn pin in synchronization with the serial clock.
(6) When transfer of the transmit data from the CFnTX register to the shift register is completed and
writing to the CFnTX register is enabled, the transmission enable interrupt request signal (INTCFnT) is
generated.
(7) To continue transmission, write the transmit data to the CFnTX register again after the INTCFnT signal
is generated.
(8) When a new transmit data is written to the CFnTX register before communication completion, the next
communication is started following communication completion.
(9) The transfer of the transmit data from the CFnTX register to the shift register is completed and the
INTCFnT signal is generated. To end continuous transmission with the current transmission, do not
write to the CFnTX register.
(10) When the next transmit data is not written to the CFnTX register before transfer completion, stop the
serial clock output to the SCKFn pin after transfer completion, and clear the CFnTSF bit to 0.
(11) To release the transmission enable status, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnTXE bit
= 0 after checking that the CFnTSF bit = 0.
Caution In continuous transmission mode, the reception completion interrupt request signal
(INTCFnR) is not generated.
Remark
n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.6.8 Continuous transfer mode (master mode, reception mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length =
8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(1) Operation flow
START
(1), (2), (3)
CFnCTL1 register ← 00H
CFnCTL2 register ← 00H
CFnCTL0 register ← A3H
(4)
CFnRX register
dummy read
(5)
Start reception
No
INTCFnR interrupt
generated?
Yes
CFnOVE bit = 1?
(CFnSTR)
No
(6)
Yes
(8)
Is data being received
last data?
CFnSCE bit = 0
(CFnCTL0)
No
(7)
Yes
(9)
Read CFnRX register
(12)
CFnOVE bit = 0
(CFnSTR)
(8)
CFnSCE bit = 0
(CFnCTL0)
(9)
(9)
Read CFnRX register
(10)
INTCFnR interrupt
generated?
Read CFnRX register
No
Yes
(11)
(13)
CFnTSF bit = 0?
(CFnSTR)
Read CFnRX register
No
Yes
(13)
CFnCTL0 register ← 00H
END
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(2) Operation timing
CFnTSF bit
INTCFnR signal
CFnSCE bit
SCKFn pin
SOFn pin
L
SIFn pin
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0 Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
SIFn pin capture
timing
(1) (3) (4)
(2)
(5)
(6) (7) (8) (9)
(10)
(11) (13)
(1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) =
fXX/2, and master mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A3H to the CFnCTL0 register, and select the reception mode, MSB first, and continuous transfer
mode at the same time as enabling the operation of the communication clock (fCCLK).
(4) Set the CFnSTR.CFnTSF bit to 1 by performing a dummy read of the CFnRX register, and start
reception.
(5) When reception is started, output the serial clock to the SCKFn pin, and capture the receive data of the
SIFn pin in synchronization with the serial clock.
(6) When reception is completed, the reception completion interrupt request signal (INTCFnR) is
generated, and reading of the CFnRX register is enabled.
(7) When the CFnCTL0.CFnSCE bit = 1 upon communication completion, the next communication is
started following communication completion.
(8) To end continuous reception with the current reception, write the CFnSCE bit = 0.
(9) Read the CFnRX register.
(10) When reception is completed, the INTCFnR signal is generated, and reading of the CFnRX register is
enabled. When the CFnSCE bit = 0 is set before communication completion, stop the serial clock
output to the SCKFn pin, and clear the CFnTSF bit to 0, to end the receive operation.
(11) Read the CFnRX register.
(12) If an overrun error occurs, write the CFnSTR.CFnOVE bit = 0, and clear the error flag.
(13) To release the reception enable status, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit =
0 after checking that the CFnTSF bit = 0.
Remark
n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.6.9 Continuous transfer mode (master mode, transmission/reception mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (fCCLK) = fXX/2 or fXX/3 (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 000), transfer data length =
8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(1) Operation flow
START
(1), (2), (3)
CFnCTL1 register ← 00H
CFnCTL2 register ← 00H
CFnCTL0 register ← E3H
(4)
Write CFnTX register
(5)
Start transmission/reception
(6), (11)
INTCFnT interrupt
generated?
No
Yes
(7)
Is data being transmitted
last data?
Yes (11)
No
(7)
No
Write CFnTX register
INTCFnR interrupt
generated?
(8)
Yes
No (9)
CFnOVE bit = 1?
(CFnSTR)
(10)
Read CFnRX register
Yes (13)
(13)
Read CFnRX register
Is receive data
last data?
(14)
(15)
CFnOVE bit = 0
(CFnSTR)
CFnTSF bit = 0?
(CFnSTR)
No
Yes (12)
No
Yes
(15)
CFnCTL0 register ← 00H
END
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(2) Operation timing
(1/2)
CFnTSF bit
INTCFnT signal
INTCFnR signal
SCKFn pin
SOFn pin
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SIFn pin
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SIFn pin capture
timing
(4)
(1)
(2)
(3)
(5)
(6)
(7)
(8) (9) (10) (11)
(12)
(13) (15)
(1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) =
fXX/2 or fXX/3, and master mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E3H to the CFnCTL0 register, and select the transmission/reception mode, MSB first, and
continuous transfer mode at the same time as enabling the operation of the communication clock
(fCCLK).
(4) Set the CFnSTR.CFnTSF bit to 1 by writing the transmit data to the CFnTX register, and start
transmission/reception.
(5) When transmission/reception is started, output the serial clock to the SCKFn pin, output the transmit
data to the SOFn pin in synchronization with the serial clock, and capture the receive data of the SIFn
pin.
(6) When transfer of the transmit data from the CFnTX register to the shift register is completed and
writing to the CFnTX register is enabled, the transmission enable interrupt request signal (INTCFnT) is
generated.
(7) To continue transmission/reception, write the transmit data to the CFnTX register again after the
INTCFnT signal is generated.
(8) When one transmission/reception is completed, the reception completion interrupt request signal
(INTCFnR) is generated, and reading of the CFnRX register is enabled.
(9) When a new transmit data is written to the CFnTX register before communication completion, the next
communication is started following communication completion.
(10) Read the CFnRX register.
Remark
n = 0 to 4
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(2/2)
(11) The transfer of the transmit data from the CFnTX register to the shift register is completed and the
INTCFnT signal is generated.
To end continuous transmission/reception with the current
transmission/reception, do not write to the CFnTX register.
(12) When the next transmit data is not written to the CFnTX register before transfer completion, stop the
serial clock output to the SCKFn pin after transfer completion, and clear the CFnTSF bit to 0.
(13) When the reception error interrupt request signal (INTCFnR) is generated, read the CFnRX register.
(14) If an overrun error occurs, write CFnSTR.CFnOVE bit = 0, and clear the error flag.
(15) To
release
the
transmission/reception
enable
status,
write
CFnCTL0.CFnPWR
bit
=
0,
CFnCTL0.CFnTXE bit = 0, and CFnCTL0.CFnRXE bit = 0 after checking that the CFnTSF bit = 0.
Remark
n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.6.10 Continuous transfer mode (slave mode, transmission mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer
data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
(1) Operation flow
START
(1), (2), (3)
CFnCTL1 register ← 07H
CFnCTL2 register ← 00H
CFnCTL0 register ← C3H
(4)
Write CFnTX register
(4)
SCKFn pin input
started?
No
Yes
(5), (8)
Start transmission
(6), (9)
INTCFnT interrupt
generated?
No
Yes
(9)
Transmission
completed?
No (7)
Yes
(10)
CFnTSF bit = 0?
(CFnSTR register)
No
Yes
(11)
CFnCTL0 ← 00H
END
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(2) Operation timing
CFnTSF bit
INTCFnT signal
SCKFn pin
SOFn pin
Bit 7
(1)
(2)
(3)
(4)
(5)
Bit 6
(6)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(7)
Bit 0 Bit 7
(8)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(9)
Bit 0
(10)
(11)
(1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) =
external clock (SCKFn), and slave mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C3H to the CFnCTL0 register, and select the transmission mode, MSB first, and continuous
transfer mode at the same time as enabling the operation of the communication clock (fCCLK).
(4) The CFnSTR.CFnTSF bit is set to 1 by writing the transmit data to the CFnTX register, and the device
waits for a serial clock input.
(5) When a serial clock is input, output the transmit data from the SOFn pin in synchronization with the
serial clock.
(6) When transfer of the transmit data from the CFnTX register to the shift register is completed and
writing to the CFnTX register is enabled, the transmission enable interrupt request signal (INTCFnT) is
generated.
(7) To continue transmission, write the transmit data to the CFnTX register again after the INTCFnT signal
is generated.
(8) When a serial clock is input following completion of the transmission of the transfer data length set with
the CFnCTL2 register, continuous transmission is started.
(9) When transfer of the transmit data from the CFnTX register to the shift register is completed and
writing to the CFnTX register is enabled, the INTCFnT signal is generated.
To end continuous
transmission with the current transmission, do not write to the CFnTX register.
(10) When the clock of the transfer data length set with the CFnCTL2 register is input without writing to the
CFnTX register, clear the CFnTSF bit to 0 to end transmission.
(11) To release the transmission enable status, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnTXE bit
= 0 after checking that the CFnTSF bit = 0.
Caution
In continuous transmission mode, the reception completion interrupt request signal
(INTCFnR) is not generated.
Remark
n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.6.11 Continuous transfer mode (slave mode, reception mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer
data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(1) Operation flow
START
(1), (2), (3)
CFnCTL1 register ← 07H
CFnCTL2 register ← 00H
CFnCTL0 register ← A3H
(4)
CFnRX register
dummy read
(4)
SCKFn pin input
started?
No
Yes
(5)
Reception start
No
INTCFnR interrupt
generated?
Yes
CFnOVE bit = 1?
(CFnSTR)
No
(6)
Yes
CFnSCE bit = 0
(CFnCTL0)
(8)
(9)
Is data being received
last data?
Read CFnRX register
(7)
Yes
(8)
CFnOVE bit = 0
(CFnSTR)
(12)
No
CFnSCE bit = 0
(CFnCTL0)
(9)
(9)
Read CFnRX register
(10)
INTCFnR interrupt
generated?
Read CFnRX register
No
Yes
(11)
CFnTSF bit = 0?
(CFnSTR)
(13)
Read CFnRX register
No
Yes
(13)
CFnCTL0 register ← 00H
END
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(2) Operation timing
CFnTSF bit
INTCFnR signal
CFnSCE bit
SCKFn pin
SIFn pin
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
SIFn pin capture
timing
(1) (3) (4)
(2)
(5)
(6) (7) (8) (9)
(10)
(11) (13)
(1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) =
external clock (SCKFn), and slave mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A3H to the CFnCTL0 register, and select the reception mode, MSB first, and continuous transfer
mode at the same time as enabling the operation of the communication clock (fCCLK).
(4) The CFnSTR.CFnTSF bit is set to 1 by performing a dummy read of the CFnRX register, and the
device waits for a serial clock input.
(5) When a serial clock is input, capture the receive data of the SIFn pin in synchronization with the serial
clock.
(6) When reception is completed, the reception completion interrupt request signal (INTCFnR) is
generated, and reading of the CFnRX register is enabled.
(7) When a serial clock is input in the CFnCTL0.CFnSCE bit = 1 status, continuous reception is started.
(8) To end continuous reception with the current reception, write the CFnSCE bit = 0.
(9) Read the CFnRX register.
(10) When reception is completed, the INTCFnR signal is generated, and reading of the CFnRX register is
enabled. When CFnSCE bit = 0 is set before communication completion, clear the CFnTSF bit to 0 to
end the receive operation.
(11) Read the CFnRX register.
(12) If an overrun error occurs, write CFnSTR.CFnOVE bit = 0, and clear the error flag.
(13) To release the reception enable status, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit =
0 after checking that the CFnTSF bit = 0.
Remark
n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.6.12 Continuous transfer mode (slave mode, transmission/reception mode)
MSB first (CFnCTL0.CFnDIR bit = 0), communication type 1 (CFnCTL1.CFnCKP and CFnCTL1.CFnDAP bits = 00),
communication clock (fCCLK) = external clock (SCKFn) (CFnCTL1.CFnCKS2 to CFnCTL1.CFnCKS0 bits = 111), transfer
data length = 8 bits (CFnCTL2.CFnCL3 to CFnCTL2.CFnCL0 bits = 0000)
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(1) Operation flow
START
(1), (2), (3)
CFnCTL1 register ← 07H
CFnCTL2 register ← 00H
CFnCTL0 register ← E3H
(4)
Write CFnTX register
(4)
SCKFn pin input
started?
No
Yes
(5)
(6), (11)
Start transmission/reception
INTCFnT interrupt
generated?
No
Yes
(7)
Is data being transmitted
last data?
Yes (11)
No
(7)
No
Write CFnTX register
INTCFnR interrupt
generated?
(8)
Yes
No (9)
CFnOVE bit = 1?
(CFnSTR)
(10)
Yes (13)
(13)
Read CFnRX register
(14)
CFnOVE bit = 0
(CFnSTR)
Read CFnRX register
Is receive data
last data?
No
Yes (12)
(15)
CFnTSF bit = 0?
(CFnSTR)
No
Yes
(15)
CFnCTL0 register ← 00H
END
Remarks 1. The broken lines indicate the hardware processing.
2. The numbers in this figure correspond to the processing numbers in (2) Operation timing.
3. n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(2) Operation timing
(1/2)
CFnTSF bit
INTCFnT signal
INTCFnR signal
SCKFn pin
SOFn pin
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
SIFn pin
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
SIFn pin capture
timing
(4)
(1)
(2)
(3)
(5)
(6)
(7)
(8) (9) (10)
(11)
(12)
(13) (15)
(1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (fCCLK) =
external clock (SCKFn), and slave mode.
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E3H to the CFnCTL0 register, and select the transmission/reception mode, MSB first, and
continuous transfer mode at the same time as enabling the operation of the communication clock
(fCCLK).
(4) The CFnSTR.CFnTSF bit is set to 1 by writing the transmit data to the CFnTX register, and the device
waits for a serial clock input.
(5) When a serial clock is input, output the transmit data to the SOFn pin in synchronization with the serial
clock, and capture the receive data of the SIFn pin.
(6) When transfer of the transmit data from the CFnTX register to the shift register is completed and
writing to the CFnTX register is enabled, the transmission enable interrupt request signal (INTCFnT) is
generated.
(7) To continue transmission, write the transmit data to the CFnTX register again after the INTCFnT signal
is generated.
(8) When reception of the transfer data length set with the CFnCTL2 register is completed, the reception
completion interrupt request signal (INTCFnR) is generated, and reading of the CFnRX register is
enabled.
(9) When a serial clock is input continuously, continuous transmission/reception is started.
(10) Read the CFnRX register.
(11) When transfer of the transmit data from the CFnTX register to the shift register is completed and
writing to the CFnTX register is enabled, the INTCFnT signal is generated.
To end continuous
transmission/reception with the current transmission/reception, do not write to the CFnTX register.
Remark
n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(2/2)
(12) When the clock of the transfer data length set with the CFnCTL2 register is input without writing to the
CFnTX register, the INTCFnR signal is generated.
Clear the CFnTSF bit to 0 to end
transmission/reception.
(13) When the INTCFnR signal is generated, read the CFnRX register.
(14) If an overrun error occurs, write CFnSTR.CFnOVE bit = 0, and clear the error flag.
(15) To
release
the
transmission/reception
enable
status,
write
CFnCTL0.CFnPWR
bit
=
0,
CFnCTL0.CFnTXE bit = 0, and CFnCTL0.CFnRXE bit = 0 after checking that the CFnTSF bit = 0.
Remark
n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.6.13 Reception error
When transfer is performed with reception enabled (CFnCTL0.CFnRXE bit = 1) in the continuous transfer mode, the
reception completion interrupt request signal (INTCFnR) is generated again when the next receive operation is completed
before the CFnRX register is read after the INTCFnR signal is generated, and the overrun error flag (CFnSTR.CFnOVE) is
set to 1.
Even if an overrun error has occurred, the previous receive data is lost since the CFnRX register is updated. Even if a
reception error has occurred, the INTCFnR signal is generated again upon the next reception completion if the CFnRX
register is not read.
To avoid an overrun error, complete reading the CFnRX register by one half clock before sampling the last bit of the
next receive data from the INTCFnR signal generation.
(1) Operation timing
CFnRX register
read signal
INTCFnR signal
CFnOVE bit
CFnRX register
AAH
Shift register
01H
02H
05H 0AH
15H 2AH 55H
AAH 00H
01H
55H
02H
05H
0AH
15H 2AH 55H
SCKFn pin
SIFn pin
SIFn pin capture
timing
(1)
(2)
(3)(4)
(1) Start continuous transfer.
(2) Completion of the first transfer
(3) The CFnRX register cannot be read until one half clock before the completion of the second transfer.
(4) An overrun error occurs, and the reception completion interrupt request signal (INTCFnR) is
generated, and then the overrun error flag (CFnSTR.CFnOVE) is set to 1.
The receive data is
overwritten.
Remark
n = 0 to 4
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CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.6.14 Clock timing
(1/2)
(i) Communication type 1 (CFnCKP and CFnDAP bits = 00)
SCKFn pin
SIFn capture
SOFn pin
D7
D6
D5
D4
D3
D2
D1
D0
Reg-R/W
INTCFnT
interruptNote 1
INTCFnR
interruptNote 2
CFnTSF bit
(ii) Communication type 3 (CFnCKP and CFnDAP bits = 10)
SCKFn pin
SIFn capture
SOFn pin
D7
D6
D5
D4
D3
D2
D1
D0
Reg-R/W
INTCFnT
interruptNote 1
INTCFnR
interruptNote 2
CFnTSF bit
Notes 1. The INTCFnT interrupt is set when the data written to the CFnTX register is transferred to the data
shift register in the continuous transmission or continuous transmission/reception mode. In the
single transmission or single transmission/reception mode, the INTCFnT interrupt request signal is
not generated, but the INTCFnR interrupt request signal is generated upon end of communication.
2. The INTCFnR interrupt occurs if reception is correctly ended and receive data is ready in the CFnRX
register while reception is enabled. In the single mode, the INTCFnR interrupt request signal is
generated even in the transmission mode, upon end of communication.
Caution
In single transfer mode, writing to the CFnTX register with the CFnTSF bit set to 1 is ignored.
This has no effect on the operation during transfer.
For example, if the next data is written to the CFnTX register when DMA is started by
generating the INTCFnR signal, the written data is not transferred because the CFnTSF bit is
set to 1.
Use the continuous transfer mode, not the single transfer mode, for such applications.
Remark
n = 0 to 4
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 808 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(2/2)
(iii) Communication type 2 (CFnCKP and CFnDAP bits = 01)
SCKFn pin
SIFn capture
D7
SOFn pin
D6
D5
D4
D3
D2
D1
D0
Reg-R/W
INTCFnT
interruptNote 1
INTCFnR
interruptNote 2
CFnTSF bit
(iv) Communication type 4 (CFnCKP and CFnDAP bits = 11)
SCKFn pin
SIFn capture
SOFn pin
D7
D6
D5
D4
D3
D2
D1
D0
Reg-R/W
INTCFnT
interruptNote 1
INTCFnR
interruptNote 2
CFnTSF bit
Notes 1. The INTCFnT interrupt is set when the data written to the CFnTX register is transferred to the data
shift register in the continuous transmission or continuous transmission/reception modes. In the
single transmission or single transmission/reception modes, the INTCFnT interrupt request signal is
not generated, but the INTCFnR interrupt request signal is generated upon end of communication.
2. The INTCFnR interrupt occurs if reception is correctly ended and receive data is ready in the CFnRX
register while reception is enabled. In the single mode, the INTCFnR interrupt request signal is
generated even in the transmission mode, upon end of communication.
Caution
In single transfer mode, writing to the CFnTX register with the CFnTSF bit set to 1 is ignored.
This has no effect on the operation during transfer.
For example, if the next data is written to the CFnTX register when DMA is started by
generating the INTCFnR signal, the written data is not transferred because the CFnTSF bit is
set to 1.
Use the continuous transfer mode, not the single transfer mode, for such applications.
Remark
n = 0 to 4
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 809 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.7 Output Pins
(1) SCKFn pin
When CSIFn operation is disabled (CFnCTL0.CFnPWR bit = 0), the SCKFn pin output status is as follows.
CFnCKP
CFnCKS2
CFnCKS1
CFnCKS0
0
1
1
1
Other than above
1
1
1
High impedance
Fixed to high level
1
Other than above
SCKFn Pin Output
High impedance
Fixed to low level
Remarks 1. The output level of the SCKFn pin changes if any of the CFnCTL1.CFnCKP or CFnCKS2 to
CFnCKS0 bits is rewritten.
2. n = 0 to 4
(2) SOFn pin
When CSIFn operation is disabled (CFnPWR bit = 0), the SOFn pin output status is as follows.
CFnTXE
CFnDAP
CFnDIR
0
×
×
Fixed to low level
1
0
×
SOFn latch value (low level)
1
SOFn Pin Output
0
CFnTX value (MSB)
1
CFnTX value (LSB)
Remarks 1. The SOFn pin output changes when any one of the
CFnCTL0.CFnTXE, CFnCTL0.CFnDIR or CFnCTL1.CFnDAP bit
is rewritten.
2. ×: Don’t care
3. n = 0 to 4
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 810 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
18.8 Baud Rate Generator
The BRG1 to BRG3 baud rate generators are connected to CSIF0 to CSIF4 as shown in the following block diagram.
fXX
BRG1
fBRG1
CSIF0
CSIF1
fXX
BRG2
fBRG2
CSIF2
CSIF3
fXX
BRG3
fBRG3
CSIF4
(1) Prescaler mode registers 1 to 3 (PRSM1 to PRSM3)
The PRSM1 to PRSM3 registers control generation of the baud rate signal for CSIF.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
After reset: 00H
R/W
Address: PRSM1 FFFFF320H, PRSM2 FFFFF324H,
PRSM3 FFFFF328H
< >
PRSMm
(m = 1 to 3)
0
0
0
BGCEm
BGCEm
0
0
BGCSm1 BGCSm0
Baud rate output
0
Disabled
1
Enabled
Input clock selection (fBGCSm)
BGCSm1 BGCSm0
Setting value (k)
0
0
fXX
0
0
1
fXX/2
1
1
0
fXX/4
2
1
1
fXX/8
3
Cautions 1. Do not rewrite the PRSMm register during operation.
2. Set the PRSMm register before setting the BGCEm bit to 1.
2. Be sure to set bits 7 to 5, 3, and 2 to “0”.
R01UH0042EJ0510 Rev.5.10
Mar 25, 2014
Page 811 of 1513
V850ES/JG3-H, V850ES/JH3-H
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(2) Prescaler compare registers 1 to 3 (PRSCM1 to PRSCM3)
The PRSCM1 to PRSCM3 registers are 8-bit compare registers.
These registers can be read or written in 8-bit units.
Reset sets these registers to 00H.
After reset: 00H
R/W
Address: PRSCM1 FFFFF321H, PRSCM2 FFFFF325H,
PRSCM3 FFFFF329H
PRSCMm
PRSCMm7 PRSCMm6 PRSCMm5 PRSCMm4 PRSCMm3 PRSCMm2 PRSCMm1 PRSCMm0
Cautions 1. Do not rewrite the PRSCMm register during operation.
2. Set
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