UPD720210K8-BAF-A

Data Sheet μPD720210 ASSP (Four-port USB3.0 Hub Controller) R19DS0070EJ0200 Rev.2.00 May 26, 2014 1. OVERVIEW The μPD720210 is a USB 3.0 hub controller that complies with the Universal Serial Bus (USB) Specification Revision 3.0 and operates at up to 5 Gbps. The device incorporates Renesas’ market proven design expertise in USB 3.0 interface technologies and market proven USB 2.0 hub core. The device is fully compatible with all prior versions of USB spec and 100% compatible with Renesas’ industry standard USB 3.0 host controller. It comes in a small 76-pin QFN package and integrates several commonly required external components, making it ideally suited for applications with limited PCB space. In addition, the μPD720210 incorporates Renesas’ low-power technologies and supports all main-stream battery charging specifications. 1.1 Features                Compliant with Universal Serial Bus 3.0 Specification Revision 1.0, which is released by USB Implementers Forum, Inc Supports the following speed data rates as follows: Low-speed (1.5 Mbps) / Full-speed (12 Mbps) / High-speed (480 Mbps) / Superspeed (5 Gbps) Supports USB 3.0 link power management (U0/U1/U2/U3) Supports USB 2.0 link power management (LPM: L0/L1/L2/L3) Configurable downstream port counts of 2, 3, or 4 ports Supports all VBUS control options Individual or global over-current detection Individual or ganged power control Supports USB 3.0/2.0 Compound (non-removable) devices by I/O pin configuration Supports clock output (24/12 MHz) for Compound (non-removal) device on downstream ports Supports Energy Star and EuP specifications for low-power PC peripheral system Single 5 V Power Supply On chip LDO for 3.3 V from 5 V input and Switching Regulator for 1.05 V from 5 V input System clock: 24 MHz Crystal or Oscillator Supports USB Battery Charging Specification Revision 1.2 and other portable devices DCP mode of BC 1.2 CDP mode of BC 1.2 China Mobile Phone Chargers EU Mobile Phone Chargers Apple iOS products Other major portable devices Supports SPI ROM for optional firmware and parameter data Small Footprint Small and low pin count package with simple pin assignment for PCB layout Integration of many peripheral components Direct routing of all USB signal traces to connector pins using one layer of the PCB Self/Bus-Powered modes can be set by pin strapping Integrated termination resistors for USB Provides SUSPEND status output Supports Port Indicator control (only Green color) R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 1 of 41 μPD720210 1.2 1. OVERVIEW Applications Stand-alone Hub, Monitor-Hub, Docking Station, Integrated Hub, etc. 1.3 Ordering Information Part Number μPD720210K8-BAF-A R19DS0070EJ0200 Rev.2.00 May 26, 2014 Package 76-pin QFN (9 × 9) Operating Temperature 0 to +70°C Remark Lead-free product Page 2 of 41 μPD720210 1.4 1. OVERVIEW Block Diagram Figure 1-1. μPD720210 Block Diagram 5v FET Control 1.05v SW Regulator (V50IN -> VDD10) VBUS Switch 5v 3.3v LDO (V50IN -> VDD33) HS/FS/LS US Port Control HS/FS/LS Hub Core HS/FS/LS DS Port Control HS/FS/LS PHY SS-PHY USB Connector VBUS Switch HS/FS/LS PHY SS-PHY VBUS VBUS Monitor VBUS Switch SS-PHY HS/FS/LS PHY OSC 24MHz CLKOUT 12/24MHz SPI ROM VBUS Control HS/FS/LS PHY USB Connector SS-PHY SPI I/F R19DS0070EJ0200 Rev.2.00 May 26, 2014 SS US Port Control SS Hub Core SS DS Port Control USB Connector USB Connector VBUS Switch HS/FS/LS PHY SS-PHY USB Connector Page 3 of 41 μPD720210 1. OVERVIEW Table 1-1. Terminology Block Name Description SS PHY SuperSpeed Tx/Rx HS/FS/LS PHY High-/Full-/Low-speed transceiver VBUS Monitor Monitors the VBUS voltage level of the upstream port. SS US Port Control Upstream port control logic for SuperSpeed HS/FS/LS US Port Control Upstream port control logic for High-/Full-/Low-speed SS Hub Core Central control logic for SS-Hub. HS/FS/LS Hub Core Central control logic for HS/FS/LS-Hub. SS DS Port Control Downstream port control logic for SuperSpeed HS/FS/LS DS Port Control Downstream port control logic for HS/FS/LS VBUS Control Controls all the port power switches SPI Interface Connected to external serial ROM which can hold the optional firmware and hub settings SW-Regulator Switching regulator control logic to output 1.05 V power from 5 V input, utilizing the external transistor LDO Low Drop Out regulator integrated in this hub R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 4 of 41 μPD720210 1.5 1. OVERVIEW Pin Configuration • 76-pin QFN (9 × 9) μPD720210K8-BAF-A PPON3B 58 59 OCI4B PPON4B 60 61 62 VDD33 U2DPU U2DMU 63 64 VDD10 U3TXDNU 65 U3TXDPU 66 67 VDD10 U3RXDNU 68 U3RXDPU 69 VDD10 70 71 RREF 72 IC(L) 73 XT1 41 18 40 19 OCI3B PPON2B OCI2B V10FB ILIM NGDRV PGDRV AVDD33R V50IN V33OUT VDD10 PPON1B/NRDRSTB OCI1B BUSSEL VBUSM VDD33 SPISCK/LED4B SPISO/LED3B 38 SPISI/LED2B SPICSB 37 LED1B/SUSPEND 36 U2DM4 35 U2DP4 34 VDD33 33 U3RXDN4 32 U3RXDP4 31 VDD10 30 U3TXDN4 29 39 U3TXDP3 R19DS0070EJ0200 Rev.2.00 May 26, 2014 74 42 17 20 U2DM2 43 16 U3TXDP4 U2DP2 44 15 28 VDD33 45 14 VDD10 U3RXDN2 46 13 27 U3RXDP2 47 12 U2DM3 VDD10 48 11 26 U3TXDN2 49 GND U2DP3 U3TXDP2 10 25 VDD10 50 9 VDD33 U2DM1 51 8 24 U2DP1 52 7 U3RXDN3 VDD33 53 6 23 U3RXDN1 54 5 U3RXDP3 U3RXDP1 55 4 22 VDD10 56 3 VDD10 U3TXDN1 75 XT2 VDD33 76 U3TXDP1 57 2 21 RESETB 1 U3TXDN3 SUSPEND/NRDCLKO AVDD33 Pin Configuration of μPD720210 (Top View) Figure 1-2. Page 5 of 41 μPD720210 2. PIN FUNCTION 2. PIN FUNCTION This section describes each pin functions. Strapping information in the tables shows the pin can be used to configure the functional settings of this controller when it is pulled up/down. See μPD720210 User’s Manual (R19UH0093E) for detail. 2.1 Power Supply Pin Name I/O Type Pin No. Function 5, 11, 14, VDD10 22, 28, 31, 47, 64, 67, Power 1.05 V power supply for Core Logic Power 3.3 V power supply for IO buffer 3.3 V power supply for Analog circuit 70 8, 17, 25, VDD33 34, 42, 61, 76 AVDD33 71 Power V50IN 49 Power LDO Regulator 5 V Input Need to be connected to GND, when integrated LDO is not used. LDO 3.3 V Output V33OUT 48 Power 15 kΩ and 4.7 μF are required between this pin and GND, when integrated LDO is not used. AVDD33R 50 Power SW Regulator 3.3 V Input NGDRV 52 - SW Regulator Nch FET Control Note PGDRV 51 - SW Regulator Pch FET Control Note ILIM 53 - SW Regulator Current Sense V10FB 54 - SW Regulator Output Monitor Note See section 3.10 for important information about the selection of FET. R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 6 of 41 μPD720210 2.2 2. PIN FUNCTION Analog Interface Pin Name I/O Type Pin No. Function Reference Voltage Input for USB 2.0 RREF must be connected to a 1.6 kΩ resistor with a tolerance of RREF 72 +/- 1%. - It is strongly recommended to use a single resistor for 1.6 kΩ, versus the combined resistance with multiple resistors to achieve this value and tolerance. 2.3 System Clock Pin Name I/O Type Pin No. Function External Oscillator Input XT1 74 IN Connect to 24 MHz crystal. This pin can be a 3.3 V Oscillator input as well. External Oscillator Output XT2 75 OUT Connect to 24 MHz crystal When using single-ended clock input to XT1, this pin should be left open. R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 7 of 41 μPD720210 2.4 2. PIN FUNCTION System Interface Pins Pin No. Pin Name I/O Type Active Level Function SUSPEND Output or CLKOUT depending on pin strap setting of SPICSB and OCI1B. SUSPEND is Suspend state output 1: in suspend state 0: not in suspend state [Note] SUSPEND/NRDCLKO output level is Hi-z till this pin function is configured as SUSPEND output or clock output for non-removable device SPICSB OCI1B Pin Function Low NRDCLKO Low High SUSPEND Depends on Serial ROM High X setting SUSPEND/NRDCLKO 1 OUT High/NA VBUSM 43 IN High BUSSEL 44 IN N/A LED1B/SUSPEND 37 OUT Low Upstream Port VBUS Monitor Divide VBUS to 3.3V and connect to VBUSM Power Mode Select Input 0: Bus-power setting 1: Self-power setting When the external ROM is not used (SPICSB is low), LED1B/SUSPEND is used as LED function for LED1B pin for port1 with the following pin strap settings. When the external ROM is used (SPICSB is high) and SUSPEND function is enabled in the ROM Writing Tool, LED1B/SUSPEND is used as SUSPEND function. If the SUSPEND function is not enabled, this pin is not functional (Hi-Z). [Function] LED1B is LED control output signal to indicate port enable. Note that μPD720210 supports only Green Color of port indicator. 0: Port is enabled Hi-Z: Port is disabled Suspend state is shown by the following pin level. 1: in suspend state 0: not in suspend state SPICSB Low Low SPISCK/ LED4B High Others SPISO/ LED3B High SPISI/ LED2B High LED1B/ SUSPEND High High Low X X X Low High X X X X Pin Function LED1B Reserved (Hi-Z) Reserved (Hi-Z) SUSPEND or Hi-Z [Pin strapping option] This pin is used for pin strap option to select the below functions. Refer to μPD720210 User’s Manual (R19UH0093E) for the following setting - LED function (Chapter 5.1.2) - Battery Charging mode (Chapter 5.1.6) - Address length of external ROM (Chapter 5.1.8) RESETB 2 R19DS0070EJ0200 Rev.2.00 May 26, 2014 IN Low Chip Reset Input Page 8 of 41 μPD720210 2.5 2. PIN FUNCTION USB Port Control Pins Pin Name I/O Type Pin No. Active Level OCI1B 45 IN Low OCI2B, OCI3B, OCI4B 55, 57, 59 IN Low PPON1B/NRDRSTB 46 I/O Low Function [Function] Over Current Input 0: Over-current condition is detected. 1: Non over-current condition is detected. [Pin strapping option] OCI1B Pin Function Removable device setting High and Over current input. Low Non-Removable setting. This pin is used to select non-removable setting. [Function] Over Current Input 0: Over-current condition is detected. 1: Non over-current condition is detected. [Pin strapping option] OCIXB Pin Function Removable device setting High and Over Current Input. Low Non-Removable setting. This pin is used to select non-removable setting. [Function] Port Power Control or NRDRSTB (Non-Removable Device Reset) depending on pin strap setting of this pin. PPON1B/NRDRSTB Pin Function High PPON1B Low NRDRSTB PPON1B is a Port Power Control signal 0: Power supply for VBUS is on. 1: Power supply for VBUS is off. NRDRSTB is a reset signal for Non-Removable device. [Function] This pin is a Port Power Control signal. 0: Power supply for VBUS is on. 1: Power supply for VBUS is off. PPON2B 56 R19DS0070EJ0200 Rev.2.00 May 26, 2014 I/O Low [Pin strapping option] This pin is used for pin strapping option: Gang/Individual Power Control of all ports. PPON2B Gang/Individual Mode High Individual Low Gang Page 9 of 41 μPD720210 2. PIN FUNCTION Pin Name PPON3B, PPON4B 2.6 I/O Type Pin No. 58, 60 I/O Active Level Low Function [Function] These pins are a Port Power Control signal. 0: Power supply for VBUS is on. 1: Power supply for VBUS is off. [Pin strapping option] These pins are used for pin strapping options to select Number of ports. PPON4B PPON3B Number of ports Low Low 2 ports setting Port 3 & 4 are not used. Low High 3 ports setting Port 4 is not used High Low Prohibit setting High High All ports are used USB Data Pins Pin Name I/O Type Pin No. Function U3TXDN1, U3TXDN2, 4, 13, 21, U3TXDN3, 30 OUT USB 3.0 Downstream Transmit data D- signal for SuperSpeed OUT USB 3.0 Upstream Transmit data D- signal for SuperSpeed OUT USB 3.0 Downstream Transmit data D+ signal for SuperSpeed OUT USB 3.0 Upstream Transmit data D+ signal for SuperSpeed IN USB 3.0 Downstream Receive data D- signal for SuperSpeed IN USB 3.0 Upstream Receive data D- signal for SuperSpeed IN USB 3.0 Downstream Receive data D+ signal for SuperSpeed IN USB 3.0 Upstream Receive data D+ signal for SuperSpeed I/O USB 2.0 Downstream D- signal for High-/Full-/Low-speed I/O USB 2.0 Upstream D- signal for High-/Full-/Low-speed I/O USB 2.0 Downstream D+ signal for High-/Full-/Low-speed I/O USB 2.0 Upstream D+ signal for High-/Full-/Low-speed U3TXDN4 U3TXDNU 65 U3TXDP1, U3TXDP2, 3, 12, 20, U3TXDP3, 29 U3TXDP4 U3TXDPU 66 U3RXDN1, U3RXDN2, 7, 16, 24, U3RXDN3, 33 U3RXDN4 U3RXDNU 68 U3RXDP1, U3RXDP2, 6, 15, 23, U3RXDP3, 32 U3RXDP4 U3RXDPU 69 U2DM1, U2DM2, 10, 19, 27, U2DM3, U2DM4 36 U2DMU 63 U2DP1, U2DP2, 9, 18, 26, U2DP3, U2DP4 35 U2DPU 62 R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 10 of 41 μPD720210 2.7 2. PIN FUNCTION SPI Interface Pin Name Pin No. I/O Type Active Level Function [Function] External serial ROM Clock Output or LED output, depending on pin strap setting. SPISCK/LED4B 41 I/O N/A [Pin strapping option] This pin is used for pin strapping option to select the below functions. Refer to μPD720210 User’s Manual (R19UH0093E) for the following setting - LED function (Refer to Chapter 5.1.2) - Battery Charging mode (Refer to Chapter 5.1.6) [Function] External serial ROM Chip Select SPICSB 38 I/O Low [Pin strapping option] This pin is used for pin strap option to select the below functions. Refer to μPD720210 User’s Manual (R19UH0093E) for the following setting - External SPI ROM (Refer to Chapter 5.1.1) - LED function (Refer to Chapter 5.1.2) - Address length of external ROM (Refer to Chapter 5.1.8) [Function] External serial ROM Data Input (to be connected to Serial Data Output pin of the external ROM) or LED output, depending on pin strap setting. SPISO/LED3B 40 I/O N/A [Pin strapping option] This pin is used for pin strap option to select the below functions. Refer to μPD720210 User’s Manual (R19UH0093E) for the following setting - LED function (Refer to Chapter 5.1.2) - Battery Charging mode (Refer to Chapter 5.1.6) - Address length of external ROM (Refer to Chapter 5.1.8) [Function] External serial ROM Data Output (to be connected to Serial Data input pin of the external ROM) or LED output, depending on pin strap setting. SPISI/LED2B 39 R19DS0070EJ0200 Rev.2.00 May 26, 2014 I/O N/A [Pin strapping option] This pin is used for pin strap option to select the below functions. Refer to μPD720210 User’s Manual (R19UH0093E) for the following setting - LED function (Refer to Chapter 5.1.2) - Battery Charging mode (Refer to Chapter 5.1.6) - Address length of external ROM (Refer to Chapter 5.1.8) Page 11 of 41 μPD720210 2.8 2. PIN FUNCTION Test Pin Pin Name IC(L) I/O Type Pin No. 73 R19DS0070EJ0200 Rev.2.00 May 26, 2014 IN Active Level High Function Test Pin to be connected to GND Page 12 of 41 μPD720210 3. ELECTRICAL SPECIFICATIONS 3. ELECTRICAL SPECIFICATIONS 3.1 Buffer List • 3.3 V input buffer IC(L) • 3.3 V input Schmitt buffer RESETB, OCI2B, OCI3B, OCI4B • 3.3 V IOLH = 4 mA output buffer SUSPEND/NRDCLKO, SPICSB, PPON1B/NRDRSTB, PPON2B, PPON3B, PPON4B • 3.3 V IOLH = 12 mA output buffer LED1B/SUSPEND, SPISI/LED2B, SPISCK/LED4B • 3.3 V IOL = 12 mA bi-directional buffer SPISO/LED3B • 5 V input Schmitt buffer VBUSM, BUSSEL, OCI1B • 3.3 V oscillator interface XT1, XT2 • USB Classic interface U2DP(4:1, U), U2DM(4:1, U) • USB SuperSpeed Serdes (Serializer-Deserializer) U3TXDP(4:1, U), U3TXDN(4:1, U), U3RXDP(4:1, U), U3RXDN(4:1, U) • LDO Interface V33OUT, V50IN • Switching Regulator Interface AVDD33R, PGDRV, NGDRV, ILIM, V10FB R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 13 of 41 μPD720210 3.2 3. ELECTRICAL SPECIFICATIONS Terminology Table 3-1. Terms Used in Absolute Maximum Ratings Parameter Symbol Meaning Power supply voltage VDD33, VDD10, AVDD33 Indicates the voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. Input voltage VI Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Output voltage VO Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Output current IO Indicates absolute tolerance values for DC current to prevent damage or reduced reliability when current flows out of or into output pin. Storage temperature Tstg Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current is applied to the device. Table 3-2. Terms Used in Recommended Operating Range Parameter Symbol Meaning Power supply voltage VDD33, VDD10, AVDD33 Indicates the voltage range for normal logic operations occur when GND = 0 V. High-level input voltage VIH Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the “Min.” value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the “Max.” value is applied, the input voltage is guaranteed as low level voltage. Input rise time Tri Indicates the limit value for the time period when an input voltage applied to the input pins of the device rises from 10% to 90%. Input fall time Tfi Indicates the limit value for the time period when an input voltage applied to the input pins of the device falls from 90% to 10%. Operating temperature TA Indicates the ambient temperature range for normal logic operations. Table 3-3. Term Used in DC Characteristics Parameter Symbol Meaning Off-state output leakage current IOZ Indicates the current that flows from the power supply pins when the rated power supply voltage is applied whena 3-state output has high impedance. Input leakage current II Indicates the current that flows when the input voltage is supplied to the input pin. R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 14 of 41 μPD720210 3.3 3. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Table 3-4. Parameter Absolute Maximum Ratings Symbol Power supply voltage Condition Rating Units VDD33, AVDD33 −0.5 to +4.6 V VDD10 −0.5 to +1.4 V V50IN 5.5 V Input voltage, 3.3 V buffer VI VI < VDD33 + 0.5 V −0.5 to +4.6 V Output voltage, 3.3 V buffer VO VO 0 during Reset of Power down ZRX-HIGH-IMP-DC-POS 25k LFPS Detect Threshold VRX-LFPS-DET-DIFF-p-p 100 Ω 300 mV Max Units Table 3-18. Receiver Informative Electrical Parameters Parameter Symbol Min Differential Rx peak-to-peak voltage VRX-DIFF-PP-POST-EQ Max Rx inherent timing error TRX-Tj 0.45 UI Max Rx inherent deterministic timing error TRX-DJ-DD 0.285 UI Rx input capacitance for return loss CRX-PARASITIC 1.1 pF Rx AC common mode voltage VRX-CM-AC-P 150 mVPeak Rx AC common mode voltage during the U1 to U0 transition VRX-CM-DC-ACTIVE-IDLE- 200 mVPeak R19DS0070EJ0200 Rev.2.00 May 26, 2014 30 mV DELTA-P Page 26 of 41 μPD720210 3.8.5 3. ELECTRICAL SPECIFICATIONS USB2.0 Interface Table 3-19. USB Interface (1 of 4) Parameter Symbol Conditions Min. Max. Unit Low-speed Electrical Characteristics Rise time (10% to 90%) tLR CL = 200 pF to 600 pF 75 300 ns Fall time (90% to 10%) tLF CL = 200 pF to 600 pF 75 300 ns 80 125 % 1.49925 1.50075 Mbps Note Differential rise and fall time matching tLRFM (tLR/tLF) Low-speed data rate tLDRATHS Average bit rate Downstream facing port source jitter total (including frequency tolerance) (Figure 319): To next transition tDDJ1 −25 +25 ns For paired transitions tDDJ2 −14 +14 ns To next transition tUJR1 −152 +152 ns For paired transitions tUJR2 −200 +200 ns Source SE0 interval of EOP (Figure 3-18) tLEOPT 1.25 1.5 μs Receiver SE0 interval of EOP (Figure 3-18) tLEOPR 670 Downstream facing port differential receiver jitter total (including frequency tolerance) (Figure 3-19): ns Width of SE0 interval during differential transition tLST 210 ns Hub differential data delay (Figure 3-15) tLHDD 300 ns Hub differential driver jitter (including cable) (Figure 3-15): Downstream facing port To next transition tLDHJ1 −45 +45 ns For paired transitions tLDHJ2 −15 +15 ns To next transition tLUHJ1 −45 +45 ns For paired transitions tLUHJ2 −45 +45 ns tLSOP −60 +60 ns tLEOPD 0 200 ns tLHESK −300 +300 ns Upstream facing port Data bit width distortion after SOP (Figure 3-15) Hub EOP delay relative to tHDD (Figure 316) Hub EOP output width skew (Figure 3-16) Full-speed Electrical Characteristics Rise time (10% to 90%) tFR CL = 50 pF, RS = 36 Ω 4 20 ns Fall time (90% to 10%) tFF CL = 50 pF, RS = 36 Ω 4 20 ns Differential rise and fall time matching tFRFM (tFR/tFF) 90 111.11 % Full-speed data rate tFDRATHS Average bit rate 11.9940 12.0060 Mbps Frame interval tFRAME 0.9995 1.0005 ms Note Excluding the first transition from the Idle state. R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 27 of 41 μPD720210 3. ELECTRICAL SPECIFICATIONS Table 3-20. USB Interface (2 of 4) Parameter Symbol Conditions Min. Max. Unit 42 ns Full-speed Electrical Characteristics (Continued) Consecutive frame interval jitter tRFI Source jitter total (including frequency No clock adjustment Note tolerance) (Figure 3-17): To next transition tDJ1 −3.5 +3.5 ns For paired transitions tDJ2 −4.0 +4.0 ns −2 +5 ns Source jitter for differential transition to SE0 tFDEOP transition (Figure 3-18) Receiver jitter (Figure 3-19): To Next Transition tJR1 −18.5 +18.5 ns For Paired Transitions tJR2 −9 +9 ns Source SE0 interval of EOP (Figure 3-18) tFEOPT 160 175 ns Receiver SE0 interval of EOP (Figure 3-18) tFEOPR 82 Width of SE0 interval during differential tFST 14 ns (with cable) tHDD1 70 ns (without cable) tHDD2 44 ns ns transition Hub differential data delay (Figure 3-15) Hub differential driver jitter (including cable) (Figure 3-15): To next transition tHDJ1 −3 +3 ns For paired transitions tHDJ2 −1 +1 ns tFSOP −5 +5 ns Hub EOP delay relative to tHDD (Figure 3-16) tFEOPD 0 15 ns Hub EOP output width skew (Figure 3-16) tFHESK −15 +15 ns Rise time (10% to 90%) tHSR 500 ps Fall time (90% to 10%) tHSF 500 ps Driver waveform See Figure 3-13. High-speed data rate tHSDRAT 479.760 480.240 Mbps Microframe interval tHSFRAM 124.9375 125.0625 μs Consecutive microframe interval difference tHSRFI Data bit width distortion after SOP (Figure 3-15) High-speed Electrical Characteristics Data source jitter See Figure 3-13. Receiver jitter tolerance See Figure 3-4. Hub data delay (without cable) tHSHDD Hub data jitter See Figure 3-4, Figure 3-13. Hub delay variation range tHSHDV 4 HHigh- Bit speed times 36 High- Bit speed+4 ns times 5 HHigh- Bit speed times Note Excluding the first transition from the Idle state. R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 28 of 41 μPD720210 3. ELECTRICAL SPECIFICATIONS Table 3-21. USB Interface (3 of 4) Parameter Symbol Conditions Min. Max. Unit Hub Event Timings Time to detect a downstream facing port tDCNN connect event (Figure 3-21): Awake hub 2.5 2000 Suspended hub 2.5 12000 μs μs tDDIS 2.0 2.5 μs tDRSMDN 20 Time to detect a disconnect event at a hub’s downstream facing port (Figure 3-20) Duration of driving resume to a downstream ms port (only from a controlling hub) Time from detecting downstream resume to tURSM 1.0 ms 10 20 ms rebroadcast Duration of driving reset to a downstream tDRST facing port (Figure 3-22) Only for a SetPortFeature (PORT_RESET) request Time to detect a long K from upstream tURLK 2.5 100 μs Time to detect a long SE0 from upstream tURLSE0 2.5 10000 μs Duration of repeating SE0 upstream (for tURPSE0 23 FS Bit Low-/Full-speed repeater) Inter-packet delay (for High-speed) of times tHSIPDSD 88 Bit packets traveling in same direction Inter-packet delay (for High-speed) of times tHSIPDOD 8 Bit packets traveling in opposite direction Inter-packet delay for device/root hub times tHSRSPIPD1 192 response with detachable cable for High- Bit times speed Time of which a Chirp J or Chirp K must be tFILT μs 2.5 continuously detected (filtered) by hub or device during Reset handshake Time after end of device Chirp K by which tWTDCH 100 μs hub must start driving first Chirp K in the hub’s chirp sequence Time for which each individual Chirp J or tDCHBIT 40 60 μs tDCHSE0 100 500 μs tSIGATT 100 ms tATTDB 100 ms 1 s Chirp K in the chirp sequence is driven downstream by hub during reset Time before end of reset by which a hub must end its downstream chirp sequence Time from internal power good to device pulling D+ beyond VIHZ (Figure 3-22) Debounce interval provided by USB system software after attach (Figure 3-22) Maximum duration of suspend averaging tSUSAVGI interval Period of idle bus before device can initiate tWTRSM 5 tDRSMUP 1 ms resume Duration of driving resume upstream R19DS0070EJ0200 Rev.2.00 May 26, 2014 15 ms Page 29 of 41 μPD720210 3. ELECTRICAL SPECIFICATIONS Table 3-22. USB Interface (4 of 4) Parameter Symbol Conditions Min. Max. Unit Hub Event Timings (Continued) Resume recovery time tRSMRCY Remote-wakeup is 10 ms enabled Time to detect a reset from upstream for tDETRST 2.5 10000 μs 10 ms non High-speed capable devices Reset recovery time (Figure 3-22) tRSTRCY Inter-packet delay for Full-speed tIPD 2 Bit times Inter-packet delay for device response with tRSPIPD1 6.5 detachable cable for Full-speed Bit times SetAddress() completion time tDSETADDR 50 ms Time to complete standard request with no tDRQCMPLTND 50 ms tDRETDATA1 500 ms tDRETDATAN 50 ms data Time to deliver first and subsequent (except last) data for standard request Time to deliver last data for standard request Time for which a suspended hub will see a μs tFILTSE0 2.5 tWTRSTFS 2.5 3000 ms tWTREV 3.0 3.125 ms tWTRSTHS 100 875 ms tUCH 1.0 continuous SE0 on upstream before beginning the High-speed detection handshake Time a hub operating in non-suspended Full-speed will wait after start of SE0 on upstream before beginning the High-speed detection handshake Time a hub operating in High-speed will wait after start of SE0 on upstream before reverting to Full-speed Time a hub will wait after reverting to Fullspeed before sampling the bus state on upstream and beginning the High-speed will wait after start of SE0 on upstream before reverting to Full-speed Minimum duration of a Chirp K on upstream ms from a hub within the reset protocol Time after start of SE0 on upstream by tUCHEND 7.0 ms tWTHS 500 μs 2.5 ms which a hub will complete its Chirp K within the reset protocol Time between detection of downstream chip and entering High-speed state Time after end of upstream Chirp at which tWTFS 1.0 hub reverts to Full-speed default state if no downstream Chirp is detected R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 30 of 41 μPD720210 3. ELECTRICAL SPECIFICATIONS Figure 3-13. Transmit Waveform for Transceiver at DP/DM +400 mV Differential Level 1 Point 3 Point 4 Point 1 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 3-14. Transmitter Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device VBUS D+ DGND 15.8 Ω 143 Ω R19DS0070EJ0200 Rev.2.00 May 26, 2014 50 Ω Coax 50 Ω Coax + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 143 Ω Page 31 of 41 μPD720210 3. ELECTRICAL SPECIFICATIONS Figure 3-15. Hub Differential Delay, Differential Jitter, and SOP Distortion Upstream End of Cable Crossover Point Upstream Port of Hub 50% Point of Initial Swing VSS VSS Downstream Port of Hub Hub Delay Downstream tHDD1 VSS 50% Point of Initial Swing Hub Delay Downstream tHDD2 Downstream Port of Hub VSS A. Downstream Hub Delay with Cable B. Downstream Hub Delay without Cable Downstream Port of Hub Crossover Point VSS Upstream Port or End of Cable Hub Delay Upstream tHDD1 tHDD2 VSS Crossover Point C. Upstream Hub Delay with or without Cable Upstream end of cable Upstream port Downstream port Receptacle Plug Host or Hub Hub Function Downstream signaling Upstream signaling D. Measurement Points Hub Differential Jitter: tHDJ1 = tHDDx(J) − tHDDx(K) or tHDDx(K) − tHDDx(J) Consecutive Transitions tHDJ2 = tHDDx(J) − tHDDx(J) or tHDDx(K) − tHDDx(K) Paired Transitions Bit after SOP Width Distortion (same as data jitter for SOP and next J transition): tFSOP = tHDDx(next J) − tHDDx(SOP) Low-speed timings are determined in the same way for: tLHDD, tLDHJ1, tLDJH2, tLUHJ1, tLUJH2, and tLSOP R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 32 of 41 μPD720210 3. ELECTRICAL SPECIFICATIONS Figure 3-16. Hub EOP Delay and EOP Skew Upstream End of Cable 50% Point of Initial Swing Upstream Port of Hub VSS Crossover Point Extended VSS tEOP- tEOP+ tEOP- tEOP+ Downstream Port of Hub Downstream Port of Hub VSS VSS A. Downstream EOP Delay with Cable B. Downstream EOP Delay without Cable Crossover Point Extended Downstream Port of Hub VSS tEOPUpstream Port or End of Cable tEOP+ Crossover Point Extended VSS C. Upstream EOP Delay with or without Cable EOP Delay: tFEOPD = tEOPy − tHDDx (tEOPy means that this equation applies to tEOP- and tEOP+) EOP Skew: tFHESK = tEOP+ − tEOPLow-speed timings are determined in the same way for: tLEOPD and tLHESK R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 33 of 41 μPD720210 3. ELECTRICAL SPECIFICATIONS Figure 3-17. USB Differential Data Jitter for Low-/Full-speed tPERIOD Crossover Points Differential Data Lines Consecutive Transitions N × tPERIOD + txDJ1 Paired Transitions N × tPERIOD + txDJ2 Figure 3-18. USB Differential-to-EOP Transition Skew and EOP Width for Low-/Full-speed tPERIOD Crossover Point Extended Crossover Point Differential Data Lines Diff. Data-toSE0 Skew N × tPERIOD + txDEOP Source EOP Width: tFEOPT tLEOPT Receiver EOP Width: tFEOPR tLEOPR Figure 3-19. USB Receiver Jitter Tolerance for Low-/Full-speed tPERIOD Differential Data Lines txJR txJR1 txJR2 Consecutive Transitions N × tPERIOD + txJR1 Paired Transitions N × tPERIOD + txJR2 R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 34 of 41 μPD720210 3. ELECTRICAL SPECIFICATIONS Figure 3-20. Low-/Full-speed Disconnect Detection D+/D− VIHZ (min) VIL D−/D+ VSS tDDIS Device Disconnected Disconnect Detected Figure 3-21. Full-/High-speed Device Connect Detection D+ VIH D− VSS tDCNN Device Connected Connect Detected Figure 3-22. Power-on and Connection Events Timing Hub port power OK Reset recovery time Attatch detected Hub port power-on ≥ 4.01 V t2SUSP VBUS VIH (min) VIH D+ or D− Δt1 R19DS0070EJ0200 Rev.2.00 May 26, 2014 tSIGATT tATTDB tDRST USB system software reads device speed tRSTRCY Page 35 of 41 μPD720210 3.8.6 3. ELECTRICAL SPECIFICATIONS SPI Type Serial ROM Interface Table 3-23. SPI Type Serial ROM Interface Signals Timing (SPI Mode 0) Parameter Symbol SPISCK/LED4B Clock Frequency Min. Max. Units - 2.0 MHz Chip Select idle time TCSIDEL 500 - ns Chip Select assertion time before clock TCSBFCLK 250 - ns Chip Select deassertion time after clock TCSAFCLK 250 - ns Clock pulses width Low TSCKLOW 250 - ns Clock pulses width high TSCKHIGH 250 - ns SPISI/LED2B validate time from SPISCK/LED4B falling edge TSIVALID - 10 ns SPISI/LED2B hold time from SPISCK/LED4B falling edge TSIHOLD -10 10 ns SPISO/LED3B setup time to SPISCK/LED4B rising edge TSOSU 5 - ns SPISO/LED3B hold time from SPISCK/LED4B rising edge TSOHOLD 5 - ns Figure 3-23. SPI Type Serial ROM Signal Timing TCSIDLE SPICSB (720210 Output) TCSBFCLK TSCKLOW TSCKHIGH TCSAFCLK SPISCK/LED4B (720210 Output) TSIVALID TSIHOLD SPISI/LED2B (720210 Output) TSOSU TSOHOLD SPISO/LED3B (720210 Input) R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 36 of 41 μPD720210 3.9 3. ELECTRICAL SPECIFICATIONS Power Consumption Table 3-24. Parameter Power Consumption of μPD720210 (without on-chip regulators operating) Device connection Power No host Consumption connection Suspend 1 device Condition VDD10 line Hub is not connected to host controller. Hub is connected to host controller both with SuperSpeed and HighSpeed, hub goes into U3 state. 0.1 mA 13.4 0.3 1.5 mA 28.3 23.0 11.8 mA 30.5 24.8 12.3 mA High-speed data transfer on the port. 32.1 54.4 10.9 mA 288.1 1.8 11.0 mA 34.3 73.2 11.1 mA 403.1 1.8 11.0 mA 36.6 91.9 11.3 mA 518.1 1.8 11.0 mA 38.3 110.7 11.6 mA 633.0 1.8 11.0 mA 658.4 103.5 20.8 mA Note Hub is connected to host controller both with SuperSpeed and HighSpeed. Two devices are connected on the ports. High-speed data transfer on the both ports. SuperSpeed transfer on the both ports. Note Hub is connected to host controller both with SuperSpeed and HighSpeed. Three devices are connected on the ports. High-speed data transfer on the three ports. SuperSpeed transfer on the three ports. Note 4 devices 0.1 Full-speed data transfer on the port. SuperSpeed transfer on the port. 3 devices 4.4 Hub is connected to host controller both with SuperSpeed and HighSpeed. Only one device is connected on the port. Low-speed data transfer on the port. 2 devices VDD33 AVDD33 Units line line Hub is connected to host controller both with SuperSpeed and HighSpeed . Four devices are connected on the ports. High-speed data transfer on the four ports. SuperSpeed transfer on the four ports. Note 4 SS hubs Hub is connected to host controller both with with SS and SuperSpeed and HighSpeed . Four HS devices SuperSpeed hubs are connected on all ports under SS and HS data transfer. Typical condition (TA = 25°C, VDD33 = 3.3 V, VDD10 = 1.05 V) Note U1/U2 is enabled in this condition. R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 37 of 41 μPD720210 3. ELECTRICAL SPECIFICATIONS Table 3-25. Parameter Power Consumption of μPD720210 (with on-chip regulators operating) Total Power Units 26.3 mW 54.8 mW Low-speed data transfer on the port. 235.5 mW Full-speed data transfer on the port. 245.1 mW High-speed data transfer on the port. 390.7 mW 523.3 mW 488.4 mW 732.5 mW 586.1 mW 920.8 mW 683.9 mW 1169.5 mW 1765.6 mW Device connection Power No host Consumption connection Suspend 1 device Condition Note2 Hub is not connected to host controller. Hub is connected to host controller both with SuperSpeed and HighSpeed, hub goes into U3 state. Hub is connected to host controller both with SuperSpeed and HighSpeed. Only one device is connected on the port. SuperSpeed transfer on the port. 2 devices Note1 Hub is connected to host controller both with SuperSpeed and HighSpeed. Two devices are connected on the ports. High-speed data transfer on the both ports. SuperSpeed transfer on the both ports. Note1 3 devices Hub is connected to host controller both with SuperSpeed and HighSpeed. Three devices are connected on the ports. High-speed data transfer on the three ports. SuperSpeed transfer on the three ports. Note1 4 devices Hub is connected to host controller both with SuperSpeed and HighSpeed . Four devices are connected on the ports. High-speed data transfer on the four ports. SuperSpeed transfer on the four ports. 4 SS hubs with SS and HS devices Note1 Hub is connected to host controller both with SuperSpeed and HighSpeed . Four SuperSpeed hubs are connected on all ports under SS and HS data transfer. Typical condition (TA = 25°C, VDD33 = 3.3 V, VDD10 = 1.05 V) Notes 1. U1/U2 is enabled in this condition. 2. The values on this page do NOT represent the chip’s pure power consumption. The values include power loss by external components, too. Remark Input voltage for on-chip regulators is 5 V. R19DS0070EJ0200 Rev.2.00 May 26, 2014 Page 38 of 41 μPD720210 3.10 3. ELECTRICAL SPECIFICATIONS Recommended FET for Internal Switching Regulator (5 V  1.05 V) Figure 3-24. Internal Switching Regulator Connection 5V uPD720210 68Ω 56Ω 4.7uF 2 4 3 6 5 1 PGDRV NGDRV 1.05V 4.7uH QS6M3 ROHM 22uF 470 KΩ ILIM V10FB It is necessary to use the correct Field Effect Transistor (FET) for the part of this switching regulator. The requirements for this FET are as follows. 1) 2) 3) 4) 5) 6) 7) Pch Vt: