Data Sheet
PD720211
ASSP (Two-port USB3.0 Hub Controller)
R19DS0080EJ0400
Rev.4.00
Sep 16, 2015
1. OVERVIEW
The PD720211 is a USB 3.0 hub controller that complies with the Universal Serial Bus (USB) Specification
Revision 3.0 and operates at up to 5 Gbps. The device incorporates Renesas’ market proven design
expertise in USB 3.0 interface technologies and market proven USB 2.0 hub core. The device is fully
compatible with all prior versions of USB spec and 100% compatible with Renesas’ industry standard USB 3.0
host controller. It comes in a small 56-pin QFN package and integrates several commonly required external
components, making it ideally suited for applications with limited PCB space. In addition, the PD720211
incorporates Renesas’ low-power technologies and supports all mainstream battery charging specifications.
1.1
Features
Compliant with Universal Serial Bus 3.0 Specification Revision 1.0, which is released by USB
Implementers Forum, Inc
Supports the following speed data rates: Low-speed (1.5 Mbps) / Full-speed (12 Mbps) /
High-speed (480 Mbps) / Superspeed (5 Gbps)
Supports USB 3.0 link power management (U0/U1/U2/U3)
Supports USB 2.0 link power management (LPM: L0/L1/L2/L3)
Supports two downstream ports
Supports all VBUS control options
Individual or global over-current detection
Individual or ganged power control
Supports USB 3.0/2.0 Compound (non-removable) devices by I/O pin configuration
Supports clock output (24/12 MHz) for Compound (non-removal) device on downstream ports
Supports Energy Star and EuP specifications for low-power PC peripheral system
Single 3.3 V Power Supply
On chip Switching Regulator for 1.05 V from 3.3 V input
System clock: 24 MHz Crystal or Oscillator
Supports USB Battery Charging Specification Revision 1.2 and other portable devices
DCP mode of BC 1.2
CDP mode of BC 1.2
ACA-Dock function of BC 1.2
China Mobile Phone Chargers
EU Mobile Phone Chargers
Apple iOS products
Other major portable devices
Supports SPI ROM for optional firmware and parameter data
UUID supported with ROM Writing Tools
Small Footprint
Small and low pin count package with simple pin assignment for PCB layout
Integration of many peripheral components
Direct routing of all USB signal traces to connector pins using one layer of the PCB
Self/Bus-Powered modes can be set by pin strapping
Integrated termination resistors for USB
Provides SUSPEND status output
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 1 of 40
PD720211
1.2
1. OVERVIEW
Applications
Standalone Hub, Monitor-Hub, Docking Station, Integrated Hub, etc.
1.3
Ordering Information
Part Number
PD720211K8-611-BAL-A
PD720211K8-711-BAL-A
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Package
56-pin QFN (8 8)
56-pin QFN (8 8)
Operating Temperature
0 to 70C
40 to 70C
Remark
Lead-free product
Lead-free product
Page 2 of 40
PD720211
1.4
1. OVERVIEW
Block Diagram
Figure 1-1. PD720211 Block Diagram
D/C/L
SW-Regulator
(VDD33
VDD10)
VDD10
VBUS
Switch
HS/FS/LS
US Port
Control
VBUS
VBUS Monitor
HS/FS/LS
DS Port
Control
HS/FS/LS PHY
SS-PHY
USB
Connector
VBUS
Control
HS/FS/LS PHY
USB
Connector
SS-PHY
OSC
24MHz
CLKOUT
12/24MHz
SPI
ROM
HS/FS/LS
Hub Core
SPI
I/F
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
SS
US Port
Control
SS
Hub Core
SS
DS Port
Control
VBUS
Switch
HS/FS/LS PHY
SS-PHY
USB
Connector
Page 3 of 40
PD720211
1. OVERVIEW
Table 1-1.
Block Name
Terminology
Description
SS PHY
SuperSpeed Tx/Rx
HS/FS/LS PHY
High-/Full-/Low-speed transceiver
VBUS Monitor
Monitors the VBUS voltage level of the upstream port.
SS US Port
Control
Upstream port control logic for SuperSpeed
HS/FS/LS US
Port Control
Upstream port control logic for High-/Full-/Low-speed
SS Hub Core
Central control logic for SS-Hub.
HS/FS/LS Hub
Core
Central control logic for HS/FS/LS-Hub.
SS DS Port
Control
Downstream port control logic for SuperSpeed
HS/FS/LS DS
Port Control
Downstream port control logic for HS/FS/LS
VBUS Control
Controls all the external port power switches
SPI Interface
Connected to external serial ROM which can hold the optional firmware and hub settings
SW-Regulator
Switching regulator control logic to output 1.05 V power from 3.3 V input.
D/C/L
D: Schottky Barrier Diode, C: Capacitor 22 F, L: Inductor 4.7 H
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 4 of 40
PD720211
1.5
1. OVERVIEW
Pin Configuration
56-pin QFN (8 8)
PD720211K8-611-BAL-A
PD720211K8-711-BAL-A
43 U3TXDP2
44 U3TXDN2
45 VDD10
46 U3RXDP2
47 U3RXDN2
48 VDD33
49 U2DP2
50 U2DM2
51 VDD10
52 VBUSM
54 OCI1B
55 PPON1B/NRDRSTB
56 VDD33
53 LPWRM
Pin Configuration of PD720211 (Top View)
Figure 1-2.
SPICSB 1
42 U2DM1
SPISI/LED2B 2
41 U2DP1
SPISO 3
40 VDD33
SPISCK 4
39 U3RXDN1
VDD10 5
38 U3RXDP1
NC 6
37 VDD10
LX1 7
GND
AVDD33IN1 8
36 U3TXDN1
35 U3TXDP1
AVDD33IN2 9
34 VDD10
FB 10
33 RESETB
NC 11
32 SUSPEND/NRDCLKO
NC 12
31 VDD33
OCI2B 13
30 XT2
PPON2B 14
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
VDD10 28
IC(L) 27
RREF 26
AVDD33 25
U3RXDPU 24
U3RXDNU 23
VDD10 22
U3TXDPU 21
U3TXDNU 20
VDD10 19
U2DMU 18
U2DPU 17
VDD33 16
LED1B/SUSPEND 15
29 XT1
Page 5 of 40
PD720211
2. PIN FUNCTION
2. PIN FUNCTION
This section describes each pin function.
Strapping information in the tables shows how the pin can be used to configure the functional settings of this
controller when the pin is pulled up/down, as detected at the end of chip reset.
2.1
Power Supply
Pin Name
AVDD33
AVDD33IN1
8
Power
SW Regulator 3.3 V Input
AVDD33IN2
9
Power
SW Regulator 3.3 V Input
LX1
7
-
SW Regulator 1.05 V Output
FB
10
-
SW Regulator Output Monitor
VDD33
Power
1.05 V power supply for Core Logic
Power
3.3 V power supply for IO buffer
Power
3.3 V power supply for Analog circuit
Analog Interface
Pin Name
RREF
2.3
Function
5, 19, 22,
28, 34,
37, 45,
51
16, 31,
40, 48,
56
25
VDD10
2.2
I/O
Type
Pin No.
I/O
Type
Pin No.
26
Function
Reference Voltage Input for USB 2.0
RREF must be connected to a 1.6 k resistor with a tolerance
of +/- 1%.
It is strongly recommended to use a single resistor of 1.6 k,
versus the combined resistance with multiple resistors to
achieve the value and tolerance.
-
System Clock
Pin Name
I/O
Type
Pin No.
XT1
29
IN
XT2
30
OUT
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Function
External Oscillator Input
Connect to 24 MHz crystal.
Alternatively, this pin can accept a 3.3 V Oscillator input.
External Oscillator Output
Connect to 24 MHz crystal. When using single-ended clock
input to XT1, this pin should be left open.
Page 6 of 40
PD720211
2.4
2. PIN FUNCTION
System Interface Pins
Pin Name
Pin
No.
I/O
Type
Active
Level
Function
SUSPEND/NRDCLKO
32
OUT
High/NA
SUSPEND Output or CLKOUT depending on pin strap setting
of SPICSB and OCI1B.
SUSPEND is Suspend state output.
1: in suspend state.
0: not in suspend state.
When ACA-Dock function is selected, this pin is used for ACADock function.
This signal is the control of VBUS. (Low active, Open-drain
output)
See User’s Manual for additional details about ACA-Dock
function.
[Note]
SUSPEND/NRDCLKO output level is Hi-Z till this pin function
is configured as SUSPEND output or clock output for nonremovable device.
LED1B/
Pin Function
SPICSB
OCI1B
SUSPEND
Low
X
NRDCLKO
Low
High
X
SUSPEND
ACA-Docking function
Low
X
Low
for VBUS control
Depends on Serial
ROM setting
(Set NRDCLKO or
High
X
X
SUSPEND.Cannot
set ACA-Docking
function)
VBUSM
52
IN
High
Upstream Port VBUS Monitor
Divide VBUS to 3.3 V and connect to VBUSM
N/A
Local power monitor input
0: Local power is lost.
1: Local power is supplied.
This value is set to Self Powered field of Device Status
dynamically.
LPWRM
53
IN
When the external ROM is used (SPICSB is high) and
SUSPEND function is enabled in the ROM Writing Tool,
LED1B/SUSPEND is used as SUSPEND function. If the
SUSPEND function is not enabled, this pin is not functional
(Hi-Z).
When ACA-Dock function is selected, this pin is used for ACADock function.
This signal is the control of RID. (High active, Push-pull output)
See User’s Manual for additional details about ACA-Dock
function.
LED1B/SUSPEND
RESETB
15
33
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
I/O
IN
Low
Low
[Function]
Suspend state is shown by the following pin level.
1: in suspend state.
0: not in suspend state.
LED1B/
SUSPEND
High
Low
SPICSB
Low
Low
SPISI/
LED2B
Low
X
High
High
X
Pin Function
Reserved
ACA-Docking function
for RID control
SUSPEND or Hi-Z
Chip Reset Input.
Page 7 of 40
PD720211
2.5
2. PIN FUNCTION
USB Port Control Pins
Pin Name
I/O
Type
Pin No.
Active
Level
Function
[Function]
Over Current Input.
0: Over-current condition is detected.
1: Non over-current condition is detected.
OCI1B
54
IN
Low
[Pin strapping option]
OCI1B
Pin Function
Removable device setting
High
and Over current input.
Low
Non-Removable setting.
This pin is used to select non-removable
setting.
[Function]
Over Current Input
0: Over-current condition is detected.
1: Non over-current condition is detected.
OCI2B
13
IN
Low
PPON1B/NRDRSTB
55
I/O
Low
[Pin strapping option]
OCI2B
Pin Function
Removable device setting
High
and Over Current Input.
Low
Non-Removable setting.
This pin is used to select non-removable
setting.
[Function]
Port Power Control or NRDRSTB (NonRemovable Device Reset) depending on
pin strap setting of this pin.
PPON1B/NRDRSTB Pin Function
High
PPON1B
Low
NRDRSTB
PPON1B is a Port Power Control signal
0: Power supply for VBUS is on.
1: Power supply for VBUS is off.
NRDRSTB is a reset signal for NonRemovable device.
[Pin strapping option]
This pin is used for pin strapping options.
[Function]
PPON2B is a Port Power Control signal.
0: Power supply for VBUS is on.
1: Power supply for VBUS is off.
PPON2B
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
14
I/O
Low
[Pin strapping option]
This pin is used for pin strapping option:
Gang/Individual Power Control of all ports.
PPON2B
Gang/Individual Mode
High
Individual
Low
Gang
Page 8 of 40
PD720211
2.6
2. PIN FUNCTION
USB Data Pins
Pin Name
U3TXDN1,
U3TXDN2
U3TXDNU
U3TXDP1,
U3TXDP2
U3TXDPU
U3RXDN1,
U3RXDN2
U3RXDNU
U3RXDP1,
U3RXDP2
U3RXDPU
U2DM1,
U2DM2
U2DMU
U2DP1,
U2DP2
U2DPU
I/O
Type
Pin No.
Function
36, 44
OUT
USB 3.0 Downstream Transmit data D- signal for SuperSpeed
20
OUT
USB 3.0 Upstream Transmit data D- signal for SuperSpeed
35, 43
OUT
USB 3.0 Downstream Transmit data D+ signal for SuperSpeed
21
OUT
USB 3.0 Upstream Transmit data D+ signal for SuperSpeed
39, 47
IN
USB 3.0 Downstream Receive data D- signal for SuperSpeed
23
IN
USB 3.0 Upstream Receive data D- signal for SuperSpeed
38, 46
IN
USB 3.0 Downstream Receive data D+ signal for SuperSpeed
24
IN
USB 3.0 Upstream Receive data D+ signal for SuperSpeed
42, 50
I/O
USB 2.0 Downstream D- signal for High-/Full-/Low-speed
18
I/O
USB 2.0 Upstream D- signal for High-/Full-/Low-speed
41, 49
I/O
USB 2.0 Downstream D+ signal for High-/Full-/Low-speed
17
I/O
USB 2.0 Upstream D+ signal for High-/Full-/Low-speed
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 9 of 40
PD720211
2.7
2. PIN FUNCTION
SPI Interface
Pin Name
Pin
No.
I/O
Type
Active
Level
Function
[Function]
External serial ROM Clock Output
SPISCK
4
I/O
N/A
[Pin strapping option]
This pin is used for pin strapping option to select U1/U2
function.
SPICSB
SPISCK
U1/U2 Function
Depends on Serial ROM
High
X
Setting
High
Enable U1/U2 function
Low
Low
Disable U1/U2 function
[Function]
External serial ROM Chip Select.
SPICSB
Pin Function
High
Use External ROM
Low
Not use External ROM
SPICSB
1
I/O
Low
SPISO
3
I/O
N/A
SPISI/LED2B
2
I/O
N/A
[Pin strapping option]
This pin is used for pin strapping option to select whether
external ROM is used.
And, this pin setting also have an impact for U1/U2 function,
LED1B/SUSPEND, SUSPEND/NRDCLKO and
SPISI/LED2B. Moreover, it is necessary to set Pin strapping
as below depending on ROM address bit length.
SPISO SPISI/LED2B LED1B/SUSPEND Function
Others
16bit (1)
Low
High
High
24bit (2)
(1) Only EEPROM is supported.
(2) Only Flash ROM is supported
“Others”: this means SPISO and SPISI/LED2B should set to
different pin setting with 24bit function.
[Function]
External serial ROM Data Input (to be connected to Serial
Data Output pin of the external ROM).
[Pin strapping option]
This pin is used for pin strapping option to select Battery
Charging (BC) mode when not using Serial ROM.
SPISO
SPISI/LED2B BC Mode
High
High
SDP
High
Low
CDP + FVO2 (port2) Note1
Low
High
CDP+ Auto(port2)Note1
Low
Low
CDP + Auto(all ports)Note2
[Function]
External serial ROM Data Output (to be connected to Serial
Data input pin of the external ROM) depending on pin strap
setting of SPICSB.
SPICSB LED1B/SUSPEND SPISI/LED2B Function
High
High
Low
SPISI
High
High
High
SPISI
Low
X
Low
Reserved
[Pin strapping option]
This pin is used for pin strapping options.
Notes 1. Only port2 supports battery charging.
2. All removable ports among available ones support battery charging.
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 10 of 40
PD720211
2.8
2. PIN FUNCTION
Test Pin
Pin Name
I/O
Type
Pin No.
Active
Level
Function
IC(L)
27
IN
High
IC(L) pin to be connected to GND
NC
6, 11, 12
N/A
N/A
NC pin to be open.
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 11 of 40
PD720211
3. ELECTRICAL SPECIFICATIONS
3. ELECTRICAL SPECIFICATIONS
3.1
Buffer List
Pin Name
Buffer Type
XT1
3.3 V oscillator interface
XT2
3.3 V oscillator interface
Strap Pin
SUSPEND : 3.3 V IOLH = 4 mA output buffer
SUSPEND/NRDCLKO
NRDCLKO : 3.3 V IOLH = 4 mA output buffer
ACA Docking function : 3.3 V IOL = 4 mA open drain
buffer
VBUSM
3.3 V input Schmitt buffer (5 V tolerant)
LPWRM
3.3 V input Schmitt buffer (5 V tolerant)
LED1B : 3.3 V IOL = 12 mA open drain buffer (Note2)
LED1B/SUSPEND
SUSPEND : 3.3 V IOL = 12 mA output buffer
Yes (Note1)
ACA Docking function : 3.3 V IOL = 12 mA output buffer
RESETB
3.3 V input Schmitt buffer
OCI1B
3.3 V input Schmitt buffer (5 V tolerant)
Yes (Note1)
OCI2B
3.3 V input Schmitt buffer
Yes (Note1)
PPON1B : 3.3 V IOL = 4 mA open drain buffer
PPON1B/NRDRSTB
Yes (Note1)
NRDRSTB : 3.3 V IOLH = 4 mA output buffer
PPON2B
3.3 V IOL = 4 mA open drain buffer
Yes (Note1)
U3TXDP(2:1, U),U3TXDN(2:1, U)
USB SuperSpeed Serdes (Serializer-Deserializer)
U3RXDP(2:1, U),U3RXDN(2:1, U)
U2DP(2:1, U),U2DM(2:1, U)
USB Classic interface
SPISCK
3.3 V IOL = 12 mA output buffer
Yes (Note1)
SPICSB
3.3 V IOLH = 4 mA output buffer
Yes (Note1)
SPISO
3.3 V input buffer
Yes (Note1)
SPISI : 3.3 V IOL = 12 mA output buffer
SPISI/LED2B
Yes (Note1)
LED2B : 3.3 V IOL = 12 mA open drain buffer (Note2)
IC(L)
3.3 V input buffer
Notes 1. The pins used for pin strap setting are input buffer during asserting RESETB and for 3us after de-asserting
RESETB.
2. LED function is not supported.
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 12 of 40
PD720211
3.2
3. ELECTRICAL SPECIFICATIONS
Terminology
Table 3-1. Terms Used in Absolute Maximum Ratings
Parameter
Symbol
Meaning
Power supply voltage
VDD33,
VDD10,
AVDD33,
AVDD33IN1,
AVDD33IN2
Indicates the voltage range within which damage or reduced
reliability will not result when power is applied to a VDD pin.
Input voltage
VI
Indicates voltage range within which damage or reduced reliability
will not result when power is applied to an input pin.
Output voltage
VO
Indicates voltage range within which damage or reduced reliability
will not result when power is applied to an output pin.
Output current
IO
Indicates absolute tolerance values for DC current to prevent
damage or reduced reliability when current flows out of or into
output pin.
Storage temperature
Tstg
Indicates the element temperature range within which damage or
reduced reliability will not result while no voltage or current is
applied to the device.
Table 3-2. Terms Used in Recommended Operating Range
Parameter
Symbol
Meaning
Power supply voltage
VDD33,
VDD10,
AVDD33,
AVDD33IN1,
AVDD33IN2
Indicates the voltage range for normal logic operations occur when
GND = 0 V.
High-level input voltage
VIH
Low-level input voltage
VIL
Input rise time
Tri
Indicates the voltage, which is applied to the input pins of the device,
is the voltage indicates that the high level states for normal operation
of the input buffer.
* If a voltage that is equal to or greater than the “Min.” value is
applied, the input voltage is guaranteed as high level voltage.
Indicates the voltage, which is applied to the input pins of the device,
is the voltage indicates that the low level states for normal operation
of the input buffer.
* If a voltage that is equal to or lesser than the “Max.” value is
applied, the input voltage is guaranteed as low level voltage.
Indicates the limit value for the time period when an input voltage
applied to the input pins of the device rises from 10% to 90%.
Input fall time
Tfi
Indicates the limit value for the time period when an input voltage
applied to the input pins of the device falls from 90% to 10%.
Operating temperature
TA
Indicates the ambient temperature range for normal logic operations.
Table 3-3. Term Used in DC Characteristics
Parameter
Symbol
Meaning
Off-state output leakage
current
IOZ
Indicates the current that flows from the power supply pins when the
rated power supply voltage is applied whena 3-state output has high
impedance.
Input leakage current
II
Indicates the current that flows when the input voltage is supplied to
the input pin.
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 13 of 40
PD720211
3.3
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Table 3-4.
Parameter
Absolute Maximum Ratings
Symbol
Power supply voltage
Condition
Rating
Units
VDD33,
AVDD33
0.5 to 4.6
V
VDD10
0.5 to 1.4
V
AVDD33IN1,
AVDD33IN2
0.5 to 4.6
V
Input voltage, 3.3 V buffer
VI
VI < VDD33 + 0.5 V
0.5 to 4.6
V
Output voltage, 3.3 V buffer
VO
VO 0 during Reset of Power down
ZRX-HIGH-IMP-DC-POS
25k
LFPS Detect Threshold
VRX-LFPS-DET-DIFF-p-p
100
300
mV
Max.
Units
Table 3-18. Receiver Informative Electrical Parameters
Parameter
Symbol
Min.
Differential Rx peak-to-peak voltage
VRX-DIFF-PP-POST-EQ
Max Rx inherent timing error
TRX-Tj
0.45
UI
Max Rx inherent deterministic timing
error
TRX-DJ-DD
0.285
UI
Rx input capacitance for return loss
CRX-PARASITIC
1.1
pF
Rx AC common mode voltage
VRX-CM-AC-P
150
mVPeak
Rx AC common mode voltage during
the U1 to U0 transition
VRX-CM-DC-ACTIVE-IDLE-
200
mVPeak
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
30
mV
DELTA-P
Page 25 of 40
PD720211
3.8.5
3. ELECTRICAL SPECIFICATIONS
USB2.0 Interface
Table 3-19. USB Interface (1 of 4)
Parameter
Symbol
Conditions
Min.
Max.
Unit
Low-speed Electrical Characteristics
Rise time (10% to 90%)
tLR
CL = 200 pF to 600 pF
75
300
ns
Fall time (90% to 10%)
tLF
CL = 200 pF to 600 pF
75
300
ns
80
125
%
1.49925
1.50075
Mbps
Note
Differential rise and fall time matching
tLRFM
(tLR/tLF)
Low-speed data rate
tLDRATHS
Average bit rate
Downstream facing port source jitter total
(including frequency tolerance) (Figure 319):
To next transition
tDDJ1
25
25
ns
For paired transitions
tDDJ2
14
14
ns
To next transition
tUJR1
152
152
ns
For paired transitions
tUJR2
200
200
ns
Source SE0 interval of EOP (Figure 3-18)
tLEOPT
1.25
1.5
s
Receiver SE0 interval of EOP (Figure 3-18)
tLEOPR
670
Downstream facing port differential receiver
jitter total (including frequency tolerance)
(Figure 3-19):
ns
Width of SE0 interval during differential
transition
tLST
210
ns
Hub differential data delay (Figure 3-15)
tLHDD
300
ns
Hub differential driver jitter (including cable)
(Figure 3-15):
Downstream facing port
To next transition
tLDHJ1
45
45
ns
For paired transitions
tLDHJ2
15
15
ns
To next transition
tLUHJ1
45
45
ns
For paired transitions
tLUHJ2
45
45
ns
tLSOP
60
60
ns
tLEOPD
0
200
ns
tLHESK
300
300
ns
Upstream facing port
Data bit width distortion after SOP (Figure
3-15)
Hub EOP delay relative to tHDD (Figure 316)
Hub EOP output width skew (Figure 3-16)
Full-speed Electrical Characteristics
Rise time (10% to 90%)
tFR
CL = 50 pF,
RS = 36
4
20
ns
Fall time (90% to 10%)
tFF
CL = 50 pF,
RS = 36
4
20
ns
Differential rise and fall time matching
tFRFM
(tFR/tFF)
90
111.11
%
Full-speed data rate
tFDRATHS
Average bit rate
11.9940
12.0060
Mbps
Frame interval
tFRAME
0.9995
1.0005
ms
Note Excluding the first transition from the Idle state.
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 26 of 40
PD720211
3. ELECTRICAL SPECIFICATIONS
Table 3-20. USB Interface (2 of 4)
Parameter
Symbol
Conditions
Min.
Max.
Unit
42
ns
Full-speed Electrical Characteristics (Continued)
Consecutive frame interval jitter
tRFI
Source jitter total (including frequency
No clock adjustment
Note
tolerance) (Figure 3-17):
To next transition
tDJ1
3.5
3.5
ns
For paired transitions
tDJ2
4.0
4.0
ns
2
5
ns
Source jitter for differential transition to SE0
tFDEOP
transition (Figure 3-18)
Receiver jitter (Figure 3-19):
To Next Transition
tJR1
18.5
18.5
ns
For Paired Transitions
tJR2
9
9
ns
Source SE0 interval of EOP (Figure 3-18)
tFEOPT
160
175
ns
Receiver SE0 interval of EOP (Figure 3-18)
tFEOPR
82
Width of SE0 interval during differential
tFST
14
ns
(with cable)
tHDD1
70
ns
(without cable)
tHDD2
44
ns
ns
transition
Hub differential data delay (Figure 3-15)
Hub differential driver jitter (including cable)
(Figure 3-15):
To next transition
tHDJ1
3
3
ns
For paired transitions
tHDJ2
1
1
ns
tFSOP
5
5
ns
Hub EOP delay relative to tHDD (Figure 3-16)
tFEOPD
0
15
ns
Hub EOP output width skew (Figure 3-16)
tFHESK
15
15
ns
Rise time (10% to 90%)
tHSR
500
ps
Fall time (90% to 10%)
tHSF
500
ps
Driver waveform
See Figure 3-13.
High-speed data rate
tHSDRAT
479.760
480.240
Mbps
Microframe interval
tHSFRAM
124.9375
125.0625
s
Consecutive microframe interval difference
tHSRFI
Data bit width distortion after SOP (Figure
3-15)
High-speed Electrical Characteristics
Data source jitter
See Figure 3-13.
Receiver jitter tolerance
See Figure 3-4.
Hub data delay (without cable)
tHSHDD
Hub data jitter
See Figure 3-4, Figure 3-13.
Hub delay variation range
tHSHDV
4 High-
Bit
speed
times
36 High-
Bit
speed4 ns
times
5 High-
Bit
speed
times
Note Excluding the first transition from the Idle state.
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 27 of 40
PD720211
3. ELECTRICAL SPECIFICATIONS
Table 3-21. USB Interface (3 of 4)
Parameter
Symbol
Conditions
Min.
Max.
Unit
Hub Event Timings
Time to detect a downstream facing port
tDCNN
connect event (Figure 3-21):
Awake hub
2.5
2000
Suspended hub
2.5
12000
s
s
tDDIS
2.0
2.5
s
tDRSMDN
20
Time to detect a disconnect event at a hub’s
downstream facing port (Figure 3-20)
Duration of driving resume to a downstream
ms
port (only from a controlling hub)
Time from detecting downstream resume to
tURSM
1.0
ms
10
20
ms
rebroadcast
Duration of driving reset to a downstream
facing port (エラー! 参照元が見つかりませ
tDRST
Only for a SetPortFeature
(PORT_RESET) request
ん。 3-22)
Time to detect a long K from upstream
tURLK
2.5
100
s
Time to detect a long SE0 from upstream
tURLSE0
2.5
10000
s
Duration of repeating SE0 upstream (for
tURPSE0
23
FS Bit
Low-/Full-speed repeater)
Inter-packet delay (for High-speed) of
times
tHSIPDSD
88
Bit
packets traveling in same direction
Inter-packet delay (for High-speed) of
times
tHSIPDOD
8
Bit
packets traveling in opposite direction
Inter-packet delay for device/root hub
times
tHSRSPIPD1
192
response with detachable cable for High-
Bit
times
speed
Time of which a Chirp J or Chirp K must be
tFILT
s
2.5
continuously detected (filtered) by hub or
device during Reset handshake
Time after end of device Chirp K by which
tWTDCH
100
s
hub must start driving first Chirp K in the
hub’s chirp sequence
Time for which each individual Chirp J or
tDCHBIT
40
60
s
tDCHSE0
100
500
s
tWTRSM
5
tDRSMUP
1
Chirp K in the chirp sequence is driven
downstream by hub during reset
Time before end of reset by which a hub
must end its downstream chirp sequence
Period of idle bus before device can initiate
ms
resume
Duration of driving resume upstream
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
15
ms
Page 28 of 40
PD720211
3. ELECTRICAL SPECIFICATIONS
Table 3-22. USB Interface (4 of 4)
Parameter
Symbol
Conditions
Min.
Max.
Unit
2.5
10000
s
Hub Event Timings (Continued)
Time to detect a reset from upstream for
tDETRST
non High-speed capable devices
Inter-packet delay for Full-speed
tIPD
2
Bit
times
Inter-packet delay for device response with
tRSPIPD1
6.5
detachable cable for Full-speed
Bit
times
SetAddress() completion time
tDSETADDR
50
ms
Time to complete standard request with no
tDRQCMPLTND
50
ms
tDRETDATA1
500
ms
tDRETDATAN
50
ms
data
Time to deliver first and subsequent (except
last) data for standard request
Time to deliver last data for standard
request
Time for which a suspended hub will see a
s
tFILTSE0
2.5
tWTRSTFS
2.5
3000
ms
tWTREV
3.0
3.125
ms
tWTRSTHS
100
875
ms
tUCH
1.0
continuous SE0 on upstream before
beginning the High-speed detection
handshake
Time a hub operating in non-suspended
Full-speed will wait after start of SE0 on
upstream before beginning the High-speed
detection handshake
Time a hub operating in High-speed will wait
after start of SE0 on upstream before
reverting to Full-speed
Time a hub will wait after reverting to Fullspeed before sampling the bus state on
upstream and beginning the High-speed will
wait after start of SE0 on upstream before
reverting to Full-speed
Minimum duration of a Chirp K on upstream
ms
from a hub within the reset protocol
Time after start of SE0 on upstream by
tUCHEND
7.0
ms
tWTHS
500
s
2.5
ms
which a hub will complete its Chirp K within
the reset protocol
Time between detection of downstream chip
and entering High-speed state
Time after end of upstream Chirp at which
tWTFS
1.0
hub reverts to Full-speed default state if no
downstream Chirp is detected
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 29 of 40
PD720211
3. ELECTRICAL SPECIFICATIONS
Figure 3-13. Transmit Waveform for Transceiver at DP/DM
+400 mV
Differential
Level 1
Point 3
Point 4
Point 1
0V
Differential
Point 2
Point 5
Point 6
−400 mV
Differential
Level 2
Unit Interval
0%
100%
Figure 3-14. Transmitter Measurement Fixtures
Test Supply Voltage
15.8 Ω
USB
Connector
Nearest
Device
VBUS
D+
DGND
15.8 Ω
143 Ω
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
50 Ω
Coax
50 Ω
Coax
+
To 50 Ω Inputs of a
High Speed Differential
Oscilloscope, or 50 Ω
Outputs of a High Speed
Differential Data Generator
−
143 Ω
Page 30 of 40
PD720211
3. ELECTRICAL SPECIFICATIONS
Figure 3-15. Hub Differential Delay, Differential Jitter, and SOP Distortion
Upstream
End of
Cable
Crossover
Point
Upstream
Port of Hub
50% Point of
Initial Swing
VSS
VSS
Downstream
Port of Hub
Hub Delay
Downstream
tHDD1
VSS
50% Point of
Initial Swing
Hub Delay
Downstream
tHDD2
Downstream
Port of Hub
VSS
A. Downstream Hub Delay with Cable
B. Downstream Hub Delay without Cable
Downstream
Port of Hub
Crossover
Point
VSS
Upstream Port
or
End of Cable
Hub Delay
Upstream
tHDD1
tHDD2
VSS
Crossover
Point
C. Upstream Hub Delay with or without Cable
Upstream end of cable
Upstream port
Downstream port
Receptacle
Plug
Host or
Hub
Hub
Function
Downstream signaling
Upstream signaling
D. Measurement Points
Hub Differential Jitter:
tHDJ1 = tHDDx(J) − tHDDx(K) or tHDDx(K) − tHDDx(J) Consecutive Transitions
tHDJ2 = tHDDx(J) − tHDDx(J) or tHDDx(K) − tHDDx(K) Paired Transitions
Bit after SOP Width Distortion (same as data jitter for SOP and next J transition):
tFSOP = tHDDx(next J) − tHDDx(SOP)
Low-speed timings are determined in the same way for:
tLHDD, tLDHJ1, tLDJH2, tLUHJ1, tLUJH2, and tLSOP
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 31 of 40
PD720211
3. ELECTRICAL SPECIFICATIONS
Figure 3-16. Hub EOP Delay and EOP Skew
Upstream
End of
Cable
50% Point of
Initial Swing
Upstream
Port of Hub
VSS
Crossover
Point
Extended
VSS
tEOP- tEOP+
tEOP- tEOP+
Downstream
Port of Hub
Downstream
Port of Hub
VSS
VSS
A. Downstream EOP Delay with Cable
B. Downstream EOP Delay without Cable
Crossover
Point
Extended
Downstream
Port of Hub
VSS
tEOPUpstream Port
or
End of Cable
tEOP+
Crossover
Point
Extended
VSS
C. Upstream EOP Delay with or without Cable
EOP Delay:
tFEOPD = tEOPy − tHDDx
(tEOPy means that this equation applies to tEOP- and tEOP+)
EOP Skew:
tFHESK = tEOP+ − tEOPLow-speed timings are determined in the same way for:
tLEOPD and tLHESK
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 32 of 40
PD720211
3. ELECTRICAL SPECIFICATIONS
Figure 3-17. USB Differential Data Jitter for Low-/Full-speed
tPERIOD
Crossover
Points
Differential
Data Lines
Consecutive
Transitions
N × tPERIOD + txDJ1
Paired
Transitions
N × tPERIOD + txDJ2
Figure 3-18. USB Differential-to-EOP Transition Skew and EOP Width for Low-/Full-speed
tPERIOD
Crossover
Point Extended
Crossover
Point
Differential
Data Lines
Diff. Data-toSE0 Skew
N × tPERIOD + txDEOP
Source EOP Width: tFEOPT
tLEOPT
Receiver EOP Width: tFEOPR
tLEOPR
Figure 3-19. USB Receiver Jitter Tolerance for Low-/Full-speed
tPERIOD
Differential
Data Lines
txJR
txJR1
txJR2
Consecutive
Transitions
N × tPERIOD + txJR1
Paired
Transitions
N × tPERIOD + txJR2
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 33 of 40
PD720211
3. ELECTRICAL SPECIFICATIONS
Figure 3-20. Low-/Full-speed Disconnect Detection
D+/D−
VIHZ (min)
VIL
D−/D+
VSS
tDDIS
Device
Disconnected
Disconnect
Detected
Figure 3-21. Full-/High-speed Device Connect Detection
D+
VIH
D−
VSS
tDCNN
Device
Connected
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Connect
Detected
Page 34 of 40
PD720211
3.8.6
3. ELECTRICAL SPECIFICATIONS
SPI Type Serial ROM Interface
Table 3-23. SPI Type Serial ROM Interface Signals Timing (SPI Mode 0)
Parameter
Symbol
SPISCK clock frequency
Min.
Max.
Units
-
2.0
MHz
Chip select idle time
TCSIDEL
500
-
ns
Chip select assertion time before clock
TCSBFCLK
250
-
ns
Chip select deassertion time after clock
TCSAFCLK
250
-
ns
Clock pulses width low
TSCKLOW
250
-
ns
Clock pulses width high
TSCKHIGH
250
-
ns
SPISI/LED2B validate time from SPISCK
falling edge
TSIVALID
-
10
ns
SPISI/LED2B hold time from SPISCK
falling edge
TSIHOLD
10
10
ns
SPISO setup time to SPISCK rising edge
TSOSU
5
-
ns
SPISO hold time from SPISCK rising edge
TSOHOLD
5
-
ns
Figure 3-22.
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
SPI Type Serial ROM Signal Timing
Page 35 of 40
PD720211
3.8.7
3. ELECTRICAL SPECIFICATIONS
ACA-Dock function control signal output timing
Table 3-24.
ACA-Dock Function Control Signal Output Timing
Parameter
Symbol
Condition
Min.
Max.
Units
RID control signal of ACA-Dock function
output timing
Tacarid
See Figure 3-24
100
ms
VBUS control signal of ACA-Dock function
output timing
Tacavbus
See Figure 3-24
100
ms
Figure 3-23.
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
SPI Type Serial ROM Signal Timing
Page 36 of 40
PD720211
3.9
3. ELECTRICAL SPECIFICATIONS
Power Consumption
Table 3-25.
Parameter
Power Consumption of PD720211 (without On-chip Regulators Operating)
Device
connection
Power
No host
Consumption connection
Condition
VDD10
line
Hub is not connected to host controller.
VDD33 AVDD33 Units
line
line
1.8
0.1
0.2
mA
“Low Power Mode during suspend” function
Note2
is enabled
3.8
0.2
0.1
mA
“Low Power Mode during suspend” function
is disabled.
5.8
0.3
1.7
mA
Selective
Suspend
Hub is connected to host controller both with
SuperSpeed and HighSpeed. The system is
working and hub goes into U3 state.
5.8
0.3
1.7
mA
1 device
Hub is connected to host controller both with
SuperSpeed and HighSpeed. Only one
device is connected on the port.
Low-speed data transfer on the port.
20
23
12
mA
Full-speed data transfer on the port.
20
25
12
mA
High-speed data transfer on the port.
22
53
12
mA
278
1.5
12
mA
25
76
12
mA
386
1.5
12
mA
437
75
23
mA
Global
Suspend
Hub is connected to host controller both with
SuperSpeed and HighSpeed. And the
system is suspended (S3).
SuperSpeed transfer on the port.
2 devices
Note1
Hub is connected to host controller both with
SuperSpeed and HighSpeed. Two devices
are connected on the ports.
High-speed data transfer on the both ports.
SuperSpeed transfer on the both ports.
Note1
2 SS hubs
Hub is connected to host controller both with
with SS and SuperSpeed and HighSpeed . Two
HS devices SuperSpeed hubs are connected on all ports
under SS and HS data transfer.
Typical condition (TA = 25C, VDD33 = 3.3 V, VDD10 = 1.05 V)
Notes 1. U1/U2 is enabled in this condition.
2. The external serial ROM is needed in order to set to enable Low power mode during suspend.
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 37 of 40
PD720211
3. ELECTRICAL SPECIFICATIONS
Table 3-26.
Parameter
Power Consumption of PD720211 (with On-chip Regulators)
Device
connection
Condition
Total
Power
Units
Note2
Power
No host
Consumption connection
Global
Suspend
Selective
Suspend
1 device
Hub is not connected to host controller.
“Low Power Mode during suspend” is enabled
6
mW
“Low Power Mode during suspend” is disabled
13
mW
“Low Power Mode during suspend” is enabled
10
mW
“Low Power Mode during suspend” is disabled
23
mW
Low Power Mode during suspend is enabled
15
mW
Low Power Mode during suspend is disabled
24
mW
Low-speed data transfer on the port.
140
mW
Full-speed data transfer on the port.
150
mW
High-speed data transfer on the port.
245
mW
410
mW
315
mW
595
mW
880
mW
Hub is connected to host controller both with
SuperSpeed and HighSpeed. And the system
is suspended (S3).
Hub is connected to host controller both with
SuperSpeed and HighSpeed. The system is
working and hub goes into U3 state.
Hub is connected to host controller both with
SuperSpeed and HighSpeed. Only one device
is connected on the port.
SuperSpeed transfer on the port.
2 devices
Note1
Hub is connected to host controller both with
SuperSpeed and HighSpeed. Two devices are
connected on the ports.
High-speed data transfer on the both ports.
SuperSpeed transfer on the both ports.
2 SS hubs
with SS
and HS
devices
Note1
Hub is connected to host controller both with
SuperSpeed and HighSpeed. Two SuperSpeed
hubs are connected on all ports under SS and
HS data transfer.
Typical condition (TA = 25C, VDD33 = 3.3 V, VDD10 = 1.05 V)
Notes 1. U1/U2 is enabled in this condition.
2. The values on this page do NOT represent the chip’s pure power consumption. The values include power loss
by external components, too.
3. The external serial ROM is needed in order to set to enable Low power mode during suspend.
Remark Input voltage for on-chip regulators is 3.3 V.
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 38 of 40
PD720211
4. PACKAGE DRAWINGS
4. PACKAGE DRAWINGS
PD720211K8-611-BAL-A
PD720211K8-711-BAL-A
56- PIN QFN (8 8)
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 39 of 40
PD720211
5. RECOMMENDED SOLDERING CONDITIONS
5. RECOMMENDED SOLDERING CONDITIONS
The PD720211 should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact a Renesas Electronics
sales representative.
For technical detail information, see the following website.
Semiconductor Package Mount Manual (http://www.renesas.com/products/package/index.jsp)
PD720211K8-611-BAL-A: 56-pin QFN (8 8)
PD720211K8-711-BAL-A: 56-pin QFN (8 8)
Soldering Method
Infrared reflow
Soldering Conditions
Peak package’s surface temperature: 260°C
Reflow time: 30 seconds or less (Over 255°C)
60 to 150 seconds (217°C or higher)
Maximum allowable number of reflow processes: 3
Note
Exposure limit
: 7 days (10 hours pre-backing is required at 125°C afterwards)
Non-heat-resistant trays, such as magazine and taping trays, cannot be baked
before unpacking.
Note The Maximum number of days during which the product can be stored at a temperature of 5 to 30°C and a relative
humidity of 70% or less after dry-pack package is opened.
R19DS0080EJ0400 Rev.4.00
Sep 16, 2015
Page 40 of 40
PD720211 Data Sheet
REVISION HISTORY
Rev.
Date
Description
Page
Summary
0.01
July 17, 2013
-
First Edition issued
0.02
Sep. 30, 2013
-
Second Edition issued.
0.03
Oct. 22, 2013
-
LED1B/SUSPEND, SPICSB, SPISO and SPISI/LED2B pin function
description are modified in section 2.
0.04
Dec. 4, 2013
-
Added the new part in section 1.3, 1.5, 4 and 5.
Updated Table 1-1.
Pin function descriptions are modified in section 2.
Modified the buffer type of SUSPEND/NRDCLKO in section 3.1.
Updated the cut-off current of on-chip regulator in Table 3-8.
0.05
1.00
Mar. 4, 2014
Mar. 14, 2014
-
Modified Table 3-12. NRDRST output and CLKOUT Signal Timing
-
Added Table 3-13, Table 3-14, Figure 3-9, Figure 3-10, Figure 3-11 and
Figure 3-12.
-
Added section 3.8.7
-
Added section 3.8.8
-
Modified Table 3-26 Power Consumption of PD720211 (without on-chip
regulators operating)
-
Added Note 2 of Table 3-26
-
Modified Table 3-27 Power Consumption of PD720211 (with on-chip
regulators operating)
-
Added Note 3 of Table 3-27
-
Changed the package picture of 4. PACKAGE DRAWINGS.
-
Document promoted from preliminary data to full data.
(Document Number. R19DS0080E)
2.00
3.00
Jul. 24, 2014
Nov. 25, 2014
Delete the Note description in Table 3-5 Recommended Operating Ranges.
Change section 4 PACKAGE DRAWING
Change section 5 RECOMMENDED SOLDERING CONDITIONS
-
Modified the feature to section 1.1 Features
-
Modified the Function to section 2. Pin Function as below pins
-
LX1
SUSPEND/NRDCLKO
LED1B/SUSPEND
SPICSB
SPISI/LED2B
4.00
Sep 16, 2015
-
Modifiled section 3.1 Buffer List
-
Modified to Table 3-9
-
Modified typo of section 3.8.2
Added section 3.8.7 ACA-Dock function signal output timing
Deleted the following parameters.
28,29
tSIGATT, tATTDB, tSUSAVGI, tRSMRCY, tRSTRCY
34
Deleted Figure 3-22 “Power-on and Connection Events Timing”
40
Modified the URL
Notice
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SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3
Tel: +1-905-237-2004
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
Renesas Electronics Hong Kong Limited
Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HALⅡ Stage, Indiranagar, Bangalore, India
Tel: +91-80-67208700, Fax: +91-80-67208777
Renesas Electronics Korea Co., Ltd.
12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
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