User’s Manual
78K0/KD1
8-Bit Single-Chip Microcontrollers
µPD780121
µPD780122
µPD780123
µPD780124
µPD78F0124
µPD780121(A)
µPD780122(A)
µPD780123(A)
µPD780124(A)
µPD78F0124(A)
Document No. U16315EJ2V0UD00 (2nd edition)
Date Published November 2003 N CP(K)
©
Printed in Japan
µPD780121(A1)
µPD780122(A1)
µPD780123(A1)
µPD780124(A1)
µPD78F0124(A1)
µPD780121(A2)
µPD780122(A2)
µPD780123(A2)
µPD780124(A2)
[MEMO]
2
User’s Manual U16315EJ2V0UD
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
TRON stands for The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
User’s Manual U16315EJ2V0UD
3
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
• The information in this document is current as of May, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
• NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
4
User’s Manual U16315EJ2V0UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
NEC Electronics (Europe) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Duesseldorf, Germany
Tel: 0211-65 03 01
Hong Kong
Tel: 2886-9318
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
• Tyskland Filial
Taeby, Sweden
Tel: 08-63 80 820
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-558-3737
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J03.4
User’s Manual U16315EJ2V0UD
5
INTRODUCTION
Readers
This manual is intended for user engineers who wish to understand the functions of the
78K0/KD1 and design and develop application systems and programs for these
devices.
The target products are as follows.
78K0/KD1: µPD780121, 780122, 780123, 780124, 78F0124, 780121(A), 780122(A),
780123(A),
780124(A),
78F0124(A),
780123(A1),
780124(A1),
78F0124(A1),
780121(A1),
780121(A2),
780122(A1),
780122(A2),
780123(A2), 780124(A2)
Purpose
This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization
The 78K0/KD1 manual is separated into two parts: this manual and the instructions
edition (common to the 78K/0 Series).
78K0/KD1
78K/0 Series
User’s Manual
User’s Manual
(This Manual)
Instructions
• Pin functions
• CPU functions
• Internal block functions
• Instruction set
• Interrupts
• Explanation of each instruction
• Other on-chip peripheral functions
• Electrical specifications
6
User’s Manual U16315EJ2V0UD
How to Read This Manual
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• When using this manual as the manual for (A) grade products, (A1) grade products,
and (A2) grade products:
→ Only the quality grade differs between standard products and (A), (A1), and (A2)
grade products. Read the part number as follows.
•
•
•
•
•
µPD780121 → µPD780121(A), 780121(A1), 780121(A2)
µPD780122 → µPD780122(A), 780122(A1), 780122(A2)
µPD780123 → µPD780123(A), 780123(A1), 780123(A2)
µPD780124 → µPD780124(A), 780124(A1), 780124(A2)
µPD78F0124 → µPD78F0124(A), 78F0124(A1)
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark
shows major
revised points.
• How to interpret the register format:
→ For a bit number enclosed in brackets, the bit name is defined as a reserved word
in the assembler, and is already defined in the header file named sfrbit.h in the C
compiler.
• To check the details of a register when you know the register name:
→ Refer to APPENDIX C REGISTER INDEX.
• To know details of the 78K/0 Series instructions:
→ Refer to the separate document 78K/0 Series Instructions User’s Manual
(U12326E).
Caution Examples in this manual employ the “standard” quality grade for
general electronics.
When using examples in this manual for the
“special” quality grade, review the quality grade of each part and/or
circuit actually used.
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note:
Footnote for item marked with Note in the text
Caution:
Information requiring particular attention
Remark:
Supplementary information
... ×××× or ××××B
Numerical representations: Binary
... ××××
Decimal
Hexadecimal
User’s Manual U16315EJ2V0UD
... ××××H
7
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
78K0/KD1 User’s Manual
This manual
78K/0 Series Instructions User’s Manual
U12326E
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name
RA78K0 Assembler Package
CC78K0 C Compiler
Document No.
Operation
U14445E
Language
U14446E
Structured Assembly Language
U11789E
Operation
U14297E
Language
SM78K Series System Simulator Ver. 2.30 or Later
U14298E
TM
Operation (Windows
Based)
External Part User Open Interface
U15373E
U15802E
Specifications
ID78K Series Integrated Debugger Ver. 2.30 or Later
Operation (Windows Based)
U15185E
RX78K0 Real-Time OS
Fundamentals
U11537E
Installation
U11536E
Project Manager Ver. 3.12 or Later (Windows Based)
U14610E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name
Document No.
IE-78K0-NS In-Circuit Emulator
U13731E
IE-78K0-NS-A In-Circuit Emulator
U14889E
IE-78K0K1-ET In-Circuit Emulator
To be prepared
IE-780148-NS-EM1 Emulation Board
To be prepared
Documents Related to Flash Memory Programming
Document Name
Document No.
PG-FP3 Flash Memory Programmer User’s Manual
U13502E
PG-FP4 Flash Memory Programmer User’s Manual
U15260E
8
User’s Manual U16315EJ2V0UD
Other Related Documents
Document Name
Document No.
SEMICONDUCTOR SELECTION GUIDE - Products and Packages -
X13769X
Semiconductor Device Mount Manual
Note
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
User’s Manual U16315EJ2V0UD
9
CONTENTS
CHAPTER 1 OUTLINE ............................................................................................................................ 17
1.1 Features ...................................................................................................................................... 17
1.2 Applications................................................................................................................................ 18
1.3 Ordering Information ................................................................................................................. 19
1.4 Pin Configuration (Top View).................................................................................................... 21
1.5 K1 Family Lineup........................................................................................................................ 23
1.6
1.7
1.5.1
78K0/Kx1 product lineup................................................................................................................ 23
1.5.2
V850ES/Kx1 product lineup ........................................................................................................... 25
Block Diagram ............................................................................................................................ 27
Outline of Functions .................................................................................................................. 28
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 30
2.1 Pin Function List ........................................................................................................................ 30
2.2 Description of Pin Functions .................................................................................................... 34
2.2.1
P00 to P03 (port 0) ........................................................................................................................ 34
2.2.2
P10 to P17 (port 1) ........................................................................................................................ 34
2.2.3
P20 to P27 (port 2) ........................................................................................................................ 35
2.2.4
P30 to P33 (port 3) ........................................................................................................................ 35
2.2.5
P60 to P63 (port 6) ........................................................................................................................ 36
2.2.6
P70 to P77 (port 7) ........................................................................................................................ 36
2.2.7
P120 (port 12)................................................................................................................................ 36
2.2.8
P130 (port 13)................................................................................................................................ 36
2.2.9
P140 (port 14)................................................................................................................................ 36
2.2.10
AVREF ............................................................................................................................................. 37
2.2.11
AVSS ............................................................................................................................................... 37
2.2.12
RESET........................................................................................................................................... 37
2.2.13
REGC ............................................................................................................................................ 37
2.2.14 X1 and X2 ...................................................................................................................................... 37
2.2.15 XT1 and XT2.................................................................................................................................. 37
2.3
2.2.16
VDD and EVDD ................................................................................................................................. 37
2.2.17
VSS and EVSS ................................................................................................................................. 37
2.2.18
VPP (flash memory versions only) .................................................................................................. 37
2.2.19
IC (mask ROM versions only) ........................................................................................................ 38
Pin I/O Circuits and Recommended Connection of Unused Pins......................................... 39
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 42
3.1 Memory Space ............................................................................................................................ 42
3.2
10
3.1.1
Internal program memory space .................................................................................................... 48
3.1.2
Internal data memory space .......................................................................................................... 49
3.1.3
Special function register (SFR) area.............................................................................................. 49
3.1.4
Data memory addressing............................................................................................................... 50
Processor Registers .................................................................................................................. 55
3.2.1
Control registers ............................................................................................................................ 55
3.2.2
General-purpose registers ............................................................................................................. 59
3.2.3
Special Function Registers (SFRs)................................................................................................ 60
User’s Manual U16315EJ2V0UD
3.3
Instruction Address Addressing .............................................................................................. 64
3.3.1
3.4
Relative addressing ........................................................................................................................64
3.3.2
Immediate addressing ....................................................................................................................65
3.3.3
Table indirect addressing ...............................................................................................................66
3.3.4
Register addressing........................................................................................................................66
Operand Address Addressing .................................................................................................. 67
3.4.1
Implied addressing .........................................................................................................................67
3.4.2
Register addressing........................................................................................................................68
3.4.3
Direct addressing............................................................................................................................69
3.4.4
Short direct addressing...................................................................................................................70
3.4.5
Special function register (SFR) addressing ....................................................................................71
3.4.6
Register indirect addressing ...........................................................................................................72
3.4.7
Based addressing...........................................................................................................................73
3.4.8
Based indexed addressing .............................................................................................................74
3.4.9
Stack addressing ............................................................................................................................75
CHAPTER 4 PORT FUNCTIONS........................................................................................................... 76
4.1 Port Functions............................................................................................................................ 76
4.2 Port Configuration ..................................................................................................................... 78
4.3
4.4
4.2.1
Port 0..............................................................................................................................................79
4.2.2
Port 1..............................................................................................................................................82
4.2.3
Port 2..............................................................................................................................................87
4.2.4
Port 3..............................................................................................................................................88
4.2.5
Port 6..............................................................................................................................................90
4.2.6
Port 7..............................................................................................................................................91
4.2.7
Port 12............................................................................................................................................92
4.2.8
Port 13............................................................................................................................................93
4.2.9
Port 14............................................................................................................................................94
Registers Controlling Port Function ........................................................................................ 95
Port Function Operations.......................................................................................................... 99
4.4.1
Writing to I/O port ...........................................................................................................................99
4.4.2
Reading from I/O port .....................................................................................................................99
4.4.3
Operations on I/O port ....................................................................................................................99
CHAPTER 5 CLOCK GENERATOR .................................................................................................... 100
5.1 Functions of Clock Generator ................................................................................................ 100
5.2 Configuration of Clock Generator .......................................................................................... 100
5.3 Registers Controlling Clock Generator ................................................................................. 102
5.4 System Clock Oscillator.......................................................................................................... 109
5.4.1
5.5
5.6
5.7
5.8
X1 oscillator ..................................................................................................................................109
5.4.2
Subsystem clock oscillator............................................................................................................109
5.4.3
When subsystem clock is not used...............................................................................................112
5.4.4
Ring-OSC oscillator ......................................................................................................................112
5.4.5
Prescaler ......................................................................................................................................112
Clock Generator Operation ..................................................................................................... 113
Time Required to Switch Between Ring-OSC Clock and X1 Input Clock .......................... 120
Time Required for CPU Clock Switchover ............................................................................ 121
Clock Switching Flowchart and Register Setting ................................................................. 122
User’s Manual U16315EJ2V0UD
11
5.8.1
Switching from Ring-OSC clock to X1 input clock.........................................................................122
5.8.2
Switching from X1 input clock to Ring-OSC clock.........................................................................123
5.8.3
Switching from X1 input clock to subsystem clock........................................................................124
5.8.4
Switching from subsystem clock to X1 input clock........................................................................125
5.8.5
Register settings ...........................................................................................................................126
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 ........................................................................... 127
6.1 Functions of 16-Bit Timer/Event Counter 00 ......................................................................... 127
6.2 Configuration of 16-Bit Timer/Event Counter 00................................................................... 128
6.3 Registers Controlling 16-Bit Timer/Event Counter 00 .......................................................... 132
6.4 Operation of 16-Bit Timer/Event Counter 00 ......................................................................... 138
6.5
6.4.1
Interval timer operation .................................................................................................................138
6.4.2
PPG output operations .................................................................................................................141
6.4.3
Pulse width measurement operations ...........................................................................................144
6.4.4
External event counter operation ..................................................................................................152
6.4.5
Square-wave output operation......................................................................................................155
6.4.6
One-shot pulse output operation...................................................................................................157
Cautions for 16-Bit Timer/Event Counter 00 ......................................................................... 162
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................... 165
7.1 Functions of 8-Bit Timer/Event Counters 50 and 51............................................................. 165
7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 ...................................................... 167
7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ............................................. 169
7.4 Operations of 8-Bit Timer/Event Counters 50 and 51........................................................... 174
7.5
7.4.1
Operation as interval timer............................................................................................................174
7.4.2
Operation as external event counter .............................................................................................176
7.4.3
Square-wave output operation......................................................................................................177
7.4.4
PWM output operation ..................................................................................................................178
Cautions for 8-Bit Timer/Event Counters 50 and 51 ............................................................. 182
CHAPTER 8 8-BIT TIMERS H0 AND H1 .......................................................................................... 183
8.1 Functions of 8-Bit Timers H0 and H1 ..................................................................................... 183
8.2 Configuration of 8-Bit Timers H0 and H1............................................................................... 183
8.3 Registers Controlling 8-Bit Timers H0 and H1 ...................................................................... 187
8.4 Operation of 8-Bit Timers H0 and H1 ..................................................................................... 192
8.4.1
Operation as interval timer/square-wave output ...........................................................................192
8.4.2
Operation as PWM output mode...................................................................................................195
8.4.3
Carrier generator mode operation (8-bit timer H1 only) ................................................................201
CHAPTER 9 WATCH TIMER................................................................................................................ 208
9.1 Functions of Watch Timer ....................................................................................................... 208
9.2 Configuration of Watch Timer................................................................................................. 210
9.3 Register Controlling Watch Timer .......................................................................................... 210
9.4 Watch Timer Operations.......................................................................................................... 212
9.5
12
9.4.1
Watch timer operation...................................................................................................................212
9.4.2
Interval timer operation .................................................................................................................213
Cautions for Watch Timer ....................................................................................................... 214
User’s Manual U16315EJ2V0UD
CHAPTER 10 WATCHDOG TIMER ..................................................................................................... 215
10.1 Functions of Watchdog Timer ................................................................................................ 215
10.2 Configuration of Watchdog Timer.......................................................................................... 217
10.3 Registers Controlling Watchdog Timer ................................................................................. 218
10.4 Operation of Watchdog Timer ................................................................................................ 220
10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by mask option ......220
10.4.2
Watchdog timer operation when “Ring-OSC can be stopped by software” is selected by mask
option............................................................................................................................................221
10.4.3
Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped by software” is
selected by mask option) ..............................................................................................................222
10.4.4
Watchdog timer operation in HALT mode (when “Ring-OSC can be stopped by software” is
selected by mask option) ..............................................................................................................224
CHAPTER 11 CLOCK OUTPUT CONTROLLER ............................................................................... 225
11.1 Functions of Clock Output Controller ................................................................................... 225
11.2 Configuration of Clock Output Controller ............................................................................. 225
11.3 Registers Controlling Clock Output Controller .................................................................... 226
11.4 Clock Output Controller Operations ...................................................................................... 227
CHAPTER 12 A/D CONVERTER ......................................................................................................... 228
12.1 Functions of A/D Converter .................................................................................................... 228
12.2 Configuration of A/D Converter.............................................................................................. 229
12.3 Registers Used in A/D Converter ........................................................................................... 231
12.4 A/D Converter Operations....................................................................................................... 236
12.4.1
Basic operations of A/D converter ................................................................................................236
12.4.2
Input voltage and conversion results ............................................................................................238
12.4.3
A/D converter operation mode......................................................................................................239
12.5 How to Read A/D Converter Characteristics Table .............................................................. 242
12.6 Cautions for A/D Converter..................................................................................................... 244
CHAPTER 13 SERIAL INTERFACE UART0 ...................................................................................... 249
13.1 Functions of Serial Interface UART0 ..................................................................................... 249
13.2 Configuration of Serial Interface UART0 ............................................................................... 250
13.3 Registers Controlling Serial Interface UART0 ...................................................................... 253
13.4 Operation of Serial Interface UART0...................................................................................... 258
13.4.1
Operation stop mode ....................................................................................................................258
13.4.2
Asynchronous serial interface (UART) mode................................................................................259
13.4.3
Dedicated baud rate generator .....................................................................................................265
CHAPTER 14 SERIAL INTERFACE UART6 ...................................................................................... 270
14.1 Functions of Serial Interface UART6 ..................................................................................... 270
14.2 Configuration of Serial Interface UART6 ............................................................................... 274
14.3 Registers Controlling Serial Interface UART6 ...................................................................... 277
14.4 Operation of Serial Interface UART6...................................................................................... 285
14.4.1
Operation stop mode ....................................................................................................................285
14.4.2
Asynchronous serial interface (UART) mode................................................................................286
14.4.3
Dedicated baud rate generator .....................................................................................................301
User’s Manual U16315EJ2V0UD
13
CHAPTER 15 SERIAL INTERFACE CSI10 ........................................................................................ 308
15.1 Functions of Serial Interface CSI10........................................................................................ 308
15.2 Configuration of Serial Interface CSI10 ................................................................................. 308
15.3 Registers Controlling Serial Interface CSI10......................................................................... 310
15.4 Operation of Serial Interface CSI10 ........................................................................................ 313
15.4.1 Operation stop mode ....................................................................................................................313
15.4.2 3-wire serial I/O mode...................................................................................................................314
CHAPTER 16 INTERRUPT FUNCTIONS ............................................................................................ 322
16.1 Interrupt Function Types ......................................................................................................... 322
16.2 Interrupt Sources and Configuration ..................................................................................... 322
16.3 Registers Controlling Interrupt Functions............................................................................. 327
16.4 Interrupt Servicing Operations ............................................................................................... 333
16.4.1 Maskable interrupt request acknowledgement..............................................................................333
16.4.2 Software interrupt request acknowledgement...............................................................................335
16.4.3
Multiple interrupt servicing ............................................................................................................336
16.4.4
Interrupt request hold....................................................................................................................339
CHAPTER 17 KEY INTERRUPT FUNCTION ..................................................................................... 340
17.1 Functions of Key Interrupt ...................................................................................................... 340
17.2 Configuration of Key Interrupt................................................................................................ 340
17.3 Register Controlling Key Interrupt ......................................................................................... 341
CHAPTER 18 STANDBY FUNCTION .................................................................................................. 342
18.1 Standby Function and Configuration..................................................................................... 342
18.1.1 Standby function ...........................................................................................................................342
18.1.2
Registers controlling standby function ..........................................................................................343
18.2 Standby Function Operation................................................................................................... 346
18.2.1 HALT mode...................................................................................................................................346
18.2.2
STOP mode ..................................................................................................................................351
CHAPTER 19 RESET FUNCTION........................................................................................................ 355
19.1 Register for Confirming Reset Source................................................................................... 361
CHAPTER 20 CLOCK MONITOR ........................................................................................................ 362
20.1 Functions of Clock Monitor..................................................................................................... 362
20.2 Configuration of Clock Monitor .............................................................................................. 362
20.3 Register Controlling Clock Monitor........................................................................................ 363
20.4 Operation of Clock Monitor..................................................................................................... 364
CHAPTER 21 POWER-ON-CLEAR CIRCUIT...................................................................................... 369
21.1 Functions of Power-on-Clear Circuit...................................................................................... 369
21.2 Configuration of Power-on-Clear Circuit ............................................................................... 370
21.3 Operation of Power-on-Clear Circuit...................................................................................... 370
21.4 Cautions for Power-on-Clear Circuit ...................................................................................... 371
CHAPTER 22 LOW-VOLTAGE DETECTOR ....................................................................................... 373
22.1 Functions of Low-Voltage Detector........................................................................................ 373
14
User’s Manual U16315EJ2V0UD
22.2
22.3
22.4
22.5
Configuration of Low-Voltage Detector................................................................................. 373
Registers Controlling Low-Voltage Detector ........................................................................ 374
Operation of Low-Voltage Detector........................................................................................ 377
Cautions for Low-Voltage Detector........................................................................................ 381
CHAPTER 23 REGULATOR ................................................................................................................. 385
23.1 Outline....................................................................................................................................... 385
CHAPTER 24 MASK OPTIONS ........................................................................................................... 387
CHAPTER 25 µPD78F0124................................................................................................................... 388
25.1 Internal Memory Size Switching Register ............................................................................. 389
25.2 Writing with Flash Programmer.............................................................................................. 390
25.3 Programming Environment..................................................................................................... 397
25.4 Communication Mode ............................................................................................................. 397
25.5 Handling of Pins on Board...................................................................................................... 400
25.5.1
VPP pin ..........................................................................................................................................400
25.5.2
Serial interface pins ......................................................................................................................400
25.5.3
RESET pin....................................................................................................................................402
25.5.4
Port pins .......................................................................................................................................402
25.5.5
REGC pin .....................................................................................................................................402
25.5.6
Other signal pins...........................................................................................................................402
25.5.7
Power supply ................................................................................................................................402
25.6 Programming Method.............................................................................................................. 403
25.6.1
Controlling flash memory ..............................................................................................................403
25.6.2 Flash memory programming mode...............................................................................................403
25.6.3 Selecting communication mode....................................................................................................404
25.6.4
Communication commands ..........................................................................................................404
CHAPTER 26 INSTRUCTION SET ...................................................................................................... 406
26.1 Conventions Used in Operation List...................................................................................... 406
26.1.1 Operand identifiers and specification methods .............................................................................406
26.1.2 Description of operation column ...................................................................................................407
26.1.3 Description of flag operation column ............................................................................................407
26.2 Operation List........................................................................................................................... 408
26.3 Instructions Listed by Addressing Type ............................................................................... 416
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE
PRODUCTS) ................................................................................................................... 419
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)................................ 438
CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)................................ 457
CHAPTER 30 PACKAGE DRAWING .................................................................................................. 471
CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS........................................................... 472
User’s Manual U16315EJ2V0UD
15
CHAPTER 32 CAUTIONS FOR WAIT................................................................................................. 474
32.1 Cautions for Wait...................................................................................................................... 474
32.2 Peripheral Hardware That Generates Wait ............................................................................ 475
32.3 Example of Wait Occurrence .................................................................................................. 476
APPENDIX A DEVELOPMENT TOOLS............................................................................................... 477
A.1 Software Package..................................................................................................................... 480
A.2 Language Processing Software.............................................................................................. 480
A.3 Control Software ...................................................................................................................... 481
A.4 Flash Memory Writing Tools ................................................................................................... 481
A.5 Debugging Tools (Hardware) .................................................................................................. 482
A.5.1
When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A .................................................482
A.5.2
When using in-circuit emulator IE-78K0K1-ET..............................................................................483
A.6 Debugging Tools (Software) ................................................................................................... 484
A.7 Embedded Software................................................................................................................. 485
APPENDIX B NOTES ON TARGET SYSTEM DESIGN ................................................................... 486
APPENDIX C REGISTER INDEX ......................................................................................................... 488
C.1 Register Index (In Alphabetical Order with Respect to Register Names) .......................... 488
C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ......................... 491
APPENDIX D REVISION HISTORY ..................................................................................................... 494
D.1 Major Revisions in This Edition.............................................................................................. 494
16
User’s Manual U16315EJ2V0UD
CHAPTER 1 OUTLINE
1.1 Features
{ Minimum instruction execution time can be changed from high speed (0.2 µs: @ 10 MHz operation with X1
input clock) to ultra low-speed (122 µs: @ 32.768 kHz operation with subsystem clock)
{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
{ ROM, RAM capacities
Item
Part Number
µPD780121
Program Memory
Data Memory
(ROM)
Internal High-Speed RAM
8 KB
Mask ROM
µPD780122
16 KB
µPD780123
24 KB
µPD780124
32 KB
µPD78F0124
Note
Flash memory
512 bytes
1024 bytes
Note
32 KB
Note
1024 bytes
The internal flash memory and internal high-speed RAM capacities can be changed using the internal
memory size switching register (IMS).
{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
{ Short startup is possible via the CPU default start using the on-chip Ring-OSC
{ On-chip clock monitor function using on-chip Ring-OSC
{ On-chip watchdog timer (operable with Ring-OSC clock)
{ On-chip key interrupt function
{ On-chip clock output controller
{ On-chip regulator
{ I/O ports: 39 (N-ch open drain: 4)
{ Timer: 7 channels
{ Serial interface: 2 channels
(UART (LIN (Local Interconnect Network)-bus supported): 1 channel, CSI/UARTNote: 1 channel)
{ 10-bit resolution A/D converter: 8 channels
{ Supply voltage: VDD = 2.7 to 5.5 V (standard product, (A) grade product)
VDD = 3.3 to 5.5 V ((A1) grade product, (A2) grade product)
{ Operating ambient temperature: TA = −40 to +85°C (standard product, (A) grade product)
TA = −40 to +105°C (flash memory version of (A1) grade product)
TA = −40 to +110°C (mask ROM version of (A1) grade product)
TA = −40 to +125°C (mask ROM version of (A2) grade product)
Note Select either of the functions of these alternate-function pins.
User’s Manual U16315EJ2V0UD
17
CHAPTER 1 OUTLINE
1.2 Applications
{ Automotive equipment
• System control for body electricals (power windows, keyless entry reception, etc.)
• Sub-microcontrollers for control
{ Home audio, car audio
{ AV equipment
{ PC peripheral equipment (keyboards, etc.)
{ Household electrical appliances
• Outdoor air conditioner units
• Microwave ovens, electric rice cookers
{ Industrial equipment
• Pumps
• Vending machines
• FA (Factory Automation)
18
User’s Manual U16315EJ2V0UD
CHAPTER 1 OUTLINE
1.3 Ordering Information
Part Number
µPD780121GB-×××-8ET
µPD780122GB-×××-8ET
µPD780123GB-×××-8ET
µPD780124GB-×××-8ET
µPD780121GB(A)-×××-8ET
µPD780122GB(A)-×××-8ET
µPD780123GB(A)-×××-8ET
µPD780124GB(A)-×××-8ET
µPD780121GB(A1)-×××-8ET
µPD780122GB(A1)-×××-8ET
µPD780123GB(A1)-×××-8ET
µPD780124GB(A1)-×××-8ET
µPD780121GB(A2)-×××-8ET
µPD780122GB(A2)-×××-8ET
µPD780123GB(A2)-×××-8ET
µPD780124GB(A2)-×××-8ET
µPD78F0124M1GB-8ET
µPD78F0124M2GB-8ET
µPD78F0124M3GB-8ET
µPD78F0124M4GB-8ET
µPD78F0124M5GB-8ET
µPD78F0124M6GB-8ET
µPD78F0124M1GB(A)-8ET
µPD78F0124M2GB(A)-8ET
µPD78F0124M3GB(A)-8ET
µPD78F0124M4GB(A)-8ET
µPD78F0124M5GB(A)-8ET
µPD78F0124M6GB(A)-8ET
µPD78F0124M1GB(A1)-8ET
µPD78F0124M2GB(A1)-8ET
µPD78F0124M5GB(A1)-8ET
µPD78F0124M6GB(A1)-8ET
Remark
Package
Quality Grade
52-pin plastic LQFP (10 × 10)
Standard
52-pin plastic LQFP (10 × 10)
Standard
52-pin plastic LQFP (10 × 10)
Standard
52-pin plastic LQFP (10 × 10)
Standard
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Standard
52-pin plastic LQFP (10 × 10)
Standard
52-pin plastic LQFP (10 × 10)
Standard
52-pin plastic LQFP (10 × 10)
Standard
52-pin plastic LQFP (10 × 10)
Standard
52-pin plastic LQFP (10 × 10)
Standard
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
52-pin plastic LQFP (10 × 10)
Special
××× indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
User’s Manual U16315EJ2V0UD
19
CHAPTER 1 OUTLINE
Mask ROM versions (µPD780121, 780122, 780123, and 780124) include mask options. When ordering, it is
possible to select “Power-on-clear (POC) circuit can be used/cannot be used”, “Ring-OSC clock can be
stopped/cannot be stopped by software” and “Pull-up resistor incorporated/not incorporated in 1-bit units (P60 to P63
pins)”.
Flash memory versions corresponding to the mask options of the mask ROM versions are as follows.
Table 1-1. Flash Memory Versions Corresponding to Mask Options of Mask ROM Versions
Flash Memory Versions
Mask Option
POC Circuit
POC cannot be used
POC used (VPOC = 2.85 V ±0.15 V)
POC used (VPOC = 3.5 V ±0.2 V)
20
Ring-OSC
(Part Number)
Cannot be stopped
µPD78F0124M1GB-8ET
µPD78F0124M1GB(A)-8ET
µPD78F0124M1GB(A1)-8ET
Can be stopped by software
µPD78F0124M2GB-8ET
µPD78F0124M2GB(A)-8ET
µPD78F0124M2GB(A1)-8ET
Cannot be stopped
µPD78F0124M3GB-8ET
µPD78F0124M3GB(A)-8ET
Can be stopped by software
µPD78F0124M4GB-8ET
µPD78F0124M4GB(A)-8ET
Cannot be stopped
µPD78F0124M5GB-8ET
µPD78F0124M5GB(A)-8ET
µPD78F0124M5GB(A1)-8ET
Can be stopped by software
µPD78F0124M6GB-8ET
µPD78F0124M6GB(A)-8ET
µPD78F0124M6GB(A1)-8ET
User’s Manual U16315EJ2V0UD
CHAPTER 1 OUTLINE
1.4 Pin Configuration (Top View)
P74/KR4
P73/KR3
P72/KR2
P71/KR1
P70/KR0
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1
P20/ANI0
• 52-pin plastic LQFP (10 × 10)
52 51 50 49 48 47 46 45 44 43 42 41 40
AVREF
1
39
P75/KR5
AVSS
2
38
P76/KR6
VPP/IC
3
37
P77/KR7
VDD
4
36
P00/TI000
REGC
5
35
P01/TI010/TO00
VSS
6
34
P02
X1
7
33
P03
X2
8
32
P10/SCK10/TxD0
RESET
9
31
P11/SI10/RxD0
XT1
10
30
P12/SO10
XT2
11
29
P13/TxD6
P130
12
28
P14/RxD6
P120/INTP0
13
27
EVDD
EVSS
P63
P62
P61
P60
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
P140/PCL/INTP6
P30/INTP1
P31/INTP2
P32/INTP3
P33/TI51/TO51/INTP4
14 15 16 17 18 19 20 21 22 23 24 25 26
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS.
2. Connect the AVSS pin to VSS.
3. Connect the REGC pin as follows.
Standard Product and (A) Grade
Product
(A1) Grade Product and (A2) Grade
Product
When regulator is used
Connect to VSS via a capacitor (1 µF: − (Regulator cannot be used.)
recommended)
When regulator is not used
Connect directly to VDD
4. Connect the VPP pin to EVSS or VSS during normal operation.
Remark
Figures in parentheses apply to the µPD78F0124.
User’s Manual U16315EJ2V0UD
21
CHAPTER 1 OUTLINE
Pin Identification
ANI0 to ANI7:
Analog input
PCL:
Programmable clock output
AVREF:
Analog reference voltage
REGC:
Regulator capacitance
AVSS:
Analog ground
RESET:
Reset
EVDD:
Power supply for port
RxD0, RxD6:
Receive data
EVSS:
Ground for port
SCK10:
Serial clock input/output
IC:
Internally connected
SI10:
Serial data input
INTP0 to INTP6: External interrupt input
SO10:
Serial data output
KR0 to KR7:
Key return
TI000, TI010,TI50, TI51: Timer input
P00 to P03:
Port 0
TO00, TO50, TO51,
P10 to P17:
Port 1
TOH0, TOH1:
P20 to P27:
Port 2
TxD0, TxD6:
Transmit data
P30 to P33:
Port 3
VDD:
Power supply
P60 to P63:
Port 6
VPP:
Programming power supply
P70 to P77:
Port 7
VSS:
Ground
P120:
Port 12
X1, X2:
Crystal oscillator (X1 input clock)
P130:
Port 13
XT1, XT2:
Crystal oscillator (Subsystem clock)
P140:
Port 14
22
User’s Manual U16315EJ2V0UD
Timer output
CHAPTER 1 OUTLINE
1.5 K1 Family Lineup
1.5.1 78K0/Kx1 product lineup
78K0/KB1: 30-pin (7.62 mm 0.65 mm pitch)
µ PD78F0103
Flash memory: 24 KB, RAM: 768 bytes
µ PD780103
Mask ROM: 24 KB, RAM: 768 bytes
µ PD780102
Mask ROM: 16 KB, RAM: 768 bytes
µ PD780101
Mask ROM: 8 KB, RAM: 512 bytes
78K0/KC1: 44-pin (10 × 10 mm 0.8 mm pitch)
µ PD78F0114
Flash memory: 32 KB, RAM: 1 KB
µ PD780114
Mask ROM: 32 KB, RAM: 1 KB
µ PD780113
Mask ROM: 24 KB, RAM: 1 KB
µ PD780112
Mask ROM: 16 KB, RAM: 512 bytes
µ PD780111
Mask ROM: 8 KB, RAM: 512 bytes
78K0/KD1: 52-pin (10 × 10 mm 0.65 mm pitch)
µ PD78F0124
Flash memory: 32 KB, RAM: 1 KB
µ PD780124
Mask ROM: 32 KB, RAM: 1 KB
µ PD780123
Mask ROM: 24 KB, RAM: 1 KB
µ PD780122
Mask ROM: 16 KB, RAM: 512 bytes
µ PD780121
Mask ROM: 8 KB, RAM: 512 bytes
78K0/KE1: 64-pin (10 × 10 mm 0.5 mm pitch, 12 × 12 mm 0.65 mm pitch, 14 × 14 mm 0.8 mm pitch)
µPD78F0134
Flash memory: 32 KB, RAM: 1 KB
µ PD780134
µ PD78F0138
Mask ROM: 32 KB, RAM: 1 KB
µ PD780133
µPD780138
Mask ROM: 24 KB, RAM: 1 KB
µ PD780132
Flash memory: 60 KB, RAM: 2 KB
µPD780136
Mask ROM: 60 KB, RAM: 2 KB
Mask ROM: 48 KB, RAM: 2 KB
Mask ROM: 16 KB, RAM: 512 bytes
µPD780131
Mask ROM: 8 KB, RAM: 512 bytes
78K0/KF1: 80-pin (12 × 12 mm 0.5 mm pitch, 14 × 14 mm 0.65 mm pitch)
µ PD78F0148
Flash memory: 60 KB, RAM: 2 KB
µ PD780148
Mask ROM: 60 KB, RAM: 2 KB
µ PD780146
Mask ROM: 48 KB, RAM: 2 KB
µ PD780144
µ PD780143
Mask ROM: 32 KB, RAM: 1 KB
Mask ROM: 24 KB, RAM: 1 KB
User’s Manual U16315EJ2V0UD
23
CHAPTER 1 OUTLINE
The list of functions in the 78K0/Kx1 is shown below.
Part Number
78K0/KB1
78K0/KC1
78K0/KD1
78K0/KE1
78K0/KF1
Item
Package
Internal
memory
(bytes)
30 pins
Mask ROM
44 pins
−
8 K 16 K
24 K
−
Flash memory
RAM
−
768
−
1K
Minimum instruction execution time
Clock
1K
0.2 µs (when 10 MHz, VDD =
4.0 to 5.5 V)
0.24 µs (when 8.38 MHz, VDD =
3.3 to 5.5 V)
0.4 µs (when 5 MHz, VDD = 2.7
to 5.5 V)
−
CMOS I/O
17
CMOS input
4
2K
60 K
1K
2K
32.768 kHz
19
26
38
54
8
1
−
4
16 bits (TM0)
1 ch
8 bits (TM5)
1 ch
2 ch
1 ch
2 ch
1 ch
2 ch
2 ch
8 bits (TMH)
2 ch
−
For watch
1 ch
WDT
1 ch
Note
Serial
3-wire CSI
interface Automatic transmit/
receive 3-wire CSI
Note
UART
1 ch
−
1 ch
UART supporting LIN-bus
1 ch
4 ch
External
Internal
Key return input
6
11
8 ch
7
12
−
8
LVI
9
15
16
2.85 V ±0.15 V/3.5 V ±0.20 V (selectable by mask option)
3.1 V/3.3 V ±0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V (selectable by software)
Provided
Provided
Standby function
Operating ambient temperature
20
8 ch
Clock monitor
ROM correction
17
Provided
WDT
Multiplier/divider
9
19
4 ch
RESET pin
POC
2 ch
1 ch
−
10-bit A/D converter
16 bits × 16 bits, 32 bits ÷ 16 bits
−
−
Provided
HALT/STOP mode
Standard products, special (A) products: −40 to +85°C
Special (A1) products: −40 to +110°C (mask ROM version),
−40 to +105°C (flash memory version)
Special (A2) products: −40 to +125°C (mask ROM version)
Note Select either of the functions of these alternate-function pins.
24
−
240 kHz (TYP.)
CMOS output
Reset
1K
32 K 60 K
60 K
2 to 10 MHz
N-ch open-drain I/O
Interrupt
−
0.2 µs (when 10 MHz, VDD = 4.0 to 5.5 V)
0.24 µs (when 8.38 MHz, VDD = 3.3 to 5.5 V)
0.4 µs (when 5 MHz, VDD = 2.7 to 5.5 V)
X1 input
Sub
Timer
512
60 K
32 K
−
24 K 48 K
VDD = 2.7 to 5.5 V
Ring-OSC
Port
−
80 pins
−
48 K
16 K 32 K
32 K
512
Power supply voltage
−
8 K 24 K
16 K 32 K
32 K
512
64 pins
−
8 K 24 K
16 K 32 K
24 K
512
52 pins
−
8 K 24 K
User’s Manual U16315EJ2V0UD
−
CHAPTER 1 OUTLINE
1.5.2
V850ES/Kx1 product lineup
V850ES/KF1
80-pin plastic QFP (14 × 14)
80-pin plastic TQFP (fine pitch) (12 × 12)
µ PD703208
µ PD703208Y
µ PD703209
µPD703209Y
µ PD703210
Mask ROM: 64 KB, RAM: 4 KB
I2C products
Mask ROM: 96 KB, RAM: 4 KB
I2C products
Mask ROM: 128 KB, RAM: 6 KB
µ PD703210Y
I2C products
µ PD70F3210
Flash memory: 128 KB, RAM: 6 KB
µPD70F3210Y
I2C products
V850ES/KG1 100-pin plastic LQFP (fine pitch) (14 × 14)
µ PD703212
µPD703212Y
µ PD703213
µ PD703213Y
µ PD703214
Mask ROM: 64 KB, RAM: 4 KB
I2C products
Mask ROM: 96 KB, RAM: 4 KB
I2C products
Mask ROM: 128 KB, RAM: 6 KB
µPD703214Y
I2C products
µ PD70F3214
Flash memory: 128 KB, RAM: 6 KB
µPD70F3214Y
I2C products
V850ES/KJ1 144-pin plastic LQFP (fine pitch) (20 × 20)
µ PD703216
µ PD703216Y
µ PD703217
Mask ROM: 96 KB, RAM: 6 KB
I2C products
Mask ROM: 128 KB, RAM: 6 KB
µ PD703217Y
I2C products
µ PD70F3217
Flash memory: 128 KB, RAM: 6 KB
µ PD70F3217Y
I2C products
User’s Manual U16315EJ2V0UD
25
CHAPTER 1 OUTLINE
The list of functions in the V850ES/Kx1 is shown below.
Function
Part No.
µPD703208
Timer
Serial Interface
8-Bit 16-Bit TMH Watch WDT
CSI
CSIA
UART
2 ch
2 ch
1 ch
2 ch
2 ch
2 ch
1 ch
2 ch
V850ES/KF1
µPD703208Y
µPD703210
V850ES/KG1
Other
8 ch
–
6 ch
67
–
8 ch
2 ch
6 ch
84
–
16 ch
2 ch
12 ch
128
–
IC
–
–
µPD703210Y
1 ch
µPD70F3210
–
1 ch
2 ch
4 ch
2 ch
1 ch
2 ch
2 ch
2 ch
2 ch
µPD703212Y
–
1 ch
µPD703213
–
µPD703213Y
1 ch
µPD703214
–
µPD703214Y
1 ch
µPD70F3214
–
µPD70F3214Y
V850ES/KJ1
I/O
1 ch
µPD70F3210Y
1 ch
2 ch
6 ch
2 ch
1 ch
2 ch
3 ch
2 ch
3 ch
µPD703216Y
–
2 ch
µPD703217
–
µPD703217Y
2 ch
µPD70F3217
–
µPD70F3217Y
26
RTO
–
µPD703209Y
µPD703216
D/A
1 ch
µPD703209
µPD703212
A/D
2
2 ch
User’s Manual U16315EJ2V0UD
CHAPTER 1 OUTLINE
1.6 Block Diagram
TO00/TI010/P01
TI000/P00
16-bit timer/
event counter 00
TOH0/P15
Port 0
4
P00 to P03
Port 1
8
P10 to P17
Port 2
8
P20 to P27
Port 3
4
P30 to P33
Port 6
4
P60 to P63
Port 7
8
P70 to P77
8-bit timer H0
TOH1/P16
8-bit timer H1
8-bit timer/
event counter 50
TI50/TO50/P17
8-bit timer/
event counter 51
TI51/TO51/P33
Watch timer
78K/0
CPU
core
ROM
(Flash
memory)
Watchdog timer
RxD0/P11
TxD0/P10
Serial
interface UART0
RxD6/P14
TxD6/P13
Serial
interface UART6
Port 12
P120
Port 13
P130
Port 14
P140
Clock output control
PCL/P140
Clock monitor
SI10/P11
SO10/P12
SCK10/P10
ANI0/P20 to
ANI7/P27
AVREF
AVSS
Internal
high-speed
RAM
Serial
interface CSI10
Key return
POC/LVI
control
8
KR0/P70 to
KR7/P77
8
A/D converter
Reset control
Ring-OSC
INTP0/P120
INTP1/P30 to
INTP4/P33
Power on clear/
low voltage
indicator
4
Interrupt control
System control
RESET
X1
X2
XT1
XT2
Voltage regulator
REGC
INTP5/P16
INTP6/P140
IC
VDD, VSS,
EVDD EVSS (VPP)
Remark
Items in parentheses are available in the µPD78F0124.
User’s Manual U16315EJ2V0UD
27
CHAPTER 1 OUTLINE
1.7 Outline of Functions
(1/2)
Item
Internal
memory
(bytes)
Mask ROM
µPD780121
8K
µPD780122
µPD780123
16 K
24 K
Flash memory
High-speed RAM
512
−
−
32 K
1K
1K
Note
Note
−
Expansion RAM
64 KB
X1 input clock (oscillation frequency)
Ceramic/crystal/external clock oscillation
REGC pin is connected directly to VDD: 10 MHz (VDD = 4.0 to 5.5 V), 8.38 MHz (VDD = 3.3
to 5.5 V), 5 MHz (VDD = 2.7 to 5.5 V)
grade products
1 µF capacitor is connected to REGC pin:
(A1) grade products
µPD78F0124
32 K
Memory space
Standard products, (A)
µPD780124
8.38 MHz (VDD = 4.0 to 5.5 V)
REGC pin is connected directly to VDD: 10 MHz (VDD = 4.5 to 5.5 V), 8.38 MHz (VDD = 4.0
to 5.5 V), 5 MHz (VDD = 3.3 to 5.5 V)
(A2) grade products
REGC pin is connected directly to VDD: 8.38 MHz (VDD = 4.0 to 5.5 V), 5 MHz (VDD = 3.3
to 5.5 V)
Ring-OSC clock
On-chip Ring oscillation (240 kHz (TYP.))
(oscillation frequency)
Subsystem clock
Crystal/external clock oscillation (32.768 kHz)
(oscillation frequency)
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.2 µs/0.4 µs/0.8 µs/1.6 µs/3.2 µs (X1 input clock: @ fXP = 10 MHz operation)
8.3 µs/16.6 µs/33.2 µs/66.4 µs/132.8 µs (TYP.) (Ring-OSC clock: @ fR = 240 kHz (TYP.)
operation)
122 µs (subsystem clock: @ fXT = 32.768 kHz operation)
• 16-bit operation
Instruction set
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
I/O ports
Total:
39
CMOS I/O
26
CMOS input
1
N-ch open-drain I/O
4
• 16-bit timer/event counter: 1 channel
Timers
Timer outputs
Clock output
8
CMOS output
• 8-bit timer/event counter:
2 channels
• 8-bit timer:
2 channels
• Watch timer
1 channel
• Watchdog timer:
1 channel
5 (PWM output: 3)
• 78.125 kHz, 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(X1 input clock: 10 MHz)
• 32.768 kHz (subsystem clock: 32.768 kHz)
A/D converter
10-bit resolution × 8 channels
Note The internal flash memory capacity and internal high-speed RAM capacity can be changed using the internal
memory size switching register (IMS).
28
User’s Manual U16315EJ2V0UD
CHAPTER 1 OUTLINE
(2/2)
µPD780121
Item
µPD780122
µPD780123
• UART mode supporting LIN-bus:
Serial interface
• 3-wire serial I/O mode/UART mode
Vectored interrupt
Internal
15
sources
External
8
µPD780124
µPD78F0124
1 channel
Note
: 1 channel
Key interrupt
Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR7).
Reset
• Reset using RESET pin
• Internal reset by watchdog timer
• Internal reset by clock monitor
• Internal reset by power-on-clear
• Internal reset by low-voltage detector
Supply voltage
Standard products, (A) grade products: VDD = 2.7 to 5.5 V
(A1) grade products, (A2) grade products: VDD = 3.3 to 5.5 V
Operating ambient temperature
• Standard products, (A) grade products: TA = −40 to +85°C
• (A1) grade products: TA = −40 to +110°C (mask ROM versions),
−40 to +105°C (flash memory versions)
• (A2) grade products: TA = −40 to +125°C (mask ROM versions)
• 52-pin plastic LQFP (10 × 10)
Package
Note
Select either of the functions of these alternate-function pins.
An outline of the timer is shown below.
16-Bit Timer/
8-Bit Timer/
8-Bit Timers H0 and
Watch
Watchdog
Event Counter 00
Event Counters
H1
Timer
Timer
50 and 51
TM00
Operation
mode
Function
TM50
TM51
TMH0
TMH1
Note
Interval timer
1 channel
1 channel 1 channel 1 channel 1 channel 1 channel 1 channel
External event counter
1 channel
1 channel 1 channel
−
−
−
−
Timer output
1 output
1 output
1 output
1 output
1 output
−
−
PPG output
1 output
−
−
−
−
−
−
PWM output
−
1 output
1 output
1 output
1 output
−
−
Pulse width measurement
2 inputs
−
−
−
−
−
−
Square-wave output
1 output
1 output
1 output
1 output
1 output
−
−
2
1
1
1
1
1
−
Interrupt source
Note The watch timer function and interval timer function can be used simultaneously.
Remark TM51 and TMH1 can be used in combination as a carrier generator mode.
User’s Manual U16315EJ2V0UD
29
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
There are three types of pin I/O buffer power supplies: AVREF, EVDD, and VDD. The relationship between these
power supplies and the pins is shown below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply
30
Corresponding Pins
AVREF
P20 to P27
EVDD
Port pins other than P20 to P27
VDD
Pins other than port pins
User’s Manual U16315EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
(1) Port pins
Pin Name
P00
I/O
I/O
Port 0.
After Reset
Input
4-bit I/O port.
P01
Alternate Function
TI000
TI010/TO00
Input/output can be specified in 1-bit units.
P02
P03
P10
Function
I/O
Use of an on-chip pull-up resistor can be specified by a
−
software setting.
−
Port 1.
Input
8-bit I/O port.
P11
SI10/RxD0
Input/output can be specified in 1-bit units.
P12
SO10
Use of an on-chip pull-up resistor can be specified by a
P13
SCK10/TxD0
TxD6
software setting.
P14
RxD6
P15
TOH0
P16
TOH1/INTP5
P17
TI50/TO50
P20 to P27
Input
Port 2.
Input
ANI0 to ANI7
Input
INTP1 to INTP3
8-bit input-only port.
P30 to P32
I/O
Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
P33
INTP4/TI51/TO51
Use of an on-chip pull-up resistor can be specified by a
software setting.
P60 to P63
I/O
Port 6.
−
Input
4-bit I/O port (N-ch open drain).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a mask
option only for mask ROM versions.
P70 to P77
I/O
Port 7.
Input
KR0 to KR7
Input
INTP0
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
I/O
Port 12.
1-bit I/O port.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P130
Output
Port 13.
Output
−
1-bit output-only port.
P140
I/O
Port 14.
Input
PCL/INTP6
1-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
User’s Manual U16315EJ2V0UD
31
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins (1/2)
Pin Name
INTP0
I/O
Input
Function
External interrupt request input for which the valid edge (rising
After Reset
P120
Input
edge, falling edge, or both rising and falling edges) can be
INTP1 to INTP3
P30 to P32
specified
INTP4
Alternate Function
P33/TI51/TO51
INTP5
P16/TOH1
INTP6
P140/PCL
SI10
Input
Serial data input to serial interface
Input
P11/RxD0
SO10
Output
Serial data output from serial interface
Input
P12
SCK10
I/O
Clock input/output for serial interface
Input
P10/TxD0
RxD0
Input
Serial data input to asynchronous serial interface
Input
P11/SI10
Output
Serial data output from asynchronous serial interface
Input
P10/SCK10
RxD6
TxD0
P14
TxD6
TI000
P13
Input
External count clock input to 16-bit timer/event counter 00
Input
P00
Capture trigger input to capture registers (CR000, CR010) of
16-bit timer/event counter 00
Capture trigger input to capture register (CR000) of 16-bit
TI010
P01/TO00
timer/event counter 00
TO00
Output
16-bit timer/event counter 00 output
Input
P01/TI010
TI50
Input
External count clock input to 8-bit timer/event counter 50
Input
P17/TO50
TI51
TO50
External count clock input to 8-bit timer/event counter 51
Output
8-bit timer/event counter 50 output
P33/TO51/INTP4
Input
P17/TI50
TO51
8-bit timer/event counter 51 output
P33/TI51/INTP4
TOH0
8-bit timer H0 output
P15
TOH1
8-bit timer H1 output
P16/INTP5
PCL
Output
Clock output (for trimming of X1 input clock, subsystem clock)
Input
P140/INTP6
ANI0 to ANI7
Input
A/D converter analog input
Input
P20 to P27
AVREF
Input
A/D converter reference voltage input and positive power
−
−
−
−
supply for port 2
AVSS
−
A/D converter ground potential. Make the same potential as
EVSS or VSS.
KR0 to KR7
REGC
Input
−
Key interrupt input
Input
Connecting regulator output stabilization capacitor. Connect
P70 to P77
−
−
to VSS via a capacitor (1µF: recommended). To use the CPU
at high speed (fXP = 10 MHz, VDD = 4.0 to 5.5 V), connect this
pin directly to VDD.
RESET
Input
System reset input
−
−
X1
Input
Connecting resonator for X1 input clock
−
−
X2
−
−
−
−
−
−
−
XT1
Input
XT2
−
32
Connecting resonator for subsystem clock
User’s Manual U16315EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins (2/2)
Pin Name
I/O
Function
After Reset
Alternate Function
Positive power supply (except for ports)
−
−
VDD
−
EVDD
−
Positive power supply for ports
−
−
VSS
−
Ground potential (except for ports)
−
−
EVSS
−
Ground potential for ports
−
−
IC
−
Internally connected. Connect directly to EVSS or VSS.
−
−
VPP
−
Flash memory programming mode setting. High-voltage
−
−
application for program write/verify. Connect to EVSS or VSS in
normal operation mode.
User’s Manual U16315EJ2V0UD
33
CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
2.2.1 P00 to P03 (port 0)
P00 to P03 function as a 4-bit I/O port. These pins also function as timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 to P03 function as a 4-bit I/O port. P00 to P03 can be set to input or output in 1-bit units using port mode
register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
(2) Control mode
P00 to P03 function as timer I/O.
(a) TI000
This is the pin for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a
capture trigger signal to the capture registers (CR000, CR010) of 16-bit timer/event counter 00.
(b) TI010
This is the pin for inputting a capture trigger signal to the capture register (CR000) of 16-bit timer/event
counter 00.
(c) TO00
This is a timer output pin.
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial
interface data I/O, clock I/O, and timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode
register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
(2) Control mode
P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
(a) SI10
This is a serial interface serial data input pin.
(b) SO10
This is a serial interface serial data output pin.
(c) SCK10
This is a serial interface serial clock I/O pin.
(d) RxD0, RxD6
These are serial data input pins of the asynchronous serial interface.
34
User’s Manual U16315EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
(e) TxD0, TxD6
These are serial data output pins of the asynchronous serial interface.
(f) TI50
This is a pin for inputting an external count clock to 8-bit timer/event counter 50.
(g) TO50, TOH0, and TOH1
These are timer output pins.
(h) INTP5
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
2.2.3 P20 to P27 (port 2)
P20 to P27 function as an 8-bit input-only port. These pins also function as pins for A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P27 function as an 8-bit input-only port.
(2) Control mode
P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7). When using these pins as analog input
pins, see (5) ANI0/P20 to ANI7/P27 in 12.6 Cautions for A/D Converter.
2.2.4 P30 to P33 (port 3)
P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and
timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode
register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
(2) Control mode
P30 to P33 function as external interrupt request input pins and timer I/O pins.
(a) INTP1 to INTP4
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TI51
This is an external count clock input pin to 8-bit timer/event counter 51.
(c) TO51
This is a timer output pin.
User’s Manual U16315EJ2V0UD
35
CHAPTER 2 PIN FUNCTIONS
2.2.5 P60 to P63 (port 6)
P60 to P63 function as a 4-bit I/O port. P60 to P63 can be set to input port or output port in 1-bit units using port
mode register 6 (PM6).
P60 to P63 are N-ch open-drain pins. Use of an on-chip pull-up resistor can be specified by a mask option only for
mask ROM versions.
2.2.6 P70 to P77 (port 7)
P70 to P77 function as an 8-bit I/O port. These pins also function as key interrupt input pins.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P70 to P77 function as an 8-bit I/O port. P70 to P77 can be set to input or output in 1-bit units using port mode
register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
(2) Control mode
P70 to P77 function as key interrupt input pins.
2.2.7 P120 (port 12)
P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input.
The following operation modes can be specified.
(1) Port mode
P120 functions as a 1-bit I/O port. P120 can be set to input or output using port mode register 12 (PM12). Use of
an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
(2) Control mode
P120 functions as an external interrupt request input pin (INTP0) for which the valid edge (rising edge, falling
edge, or both rising and falling edges) can be specified.
2.2.8 P130 (port 13)
P130 functions as a 1-bit output-only port.
2.2.9 P140 (port 14)
P140 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input and clock
output.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P140 functions as a 1-bit I/O port. P140 can be set to input or output in 1-bit units using port mode register 14
(PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14).
(2) Control mode
P140 functions as external interrupt request input and clock output.
(a) INTP6
This is the external interrupt request input pin for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
36
User’s Manual U16315EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
(b) PCL
This is a clock output pin.
2.2.10 AVREF
This is the A/D converter reference voltage input pin.
When A/D converter is not used, connect this pin to EVDD or VDDNote.
Note Connect port 2 directly to EVDD when it is used as a digital port.
2.2.11 AVSS
This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with
the same potential as the EVSS pin or VSS pin.
2.2.12 RESET
This is the active-low system reset input pin.
2.2.13 REGC
This is the pin for connecting the capacitor for the regulator. When using the regulator, connect this pin to VSS via a
capacitor (1 µF: recommended). When the regulator is not used, connect this pin directly to VDD pin.
Caution A regulator cannot be used with (A1) grade products and (A2) grade products.
Be sure to
connect the REGC pin of these products directly to VDD.
2.2.14 X1 and X2
These are the pins for connecting a resonator for X1 input clock oscillation.
When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin.
2.2.15 XT1 and XT2
These are the pins for connecting a resonator for subsystem clock oscillation.
When supplying an external clock, input a signal to the XT1 pin and input the inverse signal to the XT2 pin.
2.2.16 VDD and EVDD
VDD is the positive power supply pin for other than ports.
EVDD is the positive power supply pin for ports.
2.2.17 VSS and EVSS
VSS is the ground potential pin for other than ports.
EVSS is the ground potential pin for ports.
2.2.18 VPP (flash memory versions only)
This is a pin for flash memory programming mode setting and high-voltage application for program write/verify.
Connect to EVSS or VSS in the normal operation mode.
User’s Manual U16315EJ2V0UD
37
CHAPTER 2 PIN FUNCTIONS
2.2.19 IC (mask ROM versions only)
The IC (Internally Connected) pin is provided to set the test mode to check the 78K0/KD1 at shipment. Connect it
directly to EVSS or VSS pin with the shortest possible wire in the normal operation mode.
When a potential difference is produced between the IC pin and the EVSS or VSS pin because the wiring between
these two pins is too long or external noise is input to the IC pin, the user’s program may not operate normally.
• Connect the IC pin directly to EVSS or VSS pin.
EVSS or VSS
IC
As short as possible
38
User’s Manual U16315EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins.
Refer to Figure 2-1 for the configuration of the I/O circuit of each type.
Table 2-2. Pin I/O Circuit Types
Pin Name
P00/TI000
I/O Circuit Type
8-A
I/O
Recommended Connection of Unused Pins
Input:
I/O
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P01/TI010/TO00
P02
P03
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
5-A
P13/TxD6
P14/RxD6
8-A
P15/TOH0
5-A
P16/TOH1/INTP5
8-A
P17/TI50/TO50
P20/ANI0 to P27/ANI7
9-C
Input
Connect to EVDD or EVSS.
P30/INTP1 to P32/INTP3
8-A
I/O
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P33/TI51/TO51/INTP4
13-S
Input:
P60, P61 (Flash memory version)
13-R
Output: Leave this pin open at low-level output after clearing
P62, P63 (Mask ROM version)
13-V
P62, P63 (Flash memory version)
13-W
P70/KR0 to P77/KR7
8-A
P60, P61 (Mask ROM version)
Connect to EVSS.
the output latch of the port to 0.
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P120/INTP0
P130
3-C
Output
Leave open.
P140/PCL/INTP6
8-A
I/O
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
RESET
2
XT1
16
Connect directly to EVDD or VDD.
−
XT2
AVREF
AVSS
−
Input
−
Leave open.
Connect directly to EVDD or VDD
Note
.
Connect directly to EVSS or VSS.
IC
VPP
Connect directly to EVSS or VSS.
Note Connect port 2 directly to EVDD when it is used as a digital port.
User’s Manual U16315EJ2V0UD
39
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (1/2)
Type 8-A
Type 2
EVDD
Pullup
enable
P-ch
IN
VDD
Data
P-ch
IN/OUT
Schmitt-triggered input with hysteresis characteristics
Output
disable
N-ch
Type 9-C
Type 3-C
EVDD
P-ch
Data
Comparator
P-ch
IN
+
N-ch
–
AVSS
OUT
VREF
(threshold voltage)
N-ch
Input
enable
Type 5-A
Type 13-R
EVDD
Pullup
enable
P-ch
IN/OUT
VDD
Data
Data
Output disable
P-ch
IN/OUT
Output
disable
N-ch
Input
enable
40
User’s Manual U16315EJ2V0UD
N-ch
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (2/2)
Type 13-W
Type 13-S
EVDD
Mask
option
Data
Output disable
IN/OUT
IN/OUT
Data
Output disable
N-ch
N-ch
Input
enable
Middle-voltage input buffer
Type 16
Type 13-V
EVDD
Feedback
cut-off
Mask
option
IN/OUT
Data
Output disable
P-ch
N-ch
XT1
Input
enable
XT2
Middle-voltage input buffer
User’s Manual U16315EJ2V0UD
41
CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
Products in the 78K0/KD1 can each access a 64 KB memory space. Figures 3-1 to 3-5 show the memory maps.
Caution Regardless of the internal memory capacity, the initial value of the internal memory size
switching register (IMS) of all products in the 78K0/KD1 is fixed (IMS = CFH). Therefore, set the
value corresponding to each product as indicated below.
Table 3-1. Set Values of Internal Memory Size Switching Register (IMS)
Internal Memory Size Switching Register (IMS)
42
µPD780121
42H
µPD780122
44H
µPD780123
C6H
µPD780124
C8H
µPD78F0124
Value corresponding to mask ROM version
User’s Manual U16315EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
Figure 3-1. Memory Map (µPD780121)
F F F FH
Special function registers
(SFR)
256 × 8 bits
F F 0 0H
F E F FH
F E E 0H
F E D FH
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
512 × 8 bits
1 F F FH
F D 0 0H
F C F FH
Program area
Data memory
space
1 0 0 0H
0 F F FH
CALLF entry area
Reserved
0 8 0 0H
0 7 F FH
Program area
0 0 8 0H
0 0 7 FH
2 0 0 0H
1 F F FH
Program
memory space
CALLT table area
Internal ROM
8192 × 8 bits
0 0 0 0H
0 0 4 0H
0 0 3 FH
Vector table area
0 0 0 0H
User’s Manual U16315EJ2V0UD
43
CHAPTER 3 CPU ARCHITECTURE
Figure 3-2. Memory Map (µPD780122)
F F F FH
Special function registers
(SFR)
256 × 8 bits
F F 0 0H
F E F FH
F E E 0H
F E D FH
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
512 × 8 bits
3 F F FH
F D 0 0H
F C F FH
Program area
Data memory
space
1 0 0 0H
0 F F FH
CALLF entry area
Reserved
0 8 0 0H
0 7 F FH
Program area
0 0 8 0H
0 0 7 FH
4 0 0 0H
3 F F FH
Program
memory space
CALLT table area
Internal ROM
16384 × 8 bits
0 0 0 0H
44
0 0 4 0H
0 0 3 FH
Vector table area
0 0 0 0H
User’s Manual U16315EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
Figure 3-3. Memory Map (µPD780123)
F F F FH
Special function registers
(SFR)
256 × 8 bits
F F 0 0H
F E F FH
F E E 0H
F E D FH
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
5 F F FH
F B 0 0H
F A F FH
Program area
Data memory
space
1 0 0 0H
0 F F FH
CALLF entry area
Reserved
0 8 0 0H
0 7 F FH
Program area
0 0 8 0H
0 0 7 FH
6 0 0 0H
5 F F FH
Program
memory space
CALLT table area
Internal ROM
24576 × 8 bits
0 0 0 0H
0 0 4 0H
0 0 3 FH
Vector table area
0 0 0 0H
User’s Manual U16315EJ2V0UD
45
CHAPTER 3 CPU ARCHITECTURE
Figure 3-4. Memory Map (µPD780124)
F F F FH
Special function registers
(SFR)
256 × 8 bits
F F 0 0H
F E F FH
F E E 0H
F E D FH
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
7 F F FH
F B 0 0H
F A F FH
Program area
Data memory
space
1 0 0 0H
0 F F FH
CALLF entry area
Reserved
0 8 0 0H
0 7 F FH
Program area
0 0 8 0H
0 0 7 FH
8 0 0 0H
7 F F FH
Program
memory space
CALLT table area
Internal ROM
32768 × 8 bits
0 0 0 0H
46
0 0 4 0H
0 0 3 FH
Vector table area
0 0 0 0H
User’s Manual U16315EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
Figure 3-5. Memory Map (µPD78F0124)
F F F FH
Special function registers
(SFR)
256 × 8 bits
F F 0 0H
F E F FH
F E E 0H
F E D FH
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
7 F F FH
F B 0 0H
F A F FH
Program area
Data memory
space
1 0 0 0H
0 F F FH
CALLF entry area
Reserved
0 8 0 0H
0 7 F FH
Program area
0 0 8 0H
0 0 7 FH
8 0 0 0H
7 F F FH
Program
memory space
CALLT table area
Flash memory
32768 × 8 bits
0 0 0 0H
0 0 4 0H
0 0 3 FH
Vector table area
0 0 0 0H
User’s Manual U16315EJ2V0UD
47
CHAPTER 3 CPU ARCHITECTURE
3.1.1 Internal program memory space
The internal program memory space stores the program and table data. Normally, it is addressed with the program
counter (PC).
78K0/KD1 products incorporate internal ROM (mask ROM or flash memory), as shown below.
Table 3-2. Internal ROM Capacity
Part Number
Internal ROM
Structure
µPD780121
Capacity
8192 × 8 bits (0000H to 1FFFH)
Mask ROM
µPD780122
16384 × 8 bits (0000H to 3FFFH)
µPD780123
24576 × 8 bits (0000H to 5FFFH)
µPD780124
32768 × 8 bits (0000H to 7FFFH)
µPD78F0124
Flash memory
The internal program memory space is divided into the following areas.
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch
upon reset signal input or generation of each interrupt request are stored in the vector table area.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd
addresses.
Table 3-3. Vector Table
Vector Table Address
Interrupt Source
Vector Table Address
Interrupt Source
RESET input, POC, LVI,
001AH
INTTMH1
clock monitor, WDT
001CH
INTTMH0
0004H
INTLVI
001EH
INTTM50
0006H
INTP0
0020H
INTTM000
0008H
INTP1
0022H
INTTM010
000AH
INTP2
0024H
INTAD
000CH
INTP3
0026H
INTSR0
000EH
INTP4
0028H
INTWTI
0010H
INTP5
002AH
INTTM51
0012H
INTSRE6
002CH
INTKR
0014H
INTSR6
002EH
INTWT
0016H
INTST6
0030H
INTP6
0018H
INTCSI10/INTST0
0000H
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
48
User’s Manual U16315EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
3.1.2 Internal data memory space
78K0/KD1 products incorporate the following internal high-speed RAMs.
Table 3-4. Internal High-Speed RAM Capacity
Part Number
µPD780121
Internal High-Speed RAM
512 × 8 bits (FD00H to FEFFH)
µPD780122
µPD780123
1024 × 8 bits (FB00H to FEFFH)
µPD780124
µPD78F0124
The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit
registers per one bank.
This area cannot be used as a program area in which instructions are written and executed.
The internal high-speed RAM can also be used as a stack memory.
3.1.3 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to
Table 3-5 Special Function Register List in 3.2.3 Special Function Registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
User’s Manual U16315EJ2V0UD
49
CHAPTER 3 CPU ARCHITECTURE
3.1.4 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of
the register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
78K0/KD1, based on operability and other considerations. For areas containing data memory in particular, special
addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are
available for use. Figures 3-6 to 3-10 show correspondence between data memory and addressing. For details of
each addressing mode, refer to 3.4 Operand Address Addressing.
Figure 3-6. Correspondence Between Data Memory and Addressing (µPD780121)
F F F FH
Special function registers (SFR)
256 × 8 bits
SFR addressing
F F 2 0H
F F 1 FH
F F 0 0H
F E F FH
F E E 0H
F E D FH
General-purpose registers
32 × 8 bits
Register addressing
Short direct
addressing
Internal high-speed RAM
512 × 8 bits
F E 2 0H
F E 1 FH
F D 0 0H
F C F FH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
2 0 0 0H
1 F F FH
Internal ROM
8192 × 8 bits
0 0 0 0H
50
User’s Manual U16315EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
Figure 3-7. Correspondence Between Data Memory and Addressing (µPD780122)
F F F FH
Special function registers (SFR)
256 × 8 bits
SFR addressing
F F 2 0H
F F 1 FH
F F 0 0H
F E F FH
F E E 0H
F E D FH
General-purpose registers
32 × 8 bits
Register addressing
Short direct
addressing
Internal high-speed RAM
512 × 8 bits
F E 2 0H
F E 1 FH
F D 0 0H
F C F FH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
4 0 0 0H
3 F F FH
Internal ROM
16384 × 8 bits
0 0 0 0H
User’s Manual U16315EJ2V0UD
51
CHAPTER 3 CPU ARCHITECTURE
Figure 3-8. Correspondence Between Data Memory and Addressing (µPD780123)
F F F FH
Special function registers (SFR)
256 × 8 bits
SFR addressing
F F 2 0H
F F 1 FH
F F 0 0H
F E F FH
F E E 0H
F E D FH
General-purpose registers
32 × 8 bits
Register addressing
Short direct
addressing
Internal high-speed RAM
1024 × 8 bits
F E 2 0H
F E 1 FH
F B 0 0H
F A F FH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
6 0 0 0H
5 F F FH
Internal ROM
24576 × 8 bits
0 0 0 0H
52
User’s Manual U16315EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
Figure 3-9. Correspondence Between Data Memory and Addressing (µPD780124)
F F F FH
Special function registers (SFR)
256 × 8 bits
SFR addressing
F F 2 0H
F F 1 FH
F F 0 0H
F E F FH
F E E 0H
F E D FH
General-purpose registers
32 × 8 bits
Register addressing
Short direct
addressing
Internal high-speed RAM
1024 × 8 bits
F E 2 0H
F E 1 FH
F B 0 0H
F A F FH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
8 0 0 0H
7 F F FH
Internal ROM
32768 × 8 bits
0 0 0 0H
User’s Manual U16315EJ2V0UD
53
CHAPTER 3 CPU ARCHITECTURE
Figure 3-10. Correspondence Between Data Memory and Addressing (µPD78F0124)
F F F FH
Special function registers (SFR)
256 × 8 bits
SFR addressing
F F 2 0H
F F 1 FH
F F 0 0H
F E F FH
F E E 0H
F E D FH
General-purpose registers
32 × 8 bits
Register addressing
Short direct
addressing
Internal high-speed RAM
1024 × 8 bits
F E 2 0H
F E 1 FH
F B 0 0H
F A F FH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
8 0 0 0H
7 F F FH
Flash memory
32768 × 8 bits
0 0 0 0H
54
User’s Manual U16315EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
3.2 Processor Registers
The 78K0/KD1 products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-11. Format of Program Counter
15
PC
0
PC15 PC14 PC13 PC12 PC11 PC10 PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions.
RESET input sets the PSW to 02H.
Figure 3-12. Format of Program Status Word
7
PSW
IE
0
Z
RBS1
AC
RBS0
0
ISP
CY
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupts are disabled. Other
interrupt requests are all disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgement is
controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgement and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
User’s Manual U16315EJ2V0UD
55
CHAPTER 3 CPU ARCHITECTURE
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction
execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, lowlevel vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H)
(refer to 16.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L)) can not be acknowledged.
Actual request acknowledgement is controlled by the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit operation instruction
execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
Figure 3-13. Format of Stack Pointer
15
SP
0
SP15 SP14 SP13 SP12 SP11 SP10 SP9
SP8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from
the stack memory.
Each stack operation saves/restores data as shown in Figures 3-14 and 3-15.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before using
the stack.
56
User’s Manual U16315EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
Figure 3-14. Data to Be Saved to Stack Memory
(a) PUSH rp instruction (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
Register pair higher
FEDEH
Register pair lower
(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
PC15 to PC8
FEDEH
PC7 to PC0
(c) Interrupt, BRK instructions (when SP = FEE0H)
SP
SP
FEE0H
FEDDH
FEE0H
FEDFH
PSW
FEDEH
PC15 to PC8
FEDDH
PC7 to PC0
User’s Manual U16315EJ2V0UD
57
CHAPTER 3 CPU ARCHITECTURE
Figure 3-15. Data to Be Restored from Stack Memory
(a) POP rp instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
Register pair higher
FEDEH
Register pair lower
(b) RET instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
PC15 to PC8
FEDEH
PC7 to PC0
(c) RETI, RETB instructions (when SP = FEDDH)
SP
SP
58
FEE0H
FEDDH
FEE0H
FEDFH
PSW
FEDEH
PC15 to PC8
FEDDH
PC7 to PC0
User’s Manual U16315EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory.
The
general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register
(AX, BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of
the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupts for each bank.
Figure 3-16. Configuration of General-Purpose Registers
(a) Absolute name
16-bit processing
8-bit processing
FEFFH
R7
BANK0
RP3
R6
FEF8H
R5
BANK1
RP2
R4
FEF0H
R3
RP1
BANK2
R2
FEE8H
R1
RP0
BANK3
R0
FEE0H
15
0
7
0
(b) Function name
16-bit processing
8-bit processing
FEFFH
H
BANK0
HL
L
FEF8H
D
BANK1
DE
E
FEF0H
B
BC
BANK2
C
FEE8H
A
AX
BANK3
X
FEE0H
15
User’s Manual U16315EJ2V0UD
0
7
0
59
CHAPTER 3 CPU ARCHITECTURE
3.2.3 Special Function Registers (SFRs)
Unlike a general-purpose register, each special function register has a special function.
SFRs are allocated to the FF00H to FFFFH area.
Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit
manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When specifying an address, describe an even address.
Table 3-5 gives a list of the special function registers. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined
by the header file “sfrbit.h” in the CC78K0. When using the RA78K0, ID78K0-NS, ID78K0, or SM78K0, symbols
can be written as an instruction operand.
• R/W
Indicates whether the corresponding special function register can be read or written.
R/W: Read/write enable
R:
Read only
W:
Write only
• Manipulatable bit units
Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon RESET input.
60
User’s Manual U16315EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
Table 3-5. Special Function Register List (1/3)
Address
Special Function Register (SFR) Name
Symbol
R/W
After
Manipulatable Bit Unit
1 Bit
8 Bits
16 Bits
Reset
FF00H
Port register 0
P0
R/W
√
√
−
00H
FF01H
Port register 1
P1
R/W
√
√
−
00H
FF02H
Port register 2
P2
R
√
√
−
Undefined
FF03H
Port register 3
P3
R/W
√
√
−
00H
FF06H
Port register 6
P6
R/W
√
√
−
00H
FF07H
Port register 7
P7
R/W
√
√
−
00H
FF08H
A/D conversion result register
ADCR
R
−
−
√
Undefined
FF0AH
Receive buffer register 6
RXB6
R
−
√
−
FFH
FF0BH
Transmit buffer register 6
TXB6
R/W
−
√
−
FFH
FF0CH
Port register 12
P12
R/W
√
√
−
00H
FF0DH
Port register 13
P13
R/W
√
√
−
00H
FF0EH
Port register 14
P14
R/W
√
√
−
00H
FF0FH
Serial I/O shift register 10
SIO10
R
−
√
−
00H
FF10H
16-bit timer counter 00
TM00
R
−
−
√
0000H
16-bit timer capture/compare register 000
CR000
R/W
−
−
√
0000H
16-bit timer capture/compare register 010
CR010
R/W
−
−
√
0000H
FF16H
8-bit timer counter 50
TM50
R
−
√
−
00H
FF17H
8-bit timer compare register 50
CR50
R/W
−
√
−
00H
FF18H
8-bit timer H compare register 00
CMP00
R/W
−
√
−
00H
FF19H
8-bit timer H compare register 10
CMP10
R/W
−
√
−
00H
FF1AH
8-bit timer H compare register 01
CMP01
R/W
−
√
−
00H
FF1BH
8-bit timer H compare register 11
CMP11
R/W
−
√
−
00H
FF1FH
8-bit timer counter 51
TM51
R
−
√
−
00H
FF20H
Port mode register 0
PM0
R/W
√
√
−
FFH
FF21H
Port mode register 1
PM1
R/W
√
√
−
FFH
FF23H
Port mode register 3
PM3
R/W
√
√
−
FFH
FF26H
Port mode register 6
PM6
R/W
√
√
−
FFH
FF27H
Port mode register 7
PM7
R/W
√
√
−
FFH
FF28H
A/D converter mode register
ADM
R/W
√
√
−
00H
FF29H
Analog input channel specification register
ADS
R/W
√
√
−
00H
FF2AH
Power-fail comparison mode register
PFM
R/W
√
√
−
00H
FF2BH
Power-fail comparison threshold register
PFT
R/W
−
√
−
00H
FF2CH
Port mode register 12
PM12
R/W
√
√
−
FFH
FF2EH
Port mode register 14
PM14
R/W
√
√
−
FFH
FF30H
Pull-up resistor option register 0
PU0
R/W
√
√
−
00H
FF31H
Pull-up resistor option register 1
PU1
R/W
√
√
−
00H
FF09H
FF11H
FF12H
FF13H
FF14H
FF15H
User’s Manual U16315EJ2V0UD
61
CHAPTER 3 CPU ARCHITECTURE
Table 3-5. Special Function Register List (2/3)
Address
Special Function Register (SFR) Name
Symbol
R/W
After
Manipulatable Bit Unit
1 Bit
8 Bits
16 Bits
Reset
FF33H
Pull-up resistor option register 3
PU3
R/W
√
√
−
00H
FF37H
Pull-up resistor option register 7
PU7
R/W
√
√
−
00H
FF3CH
Pull-up resistor option register 12
PU12
R/W
√
√
−
00H
FF3EH
Pull-up resistor option register 14
PU14
R/W
√
√
−
00H
FF40H
Clock output selection register
CKS
R/W
√
√
−
00H
FF41H
8-bit timer compare register 51
CR51
R/W
−
√
−
00H
FF43H
8-bit timer mode control register 51
TMC51
R/W
√
√
−
00H
FF48H
External interrupt rising edge enable register
EGP
R/W
√
√
−
00H
FF49H
External interrupt falling edge enable register
EGN
R/W
√
√
−
00H
FF4FH
Input switch control register
ISC
R/W
√
√
−
00H
FF50H
Asynchronous serial interface operation mode
ASIM6
R/W
√
√
−
01H
ASIS6
R
−
√
−
00H
ASIF6
R
−
√
−
00H
register 6
FF53H
Asynchronous serial interface reception error
status register 6
FF55H
Asynchronous serial interface transmission
status register 6
FF56H
Clock selection register 6
CKSR6
R/W
−
√
−
00H
FF57H
Baud rate generator control register 6
BRGC6
R/W
−
√
−
FFH
FF58H
Asynchronous serial interface control register 6
ASICL6
R/W
√
√
−
16H
FF69H
8-bit timer H mode register 0
TMHMD0
R/W
√
√
−
00H
FF6AH
Timer clock selection register 50
TCL50
R/W
−
√
−
00H
FF6BH
8-bit timer mode control register 50
TMC50
R/W
√
√
−
00H
FF6CH
8-bit timer H mode register 1
TMHMD1
R/W
√
√
−
00H
FF6DH
8-bit timer H carrier control register 1
TMCYC1
R/W
√
√
−
00H
FF6EH
Key return mode register
KRM
R/W
√
√
−
00H
FF6FH
Watch timer operation mode register
WTM
R/W
√
√
−
00H
FF70H
Asynchronous serial interface operation mode
ASIM0
R/W
√
√
−
01H
register 0
FF71H
Baud rate generator control register 0
BRGC0
R/W
−
√
−
1FH
FF72H
Receive buffer register 0
RXB0
R
−
√
−
FFH
FF73H
Asynchronous serial interface reception error
ASIS0
R
−
√
−
00H
W
−
√
−
FFH
status register 0
FF74H
Transmit shift register 0
TXS0
FF80H
Serial operation mode register 10
CSIM10
R/W
√
√
−
00H
FF81H
Serial clock selection register 10
CSIC10
R/W
√
√
−
00H
FF84H
Transmit buffer register 10
SOTB10
R/W
−
√
−
Undefined
FF8CH
Timer clock selection register 51
TCL51
R/W
−
√
−
00H
FF98H
Watchdog timer mode register
WDTM
R/W
−
√
−
67H
FF99H
Watchdog timer enable register
WDTE
R/W
−
√
−
9AH
FFA0H
Ring-OSC mode register
RCM
R/W
√
√
−
00H
FFA1H
Main clock mode register
MCM
R/W
√
√
−
00H
62
User’s Manual U16315EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
Table 3-5. Special Function Register List (3/3)
Address
Special Function Register (SFR) Name
Symbol
MOC
R/W
After
Manipulatable Bit Unit
1 Bit
8 Bits
16 Bits
Reset
R/W
√
√
−
00H
R
√
√
−
00H
FFA2H
Main OSC control register
FFA3H
Oscillation stabilization time counter status register OSTC
FFA4H
Oscillation stabilization time select register
OSTS
R/W
−
√
−
05H
FFA9H
Clock monitor mode register
CLM
R/W
√
√
−
00H
FFACH
Reset control flag register
RESF
R
−
√
−
FFBAH
16-bit timer mode control register 00
TMC00
R/W
√
√
−
00H
FFBBH
Prescaler mode register 00
PRM00
R/W
√
√
−
00H
FFBCH
Capture/compare control register 00
CRC00
R/W
√
√
−
00H
FFBDH
16-bit timer output control register 00
TOC00
R/W
√
√
−
00H
FFBEH
Low-voltage detection register
LVIM
R/W
√
√
−
00H
FFBFH
Low-voltage detection level selection register
LVIS
R/W
−
√
−
00H
FFE0H
Interrupt request flag register 0L
IF0
IF0L
R/W
√
√
√
00H
FFE1H
Interrupt request flag register 0H
IF0H
R/W
√
√
FFE2H
Interrupt request flag register 1L
IF1L
R/W
√
√
−
00H
FFE4H
Interrupt mask flag register 0L
MK0
MK0L R/W
√
√
√
FFH
FFE5H
Interrupt mask flag register 0H
MK0H R/W
√
√
FFE6H
Interrupt mask flag register 1L
MK1L
FFE8H
Priority specification flag register 0L
PR0
FFE9H
Priority specification flag register 0H
FFEAH
Priority specification flag register 1L
FFF0H
Internal memory size switching register
FFFBH
Processor clock control register
Notes 1.
2.
Note 2
Note 1
00H
00H
FFH
R/W
√
√
−
FFH
PR0L R/W
√
√
√
FFH
PR0H R/W
√
√
PR1L
R/W
√
√
−
FFH
IMS
R/W
−
√
−
CFH
PCC
R/W
√
√
−
00H
FFH
This value varies depending on the reset source.
The initial value of IMS is fixed (IMS = CFH) in all products in the 78K0/KD1 regardless of the internal
memory capacity. Therefore, set the following value to each product.
Internal Memory Size Switching Register (IMS)
µPD780121
42H
µPD780122
44H
µPD780123
C6H
µPD780124
C8H
µPD78F0124
Value corresponding to mask ROM version
User’s Manual U16315EJ2V0UD
63
CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each
byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is
executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by
the following addressing (for details of instructions, refer to 78K/0 Series Instructions User’s Manual (U12326E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched.
The
displacement value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.
In other words, relative addressing consists of relative branching from the start address of the following
instruction to the −128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
0
... PC indicates the start address
of the instruction after the BR instruction.
PC
+
8
15
α
7
6
0
S
jdisp8
15
0
PC
When S = 0, all bits of α are 0.
When S = 1, all bits of α are 1.
64
User’s Manual U16315EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11
instruction is branched to the 0800H to 0FFFH area.
[Illustration]
In the case of CALL !addr16 and BR !addr16 instructions
7
0
CALL or BR
Low Addr.
High Addr.
15
8 7
0
PC
In the case of CALLF !addr11 instruction
7 6
4
3
0
CALLF
fa10–8
fa7–0
15
PC
0
11 10
0
0
0
8 7
0
1
User’s Manual U16315EJ2V0UD
65
CHAPTER 3 CPU ARCHITECTURE
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operation code are transferred to the program counter (PC) and branched.
This function is carried out when the CALLT [addr5] instruction is executed.
This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to
the entire memory space.
[Illustration]
7
Operation code
6
1
5
1
1
ta4–0
1
15
Effective address
0
7
0
0
0
0
0
0
0
Memory (Table)
8
7
6
0
0
1
5
1 0
0
0
Low Addr.
High Addr.
Effective address+1
8
15
7
0
PC
3.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
rp
0
7
A
15
X
8
7
PC
66
0
User’s Manual U16315EJ2V0UD
0
CHAPTER 3 CPU ARCHITECTURE
3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.4.1 Implied addressing
[Function]
The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically
(implicitly) addressed.
Of the 78K0/KD1 instruction words, the following instructions employ implied addressing.
Instruction
Register to Be Specified by Implied Addressing
MULU
A register for multiplicand and AX register for product storage
DIVUW
AX register for dividend and quotient storage
ADJBA/ADJBS
A register for storage of numeric values that become decimal correction targets
ROR4/ROL4
A register for storage of digit data that undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format is
necessary.
[Description example]
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
User’s Manual U16315EJ2V0UD
67
CHAPTER 3 CPU ARCHITECTURE
3.4.2 Register addressing
[Function]
The general-purpose register to be specified is accessed as an operand with the register bank select flags
(RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
rp
AX, BC, DE, HL
‘r’ and ‘rp’ can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; when selecting C register as r
Operation code
0
1
1
0
0
0
1
0
Register specify code
INCW DE; when selecting DE register pair as rp
Operation code
1
0
0
0
0
1
0
0
Register specify code
68
User’s Manual U16315EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
3.4.3 Direct addressing
[Function]
The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an
operand address.
[Operand format]
Identifier
Description
addr16
Label or 16-bit immediate data
[Description example]
MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code
1
0
0
0
1
1
1
0
OP code
0
0
0
0
0
0
0
0
00H
1
1
1
1
1
1
1
0
FEH
[Illustration]
7
0
OP code
addr16 (lower)
addr16 (upper)
Memory
User’s Manual U16315EJ2V0UD
69
CHAPTER 3 CPU ARCHITECTURE
3.4.4
Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers
(SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter
are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to
1FH, bit 8 is set to 1. Refer to the [Illustration].
[Operand format]
Identifier
Description
saddr
Immediate data that indicate label or FE20H to FF1FH
saddrp
Immediate data that indicate label or FE20H to FF1FH (even address only)
[Description example]
MOV 0FE30H, A; when transferring value of A register to saddr (FE30H)
Operation code
1
1
1
1
0
0
1
0
OP code
0
0
1
1
0
0
0
0
30H (saddr-offset)
[Illustration]
7
0
OP code
saddr-offset
Short direct memory
8 7
15
Effective address
1
1
1
1
1
1
1
α
When 8-bit immediate data is 20H to FFH, α = 0
When 8-bit immediate data is 00H to 1FH, α = 1
70
User’s Manual U16315EJ2V0UD
0
CHAPTER 3 CPU ARCHITECTURE
3.4.5 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier
Description
sfr
Special function register name
sfrp
16-bit manipulatable special function register name (even address
only)
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code
1
1
1
1
0
1
1
0
OP code
0
0
1
0
0
0
0
0
20H (sfr-offset)
[Illustration]
7
0
OP code
sfr-offset
SFR
8 7
15
Effective address
1
1
1
1
1
1
1
0
1
User’s Manual U16315EJ2V0UD
71
CHAPTER 3 CPU ARCHITECTURE
3.4.6 Register indirect addressing
[Function]
Register pair contents specified by a register pair specify code in an instruction word and by a register bank
select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be
carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[DE], [HL]
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code
1
0
0
0
0
1
0
1
[Illustration]
16
DE
8 7
D
0
E
7
Memory
The contents of the memory
addressed are transferred.
7
0
A
72
User’s Manual U16315EJ2V0UD
0
The memory address
specified with the
register pair DE
CHAPTER 3 CPU ARCHITECTURE
3.4.7 Based addressing
[Function]
8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in
the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address
the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from
the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
−
Description
[HL + byte]
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code
1
0
1
0
1
1
1
0
0
0
0
1
0
0
0
0
[Illustration]
16
HL
8 7
H
0
L
7
Memory
0
+10
The contents of the memory
addressed are transferred.
7
0
A
User’s Manual U16315EJ2V0UD
73
CHAPTER 3 CPU ARCHITECTURE
3.4.8 Based indexed addressing
[Function]
The B or C register contents specified in an instruction word are added to the contents of the base register, that
is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the
sum is used to address the memory. Addition is performed by expanding the B or C register contents as a
positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the
memory spaces.
[Operand format]
Identifier
−
Description
[HL + B], [HL + C]
[Description example]
In the case of MOV A, [HL + B] (selecting B register)
Operation code
1
0
1
0
1
0
1
1
[Illustration]
16
HL
8
7
0
L
H
+
7
0
B
7
Memory
The contents of the memory
addressed are transferred.
7
0
A
74
User’s Manual U16315EJ2V0UD
0
CHAPTER 3 CPU ARCHITECTURE
3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call and return
instructions are executed or the register is saved/reset upon generation of an interrupt request.
With stack addressing, only the internal high-speed RAM area can be accessed.
[Description example]
In the case of PUSH DE (saving DE register)
Operation code
1
0
1
1
0
1
0
1
[Illustration]
7
SP
SP
FEE0H
FEDEH
Memory
0
FEE0H
FEDFH
D
FEDEH
E
User’s Manual U16315EJ2V0UD
75
CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
There are two types of pin I/O buffer power supplies: AVREF and EVDD. The relationship between these power
supplies and the pins is shown below.
Table 4-1. Pin I/O Buffer Power Supplies
Power Supply
Corresponding Pins
AVREF
P20 to P27
EVDD
Port pins other than P20 to P27
78K0/KD1 products are provided with the ports shown in Figure 4-1, which enable variety of control operations.
The functions of each port are shown in Table 4-2.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the
alternate functions, refer to CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Types
P30
P00
P33
P03
P60
P10
Port 3
Port 0
Port 6
P63
Port 1
P70
P17
Port 7
P20
P77
76
Port 12
P120
Port 13
P130
Port 14
P140
Port 2
P27
User’s Manual U16315EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
Table 4-2. Port Functions
Pin Name
P00
I/O
I/O
Port 0.
After Reset
Input
4-bit I/O port.
P01
Alternate Function
TI000
TI010/TO00
Input/output can be specified in 1-bit units.
P02
P03
P10
Function
I/O
Use of an on-chip pull-up resistor can be specified by a
−
software setting.
−
Port 1.
Input
8-bit I/O port.
P11
SI10/RxD0
Input/output can be specified in 1-bit units.
P12
SO10
Use of an on-chip pull-up resistor can be specified by a
P13
SCK10/TxD0
TxD6
software setting.
P14
RxD6
P15
TOH0
P16
TOH1/INTP5
P17
TI50/TO50
P20 to P27
Input
Port 2.
Input
ANI0 to ANI7
Input
INTP1 to INTP3
8-bit input-only port.
P30 to P32
I/O
Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
P33
Use of an on-chip pull-up resistor can be specified by a
INTP4/TI51/TO51
software setting.
P60 to P63
I/O
Port 6.
−
Input
4-bit I/O port (N-ch open drain).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a mask
option only for mask ROM versions.
P70 to P77
I/O
Port 7.
Input
KR0 to KR7
Input
INTP0
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
I/O
Port 12.
1-bit I/O port.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P130
Output
Port 13.
Output
−
1-bit output-only port.
P140
I/O
Port 14.
Input
PCL/INTP6
1-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
User’s Manual U16315EJ2V0UD
77
CHAPTER 4 PORT FUNCTIONS
4.2 Port Configuration
Ports include the following hardware.
Table 4-3. Port Configuration
Item
Control registers
Configuration
Port mode register (PM0, PM1, PM3, PM6, PM7, PM12, PM14)
Port register (P0 to P3, P6, P7, P12 to P14)
Pull-up resistor option register (PU0, PU1, PU3, PU7, PU12, PU14)
Port
Total: 39 (CMOS I/O: 26, CMOS input: 8, CMOS output: 1, N-ch open drain I/O: 4)
Pull-up resistor
• Mask ROM version
Total: 30 (software control: 26, mask option specification: 4)
• Flash memory version: Total: 26
78
User’s Manual U16315EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
4.2.1 Port 0
Port 0 is a 4-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units
using port mode register 0 (PM0). When the P00 to P03 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
This port can also be used for timer I/O.
RESET input sets port 0 to input mode.
Figures 4-2 to 4-4 show block diagrams of port 0.
Figure 4-2. Block Diagram of P00 and P03
EVDD
WRPU
PU0
PU00, PU03
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P00, P03)
P00/TI000,
P03
WRPM
PM0
PM00, PM03
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
RD:
Read signal
WR××: Write signal
User’s Manual U16315EJ2V0UD
79
CHAPTER 4 PORT FUNCTIONS
Figure 4-3. Block Diagram of P01
EVDD
WRPU
PU0
PU01
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P01)
P01/TI010/TO00
WRPM
PM0
PM01
Alternate
function
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
RD:
Read signal
WR××: Write signal
80
User’s Manual U16315EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
Figure 4-4. Block Diagram of P02
EVDD
WRPU
PU0
PU02
P-ch
Internal bus
Selector
RD
WRPORT
Output latch
(P02)
P02
WRPM
PM0
PM02
Alternate
function
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
RD:
Read signal
WR××: Write signal
User’s Manual U16315EJ2V0UD
81
CHAPTER 4 PORT FUNCTIONS
4.2.2 Port 1
Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units
using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up
resistor can be specified 1-bit units by pull-up resistor option register 1 (PU1).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
RESET input sets port 1 to input mode.
Figures 4-5 to 4-9 show block diagrams of port 1.
Caution When P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 are used as general-purpose ports, do not
write to serial clock selection register 10 (CSIC10).
Figure 4-5. Block Diagram of P10
EVDD
WRPU
PU1
PU10
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P10)
P10/SCK10/TxD0
WRPM
PM1
PM10
Alternate
function
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
82
User’s Manual U16315EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
Figure 4-6. Block Diagram of P11 and P14
EVDD
WRPU
PU1
PU11, PU14
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P11, P14)
P11/SI10/RxD0,
P14/RxD6
WRPM
PM1
PM11, PM14
PU1:
Pull-up resistor option register 1
PM1: Port mode register 1
RD:
Read signal
WR××: Write signal
User’s Manual U16315EJ2V0UD
83
CHAPTER 4 PORT FUNCTIONS
Figure 4-7. Block Diagram of P12 and P15
EVDD
WRPU
PU1
PU12, PU15
P-ch
Internal bus
Selector
RD
WRPORT
Output latch
(P12, P15)
P12/SO10,
P15/TOH0
WRPM
PM1
PM12, PM15
Alternate
function
PU1:
Pull-up resistor option register 1
PM1: Port mode register 1
RD:
Read signal
WR××: Write signal
84
User’s Manual U16315EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
Figure 4-8. Block Diagram of P13
EVDD
WRPU
PU1
PU13
P-ch
Selector
Internal bus
RD
WRPORT
Output latch
(P13)
P13/TxD6
WRPM
PM1
PM13
Alternate
function
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
User’s Manual U16315EJ2V0UD
85
CHAPTER 4 PORT FUNCTIONS
Figure 4-9. Block Diagram of P16 and P17
EVDD
WRPU
PU1
PU16, PU17
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P16, P17)
P16/TOH1/INTP5,
P17/TI50/TO50
WRPM
PM1
PM16, PM17
Alternate
function
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
86
User’s Manual U16315EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
4.2.3 Port 2
Port 2 is an 8-bit input-only port.
This port can also be used for A/D converter analog input.
Figure 4-10 shows a block diagram of port 2.
Figure 4-10. Block Diagram of P20 to P27
Internal bus
RD
A/D converter
RD:
P20/ANI0 to P27/ANI7
Read signal
User’s Manual U16315EJ2V0UD
87
CHAPTER 4 PORT FUNCTIONS
4.2.4 Port 3
Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units
using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified in
1-bit units by pull-up resistor option register 3 (PU3).
This port can also be used for external interrupt request input.
RESET input sets port 3 to input mode.
Figures 4-11 and 4-12 show block diagrams of port 3.
Figure 4-11. Block Diagram of P30 to P32
EVDD
WRPU
PU3
PU30 to PU32
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P30 to P32)
P30/INTP1 to
P32/INTP3
WRPM
PM3
PM30 to PM32
PU3:
Pull-up resistor option register 3
PM3:
Port mode register 3
RD:
Read signal
WR××: Write signal
88
User’s Manual U16315EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
Figure 4-12. Block Diagram of P33
EVDD
WRPU
PU3
PU33
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P33)
P33/INTP4/TI51/TO51
WRPM
PM3
PM33
Alternate
function
PU3:
Pull-up resistor option register 3
PM3:
Port mode register 3
RD:
Read signal
WR××: Write signal
User’s Manual U16315EJ2V0UD
89
CHAPTER 4 PORT FUNCTIONS
4.2.5 Port 6
Port 6 is a 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units
using port mode register 6 (PM6).
This port has the following functions for pull-up resistors. These functions differ depending on whether the product
is a mask ROM version or a flash memory version.
Table 4-4. Pull-up Resistor of Port 6
Pins P60 to P63
An on-chip pull-up resistor can be
Mask ROM version
specified in 1-bit units by mask option
Flash memory version
On-chip pull-up resistors are not provided
The P60 to P63 pins are N-ch open-drain pins.
RESET input sets port 6 to input mode.
Figure 4-13 shows a block diagram of port 6.
Figure 4-13. Block Diagram of P60 to P63
EVDD
Mask option resistor
RD
Internal bus
Selector
WRPORT
Output latch
(P60 to P63)
WRPM
P60 to P63
PM6
PM60 to PM63
PM6:
Port mode register 6
RD:
Read signal
WR××: Write signal
90
Mask ROM versions only
No pull-up resistor for
flash memory versions
User’s Manual U16315EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
4.2.6 Port 7
Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units
using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7).
This port can also be used for key return input.
RESET input sets port 7 to input mode.
Figure 4-14 shows a block diagram of port 7.
Figure 4-14. Block Diagram of P70 to P77
EVDD
WRPU
PU7
PU70 to PU77
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P70 to P77)
P70/KR0 to
P77/KR7
WRPM
PM7
PM70 to PM77
PU7:
Pull-up resistor option register 7
PM7:
Port mode register 7
RD:
Read signal
WR××: Write signal
User’s Manual U16315EJ2V0UD
91
CHAPTER 4 PORT FUNCTIONS
4.2.7 Port 12
Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units
using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified
by pull-up resistor option register 12 (PU12).
This port can also be used for external interrupt input.
RESET input sets port 12 to input mode.
Figure 4-15 shows a block diagram of port 12.
Figure 4-15. Block Diagram of P120
EVDD
WRPU
PU12
PU120
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P120)
P120/INTP0
WRPM
PM12
PM120
PU12:
Pull-up resistor option register 12
PM12: Port mode register 12
RD:
Read signal
WR××: Write signal
92
User’s Manual U16315EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
4.2.8 Port 13
Port 13 is a 1-bit output-only port.
Figure 4-16 shows a block diagram of port 13.
Figure 4-16. Block Diagram of P130
Internal bus
RD
WRPORT
Output latch
(P130)
RD:
P130
Read signal
WD××: Write signal
Remark
When reset is effected, P130 outputs a low level. If P130 is set to output a high level immediately after
reset is released, the output signal of P130 can be dummy-output as the reset signal to the CPU.
User’s Manual U16315EJ2V0UD
93
CHAPTER 4 PORT FUNCTIONS
4.2.9 Port 14
Port 14 is a 1-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode using port
mode register 14 (PM14). When the P140 pin is used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 14 (PU14).
This port can also be used for external interrupt request input and clock output.
RESET input sets port 14 to input mode.
Figure 4-17 shows a block diagram of port 14.
Figure 4-17. Block Diagram of P140
EVDD
WRPU
PU14
PU140
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P140)
P140/PCL/INTP6
WRPM
PM14
PM140
Alternate
function
PU14:
Pull-up resistor option register 14
PM14: Port mode register 14
RD:
Read signal
WR××: Write signal
94
User’s Manual U16315EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
4.3 Registers Controlling Port Function
Port functions are controlled by the following three types of registers.
• Port mode registers (PM0, PM1, PM3, PM6, PM7, PM12, PM14)
• Port registers (P0 to P3, P6, P7, P12 to P14)
• Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12, PU14)
(1) Port mode registers (PM0, PM1, PM3, PM6, PM7, PM12, and PM14)
These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table
4-5.
Figure 4-18. Format of Port Mode Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM0
1
1
1
1
PM03
PM02
PM01
PM00
FF20H
FFH
R/W
7
6
5
4
3
2
1
0
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FF21H
FFH
R/W
7
6
5
4
3
2
1
0
1
1
1
1
PM33
PM32
PM31
PM30
FF23H
FFH
R/W
7
6
5
4
3
2
1
0
1
1
1
1
PM63
PM62
PM61
PM60
FF26H
FFH
R/W
7
6
5
4
3
2
1
0
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
FF27H
FFH
R/W
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
PM120
FF2CH
FFH
R/W
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
PM140
FF2EH
FFH
R/W
PM3
PM6
PM7
PM12
PM14
Pmn pin I/O mode selection
PMmn
(m = 0, 1, 3, 6, 7, 12, 14; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
User’s Manual U16315EJ2V0UD
95
CHAPTER 4 PORT FUNCTIONS
Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function
Pin Name
Alternate Function
Function Name
PM××
P××
×
I/O
P00
TI000
Input
1
P01
TI010
Input
1
×
TO00
Output
0
0
SCK10
Input
1
×
Output
0
1
TxD0
Output
0
1
SI10
Input
1
×
RxD0
Input
1
×
P12
SO10
Output
0
0
P13
TxD6
Output
0
1
P14
RxD6
Input
1
×
P15
TOH0
Output
0
0
P16
TOH1
Output
0
0
INTP5
Input
1
×
TI50
Input
1
×
TO50
Output
0
0
P30 to P32
INTP1 to INTP3
Input
1
×
P33
INTP4
Input
1
×
TI51
Input
1
×
TO51
Output
0
0
P70 to P77
KR0 to KR7
Input
1
×
P120
INTP0
Input
1
×
P140
PCL
Output
0
0
INTP6
Input
1
×
P10
P11
P17
Remark
×:
Don’t care
PM××: Port mode register
P××:
96
Port output latch
User’s Manual U16315EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
(2) Port registers (P0 to P3, P6, P7, P12 to P14)
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output
latch is read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H (but P2 is undefined).
Figure 4-19. Format of Port Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
P0
0
0
0
0
P03
P02
P01
P00
FF00H
00H (output latch)
R/W
7
6
5
4
3
2
1
0
P1
P17
P16
P15
P14
P13
P12
P11
P10
FF01H
00H (output latch)
R/W
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
FF02H
Undefined
R
7
6
5
4
3
2
1
0
0
0
0
0
P33
P32
P31
P30
FF03H
00H (output latch)
R/W
7
6
5
4
3
2
1
0
0
0
0
0
P63
P62
P61
P60
FF06H
00H (output latch)
R/W
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
FF07H
00H (output latch)
R/W
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
P120
FF0CH
00H (output latch)
R/W
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
P130
FF0DH
00H (output latch)
R/W
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
P140
FF0EH
00H (output latch)
R/W
P2
P3
P6
P7
P12
P13
P14
m = 0 to 3, 6, 7, 12 to 14; n = 0 to 7
Pmn
Output data control (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
User’s Manual U16315EJ2V0UD
97
CHAPTER 4 PORT FUNCTIONS
(3) Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12, and PU14)
These registers specify whether the on-chip pull-up resistors of P00 to P03, P10 to P17, P30 to P33, P70 to P77,
P120, or P140 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to
input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3, PU7,
PU12, and PU14. On-chip pull-up resistors cannot be connected to bits set to output mode and bits used as
alternate-function output pins, regardless of the settings of PU0, PU1, PU3, PU7, PU12, and PU14.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Caution Use of a pull-up resistor can be specified for P60 to P63 pins by a mask option only in the mask
ROM versions.
Figure 4-20. Format of Pull-up Resistor Option Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PU0
0
0
0
0
PU03
PU02
PU01
PU00
FF30H
00H
R/W
7
6
5
4
3
2
1
0
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
FF31H
00H
R/W
7
6
5
4
3
2
1
0
0
0
0
0
PU33
PU32
PU31
PU30
FF33H
00H
R/W
7
6
5
4
3
2
1
0
PU77
PU76
PU75
PU74
PU73
PU72
PU71
PU70
FF37H
00H
R/W
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
PU120
FF3CH
00H
R/W
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
PU140
FF3EH
00H
R/W
PU1
PU3
PU7
PU12
PU14
PUmn
Pmn pin on-chip pull-up resistor selection
(m = 0, 1, 3, 7, 12, 14; n = 0 to 7)
98
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
User’s Manual U16315EJ2V0UD
CHAPTER 4 PORT FUNCTIONS
4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the
port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins,
the output latch contents for pins specified as input are undefined, even for bits other than the
manipulated bit.
4.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the
pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared by reset.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does
not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
4.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output
latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared by reset.
(2) Input mode
The pin level is read and an operation is performed on its contents. The result of the operation is written to the
output latch, but since the output buffer is off, the pin status does not change.
User’s Manual U16315EJ2V0UD
99
CHAPTER 5 CLOCK GENERATOR
5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three system clock oscillators are available.
• X1 oscillator
The X1 oscillator oscillates a clock of fXP = 2.0 to 10.0 MHz. Oscillation can be stopped by executing the STOP
instruction or setting the main OSC control register (MOC) and processor clock control register (PCC).
• Ring-OSC oscillator
The Ring-OSC oscillator oscillates a clock of fR = 240 kHz (TYP.). Oscillation can be stopped by setting the
Ring-OSC mode register (RCM) when “Can be stopped by software” is set by a mask option and the X1 input
clock is used as the CPU clock.
• Subsystem clock oscillator
The subsystem clock oscillator oscillates a clock of fXT = 32.768 kHz. Oscillation cannot be stopped. When
subsystem clock oscillator is not used, setting not to use the on-chip feedback resistor is possible using the
processor clock control register (PCC), and the operating current can be reduced in the STOP mode.
Remarks 1. fXP: X1 input clock oscillation frequency
2. fR:
Ring-OSC clock oscillation frequency
3. fXT: Subsystem clock oscillation frequency
5.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item
100
Configuration
Control registers
Processor clock control register (PCC)
Ring-OSC mode register (RCM)
Main clock mode register (MCM)
Main OSC control register (MOC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Oscillator
X1 oscillator
Ring-OSC oscillator
Subsystem clock oscillator
User’s Manual U16315EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
Figure 5-1. Block Diagram of Clock Generator
Internal bus
Main OSC
control
register
(MOC)
MCC CLS
Oscillation
stabilization time
select register
(OSTS)
Main clock
mode register
(MCM)
OSTS2 OSTS1 OSTS0
MCS MCM0
MSTOP
Processor clock
control register
(PCC)
CLS CSS PCC2 PCC1 PCC0
3
4
X1 oscillation
stabilization time counter
STOP
Controller
Oscillation
stabilization
MOST MOST MOST MOST MOST time counter
11 13 14
15 16 status
register
(OSTC)
Control signal
C
P
U
CPU clock
(fCPU)
X1
X1 oscillator
X2
fXP
fX
Prescaler
Operation
clock switch
Ring-OSC
oscillator
fX
22
fX
23
fX
24
fCPU
Selector
fX
2
fR
Watch clock,
clock output
function
Prescaler
Clock to peripheral
hardware
Mask option
1: Cannot be stopped
0. Can be stopped
Prescaler
1/2
fXT
Subsystem
clock oscillator
XT1
XT2
FRC
8-bit timer H1,
watchdog timer
RSTOP
Ring-OSC mode
register (RCM)
Internal bus
User’s Manual U16315EJ2V0UD
101
CHAPTER 5 CLOCK GENERATOR
5.3 Registers Controlling Clock Generator
The following six registers are used to control the clock generator.
• Processor clock control register (PCC)
• Ring-OSC mode register (RCM)
• Main clock mode register (MCM)
• Main OSC control register (MOC)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
(1) Processor clock control register (PCC)
The PCC register is used to select the CPU clock, the division ratio, main system clock oscillator operation/stop
and whether to use the on-chip feedback resistorNote of the subsystem clock oscillator.
The PCC is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PCC to 00H.
Note The feedback resistor is required to control the bias point of the oscillation waveform so that the bias point
is in the middle of the power supply voltage.
When the subsystem clock is not used, the operating current in the STOP mode can be reduced by setting
bit 6 (FRC) of PCC to 1 (see Figure 5-11 Subsystem Clock Feedback Resistor).
102
User’s Manual U16315EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
Figure 5-2. Format of Processor Clock Control Register (PCC)
Address: FFFBH
After reset: 00H
R/W
Note 1
Symbol
3
2
1
0
PCC
MCC
FRC
CLS
CSS
0
PCC2
PCC1
PCC0
MCC
Control of X1 oscillator operation
0
Oscillation possible
1
Oscillation stopped
FRC
Subsystem clock feedback resistor selection
0
On-chip feedback resistor used
1
On-chip feedback resistor not used
Note 3
CLS
CPU clock status
0
X1 input clock or Ring-OSC clock
1
Subsystem clock
CSS
Note 4
Note 2
PCC2
PCC1
PCC0
CPU Clock (fCPU) Selection
MCM0 = 0
0
0
0
0
fX
fR
0
0
1
fX/2
fR/2
0
1
1
0
Notes 1.
2.
fXP
fXP/2
fX/2
2
fR/2
2
fXP/2
2
fR/2
3
fXP/2
3
fR/2
4
fXP/2
4
0
1
1
fX/2
3
1
0
0
fX/2
4
0
0
0
fXT/2
0
0
1
0
1
0
0
1
1
1
0
0
Other than above
MCM0 = 1
Setting prohibited
Bit 5 is read-only.
When the CPU is operating on the subsystem clock, MCC should be used to stop the X1 oscillator
operation. When the CPU is operating on the Ring-OSC clock, use bit 7 (MSTOP) of the main OSC
control register (MOC) to stop the X1 oscillator operation (this cannot be set by MCC). A STOP
instruction should not be used.
3.
4.
This bit can be set to 1 only when the subsystem clock is not used.
Be sure to switch CSS from 1 to 0 when bits 1 (MCS) and 0 (MCM0) of the main clock mode register
(MCM) are 1.
Caution Be sure to set bit 3 to 0.
Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM)
2. fX: Main system clock oscillation frequency (X1 input clock oscillation frequency or Ring-OSC clock
oscillation frequency)
3. fR: Ring-OSC clock oscillation frequency
4. fXP: X1 input clock oscillation frequency
5. fXT: Subsystem clock oscillation frequency
User’s Manual U16315EJ2V0UD
103
CHAPTER 5 CLOCK GENERATOR
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KD1. Therefore, the relationship
between the CPU clock (fCPU) and minimum instruction execution time is as shown in the Table 5-2.
Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU)
Minimum Instruction Execution Time: 2/fCPU
Note
X1 Input Clock
Ring-OSC Clock
(at 10 MHz Operation)
fX
Note
Subsystem Clock
(at 240 kHz (TYP.) Operation)
(at 32.768 kHz Operation)
0.2 µs
8.3 µs (TYP.)
−
0.4 µs
16.6 µs (TYP.)
−
fX/2
2
0.8 µs
33.2 µs (TYP.)
−
fX/2
3
1.6 µs
66.4 µs (TYP.)
−
fX/2
4
3.2 µs
fX/2
132.8 µs (TYP.)
−
fXT/2
−
122.1 µs
−
Note The main clock mode register (MCM) is used to set the CPU clock (X1 input clock/Ring-OSC clock) (see
Figure 5-4).
(2) Ring-OSC mode register (RCM)
This register sets the operation mode of Ring-OSC.
This register is valid when “Can be stopped by software” is set for Ring-OSC by a mask option, and the X1 input
clock or subsystem clock is selected as the CPU clock. If “Cannot be stopped” is selected for Ring-OSC by a
mask option, settings for this register are invalid.
RCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-3. Format of Ring-OSC Mode Register (RCM)
Address: FFA0H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
RCM
0
0
0
0
0
0
0
RSTOP
RSTOP
Ring-OSC oscillating/stopped
0
Ring-OSC oscillating
1
Ring-OSC stopped
Caution Make sure that the bit 1 (MCS) of the main clock mode register (MCM) is 1 before
setting RSTOP.
104
User’s Manual U16315EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
(3) Main clock mode register (MCM)
This register sets the CPU clock (X1 input clock/Ring-OSC clock).
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-4. Format of Main Clock Mode Register (MCM)
Address: FFA1H
After reset: 00H
R/W
Note
Symbol
7
6
5
4
3
2
MCM
0
0
0
0
0
0
MCS
MCM0
MCS
CPU clock status
0
Operates with Ring-OSC clock
1
Operates with X1 input clock
MCM0
Selection of clock supplied to CPU
0
Ring-OSC clock
1
X1 input clock
Note Bit 1 is read-only.
Cautions 1. When Ring-OSC clock is selected as the clock to be supplied to the CPU, the
divided clock of the Ring-OSC oscillator output (fX) is supplied to the peripheral
hardware (fX = 240 kHz (TYP.)).
Operation of the peripheral hardware with Ring-OSC clock cannot be
guaranteed. Therefore, when Ring-OSC clock is selected as the clock supplied
to the CPU, do not use peripheral hardware. In addition, stop the peripheral
hardware before switching the clock supplied to the CPU from the X1 input clock
to the Ring-OSC clock. Note, however, that the following peripheral hardware
can be used when the CPU operates on the Ring-OSC clock.
• Watchdog timer
• Clock monitor
• 8-bit timer H1 when fR/27 is selected as count clock
• Peripheral hardware selecting external clock as the clock source
(Except when external count clock of TM00 is selected (TI000 valid edge))
2. Set MCS = 1 and MCM0 = 1 before switching subsystem clock operation to X1
input clock operation (bit 4 (CSS) of the processor clock control register (PCC)
is changed from 1 to 0).
User’s Manual U16315EJ2V0UD
105
CHAPTER 5 CLOCK GENERATOR
(4) Main OSC control register (MOC)
This register selects the operation mode of the X1 input clock.
This register is used to stop the X1 oscillator operation when the CPU is operating with the Ring-OSC clock.
Therefore, this register is valid only when the CPU is operating with the Ring-OSC clock.
MOC can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-5. Format of Main OSC Control Register (MOC)
Address: FFA2H
After reset: 00H
R/W
Symbol
6
5
4
3
2
1
0
MOC
MSTOP
0
0
0
0
0
0
0
MSTOP
Control of X1 oscillator operation
0
X1 oscillator operating
1
X1 oscillator stopped
Cautions 1. Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before
setting MSTOP.
2. To stop X1 oscillation when the CPU is operating on the subsystem clock, set bit
7 (MCC) of the processor clock control register (PCC) to 1 (setting by MSTOP is
not possible).
106
User’s Manual U16315EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
(5) Oscillation stabilization time counter status register (OSTC)
This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used
as the CPU clock, the X1 input clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction,
MSTOP = 1, and MCC = 1 clear OSTC to 00H.
Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H
After reset: 00H
R
Symbol
7
6
5
4
3
2
1
0
OSTC
0
0
0
MOST11
MOST13
MOST14
MOST15
MOST16
MOST11
MOST13
MOST14
MOST15
MOST16
Oscillation stabilization time status
1
0
0
0
0
2 /fXP min. (204.8 µs min.)
1
1
0
0
0
2 /fXP min. (819.2 µs min.)
1
1
1
0
0
2 /fXP min. (1.64 ms min.)
1
1
1
1
0
2 /fXP min. (3.27 ms min.)
1
1
1
1
1
2 /fXP min. (6.55 ms min.)
11
13
14
15
16
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1.
2. If the STOP mode is entered and then released while the Ring-OSC clock is being used as the
CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
The X1 oscillation stabilization time counter counts up to the oscillation stabilization time set
by OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
3. The wait time when STOP mode is released does not include the time after STOP mode
release until clock oscillation starts (“a” below) regardless of whether STOP mode is
released by RESET input or interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
Remarks 1. Values in parentheses are reference values for operation with fXP = 10 MHz.
2. fXP: X1 input clock oscillation frequency
User’s Manual U16315EJ2V0UD
107
CHAPTER 5 CLOCK GENERATOR
(6) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 oscillation stabilization wait time when STOP mode is released.
The wait time set by OSTS is valid only after STOP mode is released with the X1 input clock selected as CPU
clock. After STOP mode is released with Ring-OSC selected as CPU clock, the oscillation stabilization time must
be confirmed by OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 05H.
Figure 5-7. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H
After reset: 05H
R/W
Symbol
7
6
5
4
3
2
1
0
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Oscillation stabilization time selection
0
0
1
2 /fXP (204.8 µs)
0
1
0
2 /fXP (819.2 µs)
0
1
1
2 /fXP (1.64 ms)
1
0
0
2 /fXP (3.27 ms)
1
0
1
2 /fXP (6.55 ms)
11
13
14
15
16
Other than above
Setting prohibited
Cautions 1. If the STOP mode is entered and then released while the Ring-OSC clock is
being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
2. The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether
STOP mode is released by RESET input or interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
Remarks 1. Values in parentheses are reference values for operation with fXP = 10 MHz.
2. fXP: X1 input clock oscillation frequency
108
User’s Manual U16315EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
5.4 System Clock Oscillator
5.4.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or ceramic resonator (Standard: 8.38 MHz, 10 MHz when
REGC pin is directly connected to VDD) connected to the X1 and X2 pins.
An external clock can be input to the X1 oscillator when the REGC pin is directly connected to VDD. In this case,
input the clock signal to the X1 pin and input the inverse signal to the X2 pin.
Figure 5-8 shows the examples of the external circuit of the X1 oscillator.
Figure 5-8. Examples of External Circuit of X1 Oscillator
(a) Crystal, ceramic oscillation
VSS
X1
(b) External clock
External
clock
X1
X2
X2
Crystal resonator or
ceramic resonator
5.4.2 Subsystem clock oscillator
The subsystem clock oscillator oscillates with a crystal resonator (Standard: 32.768 kHz) connected to the XT1
and XT2 pins.
External clocks can be input to the subsystem clock oscillator when the REGC pin is directly connected to VDD. In
this case, input the clock signal to the XT1 pin and the inverse signal to the XT2 pin.
Figure 5-9 shows the examples of the external circuit of the subsystem clock oscillator.
Figure 5-9. Examples of External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation
(b) External clock
VSS
XT1
External
clock
32.768
kHz
XT2
XT1
XT2
Cautions are listed on the next page.
User’s Manual U16315EJ2V0UD
109
CHAPTER 5 CLOCK GENERATOR
Cautions 1. When using the X1 oscillator and subsystem clock oscillator, wire as follows in the area
enclosed by the broken lines in the Figure 5-10 to avoid an adverse effect from wiring
capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do
not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing
power consumption.
Figure 5-10 shows examples of incorrect resonator connection.
Figure 5-10. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
PORT
VSS
Remark
X1
X2
VSS
X2
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
110
X1
User’s Manual U16315EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
Figure 5-10. Examples of Incorrect Resonator Connection (2/2)
(c) Wiring near high alternating current
(d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
VDD
Pmn
X1
X2
VSS
High current
VSS
A
X1
B
X2
C
High current
(e) Signals are fetched
VSS
Remark
X1
X2
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
Cautions 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1,
resulting in malfunctioning.
User’s Manual U16315EJ2V0UD
111
CHAPTER 5 CLOCK GENERATOR
5.4.3 When subsystem clock is not used
If it is not necessary to use the subsystem clock for low power consumption operations and watch operations,
connect the XT1 and XT2 pins as follows.
XT1: Connect directly to EVDD or VDD
XT2: Leave open
In this state, however, some current may leak via the on-chip feedback resistor of the subsystem clock oscillator
when the X1 input clock and Ring-OSC clock stop. To minimize leakage current, the above on-chip feedback resistor
can be set not to be used via bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the
XT1 and XT2 pins as described above.
Figure 5-11. Subsystem Clock Feedback Resistor
FRC
P-ch
Feedback resistor
XT1
Remark
XT2
The feedback resistor is required to control the bias point of the oscillation waveform so that the bias
point is in the middle of the power supply voltage.
5.4.4 Ring-OSC oscillator
Ring-OSC oscillator is incorporated in the 78K0/KD1.
“Can be stopped by software” or “Cannot be stopped” can be selected by a mask option. The Ring-OSC clock
always oscillates after RESET release (240 kHz (TYP.)).
5.4.5 Prescaler
The prescaler generates various clocks by dividing the X1 oscillator output when the X1 input clock is selected as
the clock to be supplied to the CPU.
Caution When the Ring-OSC clock is selected as the clock supplied to the CPU, the prescaler generates
various clocks by dividing the Ring-OSC oscillator output (fX = 240 kHz (TYP.)).
112
User’s Manual U16315EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
mode.
• X1 input clock fXP
• Ring-OSC clock fR
• Subsystem clock fXT
• CPU clock fCPU
• Clock to peripheral hardware
The CPU starts operation when the on-chip Ring-OSC oscillator starts outputting after reset release in the
78K0/KD1, thus enabling the following.
(1) Enhancement of security function
When the X1 input clock is set as the CPU clock by the default setting, the device cannot operate if the X1 input
clock is damaged or badly connected and therefore does not operate after reset is released. However, the start
clock of the CPU is the on-chip Ring-OSC clock, so the device can be started by the Ring-OSC clock after reset
release by the clock monitor (detection of X1 input clock stop). Consequently, the system can be safely shut
down by performing a minimum operation, such as acknowledging a reset source by software or performing
safety processing when there is a malfunction.
(2) Improvement of performance
Because the CPU can be started without waiting for the X1 input clock oscillation stabilization time, the total
performance can be improved.
A timing diagram of the CPU default start using Ring-OSC is shown in Figure 5-12.
User’s Manual U16315EJ2V0UD
113
CHAPTER 5 CLOCK GENERATOR
Figure 5-12. Timing Diagram of CPU Default Start Using Ring-OSC
X1 input clock
(fXP)
Ring-OSC clock
(fR)
Subsystem clock
(fXT)
RESET
Switched by software
Ring-OSC clock
CPU clock
X1 input clock
Operation
stopped: 17/fR
X1 oscillation stabilization time: 211/fXP to 216/fXPNote
Note Check using the oscillation stabilization time counter status register (OSTC).
(a) When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is set to 0 and the RingOSC clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks of the Ring-OSC
clock have elapsed after RESET release (or clock supply to the CPU stops for 17 clocks). During the
RESET period, oscillation of the X1 input clock and Ring-OSC clock is stopped.
(b) After RESET release, the CPU clock can be switched from the Ring-OSC clock to the X1 input clock using bit
0 (MCM0) of the main clock mode register (MCM) after the X1 input clock oscillation stabilization time has
elapsed. At this time, check the oscillation stabilization time using the oscillation stabilization time counter
status register (OSTC) before switching the CPU clock. The CPU clock status can be checked using bit 1
(MCS) of MCM.
(c) Ring-OSC can be set to stopped/oscillating using the Ring-OSC mode register (RCM) when “Can be stopped
by software” is selected for the Ring-OSC by a mask option, if the X1 input or subsystem clock is used as the
CPU clock. Make sure that MCS is 1 at this time.
(d) When Ring-OSC is used as the CPU clock, the X1 input clock can be set to stopped/oscillating using the
main OSC control register (MOC). Make sure that MCS is 0 at this time.
When the subsystem clock is used as the CPU clock, whether the X1 input clock stops or oscillates can be
set by the processor clock control register (PCC). In addition, HALT mode can be used during operation with
the subsystem clock, but STOP mode cannot be used (subsystem clock oscillation cannot be stopped by the
STOP instruction).
(e) Select the X1 input clock oscillation stabilization time (211/fXP, 213/fXP, 214/fXP, 215/fXP, 216/fXP) using the oscillation
stabilization time select register (OSTS) when releasing STOP mode while X1 input clock is being used as
the CPU clock. In addition, when releasing STOP mode while RESET is released and Ring-OSC clock is
being used as the CPU clock, check the X1 input clock oscillation stabilization time using the oscillation
stabilization time counter status register (OSTC).
114
User’s Manual U16315EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
A status transition diagram of this product is shown in Figure 5-13, and the relationship between the operation
clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown
in Tables 5-3 and 5-4, respectively.
Figure 5-13. Status Transition Diagram (1/4)
(1) When “Ring-OSC can be stopped by software” is selected by mask option
(when subsystem clock is not used)
HALTNote 4
HALT instruction
Interrupt
Interrupt
HALT
instruction
HALT
instruction
Status 4
RSTOP = 0
CPU clock: fXP
fXP: Oscillating
fR: Oscillation stopped
RSTOP = 1Note 1
Interrupt
Interrupt
Status 3
CPU clock: fXP
fXP: Oscillating
fR: Oscillating
STOP
instruction
MCM0 = 0
MCM0 = 1Note 2
Interrupt
STOP
instruction
HALT
instruction
Interrupt
MSTOP = 1Note 3
Status 1
CPU clock: fR
fXP: Oscillation stopped
fR: Oscillating
MSTOP = 0
Status 2
CPU clock: fR
fXP: Oscillating
fR: Oscillating
STOP
instruction
Interrupt
Interrupt
STOP
instruction
STOPNote 4
Reset release
ResetNote 5
Notes 1.
When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
2.
Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
(MCM) is 1.
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
3.
When shifting from status 2 to status 1, make sure that MCS is 0.
4.
When “Ring-OSC can be stopped by software” is selected by a mask option, the watchdog timer
stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog timer.
However, oscillation of Ring-OSC does not stop even in the HALT and STOP modes if RSTOP = 0.
5.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
User’s Manual U16315EJ2V0UD
115
CHAPTER 5 CLOCK GENERATOR
Figure 5-13. Status Transition Diagram (2/4)
(2) When “Ring-OSC can be stopped by software” is selected by mask option
(when subsystem clock is used)
Status 6
CPU clock: fXT
fXP: Oscillation
stopped
fR: Oscillating/
oscillation
stopped
Interrupt
MCC = 0
MCC = 1
HALT
instruction
Status 5
CPU clock: fXT
fXP: Oscillating
fR: Oscillating/
oscillation
stopped
Interrupt
HALTNote 4
HALT
instruction
HALT
instruction Interrupt
HALT
instruction Interrupt
CSS = 0Note 5
CSS = 1Note 5
Status 4
Status 3
CPU clock: fXP RSTOP = 0
CPU clock: fXP
fXP: Oscillating
fXP: Oscillating
fR: Oscillation RSTOP = 1Note 1 fR: Oscillating
stopped
HALT
instruction
Interrupt
Status 1
Status
2
MCM0 = 0
MSTOP = 1Note 3 CPU clock: fR
CPU clock: fR
fXP: Oscillation
fXP: Oscillating
stopped
MCM0 = 1Note 2 fR: Oscillating
MSTOP = 0
fR: Oscillating
STOP
STOP
instruction
instruction
Interrupt
Interrupt
STOP
instruction
Interrupt
STOPNote 4
Reset release
ResetNote 6
Notes 1.
When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
2.
Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
3.
4.
When shifting from status 2 to status 1, make sure that MCS is 0.
When “Ring-OSC can be stopped by software” is selected by a mask option, the clock supply to the
watchdog timer is stopped after the HALT or STOP instruction has been executed, regardless of the
setting of bit 0 (RSTOP) of the Ring-OSC mode register (RCM) and bit 0 (MCM0) of the main clock
mode register (MCM).
116
5.
The operation cannot be shifted between subsystem clock operation and Ring-OSC operation.
6.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
User’s Manual U16315EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
Figure 5-13. Status Transition Diagram (3/4)
(3) When “Ring-OSC cannot be stopped” is selected by mask option
(when subsystem clock is not used)
HALT
Interrupt
Interrupt
HALT
instruction
Status 3
CPU clock: fXP
fXP: Oscillating
fR: Oscillating
MCM0 = 0
MCM0 = 1Note 1
Status 2
CPU clock: fR
fXP: Oscillating
fR: Oscillating
HALT instruction
MSTOP = 1Note 2
MSTOP = 0
Status 1
CPU clock: fR
fXP: Oscillation stopped
fR: Oscillating
STOP
instruction
Interrupt
STOP
instruction
HALT
instruction
Interrupt
STOP
instruction
Interrupt
STOPNote 3
Interrupt
Reset release
ResetNote 4
Notes 1.
Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
2.
3.
When shifting from status 2 to status 1, make sure that MCS is 0.
The watchdog timer operates using Ring-OSC even in STOP mode if “Ring-OSC cannot be stopped”
is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer
H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer
overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer
overflow after STOP instruction execution.
4.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
User’s Manual U16315EJ2V0UD
117
CHAPTER 5 CLOCK GENERATOR
Figure 5-13. Status Transition Diagram (4/4)
(4) When “Ring-OSC cannot be stopped” is selected by mask option
(when subsystem clock is used)
Status 5
CPU clock: fXT
fXP: Oscillation stopped
fR: Oscillating
Interrupt
MCC = 0
MCC = 1
HALT instruction
Status 4
CPU clock: fXT
fXP: Oscillating
fR: Oscillating
Interrupt
HALT
HALT instruction
Interrupt
CSS = 0Note 4
Interrupt
HALT
instruction
CSS = 1Note 4
Status 3
CPU clock: fXP
fXP: Oscillating
fR: Oscillating
MCM0 = 0
MCM0 = 1Note 1
Interrupt
Status 2
CPU clock: fR
fXP: Oscillating
fR: Oscillating
MSTOP = 1Note 2
MSTOP = 0
Status 1
CPU clock: fR
fXP: Oscillation stopped
fR: Oscillating
STOP
instruction
Interrupt
STOP
instruction
HALT instruction
HALT
instruction
STOP
instruction
Interrupt
STOPNote 3
Interrupt
Reset release
ResetNote 5
Notes 1.
Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
2.
When shifting from status 2 to status 1, make sure that MCS is 0.
3.
The watchdog timer operates using Ring-OSC even in STOP mode if “Ring-OSC cannot be stopped”
is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer
H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer
overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer
overflow after STOP instruction execution.
118
4.
The operation cannot be shifted between subsystem clock operation and Ring-OSC operation.
5.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
User’s Manual U16315EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
Table 5-3. Relationship Between Operation Clocks in Each Operation Status
Status
Operation
X1 Oscillator
Ring-OSC Oscillator
MSTOP = 0 MSTOP = 1
MCC = 0
Mode
Reset
Note 1
MCC = 1
STOP
Clock
After
Oscillator
Release
Note 2
RSTOP = 0 RSTOP = 1
Stopped
Stopped
Oscillating
Notes 1.
2.
Supplied to Peripherals
MCM0 = 0 MCM0 = 1
Oscillating Ring-OSC Stopped
Oscillating Oscillating Stopped
HALT
Prescaler Clock
Subsystem CPU Clock
Stopped
Note 3
Stopped
Note 4
Ring-OSC X1
When “Cannot be stopped” is selected for Ring-OSC by a mask option.
When “Can be stopped by software” is selected for Ring-OSC by a mask option.
3.
Operates using the CPU clock at STOP instruction execution.
4.
Operates using the CPU clock at HALT instruction execution.
Caution The RSTOP setting is valid only when “Can be stopped by software” is set for Ring-OSC by a mask
option.
Remark
MSTOP: Bit 7 of the main OSC control register (MOC)
MCC:
Bit 7 of the processor clock control register (PCC)
RSTOP: Bit 0 of the Ring-OSC mode register (RCM)
MCM0:
Bit 0 of the main clock mode register (MCM)
Table 5-4. Oscillation Control Flags and Clock Oscillation Status
X1 Oscillator
MSTOP = 1
Note
MSTOP = 0
Note
RSTOP = 0
Stopped
RSTOP = 1
Setting prohibited
RSTOP = 0
Oscillating
RSTOP = 1
MCC = 1
Note
MCC = 0
Note
RSTOP = 0
Oscillating
Oscillating
Stopped
Stopped
RSTOP = 1
RSTOP = 0
Ring-OSC Oscillator
Oscillating
Stopped
Oscillating
RSTOP = 1
Oscillating
Stopped
Note Setting X1 oscillator oscillating/stopped differs depending on the CPU clock used.
• When the Ring-OSC clock is used as the CPU clock: Set using the MSTOP bit
• When the subsystem clock is used as the CPU clock: Set using the MCC bit
Caution The RSTOP setting is valid only when “Can be stopped by software” is set for Ring-OSC
by a mask option.
Remark
MSTOP: Bit 7 of the main OSC control register (MOC)
MCC:
Bit 7 of the processor clock control register (PCC)
RSTOP: Bit 0 of the Ring-OSC mode register (RCM)
User’s Manual U16315EJ2V0UD
119
CHAPTER 5 CLOCK GENERATOR
5.6 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock
Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the Ring-OSC clock and X1 input
clock.
In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions
are executed using the pre-switch clock after switching MCM0 (see Table 5-5).
Bit 1 (MCS) of MCM is used to judge that operation is performed using either the Ring-OSC clock or X1 input clock.
To stop the original clock after switching the clock, wait for the number of clocks shown in Table 5-5.
Table 5-5. Time Required to Switch Between Ring-OSC Clock and X1 Input Clock
PCC
Time Required for Switching
PCC2
PCC1
PCC0
X1→Ring-OSC
0
0
0
fXP/fR + 1 clock
0
0
1
fXP/2fR + 1 clock
0
1
0
fXP/4fR + 1 clock
0
1
1
fXP/8fR + 1 clock
1
0
0
fXP/16fR + 1 clock
Ring-OSC→X1
2 clocks
Caution To calculate the maximum time, set fR = 120 kHz.
Remarks 1. PCC: Processor clock control register
2. fXP: X1 input clock oscillation frequency
3. fR: Ring-OSC clock oscillation frequency
4. The maximum time is the number of clocks of the CPU clock before switching.
120
User’s Manual U16315EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
5.7 Time Required for CPU Clock Switchover
The CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control
register (PCC).
The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on
the pre-switchover clock for several instructions (see Table 5-6).
Whether the system is operating on the X1 input clock (or Ring-OSC clock) or the subsystem clock can be
ascertained using bit 5 (CLS) of the PCC register.
Table 5-6. Maximum Time Required for CPU Clock Switchover
Set Value Before
Set Value After Switchover
Switchover
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
0
0
0
0
0
0
0
0
0
0
0
1
16 clocks
0
0
1
16 clocks
0
0
0
1
16 clocks
1
0
1
0
0
16 clocks
1
×
×
×
fXP/fXT clocks
(306 clocks)
0
0
1
8 clocks
8 clocks
8 clocks
8 clocks
fXP/2fXT clocks
(153 clocks)
0
1
0
4 clocks
4 clocks
4 clocks
4 clocks
fXP/4fXT clocks
(77 clocks)
0
1
1
2 clocks
2 clocks
2 clocks
1
0
0
1 clock
1 clock
1 clock
2 clocks
fXP/8fXT clocks
(39 clocks)
fXP/16fXT clocks
1 clock
(20 clocks)
1
×
×
×
1 clock
1 clock
1 clock
1 clock
1 clock
Remarks 1. The maximum time is the number of clocks of the CPU clock before switching.
2. Figures in parentheses apply to operation with fXP = 10 MHz and fXT = 32.768 kHz.
Caution Selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover from the X1
input clock to the subsystem clock (changing CSS from 0 to 1) should not be set
simultaneously.
Simultaneous setting is possible, however, for selection of the CPU clock cycle division factor
(PCC0 to PCC2) and switchover from the subsystem clock to the X1 input clock (changing CSS
from 1 to 0).
User’s Manual U16315EJ2V0UD
121
CHAPTER 5 CLOCK GENERATOR
5.8 Clock Switching Flowchart and Register Setting
5.8.1 Switching from Ring-OSC clock to X1 input clock
Figure 5-14. Switching from Ring-OSC Clock to X1 Input Clock (Flowchart)
After reset release
PCC = 00H
RCM = 00H
MCM = 00H
MOC = 00H
OSTC = 00H
OSTS = 05HNote
Register initial
value after reset
; fCPU = fR
; Ring-OSC oscillation
; Ring-OSC clock operation
; X1 oscillation
; Oscillation stabilization time status register
; Oscillation stabilization time fXP/216
Each processing
OSTC checkNote
Ring-OSC clock
operation
; X1 oscillation stabilization time status check
X1 oscillation stabilization
time has not elapsed
X1 oscillation stabilization time has elapsed
PCC setting
Ring-OSC
clock operation
(dividing set PCC)
MCM.0 ← 1
MCM.1 (MCS) is changed from 0 to 1
X1 input clock operation
X1 input clock
operation
Note Check the oscillation stabilization wait time of the X1 oscillator after reset release using the OSTC register
and then switch to the X1 input clock operation after the oscillation stabilization wait time has elapsed. The
OSTS register setting is valid only after STOP mode is released by interrupt during X1 input clock operation.
122
User’s Manual U16315EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
5.8.2 Switching from X1 input clock to Ring-OSC clock
Figure 5-15. Switching from X1 Input Clock to Ring-OSC Clock (Flowchart)
Register setting
in X1 input
clock operation
PCC.7 (MCC) = 0
PCC.4 (CSS) = 0
MCM = 03H
; X1 oscillation
; X1 input clock or Ring-OSC clock
; X1 input clock operation
RCM.0Note
(RSTOP) = 1?
; Ring-OSC oscillating?
Yes: RSTOP = 1
X1 input
clock operation
No: RSTOP = 0
RSTOP = 0
MCM0 ← 0
; Ring-OSC clock operation
MCM.1 (MCS) is changed from 1 to 0
Ring-OSC
clock operation
Ring-OSC clock operation
Note Required only when “clock can be stopped by software” is selected for Ring-OSC by a mask option.
User’s Manual U16315EJ2V0UD
123
CHAPTER 5 CLOCK GENERATOR
5.8.3 Switching from X1 input clock to subsystem clock
Figure 5-16. Switching from X1 Input Clock to Subsystem Clock (Flowchart)
Register setting
in X1 input
clock operation
PCC.7 (MCC) = 0
PCC.4 (CSS) = 0
MCM = 03H
; X1 oscillation
; X1 input clock or Ring-OSC clock
; X1 input clock operation
X1 input
clock operation
CSS ← 1Note
; Subsystem clock operation
MCS = 1 not changed.
CLS is changed from 0 to 1.
Subsystem
clock
Subsystem clock operation
Note Set CSS to 1 after confirming that oscillation of the subsystem clock is stabilized.
124
User’s Manual U16315EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
5.8.4 Switching from subsystem clock to X1 input clock
Figure 5-17. Switching from Subsystem Clock to X1 Input Clock (Flowchart)
PCC.4 (CSS) = 1
MCM = 03H
; Subsystem clock operation
No: X1 oscillating
MCC = 1?
; X1 oscillating?
Yes: X1 oscillation stopped
MCC ← 0
; X1 oscillation enabled
Subsystem
clock operation
OSTC check
X1 oscillation
stabilization time
not elapsed
; Wait for X1 oscillation stabilization time
X1 oscillation stabilization time elapsed
CSS ← 0
; X1 input clock operation
CLS is changed from 1 to 0.
MCS = 1 not changed.
X1 input
clock operation
X1 input clock operation
User’s Manual U16315EJ2V0UD
125
CHAPTER 5 CLOCK GENERATOR
5.8.5 Register settings
The table below shows the statuses of the setting flags and status flags when each mode is set.
Table 5-7. Clock and Register Setting
fCPU
Mode
Setting Flag
PCC Register
MCM
Status Flag
MOC
RCM
PCC
MCM
Register Register Register Register Register
Note 2
X1 input clock
Ring-OSC clock
0
0
1
0
1
0
1
0
0
0
0
Ring-OSC oscillating
0
0
1
0
Ring-OSC stopped
0
0
1
0
0
0
Note 3
0
0
0
0
1
1
Note 5
0
Note 6
0
1
1
X1 stopped, Ring-OSC oscillating
1
1
1
Note 5
0
Note 6
0
1
1
1
Note 5
0
Note 6
1
1
1
0
Note 6
1
1
1
0
X1 stopped, Ring-OSC stopped
0
1
0
MSTOP RSTOP
X1 oscillating, Ring-OSC oscillating
X1 oscillating, Ring-OSC stopped
Notes 1.
MCS
MCM0
X1 oscillating
Note 4
CLS
CSS
X1 stopped
Subsystem clock
Note 1
MCC
1
1
0
Note 5
1
1
Valid only when “clock can be stopped by software” is selected for Ring-OSC by a mask option.
2.
Do not set MCC = 1 or MSTOP = 1 during X1 input clock operation (even if MCC = 1 or MSTOP = 1 is set,
3.
Do not set MCC = 1 during Ring-OSC operation (even if MCC = 1 is set, the X1 oscillation does not stop).
the X1 oscillation does not stop).
To stop X1 oscillation during Ring-OSC operation, use MSTOP.
4.
Shifting to subsystem clock operation mode must be performed from the X1 input clock operation mode.
From subsystem clock operation mode, only X1 input clock operation mode can be shifted to.
5.
6.
Do not set MCM0 = 0 (shifting to Ring-OSC operation) during subsystem clock operation.
Do not set MSTOP = 1 during subsystem clock operation (even if MSTOP = 1 is set, X1 oscillation does
not stop). To stop X1 oscillation during subsystem clock operation, use MCC.
126
User’s Manual U16315EJ2V0UD
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.1 Functions of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 has the following functions.
• Interval timer
• PPG output
• Pulse width measurement
• External event counter
• Square-wave output
• One-shot pulse output
(1) Interval timer
16-bit timer/event counter 00 generates an interrupt request at the preset time interval.
(2) PPG output
16-bit timer/event counter 00 can output a rectangular wave whose frequency and output pulse width can be set
freely.
(3) Pulse width measurement
16-bit timer/event counter 00 can measure the pulse width of an externally input signal.
(4) External event counter
16-bit timer/event counter 00 can measure the number of pulses of an externally input signal.
(5) Square-wave output
16-bit timer/event counter 00 can output a square wave with any selected frequency.
(6) One-shot pulse output
16-bit timer/event counter 00 can output a one-shot pulse whose output pulse width can be set freely.
User’s Manual U16315EJ2V0UD
127
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.2 Configuration of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 includes the following hardware.
Table 6-1. Configuration of 16-Bit Timer/Event Counter 00
Item
Configuration
Timer counter
16 bits (TM00)
Register
16-bit timer capture/compare register: 16 bits (CR000, CR010)
Timer input
TI000, TI010
Timer output
TO00, output controller
Control registers
16-bit timer mode control register 00 (TMC00)
16-bit timer capture/compare control register 00 (CRC00)
16-bit timer output control register 00 (TOC00)
Prescaler mode register 00 (PRM00)
Port mode register 0 (PM0)
Port register 0 (P0)
Figure 6-1 shows the block diagram.
Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00
Internal bus
Capture/compare control
register 00 (CRC00)
TI010/TO00/P01
Selector
Noise
eliminator
Selector
CRC002CRC001 CRC000
16-bit timer capture/compare
register 000 (CR000)
INTTM000
Match
Noise
eliminator
16-bit timer counter 00
(TM00)
Output
controller
TO00/TI010/
P01
Match
2
Output latch
(P01)
Noise
eliminator
TI000/P00
Clear
PM01
16-bit timer capture/compare
register 010 (CR010)
Selector
fX
Selector
fX
fX/22
fX/28
INTTM010
CRC002
PRM001 PRM000
Prescaler mode
register 00 (PRM00)
128
TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
16-bit timer output
16-bit timer mode
control register 00
control register 00
(TOC00)
(TMC00)
Internal bus
User’s Manual U16315EJ2V0UD
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(1) 16-bit timer counter 00 (TM00)
TM00 is a 16-bit read-only register that counts count pulses.
The counter is incremented in synchronization with the rising edge of the input clock.
Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00)
Address: FF10H, FF11H
Symbol
After reset: 0000H
R
FF11H
FF10H
TM00
The count value is reset to 0000H in the following cases.
At RESET input
If TMC003 and TMC002 are cleared
If the valid edge of TI000 is input in the mode in which clear & start occurs when inputting the valid edge of
TI000
If TM00 and CR000 match in the mode in which clear & start occurs on a match of TM00 and CR000
OSPT00 is set in one-shot pulse output mode
(2) 16-bit timer capture/compare register 000 (CR000)
CR000 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is
used as a capture register or as a compare register is set by bit 0 (CRC000) of capture/compare control register
00 (CRC00).
CR000 can be set by a 16-bit memory manipulation instruction.
RESET input clears this register to 0000H.
Figure 6-3. Format of 16-Bit Timer Capture/Compare Register 000 (CR000)
Address: FF12H, FF13H
Symbol
After reset: 0000H
R/W
FF13H
FF12H
CR000
• When CR000 is used as a compare register
The value set in CR000 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an
interrupt request (INTTM000) is generated if they match. The set value is held until CR000 is rewritten.
• When CR000 is used as a capture register
It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. The TI000 or
TI010 valid edge is set using prescaler mode register 00 (PRM00) (see Table 6-2).
User’s Manual U16315EJ2V0UD
129
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins
(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)
CR000 Capture Trigger
TI000 Pin Valid Edge
ES001
ES000
Falling edge
Rising edge
0
1
Rising edge
Falling edge
0
0
No capture operation
Both rising and falling edges
1
1
ES101
ES100
(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)
CR000 Capture Trigger
TI010 Pin Valid Edge
Falling edge
Falling edge
0
0
Rising edge
Rising edge
0
1
Both rising and falling edges
Both rising and falling edges
1
1
Remarks 1. Setting ES001, ES000 = 1, 0 and ES101, ES100 = 1, 0 is prohibited.
2. ES001, ES000:
Bits 5 and 4 of prescaler mode register 00 (PRM00)
ES101, ES100:
Bits 7 and 6 of prescaler mode register 00 (PRM00)
CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)
Cautions 1. Set a value other than 0000H in CR000 in the mode in which clear & start occurs on a match
of TM00 and CR000. However, in the free-running mode and in the clear mode using the
valid edge of TI000, if CR000 is cleared to 0000H, an interrupt request (INTTM000) is
generated when the value of CR000 changes from 0000H to 0001H following overflow
(FFFFH).
2. When P01 is used as the valid edge input pin of TI010, it cannot be used as the timer output
(TO00). Moreover, when P01 is used as TO00, it cannot be used as the valid edge input pin
of TI010.
3. When CR000 is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
4. Do not rewrite CR000 during TM00 operation.
130
User’s Manual U16315EJ2V0UD
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(3) 16-bit timer capture/compare register 010 (CR010)
CR010 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is
used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00
(CRC00).
CR010 can be set by a 16-bit memory manipulation instruction.
RESET input clears this register to 0000H.
Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010)
Address: FF14H, FF15H
Symbol
After reset: 0000H
R/W
FF15H
FF14H
CR010
• When CR010 is used as a compare register
The value set in the CR010 is constantly compared with 16-bit timer counter 00 (TM00) count value, and an
interrupt request (INTTM010) is generated if they match. The set value is held until CR010 is rewritten.
• When CR010 is used as a capture register
It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by
prescaler mode register 00 (PRM00) (see Table 6-3).
Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1)
CR010 Capture Trigger
TI000 Pin Valid Edge
ES001
ES000
Falling edge
Falling edge
0
0
Rising edge
Rising edge
0
1
Both rising and falling edges
Both rising and falling edges
1
1
Remarks 1. Setting ES001, ES000 = 1, 0 is prohibited.
2. ES001, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00)
CRC002:
Bit 2 of capture/compare control register 00 (CRC00)
Cautions 1. If the CR010 register is cleared to 0000H, an interrupt request (INTTM010) is generated after
the TM00 register overflows, after the timer is cleared and started on a match between the
TM00 register and the CR000 register, or after the timer is cleared by the valid edge of TI000
or a one-shot trigger.
2. When CR010 is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
3. CR010 can be rewritten during TM00 operation. For details, see Caution 2 in Figure 6-15.
User’s Manual U16315EJ2V0UD
131
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.3 Registers Controlling 16-Bit Timer/Event Counter 00
The following six registers are used to control 16-bit timer/event counter 00.
• 16-bit timer mode control register 00 (TMC00)
• Capture/compare control register 00 (CRC00)
• 16-bit timer output control register 00 (TOC00)
• Prescaler mode register 00 (PRM00)
• Port mode register 0 (PM0)
• Port register 0 (P0)
(1) 16-bit timer mode control register 00 (TMC00)
This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output
timing, and detects an overflow.
TMC00 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC00 to 00H.
Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 are set to
values other than 0, 0 (operation stop mode), respectively. Set TMC002 and TMC003 to 0, 0 to
stop the operation.
132
User’s Manual U16315EJ2V0UD
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Address FFBAH
After reset: 00H
Symbol
7
6
5
4
TMC00
0
0
0
0
R/W
3
2
1
TMC003 TMC002 TMC001 OVF00
Operating mode and clear
TMC003 TMC002 TMC001
TO00 inversion timing selection
Interrupt request generation
mode selection
0
0
0
Operation stop
0
0
1
(TM00 cleared to 0)
0
1
0
Free-running mode
0
1
No change
Not generated
Match between TM00 and
Generated on match between
CR000 or match between
TM00 and CR000, or match
TM00 and CR010
between TM00 and CR010
Match between TM00 and
1
CR000, match between TM00
and CR010 or TI000 valid edge
1
0
0
Clear & start occurs on TI000
−
1
0
1
valid edge
1
1
0
Clear & start occurs on match
Match between TM00 and
between TM00 and CR000
CR000 or match between
TM00 and CR010
1
1
Match between TM00 and
1
CR000, match between TM00
and CR010 or TI000 valid edge
OVF00
16-bit timer counter 00 (TM00) overflow detection
0
Overflow not detected
1
Overflow detected
Cautions 1. Timer operation must be stopped before writing to bits other than the OVF00 flag.
2. Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00).
3. If any of the following modes: the mode in which clear & start occurs on match between
TM00 and CR000, the mode in which clear & start occurs at the TI00 valid edge, or freerunning mode is selected, when the set value of CR000 is FFFFH and the TM00 value changes
from FFFFH to 0000H, the OVF00 flag is set to 1.
Remarks 1. TO00:
16-bit timer/event counter 00 output pin
2. TI000:
16-bit timer/event counter 00 input pin
3. TM00:
16-bit timer counter 00
4. CR000: 16-bit timer capture/compare register 000
5. CR010: 16-bit timer capture/compare register 010
User’s Manual U16315EJ2V0UD
133
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(2) Capture/compare control register 00 (CRC00)
This register controls the operation of the 16-bit timer capture/compare registers (CR000, CR010).
CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CRC00 to 00H.
Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00)
Address: FFBCH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
CRC00
0
0
0
0
0
CRC002
CRC001
CRC000
CRC002
CR010 operating mode selection
0
Operates as compare register
1
Operates as capture register
CRC001
CR000 capture trigger selection
0
Captures on valid edge of TI010
1
Captures on valid edge of TI000 by reverse phase
CRC000
CR000 operating mode selection
0
Operates as compare register
1
Operates as capture register
Cautions 1. Timer operation must be stopped before setting CRC00.
2. When the mode in which clear & start occurs on a match between TM00 and CR000 is
selected with 16-bit timer mode control register 00 (TMC00), CR000 should not be specified
as a capture register.
3. The capture operation is not performed if both the rising and falling edges are specified as
the valid edge of TI000.
4. To ensure that the capture operation is performed properly, the capture trigger requires a
pulse two cycles longer than the count clock selected by prescaler mode register 00
(PRM00).
(3) 16-bit timer output control register 00 (TOC00)
This register controls the operation of the 16-bit timer/event counter 00 output controller. It sets/resets the timer
output F/F (LV00), enables/disables output inversion and 16-bit timer/event counter 00 timer output,
enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software.
TOC00 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TOC00 to 00H.
134
User’s Manual U16315EJ2V0UD
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00)
Address: FFBDH
After reset: 00H
R/W
Symbol
7
4
1
TOC00
0
OSPT00
OSPE00
TOC004
LVS00
LVR00
TOC001
TOE00
OSPT00
One-shot pulse output trigger control via software
0
No one-shot pulse trigger
1
One-shot pulse trigger
OSPE00
One-shot pulse output operation control
0
Successive pulse output mode
1
One-shot pulse output mode
TOC004
Note
Timer output F/F control using match of CR010 and TM00
0
Disables inversion operation
1
Enables inversion operation
LVS00
LVR00
Timer output F/F status setting
0
0
No change
0
1
Timer output F/F reset (0)
1
0
Timer output F/F set (1)
1
1
Setting prohibited
TOC001
Timer output F/F control using match of CR000 and TM00
0
Disables inversion operation
1
Enables inversion operation
TOE00
Timer output control
0
Disables output (output fixed to level 0)
1
Enables output
Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between
the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow does not
occur.
Cautions 1. Timer operation must be stopped before setting other than TOC004.
2. If LVS00 and LVR00 are read, 0 is read.
3. OSPT00 is automatically cleared after data is set, so 0 is read.
4. Do not set OSPT00 to 1 other than in one-shot pulse output mode.
5. A write interval of two cycles or more of the count clock selected by prescaler mode register
00 (PRM00) is required to write to OSPT00 successively.
6. Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1 simultaneously.
User’s Manual U16315EJ2V0UD
135
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(4) Prescaler mode register 00 (PRM00)
This register is used to set the 16-bit timer counter 00 (TM00) count clock and TI000 and TI010 input valid edges.
PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PRM00 to 00H.
Figure 6-8 Format of Prescaler Mode Register 00 (PRM00)
Address: FFBBH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
PRM00
ES101
ES100
ES001
ES000
0
0
PRM001
PRM000
ES101
ES100
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES001
ES000
0
0
Falling edge
0
1
Rising edge
TI010 valid edge selection
TI000 valid edge selection
1
0
Setting prohibited
1
1
Both falling and rising edges
PRM001
PRM000
0
0
fX (10 MHz)
0
1
fX/2 (2.5 MHz)
1
0
fX/2 (39.06 kHz)
1
1
TI000 valid edge
Count clock selection
2
8
Note
Note The external clock requires a pulse two cycles longer than internal clock (fX).
136
User’s Manual U16315EJ2V0UD
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the
Ring-OSC clock, the operation of 16-bit timer/event counter 00 is not guaranteed. When an
external clock is used and when the Ring-OSC clock is selected and supplied to the CPU, the
operation of 16-bit timer/event counter 00 is not guaranteed, either, because the Ring-OSC
clock is supplied as the sampling clock to eliminate noise.
2. Always set data to PRM00 after stopping the timer operation.
3. If the valid edge of TI000 is to be set for the count clock, do not set the clear & start mode
using the valid edge of TI000 and the capture trigger.
4. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is
immediately detected after the rising edge or both the rising and falling edges are set as the
valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00
(TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, when reenabling operation after the operation has been stopped once, the rising edge is not
detected.
5. When P01 is used as the TI010 valid edge, it cannot be used as the timer output (TO00), and
when used as TO00, it cannot be used as the TI010 valid edge.
(5) Port mode register 0 (PM0)
This register sets port 0 input/output in 1-bit units.
When using the P01/TO00/TI010 pin for timer output, set PM01 and the output latch of P01 to 0.
When using the P01/TO00/TI010 pin for timer input, clear PM01 to 0. At this time, the output latch of P01 may be
0 or 1.
PM0 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM0 to FFH.
Figure 6-9. Format of Port Mode Register 0 (PM0)
Address: FF20H
After reset: FFH
Symbol
7
6
5
4
PM0
1
1
1
1
PM0n
R/W
3
2
1
0
PM03 PM02 PM01 PM00
P0n pin I/O mode selection (n = 0 to 3)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
User’s Manual U16315EJ2V0UD
137
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4 Operation of 16-Bit Timer/Event Counter 00
6.4.1 Interval timer operation
Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown
in Figure 6-10 allows operation as an interval timer.
Setting
The basic operation setting procedure is as follows.
Set the CRC00 register (see Figure 6-10 for the set value).
Set any value to the CR000 register.
Set the count clock by using the PRM00 register.
Set the TMC00 register to start the operation (see Figure 6-10 for the set value).
Caution CR000 cannot be rewritten during TM00 operation.
Remark
For how to enable the INTTM000 interrupt, see CHAPTER 16 INTERRUPT FUNCTIONS.
Interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register
000 (CR000) as the interval.
When the count value of 16-bit timer counter 00 (TM00) matches the value set in CR000, counting continues with
the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated.
The count clock of the 16-bit timer/event counter 00 can be selected with bits 0 and 1 (PRM000, PRM001) of
prescaler mode register 00 (PRM00).
138
User’s Manual U16315EJ2V0UD
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-10. Control Register Settings for Interval Timer Operation
(a) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
1
1
0/1
0
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
0/1
0/1
0
CR000 used as compare register
(c) Prescaler mode register 00 (PRM00)
ES101 ES100 ES001 ES000
PRM00
0/1
0/1
0/1
0/1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the
description of the respective control registers for details.
User’s Manual U16315EJ2V0UD
139
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-11. Interval Timer Configuration Diagram
16-bit timer capture/compare
register 000 (CR000)
INTTM000
Selector
fX
fX/22
fX/28
TI000/P00
16-bit timer counter 00
(TM00)
Note
OVF00
Noise
eliminator
Clear
circuit
fX
Note OVF00 is set to 1 only when 16-bit timer capture/compare register 000 is set to FFFFH.
Figure 6-12. Timing of Interval Timer Operation
t
Count clock
TM00 count value
0000H
0001H
Timer operation enabled
CR000
N
N
0000H 0001H
Clear
N
N
0000H 0001H
Clear
N
N
INTTM000
Interrupt acknowledged
Remark
Interval time = (N + 1) × t
N = 0001H to FFFFH
140
User’s Manual U16315EJ2V0UD
N
Interrupt acknowledged
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4.2 PPG output operations
Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown
in Figure 6-13 allows operation as PPG (Programmable Pulse Generator) output.
Setting
The basic operation setting procedure is as follows.
Set the CRC00 register (see Figure 6-13 for the set value).
Set any value to the CR000 register as the cycle.
Set any value to the CR010 register as the duty factor.
Set the TOC00 register (see Figure 6-13 for the set value).
Set the count clock by using the PRM00 register.
Set the TMC00 register to start the operation (see Figure 6-13 for the set value).
Caution To change the value of the duty factor (the value of the CR010 register) during operation, see
Caution 2 in Figure 6-15 PPG Output Operation Timing.
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 interrupt, see CHAPTER 16 INTERRUPT FUNCTIONS.
In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle
that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer
capture/compare register 000 (CR000), respectively.
User’s Manual U16315EJ2V0UD
141
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-13. Control Register Settings for PPG Output Operation
(a) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
1
1
0
0
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
0
×
0
CR000 used as compare register
CR010 used as compare register
(c) 16-bit timer output control register 00 (TOC00)
7
TOC00
0
OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
0
0
1
0/1
0/1
1
1
Enables TO00 output
Inverts output on match between TM00 and CR000
Specifies initial value of TO00 output F/F (setting “11” is prohibited.)
Inverts output on match between TM00 and CR010
Disables one-shot pulse output
(d) Prescaler mode register 00 (PRM00)
ES101 ES100 ES001 ES000
PRM00
0/1
0/1
0/1
0/1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Cautions 1. Values in the following range should be set in CR000 and CR010:
0000H ≤ CR010 < CR000 ≤ FFFFH
2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of
(CR010 setting value + 1)/(CR000 setting value + 1).
Remark
142
×: Don’t care
User’s Manual U16315EJ2V0UD
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-14. Configuration of PPG Output
16-bit timer capture/compare
register 000 (CR000)
Selector
fX
fX/22
fX/28
Noise
eliminator
Output controller
TI000/P00
Clear
circuit
16-bit timer counter 00
(TM00)
fX
TO00/TI010/P01
16-bit timer capture/compare
register 010 (CR010)
Figure 6-15. PPG Output Operation Timing
t
Count clock
TM00 count value N
0000H 0001H
M−1
M
Clear
N−1
N
0000H 0001H
Clear
CR000 capture value
N
CR010 capture value
M
TO00
Pulse width: (M + 1) × t
1 cycle: (N + 1) × t
Cautions 1. CR000 cannot be rewritten during TM00 operation.
2. In the PPG output operation, change the pulse width (rewrite CR010) during TM00 operation
using the following procedure.
Disable the timer output inversion operation by match of TM00 and CR010 (TOC004 = 0)
Disable the INTTM010 interrupt (TMMK010 = 1)
Rewrite CR010
Wait for 1 cycle of the TM00 count clock
Enable the timer output inversion operation by match of TM00 and CR010 (TOC004 = 1)
Clear the interrupt request flag of INTTM010 (TMIF010 = 0)
Enable the INTTM010 interrupt (TMMK010 = 0)
Remark
0000H ≤ M < N ≤ FFFFH
User’s Manual U16315EJ2V0UD
143
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4.3
Pulse width measurement operations
It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer
counter 00 (TM00).
There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by
restarting the timer in synchronization with the edge of the signal input to the TI000 pin.
When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate
the necessary pulse width. Clear the overflow flag after checking it.
The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by
prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating
noise with a short pulse width.
Figure 6-16. CR010 Capture Operation with Rising Edge Specified
Count clock
TM00
N−3
N−2
N−1
N
N+1
TI000
Rising edge detection
N
CR010
INTTM010
Setting
The basic operation setting procedure is as follows.
Set the CRC00 register (see Figures 6-17, 6-20, 6-22, and 6-24 for the set value).
Set the count clock by using the PRM00 register.
Set the TMC00 register to start the operation (see Figures 6-17, 6-20, 6-22, and 6-24 for the set value).
Caution To use two capture registers, set the TI000 and TI010 pins.
Remarks 1. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 16
FUNCTIONS.
144
User’s Manual U16315EJ2V0UD
INTERRUPT
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(1) Pulse width measurement with free-running counter and one capture register
When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler mode
register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare
register 010 (CR010) and an external interrupt request signal (INTTM010) is set.
Specify both the rising and falling edges by using bits 4 and 5 (ES000 and ES001) of PRM00.
Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed
when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width.
Figure 6-17. Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register (When TI000 and CR010 Are Used)
(a) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
1
0/1
0
CR000 used as compare register
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES101 ES100 ES001 ES000
PRM00
0/1
0/1
1
1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies both edges for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
User’s Manual U16315EJ2V0UD
145
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-18. Configuration Diagram for Pulse Width Measurement with Free-Running Counter
fX/22
fX/28
Selector
fX
16-bit timer counter 00
(TM00)
OVF00
16-bit timer capture/compare
register 010 (CR010)
TI000
INTTM010
Internal bus
Figure 6-19. Timing of Pulse Width Measurement Operation with Free-Running Counter
and One Capture Register (with Both Edges Specified)
t
Count clock
TM00 count value
0000H 0001H
D0
D0 + 1
D1
D1 + 1
FFFFH 0000H
D2
D3
TI000 pin input
CR010 capture value
D0
D1
D2
D3
INTTM010
Note
OVF00
(D1 − D0) × t
(10000H − D1 + D2) × t
Note Clear OVF00 by software.
146
User’s Manual U16315EJ2V0UD
(D3 − D2) × t
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(2) Measurement of two pulse widths with free-running counter
When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure
the pulse widths of the two signals input to the TI000 pin and the TI010 pin.
When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to
the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt
request signal (INTTM010) is set.
Also, when the edge specified by bits 6 and 7 (ES100 and ES101) of PRM00 is input to the TI010 pin, the value
of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal
(INTTM000) is set.
Specify both the rising and falling edges as the edges of the TI000 and TI010 pins, by using bits 4 and 5 (ES000
and ES001) and bits 6 and 7 (ES100 and ES101) of PRM00.
Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a
capture operation is only performed when a valid level of the TI000 or TI010 pin is detected twice, thus
eliminating noise with a short pulse width.
Figure 6-20. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter
(a) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
1
0
1
CR000 used as capture register
Captures valid edge of TI010 pin to CR000
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES101 ES100 ES001 ES000
PRM00
1
1
1
1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies both edges for pulse width detection.
Specifies both edges for pulse width detection.
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
User’s Manual U16315EJ2V0UD
147
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-21. Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified)
t
Count clock
TM00 count value
0000H 0001H
D0
D0 + 1
D1
D1 + 1
FFFFH 0000H
D2
D2 + 1 D2 + 2
TI000 pin input
CR010 capture value
D0
D1
D2
INTTM010
TI010 pin input
CR000 capture value
D1
D2 + 1
INTTM000
Note
OVF00
(D1 − D0) × t
(10000H − D1 + D2) × t
(10000H − D1 + (D2 + 1)) × t
Note Clear OVF00 by software.
148
User’s Manual U16315EJ2V0UD
(D3 − D2) × t
D3
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(3) Pulse width measurement with free-running counter and two capture registers
When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse width
of the signal input to the TI000 pin.
When the rising or falling edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00
(PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010
(CR010) and an interrupt request signal (INTTM010) is set.
Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken into
16-bit timer capture/compare register 000 (CR000).
Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a
capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise
with a short pulse width.
Figure 6-22. Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers (with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
1
1
1
CR000 used as capture register
Captures to CR000 at inverse edge
to valid edge of TI000.
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES101 ES100 ES001 ES000
PRM00
0/1
0/1
0
1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
User’s Manual U16315EJ2V0UD
149
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter
and Two Capture Registers (with Rising Edge Specified)
t
Count clock
TM00 count value
0000H 0001H
D0
D0 + 1
D1
D1 + 1
FFFFH 0000H
D2
D2 + 1
D3
TI000 pin input
CR010 capture value
D0
CR000 capture value
D2
D1
D3
INTTM010
Note
OVF00
(D1 − D0) × t
(10000H − D1 + D2) × t
(D3 − D2) × t
Note Clear OVF00 by software.
(4) Pulse width measurement by means of restart
When input of a valid edge to the TI000 pin is detected, the count value of 16-bit timer counter 00 (TM00) is taken
into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to the TI000
pin is measured by clearing TM00 and restarting the count operation.
Either of two edgesrising or fallingcan be selected using bits 4 and 5 (ES000 and ES001) of prescaler mode
register 00 (PRM00).
Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00) and a
capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise
with a short pulse width.
150
User’s Manual U16315EJ2V0UD
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-24. Control Register Settings for Pulse Width Measurement by Means of Restart
(with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
1
0
0/1
0
Clears and starts at valid edge of TI000 pin.
(b) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
1
1
1
CR000 used as capture register
Captures to CR000 at inverse edge to valid edge of TI000.
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES101 ES100 ES001 ES000
PRM00
0/1
0/1
0
1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Figure 6-25. Timing of Pulse Width Measurement Operation by Means of Restart
(with Rising Edge Specified)
t
Count clock
TM00 count value
0000H 0001H
D0
0000H 0001H
D2 0000H 0001H
D1
TI000 pin input
CR010 capture value
D0
D2
D1
CR000 capture value
INTTM010
D1 × t
D2 × t
User’s Manual U16315EJ2V0UD
151
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4.4 External event counter operation
Setting
The basic operation setting procedure is as follows.
Set the CRC00 register (see Figure 6-26 for the set value).
Set the count clock by using the PRM00 register.
Set any value to the CR000 register (0000H cannot be set).
Set the TMC00 register to start the operation (see Figure 6-26 for the set value).
Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 interrupt, see CHAPTER 16 INTERRUPT FUNCTIONS.
The external event counter counts the number of external clock pulses input to the TI000 pin using 16-bit timer
counter 00 (TM00).
TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input.
When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is
cleared to 0 and the interrupt request signal (INTTM000) is generated.
Input a value other than 0000H to CR000 (a count operation with 1-bit pulse cannot be carried out).
Any of three edgesrising, falling, or both edgescan be selected using bits 4 and 5 (ES000 and ES001) of
prescaler mode register 00 (PRM00).
Sampling is performed using the internal clock (fX) and an operation is only performed when a valid level of the
TI000 pin is detected twice, thus eliminating noise with a short pulse width.
152
User’s Manual U16315EJ2V0UD
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-26. Control Register Settings in External Event Counter Mode (with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
1
1
0/1
0
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
0/1
0/1
0
CR000 used as compare register
(c) Prescaler mode register 00 (PRM00)
ES101 ES100 ES001 ES000
PRM00
0/1
0/1
0
1
3
2
0
0
PRM001 PRM000
1
1
Selects external clock.
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter.
See the description of the respective control registers for details.
User’s Manual U16315EJ2V0UD
153
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-27. Configuration Diagram of External Event Counter
Internal bus
16-bit timer capture/compare
register 000 (CR000)
Match
INTTM000
Clear
Noise eliminator
fX
16-bit timer counter 00 (TM00)
OVF00Note
Valid edge of TI000
Note OVF00 is set to 1 only when CR000 is set to FFFFH.
Figure 6-28. External Event Counter Operation Timing (with Rising Edge Specified)
TI000 pin input
TM00 count value
CR000
0000H 0001H 0002H 0003H 0004H 0005H
N−1
N
0000H 0001H 0002H 0003H
N
INTTM000
Caution When reading the external event counter count value, TM00 should be read.
154
User’s Manual U16315EJ2V0UD
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4.5 Square-wave output operation
Setting
The basic operation setting procedure is as follows.
Set the count clock by using the PRM00 register.
Set the CRC00 register (see Figure 6-29 for the set value).
Set the TOC00 register (see Figure 6-29 for the set value).
Set any value to the CR000 register (0000H cannot be set).
Set the TMC00 register to start the operation (see Figure 6-29 for the set value).
Caution CR000 cannot be rewritten during TM00 operation.
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 interrupt, see CHAPTER 16 INTERRUPT FUNCTIONS.
A square wave with any selected frequency can be output at intervals determined by the count value preset to 16bit timer capture/compare register 000 (CR000).
The TO00 pin output status is reversed at intervals determined by the count value preset to CR000 + 1 by setting
bit 0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a square wave
with any selected frequency to be output.
Figure 6-29. Control Register Settings in Square-Wave Output Mode (1/2)
(a) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
1
1
0
0
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
0/1
0/1
0
CR000 used as compare register
User’s Manual U16315EJ2V0UD
155
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-29. Control Register Settings in Square-Wave Output Mode (2/2)
(c) 16-bit timer output control register 00 (TOC00)
7
TOC00
OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
0
0
0
0
0/1
0/1
1
1
Enables TO00 output.
Inverts output on match between TM00 and CR000.
Specifies initial value of TO00 output F/F (setting “11” is prohibited).
Does not invert output on match between TM00 and CR010.
Disables one-shot pulse output.
(d) Prescaler mode register 00 (PRM00)
ES101 ES100 ES001 ES000
PRM00
0/1
0/1
0/1
0/1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the
description of the respective control registers for details.
Figure 6-30. Square-Wave Output Operation Timing
Count clock
TM00 count value
CR000
0000H 0001H 0002H
N−1
N
0000H 0001H 0002H
N
INTTM000
TO00 pin output
156
User’s Manual U16315EJ2V0UD
N−1
N
0000H
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4.6 One-shot pulse output operation
16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external
trigger (TI000 pin input).
Setting
The basic operation setting procedure is as follows.
Set the count clock by using the PRM00 register.
Set the CRC00 register (see Figures 6-31 and 6-33 for the set value).
Set the TOC00 register (see Figures 6-31 and 6-33 for the set value).
Set any value to the CR000 and CR010 registers (0000H cannot be set).
Set the TMC00 register to start the operation (see Figures 6-31 and 6-33 for the set value).
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 (if necessary, INTTM010) interrupt, see CHAPTER 16
INTERRUPT FUNCTIONS.
(1) One-shot pulse output with software trigger
A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),
capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in
Figure 6-27, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software.
By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes
active at the count value (N) set in advance to 16-bit timer capture/compare register 010 (CR010). After that, the
output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000
(CR000)Note.
Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00
register, the TMC003 and TMC002 bits of the TMC00 register must be set to 00.
Note The case where N < M is described here. When N > M, the output becomes active with the CR000
register and inactive with the CR010 register. Do not set N to M.
Cautions 1. Do not set the OSPT00 bit to 1 while the one-shot pulse is being output. To output the oneshot pulse again, wait until the current one-shot pulse output is completed.
2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software
trigger, do not change the level of the TI000 pin or its alternate-function port pin.
Because the external trigger is valid even in this case, the timer is cleared and started even
at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a
pulse at an undesired timing.
User’s Manual U16315EJ2V0UD
157
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-31. Control Register Settings for One-Shot Pulse Output with Software Trigger
(a) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
TMC003
0
0
0
0
0
TMC002 TMC001
1
OVF00
0
0
Free-running mode
(b) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
0
0/1
0
CR000 as compare register
CR010 as compare register
(c) 16-bit timer output control register 00 (TOC00)
7
TOC00
0
OSPT00 OSPE00 TOC004
0
1
LVS00
LVR00
TOC001
TOE00
0/1
0/1
1
1
1
Enables TO00 output
Inverts output upon match
between TM00 and CR000
Specifies initial value of
TO00 output F/F (setting “11” is prohibited.)
Inverts output upon match
between TM00 and CR010
Sets one-shot pulse output mode
Set to 1 for output
(d) Prescaler mode register 00 (PRM00)
PRM00
ES101
ES100
ES001
ES000
3
2
0/1
0/1
0/1
0/1
0
0
PRM001 PRM000
0/1
0/1
Selects count clock.
Setting invalid
(setting “10” is prohibited.)
Setting invalid
(setting “10” is prohibited.)
Caution Do not set 0000H to the CR000 and CR010 registers.
158
User’s Manual U16315EJ2V0UD
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-32. Timing of One-Shot Pulse Output Operation with Software Trigger
Set TMC00 to 0CH
(TM00 count starts)
Count clock
TM00 count 0000H 0001H
N
N+1
0000H
N–1
N
M–1
M
M+1 M+2
CR010 set value
N
N
N
N
CR000 set value
M
M
M
M
OSPT00
INTTM010
INTTM000
TO00 pin output
Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is
set to the TMC003 and TMC002 bits.
Remark
N M, the output becomes active with the CR000
register and inactive with the CR010 register. Do not set N to M.
Caution Even if the external trigger is generated again while the one-shot pulse is output, it is ignored.
User’s Manual U16315EJ2V0UD
159
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-33. Control Register Settings for One-Shot Pulse Output with External Trigger
(with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
TMC003
0
0
0
0
1
TMC002 TMC001
0
OVF00
0
0
Clears and starts at
valid edge of TI000 pin
(b) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
0
0/1
0
CR000 used as compare register
CR010 used as compare register
(c) 16-bit timer output control register 00 (TOC00)
7
TOC00
0
OSPT00 OSPE00 TOC004
0
1
1
LVS00
LVR00
TOC001
TOE00
0/1
0/1
1
1
Enables TO00 output
Inverts output upon match
between TM00 and CR000
Specifies initial value of
TO00 output F/F (setting “11” is prohibited.)
Inverts output upon match
between TM00 and CR010
Sets one-shot pulse output mode
(d) Prescaler mode register 00 (PRM00)
PRM00
ES101
ES100
ES001
ES000
3
2
0/1
0/1
0
1
0
0
PRM001 PRM000
0/1
0/1
Selects count clock
(setting “11” is prohibited).
Specifies the rising edge
for pulse width detection.
Setting invalid
(setting “10” is prohibited.)
Caution Do not set 0000H to the CR000 and CR010 registers.
160
User’s Manual U16315EJ2V0UD
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-34. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)
When TMC00 is set to 08H
(TM00 count starts)
t
Count clock
TM00 count value 0000H 0001H
0000H
N
N+1 N+2
M−2 M−1
M
M+1 M+2
CR010 set value
N
N
N
N
CR000 set value
M
M
M
M
TI000 pin input
INTTM010
INTTM000
TO00 pin output
Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is
set to the TMC002 and TMC003 bits.
Remark
N
工商网监
湘ICP备2023018690号
