To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
User’s Manual
78K0/KF1+
8-Bit Single-Chip Microcontrollers
μPD78F0148H
μPD78F0148H(A)
μPD78F0148H(A1)
μPD78F0148HD
Document No. U16819EJ3V0UD00 (3rd edition)
Date Published December 2005 NS CP(K)
2003
Printed in Japan
[MEMO]
2
User’s Manual U16819EJ3V0UD
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
User’s Manual U16819EJ3V0UD
3
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
• The information in this document is current as of December, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
• NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
4
User’s Manual U16819EJ3V0UD
INTRODUCTION
Readers
This manual is intended for user engineers who wish to understand the functions of the
78K0/KF1+ and design and develop application systems and programs for these
devices.
The target products are as follows.
78K0/KF1+: μPD78F0148H, 78F0148H(A), 78F0148H(A1), 78F0148HD
Purpose
This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization
The 78K0/KF1+ manual is separated into two parts: this manual and the instructions
edition (common to the 78K/0 Series).
78K0/KF1+
78K/0 Series
User’s Manual
User’s Manual
(This Manual)
Instructions
• Pin functions
• CPU functions
• Internal block functions
• Instruction set
• Interrupts
• Explanation of each instruction
• Other on-chip peripheral functions
• Electrical specifications
How to Read This Manual
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• When using this manual as the manual for (A) grade products and (A1) grade
products:
→ Only the quality grade differs between standard products and (A), (A1) grade
products. Read the part number as follows.
•
μPD780148H → μPD780148H(A), 780148H(A1)
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark shows major
revised points. The revised points can be easily searched by copying an "" in
the PDF file and specifying it in the "Find what:" field.
• How to interpret the register format:
→ For a bit number enclosed in brackets, the bit name is defined as a reserved word
in the RA78K0, and is defined as an sfr variable by #pragma sfr directive in the
CC78K0.
• To check the details of a register when you know the register name:
→ Refer to APPENDIX C REGISTER INDEX.
• To know details of the 78K/0 Series instructions:
→ Refer to the separate document 78K/0 Series Instructions User’s Manual
(U12326E).
User’s Manual U16819EJ3V0UD
5
Caution Examples in this manual employ the “standard” quality grade for
general electronics.
When using examples in this manual for the
“special” quality grade, review the quality grade of each part and/or
circuit actually used.
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note:
Footnote for item marked with Note in the text.
Caution:
Information requiring particular attention
Remark:
Supplementary information
... ×××× or ××××B
Numerical representations: Binary
... ××××
Decimal
Hexadecimal
... ××××H
Differences Between 78K0/KF1+ and 78K0/KF1
Series Name
78K0/KF1+
78K0/KF1
Item
Mask ROM version
None
Available
Flash
Power supply
Single power supply
Two power supplies
memory
Self-programming function
Available
None
Option byte
Internal oscillator can be stopped/cannot
None
version
be stopped selectable
Version with on-chip debug function
Available (μPD78F0148HD)
None
Regulator
None
Available
Power-on clear function
2.1 V ±0.1 V (fixed)
2.85 V ±0.15 V or 3.5 V ±0.2 V selectable
Minimum instruction execution time
0.125 μs (at 16 MHz operation)
0.166 μs (at 12 MHz operation)
6
User’s Manual U16819EJ3V0UD
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
78K0/KF1+ User’s Manual
This manual
78K0/KF1 User’s Manual
U15947E
78K/0 Series Instructions User’s Manual
U12326E
78K0/Kx1+ Flash Memory Self Programming User’s Manual
U16701E
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name
RA78K0 Ver. 3.80 Assembler Package
CC78K0 Ver. 3.70 C Compiler
SM+ System Simulator
ID78K0-QB Ver. 2.90 Integrated Debugger
Document No.
Operation
U17199E
Language
U17198E
Structured Assembly Language
U17197E
Operation
U17201E
Language
U17200E
Operation
U17246E
User Open Interface
U17247E
Operation
U17437E
PM plus Ver. 5.20
U16934E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name
Document No.
QB-78K0KX1H In-Circuit Emulator
U17081E
QB-78K0MINI On-Chip Debug Emulator
U17029E
Documents Related to Flash Memory Programming
Document Name
PG-FP4 Flash Memory Programmer User’s Manual
Document No.
U15260E
Other Documents
Document Name
SEMICONDUCTOR SELECTION GUIDE − Products and Packages −
Document No.
X13769X
Semiconductor Device Mount Manual
Note
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
User’s Manual U16819EJ3V0UD
7
CONTENTS
CHAPTER 1 OUTLINE ............................................................................................................................ 16
1.1 Features ...................................................................................................................................... 16
1.2 Applications................................................................................................................................ 17
1.3 Ordering Information ................................................................................................................. 18
1.4 Pin Configuration (Top View).................................................................................................... 19
1.5 Kx1 Series Lineup ...................................................................................................................... 21
1.6
1.7
1.5.1
78K0/Kx1, 78K0/Kx1+ product lineup ............................................................................................ 21
1.5.2
V850ES/Kx1, V850ES/Kx1+ product lineup................................................................................... 24
Block Diagram ............................................................................................................................ 27
Outline of Functions .................................................................................................................. 28
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 31
2.1 Pin Function List ........................................................................................................................ 31
2.2 Description of Pin Functions .................................................................................................... 35
2.2.1
P00 to P06 (port 0) ........................................................................................................................ 35
2.2.2
P10 to P17 (port 1) ........................................................................................................................ 36
2.2.3
P20 to P27 (port 2) ........................................................................................................................ 37
2.2.4
P30 to P33 (port 3) ........................................................................................................................ 37
2.2.5
P40 to P47 (port 4) ........................................................................................................................ 38
2.2.6
P50 to P57 (port 5) ........................................................................................................................ 38
2.2.7
P60 to P67 (port 6) ........................................................................................................................ 38
2.2.8
P70 to P77 (port 7) ........................................................................................................................ 39
2.2.9
P120 (port 12)................................................................................................................................ 39
2.2.10 P130 (port 13)................................................................................................................................ 39
2.2.11 P140 to P145 (port 14) .................................................................................................................. 39
2.2.12 AVREF ............................................................................................................................................. 40
2.2.13 AVSS ............................................................................................................................................... 40
2.2.14 RESET........................................................................................................................................... 40
2.2.15 X1 and X2 ...................................................................................................................................... 41
2.2.16 XT1 and XT2.................................................................................................................................. 41
2.2.17 VDD and EVDD ................................................................................................................................. 41
2.2.18 VSS and EVSS ................................................................................................................................. 41
2.2.19 FLMD0 and FLMD1 ....................................................................................................................... 41
2.3
Pin I/O Circuits and Recommended Connection of Unused Pins......................................... 42
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 46
3.1 Memory Space ............................................................................................................................ 46
3.1.1
3.2
3.3
8
Internal program memory space .................................................................................................... 49
3.1.2
Internal data memory space .......................................................................................................... 50
3.1.3
Special function register (SFR) area.............................................................................................. 50
3.1.4
Data memory addressing............................................................................................................... 51
Processor Registers .................................................................................................................. 53
3.2.1
Control registers ............................................................................................................................ 53
3.2.2
General-purpose registers ............................................................................................................. 57
3.2.3
Special function registers (SFRs) .................................................................................................. 58
Instruction Address Addressing .............................................................................................. 64
User’s Manual U16819EJ3V0UD
3.4
3.3.1
Relative addressing ........................................................................................................................64
3.3.2
Immediate addressing ....................................................................................................................65
3.3.3
Table indirect addressing ...............................................................................................................66
3.3.4
Register addressing........................................................................................................................66
Operand Address Addressing .................................................................................................. 67
3.4.1
Implied addressing .........................................................................................................................67
3.4.2
Register addressing........................................................................................................................68
3.4.3
Direct addressing............................................................................................................................69
3.4.4
Short direct addressing...................................................................................................................70
3.4.5
Special function register (SFR) addressing ....................................................................................71
3.4.6
Register indirect addressing ...........................................................................................................72
3.4.7
Based addressing...........................................................................................................................73
3.4.8
Based indexed addressing .............................................................................................................74
3.4.9
Stack addressing ............................................................................................................................75
CHAPTER 4 PORT FUNCTIONS........................................................................................................... 76
4.1 Port Functions............................................................................................................................ 76
4.2 Port Configuration ..................................................................................................................... 78
4.2.1
Port 0..............................................................................................................................................79
4.2.2
Port 1..............................................................................................................................................83
4.2.3
Port 2..............................................................................................................................................88
4.2.4
Port 3..............................................................................................................................................89
4.2.5
Port 4..............................................................................................................................................91
4.2.6
Port 5..............................................................................................................................................92
4.2.7
Port 6..............................................................................................................................................93
4.2.8
Port 7..............................................................................................................................................96
4.2.9
Port 12............................................................................................................................................97
4.2.10 Port 13............................................................................................................................................98
4.2.11 Port 14............................................................................................................................................99
4.3
4.4
Registers Controlling Port Function ...................................................................................... 103
Port Function Operations........................................................................................................ 108
4.4.1
Writing to I/O port .........................................................................................................................108
4.4.2
Reading from I/O port ...................................................................................................................108
4.4.3
Operations on I/O port ..................................................................................................................108
CHAPTER 5 EXTERNAL BUS INTERFACE ...................................................................................... 109
5.1 External Bus Interface ............................................................................................................. 109
5.2 Registers Controlling External Bus Interface ....................................................................... 112
5.3 External Bus Interface Function Timing................................................................................ 114
5.4 Example of Connection with Memory.................................................................................... 119
CHAPTER 6 CLOCK GENERATOR .................................................................................................... 120
6.1 Functions of Clock Generator ................................................................................................ 120
6.2 Configuration of Clock Generator .......................................................................................... 120
6.3 Registers Controlling Clock Generator ................................................................................. 122
6.4 System Clock Oscillator.......................................................................................................... 129
6.4.1
High-speed system clock oscillator...............................................................................................129
6.4.2
Subsystem clock oscillator............................................................................................................129
6.4.3
When subsystem clock is not used...............................................................................................132
User’s Manual U16819EJ3V0UD
9
6.5
6.6
6.7
6.8
6.4.4
Internal oscillator...........................................................................................................................132
6.4.5
Prescaler.......................................................................................................................................132
Clock Generator Operation ..................................................................................................... 133
Time Required to Switch Between Internal Oscillation Clock and High-Speed
System Clock............................................................................................................................ 140
Time Required for CPU Clock Switchover............................................................................. 141
Clock Switching Flowchart and Register Setting ................................................................. 142
6.8.1
Switching from internal oscillation clock to high-speed system clock............................................142
6.8.2
Switching from high-speed system clock to internal oscillation clock............................................143
6.8.3
Switching from high-speed system clock to subsystem clock .......................................................144
6.8.4
Switching from subsystem clock to high-speed system clock .......................................................145
6.8.5
Register settings ...........................................................................................................................146
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01......................................................... 147
7.1 Functions of 16-Bit Timer/Event Counters 00 and 01........................................................... 147
7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 .................................................... 148
7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 ........................................... 153
7.4 Operation of 16-Bit Timer/Event Counters 00 and 01........................................................... 164
7.4.1
7.5
Interval timer operation .................................................................................................................164
7.4.2
PPG output operations .................................................................................................................167
7.4.3
Pulse width measurement operations ...........................................................................................170
7.4.4
External event counter operation ..................................................................................................178
7.4.5
Square-wave output operation......................................................................................................181
7.4.6
One-shot pulse output operation...................................................................................................183
Cautions for 16-Bit Timer/Event Counters 00 and 01 ........................................................... 188
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................... 191
8.1 Functions of 8-Bit Timer/Event Counters 50 and 51............................................................. 191
8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 ...................................................... 193
8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ............................................. 195
8.4 Operations of 8-Bit Timer/Event Counters 50 and 51........................................................... 200
8.4.1
8.5
Operation as interval timer............................................................................................................200
8.4.2
Operation as external event counter .............................................................................................202
8.4.3
Square-wave output operation......................................................................................................203
8.4.4
PWM output operation ..................................................................................................................204
Cautions for 8-Bit Timer/Event Counters 50 and 51 ............................................................. 208
CHAPTER 9 8-BIT TIMERS H0 AND H1 .......................................................................................... 209
9.1 Functions of 8-Bit Timers H0 and H1 ..................................................................................... 209
9.2 Configuration of 8-Bit Timers H0 and H1............................................................................... 209
9.3 Registers Controlling 8-Bit Timers H0 and H1 ...................................................................... 213
9.4 Operation of 8-Bit Timers H0 and H1 ..................................................................................... 219
9.4.1
Operation as interval timer/square-wave output ...........................................................................219
9.4.2
Operation as PWM output mode...................................................................................................222
9.4.3
Carrier generator mode operation (8-bit timer H1 only) ................................................................228
CHAPTER 10 WATCH TIMER.............................................................................................................. 235
10.1 Functions of Watch Timer ....................................................................................................... 235
10.2 Configuration of Watch Timer................................................................................................. 237
10
User’s Manual U16819EJ3V0UD
10.3 Register Controlling Watch Timer .......................................................................................... 237
10.4 Watch Timer Operations ......................................................................................................... 239
10.4.1 Watch timer operation ..................................................................................................................239
10.4.2 Interval timer operation.................................................................................................................240
10.5 Cautions for Watch Timer ....................................................................................................... 241
CHAPTER 11 WATCHDOG TIMER ..................................................................................................... 242
11.1 Functions of Watchdog Timer ................................................................................................ 242
11.2 Configuration of Watchdog Timer.......................................................................................... 244
11.3 Registers Controlling Watchdog Timer ................................................................................. 245
11.4 Operation of Watchdog Timer ................................................................................................ 248
11.4.1 Watchdog timer operation when “Internal oscillator cannot be stopped” is selected
by option byte ...............................................................................................................................248
11.4.2 Watchdog timer operation when “Internal oscillator can be stopped
by software” is selected by option byte.........................................................................................249
11.4.3 Watchdog timer operation in STOP mode (when “Internal oscillator can be stopped
by software” is selected by option byte)........................................................................................250
11.4.4 Watchdog timer operation in HALT mode (when “Internal oscillator can be stopped
by software” is selected by option byte)........................................................................................252
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 253
12.1 Functions of Clock Output/Buzzer Output Controller.......................................................... 253
12.2 Configuration of Clock Output/Buzzer Output Controller ................................................... 254
12.3 Register Controlling Clock Output/Buzzer Output Controller............................................. 254
12.4 Clock Output/Buzzer Output Controller Operations ............................................................ 256
12.4.1 Clock output operation..................................................................................................................256
12.4.2 Operation as buzzer output ..........................................................................................................256
CHAPTER 13 A/D CONVERTER ......................................................................................................... 257
13.1 Functions of A/D Converter .................................................................................................... 257
13.2 Configuration of A/D Converter.............................................................................................. 258
13.3 Registers Used in A/D Converter ........................................................................................... 260
13.4 A/D Converter Operations....................................................................................................... 265
13.4.1 Basic operations of A/D converter ................................................................................................265
13.4.2 Input voltage and conversion results ............................................................................................267
13.4.3 A/D converter operation mode......................................................................................................268
13.5 How to Read A/D Converter Characteristics Table .............................................................. 271
13.6 Cautions for A/D Converter..................................................................................................... 273
CHAPTER 14 SERIAL INTERFACE UART0 ...................................................................................... 278
14.1 Functions of Serial Interface UART0 ..................................................................................... 278
14.2 Configuration of Serial Interface UART0 ............................................................................... 279
14.3 Registers Controlling Serial Interface UART0 ...................................................................... 282
14.4 Operation of Serial Interface UART0...................................................................................... 287
14.4.1 Operation stop mode ....................................................................................................................287
14.4.2 Asynchronous serial interface (UART) mode................................................................................288
14.4.3 Dedicated baud rate generator .....................................................................................................294
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11
CHAPTER 15 SERIAL INTERFACE UART6 ...................................................................................... 299
15.1 Functions of Serial Interface UART6...................................................................................... 299
15.2 Configuration of Serial Interface UART6 ............................................................................... 303
15.3 Registers Controlling Serial Interface UART6....................................................................... 306
15.4 Operation of Serial Interface UART6 ...................................................................................... 315
15.4.1 Operation stop mode ....................................................................................................................315
15.4.2 Asynchronous serial interface (UART) mode................................................................................316
15.4.3 Dedicated baud rate generator .....................................................................................................330
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 ................................................................ 337
16.1 Functions of Serial Interfaces CSI10 and CSI11 ................................................................... 337
16.2 Configuration of Serial Interfaces CSI10 and CSI11............................................................. 338
16.3 Registers Controlling Serial Interfaces CSI10 and CSI11 .................................................... 340
16.4 Operation of Serial Interfaces CSI10 and CSI11 ................................................................... 346
16.4.1 Operation stop mode ....................................................................................................................346
16.4.2 3-wire serial I/O mode...................................................................................................................347
CHAPTER 17 SERIAL INTERFACE CSIA0........................................................................................ 357
17.1 Functions of Serial Interface CSIA0 ....................................................................................... 357
17.2 Configuration of Serial Interface CSIA0................................................................................. 358
17.3 Registers Controlling Serial Interface CSIA0 ........................................................................ 360
17.4 Operation of Serial Interface CSIA0 ....................................................................................... 369
17.4.1 Operation stop mode ....................................................................................................................369
17.4.2 3-wire serial I/O mode...................................................................................................................370
17.4.3 3-wire serial I/O mode with automatic transmit/receive function ...................................................375
CHAPTER 18 MULTIPLIER/DIVIDER ................................................................................................... 397
18.1 Functions of Multiplier/Divider ............................................................................................... 397
18.2 Configuration of Multiplier/Divider ......................................................................................... 397
18.3 Register Controlling Multiplier/Divider .................................................................................. 401
18.4 Operations of Multiplier/Divider.............................................................................................. 402
18.4.1 Multiplication operation .................................................................................................................402
18.4.2 Division operation .........................................................................................................................404
CHAPTER 19 INTERRUPT FUNCTIONS ............................................................................................ 406
19.1 Interrupt Function Types ......................................................................................................... 406
19.2 Interrupt Sources and Configuration ..................................................................................... 406
19.3 Registers Controlling Interrupt Functions............................................................................. 410
19.4 Interrupt Servicing Operations ............................................................................................... 418
19.4.1 Maskable interrupt acknowledgment ............................................................................................418
19.4.2 Software interrupt request acknowledgment.................................................................................420
19.4.3 Multiple interrupt servicing ............................................................................................................421
19.4.4 Interrupt request hold....................................................................................................................424
CHAPTER 20 KEY INTERRUPT FUNCTION ..................................................................................... 425
20.1 Functions of Key Interrupt ...................................................................................................... 425
20.2 Configuration of Key Interrupt................................................................................................ 425
20.3 Register Controlling Key Interrupt ......................................................................................... 426
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User’s Manual U16819EJ3V0UD
CHAPTER 21 STANDBY FUNCTION.................................................................................................. 427
21.1 Standby Function and Configuration..................................................................................... 427
21.1.1 Standby function...........................................................................................................................427
21.1.2 Registers controlling standby function ..........................................................................................429
21.2 Standby Function Operation................................................................................................... 431
21.2.1 HALT mode ..................................................................................................................................431
21.2.2 STOP mode..................................................................................................................................436
CHAPTER 22 RESET FUNCTION ....................................................................................................... 440
22.1 Register for Confirming Reset Source .................................................................................. 447
CHAPTER 23 CLOCK MONITOR ........................................................................................................ 448
23.1 Functions of Clock Monitor..................................................................................................... 448
23.2 Configuration of Clock Monitor .............................................................................................. 448
23.3 Registers Controlling Clock Monitor ..................................................................................... 449
23.4 Operation of Clock Monitor..................................................................................................... 450
CHAPTER 24 POWER-ON-CLEAR CIRCUIT ..................................................................................... 455
24.1 Functions of Power-on-Clear Circuit ..................................................................................... 455
24.2 Configuration of Power-on-Clear Circuit............................................................................... 456
24.3 Operation of Power-on-Clear Circuit ..................................................................................... 456
24.4 Cautions for Power-on-Clear Circuit...................................................................................... 457
CHAPTER 25 LOW-VOLTAGE DETECTOR ....................................................................................... 459
25.1 Functions of Low-Voltage Detector ....................................................................................... 459
25.2 Configuration of Low-Voltage Detector................................................................................. 459
25.3 Registers Controlling Low-Voltage Detector ........................................................................ 460
25.4 Operation of Low-Voltage Detector........................................................................................ 462
25.5 Cautions for Low-Voltage Detector........................................................................................ 466
CHAPTER 26 OPTION BYTE............................................................................................................... 469
26.1 Functions of Option Bytes ...................................................................................................... 469
26.2 Format of Option Byte ............................................................................................................. 470
CHAPTER 27 FLASH MEMORY.......................................................................................................... 472
27.1 Internal Memory Size Switching Register ............................................................................. 473
27.2 Internal Expansion RAM Size Switching Register................................................................ 474
27.3 Writing with Flash Programmer.............................................................................................. 475
27.4 Programming Environment..................................................................................................... 479
27.5 Communication Mode ............................................................................................................. 479
27.6 Connection of Pins on Board ................................................................................................. 482
27.6.1 FLMD0 pin ....................................................................................................................................482
27.6.2 FLMD1 pin ....................................................................................................................................482
27.6.3 Serial interface pins ......................................................................................................................483
27.6.4 RESET pin....................................................................................................................................485
27.6.5 Port pins .......................................................................................................................................485
27.6.6 Other signal pins...........................................................................................................................485
27.6.7 Power supply ................................................................................................................................485
27.7 Programming Method.............................................................................................................. 486
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13
27.7.1 Controlling flash memory ..............................................................................................................486
27.7.2 Flash memory programming mode ...............................................................................................487
27.7.3 Selecting communication mode ....................................................................................................488
27.7.4 Communication commands ..........................................................................................................489
27.8 Flash Memory Programming by Self-Writing ........................................................................ 490
27.8.1 Registers used for self-programming function ..............................................................................491
27.9 Boot Swap Function................................................................................................................. 495
27.9.1 Outline of boot swap function........................................................................................................495
27.9.2 Memory map and boot area..........................................................................................................496
CHAPTER 28 ON-CHIP DEBUG FUNCTION (μPD78F0148HD ONLY) .......................................... 498
28.1 On-Chip Debug Security ID ..................................................................................................... 499
CHAPTER 29 INSTRUCTION SET....................................................................................................... 500
29.1 Conventions Used in Operation List ...................................................................................... 500
29.1.1 Operand identifiers and specification methods .............................................................................500
29.1.2 Description of operation column ...................................................................................................501
29.1.3 Description of flag operation column.............................................................................................501
29.2 Operation List ........................................................................................................................... 502
29.3 Instructions Listed by Addressing Type................................................................................ 510
CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE
PRODUCTS)...................................................................................................................513
CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) ................................ 536
CHAPTER 32 PACKAGE DRAWINGS ................................................................................................ 554
CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS........................................................... 556
CHAPTER 34 CAUTIONS FOR WAIT................................................................................................. 558
34.1 Cautions for Wait...................................................................................................................... 558
34.2 Peripheral Hardware That Generates Wait ............................................................................ 559
34.3 Example of Wait Occurrence................................................................................................... 560
APPENDIX A DEVELOPMENT TOOLS............................................................................................... 561
A.1 Software Package..................................................................................................................... 564
A.2 Language Processing Software.............................................................................................. 564
A.3 Control Software ...................................................................................................................... 565
A.4 Flash Memory Writing Tools ................................................................................................... 565
A.5 Debugging Tools (Hardware) .................................................................................................. 566
A.5.1
When using in-circuit emulator QB-78K0KX1H.............................................................................566
A.5.2
When using on-chip debug emulator QB-78K0MINI .....................................................................567
A.6 Debugging Tools (Software) ................................................................................................... 567
APPENDIX B NOTES ON TARGET SYSTEM DESIGN ................................................................... 568
APPENDIX C REGISTER INDEX ......................................................................................................... 570
C.1 Register Index (In Alphabetical Order with Respect to Register Names) .......................... 570
C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ......................... 574
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User’s Manual U16819EJ3V0UD
APPENDIX D LIST OF CAUTIONS..................................................................................................... 578
APPENDIX E REVISION HISTORY ..................................................................................................... 604
E.1 Major Revisions in This Edition.............................................................................................. 604
E.2 Revision History up to Previous Edition ............................................................................... 604
User’s Manual U16819EJ3V0UD
15
CHAPTER 1 OUTLINE
1.1 Features
{ Minimum instruction execution time can be changed from high speed (0.125 μs: @ 16 MHz operation with highspeed system clock) to ultra low-speed (122 μs: @ 32.768 kHz operation with subsystem clock)
{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
{ ROM, RAM capacities
Program Memory
Item
Part Number
μPD78F0148H, 78F0148HD
Data Memory
(ROM)
Flash memory
Internal High-Speed RAM
Note
60 KB
1024 bytes
Internal Expansion RAM
Note
1024 bytes
Note The internal flash memory and internal expansion RAM capacities can be changed using the internal
memory size switching register (IMS) and the internal expansion RAM size switching register (IXS).
{ On-chip single-power-supply flash memory
{ Self-programming (with boot swap function)
{ On-chip debug function (μPD78F0148HD only)
{ Buffer RAM: 32 bytes (can be used for transfer in the 3-wire serial I/O mode with automatic transmit/receive
function)
{ External memory expansion space: 64 KB (on-chip external bus interface functionNote 1)
{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
{ Short startup is possible via the CPU default start using the internal oscillator
{ On-chip clock monitor function using the internal oscillator
{ On-chip watchdog timer (operable with internal oscillation clock)
{ On-chip multiplier/divider
{ On-chip key interrupt function
{ On-chip clock output/buzzer output controller
{ I/O ports: 67 (N-ch open drain: 4)
{ Timer: 8 channels
{ Serial interface: 4 channels
(UART (LIN (Local Interconnect Network)-bus supported): 1 channel, CSI: 1 channel, CSI/UARTNote 2: 1 channel,
CSI with automatic transmission/reception: 1 channel)
{ 10-bit resolution A/D converter: 8 channels
{ Supply voltage:
• Standard products and (A) grade products:
VDD = 2.5 to 5.5 V (with internal oscillation clock or subsystem clock: VDD = 2.0 to 5.5 VNote 3)
• (A1) grade products:
VDD = 2.7 to 5.5 V (with internal oscillation clock: VDD = 2.0 to 5.5 VNote 3)
{ Operating ambient temperature:
• Standard products and (A) grade products: TA = −40 to +85°C
• (A1) grade products: TA = −40 to +110°C
Notes 1. The external bus interface function cannot be used in (A1) grade products.
2. Select either of the functions of these alternate-function pins.
3. Use the product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the
power-on-clear (POC) circuit is 2.1 V ±0.1 V.
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User’s Manual U16819EJ3V0UD
CHAPTER 1 OUTLINE
1.2 Applications
{ Automotive equipment
• System control for body electricals (power windows, keyless entry reception, etc.)
• Sub-microcontrollers for control
{ Home audio, car audio
{ AV equipment
{ PC peripheral equipment (keyboards, etc.)
{ Household electrical appliances
• Outdoor air conditioner units
• Microwave ovens, electric rice cookers
{ Industrial equipment
• Pumps
• Vending machines
• FA (Factory Automation)
User’s Manual U16819EJ3V0UD
17
CHAPTER 1 OUTLINE
1.3 Ordering Information
• Flash memory version
Part Number
μPD78F0148HGK-9EU
μPD78F0148HGC-8BT
μPD78F0148HGK-9EU-A
μPD78F0148HGC-8BT-A
μPD78F0148HDGK-9EUNote
μPD78F0148HDGC-8BTNote
μPD78F0148HDGK-9EU-ANote
μPD78F0148HDGC-8BT-ANote
μPD78F0148HGK(A)-9EU
μPD78F0148HGC(A)-8BT
μPD78F0148HGK(A)-9EU-A
μPD78F0148HGC(A)-8BT-A
μPD78F0148HGK(A1)-9EU
μPD78F0148HGC(A1)-8BT
μPD78F0148HGK(A1)-9EU-A
μPD78F0148HGC(A1)-8BT-A
Package
Quality Grade
80-pin plastic TQFP (fine pitch) (12 × 12)
Standard
80-pin plastic QFP (14 × 14)
Standard
80-pin plastic TQFP (fine pitch) (12 × 12)
Standard
80-pin plastic QFP (14 × 14)
Standard
80-pin plastic TQFP (fine pitch) (12 × 12)
Standard
80-pin plastic QFP (14 × 14)
Standard
80-pin plastic TQFP (fine pitch) (12 × 12)
Standard
80-pin plastic QFP (14 × 14)
Standard
80-pin plastic TQFP (fine pitch) (12 × 12)
Special
80-pin plastic QFP (14 × 14)
Special
80-pin plastic TQFP (fine pitch) (12 × 12)
Special
80-pin plastic QFP (14 × 14)
Special
80-pin plastic TQFP (fine pitch) (12 × 12)
Special
80-pin plastic QFP (14 × 14)
Special
80-pin plastic TQFP (fine pitch) (12 × 12)
Special
80-pin plastic QFP (14 × 14)
Special
Note Only the ES (engineering sample) version is available. Use this product for program evaluation.
Remark Products that have the part numbers suffixed by "-A" are lead-free products.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
18
User’s Manual U16819EJ3V0UD
CHAPTER 1 OUTLINE
1.4 Pin Configuration (Top View)
• 80-pin plastic TQFP (fine pitch) (12 × 12)
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P70/KR0
P71/KR1
P72/KR2
P73/KR3
P74/KR4
P75/KR5
P76/KR6
P77/KR7
P40/AD0
P41/AD1
P42/AD2
P43/AD3
• 80-pin plastic QFP (14 × 14)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AVREF
AVSS
P120/INTP0
P33/TI51/TO51/INTP4
P32/INTP3
P31/INTP2
P30/INTP1
FLMD0
VDD
NC
VSS
X1
X2
RESET
XT1
XT2
P130
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P00/TI000
P01/TI010/TO00
P02/SO11
P03/SI11
P13/TxD6
P14/RxD6
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50/FLMD1
P140/PCL/INTP6
P141/BUZ/BUSY0/INTP7
P63
P62
EVSS
EVDD
P61
P60
P142/SCKA0
P143/SIA0
P144/SOA0
P145/STB0
P06/TI011/TO01
P05/SSI11/TI001
P04/SCK11
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Caution Connect the AVSS pin to VSS.
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19
CHAPTER 1 OUTLINE
Pin Identification
A8 to A15:
Address bus
PCL:
Programmable clock output
AD0 to AD7:
Address/data bus
RESET:
Reset
ANI0 to ANI7:
Analog input
RxD0, RxD6:
Receive data
ASTB:
Address strobe
RD:
Read strobe
AVREF:
Analog reference voltage
SCK10, SCK11,
AVSS:
Analog ground
SCKA0:
Serial clock input/output
Serial data input
BUSY0:
Serial busy input
SI10, SI11, SIA0:
BUZ:
Buzzer output
SO10, SO11,
EVDD:
Power supply for port
SOA1:
Serial data output
EVSS:
Ground for port
SSI11:
Serial interface chip select input
FLMD0, FLMD1: Flash programming mode
STB0:
Serial strobe
INTP0 to INTP7: External interrupt input
TI000, TI010,
KR0 to KR7:
Key return
TI001, TI011,
NC:
Non-connection
TI50, TI51:
P00 to P06:
Port 0
TO00, TO01,
P10 to P17:
Port 1
TO50, TO51,
P20 to P27:
Port 2
TOH0, TOH1:
Timer output
P30 to P33:
Port 3
TxD0, TxD6:
Transmit data
P40 to P47:
Port 4
VDD:
Power supply
P50 to P57:
Port 5
VSS:
Ground
P60 to P67:
Port 6
WAIT:
Wait
P70 to P77:
Port 7
WR:
Write strobe
P120:
Port 12
X1, X2:
Crystal oscillator
P130:
Port 13
P140 to P145:
Port 14
20
Timer input
(High-speed system clock)
XT1, XT2:
User’s Manual U16819EJ3V0UD
Crystal oscillator (Subsystem clock)
CHAPTER 1 OUTLINE
1.5 Kx1 Series Lineup
1.5.1 78K0/Kx1, 78K0/Kx1+ product lineup
• 30-pin SSOP (7.62 mm 0.65 mm pitch)
78K0/KB1
μ PD78F0103
Two-power-supply
flash memory: 24 KB,
RAM: 768 B
78K0/KB1+
μ PD780103
Mask ROM: 24 KB,
RAM: 768 B
Single-power-supply flash memory: 24 KB,
RAM: 768 B
μPD780102
Mask ROM: 16 KB,
RAM: 768 B
μPD78F0102H
Single-power-supply flash memory: 16 KB,
RAM: 768 B
μPD780101
Mask ROM: 8 KB,
RAM: 512 B
μPD78F0103H
μPD78F0101H
Single-power-supply flash memory: 8 KB,
RAM: 512 B
• 44-pin LQFP (10 × 10 mm 0.8 mm pitch)
78K0/KC1
μPD78F0114
Two-power-supply
flash memory: 32 KB,
RAM: 1 KB
78K0/KC1+
μPD780114
Mask ROM: 32 KB,
RAM: 1 KB
μPD780113
Mask ROM: 24 KB,
RAM: 1 KB
μPD780112
Mask ROM: 16 KB,
RAM: 512 B
μPD78F0114H/HDNote
Single-power-supply flash memory: 32 KB,
RAM: 1 KB
μPD78F0113H
Single-power-supply flash memory: 24 KB,
RAM: 1 KB
μ PD78F0112H
Single-power-supply flash memory: 16 KB,
RAM: 512 B
μ PD780111
Mask ROM: 8 KB,
RAM: 512 B
• 52-pin LQFP (10 × 10 mm 0.65 mm pitch)
78K0/KD1
μPD78F0124
Two-power-supply
flash memory: 32 KB,
RAM: 1 KB
78K0/KD1+
μPD780124
Mask ROM: 32 KB,
RAM: 1 KB
μPD780123
Mask ROM: 24 KB,
RAM: 1 KB
μPD780122
Mask ROM: 16 KB,
RAM: 512 B
μPD78F0124H/HDNote
Single-power-supply flash memory: 32 KB,
RAM: 1 KB
μ PD78F0123H
Single-power-supply flash memory: 24 KB,
RAM: 1 KB
μ PD78F0122H
Single-power-supply flash memory: 16 KB,
RAM: 512 B
μ PD780121
Mask ROM: 8 KB,
RAM: 512 B
• 64-pin LQFP, TQFP (10 × 10 mm 0.5 mm pitch, 12 × 12 mm 0.65 mm pitch, 14 × 14 mm 0.8 mm pitch)
78K0/KE1
μ PD78F0138
Two-power-supply
flash memory: 60 KB,
RAM: 2 KB
μPD78F0134
Two-power-supply
flash memory: 32 KB,
RAM: 1 KB
78K0/KE1+
μPD780138
μPD78F0138H/HDNote
Mask ROM: 60 KB,
RAM: 2 KB
Single-power-supply flash memory: 60 KB,
RAM: 2 KB
μPD780136
Mask ROM: 48 KB,
RAM: 2 KB
μPD78F0136H
Single-power-supply flash memory: 48 KB,
RAM: 2 KB
μPD780134
μPD78F0134H
Mask ROM: 32 KB,
RAM: 1 KB
Single-power-supply flash memory: 32 KB,
RAM: 1 KB
μ PD780133
Mask ROM: 24 KB,
RAM: 1 KB
Single-power-supply flash memory: 24 KB,
RAM: 1 KB
μPD780132
Mask ROM: 16 KB,
RAM: 512 B
μ PD78F0133H
μ PD78F0132H
Single-power-supply flash memory: 16 KB,
RAM: 512 B
μ PD780131
Mask ROM: 8 KB,
RAM: 512 B
• 80-pin TQFP, QFP (12 × 12 mm 0.5 mm pitch, 14 × 14 mm 0.65 mm pitch)
78K0/KF1
μ PD78F0148
Two-power-supply
flash memory: 60 KB,
RAM: 2 KB
78K0/KF1+
μPD780148
Mask ROM: 60 KB,
RAM: 2 KB
μPD78F0148H/HDNote
Single-power-supply flash memory: 60 KB,
RAM: 2 KB
μ PD780146
Mask ROM: 48 KB,
RAM: 2 KB
μPD780144
Mask ROM: 32 KB,
RAM: 1 KB
μ PD780143
Mask ROM: 24 KB,
RAM: 1 KB
Note Product with on-chip debug function
User’s Manual U16819EJ3V0UD
21
CHAPTER 1 OUTLINE
The list of functions in the 78K0/Kx1 is shown below.
Part Number
78K0/KB1
78K0/KC1
78K0/KD1
78K0/KE1
78K0/KF1
Item
Number of pins
Internal
memory
(KB)
30 pins
Mask ROM
8
−
Flash memory
RAM
16/
24
44 pins
−
8/
16
−
24
0.5
0.75
52 pins
−
24/
32
8/
16
−
32
0.5
1
Minimum instruction execution time
Clock
1
0.166 μs (when 12 MHz, VDD =
4.0 to 5.5 V)
0.2 μs (when 10 MHz, VDD =
3.5 to 5.5 V)
0.238 μs (when 8.38 MHz, VDD
= 3.0 to 5.5 V)
0.4 μs (when 5 MHz, VDD = 2.5
to 5.5 V)
X1 input
32
−
1
−
24/
32
−
48/
60
−
60
2
60
1
2
Notes 1, 2
32.768 kHz
240 kHz (TYP.)
CMOS I/O
17
CMOS input
4
19
26
38
54
8
CMOS output
1
−
4
16 bits (TM0)
1 ch
8 bits (TM5)
1 ch
2 ch
1 ch
2 ch
1 ch
2 ch
2 ch
8 bits (TMH)
2 ch
−
For watch
1 ch
WDT
1 ch
Note 3
3-wire CSI
Serial
interface Automatic transmit/
receive 3-wire CSI
Note 3
UART
1 ch
−
1 ch
UART supporting LIN-bus
1 ch
4 ch
External
Internal
Key return input
8 ch
6
11
7
12
8
−
Standby function
Operating ambient temperature
17
20
Provided
2.85 V ±0.15 V/3.5 V ±0.20 V (selectable by mask option)
2.85 V/3.1 V/3.3 V ±0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V (selectable by software)
Provided
WDT
ROM correction
9
19
8 ch
Clock monitor
Multiplier/divider
16
4 ch
POC
Clock output/buzzer output
9
15
RESET pin
LVI
2 ch
1 ch
−
10-bit A/D converter
Reset
48/
60
2 to 12 MHz
−
N-ch open-drain I/O
Interrupt
−
80 pins
−
0.166 μs (when 12 MHz, VDD = 4.0 to 5.5 V)
0.2 μs (when 10 MHz, VDD = 3.5 to 5.5 V)
0.238 μs (when 8.38 MHz, VDD = 3.0 to 5.5 V)
0.4 μs (when 5 MHz, VDD = 2.5 to 5.5 V)
Internal oscillation
Timer
24/
32
0.5
VDD = 2.5 to 5.5 V
Sub
Port
8/
16
32
0.5
Power supply voltage
64 pins
−
24/
32
Provided
−
Provided
Clock output
only
16 bits × 16 bits, 32 bits ÷ 16 bits
−
−
Provided
−
HALT/STOP mode
Standard and special (A) grade products: −40 to +85°C
Special (A1) grade products: −40 to +110°C (mask ROM version),
−40 to +105°C (flash memory version),
Special (A2) grade products: −40 to +125°C (mask ROM version)
Notes 1. If the POC circuit detection voltage (VPOC) is used with 2.85 V ±0.15 V, then use the products in the voltage
range of 3.0 to 5.5 V.
2. If the POC circuit detection voltage (VPOC) is used with 3.5 V ±0.2 V, then use the products in the voltage
range of 3.7 to 5.5 V.
3. Select either of the functions of these alternate-function pins.
22
User’s Manual U16819EJ3V0UD
CHAPTER 1 OUTLINE
The list of functions in the 78K0/Kx1+ is shown below.
Part Number
78K0/KB1+
78K0/KC1+
78K0/KD1+
78K0/KE1+
78K0/KF1+
64 pins
80 pins
Item
Number of pins
Internal
memory
(KB)
30 pins
Flash memory
RAM
52 pins
16/24
16
24/32
16
24/32
16
24/32
48/60
60
0.5
0.75
0.5
1
0.5
1
0.5
1
2
2
Power supply voltage
VDD = 2.5 to 5.5 V (with internal oscillation clock or subclock: VDD = 2.0 to 5.5 V
Crystal/ceramic
−
3 to 4 MHz
−
Sub
32.768 kHz
Internal oscillation
240 kHz (TYP.)
CMOS I/O
17
CMOS input
4
19
26
54
1
−
4
16 bits (TM0)
1 ch
8 bits (TM5)
2 ch
1 ch
2 ch
8 bits (TMH)
2 ch
−
For watch
1 ch
WDT
1 ch
Note 2
Serial
3-wire CSI
interface Automatic transmit/
receive 3-wire CSI
Note 2
UART
1 ch
2 ch
−
1 ch
−
1 ch
UART supporting LIN-bus
1 ch
10-bit A/D converter
4 ch
Interrupts External
6
Internal
Key return input
Reset
38
8
CMOS output
N-ch open-drain I/O
Timer
11
8 ch
7
12
8
16
Provided
2.1 V ±0.1 V (detection voltage is fixed)
2.35 V/2.6 V/2.85 V/3.1 V/3.3 V ±0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V
(selectable by software)
Clock monitor
Provided
Provided
−
Clock output
only
ROM correction
Provided
−
External bus interface
Multiplier/divider
Provided
16 bits × 16 bits, 32 bits ÷ 16 bits
−
−
Provided
Self-programming function
Provided
Product with on-chip debug
function
μPD78F0114HD, 78F0124HD, 78F0138HD, 78F0148HD
Standby function
Operating ambient temperature
20
8 ch
WDT
Clock output/buzzer output
9
19
4 ch
POC
LVI
9
15
−
RESET pin
Notes 1.
)
2 to 16 MHz
RC
Ports
Note 1
0.125 μs (when 16 MHz, VDD = 4.0 to 5.5 V), 0.2 μs (when 10 MHz, VDD = 3.5 to 5.5 V),
0.238 μs (when 8.38 MHz, VDD = 3.0 to 5.5 V), 0.4 μs (when 5 MHz, VDD = 2.5 to 5.5 V)
Minimum instruction execution time
Clock
44 pins
8
−
HALT/STOP mode
Standard and special (A) grade products: −40 to +85°C
Special (A1) grade products: −40 to +110°C
Because the POC circuit detection voltage (VPOC) is 2.1 V ±0.1 V, use the products in the voltage range of
2.2 to 5.5 V.
2.
Select either of the functions of these alternate-function pins.
User’s Manual U16819EJ3V0UD
23
CHAPTER 1 OUTLINE
1.5.2 V850ES/Kx1, V850ES/Kx1+ product lineup
• 64-pin plastic LQFP (10 × 10 mm, 0.5 mm pitch)
• 64-pin plastic TQFP (12 × 12 mm, 0.65 mm pitch)
V850ES/KE1
V850ES/KE1+
μ PD70F3207HY
μ PD70F3207H
Single-power flash: 128 KB,
RAM: 4 KB
μ PD703207Y
μ PD70F3302Y
μ PD703207
μ PD70F3302
Mask ROM: 128 KB,
RAM: 4 KB
Single-power flash: 128 KB,
RAM: 4 KB
μ PD703302Y
μ PD703302
Mask ROM: 128 KB,
RAM: 4 KB
• 80-pin plastic TQFP (12 × 12 mm, 0.5 mm pitch)
• 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch)
V850ES/KF1
V850ES/KF1+
μ PD70F3211HY
μ PD703211Y
μ PD703211
μ PD70F3211H
Single-power flash: 256 KB,
RAM: 12 KB
Mask ROM: 256 KB,
RAM: 12 KB
μ PD703210Y
μ PD70F3210HY
μ PD703210
μ PD70F3210H
Single-power flash: 128 KB,
RAM: 6 KB
Mask ROM: 128 KB,
RAM: 6 KB
μ PD70F3210Y
Single-power flash: 256 KB,
RAM: 12 KB
μ PD703308Y
μ PD703308
Mask ROM: 256 KB,
RAM: 12 KB
μ PD70F3306Y
μ PD70F3306
Single-power flash: 128 KB,
RAM: 6 KB
μ PD703209Y
μ PD70F3210
Two-power flash: 128 KB,
RAM: 6 KB
μ PD70F3308Y
μ PD70F3308
μ PD703209
Mask ROM: 96 KB,
RAM: 4 KB
μ PD703208Y
μ PD703208
Mask ROM: 64 KB,
RAM: 4 KB
• 100-pin plastic LQFP (14 × 14 mm, 0.5 mm pitch)
• 100-pin plastic QFP (14 × 20 mm, 0.65 mm pitch)
V850ES/KG1
V850ES/KG1+
μ PD70F3215HY
μ PD703215Y
μ PD70F3313Y
μ PD70F3215H
μ PD703215
μ PD70F3313
Mask ROM: 256 KB,
RAM: 16 KB
Single-power flash: 256 KB,
RAM: 16 KB
Single-power flash: 256 KB,
RAM: 16 KB
μ PD703214Y
μ PD70F3214HY
μ PD70F3214H
Single-power flash: 128 KB,
RAM: 6 KB
μ PD703214
Mask ROM: 128 KB,
RAM: 6 KB
μ PD70F3214Y
μ PD703213Y
μ PD70F3214
μ PD703213
Two-power flash: 128 KB,
RAM: 6 KB
μ PD70F3311Y
μ PD70F3311
Single-power flash: 128 KB,
RAM: 6 KB
Mask ROM: 96 KB,
RAM: 4 KB
μ PD703212Y
μ PD703212
Mask ROM: 64 KB,
RAM: 4 KB
• 144-pin plastic LQFP (20 × 20 mm, 0.5 mm pitch)
V850ES/KJ1
V850ES/KJ1+
μ PD70F3318Y
μ PD70F3218HY
μ PD70F3318
μ PD70F3218H
Single-power flash: 256 KB,
RAM: 16 KB
μ PD70F3217HY
μ PD70F3217H
Single-power flash: 128 KB,
RAM: 6 KB
μ PD70F3217Y
μ PD70F3217
Two-power flash: 128 KB,
RAM: 6 KB
24
Single-power flash: 256 KB,
RAM: 16 KB
μ PD703217Y
μ PD703217
Mask ROM: 128 KB,
RAM: 6 KB
μ PD70F3316Y
μ PD70F3316
Single-power flash: 128 KB,
RAM: 6 KB
μ PD703216Y
μ PD703216
Mask ROM: 96 KB,
RAM: 6 KB
User’s Manual U16819EJ3V0UD
μ PD703313Y
μ PD703313
Mask ROM: 256 KB,
RAM: 16 KB
CHAPTER 1 OUTLINE
The list of functions in the V850ES/Kx1 is shown below.
Product Name
V850ES/KE1
Number of pins
Internal
Mask ROM
64 pins
Flash memory
−
128
4
−
−
256
−
4
−
128
6
−
96/
−
−
256
16
−
128
256
6
16
2.7 to 5.5 V
50 ns @20 MHz
2 to 10 MHz
Subclock
32.768 kHz
N-ch open-drain I/O
−
128
6
X1 input
CMOS I/O
144 pins
−
256
128
4
−
Internal oscillator
Timer
−
256
12
Minimum instruction execution time
CMOS input
−
64/ 128
96
Supply voltage
Port
V850ES/KJ1
100 pins
−
64/ 128
96
RAM
Clock
V850ES/KG1
80 pins
−
128
memory
(KB)
V850ES/KF1
8
8
8
16
41 (4)Note 1
57 (6)Note 1
72 (8)Note 1
106 (12)Note 1
2
2
4
−
6
−
1 ch
16-bit (TM0)
1 ch
2 ch
4 ch
6 ch
8-bit (TM5)
2 ch
2 ch
2 ch
2 ch
8-bit (TMH)
2 ch
2 ch
2 ch
2 ch
Interval timer
1 ch
1 ch
1 ch
1 ch
Watch
1 ch
1 ch
1 ch
1 ch
WDT1
1 ch
1 ch
1 ch
1 ch
WDT2
1 ch
1 ch
1 ch
1 ch
6 bits × 1 ch
6 bits × 1 ch
6 bits × 1 ch
6 bits × 2 ch
RTO
Serial
CSI
interface
Automatic transmit/receive
1 ch
1 ch
−
16-bit (TMP)
1 ch
2 ch
2 ch
2 ch
3 ch
−
1 ch
2 ch
2 ch
2 ch
2 ch
2 ch
3 ch
−
−
−
−
1 ch
1 ch
1 ch
2 ch
128 KB
3 MB
15 MB
22 bits
3-wire CSI
UART
UART supporting LIN-bus
I2CNote 2
External
Address space
−
bus
Address bus
−
16 bits
Mode
−
Multiplex only
24 bits
Multiplex/separate
−
−
−
−
10-bit A/D converter
8 ch
8 ch
8 ch
16 ch
8-bit D/A converter
−
−
2 ch
2 ch
DMA controller
Interrupt
External
8
Internal
25/26Note 2
Key return input
Reset
8 ch
RESET pin
8
25/26Note 2
8
28/29Note 2
30/31Note 2
8 ch
8 ch
None
Clock monitor
None
WDT1
Provided
WDT2
Provided
ROM correction
Operating ambient temperature
41/43Note 2
8 ch
None
LVI
Standby function
38/40Note 2
Provided
POC
Regulator
8
33/34Note 2
4
None
Provided
HALT/IDLE/STOP/sub-IDLE mode
TA = −40 to +85°C
Notes 1. The number of channels in parentheses indicates the number of pins for which the N-ch open drain
output can be selected by software.
2. Only in products with an I2C bus (Y products). For the product name, refer to each user’s manual.
User’s Manual U16819EJ3V0UD
25
CHAPTER 1 OUTLINE
The list of functions in the V850ES/Kx1+ is shown below.
Product Name
V850ES/KE1+
Number of pins
Internal
Mask ROM
memory
Flash memory
(KB)
RAM
V850ES/KF1+
64 pins
80 pins
−
−
256
128
128
−
128
−
4
6
N-ch open-drain I/O
256
128
−
144 pins
16
−
−
−
256
128
256
6
16
50 ns @20 MHz
2 to 10 MHz
32.768 kHz
Internal oscillator
Timer
256
2.7 to 5.5 V
Subclock
CMOS I/O
−
6
X1 input
CMOS input
−
12
Minimum instruction execution time
Port
V850ES/KJ1+
100 pins
Supply voltage
Clock
V850ES/KG1+
240 kHz (TYP.)
8
41 (4)
8
Note 1
57 (6)
8
Note 1
72 (8)
16
Note 1
106 (12)Note 1
2
2
4
6
16-bit (TMP)
1 ch
1 ch
1 ch
1 ch
16-bit (TM0)
1 ch
2 ch
4 ch
6 ch
8-bit (TM5)
2 ch
2 ch
2 ch
2 ch
8-bit (TMH)
2 ch
2 ch
2 ch
2 ch
Interval timer
1 ch
1 ch
1 ch
1 ch
Watch
1 ch
1 ch
1 ch
1 ch
WDT1
1 ch
1 ch
1 ch
1 ch
WDT2
1 ch
1 ch
1 ch
1 ch
6 bits × 1 ch
6 bits × 1 ch
6 bits × 1 ch
6 bits × 2 ch
RTO
Serial
CSI
interface
Automatic transmit/receive
2 ch
2 ch
2 ch
3 ch
−
1 ch
2 ch
2 ch
UART
1 ch
1 ch
2 ch
2 ch
UART supporting LIN-bus
1 ch
1 ch
1 ch
1 ch
I2CNote 2
1 ch
1 ch
1 ch
2 ch
3-wire CSI
External
Address space
−
128 KB
3 MB
15 MB
bus
Address bus
−
16 bits
22 bits
24 bits
Mode
−
Multiplex only
−
−
10-bit A/D converter
8 ch
8-bit D/A converter
−
Interrupt
External
Internal
DMA controller
Key return input
Reset
4 ch
8 ch
8 ch
16 ch
−
2 ch
2 ch
9
9
9
9
26/27Note 2
29/30Note 2
41/42Note 2
46/48Note 2
8 ch
8 ch
8 ch
8 ch
RESET pin
Provided
POC
LVI
2.7 V or less fixed
3.1 V/3.3 V ±0.15 V or 3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V (selectable by software)
Clock monitor
Provided (monitor by internal oscillator)
WDT1
Provided
WDT2
Provided
ROM correction
Regulator
Standby function
Operating ambient temperature
Multiplex/separate
4 ch
4
None
None
Provided
HALT/IDLE/STOP/sub-IDLE mode
TA = −40 to +85°C
Notes 1. The number of channels in parentheses indicates the number of pins for which the N-ch open drain
output can be selected by software.
2. Only in products with an I2C bus (Y products). For the product name, refer to each user’s manual.
26
User’s Manual U16819EJ3V0UD
CHAPTER 1 OUTLINE
1.6 Block Diagram
TO00/TI010/P01
TI000/P00
16-bit timer/
event counter 00
TO01/TI011/P06
TI001/P05
16-bit timer/
event counter 01
TOH0/P15
8-bit timer H0
TOH1/P16
8-bit timer H1
8-bit timer/
event counter 50
TI50/TO50/P17
8-bit timer/
event counter 51
TI51/TO51/P33
Port 0
7
P00 to P06
Port 1
8
P10 to P17
Port 2
8
P20 to P27
Port 3
4
P30 to P33
Port 4
8
P40 to P47
Port 5
8
P50 to P57
Port 6
8
P60 to P67
Port 7
8
P70 to P77
Port 12
P120
Port 13
P130
Watch timer
Watchdog timer
RxD0/P11
TxD0/P10
Serial
interface UART0
RxD6/P14
TxD6/P13
Serial
interface UART6
SI10/P11
SO10/P12
SCK10/P10
Serial
interface CSI10
SI11/P03
SO11/P02
SCK11/P04
SSI11/P05
Internal
high-speed
RAM
Flash
memory
Internal
expansion
RAM
Serial
interface CSI11
Port 14
6
P140 to P145
Buzzer output
BUZ/P141
Clock output control
PCL/P140
Clock monitor
Power on clear/
low voltage
indicator
Key return
SIA0/P143
SOA0/P144
SCKA0/P142
STB0/P145
BUSY0/P141
ANI0/P20 to
ANI7/P27
AVREF
AVSS
78K/0
CPU
core
POC/LVI
control
8
KR0/P70 to
KR7/P77
Reset control
Serial
interface CSIA0
8
8
External accessNote
8
A/D converter
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
INTP0/P120
INTP1/P30 to
INTP4/P33
Internal oscillator
4
Interrupt control
INTP5/P16
INTP6/P140,
INTP7/P141
2
System control
Multiplier & divider
Note
VDD, VSS, FLMD0,
EVDD EVSS FLMD1
RESET
X1
X2
XT1
XT2
The external bus interface function cannot be used in (A1) grade products.
User’s Manual U16819EJ3V0UD
27
CHAPTER 1 OUTLINE
1.7 Outline of Functions
(1/2)
μPD78F0148H
Item
Internal
Flash memory
memory
(self-programming
60 KB
μPD78F0148HD
Note 1
supported)
High-speed RAM
1 KB
Expansion RAM
1 KB
Buffer RAM
32 bytes
Note 1
Memory space
64 KB
High-speed system clock
Crystal/ceramic/external clock oscillation
(oscillation frequency)
Standard products and
2 to 16 MHz: VDD = 4.0 to 5.5 V, 2 to 10 MHz: VDD = 3.5 to 5.5 V,
(A) grade products
2 to 8.38 MHz: VDD = 3.0 to 5.5 V, 2 to 5 MHz: VDD = 2.5 to 5.5 V
(A1) grade products
2 to 16 MHz: VDD = 4.0 to 5.5 V, 2 to 10 MHz: VDD = 3.5 to 5.5 V,
2 to 8.38 MHz: VDD = 3.0 to 5.5 V, 2 to 5 MHz: VDD = 2.7 to 5.5 V
Internal oscillation clock
Internal oscillation (240 kHz (TYP.): VDD = 2.0 to 5.5 V
Note 2
)
(oscillation frequency)
Subsystem clock
Crystal/external clock oscillation
(oscillation frequency)
Standard products and
32.768 kHz: VDD = 2.0 to 5.5 V
Note 2
(A) grade products
(A1) grade products
32.768 kHz: VDD = 2.7 to 5.5 V
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution
0.125 μs/0.25 μs/0.5 μs/1.0 μs/2.0 μs (high-speed system clock: @ fXP = 16 MHz operation)
time
8.3 μs/16.6 μs/33.3 μs/66.6 μs/133.3 μs (TYP.) (internal oscillation clock: @ fR = 240 kHz
(TYP.) operation)
122 μs (subsystem clock: when operating at fXT = 32.768 kHz)
Instruction set
• 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
I/O ports
Total:
67
CMOS I/O
54
CMOS input
8
CMOS output
1
N-ch open-drain I/O
4
• 16-bit timer/event counter: 2 channels
Timers
Timer outputs
Notes 1.
• 8-bit timer/event counter:
2 channels
• 8-bit timer:
2 channels
• Watch timer
1 channel
• Watchdog timer:
1 channel
6 (PWM output: 4)
The internal flash memory capacity and internal expansion RAM capacity can be changed using the
internal memory size switching register (IMS) and the internal expansion RAM size switching register
(IXS).
2.
Use the product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.1 V ±0.1 V.
28
User’s Manual U16819EJ3V0UD
CHAPTER 1 OUTLINE
(2/2)
μPD78F0148H
Item
μPD78F0148HD
• 78.125 kHz, 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
Clock output
(high-speed system clock: @10 MHz operation)
• 32.768 kHz (subsystem clock: @32.768 kHz operation)
Buzzer output
1.22 kHz, 2.44 kHz, 4.88 kHz, 9.77 kHz (high-speed system clock: @10 MHz operation)
A/D converter
10-bit resolution × 8 channels
Serial interface
• UART mode supporting LIN-bus:
1 channel
• 3-wire serial I/O mode:
1 channel
• 3-wire serial I/O mode with automatic transmission/reception: 1 channel
• 3-wire serial I/O mode/UART mode
Note 1
:
1 channel
• 16 bits × 16 bits = 32 bits (multiplication)
Multiplier/divider
• 32 bits ÷ 16 bits = 32 bits remainder of 16 bits (division)
Vectored interrupt
Internal
20
sources
External
9
Key interrupt
Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR7).
Reset
• Reset using RESET pin
• Internal reset by watchdog timer
• Internal reset by clock monitor
• Internal reset by power-on-clear
• Internal reset by low-voltage detector
−
On-chip debug function
Supply voltage
Provided
• Standard products and (A) grade products:
VDD = 2.5 to 5.5 V (with internal oscillation clock or subsystem clock: VDD = 2.0 to 5.5 V
Note 2
)
• (A1) grade products:
VDD = 2.7 to 5.5 V (with internal oscillation clock: VDD = 2.0 to 5.5 V
Operating ambient temperature
)
• Standard products and (A) grade products : TA = −40 to +85°C
• (A1) grade products :
Package
Note 2
TA = −40 to +110°C
• 80-pin plastic QFP (14 × 14)
• 80-pin plastic TQFP (fine pitch) (12 × 12)
Notes 1.
2.
Select either of the functions of these alternate-function pins.
Use the product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.1 V ±0.1 V.
User’s Manual U16819EJ3V0UD
29
CHAPTER 1 OUTLINE
An outline of the timer is shown below.
16-Bit Timer/
8-Bit Timer/
8-Bit Timers H0 and
Watch
Watchdog
Event Counters 00
Event Counters
H1
Timer
Timer
and 01
50 and 51
TM00
Operation
mode
TM50
TM51
TMH0
TMH1
Note
Interval timer
1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel
External event counter
1 channel 1 channel 1 channel 1 channel
−
−
−
−
−
−
−
−
−
−
1 channel
Timer output
1 output
1 output
1 output
1 output
1 output
1 output
−
−
PPG output
1 output
1 output
−
−
−
−
−
−
PWM output
1 output
1 output
1 output
−
−
1 output
−
−
Pulse width measurement
2 inputs
2 inputs
−
−
−
−
−
−
Square-wave output
1 output
1 output
1 output
1 output
1 output
1 output
−
−
2
2
1
1
1
1
1
−
Interrupt source
Note In the watch timer, the watch timer function and interval timer function can be used simultaneously.
Remark
30
−
−
Watchdog timer
Function
TM01
TM51 and TMH1 can be used in combination as a carrier generator mode.
User’s Manual U16819EJ3V0UD
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
There are three types of pin I/O buffer power supplies: AVREF, EVDD, and VDD. The relationship between these
power supplies and the pins is shown below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply
Corresponding Pins
AVREF
P20 to P27
EVDD
Port pins other than P20 to P27
VDD
Pins other than port pins
(1) Port pins (1/2)
Pin Name
P00
I/O
I/O
P01
P02
P03
Function
Port 0.
7-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
After Reset
Input
Alternate Function
TI000
TI010/TO00
SO11
SI11
P04
SCK11
P05
SSI11/TI001
P06
P10
TI011/TO01
I/O
P11
P12
P13
Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input
SCK10/TxD0
SI10/RxD0
SO10
TxD6
P14
RxD6
P15
TOH0
P16
TOH1/INTP5
P17
TI50/TO50/FLMD1
P20 to P27
Input
Port 2.
8-bit input-only port.
Input
ANI0 to ANI7
P30 to P32
I/O
Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input
INTP1 to INTP3
Port 4.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input
P33
P40 to P47
I/O
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INTP4/TI51/TO51
AD0 to AD7
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CHAPTER 2 PIN FUNCTIONS
(1) Port pins (2/2)
Pin Name
P50 to P57
I/O
I/O
Function
Port 5.
After Reset
Input
Alternate Function
A8 to A15
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P60 to P63
I/O
P64
P65
N-ch open-drain I/O port.
8-bit I/O port.
Use of an on-chip pull-up
RD
Input/output can be specified
resistor can be specified by
in 1-bit units.
WR
a software setting.
P66
Input
WAIT
P67
P70 to P77
−
Port 6.
ASTB
I/O
Port 7.
Input
KR0 to KR7
Input
INTP0
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
I/O
Port 12.
1-bit I/O port.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P130
Output
Port 13.
−
Output
1-bit output-only port.
P140
P141
P142
I/O
Port 14.
Input
PCL/INTP6
6-bit I/O port.
BUZ/BUSY0/
Input/output can be specified in 1-bit units.
INTP7
Use of an on-chip pull-up resistor can be specified by a
software setting.
SCKA0
P143
SIA0
P144
SOA0
P145
STB0
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins (1/2)
Pin Name
INTP0
I/O
Input
INTP1 to INTP3
Function
External interrupt request input for which the valid edge (rising
edge, falling edge, or both rising and falling edges) can be
specified
After Reset
Input
Alternate Function
P120
P30 to P32
INTP4
P33/TI51/TO51
INTP5
P16/TOH1
INTP6
P140/PCL
INTP7
P141/BUZ/BUSY0
SI10
Input
Serial data input to serial interface
Input
P11/RxD0
SI11
P03
SIA0
P143
SO10
Output
Serial data output from serial interface
Input
P12
SO11
P02
SOA0
P144
SCK10
I/O
Clock input/output for serial interface
Input
P10/TxD0
SCK11
P04
SCKA0
P142
SSI11
Input
Serial interface chip select input
Input
P05/TI001
BUSY0
Input
Serial interface busy input
Input
P141/BUZ/INTP7
STB0
Output
Serial interface strobe output
Input
P145
RxD0
Input
Serial data input to asynchronous serial interface
Input
P11/SI10
RxD6
TxD0
P14
Output
Serial data output from asynchronous serial interface
Input
TxD6
TI000
P10/SCK10
P13
Input
External count clock input to 16-bit timer/event counter 00
Capture trigger input to capture registers (CR000, CR010) of
16-bit timer/event counter 00
Input
P00
TI001
External count clock input to 16-bit timer/event counter 01
Capture trigger input to capture registers (CR001, CR011) of
16-bit timer/event counter 01
P05/SSI11
TI010
Capture trigger input to capture register (CR000) of 16-bit
timer/event counter 00
P01/TO00
TI011
Capture trigger input to capture register (CR001) of 16-bit
timer/event counter 01
P06/TO01
TO00
Output
TO01
TI50
Input
16-bit timer/event counter 01 output
Input
TI51
TO50
16-bit timer/event counter 00 output
External count clock input to 8-bit timer/event counter 50
P06/TI011
Input
External count clock input to 8-bit timer/event counter 51
Output
8-bit timer/event counter 50 output
P01/TI010
P17/TO50/FLMD1
P33/TO51/INTP4
Input
P17/TI50/FLMD1
TO51
8-bit timer/event counter 51 output
P33/TI51/INTP4
TOH0
8-bit timer H0 output
P15
TOH1
8-bit timer H1 output
P16/INTP5
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins (2/2)
Pin Name
PCL
I/O
Output
Function
Clock output (for trimming of high-speed system clock,
After Reset
Alternate Function
Input
P140/INTP6
subsystem clock)
BUZ
Output
Buzzer output
Input
P141/INTP7/BUSY0
AD0 to AD7
I/O
Lower address/data bus for external memory expansion
Input
P40 to P47
A8 to A15
Output
Higher address bus for external memory expansion
Input
P50 to P57
RD
Output
Strobe signal output for external memory read operation
Input
P64
WR
Output
Strobe signal output for external memory write operation
Input
P65
WAIT
Input
Wait insertion on external memory access
Input
P66
ASTB
Output
Strobe output that externally latches address information
Input
P67
Input
P20 to P27
output to ports 4 and 5 for access to external memory
ANI0 to ANI7
Input
A/D converter analog input
AVREF
Input
A/D converter reference voltage input and positive power
−
−
−
−
supply for port 2
AVSS
−
A/D converter ground potential. Make the same potential as
EVSS or VSS.
KR0 to KR7
Input
Key interrupt input
Input
RESET
Input
System reset input
−
−
X1
Input
Connecting resonator for high-speed system clock
−
−
X2
−
−
−
−
−
−
−
Connecting resonator for subsystem clock
P70 to P77
XT1
Input
XT2
−
VDD
−
Positive power supply (except for ports)
−
−
EVDD
−
Positive power supply for ports
−
−
VSS
−
Ground potential (except for ports)
−
−
EVSS
−
Ground potential for ports
−
−
FLMD0
−
Flash memory programming mode setting.
−
−
FLMD1
NC
Input
−
Not internally connected.
Leave open (connecting to VDD or VSS is also possible).
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User’s Manual U16819EJ3V0UD
P17/TI50/TO50
−
−
CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
2.2.1 P00 to P06 (port 0)
P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O,
and chip select input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 to P06 function as a 7-bit I/O port. P00 to P06 can be set to input or output in 1-bit units using port mode
register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
(2) Control mode
P00 to P06 function as timer I/O, serial interface data I/O, clock I/O, and chip select input.
(a) TI000, TI001
These are the pins for inputting an external count clock to 16-bit timer/event counters 00 and 01 and are also
for inputting a capture trigger signal to the capture registers (CR000, CR010 or CR001, CR011) of 16-bit
timer/event counters 00 and 01.
(b) TI010, TI011
These are the pins for inputting a capture trigger signal to the capture register (CR000 or CR001) of 16-bit
timer/event counters 00 and 01.
(c) TO00, TO01
These are timer output pins.
(d) SI11
This is a serial interface serial data input pin.
(e) SO11
This is a serial interface serial data output pin.
(f) SCK11
This is the serial interface serial clock I/O pin.
(g) SSI11
This is the serial interface chip select input pin.
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CHAPTER 2 PIN FUNCTIONS
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial
interface data I/O, clock I/O, timer I/O, and flash memory programming mode setting.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode
register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
(2) Control mode
P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, timer I/O, and flash
memory programming mode setting.
(a) SI10
This is a serial interface serial data input pin.
(b) SO10
This is a serial interface serial data output pin.
(c) SCK10
This is a serial interface serial clock I/O pin.
(d) RxD0, RxD6
These are the serial data input pins of the asynchronous serial interface.
(e) TxD0, TxD6
These are the serial data output pins of the asynchronous serial interface.
(f) TI50
This is the pin for inputting an external count clock to 8-bit timer/event counter 50.
(g) TO50, TOH0, and TOH1
These are timer output pins.
(h) INTP5
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
(i)
FLMD1
This is the pin for setting the flash memory programming mode.
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CHAPTER 2 PIN FUNCTIONS
2.2.3 P20 to P27 (port 2)
P20 to P27 function as an 8-bit input-only port. These pins also function as pins for A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P27 function as an 8-bit input-only port.
(2) Control mode
P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7). When using these pins as analog input
pins, see (5) ANI0/P20 to ANI7/P27 in 13.6 Cautions for A/D Converter.
2.2.4 P30 to P33 (port 3)
P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and
timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode
register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
(2) Control mode
P30 to P33 function as external interrupt request input pins and timer I/O pins.
(a) INTP1 to INTP4
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TI51
This is an external count clock input pin to 8-bit timer/event counter 51.
(c) TO51
This is a timer output pin.
Caution In the μPD78F0148HD, be sure to pull the P31 pin down after reset to prevent malfunction.
Remark
P31/INTP2 and P32/INTP3 of the μPD78F0148HD can be used as on-chip debug mode setting pins
when the on-chip debug function is used. For details, refer to CHAPTER 28 ON-CHIP DEBUG
FUNCTION (μPD78F0148HD ONLY).
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CHAPTER 2 PIN FUNCTIONS
2.2.5 P40 to P47 (port 4)
P40 to P47 function as an 8-bit I/O port. These pins also function as address/data bus pins.
The following operation modes can be specified.
(1) Port mode
P40 to P47 function as an 8-bit I/O port. P40 to P47 can be set to input or output in 1-bit units using port mode
register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).
(2) Control mode
P40 to P47 function as the pins for the lower address/data bus (AD0 to AD7) in external memory expansion mode.
Caution
The external bus interface function cannot be used in (A1) grade products.
2.2.6 P50 to P57 (port 5)
P50 to P57 function as an 8-bit I/O port. These pins also function as address bus pins.
The following operation modes can be specified.
(1) Port mode
P50 to P57 function as an 8-bit I/O port. P50 to P57 can be set to input or output in 1-bit units using port mode
register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5).
(2) Control mode
P50 to P57 function as the pins for the higher address bus (A8 to A15) in external memory expansion mode.
Caution
The external bus interface function cannot be used in (A1) grade products.
2.2.7 P60 to P67 (port 6)
P60 to P67 function as an 8-bit I/O port. These pins also function as control pins in external memory expansion
mode.
The following operation modes can be specified.
(1) Port mode
P60 to P67 function as an 8-bit I/O port. P60 to P67 can be set to input port or output port in 1-bit units using port
mode register 6 (PM6).
P60 to P63 are N-ch open-drain pins. Use of an on-chip pull-up resistor can be specified for P64 to P67 by pullup resistor option register 6 (PU6).
(2) Control mode
P64 to P67 function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode.
Cautions 1.
P66 can be used as an I/O port if the external wait is not used in external memory expansion
mode.
2. The external bus interface function cannot be used in (A1) grade products.
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CHAPTER 2 PIN FUNCTIONS
2.2.8 P70 to P77 (port 7)
P70 to P77 function as an 8-bit I/O port. These pins also function as key interrupt input pins.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P70 to P77 function as an 8-bit I/O port. P70 to P77 can be set to input or output in 1-bit units using port mode
register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
(2) Control mode
P70 to P77 function as key interrupt input pins.
2.2.9 P120 (port 12)
P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input.
The following operation modes can be specified.
(1) Port mode
P120 functions as a 1-bit I/O port. P120 can be set to input or output using port mode register 12 (PM12). Use of
an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
(2) Control mode
P120 functions as an external interrupt request input pin (INTP0) for which the valid edge (rising edge, falling
edge, or both rising and falling edges) can be specified.
2.2.10 P130 (port 13)
P130 functions as a 1-bit output-only port.
2.2.11 P140 to P145 (port 14)
P140 to P145 function as a 6-bit I/O port. These pins also function as external interrupt request input, clock output,
buzzer output, serial interface data I/O, clock I/O, busy input, and strobe output pins.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P140 to P145 function as a 6-bit I/O port. P140 to P145 can be set to input or output in 1-bit units using port
mode register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14
(PU14).
(2) Control mode
P140 to P145 function as external interrupt request input, clock output, buzzer output, serial interface data I/O,
clock I/O, busy input, and strobe output pins.
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CHAPTER 2 PIN FUNCTIONS
(a) INTP6, INTP7
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) PCL
This is a clock output pin.
(c) BUZ
This is a buzzer output pin.
(d) SIA0
This is a serial interface serial data input pin.
(e) SOA0
This is a serial interface serial data output pin.
(f) SCKA0
This is a serial interface serial clock I/O pin.
(g) BUSY0
This is a serial interface busy input pin.
(h) STB0
This is a serial interface strobe output pin.
2.2.12 AVREF
This is the A/D converter reference voltage input pin and the positive power supply pin of P20 to P27 and A/D
converter.
When the A/D converter is not used, connect this pin directly to EVDD or VDDNote.
Note Connect port 2 directly to EVDD when it is used as a digital port.
2.2.13 AVSS
This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with
the same potential as the EVSS pin or VSS pin.
2.2.14 RESET
This is the active-low system reset input pin.
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CHAPTER 2 PIN FUNCTIONS
2.2.15 X1 and X2
These are the pins for connecting a resonator for high-speed system clock.
When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin.
Remark
The X1 and X2 pins of the μPD78F0148HD can be used as on-chip debug mode setting pins when the
on-chip debug function is used. For details, refer to CHAPTER 28 ON-CHIP DEBUG FUNCTION
(μPD78F0148HD ONLY).
2.2.16 XT1 and XT2
These are the pins for connecting a resonator for subsystem clock.
When supplying an external clock, input a signal to the XT1 pin and input the inverse signal to the XT2 pin.
2.2.17 VDD and EVDD
VDD is the positive power supply pin for other than ports.
EVDD is the positive power supply pin for ports.
2.2.18 VSS and EVSS
VSS is the ground potential pin for other than ports.
EVSS is the ground potential pin for ports.
2.2.19 FLMD0 and FLMD1
This is a pin for setting flash memory programming mode.
Connect FLMD0 to EVSS or VSS in the normal operation mode (FLMD1 is used as P17/TI50/TO50 pin).
In flash memory programming mode, be sure to connect these pins to the flash programmer.
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CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins.
Refer to Figure 2-1 for the configuration of the I/O circuit of each type.
Table 2-2. Pin I/O Circuit Types (1/2)
Pin Name
P00/TI000
I/O Circuit Type
8-A
I/O
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P01/TI010/TO00
P02/SO11
P03/SI11
P04/SCK11
P05/SSI11/TI001
P06/TI011/TO01
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
5-A
P13/TxD6
P14/RxD6
8-A
P15/TOH0
5-A
P16/TOH1/INTP5
8-A
P17/TI50/TO50/FLMD1
P20/ANI0 to P27/ANI7
9-C
Input
P30/INTP1
8-A
I/O
Connect to AVREF or AVSS.
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P31/INTP2
(except μPD78F0148HD)
P31/INTP2 (μPD78F0148HD)
Connect to EVSS via a resistor.
P32/INTP3
Input:
P33/TI51/TO51/INTP4
Output: Leave open.
P40/AD0 to P47/AD7
Independently connect to EVDD or EVSS via a resistor.
5-A
P50/A8 to P57/A15
P60, P61
13-R
Input:
P62, P63
13-W
Output: Leave this pin open at low-level output after clearing
Connect to EVSS.
P64/WD
5-A
Input:
the output latch of the port to 0.
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P65/WR
P66/WAIT
P67/ASTB
P70/KR0 to P77/KR7
8-A
P120/INTP0
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CHAPTER 2 PIN FUNCTIONS
Table 2-2. Pin I/O Circuit Types (2/2)
Pin Name
I/O Circuit Type
I/O
Recommended Connection of Unused Pins
P130
3-C
Output
Leave open.
P140/PCL/INTP6
8-A
I/O
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P141/BUZ/BUSY0/INTP7
P142/SCKA0
P143/SIA0
P144/SOA0
5-A
P145/STB
RESET
2
XT1
16
Input
Note 1
Connect directly to EVSS or VSS
−
XT2
AVREF
Connect to EVDD or VDD.
−
.
Leave open.
Connect directly to EVDD or VDD
Note 2
.
AVSS
Connect directly to EVSS or VSS.
FLMD0
Connect to EVSS or VSS.
NC
Leave open (connecting to VDD or VSS is also possible).
Notes 1. Bit 6 (FRC) of the processor clock control register (PCC) must be set to 1 after reset mode is released.
2. Connect port 2 directly to EVDD when it is used as a digital port.
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (1/2)
Type 8-A
Type 2
EVDD
Pullup
enable
P-ch
IN
VDD
Data
P-ch
IN/OUT
Schmitt-triggered input with hysteresis characteristics
Output
disable
N-ch
Type 9-C
Type 3-C
EVDD
P-ch
Data
Comparator
P-ch
IN
+
N-ch
–
AVSS
OUT
VREF
(threshold voltage)
N-ch
Input
enable
Type 5-A
Type 13-R
EVDD
Pullup
enable
P-ch
IN/OUT
VDD
Data
Data
Output disable
P-ch
IN/OUT
Output
disable
N-ch
Input
enable
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N-ch
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (2/2)
Type 13-W
Type 16
Feedback
cut-off
IN/OUT
Data
Output disable
Input
enable
P-ch
N-ch
XT1
XT2
Middle-voltage input buffer
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
Products in the 78K0/KF1+ can each access a 64 KB memory space. Figures 3-1 and 3-2 show the memory maps.
Caution Because the initial value of the internal expansion RAM size switching register (IXS) is 0CH, set
IXS = 0AH as the initial setting. When using the 78K0/KF1+ to evaluate the program of a mask
ROM version of the 78K0/KF1, set the following values to the internal memory size switching
register (IMS) and IXS.
Table 3-1. Set Values of Internal Memory Size Switching Register (IMS)
and Internal Expansion RAM Size Switching Register (IXS)
46
Flash Memory Version
Target Mask ROM Version
(78K0/KF1+)
(78K0/KF1)
IMS
−
μPD780143
C6H
−
μPD780144
C8H
−
μPD780146
CCH
μPD78F0148H, 78F0148HD μPD780148
CFH
User’s Manual U16819EJ3V0UD
IXS
0CH
0AH
CHAPTER 3 CPU ARCHITECTURE
Figure 3-1. Memory Map (μPD78F0148H)
FFFFH
Special function registers
(SFR)
256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
FA20H
FA1FH
Data memory
space
FA00H
F9FFH
F800H
F7FFH
General-purpose
registers
32 × 8 bits
EFFFH
Internal high-speed RAM
1024 × 8 bits
Reserved
Buffer RAM
32 × 8 bits
Option byte areaNote
5 × 8 bits
Boot cluster 1
Program area
1000H
0FFFH
Reserved
CALLF entry area
2048 × 8 bits
0800H
07FFH
Program area
1915 × 8 bits
F400H
F3FFH
External memory
1024 × 8 bits
Flash memory
61440 × 8 bits
0000H
Note
1FFFH
1085H
1084H
1080H
107FH
Internal expansion RAM
1024 × 8 bits
ROM/RAM space
in which instructions
can be fetched
F000H
EFFFH
Program area
0085H
0084H
0080H
007FH
Option byte areaNote
5 × 8 bits
0040H
003FH
Boot cluster 0
CALLT table area
64 × 8 bits
Vector table area
64 × 8 bits
0000H
When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H.
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-2. Memory Map (μPD78F0148HD)
FFFFH
Special function registers
(SFR)
256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
EFFFH
General-purpose
registers
32 × 8 bits
Program area
108FH
108EH
Note 1
FB00H
FAFFH
FA20H
FA1FH
Data memory
space
Internal high-speed RAM
1024 × 8 bits
1080H
107FH
Reserved
Option byte areaNote 3
5 × 8 bits
Boot cluster 1
Program area
CALLF entry area
2048 × 8 bits
Reserved
F800H
F7FFH
On-chip debug security
ID setting areaNote 3
10 × 8 bits
1000H
0FFFH
Buffer RAM
32 × 8 bits
FA00H
F9FFH
1085H
1084H
1FFFH
0800H
07FFH
Program area
1905 × 8 bits
Internal expansion RAM
1024 × 8 bits
F400H
F3FFH
ROM/RAM space
in which instructions
can be fetched
0190H
018FH
008FH
008EH
0085H
0084H
0080H
007FH
External memory
1024 × 8 bits
F000H
EFFFH
0040H
003FH
Flash memory
61440 × 8 bits
Note 2
On-chip debug security
ID setting areaNote 3
10 × 8 bits
Boot cluster 0
Option byte areaNote 3
5 × 8 bits
CALLT table area
64 × 8 bits
Vector table area
64 × 8 bits
Note 2
0000H
0000H
Notes 1. During on-chip debugging, about 7 to 16 bytes of this area are used as the user data backup area for
communication.
2. During on-chip debugging, use of this area is disabled because it is used as the communication
command area (008FH to 018FH: debugger’s default setting).
3. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security
IDs to 0085H to 008EH.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the
on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH.
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3.1.1 Internal program memory space
The internal program memory space stores the program and table data. Normally, it is addressed with the program
counter (PC).
78K0/KF1+ products incorporate internal ROM (flash memory), as shown below.
Table 3-2. Internal ROM Capacity
Part Number
Internal ROM
Structure
μPD78F0148H, 78F0148HD
Capacity
61440 × 8 bits (0000H to EFFFH)
Flash memory
The internal program memory space is divided into the following areas.
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch
upon reset signal input or generation of each interrupt request are stored in the vector table area.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd
addresses.
Table 3-3. Vector Table
Vector Table Address
Interrupt Source
Vector Table Address
Interrupt Source
RESET input, POC, LVI,
0020H
INTTM000
clock monitor, WDT
0022H
INTTM010
0004H
INTLVI
0024H
INTAD
0006H
INTP0
0026H
INTSR0
0008H
INTP1
0028H
INTWTI
000AH
INTP2
002AH
INTTM51
000CH
INTP3
002CH
INTKR
000EH
INTP4
002EH
INTWT
0010H
INTP5
0030H
INTP6
0012H
INTSRE6
0032H
INTP7
0014H
INTSR6
0034H
INTDMU
0016H
INTST6
0036H
INTCSI11
0018H
INTCSI10/INTST0
0038H
INTTM001
001AH
INTTMH1
003AH
INTTM011
001CH
INTTMH0
003CH
INTACSI
001EH
INTTM50
003EH
BRK
0000H
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CHAPTER 3 CPU ARCHITECTURE
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) Option byte area
The option byte area is assigned to the 1-byte area of 0080H. Refer to CHAPTER 26 OPTION BYTE for details.
(4) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
3.1.2 Internal data memory space
78K0/KF1+ products incorporate the following RAMs.
(1) Internal high-speed RAM
The internal high-speed RAM consists of 1024 × 8 bits (FB00H to FEFFH).
The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit
registers per one bank.
This area cannot be used as a program area in which instructions are written and executed.
The internal high-speed RAM can also be used as a stack memory.
(2) Internal expansion RAM
The internal expansion RAM consists of 1024 × 8 bits (F400H to F7FFH).
The internal expansion RAM can also be used as a normal data area similar to the internal high-speed RAM, as
well as a program area in which instructions can be written and executed.
The internal expansion RAM cannot be used as a stack memory.
3.1.3 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to
Table 3-4 Special Function Register List in 3.2.3 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
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3.1.4 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of
the register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
78K0/KF1+, based on operability and other considerations. For areas containing data memory in particular, special
addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are
available for use. Figures 3-3 and 3-4 show correspondence between data memory and addressing. For details of
each addressing mode, refer to 3.4 Operand Address Addressing.
Figure 3-3. Correspondence Between Data Memory and Addressing (μPD78F0148H)
FFFFH
Special function registers (SFR)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
General-purpose registers
32 × 8 bits
Register addressing
Short direct
addressing
Internal high-speed RAM
1024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
FA20H
FA1FH
FA00H
F9FFH
F800H
F7FFH
Reserved
Buffer RAM
32 × 8 bits
Direct addressing
Reserved
Register indirect addressing
Based addressing
Based indexed addressing
Internal expansion RAM
1024 × 8 bits
F400H
F3FFH
External memory
1024 × 8 bits
F000H
EFFFH
Flash memory
61440 × 8 bits
0000H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-4. Correspondence Between Data Memory and Addressing (μPD78F0148HD)
FFFFH
Special function registers (SFR)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
General-purpose registers
32 × 8 bits
Register addressing
Short direct
addressing
Internal high-speed RAM
1024 × 8 bits
Note 1
FB00H
FAFFH
FA20H
FA1FH
FA00H
F9FFH
F800H
F7FFH
Reserved
Direct addressing
Buffer RAM
32 × 8 bits
Register indirect addressing
Reserved
Based addressing
Based indexed addressing
Internal expansion RAM
1024 × 8 bits
F400H
F3FFH
External memory
1024 × 8 bits
F000H
EFFFH
Flash memory
61440 × 8 bits
Note 2
0000H
Notes 1. During on-chip debugging, about 7 to 16 bytes of this area are used as the user data backup area for
communication.
2. During on-chip debugging, use of this area is disabled because it is used as the communication
command area (008FH to 018FH: debugger’s default setting).
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3.2 Processor Registers
The 78K0/KF1+ products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-5. Format of Program Counter
15
PC
0
PC15 PC14 PC13 PC12 PC11 PC10 PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions.
RESET input sets the PSW to 02H.
Figure 3-6. Format of Program Status Word
7
PSW
IE
0
Z
RBS1
AC
RBS0
0
ISP
CY
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
Other interrupt requests are all disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is
controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
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CHAPTER 3 CPU ARCHITECTURE
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction
execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, lowlevel vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H)
(refer to 19.3 (3)
Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be
acknowledged. Actual request acknowledgment is controlled by the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
Figure 3-7. Format of Stack Pointer
15
SP
0
SP15 SP14 SP13 SP12 SP11 SP10 SP9
SP8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from
the stack memory.
Each stack operation saves/restores data as shown in Figures 3-8 and 3-9.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before using
the stack.
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Figure 3-8. Data to Be Saved to Stack Memory
(a) PUSH rp instruction (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
Register pair higher
FEDEH
Register pair lower
(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
PC15 to PC8
FEDEH
PC7 to PC0
(c) Interrupt, BRK instructions (when SP = FEE0H)
SP
SP
FEE0H
FEDDH
FEE0H
FEDFH
PSW
FEDEH
PC15 to PC8
FEDDH
PC7 to PC0
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-9. Data to Be Restored from Stack Memory
(a) POP rp instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
Register pair higher
FEDEH
Register pair lower
(b) RET instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
PC15 to PC8
FEDEH
PC7 to PC0
(c) RETI, RETB instructions (when SP = FEDDH)
SP
SP
56
FEE0H
FEDDH
FEE0H
FEDFH
PSW
FEDEH
PC15 to PC8
FEDDH
PC7 to PC0
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CHAPTER 3 CPU ARCHITECTURE
3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory.
The
general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register
(AX, BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of
the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupts for each bank.
Figure 3-10. Configuration of General-Purpose Registers
(a) Absolute name
16-bit processing
8-bit processing
FEFFH
R7
BANK0
RP3
R6
FEF8H
R5
BANK1
RP2
R4
FEF0H
R3
RP1
BANK2
R2
FEE8H
R1
RP0
BANK3
R0
FEE0H
15
0
7
0
(b) Function name
16-bit processing
8-bit processing
FEFFH
H
BANK0
HL
L
FEF8H
D
BANK1
DE
E
FEF0H
B
BC
BANK2
C
FEE8H
A
AX
BANK3
X
FEE0H
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7
0
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CHAPTER 3 CPU ARCHITECTURE
3.2.3 Special function registers (SFRs)
Unlike a general-purpose register, each special function register has a special function.
SFRs are allocated to the FF00H to FFFFH area.
Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit
manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When specifying an address, describe an even address.
Table 3-4 gives a list of the special function registers. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined
as an sfr variable using the #pragma sfr directive in the CC78K0. When using the RA78K0, ID78K0-NS,
ID78K0, or SM78K0, symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding special function register can be read or written.
R/W: Read/write enable
R:
Read only
W:
Write only
• Manipulatable bit units
Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon RESET input.
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Table 3-4. Special Function Register List (1/4)
Address
Special Function Register (SFR) Name
Symbol
R/W
1 Bit
Manipulatable Bit Unit
8 Bits
16 Bits
After
Reset
FF00H
Port register 0
P0
R/W
√
√
−
00H
FF01H
Port register 1
P1
R/W
√
√
−
00H
FF02H
Port register 2
P2
R
√
√
−
Undefined
FF03H
Port register 3
P3
R/W
√
√
−
00H
FF04H
Port register 4
P4
R/W
√
√
−
00H
FF05H
Port register 5
P5
R/W
√
√
−
00H
FF06H
Port register 6
P6
R/W
√
√
−
00H
FF07H
Port register 7
P7
R/W
√
√
−
00H
FF08H
A/D conversion result register
ADCR
R
−
−
√
Undefined
FF0AH
Receive buffer register 6
RXB6
R
−
√
−
FFH
FF0BH
Transmit buffer register 6
TXB6
R/W
−
√
−
FFH
FF0CH
Port register 12
P12
R/W
√
√
−
00H
FF0DH
Port register 13
P13
R/W
√
√
−
00H
FF0EH
Port register 14
P14
R/W
√
√
−
00H
FF0FH
Serial I/O shift register 10
SIO10
R
−
√
−
00H
FF10H
16-bit timer counter 00
TM00
R
−
−
√
0000H
16-bit timer capture/compare register 000
CR000
R/W
−
−
√
0000H
16-bit timer capture/compare register 010
CR010
R/W
−
−
√
0000H
FF16H
8-bit timer counter 50
TM50
R
−
√
−
00H
FF17H
8-bit timer compare register 50
CR50
R/W
−
√
−
00H
FF18H
8-bit timer H compare register 00
CMP00
R/W
−
√
−
00H
FF19H
8-bit timer H compare register 10
CMP10
R/W
−
√
−
00H
FF1AH
8-bit timer H compare register 01
CMP01
R/W
−
√
−
00H
FF1BH
8-bit timer H compare register 11
CMP11
R/W
−
√
−
00H
FF1FH
8-bit timer counter 51
TM51
R
−
√
−
00H
FF20H
Port mode register 0
PM0
R/W
√
√
−
FFH
FF21H
Port mode register 1
PM1
R/W
√
√
−
FFH
FF23H
Port mode register 3
PM3
R/W
√
√
−
FFH
FF24H
Port mode register 4
PM4
R/W
√
√
−
FFH
FF25H
Port mode register 5
PM5
R/W
√
√
−
FFH
FF26H
Port mode register 6
PM6
R/W
√
√
−
FFH
FF27H
Port mode register 7
PM7
R/W
√
√
−
FFH
FF28H
A/D converter mode register
ADM
R/W
√
√
−
00H
FF29H
Analog input channel specification register
ADS
R/W
√
√
−
00H
FF2AH
Power-fail comparison mode register
PFM
R/W
√
√
−
00H
FF2BH
Power-fail comparison threshold register
PFT
R/W
−
√
−
00H
FF2CH
Port mode register 12
PM12
R/W
√
√
−
FFH
FF2EH
Port mode register 14
PM14
R/W
√
√
−
FFH
FF09H
FF11H
FF12H
FF13H
FF14H
FF15H
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Table 3-4. Special Function Register List (2/4)
Address
Special Function Register (SFR) Name
Symbol
R/W
After
Manipulatable Bit Unit
1 Bit
8 Bits
16 Bits
Reset
FF30H
Pull-up resistor option register 0
PU0
R/W
√
√
−
00H
FF31H
Pull-up resistor option register 1
PU1
R/W
√
√
−
00H
FF33H
Pull-up resistor option register 3
PU3
R/W
√
√
−
00H
FF34H
Pull-up resistor option register 4
PU4
R/W
√
√
−
00H
FF35H
Pull-up resistor option register 5
PU5
R/W
√
√
−
00H
FF36H
Pull-up resistor option register 6
PU6
R/W
√
√
−
00H
FF37H
Pull-up resistor option register 7
PU7
R/W
√
√
−
00H
FF3CH
Pull-up resistor option register 12
PU12
R/W
√
√
−
00H
FF3EH
Pull-up resistor option register 14
PU14
R/W
√
√
−
00H
FF40H
Clock output selection register
CKS
R/W
√
√
−
00H
FF41H
8-bit timer compare register 51
CR51
R/W
−
√
−
00H
FF43H
8-bit timer mode control register 51
TMC51
R/W
√
√
−
00H
FF47H
Memory expansion mode register
MEM
R/W
√
√
−
00H
FF48H
External interrupt rising edge enable register
EGP
R/W
√
√
−
00H
FF49H
External interrupt falling edge enable register
EGN
R/W
√
√
−
00H
FF4AH
Serial I/O shift register 11
SIO11
R
−
√
−
00H
FF4CH
Transmit buffer register 11
SOTB11
R/W
−
√
−
Undefined
FF4FH
Input switch control register
ISC
R/W
√
√
−
00H
FF50H
Asynchronous serial interface operation mode
ASIM6
R/W
√
√
−
01H
ASIS6
R
−
√
−
00H
ASIF6
R
−
√
−
00H
register 6
FF53H
Asynchronous serial interface reception error
status register 6
FF55H
Asynchronous serial interface transmission
status register 6
FF56H
Clock selection register 6
CKSR6
R/W
−
√
−
00H
FF57H
Baud rate generator control register 6
BRGC6
R/W
−
√
−
FFH
FF58H
Asynchronous serial interface control register 6
ASICL6
R/W
√
√
−
16H
FF60H
Remainder data register 0
SDR0 SDR0L
R
−
√
√
00H
SDR0H
−
√
MDA0L MDA0LL R/W
−
√
FF63H
MDA0LH
−
√
FF64H
MDA0H MDA0HL R/W
−
√
−
√
−
√
−
√
FF61H
FF62H
Multiplication/division data register A0
FF65H
FF66H
MDA0HH
Multiplication/division data register B0
MDB0 MDB0L
FF67H
R/W
MDB0H
00H
√
00H
00H
√
00H
00H
√
00H
00H
FF68H
Multiplier/divider control register 0
DMUC0
R/W
√
√
−
00H
FF69H
8-bit timer H mode register 0
TMHMD0
R/W
√
√
−
00H
FF6AH
Timer clock selection register 50
TCL50
R/W
−
√
−
00H
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Table 3-4. Special Function Register List (3/4)
Address
Special Function Register (SFR) Name
Symbol
R/W
After
Manipulatable Bit Unit
1 Bit
8 Bits
16 Bits
Reset
FF6BH
8-bit timer mode control register 50
TMC50
R/W
√
√
−
00H
FF6CH
8-bit timer H mode register 1
TMHMD1
R/W
√
√
−
00H
FF6DH
8-bit timer H carrier control register 1
TMCYC1
R/W
√
√
−
00H
FF6EH
Key return mode register
KRM
R/W
√
√
−
00H
FF6FH
Watch timer operation mode register
WTM
R/W
√
√
−
00H
FF70H
Asynchronous serial interface operation mode
ASIM0
R/W
√
√
−
01H
R/W
−
√
−
1FH
register 0
FF71H
Baud rate generator control register 0
BRGC0
FF72H
Receive buffer register 0
RXB0
R
−
√
−
FFH
Asynchronous serial interface reception error
ASIS0
R
−
√
−
00H
W
−
√
−
FFH
FF73H
status register 0
FF74H
Transmit shift register 0
TXS0
FF80H
Serial operation mode register 10
CSIM10
R/W
√
√
−
00H
FF81H
Serial clock selection register 10
CSIC10
R/W
√
√
−
00H
FF84H
Transmit buffer register 10
SOTB10
R/W
−
√
−
Undefined
FF88H
Serial operation mode register 11
CSIM11
R/W
√
√
−
00H
FF89H
Serial clock selection register 11
CSIC11
R/W
√
√
−
00H
FF8CH
Timer clock selection register 51
TCL51
R/W
−
√
−
00H
FF90H
Serial operation mode specification register 0
CSIMA0
R/W
√
√
−
00H
FF91H
Serial status register 0
CSIS0
R/W
√
√
−
00H
FF92H
Serial trigger register 0
CSIT0
R/W
√
√
−
00H
FF93H
Divisor selection register 0
BRGCA0
R/W
−
√
−
03H
FF94H
Automatic data transfer address point
ADTP0
R/W
−
√
−
00H
ADTI0
R/W
−
√
−
00H
specification register 0
FF95H
Automatic data transfer interval specification
register 0
FF96H
Serial I/O shift register 0
SIOA0
R/W
−
√
−
00H
FF97H
Automatic data transfer address count register 0
ADTC0
R
−
√
−
00H
FF98H
Watchdog timer mode register
WDTM
R/W
−
√
−
67H
FF99H
Watchdog timer enable register
WDTE
R/W
−
√
−
9AH
FFA0H
Internal oscillation mode register
RCM
R/W
√
√
−
00H
FFA1H
Main clock mode register
MCM
R/W
√
√
−
00H
FFA2H
Main OSC control register
MOC
R/W
√
√
−
00H
FFA3H
Oscillation stabilization time counter status register OSTC
R
√
√
−
00H
FFA4H
Oscillation stabilization time select register
OSTS
R/W
−
√
−
05H
FFA9H
Clock monitor mode register
CLM
R/W
√
√
−
00H
FFACH
Reset control flag register
RESF
R
−
√
−
00H
FFB0H
16-bit timer counter 01
TM01
R
−
−
√
0000H
Note
FFB1H
Note This value varies depending on the reset source.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-4. Special Function Register List (4/4)
Address
Special Function Register (SFR) Name
Symbol
R/W
1 Bit
Manipulatable Bit Unit
8 Bits
16 Bits
After
Reset
16-bit timer capture/compare register 001
CR001
R/W
−
−
√
0000H
16-bit timer capture/compare register 011
CR011
R/W
−
−
√
0000H
FFB6H
16-bit timer mode control register 01
TMC01
R/W
√
√
−
00H
FFB7H
Prescaler mode register 01
PRM01
R/W
√
√
−
00H
FFB8H
Capture/compare control register 01
CRC01
R/W
√
√
−
00H
FFB9H
16-bit timer output control register 01
TOC01
R/W
√
√
−
00H
FFBAH
16-bit timer mode control register 00
TMC00
R/W
√
√
−
00H
FFBBH
Prescaler mode register 00
PRM00
R/W
√
√
−
00H
FFBCH
Capture/compare control register 00
CRC00
R/W
√
√
−
00H
FFBDH
16-bit timer output control register 00
TOC00
R/W
√
√
−
FFBEH
Low-voltage detection register
LVIM
R/W
√
√
−
00H
FFBFH
Low-voltage detection level selection register
LVIS
R/W
−
√
−
00H
FFC0H
Flash protect command register
PFCMD
W
−
√
−
FFC2H
Flash status register
PFS
R/W
√
√
−
FFC4H
Flash programming mode control register
FLPMC
R/W
√
√
−
FFE0H
Interrupt request flag register 0L
IF0
IF0L
R/W
√
√
√
FFE1H
Interrupt request flag register 0H
IF0H
R/W
√
√
FFE2H
Interrupt request flag register 1L
IF1L
R/W
√
√
FFE3H
Interrupt request flag register 1H
IF1H
R/W
√
√
FFE4H
Interrupt mask flag register 0L
MK0L R/W
√
√
FFE5H
Interrupt mask flag register 0H
MK0H R/W
√
√
MK1L R/W
√
√
MK1H R/W
√
√
PR0L R/W
√
√
PR0H R/W
√
√
PR1L R/W
√
√
PR1H R/W
√
√
IMS
R/W
−
√
−
CFH
FFB2H
FFB3H
FFB4H
FFB5H
FFE6H
Interrupt mask flag register 1L
FFE7H
Interrupt mask flag register 1H
FFE8H
Priority specification flag register 0L
FFE9H
Priority specification flag register 0H
FFEAH
Priority specification flag register 1L
FFEBH
Priority specification flag register 1H
FFF0H
IF1
MK0
MK1
PR0
PR1
Internal memory size switching register
Note 3
00H
Note 1
Note 1
Undefined
00H
Note 2
0XH
00H
00H
√
00H
00H
√
FFH
FFH
√
FFH
DFH
√
FFH
FFH
√
FFH
FFH
FFF4H
Internal expansion RAM size switching register
IXS
R/W
−
√
−
0CH
FFF8H
Memory expansion wait setting register
MM
R/W
√
√
−
10H
FFFBH
Processor clock control register
PCC
R/W
√
√
−
00H
Notes 1.
This value varies depending on the reset source.
2.
Note 3
This value varies depending on the operation mode.
• User mode: 08H
• On-board mode: 0CH
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CHAPTER 3 CPU ARCHITECTURE
Note 3. Because the initial value of the internal expansion RAM size switching register (IXS) is 0CH, set IXS = 0AH
as the initial setting. When using the 78K0/KF1+ to evaluate the program of a mask ROM version of the
78K0/KF1, set the following values to the internal memory size switching register (IMS) and IXS.
Flash Memory Version
Target Mask ROM Version
(78K0/KF1+)
(78K0/KF1)
IMS
−
μPD780143
−
μPD780144
C8H
−
μPD780146
CCH
μPD78F0148H, 78F0148HD μPD780148
CFH
C6H
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0CH
0AH
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CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each
byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is
executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by
the following addressing (for details of instructions, refer to 78K/0 Series Instructions User’s Manual (U12326E).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched.
The
displacement value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.
In other words, relative addressing consists of relative branching from the start address of the following
instruction to the −128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
0
... PC indicates the start address
of the instruction after the BR instruction.
PC
+
8
15
α
7
6
0
S
jdisp8
15
0
PC
When S = 0, all bits of α are 0.
When S = 1, all bits of α are 1.
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3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11
instruction is branched to the 0800H to 0FFFH area.
[Illustration]
In the case of CALL !addr16 and BR !addr16 instructions
7
0
CALL or BR
Low Addr.
High Addr.
15
8 7
0
PC
In the case of CALLF !addr11 instruction
7 6
4
3
0
CALLF
fa10–8
fa7–0
15
PC
0
11 10
0
0
0
8 7
0
1
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CHAPTER 3 CPU ARCHITECTURE
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operation code are transferred to the program counter (PC) and branched.
This function is carried out when the CALLT [addr5] instruction is executed.
This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to
the entire memory space.
[Illustration]
7
Operation code
6
1
5
1
1
ta4–0
1
15
Effective address
0
7
0
0
0
0
0
0
0
Memory (Table)
8
7
6
0
0
1
5
1 0
0
0
Low Addr.
High Addr.
Effective address+1
8
15
7
0
PC
3.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
rp
0
7
A
15
X
8
7
PC
66
0
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CHAPTER 3 CPU ARCHITECTURE
3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.4.1 Implied addressing
[Function]
The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically
(implicitly) addressed.
Of the 78K0/KF1+ instruction words, the following instructions employ implied addressing.
Instruction
Register to Be Specified by Implied Addressing
MULU
A register for multiplicand and AX register for product storage
DIVUW
AX register for dividend and quotient storage
ADJBA/ADJBS
A register for storage of numeric values that become decimal correction targets
ROR4/ROL4
A register for storage of digit data that undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format is
necessary.
[Description example]
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
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CHAPTER 3 CPU ARCHITECTURE
3.4.2 Register addressing
[Function]
The general-purpose register to be specified is accessed as an operand with the register bank select flags
(RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
rp
AX, BC, DE, HL
‘r’ and ‘rp’ can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; when selecting C register as r
Operation code
0
1
1
0
0
0
1
0
Register specify code
INCW DE; when selecting DE register pair as rp
Operation code
1
0
0
0
0
1
0
0
Register specify code
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CHAPTER 3 CPU ARCHITECTURE
3.4.3 Direct addressing
[Function]
The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an
operand address.
[Operand format]
Identifier
Description
addr16
Label or 16-bit immediate data
[Description example]
MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code
1
0
0
0
1
1
1
0
OP code
0
0
0
0
0
0
0
0
00H
1
1
1
1
1
1
1
0
FEH
[Illustration]
7
0
OP code
addr16 (lower)
addr16 (upper)
Memory
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CHAPTER 3 CPU ARCHITECTURE
3.4.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers
(SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter
are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. Refer to the [Illustration] shown below.
[Operand format]
Identifier
Description
saddr
Immediate data that indicate label or FE20H to FF1FH
saddrp
Immediate data that indicate label or FE20H to FF1FH (even address only)
[Description example]
MOV 0FE30H, A; when transferring value of A register to saddr (FE30H)
Operation code
1
1
1
1
0
0
1
0
OP code
0
0
1
1
0
0
0
0
30H (saddr-offset)
[Illustration]
7
0
OP code
saddr-offset
Short direct memory
8 7
15
Effective address
1
1
1
1
1
1
1
α
When 8-bit immediate data is 20H to FFH, α = 0
When 8-bit immediate data is 00H to 1FH, α = 1
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CHAPTER 3 CPU ARCHITECTURE
3.4.5 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier
Description
sfr
Special function register name
sfrp
16-bit manipulatable special function register name (even address
only)
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code
1
1
1
1
0
1
1
0
OP code
0
0
1
0
0
0
0
0
20H (sfr-offset)
[Illustration]
7
0
OP code
sfr-offset
SFR
8 7
15
Effective address
1
1
1
1
1
1
1
0
1
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CHAPTER 3 CPU ARCHITECTURE
3.4.6 Register indirect addressing
[Function]
Register pair contents specified by a register pair specify code in an instruction word and by a register bank
select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be
carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[DE], [HL]
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code
1
0
0
0
0
1
0
1
[Illustration]
16
DE
8 7
D
0
E
7
Memory
The contents of the memory
addressed are transferred.
7
0
A
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0
The memory address
specified with the
register pair DE
CHAPTER 3 CPU ARCHITECTURE
3.4.7 Based addressing
[Function]
8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in
the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address
the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from
the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
−
Description
[HL + byte]
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code
1
0
1
0
1
1
1
0
0
0
0
1
0
0
0
0
[Illustration]
16
HL
8 7
H
0
L
7
Memory
0
+10
The contents of the memory
addressed are transferred.
7
0
A
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CHAPTER 3 CPU ARCHITECTURE
3.4.8 Based indexed addressing
[Function]
The B or C register contents specified in an instruction word are added to the contents of the base register, that
is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the
sum is used to address the memory. Addition is performed by expanding the B or C register contents as a
positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the
memory spaces.
[Operand format]
Identifier
−
Description
[HL + B], [HL + C]
[Description example]
MOV A, [HL + B]; when selecting B register
Operation code
1
0
1
0
1
0
1
1
[Illustration]
16
HL
8
7
0
L
H
+
7
0
B
7
Memory
The contents of the memory
addressed are transferred.
7
0
A
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CHAPTER 3 CPU ARCHITECTURE
3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call and return
instructions are executed or the register is saved/reset upon generation of an interrupt request.
With stack addressing, only the internal high-speed RAM area can be accessed.
[Description example]
PUSH DE; when saving DE register
Operation code
1
0
1
1
0
1
0
1
[Illustration]
7
SP
SP
FEE0H
FEDEH
Memory
0
FEE0H
FEDFH
D
FEDEH
E
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CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
There are two types of pin I/O buffer power supplies: AVREF and EVDD. The relationship between these power
supplies and the pins is shown below.
Table 4-1. Pin I/O Buffer Power Supplies
Power Supply
Corresponding Pins
AVREF
P20 to P27
EVDD
Port pins other than P20 to P27
78K0/KF1+ products are provided with the ports shown in Figure 4-1, which enable variety of control operations.
The functions of each port are shown in Table 4-2.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the
alternate functions, refer to CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Types
P50
P00
Port 0
Port 5
P06
P57
P10
P60
Port 1
Port 6
P17
P67
P20
P70
Port 2
Port 7
P27
P77
P30
Port 12
P120
Port 13
P130
P33
P140
P40
Port 3
Port 14
Port 4
P145
P47
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CHAPTER 4 PORT FUNCTIONS
Table 4-2. Port Functions (1/2)
Pin Name
P00
I/O
I/O
Function
Port 0.
After Reset
Input
7-bit I/O port.
P01
SO11
Use of an on-chip pull-up resistor can be specified by a
P03
TI000
TI010/TO00
Input/output can be specified in 1-bit units.
P02
Alternate Function
SI11
software setting.
P04
SCK11
P05
SSI11/TI001
P06
TI011/TO01
P10
I/O
Port 1.
Input
8-bit I/O port.
P11
SI10/RxD0
Input/output can be specified in 1-bit units.
P12
SO10
Use of an on-chip pull-up resistor can be specified by a
P13
SCK10/TxD0
TxD6
software setting.
P14
RxD6
P15
TOH0
P16
TOH1/INTP5/
FLMD1
P17
P20 to P27
TI50/TO50
Input
Port 2.
Input
ANI0 to ANI7
Input
INTP1 to INTP3
8-bit input-only port.
P30 to P32
I/O
Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
P33
Use of an on-chip pull-up resistor can be specified by a
INTP4/TI51/TO51
software setting.
P40 to P47
I/O
Port 4.
Input
AD0 to AD7
Input
A8 to A15
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P50 to P57
I/O
Port 5.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P60 to P63
P64
P65
P66
I/O
−
Port 6.
N-ch open-drain I/O port.
8-bit I/O port.
Use of an on-chip pull-up
RD
Input/output can be specified
resistor can be specified by a
in 1-bit units.
WR
software setting.
P67
Input
WAIT
ASTB
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CHAPTER 4 PORT FUNCTIONS
Table 4-2. Port Functions (2/2)
Pin Name
I/O
P70 to P77
I/O
Function
After Reset
Port 7.
Alternate Function
Input
KR0 to KR7
Input
INTP0
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
I/O
Port 12.
1-bit I/O port.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P130
Output
Port 13.
−
Output
1-bit output-only port.
P140
I/O
P141
Port 14.
Input
BUZ/BUSY0/
Input/output can be specified in 1-bit units.
INTP7
Use of an on-chip pull-up resistor can be specified by a
P142
PCL/INTP6
6-bit I/O port.
software setting.
SCKA0
P143
SIA0
P144
SOA0
P145
STB0
4.2 Port Configuration
Ports consist of the following hardware.
Table 4-3. Port Configuration
Item
Control registers
Configuration
Port mode register (PM0, PM1, PM3 to PM7, PM12, PM14)
Port register (P0 to P7, P12 to P14)
Pull-up resistor option register (PU0, PU1, PU3 to PU7, PU12, PU14)
Port
Total: 67 (CMOS I/O: 54, CMOS input: 8, CMOS output: 1, N-ch open drain I/O: 4)
Pull-up resistor
Total: 54
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CHAPTER 4 PORT FUNCTIONS
4.2.1 Port 0
Port 0 is a 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units
using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
This port can also be used for timer I/O, serial interface data I/O, and clock I/O.
RESET input sets port 0 to input mode.
Figures 4-2 to 4-5 show block diagrams of port 0.
Caution To use P02/SO11, P03/SI11, and P04/SCK11 as general-purpose ports, set serial operation mode
register 11 (CSIM11) and serial clock selection register 11 (CSIC11) to the default status (00H).
Figure 4-2. Block Diagram of P00, P03, and P05
EVDD
WRPU
PU0
PU00, PU03, PU05
P-ch
Alternate function
Selector
RD
Internal bus
WRPORT
Output latch
(P00, P03, P05)
P00/TI000,
P03/SI11,
P05/SSI11/TI001
WRPM
PM0
PM00, PM03, PM05
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
RD:
Read signal
WR××: Write signal
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Figure 4-3. Block Diagram of P01 and P06
EVDD
WRPU
PU0
PU01, PU06
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P01, P06)
P01/TI010/TO00,
P06/TI011/TO01
WRPM
PM0
PM01, PM06
Alternate
function
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
RD:
Read signal
WR××: Write signal
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Figure 4-4. Block Diagram of P02
EVDD
WRPU
PU0
PU02
P-ch
Internal bus
Selector
RD
WRPORT
Output latch
(P02)
P02/SO11
WRPM
PM0
PM02
Alternate
function
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
RD:
Read signal
WR××: Write signal
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Figure 4-5. Block Diagram of P04
EVDD
WRPU
PU0
PU04
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P04)
P04/SCK11
WRPM
PM0
PM04
Alternate
function
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
RD:
Read signal
WR××: Write signal
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4.2.2 Port 1
Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units
using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, timer I/O, and
flash memory programming mode setting.
RESET input sets port 1 to input mode.
Figures 4-6 to 4-10 show block diagrams of port 1.
Caution To use P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 as general-purpose ports, set serial
operation mode register 10 (CSIM10) and serial clock selection register 10 (CSIC10) to the default
status (00H).
Figure 4-6. Block Diagram of P10
EVDD
WRPU
PU1
PU10
P-ch
Alternate
function
Selector
RD
Internal bus
WRPORT
Output latch
(P10)
P10/SCK10/TxD0
WRPM
PM1
PM10
Alternate
function
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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Figure 4-7. Block Diagram of P11 and P14
EVDD
WRPU
PU1
PU11, PU14
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P11, P14)
P11/SI10/RxD0,
P14/RxD6
WRPM
PM1
PM11, PM14
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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Figure 4-8. Block Diagram of P12 and P15
EVDD
WRPU
PU1
PU12, PU15
P-ch
Internal bus
Selector
RD
WRPORT
Output latch
(P12, P15)
P12/SO10
P15/TOH0
WRPM
PM1
PM12, PM15
Alternate
function
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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Figure 4-9. Block Diagram of P13
EVDD
WRPU
PU1
PU13
P-ch
Selector
Internal bus
RD
WRPORT
Output latch
(P13)
P13/TxD6
WRPM
PM1
PM13
Alternate
function
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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Figure 4-10. Block Diagram of P16 and P17
EVDD
WRPU
PU1
PU16, PU17
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P16, P17)
P16/TOH1/INTP5,
P17/TI50/TO50/FLMD1
WRPM
PM1
PM16, PM17
Alternate
function
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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4.2.3 Port 2
Port 2 is an 8-bit input-only port.
This port can also be used for A/D converter analog input.
Figure 4-11 shows a block diagram of port 2.
Figure 4-11. Block Diagram of P20 to P27
Internal bus
RD
A/D converter
RD:
88
P20/ANI0 to P27/ANI7
Read signal
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CHAPTER 4 PORT FUNCTIONS
4.2.4 Port 3
Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units
using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified in
1-bit units by pull-up resistor option register 3 (PU3).
This port can also be used for external interrupt request input and timer I/O.
RESET input sets port 3 to input mode.
Figures 4-12 and 4-13 show block diagrams of port 3.
Caution In the μPD78F0148HD, be sure to pull the P31 pin down after reset to prevent malfunction.
P31/INTP2 and P32/INTP3 of the μPD78F0148HD can be used for on-chip debug mode setting when
Remark
the on-chip debug function is used. For details, refer to CHAPTER 28 ON-CHIP DEBUG FUNCTION
(μPD78F0148HD ONLY).
Figure 4-12. Block Diagram of P30 to P32
EVDD
WRPU
PU3
PU30 to PU32
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P30 to P32)
P30/INTP1 to
P32/INTP3
WRPM
PM3
PM30 to PM32
PU3:
Pull-up resistor option register 3
PM3:
Port mode register 3
RD:
Read signal
WR××: Write signal
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Figure 4-13. Block Diagram of P33
EVDD
WRPU
PU3
PU33
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P33)
P33/INTP4/TI51/TO51
WRPM
PM3
PM33
Alternate
function
PU3:
Pull-up resistor option register 3
PM3:
Port mode register 3
RD:
Read signal
WR××: Write signal
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4.2.5 Port 4
Port 4 is an 8-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units
using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor
option register 4 (PU4).
This port can also be used as an address/data bus in external memory expansion mode.
RESET input sets port 4 to input mode.
Figure 4-14 shows a block diagram of port 4.
Figure 4-14. Block Diagram of P40 to P47
EVDD
WRPU
PU4
PU40 to PU47
Alternate
function
RD
P-ch
Selector
WRPORT
Internal bus
Output latch
(P40 to P47)
Selector
P40/AD0 to P47/AD7
Alternate
function
WRPM
PM4
PM40 to PM47
Memory expansion
mode register
(MEM)
PU4:
Pull-up resistor option register 4
PM4: Port mode register 4
RD:
Read signal
WR××: Write signal
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4.2.6 Port 5
Port 5 is an 8-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units
using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified in 1-bit units using pull-up
resistor option register 5 (PU5).
This port can also be used as an address bus in external memory expansion mode.
RESET input sets port 5 to input mode.
Figure 4-15 shows a block diagram of port 5.
Figure 4-15. Block Diagram of P50 to P57
EVDD
WRPU
PU5
PU50 to PU57
P-ch
RD
Selector
WRPORT
Internal bus
Output latch
(P50 to P57)
Selector
Alternate
function
WRPM
PM5
PM50 to PM57
Memory expansion
mode register
(MEM)
PU5:
Pull-up resistor option register 5
PM5: Port mode register 5
RD:
Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
4.2.7 Port 6
Port 6 is an 8-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units
using port mode register 6 (PM6).
This port has the following functions for pull-up resistors.
These functions differ depending on the higher 4
bits/lower 4 bits of the port.
Table 4-4. Pull-up Resistor of Port 6
Higher 4 Bits (Pins P64 to P67)
An on-chip pull-up resistor can be
Lower 4 Bits (Pins P60 to P63)
On-chip pull-up resistors are not provided
connected in 1-bit units by PU6
PU6: Pull-up resistor option register 6
The P60 to P63 pins are N-ch open-drain pins.
The P64 to P67 pins can also be used for the control signal output function in external memory expansion mode.
RESET input sets port 6 to input mode.
Figures 4-16 to 4-18 show block diagrams of port 6.
Caution P66 can be used as an I/O port when an external wait is not used in external memory expansion
mode.
Figure 4-16. Block Diagram of P60 to P63
RD
Internal bus
Selector
WRPORT
Output latch
(P60 to P63)
WRPM
P60 to P63
PM6
PM60 to PM63
PM6: Port mode register 6
RD:
Read signal
WR××: Write signal
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Figure 4-17. Block Diagram of P64, P65, and P67
EVDD
WRPU
PU6
PU64, PU65, PU67
P-ch
RD
Selector
WRPORT
Internal bus
Output latch
(P64, P65, P67)
Selector
Alternate
function
WRPM
PM6
PM64, PM65, PM67
Memory expansion
mode register
(MEM)
PU6:
Pull-up resistor option register 6
PM6: Port mode register 6
RD:
Read signal
WR××: Write signal
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P64/RD,
P65/WR,
P67/ASTB
CHAPTER 4 PORT FUNCTIONS
Figure 4-18. Block Diagram of P66
EVDD
WRPU
PU6
PU66
Alternate
function
RD
P-ch
Internal bus
Selector
WRPORT
Output latch
(P66)
WRPM
Selector
P66/WAIT
Memory expansion
mode register
(MEM)
PM6
PM66
PU6:
Pull-up resistor option register 6
PM6: Port mode register 6
RD:
Read signal
WR××: Write signal
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4.2.8 Port 7
Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units
using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7).
This port can also be used for key return input.
RESET input sets port 7 to input mode.
Figure 4-19 shows a block diagram of port 7.
Figure 4-19. Block Diagram of P70 to P77
EVDD
WRPU
PU7
PU70 to PU77
P-ch
Alternate function
Selector
Internal bus
RD
WRPORT
Output latch
(P70 to P77)
P70/KR0 to
P77/KR7
WRPM
PM7
PM70 to PM77
PU7:
Pull-up resistor option register 7
PM7:
Port mode register 7
RD:
Read signal
WR××: Write signal
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4.2.9 Port 12
Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units
using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified
by pull-up resistor option register 12 (PU12).
This port can also be used for external interrupt request input.
RESET input sets port 12 to input mode.
Figure 4-20 shows a block diagram of port 12.
Figure 4-20. Block Diagram of P120
EVDD
WRPU
PU12
PU120
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P120)
P120/INTP0
WRPM
PM12
PM120
PU12:
Pull-up resistor option register 12
PM12:
Port mode register 12
RD:
Read signal
WR××: Write signal
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4.2.10 Port 13
Port 13 is a 1-bit output-only port.
Figure 4-21 shows a block diagram of port 13.
Figure 4-21. Block Diagram of P130
Internal bus
RD
WRPORT
Output latch
(P130)
RD:
P130
Read signal
WR××: Write signal
Remark
When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
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4.2.11 Port 14
Port 14 is a 6-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units
using port mode register 14 (PM14). When the P140 to P145 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, busy input,
buzzer output, and clock output.
RESET input sets port 14 to input mode.
Figures 4-22 to 4-25 show block diagrams of port 14.
Figure 4-22. Block Diagram of P140 and P141
EVDD
WRPU
PU14
PU140, PU141
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P140, P141)
P140/PCL/INTP6,
P141/BUZ/BUSY0
/INTP7
WRPM
PM14
PM140, PM141
Alternate
function
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
RD:
Read signal
WR××: Write signal
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Figure 4-23. Block Diagram of P142
EVDD
WRPU
PU14
PU142
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P142)
P142/SCKA0
WRPM
PM14
PM142
Alternate
function
PU14: Pull-up resistor option register 14
PM14: Port mode register 14
RD:
Read signal
WR××: Write signal
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Figure 4-24. Block Diagram of P143
EVDD
WRPU
PU14
PU143
P-ch
Alternate function
Selector
Internal bus
RD
WRPORT
Output latch
(P143)
P143/SIA0
WRPM
PM14
PM143
PU14: Pull-up resistor option register 14
PM14: Port mode register 14
RD:
Read signal
WR××: Write signal
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Figure 4-25. Block Diagram of P144 and P145
EVDD
WRPU
PU14
PU144, PU145
P-ch
Internal bus
Selector
RD
WRPORT
Output latch
(P144, P145)
P144/SOA0,
P145/STB0
WRPM
PM14
PM144, PM145
Alternate
function
PU14: Pull-up resistor option register 14
PM14: Port mode register 14
RD:
Read signal
WR××: Write signal
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4.3 Registers Controlling Port Function
Port functions are controlled by the following three types of registers.
• Port mode registers (PM0, PM1, PM3 to PM7, PM12, PM14)
• Port registers (P0 to P7, P12 to P14)
• Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, PU14)
(1) Port mode registers (PM0, PM1, PM3 to PM7, PM12, and PM14
These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table
4-5.
Figure 4-26. Format of Port Mode Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM0
1
PM06
PM05
PM04
PM03
PM02
PM01
PM00
FF20H
FFH
R/W
7
6
5
4
3
2
1
0
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FF21H
FFH
R/W
7
6
5
4
3
2
1
0
1
1
1
1
PM33
PM32
PM31
PM30
FF23H
FFH
R/W
7
6
5
4
3
2
1
0
PM47
PM46
PM45
PM44
PM43
PM42
PM41
PM40
FF24H
FFH
R/W
7
6
5
4
3
2
1
0
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FF25H
FFH
R/W
7
6
5
4
3
2
1
0
PM6
PM67
PM66
PM65
PM64
PM63
PM62
PM61
PM60
FF26H
FFH
R/W
7
6
5
4
3
2
1
0
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
FF27H
FFH
R/W
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
PM120
FF2CH
FFH
R/W
7
6
5
4
3
2
1
0
1
1
PM145
PM144
PM143
PM142
PM141
PM140
FF2EH
FFH
R/W
PM1
PM3
PM4
PM5
PM12
PM14
Pmn pin I/O mode selection
PMmn
(m = 0, 1, 3 to 7, 12, 14; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2)
Pin Name
Alternate Function
Function Name
PM××
P××
I/O
P00
TI000
Input
1
×
P01
TI010
Input
1
×
TO00
Output
0
0
P02
SO11
Output
0
0
P03
SI11
Input
1
×
P04
SCK11
Input
1
×
Output
0
1
P05
SSI11
Input
1
×
TI001
Input
1
×
TI011
Input
1
×
0
P06
P10
P11
TO01
Output
0
SCK10
Input
1
×
Output
0
1
TxD0
Output
0
1
×
SI10
Input
1
RxD0
Input
1
×
P12
SO10
Output
0
0
P13
TxD6
Output
0
1
P14
RxD6
Input
1
×
P15
TOH0
Output
0
0
P16
TOH1
Output
0
0
INTP5
Input
1
×
TI50
Input
1
×
TO50
Output
0
0
P30 to P32
INTP1 to INTP3
Input
1
×
P33
INTP4
Input
1
×
P17
TI51
Input
1
×
TO51
Output
0
0
P40 to P47
AD0 to AD7
I/O
×
Note
P50 to P57
A8 to A15
Output
×
Note
P64
RD
Output
×
Note
P65
WR
Output
×
Note
P66
WAIT
Input
P67
ASTB
Output
1
×
Note
Note
×
Note
Note When using the alternate functions of the P40 to P47, P50 to P57, and P64 to P67 pins, select the function by
using the memory expansion mode register (MEM).
Remark
×:
Don’t care
PM××: Port mode register
P××:
104
Port output latch
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Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2)
Pin Name
Alternate Function
Function Name
PM××
P××
×
I/O
P70 to P77
KR0 to KR7
Input
1
P120
INTP0
Input
1
×
P140
PCL
Output
0
0
INTP6
Input
1
×
BUZ
Output
0
0
BUSY0
Input
1
×
INTP7
Input
1
×
P142
SCKA0
Input
1
×
Output
0
1
P143
SIA0
Input
1
×
P144
SOA0
Output
0
0
P145
STB0
Output
0
0
P141
Remark
×:
Don’t care
PM××: Port mode register
P××:
Port output latch
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(2) Port registers (P0 to P7, P12 to P14)
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output
latch is read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H (but P2 is undefined).
Figure 4-27. Format of Port Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
P0
0
P06
P05
P04
P03
P02
P01
P00
FF00H
00H (output latch)
R/W
7
6
5
4
3
2
1
0
P1
P17
P16
P15
P14
P13
P12
P11
P10
FF01H
00H (output latch)
R/W
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
FF02H
Undefined
R
7
6
5
4
3
2
1
0
0
0
0
0
P33
P32
P31
P30
FF03H
00H (output latch)
R/W
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
FF04H
00H (output latch)
R/W
7
6
5
4
3
2
1
0
P5
P57
P56
P55
P54
P53
P52
P51
P50
FF05H
00H (output latch)
R/W
7
6
5
4
3
2
1
0
P6
P67
P66
P65
P64
P63
P62
P61
P60
FF06H
00H (output latch)
R/W
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
FF07H
00H (output latch)
R/W
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
P120
FF0CH
00H (output latch)
R/W
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
P130
FF0DH
00H (output latch)
R/W
FF0EH
00H (output latch)
R/W
P2
P3
P4
P7
P12
P13
P14
7
6
5
4
3
2
1
0
0
0
P145
P144
P143
P142
P141
P140
m = 0 to 7, 12 to 14; n = 0 to 7
Pmn
Output data control (in output mode)
106
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
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CHAPTER 4 PORT FUNCTIONS
(3) Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, and PU14)
These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30 to P33, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P120, or P140 to P145 are to be used or not. On-chip pull-up resistors can
be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor
has been specified in PU0, PU1, PU3 to PU7, PU12, and PU14. On-chip pull-up resistors cannot be connected
to bits set to output mode and bits used as alternate-function output pins, regardless of the settings of PU0, PU1,
PU3 to PU7, PU12, and PU14.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figure 4-28. Format of Pull-up Resistor Option Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PU0
0
PU06
PU05
PU04
PU03
PU02
PU01
PU00
FF30H
00H
R/W
7
6
5
4
3
2
1
0
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
FF31H
00H
R/W
7
6
5
4
3
2
1
0
PU3
0
0
0
0
PU33
PU32
PU31
PU30
FF33H
00H
R/W
7
6
5
4
3
2
1
0
PU4
PU47
PU46
PU45
PU44
PU43
PU42
PU41
PU40
FF34H
00H
R/W
7
6
5
4
3
2
1
0
PU57
PU56
PU55
PU54
PU53
PU52
PU51
PU50
FF35H
00H
R/W
7
6
5
4
3
2
1
0
PU67
PU66
PU65
PU64
0
0
0
0
FF36H
00H
R/W
7
6
5
4
3
2
1
0
PU77
PU76
PU75
PU74
PU73
PU72
PU71
PU70
FF37H
00H
R/W
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
PU120
FF3CH
00H
R/W
7
6
5
4
3
2
1
0
0
0
PU145
PU144
PU143
PU142
PU141
PU140
FF3EH
00H
R/W
PU1
PU5
PU6
PU7
PU12
PU14
PUmn
Pmn pin on-chip pull-up resistor selection
(m = 0, 1, 3 to 7, 12, 14; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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CHAPTER 4 PORT FUNCTIONS
4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the
port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the
output latch contents for pins specified as input are undefined, even for bits other than the
manipulated bit.
4.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared by reset.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does
not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
4.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output
latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared by reset.
(2) Input mode
The pin level is read and an operation is performed on its contents. The result of the operation is written to the
output latch, but since the output buffer is off, the pin status does not change.
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CHAPTER 5 EXTERNAL BUS INTERFACE
5.1
External Bus Interface
The external bus interface connects external devices to areas other than the internal ROM, RAM, and SFR areas.
Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/write strobe, wait, address
strobe, etc.
The external bus interface is usable only when the high-speed system clock is selected as the CPU clock.
Caution
The external bus interface function cannot be used in (A1) grade products.
Table 5-1. Pin Functions in External Memory Expansion Mode
Pin Function When External Device Is Connected
Name
Alternate Function
Function
AD0 to AD7
Multiplexed address/data bus
P40 to P47
A8 to A15
Address bus
P50 to P57
RD
Read strobe signal
P64
WR
Write strobe signal
P65
WAIT
Wait signal
P66
ASTB
Address strobe signal
P67
Table 5-2. State of Ports 4 to 6 Pins in External Memory Expansion Mode
External
Port 4
Port
0 to 7
Expansion Mode
Port 5
0
1
2
3
4
Port 6
5
6
7
0
1
2
3
4
5
6
7
Single-chip mode
Port
Port
Port
256-byte expansion mode
Address/data
Port
Port
RD, WR, WAIT, ASTB
4 KB expansion mode
Address/data
Address
Port
RD, WR, WAIT, ASTB
16 KB expansion mode
Address/data
Address
Port
RD, WR, WAIT, ASTB
Full-address mode
Address/data
Address
Port
RD, WR, WAIT, ASTB
Caution
Port
Port
When the external wait function is not used, the WAIT pin can be used as a port in all modes.
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CHAPTER 5 EXTERNAL BUS INTERFACE
The memory maps when the external bus interface is used are as follows.
Figure 5-1. Memory Map When Using External Bus Interface (1/2)
(a) Memory map of 78K0/KF1+ when flash memory is (b) Memory map of 78K0/KF1+ when flash memory is
24 KB, internal expansion RAM is 0 bytes
32 KB, internal expansion RAM is 0 bytes
FFFFH
FFFFH
SFR
SFR
FF00H
FEFFH
FF00H
FEFFH
Internal high-speed RAM
FB00H
FAFFH
Internal high-speed RAM
FB00H
FAFFH
Reserved
Reserved
FA20H
FA1FH
FA20H
FA1FH
Buffer RAM
FA00H
F9FFH
Buffer RAM
FA00H
F9FFH
Reserved
Reserved
F800H
F7FFH
F800H
F7FFH
Full-address mode
(when MM2 to MM0 = 111)
Full-address mode
(when MM2 to MM0 = 111)
C000H
BFFFH
A000H
9FFFH
16 KB expansion mode
(when MM2 to MM0 = 101)
16 KB expansion mode
(when MM2 to MM0 = 101)
9000H
8FFFH
4 KB expansion mode
(when MM2 to MM0 = 100)
7000H
6FFFH
4 KB expansion mode
(when MM2 to MM0 = 100)
6100H
60FFH
6000H
5FFFH
256-byte expansion mode
(when MM2 to MM0 = 011)
8100H
80FFH
8000H
7FFFH
Single-chip mode
Single-chip mode
0000H
110
256-byte expansion mode
(when MM2 to MM0 = 011)
0000H
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CHAPTER 5 EXTERNAL BUS INTERFACE
Figure 5-1. Memory Map When Using External Bus Interface (2/2)
(c) Memory map of μPD78F0148H and μPD78F0148HD (d) Memory map of μPD78F0148H and μPD78F0148HD
when flash memory is 48 KB, internal explanation
when flash memory is 60 KB, internal explanation
RAM is 1 KB
RAM is 1 KB
FFFFH
FFFFH
SFR
SFR
FF00H
FEFFH
FF00H
FEFFH
Internal high-speed RAM
Internal high-speed RAM
FB00H
FAFFH
FB00H
FAFFH
Reserved
Reserved
FA20H
FA1FH
FA20H
FA1FH
Buffer RAM
FA00H
F9FFH
Buffer RAM
FA00H
F9FFH
Reserved
Reserved
F800H
F7FFH
F800H
F7FFH
Internal expansion RAM
Internal expansion RAM
F400H
F3FFH
F400H
F3FFH
Full-address mode
(when MM2 to MM0 = 111)
or
16 KB expansion mode
(when MM2 to MM0 = 101)
or
4 KB expansion mode
(when MM2 to MM0 = 100)
Full-address mode
(when MM2 to MM0 = 111)
or
16 KB expansion mode
(when MM2 to MM0 = 101)
D000H
CFFFH
4 KB expansion mode
(when MM2 to MM0 = 100)
C100H
C0FFH
C000H
BFFFH
256-byte expansion mode
(when MM2 to MM0 = 011)
F100H
F0FFH
F000H
EFFFH
256-byte expansion mode
(when MM2 to MM0 = 011)
Single-chip mode
Single-chip mode
0000H
0000H
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CHAPTER 5 EXTERNAL BUS INTERFACE
5.2
Registers Controlling External Bus Interface
The external bus interface is controlled by the following two registers.
• Memory expansion mode register (MEM)
• Memory expansion wait setting register (MM)
(1) Memory expansion mode register (MEM)
MEM sets the external expansion area.
MEM is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears MEM to 00H.
Figure 5-2. Format of Memory Expansion Mode Register (MEM)
Address: FF47H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
MEM
0
0
0
0
0
MM2
MM1
MM0
MM2
MM1
MM0
Single-chip/memory
P40 to P47, P50 to P57, P64 to P67 pin state
expansion mode selection P40 to P47 P50 to P53 P54, P55
0
0
0
Single-chip mode
Port mode
0
1
1
Memory
AD0 to
256-byte
expansion mode
1
0
0
mode
P56, P57 P64 to P67
P64 = RD
Port mode
AD7
P65 = WR
Note
4 KB
P66 = WAIT
A8 to A11 Port mode
P67 = ASTB
mode
1
0
1
16 KB
A12, A13
Port mode
mode
1
1
1
Full-address
A14, A15
mode
Other than above
Setting prohibited
Note When the CPU accesses the external memory expansion area, the lower bits of the address to be
accessed are output to the specified pins (except in the full-address mode).
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Figure 5-3. Pins Specified for Address (When Flash Memory Is 24 KB, Internal Expansion RAM Is 0 Bytes)
External
Expansion
Mode
256-byte
expansion
mode
4 KB
expansion
mode
16 KB
expansion
mode
Full-address
mode
Remark
Address
Accessed
by CPU
Pins Specified for Address
A15
A14
A13
A12
A11
A10
A9
A8
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
6000H
(0)
(1)
(1)
(0)
(0)
(0)
(0)
(0)
0
0
0
0
0
0
0
0
6001H
(0)
(1)
(1)
(0)
(0)
(0)
(0)
(0)
0
0
0
0
0
0
0
1
6055H
(0)
(1)
(1)
(0)
(0)
(0)
(0)
(0)
0
1
0
1
0
1
0
1
60FEH
(0)
(1)
(1)
(0)
(0)
(0)
(0)
(0)
1
1
1
1
1
1
1
0
60FFH
(0)
(1)
(1)
(0)
(0)
(0)
(0)
(0)
1
1
1
1
1
1
1
1
6000H
(0)
(1)
(1)
(0)
0
0
0
0
0
0
0
0
0
0
0
0
6001H
(0)
(1)
(1)
(0)
0
0
0
0
0
0
0
0
0
0
0
1
6100H
(0)
(1)
(1)
(0)
0
0
0
1
0
0
0
0
0
0
0
0
6FFFH
(0)
(1)
(1)
(0)
1
1
1
1
1
1
1
1
1
1
1
1
6000H
(0)
(1)
1
0
0
0
0
0
0
0
0
0
0
0
0
0
7000H
(0)
(1)
1
1
0
0
0
0
0
0
0
0
0
0
0
0
8000H
(1)
(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9000H
(1)
(0)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
9FFFH
(1)
(0)
0
1
1
1
1
1
1
1
1
1
1
1
1
1
6000H
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
6001H
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
F7FFH
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
The value in ( ) is not actually output. This pin can be used as a port pin.
(2) Memory expansion wait setting register (MM)
MM sets the number of waits.
MM is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets MM to 10H.
Figure 5-4. Format of Memory Expansion Wait Setting Register (MM)
Address: FFF8H
After reset: 10H
R/W
Symbol
7
6
5
4
3
2
1
0
MM
0
0
PW1
PW0
0
0
0
0
PW1
PW0
0
0
No wait
0
1
Wait (one wait state inserted)
1
0
Setting prohibited
1
1
Wait control by external wait pin
Wait control
Cautions 1. To control wait with external wait pin, be sure to set WAIT/P66 pin to input mode
(set bit 6 (PM66) of port mode register 6 (PM6) to 1).
2. If the external wait pin is not used for wait control, the WAIT/P66 pin can be used
as an I/O port pin.
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CHAPTER 5 EXTERNAL BUS INTERFACE
5.3
External Bus Interface Function Timing
Timing control signal output pins in the external memory expansion mode are as follows.
(1) RD pin (Alternate function: P64)
Read strobe signal output pin. The read strobe signal is output in data read and instruction fetch from external
memory.
During internal memory read, the read strobe signal is not output (maintains high level).
(2) WR pin (Alternate function: P65)
Write strobe signal output pin. The write strobe signal is output in data write to external memory.
During internal memory write, the write strobe signal is not output (maintains high level).
(3) WAIT pin (Alternate function: P66)
External wait signal input pin.
When the external wait is not used, the WAIT pin can be used as an I/O port.
During internal memory access, the external wait signal is ignored.
(4) ASTB pin (Alternate function: P67)
Address strobe signal output pin.
The address strobe signal is output regardless of data access and
instruction fetch from external memory.
During internal memory access, the address strobe signal is output.
(5) AD0 to AD7, A8 to A15 pins (Alternate function: P40 to P47, P50 to P57)
Address/data signal output pins. Valid signal is output or input during data accesses and instruction fetches
from external memory.
These signals change even during internal memory access (output values are undefined).
The timing charts are shown in Figures 5-5 to 5-8.
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CHAPTER 5 EXTERNAL BUS INTERFACE
Figure 5-5. Instruction Fetch from External Memory
(a) No wait (PW1, PW0 = 0, 0) setting
ASTB
RD
AD0 to AD7
Lower address
Instruction code
Higher address
A8 to A15
(b) Wait (PW1, PW0 = 0, 1) setting
ASTB
RD
AD0 to AD7
Lower address
Instruction code
Higher address
A8 to A15
Internal wait signal
(1-clock wait)
(c) External wait (PW1, PW0 = 1, 1) setting
ASTB
RD
AD0 to AD7
A8 to A15
Lower address
Instruction code
Higher address
WAIT
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CHAPTER 5 EXTERNAL BUS INTERFACE
Figure 5-6. External Memory Read Timing
(a) No wait (PW1, PW0 = 0, 0) setting
ASTB
RD
AD0 to AD7
Lower address
Read data
Higher address
A8 to A15
(b) Wait (PW1, PW0 = 0, 1) setting
ASTB
RD
AD0 to AD7
Lower address
A8 to A15
Read data
Higher address
Internal wait signal
(1-clock wait)
(c) External wait (PW1, PW0 = 1, 1) setting
ASTB
RD
AD0 to AD7
A8 to A15
Lower address
Read data
Higher address
WAIT
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CHAPTER 5 EXTERNAL BUS INTERFACE
Figure 5-7. External Memory Write Timing
(a) No wait (PW1, PW0 = 0, 0) setting
ASTB
WR
AD0 to AD7
Hi-Z
Lower address
Write data
Higher address
A8 to A15
(b) Wait (PW1, PW0 = 0, 1) setting
ASTB
WR
AD0 to AD7
Lower
address
Hi-Z
Write data
Higher address
A8 to A15
Internal wait signal
(1-clock wait)
(c) External wait (PW1, PW0 = 1, 1) setting
ASTB
WR
AD0 to AD7
A8 to A15
Lower
address
Hi-Z
Write data
Higher address
WAIT
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CHAPTER 5 EXTERNAL BUS INTERFACE
Figure 5-8. External Memory Read Modify Write Timing
(a) No wait (PW1, PW0 = 0, 0) setting
ASTB
RD
WR
AD0 to AD7
Lower
address
Hi-Z
Read data
Write data
Higher address
A8 to A15
(b) Wait (PW1, PW0 = 0, 1) setting
ASTB
RD
WR
AD0 to AD7
Lower
address
Hi-Z
Read data
A8 to A15
Write data
Higher address
Internal wait signal
(1-clock wait)
(c) External wait (PW1, PW0 = 1, 1) setting
ASTB
RD
WR
AD0 to AD7
A8 to A15
Lower
address
Hi-Z
Read data
Write data
Higher address
WAIT
Remark
118
The read-modify-write timing is that of an operation when a bit manipulation instruction is executed.
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CHAPTER 5 EXTERNAL BUS INTERFACE
5.4
Example of Connection with Memory
An example of connecting the 78K0/KF1+ with external memory when the flash memory is 32 KB and the internal
expansion RAM is 0 bytes (in this example, SRAM) is shown in Figure 5-9. In addition, the external bus interface
function is used in the full-address mode, and the addresses from 0000H to 7FFFH (32 KB) are allocated to internal
ROM, and the addresses after 8000H to SRAM.
Figure 5-9. Connection Example of 78K0/KF1+ and Memory When Flash Memory Is 32 KB and Internal
Expansion RAM Is 0 Bytes
VDD
μ PD43256B
78K0/KF1+
CS
RD
OE
WR
WE
I/O1 to I/O8
Data bus
Address bus
A8 to A14
ASTB
A0 to A14
74HC573
LE
Q0 to Q7
AD0 to AD7
D0 to D7
OE
`
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CHAPTER 6 CLOCK GENERATOR
6.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three system clock oscillators are available.
• High-speed system clock oscillator
The high-speed system clock oscillator oscillates a clock of fXP = 2.0 to 16.0 MHz. Oscillation can be stopped
by executing the STOP instruction or setting the main OSC control register (MOC) and processor clock control
register (PCC).
• Internal oscillator
The internal oscillator oscillates a clock of fR = 240 kHz (TYP.). Oscillation can be stopped by setting the
internal oscillation mode register (RCM) when “Can be stopped by software” is set by the option byte and the
high-speed system clock is used as the CPU clock.
• Subsystem clock oscillator
The subsystem clock oscillator oscillates a clock of fXT = 32.768 kHz. Oscillation cannot be stopped. When
subsystem clock oscillator is not used, setting not to use the on-chip feedback resistor is possible using the
processor clock control register (PCC), and the operating current can be reduced in the STOP mode.
Remarks 1. fXP: High-speed system clock oscillation frequency
2. fR:
Internal oscillation clock frequency
3. fXT: Subsystem clock oscillation frequency
6.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 6-1. Configuration of Clock Generator
Item
120
Configuration
Control registers
Processor clock control register (PCC)
Internal oscillation mode register (RCM)
Main clock mode register (MCM)
Main OSC control register (MOC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Oscillators
High-speed system clock oscillator
Internal oscillator
Subsystem clock oscillator
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CHAPTER 6 CLOCK GENERATOR
Figure 6-1. Block Diagram of Clock Generator
Internal bus
Main OSC
control
register
(MOC)
MCC CLS
Oscillation
stabilization time
select register
(OSTS)
Main clock
mode register
(MCM)
OSTS2 OSTS1 OSTS0
MCS MCM0
MSTOP
Processor clock
control register
(PCC)
CLS CSS PCC2 PCC1 PCC0
3
4
Oscillation stabilization
time counter
STOP
Controller
Oscillation
stabilization
MOST MOST MOST MOST MOST time counter
11 13 14
15 16 status
register
(OSTC)
X1
X2
High-speed
system clock
oscillator
fXP
fX
C
P
U
CPU clock
(fCPU)
Prescaler
Operation
clock switch
fX
22
fX
23
fX
24
fCPU
Selector
fX
2
Internal
oscillator
Control signal
fR
Watch clock,
clock output
function
Prescaler
Clock to peripheral
hardware
Option byte (LSROSC)
1: Cannot be stopped
0: Can be stopped
Prescaler
1/2
fXT
Subsystem
clock oscillator
XT1
XT2
FRC
8-bit timer H1,
watchdog timer
RSTOP
Internal oscillation mode
register (RCM)
Internal bus
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CHAPTER 6 CLOCK GENERATOR
6.3 Registers Controlling Clock Generator
The following six registers are used to control the clock generator.
• Processor clock control register (PCC)
• Internal oscillation mode register (RCM)
• Main clock mode register (MCM)
• Main OSC control register (MOC)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
(1) Processor clock control register (PCC)
The PCC register is used to select the CPU clock, the division ratio, main system clock oscillator operation/stop
and whether to use the on-chip feedback resistorNote of the subsystem clock oscillator.
The PCC is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PCC to 00H.
Note The feedback resistor is required to control the bias point of the oscillation waveform so that the bias point
is in the middle of the power supply voltage (see Figure 6-11 Subsystem Clock Feedback Resistor).
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Figure 6-2. Format of Processor Clock Control Register (PCC)
Address: FFFBH
After reset: 00H
R/W
Note 1
Symbol
3
2
1
0
PCC
MCC
FRC
CLS
CSS
0
PCC2
PCC1
PCC0
MCC
Control of high-speed system clock oscillator operation
0
Oscillation possible
1
Oscillation stopped
FRC
Subsystem clock feedback resistor selection
0
On-chip feedback resistor used
1
On-chip feedback resistor not used
CLS
High-speed system clock or internal oscillation clock
1
Subsystem clock
Note 4
Note 3
CPU clock status
0
CSS
Note 2
PCC2
PCC1
PCC0
CPU clock (fCPU) selection
MCM0 = 0
0
0
0
1
0
0
0
1
2.
fR
fX/2
fR/2
fXP
Note 5
fXP/2
0
1
0
fX/2
2
0
1
1
fX/2
3
Setting prohibited fXP/2
3
1
0
0
fX/2
4
Setting prohibited fXP/2
4
0
0
0
fXT/2
0
0
1
0
1
0
0
1
1
1
0
0
Other than above
Notes 1.
fX
MCM0 = 1
Setting prohibited fXP/2
2
Setting prohibited
Bit 5 is read-only.
When the CPU is operating on the subsystem clock, MCC should be used to stop the high-speed
system clock oscillator operation. When the CPU is operating on the internal oscillation clock, use bit 7
(MSTOP) of the main OSC control register (MOC) to stop the high-speed system clock oscillator
operation (this cannot be set by MCC). A STOP instruction should not be used.
3.
Clear this bit to 0 when the subsystem clock is used, and set it to 1 when the subsystem clock is not
used.
4.
Be sure to switch CSS from 1 to 0 when bits 1 (MCS) and 0 (MCM0) of the main clock mode register
(MCM) are 1.
5.
Setting is prohibited for the (A1) grade products.
Caution Be sure to clear bit 3 to 0.
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Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM)
2. fX: Main system clock oscillation frequency (high-speed system clock oscillation frequency or
internal oscillation clock frequency)
3. fR: Internal oscillation clock frequency
4. fXP: High-speed system clock oscillation frequency
5. fXT: Subsystem clock oscillation frequency
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KF1+.
Therefore, the
relationship between the CPU clock (fCPU) and minimum instruction execution time is as shown in the Table 6-2.
Table 6-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU)
Minimum Instruction Execution Time: 2/fCPU
High-Speed System Clock
Note 1
Internal Oscillation
Subsystem Clock
Note 1
Clock
At 10 MHz Operation
At 16 MHz Operation
At 240 kHz (TYP.)
At 32.768 kHz
Operation
Operation
fX
0.2 μs
0.125 μs
8.3 μs (TYP.)
fX/2
0.4 μs
0.25 μs
16.6 μs (TYP.)
−
fX/2
2
0.8 μs
0.5 μs
Setting prohibited
−
fX/2
3
1.6 μs
1.0 μs
Setting prohibited
−
fX/2
4
3.2 μs
2.0 μs
Setting prohibited
−
−
fXT/2
−
Note 2
122.1 μs
−
Notes 1. The main clock mode register (MCM) is used to set the CPU clock (high-speed system clock/internal
oscillation clock) (see Figure 6-4).
2. Setting is prohibited for the (A1) grade products.
(2) Internal oscillation mode register (RCM)
This register sets the operation mode of the internal oscillator.
This register is valid when “Can be stopped by software” is set for the internal oscillator by the option byte, and
the high-speed system clock or subsystem clock is selected as the CPU clock. If “Cannot be stopped” is selected
for the internal oscillator by the option byte, settings for this register are invalid.
RCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 6-3. Format of Internal Oscillation Mode Register (RCM)
Address: FFA0H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
RCM
0
0
0
0
0
0
0
RSTOP
RSTOP
Internal oscillator oscillating/stopped
0
Internal oscillator oscillating
1
Internal oscillator stopped
Caution Make sure that the bit 1 (MCS) of the main clock mode register (MCM) is 1 before
setting RSTOP.
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(3) Main clock mode register (MCM)
This register sets the CPU clock (high-speed system clock/internal oscillation clock).
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 6-4. Format of Main Clock Mode Register (MCM)
Address: FFA1H
After reset: 00H
R/W
Note
Symbol
7
6
5
4
3
2
MCM
0
0
0
0
0
0
MCS
MCM0
MCS
CPU clock status
0
Operates with internal oscillation clock
1
Operates with high-speed system clock
MCM0
Selection of clock supplied to CPU
0
Internal oscillation clock
1
High-speed system clock
Note Bit 1 is read-only.
Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the divided clock of the internal oscillator output (fX) is supplied to the
peripheral hardware (fX = 240 kHz (TYP.)).
Operation of the peripheral hardware with the internal oscillation clock cannot
be guaranteed. Therefore, when the internal oscillation clock is selected as the
clock supplied to the CPU, do not use peripheral hardware. In addition, stop the
peripheral hardware before switching the clock supplied to the CPU from the
high-speed system clock to the internal oscillation clock. Note, however, that
the following peripheral hardware can be used when the CPU operates on the
internal oscillation clock.
• Watchdog timer
• Clock monitor
• 8-bit timer H1 when fR/27 is selected as count clock
• Peripheral hardware selecting external clock as the clock source
(Except when external count clock of TM0n (n = 0, 1) is selected (TI00n valid
edge))
2. Set MCS = 1 and MCM0 = 1 before switching subsystem clock operation to highspeed system clock operation (bit 4 (CSS) of the processor clock control
register (PCC) is changed from 1 to 0).
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(4) Main OSC control register (MOC)
This register selects the operation mode of the high-speed system clock.
This register is used to stop the high-speed system clock oscillator operation when the CPU is operating with the
internal oscillation clock.
Therefore, this register is valid only when the CPU is operating with the internal
oscillation clock.
MOC can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 6-5. Format of Main OSC Control Register (MOC)
Address: FFA2H
After reset: 00H
R/W
Symbol
6
5
4
3
2
1
0
MOC
MSTOP
0
0
0
0
0
0
0
MSTOP
Control of high-speed system clock oscillator operation
0
High-speed system clock oscillator operating
1
High-speed system clock oscillator stopped
Cautions 1. Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before
setting MSTOP.
2. To stop high-speed system clock oscillation when the CPU is operating on the
subsystem clock, set bit 7 (MCC) of the processor clock control register (PCC) to
1 (setting by MSTOP is not possible).
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(5) Oscillation stabilization time counter status register (OSTC)
This is the status register of the high-speed system clock oscillation stabilization time counter. If the internal
oscillation clock is used as the CPU clock, the high-speed system clock oscillation stabilization time can be
checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction,
MSTOP = 1, and MCC = 1 clear OSTC to 00H.
Figure 6-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H
After reset: 00H
R
Symbol
7
6
5
4
3
2
1
0
OSTC
0
0
0
MOST11
MOST13
MOST14
MOST15
MOST16
MOST11
MOST13
MOST14
MOST15
MOST16
Oscillation stabilization time status
fXP = 10 MHz fXP = 16 MHz
1
1
1
0
0
1
0
0
1
0
0
1
0
0
0
11
204.8 μs min. 128 μs min.
13
819.2 μs min. 512 μs min.
14
1.64 ms min. 1.02 ms min.
15
3.27 ms min. 2.04 ms min.
16
6.55 ms min. 4.09 ms min.
2 /fXP min.
2 /fXP min.
2 /fXP min.
1
1
1
1
0
2 /fXP min.
1
1
1
1
1
2 /fXP min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
2. If the STOP mode is entered and then released while the internal oscillation
clock is being used as the CPU clock, set the oscillation stabilization time as
follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
3. The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether
STOP mode is released by RESET input or interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
Remark
fXP: High-speed system clock oscillation frequency
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(6) Oscillation stabilization time select register (OSTS)
This register is used to select the high-speed system clock oscillation stabilization wait time when STOP mode is
released.
The wait time set by OSTS is valid only after STOP mode is released with the high-speed system clock selected
as CPU clock. After STOP mode is released with the internal oscillation clock selected as the CPU clock, the
oscillation stabilization time must be confirmed by OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 05H.
Figure 6-7. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H
After reset: 05H
R/W
Symbol
7
6
5
4
3
2
1
0
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Oscillation stabilization time selection
fXP = 10 MHz
0
0
0
1
1
0
1
1
1
819.2 μs
512 μs
14
1.64 ms
1.02 ms
15
3.27 ms
2.04 ms
16
6.55 ms
4.09 ms
2 /fXP
0
0
128 μs
2 /fXP
1
0
204.8 μs
13
2 /fXP
0
2 /fXP
1
2 /fXP
Other than above
fXP = 16 MHz
11
Setting prohibited
Cautions 1. To set the STOP mode when the high-speed system clock is used as the CPU
clock, set OSTS before executing a STOP instruction.
2. Before setting OSTS, confirm with OSTC that the desired oscillation stabilization
time has elapsed.
3. If the STOP mode is entered and then released while the internal oscillation
clock is being used as the CPU clock, set the oscillation stabilization time as
follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
4. The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether
STOP mode is released by RESET input or interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
Remark
128
fXP: High-speed system clock oscillation frequency
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6.4 System Clock Oscillator
6.4.1 High-speed system clock oscillator
The high-speed system clock oscillator oscillates with a crystal resonator or ceramic resonator connected to the X1
and X2 pins.
An external clock can be input to the high-speed system clock oscillator. In this case, input the clock signal to the
X1 pin and input the inverse signal to the X2 pin.
Figure 6-8 shows examples of the external circuit of the high-speed system clock oscillator.
Figure 6-8. Examples of External Circuit of High-Speed System Clock Oscillator
(a) Crystal, ceramic oscillation
VSS
X1
(b) External clock
External
clock
X1
X2
Crystal resonator or
ceramic resonator
X2
Cautions are listed on the next page.
6.4.2 Subsystem clock oscillator
The subsystem clock oscillator oscillates with a crystal resonator (Standard: 32.768 kHz) connected to the XT1
and XT2 pins.
External clocks can be input to the subsystem clock oscillator. In this case, input the clock signal to the XT1 pin
and the inverse signal to the XT2 pin.
Figure 6-9 shows examples of an external circuit of the subsystem clock oscillator.
Figure 6-9. Examples of External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation
(b) External clock
VSS
XT1
External
clock
XT1
32.768
kHz
XT2
XT2
Cautions are listed on the next page.
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Caution When using the high-speed system clock oscillator and subsystem clock oscillator, wire as
follows in the area enclosed by the broken lines in the Figures 6-8 and 6-9 to avoid an adverse
effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing
power consumption.
Figure 6-10 shows examples of incorrect resonator connection.
Figure 6-10. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
PORT
VSS
Remark
X1
X2
VSS
X2
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
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Figure 6-10. Examples of Incorrect Resonator Connection (2/2)
(c) Wiring near high alternating current
(d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
VDD
Pmn
X1
X2
VSS
High current
VSS
A
X1
B
X2
C
High current
(e) Signals are fetched
VSS
Remark
X1
X2
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
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6.4.3 When subsystem clock is not used
If it is not necessary to use the subsystem clock for low power consumption operations and watch operations,
connect the XT1 and XT2 pins as follows.
XT1: Connect directly to EVSS or VSSNote
XT2: Leave open
Note When the subsystem clock is not used, the on-chip feedback resistor must be set after a reset is released
so that it is not used (bit 6 (FRC) of processor clock control register (PCC) = 1).
Figure 6-11. Subsystem Clock Feedback Resistor
FRC
P-ch
Feedback resistor
XT1
Remark
XT2
The feedback resistor is required to control the bias point of the oscillation waveform so that the bias
point is in the middle of the power supply voltage.
6.4.4 Internal oscillator
An internal oscillator is incorporated in the 78K0/KF1+.
“Can be stopped by software” or “Cannot be stopped” can be selected using the option byte. The internal oscillator
always oscillates the internal oscillation clock after RESET release (240 kHz (TYP.)).
6.4.5 Prescaler
The prescaler generates various clocks by dividing the high-speed system clock oscillator output when the highspeed system clock is selected as the clock to be supplied to the CPU.
Caution When the internal oscillation clock is selected as the clock supplied to the CPU, the prescaler
generates various clocks by dividing the internal oscillator output (fX = 240 kHz (TYP.)).
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6.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
mode.
• High-speed system clock fXP
• Internal oscillation clock fR
• Subsystem clock fXT
• CPU clock fCPU
• Clock to peripheral hardware
The CPU starts operation when the internal oscillator starts outputting after reset release in the 78K0/KF1+, thus
enabling the following.
(1) Enhancement of security function
When the high-speed system clock is set as the CPU clock by the default setting, the device cannot operate if the
high-speed system clock is damaged or badly connected and therefore does not operate after reset is released.
However, the start clock of the CPU is the internal oscillation clock, so the device can be started by the internal
oscillation clock after reset release by the clock monitor (detection of high-speed system clock stop).
Consequently, the system can be safely shut down by performing a minimum operation, such as acknowledging a
reset source by software or performing safety processing when there is a malfunction.
(2) Improvement of performance
Because the CPU can be started without waiting for the high-speed system clock oscillation stabilization time, the
total performance can be improved.
A timing diagram of the CPU default start using the internal oscillator is shown in Figure 6-12.
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Figure 6-12. Timing Diagram of CPU Default Start Using Internal Oscillator
High-speed system clock
(fXP)
Internal oscillation clock
(fR)
Subsystem clock
(fXT)
RESET
Switched by software
Internal oscillation clock
CPU clock
High-speed system clock
Operation
stopped: 17/fR
High-speed system clock oscillation stabilization time:
211/fXP to 216/fXPNote
Note Check using the oscillation stabilization time counter status register (OSTC).
(a) When the RESET signal is generated, bit 0 (MCM0) of the main clock mode register (MCM) is set to 0 and
the internal oscillation clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks
of the internal oscillation clock have elapsed after RESET release (or clock supply to the CPU stops for 17
clocks). During the RESET period, oscillation of the high-speed system clock and the internal oscillation
clock is stopped.
(b) After RESET release, the CPU clock can be switched from the internal oscillation clock to the high-speed
system clock using bit 0 (MCM0) of the main clock mode register (MCM) after the high-speed system clock
oscillation stabilization time has elapsed. At this time, check the oscillation stabilization time using the
oscillation stabilization time counter status register (OSTC) before switching the CPU clock. The CPU clock
status can be checked using bit 1 (MCS) of MCM.
(c) The internal oscillator can be set to stopped/oscillating using the internal oscillation mode register (RCM)
when “Can be stopped by software” is selected for the internal oscillator by the option byte, if the high-speed
system or subsystem clock is used as the CPU clock. Make sure that MCS is 1 at this time.
(d) When the internal oscillation clock is used as the CPU clock, the high-speed system clock can be set to
stopped/oscillating using the main OSC control register (MOC). Make sure that MCS is 0 at this time.
When the subsystem clock is used as the CPU clock, whether the high-speed system clock stops or
oscillates can be set by the processor clock control register (PCC). In addition, HALT mode can be used
during operation with the subsystem clock, but STOP mode cannot be used (subsystem clock oscillation
cannot be stopped by the STOP instruction).
(e) Select the high-speed system clock oscillation stabilization time (211/fXP, 213/fXP, 214/fXP, 215/fXP, 216/fXP) using
the oscillation stabilization time select register (OSTS) when releasing STOP mode while high-speed system
clock is being used as the CPU clock. In addition, when releasing STOP mode while RESET is released and
the internal oscillation clock is being used as the CPU clock, check the high-speed system clock oscillation
stabilization time using the oscillation stabilization time counter status register (OSTC).
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A status transition diagram of this product is shown in Figure 6-13, and the relationship between the operation
clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown
in Tables 6-3 and 6-4, respectively.
Figure 6-13. Status Transition Diagram (1/4)
(1) When “Internal oscillator can be stopped by software” is selected by option byte
(when subsystem clock is not used)
HALTNote 4
HALT instruction
Interrupt
Interrupt
HALT
instruction
HALT
instruction
Status 4
RSTOP = 0
CPU clock: fXP
fXP: Oscillating
fR: Oscillation stopped
RSTOP = 1Note 1
Status 3
CPU clock: fXP
fXP: Oscillating
fR: Oscillating
Interrupt
Interrupt
STOP
instruction
MCM0 = 0
MCM0 = 1Note 2
Interrupt
STOP
instruction
HALT
instruction
Interrupt
MSTOP = 1Note 3
Status 1
CPU clock: fR
fXP: Oscillation stopped
fR: Oscillating
MSTOP = 0
Status 2
CPU clock: fR
fXP: Oscillating
fR: Oscillating
STOP
instruction
Interrupt
Interrupt
STOP
instruction
STOPNote 4
Reset release
ResetNote 5
Notes 1.
When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
2.
Before shifting from status 2 to status 3 after reset and STOP are released, check the high-speed
(MCM) is 1.
system clock oscillation stabilization time status using the oscillation stabilization time counter status
register (OSTC).
3.
When shifting from status 2 to status 1, make sure that MCS is 0.
4.
When “Internal oscillator can be stopped by software” is selected by the option byte, the watchdog
timer stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog
timer. However, oscillation of the internal oscillator does not stop even in the HALT and STOP
modes if RSTOP = 0.
5.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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CHAPTER 6 CLOCK GENERATOR
Figure 6-13. Status Transition Diagram (2/4)
(2) When “Internal oscillator can be stopped by software” is selected by option byte
(when subsystem clock is used)
Status 6
CPU clock: fXT
fXP: Oscillation
stopped
fR: Oscillating/
oscillation
stopped
Interrupt
MCC = 0
MCC = 1
HALT
instruction
Status 5
CPU clock: fXT
fXP: Oscillating
fR: Oscillating/
oscillation
stopped
Interrupt
HALTNote 4
HALT
instruction
HALT
instruction Interrupt
HALT
instruction Interrupt
CSS = 0Note 5
CSS = 1Note 5
Status 4
Status 3
CPU clock: fXP RSTOP = 0
CPU clock: fXP
fXP: Oscillating
fXP: Oscillating
fR: Oscillation RSTOP = 1Note 1 fR: Oscillating
stopped
HALT
instruction
Interrupt
Status 1
Status
2
MCM0 = 0
MSTOP = 1Note 3 CPU clock: fR
CPU clock: fR
fXP: Oscillation
fXP: Oscillating
stopped
MCM0 = 1Note 2 fR: Oscillating
MSTOP = 0
fR: Oscillating
STOP
STOP
instruction
instruction
Interrupt
Interrupt
STOP
instruction
Interrupt
STOPNote 4
Reset release
ResetNote 6
Notes 1.
When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
2.
Before shifting from status 2 to status 3 after reset and STOP are released, check the high-speed
system clock oscillation stabilization time status using the oscillation stabilization time counter status
register (OSTC).
3.
4.
When shifting from status 2 to status 1, make sure that MCS is 0.
When “Internal oscillator can be stopped by software” is selected by the option byte, the clock supply
to the watchdog timer is stopped after the HALT or STOP instruction has been executed, regardless
of the setting of bit 0 (RSTOP) of the internal oscillation mode register (RCM) and bit 0 (MCM0) of the
main clock mode register (MCM).
5.
The operation cannot be shifted between subsystem clock operation and internal oscillation clock
operation.
6.
136
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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Figure 6-13. Status Transition Diagram (3/4)
(3) When “Internal oscillator cannot be stopped” is selected by option byte
(when subsystem clock is not used)
HALT
Interrupt
Interrupt
HALT
instruction
Status 3
CPU clock: fXP
fXP: Oscillating
fR: Oscillating
MCM0 = 0
MCM0 = 1Note 1
Status 2
CPU clock: fR
fXP: Oscillating
fR: Oscillating
HALT instruction
MSTOP = 1Note 2
MSTOP = 0
Status 1
CPU clock: fR
fXP: Oscillation stopped
fR: Oscillating
STOP
instruction
Interrupt
STOP
instruction
HALT
instruction
Interrupt
STOP
instruction
Interrupt
STOPNote 3
Interrupt
Reset release
ResetNote 4
Notes 1.
Before shifting from status 2 to status 3 after reset and STOP are released, check the high-speed
system clock oscillation stabilization time status using the oscillation stabilization time counter status
register (OSTC).
2.
When shifting from status 2 to status 1, make sure that MCS is 0.
3.
The watchdog timer operates using the internal oscillation clock even in STOP mode if “Internal
oscillator cannot be stopped” is selected by the option byte. Internal oscillation clock division can be
selected as the count source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1
interrupt request before watchdog timer overflow. If this processing is not performed, an internal
reset signal is generated at watchdog timer overflow after STOP instruction execution.
4.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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Figure 6-13. Status Transition Diagram (4/4)
(4) When “Internal oscillator cannot be stopped” is selected by option byte
(when subsystem clock is used)
Status 5
CPU clock: fXT
fXP: Oscillation stopped
fR: Oscillating
Interrupt
MCC = 0
MCC = 1
HALT instruction
Status 4
CPU clock: fXT
fXP: Oscillating
fR: Oscillating
Interrupt
HALT
HALT instruction
Interrupt
CSS = 0Note 5
Interrupt
HALT
instruction
CSS = 1Note 4
Status 3
CPU clock: fXP
fXP: Oscillating
fR: Oscillating
MCM0 = 0
MCM0 = 1Note 1
Interrupt
Status 2
CPU clock: fR
fXP: Oscillating
fR: Oscillating
MSTOP = 1Note 2
MSTOP = 0
Status 1
CPU clock: fR
fXP: Oscillation stopped
fR: Oscillating
STOP
instruction
Interrupt
STOP
instruction
HALT instruction
HALT
instruction
STOP
instruction
Interrupt
STOPNote 3
Interrupt
Reset release
ResetNote 5
Notes 1.
Before shifting from status 2 to status 3 after reset and STOP are released, check the high-speed
system clock oscillation stabilization time status using the oscillation stabilization time counter status
register (OSTC).
2.
When shifting from status 2 to status 1, make sure that MCS is 0.
3.
The watchdog timer operates using the internal oscillation clock even in STOP mode if “Internal
oscillator cannot be stopped” is selected by the option byte. Internal oscillation clock division can be
selected as the count source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1
interrupt request before watchdog timer overflow. If this processing is not performed, an internal
reset signal is generated at watchdog timer overflow after STOP instruction execution.
4.
The operation cannot be shifted between subsystem clock operation and the internal oscillation clock
operation.
5.
138
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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Table 6-3. Relationship Between Operation Clocks in Each Operation Status
Status
High-Speed System
Internal Oscillator
Subsystem CPU Clock
Clock
After
Oscillator
Release
Clock Oscillator
MSTOP = 0 MSTOP = 1
Operation
MCC = 0
Mode
Reset
Note 1
MCC = 1
Note 2
RSTOP = 0 RSTOP = 1
Stopped
Stopped
MCM0 = 0 MCM0 = 1
Oscillating Internal
oscillation
Oscillating Oscillating Stopped
STOP
HALT
Oscillating
Prescaler Clock
Supplied to Peripherals
Stopped
Stopped
Note 3
Stopped
Note 4
Internal
High-
oscillation
speed
system
clock
Notes 1.
When “Cannot be stopped” is selected for the internal oscillator by the option byte.
2.
When “Can be stopped by software” is selected for the internal oscillator by the option byte.
3.
Operates using the CPU clock at STOP instruction execution.
4.
Operates using the CPU clock at HALT instruction execution.
Caution The RSTOP setting is valid only when “Can be stopped by software” is set for the internal oscillator
by the option byte.
Remark
MSTOP: Bit 7 of the main OSC control register (MOC)
MCC:
Bit 7 of the processor clock control register (PCC)
RSTOP: Bit 0 of the internal oscillation mode register (RCM)
MCM0:
Bit 0 of the main clock mode register (MCM)
Table 6-4. Oscillation Control Flags and Clock Oscillation Status
High-Speed System Clock Oscillator
MSTOP = 1
Note
MSTOP = 0
Note
RSTOP = 0
Stopped
RSTOP = 1
Setting prohibited
RSTOP = 0
Oscillating
RSTOP = 1
MCC = 1
Note
RSTOP = 0
Note
RSTOP = 0
Oscillating
Oscillating
Stopped
Stopped
RSTOP = 1
MCC = 0
Internal Oscillator
Oscillating
Stopped
Oscillating
RSTOP = 1
Oscillating
Stopped
Note Setting high-speed system clock oscillator oscillating/stopped differs depending on the CPU clock
used.
• When the internal oscillation clock is used as the CPU clock: Set using the MSTOP bit
• When the subsystem clock is used as the CPU clock: Set using the MCC bit
Caution The RSTOP setting is valid only when “Can be stopped by software” is set for the internal
oscillator by the option byte.
Remark
MSTOP: Bit 7 of the main OSC control register (MOC)
MCC:
Bit 7 of the processor clock control register (PCC)
RSTOP: Bit 0 of the internal oscillation mode register (RCM)
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6.6 Time Required to Switch Between Internal Oscillation Clock and High-Speed System Clock
Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the internal oscillation clock and
high-speed system clock.
In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions
are executed using the pre-switch clock after switching MCM0 (see Table 6-5).
Bit 1 (MCS) of MCM is used to judge that operation is performed using either the internal oscillation clock or highspeed system clock.
To stop the original clock after switching the clock, wait for the number of clocks shown in Table 6-5 before
stopping.
Table 6-5. Time Required to Switch Between Internal Oscillation Clock and High-Speed System Clock
PCC
PCC2
0
0
PCC1
0
0
Time Required for Switching
PCC0
0
1
High-Speed System Clock →
Internal Oscillation →
Internal Oscillation
High-Speed System Clock
fXP/fR + 1 clock
2 clocks
Note
fXP/2fR + 1 clock
Note
2 clocks
Note Setting is prohibited for the (A1) grade products.
Caution To calculate the maximum time, set fR = 120 kHz.
Remarks 1. PCC: Processor clock control register
2. fXP: High-speed system clock oscillation frequency
3. fR: Internal oscillation clock frequency
4. The maximum time is the number of clocks of the CPU clock before switching.
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6.7 Time Required for CPU Clock Switchover
The CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control
register (PCC).
The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on
the pre-switchover clock for several instructions (see Table 6-6).
Whether the system is operating on the high-speed system clock (or internal oscillation clock) or the subsystem
clock can be ascertained using bit 5 (CLS) of the PCC register.
Table 6-6. Maximum Time Required for CPU Clock Switchover
Set Value Before
Set Value After Switchover
Switchover
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
0
0
0
0
0
0
0
0
0
0
0
1
0
16 clocks
0
1
16 clocks
0
0
0
1
16 clocks
1
0
1
0
0
16 clocks
1
×
×
×
2fXP/fXT clocks
(977 clocks)
0
0
1
8 clocks
8 clocks
8 clocks
8 clocks
fXP/fXT clocks
(489 clocks)
0
1
0
4 clocks
4 clocks
4 clocks
4 clocks
fXP/2fXT clocks
(245 clocks)
0
1
1
2 clocks
2 clocks
2 clocks
1
0
0
1 clock
1 clock
1 clock
2 clocks
fXP/4fXT clocks
(123 clocks)
fXP/8fXT clocks
1 clock
(62 clocks)
1
×
×
×
2 clocks
2 clocks
2 clocks
2 clocks
2 clocks
Cautions 1. Selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover from the
high-speed system clock to the subsystem clock (changing CSS from 0 to 1) should not be
set simultaneously.
Simultaneous setting is possible, however, for selection of the CPU clock cycle division
factor (PCC0 to PCC2) and switchover from the subsystem clock to the high-speed system
clock (changing CSS from 1 to 0).
2. While the CPU is operating on internal oscillator, setting the following values is prohibited.
• CSS, PCC2, PCC1, PCC0 = 0, 0, 1, 0
• CSS, PCC2, PCC1, PCC0 = 0, 0, 1, 1
• CSS, PCC2, PCC1, PCC0 = 0, 1, 0, 0
Remarks 1. The maximum time is the number of clocks of the pre-switchover CPU clock.
2. Figures in parentheses apply to operation with fXP = 16 MHz and fXT = 32.768 kHz.
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6.8 Clock Switching Flowchart and Register Setting
6.8.1 Switching from internal oscillation clock to high-speed system clock
Figure 6-14. Switching from Internal Oscillation Clock to High-Speed System Clock (Flowchart)
After reset
PCC = 00H
RCM = 00H
MCM = 00H
MOC = 00H
OSTC = 00H
OSTS = 05HNote
Register value
after reset
; fCPU = fR
; Internal oscillation
; Internal oscillation clock operation
; High-speed system clock oscillation
; Oscillation stabilization time status register
; Oscillation stabilization time fXP/216
Each processing
OSTC checkNote
Internal oscillation
clock operation
High-speed system clock
oscillation stabilization
time has not elapsed
; High-speed system clock oscillation
stabilization time status check
High-speed system clock oscillation stabilization time has elapsed
PCC setting
Internal oscillation
clock operation
(dividing set PCC)
MCM.0 ← 1
MCM.1 (MCS) is changed from 0 to 1
High-speed system clock operation
High-speed system
clock operation
Note Check the oscillation stabilization wait time of the high-speed system clock oscillator after reset release
using the OSTC register and then switch to the high-speed system clock operation after the oscillation
stabilization wait time has elapsed. The OSTS register setting is valid only after STOP mode is released by
interrupt during high-speed system clock operation.
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6.8.2 Switching from high-speed system clock to internal oscillation clock
Figure 6-15. Switching from High-Speed System Clock to Internal Oscillation Clock (Flowchart)
Register setting
in high-speed system
clock operation
High-speed
system clock
operation
PCC.7 (MCC) = 0
PCC.4 (CSS) = 0
MCM = 03H
; High-speed system clock oscillation
; High-speed system clock or internal
oscillation clock
; High-speed system clock operation
Yes: RSTOP = 1
RCM.0Note
(RSTOP) = 1?
; Internal oscillator oscillating?
No: RSTOP = 0
RSTOP = 0
MCM.0 ← 0
; Internal oscillator oscillating
MCM.1 (MCS) is changed from 1 to 0
Internal oscillation
clock operation
Internal oscillation clock operation
Note Required only when “can be stopped by software” is selected for the internal oscillator by the option byte.
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6.8.3 Switching from high-speed system clock to subsystem clock
Figure 6-16. Switching from High-Speed System Clock to Subsystem Clock (Flowchart)
Register setting
in high-speed system
clock operation
PCC.7 (MCC) = 0
PCC.4 (CSS) = 0
MCM = 03H
; High-speed system clock oscillation
; High-speed system clock or internal
oscillation clock
; High-speed system clock operation
High-speed system
clock operation
CSS ← 1Note
; Subsystem clock operation
MCS = 1 not changed.
CLS is changed from 0 to 1.
Subsystem
clock
Subsystem clock operation
Note Set CSS to 1 after confirming that oscillation of the subsystem clock is stabilized.
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6.8.4 Switching from subsystem clock to high-speed system clock
Figure 6-17. Switching from Subsystem Clock to High-Speed System Clock (Flowchart)
PCC.4 (CSS) = 1
MCM = 03H
; Subsystem clock operation
No: High-speed system
clock oscillating
MCC = 1?
; High-speed system clock oscillating?
Yes: High-speed system clock oscillation stopped
MCC ← 0
; High-speed system clock oscillation enabled
OSTC check
; Wait for high-speed system clock oscillation
stabilization time
Subsystem
clock operation
High-speed system
clock oscillation
stabilization time
not elapsed
High-speed system clock oscillation stabilization time elapsed
CSS ← 0
; High-speed system clock operation
CLS is changed from 1 to 0.
MCS = 1 not changed.
High-speed system
cock operation
High-speed system clock operation
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6.8.5 Register settings
The table below shows the statuses of the setting flags and status flags when each mode is set.
Table 6-7. Clock and Register Setting
fCPU
Mode
Setting Flag
PCC Register
MCM
Status Flag
MOC
RCM
PCC
MCM
Register Register Register Register Register
High-speed system
MCC
CSS
MCM0
Note 1
MSTOP RSTOP
CLS
MCS
Internal oscillation clock oscillating
0
0
1
0
0
0
1
clock
Internal oscillation clock stopped
0
0
1
0
1
0
1
Internal oscillation
High-speed system clock
0
0
0
0
0
0
0
clock
oscillating
Note 2
High-speed system clock stopped
Subsystem clock
Note 4
High-speed system clock
0
Note 3
0
0
0
0
1
0
1
Note 5
0
0
Note 6
1
0
1
1
1
1
1
Note 5
0
Note 6
0
1
1
0
1
1
Note 5
0
Note 6
1
1
1
1
1
1
Note 5
0
Note 6
1
1
1
oscillating, internal oscillation clock
oscillating
High-speed system clock stopped,
internal oscillation clock oscillating
High-speed system clock
oscillating, internal oscillation clock
stopped
High-speed system clock stopped,
internal oscillation clock stopped
Notes 1.
Valid only when “can be stopped by software” is selected for the internal oscillator by the option byte.
2.
Do not set MCC = 1 or MSTOP = 1 during high-speed system clock operation (even if MCC = 1 or
3.
Do not set MCC = 1 during internal oscillation clock operation (even if MCC = 1 is set, the high-speed
MSTOP = 1 is set, the high-speed system clock oscillation does not stop).
system clock oscillation does not stop).
To stop high-speed system clock oscillation during internal
oscillation clock operation, use MSTOP.
4.
Shifting to subsystem clock operation mode must be performed from the high-speed system clock
operation mode. From subsystem clock operation mode, only high-speed system clock operation mode
can be shifted to.
5.
6.
Do not set MCM0 = 0 (shifting to internal oscillation clock) during subsystem clock operation.
Do not set MSTOP = 1 during subsystem clock operation (even if MSTOP = 1 is set, high-speed system
clock oscillation does not stop). To stop high-speed system clock oscillation during subsystem clock
operation, use MCC.
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7.1 Functions of 16-Bit Timer/Event Counters 00 and 01
16-bit timer/event counters 00 and 01 have the following functions.
• Interval timer
• PPG output
• Pulse width measurement
• External event counter
• Square-wave output
• One-shot pulse output
(1) Interval timer
16-bit timer/event counters 00 and 01 generate an interrupt request at the preset time interval.
(2) PPG output
16-bit timer/event counters 00 and 01 can output a rectangular wave whose frequency and output pulse width can
be set freely.
(3) Pulse width measurement
16-bit timer/event counters 00 and 01 can measure the pulse width of an externally input signal.
(4) External event counter
16-bit timer/event counters 00 and 01 can measure the number of pulses of an externally input signal.
(5) Square-wave output
16-bit timer/event counters 00 and 01 can output a square wave with any selected frequency.
(6) One-shot pulse output
16-bit timer event counters 00 and 01 can output a one-shot pulse whose output pulse width can be set freely.
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7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01
16-bit timer/event counters 00 and 01 include the following hardware.
Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 and 01
Item
Configuration
Timer counter
16 bits (TM0n)
Register
16-bit timer capture/compare register: 16 bits (CR00n, CR01n)
Timer input
TI00n, TI01n
Timer output
TO0n, output controller
Control registers
16-bit timer mode control register 0n (TMC0n)
16-bit timer capture/compare control register 0n (CRC0n)
16-bit timer output control register 0n (TOC0n)
Prescaler mode register 0n (PRM0n)
Port mode register 0 (PM0)
Port register 0 (P0)
Remark
n = 0, 1
Figures 7-1 and 7-2 show the block diagrams.
Figure 7-1. Block Diagram of 16-Bit Timer/Event Counter 00
Internal bus
Capture/compare control
register 00 (CRC00)
Selector
CRC002CRC001 CRC000
Noise
eliminator
TI010/TO00/P01
Selector
To CR010
16-bit timer capture/compare
register 000 (CR000)
INTTM000
Match
Noise
eliminator
16-bit timer counter 00
(TM00)
Output
controller
TO00/TI010/
P01
Match
2
Output latch
(P01)
Noise
eliminator
TI000/P00
Clear
PM01
16-bit timer capture/compare
register 010 (CR010)
Selector
fX
Selector
fX
fX/22
fX/28
INTTM010
CRC002
PRM001 PRM000
Prescaler mode
register 00 (PRM00)
148
TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
16-bit timer output
16-bit timer mode
control register 00
control register 00
(TOC00)
(TMC00)
Internal bus
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Figure 7-2. Block Diagram of 16-Bit Timer/Event Counter 01
Internal bus
Capture/compare control
register 01 (CRC01)
Selector
CRC012CRC011 CRC010
Noise
eliminator
TI011/TO01/P06
Selector
To CR011
16-bit timer capture/compare
register 001 (CR001)
INTTM001
Match
Noise
eliminator
16-bit timer counter 01
(TM01)
Output
controller
TO01/TI011/
P06
Match
2
Output latch
(P06)
Noise
eliminator
TI001/P05
Clear
PM06
16-bit timer capture/compare
register 011 (CR011)
Selector
fX
Selector
fX
fX/24
fX/26
INTTM011
CRC012
PRM011 PRM010
Prescaler mode
register 01 (PRM01)
TMC013 TMC012 TMC011 OVF01 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01
16-bit timer output
16-bit timer mode
control register 01
control register 01
(TOC01)
(TMC01)
Internal bus
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
(1) 16-bit timer counter 0n (TM0n)
TM0n is a 16-bit read-only register that counts count pulses.
The counter is incremented in synchronization with the rising edge of the input clock.
Figure 7-3. Format of 16-Bit Timer Counter 0n (TM0n)
Address: FF10H, FF11H (TM00), FFB0H, FFB1H (TM01)
Symbol
After reset: 0000H
FF11H (TM00)
FFB1H (TM01)
R
FF10H (TM00)
FFB0H (TM01)
TM0n
(n = 0, 1)
The count value is reset to 0000H in the following cases.
At RESET input
If TMC0n3 and TMC0n2 are cleared
If the valid edge of the TI00n pin is input in the mode in which clear & start occurs when inputting the valid
edge of the TI00n pin
If TM0n and CR00n match in the mode in which clear & start occurs on a match of TM0n and CR00n
If OSPT0n is set to 1 in one-shot pulse output mode
(2) 16-bit timer capture/compare register 00n (CR00n)
CR00n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is
used as a capture register or as a compare register is set by bit 0 (CRC0n0) of capture/compare control register
0n (CRC0n).
CR00n can be set by a 16-bit memory manipulation instruction.
RESET input clears this register to 0000H.
Figure 7-4. Format of 16-Bit Timer Capture/Compare Register 00n (CR00n)
Address: FF12H, FF13H (CR000), FFB2H, FFB3H (CR001)
Symbol
After reset: 0000H
FF13H (CR000)
FFB3H (CR001)
R/W
FF12H (CR000)
FFB2H (CR001)
CR00n
(n = 0, 1)
• When CR00n is used as a compare register
The value set in CR00n is constantly compared with 16-bit timer counter 0n (TM0n) count value, and an
interrupt request (INTTM00n) is generated if they match. The set value is held until CR00n is rewritten.
• When CR00n is used as a capture register
It is possible to select the valid edge of the TI00n pin or the TI01n pin as the capture trigger. The TI00n or
TI01n pin valid edge is set using prescaler mode register 0n (PRM0n) (see Table 7-2).
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Table 7-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins
(1) TI00n pin valid edge selected as capture trigger (CRC0n1 = 1, CRC0n0 = 1)
CR00n Capture Trigger
TI00n Pin Valid Edge
ES0n1
ES0n0
Falling edge
Rising edge
0
1
Rising edge
Falling edge
0
0
No capture operation
Both rising and falling edges
1
1
ES1n1
ES1n0
(2) TI01n pin valid edge selected as capture trigger (CRC0n1 = 0, CRC0n0 = 1)
CR00n Capture Trigger
TI01n Pin Valid Edge
Falling edge
Falling edge
0
0
Rising edge
Rising edge
0
1
Both rising and falling edges
Both rising and falling edges
1
1
Remarks 1. Setting ES0n1, ES0n0 = 1, 0 and ES1n1, ES1n0 = 1, 0 is prohibited.
2. ES0n1, ES0n0:
Bits 5 and 4 of prescaler mode register 0n (PRM0n)
ES1n1, ES1n0:
Bits 7 and 6 of prescaler mode register 0n (PRM0n)
CRC0n1, CRC0n0: Bits 1 and 0 of capture/compare control register 0n (CRC0n)
3. n = 0, 1
Cautions 1. Set a value other than 0000H in CR00n in the mode in which clear & start occurs on a match
of TM0n and CR00n.
2. If CR00n is cleared to 0000H in the free-running mode and in the clear mode using the valid
edge of the TI00n pin, an interrupt request (INTTM00n) is generated when the value of
CR00n changes from 0000H to 0001H following TM0n overflow (FFFFH).
In addition,
INTTM00n is generated after a match between TM0n and CR00n, after detecting the valid
edge of the TI01n pin, or the timer is cleared by a one-shot trigger.
3. When the valid edge of the TI01n pin is used, P01 or P06 cannot be used as the timer output
pin (TO0n). When P01 or P06 is used as the TO0n pin, the valid edge of the TI01n pin
cannot be used.
4. When CR00n is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value). If a timer
count stop and a capture trigger input conflict, the captured data is undefined.
5. Do not rewrite CR00n during TM0n operation.
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(3) 16-bit timer capture/compare register 01n (CR01n)
CR01n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is
used as a capture register or a compare register is set by bit 2 (CRC0n2) of capture/compare control register 0n
(CRC0n).
CR01n can be set by a 16-bit memory manipulation instruction.
RESET input clears this register to 0000H.
Figure 7-5. Format of 16-Bit Timer Capture/Compare Register 01n (CR01n)
Address: FF14H, FF15H (CR010), FFB4H, FFB5H (CR011)
Symbol
After reset: 0000H
FF15H (CR010)
FFB5H (CR011)
R/W
FF14H (CR010)
FFB4H (CR011)
CR01n
(n = 0, 1)
• When CR01n is used as a compare register
The value set in CR01n is constantly compared with 16-bit timer counter 0n (TM0n) count value, and an
interrupt request (INTTM01n) is generated if they match. The set value is held until CR01n is rewritten.
• When CR01n is used as a capture register
It is possible to select the valid edge of the TI00n pin as the capture trigger. The TI00n pin valid edge is set by
prescaler mode register 0n (PRM0n) (see Table 7-3).
Table 7-3. CR01n Capture Trigger and Valid Edge of TI00n Pin (CRC0n2 = 1)
CR01n Capture Trigger
TI00n Pin Valid Edge
ES0n1
ES0n0
Falling edge
Falling edge
0
0
Rising edge
Rising edge
0
1
Both rising and falling edges
Both rising and falling edges
1
1
Remarks 1. Setting ES0n1, ES0n0 = 1, 0 is prohibited.
2. ES0n1, ES0n0: Bits 5 and 4 of prescaler mode register 0n (PRM0n)
CRC0n2:
Bit 2 of capture/compare control register 0n (CRC0n)
3. n = 0, 1
Cautions 1. If the CR01n register is cleared to 0000H, an interrupt request (INTTM01n) is generated when
the value of CR01n changes from 0000H to 0001H following TM0n overflow (FFFFH). In
addition, INTTM01n is generated after a match between TM0n and CR01n, after detecting the
valid edge of the TI00n pin, or the timer is cleared by a one-shot trigger.
2. When CR01n is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
3. CR01n can be rewritten during TM0n operation. For details, see Caution 2 in Figure 7-20.
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7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01
The following six registers are used to control 16-bit timer/event counters 00 and 01.
• 16-bit timer mode control register 0n (TMC0n)
• Capture/compare control register 0n (CRC0n)
• 16-bit timer output control register 0n (TOC0n)
• Prescaler mode register 0n (PRM0n)
• Port mode register 0 (PM0)
• Port register 0 (P0)
(1) 16-bit timer mode control register 0n (TMC0n)
This register sets the 16-bit timer operating mode, the 16-bit timer counter 0n (TM0n) clear mode, and output
timing, and detects an overflow.
TMC0n can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC0n to 00H.
Caution 16-bit timer counter 0n (TM0n) starts operation at the moment TMC0n2 and TMC0n3 are set to
values other than 0, 0 (operation stop mode), respectively. Set TMC0n2 and TMC0n3 to 0, 0 to
stop the operation.
Remark
n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Address FFBAH
After reset: 00H
Symbol
7
6
5
4
TMC00
0
0
0
0
R/W
3
2
1
TMC003 TMC002 TMC001 OVF00
Operating mode and clear
TMC003 TMC002 TMC001
TO00 inversion timing selection
Interrupt request generation
mode selection
0
0
0
Operation stop
0
0
1
(TM00 cleared to 0)
0
1
0
Free-running mode
0
1
1
No change
Not generated
Match between TM00 and
TM00 and CR010
Generated on match between
Match between TM00 and
TM00 and CR000, or match
CR000, match between TM00
between TM00 and CR010
and CR010 or TI000 pin valid
−
1
0
0
Clear & start occurs on TI000
1
0
1
pin valid edge
1
1
0
Clear & start occurs on match
Match between TM00 and
between TM00 and CR000
CR000 or match between
Generated by inputting CR000
capture trigger
TM00 and CR010
1
1
Match between TM00 and
1
CR000, match between TM00
and CR010 or TI000 pin valid
edge
OVF00
16-bit timer counter 00 (TM00) overflow detection
0
Overflow not detected
1
Overflow detected
Cautions 1. Timer operation must be stopped before writing to bits other than the OVF00 flag.
2. Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00).
3. If any the following modes: the mode in which clear & start occurs on match between TM00
and CR000, the mode in which clear & start occurs at the TI000 pin valid edge, or free-running
mode is selected, when the set value of CR000 is FFFFH and the TM00 value changes from
FFFFH to 0000H, the OVF00 flag is set to 1.
Remark
TO00:
16-bit timer/event counter 00 output pin
TI000:
16-bit timer/event counter 00 input pin
TM00:
16-bit timer counter 00
CR000: 16-bit timer capture/compare register 000
CR010: 16-bit timer capture/compare register 010
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Figure 7-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01)
Address FFB6H
After reset: 00H
Symbol
7
6
5
4
TMC01
0
0
0
0
R/W
3
2
1
TMC013 TMC012 TMC011 OVF01
Operating mode and clear
TMC013 TMC012 TMC011
TO01 inversion timing selection
Interrupt request generation
mode selection
0
0
0
Operation stop
0
0
1
(TM01 cleared to 0)
0
1
0
Free-running mode
0
1
1
No change
Not generated
Match between TM01 and
TM01 and CR011
Generated on match between
Match between TM01 and
TM01 and CR001, or match
CR001, match between TM01
between TM01 and CR011
and CR011 or TI001 pin valid
−
1
0
0
Clear & start occurs on TI001
1
0
1
pin valid edge
1
1
0
Clear & start occurs on match
Match between TM01 and
between TM01 and CR001
CR001 or match between
Generated by inputting CR001
capture trigger
TM01 and CR011
1
1
Match between TM01 and
1
CR001, match between TM01
and CR011 or TI001 pin valid
edge
OVF01
16-bit timer counter 01 (TM01) overflow detection
0
Overflow not detected
1
Overflow detected
Cautions 1. Timer operation must be stopped before writing to bits other than the OVF01 flag.
2. Set the valid edge of the TI001/P05 pin using prescaler mode register 01 (PRM01).
3. If any the following modes: the mode in which clear & start occurs on match between TM01
and CR001, the mode in which clear & start occurs at the TI001 pin valid edge, or free-running
mode is selected, when the set value of CR001 is FFFFH and the TM01 value changes from
FFFFH to 0000H, the OVF01 flag is set to 1.
Remark
TO01:
16-bit timer/event counter 01 output pin
TI001:
16-bit timer/event counter 01 input pin
TM01:
16-bit timer counter 01
CR001: 16-bit timer capture/compare register 001
CR011: 16-bit timer capture/compare register 011
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
(2) Capture/compare control register 0n (CRC0n)
This register controls the operation of the 16-bit timer capture/compare registers (CR00n, CR01n).
CRC0n can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CRC0n to 00H.
Remark
n = 0, 1
Figure 7-8. Format of Capture/Compare Control Register 00 (CRC00)
Address: FFBCH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
CRC00
0
0
0
0
0
CRC002
CRC001
CRC000
CRC002
CR010 operating mode selection
0
Operates as compare register
1
Operates as capture register
CRC001
CR000 capture trigger selection
0
Captures on valid edge of TI010 pin
1
Captures on valid edge of TI000 pin by reverse phase
CRC000
Note
CR000 operating mode selection
0
Operates as compare register
1
Operates as capture register
Note The capture operation is not performed if both the rising and falling edges are specified as the valid edge of
the TI000 pin.
Cautions 1. Timer operation must be stopped before setting CRC00.
2. When the mode in which clear & start occurs on a match between TM00 and CR000 is
selected with 16-bit timer mode control register 00 (TMC00), CR000 should not be specified
as a capture register.
3. To ensure that the capture operation is performed properly, the capture trigger requires a
pulse longer than two cycles of the count clock selected by prescaler mode register 00
(PRM00).
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Figure 7-9. Format of Capture/Compare Control Register 01 (CRC01)
Address: FFB8H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
CRC01
0
0
0
0
0
CRC012
CRC011
CRC010
CRC012
CR011 operating mode selection
0
Operates as compare register
1
Operates as capture register
CRC011
CR001 capture trigger selection
0
Captures on valid edge of TI011 pin
1
Captures on valid edge of TI001 pin by reverse phase
CRC010
Note
CR001 operating mode selection
0
Operates as compare register
1
Operates as capture register
Note The capture operation is not performed if both the rising and falling edges are specified as the valid edge of
the TI001 pin.
Cautions 1. Timer operation must be stopped before setting CRC01.
2. When the mode in which clear & start occurs on a match between TM01 and CR001 is
selected with 16-bit timer mode control register 01 (TMC01), CR001 should not be specified
as a capture register.
3. To ensure that the capture operation is performed properly, the capture trigger requires a
pulse longer than two cycles of the count clock selected by prescaler mode register 01
(PRM01).
(3) 16-bit timer output control register 0n (TOC0n)
This register controls the operation of the 16-bit timer/event counter 0n output controller. It sets/resets the timer
output F/F (LV0n), enables/disables output inversion and 16-bit timer/event counter 0n timer output,
enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software.
TOC0n can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TOC0n to 00H.
Remark
n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-10. Format of 16-Bit Timer Output Control Register 00 (TOC00)
Address: FFBDH
After reset: 00H
R/W
Symbol
7
4
1
TOC00
0
OSPT00
OSPE00
TOC004
LVS00
LVR00
TOC001
TOE00
OSPT00
One-shot pulse output trigger control via software
0
No one-shot pulse output trigger
1
One-shot pulse output trigger
OSPE00
One-shot pulse output operation control
0
Successive pulse output mode
1
One-shot pulse output mode
TOC004
Note
Timer output F/F control using match of CR010 and TM00
0
Disables inversion operation
1
Enables inversion operation
LVS00
LVR00
Timer output F/F status setting
0
0
No change
0
1
Timer output F/F reset (0)
1
0
Timer output F/F set (1)
1
1
Setting prohibited
TOC001
Timer output F/F control using match of CR000 and TM00
0
Disables inversion operation
1
Enables inversion operation
TOE00
Timer output control
0
Disables output (output fixed to level 0)
1
Enables output
Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI000 pin valid edge. In the mode in which clear & start occurs on a match
between the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow
does not occur.
Cautions 1. Timer operation must be stopped before setting other than TOC004.
2. If LVS00 and LVR00 are read, 0 is read.
3. OSPT00 is automatically cleared after data is set, so 0 is read.
4. Do not set OSPT00 to 1 other than in one-shot pulse output mode.
5. A write interval of two cycles or more of the count clock selected by prescaler mode register
00 (PRM00) is required to write to OSPT00 successively.
6. Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1 simultaneously.
7. Perform and below in the following order, not at the same time.
Set TOC001, TOC004, TOE00, OSPE00: Timer output operation setting
Set LVS00, LVR00:
158
Timer output F/F setting
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-11. Format of 16-Bit Timer Output Control Register 01 (TOC01)
Address: FFB9H
After reset: 00H
R/W
Symbol
7
4
1
TOC01
0
OSPT01
OSPE01
TOC014
LVS01
LVR01
TOC011
TOE01
OSPT01
One-shot pulse output trigger control via software
0
No one-shot pulse output trigger
1
One-shot pulse output trigger
OSPE01
One-shot pulse output operation control
0
Successive pulse output mode
1
One-shot pulse output mode
TOC014
Note
Timer output F/F control using match of CR011 and TM01
0
Disables inversion operation
1
Enables inversion operation
LVS01
LVR01
Timer output F/F status setting
0
0
No change
0
1
Timer output F/F reset (0)
1
0
Timer output F/F set (1)
1
1
Setting prohibited
TOC011
Timer output F/F control using match of CR001 and TM01
0
Disables inversion operation
1
Enables inversion operation
TOE01
Timer output control
0
Disables output (output fixed to level 0)
1
Enables output
Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI001 pin valid edge. In the mode in which clear & start occurs on a match
between the TM01 register and CR001 register, one-shot pulse output is not possible because an overflow
does not occur.
Cautions 1. Timer operation must be stopped before setting other than TOC014.
2. If LVS01 and LVR01 are read, 0 is read.
3. OSPT01 is automatically cleared after data is set, so 0 is read.
4. Do not set OSPT01 to 1 other than in one-shot pulse output mode.
5. A write interval of two cycles or more of the count clock selected by prescaler mode register
01 (PRM01) is required to write to OSPT01 successively.
6. Do not set LVS01 to 1 before TOE01, and do not set LVS01 and TOE01 to 1 simultaneously.
7. Perform and below in the following order, not at the same time.
Set TOC011, TOC014, TOE01, OSPE01: Timer output operation setting
Set LVS01, LVR01:
Timer output F/F setting
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
(4) Prescaler mode register 0n (PRM0n)
This register is used to set the 16-bit timer counter 0n (TM0n) count clock and TI00n and TI01n pin input valid
edges.
PRM0n can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PRM0n to 00H.
Remark
n = 0, 1
Figure 7-12. Format of Prescaler Mode Register 00 (PRM00)
Address: FFBBH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
PRM00
ES101
ES100
ES001
ES000
0
0
PRM001
PRM000
ES101
ES100
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES001
ES000
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
PRM001
PRM000
0
0
fX (10 MHz)
0
1
fX/2 (2.5 MHz)
1
0
fX/2 (39.06 kHz)
1
1
TI000 valid edge
Notes 1.
TI010 pin valid edge selection
TI000 pin valid edge selection
Note 1
Count clock selection
2
8
Note 2
Be sure to set the count clock so that the following condition is satisfied.
• VDD = 4.0 to 5.5 V: Count clock ≤ 10 MHz
• VDD = 3.3 to 4.0 V: Count clock ≤ 8.38 MHz
• VDD = 2.7 to 3.3 V: Count clock ≤ 5 MHz
• VDD = 2.5 to 2.7 V: Count clock ≤ 2.5 MHz (standard products, (A) grade products only)
2.
160
The external clock requires a pulse longer than two cycles of the internal count clock (fX).
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the
clock of the internal oscillator is divided and supplied as the count clock. If the count clock
is the internal oscillation clock, the operation of 16-bit timer/event counter 00 is not
guaranteed.
When an external clock is used and when the internal oscillation clock is
selected and supplied to the CPU, the operation of 16-bit timer/event counter 00 is not
guaranteed, either, because the internal oscillation clock is supplied as the sampling clock to
eliminate noise.
2. Always set data to PRM00 after stopping the timer operation.
3. If the valid edge of the TI000 pin is to be set for the count clock, do not set the clear & start
mode using the valid edge of the TI000 pin and the capture trigger.
4. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is
immediately detected after the rising edge or both the rising and falling edges are set as the
valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00
(TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, if the
TI000 or TI010 pin is high level when re-enabling operation after the operation has been
stopped, the rising edge is not detected.
5. When the valid edge of the TI010 pin is used, P01 cannot be used as the timer output pin
(TO00). When P01 is used as the TO00 pin, the valid edge of the TI010 pin cannot be used.
Remarks 1. fX: High-speed system clock oscillation frequency
2. Figures in parentheses are for operation with fX = 10 MHz.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-13. Format of Prescaler Mode Register 01 (PRM01)
Address: FFB7H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
PRM01
ES111
ES110
ES011
ES010
0
0
PRM011
PRM010
ES111
ES110
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES011
ES010
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
PRM011
PRM010
0
0
fX (10 MHz)
0
1
fX/2 (625 kHz)
1
0
fX/2 (156.25 kHz)
1
1
TI001 valid edge
Notes 1.
TI011 pin valid edge selection
TI001 pin valid edge selection
Note 1
Count clock selection
4
6
Note 2
Be sure to set the count clock so that the following condition is satisfied.
• VDD = 4.0 to 5.5 V: Count clock ≤ 10 MHz
• VDD = 3.3 to 4.0 V: Count clock ≤ 8.38 MHz
• VDD = 2.7 to 3.3 V: Count clock ≤ 5 MHz
• VDD = 2.5 to 2.7 V: Count clock ≤ 2.5 MHz (standard products, (A) grade products only)
2.
162
The external clock requires a pulse longer than two cycles of the internal count clock (fX).
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the
clock of the internal oscillator is divided and supplied as the count clock. If the count clock
is the internal oscillation clock, the operation of 16-bit timer/event counter 01 is not
guaranteed.
When an external clock is used and when the internal oscillation clock is
selected and supplied to the CPU, the operation of 16-bit timer/event counter 01 is not
guaranteed, either, because the internal oscillation clock is supplied as the sampling clock to
eliminate noise.
2. Always set data to PRM01 after stopping the timer operation.
3. If the valid edge of the TI001 pin is to be set for the count clock, do not set the clear & start
mode using the valid edge of the TI001 pin and the capture trigger.
4. If the TI001 or TI011 pin is high level immediately after system reset, the rising edge is
immediately detected after the rising edge or both the rising and falling edges are set as the
valid edge(s) of the TI001 pin or TI011 pin to enable the operation of 16-bit timer counter 01
(TM01). Care is therefore required when pulling up the TI001 or TI011 pin. However, if the
TI001 or TI011 pin is high level when re-enabling operation after the operation has been
stopped, the rising edge is not detected.
5. When the valid edge of the TI011 pin is used, P06 cannot be used as the timer output pin
(TO01). When P06 is used as the TO01 pin, the valid edge of the TI011 pin cannot be used.
Remarks 1. fX: High-speed system clock oscillation frequency
2. Figures in parentheses are for operation with fX = 10 MHz.
(5) Port mode register 0 (PM0)
This register sets port 0 input/output in 1-bit units.
When using the P01/TO00/TI010 and P06/TO01/TI011 pins for timer output, set PM01 and PM06 and the output
latch of P01 and P06 to 0.
When using the P01/TO00/TI010 and P06/TO01/TI011 pins for timer input, set PM01 and PM06 to 1. At this time,
the output latch of P01 and P06 may be 0 or 1.
PM0 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM0 to FFH.
Figure 7-14. Format of Port Mode Register 0 (PM0)
Address: FF20H
After reset: FFH
6
5
4
R/W
Symbol
7
3
2
PM0
1
PM06 PM05 PM04 PM03 PM02 PM01 PM00
PM0n
P0n pin I/O mode selection (n = 0 to 6)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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0
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
7.4 Operation of 16-Bit Timer/Event Counters 00 and 01
7.4.1 Interval timer operation
Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown
in Figure 7-15 allows operation as an interval timer.
Setting
The basic operation setting procedure is as follows.
Set the CRC0n register (see Figure 7-15 for the set value).
Set any value to the CR00n register.
Set the count clock by using the PRM0n register.
Set the TMC0n register to start the operation (see Figure 7-15 for the set value).
Caution Do not rewrite CR00n during TM0n operation.
Remark
For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS.
Interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register
00n (CR00n) as the interval.
When the count value of 16-bit timer counter 0n (TM0n) matches the value set in CR00n, counting continues with
the TM0n value cleared to 0 and the interrupt request signal (INTTM00n) is generated.
The count clock of 16-bit timer/event counter 0n can be selected with bits 0 and 1 (PRM0n0, PRM0n1) of prescaler
mode register 0n (PRM0n).
Remark
164
n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-15. Control Register Settings for Interval Timer Operation
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n
7
6
5
4
0
0
0
0
TMC0n3 TMC0n2 TMC0n1 OVF0n
1
1
0/1
0
Clears and starts on match between TM0n and CR00n.
(b) Capture/compare control register 0n (CRC0n)
CRC0n
7
6
5
4
3
0
0
0
0
0
CRC0n2 CRC0n1 CRC0n0
0/1
0/1
0
CR00n used as compare register
(c) Prescaler mode register 0n (PRM0n)
ES1n1 ES1n0 ES0n1 ES0n0
PRM0n
0/1
0/1
0/1
0/1
3
2
0
0
PRM0n1 PRM0n0
0/1
0/1
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Remarks 1. 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the
description of the respective control registers for details.
2. n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-16. Interval Timer Configuration Diagram
16-bit timer capture/compare
register 00n (CR00n)
INTTM00n
Selector
fX (fX)Note 1
fX/22 (fX/24)Note 1
fX/28 (fX/26)Note 1
Note 2
16-bit timer counter 0n
(TM0n)
OVF0n
Noise
eliminator
TI000/P00
(TI001/P05)Note 1
Clear
circuit
fX
Notes 1.
Frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in
parentheses are for 16-bit timer/event counter 01.
2.
OVF0n is set to 1 only when 16-bit timer capture/compare register 00n is set to FFFFH.
Figure 7-17. Timing of Interval Timer Operation
t
Count clock
TM0n count value
0000H
0001H
N
Timer operation enabled
CR00n
0000H 0001H
Clear
N
N
N
0000H 0001H
Clear
N
N
INTTM00n
Interrupt acknowledged
Remark
Interval time = (N + 1) × t
N = 0001H to FFFFH (settable range)
n = 0, 1
166
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Interrupt acknowledged
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
7.4.2 PPG output operations
Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown
in Figure 7-18 allows operation as PPG (Programmable Pulse Generator) output.
Setting
The basic operation setting procedure is as follows.
Set the CRC0n register (see Figure 7-18 for the set value).
Set any value to the CR00n register as the cycle.
Set any value to the CR01n register as the duty factor.
Set the TOC0n register (see Figure 7-18 for the set value).
Set the count clock by using the PRM0n register.
Set the TMC0n register to start the operation (see Figure 7-18 for the set value).
Caution To change the value of the duty factor (the value of the CR01n register) during operation, see
Caution 2 in Figure 7-20 PPG Output Operation Timing.
Remarks 1. For the setting of the TO0n pin, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS.
In the PPG output operation, rectangular waves are output from the TO0n pin with the pulse width and the cycle
that correspond to the count values preset in 16-bit timer capture/compare register 01n (CR01n) and in 16-bit timer
capture/compare register 00n (CR00n), respectively.
Remark
n = 0, 1
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Figure 7-18. Control Register Settings for PPG Output Operation
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n
7
6
5
4
0
0
0
0
TMC0n3 TMC0n2 TMC0n1 OVF0n
1
1
0
0
Clears and starts on match between TM0n and CR00n.
(b) Capture/compare control register 0n (CRC0n)
CRC0n
7
6
5
4
3
0
0
0
0
0
CRC0n2 CRC0n1 CRC0n0
0
×
0
CR00n used as compare register
CR01n used as compare register
(c) 16-bit timer output control register 0n (TOC0n)
7
TOC0n
0
OSPT0n OSPE0n TOC0n4 LVS0n LVR0n TOC0n1 TOE0n
0
0
1
0/1
0/1
1
1
Enables TO0n output.
Inverts output on match between TM0n and CR00n.
Specifies initial value of TO0n output F/F (setting “11” is prohibited).
Inverts output on match between TM0n and CR01n.
Disables one-shot pulse output.
(d) Prescaler mode register 0n (PRM0n)
ES1n1 ES1n0 ES0n1 ES0n0
PRM0n
0/1
0/1
0/1
0/1
3
2
0
0
PRM0n1 PRM0n0
0/1
0/1
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Cautions 1. Values in the following range should be set in CR00n and CR01n:
0000H ≤ CR01n < CR00n ≤ FFFFH
2. The pulse generated through PPG output has a cycle of [CR00n setting value + 1], and a duty
of [(CR01n setting value + 1)/(CR00n setting value + 1)].
Remark
×: Don’t care
n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-19. Configuration Diagram of PPG Output
16-bit timer capture/compare
register 00n (CR00n)
Selector
fX (fX)Note
fX/2 (fX/24)Note
2
fX/28 (fX/26)Note
Noise
eliminator
Output controller
TI000/P00
(TI001/P05)Note
Clear
circuit
16-bit timer counter 0n
(TM0n)
fX
TO00/TI010/P01
( TO01/TI011/P06 )
16-bit timer capture/compare
register 01n (CR01n)
Note Frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in
parentheses are for 16-bit timer/event counter 01.
Figure 7-20. PPG Output Operation Timing
t
Count clock
TM0n count value N
0000H 0001H
M−1
M
Clear
N−1
N
0000H 0001H
Clear
CR00n capture value
N
CR01n capture value
M
TO0n
Pulse width: (M + 1) × t
1 cycle: (N + 1) × t
Cautions 1. Do not rewrite CR00n during TM0n operation.
2. In the PPG output operation, change the pulse width (rewrite CR01n) during TM0n operation
using the following procedure.
Disable the timer output inversion operation by match of TM0n and CR01n (TOC0n4 = 0)
Disable the INTTM01n interrupt (TMMK01n = 1)
Rewrite CR01n
Wait for 1 cycle of the TM0n count clock
Enable the timer output inversion operation by match of TM0n and CR01n (TOC0n4 = 1)
Clear the interrupt request flag of INTTM01n (TMIF01n = 0)
Enable the INTTM01n interrupt (TMMK01n = 0)
Remarks 1. 0000H ≤ M < N ≤ FFFFH
2. n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
7.4.3 Pulse width measurement operations
It is possible to measure the pulse width of the signals input to the TI00n pin and TI01n pin using 16-bit timer
counter 0n (TM0n).
There are two measurement methods: measuring with TM0n used in free-running mode, and measuring by
restarting the timer in synchronization with the edge of the signal input to the TI00n pin.
When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate
the necessary pulse width. Clear the overflow flag after checking it.
The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by
prescaler mode register 0n (PRM0n) and the valid level of the TI00n or TI01n pin is detected twice, thus eliminating
noise with a short pulse width.
Figure 7-21. CR01n Capture Operation with Rising Edge Specified
Count clock
TM0n
N−3
N−2
N−1
N
N+1
TI00n
Rising edge detection
N
CR01n
INTTM01n
Setting
The basic operation setting procedure is as follows.
Set the CRC0n register (see Figures 7-22, 7-25, 7-27, and 7-29 for the set value).
Set the count clock by using the PRM0n register.
Set the TMC0n register to start the operation (see Figures 7-22, 7-25, 7-27, and 7-29 for the set value).
Caution To use two capture registers, set the TI00n and TI01n pins.
Remarks 1. For the setting of the TI00n (or TI01n) pin, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n (or INTTM01n) interrupt, see CHAPTER 19
FUNCTIONS.
3. n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
(1) Pulse width measurement with free-running counter and one capture register
When 16-bit timer counter 0n (TM0n) is operated in free-running mode, and the edge specified by prescaler mode
register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare
register 01n (CR01n) and an external interrupt request signal (INTTM01n) is set.
Specify both the rising and falling edges of the TI00n pin by using bits 4 and 5 (ES0n0 and ES0n1) of PRM0n.
Sampling is performed using the count clock selected by PRM0n, and a capture operation is only performed
when a valid level of the TI00n pin is detected twice, thus eliminating noise with a short pulse width.
Figure 7-22. Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register (When TI00n and CR01n Are Used)
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n
7
6
5
4
0
0
0
0
TMC0n3 TMC0n2 TMC0n1 OVF0n
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 0n (CRC0n)
CRC0n
7
6
5
4
3
0
0
0
0
0
CRC0n2 CRC0n1 CRC0n0
1
0/1
0
CR00n used as compare register
CR01n used as capture register
(c) Prescaler mode register 0n (PRM0n)
ES1n1 ES1n0 ES0n1 ES0n0
PRM0n
0/1
0/1
1
1
3
2
0
0
PRM0n1 PRM0n0
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies both edges for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-23. Configuration Diagram for Pulse Width Measurement with Free-Running Counter
fX/22 (fX/24)Note
fX/28 (fX/26)Note
Selector
fX (fX)Note
16-bit timer counter 0n
(TM0n)
OVF0n
16-bit timer capture/compare
register 01n (CR01n)
TI00n
INTTM01n
Internal bus
Note Frequencies without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16bit timer/event counter 01.
Figure 7-24. Timing of Pulse Width Measurement Operation with Free-Running Counter
and One Capture Register (with Both Edges Specified)
t
Count clock
TM0n count value
0000H 0001H
D0
D0 + 1
D1
D1 + 1
FFFFH 0000H
D2
D3
TI00n pin input
CR01n capture value
D0
D1
D2
D3
INTTM01n
Note
OVF0n
(D1 − D0) × t
(10000H − D1 + D2) × t
Note Clear OVF0n by software.
Remark
172
n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
(2) Measurement of two pulse widths with free-running counter
When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to simultaneously measure
the pulse widths of the two signals input to the TI00n pin and the TI01n pin.
When the edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n) is input to
the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an interrupt
request signal (INTTM01n) is set.
Also, when the edge specified by bits 6 and 7 (ES1n0 and ES1n1) of PRM0n is input to the TI01n pin, the value
of TM0n is taken into 16-bit timer capture/compare register 00n (CR00n) and an interrupt request signal
(INTTM00n) is set.
Specify both the rising and falling edges as the edges of the TI00n and TI01n pins, by using bits 4 and 5 (ES0n0
and ES0n1) and bits 6 and 7 (ES1n0 and ES1n1) of PRM0n.
Sampling is performed using the count clock cycle selected by prescaler mode register 0n (PRM0n), and a
capture operation is only performed when a valid level of the TI00n or TI01n pin is detected twice, thus
eliminating noise with a short pulse width.
Figure 7-25. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n
7
6
5
4
0
0
0
0
TMC0n3 TMC0n2 TMC0n1 OVF0n
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 0n (CRC0n)
CRC0n
7
6
5
4
3
0
0
0
0
0
CRC0n2 CRC0n1 CRC0n0
1
0
1
CR00n used as capture register
Captures valid edge of TI01n pin to CR00n.
CR01n used as capture register
(c) Prescaler mode register 0n (PRM0n)
ES1n1 ES1n0 ES0n1 ES0n0
PRM0n
1
1
1
1
3
2
0
0
PRM0n1 PRM0n0
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies both edges for pulse width detection.
Specifies both edges for pulse width detection.
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-26. Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified)
t
Count clock
TM0n count value
0000H 0001H
D0
D0 + 1
D1
D1 + 1
FFFFH 0000H
D2
D2 + 1 D2 + 2
TI00n pin input
CR01n capture value
D0
D1
D2
INTTM01n
TI01n pin input
CR00n capture value
D1
D2 + 1
INTTM00n
Note
OVF0n
(D1 − D0) × t
(10000H − D1 + D2) × t
(10000H − D1 + (D2 + 1)) × t
Note Clear OVF0n by software.
Remark
174
n = 0, 1
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(D3 − D2) × t
D3
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
(3) Pulse width measurement with free-running counter and two capture registers
When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to measure the pulse width
of the signal input to the TI00n pin.
When the rising or falling edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n
(PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n
(CR01n) and an interrupt request signal (INTTM01n) is set.
Also, when the inverse edge to that of the capture operation is input into CR01n, the value of TM0n is taken into
16-bit timer capture/compare register 00n (CR00n).
Sampling is performed using the count clock cycle selected by prescaler mode register 0n (PRM0n), and a
capture operation is only performed when a valid level of the TI00n pin is detected twice, thus eliminating noise
with a short pulse width.
Figure 7-27. Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers (with Rising Edge Specified)
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n
7
6
5
4
0
0
0
0
TMC0n3 TMC0n2 TMC0n1 OVF0n
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 0n (CRC0n)
CRC0n
7
6
5
4
3
0
0
0
0
0
CRC0n2 CRC0n1 CRC0n0
1
1
1
CR00n used as capture register
Captures to CR00n at inverse edge
to valid edge of TI00n.
CR01n used as capture register
(c) Prescaler mode register 0n (PRM0n)
ES1n1 ES1n0 ES0n1 ES0n0
PRM0n
0/1
0/1
0
1
3
2
0
0
PRM0n1 PRM0n0
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-28. Timing of Pulse Width Measurement Operation with Free-Running Counter
and Two Capture Registers (with Rising Edge Specified)
t
Count clock
TM0n count value
0000H 0001H
D0
D0 + 1
D1
D1 + 1
FFFFH 0000H
D2
D2 + 1
D3
TI00n pin input
CR01n capture value
D0
CR00n capture value
D2
D1
D3
INTTM01n
Note
OVF0n
(D1 − D0) × t
(10000H − D1 + D2) × t
(D3 − D2) × t
Note Clear OVF0n by software.
(4) Pulse width measurement by means of restart
When input of a valid edge to the TI00n pin is detected, the count value of 16-bit timer counter 0n (TM0n) is taken
into 16-bit timer capture/compare register 01n (CR01n), and then the pulse width of the signal input to the TI00n
pin is measured by clearing TM0n and restarting the count operation.
Either of two edges⎯rising or falling⎯can be selected using bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode
register 0n (PRM0n).
Sampling is performed using the count clock cycle selected by prescaler mode register 0n (PRM0n) and a
capture operation is only performed when a valid level of the TI00n pin is detected twice, thus eliminating noise
with a short pulse width.
Remark
176
n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-29. Control Register Settings for Pulse Width Measurement by Means of Restart
(with Rising Edge Specified)
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n
7
6
5
4
0
0
0
0
TMC0n3 TMC0n2 TMC0n1 OVF0n
1
0
0/1
0
Clears and starts at valid edge of TI00n pin.
(b) Capture/compare control register 0n (CRC0n)
CRC0n
7
6
5
4
3
0
0
0
0
0
CRC0n2 CRC0n1 CRC00n
1
1
1
CR00n used as capture register
Captures to CR00n at inverse edge to valid edge of TI00n.
CR01n used as capture register
(c) Prescaler mode register 0n (PRM0n)
ES1n1 ES1n0 ES0n1 ES0n0
PRM0n
0/1
0/1
0
1
3
2
0
0
PRM0n1 PRM0n0
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Figure 7-30. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified)
t
Count clock
TM0n count value
0000H 0001H
D0
0000H 0001H
D2 0000H 0001H
D1
TI00n pin input
CR01n capture value
D0
D2
D1
CR00n capture value
INTTM01n
D1 × t
D2 × t
Remark
n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
7.4.4 External event counter operation
Setting
The basic operation setting procedure is as follows.
Set the CRC0n register (see Figure 7-31 for the set value).
Set the count clock by using the PRM0n register.
Set any value to the CR00n register (0000H cannot be set).
Set the TMC0n register to start the operation (see Figure 7-31 for the set value).
Remarks 1. For the setting of the TI00n pin, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS.
The external event counter counts the number of external clock pulses input to the TI00n pin using 16-bit timer
counter 0n (TM0n).
TM0n is incremented each time the valid edge specified by prescaler mode register 0n (PRM0n) is input.
When the TM0n count value matches the 16-bit timer capture/compare register 00n (CR00n) value, TM0n is
cleared to 0 and the interrupt request signal (INTTM00n) is generated.
Input a value other than 0000H to CR00n (a count operation with 1-bit pulse cannot be carried out).
Any of three edges⎯rising, falling, or both edges⎯can be selected using bits 4 and 5 (ES0n0 and ES0n1) of
prescaler mode register 0n (PRM0n).
Sampling is performed using the internal clock (fX) and an operation is only performed when a valid level of the
TI00n pin is detected twice, thus eliminating noise with a short pulse width.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-31. Control Register Settings in External Event Counter Mode (with Rising Edge Specified)
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n
7
6
5
4
0
0
0
0
TMC0n3 TMC0n2 TMC0n1 OVF0n
1
1
0/1
0
Clears and starts on match between TM0n and CR00n.
(b) Capture/compare control register 0n (CRC0n)
CRC0n
7
6
5
4
3
0
0
0
0
0
CRC0n2 CRC0n1 CRC0n0
0/1
0/1
0
CR00n used as compare register
(c) Prescaler mode register 0n (PRM0n)
ES1n1 ES1n0 ES0n1 ES0n0
PRM0n
0/1
0/1
0
1
3
2
0
0
PRM0n1 PRM0n0
1
1
Selects external clock.
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter.
See the description of the respective control registers for details.
n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-32. Configuration Diagram of External Event Counter
Internal bus
16-bit timer capture/compare
register 00n (CR00n)
Match
INTTM00n
Clear
Noise eliminator
fX
16-bit timer counter 0n (TM0n)
OVF0nNote
Valid edge of TI00n pin
Note OVF0n is set to 1 only when CR00n is set to FFFFH.
Figure 7-33. External Event Counter Operation Timing (with Rising Edge Specified)
TI00n pin input
TM0n count value
CR00n
0000H 0001H 0002H 0003H 0004H 0005H
N–1
N
0000H 0001H 0002H 0003H
N
INTTM00n
Caution When reading the external event counter count value, TM0n should be read.
Remark
180
n = 0, 1
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
7.4.5 Square-wave output operation
Setting
The basic operation setting procedure is as follows.
Set the count clock by using the PRM0n register.
Set the CRC0n register (see Figure 7-34 for the set value).
Set the TOC0n register (see Figure 7-34 for the set value).
Set any value to the CR00n register (0000H cannot be set).
Set the TMC0n register to start the operation (see Figure 7-34 for the set value).
Caution Do not rewrite CR00n during TM0n operation.
Remarks 1. For the setting of the TO0n pin, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS.
A square wave with any selected frequency can be output at intervals determined by the count value preset to 16bit timer capture/compare register 00n (CR00n).
The TO0n pin output status is reversed at intervals determined by the count value preset to CR00n + 1 by setting
bit 0 (TOE0n) and bit 1 (TOC0n1) of 16-bit timer output control register 0n (TOC0n) to 1. This enables a square wave
with any selected frequency to be output.
Figure 7-34. Control Register Settings in Square-Wave Output Mode (1/2)
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n
7
6
5
4
0
0
0
0
TMC0n3 TMC0n2 TMC0n1 OVF0n
1
1
0
0
Clears and starts on match between TM0n and CR00n.
(b) Capture/compare control register 0n (CRC0n)
CRC0n
7
6
5
4
3
0
0
0
0
0
CRC0n2 CRC0n1 CRC0n0
0/1
0/1
0
CR00n used as compare register
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-34. Control Register Settings in Square-Wave Output Mode (2/2)
(c) 16-bit timer output control register 0n (TOC0n)
7
TOC0n
OSPT0n OSPE0n TOC0n4 LVS0n LVR0n TOC0n1 TOE0n
0
0
0
0
0/1
0/1
1
1
Enables TO0n output.
Inverts output on match between TM0n and CR00n.
Specifies initial value of TO0n output F/F (setting “11” is prohibited).
Does not invert output on match between TM0n and CR01n.
Disables one-shot pulse output.
(d) Prescaler mode register 0n (PRM0n)
ES1n1 ES1n0 ES0n1 ES0n0
PRM0n
0/1
0/1
0/1
0/1
3
2
0
0
PRM0n1 PRM0n0
0/1
0/1
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the
description of the respective control registers for details.
n = 0, 1
Figure 7-35. Square-Wave Output Operation Timing
Count clock
TM0n count value
CR00n
0000H 0001H 0002H
N–1
N
0000H 0001H 0002H
N
INTTM00n
TO0n pin output
Remark
182
n = 0, 1
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N–1
N
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
7.4.6 One-shot pulse output operation
16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external
trigger (TI00n pin input).
Setting
The basic operation setting procedure is as follows.
Set the count clock by using the PRM0n register.
Set the CRC0n register (see Figures 7-36 and 7-38 for the set value).
Set the TOC0n register (see Figures 7-36 and 7-38 for the set value).
Set any value to the CR00n and CR01n registers (0000H cannot be set).
Set the TMC0n register to start the operation (see Figures 7-36 and 7-38 for the set value).
Remarks 1. For the setting of the TO0n pin, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n (if necessary, INTTM01n) interrupt, see CHAPTER 19
INTERRUPT FUNCTIONS.
(1) One-shot pulse output with software trigger
A one-shot pulse can be output from the TO0n pin by setting 16-bit timer mode control register 0n (TMC0n),
capture/compare control register 0n (CRC0n), and 16-bit timer output control register 0n (TOC0n) as shown in
Figure 7-36, and by setting bit 6 (OSPT0n) of the TOC0n register to 1 by software.
By setting the OSPT0n bit to 1, 16-bit timer/event counter 0n is cleared and started, and its output becomes
active at the count value (N) set in advance to 16-bit timer capture/compare register 01n (CR01n). After that, the
output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 00n
(CR00n)Note.
Even after the one-shot pulse has been output, the TM0n register continues its operation. To stop the TM0n
register, the TMC0n3 and TMC0n2 bits of the TMC0n register must be set to 00.
Note The case where N < M is described here. When N > M, the output becomes active with the CR00n register
and inactive with the CR01n register. Do not set N to M.
Cautions 1. Do not set the OSPT0n bit to 1 again while the one-shot pulse is being output. To output
the one-shot pulse again, wait until the current one-shot pulse output is completed.
2. When using the one-shot pulse output of 16-bit timer/event counter 0n with a software
trigger, do not change the level of the TI00n pin or its alternate-function port pin.
Because the external trigger is valid even in this case, the timer is cleared and started even
at the level of the TI00n pin or its alternate-function port pin, resulting in the output of a
pulse at an undesired timing.
Remark
n = 0, 1
User’s Manual U16819EJ3V0UD
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-36. Control Register Settings for One-Shot Pulse Output with Software Trigger
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n
7
6
5
4
TMC0n3
0
0
0
0
0
TMC0n2 TMC0n1
1
OVF0n
0
0
Free-running mode
(b) Capture/compare control register 0n (CRC0n)
CRC0n
7
6
5
4
3
0
0
0
0
0
CRC0n2 CRC0n1 CRC0n0
0
0/1
0
CR00n as compare register
CR01n as compare register
(c) 16-bit timer output control register 0n (TOC0n)
7
TOC0n
OSPT0n OSPE0n TOC0n4
0
0
1
LVS0n
LVR0n
TOC0n1
TOE0n
0/1
0/1
1
1
1
Enables TO0n output.
Inverts output upon match
between TM0n and CR00n.
Specifies initial value of
TO0n output F/F (setting “11” is prohibited.)
Inverts output upon match
between TM0n and CR01n.
Sets one-shot pulse output mode.
Set to 1 for output.
(d) Prescaler mode register 0n (PRM0n)
PRM0n
ES1n1
ES1n0
ES0n1
ES0n0
3
2
0/1
0/1
0/1
0/1
0
0
PRM0n1 PRM0n0
0/1
0/1
Selects count clock.
Setting invalid
(setting “10” is prohibited.)
Setting invalid
(setting “10” is prohibited.)
Caution Do not set the CR00n and CR01n registers to 0000H.
Remark
184
n = 0, 1
User’s Manual U16819EJ3V0UD
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-37. Timing of One-Shot Pulse Output Operation with Software Trigger
Set TMC0n to 04H
(TM0n count starts)
Count clock
TM0n count 0000H 0001H
N
N+1
0000H
N–1
N
M–1
M
M+1 M+2
CR01n set value
N
N
N
N
CR00n set value
M
M
M
M
OSPT0n
INTTM01n
INTTM00n
TO0n pin output
Caution 16-bit timer counter 0n starts operating as soon as a value other than 00 (operation stop mode) is
set to the TMC0n3 and TMC0n2 bits.
Remark
N M, the output becomes active with the CR00n register
and inactive with the CR01n register. Do not set N to M.
Caution Do not input the external trigger again while the one-shot pulse is output.
To output the one-shot pulse again, wait until the current one-shot pulse output is completed.
Remark
n = 0, 1
User’s Manual U16819EJ3V0UD
185
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-38. Control Register Settings for One-Shot Pulse Output with External Trigger
(with Rising Edge Specified)
(a) 16-bit timer mode control register 0n (TMC0n)
TMC0n
7
6
5
4
0
0
0
0
TMC0n3 TMC0n2 TMC0n1
1
0
OVF0n
0
0
Clears and starts at
valid edge of TI00n pin.
(b) Capture/compare control register 0n (CRC0n)
CRC0n
7
6
5
4
3
0
0
0
0
0
CRC0n2 CRC0n1 CRC0n0
0
0/1
0
CR00n used as compare register
CR01n used as compare register
(c) 16-bit timer output control register 0n (TOC0n)
7
TOC0n
OSPT0n OSPE0n TOC0n4
0
0
1
1
LVS0n
LVR0n
TOC0n1
TOE0n
0/1
0/1
1
1
Enables TO0n output.
Inverts output upon match
between TM0n and CR00n.
Specifies initial value of
TO0n output F/F (setting “11” is prohibited.)
Inverts output upon match
between TM0n and CR01n.
Sets one-shot pulse output mode.
(d) Prescaler mode register 0n (PRM0n)
PRM0n
ES1n1
ES1n0
ES0n1
ES0n0
3
2
0/1
0/1
0
1
0
0
PRM0n1 PRM0n0
0/1
0/1
Selects count clock
(setting “11” is prohibited).
Specifies the rising edge
for pulse width detection.
Setting invalid
(setting “10” is prohibited.)
Caution Do not set the CR00n and CR01n registers to 0000H.
Remark
186
n = 0, 1
User’s Manual U16819EJ3V0UD
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-39. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)
When TMC0n is set to 08H
(TM0n count starts)
t
Count clock
TM0n count value 0000H 0001H
0000H
N
N+1 N+2
M–2 M–1
M
M+1 M+2
CR01n set value
N
N
N
N
CR00n set value
M
M
M
M
TI00n pin input
INTTM01n
INTTM00n
TO0n pin output
Caution 16-bit timer counter 0n starts operating as soon as a value other than 00 (operation stop mode) is
set to the TMC0n3 and TMC0n2 bits.
Remark
N
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