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Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
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When exporting the products or technology described in this document, you should comply with the applicable export control
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“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
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User’s Manual
78K0/LE2
8-Bit Single-Chip Microcontrollers
With LCD Controller/Driver
μPD78F0361
μPD78F0362
μPD78F0363
μPD78F0363D
Document No. U17734EJ2V0UD00 (2nd edition)
Date Published July 2006 NS CP(K)
2005
Printed in Japan
[MEMO]
2
User’s Manual U17734EJ2V0UD
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
User’s Manual U17734EJ2V0UD
3
EEPROM is a trademark of NEC Electronics Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
4
User’s Manual U17734EJ2V0UD
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
• The information in this document is current as of July, 2006. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
• NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
User’s Manual U17734EJ2V0UD
5
INTRODUCTION
Readers
This manual is intended for user engineers who wish to understand the functions of the
78K0/LE2 and design and develop application systems and programs for these devices.
The target products are as follows.
78K0/LE2: μPD78F0361, 78F0362, 78F0363, 78F0363D
Purpose
This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization
The 78K0/LE2 manual is separated into two parts: this manual and the instructions
edition (common to the 78K/0 Series).
78K0/LE2
78K/0 Series
User’s Manual
User’s Manual
(This Manual)
Instructions
• Pin functions
• CPU functions
• Internal block functions
• Instruction set
• Interrupts
• Explanation of each instruction
• Other on-chip peripheral functions
• Electrical specifications
How to Read This Manual
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark “” shows major
revised points. The revised points can be easily searched by copying an “” in
the PDF file and specifying it in the “Find what:” field.
• How to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a
reserved word in the RA78K0, and is defined as an sfr variable using the
#pragma sfr directive in the CC78K0.
• To check the details of a register when you know the register name:
→ Refer to APPENDIX B REGISTER INDEX.
• To know details of the 78K/0 Series instructions:
→ Refer to the separate document 78K/0 Series Instructions User’s Manual
(U12326E).
6
User’s Manual U17734EJ2V0UD
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note:
Footnote for item marked with Note in the text
Caution:
Information requiring particular attention
Remark:
Supplementary information
... ×××× or ××××B
Numerical representations: Binary
Related Documents
Decimal
... ××××
Hexadecimal
... ××××H
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
78K0/LE2 User’s Manual
This manual
78K/0 Series Instructions User’s Manual
U12326E
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name
RA78K0 Ver. 3.80 Assembler Package
CC78K0 Ver. 3.70 C Compiler
ID78K0-QB Ver. 2.90 Integrated Debugger
Document No.
Operation
U17199E
Language
U17198E
Structured Assembly Language
U17197E
Operation
U17201E
Language
U17200E
Operation
U17437E
PM plus Ver. 5.20
U16934E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name
Document No.
QB-78K0LX2 In-Circuit Emulator
U17468E
QB-78K0MINI On-Chip Debug Emulator
U17029E
Documents Related to Flash Memory Programming
Document Name
PG-FP4 Flash Memory Programmer User’s Manual
Document No.
U15260E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
User’s Manual U17734EJ2V0UD
7
Other Documents
Document Name
Document No.
SEMICONDUCTOR SELECTION GUIDE − Products and Packages −
X13769X
Semiconductor Device Mount Manual
Note
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
8
User’s Manual U17734EJ2V0UD
CONTENTS
CHAPTER 1 OUTLINE ............................................................................................................................ 17
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Features ........................................................................................................................................ 17
Applications.................................................................................................................................. 18
Ordering Information ................................................................................................................... 18
Pin Configuration (Top View)...................................................................................................... 19
78K0/Lx2 Series Lineup............................................................................................................... 21
Block Diagram .............................................................................................................................. 23
Outline of Functions .................................................................................................................... 24
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 26
2.1 Pin Function List .......................................................................................................................... 26
2.2 Description of Pin Functions ...................................................................................................... 29
2.2.1 P00, P01 (port 0) .............................................................................................................................29
2.2.2 P10 to P17 (port 1)...........................................................................................................................29
2.2.3 P20 to P24 (port 2)...........................................................................................................................30
2.2.4 P30 to P33 (port 3)...........................................................................................................................30
2.2.5 P60, P61 (port 6) .............................................................................................................................31
2.2.6 P120 to P124 (port 12).....................................................................................................................31
2.2.7 AVREF ...............................................................................................................................................32
2.2.8 AVSS .................................................................................................................................................32
2.2.9 S0 to S19 .........................................................................................................................................32
2.2.10 COM0 to COM3 .............................................................................................................................32
2.2.11 LVDD ...............................................................................................................................................32
2.2.12 LVSS ...............................................................................................................................................32
2.2.13 VLC0 to VLC2 ....................................................................................................................................32
2.2.14 CAPH, CAPL .................................................................................................................................33
2.2.15 RESET...........................................................................................................................................33
2.2.16 REGC ............................................................................................................................................33
2.2.17 VDD .................................................................................................................................................33
2.2.18 VSS .................................................................................................................................................33
2.2.19 FLMD0 ...........................................................................................................................................33
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................... 34
CHAPTER 3 CPU ARCHITECTURE...................................................................................................... 37
3.1 Memory Space .............................................................................................................................. 37
3.1.1 Internal program memory space ......................................................................................................42
3.1.2 Internal data memory space ............................................................................................................43
3.1.3 Special function register (SFR) area ................................................................................................44
3.1.4 Data memory addressing.................................................................................................................44
3.2 Processor Registers .................................................................................................................... 47
3.2.1 Control registers...............................................................................................................................47
3.2.2 General-purpose registers ...............................................................................................................51
3.2.3 Special function registers (SFRs).....................................................................................................52
3.3 Instruction Address Addressing ................................................................................................ 56
User’s Manual U17734EJ2V0UD
9
3.3.1 Relative addressing......................................................................................................................... 56
3.3.2 Immediate addressing..................................................................................................................... 57
3.3.3 Table indirect addressing ................................................................................................................ 58
3.3.4 Register addressing ........................................................................................................................ 58
3.4 Operand Address Addressing .................................................................................................... 59
3.4.1 Implied addressing .......................................................................................................................... 59
3.4.2 Register addressing ........................................................................................................................ 60
3.4.3 Direct addressing ............................................................................................................................ 61
3.4.4 Short direct addressing ................................................................................................................... 62
3.4.5 Special function register (SFR) addressing ..................................................................................... 63
3.4.6 Register indirect addressing............................................................................................................ 64
3.4.7 Based addressing ........................................................................................................................... 65
3.4.8 Based indexed addressing.............................................................................................................. 66
3.4.9 Stack addressing............................................................................................................................. 67
CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 68
4.1 Port Functions .............................................................................................................................. 68
4.2 Port Configuration........................................................................................................................ 69
4.2.1 Port 0 .............................................................................................................................................. 70
4.2.2 Port 1 .............................................................................................................................................. 72
4.2.3 Port 2 .............................................................................................................................................. 77
4.2.4 Port 3 .............................................................................................................................................. 78
4.2.5 Port 6 .............................................................................................................................................. 80
4.2.6 Port 12 ............................................................................................................................................ 81
4.3 Registers Controlling Port Function .......................................................................................... 83
4.4 Port Function Operations ............................................................................................................ 87
4.4.1 Writing to I/O port ............................................................................................................................ 87
4.4.2 Reading from I/O port...................................................................................................................... 87
4.4.3 Operations on I/O port..................................................................................................................... 87
4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function............. 88
CHAPTER 5 CLOCK GENERATOR ...................................................................................................... 90
5.1
5.2
5.3
5.4
Functions of Clock Generator..................................................................................................... 90
Configuration of Clock Generator .............................................................................................. 91
Registers Controlling Clock Generator...................................................................................... 93
System Clock Oscillator ............................................................................................................ 102
5.4.1 X1 oscillator....................................................................................................................................102
5.4.2 XT1 oscillator .................................................................................................................................102
5.4.3 When subsystem clock is not used ................................................................................................105
5.4.4 Internal high-speed oscillator .........................................................................................................105
5.4.5 Internal low-speed oscillator...........................................................................................................105
5.4.6 Prescaler ........................................................................................................................................105
5.5 Clock Generator Operation ....................................................................................................... 106
5.6 Controlling Clock........................................................................................................................ 109
5.6.1 Example of controlling high-speed system clock............................................................................109
5.6.2 Example of controlling internal high-speed oscillation clock...........................................................112
5.6.3 Example of controlling subsystem clock.........................................................................................114
5.6.4 Example of controlling internal low-speed oscillation clock ............................................................116
10
User’s Manual U17734EJ2V0UD
5.6.5 Clocks supplied to CPU and peripheral hardware .........................................................................116
5.6.6 CPU clock status transition diagram ..............................................................................................117
5.6.7 Condition before changing CPU clock and processing after changing CPU clock .........................122
5.6.8 Time required for switchover of CPU clock and main system clock ...............................................123
5.6.9 Conditions before clock oscillation is stopped................................................................................124
5.6.10 Peripheral hardware and source clocks .......................................................................................125
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00........................................................................... 126
6.1
6.2
6.3
6.4
Functions of 16-Bit Timer/Event Counter 00 ........................................................................... 126
Configuration of 16-Bit Timer/Event Counter 00..................................................................... 127
Registers Controlling 16-Bit Timer/Event Counter 00 ............................................................ 131
Operation of 16-Bit Timer/Event Counter 00 ........................................................................... 138
6.4.1 Interval timer operation ..................................................................................................................138
6.4.2 Square wave output operation .......................................................................................................141
6.4.3 External event counter operation ...................................................................................................144
6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input..........................................147
6.4.5 Free-running timer operation .........................................................................................................160
6.4.6 PPG output operation ....................................................................................................................169
6.4.7 One-shot pulse output operation....................................................................................................172
6.4.8 Pulse width measurement operation..............................................................................................177
6.5 Special Use of TM00 .................................................................................................................. 185
6.5.1 Rewriting CR010 during TM00 operation.......................................................................................185
6.5.2 Setting LVS00 and LVR00 .............................................................................................................185
6.6 Cautions for 16-Bit Timer/Event Counter 00 ........................................................................... 187
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 .......................................................... 191
7.1
7.2
7.3
7.4
Functions of 8-Bit Timer/Event Counters 50 and 51............................................................... 191
Configuration of 8-Bit Timer/Event Counters 50 and 51 ........................................................ 191
Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ............................................... 194
Operations of 8-Bit Timer/Event Counters 50 and 51............................................................. 199
7.4.1 Operation as interval timer.............................................................................................................199
7.4.2 Operation as external event counter ..............................................................................................201
7.4.3 Square-wave output operation .......................................................................................................202
7.4.4 PWM output operation ...................................................................................................................203
7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 ............................................................... 207
CHAPTER 8 8-BIT TIMERS H0 AND H1 .......................................................................................... 208
8.1
8.2
8.3
8.4
Functions of 8-Bit Timers H0 and H1 ....................................................................................... 208
Configuration of 8-Bit Timers H0 and H1................................................................................. 208
Registers Controlling 8-Bit Timers H0 and H1 ........................................................................ 212
Operation of 8-Bit Timers H0 and H1 ....................................................................................... 217
8.4.1 Operation as interval timer/square-wave output ............................................................................217
8.4.2 Operation as PWM output..............................................................................................................220
8.4.3 Carrier generator operation (8-bit timer H1 only) ...........................................................................226
CHAPTER 9 WATCH TIMER ............................................................................................................... 233
9.1 Functions of Watch Timer ......................................................................................................... 233
User’s Manual U17734EJ2V0UD
11
9.2 Configuration of Watch Timer................................................................................................... 234
9.3 Register Controlling Watch Timer ............................................................................................ 235
9.4 Watch Timer Operations............................................................................................................ 237
9.4.1 Watch timer operation ....................................................................................................................237
9.4.2 Interval timer operation ..................................................................................................................237
9.5 Cautions for Watch Timer.......................................................................................................... 238
CHAPTER 10 WATCHDOG TIMER ..................................................................................................... 239
10.1
10.2
10.3
10.4
Functions of Watchdog Timer................................................................................................. 239
Configuration of Watchdog Timer .......................................................................................... 240
Register Controlling Watchdog Timer.................................................................................... 241
Operation of Watchdog Timer................................................................................................. 242
10.4.1 Controlling operation of watchdog timer.......................................................................................242
10.4.2 Setting overflow time of watchdog timer.......................................................................................243
10.4.3 Setting window open period of watchdog timer ............................................................................244
CHAPTER 11 CLOCK OUTPUT CONTROLLER ............................................................................... 246
11.1
11.2
11.3
11.4
Functions of Clock Output Controller .................................................................................... 246
Configuration of Clock Output Controller ............................................................................. 247
Registers Controlling Clock Output Controller..................................................................... 247
Operations of Clock Output Controller .................................................................................. 249
CHAPTER 12 A/D CONVERTER ......................................................................................................... 250
12.1
12.2
12.3
12.4
Function of A/D Converter....................................................................................................... 250
Configuration of A/D Converter .............................................................................................. 251
Registers Used in A/D Converter............................................................................................ 253
A/D Converter Operations ....................................................................................................... 261
12.4.1 Basic operations of A/D converter................................................................................................261
12.4.2 Input voltage and conversion results............................................................................................263
12.4.3 A/D converter operation mode .....................................................................................................264
12.5 How to Read A/D Converter Characteristics Table............................................................... 266
12.6 Cautions for A/D Converter ..................................................................................................... 268
CHAPTER 13 SERIAL INTERFACE UART0 ...................................................................................... 272
13.1
13.2
13.3
13.4
Functions of Serial Interface UART0 ...................................................................................... 272
Configuration of Serial Interface UART0 ............................................................................... 273
Registers Controlling Serial Interface UART0....................................................................... 276
Operation of Serial Interface UART0 ...................................................................................... 281
13.4.1 Operation stop mode....................................................................................................................281
13.4.2 Asynchronous serial interface (UART) mode ...............................................................................282
13.4.3 Dedicated baud rate generator.....................................................................................................288
CHAPTER 14 SERIAL INTERFACE UART6 ...................................................................................... 293
14.1 Functions of Serial Interface UART6 ...................................................................................... 293
14.2 Configuration of Serial Interface UART6 ............................................................................... 297
14.3 Registers Controlling Serial Interface UART6....................................................................... 300
12
User’s Manual U17734EJ2V0UD
14.4 Operation of Serial Interface UART6...................................................................................... 309
14.4.1 Operation stop mode ...................................................................................................................309
14.4.2 Asynchronous serial interface (UART) mode ...............................................................................310
14.4.3 Dedicated baud rate generator ....................................................................................................323
CHAPTER 15 SERIAL INTERFACE CSI10 ........................................................................................ 330
15.1
15.2
15.3
15.4
Functions of Serial Interface CSI10........................................................................................ 330
Configuration of Serial Interface CSI10 ................................................................................. 330
Registers Controlling Serial Interface CSI10......................................................................... 332
Operation of Serial Interface CSI10 ........................................................................................ 335
15.4.1 Operation stop mode ...................................................................................................................335
15.4.2 3-wire serial I/O mode..................................................................................................................336
CHAPTER 16 SERIAL INTERFACE IIC0 ........................................................................................... 347
16.1
16.2
16.3
16.4
Functions of Serial Interface IIC0 ........................................................................................... 347
Configuration of Serial Interface IIC0..................................................................................... 350
Registers to Control Serial Interface IIC0 .............................................................................. 353
I2C Bus Mode Functions .......................................................................................................... 366
16.4.1 Pin configuration ..........................................................................................................................366
16.5 I2C Bus Definitions and Control Methods .............................................................................. 367
16.5.1 Start conditions ............................................................................................................................367
16.5.2 Addresses....................................................................................................................................368
16.5.3 Transfer direction specification ....................................................................................................368
16.5.4 Acknowledge (ACK).....................................................................................................................369
16.5.5 Stop condition ..............................................................................................................................370
16.5.6 Wait..............................................................................................................................................371
16.5.7 Canceling wait..............................................................................................................................373
16.5.8 Interrupt request (INTIIC0) generation timing and wait control ....................................................373
16.5.9 Address match detection method ................................................................................................374
16.5.10 Error detection ...........................................................................................................................374
16.5.11 Extension code ..........................................................................................................................375
16.5.12 Arbitration ..................................................................................................................................376
16.5.13 Wakeup function ........................................................................................................................377
16.5.14 Communication reservation .......................................................................................................378
16.5.15 Other cautions ...........................................................................................................................381
16.5.16 Communication operations ........................................................................................................383
16.5.17 Timing of I2C interrupt request (INTIIC0) occurrence .................................................................390
16.6 Timing Charts ........................................................................................................................... 411
16.7 Communication with LCD Controller/Driver.......................................................................... 418
16.7.1 System configuration ...................................................................................................................418
16.7.2 Write operation.............................................................................................................................419
16.7.3 Read operation ............................................................................................................................422
CHAPTER 17 LCD CONTROLLER/DRIVER....................................................................................... 426
17.1 Functions of LCD Controller/Driver ....................................................................................... 426
17.2 Configuration of LCD Controller/Driver ................................................................................. 427
17.3 Registers Controlling LCD Controller/Driver ........................................................................ 430
User’s Manual U17734EJ2V0UD
13
17.4
17.5
17.6
17.7
Setting LCD Controller/Driver ................................................................................................. 436
LCD Display Data Memory....................................................................................................... 438
Common and Segment Signals .............................................................................................. 439
Display Modes .......................................................................................................................... 443
17.7.1 Static display example .................................................................................................................443
17.7.2 Two-time-slice display example ...................................................................................................446
17.7.3 Three-time-slice display example.................................................................................................449
17.7.4 Four-time-slice display example...................................................................................................453
17.8 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2 ....................................................... 456
17.8.1 Internal resistance division method ..............................................................................................456
17.8.2 External resistance division method.............................................................................................458
17.8.3 Internal voltage boosting method .................................................................................................459
CHAPTER 18 INTERRUPT FUNCTIONS ............................................................................................ 460
18.1
18.2
18.3
18.4
Interrupt Function Types ......................................................................................................... 460
Interrupt Sources and Configuration ..................................................................................... 460
Registers Controlling Interrupt Functions............................................................................. 463
Interrupt Servicing Operations ............................................................................................... 471
18.4.1 Maskable interrupt acknowledgement..........................................................................................471
18.4.2 Software interrupt request acknowledgement ..............................................................................473
18.4.3 Multiple interrupt servicing ...........................................................................................................474
18.4.4 Interrupt request hold ...................................................................................................................477
CHAPTER 19 STANDBY FUNCTION .................................................................................................. 478
19.1 Standby Function and Configuration ..................................................................................... 478
19.1.1 Standby function ..........................................................................................................................478
19.1.2 Registers controlling standby function..........................................................................................478
19.2 Standby Function Operation ................................................................................................... 481
19.2.1 HALT mode ..................................................................................................................................481
19.2.2 STOP mode .................................................................................................................................486
CHAPTER 20 RESET FUNCTION........................................................................................................ 491
20.1 Register for Confirming Reset Source ................................................................................... 499
CHAPTER 21 POWER-ON-CLEAR CIRCUIT...................................................................................... 500
21.1
21.2
21.3
21.4
Functions of Power-on-Clear Circuit...................................................................................... 500
Configuration of Power-on-Clear Circuit ............................................................................... 501
Operation of Power-on-Clear Circuit ...................................................................................... 501
Cautions for Power-on-Clear Circuit ...................................................................................... 504
CHAPTER 22 LOW-VOLTAGE DETECTOR ....................................................................................... 506
22.1
22.2
22.3
22.4
Functions of Low-Voltage Detector........................................................................................ 506
Configuration of Low-Voltage Detector ................................................................................. 506
Registers Controlling Low-Voltage Detector......................................................................... 507
Operation of Low-Voltage Detector ........................................................................................ 510
22.4.1 When used as reset .....................................................................................................................511
14
User’s Manual U17734EJ2V0UD
22.4.2 When used as interrupt................................................................................................................516
22.5 Cautions for Low-Voltage Detector ........................................................................................ 521
CHAPTER 23 OPTION BYTE............................................................................................................... 524
23.1
23.2
Functions of Option Bytes .................................................................................................... 524
Format of Option Byte ........................................................................................................... 525
CHAPTER 24 FLASH MEMORY.......................................................................................................... 528
24.1
24.2
24.3
24.4
24.5
Internal Memory Size Switching Register.............................................................................. 528
Writing with Flash Programmer.............................................................................................. 529
Programming Environment..................................................................................................... 532
Communication Mode.............................................................................................................. 532
Handling of Pins on Board ...................................................................................................... 534
24.5.1 FLMD0 pin ...................................................................................................................................534
24.5.2 Serial interface pins .....................................................................................................................534
24.5.3 RESET pin ...................................................................................................................................536
24.5.4 Port pins.......................................................................................................................................536
24.5.5 REGC pin.....................................................................................................................................536
24.5.6 Other signal pins ..........................................................................................................................536
24.5.7 Power supply ...............................................................................................................................536
24.6 Programming Method .............................................................................................................. 537
24.6.1 Controlling flash memory .............................................................................................................537
24.6.2 Flash memory programming mode ..............................................................................................537
24.6.3 Selecting communication mode ...................................................................................................538
24.6.4 Communication commands .........................................................................................................539
24.7 Security Settings...................................................................................................................... 540
24.8 Flash Memory Programming by Self-Writing ........................................................................ 542
24.8.1 Boot swap function.......................................................................................................................544
CHAPTER 25 ON-CHIP DEBUG FUNCTION (μPD78F0363D ONLY) ............................................. 546
25.1 On-Chip Debug Security ID ..................................................................................................... 547
CHAPTER 26 INSTRUCTION SET ...................................................................................................... 548
26.1 Conventions Used in Operation List...................................................................................... 548
26.1.1 Operand identifiers and specification methods ............................................................................548
26.1.2 Description of operation column ..................................................................................................549
26.1.3 Description of flag operation column............................................................................................549
26.2 Operation List ........................................................................................................................... 550
26.3 Instructions Listed by Addressing Type ............................................................................... 558
CHAPTER 27 ELECTRICAL SPECIFICATIONS................................................................................. 561
CHAPTER 28 PACKAGE DRAWINGS................................................................................................ 582
CHAPTER 29 CAUTIONS FOR WAIT ................................................................................................ 584
User’s Manual U17734EJ2V0UD
15
29.1 Cautions for Wait...................................................................................................................... 584
29.2 Peripheral Hardware That Generates Wait ............................................................................ 585
APPENDIX A DEVELOPMENT TOOLS............................................................................................... 586
A.1
A.2
A.3
A.4
A.5
Software Package ...................................................................................................................... 589
Language Processing Software ............................................................................................... 589
Control Software ........................................................................................................................ 590
Flash Memory Writing Tools..................................................................................................... 590
Debugging Tools (Hardware).................................................................................................... 591
A.5.1 When using in-circuit emulator QB-78K0LX2.................................................................................591
A.5.2 When using on-chip debug emulator QB-78K0MINI ......................................................................592
A.6 Debugging Tools (Software)..................................................................................................... 592
APPENDIX B REGISTER INDEX ......................................................................................................... 593
B.1 Register Index (In Alphabetical Order with Respect to Register Names) ............................ 593
B.2 Register Index (In Alphabetical Order with Respect to Register Symbol)........................... 596
APPENDIX C REVISION HISTORY ..................................................................................................... 599
C.1 Major Revisions in This Edition ............................................................................................... 599
16
User’s Manual U17734EJ2V0UD
CHAPTER 1 OUTLINE
1.1 Features
{ Minimum instruction execution time can be changed from high speed (0.1 μs: @ 20 MHz operation with highspeed system clock) to ultra low-speed (122 μs: @ 32.768 kHz operation with subsystem clock)
{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
{ ROM, RAM capacities
Item
Program Memory
(ROM)
Data Memory
Internal High-Speed
Note
RAM
Part Number
μPD78F0361
Note
16 KB
768 bytes
μPD78F0362
24 KB
1 KB
μPD78F0363, 78F0363D
32 KB
Flash memory
LCD Display RAM
20 × 4 bits
Note The internal flash memory and internal high-speed RAM capacities can be changed using the internal
memory size switching register (IMS).
{ On-chip single-power-supply flash memory
{ Self-programming (with boot swap function)
{ On-chip debug function (μPD78F0363D only)
{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
{ On-chip watchdog timer (operable with internal low-speed oscillation clock)
{ LCD controller/driver (internal voltage boosting, external resistance division, and internal resistance division are
switchable)
Segment signals: 20, Common signals: 4
{ On-chip clock output controller
{ I/O ports: 24
{ Timer: 7 channels
• 16-Bit Timer/Event Counter: 1 channel
• 8-Bit Timer/Event Counter: 2 channels
• 8-Bit Timer:
2 channels
• Watch Timer:
1 channel
• Watchdog Timer:
1 channel
{ Serial interface: 3 channels
• UART (LIN (Local Interconnect Network)-bus supported): 1 channel
• CSI/UARTNote:
1 channel
• I2C:
1 channel
Note Select either of the functions of these alternate-function pins.
{ 10-bit resolution A/D converter: 5 channels
{ Power supply voltage: VDD = 1.8 to 5.5 V
{ Operating ambient temperature: TA = −40 to +85°C
User’s Manual U17734EJ2V0UD
17
CHAPTER 1 OUTLINE
1.2 Applications
APS cameras, digital cameras, AV equipments, and household electrical appliances, etc.
1.3 Ordering Information
• Flash memory version (Lead-free products)
Part Number
μPD78F0361GB-UEU-A
μPD78F0362GB-UEU-A
μPD78F0363GB-UEU-A
μPD78F0363DGB-UEU-ANote
μPD78F0361GK-UET-A
μPD78F0362GK-UET-A
μPD78F0363GK-UET-A
μPD78F0363DGK-UET-ANote
Package
64-pin plastic LQFP (fine pitch) (10 × 10)
64-pin plastic LQFP (fine pitch) (10 × 10)
64-pin plastic LQFP (fine pitch) (10 × 10)
64-pin plastic LQFP (fine pitch) (10 × 10)
64-pin plastic LQFP (12 × 12)
64-pin plastic LQFP (12 × 12)
64-pin plastic LQFP (12 × 12)
64-pin plastic LQFP (12 × 12)
Note The μPD78F0363D has an on-chip debug function. Do not use this product for mass production, because its
reliability cannot be guaranteed after the on-chip debug function has been used, with respect to the number of
times the flash memory can be rewritten. NEC Electronics does not accept complaints about this product.
18
User’s Manual U17734EJ2V0UD
CHAPTER 1 OUTLINE
1.4 Pin Configuration (Top View)
• 64-pin plastic LQFP (fine pitch) (10 × 10)
RESET
SCL0/P60
SDA0/P61
P33/INTP4/TI51/TO51
P120/INTP0/EXLVI
P00/TI000
P01/TI010/TO00
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
AVSS
AVREF
P10/SCK10/TxD0
P11/SI10/RxD0
• 64-pin plastic LQFP (12 × 12)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P124/XT2/EXCLKS
P123/XT1
FLMD0
P122/X2/EXCLK/OCD0BNote
P121/X1/OCD0ANote
REGC
VSS
VDD
CAPH
CAPL
VLC0
VLC1
VLC2
COM0
COM1
COM2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P12/SO10
P13/TxD6
P14/RxD6
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
P30/INTP1
P31/INTP2/OCD1ANote
P32/INTP3/OCD1BNote
LVDD
LVSS
S19
S18
S17
S16
S15
COM3
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note μPD78F0363D (product with on-chip debug function) only.
Cautions 1. Connect the AVSS pin to VSS.
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF: recommended).
3. ANI0/P20 to ANI4/P24 are set in the analog input mode after release of reset.
User’s Manual U17734EJ2V0UD
19
CHAPTER 1 OUTLINE
Pin Identification
ANI0 to ANI4:
Analog input
REGC
Regulator capacitance
AVREF:
Analog reference voltage
RESET:
Reset
AVSS:
Analog ground
RxD0, RxD6:
Receive data
CAPH, CAPL:
LCD power supply
S0 to S19:
Segment output
capacitance control
SCK10:
Serial clock input/output
Common output
SCL0:
Serial clock input/output
COM0 to COM3:
EXCLK:
External clock input
SDA0:
Serial data input/output
(main system clock)
SI10:
Serial data input
External clock input
SO10:
Serial data output
(subsystem clock)
TI000, TI010:
Timer input
External potential input
TI50, TI51:
Timer input
for low-voltage detector
TO00:
Timer output
FLMD0:
Flash programming mode
TO50, TO51:
Timer output
INTP0 to INTP5:
External interrupt input
TOH0, TOH1:
Timer output
LVDD:
Power supply for
TxD0, TxD6:
Transmit data
LCD controller/driver
VDD:
Power supply
Ground for
VSS:
Ground
LCD controller/driver
VLC0 to VLC2:
LCD power supply
X1, X2:
Crystal oscillator
EXCLKS:
EXLVI:
LVSS:
Note
OCD0A
Note
, OCD0B
: On Chip Debug Input/Output
OCD1ANote, OCD1BNote: On Chip Debug Input/Output
P00, P01:
Port 0
P10 to P17:
Port 1
P20 to P24:
Port 2
P30 to P33:
Port 3
P60, P61:
Port 6
P120 to P124:
Port 12
Note
20
(main system clock)
XT1, XT2:
Crystal oscillator
(subsystem clock)
μPD78F0363D (product with on-chip debug function) only.
User’s Manual U17734EJ2V0UD
CHAPTER 1 OUTLINE
1.5 78K0/Lx2 Series Lineup
ROM
RAM
78K0/LE2
78K0/LF2
78K0/LG2
64 Pins
80 Pins
100 Pins
128 KB
7 KB
−
−
μPD78F0397DNote
μPD78F0397
96 KB
5 KB
−
μPD78F0386DNote
μPD78F0376DNote
μPD78F0386
μPD78F0376
μPD78F0396
60 KB
3 KB
−
μPD78F0385
μPD78F0375
μPD78F0395
48 KB
2 KB
−
μPD78F0384
μPD78F0374
μPD78F0394
32 KB
1 KB
μPD78F0363DNote
μPD78F0363
μPD78F0383
μPD78F0373
μPD78F0393
24 KB
1 KB
μPD78F0362
μPD78F0382
μPD78F0372
−
16 KB
768 B
μPD78F0361
−
−
Note Product with on-chip debug function
User’s Manual U17734EJ2V0UD
21
CHAPTER 1 OUTLINE
The list of functions in the 78K0/Lx2 Series is shown below.
Part Number
78K0/LE2
78K0/LF2
μPD78F036x
Item
μPD78F038x
64 Pins
Flash memory (KB)
RAM (KB)
80 Pins
32
24
32
48
60
96
24
32
48
60
96
32
48
60
96
128
0.75
1
1
1
1
2
3
5
1
1
2
3
5
1
2
3
5
7
4
6
−
−
4
Provided
0.1 μs (20 MHz: VDD = 4.0 to 5.5 V)/0.2 μs (10 MHz: VDD = 2.7 to 5.5 V)/
0.4 μs (5 MHz: VDD = 1.8 to 5.5 V)
Clock
Main
Minimum instruction
execution time
High-speed system
clock
20 MHz: VDD = 4.0 to 5.5 V/10 MHz: VDD = 2.7 to 5.5 V/5 MHz: VDD = 1.8 to 5.5 V
Internal high-speed
oscillation clock
8 MHz (TYP.): VDD = 1.8 to 5.5 V
Subclock
32.768 kHz (TYP.): VDD = 1.8 to 5.5 V
Port
Internal low-speed
oscillation clock
Total
240 kHz (TYP.): VDD = 1.8 to 5.5 V
24
Serial interface
Timer
16 bits (TM0)
34
1 ch
26
2 ch
1 ch
8 bits (TM5)
2 ch
8 bits (TMH)
2 ch
Watch
1 ch
WDT
1 ch
3-wire CSI/UART
2 ch
1 ch
1 ch
1 ch
2
I C bus
Segment signal
1 ch
Internal voltage boosting, external resistance division, and internal resistance division are switchable.
20
26
Common signal
10-bit A/D
External
5 ch
8 ch
6
40
−
8 ch
7
16
18
−
15
17
16
19
7 ch
RESET pin
8 ch
Provided
1.59 V ±0.15 V (Time for rising up to 1.8 V : 3.6 ms (MAX.))
POC
LVI
The detection level of the supply voltage is selectable in 16 steps.
WDT
Provided
Clock output
Provided
−
Multiplier/divider
On-chip debug function
36
4
Internal
Key interrupt
2 ch
1 ch
Note
UART supporting LINbus
Operating ambient
temperature
40
−
3-wire CSI
Type
LCD
−
4
VDD = 1.8 to 5.5 V
Regulator
Interrupt
100 Pins
24
Power supply voltage
μPD78F0363D only
−
Provided
μPD78F0376D only
Provided
μPD78F0386D only
TA = −40 to +85°C
Note Select either of the functions of these alternate-function pins.
22
μPD78F039x
16
Bank (flash memory)
Reset
78K0/LG2
μPD78F037x
User’s Manual U17734EJ2V0UD
−
Provided
μPD78F0397D only
CHAPTER 1 OUTLINE
1.6 Block Diagram
TO00/TI010/P01
TI000/P00 (LINSEL)
RxD6/P14 (LINSEL)
16-bit TIMER/
EVENT COUNTER 00
TOH0/P15
CPU part
PORT 0
2
P00, P01
PORT 1
8
P10 to P17
PORT 2
5
P20 to P24
8-bit TIMER H1
PORT 3
4
P30 to P33
INTERNAL
LOW-SPEED
OSCILLATOR
PORT 6
2
P60, P61
PORT 12
5
P120 to P124
5
ANI0/P20 to
ANI4/P24
8-bit TIMER H0
TOH1/P16
WATCHDOG TIMER
8-bit TIMER/
EVENT COUNTER 50
TI50/TO50/P17
78K/0
CPU
CORE
FLASH
MEMORY
A/D
CONVERTER
AVSS
RxD6/P14 (LINSEL)
INTP0/P120 (LINSEL)
8-bit TIMER/
EVENT COUNTER 51
TI51/TO51/P33
INTERRUPT
CONTROL
WATCH TIMER
RxD0/P11
TxD0/P10
SERIAL
INTERFACE UART0
RxD6/P14
TxD6/P13
SERIAL
INTERFACE UART6
LINSEL
SI10/P11
SO10/P12
SCK10/P10
SERIAL
INTERFACE CSI10
INTERNAL
EXPANSION
RAM
S0 to S19
4
INTP1/P30 to
INTP4/P33
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
POC/LVI
CONTROL
ON-CHIP
DEBUG
SYSTEM
CONTROL
INTERNAL
HIGH-SPEED
OSCILLATOR
CLOCK OUTPUT
CONTROL
RESET CONTROL
4
INTP5/P16
INTERNAL
HIGH-SPEED
RAM
SERIAL
INTERFACE IIC0
P61/SDA0
P60/SCL0
COM0-COM3
VLC0-VLC2
CAPH
CAPL
LVDD
LVSS
AVREF
VDD
VSS FLMD0
VOLTAGE
REGULATOR
EXLVI/P120
OCD0ANote/X1, OCD1ANote/P31
OCD0BNote/X2, OCD1BNote/P32
RESET
X1/P121
X2/EXCLK/P122
XT1/P123
XT2/EXCLKS/P124
REGC
LCD
CONTROLLER
DRIVER
RAM SPACE
FOR
LCD DATA
LCD part
Note
μPD78F0363D only.
User’s Manual U17734EJ2V0UD
23
CHAPTER 1 OUTLINE
1.7 Outline of Functions
(1/2)
μPD78F0361
Item
Internal
memory
Flash memory
(self-programming
Note1
supported)
High-speed RAM
Note1
LCD display RAM
μPD78F0362
16 KB
24 KB
768 bytes
1 KB
μPD78F0363
μPD78F0363D
32 KB
20 × 4 bits
Memory space
64 KB
Main system High-speed system
clock
clock
(oscillation
frequency)
Internal high-speed
oscillation clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 4.0 to 5.5 V, 1 to 10 MHz: VDD = 2.7 to 5.5 V,
1 to 5 MHz: VDD = 1.8 to 5.5 V
Internal oscillation
8 MHz (TYP.): VDD = 1.8 to 5.5 V
Subsystem clock
(oscillation frequency)
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): VDD = 1.8 to 5.5 V
Internal low-speed oscillation clock
(for TMH1, WDT)
Internal oscillation
240 kHz (TYP.): VDD = 1.8 to 5.5 V
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time 0.1 μs (high-speed system clock: @ fXH = 20 MHz operation)
0.25 μs (internal high-speed oscillation clock: @ fRH = 8 MHz (TYP.) operation)
122 μs (subsystem clock: @ fSUB = 32.768 kHz operation)
Instruction set
•
•
•
•
8-bit operation, 16-bit operation
Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
Bit manipulate (set, reset, test, and Boolean operation)
BCD adjust, etc.
I/O ports
CMOS I/O: 24
Timers
•
•
•
•
•
Timer outputs
Clock output
16-bit timer/event counter: 1 channel
8-bit timer/event counter: 2 channels
8-bit timer:
2 channels
Watch timer:
1 channel
Watchdog timer:
1 channel
5 (PWM output: 4, PPG output: 1)
• 156.25 kHz, 312.5 kHz (peripheral hardware clock: @ fPRS = 20 MHz operation)
• 32.768 kHz (subsystem clock: @ fSUB = 32.768 kHz operation)
A/D converter
10-bit resolution × 5 channels (AVREF = 2.3 to 5.5 V)
Serial interface
• UART supporting LIN-bus: 1 channel
Note2
• 3-wire serial I/O/UART : 1 channel
2
• I C bus:
1 channel
Notes 1.
The internal flash memory and internal high-speed RAM capacities can be changed using the internal
memory size switching register (IMS).
2.
24
Select either of the functions of these alternate-function pins.
User’s Manual U17734EJ2V0UD
CHAPTER 1 OUTLINE
(2/2)
μPD78F0361
Item
LCD controller/driver
μPD78F0362
μPD78F0363
μPD78F0363D
• Internal voltage boosting, external resistance division, and internal resistance division are
switchable.
• Segment signal outputs: 20
• Common signal outputs: 4
Vectored
Internal
interrupt sources External
16
Reset
•
•
•
•
6
Reset using RESET pin
Internal reset by watchdog timer
Internal reset by power-on-clear
Internal reset by low-voltage detector
−
On-chip debug function
Provided
Power supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = −40 to +85°C
Package
• 64-pin plastic LQFP (fine pitch) (10 × 10)
• 64-pin plastic LQFP (12 × 12)
An outline of the timer is shown below.
16-Bit Timer/
Event Counter
00
Function
Interval timer
8-Bit Timer/
Event Counters
50 and 51
8-Bit Timers H0 and H1
TM00
TM50
TM51
TMH0
TMH1
1 channel
1 channel
1 channel
1 channel
1 channel
Watch
Timer
Watchdog
Timer
1 channel
−
Note 1
1 channel
1 channel
1 channel
−
−
−
−
PPG output
1 output
−
−
−
−
−
−
PWM output
−
1 output
1 output
1 output
1 output
−
−
Pulse width
measurement
2 inputs
−
−
−
−
−
−
Square-wave
output
1 output
1 output
1 output
1 output
1 output
−
−
−
−
−
−
1 output
−
−
1 channel
−
External event
counter
Carrier generator
Note 2
Watch timer
−
−
−
−
−
Note 1
Watchdog timer
Interrupt source
Notes 1.
2.
−
−
−
−
−
−
1 channel
2
1
1
1
1
1
−
In the watch timer, the watch timer function and interval timer function can be used simultaneously.
TM51 and TMH1 can be used in combination as a carrier generator mode.
User’s Manual U17734EJ2V0UD
25
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
There are three types of pin I/O buffer power supplies: AVREF, LVDD, and VDD. The relationship between these
power supplies and the pins is shown below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply
Corresponding Pins
AVREF
P20 to P24
LVDD
CAPH, CAPL, COM0 to COM3, S0 to S19, VLC0 to VLC2
VDD
Pins other than above
(1) Port pins
Pin Name
P00
I/O
I/O
Function
Port 0.
After Reset
Input
Alternate Function
TI000
2-bit I/O port.
Input/output can be specified in 1-bit units.
P01
TI010/TO00
Use of an on-chip pull-up resistor can be specified by a
software setting.
I/O
P10
Port 1.
Input
8-bit I/O port.
P11
SI10/RxD0
Input/output can be specified in 1-bit units.
P12
SO10
Use of an on-chip pull-up resistor can be specified by a
P13
SCK10/TxD0
TxD6
software setting.
P14
RxD6
P15
TOH0
P16
TOH1/INTP5
P17
TI50/TO50
P20 to P24
I/O
Port 2.
Input
ANI0 to ANI4
Input
INTP1 to INTP3
5-bit I/O port.
Input/output can be specified in 1-bit units.
P30
I/O
4-bit I/O port.
P31
Input/output can be specified in 1-bit units.
P32
Use of an on-chip pull-up resistor can be specified by a
P33
P60
Port 3.
Port 6.
Input
2-bit I/O port.
P61
Note
INTP3/OCD1B
Note
INTP4/TI51/TO51
software setting.
I/O
INTP2/OCD1A
SCL0
SDA0
Output of P60 and P61 is N-ch open-drain output (6 V
tolerance).
Input/output can be specified in 1-bit units.
P120
P121
P122
P123
I/O
Port 12.
Input
5-bit I/O port.
X1/OCD0A
Input/output can be specified in 1-bit units.
Only for P120, use of an on-chip pull-up resistor can be
specified by a software setting.
P124
Note
26
INTP0/EXLVI
Note
X2/EXCLK/OCD0B
XT1
XT2/EXCLKS
μPD78F0363D only.
User’s Manual U17734EJ2V0UD
Note
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Pin Name
(1/2)
I/O
Input
INTP0
Function
External interrupt request input for which the valid edge (rising
After Reset
P120/EXLVI
Input
edge, falling edge, or both rising and falling edges) can be
INTP1
Alternate Function
P30
specified
P31/OCD1A
Note
INTP3
P32/OCD1B
Note
INTP4
P33/TI51/TO51
INTP5
P16/TOH1
INTP2
SI10
Input
Serial data input to serial interface
Input
P11/RxD0
SO10
Output
Serial data output from serial interface
Input
P12
SDA0
I/O
Serial data I/O for serial interface
Input
P61
SCK10
I/O
Clock input/output for serial interface
Input
P10/TxD0
SCL0
P60
RxD0
Input
Serial data input to asynchronous serial interface
P11/SI10
Input
RxD6
P14
Output
TxD0
Serial data output from asynchronous serial interface
Input
P10/SCK10
TxD6
P13
Input
TI000
External count clock input to 16-bit timer/event counter 00
Input
P00
Capture trigger input to capture registers (CR000, CR010) of
16-bit timer/event counter 00
Capture trigger input to capture register (CR000) of 16-bit
TI010
P01/TO00
timer/event counter 00
TO00
Output
16-bit timer/event counter 00 output
Input
P01/TI010
TI50
Input
External count clock input to 8-bit timer/event counter 50
Input
P17/TO50
TI51
External count clock input to 8-bit timer/event counter 51
Output
TO50
8-bit timer/event counter 50 output
P33/TO51/INTP4
Input
P17/TI50
TO51
8-bit timer/event counter 51 output
P33/TI51/INTP4
TOH0
8-bit timer H0 output
P15
TOH1
8-bit timer H1 output
P16/INTP5
ANI0 to ANI4
Input
A/D converter analog input
AVREF
Input
A/D converter reference voltage input and positive power
Input
P20 to P24
−
−
−
−
supply for port 2
−
AVSS
A/D converter ground potential. Make the same potential as
VSS.
S0 to S19
Output
LCD controller/driver segment signal outputs
Output
−
COM0 to COM3
Output
LCD controller/driver common signal outputs
Output
−
LVDD
−
Positive power supply for LCD controller/driver
−
−
LVSS
−
Ground potential for LCD controller/driver
−
−
VLC0 to VLC2
−
LCD drive voltage
−
−
CAPH
−
LCD drive voltage booster capacitor connection
−
−
CAPL
−
Note
μPD78F0363D only.
User’s Manual U17734EJ2V0UD
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Pin Name
REGC
(2/2)
I/O
Function
After Reset
Alternate Function
−
Connecting regulator output (2.5 V) stabilization capacitance
−
−
for internal operation.
Connect to VSS via a capacitor (0.47 to 1 μF: recommended).
−
−
RESET
Input
System reset input
EXLVI
Input
Potential input for external low-voltage detection
Input
P120/INTP0
X1
Input
Connecting resonator for main system clock
Input
P121/OCD0A
X2
−
Note
Note
P122/EXCLK/OCD0B
EXCLK
Input
External clock input for main system clock
Input
P122/X2/OCD0B
XT1
Input
Connecting resonator for subsystem clock
Input
P123
XT2
−
EXCLKS
Input
P124/EXCLKS
External clock input for subsystem clock
Input
P124/XT2
VDD
−
Positive power supply
−
−
VSS
−
Ground potential
−
−
−
Flash memory programming mode setting
−
−
FLMD0
OCD0A
Note
OCD1A
Note
OCD0B
Note
OCD1B
Note
Note
28
Input
On-chip debug mode setting connection
Input
P121/X1
P31/INTP2
−
P122/X2/EXCLK
P32/INTP3
μPD78F0363D only.
User’s Manual U17734EJ2V0UD
Note
CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
2.2.1 P00, P01 (port 0)
P00 and P01 function as a 2-bit I/O port. These pins also function as timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 and P01 function as a 2-bit I/O port. P00 and P01 can be set to input or output port in 1-bit units using port
mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0
(PU0).
(2) Control mode
P00 and P01 function as timer I/O.
(a) TI000
This is the pin for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a
capture trigger signal to the capture registers (CR000, CR010) of 16-bit timer/event counter 00.
(b) TI010
This is the pin for inputting a capture trigger signal to the capture register (CR000) of 16-bit timer/event
counter 00.
(c) TO00
This is timer output pin.
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial
interface data I/O, clock I/O, and timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output port in 1-bit units using port
mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1
(PU1).
(2) Control mode
P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
(a) SI10
This is a serial interface serial data input pin.
(b) SO10
This is a serial interface serial data output pin.
(c) SCK10
This is a serial interface serial clock I/O pin.
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CHAPTER 2 PIN FUNCTIONS
(d) RxD0, RxD6
These are the serial data input pins of the asynchronous serial interface.
(e) TxD0, TxD6
These are the serial data output pins of the asynchronous serial interface.
(f) TI50
This is the pin for inputting an external count clock to 8-bit timer/event counter 50.
(g) TO50, TOH0, and TOH1
These are timer output pins.
(h) INTP5
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
2.2.3 P20 to P24 (port 2)
P20 to P24 function as a 5-bit I/O port. These pins also function as pins for A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P24 function as a 5-bit I/O port. P20 to P24 can be set to input or output port in 1-bit units using port
mode register 2 (PM2).
(2) Control mode
P20 to P24 function as A/D converter analog input pins (ANI0 to ANI4). When using these pins as analog input
pins, see (5) ANI0/P20 to ANI4/P24 in 12.6 Cautions for A/D Converter.
Caution P20/ANI0 to P24/ANI4 are set in the analog input mode after release of reset.
2.2.4 P30 to P33 (port 3)
P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and
timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output port in 1-bit units using port
mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3
(PU3).
(2) Control mode
P30 to P33 function as external interrupt request input and timer I/O.
(a) INTP1 to INTP4
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
30
User’s Manual U17734EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
(b) TI51
This is an external count clock input pin to 8-bit timer/event counter 51.
(c) TO51
This is a timer output pin.
Caution In the μPD78F0363D be sure to pull the P31 pin down after reset to prevent malfunction.
Remark P31 and P32 of the μPD78F0363D can be used as on-chip debug mode setting pins (OCD1A,
OCD1B) when the on-chip debug function is used. For details, see CHAPTER 25 ON-CHIP
DEBUG FUNCTION (μPD78F0363D ONLY).
2.2.5 P60, P61 (port 6)
P60 and P61 function as a 2-bit I/O port. These pins also function as pins for serial interface data I/O and clock I/O.
(1) Port mode
P60 and P61 function as a 2-bit I/O port. P60 and P61 can be set to input port or output port in 1-bit units using
port mode register 6 (PM6).
Output of P60 and P61 is N-ch open-drain output (6 V tolerance).
(2) Control mode
P60 and P61 function as serial interface data I/O and clock I/O.
(a) SDA0
This is a serial data I/O pin for serial interface IIC0.
Be sure to pull up this pin externally.
(b) SCL0
This is a serial clock I/O pin for serial interface IIC0.
Be sure to pull up this pin externally.
Caution In the 78K0/LE2, be sure to use the P60/SCL0 and P61/SDA0 as the serial clock I/O pin and serial data
I/O pin, respectively, in accordance with the specifications.
2.2.6 P120 to P124 (port 12)
P120 to P124 function as a 5-bit I/O port. These pins also function as pins for external interrupt request input,
potential input for external low-voltage detection, resonator for main system clock connection, resonator for subsystem
clock connection, and external clock input. The following operation modes can be specified in 1-bit units.
(1) Port mode
P120 to P124 function as a 5-bit I/O port. P120 to P124 can be set to input or output port using port mode
register 12 (PM12). Only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option
register 12 (PU12).
(2) Control mode
P120 to P124 function as an external interrupt request input, potential input for external low-voltage detection,
resonator for main system clock connection, resonator for subsystem clock connection, and external clock input.
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CHAPTER 2 PIN FUNCTIONS
(a) INTP0
This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling
edge, or both rising and falling edges) can be specified.
(b) EXLVI
This is a potential input pin for external low-voltage detection.
(c) X1, X2
These are the pins for connecting a resonator for main system clock.
(d) EXCLK
This is an external clock input pin for main system clock.
(e) XT1, XT2
These are the pins for connecting a resonator for subsystem clock.
(f) EXCLKS
This is an external clock input pin for subsystem clock.
Remark X1 and X2 of the μPD78F0363D can be used as on-chip debug mode setting pins (OCD0A,
OCD0B) when the on-chip debug function is used. For details, see CHAPTER 25 ON-CHIP
DEBUG FUNCTION (μPD78F0363D ONLY).
2.2.7 AVREF
This is the A/D converter reference voltage input pin.
When the A/D converter is not used, connect this pin directly to VDDNote.
Note Make the AVREF pin the same potential as the VDD pin when port 2 is used as a digital port.
2.2.8 AVSS
This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with
the same potential as the VSS pin.
2.2.9 S0 to S19
These pins are the segment signal output pins for the LCD controller/driver.
2.2.10 COM0 to COM3
These pins are the common signal output pins for the LCD controller/driver.
2.2.11 LVDD
This is the positive power supply pin for the LCD controller/driver.
2.2.12 LVSS
This is the ground potential pin for the LCD controller/driver.
2.2.13 VLC0 to VLC2
These pins are the power supply voltage pins for driving the LCD.
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CHAPTER 2 PIN FUNCTIONS
2.2.14 CAPH, CAPL
These pins are the capacitor connection pins for driving the LCD.
2.2.15 RESET
This is the active-low system reset input pin.
2.2.16 REGC
This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this
pin to VSS via a capacitor (0.47 to 1 μF: recommended).
REGC
VSS
Caution Keep the wiring length as short as possible in the area enclosed by the broken lines in the above figures.
2.2.17 VDD
This is the positive power supply pin.
2.2.18 VSS
This is the ground potential pin.
2.2.19 FLMD0
This is a pin for setting flash memory programming mode.
Connect FLMD0 to VSS in the normal operation mode.
In flash memory programming mode, be sure to connect this pin to the flash programmer.
User’s Manual U17734EJ2V0UD
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CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins.
See Figure 2-1 for the configuration of the I/O circuit of each type.
Table 2-2. Pin I/O Circuit Types
Pin Name
I/O Circuit Type
P00/TI000
I/O
Input:
I/O
5-AH
Recommended Connection of Unused Pins
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P01/TI010/TO00
P10/SCK10/TxD0
P11/SI10/RxD0
5-AG
P12/SO10
P13/TxD6
P14/RxD6
5-AH
P15/TOH0
5-AG
P16/TOH1/INTP5
5-AH
P17/TI50/TO50
P20/ANI0 to P24/ANI4
Note 1
11-G
Connect to AVREF or AVSS.
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
Input:
5-AH
P30/INTP1
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P31/INTP2
P32/INTP3
P33/TI51/TO51/INTP4
P60/SCL0
13-AD
Input:
Output: Leave open.
P61/SDA0
P120/INTP0/EXLVI
Note 2
P121/X1
P122/X2/EXCLK
P123/XT1
Connect to VSS.
Independently connect to VDD or VSS via a resistor.
5-AH
Input:
37
Output: Leave open.
Note 2
Note 2
P124/XT2/EXCLKS
Note 2
S0 to S19
17
COM0 to COM3
18
Output
−
VLC0 to VLC2
Leave open.
−
CAPH, CAPL
RESET
2
Input
FLMD0
38
Input
AVREF
AVSS
−
−
−
Connect to VSS.
Connect directly to VDD.
Connect directly to VSS.
Notes 1. P20/ANI0 to P24/ANI4 are set in the analog input mode after release of reset.
2. Use recommended connection above in I/O port mode (see Figure 5-2 Format of Clock Operation
Mode Select Register (OSCCTL)) when these pins are not used.
34
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (1/2)
Type 2
Type 11-G
AVREF
Data
P-ch
IN/OUT
Output
disable
IN
N-ch
AVSS
P-ch
Comparator
+
_
N-ch
Schmitt-triggered input with hysteresis characteristics
AVREF
(threshold voltage)
AVSS
Input enable
Type 5-AG
Type 13-AD
VDD
Pull-up
enable
P-ch
IN/OUT
Data
VDD
Data
Output
disable
N-ch
P-ch
VSS
IN/OUT
Output
disable
Input
enable
N-ch
VSS
Input
enable
Type 5-AH
Type 17
VDD
VLC0
P-ch
Pull-up
enable
P-ch
VLC1
P-ch
N-ch
VDD
P-ch
Data
P-ch
IN/OUT
Output
disable
SEG
data
OUT
N-ch
N-ch
P-ch
VLC2
N-ch
N-ch
VSS
Input
enable
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (2/2)
Type 18
VLC0
VLC1
Type 38
P-ch
P-ch
N-ch
IN
P-ch
N-ch
OUT
COM
data
N-ch
Input
enable
P-ch
P-ch
VLC2
N-ch
N-ch
Type 37
Reset
Data
VDD
P-ch
X2,
XT2
Output
disable
N-ch
VSS
Data
VDD
P-ch
Reset
N-ch
Input
enable
P-ch
X1,
XT1
Output
disable
N-ch
VSS
Input
enable
36
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
Products in the 78K0/LE2 can each access a 64 KB memory space. Figures 3-1 to 3-4 show the memory maps.
Caution
Regardless of the internal memory capacity, the initial values of the internal memory size
switching register (IMS) of all products in the 78K0/LE2 are fixed (IMS = CFH). Therefore, set the
value corresponding to each product as indicated below.
Table 3-1. Set Values of Internal Memory Size Switching Register (IMS)
Flash Memory Version
IMS
ROM Capacity
(78K0/LE2)
RAM Capacity
μPD78F0361
μPD78F0362
μPD78F0363, 78F0363D
Note
Internal High-Speed
04H
16 KB
768 bytes
C6H
24 KB
1 KB
C8H
32 KB
Note The ROM and RAM capacities of the products with the on-chip debug function can be debugged
according to the debug target products. Set IMS according to the debug target products.
User’s Manual U17734EJ2V0UD
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-1. Memory Map (μPD78F0361)
FFFFH
Special function registers
(SFR)
256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
General-purpose
registers
32 × 8 bits
3FFFH
Program area
Internal high-speed RAM
768 × 8 bits
FC00H
FBFFH
1FFFH
1085H
1084H
1080H
107FH
Option byte areaNote 1
5 × 8 bits
Boot cluster 1
Program area
Data memory
space
1000H
0FFFH
CALLF entry area
2048 × 8 bits
Reserved
0800H
07FFH
Program area
1915 × 8 bits
0085H
0084H
0080H
007FH
4000H
3FFFH
Program
memory space
Flash memory
16384 × 8 bits
0000H
0040H
003FH
Option byte areaNote 1
5 × 8 bits
Boot cluster 0Note 2
CALLT table area
64 × 8 bits
Vector table area
64 × 8 bits
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 24.7
Settings).
38
User’s Manual U17734EJ2V0UD
Security
CHAPTER 3 CPU ARCHITECTURE
Figure 3-2. Memory Map (μPD78F0362)
FFFFH
Special function registers
(SFR)
256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
General-purpose
registers
32 × 8 bits
5FFFH
Program area
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
1FFFH
1085H
1084H
1080H
107FH
Option byte areaNote 1
5 × 8 bits
Boot cluster 1
Program area
Data memory
space
1000H
0FFFH
CALLF entry area
2048 × 8 bits
Reserved
0800H
07FFH
Program area
1915 × 8 bits
0085H
0084H
0080H
007FH
6000H
5FFFH
Program
memory space
Flash memory
24576 × 8 bits
0000H
0040H
003FH
Option byte areaNote 1
5 × 8 bits
Boot cluster 0Note 2
CALLT table area
64 × 8 bits
Vector table area
64 × 8 bits
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 24.7
Security
Settings).
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-3. Memory Map (μPD78F0363)
FFFFH
Special function registers
(SFR)
256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
General-purpose
registers
32 × 8 bits
7FFFH
Program area
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
1FFFH
1085H
1084H
1080H
107FH
Option byte areaNote 1
5 × 8 bits
Boot cluster 1
Program area
Data memory
space
1000H
0FFFH
CALLF entry area
2048 × 8 bits
Reserved
0800H
07FFH
Program area
1915 × 8 bits
0085H
0084H
0080H
007FH
8000H
7FFFH
Program
memory space
Flash memory
32768 × 8 bits
0000H
0040H
003FH
Option byte areaNote 1
5 × 8 bits
Boot cluster 0Note 2
CALLT table area
64 × 8 bits
Vector table area
64 × 8 bits
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 24.7
Settings).
40
User’s Manual U17734EJ2V0UD
Security
CHAPTER 3 CPU ARCHITECTURE
Figure 3-4. Memory Map (μPD78F0363D)
FFFFH
Special function registers
(SFR)
256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
7FFFH
Program area
108FH
108EH
General-purpose
registers
32 × 8 bits
1085H
1084H
Internal high-speed RAM
1024 × 8 bits
1080H
107FH
1FFFH
On-chip debug security
ID setting areaNote 1
10 × 8 bits
Option byte areaNote 1
5 × 8 bits
Boot cluster 1
Program area
1000H
0FFFH
FB00H
FAFFH
CALLF entry area
2048 × 8 bits
Data memory
space
0800H
07FFH
Program area
1905 × 8 bits
Reserved
008FH
008EH
0085H
0084H
0080H
007FH
8000H
7FFFH
Program
memory space
Flash memory
32768 × 8 bits
0000H
0040H
003FH
On-chip debug security
ID setting areaNote 1
10 × 8 bits
Boot cluster 0Note 2
Option byte areaNote 1
5 × 8 bits
CALLT table area
64 × 8 bits
Vector table area
64 × 8 bits
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security
IDs to 0085H to 008EH.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the
on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 24.7
Security
Settings).
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CHAPTER 3 CPU ARCHITECTURE
3.1.1 Internal program memory space
The internal program memory space stores the program and table data. Normally, it is addressed with the program
counter (PC).
78K0/LE2 products incorporate internal ROM (flash memory), as shown below.
Table 3-2. Internal ROM Capacity
Part Number
Internal ROM
Structure
μPD78F0361
Capacity
16384 × 8 bits (0000H to 3FFFH)
Flash memory
μPD78F0362
24576 × 8 bits (0000H to 5FFFH)
μPD78F0363, 78F0363D
32768 × 8 bits (0000H to 7FFFH)
The internal program memory space is divided into the following areas.
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch
upon reset signal input or generation of each interrupt request are stored in the vector table area.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd
addresses.
Table 3-3. Vector Table
Vector Table Address
Interrupt Source
Vector Table Address
Interrupt Source
0000H
RESET input, POC, LVI, WDT
001AH
INTTMH1
0004H
INTLVI
001CH
INTTMH0
0006H
INTP0
001EH
INTTM50
0008H
INTP1
0020H
INTTM000
000AH
INTP2
0022H
INTTM010
000CH
INTP3
0024H
INTAD
000EH
INTP4
0026H
INTSR0
0010H
INTP5
0028H
INTWTI
0012H
INTSRE6
002AH
INTTM51
0014H
INTSR6
002EH
INTWT
0016H
INTST6
0034H
INTIIC0
0018H
INTCSI10/INTST0
003EH
BRK
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) Option byte area
A 5-byte area of 0080H to 0084H and 1080H to 1084H can be used as an option byte area. Set the option byte
at 0080H to 0084H when the boot swap is not used, and at 0080H to 0084H and 1080H to 1084H when the boot
swap is used. For details, see CHAPTER 23 OPTION BYTE.
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(4) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
(5) On-chip debug security ID setting area (μPD78F0363D only)
A 10-byte area of 0085H to 008EH and 1085H to 108EH can be used as an on-chip debug security ID setting
area. Set the on-chip debug security ID of 10 bytes at 0085H to 008EH when the boot swap is not used and at
0085H to 008EH and 1085H to 108EH when the boot swap is used. For details, see CHAPTER 25 ON-CHIP
DEBUG FUNCTION (μPD78F0363D ONLY).
3.1.2 Internal data memory space
78K0/LE2 products incorporate the following RAMs.
(1) Internal High-Speed RAM
Table 3-4. Internal High-Speed RAM Capacity
Part Number
Internal High-Speed RAM
μPD78F0361
768 × 8 bits (FC00H to FEFFH)
μPD78F0362
1024 × 8 bits (FB00H to FEFFH)
μPD78F0363, 78F0363D
The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit
registers per bank.
This area cannot be used as a program area in which instructions are written and executed.
The internal high-speed RAM can also be used as a stack memory.
(2) LCD display RAM
LCD display RAM is incorporated in the LCD controller/driver (see Figure 17-4 LCD Display RAM).
Table 3-5. LCD Display RAM Capacity
Part Number
μPD78F0361,
μPD78F0362,
μPD78F0363, 78F0363D
LCD Display RAM
20 × 4 bits (00H to 13H of LCDSEG)
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3.1.3 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (see
Table 3-6 Special Function Register List in 3.2.3 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
3.1.4 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of
the register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
78K0/LE2, based on operability and other considerations. For areas containing data memory in particular, special
addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are
available for use. Figures 3-5 to 3-7 show correspondence between data memory and addressing. For details of
each addressing mode, see 3.4 Operand Address Addressing.
Figure 3-5. Correspondence Between Data Memory and Addressing (μPD78F0361)
FFFFH
Special function registers (SFR)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
General-purpose registers
32 × 8 bits
Register addressing
Short direct
addressing
Internal high-speed RAM
768 × 8 bits
FE20H
FE1FH
Direct addressing
FC00H
FBFFH
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
4000H
3FFFH
Flash memory
16384 × 8 bits
0000H
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Figure 3-6. Correspondence Between Data Memory and Addressing (μPD78F0362)
FFFFH
Special function registers (SFR)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
General-purpose registers
32 × 8 bits
Register addressing
Short direct
addressing
Internal high-speed RAM
1024 × 8 bits
FE20H
FE1FH
Direct addressing
FB00H
FAFFH
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
6000H
5FFFH
Flash memory
24576 × 8 bits
0000H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-7. Correspondence Between Data Memory and Addressing (μPD78F0363, 78F0363D)
FFFFH
Special function registers (SFR)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
General-purpose registers
32 × 8 bits
Register addressing
Short direct
addressing
Internal high-speed RAM
1024 × 8 bits
FE20H
FE1FH
Direct addressing
FB00H
FAFFH
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
8000H
7FFFH
Flash memory
32768 × 8 bits
0000H
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3.2 Processor Registers
The 78K0/LE2 products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-8. Format of Program Counter
15
PC
0
PC15 PC14 PC13 PC12 PC11 PC10 PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions.
Reset signal generation sets PSW to 02H.
Figure 3-9. Format of Program Status Word
7
PSW
IE
0
Z
RBS1
AC
RBS0
0
ISP
CY
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgement is
controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgement and is set (1) upon EI
instruction execution.
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CHAPTER 3 CPU ARCHITECTURE
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction
execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, lowlevel vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H)
(see 18.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged.
Actual request acknowledgement is controlled by the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
Figure 3-10. Format of Stack Pointer
15
SP
0
SP15 SP14 SP13 SP12 SP11 SP10 SP9
SP8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from
the stack memory.
Each stack operation saves/restores data as shown in Figures 3-11 and 3-12.
Caution Since reset signal generation makes the SP contents undefined, be sure to initialize the SP
before using the stack.
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Figure 3-11. Data to Be Saved to Stack Memory
(a) PUSH rp instruction (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
Register pair higher
FEDEH
Register pair lower
(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
PC15 to PC8
FEDEH
PC7 to PC0
(c) Interrupt, BRK instructions (when SP = FEE0H)
SP
SP
FEE0H
FEDDH
FEE0H
FEDFH
PSW
FEDEH
PC15 to PC8
FEDDH
PC7 to PC0
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-12. Data to Be Restored from Stack Memory
(a) POP rp instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
Register pair higher
FEDEH
Register pair lower
(b) RET instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
PC15 to PC8
FEDEH
PC7 to PC0
(c) RETI, RETB instructions (when SP = FEDDH)
SP
SP
50
FEE0H
FEDDH
FEE0H
FEDFH
PSW
FEDEH
PC15 to PC8
FEDDH
PC7 to PC0
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CHAPTER 3 CPU ARCHITECTURE
3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory.
The
general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register
(AX, BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of
the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupts for each bank.
Figure 3-13. Configuration of General-Purpose Registers
(a) Function name
16-bit processing
8-bit processing
FEFFH
H
BANK0
HL
L
FEF8H
D
BANK1
DE
E
FEF0H
B
BC
BANK2
C
FEE8H
A
AX
BANK3
X
FEE0H
15
0
7
0
(b) Absolute name
16-bit processing
8-bit processing
FEFFH
R7
BANK0
RP3
R6
FEF8H
R5
BANK1
RP2
R4
FEF0H
R3
RP1
BANK2
R2
FEE8H
R1
RP0
BANK3
R0
FEE0H
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0
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CHAPTER 3 CPU ARCHITECTURE
3.2.3 Special function registers (SFRs)
Unlike a general-purpose register, each special function register has a special function.
SFRs are allocated to the FF00H to FFFFH areas in the CPU, and are allocated to the 00H to 03H areas of
LCDCTL in the LCD controller/driver.
Special function registers of the CPU can be manipulated like general-purpose registers, using operation, transfer,
and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register
type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When specifying an address, describe an even address.
Remark
For the operation method of special function registers in the LCD controller/driver, see 16.7
Communication with LCD Controller/Driver.
Table 3-6 gives a list of the special function registers. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined
as an sfr variable using the #pragma sfr directive in the CC78K0. When using the RA78K0, ID78K0-QB, and
SM+, symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding special function register can be read or written.
R/W: Read/write enable
R:
Read only
W:
Write only
• Manipulatable bit units
Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon reset signal generation.
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Table 3-6. Special Function Register List (1/3)
Address
Special Function Register (SFR) Name
Symbol
R/W
1 Bit
Manipulatable Bit Unit
8 Bits
16 Bits
After
Reset
FF00H
Port register 0
P0
R/W
√
√
−
00H
FF01H
Port register 1
P1
R/W
√
√
−
00H
FF02H
Port register 2
P2
R/W
√
√
−
00H
FF03H
Port register 3
P3
R/W
√
√
−
00H
FF06H
Port register 6
P6
R/W
√
√
−
00H
FF08H
10-bit A/D conversion result register
ADCR
R
−
−
√
0000H
ADCRH
R
−
√
−
00H
FF0AH
Receive buffer register 6
RXB6
R
−
√
−
FFH
FF0BH
Transmit buffer register 6
TXB6
R/W
−
√
−
FFH
FF0CH
Port register 12
P12
R/W
√
√
−
00H
FF0DH
Port register 13
P13
R/W
√
√
−
00H
FF0FH
Serial I/O shift register 10
SIO10
R
−
√
−
00H
FF10H
16-bit timer counter 00
TM00
R
−
−
√
0000H
16-bit timer capture/compare register 000
CR000
R/W
−
−
√
0000H
16-bit timer capture/compare register 010
CR010
R/W
−
−
√
0000H
FF16H
8-bit timer counter 50
TM50
R
−
√
−
00H
FF17H
8-bit timer compare register 50
CR50
R/W
−
√
−
00H
FF18H
8-bit timer H compare register 00
CMP00
R/W
−
√
−
00H
FF19H
8-bit timer H compare register 10
CMP10
R/W
−
√
−
00H
FF1AH
8-bit timer H compare register 01
CMP01
R/W
−
√
−
00H
FF1BH
8-bit timer H compare register 11
CMP11
R/W
−
√
−
00H
FF1FH
8-bit timer counter 51
TM51
R
−
√
−
00H
FF20H
Port mode register 0
PM0
R/W
√
√
−
FFH
FF21H
Port mode register 1
PM1
R/W
√
√
−
FFH
FF22H
Port mode register 2
PM2
R/W
√
√
−
FFH
FF23H
Port mode register 3
PM3
R/W
√
√
−
FFH
FF26H
Port mode register 6
PM6
R/W
√
√
−
FFH
FF27H
Port mode register 7
PM7
R/W
√
√
−
FFH
FF28H
A/D converter mode register
ADM
R/W
√
√
−
00H
FF29H
Analog input channel specification register
ADS
R/W
√
√
−
00H
FF2CH
Port mode register 12
PM12
R/W
√
√
−
FFH
FF2EH
Port mode register 14
PM14
R/W
√
√
−
FFH
FF2FH
A/D port configuration register
ADPC
R/W
√
√
−
00H
FF30H
Pull-up resistor option register 0
PU0
R/W
√
√
−
00H
FF31H
Pull-up resistor option register 1
PU1
R/W
√
√
−
00H
FF33H
Pull-up resistor option register 3
PU3
R/W
√
√
−
00H
FF3CH
Pull-up resistor option register 12
PU12
R/W
√
√
−
00H
FF40H
Clock output selection register
CKS
R/W
√
√
−
00H
FF41H
8-bit timer compare register 51
CR51
R/W
−
√
−
00H
FF09H
8-bit A/D conversion result register
FF11H
FF12H
FF13H
FF14H
FF15H
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Table 3-6. Special Function Register List (2/3)
Address
Special Function Register (SFR) Name
Symbol
R/W
1 Bit
Manipulatable Bit Unit
8 Bits
16 Bits
After
Reset
FF43H
8-bit timer mode control register 51
TMC51
R/W
√
√
−
00H
FF48H
External interrupt rising edge enable register
EGP
R/W
√
√
−
00H
FF49H
External interrupt falling edge enable register
EGN
R/W
√
√
−
00H
FF4FH
Input switch control register
ISC
R/W
√
√
−
00H
FF50H
Asynchronous serial interface operation mode
register 6
ASIM6
R/W
√
√
−
01H
FF53H
Asynchronous serial interface reception error
status register 6
ASIS6
R
−
√
−
00H
FF55H
Asynchronous serial interface transmission
status register 6
ASIF6
R
−
√
−
00H
FF56H
Clock selection register 6
CKSR6
R/W
−
√
−
00H
FF57H
Baud rate generator control register 6
BRGC6
R/W
−
√
−
FFH
FF58H
Asynchronous serial interface control register 6
ASICL6
R/W
√
√
−
16H
FF69H
8-bit timer H mode register 0
TMHMD0
R/W
√
√
−
00H
FF6AH
Timer clock selection register 50
TCL50
R/W
√
√
−
00H
FF6BH
8-bit timer mode control register 50
TMC50
R/W
√
√
−
00H
FF6CH
8-bit timer H mode register 1
TMHMD1
R/W
√
√
−
00H
FF6DH
8-bit timer H carrier control register 1
TMCYC1
R/W
√
√
−
00H
FF6FH
Watch timer operation mode register
WTM
R/W
√
√
−
00H
FF70H
Asynchronous serial interface operation mode
register 0
ASIM0
R/W
√
√
−
01H
FF71H
Baud rate generator control register 0
BRGC0
R/W
−
√
−
1FH
FF72H
Receive buffer register 0
RXB0
R
−
√
−
FFH
FF73H
Asynchronous serial interface reception error
status register 0
ASIS0
R
−
√
−
00H
FF74H
Transmit shift register 0
TXS0
W
−
√
−
FFH
FF80H
Serial operation mode register 10
CSIM10
R/W
√
√
−
00H
FF81H
Serial clock selection register 10
CSIC10
R/W
√
√
−
00H
FF84H
Transmit buffer register 10
SOTB10
R/W
−
√
−
00H
FF8CH
Timer clock selection register 51
TCL51
R/W
√
√
−
00H
FF99H
Watchdog timer enable register
WDTE
R/W
−
√
−
FF9FH
Clock operation mode select register
OSCCTL
R/W
√
√
−
FFA0H
Internal oscillation mode register
RCM
R/W
√
√
−
FFA1H
Main clock mode register
MCM
R/W
√
√
−
00H
FFA2H
Main OSC control register
MOC
R/W
√
√
−
80H
FFA3H
Oscillation stabilization time counter status register OSTC
R
√
√
−
00H
FFA4H
Oscillation stabilization time select register
OSTS
R/W
−
√
−
05H
FFA5H
IIC shift register 0
IIC0
R/W
−
√
−
00H
FFA6H
IIC control register 0
IICC0
R/W
√
√
−
00H
FFA7H
Slave address register 0
SVA0
R/W
−
√
−
00H
Notes 1.
2.
00H
Note 2
80H
The reset value of WDTE is determined by setting of option byte.
The value of this register is 00H immediately after a reset release but automatically changes to 80H after
oscillation accuracy stabilization of internal high-speed oscillator has been waited.
54
Note 1
1AH/9AH
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Special Function Register List (3/3)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulatable Bit Unit
8 Bits
16 Bits
After
Reset
FFA8H
IIC clock selection register 0
IICCL0
R/W
√
√
−
00H
FFA9H
IIC function expansion register 0
IICX0
R/W
√
√
−
00H
FFAAH
IIC status register 0
IICS0
R
√
√
−
00H
FFABH
IIC flag register 0
IICF0
R/W
√
√
−
00H
FFACH
Reset control flag register
RESF
R
−
√
−
FFBAH
16-bit timer mode control register 00
TMC00
R/W
√
√
−
00H
FFBBH
Prescaler mode register 00
PRM00
R/W
√
√
−
00H
FFBCH
Capture/compare control register 00
CRC00
R/W
√
√
−
00H
FFBDH
16-bit timer output control register 00
TOC00
R/W
√
√
−
FFBEH
Low-voltage detection register
LVIM
R/W
√
√
−
00H
FFBFH
Low-voltage detection level selection register
LVIS
R/W
√
√
−
00H
FFE0H
Interrupt request flag register 0L
IF0
IF0L
R/W
√
√
√
FFE1H
Interrupt request flag register 0H
IF0H
R/W
√
√
FFE2H
Interrupt request flag register 1L
IF1L
R/W
√
√
FFE3H
Interrupt request flag register 1H
IF1H
R/W
√
√
FFE4H
Interrupt mask flag register 0L
MK0
MK0L R/W
√
√
FFE5H
Interrupt mask flag register 0H
MK0H R/W
√
√
FFE6H
Interrupt mask flag register 1L
MK1
MK1L R/W
√
√
FFE7H
Interrupt mask flag register 1H
MK1H R/W
√
√
FFE8H
Priority specification flag register 0L
PR0
PR0L R/W
√
√
PR0H R/W
√
√
PR1
PR1L R/W
√
√
PR1H R/W
√
√
R/W
−
√
−
CFH
IF1
FFE9H
Priority specification flag register 0H
FFEAH
Priority specification flag register 1L
FFEBH
Priority specification flag register 1H
FFF0H
Internal memory size switching register
Note 2
IMS
Note 1
00H
00H
Note 1
Note 1
00H
00H
√
00H
00H
√
FFH
√
FFH
FFH
FFH
√
FFH
√
FFH
FFH
FFH
FFFBH
Processor clock control register
PCC
R/W
√
√
−
01H
LCDCTL's
00H
LCD mode setting register
LCDMD
R/W
−
√
−
00H
LCDCTL's
01H
LCD display mode register
LCDM
R/W
−
√
−
00H
LCDCTL's
02H
LCD clock control register
LCDC
R/W
−
√
−
00H
LCDCTL's
03H
LCD voltage boost control register 0
VLCG0
R/W
−
√
−
00H
Notes 1.
2.
The reset values of RESF, LVIM and LVIS vary depending on the reset source.
Regardless of the internal memory capacity, the initial values of the internal memory size switching
register (IMS) of all products in the 78K0/LE2 are fixed (IMS = CFH). Therefore, set the value
corresponding to each product as indicated below.
Flash Memory Version
IMS
ROM Capacity
(78K0/LE2)
μPD78F0362
μPD78F0363, 78F0363D
Note 3
3.
Internal High-Speed
RAM Capacity
μPD78F0361
1 Bit
04H
16 KB
768 bytes
C6H
24 KB
1 KB
C8H
32 KB
The ROM and RAM capacities of the products with the on-chip debug function can be debugged
according to the debug target products. Set IMS according to the debug target products.
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CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each
byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is
executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by
the following addressing (for details of instructions, refer to 78K/0 Series Instructions User’s Manual (U12326E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched.
The
displacement value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.
In other words, relative addressing consists of relative branching from the start address of the following
instruction to the −128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
0
... PC indicates the start address
of the instruction after the BR instruction.
PC
+
8
15
α
7
6
0
S
jdisp8
15
0
PC
When S = 0, all bits of α are 0.
When S = 1, all bits of α are 1.
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CHAPTER 3 CPU ARCHITECTURE
3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11
instruction is branched to the 0800H to 0FFFH area.
[Illustration]
In the case of CALL !addr16 and BR !addr16 instructions
7
0
CALL or BR
Low Addr.
High Addr.
15
8 7
0
PC
In the case of CALLF !addr11 instruction
7 6
4
3
0
CALLF
fa10–8
fa7–0
15
PC
0
11 10
0
0
0
8 7
0
1
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CHAPTER 3 CPU ARCHITECTURE
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operation code are transferred to the program counter (PC) and branched.
This function is carried out when the CALLT [addr5] instruction is executed.
This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to
the entire memory space.
[Illustration]
7
Operation code
6
1
5
1
1
ta4–0
1
15
Effective address
0
7
0
0
0
0
0
0
0
Memory (Table)
8
7
6
0
0
1
5
1 0
0
0
Low Addr.
High Addr.
Effective address+1
8
15
7
0
PC
3.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
rp
0
7
A
15
X
8
7
PC
58
0
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CHAPTER 3 CPU ARCHITECTURE
3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.4.1 Implied addressing
[Function]
The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically
(implicitly) addressed.
Of the 78K0/LE2 instruction words, the following instructions employ implied addressing.
Instruction
Register to Be Specified by Implied Addressing
MULU
A register for multiplicand and AX register for product storage
DIVUW
AX register for dividend and quotient storage
ADJBA/ADJBS
A register for storage of numeric values that become decimal correction targets
ROR4/ROL4
A register for storage of digit data that undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format is
necessary.
[Description example]
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
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CHAPTER 3 CPU ARCHITECTURE
3.4.2 Register addressing
[Function]
The general-purpose register to be specified is accessed as an operand with the register bank select flags
(RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
rp
AX, BC, DE, HL
‘r’ and ‘rp’ can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; when selecting C register as r
Operation code
0
1
1
0
0
0
1
0
Register specify code
INCW DE; when selecting DE register pair as rp
Operation code
1
0
0
0
0
1
0
0
Register specify code
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CHAPTER 3 CPU ARCHITECTURE
3.4.3 Direct addressing
[Function]
The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an
operand address.
[Operand format]
Identifier
Description
addr16
Label or 16-bit immediate data
[Description example]
MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code
1
0
0
0
1
1
1
0
OP code
0
0
0
0
0
0
0
0
00H
1
1
1
1
1
1
1
0
FEH
[Illustration]
7
0
OP code
addr16 (lower)
addr16 (upper)
Memory
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CHAPTER 3 CPU ARCHITECTURE
3.4.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers
(SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter
are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. Refer to the [Illustration] shown below.
[Operand format]
Identifier
Description
saddr
Immediate data that indicate label or FE20H to FF1FH
saddrp
Immediate data that indicate label or FE20H to FF1FH (even address only)
[Description example]
MOV 0FE30H, A; when transferring value of A register to saddr (FE30H)
Operation code
1
1
1
1
0
0
1
0
OP code
0
0
1
1
0
0
0
0
30H (saddr-offset)
[Illustration]
7
0
OP code
saddr-offset
Short direct memory
8 7
15
Effective address
1
1
1
1
1
1
1
α
When 8-bit immediate data is 20H to FFH, α = 0
When 8-bit immediate data is 00H to 1FH, α = 1
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CHAPTER 3 CPU ARCHITECTURE
3.4.5 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier
Description
sfr
Special function register name
sfrp
16-bit manipulatable special function register name (even address
only)
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code
1
1
1
1
0
1
1
0
OP code
0
0
1
0
0
0
0
0
20H (sfr-offset)
[Illustration]
7
0
OP code
sfr-offset
SFR
8 7
15
Effective address
1
1
1
1
1
1
1
0
1
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CHAPTER 3 CPU ARCHITECTURE
3.4.6 Register indirect addressing
[Function]
Register pair contents specified by a register pair specify code in an instruction word and by a register bank
select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be
carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[DE], [HL]
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code
1
0
0
0
0
1
0
1
[Illustration]
16
DE
8 7
D
0
E
7
Memory
The contents of the memory
addressed are transferred.
7
0
A
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The memory address
specified with the
register pair DE
CHAPTER 3 CPU ARCHITECTURE
3.4.7 Based addressing
[Function]
8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in
the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address
the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from
the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
−
Description
[HL + byte]
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code
1
0
1
0
1
1
1
0
0
0
0
1
0
0
0
0
[Illustration]
16
8 7
H
HL
0
L
7
Memory
0
+10H
The contents of the memory
addressed are transferred.
7
0
A
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CHAPTER 3 CPU ARCHITECTURE
3.4.8 Based indexed addressing
[Function]
The B or C register contents specified in an instruction word are added to the contents of the base register, that
is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the
sum is used to address the memory. Addition is performed by expanding the B or C register contents as a
positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the
memory spaces.
[Operand format]
Identifier
−
Description
[HL + B], [HL + C]
[Description example]
MOV A, [HL +B]; when selecting B register
Operation code
1
0
1
0
1
0
1
1
[Illustration]
16
HL
8
7
0
L
H
+
7
0
B
7
Memory
The contents of the memory
addressed are transferred.
7
0
A
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CHAPTER 3 CPU ARCHITECTURE
3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call and return
instructions are executed or the register is saved/reset upon generation of an interrupt request.
With stack addressing, only the internal high-speed RAM area can be accessed.
[Description example]
PUSH DE; when saving DE register
Operation code
1
0
1
1
0
1
0
1
[Illustration]
7
SP
SP
FEE0H
FEDEH
Memory
0
FEE0H
FEDFH
D
FEDEH
E
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CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
There are two types of pin I/O buffer power supplies: AVREF and VDD. The relationship between these power
supplies and the pins is shown below.
Table 4-1. Pin I/O Buffer Power Supplies
Power Supply
Corresponding Pins
AVREF
P20 to P24
VDD
Port pins other than P20 to P24
78K0/LE2 products are provided with the ports shown in Figure 4-1, which enable variety of control operations.
The functions of each port are shown in Table 4-2.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the
alternate functions, see CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Types
P30
P00
P01
P33
P10
Port 3
Port 6
P60
P61
Port 0
Port 1
P120
P17
Port 12
P20
P124
Port 2
P24
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CHAPTER 4 PORT FUNCTIONS
Table 4-2. Port Functions
Pin Name
I/O
P00
I/O
Function
After Reset
Port 0.
Input
Alternate Function
TI000
2-bit I/O port.
Input/output can be specified in 1-bit units.
P01
TI010/TO00
Use of an on-chip pull-up resistor can be specified by a
software setting.
P10
I/O
Port 1.
Input
8-bit I/O port.
P11
SI10/RxD0
Input/output can be specified in 1-bit units.
P12
SO10
Use of an on-chip pull-up resistor can be specified by a
P13
SCK10/TxD0
TxD6
software setting.
P14
RxD6
P15
TOH0
P16
TOH1/INTP5
P17
TI50/TO50
P20 to P24
I/O
Port 2.
Input
ANI0 to ANI4
Input
INTP1 to INTP3
5-bit I/O port.
Input/output can be specified in 1-bit units.
I/O
P30
Port 3.
4-bit I/O port.
P31
Input/output can be specified in 1-bit units.
P32
Use of an on-chip pull-up resistor can be specified by a
P33
I/O
Port 6.
Input
2-bit I/O port.
P61
Note
INTP3/OCD1B
Note
INTP4/TI51/TO51
software setting.
P60
INTP2/OCD1A
SCL0
SDA0
Output of P60 and P61 is N-ch open-drain output (6 V
tolerance).
Input/output can be specified in 1-bit units.
P120
I/O
Port 12.
Input
5-bit I/O port.
P121
X1/OCD0A
Input/output can be specified in 1-bit units.
P122
Only for P120, use of an on-chip pull-up resistor can be
P123
Note
X2/EXCLK/OCD0B
Note
XT1
specified by a software setting.
P124
Note
INTP0/EXLVI
XT2/EXCLKS
μPD78F0363D only.
4.2 Port Configuration
Ports include the following hardware.
Table 4-3. Port Configuration
Item
Control registers
Configuration
Port mode register (PM0 to PM3, PM6, PM7, PM12)
Port register (P0 to P3, P6, P12)
Pull-up resistor option register (PU0, PU1, PU3, PU12)
A/D port configuration register (ADPC)
Port
24
Pull-up resistor
15
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CHAPTER 4 PORT FUNCTIONS
4.2.1 Port 0
Port 0 is a 2-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units
using port mode register 0 (PM0). When the P00 and P01 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
This port can also be used for timer I/O.
Reset signal generation sets port 0 to input mode.
Figures 4-2 and 4-3 show block diagrams of port 0.
Figure 4-2. Block Diagram of P00
VDD
WRPU
PU0
PU00
P-ch
Alternate function
Selector
Internal bus
RD
WRPORT
Output latch
(P00)
P00/TI000
WRPM
PM0
PM00
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
RD:
Read signal
WR××: Write signal
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Figure 4-3. Block Diagram of P01
VDD
WRPU
PU0
PU01
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P01)
P01/TI010/TO00
WRPM
PM0
PM01
Alternate
function
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
RD:
Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
4.2.2 Port 1
Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units
using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
Reset signal generation sets port 1 to input mode.
Figures 4-4 to 4-8 show block diagrams of port 1.
Caution When P10/SCK10/TxD0 and P12/SO10 are used as general-purpose ports, set serial operation
mode register 10 (CSIM10) and serial clock selection register 10 (CSIC10) to the initial setting
(00H).
Figure 4-4. Block Diagram of P10
VDD
WRPU
PU1
PU10
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P10)
P10/SCK10/TxD0
WRPM
PM1
PM10
Alternate
function
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-5. Block Diagram of P11 and P14
VDD
WRPU
PU1
PU11, PU14
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P11, P14)
P11/SI10/RxD0,
P14/RxD6
WRPM
PM1
PM11, PM14
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-6. Block Diagram of P12 and P15
VDD
WRPU
PU1
PU12, PU15
P-ch
Internal bus
Selector
RD
WRPORT
Output latch
(P12, P15)
P12/SO10
P15/TOH0
WRPM
PM1
PM12, PM15
Alternate
function
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-7. Block Diagram of P13
VDD
WRPU
PU1
PU13
P-ch
Selector
Internal bus
RD
WRPORT
Output latch
(P13)
P13/TxD6
WRPM
PM1
PM13
Alternate
function
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-8. Block Diagram of P16 and P17
VDD
WRPU
PU1
PU16, PU17
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P16, P17)
P16/TOH1/INTP5,
P17/TI50/TO50
WRPM
PM1
PM16, PM17
Alternate
function
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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4.2.3 Port 2
Port 2 is a 5-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units
using port mode register 2 (PM2).
This port can also be used for A/D converter analog input.
When P20/ANI0 to P24/ANI4 are used as digital input ports, select digital I/O using the A/D port configuration
register (ADPC), set the input mode using PM2, and then use these ports from the lower bits.
When P20/ANI0 to P24/ANI4 are used as digital output ports, select digital I/O using ADPC, and then set output
mode using PM2.
Table 4-4. Settings of P20/ANI0 to P24/ANI4 pin function
ADPC Setting
Digital I/O selection
PM2 Setting
ADS Setting
Input mode
Output mode
Analog input selection
Input mode
P20/ANI0 to P24/ANI4 Pins
ANI selection
Setting prohibited
ANI non-selection
Digital input
ANI selection
Setting prohibited
ANI non-selection
Digital output
ANI selection
Analog input (target for
conversion)
ANI non-selection
Analog input (target for nonconversion)
Output mode
ANI selection
Setting prohibited
ANI non-selection
When a reset signal is generated, P20/ANI0 to P24/ANI4 are all set to analog input mode.
Figure 4-9 shows a block diagram of port 2.
Figure 4-9. Block Diagram of P20 to P24
Selector
Internal bus
RD
WRPORT
Output latch
(P20 to P24)
P20/ANI0 to
P24/ANI4
WRPM
PM2
PM20 to PM24
A/D converter
PM2:
Port mode register 2
RD:
Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
4.2.4 Port 3
Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units
using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified in
1-bit units by pull-up resistor option register 3 (PU3).
This port can also be used for external interrupt request input and timer I/O.
Reset signal generation sets port 3 to input mode.
Figures 4-10 and 4-11 show block diagrams of port 3.
Caution In the 78F0363D, be sure to pull the P31 pin down after reset to prevent malfunction.
Remark
P31 and P32 of the μPD78F0363D can be used as on-chip debug mode setting pins (OCD1A, OCD1B)
when the on-chip debug function is used. For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION
(μPD78F0363D ONLY).
Figure 4-10. Block Diagram of P30 to P32
VDD
WRPU
PU3
PU30 to PU32
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P30 to P32)
P30/INTP1,
P31/INTP2/OCD1ANote,
P32/INTP3/OCD1BNote
WRPM
PM3
PM30 to PM32
PU3:
Pull-up resistor option register 3
PM3:
Port mode register 3
RD:
Read signal
WR××: Write signal
Note μPD78F0363D only.
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Figure 4-11. Block Diagram of P33
VDD
WRPU
PU3
PU33
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P33)
P33/INTP4/TI51/TO51
WRPM
PM3
PM33
Alternate
function
PU3:
Pull-up resistor option register 3
PM3:
Port mode register 3
RD:
Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
4.2.5 Port 6
Port 6 is a 2-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units
using port mode register 6 (PM6).
The output of the P60 and P61 pins is N-ch open-drain output (6 V tolerance).
This port can also be used for serial interface data I/O and clock I/O.
Reset signal generation sets port 6 to input mode.
Figures 5-18 to 5-20 show block diagrams of port 6.
Caution In the 78K0/LE2, be sure to use the P60/SCL0 and P61/SDA0 as the serial clock I/O pin and serial data
I/O pin, respectively, in accordance with the specifications.
Figure 4-12 Block Diagram of P60 and P61
Alternate
function
Selector
RD
Internal bus
WRPORT
P6
Output latch
(P60, P61)
P60/SCL0,
P61/SDA0
WRPM
PM6
PM60, PM61
Alternate
function
P6:
Port register 6
PM6:
Port mode register 6
RD:
Read signal
WR××: Write signal
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4.2.6 Port 12
Port 12 is a 5-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units
using port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can
be specified by pull-up resistor option register 12 (PU12).
This port can also be used for external interrupt request input, potential input for external low-voltage detection,
resonator for main system clock connection, external clock input, and resonator for subsystem clock connection.
Reset signal generation sets port 12 to input mode.
Figures 4-13 and 4-14 show block diagrams of port 12.
Caution When using P121 to P124 pins to connect a resonator for the main system clock or subsystem
clock, or to input an external clock, the X1 oscillation mode, XT1 oscillation mode, or external
clock input mode must be set by using the clock operation mode select register (OSCCTL) (for
details, see 5.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation
mode for subsystem clock pin). The reset value of OSCCTL is 00H (all P121 to P124 are I/O port
pins). At this time, settings of PM121 to PM124 and P121 to P124 are not necessary.
Remark
X1 and X2 of the μPD78F0363D can be used as on-chip debug mode setting pins (OCD0A, OCD0B)
when the on-chip debug function is used. For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION
(μPD78F0363D ONLY).
Figure 4-13. Block Diagram of P120
VDD
WRPU
PU12
PU120
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
Output latch
(P120)
P120/INTP0/EXLVI
WRPM
PM12
PM120
PU12:
Pull-up resistor option register 12
PM12:
Port mode register 12
RD:
Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-14. Block Diagram of P121 to P124
OSCCTL
OSCSEL/
OSCSELS
Selector
RD
WRPORT
Output latch
(P122/P124)
P122/X2/EXCLK/OCD0BNote,
P124/XT2/EXCLKS
WRPM
PM12
PM122/PM124
OSCCTL
OSCSEL/
OSCSELS
Internal bus
OSCCTL
EXCLK, OSCSEL/
EXCLKS, OSCSELS
Selector
RD
WRPORT
Output latch
(P121/P123)
P121/X1/OCD0ANote,
P123/XT1
WRPM
PM12
PM121/PM123
OSCCTL
OSCSEL/
OSCSELS
PU12:
Pull-up resistor option register 12
PM12:
Port mode register 12
OSCCTL:
Clock operation mode select register
RD:
Read signal
WR××:
Write signal
Note μPD78F0363D only.
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4.3 Registers Controlling Port Function
Port functions are controlled by the following four types of registers.
• Port mode registers (PM0, PM1, PM2, PM3, PM6, PM7, PM12)
• Port registers (P0, P1, P2, P3, P6, P12)
• Pull-up resistor option registers (PU0, PU1, PU3, PU12)
• A/D port configuration register (ADPC)
(1) Port mode registers (PM0, PM1, PM2, PM3, PM6, PM7, and PM12)
These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table
4-4.
Figure 4-15. Format of Port Mode Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM0
1
1
1
1
1
1
PM01
PM00
FF20H
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FF21H
FFH
R/W
PM2
1
1
1
PM24
PM23
PM22
PM21
PM20
FF22H
FFH
R/W
PM3
1
1
1
1
PM33
PM32
PM31
PM30
FF23H
FFH
R/W
PM6
1
1
1
1
1
PM62
PM61
PM60
FF26H
FFH
R/W
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
FF27H
FFH
R/W
PM12
1
1
1
PM124
PM123
PM122
PM121
PM120
FF2CH
FFH
R/W
Pmn pin I/O mode selection
PMmn
(m = 0 to 3, 6, 7, 12; n = 0 to 7)
Caution
Remark
0
Output mode (output buffer on)
1
Input mode (output buffer off)
After a reset release, be sure to set PM62 to 0, and set PM7 to 00H.
For PM14, see 11.3 Registers Controlling Clock Output Controller or 17.3 Registers Controlling
LCD Controller/Driver.
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CHAPTER 4 PORT FUNCTIONS
(2) Port registers (P0, P1, P2, P3, P6, P12)
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output
latch is read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to 00H.
Figure 4-16. Format of Port Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
P0
0
0
0
0
0
0
P01
P00
FF00H
00H (output latch)
R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FF01H
00H (output latch)
R/W
P2
0
0
0
P24
P23
P22
P21
P20
FF02H
00H (output latch)
R/W
P3
0
0
0
0
P33
P32
P31
P30
FF03H
00H (output latch)
R/W
P6
0
0
0
0
0
0
P61
P60
FF06H
00H (output latch)
R/W
P12
0
0
0
P124
P123
P122
P121
P120
FF0CH
00H (output latch)
R/W
m = 0 to 3, 6, 12; n = 0 to 7
Pmn
Output data control (in output mode)
Remark
84
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
For P13, see 17.3 Registers Controlling LCD Controller/Driver.
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CHAPTER 4 PORT FUNCTIONS
(3) Pull-up resistor option registers (PU0, PU1, PU3, PU12)
These registers specify whether the on-chip pull-up resistors of P00, P01, P10 to P17, P30 to P33, and P120 are
to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the
pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3, and PU12. On-chip
pull-up resistors cannot be connected to bits set to output mode and bits used as alternate-function output pins,
regardless of the settings of PU0, PU1, PU3, and PU12.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to 00H.
Figure 4-17. Format of Pull-up Resistor Option Register
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PU0
0
0
0
0
0
0
PU01
PU00
FF30H
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
FF31H
00H
R/W
PU3
0
0
0
0
PU33
PU32
PU31
PU30
FF33H
00H
R/W
PU12
0
0
0
0
0
0
0
PU120
FF3CH
00H
R/W
PUmn
Pmn pin on-chip pull-up resistor selection
(m = 0, 1, 3, 12; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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CHAPTER 4 PORT FUNCTIONS
(4) A/D port configuration register (ADPC)
This register switches the P20/ANI0 to P24/ANI4 pins to analog input of A/D converter or digital I/O of port.
ADPC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 4-18. Format of A/D Port Configuration Register (ADPC)
Address: FF2FH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ADPC
0
0
0
0
0
ADPC2
ADPC1
ADPC0
ADPC2
ADPC1
ADPC0
Analog input (A)/digital input (D) switching
P24/
ANI4
P23/
ANI3
P22/
ANI2
P21/
ANI1
P20/
ANI0
0
0
0
A
A
A
A
A
0
0
1
A
A
A
A
D
0
1
0
A
A
A
D
D
0
1
1
A
A
D
D
D
1
0
0
A
D
D
D
D
1
0
1
D
D
D
D
D
Other than above
Setting prohibited
Cautions 1. Set the channel used for A/D conversion in the input mode by using port mode register 2
(PM2).
2. Do not set a pin to be used as a digital I/O pin with ADPC with ADS.
3. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU
is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 29 CAUTIONS FOR WAIT.
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4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the
port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the
output latch contents for pins specified as input are undefined, even for bits other than the
manipulated bit.
4.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared by reset.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does
not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
4.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output
latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared by reset.
(2) Input mode
The pin level is read and an operation is performed on its contents. The result of the operation is written to the
output latch, but since the output buffer is off, the pin status does not change.
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CHAPTER 4 PORT FUNCTIONS
4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function
When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table
4-5.
Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function
Pin Name
Alternate Function
Function Name
PM××
P××
I/O
P00
TI000
Input
1
×
P01
TI010
Input
1
×
P10
TO00
Output
0
0
SCK10
Input
1
×
Output
0
1
TxD0
Output
0
1
SI10
Input
1
×
RxD0
Input
1
×
P12
SO10
Output
0
0
P13
TxD6
Output
0
1
P14
RxD6
Input
1
×
P15
TOH0
Output
0
0
P16
TOH1
Output
0
0
INTP5
Input
1
×
TI50
Input
1
×
TO50
Output
0
0
P11
P17
Input
1
×
P30 to P32
INTP1 to INTP3
Input
1
×
P33
INTP4
Input
1
×
TI51
Input
1
×
P20 to P24
Note1
ANI0 to ANI4
Note1
TO51
Output
0
0
P60
SCL0
I/O
0
0
P61
SDA0
I/O
0
0
P120
INTP0
Input
1
×
EXLVI
Input
1
×
Note2
−
×
×
Note2
−
×
×
×
×
−
×
×
−
×
×
×
×
P121
X1
P122
X2
EXCLK
P123
XT1
Note2
P124
XT2
Note2
Note2
EXCLKS
Input
Note2
Input
(Refer to Notes and Remarks on the next page.)
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Notes1.
The functions of the ANI0/P20 to ANI4/P24 pins are determined according to the settings of A/D port
configuration register (ADPC), Analog input channel specification register (ADS), and PM2.
Table 4-6. Settings of ANI0/P20 to ANI4/P24 pin function
ADPC Setting
Analog input selection
PM2 Setting
Input mode
ADS Setting
ANI selection
ANI0/P20 to ANI4/P24 Pins
Analog input (target for
conversion)
ANI non-selection
Analog input (target for nonconversion)
Output mode
ANI selection
Setting prohibited
ANI non-selection
Digital I/O selection
2.
Input mode
ANI selection
Setting prohibited
ANI non-selection
Digital input
Output mode
ANI selection
Setting prohibited
ANI non-selection
Digital output
When using P121 to P124 pins to connect a resonator for the main system clock or subsystem clock, or to
input an external clock, the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be
set by using the clock operation mode select register (OSCCTL) (for details, see 5.3 (1) Clock operation
mode select register (OSCCTL) and (3) Setting of operation mode for subsystem clock pin). The
reset value of OSCCTL is 00H (all P121 to P124 are I/O port pins). At this time, settings of PM121 to
PM124 and P121 to P124 are not necessary.
Remarks1. ×:
Don’t care
PM××:
Port mode register
P××:
Port output latch
2. X1, X2, P31, and P32 pins of the μPD78F0363D can be used as on-chip debug mode setting pins
(OCD0A, OCD0B, OCD1A, OCD1B) when the on-chip debug function is used.
For details, see
CHAPTER 25 ON-CHIP DEBUG FUNCTION (μPD78F0363D ONLY).
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CHAPTER 5 CLOCK GENERATOR
5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three kinds of system clocks and clock oscillators are selectable.
(1) Main system clock
X1 oscillator
This circuit oscillates a clock of fX = 1 to 20 MHz by connecting a resonator to X1 and X2.
Oscillation can be stopped by executing the STOP instruction or using the main OSC control register
(MOC).
Internal high-speed oscillator
This circuit oscillates a clock of fRH = 8 MHz (TYP.). After a reset release, the CPU always starts
operating with this internal high-speed oscillation clock. Oscillation can be stopped by executing the
STOP instruction or using the internal oscillation mode register (RCM).
An external main system clock (fEXCLK = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An
external main system clock input can be disabled by executing the STOP instruction or using RCM.
As the main system clock, a high-speed system clock (X1 clock or external main system clock) or internal highspeed oscillation clock can be selected by using the main clock mode register (MCM).
(2) Subsystem clock
• Subsystem clock oscillator
This circuit oscillates at a frequency of fXT = 32.768 kHz by connecting a 32.768 kHz resonator across XT1
and XT2.
Oscillation can be stopped by using the processor clock control register (PCC) and clock
operation mode select register (OSCCTL).
An external subsystem clock (fEXCLKS = 32.768 kHz) can also be supplied from the EXCLKS/XT2/P124 pin. An
external subsystem clock input can be disabled by setting PCC and OSCCTL.
Remarks 1. fX:
2. fRH:
X1 clock oscillation frequency
Internal high-speed oscillation clock frequency
3. fEXCLK:
External main system clock frequency
4. fXT:
XT1 clock oscillation frequency
5. fEXCLKS: External subsystem clock frequency
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CHAPTER 5 CLOCK GENERATOR
(3) Internal low-speed oscillation clock (clock for watchdog timer)
• Internal low-speed oscillator
This circuit oscillates a clock of fRL = 240 kHz (TYP.). After a reset release, the internal low-speed oscillation
clock always starts operating.
Oscillation can be stopped by using the internal oscillation mode register (RCM) when “internal low-speed
oscillator can be stopped by software” is set by option byte.
The internal low-speed oscillation clock cannot be used as the CPU clock. The following hardware operates
with the internal low-speed oscillation clock.
• Watchdog timer
• TMH1 (when fRL, fRL/27, or fRL/29 is selected)
Remark
fRL:
Internal low-speed oscillation clock frequency
5.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item
Configuration
Control registers
Clock operation mode select register (OSCCTL)
Processor clock control register (PCC)
Internal oscillation mode register (RCM)
Main OSC control register (MOC)
Main clock mode register (MCM)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Oscillators
X1 oscillator
XT1 oscillator
Internal high-speed oscillator
Internal low-speed oscillator
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92
Figure 5-1. Block Diagram of Clock Generator
Internal bus
Main OSC
control register
(MOC)
Clock operation mode
select register
(OSCCTL)
AMPH EXCLK OSCSEL
Main clock
mode register
(MCM)
MCS
MSTOP
Main clock
mode register
(MCM)
Oscillation stabilization
time select register (OSTS)
OSTS2 OSTS1 OSTS0
Processor clock
control register
(PCC)
XTSTART CLS CSS PCC2 PCC1 PCC0
XSEL MCM0
3
4
STOP
X1 oscillation
stabilization time counter
Subsystem
clock oscillator
Oscillation
stabilization
MOST MOST MOST MOST MOST time counter
11 13 14
15 16 status register
(OSTC)
fX
External input
clock
fEXCLK
Controller
Main system fXP
clock switch
Internal hghspeed oscillator fRH
(8 MHz (TYP.))
Subsystem
clock oscillator
XT1/P123
Crystal
oscillation
XT2/EXCLKS/
P124
External input
clock
XTSTART
Processor clock
control register
(PCC)
Prescaler
fXP
2
1/2
fXT
fSUB
fXP
22
fSUB
2
fEXCLKS
RSTS
LSRSTOP RSTOP
Internal oscillation
mode register
(RCM)
Clock operation mode
select register
(OSCCTL)
Internal bus
fXP
24
Internal lowspeed oscillator fRL
(240 kHz (TYP.))
Watch timer,
LCD controller/driver
EXCLKS OSCSELS
fXP
23
Selector
User’s Manual U17734EJ2V0UD
X2/EXCLK/
P122
fXH
Crystal/ceramic
oscillation
Option byte
1: Cannot be stopped
0: Can be stopped
CPU clock
(fCPU)
Watchdog timer,
8-bit timer H1
CHAPTER 5 CLOCK GENERATOR
X1/P121
Peripheral
hardware
clock (fPRS)
Peripheral
hardware
clock switch
High-speed system
clock oscillator
CHAPTER 5 CLOCK GENERATOR
Remarks 1. fX:
2. fRH:
X1 clock oscillation frequency
Internal high-speed oscillation clock frequency
3. fEXCLK:
External main system clock frequency
4. fXH:
High-speed system clock oscillation frequency
5. fXP:
Main system clock oscillation frequency
6. fPRS:
Peripheral hardware clock oscillation frequency
7. fCPU:
CPU clock oscillation frequency
8. fXT:
XT1 clock oscillation frequency
9. fEXCLKS: External subsystem clock frequency
10. fSUB:
Subsystem clock oscillation frequency
11. fRL:
Internal low-speed oscillation clock frequency
5.3 Registers Controlling Clock Generator
The following seven registers are used to control the clock generator.
• Clock operation mode select register (OSCCTL)
• Processor clock control register (PCC)
• Internal oscillation mode register (RCM)
• Main OSC control register (MOC)
• Main clock mode register (MCM)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
(1) Clock operation mode select register (OSCCTL)
This register selects the operation modes of the high-speed system and subsystem clocks, and the gain of the
on-chip oscillator.
OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
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CHAPTER 5 CLOCK GENERATOR
Figure 5-2. Format of Clock Operation Mode Select Register (OSCCTL)
Address: FF9FH
Symbol
OSCCTL
After reset: 00H
R/W
Note
Note
3
2
1
0
0
0
AMPH
EXCLK
OSCSEL
EXCLKS
EXCLK
OSCSEL
High-speed system clock
pin operation mode
0
0
I/O port mode
I/O port
0
1
X1 oscillation mode
Crystal/ceramic resonator connection
1
0
I/O port mode
I/O port
1
1
External clock input
mode
I/O port
AMPH
Note
OSCSELS
P121/X1 pin
P122/X2/EXCLK pin
External clock input
Operating frequency control
0
1 MHz ≤ fXH ≤ 10 MHz
1
10 MHz < fXH ≤ 20 MHz
EXCLKS and OSCSELS are used in combination with XTSTART (bit 6 of the processor
clock control register (PCC)). See (3) Setting of operation mode for subsystem clock
pin.
Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency
exceeds 10 MHz.
2. Set AMPH before setting the peripheral functions after a reset release. The value
of AMPH can be changed only once after a reset release. The clock supply to the
CPU is stopped for 5 μs (MIN.) after AMPH has been set to 1.
3. If the STOP instruction is executed with AMPH set to 1 when the internal highspeed oscillation clock or external main system clock is used as the CPU clock,
then the clock supply to the CPU is stopped for 5 μs (MIN.) after the STOP mode
has been released.
If the X1 clock is used as the CPU clock, oscillation
stabilization time is counted after the STOP mode has been released.
4. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7
(MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or
the external clock from the EXCLK pin is disabled).
Remark fXH: High-speed system clock oscillation frequency
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(2) Processor clock control register (PCC)
This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock.
PCC is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PCC to 01H.
Figure 5-3. Format of Processor Clock Control Register (PCC)
Address: FFFBH
Symbol
PCC
After reset: 01H
7
R/W
6
XTSTART
0
Note2
Note 1
3
2
1
0
CLS
CSS
0
PCC2
PCC1
PCC0
CLS
CPU clock status
0
Main system clock
1
Subsystem clock
CSS
PCC2
PCC1
PCC0
0
0
0
0
fXP
0
0
1
fXP/2 (default)
0
1
0
fXP/2
2
0
1
1
fXP/2
3
1
0
0
fXP/2
4
0
0
0
fSUB/2
0
0
1
0
1
0
0
1
1
1
0
0
1
Other than above
CPU clock (fCPU) selection
Setting prohibited
Notes 1. Bit 5 is read-only.
2. XTSTART is used in combination with EXCLKS and OSCSELS (bits 5 and 4 of the Clock
operation mode select register (OSCCTL)). See (3)
Setting of operation mode for
subsystem clock pin.
Caution
Be sure to clear bits 3 and 7 to 0.
Remarks 1. fXP:
Main system clock oscillation frequency
2. fSUB: Subsystem clock oscillation frequency
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/LE2. Therefore, the relationship
between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 5-2.
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Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU)
Minimum Instruction Execution Time: 2/fCPU
Main System Clock
High-Speed System Clock
At 10 MHz
Operation
Note
At 20 MHz
Operation
Subsystem Clock
Internal High-Speed
Note
Oscillation Clock
At 8 MHz (TYP.) Operation
At 32.768 kHz Operation
fXP
0.2 μs
0.1 μs
0.25 μs (TYP.)
−
fXP/2
0.4 μs
0.2 μs
0.5 μs (TYP.)
−
fXP/2
2
0.8 μs
0.4 μs
1.0 μs (TYP.)
−
fXP/2
3
1.6 μs
0.8 μs
2.0 μs (TYP.)
−
fXP/2
4
3.2 μs
1.6 μs
4.0 μs (TYP.)
−
fSUB/2
−
122.1 μs
−
Note The main clock mode register (MCM) is used to set the main system clock supplied to CPU clock (highspeed system clock/internal high-speed oscillation clock) (see Figure 5-6).
(3) Setting of operation mode for subsystem clock pin
The operation mode for the subsystem clock pin can be set by using bit 6 (XTSTART) of the processor clock
control register (PCC) and bits 5 and 4 (EXCLKS, OSCSELS) of the clock operation mode select register
(OSCCTL) in combination.
Table 5-3. Setting of Operation Mode for Subsystem Clock Pin
PCC
OSCCTL
Subsystem Clock Pin
Operation Mode
P123/XT1 Pin
P124/XT2/EXCLKS
Pin
Bit 6
Bit 5
Bit 4
XTSTART
EXCLKS
OSCSELS
0
0
0
I/O port mode
I/O port
0
0
1
XT1 oscillation mode
Crystal resonator connection
0
1
0
I/O port mode
I/O port
0
1
1
External clock input mode
I/O port
1
×
×
XT1 oscillation mode
Crystal resonator connection
Caution
External clock input
Confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (CPU is operating
with main system clock) when changing the current values of XTSTART, EXCLKS, and
OSCSELS.
Remark
96
×: don’t care
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(4) Internal oscillation mode register (RCM)
This register sets the operation mode of internal oscillator.
RCM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 80HNote 1.
Figure 5-4. Format of Internal Oscillation Mode Register (RCM)
Note 1
Address: FFA0H
After reset: 80H
R/W
Note 2
Symbol
6
5
4
3
2
RCM
RSTS
0
0
0
0
0
LSRSTOP
RSTOP
RSTS
Status of internal high-speed oscillator
0
Waiting for accuracy stabilization of internal high-speed oscillator
1
Stability operating of internal high-speed oscillator
LSRSTOP
Internal low-speed oscillator oscillating/stopped
0
Internal low-speed oscillator oscillating
1
Internal low-speed oscillator stopped
RSTOP
Internal high-speed oscillator oscillating/stopped
0
Internal high-speed oscillator oscillating
1
Internal high-speed oscillator stopped
Notes 1. The value of this register is 00H immediately after a reset release but automatically
changes to 80H after internal high-speed oscillator has been stabilized.
2. Bit 7 is read-only.
Caution When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock
other than the internal high-speed oscillation clock. Specifically, set under either of
the following conditions.
• When MCS = 1 (when CPU operates with the high-speed system clock)
• When CLS = 1 (when CPU operates with the subsystem clock)
In addition, stop peripheral hardware that is operating on the internal high-speed
oscillation clock before setting RSTOP to 1.
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(5) Main OSC control register (MOC)
This register selects the operation mode of the high-speed system clock.
This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the
CPU operates with a clock other than the high-speed system clock.
MOC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 80H.
Figure 5-5. Format of Main OSC Control Register (MOC)
Address: FFA2H
After reset: 80H
R/W
Symbol
6
5
4
3
2
1
0
MOC
MSTOP
0
0
0
0
0
0
0
Control of high-speed system clock operation
MSTOP
X1 oscillation mode
External clock input mode
0
X1 oscillator operating
External clock from EXCLK pin is enabled
1
X1 oscillator stopped
External clock from EXCLK pin is disabled
Cautions 1. When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock
other than the high-speed system clock. Specifically, set under either of the
following conditions.
• When MCS = 0 (when CPU operates with the internal high-speed oscillation
clock)
• When CLS = 1 (when CPU operates with the subsystem clock)
In addition, stop peripheral hardware that is operating on the high-speed system
clock before setting MSTOP to 1.
2. Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select
register (OSCCTL) is 0 (I/O port mode).
3. The peripheral hardware cannot operate when the peripheral hardware clock is
stopped.
To resume the operation of the peripheral hardware after the
peripheral hardware clock has been stopped, initialize the peripheral hardware.
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(6) Main clock mode register (MCM)
This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware
clock.
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 5-6. Format of Main Clock Mode Register (MCM)
Address: FFA1H
After reset: 00H
R/W
Note
Symbol
7
6
5
4
3
MCM
0
0
0
0
0
XSEL
MCS
MCM0
XSEL
MCM0
Selection of clock supplied to main system clock and peripheral hardware
Main system clock (fXP)
0
0
Peripheral hardware clock (fPRS)
0
Internal high-speed oscillation clock
Internal high-speed oscillation clock
1
(fRH)
(fRH)
1
0
1
1
MCS
High-speed system clock (fXH)
High-speed system clock (fXH)
Main system clock status
0
Operates with internal high-speed oscillation clock
1
Operates with high-speed system clock
Note Bit 1 is read-only.
Cautions 1. XSEL can be changed only once after a reset release.
2. A clock other than fPRS is supplied to the following peripheral functions
regardless of the setting of XSEL and MCM0.
• Watchdog timer (operates with internal low-speed oscillation clock)
• When “fRL”, “fRL/27”, or “fRL/29” is selected as the count clock for 8-bit timer H1
(operates with internal low-speed oscillation clock)
• Peripheral hardware selects the external clock as the clock source
(Except when the external count clock of TM00 is selected (TI000 pin valid
edge))
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(7) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1
clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock,
the X1 clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of
MOC register) = 1 clear OSTC to 00H.
Figure 5-7. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H
After reset: 00H
R
Symbol
7
6
5
4
3
2
1
0
OSTC
0
0
0
MOST11
MOST13
MOST14
MOST15
MOST16
MOST11
MOST13
MOST14
MOST15
MOST16
Oscillation stabilization time status
fX = 10 MHz
1
1
1
0
0
1
0
0
1
0
0
1
0
0
0
fX = 20 MHz
11
204.8 μs min. 102.4 μs min.
13
819.2 μs min. 409.6 μs min.
14
1.64 ms min. 819.2 μs min.
15
3.27 ms min. 1.64 ms min.
16
6.55 ms min. 3.27 ms min.
2 /fX min.
2 /fX min.
2 /fX min.
1
1
1
1
0
2 /fX min.
1
1
1
1
1
2 /fX min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
2. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
3. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark
100
fX: X1 clock oscillation frequency
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(8) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP
mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired
oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can
be checked up to the time set using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets OSTS to 05H.
Figure 5-8. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H
After reset: 05H
R/W
Symbol
7
6
5
4
3
2
1
0
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Oscillation stabilization time selection
fX = 10 MHz
0
0
0
1
1
204.8 μs
102.4 μs
13
819.2 μs
409.6 μs
2 /fX
0
2 /fX
14
1.64 ms
819.2 μs
15
3.27 ms
1.64 ms
16
6.55 ms
3.27 ms
0
1
1
2 /fX
1
0
0
2 /fX
1
0
1
2 /fX
Other than above
fX = 20 MHz
11
Setting prohibited
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
2. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
3. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
4. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark
fX: X1 clock oscillation frequency
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5.4 System Clock Oscillator
5.4.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2
pins.
Figure 5-9 shows an example of the external circuit of the X1 oscillator.
Figure 5-9. Example of External Circuit of X1 Oscillator (Crystal or Ceramic Oscillation)
VSS
X1
X2
Crystal resonator
or
ceramic resonator
Cautions are listed on the next page.
5.4.2 XT1 oscillator
The XT1 oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins.
Figure 5-10 shows an example of the external circuit of the XT1 oscillator.
Figure 5-10. Example of External Circuit of XT1 Oscillator (Crystal Oscillation)
VSS
XT1
32.768
kHz
XT2
Cautions are listed on the next page.
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Cautions 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the
broken lines in the Figures 5-9 and 5-10 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do
not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power
consumption.
Figure 5-11 shows examples of incorrect resonator connection.
Figure 5-11. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
PORT
VSS
Remark
X1
X2
VSS
X1
X2
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
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Figure 5-11. Examples of Incorrect Resonator Connection (2/2)
(c) Wiring near high alternating current
(d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
VDD
Pmn
X1
X2
VSS
High current
VSS
A
X1
B
X2
C
High current
(e) Signals are fetched
VSS
Remark
X1
X2
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
Cautions 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1,
resulting in malfunctioning.
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5.4.3 When subsystem clock is not used
If it is not necessary to use the subsystem clock for low power consumption operations, or if not using the
subsystem clock as an I/O port, set the XT1 and XT2 pins to I/O mode (OSCSELS = 0) and connect them as follows.
Input (PM123/PM124 = 1):
Independently connect to VDD or VSS via a resistor.
Output (PM123/PM124 = 0): Leave open.
Remark
OSCSELS:
Bit 4 of clock operation mode select register (OSCCTL)
PM123, PM124: Bits 3 and 4 of port mode register 12 (PM12)
5.4.4 Internal high-speed oscillator
The internal high-speed oscillator is incorporated in the 78K0/LE2. Oscillation can be controlled by the internal
oscillation mode register (RCM).
After a reset release, the internal high-speed oscillator automatically starts oscillation (8 MHz (TYP.)).
5.4.5 Internal low-speed oscillator
The internal low-speed oscillator is incorporated in the 78K0/LE2.
The internal low-speed oscillation clock is only used as the watchdog timer and the clock of 8-bit timer H1. The
internal low-speed oscillation clock cannot be used as the CPU clock.
“Can be stopped by software” or “Cannot be stopped” can be selected by the option byte. When “Can be stopped
by software” is set, oscillation can be controlled by the internal oscillation mode register (RCM).
After a reset release, the internal low-speed oscillator automatically starts oscillation, and the watchdog timer is
driven (240 kHz (TYP.)) if the watchdog timer operation is enabled using the option byte.
5.4.6 Prescaler
The prescaler generates various clocks by dividing the main system clock when the main system clock is selected
as the clock to be supplied to the CPU.
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5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
mode (see Figure 5-1).
• Main system clock fXP
• High-speed system clock fXH
X1 clock fX
External main system clock fEXCLK
• Internal high-speed oscillation clock fRH
• Subsystem clock fSUB
• XT1 clock fXT
• External subsystem clock fEXCLKS
• Internal low-speed oscillation clock fRL
• CPU clock fCPU
• Peripheral hardware clock fPRS
The CPU starts operation when the internal high-speed oscillator starts outputting after a reset release in the
78K0/LE2, thus enabling the following.
(1) Enhancement of security function
When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is
damaged or badly connected and therefore does not operate after reset is released. However, the start clock of
the CPU is the internal high-speed oscillation clock, so the device can be started by the internal high-speed
oscillation clock after a reset release. Consequently, the system can be safely shut down by performing a
minimum operation, such as acknowledging a reset source by software or performing safety processing when
there is a malfunction.
(2) Improvement of performance
Because the CPU can be started without waiting for the X1 clock oscillation stabilization time, the total
performance can be improved.
When the power supply voltage is turned on, the clock generator operation is shown in Figure 5-12.
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Figure 5-12. Clock Generator Operation When Power Supply Voltage Is Turned On
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
Power supply
voltage (VDD)
1.8 V
1.59 V
(TYP.)
0.5 V/ms
(MAX.)
0V
Internal reset signal
CPU clock
Reset processing
(20 μ s (TYP.))
Waiting for
voltage stabilization
(3.24 ms (TYP.))
Internal high-speed oscillation clock
Switched by
software
High-speed system clock
Subsystem clock
Internal high-speed
oscillation clock (fRH)
High-speed
system clock (fXH)
(when X1 oscillation
selected)
Subsystem clock (fSUB)
(when XT1 oscillation
selected)
Waiting for oscillation
accuracy stabilization
X1 clock
oscillation stabilization time:
11
2 /fX to 216/fXNote
Starting X1 oscillation
is specified by software.
Starting XT1 oscillation
is specified by software.
When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
When the power supply voltage exceeds 1.59 V (TYP.), the reset is released and the internal high-speed
oscillator automatically starts oscillation.
When the power supply voltage rises with a slope of 0.5 V/ms (MAX.), the CPU starts operation on the
internal high-speed oscillation clock after the reset is released and after the stabilization times for the voltage
of the power supply and regulator have elapsed, and then reset processing is performed.
Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 5.6.1 Example of controlling highspeed system clock and (1) in 5.6.3 Example of controlling subsystem clock).
When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see (3) in 5.6.1 Example of controlling high-speed system clock and (3) in 5.6.3
Example of controlling subsystem clock).
Note
When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal
high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation
stabilization time counter status register (OSTC). If the CPU operates on the high-speed system clock (X1
oscillation), set the oscillation stabilization time when releasing STOP mode using the oscillation
stabilization time select register (OSTS).
Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MAX.) from power application until the
voltage reaches 1.8 V, input a low level to the RESET pin from power application until the
voltage reaches 1.8 V, or set the 2.7 V/1.59 V POC mode by using the option byte (POCMODE
= 1) (see Figure 5-13). By doing so, the CPU operates with the same timing as and
thereafter in Figure 5-12 after reset release by the RESET pin.
2. It is not necessary to wait for the oscillation stabilization time when an external clock input
from the EXCLK and EXCLKS pins is used.
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Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via
software settings.
The internal high-speed oscillation clock and high-speed system clock can be
stopped by executing the STOP instruction (see (4) in 5.6.1
Example of controlling high-speed
system clock, (3) in 5.6.2 Example of controlling internal high-speed oscillation clock, and (4) in
5.6.3 Example of controlling subsystem clock).
Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On
(When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1))
2.7 V (TYP.)
Power supply
voltage (VDD)
0V
Internal reset signal
Reset processing
(20 μs (TYP.))
Internal high-speed
oscillation clock
CPU clock
Switched by
software
High-speed system clock
Subsystem clock
Internal high-speed
oscillation clock (fRH)
High-speed
system clock (fXH)
(when X1 oscillation
selected)
Subsystem clock (fSUB)
(when XT1 oscillation
selected)
Waiting for oscillation
accuracy stabilization
X1 clock
oscillation stabilization time:
211/fX to 216/fXNote
Starting X1 oscillation
is specified by software.
Starting XT1 oscillation
is specified by software.
When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
When the power supply voltage exceeds 2.7 V (TYP.), the reset is released and the internal high-speed
oscillator automatically starts oscillation.
After the reset is released and reset processing is performed, the CPU starts operation on the internal highspeed oscillation clock.
Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 5.6.1 Example of controlling highspeed system clock and (1) in 5.6.3 Example of controlling subsystem clock).
When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see (3) in 5.6.1 Example of controlling high-speed system clock and (3) in 5.6.3
Example of controlling subsystem clock).
Note
When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal
high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation
stabilization time counter status register (OSTC). If the CPU operates on the high-speed system clock (X1
oscillation), set the oscillation stabilization time when releasing STOP mode using the oscillation
stabilization time select register (OSTS).
Caution It is not necessary to wait for the oscillation stabilization time when an external clock input from
the EXCLK and EXCLKS pins is used.
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Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via
software settings.
The internal high-speed oscillation clock and high-speed system clock can be
stopped by executing the STOP instruction (see (4) in 5.6.1
Example of controlling high-speed
system clock, (3) in 5.6.2 Example of controlling internal high-speed oscillation clock, and (4) in
5.6.3 Example of controlling subsystem clock).
5.6 Controlling Clock
5.6.1 Example of controlling high-speed system clock
The following two types of high-speed system clocks are available.
• X1 clock:
Crystal/ceramic resonator is connected across the X1 and X2 pins.
• External main system clock: External clock is input to the EXCLK pin.
When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as I/O port
pins.
Caution The X1/P121 and X2/EXCLK/P122 pins are in the I/O port mode after a reset release.
The following describes examples of setting procedures for the following cases.
(1) When oscillating X1 clock
(2) When using external main system clock
(3) When using high-speed system clock as CPU clock and peripheral hardware clock
(4) When stopping high-speed system clock
(1) Example of setting procedure when oscillating the X1 clock
Setting frequency (OSCCTL register)
Using AMPH, set the gain of the on-chip oscillator according to the frequency to be used.
Note
AMPH
Operating Frequency Control
0
1 MHz ≤ f XH ≤ 10 MHz
1
10 MHz < f XH ≤ 20 MHz
Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can
be changed only once after a reset release. When AMPH is set to 1, the clock supply to the CPU
is stopped for 5 μs (MIN.).
Remark fXH: High-speed system clock oscillation frequency
Setting P121/X1 and P122/X2/EXCLK pins and selecting X1 clock or external clock (OSCCTL register)
When EXCLK is cleared to 0 and OSCSEL is set to 1, the mode is switched from port mode to X1
oscillation mode.
EXCLK
OSCSEL
Operation Mode of High-
P121/X1 Pin
P122/X2/EXCLK Pin
Speed System Clock Pin
0
1
X1 oscillation mode
Crystal/ceramic resonator connection
Controlling oscillation of X1 clock (MOC register)
If MSTOP is cleared to 0, the X1 oscillator starts oscillating.
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Waiting for the stabilization of the oscillation of X1 clock
Check the OSTC register and wait for the necessary time.
During the wait time, other software processing can be executed with the internal high-speed oscillation
clock.
Cautions 1. Do not change the value of EXCLK and OSCSEL while the X1 clock is operating.
2. Set the X1 clock after the supply voltage has reached the operable voltage of the clock to
be used (see CHAPTER 27 ELECTRICAL SPECIFICATIONS).
(2) Example of setting procedure when using the external main system clock
Setting frequency (OSCCTL register)
Using AMPH, set the frequency to be used.
Note
AMPH
Operating Frequency Control
0
1 MHz ≤ f XH ≤ 10 MHz
1
10 MHz < f XH ≤ 20 MHz
Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can
be changed only once after a reset release. When AMPH is set to 1, the clock supply to the CPU
is stopped for 5 μs (MIN.).
Remark fXH: High-speed system clock oscillation frequency
Setting P121/X1 and P122/X2/EXCLK pins and selecting operation mode (OSCCTL register)
When EXCLK and OSCSEL are set to 1, the mode is switched from port mode to external clock input
mode.
EXCLK
OSCSEL
Operation Mode of High-
P121/X1 Pin
P122/X2/EXCLK Pin
Speed System Clock Pin
1
1
External clock input mode
I/O port
External clock input
Controlling external main system clock input (MOC register)
When MSTOP is cleared to 0, the input of the external main system clock is enabled.
Cautions 1. Do not change the value of EXCLK and OSCSEL while the external main system clock is
operating.
2. Set the external main system clock after the supply voltage has reached the operable
voltage of the clock to be used (see CHAPTER 27 ELECTRICAL SPECIFICATIONS).
(3) Example of setting procedure when using high-speed system clock as CPU clock and peripheral
hardware clock
Setting high-speed system clock oscillationNote
(See 5.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of
setting procedure when using the external main system clock.)
Note The setting of is not necessary when high-speed system clock is already operating.
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Setting the high-speed system clock as the main system clock (MCM register)
When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock
and peripheral hardware clock.
XSEL
MCM0
Selection of Main System Clock and Clock Supplied to Peripheral Hardware
Main System Clock (f XP )
1
1
Peripheral Hardware Clock (f PRS )
High-speed system clock (f XH )
High-speed system clock (f XH )
Caution If the high-speed system clock is selected as the main system clock, a clock other than
the high-speed system clock cannot be set as the peripheral hardware clock.
Setting the main system clock as the CPU clock and selecting the division ratio (PCC register)
When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock
division ratio, use PCC0, PCC1, and PCC2.
CSS
PCC2
PCC1
PCC0
0
0
0
0
fXP
0
0
1
fXP/2 (default)
0
1
0
fXP/2
2
0
1
1
fXP/2
3
1
0
0
fXP/2
4
Other than above
CPU Clock (fCPU) Selection
Setting prohibited
(4) Example of setting procedure when stopping the high-speed system clock
The high-speed system clock can be stopped in the following two ways.
• Executing the STOP instruction to set the STOP mode
• Setting MSTOP to 1 and stopping the X1 oscillation (disabling clock input if the external clock is used)
(a) To execute a STOP instruction
Setting to stop peripheral hardware
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that
cannot be used in STOP mode, see CHAPTER 19 STANDBY FUNCTION).
Setting the X1 clock oscillation stabilization time after standby release
When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP
instruction is executed.
Executing the STOP instruction
When the STOP instruction is executed, the system is placed in the STOP mode and X1 oscillation
is stopped (the input of the external clock is disabled).
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(b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1
Confirming the CPU clock status (PCC and MCM registers)
Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock.
When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the
CPU clock to the subsystem clock or internal high-speed oscillation clock.
CLS
MCS
CPU Clock Status
0
0
Internal high-speed oscillation clock
0
1
High-speed system clock
1
×
Subsystem clock
Stopping the high-speed system clock (MOC register)
When MSTOP is set to 1, X1 oscillation is stopped (the input of the external clock is disabled).
Caution Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop
peripheral hardware that is operating on the high-speed system clock.
5.6.2 Example of controlling internal high-speed oscillation clock
The following describes examples of clock setting procedures for the following cases.
(1) When restarting oscillation of the internal high-speed oscillation clock
(2) When using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or highspeed system clock as peripheral hardware clock
(3) When stopping the internal high-speed oscillation clock
(1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clockNote 1
Setting restart of oscillation of the internal high-speed oscillation clock (RCM register)
When RSTOP is cleared to 0, the internal high-speed oscillation clock starts operating.
Waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (RCM
register)
Wait until RSTS is set to 1Note 2.
Notes 1. After a reset release, the internal high-speed oscillator automatically starts oscillating and the
internal high-speed oscillation clock is selected as the CPU clock.
2. This wait time is not necessary if high accuracy is not necessary for the CPU clock and peripheral
hardware clock.
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(2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and
internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock
• Restarting oscillation of the internal high-speed oscillation clockNote
(See 5.6.2 (1) Example of setting procedure when restarting internal high-speed oscillation
clock).
• Oscillating the high-speed system clockNote
(This setting is required when using the high-speed system clock as the peripheral hardware clock.
See 5.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of
setting procedure when using the external main system clock.)
Note The setting of is not necessary when the internal high-speed oscillation clock or highspeed system clock is already operating.
Selecting the clock supplied as the main system clock and peripheral hardware clock (MCM register)
Set the main system clock and peripheral hardware clock using XSEL and MCM0.
XSEL
MCM0
Selection of Main System Clock and Clock Supplied to Peripheral Hardware
Main System Clock (f XP )
0
0
0
1
1
0
Peripheral Hardware Clock (f PRS )
Internal high-speed oscillation clock
(f RH )
Internal high-speed oscillation clock
(f RH )
High-speed system clock (f XH )
Selecting the CPU clock division ratio (PCC register)
When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock
division ratio, use PCC0, PCC1, and PCC2.
CSS
PCC2
PCC1
PCC0
0
0
0
0
fXP
0
0
1
fXP/2 (default)
0
1
0
fXP/2
2
0
1
1
fXP/2
3
1
0
0
fXP/2
4
Other than above
CPU Clock (fCPU) Selection
Setting prohibited
(3) Example of setting procedure when stopping the internal high-speed oscillation clock
The internal high-speed oscillation clock can be stopped in the following two ways.
• Executing the STOP instruction to set the STOP mode
• Setting RSTOP to 1 and stopping the internal high-speed oscillation clock
(a) To execute a STOP instruction
Setting of peripheral hardware
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that
cannot be used in STOP mode, see CHAPTER 19 STANDBY FUNCTION).
Setting the X1 clock oscillation stabilization time after standby release
When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP
instruction is executed.
Executing the STOP instruction
When the STOP instruction is executed, the system is placed in the STOP mode and internal highspeed oscillation clock is stopped.
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(b) To stop internal high-speed oscillation clock by setting RSTOP to 1
Confirming the CPU clock status (PCC and MCM registers)
Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed
oscillation clock.
When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so
change the CPU clock to the high-speed system clock or subsystem clock.
CLS
MCS
CPU Clock Status
0
0
Internal high-speed oscillation clock
0
1
High-speed system clock
1
×
Subsystem clock
Stopping the internal high-speed oscillation clock (RCM register)
When RSTOP is set to 1, internal high-speed oscillation clock is stopped.
Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting RSTOP to 1. In addition, stop
peripheral hardware that is operating on the internal high-speed oscillation clock.
5.6.3 Example of controlling subsystem clock
The following two types of subsystem clocks are available.
• XT1 clock:
Crystal/ceramic resonator is connected across the XT1 and XT2 pins.
• External subsystem clock: External clock is input to the EXCLKS pin.
When the subsystem clock is not used, the XT1/P123 and XT2/EXCLKS/P124 pins can be used as I/O port pins.
Caution The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset release.
The following describes examples of setting procedures for the following cases.
(1) When oscillating XT1 clock
(2) When using external subsystem clock
(3) When using subsystem clock as CPU clock
(4) When stopping subsystem clock
(1) Example of setting procedure when oscillating the XT1 clock
Setting XT1 and XT2 pins and selecting operation mode (PCC and OSCCTL registers)
When XTSTART, EXCLKS, and OSCSELS are set as any of the following, the mode is switched from
port mode to XT1 oscillation mode.
XTSTART
EXCLKS
OSCSELS
Operation Mode of
P123/XT1 Pin
Subsystem Clock Pin
0
0
1
1
×
×
Remark
XT1 oscillation mode
P124/XT2/
EXCLKS Pin
Crystal/ceramic resonator connection
×: don’t care
Waiting for the stabilization of the subsystem clock oscillation
Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function.
Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is
operating.
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(2) Example of setting procedure when using the external subsystem clock
Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and
OSCCTL registers)
When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set to 1, the mode is switched from
port mode to external clock input mode. In this case, input the external clock to the EXCLKS/XT2/P124
pins.
XTSTART
EXCLKS
OSCSELS
0
1
1
Operation Mode of
Subsystem Clock Pin
External clock input
mode
P123/XT1 Pin
I/O port
P124/XT2/
EXCLKS Pin
External clock input
Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is
operating.
(3) Example of setting procedure when using the subsystem clock as the CPU clock
Setting subsystem clock oscillationNote
(See 5.6.3 (1) Example of setting procedure when oscillating the XT1 clock and (2) Example of
setting procedure when using the external subsystem clock.)
Note The setting of is not necessary when while the subsystem clock is operating.
Switching the CPU clock (PCC register)
When CSS is set to 1, the subsystem clock is supplied to the CPU.
CSS
PCC2
PCC1
PCC0
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Other than above
CPU Clock (fCPU) Selection
fSUB/2
Setting prohibited
(4) Example of setting procedure when stopping the subsystem clock
Confirming the CPU clock status (PCC and MCM registers)
Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock.
When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal
high-speed oscillation clock or high-speed system clock.
CLS
MCS
CPU Clock Status
0
0
Internal high-speed oscillation clock
0
1
High-speed system clock
1
×
Subsystem clock
Stopping the subsystem clock (OSCCTL register)
When OSCSELS is cleared to 0, XT1 oscillation is stopped (the input of the external clock is disabled).
Caution1. Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the watch
timer if it is operating on the subsystem clock.
2. The subsystem clock oscillation cannot be stopped using the STOP instruction.
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5.6.4 Example of controlling internal low-speed oscillation clock
The internal low-speed oscillation clock cannot be used as the CPU clock.
Only the following peripheral hardware can operate with this clock.
• Watchdog timer
• 8-bit timer H1 (if fRL is selected as the count clock)
In addition, the following operation modes can be selected by the option byte.
• Internal low-speed oscillator cannot be stopped
• Internal low-speed oscillator can be stopped by software
The internal low-speed oscillator automatically starts oscillation after a reset release, and the watchdog timer is
driven (240 kHz (TYP.)) if the watchdog timer operation has been enabled by the option byte.
(1) Example of setting procedure when stopping the internal low-speed oscillation clock
Setting LSRSTOP to 1 (RCM register)
When LSRSTOP is set to 1, the internal low-speed oscillation clock is stopped.
(2) Example of setting procedure when restarting oscillation of the internal low-speed oscillation clock
Clearing LSRSTOP to 0 (RCM register)
When LSRSTOP is cleared to 0, the internal low-speed oscillation clock is restarted.
Caution If “Internal low-speed oscillator cannot be stopped” is selected by the option byte, oscillation of
the internal low-speed oscillation clock cannot be controlled.
5.6.5 Clocks supplied to CPU and peripheral hardware
The following table shows the relation among the clocks supplied to the CPU and peripheral hardware, and setting
of registers.
Table 5-4. Clocks Supplied to CPU and Peripheral Hardware, and Register Setting
Supplied Clock
Clock Supplied to CPU
XSEL
CSS
MCM0
EXCLK
Clock Supplied to Peripheral Hardware
0
0
×
×
X1 clock
1
0
0
0
External main system clock
1
0
0
1
X1 clock
1
0
1
0
External main system clock
1
0
1
1
Internal high-speed oscillation clock
0
1
×
×
X1 clock
1
1
0
0
1
1
1
0
1
1
0
1
1
1
1
1
Internal high-speed oscillation clock
Internal high-speed oscillation clock
Subsystem clock
External main system clock
Remarks 1. XSEL:
Bit 2 of the main clock mode register (MCM)
2. CSS:
Bit 4 of the processor clock control register (PCC)
3. MCM0:
Bit 0 of MCM
4. EXCLK: Bit 7 of the clock operation mode select register (OSCCTL)
5. ×:
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5.6.6 CPU clock status transition diagram
Figure 5-14 shows the CPU clock status transition diagram of this product.
Figure 5-14. CPU Clock Status Transition Diagram
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
Internal low-speed oscillation: Woken up
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation/EXCLKS input: Stops (I/O port mode)
Power ON
VDD < 1.59 V (TYP.)
(A)
VDD 1.59 V (TYP.)
Reset release
Internal low-speed oscillation: Operating
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation/EXCLKS input: Stops (I/O port mode)
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation/EXCLKS input: Operating
(D)
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation/EXCLKS input:
Selectable by CPU
CPU: Operating
with internal highspeed oscillation
(H)
CPU: Internal highspeed oscillation
→ STOP
CPU: Operating
with XT1 oscillation or
EXCLKS input
(E)
CPU: Internal highspeed oscillation
→ HALT
(C)
(G)
CPU: XT1
oscillation/EXCLKS
input → HALT
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operable
X1 oscillation/EXCLK input: Operable
XT1 oscillation/EXCLKS input:
Operating
VDD 1.8 V (MIN.)
(B)
CPU: Operating
with X1 oscillation or
EXCLK input
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input:
Selectable by CPU
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input: Operable
XT1 oscillation/EXCLKS input:
Operable
(I)
CPU: X1
oscillation/EXCLK
input → STOP
(F)
CPU: X1
oscillation/EXCLK
input → HALT
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operable
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input: Operable
Remark
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Stops
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation: Stops
In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the
above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (20 μs
(TYP.)).
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Table 5-5 shows transition of the CPU clock and examples of setting the SFR registers.
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (1/4)
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
Status Transition
SFR Register Setting
(A) → (B)
SFR registers do not have to be set (default status after reset release).
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
AMPH
EXCLK
OSCSEL
MSTOP
OSTC
XSEL
MCM0
1
1
1
1
1
1
1
1
Register
Status Transition
(A) → (B) → (C) (X1 clock: 1 MHz ≤ fXH ≤
0
0
1
0
10 MHz)
Must be
checked
(A) → (B) → (C) (external main clock: 1 MHz ≤
0
1
1
0
fXH ≤ 10 MHz)
Must not be
checked
(A) → (B) → (C) (X1 clock: 10 MHz < fXH ≤
1
0
1
0
20 MHz)
Must be
checked
(A) → (B) → (C) (external main clock: 10 MHz <
1
1
1
0
fXH ≤ 20 MHz)
Must not be
checked
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 27 ELECTRICAL SPECIFICATIONS).
(3) CPU operating with subsystem clock (D) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
XTSTART
EXCLKS
Waiting for
OSCSELS
CSS
Oscillation
Status Transition
Stabilization
(A) → (B) → (D) (XT1 clock)
(A) → (B) → (D) (external subsystem clock)
0
0
1
1
×
×
0
1
1
Necessary
1
Unnecessary
1
Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figure 5-14.
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
MSTOP:
Bit 7 of the main OSC control register (MOC)
XSEL, MCM0:
Bits 2 and 0 of the main clock mode register (MCM)
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×:
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Table 5-5. CPU Clock Transition and SFR Register Setting Examples (2/4)
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Note
AMPH
EXCLK
OSCSEL
OSTC
MSTOP
XSEL
Note
MCM0
Register
Status Transition
(B) → (C) (X1 clock: 1 MHz ≤ fXH ≤ 10 MHz)
0
0
1
0
Must be
1
1
1
1
1
1
1
1
checked
(B) → (C) (external main clock: 1 MHz ≤ fXH ≤
0
1
1
0
10 MHz)
Must not be
checked
(B) → (C) (X1 clock: 10 MHz < fXH ≤ 20 MHz)
1
0
1
0
Must be
checked
(B) → (C) (external main clock: 10 MHz < fXH ≤
1
1
1
0
20 MHz)
Must not be
checked
Unnecessary if these registers
Unnecessary if the
are already set
CPU is operating
with the high-speed
system clock
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
already been set.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 27 ELECTRICAL SPECIFICATIONS).
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
XTSTART
EXCLKS
Waiting for
OSCSELS
CSS
Oscillation
Status Transition
Stabilization
(B) → (D) (XT1 clock)
(B) → (D) (external subsystem clock)
0
0
1
1
×
×
0
1
1
Necessary
1
Unnecessary
1
Unnecessary if the CPU is operating
with the subsystem clock
Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figure 5-14.
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
MSTOP:
Bit 7 of the main OSC control register (MOC)
XSEL, MCM0:
Bits 2 and 0 of the main clock mode register (MCM)
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×:
Don’t care
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Table 5-5. CPU Clock Transition and SFR Register Setting Examples (3/4)
(6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
RSTOP
RSTS
MCM0
0
Confirm this flag is 1.
0
Status Transition
(C) → (B)
Unnecessary if the CPU is operating
with the internal high-speed oscillation clock
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
XTSTART
EXCLKS
Waiting for
OSCSELS
CSS
Oscillation
Status Transition
Stabilization
(C) → (D) (XT1 clock)
(C) → (D) (external subsystem clock)
0
0
1
1
×
×
0
1
1
Necessary
1
Unnecessary
1
Unnecessary if the CPU is operating
with the subsystem clock
(8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
RSTOP
RSTS
MCM0
CSS
0
Confirm this flag
0
0
Status Transition
(D) → (B)
is 1.
↑
Unnecessary if the CPU is operating
Unnecessary if
with the internal high-speed
XSEL is 0
oscillation clock
Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figure 5-14.
2. MCM0:
Bit 0 of the main clock mode register (MCM)
EXCLKS, OSCSELS: Bits 5 and 4 of the clock operation mode select register (OSCCTL)
120
RSTS, RSTOP:
Bits 7 and 0 of the internal oscillation mode register (RCM)
XTSTART, CSS:
Bits 6 and 4 of the processor clock control register (PCC)
×:
Don’t care
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CHAPTER 5 CLOCK GENERATOR
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (4/4)
(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
(Setting sequence of SFR registers)
Note
Setting Flag of SFR Register AMPH
EXCLK
OSCSEL
OSTC
MSTOP
XSEL
Note
MCM0
CSS
1
1
0
1
1
0
1
1
0
1
1
0
Register
Status Transition
(D) → (C) (X1 clock: 1 MHz ≤ fXH ≤
0
0
1
Must be
0
10 MHz)
checked
(D) → (C) (external main clock: 1 MHz ≤
0
1
1
0
Must not be
fXH ≤ 10 MHz
checked
(D) → (C) (X1 clock: 10 MHz < fXH ≤
1
0
1
Must be
0
20 MHz)
checked
(D) → (C) (external main clock: 10 MHz <
1
1
1
0
Must not be
fXH ≤ 20 MHz)
checked
Unnecessary if these registers
Unnecessary if the
Unnecessary if this register
are already set
CPU is operating
is already set
with the high-speed
system clock
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
already been set.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 27 ELECTRICAL SPECIFICATIONS).
(10) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
Status Transition
Setting
(B) → (E)
Executing HALT instruction
(C) → (F)
(D) → (G)
(11) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
(Setting sequence)
Status Transition
Setting
(B) → (H)
Stopping peripheral functions that
(C) → (I)
cannot operate in STOP mode
Executing STOP instruction
Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figure 5-14.
2. EXCLK, OSCSEL, AMPH: Bits 7, 6 and 0 of the clock operation mode select register (OSCCTL)
MSTOP:
Bit 7 of the main OSC control register (MOC)
XSEL, MCM0:
Bits 2 and 0 of the main clock mode register (MCM)
CSS:
Bit 4 of the processor clock control register (PCC)
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CHAPTER 5 CLOCK GENERATOR
5.6.7 Condition before changing CPU clock and processing after changing CPU clock
Condition before changing the CPU clock and processing after changing the CPU clock are shown below.
Table 5-6. Changing CPU Clock
CPU Clock
Before Change
Internal high-
Condition Before Change
Processing After Change
After Change
X1 clock
Stabilization of X1 oscillation
• Internal high-speed oscillator can be
speed oscillation
• MSTOP = 0, OSCSEL = 1, EXCLK = 0
clock
• After elapse of oscillation stabilization time
• Clock supply to CPU is stopped for 5 μs
External main
Enabling input of external clock from EXCLK
(MIN.) after AMPH has been set to 1.
system clock
pin
stopped (RSTOP = 1).
• MSTOP = 0, OSCSEL = 1, EXCLK = 1
X1 clock
Internal high-
Oscillation of internal high-speed oscillator
X1 oscillation can be stopped (MSTOP = 1).
External main
speed oscillation
• RSTOP = 0
External main system clock input can be
system clock
clock
Internal high-
XT1 clock
speed oscillation
clock
disabled (MSTOP = 1).
Stabilization of XT1 oscillation
Operating current can be reduced by
• XTSTART = 0, EXCLKS = 0,
stopping internal high-speed oscillator
OSCSELS = 1, or XTSTART = 1
• After elapse of oscillation stabilization time
X1 clock
(RSTOP = 1).
X1 oscillation can be stopped (MSTOP = 1).
External main
External main system clock input can be
system clock
disabled (MSTOP = 1).
Internal high-
External
Enabling input of external clock from
Operating current can be reduced by
speed oscillation
subsystem clock
EXCLKS pin
stopping internal high-speed oscillator
• XTSTART = 0, EXCLKS = 1,
(RSTOP = 1).
clock
OSCSELS = 1
X1 clock
X1 oscillation can be stopped (MSTOP = 1).
External main
External main system clock input can be
system clock
disabled (MSTOP = 1).
XT1 clock,
Internal high-
Oscillation of internal high-speed oscillator
XT1 oscillation can be stopped or external
external
speed oscillation
and selection of internal high-speed
subsystem clock input can be disabled
subsystem clock
clock
oscillation clock as main system clock
(OSCSELS = 0).
• RSTOP = 0, MCS = 0
X1 clock
Stabilization of X1 oscillation and selection
of high-speed system clock as main system
clock
subsystem clock input can be disabled
(OSCSELS = 0).
• MSTOP = 0, OSCSEL = 1, EXCLK = 0
• After elapse of oscillation stabilization time
• MCS = 1
External main
Enabling input of external clock from EXCLK
system clock
pin and selection of high-speed system
clock as main system clock
• MSTOP = 0, OSCSEL = 1, EXCLK = 1
• MCS = 1
122
• XT1 oscillation can be stopped or external
User’s Manual U17734EJ2V0UD
• Clock supply to CPU is stopped for 5 μs
(MIN.) after AMPH has been set to 1.
CHAPTER 5 CLOCK GENERATOR
5.6.8 Time required for switchover of CPU clock and main system clock
By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock
can be switched (between the main system clock and the subsystem clock) and the division ratio of the main system
clock can be changed.
The actual switchover operation is not performed immediately after rewriting to PCC; operation continues on the
pre-switchover clock for several clocks (see Table 5-7).
Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 5
(CLS) of the PCC register.
Table 5-7. Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor
Set Value Before
Set Value After Switchover
Switchover
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
8 clocks
0
1
0
4 clocks
4 clocks
1
16 clocks
0
0
1
0
0
0
1
1
0
1
0
0
1
×
×
×
16 clocks
16 clocks
16 clocks
2fXP/fSUB clocks
8 clocks
8 clocks
8 clocks
fXP/fSUB clocks
4 clocks
4 clocks
fXP/2fSUB clocks
0
1
1
2 clocks
2 clocks
2 clocks
1
0
0
1 clock
1 clock
1 clock
1 clock
2 clocks
×
×
×
2 clocks
2 clocks
2 clocks
2 clocks
fXP/4fSUB clocks
fXP/8fSUB clocks
2 clocks
Caution Selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the
main system clock to the subsystem clock (changing CSS from 0 to 1) should not be set
simultaneously.
Simultaneous setting is possible, however, for selection of the main system clock cycle division
factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock
(changing CSS from 1 to 0).
Remarks 1. The number of clocks listed in Table 5-7 is the number of CPU clocks before switchover.
2. When switching the CPU clock from the subsystem clock to the main system clock, calculate the
number of clocks by rounding up to the next clock and discarding the decimal portion, as shown
below.
Example When switching CPU clock from fSUB/2 to fXP/2 (@ oscillation with fSUB = 32.768 kHz, fXP =
10 MHz)
fXP/fSUB = 10000/32.768 ≅ 305.1 → 306 clocks
By setting bit 0 (MCM0) of the main clock mode register (MCM), the main system clock can be switched (between
the internal high-speed oscillation clock and the high-speed system clock).
The actual switchover operation is not performed immediately after rewriting to MCM0; operation continues on the
pre-switchover clock for several clocks (see Table 5-8).
Whether the CPU is operating on the internal high-speed oscillation clock or the high-speed system clock can be
ascertained using bit 1 (MCS) of MCM.
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CHAPTER 5 CLOCK GENERATOR
Table 5-8. Maximum Time Required for Main System Clock Switchover
Set Value Before Switchover
Set Value After Switchover
MCM0
MCM0
0
0
1
1 + 2fRH/fXH clock
1
1 + 2fXH/fRH clock
Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2
(XSEL) of MCM must be set to 1 in advance. The value of XSEL can be changed only once after a
reset release.
Remarks 1. The number of clocks listed in Table 5-8 is the number of main system clocks before switchover.
2. Calculate the number of clocks in Table 5-8 by removing the decimal portion.
Example When switching the main system clock from the internal high-speed oscillation clock to the
high-speed system clock (@ oscillation with fRH = 8 MHz, fXH = 10 MHz)
1 + 2fRH/fXH = 1 + 2 × 8/10 = 1 + 2 × 0.8 = 1 + 1.6 = 2.6 → 2 clocks
5.6.9 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 5-9. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock
Conditions Before Clock Oscillation Is Stopped
Flag Settings of SFR
(External Clock Input Disabled)
Register
Internal high-speed
MCS = 1 or CLS = 1
oscillation clock
(The CPU is operating on a clock other than the internal high-speed
RSTOP = 1
oscillation clock)
X1 clock
MCS = 1 or CLS = 1
External main system clock
(The CPU is operating on a clock other than the high-speed system clock)
XT1 clock
CLS = 0
External subsystem clock
(The CPU is operating on a clock other than the subsystem clock)
124
MSTOP = 1
OSCSELS = 0
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CHAPTER 5 CLOCK GENERATOR
5.6.10 Peripheral hardware and source clocks
The following lists peripheral hardware and source clocks incorporated in the 78K0/LE2.
Table 5-10. Peripheral Hardware and Source Clocks
Source Clock
Peripheral Hardware
16-bit timer/
event counter 00
Peripheral
Hardware Clock
(fPRS)
Subsystem Clock
(fSUB)
Internal LowSpeed Oscillation
Clock (fRL)
TM50 Output
Y
N
N
N
Y (TI000 pin)
External Clock
from Peripheral
Hardware Pins
Note
8-bit timer/
event counter
50
Y
N
N
N
Y (TI50 pin)
Note
51
Y
N
N
N
Y (TI51 pin)
Note
8-Bit timer
H0
Y
N
N
Y
H1
N
Y
N
Y
N
N
Watch timer
Y
Y
N
N
N
Watchdog timer
N
N
Y
N
N
Clock output
Y
Y
N
N
N
A/D converter
Y
N
N
N
N
UART0
Y
N
N
Y
N
UART6
Y
N
N
Y
N
CSI10
Y
N
N
N
Serial interface
IIC0
LCD controller/driver
Y
N
N
N
Y
Y
N
N
Note
Y (SCK10 pin)
Note
Y (SCL0 pin)
N
Note When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been
stopped, do not start operation of these functions on the external clock input from peripheral hardware pins.
Remark
Y: Can be selected, N: Cannot be selected
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.1 Functions of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 has the following functions.
(1) Interval timer
16-bit timer/event counter 00 generates an interrupt request at the preset time interval.
(2) Square-wave output
16-bit timer/event counter 00 can output a square wave with any selected frequency.
(3) External event counter
16-bit timer/event counter 00 can measure the number of pulses of an externally input signal.
(4) One-shot pulse output
16-bit timer event counter 00 can output a one-shot pulse whose output pulse width can be set freely.
(5) PPG output
16-bit timer/event counter 00 can output a rectangular wave whose frequency and output pulse width can be set
freely.
(6) Pulse width measurement
16-bit timer/event counter 00 can measure the pulse width of an externally input signal.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
6.2 Configuration of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 includes the following hardware.
Table 6-1. Configuration of 16-Bit Timer/Event Counter 00
Item
Configuration
Time/counter
16-bit timer counter 00 (TM00)
Register
16-bit timer capture/compare registers 000, 010 (CR000, CR010)
Timer input
TI000, TI010 pins
Timer output
TO00 pin, output controller
Control registers
16-bit timer mode control register 00 (TMC00)
16-bit timer capture/compare control register 00 (CRC00)
16-bit timer output control register 00 (TOC00)
Prescaler mode register 00 (PRM00)
Port mode register 0 (PM0)
Port register 0 (P0)
Figures 6-1 shows the block diagrams.
Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00
Internal bus
Capture/compare control
register 00 (CRC00)
Selector
CRC002CRC001 CRC000
Noise
eliminator
TI010/TO00/P01
Selector
To CR010
16-bit timer capture/compare
register 000 (CR000)
INTTM000
Match
Noise
eliminator
16-bit timer counter 00
(TM00)
Output
controller
TO00/TI010/
P01
Match
2
Output latch
(P01)
Noise
eliminator
TI000/P00
Clear
PM01
16-bit timer capture/compare
register 010 (CR010)
Selector
fPRS
Selector
fPRS
fPRS/22
fPRS/28
INTTM010
CRC002
PRM001 PRM000
Prescaler mode
register 00 (PRM00)
TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
16-bit timer output
16-bit timer mode
control register 00
control register 00
(TOC00)
(TMC00)
Internal bus
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(1) 16-bit timer counter 00 (TM00)
TM00 is a 16-bit read-only register that counts count pulses.
The counter is incremented in synchronization with the rising edge of the count clock.
If the count value is read during operation, then input of the count clock is temporarily stopped, and the count
value at that point is read.
Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00)
Address: FF10H, FF11H
After reset: 0000H
R
FF11H
15
14
13
12
FF10H
11
10
9
8
7
6
5
4
3
2
1
0
TM00
The count value of TM00 can be read by reading TM00 when the value of bits 3 and 2 (TMC003 and TMC002) of
16-bit timer mode control register 00 (TMC00) is other than 00. The value of TM00 is 0000H if it is read when
TMC003 and TMC002 = 00.
The count value is reset to 0000H in the following cases.
• At reset signal generation
• If TMC003 and TMC002 are cleared to 00
• If the valid edge of the TI000 pin is input in the mode in which the clear & start occurs when inputting the valid
edge to the TI000 pin
• If TM00 and CR000 match in the mode in which the clear & start occurs when TM00 and CR000 match
• OSPT00 is set to 1 in one-shot pulse output mode or the valid edge is input to the TI000 pin
Cautions 1. Even if TM00 is read, the value is not captured by CR010.
2. When TM00 is read, input of the count clock is temporarily stopped and it is resumed after
the timer has been read. Therefore, no clock miss occurs.
(2) 16-bit timer capture/compare register 000 (CR000)), 16-bit timer capture/compare register 010 (CR010)
CR000 and CR010 are 16-bit registers that are used with a capture function or comparison function selected by
using CRC00.
Change the value of CR000 while the timer is stopped (TMC003 and TMC002 = 00).
The value of CR010 can be changed during operation if the value has been set in a specific way. For details, see
6.5.1 Rewriting CR010 during TM00 operation.
These registers can be read or written in 16-bit units.
Reset signal generation sets these registers to 0000H.
Figure 6-3. Format of 16-Bit Timer Capture/Compare Register 000 (CR000)
Address: FF12H, FF13H
After reset: 0000H
R/W
FF13H
15
14
13
12
FF12H
11
10
9
8
7
6
CR000
128
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4
3
2
1
0
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
(i) When CR000 is used as a compare register
The value set in CR000 is constantly compared with the TM00 count value, and an interrupt request signal
(INTTM000) is generated if they match. The value is held until CR000 is rewritten.
(ii) When CR000 is used as a capture register
The count value of TM00 is captured to CR000 when a capture trigger is input.
As the capture trigger, an edge of a phase reverse to that of the TI000 pin or the valid edge of the TI010 pin
can be selected by using CRC00 or PRM00.
Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010)
Address: FF14H, FF15H
After reset: 0000H
R/W
FF15H
15
14
13
12
FF14H
11
10
9
8
7
6
5
4
3
2
1
0
CR010
(i) When CR010 is used as a compare register
The value set in CR010 is constantly compared with the TM00 count value, and an interrupt request signal
(INTTM010) is generated if they match.
(ii) When CR010 is used as a capture register
The count value of TM00 is captured to CR010 when a capture trigger is input.
It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 pin valid edge is set
by PRM00.
Cautions 1. To use this register as a compare register, set a value other than 0000H to CR000 and
CR010.
2. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same
time. Select either of the functions.
3. If clearing of its 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00
(TMC00) to 00 and input of the capture trigger conflict, then the captured data is undefined.
4. To change the mode from the capture mode to the comparison mode, first clear the TMC003
and TMC002 bits to 00, and then change the setting.
A value that has been once captured remains stored in CR000 unless the device is reset. If
the mode has been changed to the comparison mode, be sure to set a comparison value.
5. CR000/CR010 does not perform the capture operation when it is set in the comparison
mode, even if a capture trigger is input to it.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Table 6-2. Capture Operation of CR000 and CR010
External Input
Signal
TI010 Pin Input
TI000 Pin Input
Capture
Operation
Capture operation of
CRC001 = 1
Set values of ES001 and
CRC001 bit = 0
Set values of ES101 and
CR000
TI000 pin input
ES000
TI010 pin input
ES100
(reverse phase)
Position of edge to be
Position of edge to be
captured
captured
01: Rising
01: Rising
00: Falling
00: Falling
11: Both edges
11: Both edges
(cannot be captured)
INTTM000 signal is not
Interrupt signal
Capture operation of
TI000 pin input
CR010
Note
Interrupt signal
INTTM000 signal is
generated even if value
generated each time
is captured.
value is captured.
Set values of ES001 and
ES000
Position of edge to be
captured
01: Rising
00: Falling
11: Both edges
Interrupt signal
INTTM010 signal is
generated each time
value is captured.
Note The capture operation of CR010 is not affected by the setting of the CRC001 bit.
Caution To capture the count value of the TM00 register to the CR000 register by using the phase
reverse to that input to the TI000 pin, the interrupt request signal (INTTM000) is not generated
after the value has been captured. If the valid edge is detected on the TI010 pin during this
operation, the capture operation is not performed but the INTTM000 signal is generated as an
external interrupt signal. To not use the external interrupt, mask the INTTM000 signal.
Remark
CRC001: See 6.3 (2) Capture/compare control register 00 (CRC00).
ES101, ES100, ES001, ES000: See 6.3 (4) Prescaler mode register 00 (PRM00).
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
6.3 Registers Controlling 16-Bit Timer/Event Counter 00
Registers used to control 16-bit timer/event counter 00 are shown below.
• 16-bit timer mode control register 00 (TMC00)
• Capture/compare control register 00 (CRC00)
• 16-bit timer output control register 00 (TOC00)
• Prescaler mode register 00 (PRM00)
• Port mode register 0 (PM0)
• Port register 0 (P0)
(1) 16-bit timer mode control register 00 (TMC00)
TMC00 is an 8-bit register that sets the 16-bit timer/event counter 00 operation mode, TM00 clear mode, and
output timing, and detects an overflow.
Rewriting TMC00 is prohibited during operation (when TMC003 and TMC002 = other than 00). However, it can
be changed when TMC003 and TMC002 are cleared to 00 (stopping operation) and when OVF00 is cleared to 0.
TMC00 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets TMC00 to 00H.
Caution 16-bit timer/event counter 00 starts operation at the moment TMC002 and TMC003 are set to
values other than 00 (operation stop mode), respectively. Set TMC002 and TMC003 to 00 to
stop the operation.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Address: FFBAH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
TMC00
0
0
0
0
TMC003
TMC002
TMC001
OVF00
TMC003
TMC002
0
0
Operation enable of 16-bit timer/event counter 00
Disables TM00 operation. Stops supplying operating clock. Asynchronously resets
the internal circuit.
0
1
Free-running timer mode
1
0
Clear & start mode entered by TI000 pin valid edge input
1
1
Clear & start mode entered upon a match between TM00 and CR000
Note
TMC001
Condition to reverse timer output (TO00)
0
• Match between TM00 and CR000 or match between TM00 and CR010
1
• Match between TM00 and CR000 or match between TM00 and CR010
• Trigger input of TI000 pin valid edge
OVF00
Clear (0)
Set (1)
TM00 overflow flag
Clears OVF00 to 0 or TMC003 and TMC002 = 00
Overflow occurs.
OVF00 is set to 1 when the value of TM00 changes from FFFFH to 0000H in all the operation modes (free-running
timer mode, clear & start mode entered by TI000 pin valid edge input, and clear & start mode entered upon a match
between TM00 and CR000).
It can also be set to 1 by writing 1 to OVF00.
Note The TI000 pin valid edge is set by bits 5 and 4 (ES001, ES000) of prescaler mode register 00 (PRM00).
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
(2) Capture/compare control register 00 (CRC00)
CRC00 is the register that controls the operation of CR000 and CR010.
Changing the value of CRC00 is prohibited during operation (when TMC003 and TMC002 = other than 00).
CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears CRC00 to 00H.
Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00)
Address: FFBCH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
CRC00
0
0
0
0
0
CRC002
CRC001
CRC000
CRC002
CR010 operating mode selection
0
Operates as compare register
1
Operates as capture register
CRC001
CR000 capture trigger selection
0
Captures on valid edge of TI010 pin
1
Captures on valid edge of TI000 pin by reverse phase
Note
The valid edge of the TI010 and TI000 pin is set by PRM00.
If ES001 and ES000 are set to 11 (both edges) when CRC001 is 1, the valid edge of the TI000 pin cannot
be detected.
CRC000
CR000 operating mode selection
0
Operates as compare register
1
Operates as capture register
If TMC003 and TMC002 are set to 11 (clear & start mode entered upon a match between TM00 and
CR000), be sure to set CRC000 to 0.
Note When the valid edge is detected from the TI010 pin, the capture operation is not performed but the
INTTM000 signal is generated as an external interrupt signal.
Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse
two cycles longer than the count clock selected by prescaler mode register 00 (PRM00).
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-7. Example of CR010 Capture Operation (When Rising Edge Is Specified)
Valid edge
Count clock
TM00
N−3
N−2
N−1
N
N+1
TI000
Rising edge detection
CR010
N
INTTM010
(3) 16-bit timer output control register 00 (TOC00)
TOC00 is an 8-bit register that controls the TO00 pin output.
TOC00 can be rewritten while only OSPT00 is operating (when TMC003 and TMC002 = other than 00).
Rewriting the other bits is prohibited during operation.
However, TOC004 can be rewritten during timer operation as a means to rewrite CR010 (see 6.5.1 Rewriting
CR010 during TM00 operation).
TOC00 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears TOC00 to 00H.
Caution Be sure to set TOC00 using the following procedure.
Set TOC004 and TOC001 to 1.
Set only TOE00 to 1.
Set either of LVS00 or LVR00 to 1.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
Figure 6-8. Format of 16-Bit Timer Output Control Register 00 (TOC00)
Address: FFBDH
After reset: 00H
R/W
Symbol
7
4
1
TOC00
0
OSPT00
OSPE00
TOC004
LVS00
LVR00
TOC001
TOE00
OSPT00
One-shot pulse output trigger via software
0
−
1
One-shot pulse output
The value of this bit is always “0” when it is read. Do not set this bit to 1 in a mode other than the oneshot pulse output mode.
If it is set to 1, TM00 is cleared and started.
OSPE00
One-shot pulse output operation control
0
Successive pulse output
1
One-shot pulse output
One-shot pulse output operates correctly in the free-running timer mode or clear & start mode entered by
TI000 pin valid edge input.
The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM00 and
CR000.
TOC004
TO00 pin output control on match between CR010 and TM00
0
Disables inversion operation
1
Enables inversion operation
The interrupt signal (INTTM010) is generated even when TOC004 = 0.
LVS00
LVR00
Setting of TO00 pin output status
0
0
No change
0
1
Initial value of TO00 pin output is low level (TO00 pin output is cleared to 0).
1
0
Initial value of TO00 pin output is high level (TO00 pin output is set to 1).
1
1
Setting prohibited
• LVS00 and LVR00 can be used to set the initial value of the output level of the TO00 pin. If the initial
value does not have to be set, leave LVS00 and LVR00 as 00.
• Be sure to set LVS00 and LVR00 when TOE00 = 1.
LVS00, LVR00, and TOE00 being simultaneously set to 1 is prohibited.
• LVS00 and LVR00 are trigger bits. By setting these bits to 1, the initial value of the output level of the
TO00 pin can be set. Even if these bits are cleared to 0, output of the TO00 pin is not affected.
• The values of LVS00 and LVR00 are always 0 when they are read.
• For how to set LVS00 and LVR00, see 6.5.2 Setting LVS00 and LVR00.
TOC001
TO00 pin output control on match between CR000 and TM00
0
Disables inversion operation
1
Enables inversion operation
The interrupt signal (INTTM000) is generated even when TOC001 = 0.
TOE00
TO00 pin output control
0
Disables output (TO00 pin output fixed to low level)
1
Enables output
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(4) Prescaler mode register 00 (PRM00)
PRM00 is the register that sets the TM00 count clock and TI000 and TI010 pin input valid edges.
Rewriting PRM00 is prohibited during operation (when TMC003 and TMC002 = other than 00).
PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PRM00 to 00H.
Cautions 1. Do not apply the following setting when setting the PRM001 and PRM000 bits to 11 (to
specify the valid edge of the TI000 pin as a count clock).
• Clear & start mode entered by the TI000 pin valid edge
• Setting the TI000 pin as a capture trigger
2. If the operation of the 16-bit timer/event counter 00 is enabled when the TI000 or TI010 pin is
at high level and when the valid edge of the TI000 or TI010 pin is specified to be the rising
edge or both edges, the high level of the TI000 or TI010 pin is detected as a rising edge.
Note this when the TI000 or TI010 pin is pulled up. However, the rising edge is not detected
when the timer operation has been once stopped and then is enabled again.
3. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same
time. Select either of the functions.
Figure 6-8. Format of Prescaler Mode Register 00 (PRM00)
Address: FFBBH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
PRM00
ES101
ES100
ES001
ES000
0
0
PRM001
PRM000
ES101
ES100
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES001
ES000
TI010 pin valid edge selection
TI000 pin valid edge selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
PRM001
PRM000
Count clock selection
fPRS = 2 MHz
0
0
1
1
0
1
0
1
fPRS
fPRS = 5 MHz
fPRS = 10 MHz
fPRS = 20 MHz
2 MHz
5 MHz
10 MHz
20 MHz
fPRS/2
2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
fPRS/2
8
7.81 kHz
19.53 kHz
39.06 kHz
78.12 kHz
TI000 valid edge
Note
Note The external clock requires a pulse two cycles longer than internal clock (fPRS).
Remark
136
fPRS: Peripheral hardware clock frequency
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
(5) Port mode register 0 (PM0)
This register sets port 0 input/output in 1-bit units.
When using the P01/TO00/TI010 pin for timer output, set PM01 and the output latches of P01 to 0.
When using the P00/TI000 and P01/TO00/TI010 pins for timer input, set PM00 and PM01 to 1. At this time, the
output latches of P00 and P01 may be 0 or 1.
PM0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM0 to FFH.
Figure 6-10. Format of Port Mode Register 0 (PM0)
Address: FF20H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
PM0
1
1
1
1
1
1
PM0n
1
0
PM01 PM00
P0n pin I/O mode selection (n = 0, 1)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4 Operation of 16-Bit Timer/Event Counter 00
6.4.1 Interval timer operation
If bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register (TMC00) are set to 11 (clear & start
mode entered upon a match between TM00 and CR000), the count operation is started in synchronization with the
count clock.
When the value of TM00 later matches the value of CR000, TM00 is cleared to 0000H and a match interrupt signal
(INTTM000) is generated. This INTTM000 signal enables TM00 to operate as an interval timer.
Remarks 1. For the setting of I/O pins, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 interrupt, see CHAPTER 18 INTERRUPT FUNCTIONS.
Figure 6-11. Block Diagram of Interval Timer Operation
Clear
Count clock
16-bit counter (TM00)
Match signal
INTTM000 signal
Operable bits
TMC003, TMC002
CR000 register
Figure 6-12. Basic Timing Example of Interval Timer Operation
N
N
N
N
Interval
(N + 1)
Interval
(N + 1)
TM00 register
0000H
Operable bits
(TMC003, TMC002)
00
11
Compare register
(CR000)
N
Compare match interrupt
(INTTM000)
Interval
(N + 1)
138
Interval
(N + 1)
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
Figure 6-13. Example of Register Settings for Interval Timer Operation
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001
0
0
0
0
1
1
OVF00
0
0
Clears and starts on match
between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
0
0
0
0
0
0
0
0
CR000 used as
compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004
0
0
0
LVS00
LVR00
TOC001
TOE00
0
0
0
0
0
(d) Prescaler mode register 00 (PRM00)
ES101
ES100
ES001
ES000
3
2
0
0
0
0
0
0
PRM001 PRM000
0/1
0/1
Selects count clock
(e) 16-bit timer counter 00 (TM00)
By reading TM00, the count value can be read.
(f) 16-bit capture/compare register 000 (CR000)
If M is set to CR000, the interval time is as follows.
• Interval time = (M + 1) × Count clock cycle
Setting CR000 to 0000H is prohibited.
(g) 16-bit capture/compare register 010 (CR010)
Usually, CR010 is not used for the interval timer function. However, a compare match interrupt (INTTM010)
is generated when the set value of CR010 matches the value of TM00.
Therefore, mask the interrupt request by using the interrupt mask flag (TMMK010).
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-14. Example of Software Processing for Interval Timer Function
N
N
N
TM00 register
0000H
Operable bits
(TMC003, TMC002)
00
11
CR000 register
N
INTTM000 signal
Count operation start flow
START
Register initial setting
PRM00 register,
CRC00 register,
CR000 register,
port setting
TMC003, TMC002 bits = 11
Initial setting of these registers is performed before
setting the TMC003 and TMC002 bits to 11.
Starts count operation
Count operation stop flow
TMC003, TMC002 bits = 00
The counter is initialized and counting is stopped
by clearing the TMC003 and TMC002 bits to 00.
STOP
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6.4.2 Square wave output operation
When 16-bit timer/event counter 00 operates as an interval timer (see 6.4.1), a square wave can be output from the
TO00 pin by setting the 16-bit timer output control register 00 (TOC00) to 03H.
When TMC003 and TMC002 are set to 11 (count clear & start mode entered upon a match between TM00 and
CR000), the counting operation is started in synchronization with the count clock.
When the value of TM00 later matches the value of CR000, TM00 is cleared to 0000H, an interrupt signal
(INTTM000) is generated, and output of the TO00 pin is inverted. This TO00 pin output that is inverted at fixed
intervals enables TO00 to output a square wave.
Remarks 1. For the setting of I/O pins, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 signal interrupt, see CHAPTER 18 INTERRUPT FUNCTIONS.
Figure 6-15. Block Diagram of Square Wave Output Operation
Clear
Count clock
Output
controller
16-bit counter (TM00)
Match signal
TO00 pin
INTTM000 signal
Operable bits
TMC003, TMC002
CR000 register
Figure 6-16. Basic Timing Example of Square Wave Output Operation
N
N
N
N
Interval
(N + 1)
Interval
(N + 1)
TM00 register
0000H
Operable bits
(TMC003, TMC002)
00
11
Compare register
(CR000)
N
TO0n pin output
Compare match interrupt
(INTTM000)
Interval
(N + 1)
Interval
(N + 1)
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-17. Example of Register Settings for Square Wave Output Operation
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001
0
0
0
0
1
1
OVF00
0
0
Clears and starts on match
between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
0
0
0
0
0
0
0
0
CR000 used as
compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004
0
0
0
LVS00
LVR00
TOC001
TOE00
0
0
1
1
0
Enables TO00 pin output.
Inverts TO00 pin output on match
between TM00 and CR000.
(d) Prescaler mode register 00 (PRM00)
ES101
ES100
ES001
ES000
3
2
0
0
0
0
0
0
PRM001 PRM000
0/1
0/1
Selects count clock
(e) 16-bit timer counter 00 (TM00)
By reading TM00, the count value can be read.
(f) 16-bit capture/compare register 000 (CR000)
If M is set to CR000, the interval time is as follows.
• Square wave frequency = 1 / [2 × (M + 1) × Count clock cycle]
Setting CR000 to 0000H is prohibited.
(g) 16-bit capture/compare register 010 (CR010)
Usually, CR010 is not used for the square wave output function. However, a compare match interrupt
(INTTM010) is generated when the set value of CR010 matches the value of TM00.
Therefore, mask the interrupt request by using the interrupt mask flag (TMMK010).
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Figure 6-18. Example of Software Processing for Square Wave Output Function
N
N
N
TM00 register
0000H
Operable bits
(TMC003, TMC002)
00
11
CR000 register
N
TO00 pin output
INTTM000 signal
TO00 output control bit
(TOE00)
Count operation start flow
START
Register initial setting
PRM00 register,
CRC00 register,
TOC00 registerNote,
CR000 register,
port setting
TMC003, TMC002 bits = 11
Initial setting of these registers is performed before
setting the TMC003 and TMC002 bits to 11.
Starts count operation
Count operation stop flow
TMC003, TMC002 bits = 00
The counter is initialized and counting is stopped
by clearing the TMC003 and TMC002 bits to 00.
STOP
Note Care must be exercised when setting TOC00. For details, see 6.3 (3) 16-bit timer output control
register 00 (TOC00).
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4.3 External event counter operation
When bits 1 and 0 (PRM001 and PRM000) of the prescaler mode register 00 (PRM00) are set to 11 (for counting
up with the valid edge of the TI000 pin) and bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register
00 (TMC00) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating
matching between TM00 and CR000 (INTTM000) is generated.
To input the external event, the TI000 pin is used. Therefore, the timer/event counter cannot be used as an
external event counter in the clear & start mode entered by the TI000 pin valid edge input (when TMC003 and
TMC002 = 10).
The INTTM000 signal is generated with the following timing.
• Timing of generation of INTTM000 signal (second time or later)
= Number of times of detection of valid edge of external event × (Set value of CR000 + 1)
However, the first match interrupt immediately after the timer/event counter has started operating is generated with
the following timing.
• Timing of generation of INTTM000 signal (first time only)
= Number of times of detection of valid edge of external event input × (Set value of CR000 + 2)
To detect the valid edge, the signal input to the TI000 pin is sampled during the clock cycle of fPRS. The valid edge
is not detected until it is detected two times in a row. Therefore, a noise with a short pulse width can be eliminated.
Remarks 1. For the setting of I/O pins, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 signal interrupt, see CHAPTER 18 INTERRUPT FUNCTIONS.
Figure 6-19. Block Diagram of External Event Counter Operation
fPRS
Clear
TI000 pin
Edge
detection
16-bit counter (TM00)
Match signal
Operable bits
TMC003, TMC002
CR000 register
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Output
controller
INTTM000 signal
TO00 pin
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
Figure 6-20. Example of Register Settings in External Event Counter Mode
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001
0
0
0
0
1
1
OVF00
0
0
Clears and starts on match
between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
0
0
0
0
0
0
0
0
CR000 used as
compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004
0
0
0
LVS00
LVR00
TOC001
TOE00
0
0
0
0
0
(d) Prescaler mode register 00 (PRM00)
ES101
ES100
ES001
ES000
3
2
0
0
0/1
0/1
0
0
PRM001 PRM000
1
1
Selects count clock
(specifies valid edge of TI000).
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
(e) 16-bit timer counter 00 (TM00)
By reading TM00, the count value can be read.
(f) 16-bit capture/compare register 000 (CR000)
If M is set to CR000, the interrupt signal (INTTM000) is generated when the number of external events
reaches (M + 1).
Setting CR000 to 0000H is prohibited.
(g) 16-bit capture/compare register 010 (CR010)
Usually, CR010 is not used in the external event counter mode. However, a compare match interrupt
(INTTM010) is generated when the set value of CR010 matches the value of TM00.
Therefore, mask the interrupt request by using the interrupt mask flag (TMMK010).
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-21. Example of Software Processing in External Event Counter Mode
N
N
N
TM00 register
0000H
Operable bits
(TMC003, TMC002)
00
11
Compare register
(CR000)
N
Compare match signal
(INTTM000)
Count operation start flow
START
Register initial setting
PRM00 register,
CRC00 register,
CR000 register,
port setting
TMC003, TMC002 bits = 11
Initial setting of these registers is performed before
setting the TMC003 and TMC002 bits to 11.
Starts count operation
Count operation stop flow
TMC003, TMC002 bits = 00
The counter is initialized and counting is stopped
by clearing the TMC003 and TMC002 bits to 00.
STOP
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6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input
When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 10 (clear &
start mode entered by the TI000 pin valid edge input) and the count clock (set by PRM00) is supplied to the
timer/event counter, TM00 starts counting up. When the valid edge of the TI000 pin is detected during the counting
operation, TM00 is cleared to 0000H and starts counting up again. If the valid edge of the TI000 pin is not detected,
TM00 overflows and continues counting.
The valid edge of the TI000 pin is a cause to clear TM00. Starting the counter is not controlled immediately after
the start of the operation.
CR000 and CR010 are used as compare registers and capture registers.
(a) When CR000 and CR010 are used as compare registers
Signals INTTM000 and INTTM010 are generated when the value of TM00 matches the value of CR000 and
CR010.
(b) When CR000 and CR010 are used as capture registers
The count value of TM00 is captured to CR000 and the INTTM000 signal is generated when the valid edge is
input to the TI010 pin (or when the phase reverse to that of the valid edge is input to the TI000 pin).
When the valid edge is input to the TI000 pin, the count value of TM00 is captured to CR010 and the
INTTM010 signal is generated. As soon as the count value has been captured, the counter is cleared to
0000H.
Caution Do not set the count clock as the valid edge of the TI000 pin (PRM001 and PRM000 = 11). When
PRM001 and PRM000 = 11, TM00 is cleared.
Remarks 1. For the setting of the I/O pins, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 signal interrupt, see CHAPTER 18 INTERRUPT FUNCTIONS.
(1) Operation in clear & start mode entered by TI000 pin valid edge input
(CR000: compare register, CR010: compare register)
Figure 6-22. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Compare Register)
TI000 pin
Edge
detection
Clear
Count clock
Timer counter
(TM00)
Match signal
Interrupt signal
(INTTM000)
Operable bits
TMC003, TMC002
Compare register
(CR000)
Match signal
Output
controller
TO00 pin
Interrupt signal
(INTTM010)
Compare register
(CR010)
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-23. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Compare Register)
(a) TOC00 = 13H, PRM00 = 10H, CRC00, = 00H, TMC00 = 08H
M
TM00 register
N
M
N
M
N
M
N
0000H
Operable bits
(TMC003, TMC002)
00
10
Count clear input
(TI000 pin input)
Compare register
(CR000)
Compare match interrupt
(INTTM000)
M
Compare register
(CR010)
N
Compare match interrupt
(INTTM010)
TO00 pin output
(b) TOC00 = 13H, PRM00 = 10H, CRC00, = 00H, TMC00 = 0AH
M
TM00 register
N
M
N
M
N
M
N
0000H
Operable bits
(TMC003, TMC002)
00
10
Count clear input
(TI000 pin input)
Compare register
(CR000)
Compare match interrupt
(INTTM000)
Compare register
(CR010)
M
N
Compare match interrupt
(INTTM010)
TO00 pin output
(a) and (b) differ as follows depending on the setting of bit 1 (TMC001) of the 16-bit timer mode control register 01
(TMC00).
(a) The output level of the TO00 pin is inverted when TM00 matches a compare register.
(b) The output level of the TO00 pin is inverted when TM00 matches a compare register or when the valid
edge of the TI000 pin is detected.
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(2) Operation in clear & start mode entered by TI000 pin valid edge input
(CR000: compare register, CR010: capture register)
Figure 6-24. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Capture Register)
TI000 pin
Edge
detector
Clear
Timer counter
(TM00)
Count clock
Match signal
Interrupt signal
(INTTM000)
Operable bits
TMC003, TMC002
Compare register
(CR000)
Capture signal
Output
controller
TO00 pin
Interrupt signal
(INTTM010)
Capture register
(CR010)
Figure 6-25. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Capture Register) (1/2)
(a) TOC00 = 13H, PRM00 = 10H, CRC00, = 04H, TMC00 = 08H, CR000 = 0001H
M
N
P
TM00 register
Q
S
0000H
Operable bits
(TMC003, TMC002)
10
00
Capture & count clear input
(TI000 pin input)
Compare register
(CR000)
0001H
Compare match interrupt
(INTTM000)
Capture register
(CR010)
0000H
M
N
S
P
Q
Capture interrupt
(INTTM010)
TO00 pin output
This is an application example where the output level of the TO00 pin is inverted when the count value has been
captured & cleared.
The count value is captured to CR010 and TM00 is cleared (to 0000H) when the valid edge of the TI000 pin is
detected. When the count value of TM00 is 0001H, a compare match interrupt signal (INTTM000) is generated,
and the output level of the TO00 pin is inverted.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-25. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Capture Register) (2/2)
(b) TOC00 = 13H, PRM00 = 10H, CRC00, = 04H, TMC00 = 0AH, CR000 = 0003H
M
N
P
TM00 register
Q
S
0003H
0000H
Operable bits
(TMC003, TMC002)
00
10
Capture & count clear input
(TI000 pin input)
Compare register
(CR000)
0003H
Compare match interrupt
(INTTM000)
Capture register
(CR010)
0000H
M
N
S
P
Q
Capture interrupt
(INTTM010)
TO00 pin output
4
4
4
4
This is an application example where the width set to CR000 (4 clocks in this example) is to be output from the
TO00 pin when the count value has been captured & cleared.
The count value is captured to CR010, a capture interrupt signal (INTTM010) is generated, TM00 is cleared (to
0000H), and the output level of the TO00 pin is inverted when the valid edge of the TI000 pin is detected. When
the count value of TM00 is 0003H (four clocks have been counted), a compare match interrupt signal (INTTM000)
is generated and the output level of the TO00 pin is inverted.
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(3) Operation in clear & start mode by entered TI000 pin valid edge input
(CR000: capture register, CR010: compare register)
Figure 6-26. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Compare Register)
TI000 pin
Edge
detection
Clear
Timer counter
(TM00)
Count clock
Match signal
Interrupt signal
(INTTM010)
Operable bits
TMC003, TMC002
Compare register
(CR010)
Capture signal
Capture register
(CR000)
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controller
TO00 pin
Interrupt signal
(INTTM000)
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-27. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Compare Register) (1/2)
(a) TOC00 = 13H, PRM00 = 10H, CRC00, = 03H, TMC00 = 08H, CR010 = 0001H
TM00 register
M
P
N
0000H
Operable bits
(TMC003, TMC002)
S
00
10
Capture & count clear input
(TI000 pin input)
Capture register
(CR000)
Capture interrupt
(INTTM000)
Compare register
(CR010)
0000H
M
N
S
P
L
0001H
Compare match interrupt
(INTTM010)
TO00 pin output
This is an application example where the output level of the TO00 pin is to be inverted when the count value has
been captured & cleared.
TM00 is cleared at the rising edge detection of the TI000 pin and it is captured to CR000 at the falling edge
detection of the TI000 pin.
When bit 1 (CRC001) of capture/compare control register 00 (CRC00) is set to 1, the count value of TM00 is
captured to CR000 in the phase reverse to that of the signal input to the TI000 pin, but the capture interrupt signal
(INTTM000) is not generated. However, the INTTM000 signal is generated when the valid edge of the TI010 pin
is detected. Mask the INTTM000 signal when it is not used.
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Figure 6-27. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Compare Register) (2/2)
(b) TOC00 = 13H, PRM00 = 10H, CRC00, = 03H, TMC00 = 0AH, CR010 = 0003H
TM00 register
M
0003H
0000H
Operable bits
(TMC003, TMC002)
S
P
N
00
10
Capture & count clear input
(TI000 pin input)
Compare register
(CR000)
Compare match interrupt
(INTTM000)
Capture register
(CR010)
0000H
M
N
S
P
L
0003H
Capture interrupt
(INTTM010)
TO00 pin output
4
4
4
4
This is an application example where the width set to CR010 (4 clocks in this example) is to be output from the
TO00 pin when the count value has been captured & cleared.
TM00 is cleared (to 0000H) at the rising edge detection of the TI000 pin and captured to CR000 at the falling
edge detection of the TI000 pin. The output level of the TO00 pin is inverted when TM00 is cleared (to 0000H)
because the rising edge of the TI000 pin has been detected or when the value of TM00 matches that of a
compare register (CR010).
When bit 1 (CRC001) of capture/compare control register 00 (CRC00) is 1, the count value of TM00 is captured
to CR000 in the phase reverse to that of the input signal of the TI000 pin, but the capture interrupt signal
(INTTM000) is not generated. However, the INTTM000 interrupt is generated when the valid edge of the TI010
pin is detected. Mask the INTTM000 signal when it is not used.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(4) Operation in clear & start mode entered by TI000 pin valid edge input
(CR000: capture register, CR010: capture register)
Figure 6-28. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Capture Register)
Operable bits
TMC003, TMC002
Clear
Timer counter
(TM00)
Count clock
Capture register
(CR010)
Capture signal
Interrupt signal
(INTTM010)
Output
controller
TI010 pin
Note
Edge
detection
Selector
TI000 pin
Edge
detection
TO00 pinNote
Capture register
(CR000)
Capture
signal
Interrupt signal
(INTTM000)
Note The timer output (TO00) cannot be used when detecting the valid edge of the TI010 pin is used.
Figure 6-29. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Capture Register) (1/3)
(a) TOC00 = 13H, PRM00 = 30H, CRC00 = 05H, TMC00 = 0AH
L
TM00 register
N
M
O
Q
P
R
S
T
0000H
Operable bits
(TMC003, TMC002)
00
10
Capture & count clear input
(TI000 pin input)
Capture register
(CR000)
Capture interrupt
(INTTM000)
Capture register
(CR010)
0000H
L
0000H
L
M
N
O
P
Q
R
S
T
Capture interrupt
(INTTM010)
TO00 pin output
This is an application example where the count value is captured to CR010, TM00 is cleared, and the TO00 pin
output is inverted when the rising or falling edge of the TI000 pin is detected.
When the edge of the TI010 pin is detected, an interrupt signal (INTTM000) is generated. Mask the INTTM000
signal when it is not used.
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Figure 6-29. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Capture Register) (2/3)
(b) TOC00 = 13H, PRM00 = C0H, CRC00 = 05H, TMC00 = 0AH
FFFFH
N
M
00
T
Q
S
P
0000H
Operable bits
(TMC003, TMC002)
R
O
L
TM00 register
10
Capture trigger input
(TI010 pin input)
Capture register
(CR000)
0000H
L
M
N
O
P
Q
R
S
T
Capture interrupt
(INTTM000)
Capture & count clear input
(TI000)
L
Capture register
(CR010)
Capture interrupt
(INTTM010)
0000H
L
This is a timing example where an edge is not input to the TI000 pin, in an application where the count value is
captured to CR000 when the rising or falling edge of the TI010 pin is detected.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-29. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Capture Register) (3/3)
(c) TOC00 = 13H, PRM00 = 00H, CRC00 = 07H, TMC00 = 0AH
O
M
TM00 register
N
L
S
Q
W
T
R
P
0000H
Operable bits
(TMC003, TMC002)
10
00
Capture & count clear input
(TI000 pin input)
Capture register
(CR000)
0000H
Capture register
(CR010)
L
0000H
N
M
P
O
R
Q
T
S
W
Capture interrupt
(INTTM010)
Capture input
(TI010)
Compare match interrupt
(INTTM000)
L
L
This is an application example where the pulse width of the signal input to the TI000 pin is measured.
By setting CRC00, the count value can be captured to CR000 in the phase reverse to the falling edge of the
TI000 pin (i.e., rising edge) and to CR010 at the falling edge of the TI000 pin.
The high- and low-level widths of the input pulse can be calculated by the following expressions.
• High-level width = [CR010 value] – [CR000 value] × [Count clock cycle]
• Low-level width = [CR000 value] × [Count clock cycle]
If the reverse phase of the TI000 pin is selected as a trigger to capture the count value to CR000, the INTTM000
signal is not generated. Read the values of CR000 and CR010 to measure the pulse width immediately after the
INTTM010 signal is generated.
However, if the valid edge specified by bits 6 and 5 (ES101 and ES100) of prescaler mode register 00 (PRM00) is
input to the TI010 pin, the count value is not captured but the INTTM000 signal is generated. To measure the
pulse width of the TI000 pin, mask the INTTM000 signal when it is not used.
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Figure 6-30. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (1/2)
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001
0
0
0
0
1
0
OVF00
0/1
0
0: Inverts TO00 output on match
between CR000 and CR010.
1: Inverts TO00 output on match
between CR000 and CR010
and valid edge of TI000 pin.
Clears and starts at valid
edge input of TI000 pin.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
0
0
0
0
0
0/1
0/1
0/1
0: CR000 used as compare register
1: CR000 used as capture register
0: TI010 pin is used as capture
trigger of CR00n.
1: Reverse phase of TI000 pin is
used as capture trigger of CR000.
0: CR010 used as compare register
1: CR010 used as capture register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004
0
0
0
0/1
LVS00
LVR00
TOC001
TOE00
0/1
0/1
0/1
0/1
0: Disables TO00 outputNote
1: Enables TO00 output
Specifies initial value of
TO00 output F/F
00: Does not invert TO00 output on match
between TM00 and CR000/CR010.
01: Inverts TO00 output on match between
TM00 and CR000.
10: Inverts TO00 output on match between
TM00 and CR010.
11: Inverts TO00 output on match between
TM00 and CR000/CR010.
Note The timer output (TO00) cannot be used when detecting the valid edge of the TI010 pin is used.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-30. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (2/2)
(d) Prescaler mode register 00 (PRM00)
ES101
ES100
ES001
ES000
3
2
0/1
0/1
0/1
0/1
0
0
PRM001 PRM000
0/1
0/1
Count clock selection
(setting TI00n valid edge is prohibited)
00:
01:
10:
11:
Falling edge detection
Rising edge detection
Setting prohibited
Both edges detection
(setting prohibited when CRC001 = 1)
00:
01:
10:
11:
Falling edge detection
Rising edge detection
Setting prohibited
Both edges detection
(e) 16-bit timer counter 00 (TM00)
By reading TM00, the count value can be read.
(f) 16-bit capture/compare register 000 (CR000)
When this register is used as a compare register and when its value matches the count value of TM00, an
interrupt signal (INTTM000) is generated. The count value of TM00 is not cleared.
To use this register as a capture register, select either the TI000 or TI010 pinNote input as a capture trigger.
When the valid edge of the capture trigger is detected, the count value of TM00 is stored in CR000.
Note The timer output (TO00) cannot be used when detection of the valid edge of the TI010 pin is used.
(g) 16-bit capture/compare register 010 (CR010)
When this register is used as a compare register and when its value matches the count value of TM00, an
interrupt signal (INTTM010) is generated. The count value of TM00 is not cleared.
When this register is used as a capture register, the TI000 pin input is used as a capture trigger. When the
valid edge of the capture trigger is detected, the count value of TM00 is stored in CR010.
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Figure 6-31. Example of Software Processing in Clear & Start Mode Entered by TI000 Pin Valid Edge Input
M
M
TM00 register
M
N
N
M
N
N
0000H
Operable bits
(TMC003, TMC002)
10
00
00
Count clear input
(TI000 pin input)
Compare register
(CR000)
M
Compare match interrupt
(INTTM000)
Compare register
(CR010)
N
Compare match interrupt
(INTTM010)
TO00 pin output
Count operation start flow
Count operation stop flow
TMC003, TMC002 bits = 00
START
Register initial setting
PRM00 register,
CRC00 register,
TOC00 registerNote,
CR000, CR010 registers,
TMC00.TMC001 bit,
port setting
Initial setting of these
registers is performed
before setting the
TMC003 and TMC002
bits to 10.
TMC003, TMC002 bits = 10
Starts count operation
The counter is initialized
and counting is stopped
by clearing the TMC003
and TMC002 bits to 00.
STOP
TM00 register clear & start flow
Edge input to TI000 pin
When the valid edge is input to the TI000 pin,
the value of the TM00 register is cleared.
Note Care must be exercised when setting TOC00. For details, see 6.3 (3) 16-bit timer output control register
00 (TOC00).
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4.5 Free-running timer operation
When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 01 (freerunning timer mode), 16-bit timer/event counter 00 continues counting up in synchronization with the count clock.
When it has counted up to FFFFH, the overflow flag (OVF00) is set to 1 at the next clock, and TM00 is cleared (to
0000H) and continues counting. Clear OVF00 to 0 by executing the CLR instruction via software.
The following three types of free-running timer operations are available.
• Both CR000 and CR010 are used as compare registers.
• One of CR000 or CR010 is used as a compare register and the other is used as a capture register.
• Both CR000 and CR010 are used as capture registers.
Remarks 1. For the setting of the I/O pins, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 signal interrupt, see CHAPTER 18 INTERRUPT FUNCTIONS.
(1) Free-running timer mode operation
(CR000: compare register, CR010: compare register)
Figure 6-32. Block Diagram of Free-Running Timer Mode
(CR000: Compare Register, CR010: Compare Register)
Count clock
Timer counter
(TM00)
Match signal
Interrupt signal
(INTTM000)
Operable bits
TMC003, TMC002
Compare register
(CR000)
Match signal
Compare register
(CR010)
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Output
controller
TO00 pin
Interrupt signal
(INTTM010)
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
Figure 6-33. Timing Example of Free-Running Timer Mode
(CR000: Compare Register, CR010: Compare Register)
• TOC00 = 13H, PRM00 = 00H, CRC00 = 00H, TMC00 = 04H
FFFFH
N
TM00 register
0000H
Operable bits
(TMC003, TMC002)
00
Compare register
(CR000)
M
N
M
N
M
N
M
01
00
M
Compare match interrupt
(INTTM000)
Compare register
(CR010)
N
Compare match interrupt
(INTTM010)
TO00 pin output
OVF00 bit
0 write clear
0 write clear
0 write clear
0 write clear
This is an application example where two compare registers are used in the free-running timer mode.
The output level of the TO00 pin is reversed each time the count value of TM00 matches the set value of CR000
or CR010. When the count value matches the register value, the INTTM000 or INTTM010 signal is generated.
(2) Free-running timer mode operation
(CR000: compare register, CR010: capture register)
Figure 6-34. Block Diagram of Free-Running Timer Mode
(CR000: Compare Register, CR010: Capture Register)
Timer counter
(TM00)
Count clock
Match signal
Interrupt signal
(INTTM000)
Operable bits
TMC003, TMC002
Compare register
(CR000)
TI000 pin
Edge
detection
Capture signal
Capture register
(CR010)
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Output
controller
TO00 pin
Interrupt signal
(INTTM010)
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-35. Timing Example of Free-Running Timer Mode
(CR000: Compare Register, CR010: Capture Register)
• TOC00 = 13H, PRM00 = 10H, CRC00 = 04H, TMC00 = 04H
FFFFH
M
N
TM00 register
P
S
Q
0000H
Operable bits
(TMC003, TMC002)
00
01
Capture trigger input
(TI000)
Compare register
(CR000)
0001H
Compare match interrupt
(INTTM000)
Compare register
(CR010)
0000H
M
N
S
P
Q
Capture interrupt
(INTTM010)
TO00 pin output
Overflow flag
(OVF00)
0 write clear
0 write clear
0 write clear
0 write clear
This is an application example where a compare register and a capture register are used at the same time in the
free-running timer mode.
In this example, the INTTM000 signal is generated and the output level of the TO00 pin is reversed each time the
count value of TM00 matches the set value of CR000 (compare register). In addition, the INTTM010 signal is
generated and the count value of TM00 is captured to CR010 each time the valid edge of the TI000 pin is
detected.
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(3) Free-running timer mode operation
(CR000: capture register, CR010: capture register)
Figure 6-36. Block Diagram of Free-Running Timer Mode
(CR000: Capture Register, CR010: Capture Register)
Operable bits
TMC003, TMC002
Timer counter
(TM00)
Count clock
TI000 pin
TI010 pin
Remark
Edge
detection
Edge
detection
Selector
Capture signal
Capture
signal
Capture register
(CR010)
Capture register
(CR000)
Interrupt signal
(INTTM010)
Interrupt signal
(INTTM000)
If both CR000 and CR010 are used as capture registers in the free-running timer mode, the output
level of the TO00 pin is not inverted.
However, it can be inverted each time the valid edge of the TI000 pin is detected if bit 1 (TMC001) of
16-bit timer mode control register 00 (TMC00) is set to 1.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-37. Timing Example of Free-Running Timer Mode
(CR000: Capture Register, CR010: Capture Register) (1/2)
(a) TOC00 = 13H, PRM00 = 50H, CRC00 = 05H, TMC00 = 04H
FFFFH
M
N
TM00 register
A
0000H
Operable bits
(TMC003, TMC002)
00
P
S
C
B
Q
D
E
01
Capture trigger input
(TI000)
Capture register
(CR010)
0000H
M
N
S
P
Q
Capture interrupt
(INTTM010)
Capture trigger input
(TI010)
Capture register
(CR000)
0000H
A
B
C
D
E
Capture interrupt
(INTTM000)
Overflow flag
(OVF00)
0 write clear
0 write clear
0 write clear
0 write clear
This is an application example where the count values that have been captured at the valid edges of separate
capture trigger signals are stored in separate capture registers in the free-running timer mode.
The count value is captured to CR010 when the valid edge of the TI000 pin input is detected and to CR000 when
the valid edge of the TI010 pin input is detected.
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Figure 6-37. Timing Example of Free-Running Timer Mode
(CR000: Capture Register, CR010: Capture Register) (2/2)
(b) TOC00 = 13H, PRM00 = C0H, CRC00 = 05H, TMC00 = 04H
FFFFH
O
L
00
T
Q
M
0000H
Operable bits
(TMC003, TMC002)
R
N
TM00 register
S
P
01
Capture trigger input
(TI010)
Capture register
(CR000)
0000H
L
M
N
O
P
Q
R
S
T
Capture interrupt
(INTTM000)
Capture trigger input
(TI000)
L
Capture register
(CR010)
Capture interrupt
(INTTM010)
0000H
L
This is an application example where both the edges of the TI010 pin are detected and the count value is
captured to CR000 in the free-running timer mode.
When both CR000 and CR010 are used as capture registers and when the valid edge of only the TI010 pin is to
be detected, the count value cannot be captured to CR010.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-38. Example of Register Settings in Free-Running Timer Mode (1/2)
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001
0
0
0
0
0
1
OVF00
0/1
0
0: Inverts TO00 pin output on match
between CR000 and CR010.
1: Inverts TO00 pin output on match
between CR000 and CR010 and
valid edge of TI000 pin.
Free-running timer mode
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
0
0
0
0
0
0/1
0/1
0/1
0: CR000 used as compare register
1: CR000 used as capture register
0: TI010 pin is used as capture
trigger of CR002.
1: Reverse phase of TI000 pin is
used as capture trigger of CR000.
0: CR010 used as compare register
1: CR010 used as capture register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004
0
0
0
0/1
LVS00
LVR00
TOC001
TOE00
0/1
0/1
0/1
0/1
0: Disables TO00 output
1: Enables TO00 output
Specifies initial value of
TO00 output F/F
00: Does not invert TO00 output on match
between TM00 and CR000/CR010.
01: Inverts TO00 output on match between
TM00 and CR000.
10: Inverts TO00 output on match between
TM00 and CR010.
11: Inverts TO00 output on match between
TM00 and CR000/CR010.
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Figure 6-38. Example of Register Settings in Free-Running Timer Mode (2/2)
(d) Prescaler mode register 00 (PRM00)
ES101
ES100
ES001
ES000
3
2
0/1
0/1
0/1
0/1
0
0
PRM001 PRM000
0/1
0/1
Count clock selection
(setting TI000 valid edge is prohibited)
00:
01:
10:
11:
Falling edge detection
Rising edge detection
Setting prohibited
Both edges detection
(setting prohibited when CRC001 = 1)
00:
01:
10:
11:
Falling edge detection
Rising edge detection
Setting prohibited
Both edges detection
(e) 16-bit timer counter 00 (TM00)
By reading TM00, the count value can be read.
(f) 16-bit capture/compare register 000 (CR000)
When this register is used as a compare register and when its value matches the count value of TM00, an
interrupt signal (INTTM000) is generated. The count value of TM00 is not cleared.
To use this register as a capture register, select either the TI000 or TI010 pin input as a capture trigger.
When the valid edge of the capture trigger is detected, the count value of TM00 is stored in CR000.
(g) 16-bit capture/compare register 010 (CR010)
When this register is used as a compare register and when its value matches the count value of TM00, an
interrupt signal (INTTM010) is generated. The count value of TM00 is not cleared.
When this register is used as a capture register, the TI000 pin input is used as a capture trigger. When the
valid edge of the capture trigger is detected, the count value of TM00 is stored in CR010.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-39. Example of Software Processing in Free-Running Timer Mode
FFFFH
M
M
TM0n register
0000H
Operable bits
(TMC003, TMC002)
N
N
00
M
N
01
Compare register
(CR003)
N
00
M
Compare match interrupt
(INTTM000)
Compare register
(CR010)
N
Compare match interrupt
(INTTM010)
Timer output control bits
(TOE0, TOC004, TOC001)
TO00 pin output
Count operation start flow
START
Register initial setting
PRM00 register,
CRC00 register,
TOC00 registerNote,
CR000/CR010 register,
TMC00.TMC001 bit,
port setting
TMC003, TMC002 bits = 0, 1
Initial setting of these registers is performed
before setting the TMC003 and TMC002
bits to 01.
Starts count operation
Count operation stop flow
TMC003, TMC002 bits = 0, 0
The counter is initialized and counting is stopped
by clearing the TMC003 and TMC002 bits to 00.
STOP
Note Care must be exercised when setting TOC00. For details, see 6.3 (3) 16-bit timer output control
register 00 (TOC00).
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6.4.6 PPG output operation
A square wave having a pulse width set in advance by CR010 is output from the TO00 pin as a PPG
(Programmable Pulse Generator) signal during a cycle set by CR000 when bits 3 and 2 (TMC003 and TMC002) of 16bit timer mode control register 00 (TMC00) are set to 11 (clear & start upon a match between TM00 and CR000).
The pulse cycle and duty factor of the pulse generated as the PPG output are as follows.
• Pulse cycle = (Set value of CR000 + 1) × Count clock cycle
• Duty = (Set value of CR010 + 1) / (Set value of CR000 + 1)
Caution To change the duty factor (value of CR010) during operation, see 6.5.1 Rewriting CR010 during
TM00 operation.
Remarks 1. For the setting of I/O pins, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 signal interrupt, see CHAPTER 18 INTERRUPT FUNCTIONS.
Figure 6-40. Block Diagram of PPG Output Operation
Clear
Count clock
Timer counter
(TM00)
Match signal
Interrupt signal
(INTTM000)
Operable bits
TMC003, TMC002
Compare register
(CR000)
Match signal
Output
controller
TO00 pin
Interrupt signal
(INTTM010)
Compare register
(CR010)
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-41. Example of Register Settings for PPG Output Operation
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001
0
0
0
0
1
1
OVF00
0
0
Clears and starts on match
between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
0
0
0
0
0
0
0
0
CR000 used as
compare register
CR010 used as
compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004
0
0
0
1
LVS00
LVR00
TOC001
TOE00
0/1
0/1
1
1
Enables TO00 output
Specifies initial value of
TO00 output F/F
11: Inverts TO00 output on
match between TM00
and CR000/CR010.
00: Disables one-shot pulse
output
(d) Prescaler mode register 00 (PRM00)
ES101
ES100
ES001
ES000
3
2
0
0
0
0
0
0
PRM001 PRM000
0/1
0/1
Selects count clock
(e) 16-bit timer counter 00 (TM00)
By reading TM00, the count value can be read.
(f) 16-bit capture/compare register 000 (CR000)
An interrupt signal (INTTM000) is generated when the value of this register matches the count value of TM00.
The count value of TM00 is not cleared.
(g) 16-bit capture/compare register 010 (CR010)
An interrupt signal (INTTM010) is generated when the value of this register matches the count value of TM00.
The count value of TM00 is not cleared.
Caution Set values to CR000 and CR010 such that the condition 0000H < CR010 < CR000 ≤ FFFFH is
satisfied.
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Figure 6-42. Example of Software Processing for PPG Output Operation
M
TM00 register
M
N
N
M
N
0000H
Operable bits
(TMC003, TMC002)
00
00
11
Compare register
(CR000)
N
Compare match interrupt
(INTTM000)
Compare register
(CR010)
M
Compare match interrupt
(INTTM010)
Timer output control bits
(TOE00, TOC004, TOC001)
TO00 pin output
N+1
M+1
N+1
M+1
N+1
M+1
Count operation stop flow
Count operation start flow
TMC003, TMC002 bits = 00
START
Register initial setting
PRM00 register,
CRC00 register,
TOC00 registerNote,
CR000, CR010 registers,
port setting
Initial setting of these
registers is performed
before setting the
TMC003 and TMC002
bits.
TMC003, TMC002 bits = 11
Starts count operation
The counter is initialized
and counting is stopped
by clearing the TMC003
and TMC002 bits to 00.
STOP
Note Care must be exercised when setting TOC00. For details, see 6.3 (3) 16-bit timer output control
register 00 (TOC00).
Remark
PPG pulse cycle = (M + 1) × Count clock cycle
PPG duty = (N + 1)/(M + 1)
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6.4.7 One-shot pulse output operation
A one-shot pulse can be output by setting bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control
register 00 (TMC00) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI000 pin valid edge)
and setting bit 5 (OSPE00) of 16-bit timer output control register 00 (TOC00) to 1.
When bit 6 (OSPT00) of TOC00 is set to 1 or when the valid edge is input to the TI000 pin during timer operation,
clearing & starting of TM00 is triggered, and a pulse of the difference between the values of CR000 and CR010 is
output only once from the TO00 pin.
Cautions 1. Do not input the trigger again (setting OSPT00 to 1 or detecting the valid edge of the TI000
pin) while the one-shot pulse is output. To output the one-shot pulse again, generate the
trigger after the current one-shot pulse output has completed.
2. To use only the setting of OSPT00 to 1 as the trigger of one-shot pulse output, do not change
the level of the TI000 pin or its alternate function port pin. Otherwise, the pulse will be
unexpectedly output.
Remarks 1. For the setting of the I/O pins, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 signal interrupt, see CHAPTER 18 INTERRUPT FUNCTIONS.
Figure 6-43. Block Diagram of One-Shot Pulse Output Operation
TI000 edge detection
OSPT00 bit
Clear
OSPE00 bit
Count clock
Timer counter
(TM00)
Match signal
Interrupt signal
(INTTM000)
Operable bits
TMC003, TMC002
Compare register
(CR000)
Match signal
Compare register
(CR010)
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Output
controller
TO00 pin
Interrupt signal
(INTTM010)
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
Figure 6-44. Example of Register Settings for One-Shot Pulse Output Operation (1/2)
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001
0
0
0
0
0/1
0/1
OVF00
0
0
01: Free running timer mode
10: Clear and start mode by
valid edge of TI000 pin.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
0
0
0
0
0
0
0
0
CR000 used as
compare register
CR010 used as
compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004
0
0/1
1
1
LVS00
LVR00
TOC001
TOE00
0/1
0/1
1
1
Enables TO00 pin output
Specifies initial value of
TO00 pin output
Inverts TO00 output on
match between TM00
and CR000/CR010.
Enables one-shot pulse
output
Software trigger is generated
by writing 1 to this bit
(operation is not affected
even if 0 is written to it).
(d) Prescaler mode register 00 (PRM00)
ES101
ES100
ES001
ES000
3
2
0
0
0
0
0
0
PRM001 PRM000
0/1
0/1
Selects count clock
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Figure 6-44. Example of Register Settings for One-Shot Pulse Output Operation (2/2)
(e) 16-bit timer counter 00 (TM00)
By reading TM00, the count value can be read.
(f) 16-bit capture/compare register 000 (CR000)
This register is used as a compare register when a one-shot pulse is output. When the value of TM00
matches that of CR000, an interrupt signal (INTTM000) is generated and the output level of the TO00 pin is
inverted.
(g) 16-bit capture/compare register 010 (CR010)
This register is used as a compare register when a one-shot pulse is output. When the value of TM00
matches that of CR010, an interrupt signal (INTTM010) is generated and the output level of the TO00 pin is
inverted.
Caution Do not set identical values or 0000H for CR000 and CR010.
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Figure 6-45. Example of Software Processing for One-Shot Pulse Output Operation (1/2)
FFFFH
N
N
M
TM00 register
N
M
M
0000H
Operable bits
(TMC003, TMC002)
00
01 or 10
00
One-shot pulse enable bit
(OSPE00)
One-shot pulse trigger bit
(OSPT00)
One-shot pulse trigger input
(TI000 pin)
Overflow plug
(OVF00)
Compare register
(CR000)
N
Compare match interrupt
(INTTM000)
Compare register
(CR010)
M
Compare match interrupt
(INTTM010)
TO00 pin output
M+1
TO00 output control bits
(TOE00, TOC004, TOC001)
N−M
M+1 N−M
TO00 output level is not
inverted because no oneshot trigger is input.
• Time from when the one-shot pulse trigger is input until the one-shot pulse is output
= (M + 1) × Count clock cycle
• One-shot pulse output active level width
= (N − M) × Count clock cycle
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Figure 6-45. Example of Software Processing for One-Shot Pulse Output Operation (2/2)
Count operation start flow
START
Register initial setting
PRM00 register,
CRC00 register,
TOC00 registerNote,
CR000, CR010 registers,
port setting
TMC003, TMC002 bits =
01 or 10
Initial setting of these registers is performed
before setting the TMC003 and TMC002 bits.
Starts count operation
One-shot trigger input flow
TOC00.OSPT00 bit = 1
or edge input to TI000 pin
Write the same value to the bits other than the
OSTP00 bit.
Count operation stop flow
TMC003, TMC002 bits = 00
The counter is initialized and counting is stopped
by clearing the TMC003 and TMC002 bits to 00.
STOP
Note Care must be exercised when setting TOC00. For details, see 6.3 (3) 16-bit timer output control
register 00 (TOC00).
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6.4.8 Pulse width measurement operation
TM00 can be used to measure the pulse width of the signal input to the TI000 and TI010 pins.
Measurement can be accomplished by operating the 16-bit timer/event counter 00 in the free-running timer mode
or by restarting the timer in synchronization with the signal input to the TI000 pin.
When an interrupt is generated, read the value of the valid capture register and measure the pulse width. Check
bit 0 (OVF00) of 16-bit timer mode control register 00 (TMC00). If it is set (to 1), clear it to 0 by software.
Figure 6-46. Block Diagram of Pulse Width Measurement (Free-Running Timer Mode)
Operable bits
TMC003, TMC002
Timer counter
(TM00)
Count clock
TI000 pin
Edge
detection
TI010 pin
Edge
detection
Selector
Capture signal
Capture
signal
Capture register
(CR010)
Capture register
(CR000)
Interrupt signal
(INTTM010)
Interrupt signal
(INTTM000)
Figure 6-47. Block Diagram of Pulse Width Measurement
(Clear & Start Mode Entered by TI000 Pin Valid Edge Input)
Operable bits
TMC003, TMC002
Clear
Timer counter
(TM00)
Count clock
TI000 pin
Edge
detection
TI010 pin
Edge
detection
Selector
Capture signal
Capture
signal
Capture register
(CR010)
Capture register
(CR000)
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Interrupt signal
(INTTM010)
Interrupt signal
(INTTM000)
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A pulse width can be measured in the following three ways.
• Measuring the pulse width by using two input signals of the TI000 and TI010 pins (free-running timer mode)
• Measuring the pulse width by using one input signal of the TI000 pin (free-running timer mode)
• Measuring the pulse width by using one input signal of the TI000 pin (clear & start mode entered by the TI000 pin
valid edge input)
Remarks 1. For the setting of the I/O pins, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 signal interrupt, see CHAPTER 18 INTERRUPT FUNCTIONS.
(1) Measuring the pulse width by using two input signals of the TI000 and TI010 pins (free-running timer
mode)
Set the free-running timer mode (TMC003 and TMC002 = 01). When the valid edge of the TI000 pin is detected,
the count value of TM00 is captured to CR010. When the valid edge of the TI010 pin is detected, the count value
of TM00 is captured to CR000. Specify detection of both the edges of the TI000 and TI010 pins.
By this measurement method, the previous count value is subtracted from the count value captured by the edge
of each input signal. Therefore, save the previously captured value to a separate register in advance.
If an overflow occurs, the value becomes negative if the previously captured value is simply subtracted from the
current captured value and, therefore, a borrow occurs (bit 0 (CY) of the program status word (PSW) is set to 1).
If this happens, ignore CY and take the calculated value as the pulse width. In addition, clear bit 0 (OVF00) of
16-bit timer mode control register 00 (TMC00) to 0.
Figure 6-48. Timing Example of Pulse Width Measurement (1)
• TMC00 = 04H, PRM00 = F0H, CRC00 = 05H
FFFFH
M
TM00 register
N
A
B
0000H
Operable bits
(TMC003, TMC002)
00
P
S
C
Q
D
E
01
Capture trigger input
(TI000)
Capture register
(CR010)
0000H
M
N
S
P
Q
Capture interrupt
(INTTM010)
Capture trigger input
(TI010)
Capture register
(CR000)
0000H
A
B
C
D
E
Capture interrupt
(INTTM000)
Overflow flag
(OVF00)
0 write clear
178
0 write clear
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0 write clear
0 write clear
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
(2) Measuring the pulse width by using one input signal of the TI000 pin (free-running mode)
Set the free-running timer mode (TMC003 and TMC002 = 01). The count value of TM00 is captured to CR000 in
the phase reverse to the valid edge detected on the TI000 pin. When the valid edge of the TI000 pin is detected,
the count value of TM00 is captured to CR010.
By this measurement method, values are stored in separate capture registers when a width from one edge to
another is measured. Therefore, the capture values do not have to be saved. By subtracting the value of one
capture register from that of another, a high-level width, low-level width, and cycle are calculated.
If an overflow occurs, the value becomes negative if one captured value is simply subtracted from another and,
therefore, a borrow occurs (bit 0 (CY) of the program status word (PSW) is set to 1). If this happens, ignore CY
and take the calculated value as the pulse width. In addition, clear bit 0 (OVF00) of 16-bit timer mode control
register 00 (TMC00) to 0.
Figure 6-49. Timing Example of Pulse Width Measurement (2)
• TMC00 = 04H, PRM00 = 10H, CRC00 = 07H
FFFFH
M
TM00 register
N
A
B
0000H
Operable bits
(TMC003, TMC002)
00
P
S
C
Q
D
E
01
Capture trigger input
(TI000)
Capture register
(CR000)
0000H
Capture register
(CR010)
0000H
A
B
M
C
N
E
D
S
P
Q
Capture interrupt
(INTTM010)
Overflow flag
(OVF00)
0 write clear
Capture trigger input
(TI010)
L
Compare match interrupt
(INTTM000)
L
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0 write clear
0 write clear
0 write clear
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(3) Measuring the pulse width by using one input signal of the TI000 pin (clear & start mode entered by the
TI000 pin valid edge input)
Set the clear & start mode entered by the TI000 pin valid edge (TMC003 and TMC002 = 10). The count value of
TM00 is captured to CR000 in the phase reverse to the valid edge of the TI000 pin, and the count value of TM00
is captured to CR010 and TM00 is cleared (0000H) when the valid edge of the TI000 pin is detected. Therefore,
a cycle is stored in CR010 if TM00 does not overflow.
If an overflow occurs, take the value that results from adding 10000H to the value stored in CR010 as a cycle.
Clear bit 0 (OVF00) of 16-bit timer mode control register 00 (TMC00) to 0.
Figure 6-50. Timing Example of Pulse Width Measurement (3)
• TMC00 = 08H, PRM00 = 10H, CRC00 = 07H
FFFFH
TM00 register
N
C
D
S
A
0000H
Operable bits
00
(TMC003, TMC002)
Q
P
B
M
10
00
Capture & count clear input
(TI000)
Capture register
(CR000)
0000H
Capture register
(CR010)
0000H
A
M
B
N
C
S
D
P
Q
Capture interrupt
(INTTM010)
Overflow flag
(OVF00)
0 write clear
Capture trigger input
(TI010) L
Capture interrupt
(INTTM000) L
(10000H × Number of times OVF00 bit is set to 1 + Captured value of CR010) ×
Pulse cycle =
High-level pulse width = (10000H × Number of times OVF00 bit is set to 1 + Captured value of CR000) ×
Low-level pulse width = (Pulse cycle − High-level pulse width)
Count clock cycle
Count clock cycle
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Figure 6-51. Example of Register Settings for Pulse Width Measurement (1/2)
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001
0
0
0
0
0/1
0/1
OVF00
0
0
01: Free running timer mode
10: Clear and start mode entered
by valid edge of TI000 pin.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
0
0
0
0
0
1
0/1
1
1: CR000 used as capture register
0: TI010 pin is used as capture
trigger of CR000.
1: Reverse phase of TI000 pin is
used as capture trigger of CR000.
1: CR010 used as capture register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004
0
0
0
LVS00
LVR00
TOC001
TOE00
0
0
0
0
0
(d) Prescaler mode register 00 (PRM00)
ES101
ES100
ES001
ES000
3
2
0/1
0/1
0/1
0/1
0
0
PRM001 PRM000
0/1
0/1
Selects count clock
(setting valid edge of TI000 is prohibited)
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
(setting when CRC001 = 1 is prohibited)
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
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Figure 6-51. Example of Register Settings for Pulse Width Measurement (2/2)
(e) 16-bit timer counter 00 (TM00)
By reading TM00, the count value can be read.
(f) 16-bit capture/compare register 000 (CR000)
This register is used as a capture register. Either the TI000 or TI010 pin is selected as a capture trigger.
When a specified edge of the capture trigger is detected, the count value of TM00 is stored in CR000.
(g) 16-bit capture/compare register 010 (CR010)
This register is used as a capture register. The signal input to the TI000 pin is used as a capture trigger.
When the capture trigger is detected, the count value of TM00 is stored in CR010.
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Figure 6-52. Example of Software Processing for Pulse Width Measurement (1/2)
(a) Example of free-running timer mode
FFFFH
D10
TM00 register
D11
D00
D13
D12
D01
D02
D03
D04
0000H
Operable bits
(TMC003, TMC002)
00
01
00
Capture trigger input
(TI000)
Capture register
(CR010)
D10
0000H
D11
D12
D13
Capture interrupt
(INTTM010)
Capture trigger input
(TI010)
Capture register
(CR000)
0000H
D00
D01
D02
D03
D04
Capture interrupt
(INTTM000)
(b) Example of clear & start mode entered by TI000 pin valid edge
FFFFH
TM00 register
0000H
Operable bits
(TMC003, TMC002)
D3
D2
D5
D0
D7
D4
D1
00
D8
D6
10
00
Capture & count clear input
(TI000)
Capture register
0000H
(CR000)
Capture interrupt
(INTTM000)
D3
D1
D5
D7
L
Capture register
(CR010) 0000H
D0
D2
D4
D6
D8
Capture interrupt
(INTTM010)
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Figure 6-52. Example of Software Processing for Pulse Width Measurement (2/2)
Count operation start flow
START
Register initial setting
PRM00 register,
CRC00 register,
port setting
TMC003, TMC002 bits =
01 or 10
Initial setting of these registers is performed
before setting the TMC003 and TMC002 bits.
Starts count operation
Capture trigger input flow
Edge detection of TI000, TI010 pins
Stores count value to
CR000, CR010 registers
Generates capture interruptNote
Calculated pulse width
from capture value
Count operation stop flow
TMC003, TMC002 bits = 00
The counter is initialized and counting is stopped
by clearing the TMC003 and TMC002 bits to 00.
STOP
Note The capture interrupt signal (INTTM000) is not generated when the reverse-phase edge of the TI000 pin
input is selected to the valid edge of CR000.
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6.5 Special Use of TM00
6.5.1 Rewriting CR010 during TM00 operation
In principle, rewriting CR000 and CR010 of the 78K0/LE2 when they are used as compare registers is prohibited
while TM00 is operating (TMC003 and TMC002 = other than 00).
However, the value of CR010 can be changed, even while TM00 is operating, using the following procedure if
CR010 is used for PPG output and the duty factor is changed (change the value of CR010 immediately after its value
matches the value of TM00. If the value of CR010 is changed immediately before its value matches TM00, an
unexpected operation may be performed).
Procedure for changing value of CR010
Disable interrupt INTTM010 (TMMK010 = 1).
Disable reversal of the timer output when the value of TM00 matches that of CR010 (TOC004 = 0).
Change the value of CR010.
Wait for one cycle of the count clock of TM00.
Enable reversal of the timer output when the value of TM00 matches that of CR010 (TOC004 = 1).
Clear the interrupt flag of INTTM010 (TMIF010 = 0) to 0.
Enable interrupt INTTM010 (TMMK010 = 0).
Remark
For TMIF010 and TMMK010, see CHAPTER 18 INTERRUPT FUNCTIONS.
6.5.2 Setting LVS00 and LVR00
(1) Usage of LVS00 and LVR00
LVS00 and LVR00 are used to set the default value of the TO00 pin output and to invert the timer output without
enabling the timer operation (TMC003 and TMC002 = 00). Clear LVS00 and LVR00 to 00 (default value: lowlevel output) when software control is unnecessary.
LVS00
LVR00
Timer Output Status
0
0
Not changed (low-level output)
0
1
Cleared (low-level output)
1
0
Set (high-level output)
1
1
Setting prohibited
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(2) Setting LVS00 and LVR00
Set LVS00 and LVR00 using the following procedure.
Figure 6-53. Example of Flow for Setting LVS00 and LVR00 Bits
Setting TOC00.OSPE00, TOC004, TOC001 bits
Setting of timer output operation
Setting TOC00.TOE00 bit
Setting TOC00.LVS00, LVR00 bits
Setting TMC00.TMC003, TMC002 bits
Setting of timer output F/F
Enabling timer operation
Caution Be sure to set LVS00 and LVR00 following steps , , and above.
Step can be performed after and before .
Figure 6-54. Timing Example of LVR00 and LVS00
TOC00.LVS00 bit
TOC00.LVR00 bit
Operable bits
(TMC003, TMC002)
00
01, 10, or 11
TO00 pin output
INTTM000 signal
The TO00 pin output goes high when LVS00 and LVR00 = 10.
The TO00 pin output goes low when LVS00 and LVR00 = 01 (the pin output remains unchanged from the
high level even if LVS00 and LVR00 are cleared to 00).
The timer starts operating when TMC003 and TMC002 are set to 01, 10, or 11. Because LVS00 and
LVR00 were set to 10 before the operation was started, the TO00 pin output starts from the high level.
After the timer starts operating, setting LVS00 and LVR00 is prohibited until TMC003 and TMC002 = 00
(disabling the timer operation).
The output level of the TO00 pin is inverted each time an interrupt signal (INTTM000) is generated.
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6.6 Cautions for 16-Bit Timer/Event Counter 00
(1) Restrictions for each channel of 16-bit timer/event counter 00
Table 6-5 shows the restrictions for each channel.
Table 6-5. Restrictions for Each Channel of 16-Bit Timer/Event Counter 00
Operation
Restriction
−
As interval timer
As square wave output
As external event counter
TOC00 = 00H
As clear & start mode entered by
Using timer output (TO00) is prohibited when detection of the valid edge of the TI010 pin is
TI000 pin valid edge input
used.
TOC00 = 00H
−
As free-running timer
As PPG output
Setting identical values or 0000H to CR000 and CP010 is prohibited.
−
As one-shot pulse output
As pulse width measurement
TOC00 = 00H
(2) Timer start errors
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because counting TM00 is started asynchronously to the count pulse.
Figure 6-55. Start Timing of TM00 Count
Count pulse
TM00 count value
0000H
0001H
0002H
0003H
0004H
Timer start
(3) Setting of CR000 and CR010 (clear & start mode entered upon a match between TM00 and CR000)
Set a value other than 0000H to CR000 and CR010 (TM00 cannot count one pulse when it is used as an external
event counter).
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(4) Timing of holding data by capture register
(a) When the valid edge is input to the TI000/TI010 pin and the reverse phase of the TI000 pin is detected while
CR000/CR010 is read, CR010 performs a capture operation but the read value of CR000/CR010 is not
guaranteed. At this time, an interrupt signal (INTTM000/INTTM010) is generated when the valid edge of the
TI000/TI010 pin is detected (the interrupt signal is not generated when the reverse-phase edge of the TI000
pin is detected).
When the count value is captured because the valid edge of the TI000/TI010 pin was detected, read the
value of CR000/CR010 after INTTM000/INTTM010 is generated.
Figure 6-56. Timing of Holding Data by Capture Register
Count pulse
TM00 count value
N
N+1
N+2
M
M+1
M+2
Edge input
INTTM010
Capture read signal
Value captured to CR010
X
N+1
Capture operation
Capture operation is performed
but read value is not guaranteed.
(b) The values of CR000 and CR010 are not guaranteed after 16-bit timer/event counter 00 stops.
(5) Setting valid edge
Set the valid edge of the TI000 pin while the timer operation is stopped (TMC003 and TMC002 = 00). Set the
valid edge by using ES000 and ES001.
(6) Re-triggering one-shot pulse
Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode.
Be sure to input the next trigger after the current active level is output.
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(7) Operation of OVF00 flag
(a) Setting OVF00 flag (1)
The OVF00 flag is set to 1 in the following case, as well as when TM00 overflows.
Select the clear & start mode entered upon a match between TM00 and CR000.
↓
Set CR000 to FFFFH.
↓
When TM00 matches CR000 and TM00 is cleared from FFFFH to 0000H
Figure 6-57. Operation Timing of OVF00 Flag
Count pulse
CR000
FFFFH
TM00
FFFEH
FFFFH
0000H
0001H
OVF00
INTTM000
(b) Clearing OVF00 flag
Even if the OVF00 flag is cleared to 0 after TM00 overflows and before the next count clock is counted
(before the value of TM00 becomes 0001H), it is set to 1 again and clearing is invalid.
(8) One-shot pulse output
One-shot pulse output operates correctly in the free-running timer mode or the clear & start mode entered by the
TI000 pin valid edge. The one-shot pulse cannot be output in the clear & start mode entered upon a match
between TM00 and CR000.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(9) Capture operation
(a) When valid edge of TI000 is specified as count clock
When the valid edge of TI000 is specified as the count clock, the capture register for which TI000 is specified
as a trigger does not operate correctly.
(b) Pulse width to accurately capture value by signals input to TI010 and TI000 pins
To accurately capture the count value, the pulse input to the TI000 and TI010 pins as a capture trigger must
be wider than two count clocks selected by PRM00 (see Figure 6-7).
(c) Generation of interrupt signal
The capture operation is performed at the falling edge of the count clock but the interrupt signals (INTTM000
and INTTM010) are generated at the rising edge of the next count clock (see Figure 6-7).
(d) Note when CRC001 (bit 1 of capture/compare control register 00 (CRC00)) is set to 1
When the count value of the TM00 register is captured to the CR000 register in the phase reverse to the
signal input to the TI000 pin, the interrupt signal (INTTM000) is not generated after the count value is
captured. If the valid edge is detected on the TI010 pin during this operation, the capture operation is not
performed but the INTTM000 signal is generated as an external interrupt signal. Mask the INTTM000 signal
when the external interrupt is not used.
(10) Edge detection
(a) Specifying valid edge after reset
If the operation of the 16-bit timer/event counter 00 is enabled after reset and while the TI000 or TI010 pin is
at high level and when the rising edge or both the edges are specified as the valid edge of the TI000 or TI010
pin, then the high level of the TI000 or TI010 pin is detected as the rising edge. Note this when the TI000 or
TI010 pin is pulled up. However, the rising edge is not detected when the operation is once stopped and
then enabled again.
(b) Sampling clock for eliminating noise
The sampling clock for eliminating noise differs depending on whether the valid edge of TI000 is used as the
count clock or capture trigger. In the former case, the sampling clock is fixed to fPRS. In the latter, the count
clock selected by PRM00 is used for sampling.
When the signal input to the TI000 pin is sampled and the valid level is detected two times in a row, the valid
edge is detected. Therefore, noise having a short pulse width can be eliminated (see Figure 6-7).
(11) Timer operation
The signal input to the TI000/TI010 pin is not acknowledged while the timer is stopped, regardless of the
operation mode of the CPU.
Remark fPRS: Peripheral hardware clock frequency
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
7.1 Functions of 8-Bit Timer/Event Counters 50 and 51
8-bit timer/event counters 50 and 51 have the following functions.
• Interval timer
• External event counter
• Square-wave output
• PWM output
7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51
8-bit timer/event counters 50 and 51 include the following hardware.
Table 7-1. Configuration of 8-Bit Timer/Event Counters 50 and 51
Item
Timer register
Configuration
8-bit timer counter 5n (TM5n)
Register
8-bit timer compare register 5n (CR5n)
Timer input
TI5n
Timer output
TO5n
Control registers
Timer clock selection register 5n (TCL5n)
8-bit timer mode control register 5n (TMC5n)
Port mode register 1 (PM1) or port mode register 3 (PM3)
Port register 1 (P1) or port register 3 (P3)
Figures 7-1 and 7-2 show the block diagrams of 8-bit timer/event counters 50 and 51.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50
Internal bus
Selector
Match
Selector
INTTM50
Note 1
S
Q
INV
8-bit timer
OVF
counter 50 (TM50)
To TMH0
To UART0
To UART6
Selector
TI50/TO50/P17
fPRS
fPRS/2
fPRS/22
fPRS/26
fPRS/28
fPRS/213
Mask circuit
8-bit timer compare
register 50 (CR50)
R
TO50/TI50/
P17
Output latch
(P17)
Note 2
S
3
Invert
level
R
Clear
PM17
TCE50 TMC506 LVS50 LVR50 TMC501 TOE50
TCL502 TCL501 TCL500
8-bit timer mode control
register 50 (TMC50)
Timer clock selection
register 50 (TCL50)
Internal bus
Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 51
Internal bus
Selector
Match
Selector
INTTM51
Note 1
S
Q
INV
8-bit timer
OVF
counter 51 (TM51)
R
Selector
TI51/TO51/
P33/INTP4
fPRS
fPRS/2
fPRS/24
fPRS/26
fPRS/28
fPRS/212
Mask circuit
8-bit timer compare
register 51 (CR51)
Note 2
S
3
Clear
TCL512 TCL511 TCL510
Timer clock selection
register 51 (TCL51)
R
Invert
level
TCE51 TMC516 LVS51 LVR51 TMC511 TOE51
8-bit timer mode control
register 51 (TMC51)
Internal bus
Notes 1.
Timer output F/F
2.
PWM output F/F
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User’s Manual U17734EJ2V0UD
TO51/TI51/
P33/INTP4
Output latch
(P33)
PM33
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
(1) 8-bit timer counter 5n (TM5n)
TM5n is an 8-bit register that counts the count pulses and is read-only.
The counter is incremented in synchronization with the rising edge of the count clock.
Figure 7-3. Format of 8-Bit Timer Counter 5n (TM5n)
Address: FF16H (TM50), FF1FH (TM51)
After reset: 00H
R
Symbol
TM5n
(n = 0, 1)
In the following situations, the count value is cleared to 00H.
Reset signal generation
When TCE5n is cleared
When TM5n and CR5n match in the mode in which clear & start occurs upon a match of the TM5n and
CR5n.
(2) 8-bit timer compare register 5n (CR5n)
CR5n can be read and written by an 8-bit memory manipulation instruction.
Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count
value, and an interrupt request (INTTM5n) is generated if they match.
In the PWM mode, the TO5n pin becomes inactive when the values of TM5n and CR5n match, but no interrupt is
generated.
The value of CR5n can be set within 00H to FFH.
Reset signal generation sets CR5n to 00H.
Figure 7-4. Format of 8-Bit Timer Compare Register 5n (CR5n)
Address: FF17H (CR50), FF41H (CR51)
After reset: 00H
R/W
Symbol
CR5n
(n = 0, 1)
Cautions 1. In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do
not write other values to CR5n during operation.
2. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock
selected by TCL5n) or more.
Remark
n = 0, 1
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51
The following four registers are used to control 8-bit timer/event counters 50 and 51.
• Timer clock selection register 5n (TCL5n)
• 8-bit timer mode control register 5n (TMC5n)
• Port mode register 1 (PM1) or port mode register 3 (PM3)
• Port register 1 (P1) or port register 3 (P3)
(1) Timer clock selection register 5n (TCL5n)
This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input.
TCL5n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets TCL5n to 00H.
Remark
n = 0, 1
Figure 7-5. Format of Timer Clock Selection Register 50 (TCL50)
Address: FF6AH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
TCL50
0
0
0
0
0
TCL502
TCL501
TCL500
TCL502
TCL501
TCL500
Count clock selection
fPRS =
fPRS =
fPRS =
fPRS =
2 MHz
5 MHz
10 MHz
20 MHz
0
0
0
TI50 pin falling edge
0
0
1
TI50 pin rising edge
0
1
0
fPRS
2 MHz
5 MHz
10 MHz
20 MHz
0
1
1
fPRS/2
1 MHz
2.5 MHz
5 MHz
10 MHz
1
0
0
fPRS/2
2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
fPRS/2
6
31.25 kHz
78.13 kHz
156.25 kHz 312.5 kHz
fPRS/2
8
7.81 kHz
19.53 kHz
39.06 kHz
78.13 kHz
fPRS/2
13
0.24 kHz
0.61 kHz
1.22 kHz
2.44 kHz
1
1
1
0
1
1
1
0
1
Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to 0.
Remark
194
fPRS: Peripheral hardware clock frequency
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Figure 7-6. Format of Timer Clock Selection Register 51 (TCL51)
Address: FF8CH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
TCL51
0
0
0
0
0
TCL512
TCL511
TCL510
TCL512
TCL511
TCL510
Count clock selection
fPRS =
fPRS =
fPRS =
fPRS =
2 MHz
5 MHz
10 MHz
20 MHz
0
0
0
TI51 pin falling edge
0
0
1
TI51 pin rising edge
0
1
0
fPRS
2 MHz
5 MHz
10 MHz
20 MHz
0
1
1
fPRS/2
1 MHz
2.5 MHz
5 MHz
10 MHz
1
0
0
fPRS/2
4
125 kHz
312.5 kHz
625 kHz
1.25 MHz
fPRS/2
6
31.25 kHz
78.13 kHz
156.25 kHz 312.5 kHz
fPRS/2
8
7.81 kHz
19.53 kHz
39.06 kHz
78.13 kHz
fPRS/2
12
0.49 kHz
1.22 kHz
2.44 kHz
4.88 kHz
1
1
1
0
1
1
1
0
1
Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to 0.
Remark
fPRS: Peripheral hardware clock frequency
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
(2) 8-bit timer mode control register 5n (TMC5n)
TMC5n is a register that performs the following five types of settings.
8-bit timer counter 5n (TM5n) count operation control
8-bit timer counter 5n (TM5n) operating mode selection
Timer output F/F (flip flop) status setting
Active level selection in timer F/F control or PWM (free-running) mode.
Timer output control
TMC5n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Remark
n = 0, 1
Figure 7-7. Format of 8-Bit Timer Mode Control Register 50 (TMC50)
Address: FF6BH
After reset: 00H
R/W
Note
Symbol
6
5
4
1
TMC50
TCE50
TMC506
0
0
LVS50
LVR50
TMC501
TOE50
TCE50
TM50 count operation control
0
After clearing to 0, count operation disabled (counter stopped)
1
Count operation start
TMC506
TM50 operating mode selection
0
Mode in which clear & start occurs on a match between TM50 and CR50
1
PWM (free-running) mode
LVS50
LVR50
0
0
No change
0
1
Timer output F/F clear (0) (default output value of TO50 pin: low level)
1
0
Timer output F/F set (1) (default output value of TO50 pin: high level)
1
1
Setting prohibited
TMC501
Timer output F/F status setting
In other modes (TMC506 = 0)
In PWM mode (TMC506 = 1)
Timer F/F control
Active level selection
0
Inversion operation disabled
Active-high
1
Inversion operation enabled
Active-low
TOE50
Timer output control
0
Output disabled (TM50 output is low level)
1
Output enabled
Note Bits 2 and 3 are write-only.
(Cautions and Remarks are listed on the next page.)
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Figure 7-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51)
Address: FF43H
After reset: 00H
R/W
Note
Symbol
6
5
4
1
TMC51
TCE51
TMC516
0
0
LVS51
LVR51
TMC511
TOE51
TCE51
TM51 count operation control
0
After clearing to 0, count operation disabled (counter stopped)
1
Count operation start
TMC516
TM51 operating mode selection
0
Mode in which clear & start occurs on a match between TM51 and CR51
1
PWM (free-running) mode
LVS51
LVR51
0
0
No change
0
1
Timer output F/F clear (0) (default output value of TO51 pin: low)
1
0
Timer output F/F set (1) (default output value of TO51 pin: high)
1
1
Setting prohibited
TMC511
Timer output F/F status setting
In other modes (TMC516 = 0)
In PWM mode (TMC516 = 1)
Timer F/F control
Active level selection
0
Inversion operation disabled
Active-high
1
Inversion operation enabled
Active-low
TOE51
Timer output control
0
Output disabled (TM51 output is low level)
1
Output enabled
Note Bits 2 and 3 are write-only.
Cautions 1. The settings of LVS5n and LVR5n are valid in other than PWM mode.
2. Perform to below in the following order, not at the same time.
Set TMC5n1, TMC5n6:
Operation mode setting
Set TOE5n to enable output:
Timer output enable
Set LVS5n, LVR5n (see Caution 1): Timer F/F setting
Set TCE5n
3. Stop operation before rewriting TMC5n6.
Remarks 1. In PWM mode, PWM output is made inactive by clearing TCE5n to 0.
2. If LVS5n and LVR5n are read, the value is 0.
3. The values of the TMC5n6, LVS5n, LVR5n, TMC5n1, and TOE5n bits are reflected at the TO5n pin
regardless of the value of TCE5n.
4. n = 0, 1
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
(3) Port mode registers 1 and 3 (PM1, PM3)
These registers set port 1 and 3 input/output in 1-bit units.
When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer output, clear PM17 and PM33 and the
output latches of P17 and P33 to 0.
When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer input, set PM17 and PM33 to 1. The
output latches of P17 and P33 at this time may be 0 or 1.
PM1 and PM3 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 7-9. Format of Port Mode Register 1 (PM1)
Address: FF21H
Symbol
PM1
After reset: FFH
R/W
7
6
5
4
3
2
1
0
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
PM1n
P1n pin I/O mode selection (n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Figure 7-10. Format of Port Mode Register 3 (PM3)
Address: FF23H
R/W
Symbol
7
6
5
4
3
2
1
0
PM3
1
1
1
1
PM33
PM32
PM31
PM30
PM3n
198
After reset: FFH
P3n pin I/O mode selection (n = 0 to 3)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
7.4 Operations of 8-Bit Timer/Event Counters 50 and 51
7.4.1 Operation as interval timer
8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals
of the count value preset to 8-bit timer compare register 5n (CR5n).
When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the
TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n
(TCL5n).
Setting
Set the registers.
• TCL5n:
Select the count clock.
• CR5n:
Compare value
• TMC5n:
Stop the count operation, select the mode in which clear & start occurs on a match of TM5n
and CR5n.
(TMC5n = 0000×××0B × = Don’t care)
After TCE5n = 1 is set, the count operation starts.
If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).
INTTM5n is generated repeatedly at the same interval.
Set TCE5n to 0 to stop the count operation.
Caution Do not write other values to CR5n during operation.
Remarks 1. For how to enable the INTTM5n signal interrupt, see CHAPTER 18 INTERRUPT FUNCTIONS.
2. n = 0, 1
Figure 7-11. Interval Timer Operation Timing (1/2)
(a) Basic operation
t
Count clock
TM5n count value
00H
01H
Count start
CR5n
N
N
00H
01H
Clear
N
00H
01H
N
Clear
N
N
N
TCE5n
INTTM5n
Interrupt acknowledged
Interval time
Remark
Interrupt acknowledged
Interval time
Interval time = (N + 1) × t
N = 01H to FFH
n = 0, 1
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Figure 7-11. Interval Timer Operation Timing (2/2)
(b) When CR5n = 00H
t
Count clock
TM5n 00H
00H
00H
CR5n
00H
00H
TCE5n
INTTM5n
Interval time
(c) When CR5n = FFH
t
Count clock
TM5n
CR5n
01H
FFH
FEH
FFH
00H
FEH FFH
FFH
00H
FFH
TCE5n
INTTM5n
Interrupt acknowledged
Interval time
Remark
200
n = 0, 1
User’s Manual U17734EJ2V0UD
Interrupt
acknowledged
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
7.4.2 Operation as external event counter
The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer
counter 5n (TM5n).
TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input.
Either the rising or falling edge can be selected.
When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0
and an interrupt request signal (INTTM5n) is generated.
Whenever the TM5n value matches the value of CR5n, INTTM5n is generated.
Setting
Set each register.
• Set the port mode register (PM17 or PM33)Note to 1.
• TCL5n: Select TI5n pin input edge.
TI5n pin falling edge → TCL5n = 00H
TI5n pin rising edge → TCL5n = 01H
• CR5n:
Compare value
• TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and
CR5n, disable the timer F/F inversion operation, disable timer output.
(TMC5n = 0000××00B × = Don’t care)
When TCE5n = 1 is set, the number of pulses input from the TI5n pin is counted.
When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).
After these settings, INTTM5n is generated each time the values of TM5n and CR5n match.
Note 8-bit timer/event counter 50: PM17
8-bit timer/event counter 51: PM33
Remark
For how to enable the INTTM5n signal interrupt, see CHAPTER 18 INTERRUPT FUNCTIONS.
Figure 7-12. External Event Counter Operation Timing (with Rising Edge Specified)
TI5n
Count start
TM5n count value
00H
01H
02H
03H
04H
05H
CR5n
N−1
N
00H
01H
02H
03H
N
INTTM5n
Remark
N = 00H to FFH
n = 0, 1
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
7.4.3 Square-wave output operation
A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer
compare register 5n (CR5n).
The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0
(TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1. This enables a square wave with any selected
frequency to be output (duty = 50%).
Setting
Set each register.
• Clear the port output latch (P17 or P33)Note and port mode register (PM17 or PM33)Note to 0.
• TCL5n: Select the count clock.
• CR5n:
Compare value
• TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and
CR5n.
LVS5n
LVR5n
Timer Output F/F Status Setting
1
0
Timer output F/F clear (0) (default output value of TO50 pin: low level)
0
1
Timer output F/F set (1) (default output value of TO5n pin: high level)
Timer output enabled
(TMC5n = 00001011B or 00000111B)
After TCE5n = 1 is set, the count operation starts.
The timer output F/F is inverted by a match of TM5n and CR5n. After INTTM5n is generated, TM5n is
cleared to 00H.
After these settings, the timer output F/F is inverted at the same interval and a square wave is output from
TO5n.
The frequency is as follows.
• Frequency = 1/2t (N + 1)
(N: 00H to FFH)
Note 8-bit timer/event counter 50: P17, PM17
8-bit timer/event counter 51: P33, PM33
Caution Do not write other values to CR5n during operation.
Remarks 1. For how to enable the INTTM5n signal interrupt, see CHAPTER 18 INTERRUPT FUNCTIONS.
2. n = 0, 1
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Figure 7-13. Square-Wave Output Operation Timing
t
Count clock
TM5n count value
00H
01H
02H
N−1
N
00H
01H
02H
N−1
N
00H
Count start
CR5n
N
TO5nNote
Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control
register 5n (TMC5n).
7.4.4 PWM output operation
8-bit timer/event counter 5n operates as a PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n
(TMC5n) is set to 1.
The duty pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n.
Set the active level width of the PWM pulse to CR5n; the active level can be selected with bit 1 (TMC5n1) of
TMC5n.
The count clock can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n).
PWM output can be enabled/disabled with bit 0 (TOE5n) of TMC5n.
Caution In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by
TCL5n) or more.
Remark
n = 0, 1
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
(1) PWM output basic operation
Setting
Set each register.
• Clear the port output latch (P17 or P33)Note and port mode register (PM17 or PM33)Note to 0.
• TCL5n: Select the count clock.
• CR5n:
Compare value
• TMC5n: Stop the count operation, select PWM mode.
The timer output F/F is not changed.
TMC5n1
Active Level Selection
0
Active-high
1
Active-low
Timer output enabled
(TMC5n = 01000001B or 01000011B)
The count operation starts when TCE5n = 1.
Clear TCE5n to 0 to stop the count operation.
Note 8-bit timer/event counter 50: P17, PM17
8-bit timer/event counter 51: P33, PM33
PWM output operation
PWM output (output from TO5n) outputs an inactive level until an overflow occurs.
When an overflow occurs, the active level is output. The active level is output until CR5n matches the count
value of 8-bit timer counter 5n (TM5n).
After the CR5n matches the count value, the inactive level is output until an overflow occurs again.
Operations and are repeated until the count operation stops.
When the count operation is stopped with TCE5n = 0, PWM output becomes inactive.
For details of timing, see Figures 7-14 and 7-15.
The cycle, active-level width, and duty are as follows.
• Cycle = 28t
• Active-level width = Nt
• Duty = N/28
(N = 00H to FFH)
Remark
204
n = 0, 1
User’s Manual U17734EJ2V0UD
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Figure 7-14. PWM Output Operation Timing
(a) Basic operation (active level = H)
t
Count clock
TM5n
00H 01H
CR5n
N
FFH 00H 01H 02H
N N+1
FFH 00H 01H 02H
M
00H
TCE5n
INTTM5n
TO5n
Active level
Inactive level
Inactive level
Inactive level
Active level
(b) CR5n = 00H
t
Count clock
TM5n
00H 01H
CR5n
00H
FFH 00H 01H 02H
FFH 00H 01H 02H
M 00H
TCE5n
INTTM5n
TO5n L (Inactive level)
(c) CR5n = FFH
t
TM5n
00H 01H
CR5n
FFH
FFH 00H 01H 02H
FFH 00H 01H 02H
M 00H
TCE5n
INTTM5n
TO5n
Inactive level
Active level
Active level
Inactive level
Inactive level
Remarks 1. to and in Figure 7-14 (a) correspond to to and in PWM output operation in
7.4.4 (1) PWM output basic operation.
2. n = 0, 1
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
(2) Operation with CR5n changed
Figure 7-15. Timing of Operation with CR5n Changed
(a) CR5n value is changed from N to M before clock rising edge of FFH
→ Value is transferred to CR5n at overflow immediately after change.
t
Count clock
TM5n
N N+1 N+2
CR5n
N
TCE5n
INTTM5n
FFH 00H 01H 02H
M M+1 M+2
FFH 00H 01H 02H
M M+1 M+2
M
H
TO5n
CR5n change (N → M)
(b) CR5n value is changed from N to M after clock rising edge of FFH
→ Value is transferred to CR5n at second overflow.
t
Count clock
TM5n
N N+1 N+2
CR5n
TCE5n
INTTM5n
N
FFH 00H 01H 02H
N N+1 N+2
FFH 00H 01H 02H
N
M M+1 M+2
M
H
TO5n
CR5n change (N → M)
Caution When reading from CR5n between and in Figure 7-15, the value read differs from the
actual value (read value: M, actual value of CR5n: N).
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51
(1) Timer start error
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock.
Figure 7-16. 8-Bit Timer Counter 5n Start Timing
Count clock
TM5n count value
00H
01H
02H
03H
04H
Timer start
Remark
n = 0, 1
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CHAPTER 8 8-BIT TIMERS H0 AND H1
8.1 Functions of 8-Bit Timers H0 and H1
8-bit timers H0 and H1 have the following functions.
• Interval timer
• Square-wave output
• PWM output
• Carrier generator (8-bit timer H1 only)
8.2 Configuration of 8-Bit Timers H0 and H1
8-bit timers H0 and H1 include the following hardware.
Table 8-1. Configuration of 8-Bit Timers H0 and H1
Item
Configuration
Timer register
8-bit timer counter Hn
Registers
8-bit timer H compare register 0n (CMP0n)
Timer output
TOHn, output controller
Control registers
8-bit timer H mode register n (TMHMDn)
8-bit timer H compare register 1n (CMP1n)
8-bit timer H carrier control register 1 (TMCYC1)
Port mode register 1 (PM1)
Port register 1 (P1)
Note 8-bit timer H1 only
Remark
n = 0, 1
Figures 8-1 and 8-2 show the block diagrams.
208
User’s Manual U17734EJ2V0UD
Note
Figure 8-1. Block Diagram of 8-Bit Timer H0
Internal bus
8-bit timer H mode register 0
(TMHMD0)
TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0
3
8-bit timer H
compare register
10 (CMP10)
8-bit timer H
compare register
00 (CMP00)
2
Decoder
TOH0/P15
fPRS
fPRS/2
fPRS/22
fPRS/26
fPRS/210
8-bit timer/
event counter 50
output
Selector
User’s Manual U17734EJ2V0UD
Match
Interrupt
generator
F/F
R
Output
controller
Level
inversion
Output latch
(P15)
8-bit timer
counter H0
Clear
PWM mode signal
Timer H enable signal
1
0
INTTMH0
PM15
CHAPTER 8 8-BIT TIMERS H0 AND H1
Selector
209
210
Figure 8-2. Block Diagram of 8-Bit Timer H1
Internal bus
8-bit timer H mode
register 1 (TMHMD1)
TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1
3
8-bit timer H
compare
register 0 1
(CMP01)
8-bit timer H
compare
register 1 1
(CMP11)
8-bit timer H carrier
control register 1
RMC1 NRZB1 NRZ1 (TMCYC1)
INTTM51
Reload/
interrupt control
2
TOH1/
INTP5/
P16
Decoder
Selector
User’s Manual U17734EJ2V0UD
Match
fPRS
fPRS/22
fPRS/24
fPRS/26
fPRS/212
fRL
fRL/27
fRL/29
Interrupt
generator
F/F
R
Output
controller
Level
inversion
Output latch
(P16)
8-bit timer
counter H1
Carrier generator mode signal
Clear
PWM mode signal
Timer H enable signal
1
0
INTTMH1
PM16
CHAPTER 8 8-BIT TIMERS H0 AND H1
Selector
CHAPTER 8 8-BIT TIMERS H0 AND H1
(1) 8-bit timer H compare register 0n (CMP0n)
This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the
timer operation modes.
This register constantly compares the value set to CMP0n with the count value of the 8-bit timer counter Hn and,
when the two values match, generates an interrupt request signal (INTTMHn) and inverts the output level of
TOHn.
Rewrite the value of CMP0n while the timer is stopped (TMHEn = 0).
A reset signal generation sets this register to 00H.
Figure 8-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n)
Address: FF18H (CMP00), FF1AH (CMP01)
Symbol
CMP0n
(n = 0, 1)
7
5
6
After reset: 00H
4
3
R/W
2
1
0
Caution CMP0n cannot be rewritten during timer count operation.
(2) 8-bit timer H compare register 1n (CMP1n)
This register can be read or written by an 8-bit memory manipulation instruction. This register is used in the
PWM output mode and carrier generator mode.
In the PWM output mode, this register constantly compares the value set to CMP1n with the count value of the 8bit timer counter Hn and, when the two values match, inverts the output level of TOHn. No interrupt request
signal is generated.
In the carrier generator mode, the CMP1n register always compares the value set to CMP1n with the count value
of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn).
At the same time, the count value is cleared.
CMP1n can be rewritten during timer count operation.
If the value of CMP1n is rewritten while the timer is operating, the new value is latched and transferred to CMP1n
when the count value of the timer matches the old value of CMP1n, and then the value of CMP1n is changed to
the new value. If matching of the count value and the CMP1n value and writing a value to CMP1n conflict, the
value of CMP1n is not changed.
A reset signal generation sets this register to 00H.
Figure 8-4. Format of 8-Bit Timer H Compare Register 1n (CMP1n)
Address: FF19H (CMP10), FF1BH (CMP11)
Symbol
CMP1n
(n = 0, 1)
7
6
5
After reset: 00H
4
3
R/W
2
1
0
Caution In the PWM output mode and carrier generator mode, be sure to set CMP1n when starting the
timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be
sure to set again even if setting the same value to CMP1n).
Remark
n = 0, 1
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CHAPTER 8 8-BIT TIMERS H0 AND H1
8.3 Registers Controlling 8-Bit Timers H0 and H1
The following four registers are used to control 8-bit timers H0 and H1.
• 8-bit timer H mode register n (TMHMDn)
• 8-bit timer H carrier control register 1 (TMCYC1)Note
• Port mode register 1 (PM1)
• Port register 1 (P1)
Note 8-bit timer H1 only
(1) 8-bit timer H mode register n (TMHMDn)
This register controls the mode of timer H.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Remark n = 0, 1
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CHAPTER 8 8-BIT TIMERS H0 AND H1
Figure 8-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0)
Address: FF69H
TMHMD0
After reset: 00H
R/W
6
5
4
TMHE0
CKS02
CKS01
CKS00
TMHE0
3
2
TMMD01 TMMD00 TOLEV0
TOEN0
Timer operation enable
0
Stops timer count operation (counter is cleared to 0)
1
Enables timer count operation (count operation started by inputting clock)
CKS02
CKS01
CKS00
Count clock selection
0
0
0
fPRS
0
0
1
fPRS/2
fPRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
fPRS =
20 MHz
2 MHz
5 MHz
10 MHz
20 MHz
1 MHz
2.5 MHz
5 MHz
10 MHz
2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
6
31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
0
1
0
0
1
1
fPRS/2
1
0
0
fPRS/210 1.95 kHz
1
0
1
Other than above
fPRS/2
9.77 kHz
19.54 kHz
TM50 output
Setting prohibited
TMMD01 TMMD00
Timer operation mode
0
0
Interval timer mode
1
0
PWM output mode
Other than above
4.88 kHz
Note
Setting prohibited
TOLEV0
Timer output level control (in default mode)
0
Low level
1
High level
TOEN0
Timer output control
0
Disables output
1
Enables output
Note Note the following points when selecting the TM50 output as the count clock.
• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of the 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
• PWM mode (TMC506 = 1)
Start the operation of the 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
It is not necessary to enable the TO50 pin as a timer output pin in any mode.
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CHAPTER 8 8-BIT TIMERS H0 AND H1
Cautions 1. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited.
2. In the PWM output mode, be sure to set the 8-bit timer H compare register 10 (CMP10) when
starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped
(TMHE0 = 0) (be sure to set again even if setting the same value to CMP10).
Remarks 1. fPRS: Peripheral hardware clock frequency
2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)
TMC501: Bit 1 of TMC50
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CHAPTER 8 8-BIT TIMERS H0 AND H1
Figure 8-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
Address: FF6CH
TMHMD1
After reset: 00H
R/W
6
5
4
TMHE1
CKS12
CKS11
CKS10
TMHE1
3
2
TMMD11 TMMD10 TOLEV1
TOEN1
Timer operation enable
0
Stops timer count operation (counter is cleared to 0)
1
Enables timer count operation (count operation started by inputting clock)
CKS12
0
0
CKS11
0
0
CKS10
0
1
Count clock selection
fPRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
fPRS =
20 MHz
10 MHz
20 MHz
2 MHz
5 MHz
2
500 kHz
1.25 MHz 2.5 MHz
5 MHz
4
125 kHz
312.5 kHz 625 kHz
1.25 MHz
6
31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
fPRS
fPRS/2
0
1
0
0
1
1
fPRS/2
1
0
0
fPRS/212 0.49 kHz
1
0
1
fPRS/2
1.22 kHz
7
1.88 kHz (TYP.)
9
fRL/2
1
1
0
fRL/2
0.47 kHz (TYP.)
1
1
1
fRL
240 kHz (TYP.)
TMMD11 TMMD10
4.88 kHz
Timer operation mode
0
0
Interval timer mode
0
1
Carrier generator mode
1
0
PWM output mode
1
1
Setting prohibited
TOLEV1
2.44 kHz
Timer output level control (in default mode)
0
Low level
1
High level
TOEN1
Timer output control
0
Disables output
1
Enables output
Cautions 1. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited.
2. In the PWM output mode and carrier generator mode, be sure to set the 8-bit timer H compare
register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count
operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to
CMP11).
3. When the carrier generator mode is used, set so that the count clock frequency of TMH1
becomes more than 6 times the count clock frequency of TM51.
Remarks 1. fPRS: Peripheral hardware clock frequency
2. fRL:
Internal low-speed oscillation clock frequency
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CHAPTER 8 8-BIT TIMERS H0 AND H1
(2) 8-bit timer H carrier control register 1 (TMCYC1)
This register controls the remote control output and carrier pulse output status of 8-bit timer H1.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 8-7. Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1)
Address: FF6DH
After reset: 00H
R/WNote
TMCYC1
0
0
0
0
0
RMC1
NRZB1
0
0
Low-level output
0
1
High-level output
1
0
Low-level output
1
1
Carrier pulse output
RMC1
NRZB1
NRZ1
Remote control output
NRZ1
Carrier pulse output status flag
0
Carrier output disabled status (low-level status)
1
Carrier output enabled status
(RMC1 = 1: Carrier pulse output, RMC1 = 0: High-level status)
Note Bit 0 is read-only.
(3) Port mode register 1 (PM1)
This register sets port 1 input/output in 1-bit units.
When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output
latches of P15 and P16 to 0.
PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 8-8. Format of Port Mode Register 1 (PM1)
Address: FF21H
Symbol
PM1
R/W
7
6
5
4
3
2
1
0
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
PM1n
216
After reset: FFH
P1n pin I/O mode selection (n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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CHAPTER 8 8-BIT TIMERS H0 AND H1
8.4 Operation of 8-Bit Timers H0 and H1
8.4.1 Operation as interval timer/square-wave output
When the 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn)
is generated and the 8-bit timer counter Hn is cleared to 00H.
Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of the 8-bit timer counter Hn and
the CMP1n register is not detected even if the CMP1n register is set, timer output is not affected.
By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%)
is output from TOHn.
Setting
Set each register.
Figure 8-9. Register Setting During Interval Timer/Square-Wave Output Operation
(i)
TMHMDn
Setting timer H mode register n (TMHMDn)
TMHEn
CKSn2
CKSn1
CKSn0
0
0/1
0/1
0/1
TMMDn1 TMMDn0 TOLEVn
0
0
0/1
TOENn
0/1
Timer output setting
Default setting of timer output level
Interval timer mode setting
Count clock (fCNT) selection
Count operation stopped
(ii) CMP0n register setting
The interval time is as follows if N is set as a comparison value.
• Interval time = (N +1)/fCNT
Count operation starts when TMHEn = 1.
When the values of the 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is
generated and the 8-bit timer counter Hn is cleared to 00H.
Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, clear
TMHEn to 0.
Remarks 1. For the setting of the output pin, see 8.3 (3) Port mode register 1 (PM1).
2. For how to enable the INTTMHn signal interrupt, see CHAPTER 18 INTERRUPT FUNCTIONS.
3. n = 0, 1
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CHAPTER 8 8-BIT TIMERS H0 AND H1
Figure 8-10. Timing of Interval Timer/Square-Wave Output Operation (1/2)
(a) Basic operation (Operation When 01H ≤ CMP0n ≤ FEH)
Count clock
Count start
00H
8-bit timer counter Hn
01H
N
00H
01H
N
Clear
00H
01H 00H
Clear
N
CMP0n
TMHEn
INTTMHn
Interval time
TOHn
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear
The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than
1 clock after the operation is enabled.
When the value of the 8-bit timer counter Hn matches the value of the CMP0n register, the value of the timer
counter is cleared, and the level of the TOHn output is inverted. In addition, the INTTMHn signal is output at
the rising edge of the count clock.
If the TMHEn bit is cleared to 0 while timer H is operating, the INTTMHn signal and TOHn output are set to
the default level. If they are already at the default level before the TMHEn bit is cleared to 0, then that level
is maintained.
Remark
n = 0, 1
01H ≤ N ≤ FEH
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CHAPTER 8 8-BIT TIMERS H0 AND H1
Figure 8-10. Timing of Interval Timer/Square-Wave Output Operation (2/2)
(b) Operation when CMP0n = FFH
Count clock
Count start
8-bit timer counter Hn
00H
01H
FEH
FFH
00H
FEH
Clear
FFH
00H
Clear
FFH
CMP0n
TMHEn
INTTMHn
TOHn
Interval time
(c) Operation when CMP0n = 00H
Count clock
Count start
8-bit timer counter Hn
00H
CMP0n
00H
TMHEn
INTTMHn
TOHn
Interval time
Remark
n = 0, 1
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CHAPTER 8 8-BIT TIMERS H0 AND H1
8.4.2 Operation as PWM output
In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n
register during timer operation is prohibited.
The 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n
register during timer operation is possible.
The operation in PWM output mode is as follows.
The TOHn output level is inverted and the 8-bit timer counter Hn is cleared to 0 when the 8-bit timer counter Hn
and the CMP0n register match after the timer count is started. The TOHn output level is inverted when the 8-bit timer
counter Hn and the CMP1n register match.
Setting
Set each register.
Figure 8-11. Register Setting in PWM Output Mode
(i)
TMHMDn
Setting timer H mode register n (TMHMDn)
TMHEn
CKSn2
CKSn1
CKSn0
0
0/1
0/1
0/1
TMMDn1 TMMDn0 TOLEVn
1
0
0/1
TOENn
1
Timer output enabled
Default setting of timer output level
PWM output mode selection
Count clock (fCNT) selection
Count operation stopped
(ii) Setting CMP0n register
• Compare value (N): Cycle setting
(iii) Setting CMP1n register
• Compare value (M): Duty setting
Remarks 1. n = 0, 1
2. 00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
The count operation starts when TMHEn = 1.
The CMP0n register is the compare register that is to be compared first after counter operation is enabled.
When the values of the 8-bit timer counter Hn and the CMP0n register match, the 8-bit timer counter Hn is
cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output is inverted. At the same time,
the compare register to be compared with the 8-bit timer counter Hn is changed from the CMP0n register to
the CMP1n register.
When the 8-bit timer counter Hn and the CMP1n register match, TOHn output is inverted and the compare
register to be compared with the 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n
register. At this time, the 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
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CHAPTER 8 8-BIT TIMERS H0 AND H1
By performing procedures and repeatedly, a pulse with an arbitrary duty can be obtained.
To stop the count operation, set TMHEn = 0.
If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count
clock frequency is fCNT, the PWM pulse output cycle and duty are as follows.
• PWM pulse output cycle = (N + 1)/fCNT
• Duty = (M + 1)/(N + 1)
Cautions 1. The set value of the CMP1n register can be changed while the timer counter is operating.
However, this takes a duration of three operating clocks (signal selected by the CKSn2 to
CKSn0 bits of the TMHMDn register) from when the value of the CMP1n register is changed
until the value is transferred to the register.
2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after
the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the
same value to the CMP1n register).
3. Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are
within the following range.
00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
Remarks 1. For the setting of the output pin, see 8.3 (3) Port mode register 1 (PM1).
2. For details on how to enable the INTTMHn signal interrupt, see CHAPTER 18
INTERRUPT
FUNCTIONS.
3. n = 0, 1
User’s Manual U17734EJ2V0UD
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CHAPTER 8 8-BIT TIMERS H0 AND H1
Figure 8-12. Operation Timing in PWM Output Mode (1/4)
(a) Basic operation
Count clock
8-bit timer counter Hn
00H 01H
A5H 00H 01H 02H
CMP0n
A5H
CMP1n
01H
A5H 00H 01H 02H
A5H 00H
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
TOHn
(TOLEVn = 1)
The count operation is enabled by setting the TMHEn bit to 1. Start the 8-bit timer counter Hn by masking
one count clock to count up. At this time, TOHn output remains the default.
When the values of the 8-bit timer counter Hn and the CMP0n register match, the TOHn output level is
inverted, the value of the 8-bit timer counter Hn is cleared, and the INTTMHn signal is output.
When the values of the 8-bit timer counter Hn and the CMP1n register match, the TOHn output level is
inverted. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output.
Clearing the TMHEn bit to 0 during timer Hn operation sets the INTTMHn signal and TOHn output to the
default.
Remark n = 0, 1
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CHAPTER 8 8-BIT TIMERS H0 AND H1
Figure 8-12. Operation Timing in PWM Output Mode (2/4)
(b) Operation when CMP0n = FFH, CMP1n = 00H
Count clock
8-bit timer counter Hn
00H 01H
FFH 00H 01H 02H
FFH 00H 01H 02H
CMP0n
FFH
CMP1n
00H
FFH 00H
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
(c) Operation when CMP0n = FFH, CMP1n = FEH
Count clock
8-bit timer counter Hn
00H 01H
FEH FFH 00H 01H
FEH FFH 00H 01H
CMP0n
FFH
CMP1n
FEH
FEH FFH 00H
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
Remark
n = 0, 1
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CHAPTER 8 8-BIT TIMERS H0 AND H1
Figure 8-12. Operation Timing in PWM Output Mode (3/4)
(d) Operation when CMP0n = 01H, CMP1n = 00H
Count clock
8-bit timer counter Hn
00H
01H 00H 01H 00H
00H 01H 00H 01H
CMP0n
01H
CMP1n
00H
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
Remark
224
n = 0, 1
User’s Manual U17734EJ2V0UD
CHAPTER 8 8-BIT TIMERS H0 AND H1
Figure 8-12. Operation Timing in PWM Output Mode (4/4)
(e) Operation by changing CMP1n (CMP1n = 02H → 03H, CMP0n = A5H)
Count clock
8-bit timer
counter Hn
00H 01H 02H
80H
A5H 00H 01H 02H 03H
A5H 00H 01H 02H 03H
A5H 00H
A5H
CMP01
02H
CMP11
02H (03H)
03H
’
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
The count operation is enabled by setting TMHEn = 1. Start the 8-bit timer counter Hn by masking one count
clock to count up. At this time, the TOHn output remains default.
The CMP1n register value can be changed during timer counter operation. This operation is asynchronous
to the count clock.
When the values of the 8-bit timer counter Hn and the CMP0n register match, the value of the 8-bit timer
counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is output.
If the CMP1n register value is changed, the value is latched and not transferred to the register. When the
values of the 8-bit timer counter Hn and the CMP1n register before the change match, the value is
transferred to the CMP1n register and the CMP1n register value is changed (’).
However, three count clocks or more are required from when the CMP1n register value is changed to when
the value is transferred to the register. If a match signal is generated within three count clocks, the changed
value cannot be transferred to the register.
When the values of the 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn
output level is inverted. The 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
Clearing the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output default.
Remark n = 0, 1
User’s Manual U17734EJ2V0UD
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CHAPTER 8 8-BIT TIMERS H0 AND H1
8.4.3 Carrier generator operation (8-bit timer H1 only)
In the carrier generator mode, the 8-bit timer H1 is used to generate the carrier signal of an infrared remote
controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count).
The carrier clock generated by the 8-bit timer H1 is output in the cycle set by the 8-bit timer/event counter 51.
In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by the 8-bit timer/event counter
51, and the carrier pulse is output from the TOH1 output.
(1) Carrier generation
In carrier generator mode, the 8-bit timer H compare register 01 (CMP01) generates a low-level width carrier
pulse waveform and the 8-bit timer H compare register 11 (CMP11) generates a high-level width carrier pulse
waveform.
Rewriting the CMP11 register during the 8-bit timer H1 operation is possible but rewriting the CMP01 register is
prohibited.
(2) Carrier output control
Carrier output is controlled by the interrupt request signal (INTTM51) of the 8-bit timer/event counter 51 and the
NRZB1 and RMC1 bits of the 8-bit timer H carrier control register (TMCYC1). The relationship between the
outputs is shown below.
226
RMC1 Bit
NRZB1 Bit
Output
0
0
Low-level output
0
1
High-level output
1
0
Low-level output
1
1
Carrier pulse output
User’s Manual U17734EJ2V0UD
CHAPTER 8 8-BIT TIMERS H0 AND H1
To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register
have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written.
The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal.
The INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to
the NRZ1 bit. The timing for transfer from the NRZB1 bit to the NRZ1 bit is as shown below.
Figure 8-13. Transfer Timing
TMHE1
8-bit timer H1
count clock
INTTM51
INTTM5H1
NRZ1
0
1
0
NRZB1
1
0
1
RMC1
The INTTM51 signal is synchronized with the count clock of the 8-bit timer H1 and is output as the
INTTM5H1 signal.
The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the
INTTM5H1 signal.
Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the
INTTM5H1 interrupt or after timing has been checked by polling the interrupt request flag. Write data to
count the next time to the CR51 register.
Cautions 1. Do not rewrite the NRZB1 bit again until at least the second clock after it has been rewritten,
or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed.
2. When the 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is
generated at the timing of . When the 8-bit timer/event counter 51 is used in a mode other
than the carrier generator mode, the timing of the interrupt generation differs.
User’s Manual U17734EJ2V0UD
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CHAPTER 8 8-BIT TIMERS H0 AND H1
Setting
Set each register.
Figure 8-14. Register Setting in Carrier Generator Mode
(i)
TMHMD1
Setting 8-bit timer H mode register 1 (TMHMD1)
TMHE1
CKS12
CKS11
CKS10
0
0/1
0/1
0/1
TMMD11 TMMD10 TOLEV1
TOEN1
1
1
0
0/1
Timer output enabled
Default setting of timer output level
Carrier generator mode selection
Count clock (fCNT) selection
Count operation stopped
(ii) CMP01 register setting
• Compare value
(iii) CMP11 register setting
• Compare value
(iv) TMCYC1 register setting
• RMC1 = 1 ... Remote control output enable bit
• NRZB1 = 0/1 ... carrier output enable bit
(v) TCL51 and TMC51 register setting
• See 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51.
When TMHE1 = 1, the 8-bit timer H1 starts counting.
When TCE51 of the 8-bit timer mode control register 51 (TMC51) is set to 1, the 8-bit timer/event counter
51 starts counting.
After the count operation is enabled, the first compare register to be compared is the CMP01 register.
When the count value of the 8-bit timer counter H1 and the CMP01 register value match, the INTTMH1
signal is generated, the 8-bit timer counter H1 is cleared. At the same time, the compare register to be
compared with the 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register.
When the count value of the 8-bit timer counter H1 and the CMP11 register value match, the INTTMH1
signal is generated, the 8-bit timer counter H1 is cleared. At the same time, the compare register to be
compared with the 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register.
By performing procedures and repeatedly, a carrier clock is generated.
The INTTM51 signal is synchronized with count clock of the 8-bit timer H1 and output as the INTTM5H1
signal. The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value
is transferred to the NRZ1 bit.
Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the
INTTM5H1 interrupt or after timing has been checked by polling the interrupt request flag. Write data to
count the next time to the CR51 register.
When the NRZ1 bit is high level, a carrier clock is output from the TOH1 pin.
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CHAPTER 8 8-BIT TIMERS H0 AND H1
By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation,
clear TMHE1 to 0.
If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count
clock frequency is fCNT, the carrier clock output cycle and duty are as follows.
• Carrier clock output cycle = (N + M + 2)/fCNT
• Duty = High-level width/carrier clock output width = (M + 1)/(N + M + 2)
Cautions 1. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1)
after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if
setting the same value to the CMP11 register).
2. Set so that the count clock frequency of TMH1 becomes more than 6 times the count
clock frequency of TM51.
3. Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH.
4. The set value of the CMP11 register can be changed while the timer counter is
operating. However, it takes the duration of three operating clocks (signal selected by
the CKS12 to CKS10 bits of the TMHMD1 register) since the value of the CMP11
register has been changed until the value is transferred to the register.
5. Be sure to set the RMC1 bit before the count operation is started.
Remarks 1. For the setting of the output pin, see 8.3 (3) Port mode register 1 (PM1).
2. For how to enable the INTTMH1 signal interrupt, see CHAPTER 18
INTERRUPT
FUNCTIONS.
User’s Manual U17734EJ2V0UD
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CHAPTER 8 8-BIT TIMERS H0 AND H1
Figure 8-15. Carrier Generator Mode Operation Timing (1/3)
(a) Operation when CMP01 = N, CMP11 = N
8-bit timer H1
count clock
8-bit timer counter
H1 count value
00H
N 00H
N
00H
N 00H
CMP01
N
CMP11
N
N 00H
N
00H
N
TMHE11
INTTMH1
Carrier clock
8-bit timer 51
count clock
TM51 count value
00H 01H
K 00H 01H
L
K
CR51
00H 01H
M 00H 01H
L
N 00H 01H
N
M
TCE51
INTTM5n1
INTTM5H1
NRZB1
0
1
0
1
0
NRZ1
0
1
0
1
0
Carrier clock
TOH11
When TMHE1 = 0 and TCE51 = 0, the 8-bit timer counter H1 operation is stopped.
When TMHE1 = 1 is set, the 8-bit timer counter H1 starts a count operation. At that time, the carrier clock
remains default.
When the count value of the 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1
signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8bit timer counter H1 is switched from the CMP01 register to the CMP11 register. The 8-bit timer counter H1
is cleared to 00H.
When the count value of the 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal
is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer
counter H1 is switched from the CMP11 register to the CMP01 register. The 8-bit timer counter H1 is cleared
to 00H.
By performing procedures and repeatedly, a carrier clock with duty fixed to 50% is
generated.
When the INTTM51 signal is generated, it is synchronized with the 8-bit timer H1 count clock and is output as
the INTTM5H1 signal.
The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is
transferred to the NRZ1 bit.
When NRZ1 = 0 is set, the TOH1 output becomes low level.
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CHAPTER 8 8-BIT TIMERS H0 AND H1
Figure 8-15. Carrier Generator Mode Operation Timing (2/3)
(b) Operation when CMP01 = N, CMP11 = M
8-bit timer H1
count clock
8-bit timer counter
H1 count value
00H
N
00H 01H
M 00H
N 00H 01H
CMP01
N
CMP11
M
M 00H
N
00H
TMHE1
INTTMH1
Carrier clock
8-bit timer 51
count clock
TM51 count value
00H 01H
K 00H 01H
L 00H 01H
K
CR51
M 00H 01H
N 00H 01H
M
L
N
TCE51
INTTM51
INTTM5H1
NRZB1
NRZ1
0
1
0
0
1
1
0
0
1
0
Carrier clock
TOH1
When TMHE1 = 0 and TCE51 = 0, the 8-bit timer counter H1 operation is stopped.
When TMHE1 = 1 is set, the 8-bit timer counter H1 starts a count operation. At that time, the carrier clock
remains default.
When the count value of the 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1
signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8bit timer counter H1 is switched from the CMP01 register to the CMP11 register. The 8-bit timer counter H1
is cleared to 00H.
When the count value of the 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal
is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer
counter H1 is switched from the CMP11 register to the CMP01 register. The 8-bit timer counter H1 is cleared
to 00H. By performing procedures and repeatedly, a carrier clock with duty fixed to other than 50%
is generated.
When the INTTM51 signal is generated, it is synchronized with the 8-bit timer H1 count clock and is output as
the INTTM5H1 signal.
A carrier signal is output at the first rising edge of the carrier clock if NRZ1 is set to 1.
When NRZ1 = 0, the TOH1 output is held at the high level and is not changed to low level while the carrier
clock is high level (from and , the high-level width of the carrier clock waveform is guaranteed).
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CHAPTER 8 8-BIT TIMERS H0 AND H1
Figure 8-15. Carrier Generator Mode Operation Timing (3/3)
(c) Operation when CMP11 is changed
8-bit timer H1
count clock
8-bit timer counter
H1 count value
00H 01H
N
00H 01H
M
00H
N
00H 01H
L
00H
N
CMP01
M
CMP11
’
M (L)
L
TMHE1
INTTMH1
Carrier clock
When TMHE1 = 1 is set, the 8-bit timer H1 starts a count operation. At that time, the carrier clock remains
default.
When the count value of the 8-bit timer counter H1 matches the value of the CMP01 register, the INTTMH1
signal is output, the carrier signal is inverted, and the timer counter is cleared to 00H. At the same time, the
compare register whose value is to be compared with that of the 8-bit timer counter H1 is changed from the
CMP01 register to the CMP11 register.
The CMP11 register is asynchronous to the count clock, and its value can be changed while the 8-bit timer
H1 is operating. The new value (L) to which the value of the register is to be changed is latched. When the
count value of the 8-bit timer counter H1 matches the value (M) of the CMP11 register before the change, the
CMP11 register is changed (’).
However, it takes three count clocks or more since the value of the CMP11 register has been changed until
the value is transferred to the register. Even if a match signal is generated before the duration of three count
clocks elapses, the new value is not transferred to the register.
When the count value of 8-bit timer counter H1 matches the value (M) of the CMP1 register before the
change, the INTTMH1 signal is output, the carrier signal is inverted, and the timer counter is cleared to 00H.
At the same time, the compare register whose value is to be compared with that of the 8-bit timer counter H1
is changed from the CMP11 register to the CMP01 register.
The timing at which the count value of the 8-bit timer counter H1 and the CMP11 register value match again
is indicated by the value after the change (L).
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CHAPTER 9 WATCH TIMER
9.1 Functions of Watch Timer
The watch timer has the following functions.
• Watch timer
• Interval timer
The watch timer and the interval timer can be used simultaneously.
Figure 9-1 shows the watch timer block diagram.
7
fPRS/2
11-bit prescaler
fW
fWX
fWX/24
5-bit counter
fWX/25
INTWT
Clear
fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29
Selector
fSUB
Selector
Clear
Selector
Selector
Figure 9-1. Block Diagram of Watch Timer
WTM7
WTM6
WTM5
INTWTI
WTM4
WTM3
WTM2
WTM1
WTM0
Watch timer operation
mode register (WTM)
Internal bus
Remark
fPRS: Peripheral hardware clock frequency
fSUB: Subsystem clock frequency
fW:
Watch timer clock frequency (fPRS/27 or fSUB)
fWX: fW or fW/29
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CHAPTER 9 WATCH TIMER
(1) Watch timer
When the peripheral hardware clock or subsystem clock is used, interrupt request signals (INTWT) are
generated at preset intervals.
Table 9-1. Watch Timer Interrupt Time
Interrupt Time
When Operated at
When Operated at
When Operated at
When Operated at
When Operated at
fSUB = 32.768 kHz
fPRS = 2 MHz
fPRS = 5 MHz
fPRS = 10 MHz
fPRS = 20 MHz
488 μs
4
2 /fW
1.02 ms
410 μs
205 μs
102 μs
5
977 μs
2.05 ms
819 μs
410 μs
205 μs
13
0.25 s
0.52 s
0.210 s
0.105 s
52.5 ms
14
0.5 s
1.05 s
0.419 s
0.210 s
0.105 s
2 /fW
2 /fW
2 /fW
Remark
fPRS: Peripheral hardware clock frequency
fSUB: Subsystem clock frequency
fW:
Watch timer clock frequency (fPRS/27 or fSUB)
(2) Interval timer
Interrupt request signals (INTWTI) are generated at preset time intervals.
Table 9-2. Interval Timer Interval Time
Interval Time
When Operated at
When Operated at
When Operated at
When Operated at
When Operated at
fSUB = 32.768 kHz
fPRS = 2 MHz
fPRS = 5 MHz
fPRS = 10 MHz
fPRS = 20 MHz
4
488 μs
1.02 ms
410 μs
205 μs
102 μs
5
977 μs
2.05 ms
820 μs
410 μs
205 μs
6
1.95 ms
4.10 ms
1.64 ms
820 μs
410 μs
7
3.91 ms
8.20 ms
3.28 ms
1.64 ms
820 μs
8
7.81 ms
16.4 ms
6.55 ms
3.28 ms
1.64 ms
9
15.6 ms
32.8 ms
13.1 ms
6.55 ms
3.28 ms
10
31.3 ms
65.5 ms
26.2 ms
13.1 ms
6.55 ms
11
62.5 ms
131.1 ms
52.4 ms
26.2 ms
13.1 ms
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
2 /fW
Remark
fPRS: Peripheral hardware clock frequency
fSUB: Subsystem clock frequency
fW:
Watch timer clock frequency (fPRS/27 or fSUB)
9.2 Configuration of Watch Timer
The watch timer includes the following hardware.
Table 9-3. Watch Timer Configuration
Item
234
Configuration
Counter
5 bits × 1
Prescaler
11 bits × 1
Control register
Watch timer operation mode register (WTM)
User’s Manual U17734EJ2V0UD
CHAPTER 9 WATCH TIMER
9.3 Register Controlling Watch Timer
The watch timer is controlled by the watch timer operation mode register (WTM).
• Watch timer operation mode register (WTM)
This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit
counter operation control.
WTM is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets WTM to 00H.
Figure 9-2. Format of Watch Timer Operation Mode Register (WTM)
Address: FF6FH
Symbol
WTM
After reset: 00H
R/W
7
6
5
4
3
2
WTM7
WTM6
WTM5
WTM4
WTM3
WTM2
WTM1
WTM0
WTM7
Watch timer count clock selection (fW)
fSUB = 32.768 kHz
0
fPRS/2
1
fSUB
WTM6
−
7
fPRS = 2 MHz
15.625 kHz
fPRS = 5 MHz
39.062 kHz
fPRS = 20 MHz
78.125 kHz
156.25 kHz
−
32.768 kHz
WTM5
fPRS = 10 MHz
WTM4
Prescaler interval time selection
4
0
0
0
2 /fW
0
0
1
2 /fW
0
1
0
2 /fW
0
1
1
2 /fW
1
0
0
2 /fW
1
0
1
2 /fW
1
1
0
2 /fW
1
1
1
2 /fW
WTM3
WTM2
5
6
7
8
9
10
11
Selection of watch timer interrupt time
14
0
0
2 /fW
0
1
2 /fW
1
0
2 /fW
1
1
2 /fW
13
5
4
WTM1
5-bit counter operation control
0
Clear after operation stop
1
Start
WTM0
Watch timer operation enable
0
Operation stop (clear both prescaler and 5-bit counter)
1
Operation enable
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CHAPTER 9 WATCH TIMER
Caution
Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM)
during watch timer operation.
Remarks 1. fW:
Watch timer clock frequency (fPRS/27 or fSUB)
2. fPRS: Peripheral hardware clock frequency
3. fSUB: Subsystem clock frequency
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CHAPTER 9 WATCH TIMER
9.4 Watch Timer Operations
9.4.1 Watch timer operation
The watch timer generates an interrupt request signal (INTWT) at a specific time interval by using the peripheral
hardware clock or subsystem clock.
When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count
operation starts. When these bits are cleared to 0, the 5-bit counter is cleared and the count operation stops.
When the interval timer is simultaneously operated, zero-second start can be achieved only for the watch timer by
clearing WTM1 to 0. In this case, however, the 11-bit prescaler is not cleared. Therefore, an error up to 29 × 1/fW
seconds occurs in the first overflow (INTWT) after zero-second start.
The interrupt request is generated at the following time intervals.
Table 9-4. Watch Timer Interrupt Time
WTM3
WTM2
Interrupt Time When Operated at When Operated at When Operated at When Operated at When Operated at
Selection
fPRS = 20 MHz
(WTM7 = 0)
0.210 s
0.105 s
13
0.25 s
0.52 s
0.210 s
0.105 s
52.5 ms
5
977 μs
2.05 ms
819 μs
410 μs
205 μs
4
488 μs
1.02 ms
410 μs
205 μs
102 μs
1
2 /fW
Remarks 1. fW:
(WTM7 = 0)
0.419 s
0
1
fPRS = 10 MHz
(WTM7 = 0)
1.05 s
2 /fW
1
fPRS = 5 MHz
(WTM7 = 0)
0.5 s
0
0
fPRS = 2 MHz
(WTM7 = 1)
14
0
1
fSUB = 32.768 kHz
2 /fW
2 /fW
7
Watch timer clock frequency (fPRS/2 or fSUB)
2. fPRS: Peripheral hardware clock frequency
3. fSUB: Subsystem clock frequency
9.4.2 Interval timer operation
The watch timer operates as interval timer which generates interrupt request signals (INTWTI) repeatedly at an
interval of the preset count value.
The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register
(WTM).
When bit 0 (WTM0) of the WTM is set to 1, the count operation starts. When this bit is set to 0, the count operation
stops.
Table 9-5. Interval Timer Interval Time
WTM6
WTM5
WTM4
Interval Time
(WTM7 = 0)
5
977 μs
2.05 ms
820 μs
410 μs
205 μs
6
1.95 ms
4.10 ms
1.64 ms
820 μs
410 μs
7
3.91 ms
8.20 ms
3.28 ms
1.64 ms
820 μs
8
7.81 ms
16.4 ms
6.55 ms
3.28 ms
1.64 ms
9
15.6 ms
32.8 ms
13.1 ms
6.55 ms
3.28 ms
10
31.3 ms
65.5 ms
26.2 ms
13.1 ms
6.55 ms
11
62.5 ms
131.1 ms
52.4 ms
26.2 ms
13.1 ms
1
2 /fW
0
1
0
2 /fW
0
1
1
2 /fW
2 /fW
2 /fW
1
1
0
2 /fW
1
1
1
2 /fW
Remarks 1. fW:
(WTM7 = 0)
102 μs
0
1
(WTM7 = 0)
205 μs
0
0
at fPRS = 5 MHz at fPRS = 10 MHz at fPRS = 20 MHz
410 μs
2 /fW
1
(WTM7 = 0)
1.02 ms
0
0
at fPRS = 2 MHz
488 μs
0
0
at fSUB = 32.768
kHz (WTM7 = 1)
4
0
1
When Operated When Operated When Operated When Operated When Operated
7
Watch timer clock frequency (fPRS/2 or fSUB)
2. fPRS: Peripheral hardware clock frequency
3. fSUB: Subsystem clock frequency
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CHAPTER 9 WATCH TIMER
Figure 9-3. Operation Timing of Watch Timer/Interval Timer
5-bit counter
0H
Overflow
Start
Overflow
Count clock
Watch timer
interrupt INTWT
Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s)
Interval timer
interrupt INTWTI
Interval time
(T)
Remark
T
fW: Watch timer clock frequency
Figures in parentheses are for operation with fW = 32.768 kHz (WTM7 = 1, WTM3, WTM2 = 0, 0)
9.5 Cautions for Watch Timer
When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by
setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request signal (INTWT) is
generated after the register is set does not exactly match the specification made with bits 2 and 3 (WTM2, WTM3) of
WTM. Subsequently, however, the INTWT signal is generated at the specified intervals.
Figure 9-4. Example of Generation of Watch Timer Interrupt Request Signal (INTWT)
(When Interrupt Period = 0.5 s)
It takes 0.515625 seconds for the first INTWT to be generated (29 × 1/32768 = 0.015625 s longer).
INTWT is then generated every 0.5 seconds.
WTM0, WTM1
0.515625 s
0.5 s
INTWT
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0.5 s
CHAPTER 10 WATCHDOG TIMER
10.1 Functions of Watchdog Timer
The watchdog timer operates on the internal low-speed oscillation clock.
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset
signal is generated.
Program loop is detected in the following cases.
• If the watchdog timer counter overflows
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
• If data other than “ACH” is written to WDTE
• If data is written to WDTE during a window close period
• If the instruction is fetched from an area not set by the IMS and IXS registers (detection of an invalid check while
the CPU hangs up)
• If the CPU accesses an area that is not set by the IMS and IXS registers (excluding FB00H to FFFFH) by
executing a read/write instruction (detection of an abnormal access during a CPU program loop)
When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1.
For details of RESF, see CHAPTER 20 RESET FUNCTION.
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CHAPTER 10 WATCHDOG TIMER
10.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Table 10-1. Configuration of Watchdog Timer
Item
Configuration
Control register
Watchdog timer enable register (WDTE)
How the counter operation is controlled, overflow time, and window open period are set by the option byte.
Table 10-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer
Option Byte (0080H)
Window open period
Bits 6 and 5 (WINDOW1, WINDOW0)
Controlling counter operation of watchdog timer
Bit 4 (WDTON)
Overflow time of watchdog timer
Bits 3 to 1 (WDCS2 to WDCS0)
Remark
For the option byte, see CHAPTER 23 OPTION BYTE.
Figure 10-1. Block Diagram of Watchdog Timer
CPU access
error detector
CPU access signal
WDCS2 to WDCS0 of
option byte (0080H)
fRL/2
Clock
input
controller
17-bit
counter
210/fRL to
217/fRL
Selector
Count clear
signal
WINDOW1 and WINDOW0
of option byte (0080H)
WDTON of option
byte (0080H)
Overflow
signal
Window size
determination
signal
Clear, reset control
Watchdog timer enable
register (WDTE)
Internal bus
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Reset
output
controller
Internal reset signal
CHAPTER 10 WATCHDOG TIMER
10.3 Register Controlling Watchdog Timer
The watchdog timer is controlled by the watchdog timer enable register (WDTE).
(1) Watchdog timer enable register (WDTE)
Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 9AH or 1AHNote.
Figure 10-2. Format of Watchdog Timer Enable Register (WDTE)
Address: FF99H
Symbol
7
After reset: 9AH/1AHNote
6
R/W
5
4
3
2
1
0
WDTE
Note The WDTE reset value differs depending on the WDTON setting value of the option byte (0080H). To
operate watchdog timer, set WDTON to 1.
WDTON Setting Value
WDTE Reset Value
0 (watchdog timer count operation disabled)
1AH
1 (watchdog timer count operation enabled)
9AH
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If the
source clock to the watchdog timer is stopped, however, an internal reset signal is
generated when the source clock to the watchdog timer resumes operation.
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal
is generated. If the source clock to the watchdog timer is stopped, however, an internal
reset signal is generated when the source clock to the watchdog timer resumes operation.
3. The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)).
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CHAPTER 10 WATCHDOG TIMER
10.4 Operation of Watchdog Timer
10.4.1 Controlling operation of watchdog timer
1.
When the watchdog timer is used, its operation is specified by the option byte (0080H).
• Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1
(the counter starts operating after a reset release) (for details, see CHAPTER 23).
WDTON
Operation Control of Watchdog Timer Counter/Illegal Access Detection
0
Counter operation disabled (counting stopped after reset), illegal access detection operation disabled
1
Counter operation enabled (counting started after reset), illegal access detection operation enabled
• Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H) (for details, see
10.4.2 and CHAPTER 23).
• Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (0080H) (for
details, see 10.4.3 and CHAPTER 23).
2.
After a reset release, the watchdog timer starts counting.
3.
By writing “ACH” to WDTE after the watchdog timer starts counting and before the overflow time set by the
4.
After that, write WDTE the second time or later after a reset release during the window open period. If WDTE
5.
If the overflow time expires without “ACH” written to WDTE, an internal reset signal is generated.
option byte, the watchdog timer is cleared and starts counting again.
is written during a window close period, an internal reset signal is generated.
A internal reset signal is generated in the following cases.
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
• If data other than “ACH” is written to WDTE
• If the instruction is fetched from an area not set by the IMS and IXS registers (detection of an invalid check
during a CPU program loop)
• If the CPU accesses an area not set by the IMS and IXS registers (excluding FB00H to FFFFH) by executing
a read/write instruction (detection of an abnormal access during a CPU program loop)
Cautions 1. The first writing to WDTE after a reset release clears the watchdog timer, if it is made before
the overflow time regardless of the timing of the writing, and the watchdog timer starts
counting again.
2. If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow time may be
different from the overflow time set by the option byte by up to 2/fRL seconds.
3. The watchdog timer can be cleared immediately before the count value overflows (FFFFH).
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CHAPTER 10 WATCHDOG TIMER
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows
depending on the set value of bit 0 (LSROSC) of the option byte.
In HALT mode
LSROSC = 0 (Internal Low-Speed
LSROSC = 1 (Internal Low-Speed
Oscillator Can Be Stopped by Software)
Oscillator Cannot Be Stopped)
Watchdog timer operation stops.
Watchdog timer operation continues.
In STOP mode
If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is not cleared to 0 but starts counting from the value at
which it was stopped.
If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the
internal oscillation mode register (RCM) = 1) when LSROSC = 0, the watchdog timer stops
operating. At this time, the counter is not cleared to 0.
5. The watchdog timer does not stop during self-programming of the flash memory and
EEPROMTM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
10.4.2 Setting overflow time of watchdog timer
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer
starts counting again by writing “ACH” to WDTE during the window open period before the overflow time.
The following overflow time is set.
Table 10-3. Setting of Overflow Time of Watchdog Timer
WDCS2
WDCS1
WDCS0
Overflow Time of Watchdog Timer
10
0
0
0
2 /fRL (3.88 ms)
0
0
1
2 /fRL (7.76 ms)
0
1
0
2 /fRL (15.52 ms)
0
1
1
2 /fRL (31.03 ms)
1
0
0
2 /fRL (62.06 ms)
1
0
1
2 /fRL (124.12 ms)
1
1
0
2 /fRL (248.24 ms)
1
1
1
2 /fRL (496.48 ms)
11
12
13
14
15
16
17
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0
is prohibited.
2. The watchdog timer does not stop during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed.
Set the overflow time and window size taking this delay into consideration.
Remarks 1. fRL: Internal low-speed oscillation clock frequency
2. ( ): fRL = 264 kHz (MAX.)
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CHAPTER 10 WATCHDOG TIMER
10.4.3 Setting window open period of watchdog timer
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option
byte (0080H). The outline of the window is as follows.
• If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting
again.
• Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal
reset signal is generated.
Example: If the window open period is 25%
Counting
starts
Overflow
time
Window close period (75%)
Internal reset signal is generated
if ACH is written to WDTE.
Window open
period (25%)
Counting starts again when
ACH is written to WDTE.
Caution The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the
overflow time regardless of the timing of the writing, and the watchdog timer starts counting
again.
The window open period to be set is as follows.
Table 10-4. Setting Window Open Period of Watchdog Timer
WINDOW1
WINDOW0
Window Open Period of Watchdog Timer
0
0
25%
0
1
50%
1
0
75%
1
1
100%
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0
is prohibited.
2. The watchdog timer does not stop during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed.
Set the overflow time and window size taking this delay into consideration.
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CHAPTER 10 WATCHDOG TIMER
Remark If the overflow time is set to 210/fRL, the window close time and open time are as follows.
Setting of Window Open Period
25%
50%
75%
100%
Window close time
0 to 3.56 ms
0 to 2.37 ms
0 to 0.119 ms
None
Window open time
3.56 to 3.88 ms
2.37 to 3.88 ms
0.119 to 3.88 ms
0 to 3.88 ms
• Overflow time:
210/fRL (MAX.) = 210/264 kHz (MAX.) = 3.88 ms
• Window close time:
0 to 210/fRL (MIN.) × (1 − 0.25) = 0 to 210/216 kHz (MIN.) × 0.75 = 0 to 3.56 ms
• Window open time:
210/fRL (MIN.) × (1 − 0.25) to 210/fRL (MAX.) = 210/216 kHz (MIN.) × 0.75 to 210/264 kHz (MAX.)
= 3.56 to 3.88 ms
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CHAPTER 11 CLOCK OUTPUT CONTROLLER
11.1 Functions of Clock Output Controller
The clock output controller of 78K0/LE2 is intended for clock output for supply to LCD controller/driver. The clock
selected with the clock output selection register (CKS) is supplied to the LCD controller/driver.
Figure 11-1 shows the block diagram of clock output controller.
Figure 11-1. Block Diagram of Clock Output Controller
fPRS
Prescaler
fPRS/26, fPRS/27
fSUB
Selector
2
Clock
controller
fPCL
LCD controller/driver
PM140
CLOE
CCS3
CCS2
CCS1
CCS0
Port mode register 14
(PM14)
Clock output selection register (CKS)
Internal bus
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CHAPTER 11 CLOCK OUTPUT CONTROLLER
11.2 Configuration of Clock Output Controller
The clock output controller includes the following hardware.
Table 11-1. Configuration of Clock Output Controller
Item
Control registers
Configuration
Clock output selection register (CKS)
Port mode register 14 (PM14)
11.3 Registers Controlling Clock Output Controller
The following two registers are used to control the clock output controller.
• Clock output selection register (CKS)
• Port mode register 14 (PM14)
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CHAPTER 11 CLOCK OUTPUT CONTROLLER
(1) Clock output selection register (CKS)
This register enables/disables the clock output to the LCD controller/driver, and sets the output clock.
CKS is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets CKS to 00H.
Figure 11-2. Format of Clock Output Selection Register (CKS)
Address: FF40H
After reset: 00H
R/W
Symbol
7
6
5
3
2
1
0
CKS
0
0
0
CLOE
CCS3
CCS2
CCS1
CCS0
CLOE
PM140
Specification of enable/disable for clock output
Note
to LCD controller/driver
1
0
Other than above
CCS3
0
Clock output to LCD controller/driver enabled
Clock output to LCD controller/driver disabled
CCS2
1
CCS1
1
CCS0
0
fPRS/2
6
7
0
1
1
1
fPRS/2
1
0
0
0
fSUB
Other than above
Note
PCL output clock selection
fSUB =
fPRS =
fPRS =
32.768 kHz
10 MHz
20 MHz
−
156.25 kHz
312.5 kHz
78.125 kHz
32.768 kHz
156.25 kHz
−
Setting prohibited
Enabling/disabling the PCL clock output is specified by combining the PM140 settings (see 17.3 (7)
Port mode register 14 (PM14)).
Cautions 1. Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
2. Bits 5 to 7 must be set to 0.
Remarks 1. fPRS: Peripheral hardware clock oscillation frequency
2. fSUB: Subsystem clock oscillation frequency
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CHAPTER 11 CLOCK OUTPUT CONTROLLER
(2) Port mode register 14 (PM14)
PM14 controls the clock output to the LCD controller/driver.
Set the PM140 bit to 0 to use this register as the clock output function.
PM14 is set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM14 to FFH.
Figure 11-3. Format of Port Mode Register 14 (PM14)
Address: FF2EH
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM14
1
1
1
1
1
1
1
PM140
PM140
Clock output control to LCD controller/driver
0
Clock output to LCD controller/driver enabled
1
Clock output to LCD controller/driver disabled
11.4 Operations of Clock Output Controller
The clock pulse is output as the following procedure.
Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register
(CKS) (clock pulse output in disabled status).
Set bit 4 (CLOE) of CKS to 1 to enable clock output.
Remark
The clock output controller is designed not to output pulses with a small width during output
enable/disable switching of the clock output. As shown in Figure 11-4, be sure to start output from the
low period of the clock (marked with * in the figure). When stopping output, do so after securing a high
level of the clock.
Figure 11-4. Clock Output Application Example
CLOE
*
*
Clock output
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CHAPTER 12 A/D CONVERTER
12.1 Function of A/D Converter
The A/D converter converts an analog input signal into a digital value, and consists of up to five channels (ANI0 to
ANI4) with a resolution of 10 bits.
The A/D converter has the following function.
• 10-bit resolution A/D conversion
10-bit resolution A/D conversion is carried out repeatedly for one analog input channel selected from ANI0 to
ANI4. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated.
Figure 12-1. Block Diagram of A/D Converter
AVREF
ADCS bit
Selector
Voltage comparator
AVSS
Successive
approximation
register (SAR)
Controller
3
ADS2
ADS1
ADS0
ADPC2 ADPC1 ADPC0
Analog input channel
specification register (ADS)
A/D conversion result
register (ADCR)
5
3
ADCS
FR2
FR1
FR0
LV1
ADCE
A/D converter mode
register (ADM)
A/D port configuration
register (ADPC)
Internal bus
250
LV0
User’s Manual U17734EJ2V0UD
Tap selector
Sample & hold circuit
ANI0/P20
ANI1/P21
ANI2/P22
ANI3/P23
ANI4/P24
AVSS
INTAD
CHAPTER 12 A/D CONVERTER
12.2 Configuration of A/D Converter
The A/D converter includes the following hardware.
(1) ANI0 to ANI4 pins
These are the analog input pins of the 5-channel A/D converter. They input analog signals to be converted into
digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins.
(2) Sample & hold circuit
The sample & hold circuit samples the input voltage of the analog input pin selected by the selector when A/D
conversion is started, and holds the sampled voltage value during A/D conversion.
(3) Series resistor string
The series resistor string is connected between AVREF and AVSS, and generates a voltage to be compared with
the sampled voltage value.
Figure 12-2. Circuit Configuration of Series Resistor String
AVREF
P-ch
ADCS
Series resistor string
AVSS
(4) Voltage comparator
The voltage comparator compares the sampled voltage value and the output voltage of the series resistor string.
(5) Successive approximation register (SAR)
This register converts the result of comparison by the voltage comparator, starting from the most significant bit
(MSB).
When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D
conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR).
(6) 10-bit A/D conversion result register (ADCR)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6
bits are fixed to 0).
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CHAPTER 12 A/D CONVERTER
(7) 8-bit A/D conversion result register (ADCRH)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result.
Caution When data is read from ADCR and ADCRH, a wait cycle is generated. Do not read data from
ADCR and ADCRH when the CPU is operating on the subsystem clock and the peripheral
hardware clock is stopped. For details, see CHAPTER 29 CAUTIONS FOR WAIT.
(8) Controller
This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as
well as starting and stopping of the conversion operation. When A/D conversion has been completed, this
controller generates INTAD.
(9) AVREF pin
This pin inputs an analog power/reference voltage to the A/D converter. Make this pin the same potential as the
VDD pin when port 2 is used as a digital port.
The signal input to ANI0 to ANI4 is converted into a digital signal, based on the voltage applied across AVREF and
AVSS.
(10) AVSS pin
This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the VSS
pin even when the A/D converter is not used.
(11) A/D converter mode register (ADM)
This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the
conversion operation.
(12) A/D port configuration register (ADPC)
This register switches the ANI0/P20 to ANI4/P24 pins to analog input of A/D converter or digital I/O of port.
(13) Analog input channel specification register (ADS)
This register is used to specify the port that inputs the analog voltage to be converted into a digital signal.
(14) Port mode register 2 (PM2)
This register switches the ANI0/P20 to ANI4/P24 pins to input or output.
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12.3 Registers Used in A/D Converter
The A/D converter uses the following six registers.
• A/D converter mode register (ADM)
• A/D port configuration register (ADPC)
• Analog input channel specification register (ADS)
• Port mode register 2 (PM2)
• 10-bit A/D conversion result register (ADCR)
• 8-bit A/D conversion result register (ADCRH)
(1) A/D converter mode register (ADM)
This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
ADM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 12-3. Format of A/D Converter Mode Register (ADM)
Address: FF28H
Symbol
ADM
After reset: 00H
6
ADCS
0
R/W
5
Note 1
FR2
ADCS
4
FR1
Note 1
FR0
2
1
Note 1
LV1
Note 1
LV0
ADCE
A/D conversion operation control
0
Stops conversion operation
1
Enables conversion operation
Comparator operation controlNote 2
ADCE
Notes 1.
3
Note 1
0
Stops comparator operation
1
Enables comparator operation (comparator: 1/2AVREF operation)
For details of FR2 to FR0, LV1, LV0, and A/D conversion, see Table 12-2 A/D Conversion Time
Selection.
2.
The operation of the comparator is controlled by ADCS and ADCE, and it takes 1 μs from operation
start to operation stabilization. Therefore, when ADCS is set to 1 after 1 μs or more has elapsed from
the time ADCE is set to 1, the conversion result at that time has priority over the first conversion
result. Otherwise, ignore data of the first conversion.
Table 12-1. Settings of ADCS and ADCE
ADCS
ADCE
0
0
0
1
A/D Conversion Operation
Stop status (DC power consumption path does not exist)
Conversion waiting mode (comparator: 1/2AVREF operation, only comparator
consumes power)
Note
1
0
Conversion mode (comparator operation stopped
1
1
Conversion mode (comparator: 1/2AVREF operation)
)
Note Ignore data of the first conversion because it is not guaranteed range.
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CHAPTER 12 A/D CONVERTER
Figure 12-4. Timing Chart When Comparator Is Used
Comparator: 1/2AVREF operation
ADCE
Comparator
Conversion
operation
Conversion
waiting
Conversion
operation
Conversion
stopped
ADCS
Note
Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be
1 μs or longer.
Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to values
other than the identical data.
2. If data is written to ADM, a wait cycle is generated. Do not write data to ADM when the CPU is
operating on the subsystem clock and the peripheral hardware clock is stopped. For details,
see CHAPTER 29 CAUTIONS FOR WAIT.
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Table 12-2. A/D Conversion Time Selection
(1) 2.7 V ≤ AVREF ≤ 5.5 V
A/D Converter Mode Register (ADM)
FR2
FR1
FR0
LV1
Conversion Time Selection
LV0
fPRS =
2 MHz
Conversion
Clock (fAD)
fPRS =
fPRS =
Note
10 MHz 20 MHz
Conversion Time Configuration
SAR
Clear
Sampling Successive
ADCR
Conversion Transfer,
Time
INTAD
Generation
0
0
0
0
0
264/fPRS
Setting
26.4 μs
13.2 μs
fPRS/12
Note
0
0
1
0
0
176/fPRS
prohibited 17.6 μs
8.8 μs
fPRS/8
0
1
0
0
0
132/fPRS
13.2 μs
6.6 μs
fPRS/6
Note
Note
0
1
1
0
0
88/fPRS
8.8 μs
Setting
fPRS/4
1
0
0
0
0
66/fPRS
33.0 μs
6.6 μs
prohibited
fPRS/3
1
0
1
0
0
44/fPRS
22.0 μs
Setting
Note
Note
2/fAD
6/fAD
12/fAD
2/fAD
fPRS/2
prohibited
Other than above
Setting prohibited
Note This can be set only when 4.0 V ≤ AVREF ≤ 5.5 V.
(2) 2.3 V ≤ AVREF < 2.7 V
A/D Converter Mode Register (ADM)
FR2
FR1
FR0
LV1
Conversion Time Selection
LV0
fPRS =
2 MHz
Conversion
fPRS =
5 MHz
Clock (fAD)
Conversion Time Configuration
SAR
Clear
Sampling Successive
ADCR
Conversion Transfer,
Time
INTAD
Generation
0
0
0
0
1
480/fPRS
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
160/fPRS
1
0
0
0
1
120/fPRS
60.0 μs
1
0
1
0
1
80/fPRS
40.0 μs
Other than above
Setting
prohibited
Setting
prohibited
fPRS/12
320/fPRS
64.0 μs
fPRS/8
240/fPRS
48.0 μs
fPRS/6
32.0 μs
fPRS/4
Setting
prohibited
fPRS/3
Setting
prohibited
fPRS/2
2/fAD
24/fAD
12/fAD
2/fAD
Setting prohibited
Cautions 1. Set the conversion times with the following conditions.
• 4.0 V ≤ AVREF ≤ 5.5 V: Sampling + successive conversion time = 5 to 30 μs
(fAD = 0.6 to 3.6 MHz)
• 2.7 V ≤ AVREF < 4.0 V: Sampling + successive conversion time = 10 to 30 μs
(fAD = 0.6 to 1.8 MHz)
• 2.3 V ≤ AVREF < 2.7 V: Sampling + successive conversion time = 25 to 62 μs
(fAD = 0.6 to 1.48 MHz)
2. When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
3. Change LV1 and LV0 from the default value, when 2.3 V ≤ AVREF < 2.7 V.
4. The above conversion time does not include clock frequency errors. Select conversion time,
taking clock frequency errors into consideration.
Remark
fPRS: Peripheral hardware clock frequency
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Figure 12-5. A/D Converter Sampling and A/D Conversion Timing
ADCS ← 1 or ADS rewrite
ADCS
Sampling
timing
INTAD
Wait
periodNote
SAR
clear
Sampling time
Successive
conversion time
Sampling time
Transfer SAR
to ADCR, clear
INTAD
generation
Conversion time
Conversion time
Note For details of wait period, see CHAPTER 29 CAUTIONS FOR WAIT.
(2) 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time
A/D conversion ends, the conversion result is loaded from the successive approximation register. The higher 8
bits of the conversion result are stored in FF09H and the lower 2 bits are stored in the higher 2 bits of FF08H.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to 0000H.
Figure 12-6. Format of 10-Bit A/D Conversion Result Register (ADCR)
Address: FF08H, FF09H
Symbol
After reset: 0000H
R
FF09H
FF08H
ADCR
0
0
0
0
0
0
Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may
become undefined.
Read the conversion result following conversion completion before
writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect
conversion result to be read.
2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 29 CAUTIONS FOR WAIT.
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(3) 8-bit A/D conversion result register (ADCRH)
This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are
stored.
ADCRH can be read by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 12-7. Format of 8-Bit A/D Conversion Result Register (ADCRH)
Address: FF09H
Symbol
After reset: 00H
7
6
R
5
4
3
2
1
0
ADCRH
Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of ADCRH may
become undefined.
Read the conversion result following conversion completion before
writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect
conversion result to be read.
2. If data is read from ADCRH, a wait cycle is generated. Do not read data from ADCRH when
the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped.
For details, see CHAPTER 29 CAUTIONS FOR WAIT.
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CHAPTER 12 A/D CONVERTER
(4) Analog input channel specification register (ADS)
This register specifies the input channel of the analog voltage to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 12-8. Format of Analog Input Channel Specification Register (ADS)
Address: FF29H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ADS
0
0
0
0
0
ADS2
ADS1
ADS0
ADS2
ADS1
ADS0
0
0
0
ANI0
0
0
1
ANI1
0
1
0
ANI2
0
1
1
ANI3
0
0
1
Other than above
Analog input channel specification
ANI4
Setting prohibited
Cautions 1. Be sure to clear bits 3 to 7 to 0.
2 Set a channel to be used for A/D conversion in the input mode by using port mode register 2
(PM2).
3. Do not set a pin to be used as a digital I/O pin with ADPC with ADS.
4. If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the CPU is
operating on the subsystem clock and the peripheral hardware clock is stopped. For details,
see CHAPTER 29 CAUTIONS FOR WAIT.
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(5) A/D port configuration register (ADPC)
This register switches the ANI0/P20 to ANI4/P24 pins to analog input of A/D converter or digital I/O of port.
ADPC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 12-9. Format of A/D Port Configuration Register (ADPC)
Address: FF2FH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ADPC
0
0
0
0
0
ADPC2
ADPC1
ADPC0
ADPC2
ADPC1
ADPC0
Analog input (A)/digital input (D) switching
P24/
ANI4
P23/
ANI3
P22/
ANI2
P21/
ANI1
P20/
ANI0
0
0
0
A
A
A
A
A
0
0
1
A
A
A
A
D
0
1
0
A
A
A
D
D
0
1
1
A
A
D
D
D
1
0
0
A
D
D
D
D
1
0
1
D
D
D
D
D
Other than above
Setting prohibited
Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode register 2
(PM2).
2. Do not set a pin to be used as a digital I/O pin with ADPC with ADS.
3. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU
is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 29 CAUTIONS FOR WAIT.
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(6) Port mode register 2 (PM2)
When using the ANI0/P20 to ANI4/P24 pins for analog input port, set PM20 to PM24 to 1. The output latches of
P20 to P24 at this time may be 0 or 1.
If PM20 to PM24 are set to 0, they cannot be used as analog input port pins.
PM2 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 12-10. Format of Port Mode Register 2 (PM2)
Address: FF22H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM2
1
1
1
PM24
PM23
PM22
PM21
PM20
PM2n
P2n pin I/O mode selection (n = 0 to 4)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
ANI0/P20 to ANI4/P24 pins are as shown below depending on the settings of ADPC, ADS, and PM2.
Table 12-3. Setting Functions of ANI0/P20 to ANI4/P24 Pins
ADPC
Analog input selection
PM2
Input mode
Output mode
ADS
Selects ANI.
ANI0/P20 to ANI4/P24 Pin
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
Digital I/O selection
Input mode
Output mode
260
Selects ANI.
Setting prohibited
Does not select ANI.
Digital input
Selects ANI.
Setting prohibited
Does not select ANI.
Digital output
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CHAPTER 12 A/D CONVERTER
12.4 A/D Converter Operations
12.4.1 Basic operations of A/D converter
Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1 to start the operation of the comparator.
Set channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and set
to input mode by using port mode register 2 (PM2).
Set A/D conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM.
Select one channel for A/D conversion using the analog input channel specification register (ADS).
Start the conversion operation by setting bit 7 (ADCS) of ADM to 1.
( to are operations performed by hardware.)
The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
sampled voltage is held until the A/D conversion operation has ended.
Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to
(1/2) AVREF by the tap selector.
The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the
analog input is smaller than (1/2) AVREF, the MSB is reset to 0.
Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series
resistor string voltage tap is selected according to the preset value of bit 9, as described below.
• Bit 9 = 1: (3/4) AVREF
• Bit 9 = 0: (1/4) AVREF
The voltage tap and sampled voltage are compared and bit 8 of SAR is manipulated as follows.
• Analog input voltage ≥ Voltage tap: Bit 8 = 1
• Analog input voltage < Voltage tap: Bit 8 = 0
Comparison is continued in this way up to bit 0 of SAR.
Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result
value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
Repeat steps to , until ADCS is cleared to 0.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from . To start A/D conversion again when
ADCE = 0, set ADCE to 1, wait for 1 μs or longer, and start . To change a channel of A/D conversion,
start from .
Caution Make sure the period of to is 1 μs or more.
Remark
Two types of A/D conversion result registers are available.
• ADCR (16 bits): Store 10-bit A/D conversion value
• ADCRH (8 bits): Store 8-bit A/D conversion value
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Figure 12-11. Basic Operation of A/D Converter
Conversion time
Sampling time
A/D converter
operation
Sampling
A/D conversion
Conversion
result
SAR Undefined
Conversion
result
ADCR
INTAD
A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM)
is reset (0) by software.
If a write operation is performed to the analog input channel specification register (ADS) during an A/D conversion
operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the
beginning.
Reset signal generation sets the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H.
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12.4.2 Input voltage and conversion results
The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI4) and the theoretical
A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following
expression.
SAR = INT (
VAIN
AVREF
× 1024 + 0.5)
ADCR = SAR × 64
or
(
ADCR
64
− 0.5) ×
where, INT( ):
AVREF
1024
≤ VAIN < (
ADCR
64
+ 0.5) ×
AVREF
1024
Function which returns integer part of value in parentheses
VAIN:
Analog input voltage
AVREF:
AVREF pin voltage
ADCR: A/D conversion result register (ADCR) value
SAR:
Successive approximation register
Figure 12-12 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 12-12. Relationship Between Analog Input Voltage and A/D Conversion Result
SAR
ADCR
1023
FFC0H
1022
FF80H
1021
FF40H
3
00C0H
2
0080H
1
0040H
A/D conversion result
0
0000H
1
1
3
2
5
3
2048 1024 2048 1024 2048 1024
2043 1022 2045 1023 2047 1
2048 1024 2048 1024 2048
Input voltage/AVREF
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12.4.3 A/D converter operation mode
The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to
ANI4 by the analog input channel specification register (ADS) and A/D conversion is executed.
(1) A/D conversion operation
By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the
voltage, which is applied to the analog input pin specified by the analog input channel specification register
(ADS), is started.
When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result
register (ADCR), and an interrupt request signal (INTAD) is generated. When one A/D conversion has been
completed, the next A/D conversion operation is immediately started.
If ADS is rewritten during A/D conversion, the A/D conversion operation under execution is stopped and restarted
from the beginning.
If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped.
At this time, the
conversion result immediately before is retained.
Figure 12-13. A/D Conversion Operation
Rewriting ADM
ADCS = 1
A/D conversion
ANIn
Rewriting ADS
ANIn
ANIn
ADCS = 0
ANIm
ANIm
Conversion is stopped
Conversion result immediately
before is retained
ANIn
ADCR,
ADCRH
ANIn
INTAD
Remarks 1. n = 0 to 4
2. m = 0 to 4
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Stopped
Conversion result
immediately before
is retained
ANIm
CHAPTER 12 A/D CONVERTER
The setting methods are described below.
Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.
Set the channel to be used in the analog input mode by using bits 2 to 0 (ADPC2 to ADPC0) of the A/D
port configuration register (ADPC) and bits 4 to 0 (PM24 to PM20) of port mode register 2 (PM2).
Select conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM.
Select a channel to be used by using bits 2 to 0 (ADS2 to ADS0) of the analog input channel
specification register (ADS).
Set bit 7 (ADCS) of ADM to 1 to start A/D conversion.
When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
Change the channel using bits 2 to 0 (ADS2 to ADS0) of ADS to start A/D conversion.
When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
Clear ADCS to 0.
Clear ADCE to 0.
Cautions 1. Make sure the period of to is 1 μs or more.
2. may be done between and .
3. can be omitted. However, ignore data of the first conversion after in this case.
4. The period from to differs from the conversion time set using bits 5 to 1 (FR2 to
FR0, LV1, LV0) of ADM. The period from to is the conversion time set using FR2
to FR0, LV1, and LV0.
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12.5 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained.
(1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input
voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the
full scale is expressed by %FSR (Full Scale Range).
1LSB is as follows when the resolution is 10 bits.
1LSB = 1/210 = 1/1024
= 0.098%FSR
Accuracy has no relation to resolution, but is determined by overall error.
(2) Overall error
This shows the maximum error value between the actual measured value and the theoretical value.
Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of
these express the overall error.
Note that the quantization error is not included in the overall error in the characteristics table.
(3) Quantization error
When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an
analog input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot
be avoided.
Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral
linearity error, and differential linearity error in the characteristics table.
Figure 12-14. Overall Error
Figure 12-15. Quantization Error
1……1
1……1
Overall
error
Digital output
Digital output
Ideal line
1/2LSB
Quantization error
1/2LSB
0……0
AVREF
0
0……0
Analog input
0
Analog input
AVREF
(4) Zero-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (1/2LSB) when the digital output changes from 0......000 to 0......001.
If the actual measurement value is greater than the theoretical value, it shows the difference between the actual
measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output
changes from 0……001 to 0……010.
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(5) Full-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111.
(6) Integral linearity error
This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It
expresses the maximum value of the difference between the actual measurement value and the ideal straight line
when the zero-scale error and full-scale error are 0.
(7) Differential linearity error
While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value
and the ideal value.
Figure 12-16. Zero-Scale Error
Figure 12-17. Full-Scale Error
Full-scale error
Digital output (Lower 3 bits)
Digital output (Lower 3 bits)
111
Ideal line
011
010
001
Zero-scale error
000
111
110
101
Ideal line
000
0
1
2
3
AVREF
AVREF−3
0
Analog input (LSB)
AVREF−2
AVREF−1
AVREF
Analog input (LSB)
Figure 12-18. Integral Linearity Error
Figure 12-19. Differential Linearity Error
1……1
1……1
Ideal 1LSB width
Digital output
Digital output
Ideal line
Differential
linearity error
Integral linearity
error
0……0
0
Analog input
0……0
0
AVREF
Analog input
AVREF
(8) Conversion time
This expresses the time from the start of sampling to when the digital output is obtained.
The sampling time is included in the conversion time in the characteristics table.
(9) Sampling time
This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling
time
Conversion time
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12.6 Cautions for A/D Converter
(1) Operating current in STOP mode
The A/D converter stops operating in the STOP mode. At this time, the operating current can be reduced by
clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0.
To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start
operation.
(2) Input range of ANI0 to ANI4
Observe the rated range of the ANI0 to ANI4 input voltage. If a voltage of AVREF or higher and AVSS or lower
(even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that
channel becomes undefined. In addition, the converted values of the other channels may also be affected.
(3) Conflicting operations
Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR or ADCRH read by
instruction upon the end of conversion
ADCR or ADCRH read has priority. After the read operation, the new conversion result is written to ADCR
or ADCRH.
Conflict between ADCR or ADCRH write and A/D converter mode register (ADM) write, analog input
channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end of
conversion
ADM, ADS, or ADPC write has priority. ADCR or ADCRH write is not performed, nor is the conversion end
interrupt signal (INTAD) generated.
(4) Noise countermeasures
To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and pins ANI0 to ANI4.
Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply.
The higher the output impedance of the analog input source, the greater the influence. To reduce the
noise, connecting external C as shown in Figure 12-20 is recommended.
Do not switch these pins with other pins during conversion.
The accuracy is improved if the HALT mode is set immediately after the start of conversion.
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Figure 12-20. Analog Input Pin Connection
If there is a possibility that noise equal to or higher than AVREF or
equal to or lower than AVSS may enter, clamp with a diode with a
small VF value (0.3 V or lower).
Reference
voltage
input
AVREF
ANI0 to ANI4
C = 100 to 1,000 pF
AVSS
VSS
(5) ANI0/P20 to ANI4/P24
The analog input pins (ANI0 to ANI4) are also used as input port pins (P20 to P24).
When A/D conversion is performed with any of ANI0 to ANI4 selected, do not access P20 to P24 while
conversion is in progress; otherwise the conversion resolution may be degraded. It is recommended to
select pins used as P20 to P24 starting with the ANI0/P20 that is the furthest from AVREF.
If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected
value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to
the pins adjacent to the pin undergoing A/D conversion.
(6) Input impedance of ANI0 to ANI4 pins
This A/D converter charges a sampling capacitor for sampling during sampling time.
Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the
capacitor flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling
is in progress, and on the other states.
To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog
input source to within 10 kΩ, and to connect a capacitor of about 100 pF to the ANI0 to ANI4 pins (see Figure 1220).
(7) AVREF pin input impedance
A series resistor string of several tens of kΩ is connected between the AVREF and AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to
the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error.
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CHAPTER 12 A/D CONVERTER
(8) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the
pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time,
when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the postchange analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.
Figure 12-21. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite
(start of ANIn conversion)
A/D conversion
ADCR
ANIn
ADS rewrite
(start of ANIm conversion)
ANIn
ANIn
ADIF is set but ANIm conversion
has not ended.
ANIm
ANIn
ANIm
ANIm
ANIm
ADIF
Remarks 1. n = 0 to 4
2. m = 0 to 4
(9) Conversion results just after A/D conversion start
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the
ADCS bit is set to 1 within 1 μs after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit =
0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first
conversion result.
(10) A/D conversion result register (ADCR, ADCRH) read operation
When a write operation is performed to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR and ADCRH may
become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and
ADPC. Using a timing other than the above may cause an incorrect conversion result to be read.
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(11) Internal equivalent circuit
The equivalent circuit of the analog input block is shown below.
Figure 12-22. Internal Equivalent Circuit of ANIn Pin
R1
ANIn
C1
C2
Table 12-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values)
AVREF
R1
C1
C2
4.0 V ≤ AVREF ≤ 5.5 V
8.1 kΩ
8 pF
5 pF
2.7 V ≤ AVREF < 4.0 V
31 kΩ
8 pF
5 pF
2.3 V ≤ AVREF < 2.7 V
381 kΩ
8 pF
5 pF
Remarks 1. The resistance and capacitance values shown in Table 12-4 are not guaranteed values.
2. n = 0 to 4
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CHAPTER 13 SERIAL INTERFACE UART0
13.1 Functions of Serial Interface UART0
Serial interface UART0 has the following two modes.
(1) Operation stop mode
This mode is used when serial communication is not executed and can enable a reduction in the power
consumption.
For details, see 13.4.1 Operation stop mode.
(2) Asynchronous serial interface (UART) mode
The functions of this mode are outlined below.
For details, see 13.4.2
Asynchronous serial interface (UART) mode and 13.4.3
Dedicated baud rate
generator.
• Maximum transfer rate: 312.5 kbps
• Two-pin configuration
TXD0: Transmit data output pin
RXD0: Receive data input pin
• Length of communication data can be selected from 7 or 8 bits.
• Dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set
• Transmission and reception can be performed independently (full-duplex operation).
• Fixed to LSB-first communication
Cautions 1. If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal
operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP
mode), each register stops operating, and holds the value immediately before clock supply
was stopped. The TXD0 pin also holds the value immediately before clock supply was
stopped and outputs it. However, the operation is not guaranteed after clock supply is
resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0.
2. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start
communication.
3. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0.
To enable
transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock
after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base
clock, the transmission circuit or reception circuit may not be initialized.
4. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1.
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13.2 Configuration of Serial Interface UART0
Serial interface UART0 includes the following hardware.
Table 13-1. Configuration of Serial Interface UART0
Item
Registers
Configuration
Receive buffer register 0 (RXB0)
Receive shift register 0 (RXS0)
Transmit shift register 0 (TXS0)
Control registers
Asynchronous serial interface operation mode register 0 (ASIM0)
Asynchronous serial interface reception error status register 0 (ASIS0)
Baud rate generator control register 0 (BRGC0)
Port mode register 1 (PM1)
Port register 1 (P1)
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274
Figure 13-1. Block Diagram of Serial Interface UART0
Filter
RXD0/
SI10/P11
Receive shift register 0
(RXS0)
Asynchronous serial
interface operation mode
register 0 (ASIM0)
fPRS/23
Baud rate
generator
User’s Manual U17734EJ2V0UD
INTSR0
Reception control
Receive buffer register 0
(RXB0)
INTST0
Transmission control
Transmit shift register 0
(TXS0)
Reception unit
Internal bus
8-bit timer/
event counter
50 output
Baud rate generator
control register 0
(BRGC0)
7
Baud rate
generator
7
TXD0/
SCK10/P10
Output latch
(P10)
Registers
Transmission unit
PM10
CHAPTER 13 SERIAL INTERFACE UART0
fPRS/25
Asynchronous serial
interface reception error
status register 0 (ASIS0)
Selector
fPRS/2
CHAPTER 13 SERIAL INTERFACE UART0
(1) Receive buffer register 0 (RXB0)
This 8-bit register stores parallel data converted by receive shift register 0 (RXS0).
Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift
register 0 (RXS0).
If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is
always 0.
If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0.
RXB0 can be read by an 8-bit memory manipulation instruction. No data can be written to this register.
Reset signal generation and POWER0 = 0 set this register to FFH.
(2) Receive shift register 0 (RXS0)
This register converts the serial data input to the RXD0 pin into parallel data.
RXS0 cannot be directly manipulated by a program.
(3) Transmit shift register 0 (TXS0)
This register is used to set transmit data. Transmission is started when data is written to TXS0, and serial data is
transmitted from the TXD0 pins.
TXS0 can be written by an 8-bit memory manipulation instruction. This register cannot be read.
Reset signal generation, POWER0 = 0, and TXE0 = 0 set this register to FFH.
Cautions 1. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1.
2. Do not write the next transmit data to TXS0 before the transmission completion interrupt
signal (INTST0) is generated.
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13.3 Registers Controlling Serial Interface UART0
Serial interface UART0 is controlled by the following five registers.
• Asynchronous serial interface operation mode register 0 (ASIM0)
• Asynchronous serial interface reception error status register 0 (ASIS0)
• Baud rate generator control register 0 (BRGC0)
• Port mode register 1 (PM1)
• Port register 1 (P1)
(1) Asynchronous serial interface operation mode register 0 (ASIM0)
This 8-bit register controls the serial communication operations of serial interface UART0.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Figure 13-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2)
Address: FF70H After reset: 01H R/W
Symbol
4
3
2
1
0
ASIM0
POWER0
TXE0
RXE0
PS01
PS00
CL0
SL0
1
POWER0
0
Note 1
Enables/disables operation of internal operation clock
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit
1
Enables/disables transmission
0
Disables transmission (synchronously resets the transmission circuit).
1
Enables transmission.
RXE0
2.
.
Enables operation of the internal operation clock.
TXE0
Notes 1.
Note 2
Enables/disables reception
0
Disables reception (synchronously resets the reception circuit).
1
Enables reception.
The input from the RXD0 pin is fixed to high level when POWER0 = 0.
Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0),
and receive buffer register 0 (RXB0) are reset.
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Figure 13-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2)
PS01
PS00
Transmission operation
0
0
Does not output parity bit.
Reception without parity
0
1
Outputs 0 parity.
Reception as 0 parity
1
0
Outputs odd parity.
Judges as odd parity.
1
1
Outputs even parity.
Judges as even parity.
CL0
Reception operation
Note
Specifies character length of transmit/receive data
0
Character length of data = 7 bits
1
Character length of data = 8 bits
SL0
Specifies number of stop bits of transmit data
0
Number of stop bits = 1
1
Number of stop bits = 2
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial
interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur.
Cautions 1. To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the transmission,
clear TXE0 to 0, and then clear POWER0 to 0.
2. To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the reception, clear
RXE0 to 0, and then clear POWER0 to 0.
3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If
POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started.
4. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0.
To enable
transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after
TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock,
the transmission circuit or reception circuit may not be initialized.
5. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1.
6. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.
7. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with
“number of stop bits = 1”, and therefore, is not affected by the set value of the SL0 bit.
8. Be sure to set bit 0 to 1.
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(2) Asynchronous serial interface reception error status register 0 (ASIS0)
This register indicates an error status on completion of reception by serial interface UART0. It includes three
error flag bits (PE0, FE0, OVE0).
This register is read-only by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0. 00H is read
when this register is read. If a reception error occurs, read ASIS0 and then read receive buffer register 0 (RXB0)
to clear the error flag.
Figure 13-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0)
Address: FF73H After reset: 00H R
Symbol
7
6
5
4
3
2
1
0
ASIS0
0
0
0
0
0
PE0
FE0
OVE0
PE0
Status flag indicating parity error
0
If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
1
If the parity of transmit data does not match the parity bit on completion of reception.
FE0
Status flag indicating framing error
0
If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
1
If the stop bit is not detected on completion of reception.
OVE0
Status flag indicating overrun error
0
If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
1
If receive data is set to the RXB0 register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of
asynchronous serial interface operation mode register 0 (ASIM0).
2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of
stop bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 0
(RXB0) but discarded.
4. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 29 CAUTIONS FOR WAIT.
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CHAPTER 13 SERIAL INTERFACE UART0
(3) Baud rate generator control register 0 (BRGC0)
This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter.
BRGC0 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 1FH.
Figure 13-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
Address: FF71H After reset: 1FH R/W
Symbol
7
6
5
4
3
2
1
0
BRGC0
TPS01
TPS00
0
MDL04
MDL03
MDL02
MDL01
MDL00
TPS01
TPS00
Base clock (fXCLK0) selection
fPRS = 2 MHz
0
0
TM50 output
0
1
fPRS/2
1
0
fPRS = 5 MHz
fPRS = 10 MHz
fPRS = 20 MHz
Note
1 MHz
2.5 MHz
5 MHz
10 MHz
fPRS/2
3
250 kHz
625 kHz
1.25 MHz
2.5 MHz
fPRS/2
5
62.5 kHz
156.25 kHz
312.5 kHz
625 kHz
1
1
MDL04
MDL03
MDL02
MDL01
MDL00
k
0
0
×
×
×
×
Setting prohibited
0
1
0
0
0
8
fXCLK0/8
0
1
0
0
1
9
fXCLK0/9
0
1
0
1
0
10
fXCLK0/10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
0
1
0
26
fXCLK0/26
1
1
0
1
1
27
fXCLK0/27
1
1
1
0
0
28
fXCLK0/28
1
1
1
0
1
29
fXCLK0/29
1
1
1
1
0
30
fXCLK0/30
1
1
1
1
1
31
fXCLK0/31
Selection of 5-bit counter
output clock
•
•
•
•
•
Note Note the following points when selecting the TM50 output as the base clock.
• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation
(TMC501 = 1).
• PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
It is not necessary to enable the TO50 pin as a timer output pin in any mode.
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Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the
MDL04 to MDL00 bits.
2. The baud rate value is the output clock of the 5-bit counter divided by 2.
Remarks 1. fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits
2. fPRS:
Peripheral hardware clock frequency
3. k:
Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31)
4. ×:
Don’t care
5. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)
TMC501: Bit 1 of TMC50
(4) Port mode register 1 (PM1)
This register sets port 1 input/output in 1-bit units.
When using the P10/TxD0/SCK10 pin for serial interface data output, clear PM10 to 0 and set the output latch of
P10 to 1.
When using the P11/RxD0/SI10 pin for serial interface data input, set PM11 to 1. The output latch of P11 at this
time may be 0 or 1.
PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 13-5. Format of Port Mode Register 1 (PM1)
Address: FF21H
Symbol
PM1
R/W
7
6
5
4
3
2
1
0
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
PM1n
280
After reset: FFH
P1n pin I/O mode selection (n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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13.4 Operation of Serial Interface UART0
Serial interface UART0 has the following two modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
13.4.1 Operation stop mode
In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the
pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER0,
TXE0, and RXE0) of ASIM0 to 0.
(1) Register used
The operation stop mode is set by asynchronous serial interface operation mode register 0 (ASIM0).
ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Address: FF70H After reset: 01H R/W
Symbol
4
3
2
1
0
ASIM0
POWER0
TXE0
RXE0
PS01
PS00
CL0
SL0
1
POWER0
0
Note 1
Enables/disables operation of internal operation clock
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit
TXE0
0
Notes 1.
2.
.
Enables/disables transmission
Disables transmission (synchronously resets the transmission circuit).
RXE0
0
Note 2
Enables/disables reception
Disables reception (synchronously resets the reception circuit).
The input from the RXD0 pin is fixed to high level when POWER0 = 0.
Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0),
and receive buffer register 0 (RXB0) are reset.
Caution Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode.
To start the communication, set POWER0 to 1, and then set TXE0 or RXE0 to 1.
Remark
To use the RxD0/SI10/P11 and TxD0/SCK10/P10 pins as general-purpose port pins, see CHAPTER 4
PORT FUNCTIONS.
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13.4.2 Asynchronous serial interface (UART) mode
In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed.
A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of
baud rates.
(1) Registers used
• Asynchronous serial interface operation mode register 0 (ASIM0)
• Asynchronous serial interface reception error status register 0 (ASIS0)
• Baud rate generator control register 0 (BRGC0)
• Port mode register 1 (PM1)
• Port register 1 (P1)
The basic procedure of setting an operation in the UART mode is as follows.
Set the BRGC0 register (see Figure 13-4).
Set bits 1 to 4 (SL0, CL0, PS00, and PS01) of the ASIM0 register (see Figure 13-2).
Set bit 7 (POWER0) of the ASIM0 register to 1.
Set bit 6 (TXE0) of the ASIM0 register to 1. → Transmission is enabled.
Set bit 5 (RXE0) of the ASIM0 register to 1. → Reception is enabled.
Write data to the TXS0 register. → Data transmission is started.
Caution Take relationship with the other party of communication when setting the port mode register
and port register.
The relationship between the register settings and pins is shown below.
Table 13-2. Relationship Between Register Settings and Pins
POWER0
0
1
TXE0
0
0
RXE0
PM10
P10
0
×
×
1
×
×
Note
Note
Note
PM11
×
Note
Note
1
0
0
1
1
1
0
1
P11
×
Note
×
1
×
Note
1
UART0
Pin Function
Operation
TxD0/SCK10/P10
RxD0/SI10/P11
Stop
SCK10/P10
SI10/P11
Reception
SCK10/P10
RxD0
Note
Transmission
TxD0
SI10/P11
×
Transmission/
TxD0
RxD0
×
reception
Note Can be set as port function or serial interface CSI10.
Remark
×:
don’t care
POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0)
282
TXE0:
Bit 6 of ASIM0
RXE0:
Bit 5 of ASIM0
PM1×:
Port mode register
P1×:
Port output latch
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CHAPTER 13 SERIAL INTERFACE UART0
(2) Communication operation
(a) Format and waveform example of normal transmit/receive data
Figures 13-6 and 13-7 show the format and waveform example of the normal transmit/receive data.
Figure 13-6. Format of Normal UART Transmit/Receive Data
1 data frame
Start
bit
D0
D1
D2
D3
D4
D5
D6
Parity
bit
D7
Stop bit
Character bits
One data frame consists of the following bits.
• Start bit ... 1 bit
• Character bits ... 7 or 8 bits (LSB first)
• Parity bit ... Even parity, odd parity, 0 parity, or no parity
• Stop bit ... 1 or 2 bits
The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial
interface operation mode register 0 (ASIM0).
Figure 13-7. Example of Normal UART Transmit/Receive Data Waveform
1. Data length: 8 bits, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
2. Data length: 7 bits, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
Parity
Stop
Stop
3. Data length: 8 bits, Parity: None, Stop bit: 1 bit, Communication data: 87H
1 data frame
Start
D0
D1
D2
D3
D4
D5
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D6
D7
Stop
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CHAPTER 13 SERIAL INTERFACE UART0
(b) Parity types and operation
The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used
on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error
can be detected. With zero parity and no parity, an error cannot be detected.
(i)
Even parity
• Transmission
Transmit data, including the parity bit, is controlled so that the number of bits that are “1” is even.
The value of the parity bit is as follows.
If transmit data has an odd number of bits that are “1”: 1
If transmit data has an even number of bits that are “1”: 0
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a
parity error occurs.
(ii) Odd parity
• Transmission
Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that
are “1” is odd.
If transmit data has an odd number of bits that are “1”: 0
If transmit data has an even number of bits that are “1”: 1
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is even, a
parity error occurs.
(iii) 0 parity
The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.
The parity bit is not detected when the data is received. Therefore, a parity error does not occur
regardless of whether the parity bit is “0” or “1”.
(iv) No parity
No parity bit is appended to the transmit data.
Reception is performed assuming that there is no parity bit when data is received. Because there is no
parity bit, a parity error does not occur.
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CHAPTER 13 SERIAL INTERFACE UART0
(c) Transmission
If bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and bit 6
(TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit
data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to
the data.
When transmission is started, the start bit is output from the TXD0 pin, and the transmit data is output
followed by the rest of the data in order starting from the LSB. When transmission is completed, the parity
and stop bits set by ASIM0 are appended and a transmission completion interrupt request (INTST0) is
generated.
Transmission is stopped until the data to be transmitted next is written to TXS0.
Figure 13-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt
occurs as soon as the last stop bit has been output.
Caution After transmit data is written to TXS0, do not write the next transmit data before the
transmission completion interrupt signal (INTST0) is generated.
Figure 13-8. Transmission Completion Interrupt Request Timing
1. Stop bit length: 1
TXD0 (output)
Start
D0
D1
D2
D6
D7
Parity
Start
D0
D1
D2
D6
D7
Parity
Stop
INTST0
2. Stop bit length: 2
TXD0 (output)
Stop
INTST0
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(d) Reception
Reception is enabled and the RXD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial
interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1.
The 5-bit counter of the baud rate generator starts counting when the falling edge of the RXD0 pin input is
detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the
RXD0 pin input is sampled again (
in Figure 13-9). If the RXD0 pin is low level at this time, it is recognized
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift
register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion
interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an
overrun error (OVE0) occurs, however, the receive data is not written to RXB0.
Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception
position of the stop bit, and an reception error interrupt (INTSR0) is generated after completion of reception.
INTSR0 occurs upon completion of reception and in case of a reception error.
Figure 13-9. Reception Completion Interrupt Request Timing
RXD0 (input)
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
INTSR0
RXB0
Cautions 1. If a reception error occurs, read asynchronous serial interface reception error status
register 0 (ASIS0) and then read receive buffer register 0 (RXB0) to clear the error flag.
Otherwise, an overrun error will occur when the next data is received, and the reception
error status will persist.
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit
is ignored.
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(e) Reception error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data
reception, a reception error interrupt (INTSR0) is generated.
Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception
error interrupt (INTSR0) servicing (see Figure 13-3).
The contents of ASIS0 are cleared to 0 when ASIS0 is read.
Table 13-3. Cause of Reception Error
Reception Error
Cause
Parity error
The parity specified for transmission does not match the parity of the receive data.
Framing error
Stop bit is not detected.
Overrun error
Reception of the next data is completed before data is read from receive buffer
register 0 (RXB0).
(f) Noise filter of receive data
The RXD0 signal is sampled using the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 13-10, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
Figure 13-10. Noise Filter Circuit
Base clock
RXD0/SI10/P11
In
Q
Internal signal A
Match detector
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In
Q
Internal signal B
LD_EN
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CHAPTER 13 SERIAL INTERFACE UART0
13.4.3 Dedicated baud rate generator
The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and
generates a serial clock for transmission/reception of UART0.
Separate 5-bit counters are provided for transmission and reception.
(1) Configuration of baud rate generator
• Base clock
The clock selected by bits 7 and 6 (TPS01 and TPS00) of baud rate generator control register 0 (BRGC0) is
supplied to each module when bit 7 (POWER0) of asynchronous serial interface operation mode register 0
(ASIM0) is 1. This clock is called the base clock and its frequency is called fXCLK0. The base clock is fixed
to low level when POWER0 = 0.
• Transmission counter
This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 6 (TXE0) of asynchronous serial
interface operation mode register 0 (ASIM0) is 0.
It starts counting when POWER0 = 1 and TXE0 = 1.
The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (TXS0).
• Reception counter
This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 5 (RXE0) of asynchronous serial
interface operation mode register 0 (ASIM0) is 0.
It starts counting when the start bit has been detected.
The counter stops operation after one frame has been received, until the next start bit is detected.
Figure 13-11. Configuration of Baud Rate Generator
POWER0
Baud rate generator
fPRS/2
POWER0, TXE0 (or RXE0)
fPRS/23
Selector
5-bit counter
fXCLK0
fPRS/25
8-bit timer/
event counter
50 output
Match detector
BRGC0: TPS01, TPS00
Remark
288
1/2
Baud rate
BRGC0: MDL04 to MDL00
POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0)
TXE0:
Bit 6 of ASIM0
RXE0:
Bit 5 of ASIM0
BRGC0:
Baud rate generator control register 0
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CHAPTER 13 SERIAL INTERFACE UART0
(2) Generation of serial clock
A serial clock to be generated can be specified by using baud rate generator control register 0 (BRGC0).
Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0.
Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value (fXCLK0/8 to fXCLK0/31) of the 5-bit
counter.
Table 13-4. Set Value of TPS01 and TPS00
TPS01
TPS00
Base clock (fXCLK0) selection
fPRS = 2 MHz
0
0
TM50 output
0
1
fPRS/2
1
0
1
1
fPRS = 5 MHz
fPRS = 10 MHz
fPRS = 20 MHz
1 MHz
2.5 MHz
5 MHz
10 MHz
fPRS/2
3
250 kHz
625 kHz
1.25 MHz
2.5 MHz
fPRS/2
5
62.5 kHz
156.25 kHz
312.5 kHz
625 kHz
(a) Baud rate
The baud rate can be calculated by the following expression.
• Baud rate =
fXCLK0
2×k
[bps]
fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register
k:
Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31)
(b) Error of baud rate
The baud rate error can be calculated by the following expression.
• Error (%) =
Actual baud rate (baud rate with error)
Desired baud rate (correct baud rate)
− 1 × 100 [%]
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at
the reception destination.
2. Make sure that the baud rate error during reception satisfies the range shown in (4)
Permissible baud rate range during reception.
Example: Frequency of base clock = 2.5 MHz = 2,500,000 Hz
Set value of MDL04 to MDL00 bits of BRGC0 register = 10000B (k = 16)
Target baud rate = 76,800 bps
Baud rate = 2.5 M/(2 × 16)
= 2,500,000/(2 × 16) = 78,125 [bps]
Error = (78,125/76,800 − 1) × 100
= 1.725 [%]
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CHAPTER 13 SERIAL INTERFACE UART0
(3) Example of setting baud rate
Table 13-5. Set Data of Baud Rate Generator
Baud
fPRS = 2.0 MHz
Rate
TPS01,
[bps]
TPS00
4800
2
9600
2
10400
k
fPRS = 5.0 MHz
Calculated ERR TPS01,
Value
[%]
TPS00
26
4808
0.16
3
13
9615
0.16
3
2
12
10417
0.16
19200
1
26
19231
24000
1
21
31250
1
33660
38400
fPRS = 10.0 MHz
Calculated ERR TPS01,
k
k
fPRS = 20.0 MHz
Calculated ERR TPS01,
Calculated ERR
[%]
TPS00
16
4883
1.73
−
−
−
−
−
−
−
−
8
9766
1.73
3
16
9766
1.73
−
−
−
−
2
30
10417
0.16
3
15
10417
0.16
3
30
10417
0.16
0.16
2
16
19531
1.73
3
8
19531
1.73
3
16
19531
1.73
23810
−0.79
2
13
24038
0.16
2
26
24038
0.16
3
13
24038
0.16
16
31250
0
2
10
31250
0
2
20
31250
0
3
10
31250
0
1
15
33333
−0.79
2
9
34722
3.34
2
18
34722
3.34
3
9
34722
3.34
1
13
38462
0.16
2
8
39063
1.73
2
16
39063
1.73
3
8
39063
1.73
Value
[%]
k
Value
TPS00
Value
[%]
56000
1
9
55556
−0.79
1
22
56818
1.46
2
11
56818
1.46
2
22
56818
1.46
62500
1
8
62500
0
1
20
62500
0
2
10
62500
0
2
20
62500
0
76800
−
−
−
−
1
16
78125
1.73
2
8
78125
1.73
2
16
78125
1.73
115200
−
−
−
−
1
11
113636 −1.36
1
22
113636 −1.36
2
11
113636 −1.36
153600
−
−
−
−
1
8
156250
1
16
156250
2
8
156250
Remark
1.73
1.73
TPS01, TPS00: Bits 7 and 6 of baud rate generator control register 0 (BRGC0) (setting of base clock
(fXCLK0))
290
1.73
k:
Value set by the MDL04 to MDL00 bits of BRGC0 (k = 8, 9, 10, ..., 31)
fPRS:
Peripheral hardware clock frequency
ERR:
Baud rate error
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CHAPTER 13 SERIAL INTERFACE UART0
(4) Permissible baud rate range during reception
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
using the calculation expression shown below.
Figure 13-12. Permissible Baud Rate Range During Reception
Latch timing
Data frame length
of UART0
Start bit
Bit 0
Bit 1
Bit 7
Stop bit
Parity bit
FL
1 data frame (11 × FL)
Minimum permissible
data frame length
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmin
Maximum permissible
data frame length
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmax
As shown in Figure 13-12, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
FL = (Brate)−1
Brate: Baud rate of UART0
k:
Set value of BRGC0
FL:
1-bit data length
Margin of latch timing: 2 clocks
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CHAPTER 13 SERIAL INTERFACE UART0
Minimum permissible data frame length: FLmin = 11 × FL −
k−2
2k
× FL =
21k + 2
2k
FL
Therefore, the maximum receivable baud rate at the transmission destination is as follows.
BRmax = (FLmin/11)−1 =
22k
21k + 2
Brate
Similarly, the maximum permissible data frame length can be calculated as follows.
10
11
× FLmax = 11 × FL −
FLmax =
21k – 2
20k
k+2
2×k
× FL =
21k − 2
2×k
FL
FL × 11
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
BRmin = (FLmax/11)−1 =
20k
21k − 2
Brate
The permissible baud rate error between UART0 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Table 13-6. Maximum/Minimum Permissible Baud Rate Error
Division Ratio (k)
Maximum Permissible Baud Rate Error
Minimum Permissible Baud Rate Error
8
+3.53%
−3.61%
16
+4.14%
−4.19%
24
+4.34%
−4.38%
31
+4.44%
−4.47%
Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock
frequency, and division ratio (k). The higher the input clock frequency and the higher the division
ratio (k), the higher the permissible error.
2. k: Set value of BRGC0
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CHAPTER 14 SERIAL INTERFACE UART6
14.1 Functions of Serial Interface UART6
Serial interface UART6 has the following two modes.
(1) Operation stop mode
This mode is used when serial communication is not executed and can enable a reduction in the power
consumption.
For details, see 14.4.1 Operation stop mode.
(2) Asynchronous serial interface (UART) mode
This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below.
For details, see 14.4.2
Asynchronous serial interface (UART) mode and 14.4.3
Dedicated baud rate
generator.
• Maximum transfer rate: 312.5 kbps
• Two-pin configuration
TXD6: Transmit data output pin
RXD6: Receive data input pin
• Data length of communication data can be selected from 7 or 8 bits.
• Dedicated internal 8-bit baud rate generator allowing any baud rate to be set
• Transmission and reception can be performed independently (full duplex operation).
• MSB- or LSB-first communication selectable
• Inverted transmission operation
• Sync break field transmission from 13 to 20 bits
• More than 11 bits can be identified for sync break field reception (SBF reception flag provided).
Cautions 1. The TXD6 output inversion function inverts only the transmission side and not the reception
side. To use this function, the reception side must be ready for reception of inverted data.
2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal
operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP
mode), each register stops operating, and holds the value immediately before clock supply
was stopped. The TXD6 pin also holds the value immediately before clock supply was
stopped and outputs it. However, the operation is not guaranteed after clock supply is
resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0.
3. Set POWER6 = 1 and then set TXE6 = 1 (transmission) or RXE6 = 1 (reception) to start
communication.
4. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6.
To enable
transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock
after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the
base clock, the transmission circuit or reception circuit may not be initialized.
5. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1.
6. If data is continuously transmitted, the communication timing from the stop bit to the next
start bit is extended two operating clocks of the macro. However, this does not affect the
result of communication because the reception side initializes the timing when it has
detected a start bit. Do not use the continuous transmission function if the interface is
incorporated in LIN.
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CHAPTER 14 SERIAL INTERFACE UART6
Remark
LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication
protocol intended to aid the cost reduction of an automotive network.
LIN communication is single-master communication, and up to 15 slaves can be connected to one
master.
The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the
LIN master via the LIN network.
Normally, the LIN master is connected to a network such as CAN (Controller Area Network).
In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that
complies with ISO9141.
In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and
corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave
is ±15% or less.
Figures 14-1 and 14-2 outline the transmission and reception operations of LIN.
Figure 14-1. LIN Transmission Operation
Wakeup
signal frame
Sync
break field
Sync field
Identifier
field
Data field
Data field
Checksum
field
LIN Bus
8 bits
Note 1
13-bitNote 2 SBF
transmission
55H
Data
Data
Data
Data
transmission transmission transmission transmission transmission
TX6
(output)
INTST6Note 3
Notes 1.
2.
The wakeup signal frame is substituted by 80H transmission in the 8-bit mode.
The sync break field is output by hardware. The output width is the bit length set by bits 4 to 2 (SBL62
to SBL60) of asynchronous serial interface control register 6 (ASICL6) (see 14.4.2 (2) (h)
transmission).
3.
Remark
294
INTST6 is output on completion of each transmission. It is also output when SBF is transmitted.
The interval between each field is controlled by software.
User’s Manual U17734EJ2V0UD
SBF
CHAPTER 14 SERIAL INTERFACE UART6
Figure 14-2. LIN Reception Operation
Wakeup
signal frame
Sync
break field
Sync field
Identifier
field
Data field
Data field Checksum
field
13-bit
SBF reception
SF
reception
ID
reception
Data
reception
Data
reception
LIN Bus
RXD6
(input)
Disable
Data
reception
Enable
Reception interrupt
(INTSR6)
Edge detection
(INTP0)
Capture timer
Disable
Enable
Reception processing is as follows.
The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception
mode.
Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has
been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is
output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF
reception error has occurred. The interrupt signal is not output and the SBF reception mode is restored.
If SBF reception has been completed correctly, an interrupt signal is output. Start 16-bit timer/event counter
00 by the SBF reception end interrupt servicing and measure the bit interval (pulse width) of the sync field
(see 6.4.8
Pulse width measurement operation).
Detection of errors OVE6, PE6, and FE6 is
suppressed, and error detection processing of UART communication and data transfer of the shift register
and RXB6 is not performed. The shift register holds the reset value FFH.
Calculate the baud rate error from the bit interval of the sync field, disable UART6 after SF reception, and
then re-set baud rate generator control register 6 (BRGC6).
Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after
reception of the checksum field and to set the SBF reception mode again.
Figure 14-3 shows the port configuration for LIN reception operation.
The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt
(INTP0). The length of the sync field transmitted from the LIN master can be measured using the external event
capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated.
The input source of the reception port input (RXD6) can be input to the external interrupt (INTP0) and 16-bit
timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RXD6 and INTP0/TI000 externally.
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CHAPTER 14 SERIAL INTERFACE UART6
Figure 14-3. Port Configuration for LIN Reception Operation
Selector
P14/RxD6
RXD6 input
Port mode
(PM14)
Output latch
(P14)
Selector
Selector
P120/INTP0
INTP0 input
Port mode
(PM120)
Output latch
(P120)
Port input
switch control
(ISC0)
0: Select INTP0 (P120)
1: Select RxD6 (P14)
Selector
Selector
P00/TI000
TI000 input
Port mode
(PM00)
Output latch
(P00)
Remark
Port input
switch control
(ISC1)
0: Select TI000 (P00)
1: Select RxD6 (P14)
ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 14-11)
The peripheral functions used in the LIN communication operation are shown below.
• External interrupt (INTP0); wakeup signal detection
Use: Detects the wakeup signal edges and detects start of communication.
• 16-bit timer/event counter 00 (TI000); baud rate error detection
Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the
sync field (SF) length and divides it by the number of bits.
• Serial interface UART6
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CHAPTER 14 SERIAL INTERFACE UART6
14.2 Configuration of Serial Interface UART6
Serial interface UART6 includes the following hardware.
Table 14-1. Configuration of Serial Interface UART6
Item
Registers
Configuration
Receive buffer register 6 (RXB6)
Receive shift register 6 (RXS6)
Transmit buffer register 6 (TXB6)
Transmit shift register 6 (TXS6)
Control registers
Asynchronous serial interface operation mode register 6 (ASIM6)
Asynchronous serial interface reception error status register 6 (ASIS6)
Asynchronous serial interface transmission status register 6 (ASIF6)
Clock selection register 6 (CKSR6)
Baud rate generator control register 6 (BRGC6)
Asynchronous serial interface control register 6 (ASICL6)
Input switch control register (ISC)
Port mode register 1 (PM1)
Port register 1 (P1)
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298
Figure 14-4. Block Diagram of Serial Interface UART6
TI000, INTP0Note
Filter
INTSR6
Reception control
INTSRE6
Selector
Asynchronous serial
interface operation mode
register 6 (ASIM6)
Asynchronous serial
interface reception error
status register 6 (ASIS6)
Baud rate
generator
Receive shift register 6
(RXS6)
Asynchronous serial interface
control register 6 (ASICL6)
Receive buffer register 6
(RXB6)
Asynchronous serial interface
control register 6 (ASICL6)
Transmit buffer register 6
(TXB6)
Transmission control
Transmit shift register 6
(TXS6)
Reception unit
Internal bus
Baud rate generator
control register 6
(BRGC6)
8
Asynchronous serial
Clock selection
interface transmission
register 6 (CKSR6) status register 6 (ASIF6)
Baud rate
generator
8
INTST6
TXD6/
P13
Registers
Output latch
(P13)
Transmission unit
Note Selectable with input switch control register (ISC).
PM13
CHAPTER 14 SERIAL INTERFACE UART6
User’s Manual U17734EJ2V0UD
fPRS
fPRS/2
fPRS/22
fPRS/23
fPRS/24
fPRS/25
fPRS/26
fPRS/27
fPRS/28
fPRS/29
fPRS/210
8-bit timer/
event counter
50 output
RXD6/
P14
CHAPTER 14 SERIAL INTERFACE UART6
(1) Receive buffer register 6 (RXB6)
This 8-bit register stores parallel data converted by receive shift register 6 (RXS6).
Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the
data length is set to 7 bits, data is transferred as follows.
• In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0.
• In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0.
If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6.
RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register.
Reset signal generation sets this register to FFH.
(2) Receive shift register 6 (RXS6)
This register converts the serial data input to the RXD6 pin into parallel data.
RXS6 cannot be directly manipulated by a program.
(3) Transmit buffer register 6 (TXB6)
This buffer register is used to set transmit data. Transmission is started when data is written to TXB6.
This register can be read or written by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission
status register 6 (ASIF6) is 1.
2. Do not refresh (write the same value to) TXB6 by software during a communication
operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation
mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1).
3. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1.
(4) Transmit shift register 6 (TXS6)
This register transmits the data transferred from TXB6 from the TXD6 pin as serial data. Data is transferred from
TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one
frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the TXD6
pin at the falling edge of the base clock.
TXS6 cannot be directly manipulated by a program.
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CHAPTER 14 SERIAL INTERFACE UART6
14.3 Registers Controlling Serial Interface UART6
Serial interface UART6 is controlled by the following nine registers.
• Asynchronous serial interface operation mode register 6 (ASIM6)
• Asynchronous serial interface reception error status register 6 (ASIS6)
• Asynchronous serial interface transmission status register 6 (ASIF6)
• Clock selection register 6 (CKSR6)
• Baud rate generator control register 6 (BRGC6)
• Asynchronous serial interface control register 6 (ASICL6)
• Input switch control register (ISC)
• Port mode register 1 (PM1)
• Port register 1 (P1)
(1) Asynchronous serial interface operation mode register 6 (ASIM6)
This 8-bit register controls the serial communication operations of serial interface UART6.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Remark
ASIM6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Figure 14-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)
Address: FF50H After reset: 01H R/W
Symbol
4
3
2
1
0
ASIM6
POWER6
TXE6
RXE6
PS61
PS60
CL6
SL6
ISRM6
POWER6
0
Note 1
Enables/disables operation of internal operation clock
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit
1
Note 2
.
Enables operation of the internal operation clock
TXE6
Enables/disables transmission
0
Disables transmission (synchronously resets the transmission circuit).
1
Enables transmission
RXE6
Notes 1.
Enables/disables reception
0
Disables reception (synchronously resets the reception circuit).
1
Enables reception
The output of the TXD6 pin goes high level and the input from the RXD6 pin is fixed to the high level
when POWER6 = 0 during transmission.
2.
Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
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CHAPTER 14 SERIAL INTERFACE UART6
Figure 14-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)
PS61
PS60
Transmission operation
0
0
Does not output parity bit.
Reception without parity
0
1
Outputs 0 parity.
Reception as 0 parity
1
0
Outputs odd parity.
Judges as odd parity.
1
1
Outputs even parity.
Judges as even parity.
CL6
Note
Specifies character length of transmit/receive data
0
Character length of data = 7 bits
1
Character length of data = 8 bits
SL6
Specifies number of stop bits of transmit data
0
Number of stop bits = 1
1
Number of stop bits = 2
ISRM6
Reception operation
Enables/disables occurrence of reception completion interrupt in case of error
0
“INTSRE6” occurs in case of error (at this time, INTSR6 does not occur).
1
“INTSR6” occurs in case of error (at this time, INTSRE6 does not occur).
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial
interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur.
Cautions 1. To start the transmission, set POWER6 to 1 and then set TXE6 to 1. To stop the transmission,
clear TXE6 to 0, and then clear POWER6 to 0.
2. To start the reception, set POWER6 to 1 and then set RXE6 to 1. To stop the reception, clear
RXE6 to 0, and then clear POWER6 to 0.
3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RXD6 pin. If
POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started.
4. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6.
To enable
transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock
after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the
base clock, the transmission circuit or reception circuit may not be initialized.
5. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1.
6. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
7. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN.
8. Clear TXE6 to 0 before rewriting the SL6 bit.
Reception is always performed with “the
number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.
9. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
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CHAPTER 14 SERIAL INTERFACE UART6
(2) Asynchronous serial interface reception error status register 6 (ASIS6)
This register indicates an error status on completion of reception by serial interface UART6. It includes three
error flag bits (PE6, FE6, OVE6).
This register is read-only by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read
when this register is read. If a reception error occurs, read ASIS6 and then read receive buffer register 6 (RXB6)
to clear the error flag.
Figure 14-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)
Address: FF53H After reset: 00H R
Symbol
7
6
5
4
3
2
1
0
ASIS6
0
0
0
0
0
PE6
FE6
OVE6
PE6
Status flag indicating parity error
0
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1
If the parity of transmit data does not match the parity bit on completion of reception
FE6
Status flag indicating framing error
0
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1
If the stop bit is not detected on completion of reception
OVE6
Status flag indicating overrun error
0
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1
If receive data is set to the RXB6 register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of
asynchronous serial interface operation mode register 6 (ASIM6).
2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop
bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 6
(RXB6) but discarded.
4. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 29 CAUTIONS FOR WAIT.
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CHAPTER 14 SERIAL INTERFACE UART6
(3) Asynchronous serial interface transmission status register 6 (ASIF6)
This register indicates the status of transmission by serial interface UART6. It includes two status flag bits
(TXBF6 and TXSF6).
Transmission can be continued without disruption even during an interrupt period, by writing the next data to the
TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
This register is read-only by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0.
Figure 14-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6)
Address: FF55H After reset: 00H R
Symbol
7
6
5
4
3
2
1
0
ASIF6
0
0
0
0
0
0
TXBF6
TXSF6
TXBF6
Transmit buffer data flag
0
If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6)
1
If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6)
TXSF6
0
Transmit shift register data flag
If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6
(TXB6) after completion of transfer
1
If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress)
Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.
Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte)
to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the
transmit data cannot be guaranteed.
2. To initialize the transmission unit upon completion of continuous transmission, be sure to
check that the TXSF6 flag is “0” after generation of the transmission completion interrupt,
and then execute initialization. If initialization is executed while the TXSF6 flag is “1”, the
transmit data cannot be guaranteed.
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CHAPTER 14 SERIAL INTERFACE UART6
(4) Clock selection register 6 (CKSR6)
This register selects the base clock of serial interface UART6.
CKSR6 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Remark
CKSR6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 =
1).
Figure 14-8. Format of Clock Selection Register 6 (CKSR6)
Address: FF56H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
CKSR6
0
0
0
0
TPS63
TPS62
TPS61
TPS60
TPS63
TPS62
TPS61
TPS60
Base clock (fXCLK6) selection
0
0
0
0
fPRS
0
0
0
1
fPRS/2
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
1
fPRS =
fPRS =
fPRS =
fPRS =
2 MHz
5 MHz
10 MHz
20 MHz
2 MHz
5 MHz
10 MHz
20 MHz
1 MHz
2.5 MHz
5 MHz
10 MHz
fPRS/2
2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
fPRS/2
3
250 kHz
625 kHz
1.25 MHz
2.5 MHz
fPRS/2
4
125 kHz
312.5 kHz 625 kHz
fPRS/2
5
62.5 kHz
156.25 kHz 312.5 kHz 625 kHz
31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
1.25 MHz
0
1
1
0
fPRS/2
6
0
1
1
1
fPRS/2
7
15.625 kHz 39.06 kHz 78.13 kHz 156.25 kHz
fPRS/2
8
7.813 kHz 19.53 kHz 39.06 kHz 78.13 kHz
fPRS/2
9
3.906 kHz 9.77 kHz
19.53 kHz 39.06 kHz
fPRS/2
10
1.953 kHz 4.88 kHz
9.77 kHz
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
1
Other than above
TM50 output
19.53 kHz
Note
Setting prohibited
Note Note the following points when selecting the TM50 output as the base clock.
• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation
(TMC501 = 1).
• PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
It is not necessary to enable the TO50 pin as a timer output pin in any mode.
Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Remarks 1. fPRS: Peripheral hardware clock frequency
2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)
TMC501: Bit 1 of TMC50
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CHAPTER 14 SERIAL INTERFACE UART6
(5) Baud rate generator control register 6 (BRGC6)
This register sets the division value of the 8-bit counter of serial interface UART6.
BRGC6 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Remark
BRGC6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Figure 14-9. Format of Baud Rate Generator Control Register 6 (BRGC6)
Address: FF57H After reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
BRGC6
MDL67
MDL66
MDL65
MDL64
MDL63
MDL62
MDL61
MDL60
MDL67
MDL66
MDL65
MDL64
MDL63
MDL62
MDL61
MDL60
k
Output clock selection of
8-bit counter
0
0
0
0
0
×
×
×
×
Setting prohibited
0
0
0
0
1
0
0
0
8
fXCLK6/8
0
0
0
0
1
0
0
1
9
fXCLK6/9
0
0
0
0
1
0
1
0
10
fXCLK6/10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
0
0
252
fXCLK6/252
1
1
1
1
1
1
0
1
253
fXCLK6/253
1
1
1
1
1
1
1
0
254
fXCLK6/254
1
1
1
1
1
1
1
1
255
fXCLK6/255
Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the
MDL67 to MDL60 bits.
2. The baud rate is the output clock of the 8-bit counter divided by 2.
Remarks 1. fXCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register
2. k: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255)
3. ×: Don’t care
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CHAPTER 14 SERIAL INTERFACE UART6
(6) Asynchronous serial interface control register 6 (ASICL6)
This register controls the serial communication operations of serial interface UART6.
ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 16H.
Caution ASICL6 can be refreshed (the same value is written) by software during a communication
operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5
(RXE6) of ASIM6 = 1). However, do not set both SBRT6 and SBTT6 to 1 by a refresh operation
during SBF reception (SBRT6 = 1) or SBF transmission (until INTST6 occurs since SBTT6 has
been set (1)), because it may re-trigger SBF reception or SBF transmission.
Figure 14-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2)
Address: FF58H After reset: 16H R/W
Note
Symbol
5
4
3
2
1
0
ASICL6
SBRF6
SBRT6
SBTT6
SBL62
SBL61
SBL60
DIR6
TXDLV6
SBRF6
SBF reception status flag
0
If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly
1
SBF reception in progress
SBRT6
SBF reception trigger
−
0
1
SBF reception trigger
SBTT6
SBF transmission trigger
0
−
1
SBF transmission trigger
Note Bit 7 is read-only.
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CHAPTER 14 SERIAL INTERFACE UART6
Figure 14-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2)
SBL62
SBL61
SBL60
SBF transmission output width control
1
0
1
SBF is output with 13-bit length.
1
1
0
SBF is output with 14-bit length.
1
1
1
SBF is output with 15-bit length.
0
0
0
SBF is output with 16-bit length.
0
0
1
SBF is output with 17-bit length.
0
1
0
SBF is output with 18-bit length.
0
1
1
SBF is output with 19-bit length.
1
0
0
SBF is output with 20-bit length.
DIR6
First-bit specification
0
MSB
1
LSB
TXDLV6
Enables/disables inverting TXD6 output
0
Normal output of TXD6
1
Inverted output of TXD6
Cautions 1. In the case of an SBF reception error, the mode returns to the SBF reception mode. The
status of the SBRF6 flag is held (1).
2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1.
After setting the SBRT6 bit to 1, do not clear it to 0 before SBF reception is completed (before
an interrupt request signal is generated).
3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF
reception has been correctly completed.
4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 =
1. After setting the SBTT6 bit to 1, do not clear it to 0 before SBF transmission is completed
(before an interrupt request signal is generated).
5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of
SBF transmission.
6. Do not set the SBRT6 bit to 1 during reception, and do not set the SBTT6 bit to 1 during
transmission.
7. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.
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CHAPTER 14 SERIAL INTERFACE UART6
(7) Input switch control register (ISC)
The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN
(Local Interconnect Network) reception.
The signal input from the P14/RXD6 pin is selected as the input source of INTP0 and TI000 when ISC0 and ISC1
are set to 1.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 14-11. Format of Input Switch Control Register (ISC)
Address: FF4FH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ISC
0
0
0
0
0
0
ISC1
ISC0
ISC1
TI000 input source selection
0
TI000 (P00)
1
RXD6 (P14)
ISC0
INTP0 input source selection
0
INTP0 (P120)
1
RXD6 (P14)
(8) Port mode register 1 (PM1)
This register sets port 1 input/output in 1-bit units.
When using the P13/TXD6 pin for serial interface data output, clear PM13 to 0 and set the output latch of P13 to 1.
When using the P14/RXD6 pin for serial interface data input, set PM14 to 1. The output latch of P14 at this time
may be 0 or 1.
PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 14-12. Format of Port Mode Register 1 (PM1)
Address: FF21H
Symbol
PM1
R/W
7
6
5
4
3
2
1
0
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
PM1n
308
After reset: FFH
P1n pin I/O mode selection (n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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CHAPTER 14 SERIAL INTERFACE UART6
14.4 Operation of Serial Interface UART6
Serial interface UART6 has the following two modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
14.4.1 Operation stop mode
In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In
addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and
5 (POWER6, TXE6, and RXE6) of ASIM6 to 0.
(1) Register used
The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6).
ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Address: FF50H After reset: 01H R/W
Symbol
4
3
2
1
0
ASIM6
POWER6
TXE6
RXE6
PS61
PS60
CL6
SL6
ISRM6
POWER6
0
Note 1
Enables/disables operation of internal operation clock
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit
Note 2
TXE6
0
Enables/disables transmission
Disables transmission operation (synchronously resets the transmission circuit).
RXE6
0
Notes 1.
.
Enables/disables reception
Disables reception (synchronously resets the reception circuit).
The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to high level when
POWER6 = 0 during transmission.
2.
Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to stop the operation.
To start the communication, set POWER6 to 1, and then set TXE6 or RXE6 to 1.
Remark
To use the RXD6/P14 and TXD6/P13 pins as general-purpose port pins, see CHAPTER 4
PORT
FUNCTIONS.
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CHAPTER 14 SERIAL INTERFACE UART6
14.4.2 Asynchronous serial interface (UART) mode
In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be
performed.
A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of
baud rates.
(1) Registers used
• Asynchronous serial interface operation mode register 6 (ASIM6)
• Asynchronous serial interface reception error status register 6 (ASIS6)
• Asynchronous serial interface transmission status register 6 (ASIF6)
• Clock selection register 6 (CKSR6)
• Baud rate generator control register 6 (BRGC6)
• Asynchronous serial interface control register 6 (ASICL6)
• Input switch control register (ISC)
• Port mode register 1 (PM1)
• Port register 1 (P1)
The basic procedure of setting an operation in the UART mode is as follows.
Set the CKSR6 register (see Figure 14-8).
Set the BRGC6 register (see Figure 14-9).
Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 14-5).
Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 14-10).
Set bit 7 (POWER6) of the ASIM6 register to 1.
Set bit 6 (TXE6) of the ASIM6 register to 1. → Transmission is enabled.
Set bit 5 (RXE6) of the ASIM6 register to 1. → Reception is enabled.
Write data to transmit buffer register 6 (TXB6). → Data transmission is started.
Caution Take relationship with the other party of communication when setting the port mode register
and port register.
The relationship between the register settings and pins is shown below.
Table 14-2. Relationship Between Register Settings and Pins
POWER6
TXE6
RXE6
PM13
P13
0
0
0
×
×
1
0
1
×
×
1
0
0
1
1
1
0
1
Note
Note
Note
PM14
×
Note
Note
P14
×
Note
×
1
×
Note
1
×
UART6
Operation
TXD6/P13
Pin Function
Stop
P13
P14
Reception
P13
RXD6
Note
Transmission
TXD6
P14
×
Transmission/
reception
TXD6
RXD6
Note Can be set as port function.
Remark
×:
don’t care
POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)
310
TXE6:
Bit 6 of ASIM6
RXE6:
Bit 5 of ASIM6
PM1×:
Port mode register
P1×:
Port output latch
RXD6/P14
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CHAPTER 14 SERIAL INTERFACE UART6
(2) Communication operation
(a) Format and waveform example of normal transmit/receive data
Figures 14-13 and 14-14 show the format and waveform example of the normal transmit/receive data.
Figure 14-13. Format of Normal UART Transmit/Receive Data
1. LSB-first transmission/reception
1 data frame
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
bit
Stop bit
D1
D0
Parity
bit
Stop bit
Character bits
2. MSB-first transmission/reception
1 data frame
Start
bit
D7
D6
D5
D4
D3
D2
Character bits
One data frame consists of the following bits.
• Start bit ... 1 bit
• Character bits ... 7 or 8 bits
• Parity bit ... Even parity, odd parity, 0 parity, or no parity
• Stop bit ... 1 or 2 bits
The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial
interface operation mode register 6 (ASIM6).
Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial
interface control register 6 (ASICL6).
Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6.
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CHAPTER 14 SERIAL INTERFACE UART6
Figure 14-14. Example of Normal UART Transmit/Receive Data Waveform
1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H
1 data frame
Start
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Stop
3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6 pin
inverted output
1 data frame
Start
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Stop
4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
Parity
Stop
5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H
1 data frame
Start
312
D0
D1
D2
D3
D4
D5
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D6
D7
Stop
Stop
CHAPTER 14 SERIAL INTERFACE UART6
(b) Parity types and operation
The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used
on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error
can be detected. With zero parity and no parity, an error cannot be detected.
Caution Fix the PS61 and PS60 bits to 0 when the device is incorporated in LIN.
(i)
Even parity
• Transmission
Transmit data, including the parity bit, is controlled so that the number of bits that are “1” is even.
The value of the parity bit is as follows.
If transmit data has an odd number of bits that are “1”: 1
If transmit data has an even number of bits that are “1”: 0
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a
parity error occurs.
(ii) Odd parity
• Transmission
Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that
are “1” is odd.
If transmit data has an odd number of bits that are “1”: 0
If transmit data has an even number of bits that are “1”: 1
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is even, a
parity error occurs.
(iii) 0 parity
The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.
The parity bit is not detected when the data is received. Therefore, a parity error does not occur
regardless of whether the parity bit is “0” or “1”.
(iv) No parity
No parity bit is appended to the transmit data.
Reception is performed assuming that there is no parity bit when data is received. Because there is no
parity bit, a parity error does not occur.
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CHAPTER 14 SERIAL INTERFACE UART6
(c) Normal transmission
When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and bit
6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit
data to transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to
the data.
When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that,
the transmit data is sequentially output from TXS6 to the TXD6 pin. When transmission is completed, the
parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is
generated.
Transmission is stopped until the data to be transmitted next is written to TXB6.
Figure 14-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt
occurs as soon as the last stop bit has been output.
Figure 14-15. Normal Transmission Completion Interrupt Request Timing
1. Stop bit length: 1
TXD6 (output)
Start
D0
D1
D2
D6
D7
Parity
Start
D0
D1
D2
D6
D7
Parity
Stop
INTST6
2. Stop bit length: 2
TXD6 (output)
INTST6
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CHAPTER 14 SERIAL INTERFACE UART6
(d) Continuous transmission
The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6
(TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after
transmission of one data frame, data can be continuously transmitted and an efficient communication rate
can be realized. In addition, the TXB6 register can be efficiently written twice (2 bytes) without having to wait
for the transmission time of one data frame, by reading bit 0 (TXSF6) of asynchronous serial interface
transmission status register 6 (ASIF6) when the transmission completion interrupt has occurred.
To transmit data continuously, be sure to reference the ASIF6 register to check the transmission status and
whether the TXB6 register can be written, and then write the data.
Cautions 1. The TXBF6 and TXSF6 flags of the ASIF6 register change from “10” to “11”, and to “01”
during continuous transmission.
To check the status, therefore, do not use a
combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag
when executing continuous transmission.
2. When the device is incorporated in a LIN, the continuous transmission function cannot
be used. Make sure that asynchronous serial interface transmission status register 6
(ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6).
TXBF6
Writing to TXB6 Register
0
Writing enabled
1
Writing disabled
Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.
Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte)
to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the
transmit data cannot be guaranteed.
The communication status can be checked using the TXSF6 flag.
TXSF6
Transmission Status
0
Transmission is completed.
1
Transmission is in progress.
Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure
to check that the TXSF6 flag is “0” after generation of the transmission completion
interrupt, and then execute initialization. If initialization is executed while the TXSF6
flag is “1”, the transmit data cannot be guaranteed.
2. During continuous transmission, the next transmission may complete before execution
of INTST6 interrupt servicing after transmission of one data frame.
As a
countermeasure, detection can be performed by developing a program that can count
the number of transmit data and by referencing the TXSF6 flag.
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CHAPTER 14 SERIAL INTERFACE UART6
Figure 14-16 shows an example of the continuous transmission processing flow.
Figure 14-16. Example of Continuous Transmission Processing Flow
Set registers.
Write TXB6.
Transfer
executed necessary
number of times?
Yes
No
Read ASIF6
TXBF6 = 0?
No
Yes
Write TXB6.
Transmission
completion interrupt
occurs?
No
Yes
Transfer
executed necessary
number of times?
Yes
No
Read ASIF6
TXSF6 = 0?
Yes
Yes of
Completion
transmission processing
Remark
TXB6:
Transmit buffer register 6
ASIF6: Asynchronous serial interface transmission status register 6
TXBF6: Bit 1 of ASIF6 (transmit buffer data flag)
TXSF6: Bit 0 of ASIF6 (transmit shift register data flag)
316
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CHAPTER 14 SERIAL INTERFACE UART6
Figure 14-17 shows the timing of starting continuous transmission, and Figure 14-18 shows the timing of
ending continuous transmission.
Figure 14-17. Timing of Starting Continuous Transmission
Start
TXD6
Data (1)
Parity
Stop
Start
Data (2)
Parity
Stop
Start
INTST6
TXB6
FF
TXS6
FF
Data (1)
Data (2)
Data (1)
Data (3)
Data (2)
Data (3)
TXBF6
Note
TXSF6
Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether
writing is enabled using only the TXBF6 bit.
Remark
TXD6:
TXD6 pin (output)
INTST6: Interrupt request signal
TXB6:
Transmit buffer register 6
TXS6:
Transmit shift register 6
ASIF6:
Asynchronous serial interface transmission status register 6
TXBF6: Bit 1 of ASIF6
TXSF6: Bit 0 of ASIF6
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CHAPTER 14 SERIAL INTERFACE UART6
Figure 14-18. Timing of Ending Continuous Transmission
TXD6
Stop
Start
Data (n − 1)
Parity
Stop
Start
Data (n)
Parity
Stop
INTST6
TXB6
Data (n − 1)
Data (n)
Data (n − 1)
TXS6
Data (n)
TXBF6
TXSF6
POWER6 or TXE6
Remark
TXD6:
TXD6 pin (output)
INTST6:
Interrupt request signal
TXB6:
Transmit buffer register 6
TXS6:
Transmit shift register 6
ASIF6:
Asynchronous serial interface transmission status register 6
TXBF6:
Bit 1 of ASIF6
TXSF6:
Bit 0 of ASIF6
POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6)
TXE6:
318
Bit 6 of asynchronous serial interface operation mode register (ASIM6)
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CHAPTER 14 SERIAL INTERFACE UART6
(e) Normal reception
Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial
interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is
detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the
RXD6 pin input is sampled again (
in Figure 14-19). If the RXD6 pin is low level at this time, it is recognized
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift
register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt
(INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun
error (OVE6) occurs, however, the receive data is not written to RXB6.
Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception
position of the stop bit, and a reception error interrupt (INTSR6/INTSRE6) is generated on completion of
reception.
Figure 14-19. Reception Completion Interrupt Request Timing
RXD6 (input)
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
INTSR6
RXB6
Cautions 1. If a reception error occurs, read ASIS6 and then RXB6 to clear the error flag. Otherwise,
an overrun error will occur when the next data is received, and the reception error
status will persist.
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit
is ignored.
3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6)
before reading RXB6.
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CHAPTER 14 SERIAL INTERFACE UART6
(f) Reception error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data
reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception
error interrupt (INTSR6/INTSRE6) servicing (see Figure 14-6).
The contents of ASIS6 are cleared to 0 when ASIS6 is read.
Table 14-3. Cause of Reception Error
Reception Error
Cause
Parity error
The parity specified for transmission does not match the parity of the receive data.
Framing error
Stop bit is not detected.
Overrun error
Reception of the next data is completed before data is read from receive buffer
register 6 (RXB6).
The reception error interrupt can be separated into reception completion interrupt (INTSR6) and error
interrupt (INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6
(ASIM6) to 0.
Figure 14-20. Reception Error Interrupt
1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are
separated)
(a) No error during reception
(b) Error during reception
INTSR6
INTSR6
INTSRE6
INTSRE6
2. If ISRM6 is set to 1 (error interrupt is included in INTSR6)
(a) No error during reception
320
(b) Error during reception
INTSR6
INTSR6
INTSRE6
INTSRE6
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CHAPTER 14 SERIAL INTERFACE UART6
(g) Noise filter of receive data
The RXD6 signal is sampled with the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 14-21, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
Figure 14-21. Noise Filter Circuit
Base clock
RXD6/P14
In
Internal signal A
Q
In
Internal signal B
Q
LD_EN
Match detector
(h) SBF transmission
When the device is incorporated in LIN, the SBF (Synchronous Break Field) transmission control function is
used for transmission.
For the transmission operation of LIN, see Figure 14-1
LIN Transmission
Operation.
When bit 7 (POWER6) of asynchronous serial interface mode register 6 (ASIM6) is set to 1, the TXD6 pin
outputs high level. Next, when bit 6 (TXE6) of ASIM6 is set to 1, the transmission enabled status is entered,
and SBF transmission is started by setting bit 5 (SBTT6) of asynchronous serial interface control register 6
(ASICL6) to 1.
Thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of ASICL6) is output. Following
the end of SBF transmission, the transmission completion interrupt request (INTST6) is generated and
SBTT6 is automatically cleared. Thereafter, the normal transmission mode is restored.
Transmission is suspended until the data to be transmitted next is written to transmit buffer register 6 (TXB6),
or until SBTT6 is set to 1.
Figure 14-22. SBF Transmission
1
TXD6
2
3
4
5
6
7
8
9
10
11
12
13
Stop
INTST6
SBTT6
Remark
TXD6:
TXD6 pin (output)
INTST6: Transmission completion interrupt request
SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6)
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CHAPTER 14 SERIAL INTERFACE UART6
(i)
SBF reception
When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is
used for reception. For the reception operation of LIN, see Figure 14-2 LIN Reception Operation.
Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6
(ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6)
of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status,
the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable
status.
When the start bit has been detected, reception is started, and serial data is sequentially stored in the
receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is
11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At
this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of
errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status
register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed.
In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not
performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not
occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In
this case, the SBRF6 and SBRT6 bits are not cleared.
Figure 14-23. SBF Reception
1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits)
1
RXD6
2
3
4
5
6
7
8
9
10
11
SBRT6
/SBRF6
INTSR6
2. SBF reception error (stop bit is detected with a width of 10.5 bits or less)
1
RXD6
2
3
4
5
6
7
8
9
SBRT6
/SBRF6
INTSR6
Remark
RXD6:
“0”
RXD6 pin (input)
SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6)
SBRF6: Bit 7 of ASICL6
INTSR6: Reception completion interrupt request
322
User’s Manual U17734EJ2V0UD
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CHAPTER 14 SERIAL INTERFACE UART6
14.4.3 Dedicated baud rate generator
The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and
generates a serial clock for transmission/reception of UART6.
Separate 8-bit counters are provided for transmission and reception.
(1) Configuration of baud rate generator
• Base clock
The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to
each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is
1. This clock is called the base clock and its frequency is called fXCLK6. The base clock is fixed to low level
when POWER6 = 0.
• Transmission counter
This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial
interface operation mode register 6 (ASIM6) is 0.
It starts counting when POWER6 = 1 and TXE6 = 1.
The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6).
If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been
completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues
counting until POWER6 or TXE6 is cleared to 0.
• Reception counter
This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial
interface operation mode register 6 (ASIM6) is 0.
It starts counting when the start bit has been detected.
The counter stops operation after one frame has been received, until the next start bit is detected.
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CHAPTER 14 SERIAL INTERFACE UART6
Figure 14-24. Configuration of Baud Rate Generator
POWER6
fPRS
Baud rate generator
fPRS/2
fPRS/22
POWER6, TXE6 (or RXE6)
fPRS/23
fPRS/24
fPRS/25
Selector
fPRS/26
8-bit counter
fXCLK6
fPRS/27
fPRS/28
fPRS/29
fPRS/210
8-bit timer/
event counter
50 output
Match detector
CKSR6: TPS63 to TPS60
Remark
Baud rate
1/2
BRGC6: MDL67 to MDL60
POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)
TXE6:
Bit 6 of ASIM6
RXE6:
Bit 5 of ASIM6
CKSR6:
Clock selection register 6
BRGC6:
Baud rate generator control register 6
(2) Generation of serial clock
A serial clock to be generated can be specified by using clock selection register 6 (CKSR6) and baud rate
generator control register 6 (BRGC6).
The clock to be input to the 8-bit counter can be set by bits 3 to 0 (TPS63 to TPS60) of CKSR6 and the division
value (fXCLK6/8 to fXCLK6/255) of the 8-bit counter can be set by bits 7 to 0 (MDL67 to MDL60) of BRGC6.
Table 14-4. Set Value of TPS63 to TPS60
TPS63
TPS62
TPS61
TPS60
Base Clock (fXCLK6) Selection
fPRS =
2 MHz
fPRS =
10 MHz
fPRS =
20 MHz
0
0
0
0
fPRS
2 MHz
5 MHz
10 MHz
20 MHz
0
0
0
1
fPRS/2
1 MHz
2.5 MHz
5 MHz
10 MHz
0
0
1
0
fPRS/2
2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
1.25 MHz
0
0
1
1
fPRS/2
3
250 kHz
625 kHz
0
1
0
0
fPRS/2
4
125 kHz
312.5 kHz 625 kHz
0
1
0
1
fPRS/2
5
62.5 kHz
156.25 kHz 312.5 kHz 625 kHz
0
1
1
0
fPRS/2
6
31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
0
1
1
1
fPRS/2
7
15.625 kHz 39.06 kHz 78.13 kHz 156.25 kHz
1
0
0
0
fPRS/2
8
7.813 kHz 19.53 kHz 39.06 kHz 78.13 kHz
3.906 kHz 9.77 kHz
19.53 kHz 39.06 kHz
1.953 kHz 4.88 kHz
9.77 kHz
1
0
0
1
fPRS/2
9
1
0
1
0
fPRS/2
10
1
0
1
1
TM50 output
Other than above
324
fPRS =
5 MHz
Setting prohibited
User’s Manual U17734EJ2V0UD
2.5 MHz
1.25 MHz
19.53 kHz
CHAPTER 14 SERIAL INTERFACE UART6
(a) Baud rate
The baud rate can be calculated by the following expression.
• Baud rate =
fXCLK6
2×k
[bps]
fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register
k:
Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255)
(b) Error of baud rate
The baud rate error can be calculated by the following expression.
• Error (%) =
Actual baud rate (baud rate with error)
Desired baud rate (correct baud rate)
− 1 × 100 [%]
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at
the reception destination.
2. Make sure that the baud rate error during reception satisfies the range shown in (4)
Permissible baud rate range during reception.
Example: Frequency of base clock = 10 MHz = 10,000,000 Hz
Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33)
Target baud rate = 153600 bps
Baud rate = 10 M/(2 × 33)
= 10000000/(2 × 33) = 151,515 [bps]
Error = (151515/153600 − 1) × 100
= −1.357 [%]
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CHAPTER 14 SERIAL INTERFACE UART6
(3) Example of setting baud rate
Table 14-5. Set Data of Baud Rate Generator
Baud
fPRS = 2.0 MHz
Rate
TPS63-
[bps]
TPS60
300
8H
600
7H
1200
k
fPRS = 5.0 MHz
Calculated ERR TPS63Value
[%]
TPS60
13
301
0.16
7H
13
601
0.16
6H
6H
13
1202
0.16
2400
5H
13
2404
4800
4H
13
9600
3H
19200
fPRS = 10.0 MHz
Calculated ERR TPS63-
k
Value
[%]
TPS60
65
301
0.16
8H
65
601
0.16
7H
5H
65
1202
0.16
0.16
4H
65
2404
4808
0.16
3H
65
13
9615
0.16
2H
2H
13
19231
0.16
24000
1H
21
23810
31250
1H
4
38400
1H
13
48000
0H
76800
k
fPRS = 20.0 MHz
Calculated ERR TPS63Value
[%]
TPS60
65
301
0.16
9H
65
601
0.16
8H
6H
65
1202
0.16
0.16
5H
65
2404
4808
0.16
4H
65
65
9615
0.16
3H
1H
65
19231
0.16
−0.79
3H
13
24038
31250
0
4H
5
38462
0.16
0H
65
21
47619
−0.79
2H
0H
13
76923
0.16
115200
0H
9
111111 −3.55
153600
−
−
−
312500
−
−
−
Remark
Calculated ERR
Value
[%]
65
301
0.16
65
601
0.16
7H
65
1202
0.16
0.16
6H
65
2404
0.16
4808
0.16
5H
65
4808
0.16
65
9615
0.16
4H
65
9615
0.16
2H
65
19231
0.16
3H
65
19231
0.16
0.16
4H
13
24038
0.16
5H
13
24038
0.16
31250
0
5H
5
31250
0
6H
5
31250
0
38462
0.16
1H
65
38462
0.16
2H
65
38462
0.16
13
48077
0.16
3H
13
48077
0.16
4H
13
48077
0.16
0H
33
75758
−1.36
0H
65
76923
0.16
1H
65
76923
0.16
1H
11
113636 −1.36
0H
43
116279
0.94
0H
87
114943 −0.22
−
1H
8
156250
1.73
0H
33
151515 −1.36
1H
33
151515 −1.36
−
0H
8
312500
0
1H
8
312500
2H
8
312500
0
0
TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6))
k:
Value set by MDL67 to MDL60 bits of baud rate generator control register 6
(BRGC6) (k = 8, 9, 10, ..., 255)
326
k
fPRS:
Peripheral hardware clock frequency
ERR:
Baud rate error
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CHAPTER 14 SERIAL INTERFACE UART6
(4) Permissible baud rate range during reception
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
using the calculation expression shown below.
Figure 14-25. Permissible Baud Rate Range During Reception
Latch timing
Data frame length
of UART6
Start bit
Bit 0
Bit 1
Bit 7
Stop bit
Parity bit
FL
1 data frame (11 × FL)
Minimum permissible
data frame length
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmin
Maximum permissible
data frame length
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmax
As shown in Figure 14-25, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
FL = (Brate)−1
Brate: Baud rate of UART6
k:
Set value of BRGC6
FL:
1-bit data length
Margin of latch timing: 2 clocks
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CHAPTER 14 SERIAL INTERFACE UART6
Minimum permissible data frame length: FLmin = 11 × FL −
k−2
2k
× FL =
21k + 2
2k
FL
Therefore, the maximum receivable baud rate at the transmission destination is as follows.
22k
BRmax = (FLmin/11)−1 =
Brate
21k + 2
Similarly, the maximum permissible data frame length can be calculated as follows.
10
11
× FLmax = 11 × FL −
FLmax =
21k – 2
20k
k+2
2×k
× FL =
21k − 2
2×k
FL
FL × 11
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
BRmin = (FLmax/11)−1 =
20k
21k − 2
Brate
The permissible baud rate error between UART6 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Table 14-6. Maximum/Minimum Permissible Baud Rate Error
Division Ratio (k)
Maximum Permissible Baud Rate Error
Minimum Permissible Baud Rate Error
8
+3.53%
−3.61%
20
+4.26%
−4.31%
50
+4.56%
−4.58%
100
+4.66%
−4.67%
255
+4.72%
−4.73%
Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock
frequency, and division ratio (k). The higher the input clock frequency and the higher the division
ratio (k), the higher the permissible error.
2. k: Set value of BRGC6
328
User’s Manual U17734EJ2V0UD
CHAPTER 14 SERIAL INTERFACE UART6
(5) Data frame length during continuous transmission
When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by
two clocks of base clock from the normal value. However, the result of communication is not affected because
the timing is initialized on the reception side when the start bit is detected.
Figure 14-26. Data Frame Length During Continuous Transmission
Start bit of
second byte
1 data frame
Start bit
FL
Bit 0
Bit 1
Bit 7
FL
FL
FL
Parity bit
FL
Stop bit
FLstp
Start bit
FL
Bit 0
FL
Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following
expression is satisfied.
FLstp = FL + 2/fXCLK6
Therefore, the data frame length during continuous transmission is:
Data frame length = 11 × FL + 2/fXCLK6
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15.1 Functions of Serial Interface CSI10
Serial interface CSI10 has the following two modes.
• Operation stop mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial communication is not performed and can enable a reduction in the power
consumption.
For details, see 15.4.1 Operation stop mode.
(2) 3-wire serial I/O mode (MSB/LSB-first selectable)
This mode is used to communicate 8-bit data using three lines: a serial clock line (SCK10) and two serial data
lines (SI10 and SO10).
The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission
and reception can be simultaneously executed.
In addition, whether 8-bit data is communicated with the MSB or LSB first can be specified, so this interface can
be connected to any device.
The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial
interface.
For details, see 15.4.2 3-wire serial I/O mode.
15.2 Configuration of Serial Interface CSI10
Serial interface CSI10 includes the following hardware.
Table 15-1. Configuration of Serial Interface CSI10
Item
Controller
Configuration
Transmit controller
Clock start/stop controller & clock phase controller
Registers
Transmit buffer register 10 (SOTB10)
Serial I/O shift register 10 (SIO10)
Control registers
Serial operation mode register 10 (CSIM10)
Serial clock selection register 10 (CSIC10)
Port mode register 1 (PM1)
Port register 1 (P1)
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Figure 15-1. Block Diagram of Serial Interface CSI10
Internal bus
(a)
8
8
Serial I/O shift
register 10 (SIO10)
SI10/P11/RXD0
Transmit buffer
register 10 (SOTB10)
Output
selector
SO10/P12
Output latch
(P12)
Output latch
Transmit data
controller
PM12
Selector
Transmit controller
fPRS/2
fPRS/22
fPRS/23
fPRS/24
fPRS/25
fPRS/26
fPRS/27
SCK10/P10/TxD0
Clock start/stop controller &
clock phase controller
INTCSI10
Baud rate generator
PM10
Remark
Output latch
(P10)
(a): SO10 output
(1) Transmit buffer register 10 (SOTB10)
This register sets the transmit data.
Transmission/reception is started by writing data to SOTB10 when bit 7 (CSIE10) and bit 6 (TRMD10) of serial
operation mode register 10 (CSIM10) is 1.
The data written to SOTB10 is converted from parallel data into serial data by serial I/O shift register 10, and
output to the serial output pin (SO10).
SOTB10 can be written or read by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Caution Do not access SOTB10 when CSOT10 = 1 (during serial communication).
(2) Serial I/O shift register 10 (SIO10)
This is an 8-bit register that converts data from parallel data into serial data and vice versa.
This register can be read by an 8-bit memory manipulation instruction.
Reception is started by reading data from SIO10 if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10)
is 0.
During reception, the data is read from the serial input pin (SI10) to SIO10.
Reset signal generation sets this register to 00H.
Caution Do not access SIO10 when CSOT10 = 1 (during serial communication).
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15.3 Registers Controlling Serial Interface CSI10
Serial interface CSI10 is controlled by the following four registers.
• Serial operation mode register 10 (CSIM10)
• Serial clock selection register 10 (CSIC10)
• Port mode register 1 (PM1)
• Port register 1 (P1)
(1) Serial operation mode register 10 (CSIM10)
CSIM10 is used to select the operation mode and enable or disable operation.
CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 15-2. Format of Serial Operation Mode Register 10 (CSIM10)
Address: FF80H After reset: 00H R/W
Note 1
Symbol
6
5
4
3
2
1
0
CSIM10
CSIE10
TRMD10
0
DIR10
0
0
0
CSOT10
CSIE10
Operation control in 3-wire serial I/O mode
Note 2
0
Disables operation
1
Enables operation
and asynchronously resets the internal circuit
Note 4
TRMD10
0
Note 5
1
DIR10
.
Transmit/receive mode control
Receive mode (transmission disabled).
Transmit/receive mode
Note 6
First bit specification
0
MSB
1
LSB
CSOT10
Notes 1.
Note 3
Communication status flag
0
Communication is stopped.
1
Communication is in progress.
Bit 0 is a read-only bit.
2.
To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIM10 in the default status
3.
Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset.
(00H).
4.
Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication).
5.
The SO10 output (see (a) in Figure 15-1) is fixed to the low level when TRMD10 is 0. Reception is
6.
Do not rewrite DIR10 when CSOT10 = 1 (during serial communication).
started when data is read from SIO10.
Caution Be sure to clear bit 5 to 0.
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CHAPTER 15 SERIAL INTERFACE CSI10
(2) Serial clock selection register 10 (CSIC10)
This register specifies the timing of the data transmission/reception and sets the serial clock.
CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 15-3. Format of Serial Clock Selection Register 10 (CSIC10)
Address: FF81H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
CSIC10
0
0
0
CKP10
DAP10
CKS102
CKS101
CKS100
CKP10
DAP10
0
0
Specification of data transmission/reception timing
1
SCK10
SO10
Type
D7 D6 D5 D4 D3 D2 D1 D0
SI10 input timing
0
1
2
SCK10
SO10
D7 D6 D5 D4 D3 D2 D1 D0
SI10 input timing
1
0
3
SCK10
SO10
D7 D6 D5 D4 D3 D2 D1 D0
SI10 input timing
1
1
4
SCK10
SO10
D7 D6 D5 D4 D3 D2 D1 D0
SI10 input timing
CKS102
CKS101
CKS100
Mode
CSI10 serial clock selection
fPRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
fPRS =
20 MHz
1 MHz
2.5 MHz
5 MHz
Setting
prohibited
0
0
0
fPRS/2
0
0
1
fPRS/2
2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
fPRS/2
3
250 kHz
625 kHz
1.25 MHz
2.5 MHz
625 kHz
0
1
0
0
1
1
fPRS/2
4
125 kHz
312.5 kHz
1
0
0
fPRS/2
5
62.5 kHz
156.25 kHz 312.5 kHz
1
0
1
fPRS/2
6
31.25 kHz 78.13 kHz
7
15.63 kHz 39.06 kHz 78.13 kHz
1
1
0
fPRS/2
1
1
1
External clock input to SCK10
Master mode
1.25 MHz
625 kHz
156.25 kHz 312.5 kHz
156.25 kHz
Slave mode
Cautions 1. Do not write to CSIC10 while CSIE10 = 1 (operation enabled).
2. To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIC10 in the default
status (00H).
3. The phase type of the data clock is type 1 after reset.
Remark
fPRS: Peripheral hardware clock oscillation frequency
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(3) Port mode register 1 (PM1)
This register sets port 1 input/output in 1-bit units.
When using P10/SCK10 as the clock output pin of the serial interface, clear PM10 to 0, and set the output latches
of P10 to 1.
When using P12/SO10 as the data output pin of the serial interface, clear PM12 and the output latches of P12 to
0.
When using P10/SCK10 as the clock input pin of the serial interface and P11/SI10/RxD0 as the data input pin, set
PM10 and PM11 to 1. At this time, the output latches of P10 and P11 may be 0 or 1.
PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 15-4. Format of Port Mode Register 1 (PM1)
Address: FF21H
Symbol
7
After reset: FFH
6
5
4
R/W
3
2
1
0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
PM1n
334
P1n pin I/O mode selection (n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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CHAPTER 15 SERIAL INTERFACE CSI10
15.4 Operation of Serial Interface CSI10
Serial interface CSI10 can be used in the following two modes.
• Operation stop mode
• 3-wire serial I/O mode
15.4.1 Operation stop mode
Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In
addition, the P10/SCK10/TXD0, P11/SI10/RXD0, and P12/SO10 pins can be used as ordinary I/O port pins in this
mode.
(1) Register used
The operation stop mode is set by serial operation mode register 10 (CSIM10).
To set the operation stop mode, clear bit 7 (CSIE10) of CSIM10 to 0.
(a) Serial operation mode register 10 (CSIM10)
CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets CSIM1n to 00H.
Address: FF80H After reset: 00H R/W
Symbol
6
5
4
3
2
1
0
CSIM10
CSIE10
TRMD10
0
DIR10
0
0
0
CSOT10
CSIE10
0
Notes 1.
Operation control in 3-wire serial I/O mode
Note 1
Disables operation
and asynchronously resets the internal circuit
Note 2
.
To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIM10 in the default
status (00H).
2.
Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset.
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15.4.2 3-wire serial I/O mode
The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial
interface.
In this mode, communication is executed by using three lines: the serial clock (SCK10), serial output (SO10), and
serial input (SI10) lines.
(1) Registers used
• Serial operation mode register 10 (CSIM10)
• Serial clock selection register 10 (CSIC10)
• Port mode register 1 (PM1)
• Port register 1 (P1)
The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows.
Set the CSIC10 register (see Figures 15-3).
Set bits 0, 4, and 6 (CSOT10, DIR10, and TRMD10) of the CSIM10 register (see Figures 15-2).
Set bit 7 (CSIE10) of the CSIM10 register to 1. → Transmission/reception is enabled.
Write data to transmit buffer register 10 (SOTB10). → Data transmission/reception is started.
Read data from serial I/O shift register 10 (SIO10). → Data reception is started.
Caution Take relationship with the other party of communication when setting the port mode register
and port register.
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The relationship between the register settings and pins is shown below.
Table 15-2. Relationship Between Register Settings and Pins
CSIE10 TRMD10 PM11
P11
PM12
P12
PM10
CSI10
P10
Pin Function
Operation
SI10/RxD0/ SO10/P12
P11
0
×
Note 1
×
×
Note 1
×
Note 1
×
Note 1
×
Note 1
×
Note 1
Stop
SCK10/
TxD0/P10
RxD0/P11
P12
TxD0/
P10
1
0
×
1
×
Note 1
×
Note 1
1
×
Slave
reception
1
×
Note 1
1
×
Note 1
0
0
1
×
SI10
P12
Note 3
Slave
Note 3
RxD0/P11
SO10
Note 3
1
×
1
0
0
1
×
Slave
reception
1
0
×
1
×
×
Note 1
0
1
SCK10
Note 3
(input)
SI10
SO10
SCK10
Note 3
transmission/
Note 1
SCK10
(input)
transmission
1
Note 2
(input)
Note 3
Master reception
SI10
P12
SCK10
(output)
1
×
Note 1
1
×
Note 1
0
0
0
Master
1
RxD0/P11
SO10
transmission
1
1
1
×
0
0
0
Master
1
SCK10
(output)
SI10
SO10
transmission/
SCK10
(output)
reception
Notes 1. Can be set as port function.
2. To use P10/SCK10/TxD0 as port pins, clear CKP10 to 0.
3. To use the slave mode, set CKS102, CKS101, and CKS100 to 1, 1, 1.
Remark
×:
don’t care
CSIE10:
Bit 7 of serial operation mode register 10 (CSIM10)
TRMD10:
Bit 6 of CSIM10
CKP10:
Bit 4 of serial clock selection register 10 (CSIC10)
CKS102, CKS101, CKS100: Bits 2 to 0 of CSIC10
PM1×:
Port mode register
P1×:
Port output latch
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CHAPTER 15 SERIAL INTERFACE CSI10
(2) Communication operation
In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or
received in synchronization with the serial clock.
Data can be transmitted or received if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1.
Transmission/reception is started when a value is written to transmit buffer register 10 (SOTB10). In addition,
data can be received when bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 0.
Reception is started when data is read from serial I/O shift register 10 (SIO10).
After communication has been started, bit 0 (CSOT10) of CSIM10 is set to 1. When communication of 8-bit data
has been completed, a communication completion interrupt request flag (CSIIF10) is set, and CSOT10 is cleared
to 0. Then the next communication is enabled.
Caution Do not access the control register and data register when CSOT10 = 1 (during serial
communication).
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Figure 15-5. Timing in 3-Wire Serial I/O Mode (1/2)
(a) Transmission/reception timing (Type 1: TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 0)
SCK10
Read/write trigger
SOTB10
SIO10
55H (communication data)
ABH
56H
ADH
5AH
B5H
6AH
D5H
AAH
CSOT10
INTCSI10
CSIIF10
SI10 (receive AAH)
SO10
55H is written to SOTB10.
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CHAPTER 15 SERIAL INTERFACE CSI10
Figure 15-5. Timing in 3-Wire Serial I/O Mode (2/2)
(b) Transmission/reception timing (Type 2: TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1)
SCK10
Read/write trigger
SOTB10
SIO10
55H (communication data)
ABH
56H
ADH
5AH
CSOT10
INTCSI10
CSIIF10
SI10 (input AAH)
SO10
55H is written to SOTB10.
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B5H
6AH
D5H
AAH
CHAPTER 15 SERIAL INTERFACE CSI10
Figure 15-6. Timing of Clock/Data Phase
(a) Type 1: CKP10 = 0, DAP10 = 0, DIR10 = 0
SCK10
SI10 capture
SO10
Writing to SOTB10 or
reading from SIO10
CSIIF10
D7
D6
D5
D4
D3
D2
D1
D0
CSOT10
(b) Type 2: CKP10 = 0, DAP10 = 1, DIR10 = 0
SCK10
SI10 capture
SO10
Writing to SOTB10 or
reading from SIO10
CSIIF10
D7
D6
D5
D4
D3
D2
D1
D0
CSOT10
(c) Type 3: CKP10 = 1, DAP10 = 0, DIR10 = 0
SCK10
SI10 capture
SO10
Writing to SOTB10 or
reading from SIO10
CSIIF10
D7
D6
D5
D4
D3
D2
D1
D0
CSOT10
(d) Type 4: CKP10 = 1, DAP10 = 1, DIR10 = 0
SCK10
SI10 capture
SO10
Writing to SOTB10 or
reading from SIO10
CSIIF10
D7
D6
D5
D4
D3
D2
D1
D0
CSOT10
Remark
The above figure illustrates a communication operation where data is transmitted with the MSB first.
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CHAPTER 15 SERIAL INTERFACE CSI10
(3) Timing of output to SO10 pin (first bit)
When communication is started, the value of transmit buffer register 10 (SOTB10) is output from the SO10 pin.
The output operation of the first bit at this time is described below.
Figure 15-7. Output Operation of First Bit (1/2)
(a) Type 1: CKP10 = 0, DAP10 = 0
SCK10
Writing to SOTB10 or
reading from SIO10
SOTB10
SIO10
Output latch
First bit
SO10
2nd bit
(b) Type 3: CKP10 = 1, DAP10 = 0
SCK10
Writing to SOTB10 or
reading from SIO10
SOTB10
SIO10
Output latch
SO10
First bit
2nd bit
The first bit is directly latched by the SOTB10 register to the output latch at the falling (or rising) edge of SCK10,
and output from the SO10 pin via an output selector. Then, the value of the SOTB10 register is transferred to the
SIO10 register at the next rising (or falling) edge of SCK10, and shifted one bit. At the same time, the first bit of
the receive data is stored in the SIO10 register via the SI10 pin.
The second and subsequent bits are latched by the SIO10 register to the output latch at the next falling (or rising)
edge of SCK10, and the data is output from the SO10 pin.
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CHAPTER 15 SERIAL INTERFACE CSI10
Figure 15-7. Output Operation of First Bit (2/2)
(c) Type 2: CKP10 = 0, DAP10 = 1
SCK10
Writing to SOTB10 or
reading from SIO10
SOTB10
SIO10
Output latch
SO10
First bit
2nd bit
3rd bit
2nd bit
3rd bit
(d) Type 4: CKP10 = 1, DAP10 = 1
SCK10
Writing to SOTB10 or
reading from SIO10
SOTB10
SIO10
Output latch
SO10
First bit
The first bit is directly latched by the SOTB10 register at the falling edge of the write signal of the SOTB10
register or the read signal of the SIO10 register, and output from the SO10 pin via an output selector. Then, the
value of the SOTB10 register is transferred to the SIO10 register at the next falling (or rising) edge of SCK10, and
shifted one bit. At the same time, the first bit of the receive data is stored in the SIO10 register via the SI10 pin.
The second and subsequent bits are latched by the SIO10 register to the output latch at the next rising (or falling)
edge of SCK10, and the data is output from the SO10 pin.
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CHAPTER 15 SERIAL INTERFACE CSI10
(4) Output value of SO10 pin (last bit)
After communication has been completed, the SO10 pin holds the output value of the last bit.
Figure 15-8. Output Value of SO10 Pin (Last Bit) (1/2)
(a) Type 1: CKP10 = 0, DAP10 = 0
SCK10
( ← Next request is issued.)
Writing to SOTB10 or
reading from SIO10
SOTB10
SIO10
Output latch
Last bit
SO10
(b) Type 3: CKP10 = 1, DAP10 = 0
SCK10
Writing to SOTB10 or
reading from SIO10
( ← Next request is issued.)
SOTB10
SIO10
Output latch
SO10
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CHAPTER 15 SERIAL INTERFACE CSI10
Figure 15-8. Output Value of SO10 Pin (Last Bit) (2/2)
(c) Type 2: CKP10 = 0, DAP10 = 1
SCK10
Writing to SOTB10 or
reading from SIO10
( ← Next request is issued.)
SOTB10
SIO10
Output latch
SO10
Last bit
(d) Type 4: CKP10 = 1, DAP10 = 1
SCK10
Writing to SOTB10 or
reading from SIO10
( ← Next request is issued.)
SOTB10
SIO10
Output latch
SO10
Last bit
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CHAPTER 15 SERIAL INTERFACE CSI10
(5) SO10 output (see (a) in Figure 15-1)
The status of the SO10 output is as follows if bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) is
cleared to 0.
Table 15-3. SO10 Output Status
TRMD10
TRMD10 = 0
TRMD10 = 1
Note 1
DAP10
DIR10
−
−
Outputs low level
DAP10 = 0
−
Value of SO10 latch
Note 2
SO10 Output
Note 2
(low-level output)
DAP10 = 1
Notes 1.
DIR10 = 0
Value of bit 7 of SOTB10
DIR10 = 1
Value of bit 0 of SOTB10
The actual output of the SO10/P12 pin is determined according to PM12 and P12, as well as
the SO10 output.
2.
Status after reset
Caution If a value is written to TRMD10, DAP10, and DIR10, the output value of SO10 changes.
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CHAPTER 16 SERIAL INTERFACE IIC0
16.1 Functions of Serial Interface IIC0
Serial interface IIC0 has the following two modes.
(1) Operation stop mode
This mode is used when serial transfers are not performed. It can therefore be used to reduce power
consumption.
(2) I2C bus mode (multimaster supported)
This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a
serial data bus (SDA0) line.
This mode complies with the I2C bus format and the master device can generated “start condition”, “address”,
“transfer direction specification”, “data”, and “stop condition” data to the slave device, via the serial data bus.
The slave device automatically detects these received status and data by hardware. This function can simplify
the part of application program that controls the I2C bus.
Since the SCL0 and SDA0 pins are used for open drain outputs, IIC0 requires pull-up resistors for the serial
clock line and the serial data bus line.
Figure 16-1 shows a block diagram of serial interface IIC0.
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CHAPTER 16 SERIAL INTERFACE IIC0
Figure 16-1. Block Diagram of Serial Interface IIC0
Internal bus
IIC status register 0 (IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
IIC control register 0 (IICC0)
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
Slave address
register 0 (SVA0)
SDA0/
P61
Noise
eliminator
IIC shift
register 0 (IIC0)
DFC0
PM61
Set
D Q
Stop
condition
generator
SO latch
CL01,
CL00
Data hold
time correction
circuit
TRC0
N-ch opendrain output
Start
condition
generator
Clear
Match
signal
ACK
generator
Output control
Output latch
(P61)
Wake-up
controller
ACK detector
Start condition
detector
Stop condition
detector
SCL0/
P60
Noise
eliminator
DFC0
Interrupt request
signal generator
Serial clock
counter
Serial clock
controller
Serial clock
wait controller
N-ch opendrain output
PM60
Output latch
(P60)
IICS0.MSTS0,
EXC0, COI0
IIC shift register 0 (IIC0)
IICC0.STT0, SPT0
IICS0.MSTS0, EXC0, COI0
fPRS
Bus status
detector
Prescaler
CLD0 DAD0 SMC0 DFC0 CL01 CL00
IIC clock selection
register 0 (IICCL0)
CLX0
STCF
IIC function expansion
register 0 (IICX0)
Internal bus
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INTIIC0
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IICBSY STCEN IICRSV
IIC flag register 0
(IICF0)
CHAPTER 16 SERIAL INTERFACE IIC0
Figure 16-2 shows a serial bus configuration example.
Figure 16-2. Serial Bus Configuration Example Using I2C Bus
+ VDD + VDD
Master CPU1
SDA0
Slave CPU1
Address 0
SCL0
Serial data bus
Serial clock
SDA0
Slave CPU2
SCL0
SDA0
SCL0
SDA0
SCL0
SDA0
SCL0
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Master CPU2
Address 1
Slave CPU3
Address 2
Slave IC
Address 3
Slave IC
Address N
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16.2 Configuration of Serial Interface IIC0
Serial interface IIC0 includes the following hardware.
Table 16-1. Configuration of Serial Interface IIC0
Item
Configuration
Registers
IIC shift register 0 (IIC0)
Slave address register 0 (SVA0)
Control registers
IIC control register 0 (IICC0)
IIC status register 0 (IICS0)
IIC flag register 0 (IICF0)
IIC clock selection register 0 (IICCL0)
IIC function expansion register 0 (IICX0)
Port mode register 6 (PM6)
Port register 6 (P6)
(1) IIC shift register 0 (IIC0)
IIC0 is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial
clock. IIC0 can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing and reading operations to IIC0.
Cancel the wait state and start data transfer by writing data to IIC0 during the wait period.
IIC0 is set by an 8-bit memory manipulation instruction.
Reset signal generation sets IIC0 to 00H.
Figure 16-3. Format of IIC Shift Register 0 (IIC0)
Address: FFA5H
Symbol
7
After reset: 00H
6
R/W
5
4
3
2
1
0
IIC0
Cautions 1. Do not write data to IIC0 during data transfer.
2. Write or read IIC0 only during the wait period. Accessing IIC0 in a communication state
other than during the wait period is prohibited. When the device serves as the master,
however, IIC0 can be written only once after the communication trigger bit (STT0) is set to
1.
(2) Slave address register 0 (SVA0)
This register stores local addresses when in slave mode.
SVA0 is set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STD0 = 1 (while the start condition is detected).
Reset signal generation sets SVA0 to 00H.
Figure 16-4. Format of Slave Address Register 0 (SVA0)
Address: FFA7H
Symbol
7
After reset: 00H
6
R/W
5
4
3
Note Bit 0 is fixed to 0.
350
2
1
0
0Note
SVA0
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(3) SO latch
The SO latch is used to retain the SDA0 pin’s output level.
(4) Wake-up controller
This circuit generates an interrupt request (INTIIC0) when the address received by this register matches the
address value set to slave address register 0 (SVA0) or when an extension code is received.
(5) Prescaler
This selects the sampling clock to be used.
(6) Serial clock counter
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to
verify that 8-bit data was transmitted or received.
(7) Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIIC0).
An I2C interrupt request is generated by the following two triggers.
• Falling edge of eighth or ninth clock of the serial clock (set by WTIM0 bit)
• Interrupt request generated when a stop condition is detected (set by SPIE0 bit)
Remark
WTIM0 bit: Bit 3 of IIC control register 0 (IICC0)
SPIE0 bit:
Bit 4 of IIC control register 0 (IICC0)
(8) Serial clock controller
In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock.
(9) Serial clock wait controller
This circuit controls the wait timing.
(10) ACK generator, stop condition detector, start condition detector, and ACK detector
These circuits generate and detect each status.
(11) Data hold time correction circuit
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
(12) Start condition generator
This circuit generates a start condition when the STT0 bit is set to 1.
However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released
(IICBSY bit = 1), start condition requests are ignored and the STCF bit is set to 1.
(13) Stop condition generator
This circuit generates a stop condition when the SPT0 bit is set to 1.
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(14) Bus status detector
This circuit detects whether or not the bus is released by detecting start conditions and stop conditions.
However, as the bus status cannot be detected immediately following operation, the initial status is set by the
STCEN bit.
Remark
STT0 bit:
Bit 1 of IIC control register 0 (IICC0)
SPT0 bit:
Bit 0 of IIC control register 0 (IICC0)
IICRSV bit: Bit 0 of IIC flag register 0
IICBSY bit:
Bit 6 of IIC flag register 0
STCF bit:
Bit 7 of IIC flag register 0
STCEN bit: Bit 1 of IIC flag register 0
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16.3 Registers to Control Serial Interface IIC0
Serial interface IIC0 is controlled by the following seven registers.
• IIC control register 0 (IICC0)
• IIC flag register 0 (IICF0)
• IIC status register 0 (IICS0)
• IIC clock selection register 0 (IICCL0)
• IIC function expansion register 0 (IICX0)
• Port mode register 6 (PM6)
• Port register 6 (P6)
(1) IIC control register 0 (IICC0)
This register is used to enable/stop I2C operations, set wait timing, and set other I2C operations.
IICC0 is set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and ACKE0
bits while IICE0 bit = 0 or during the wait period. These bits can be set at the same time when the IICE0 bit is
set from “0” to “1”.
Reset signal generation sets IICC0 to 00H.
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Figure 16-5. Format of IIC Control Register 0 (IICC0) (1/4)
Address: FFA6H
After reset: 00H
R/W
Symbol
IICC0
IICE0
LREL0
WREL0
SPIE0
WTIM0
ACKE0
STT0
SPT0
2
IICE0
I C operation enable
0
Stop operation. Reset IIC status register 0 (IICS0)
1
Enable operation.
Note 1
. Stop internal operation.
Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level.
Condition for clearing (IICE0 = 0)
Condition for setting (IICE0 = 1)
• Cleared by instruction
• Set by instruction
• Reset
LREL0
Note 2
Exit from communications
0
Normal operation
1
This exits from the current communications and sets standby mode. This setting is automatically cleared after
being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCL0 and SDA0 lines are set to high impedance.
The following flags of IIC control register 0 (IICC0) and IIC status register 0 (IICS0) are cleared to 0.
• STT0 • SPT0 • MSTS0 • EXC0 • COI0 • TRC0 • ACKD0 • STD0
The standby mode following exit from communications remains in effect until the following communications entry conditions
are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0)
Condition for setting (LREL0 = 1)
• Automatically cleared after execution
• Set by instruction
• Reset
WREL0
Note 2
Wait cancellation
0
Do not cancel wait
1
Cancel wait. This setting is automatically cleared after wait is canceled.
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 = 1), the
SDA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0)
Condition for setting (WREL0 = 1)
• Automatically cleared after execution
• Set by instruction
• Reset
Notes 1. The IICS0 register, the STCF0 and IICBSY bits of the IICF0 register, and the CLD0 and DAD0 bits of the
IICCL0 register are reset.
2. This flag’s signal is invalid when IICE0 = 0.
Caution
The start condition is detected immediately after I2C is enabled to operate (IICE0 = 1) while the
SCL0 line is at high level and the SDA0 line is at low level. Immediately after enabling I2C to
operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory manipulation instruction.
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Figure 16-5. Format of IIC Control Register 0 (IICC0) (2/4)
Note 1
SPIE0
Enable/disable generation of interrupt request when stop condition is detected
0
Disable
1
Enable
Condition for clearing (SPIE0 = 0)
Condition for setting (SPIE0 = 1)
• Cleared by instruction
• Set by instruction
• Reset
Note 1
WTIM0
Control of wait and interrupt request generation
0
Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
1
Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit.
The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling
edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the
falling edge of the ninth clock after an acknowledge signal (ACK) is issued. However, when the slave device has received an
extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM0 = 0)
Condition for setting (WTIM0 = 1)
• Cleared by instruction
• Set by instruction
• Reset
Notes 1, 2
ACKE0
0
1
Acknowledgment control
Disable acknowledgment.
Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level. However, ACK is
invalid during address transfers and other than in expansion mode.
Condition for clearing (ACKE0 = 0)
Condition for setting (ACKE0 = 1)
• Cleared by instruction
• Set by instruction
• Reset
Notes 1. This flag’s signal is invalid when IICE0 = 0.
2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledge signal is generated
regardless of the set value.
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Figure 16-5. Format of IIC Control Register 0 (IICC0) (3/4)
STT0
Note
Start condition trigger
0
Do not generate a start condition.
1
When bus is released (in STOP mode):
Generate a start condition (for starting as master). When the SCL0 line is high level, the SDA0 line is changed
from high level to low level and then the start condition is generated. Next, after the rated amount of time has
elapsed, SCL0 is changed to low level.
When a third party is communicating:
• When communication reservation function is enabled (IICRSV = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start condition
after the bus is released.
• When communication reservation function is disabled (IICRSV = 1)
STCF is set to 1 and information that is set (1) to STT0 is cleared. No start condition is generated.
In the wait state (when master device):
Generates a restart condition after releasing the wait.
Cautions concerning set timing
• For master reception:
Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE0 has
been cleared to 0 and slave has been notified of final reception.
• For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1 during
the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as SPT0.
• Setting STT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (STT0 = 0)
Condition for setting (STT0 = 1)
• Cleared by setting SST0 to 1 while communication
• Set by instruction
reservation is prohibited.
• Cleared by loss in arbitration
• Cleared after start condition is generated by master device
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
Note This flag’s signal is invalid when IICE0 = 0.
Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting.
2. IICRSV: Bit 0 of IIC flag register (IICF0)
STCF:
356
Bit 7 of IIC flag register (IICF0)
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Figure 16-5. Format of IIC Control Register 0 (IICC0) (4/4)
SPT0
Stop condition trigger
0
Stop condition is not generated.
1
Stop condition is generated (termination of master device’s transfer).
After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to high level. Next,
after the rated amount of time has elapsed, the SDA0 line changes from low level to high level and a stop
condition is generated.
Cautions concerning set timing
• For master reception:
Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been
notified of final reception.
• For master transmission: A stop condition cannot be generated normally during the acknowledge period. Therefore, set it
during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as STT0.
• SPT0 can be set to 1 only when in master mode
Note
.
• When WTIM0 has been cleared to 0, if SPT0 is set to 1 during the wait period that follows output of eight clocks, note that a
stop condition will be generated during the high-level period of the ninth clock. WTIM0 should be changed from 0 to 1 during
the wait period following the output of eight clocks, and SPT0 should be set to 1 during the wait period that follows the output
of the ninth clock.
• Setting SPT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (SPT0 = 0)
Condition for setting (SPT0 = 1)
• Cleared by loss in arbitration
• Set by instruction
• Automatically cleared after stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
Note Set SPT0 to 1 only in master mode. However, SPT0 must be set to 1 and a stop condition generated before
the first stop condition is detected following the switch to the operation enabled status. For details, see
16.5.15 Other cautions.
Caution
When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1 during the ninth
clock and wait is canceled, after which TRC0 is cleared and the SDA0 line is set to high
impedance.
Remark
Bit 0 (SPT0) becomes 0 when it is read after data setting.
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(2) IIC status register 0 (IICS0)
This register indicates the status of I2C.
IICS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait
period.
Reset signal generation sets IICS0 to 00H.
Caution
If data is read from IICS0, a wait cycle is generated. Do not read data from IICS0 when the
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 29 CAUTIONS FOR WAIT.
Figure 16-6. Format of IIC Status Register 0 (IICS0) (1/3)
Address: FFAAH
After reset: 00H
R
Symbol
IICS0
MSTS0
ALD0
EXC0
COI0
TRC0
ACKD0
STD0
SPD0
MSTS0
Master device status
0
Slave device status or communication standby status
1
Master device communication status
Condition for clearing (MSTS0 = 0)
Condition for setting (MSTS0 = 1)
• When a stop condition is detected
• When ALD0 = 1 (arbitration loss)
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When a start condition is generated
ALD0
Detection of arbitration loss
0
This status means either that there was no arbitration or that the arbitration result was a “win”.
1
This status indicates the arbitration result was a “loss”. MSTS0 is cleared.
Condition for clearing (ALD0 = 0)
Condition for setting (ALD0 = 1)
Note
• Automatically cleared after IICS0 is read
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
EXC0
• When the arbitration result is a “loss”.
Detection of extension code reception
0
Extension code was not received.
1
Extension code was received.
Condition for clearing (EXC0 = 0)
Condition for setting (EXC0 = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When the higher four bits of the received address data is
either “0000” or “1111” (set at the rising edge of the
eighth clock).
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other
than IICS0. Therefore, when using the ALD0 bit, read the data of this bit before the data of the other
bits.
Remark
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
358
Bit 7 of IIC control register 0 (IICC0)
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Figure 16-6. Format of IIC Status Register 0 (IICS0) (2/3)
COI0
Detection of matching addresses
0
Addresses do not match.
1
Addresses match.
Condition for clearing (COI0 = 0)
Condition for setting (COI0 = 1)
• When a start condition is detected
• When the received address matches the local address
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
(slave address register 0 (SVA0))
(set at the rising edge of the eighth clock).
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
TRC0
Detection of transmit/receive status
0
Receive status (other than transmit status). The SDA0 line is set for high impedance.
1
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at the
falling edge of the first byte’s ninth clock).
Condition for clearing (TRC0 = 0)
Condition for setting (TRC0 = 1)
• When a stop condition is detected
• When a start condition is generated
• Cleared by LREL0 = 1 (exit from communications)
• When “0” is output to the first byte’s LSB (transfer
• When IICE0 changes from 1 to 0 (operation stop)
• Cleared by WREL0 = 1
Note
(wait cancel)
direction specification bit)
• When ALD0 changes from 0 to 1 (arbitration loss)
• Reset
• When “1” is input to the first byte’s LSB (transfer
direction specification bit)
• When “1” is output to the first byte’s LSB (transfer
direction specification bit)
• When a start condition is detected
• When “0” is input to the first byte’s LSB (transfer direction
specification bit)
Note If the wait status is canceled by setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1 at the ninth
clock when bit 3 (TRC0) of IIC status register 0 (IICS0) is 1, TRC0 is cleared, and the SDA0 line goes
into a high-impedance state.
Remark
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
Bit 7 of IIC control register 0 (IICC0)
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Figure 16-6. Format of IIC Status Register 0 (IICS0) (3/3)
ACKD0
Detection of acknowledge (ACK)
0
Acknowledge was not detected.
1
Acknowledge was detected.
Condition for clearing (ACKD0 = 0)
Condition for setting (ACKD0 = 1)
• When a stop condition is detected
• After the SDA0 line is set to low level at the rising edge of
• At the rising edge of the next byte’s first clock
SCL0’s ninth clock
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
STD0
Detection of start condition
0
Start condition was not detected.
1
Start condition was detected. This indicates that the address transfer period is in effect.
Condition for clearing (STD0 = 0)
Condition for setting (STD0 = 1)
• When a stop condition is detected
• When a start condition is detected
• At the rising edge of the next byte’s first clock following
address transfer
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
SPD0
Detection of stop condition
0
Stop condition was not detected.
1
Stop condition was detected. The master device’s communication is terminated and the bus is released.
Condition for clearing (SPD0 = 0)
Condition for setting (SPD0 = 1)
• At the rising edge of the address transfer byte’s first
• When a stop condition is detected
clock following setting of this bit and detection of a start
condition
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Remark
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
Bit 7 of IIC control register 0 (IICC0)
(3) IIC flag register 0 (IICF0)
This register sets the operation mode of I2C and indicates the status of the I2C bus.
IICF0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the STCF and IICBSY bits are readonly.
The IICRSV bit can be used to enable/disable the communication reservation function (see 16.5.14
Communication reservation).
STCEN can be used to set the initial value of the IICBSY bit (see 16.5.15 Other cautions).
IICRSV and STCEN can be written only when the operation of I2C is disabled (bit 7 (IICE0) of IIC control
register 0 (IICC0) = 0). When operation is enabled, the IICF0 register can be read.
Reset signal generation sets IICF0 to 00H.
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Figure 16-7. Format of IIC Flag Register 0 (IICF0)
Address: FFABH
After reset: 00H
R/WNote
Symbol
5
4
3
2
IICF0
STCF
IICBSY
0
0
0
0
STCEN
IICRSV
STCF
STT0 clear flag
0
Generate start condition
1
Start condition generation unsuccessful: clear STT0 flag
Condition for clearing (STCF = 0)
Condition for setting (STCF = 1)
• Cleared by STT0 = 1
• When IICE0 = 0 (operation stop)
• Reset
• Generating start condition unsuccessful and STT0
cleared to 0 when communication reservation is
disabled (IICRSV = 1).
I2C bus status flag
IICBSY
0
Bus release status (communication initial status when STCEN0 = 1)
1
Bus communication status (communication initial status when STCEN0 = 0)
Condition for clearing (IICBSY = 0)
Condition for setting (IICBSY = 1)
• Detection of stop condition
• When IICE0 = 0 (operation stop)
• Reset
• Detection of start condition
• Setting of IICE0 when STCEN = 0
STCEN
Initial start enable trigger
0
After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of
a stop condition.
1
After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting
a stop condition.
Condition for clearing (STCEN = 0)
Condition for setting (STCEN = 1)
• Detection of stop condition
• Reset
• Set by instruction
IICRSV
Communication reservation function disable bit
0
Enable communication reservation
1
Disable communication reservation
Condition for clearing (IICRSV = 0)
Condition for setting (IICRSV = 1)
• Cleared by instruction
• Reset
• Set by instruction
Note Bits 6 and 7 are read-only.
Cautions 1. Write to STCEN only when the operation is stopped (IICE0 = 0).
2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus
status when STCEN = 1, when generating the first start condition (STT0 = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
3. Write to IICRSV only when the operation is stopped (IICE0 = 0).
Remark
STT0: Bit 1 of IIC control register 0 (IICC0)
IICE0: Bit 7 of IIC control register 0 (IICC0)
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(4) IIC clock selection register 0 (IICCL0)
This register is used to set the transfer clock for the I2C bus.
IICCL0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are readonly. The SMC0, CL01, and CL00 bits are set in combination with bit 0 (CLX0) of IIC function expansion
register 0 (IICX0) (see 16.3 (6) I2C transfer clock setting method).
Set IICCL0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0.
Reset signal generation sets IICCL0 to 00H.
Figure 16-8. Format of IIC Clock Selection Register 0 (IICCL0) (1/2)
Address: FFA8H
After reset: 00H
R/W
Note
Symbol
7
6
1
0
IICCL0
0
0
CLD0
DAD0
SMC0
DFC0
CL01
CL00
CLD0
Detection of SCL0 pin level (valid only when IICE0 = 1)
0
The SCL0 pin was detected at low level.
1
The SCL0 pin was detected at high level.
Condition for clearing (CLD0 = 0)
Condition for setting (CLD0 = 1)
• When the SCL0 pin is at low level
• When the SCL0 pin is at high level
• When IICE0 = 0 (operation stop)
• Reset
DAD0
Detection of SDA0 pin level (valid only when IICE0 = 1)
0
The SDA0 pin was detected at low level.
1
The SDA0 pin was detected at high level.
Condition for clearing (DAD0 = 0)
Condition for setting (DAD0 = 1)
• When the SDA0 pin is at low level
• When the SDA0 pin is at high level
• When IICE0 = 0 (operation stop)
• Reset
Note Bits 4 and 5 are read-only.
Remark
IICE0: Bit 7 of IIC control register 0 (IICC0)
Figure 16-8. Format of IIC Clock Selection Register 0 (IICCL0) (2/2)
SMC0
Operation mode switching
0
Operates in standard mode.
1
Operates in high-speed mode.
DFC0
Digital filter operation control
0
Digital filter off.
1
Digital filter on.
Digital filter can be used only in high-speed mode.
In high-speed mode, the transfer clock does not vary regardless of DFC0 bit set (1)/clear (0).
The digital filter is used for noise elimination in high-speed mode.
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(5) IIC function expansion register 0 (IICX0)
This register sets the function expansion of I2C.
IICX0 is set by a 1-bit or 8-bit memory manipulation instruction. The CLX0 bit is set in combination with bits 3,
1, and 0 (SMC0, CL01, and CL00) of IIC clock selection register 0 (IICCL0) (see 16.3 (6) I2C transfer clock
setting method).
Set IICX0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0.
Reset signal generation sets IICX0 to 00H.
Figure 16-9. Format of IIC Function Expansion Register 0 (IICX0)
Address: FFA9H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
IICX0
0
0
0
0
0
0
0
CLX0
(6) I2C transfer clock setting method
The I2C transfer clock frequency (fSCL) is calculated using the following expression.
fSCL = 1/(m × T + tR + tF)
m = 12, 18, 24, 44, 66, 86 (see Table 16-2 Selection Clock Setting)
T:
1/fW
tR:
SCL0 rise time
tF:
SCL0 fall time
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For example, the I2C transfer clock frequency (fSCL) when fW = fPRS/2 = 4.19 MHz, m = 86, tR = 200 ns, and tF =
50 ns is calculated using following expression.
fSCL = 1/(88 × 238.7 ns + 200 ns + 50 ns) ≅ 48.1 kHz
m × T + tR + tF
tF
m/2 × T
tR
m/2 × T
SCL0
SCL0 inversion
SCL0 inversion
SCL0 inversion
The selection clock is set using a combination of bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection
register 0 (IICCL0) and bit 0 (CLX0) of IIC function expansion register 0 (IICX0).
Table 16-2. Selection Clock Setting
IICX0
IICCL0
Selection Clock
Transfer Clock
Settable Selection Clock
(fW)
(fW/m)
(fW) Range
Operation Mode
Bit 0
Bit 3
Bit 1
Bit 0
CLX0
SMC0
CL01
CL00
0
0
0
0
fPRS/2
fW/44
2.00 to 4.19 MHz
Normal mode
0
0
0
1
fPRS/2
fW/86
4.19 to 8.38 MHz
(SMC0 bit = 0)
0
0
1
0
fPRS/4
fW/86
0
0
1
1
Setting prohibited
0
1
0
×
fPRS/2
fW/24
4.00 to 8.38 MHz
High-speed mode
0
1
1
0
fPRS/4
fW/24
0
1
1
1
Setting prohibited
1
0
×
×
1
1
0
×
fPRS/2
fW/12
1
1
1
0
fPRS/4
fW/12
1
1
1
1
Setting prohibited
Caution
(SMC0 bit = 1)
4.00 to 4.19 MHz
High-speed mode
(SMC0 bit = 1)
Determine the transfer clock frequency of I2C by using CLX0, SMC0, CL01, and CL00 before
enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change
the transfer clock frequency, clear IICE0 once to 0.
Remarks 1. ×:
2. fPRS:
364
don’t care
Peripheral hardware clock frequency
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(7) Port mode register 6 (PM6)
This register sets the input/output of port 6 in 1-bit units.
When using the P60/SCL0 pin as clock I/O and the P61/SDA0 pin as serial data I/O, clear PM60 and PM61,
and the output latches of P60 and P61 to 0.
Set IICE0 (bit 7 of IIC control register 0 (IICC0)) to 1 before setting the output mode because the P60/SCL0
and P61/SDA0 pins output a low level (fixed) when IICE0 is 0.
PM6 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM6 to FFH.
Figure 16-10. Format of Port Mode Register 6 (PM6)
Address: FF26H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM6
1
1
1
1
1
PM62
PM61
PM60
PM61
0
Output mode (output buffer on)
1
Input mode (output buffer off)
PM60
Caution
SDA0 pin I/O mode selection
SCL0 pin I/O mode selection
0
Output mode (output buffer on)
1
Input mode (output buffer off)
After a reset release, be sure to set bit 2 to 0.
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16.4 I2C Bus Mode Functions
16.4.1 Pin configuration
The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows.
(1) SCL0....... This pin is used for serial clock input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
(2) SDA0 ...... This pin is used for serial data input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up
resistor is required.
Figure 16-11. Pin Configuration Diagram
Slave device
VDD
Master device
SCL0
SCL0
Clock output
(Clock output)
VDD
VSS
VSS
(Clock input)
Clock input
SDA0
SDA0
Data output
Data output
VSS
VSS
Data input
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16.5 I2C Bus Definitions and Control Methods
The following section describes the I2C bus’s serial data communication format and the signals used by the I2C bus.
Figure 16-12 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the
I2C bus’s serial data bus.
Figure 16-12. I2C Bus Serial Data Transfer Timing
SCL0
1-7
8
9
1-8
9
1-8
9
ACK
Data
ACK
SDA0
Start
condition
Address R/W ACK
Data
Stop
condition
The master device generates the start condition, slave address, and stop condition.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device
that receives 8-bit data).
The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0’s low
level period can be extended and a wait can be inserted.
16.5.1 Start conditions
A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level.
The start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device
when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
Figure 16-13. Start Conditions
SCL0
H
SDA0
A start condition is output when bit 1 (STT0) of IIC control register 0 (IICC0) is set (to 1) after a stop condition has
been detected (SPD0: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD0) of
IICS0 is set (to 1).
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16.5.2 Addresses
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to
the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique
address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address
data matches the data values stored in slave address register 0 (SVA0). If the address data matches the SVA0
values, the slave device is selected and communicates with the master device until the master device generates a
start condition or stop condition.
Figure 16-14. Address
SCL0
1
2
3
4
5
6
7
8
SDA0
A6
A5
A4
A3
A2
A1
A0
R/W
9
Address
Note
INTIIC0
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
The slave address and the eighth bit, which specifies the transfer direction as described in 16.5.3
Transfer
direction specification below, are together written to IIC shift register 0 (IIC0) and are then output. Received
addresses are written to IIC0.
The slave address is assigned to the higher 7 bits of IIC0.
16.5.3 Transfer direction specification
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction.
When this transfer direction specification bit has a value of “0”, it indicates that the master device is transmitting
data to a slave device. When the transfer direction specification bit has a value of “1”, it indicates that the master
device is receiving data from a slave device.
Figure 16-15. Transfer Direction Specification
SCL0
1
2
3
4
5
6
7
8
SDA0
A6
A5
A4
A3
A2
A1
A0
R/W
9
Transfer direction specification
Note
INTIIC0
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
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16.5.4 Acknowledge (ACK)
ACK is used to check the status of serial data at the transmission and reception sides.
The reception side returns ACK each time it has received 8-bit data.
The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception
side, it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been
detected can be checked by using bit 2 (ACKD0) of IIC status register 0 (IICS0).
When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a
slave does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops
transmission. If ACK is not returned, the possible causes are as follows.
Reception was not performed normally.
The final data item was received.
The reception side specified by the address does not exist.
To generate ACK, the reception side makes the SDA0 line low at the ninth clock (indicating normal reception).
Automatic generation of ACK is enabled by setting bit 2 (ACKE0) of IIC control register 0 (IICC0) to 1. Bit 3 (TRC0)
of the IICS0 register is set by the data of the eighth bit that follows 7-bit address information. Usually, set ACKE0 to 1
for reception (TRC0 = 0).
If a slave can receive no more data during reception (TRC0 = 0) or does not require the next data item, then the
slave must inform the master, by clearing ACKE0 to 0, that it will not receive any more data.
When the master does not require the next data item during reception (TRC0 = 0), it must clear ACKE0 to 0 so that
ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any
more data (transmission will be stopped).
Figure 16-16. ACK
SCL0
1
2
3
4
5
6
7
8
9
SDA0
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
When the local address is received, ACK is automatically generated, regardless of the value of ACKE0. When an
address other than that of the local address is received, ACK is not generated (NACK).
When an extension code is received, ACK is generated if ACKE0 is set to 1 in advance.
How ACK is generated when data is received differs as follows depending on the setting of the wait timing.
• When 8-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 0):
By setting ACKE0 to 1 before releasing the wait state, ACK is generated at the falling edge of the eighth clock of
the SCL0 pin.
• When 9-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 1):
ACK is generated by setting ACKE0 to 1 in advance.
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16.5.5 Stop condition
When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition.
A stop condition is a signal that the master device generates to the slave device when serial transfer has been
completed. When the device is used as a slave, stop conditions can be detected.
Figure 16-17. Stop Condition
SCL0
H
SDA0
A stop condition is generated when bit 0 (SPT0) of IIC control register 0 (IICC0) is set to 1. When the stop
condition is detected, bit 0 (SPD0) of IIC status register 0 (IICS0) is set to 1 and INTIIC0 is generated when bit 4
(SPIE0) of IICC0 is set to 1.
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16.5.6 Wait
The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or
receive data (i.e., is in a wait state).
Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been
canceled for both the master and slave devices, the next data transfer can begin.
Figure 16-18. Wait (1/2)
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(master transmits, slave receives, and ACKE0 = 1)
Master
Master returns to high
impedance but slave
is in wait state (low level).
IIC0
Wait after output
of ninth clock
IIC0 data write (cancel wait)
6
SCL0
7
8
9
1
2
3
Slave
Wait after output
of eighth clock
FFH is written to IIC0 or WREL0 is set to 1
IIC0
SCL0
ACKE0
H
Transfer lines
Wait from slave
SCL0
6
7
8
SDA0
D2
D1
D0
Wait from master
9
ACK
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2
3
D7
D6
D5
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Figure 16-18. Wait (2/2)
(2) When master and slave devices both have a nine-clock wait
(master transmits, slave receives, and ACKE0 = 1)
Master
Master and slave both wait
after output of ninth clock
IIC0 data write (cancel wait)
IIC0
SCL0
6
7
8
9
1
2
3
Slave
FFH is written to IIC0 or WREL0 is set to 1
IIC0
SCL0
ACKE0
H
Wait from
master and
slave
Transfer lines
SCL0
6
7
8
9
SDA0
D2
D1
D0
ACK
Wait from slave
1
D7
2
3
D6
D5
Generate according to previously set ACKE0 value
Remark
ACKE0: Bit 2 of IIC control register 0 (IICC0)
WREL0: Bit 5 of IIC control register 0 (IICC0)
A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IIC control register 0 (IICC0).
Normally, the receiving side cancels the wait state when bit 5 (WREL0) of IICC0 is set to 1 or when FFH is written
to IIC shift register 0 (IIC0), and the transmitting side cancels the wait state when data is written to IIC0.
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STT0) of IICC0 to 1
• By setting bit 0 (SPT0) of IICC0 to 1
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16.5.7 Canceling wait
The I2C usually cancels a wait state by the following processing.
• Writing data to IIC shift register 0 (IIC0)
• Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait)
• Setting bit 1 (STT0) of IIC0 register (generating start condition)Note
• Setting bit 0 (SPT0) of IIC0 register (generating stop condition)Note
Note Master only
When the above wait canceling processing is executed, the I2C cancels the wait state and communication is
resumed.
To cancel a wait state and transmit data (including addresses), write the data to IIC0.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IIC0 control
register 0 (IICC0) to 1.
To generate a restart condition after canceling a wait state, set bit 1 (STT0) of IICC0 to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of IICC0 to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to IIC0 after canceling a wait state by setting WREL0 to 1, an incorrect value may be
output to SDA0 because the timing for changing the SDA0 line conflicts with the timing for writing IIC0.
In addition to the above, communication is stopped if IICE0 is cleared to 0 when communication has been aborted,
so that the wait state can be canceled.
If the I2C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of
IICC0, so that the wait state can be canceled.
16.5.8 Interrupt request (INTIIC0) generation timing and wait control
The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated
and the corresponding wait control, as shown in Table 16-3.
Table 16-3. INTIIC0 Generation Timing and Wait Control
WTIM0
During Slave Device Operation
Address
0
1
9
Notes 1, 2
9
Notes 1, 2
Data Reception
8
Note 2
9
Note 2
During Master Device Operation
Data Transmission
Address
Data Reception
Data Transmission
8
Note 2
9
8
8
9
Note 2
9
9
9
Notes 1. The slave device’s INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to slave address register 0 (SVA0).
At this point, ACK is generated regardless of the value set to IICC0’s bit 2 (ACKE0). For a slave device
that has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIIC0 is generated at the falling edge of the 9th
clock, but wait does not occur.
2. If the received address does not match the contents of slave address register 0 (SVA0) and extension
code is not received, neither INTIIC0 nor a wait occurs.
Remark
The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and
wait control are both synchronized with the falling edge of these clock signals.
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(1) During address transmission/reception
• Slave device operation:
Interrupt and wait timing are determined depending on the conditions described in
Notes 1 and 2 above, regardless of the WTIM0 bit.
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
the WTIM0 bit.
(2) During data reception
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(3) During data transmission
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(4) Wait cancellation method
The four wait cancellation methods are as follows.
• Writing data to IIC shift register 0 (IIC0)
• Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait)
• Setting bit 1 (STT0) of IIC0 register (generating start condition)Note
• Setting bit 0 (SPT0) of IIC0 register (generating stop condition)
Note
Note Master only.
When an 8-clock wait has been selected (WTIM0 = 0), the presence/absence of the acknowledge generation
must be determined prior to wait cancellation.
(5) Stop condition detection
INTIIC0 is generated when a stop condition is detected (only when SPIE0 = 1).
16.5.9 Address match detection method
In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave
address.
Address match can be detected automatically by hardware. An interrupt request (INTIIC0) occurs when a local
address has been set to slave address register 0 (SVA0) and when the address set to SVA0 matches the slave
address sent by the master device, or when an extension code has been received.
16.5.10 Error detection
In I2C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by IIC shift register 0
(IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted IIC0 data
to enable detection of transmission errors. A transmission error is judged as having occurred when the compared
data values do not match.
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16.5.11 Extension code
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag
(EXC0) is set to 1 for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge
of the eighth clock. The local address stored in slave address register 0 (SVA0) is not affected.
(2) If “11110××0” is set to SVA0 by a 10-bit address transfer and “11110××0” is transferred from the master device,
the results are as follows. Note that INTIIC0 occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC0 = 1
• Seven bits of data match:
Remark
COI0 = 1
EXC0: Bit 5 of IIC status register 0 (IICS0)
COI0: Bit 4 of IIC status register 0 (IICS0)
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension
code, such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave
device, set bit 6 (LREL0) of the IIC control register 0 (IICC0) to 1 to set the standby mode for the next
communication operation.
Table 16-4. Extension Code Bit Definitions
Slave Address
R/W Bit
Description
0000 000
0
General call address
0000 000
1
Start byte
0000 001
×
C-BUS address
0000 010
×
Address that is reserved for different bus format
1111 0XX
×
10-bit slave address specification
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16.5.12 Arbitration
When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set
to 1), communication among the master devices is performed as the number of clocks are adjusted until the data
differs. This kind of operation is called arbitration.
When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in IIC status register 0 (IICS0)
is set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high
impedance, which releases the bus.
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a
stop condition is detected, etc.) and the ALD0 = 1 setting that has been made by software.
For details of interrupt request timing, see 16.5.17 Timing of I2C interrupt request (INTIIC0) occurrence.
Remark
STD0: Bit 1 of IIC status register 0 (IICS0)
STT0: Bit 1 of IIC control register 0 (IICC0)
Figure 16-19. Arbitration Timing Example
Master 1
Hi-Z
SCL0
Hi-Z
SDA0
Master 2
Master 1 loses arbitration
SCL0
SDA0
Transfer lines
SCL0
SDA0
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Table 16-5. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration
Interrupt Request Generation Timing
At falling edge of eighth or ninth clock following byte transfer
During address transmission
Note 1
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
Note 2
When stop condition is detected during data transfer
When stop condition is generated (when SPIE0 = 1)
When data is at low level while attempting to generate a restart
At falling edge of eighth or ninth clock following byte transfer
Note 1
condition
When stop condition is detected while attempting to generate a
Note 2
When stop condition is generated (when SPIE0 = 1)
restart condition
When data is at low level while attempting to generate a stop
At falling edge of eighth or ninth clock following byte transfer
Note 1
condition
When SCL0 is at low level while attempting to generate a
restart condition
Notes 1. When WTIM0 (bit 3 of IIC control register 0 (IICC0)) = 1, an interrupt request occurs at the falling edge
of the ninth clock. When WTIM0 = 0 and the extension code’s slave address is received, an interrupt
request occurs at the falling edge of the eighth clock.
2. When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation.
Remark
SPIE0: Bit 4 of IIC control register 0 (IICC0)
16.5.13 Wakeup function
The I2C bus slave function is a function that generates an interrupt request signal (INTIIC0) when a local address
and extension code have been received.
This function makes processing more efficient by preventing unnecessary INTIIC0 signal from occurring when
addresses do not match.
When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has
generated a start condition) to a slave device.
However, when a stop condition is detected, bit 4 (SPIE0) of IIC control register 0 (IICC0) is set regardless of the
wakeup function, and this determines whether interrupt requests are enabled or disabled.
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16.5.14 Communication reservation
(1) When communication reservation function is enabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 0)
To start master device communications when not currently using a bus, a communication reservation can be
made to enable transmission of a start condition when the bus is released. There are two modes under which
the bus is not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released when bit 6 (LREL0) of IIC control register 0 (IICC0) was set to 1).
If bit 1 (STT0) of IICC0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition
is automatically generated and wait state is set.
If an address is written to IIC shift register 0 (IIC0) after bit 4 (SPIE0) of IICC0 was set to 1, and it was detected
by generation of an interrupt request signal (INTIIC0) that the bus was released (detection of the stop
condition), then the device automatically starts communication as the master. Data written to IIC0 before the
stop condition is detected is invalid.
When STT0 has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
• If the bus has been released ........................................ a start condition is generated
• If the bus has not been released (standby mode)......... communication reservation
Check whether the communication reservation operates or not by using MSTS0 (bit 7 of IIC status register 0
(IICS0)) after STT0 is set to 1 and the wait time elapses.
The wait periods, which should be set via software, are listed in Table 16-6.
Table 16-6. Wait Periods
CLX0
SMC0
CL01
CL00
Wait Period
0
0
0
0
46 clocks
0
0
0
1
86 clocks
0
0
1
0
172 clocks
0
0
1
1
34 clocks
0
1
0
0
30 clocks
0
1
0
1
0
1
1
0
60 clocks
0
1
1
1
12 clocks
1
1
0
0
18 clocks
1
1
0
1
1
1
1
0
36 clocks
Figure 16-20 shows the communication reservation timing.
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Figure 16-20. Communication Reservation Timing
Program processing
Write to
IIC0
STT0 = 1
CommuniHardware processing cation
reservation
SCL0
1
2
3
4
Set SPD0
and
INTIIC0
5
6
7
8
9
Set
STD0
1
2
3
4
5
6
SDA0
Generate by master device with bus mastership
Remark
IIC0:
IIC shift register 0
STT0:
Bit 1 of IIC control register 0 (IICC0)
STD0:
Bit 1 of IIC status register 0 (IICS0)
SPD0: Bit 0 of IIC status register 0 (IICS0)
Communication reservations are accepted via the following timing. After bit 1 (STD0) of IIC status register 0
(IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IIC control register 0
(IICC0) to 1 before a stop condition is detected.
Figure 16-21. Timing for Accepting Communication Reservations
SCL0
SDA0
STD0
SPD0
Standby mode
Figure 16-22 shows the communication reservation protocol.
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Figure 16-22. Communication Reservation Protocol
DI
SET1 STT0
Define communication
reservation
Wait
(Communication reservation)Note
Yes
MSTS0 = 0?
Sets STT0 flag (communication reservation)
Defines that communication reservation is in effect
(defines and sets user flag to any part of RAM)
Secures wait period set by software (see Table 16-6).
Confirmation of communication reservation
No
(Generate start condition)
Cancel communication
reservation
MOV IIC0, #××H
Clear user flag
IIC0 write operation
EI
Note The communication reservation operation executes a write to IIC shift register 0 (IIC0) when a stop
condition interrupt request occurs.
Remark
STT0:
Bit 1 of IIC control register 0 (IICC0)
MSTS0: Bit 7 of IIC status register 0 (IICS0)
IIC0:
IIC shift register 0
(2) When communication reservation function is disabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 1)
When bit 1 (STT0) of IIC control register 0 (IICC0) is set to 1 when the bus is not used in a communication
during bus communication, this request is rejected and a start condition is not generated. The following two
statuses are included in the status where bus is not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released when bit 6 (LREL0) of IICC0 was set to 1)
To confirm whether the start condition was generated or request was rejected, check STCF (bit 7 of IICF0).
The time shown in Table 16-7 is required until STCF is set to 1 after setting STT0 = 1. Therefore, secure the
time by software.
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Table 16-7. Wait Periods
CL01
CL00
Wait Period
0
0
6 clocks
0
1
6 clocks
1
0
12 clocks
1
1
3 clocks
16.5.15 Other cautions
(1) When STCEN (bit 1 of IIC flag register 0 (IICF0)) = 0
Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status (IICBSY (bit 6 of IICF0) =
1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition
has been detected to a master device communication mode, first generate a stop condition to release the bus,
then perform master device communication.
When using multiple masters, it is not possible to perform master device communication when the bus has not
been released (when a stop condition has not been detected).
Use the following sequence for generating a stop condition.
Set IIC clock selection register 0 (IICCL0).
Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
Set bit 0 (SPT0) of IICC0 to 1.
(2) When STCEN = 1
Immediately after I2C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized
regardless of the actual bus status. To generate the first start condition (STT0 (bit 1 of IIC control register 0
(IICC0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other
communications.
(3) If other I2C communications are already in progress
If I2C operation is enabled and the device participates in communication already in progress when the SDA0
pin is low and the SCL0 pin is high, the macro of I2C recognizes that the SDA0 pin has gone low (detects a
start condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned,
but this interferes with other I2C communications. To avoid this, start I2C in the following sequence.
Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request signal (INTIIC0) when the
stop condition is detected.
Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I2C.
Wait for detection of the start condition.
Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after setting IICE0 to 1), to forcibly
disable detection.
(4) Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0 of IICL0), and CLX0
(bit 0 of IICX0) before enabling the operation (IICE0 = 1). To change the transfer clock frequency, clear
IICE0 to 0 once.
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CHAPTER 16 SERIAL INTERFACE IIC0
(5) Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before they are cleared to 0 is
prohibited.
(6) When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt request is generated
when the stop condition is detected. Transfer is started when communication data is written to IIC0
after the interrupt request is generated. Unless the interrupt is generated when the stop condition is
detected, the device stops in the wait state because the interrupt request is not generated when
communication is started. However, it is not necessary to set SPIE0 to 1 when MSTS0 (bit 7 of IICS0) is
detected by software.
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16.5.16 Communication operations
(1) Master operation (single-master system)
Figure 16-23. Master Operation Flowchart (Single-Master System)
START
Initializing I2C busNote
Initial setting
Setting port
Sets each pin in the I2C mode (see 16.3 (7) Port mode register 6 (PM6)).
IICX0 ← 0XH
IICCL0 ← XXH
Selects a transfer clock.
SVA0 ← XXH
Sets a local address.
IICF0 ← 0XH
Setting STCEN, IICRSV = 0
Sets a start condition.
IICC0 ← XXH
ACKE0 = WTIM0 = SPIE0 = 1
IICE0 = 1
STCEN = 1?
No
SPT0 = 1
Yes
STT0 = 1
Prepares for starting communication
(generates a start condition).
Writing IIC0
Starts communication
(specifies an address and transfer
direction).
INTIIC0
interrupt occurs?
No
Waits for detection of acknowledge.
INTIIC0
Interrupt occurs?
Yes
Prepares for starting
communication
(generates a stop condition).
No
Waits for detection of
the stop condition.
Yes
No
ACKD0 = 1?
Communication processing
Yes
TRC0 = 1?
No
ACKE0 = 1
WTIM0 = 0
Yes
Writing IIC0
INTIIC0
interrupt occurs?
Starts transmission.
WREL0 = 1
No
Waits for data transmission.
INTIIC0
interrupt occurs?
Yes
Yes
ACKD0 = 1?
No
Starts reception.
No
Waits for data
reception.
Reading IIC0
Yes
No
End of transfer?
No
End of transfer?
Yes
Yes
Restart?
Yes
ACKE0 = 0
WTIM0 = WREL0 = 1
No
SPT0 = 1
INTIIC0
interrupt occurs?
Yes
No
Waits for detection
of acknowledge.
END
2
Note Release (SCL0 and SDA0 pins = high level) the I C bus in conformance with the specifications of the
product that is communicating. If EEPROM is outputting a low level to the SDA0 pin, for example, set the
SCL0 pin in the output port mode, and output a clock pulse from the output port until the SDA0 pin is
constantly at high level.
Remark
Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
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(2) Master operation (multi-master system)
Figure 16-24. Master Operation Flowchart (Multi-Master System) (1/3)
START
Setting port
Sets each pin in the I2C mode (see 16.3 (7) Port mode register 6 (PM6)).
IICX0 ← 0XH
IICCL0 ← XXH
Selects a transfer clock.
SVA0 ← XXH
Sets a local address.
IICF0 ← 0XH
Setting STCEN and IICRSV
Sets a start condition.
Initial setting
IICC0 ← XXH
ACKE0 = WTIM0 = SPIE0 = 1
IICE0 = 1
Checking bus statusNote
Releases the bus for a specific period.
Bus status is
being checked.
No
No
STCEN = 1?
INTIIC0
interrupt occurs?
Prepares for starting
communication
(generates a stop condition).
SPT0 = 1
Yes
Yes
SPD0 = 1?
INTIIC0
interrupt occurs?
No
Yes
Yes
Slave operation
SPD0 = 1?
No
Waits for detection
of the stop condition.
No
Yes
1
Master operation
starts?
Waits for a communication
Slave operation
• Waiting to be specified as a slave by other master
• Waiting for a communication start request (depends on user program)
No
(No communication start request)
Yes
(Communication start request)
SPIE0 = 0
INTIIC0
interrupt occurs?
SPIE0 = 1
No
Waits for a communication request.
Yes
IICRSV = 0?
No
Slave operation
Yes
A
B
Enables reserving Disables reserving
communication.
communication.
Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period
of one frame). If the SDA0 pin is constantly at low level, decide whether to release the I2C bus (SCL0 and
SDA0 pins = high level) in conformance with the specifications of the product that is communicating.
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Figure 16-24. Master Operation Flowchart (Multi-Master System) (2/3)
A
Enables reserving communication.
STT0 = 1
Secure wait time by software
(see Table 16-6).
Wait
Communication processing
Prepares for starting communication
(generates a start condition).
MSTS0 = 1?
No
Yes
INTIIC0
interrupt occurs?
Yes
No
Wait state after stop condition
was detected and start condition
was generated by the communication
reservation function.
EXC0 = 1 or COI0 =1?
Yes
C
Slave operation
B
Disables reserving communication.
IICBSY = 0?
No
Yes
D
Communication processing
No
Waits for bus release
(communication being reserved).
STT0 = 1
Wait
STCF = 0?
Yes
Prepares for starting communication
(generates a start condition).
Secure wait time by software
(see Table 16-7).
No
INTIIC0
interrupt occurs?
No
Waits for bus release
Yes
C
EXC0 = 1 or COI0 =1?
No
Detects a stop condition.
Yes
Slave operation
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CHAPTER 16 SERIAL INTERFACE IIC0
Figure 16-24. Master Operation Flowchart (Multi-Master System) (3/3)
C
Writing IIC0
INTIIC0
interrupt occurs?
Starts communication
(specifies an address and transfer direction).
No
Waits for detection of ACK.
Yes
MSTS0 = 1?
No
Yes
No
2
ACKD0 = 1?
Yes
TRC0 = 1?
No
ACKE0 = 1
WTIM0 = 0
Yes
Communication processing
WTIM0 = 1
WREL0 = 1
Writing IIC0
Starts transmission.
INTIIC0
interrupt occurs?
INTIIC0
interrupt occurs?
No
Waits for data transmission.
Yes
MSTS0 = 1?
No
Waits for data reception.
Yes
MSTS0 = 1?
No
No
Yes
Yes
ACKD0 = 1?
Starts reception.
2
2
Reading IIC0
No
Transfer end?
No
Yes
Yes
No
WTIM0 = WREL0 = 1
ACKE0 = 0
Transfer end?
Yes
Restart?
INTIIC0
interrupt occurs?
No
No
Waits for detection of ACK.
Yes
SPT0 = 1
Yes
MSTS0 = 1?
STT0 = 1
END
Yes
No
2
Communication processing
C
2
EXC0 = 1 or COI0 = 1?
Yes
Slave operation
No
1
Does not participate
in communication.
Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission
and reception formats.
2. To use the device as a master in a multi-master system, read the MSTS0 bit each time interrupt
INTIIC0 has occurred to check the arbitration result.
3. To use the device as a slave in a multi-master system, check the status by using the IICS0 and IICF0
registers each time interrupt INTIIC0 has occurred, and determine the processing to be performed
next.
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CHAPTER 16 SERIAL INTERFACE IIC0
(3) Slave operation
The processing procedure of the slave operation is as follows.
Basically, the slave operation is event-driven. Therefore, processing by the INTIIC0 interrupt (processing that
must substantially change the operation status such as detection of a stop condition during communication) is
necessary.
In the following explanation, it is assumed that the extension code is not supported for data communication. It
is also assumed that the INTIIC0 interrupt servicing only performs status transition processing, and that actual
data communication is performed by the main processing.
INTIIC0
Flag
Interrupt servicing
Setting
Main processing
IIC0
Data
Setting
Therefore, data communication processing is performed by preparing the following three flags and passing
them to the main processing instead of INTIIC0.
Communication mode flag
This flag indicates the following two communication statuses.
• Clear mode:
Status in which data communication is not performed
• Communication mode: Status in which data communication is performed (from valid address detection
to stop condition detection, no detection of ACK from master, address
mismatch)
Ready flag
This flag indicates that data communication is enabled. Its function is the same as the INTIIC0 interrupt
for ordinary data communication.
This flag is set by interrupt servicing and cleared by the main
processing. Clear this flag by interrupt servicing when communication is started. However, the ready flag
is not set by interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted
without the flag being cleared (an address match is interpreted as a request for the next data).
Communication direction flag
This flag indicates the direction of communication. Its value is the same as TRC0.
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The main processing of the slave operation is explained next.
Start serial interface IIC0 and wait until communication is enabled. When communication is enabled, execute
communication by using the communication mode flag and ready flag (processing of the stop condition and
start condition is performed by an interrupt. Here, check the status by using the flags).
The transmission operation is repeated until the master no longer returns ACK. If ACK is not returned from the
master, communication is completed.
For reception, the necessary amount of data is received. When communication is completed, ACK is not
returned as the next data. After that, the master generates a stop condition or restart condition. Exit from the
communication status occurs in this way.
Figure 16-25. Slave Operation Flowchart (1)
START
IICX0 ← 0XH
Selects a transfer clock.
IICCL0 ← XXH
SVA0 ← XXH
Sets a local address.
IICF0 ← 0XH
Setting IICRSV
Sets a start condition.
IICC0 ← XXH
ACKE0 = WTIM0 = 1
SPIE0 = 0, IICE0 = 1
No
Communication
mode flag = 1?
Yes
Communication
direction flag = 1?
No
Yes
WREL0 = 1
Writing IIC0
No
Starts
transmission.
Communication
mode flag = 1?
Communication
mode flag = 1?
No
Yes
Yes
No
Starts
reception.
Communication
direction flag = 1?
Communication
direction flag = 1?
No
Yes
No
Yes
No
Ready flag = 1?
Ready flag = 1?
Yes
Yes
Reading IIC0
Clearing ready flag
Yes
Clearing ready flag
ACKD0 = 1?
No
Clearing communication
mode flag
WREL0 = 1
Remark
Conform to the specifications of the product that is in communication, regarding the transmission and
reception formats.
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An example of the processing procedure of the slave with the INTIIC0 interrupt is explained below (processing
is performed assuming that no extension code is used). The INTIIC0 interrupt checks the status, and the
following operations are performed.
Communication is stopped if the stop condition is issued.
If the start condition is issued, the address is checked and communication is completed if the address
does not match.
If the address matches, the communication mode is set, wait is cancelled, and
processing returns from the interrupt (the ready flag is cleared).
For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I2C bus
remaining in the wait state.
Remark
to above correspond to to in Figure 16-26 Slave Operation Flowchart (2).
Figure 16-26. Slave Operation Flowchart (2)
INTIIC0 generated
Yes
Yes
SPD0 = 1?
No
STD0 = 1?
No
No
COI0 = 1?
Yes
Set ready flag
Communication direction flag
← TRC0
Set communication mode flag
Clear ready flag
Clear communication direction
flag, ready flag, and
communication mode flag
Interrupt servicing completed
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16.5.17 Timing of I2C interrupt request (INTIIC0) occurrence
The timing of transmitting or receiving data and generation of interrupt request signal INTIIC0, and the value of the
IICS0 register when the INTIIC0 signal is generated are shown below.
Remark
ST:
Start condition
AD6 to AD0: Address
390
R/W:
Transfer direction specification
ACK:
Acknowledge
D7 to D0:
Data
SP:
Stop condition
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CHAPTER 16 SERIAL INTERFACE IIC0
(1) Master device operation
(a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception)
(i) When WTIM0 = 0
SPT0 = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
D7 to D0
2
ACK
SP
3
4
5
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B
3: IICS0 = 1000×000B (Sets WTIM0 to 1)Note
4: IICS0 = 1000××00B (Sets SPT0 to 1)
5: IICS0 = 00000001B
Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt
request signal.
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1
SPT0 = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
2
ACK
SP
3
4
1: IICS0 = 1000×110B
2: IICS0 = 1000×100B
3: IICS0 = 1000××00B (Sets SPT0 to 1)
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
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(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart)
(i) When WTIM0 = 0
STT0 = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
ST
2
3
SPT0 = 1
↓
AD6 to AD0 R/W ACK
D7 to D0
4
ACK
SP
5
6
7
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets WTIM0 to 1)Note 1
3: IICS0 = 1000××00B (Clears WTIM0 to 0Note 2, sets STT0 to 1)
4: IICS0 = 1000×110B
5: IICS0 = 1000×000B (Sets WTIM0 to 1)Note 3
6: IICS0 = 1000××00B (Sets SPT0 to 1)
7: IICS0 = 00000001B
Notes 1. To generate a start condition, set WTIM0 to 1 and change the timing for generating the INTIIC0
interrupt request signal.
2. Clear WTIM0 to 0 to restore the original setting.
3. To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0
interrupt request signal.
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1
STT0 = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
ST
SPT0 = 1
↓
AD6 to AD0 R/W ACK
2
1: IICS0 = 1000×110B
2: IICS0 = 1000××00B (Sets STT0 to 1)
3: IICS0 = 1000×110B
4: IICS0 = 1000××00B (Sets SPT0 to 1)
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
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D7 to D0
3
ACK
SP
4
5
CHAPTER 16 SERIAL INTERFACE IIC0
(c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission)
(i) When WTIM0 = 0
SPT0 = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
2
ACK
SP
3
4
5
1: IICS0 = 1010×110B
2: IICS0 = 1010×000B
3: IICS0 = 1010×000B (Sets WTIM0 to 1)Note
4: IICS0 = 1010××00B (Sets SPT0 to 1)
5: IICS0 = 00000001B
Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt
request signal.
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1
SPT0 = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
2
ACK
SP
3
4
1: IICS0 = 1010×110B
2: IICS0 = 1010×100B
3: IICS0 = 1010××00B (Sets SPT0 to 1)
4: IICS0 = 00001001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
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CHAPTER 16 SERIAL INTERFACE IIC0
(2) Slave device operation (slave address data reception)
(a) Start ~ Address ~ Data ~ Data ~ Stop
(i) When WTIM0 = 0
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
2
ACK
SP
3
4
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 0001×000B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
2
1: IICS0 = 0001×110B
2: IICS0 = 0001×100B
3: IICS0 = 0001××00B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
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ACK
SP
3
4
CHAPTER 16 SERIAL INTERFACE IIC0
(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, matches with SVA0)
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
ST
AD6 to AD0 R/W ACK
2
D7 to D0
3
ACK
SP
4
5
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 0001×110B
4: IICS0 = 0001×000B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1 (after restart, matches with SVA0)
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
ST
AD6 to AD0 R/W ACK
2
D7 to D0
3
ACK
SP
4
5
1: IICS0 = 0001×110B
2: IICS0 = 0001××00B
3: IICS0 = 0001×110B
4: IICS0 = 0001××00B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
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CHAPTER 16 SERIAL INTERFACE IIC0
(c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, does not match address (= extension code))
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
ST
AD6 to AD0 R/W ACK
2
D7 to D0
3
ACK
SP
4
5
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 0010×010B
4: IICS0 = 0010×000B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1 (after restart, does not match address (= extension code))
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
ST
AD6 to AD0 R/W ACK
2
1: IICS0 = 0001×110B
2: IICS0 = 0001××00B
3: IICS0 = 0010×010B
4: IICS0 = 0010×110B
5: IICS0 = 0010××00B
6: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
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3
D7 to D0
4
ACK
SP
5
6
CHAPTER 16 SERIAL INTERFACE IIC0
(d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, does not match address (= not extension code))
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
ST
AD6 to AD0 R/W ACK
2
D7 to D0
ACK
SP
3
4
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 00000110B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1 (after restart, does not match address (= not extension code))
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
ST
AD6 to AD0 R/W ACK
2
D7 to D0
3
ACK
SP
4
1: IICS0 = 0001×110B
2: IICS0 = 0001××00B
3: IICS0 = 00000110B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
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(3) Slave device operation (when receiving extension code)
The device is always participating in communication when it receives an extension code.
(a) Start ~ Code ~ Data ~ Data ~ Stop
(i) When WTIM0 = 0
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
2
ACK
SP
3
4
1: IICS0 = 0010×010B
2: IICS0 = 0010×000B
3: IICS0 = 0010×000B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1
ST
AD6 to AD0 R/W ACK
1
D7 to D0
ACK
2
D7 to D0
3
1: IICS0 = 0010×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010×100B
4: IICS0 = 0010××00B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
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Don’t care
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SP
4
5
CHAPTER 16 SERIAL INTERFACE IIC0
(b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, matches SVA0)
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
ST
AD6 to AD0 R/W ACK
2
D7 to D0
3
ACK
SP
4
5
1: IICS0 = 0010×010B
2: IICS0 = 0010×000B
3: IICS0 = 0001×110B
4: IICS0 = 0001×000B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1 (after restart, matches SVA0)
ST
AD6 to AD0 R/W ACK
1
D7 to D0
ACK
2
ST
AD6 to AD0 R/W ACK
3
D7 to D0
4
ACK
SP
5
6
1: IICS0 = 0010×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010××00B
4: IICS0 = 0001×110B
5: IICS0 = 0001××00B
6: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
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(c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, extension code reception)
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
ST
AD6 to AD0 R/W ACK
2
D7 to D0
3
ACK
SP
4
5
1: IICS0 = 0010×010B
2: IICS0 = 0010×000B
3: IICS0 = 0010×010B
4: IICS0 = 0010×000B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1 (after restart, extension code reception)
ST
AD6 to AD0 R/W ACK
1
D7 to D0
ACK
2
ST
AD6 to AD0 R/W ACK
3
1: IICS0 = 0010×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010××00B
4: IICS0 = 0010×010B
5: IICS0 = 0010×110B
6: IICS0 = 0010××00B
7: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
400
Don’t care
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D7 to D0
5
ACK
SP
6
7
CHAPTER 16 SERIAL INTERFACE IIC0
(d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, does not match address (= not extension code))
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
ST
AD6 to AD0 R/W ACK
2
D7 to D0
ACK
SP
3
4
1: IICS0 = 00100010B
2: IICS0 = 00100000B
3: IICS0 = 00000110B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1 (after restart, does not match address (= not extension code))
ST
AD6 to AD0 R/W ACK
1
D7 to D0
ACK
2
ST
AD6 to AD0 R/W ACK
3
D7 to D0
4
ACK
SP
5
1: IICS0 = 00100010B
2: IICS0 = 00100110B
3: IICS0 = 00100×00B
4: IICS0 = 00000110B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
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(4) Operation without communication
(a) Start ~ Code ~ Data ~ Data ~ Stop
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
D7 to D0
ACK
SP
1
1: IICS0 = 00000001B
Remark
: Generated only when SPIE0 = 1
(5) Arbitration loss operation (operation as slave after arbitration loss)
When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request
signal INTIIC0 has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data
(i) When WTIM0 = 0
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
2
1: IICS0 = 0101×110B
2: IICS0 = 0001×000B
3: IICS0 = 0001×000B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
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3
SP
4
CHAPTER 16 SERIAL INTERFACE IIC0
(ii) When WTIM0 = 1
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
ACK
2
SP
3
4
1: IICS0 = 0101×110B
2: IICS0 = 0001×100B
3: IICS0 = 0001××00B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(b) When arbitration loss occurs during transmission of extension code
(i) When WTIM0 = 0
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
D7 to D0
2
ACK
3
SP
4
1: IICS0 = 0110×010B
2: IICS0 = 0010×000B
3: IICS0 = 0010×000B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
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(ii) When WTIM0 = 1
ST
AD6 to AD0 R/W ACK
1
D7 to D0
ACK
2
D7 to D0
ACK
3
SP
4
5
1: IICS0 = 0110×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010×100B
4: IICS0 = 0010××00B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(6) Operation when arbitration loss occurs (no communication after arbitration loss)
When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request
signal INTIIC0 has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data (when WTIM0 = 1)
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
D7 to D0
1
2: IICS0 = 00000001B
: Always generated
: Generated only when SPIE0 = 1
404
SP
2
1: IICS0 = 01000110B
Remark
ACK
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CHAPTER 16 SERIAL INTERFACE IIC0
(b) When arbitration loss occurs during transmission of extension code
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
D7 to D0
ACK
SP
1
2
1: IICS0 = 0110×010B
Sets LREL0 = 1 by software
2: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(c) When arbitration loss occurs during transmission of data
(i) When WTIM0 = 0
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
2
ACK
SP
3
1: IICS0 = 10001110B
2: IICS0 = 01000000B
3: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
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CHAPTER 16 SERIAL INTERFACE IIC0
(ii) When WTIM0 = 1
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
ACK
SP
2
3
1: IICS0 = 10001110B
2: IICS0 = 01000100B
3: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
(d) When loss occurs due to restart condition during data transfer
(i) Not extension code (Example: unmatches with SVA0)
ST
AD6 to AD0 R/W ACK
D7 to Dn
ST
AD6 to AD0 R/W ACK
1
2
1: IICS0 = 1000×110B
2: IICS0 = 01000110B
3: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
n = 6 to 0
406
D7 to D0
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SP
3
CHAPTER 16 SERIAL INTERFACE IIC0
(ii) Extension code
ST
AD6 to AD0 R/W ACK
D7 to Dn
ST
AD6 to AD0 R/W ACK
1
2
D7 to D0
ACK
SP
3
1: IICS0 = 1000×110B
2: IICS0 = 01100010B
Sets LREL0 = 1 by software
3: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
n = 6 to 0
(e) When loss occurs due to stop condition during data transfer
ST
AD6 to AD0 R/W ACK
D7 to Dn
SP
1
2
1: IICS0 = 10000110B
2: IICS0 = 01000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
n = 6 to 0
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CHAPTER 16 SERIAL INTERFACE IIC0
(f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition
(i) When WTIM0 = 0
STT0 = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
2
D7 to D0
3
ACK
D7 to D0
ACK
SP
4
5
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets WTIM0 to 1)
3: IICS0 = 1000×100B (Clear WTIM0 to 0)
4: IICS0 = 01000000B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1
STT0 = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
2
ACK
D7 to D0
3
1: IICS0 = 1000×110B
2: IICS0 = 1000×100B (Sets STT0 to 1)
3: IICS0 = 01000100B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
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Don’t care
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SP
4
CHAPTER 16 SERIAL INTERFACE IIC0
(g) When arbitration loss occurs due to a stop condition when attempting to generate a restart
condition
(i) When WTIM0 = 0
STT0 = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
2
SP
3
4
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets WTIM0 to 1)
3: IICS0 = 1000××00B (Sets STT0 to 1)
4: IICS0 = 01000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1
STT0 = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
SP
2
3
1: IICS0 = 1000×110B
2: IICS0 = 1000××00B (Sets STT0 to 1)
3: IICS0 = 01000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
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CHAPTER 16 SERIAL INTERFACE IIC0
(h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition
(i) When WTIM0 = 0
SPT0 = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
2
D7 to D0
ACK
3
D7 to D0
ACK
SP
4
5
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets WTIM0 to 1)
3: IICS0 = 1000×100B (Clear WTIM0 to 0)
4: IICS0 = 01000100B
5: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
Don’t care
(ii) When WTIM0 = 1
SPT0 = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
2
ACK
D7 to D0
3
1: IICS0 = 1000×110B
2: IICS0 = 1000×100B (Sets SPT0 to 1)
3: IICS0 = 01000100B
4: IICS0 = 00000001B
Remark
: Always generated
: Generated only when SPIE0 = 1
×:
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ACK
SP
4
CHAPTER 16 SERIAL INTERFACE IIC0
16.6 Timing Charts
When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several
slave devices as its communication partner.
After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)),
which specifies the data transfer direction, and then starts serial communication with the slave device.
Figures 16-27 and 16-28 show timing charts of the data communication.
IIC shift register 0 (IIC0)’s shift operation is synchronized with the falling edge of the serial clock (SCL0). The
transmit data is transferred to the SO0 latch and is output (MSB first) via the SDA0 pin.
Data input via the SDA0 pin is captured into IIC0 at the rising edge of SCL0.
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CHAPTER 16 SERIAL INTERFACE IIC0
Figure 16-27. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (1/3)
(1) Start condition ~ address
Processing by master device
IIC0 ← address
IIC0
IIC0 ← data
ACKD0
STD0
SPD0
WTIM0
H
ACKE0
H
MSTS0
STT0
SPT0
L
WREL0
L
INTIIC0
TRC0
H
Transmit
Transfer lines
1
SCL0
2
3
4
5
6
7
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDA0
8
9
1
2
3
4
W
ACK
D7
D6
D5
D4
Start condition
Processing by slave device
IIC0 ← FFH Note
IIC0
ACKD0
STD0
SPD0
WTIM0
H
ACKE0
H
MSTS0
L
STT0
L
SPT0
L
Note
WREL0
INTIIC0
(When EXC0 = 1)
TRC0
L
Receive
Note To cancel slave wait, write “FFH” to IIC0 or set WREL0.
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CHAPTER 16 SERIAL INTERFACE IIC0
Figure 16-27. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (2/3)
(2) Data
Processing by master device
IIC0 ← data
IIC0
IIC0 ← data
ACKD0
STD0
L
SPD0
L
WTIM0
H
ACKE0
H
MSTS0
H
STT0
L
SPT0
L
WREL0
L
INTIIC0
TRC0
H
Transmit
Transfer lines
SCL0
8
9
1
2
3
4
5
6
7
8
9
SDA0
D0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
1
2
3
D7
D6
D5
Processing by slave device
IIC0 ← FFH Note
IIC0
IIC0 ← FFH Note
ACKD0
STD0
L
SPD0
L
WTIM0
H
ACKE0
H
MSTS0
L
STT0
L
SPT0
L
Note
WREL0
Note
INTIIC0
TRC0
L
Receive
Note To cancel slave wait, write “FFH” to IIC0 or set WREL0.
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CHAPTER 16 SERIAL INTERFACE IIC0
Figure 16-27. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (3/3)
(3) Stop condition
Processing by master device
IIC0 ← data
IIC0
IIC0 ← address
ACKD0
STD0
SPD0
WTIM0
H
ACKE0
H
MSTS0
STT0
SPT0
WREL0
L
INTIIC0
(When SPIE0 = 1)
TRC0
H Transmit
Transfer lines
SCL0
1
2
3
4
5
6
7
8
9
SDA0
D7
D6
D5
D4
D3
D2
D1
D0
ACK
IIC0 ← FFH Note
Start
condition
IIC0 ← FFH Note
ACKD0
STD0
SPD0
WTIM0
H
ACKE0
H
MSTS0
L
STT0
L
SPT0
L
Note
WREL0
Note
INTIIC0
(When SPIE0 = 1)
TRC0
L Receive
Note To cancel slave wait, write “FFH” to IIC0 or set WREL0.
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2
AD6 AD5
Stop
condition
Processing by slave device
IIC0
1
CHAPTER 16 SERIAL INTERFACE IIC0
Figure 16-28. Example of Slave to Master Communication
(When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3)
(1) Start condition ~ address
Processing by master device
IIC0 ← address
IIC0
IIC0 ← FFH Note
ACKD0
STD0
SPD0
WTIM0
L
ACKE0
H
MSTS0
STT0
L
SPT0
Note
WREL0
INTIIC0
TRC0
Transfer lines
1
SCL0
2
3
4
5
6
7
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDA0
8
9
R
ACK
1
D7
2
3
4
5
6
D6
D5
D4
D3
D2
Start condition
Processing by slave device
IIC0 ← data
IIC0
ACKD0
STD0
SPD0
WTIM0
H
ACKE0
H
MSTS0
L
STT0
L
SPT0
L
WREL0
L
INTIIC0
TRC0
Note To cancel master wait, write “FFH” to IIC0 or set WREL0.
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CHAPTER 16 SERIAL INTERFACE IIC0
Figure 16-28. Example of Slave to Master Communication
(When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3)
(2) Data
Processing by master device
IIC0 ← FFH Note
IIC0
IIC0 ← FFH Note
ACKD0
STD0
L
SPD0
L
WTIM0
L
ACKE0
H
MSTS0
H
STT0
L
SPT0
L
Note
WREL0
Note
INTIIC0
L Receive
TRC0
Transfer lines
SCL0
8
9
SDA0
D0
ACK
1
D7
2
3
4
5
6
7
8
9
D6
D5
D4
D3
D2
D1
D0
ACK
1
D7
2
3
D6
D5
Processing by slave device
IIC0 ← data
IIC0
IIC0 ← data
ACKD0
STD0
L
SPD0
L
WTIM0
H
ACKE0
H
MSTS0
L
STT0
L
SPT0
L
WREL0
L
INTIIC0
TRC0
H Transmit
Note To cancel master wait, write “FFH” to IIC0 or set WREL0.
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CHAPTER 16 SERIAL INTERFACE IIC0
Figure 16-28. Example of Slave to Master Communication
(When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3)
(3) Stop condition
Processing by master device
IIC0 ← address
IIC0 ← FFH Note
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
Note
WREL0
INTIIC0
(When SPIE0 = 1)
TRC0
Transfer lines
SCL0
1
2
3
4
5
6
7
8
SDA0
D7
D6
D5
D4
D3
D2
D1
D0
9
1
AD6
NACK
Stop
condition
Start
condition
Processing by slave device
IIC0 ← data
IIC0
ACKD0
STD0
SPD0
WTIM0
H
ACKE0
H
MSTS0
L
STT0
L
SPT0
L
WREL0
INTIIC0
(When SPIE0 = 1)
TRC0
Note To cancel master wait, write “FFH” to IIC0 or set WREL0.
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CHAPTER 16 SERIAL INTERFACE IIC0
16.7 Communication with LCD Controller/Driver
2
With the 78K0/LE2, setting to LCD controller/driver is performed via the I C bus interface. Therefore reading and
writing to the LCD controller/driver registers can be performed.
16.7.1 System configuration
The system configuration of the LCD controller/driver in the 78K0/LE2 is illustrated in Figure 16-29.
Figure 16-29. System configuration
78K0/LE2
LCD controller
/driver
CPU
VDD
P60/SCL0
LSCL
P61/SDA0
LSDA
VDD
SDA0
SCL0
Serial clock
Serial data bus
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CHAPTER 16 SERIAL INTERFACE IIC0
16.7.2 Write operation
2
The processing procedure, format, and operation of writing to the LCD controller/driver via the I C bus interface are
explained below.
The LCD controller/driver register to be accessed can be specified with the slave ID and address (see Figure 17-3).
(1) Processing procedure
Figure 16-30. Processing procedure of Write Operation
LCD controller/driver side (slave)
CPU side (master)
Transfer direction
ST detected?
ST generation
No
Yes
Slave ID transmission
Slave ID reception
ID matched?
No
Yes
No
— M
ACKACK‘
transmission
ACK reception
Yes
Address transmission
No
Address reception
ACK reception
ACK transmission
Yes
No
WD transmission
WD reception
ACK reception
ACK transmission
Yes
Completed?
No
Yes
SP generation
SP detection
No
Yes
End
Remark
ST:
End
Start condition
RST: Restart condition
SP:
Stop condition
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CHAPTER 16 SERIAL INTERFACE IIC0
(2) Communication format
Write data to each register on the LCD controller/driver starting from the start condition, slave ID, address,
write data, then stop condition in that order.
Figure 16-31. Communication Format for Write Operation (When Writing Twice)
Access
target
ST
Slave ID
R/W
ACK
Address
ACK
LCDCTL
ST
0
1
1
1
0
0
0
0
ACK
A7
A6
A5
A4
A3
A2
A1
A0
ACK
LCDSEG
ST
0
1
1
1
0
0
1
0
ACK
A7
A6
A5
A4
A3
A2
A1
A0
ACK
Write data 1
ACK
Write data 2
ACK
SP
D7
D6
D5
D4
D3
D2
D1
D0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
SP
D7
D6
D5
D4
D3
D2
D1
D0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
SP
Address
LCDCTL : A7, A6, A5, A4, A3, A2, A1, A0
LCDSEG: A7, A6, A5, A4, A3, A2, A1, A0
Note
Note
Address
LCDCTL : (A7, A6, A5, A4, A3, A2, A1, A0) + 1
LCDSEG: (A7, A6, A5, A4, A3, A2, A1, A0) + 1
With the 78K0/LE2, the address is incremented by one based on the register read/write start address by
continuously performing read/write access from transmissions of the start condition to stop condition. With
this function, the address does not need to be set each time.
Cautions 1. Generate a stop condition if an access like the one shown below is made.
• An access made in a format other than specified
• An access made with a slave ID other than specified
2. When SDA0 is fixed at the low level output status due to noise, input 0 to P130 (bit 0 of port
register 13) to reset the LCD controller/driver.
Remark
ST:
Start condition
SP:
Stop condition
A7 to A0: Addresses for LCDCTL or LCDSEG
420
User’s Manual U17734EJ2V0UD
CHAPTER 16 SERIAL INTERFACE IIC0
(3) Operation
The operation flow when transmitting write data twice is shown below.
Steps to correspond to to in Figure 16-31.
The start condition is transmitted.
The slave ID is transmitted (from the 1st to 7th clocks).
R/W information (0) is transmitted (at the 8th clock).
An acknowledge signal is received (at the rising edge of the 9th clock).
The write start address is transmitted (from the 1st to 8th clocks following ).
An acknowledge signal is received (at the rising edge of the 9th clock).
Write data is transmitted (first time) (from the 1st to 8th clocks following ).
An acknowledge signal is received (at the rising edge of the 9th clock).
Write data is transmitted (second time) (from the 1st to 8th clocks following ).
(The address is automatically incremented by 1.)
An acknowledge signal is received (at the rising edge of the 9th clock).
The stop condition is transmitted.
Figures 16-32 shows the timing chart of the write operation.
Figure 16-32. Timing Chart of Write Operation
Start condition
Master
Setup
Setup
SCL0
1
8
SDA0
ID6
W
IIC shift
register 0
xxH
xxH
xxH
9
xxH
Write to IIC shift register 0
IIC bus
xxH
Stop condition
Setup
1
8
0
A0
xxH
9
xxH
xxH
Write to IIC shift register 0
1
8
WD7
WD0
xxH
9
xxH
xxH
Write to IIC shift register 0
Stop condition
Start condition
1
SCL
ID6
SDA
8
9
1
R
ACK
8
9
0
8
9
1
8
9
A0
ACK
WD7
WD0
ACK
8
9
1
8
9
Slave
1
LSCL
ACK
LSDA
IIC shift
register
1
xxH
xxH
xxH
ACK
xxH
xxH
User’s Manual U17734EJ2V0UD
ACK
xxH
xxH
421
CHAPTER 16 SERIAL INTERFACE IIC0
16.7.3 Read operation
2
The processing procedure, format, and operation of reading the LCD controller/driver via the I C bus interface are
explained below.
The LCD controller/driver register to be accessed can be specified with the slave ID and address (see Figure 17-3).
(1) Processing procedure
Figure 16-33. Processing procedure of Read Operation
LCD controller/driver side (slave)
CPU side (master)
Transfer direction
No
ST generation
ST detected?
Slave ID transmission
Slave ID reception
Yes
No
ID matched?
Yes
No
ACKACK‘
transmission
—M
ACK reception
Yes
Address reception
Address transmission
No
ACK transmission
ACK reception
Yes
No
RST generation
RST detected?
Slave ID transmission
Slave ID reception
Yes
No
ID matched?
Yes
No
ACK reception
ACK transmission
Yes
RD reception
ACK transmission
RD transmission
Yes
ACK reception
No
No
SP detection
SP generation
Yes
End
Remark
ST:
End
Start condition
RST: Restart condition
SP:
422
Yes
Stop condition
User’s Manual U17734EJ2V0UD
No
CHAPTER 16 SERIAL INTERFACE IIC0
(2) Communication format
Read data from each register on the LCD controller/driver starting from the start condition, slave ID, address,
restart condition, slave ID, read data, then stop condition in that order.
Figure 16-34. Communication Format for Read Operation (When Reading Twice)
Access
target
ST
Slave ID
R/W
ACK
Address
ACK
LCDCTL
ST
0 1 1 1 0 0 0
0
ACK
A7
A6
A5
A4
A3
A2
A1
A0
ACK
LCDSEG
ST
0 1 1 1 0 0 1
0
ACK
A7
A6
A5
A4
A3
A2
A1
A0
ACK
RST
Slave ID
R/W
ACK
Read dara 1
ACK
RST
0 1
1 1 0
0 0
1
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
RST
0 1
1 1 0
0 1
1
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Address
LCDCTL : A7, A6, A5, A4, A3, A2, A1, A0
LCDSEG: A7, A6, A5, A4, A3, A2, A1, A0
Read data2
ACK
SP
D7
D6
D5
D4
D3
D2
D1
D0
NAK
SP
D7
D6
D5
D4
D3
D2
D1
D0
NAK
SP
Note
Address
LCDCTL : (A7, A6, A5, A4, A3, A2, A1, A0) + 1
LCDSEG: (A7, A6, A5, A4, A3, A2, A1, A0) + 1
Note
With the 78K0/LE2, the address is incremented by one based on the register read/write start address by
continuously performing read/write access from transmissions of the start condition to stop condition. With
this function, the address does not need to be set each time.
Cautions 1. Generate a stop condition if an access like the one shown below is made.
• An access made in a format other than specified
• An access made with a slave ID other than specified
2. When SDA0 is fixed at the low level output status due to noise, input 0 to P130 (bit 0 of port
register 13) to reset the LCD controller/driver.
Remark
ST:
Start condition
RST:
Restart condition
SP:
Stop condition
A7 to A0: Addresses for LCDCTL or LCDSEG
User’s Manual U17734EJ2V0UD
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CHAPTER 16 SERIAL INTERFACE IIC0
(3) Operation
The operation flow when receiving read data twice is shown below.
Steps to correspond to to in Figure 16-34.
The start condition is transmitted.
The slave ID is transmitted (first time) (from the 1st to 7th clocks).
R/W information (0) is transmitted (at the 8th clock).
An acknowledge signal is received (at the rising edge of the 9th clock).
The read start address is transmitted (from the 1st to 8th clocks following ).
An acknowledge signal is received (at the rising edge of the 9th clock).
The restart condition is transmitted.
The slave ID is transmitted (second time) (from the 1st to 7th clocks following ).
R/W information (1) is transmitted (at the 8th clock).
An acknowledge signal is received (at the rising edge of the 9th clock).
Read data is received (first time) (from the 1st to 8th clocks following ).
An acknowledge signal is transmitted (from the falling edge of the 8th clock to the falling edge of the 9th
clock).
Read data is received (second time) (from the 1st to 8th clocks following ).
(The address is automatically incremented by 1.)
Stop the acknowledge signal transmission.
Note
The stop condition is transmitted.
Note
424
Do not transmit the acknowledge signal when completing data reception.
User’s Manual U17734EJ2V0UD
CHAPTER 16 SERIAL INTERFACE IIC0
Figures 16-35 shows the timing chart of the read operation.
Figure 16-35. Timing Chart of Read Operation
Start condition
Master
Setup
Setup
SCL0
1
2
7
8
SDA0
ID6
ID5
ID0
W
IIC shift
register 0
xxH
xxH
xxH
xxH
9
xxH
xxH
1
2
8
0
0
A0
xxH
xxH
xxH
9
xxH
xxH
Write to IIC shift register 0
IIC bus
Start condition
SCL
1
2
7
8
9
1
2
8
9
SDA
ID6
ID5
ID0
W
ACK
0
0
A0
ACK
LSCL
1
2
7
8
9
1
2
8
9
Slave
ACK
LSDA
IIC shift
register
xxH
xxH
ACK
xxH
xxH
xxH
xxH
xxH
xxH
(Continued from above)
Master
Stop condition
Restart condition
Setup
Setup
SCL0
1
8
SDA0
ID6
R
IIC shift
register 0
xxH
xxH
9
1
8
9
1
8
9
ACK
xxH
xxH
FFH
xxH
xxH
Write FFH or WREL0 = 1
Write to IIC shift register 0
IIC bus
Setup
FFH
xxH
xxH
xxH
Write FFH or WREL0 = 1
Stop condition
Restart condition
SCL
1
SDA
ID6
8
9
R
ACK
8
9
1
RD7
8
9
RD0
ACK
8
9
1
RD7
8
9
RD0
Slave
LSCL
1
LSDA
IIC shift
register
1
ACK
xxH
xxH
xxH
RD7
xxH
Write to IIC shift register
1
RD0
xxH
xxH
RD7
xxH
Write to IIC shift register
User’s Manual U17734EJ2V0UD
8
9
RD0
xxH
xxH
xxH
Write to IIC shift register
425
CHAPTER 17 LCD CONTROLLER/DRIVER
17.1 Functions of LCD Controller/Driver
The functions of the LCD controller/driver in the 78K0/LE2 are as follows.
(1)
The LCD driver reference voltage generator can switch internal voltage boosting, external resistance division,
(2)
Automatic output of segment and common signals based on automatic display data memory read
(3)
Five different display modes:
and internal resistance division.
• Static
• 1/2 duty (1/2 bias)
• 1/3 duty (1/2 bias)
• 1/3 duty (1/3 bias)
• 1/4 duty (1/3 bias)
(4)
Four different frame frequencies, selectable in each display mode
(5)
Up to 20 segment signal outputs (S0 to S19) and four common signal outputs (COM0 to COM3)
Table 17-1 lists the maximum number of pixels that can be displayed in each display mode.
Table 17-1. Maximum Number of Pixels
LCD Driver Reference
Bias
Number of
Voltage Generator
Mode
Time Slices
• External resistance division
−
Static
Common Signals Used
COM0 (COM1 to COM3)
Number of
Maximum Number of
Segments
Pixels
20
20 (20 segment signals,
Note 1
1 common signal)
• Internal resistance division
1/2
2
COM0, COM1
40 (20 segment signals,
2 common signals)
• Internal voltage boosting
• External resistance division
1/3
3
COM0 to COM2
3
COM0 to COM2
4
COM0 to COM3
Notes 1. 2-digit LCD panel, each digit having an 8-segment
configuration.
2. 5-digit LCD panel, each digit having a 4-segment
configuration.
3. 7-digit LCD panel, each digit having a 3-segment
configuration.
4. 10-digit LCD panel, each digit having a 2-segment
426
60 (20 segment signals,
3 common signals)
configuration.
User’s Manual U17734EJ2V0UD
Note 3
80 (20 segment signals,
4 common signals)
• Internal resistance division
Note 2
Note 4
CHAPTER 17 LCD CONTROLLER/DRIVER
17.2 Configuration of LCD Controller/Driver
The LCD controller/driver consists of the following hardware.
The LCD controller/driver includes of two blocks: LCDSEG block for controlling segments, and LCDCTL block for
controlling LCD register setting and mode setting.
Table 17-2. Configuration of LCD Controller/Driver
Item
Configuration
LCD
Display outputs
20 segment signals
controller/
(LCDSEG)
4 common signals (COM0 to COM3)
Control registers
LCD mode setting register (LCDMD)
(LCDCTL)
LCD display mode register (LCDM)
driver
LCD clock control register (LCDC)
LCD voltage boost control register 0 (VLCG0)
CPU
Control registers
Clock output selection register (CKS)
Port register 13 (P13)
Port mode register 14 (PM14)
Figure 17-1. Hardware Configuration of LCD Controller/Driver
LCD Controller
SCL0
LCDSEG
SDA0
CPU
I2C Bus Interface
LCD Driver
LCDCTL
Reset Input
P13
CKS
PM14
fPCL
Clock Input
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427
428
Figure 17-2. Block Diagram of LCD Controller/Driver
Internal bus
LCD mode setting
register (LCDMD)
LCD clock control
register (LCDC)
SEGSET2 SEGSET1 SEGSET0 MDSET1 MDSET0
LCD display mode
register (LCDM)
LCDC3 LCDC2 LCDC1 LCDC0
Selector
fLCD
User’s Manual U17734EJ2V0UD
fLCD
26
Clock
generator for
boosting
Prescaler
fLCD
27
fLCD
28
fLCD
29
LCD
clock LCDCL
selector
Timing
controller
-------
VLCON
3210
selector
Segment voltage
controller
3210
selector
------LCDON
-------
LCDON
-------
Booster
circuit
Segment voltage
controller
LCD drive voltage controller
Common voltage
controller
-------------
Common driver
Segment
driver
COM0 COM1 COM2 COM3
S0
-------
Segment
driver
- - - - - - - - - CAPH CAPL
VLC2 VLC1 VLC0
Remark fPCL: The clock generated by the clock output controller
S19
CHAPTER 17 LCD CONTROLLER/DRIVER
fPCL
fPCL/2
fPCL/22
3
2
2
2
LCDON SCOC VLCON LCDM2 LCDM1 LCDM0
LCD voltage boost control
Display data memory
register 0 (VLCG0)
LCDSEG's 13H
LCDSEG's
00H
CTSEL1 CTSEL0 GAIN
7 6 5 4 3 2 1 0 ------- 7 6 5 4 3 2 1 0
CHAPTER 17 LCD CONTROLLER/DRIVER
Figure 17-3 shows the controll register of LCD controller/driver, and Figure 17-4 shows the LCD display RAM.
Figure 17-3. Controll Register of LCD Controller/Driver
Address
Bit
Register
7
6
5
4
3
2
1
0
CTSEL1
CTSEL0
0
0
0
0
0
GAIN
02H
0
0
0
0
LCDC3
LCDC2
LCDC1
LCDC0
→ LCDC
01H
LCDON
SCOC
VLCON
0
0
LCDM2
LCDM1
LCDM0
→ LCDM
0
0
0
LCDCTL's 03H
LCDCTL's 00H
SEGSET2 SEGSET1 SEGSET0
→ VLCG0
MDSET1 MDSET0 → LCDMD
Figure 17-4. LCD Display RAM
Address
Bit
Segment
7
6
5
4
0
0
0
0
→ S19
12H
0
0
0
0
→ S18
11H
0
0
0
0
→ S17
10H
0
0
0
0
→ S16
0FH
0
0
0
0
→ S15
0EH
0
0
0
0
→ S14
0DH
0
0
0
0
→ S13
0CH
0
0
0
0
→ S12
0BH
0
0
0
0
→ S11
0AH
0
0
0
0
→ S10
09H
0
0
0
0
→ S9
08H
0
0
0
0
→ S8
07H
0
0
0
0
→ S7
06H
0
0
0
0
→ S6
05H
0
0
0
0
→ S5
04H
0
0
0
0
→ S4
03H
0
0
0
0
→ S3
02H
0
0
0
0
→ S2
01H
0
0
0
0
→ S1
0
0
0
0
→ S0
LCDSEG's 13H
LCDSEG's 00H
Common
3
2
1
0
↑
↑
↑
↑
COM3
COM2
COM1
COM0
Remark Bits 4 to 7 are fixed to 0.
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CHAPTER 17 LCD CONTROLLER/DRIVER
17.3 Registers Controlling LCD Controller/Driver
The following seven registers are used to control the LCD controller/driver.
• LCD mode setting register (LCDMD)
• LCD display mode register (LCDM)
• LCD clock control register (LCDC)
• LCD voltage boost control register 0 (VLCG0)
• Clock output selection register (CKS)
• Port register 13 (P13)
• Port mode register 14 (PM14)
(1)
LCD mode setting register (LCDMD)
LCDMD sets the number of segments and the LCD reference voltage generator.
LCDMD is set using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDMD to 00H.
Figure 17-5. Format of LCD Mode Setting Register
After reset: 00H R/W
Address: LCDCTL's 00H
Symbol
7
6
5
4
3
2
1
0
LCDMD
SEGSET2
SEGSET1
SEGSET0
0
0
0
MDSET1
MDSET0
SEGSET2
SEGSET1
SEGSET0
1
0
0
Other than above
Segment number setting
20
Setting prohibited
MDSET1
MDSET0
LCD reference voltage generator selection
0
0
External resistance division method
0
1
Internal resistance division method
1
×
Internal voltage boosting method
Cautions 1. Bits 2 to 4 must be set to 0.
2. LCDMD can be set only once after a reset release.
430
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CHAPTER 17 LCD CONTROLLER/DRIVER
(2)
LCD display mode register (LCDM)
LCDM specifies whether to enable display operation.
It also specifies whether to enable segment
pin/common pin output, booster circuit operation, and the display mode.
LCDM is set using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDM to 00H.
Figure 17-6. Format of LCD Display Mode Register
Address: LCDCTL's 01H
After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
LCDM
LCDON
SCOC
VLCON
0
0
LCDM2
LCDM1
LCDM0
LCDON
LCD display enable/disable
0
Display off (all segment outputs are deselected.)
1
Display on
SCOC
Segment pin/common pin output control
Note
0
Output ground level to segment/common pin
1
Output deselect level to segment pin and LCD waveform to common pin
VLCON
Booster circuit operation enable/disable
0
No internal voltage boosting
1
Internal voltage boosting enabled
LCDM2
LCDM1
LCDM0
Note
LCD controller/driver display mode selection
Resistance division method
Number of
Voltage boosting method
Bias mode
Number of
time slices
Bias mode
time slices
0
0
0
4
1/3
4
1/3
0
0
1
3
1/3
3
1/3
0
1
0
2
1/2
4
1/3
0
1
1
3
1/2
3
1/3
1
0
0
Static
Other than above
Setting prohibited
Setting prohibited
Note When the LCD display panel is not used, SCOC and VLCON must be set to 0 to conserve power.
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CHAPTER 17 LCD CONTROLLER/DRIVER
Cautions 1. Bits 3 and 4 must be set to 0.
2. When operating VLCON, follow the procedure described below.
A. To stop voltage boosting after switching display status from on to off:
1) Set to display off status by setting LCDON = 0.
2) Disable outputs of all the segment buffers and common buffers by setting
SCOC = 0.
3) Stop voltage boosting by setting VLCON = 0.
B. To stop voltage boosting during display on status:
Setting prohibited. Be sure to stop voltage boosting after setting display off.
C. To set display on from voltage boosting stop status:
1) Start voltage boosting by setting VLCON = 1, then wait for voltage boost wait time
(tVAWAIT) (see CHAPTER 27 ELECTRICAL SPECIFICATIONS).
2) Set all the segment buffers and common buffers to non-display output status
by setting SCOC = 1.
3) Set display on by setting LCDON = 1.
(3) LCD clock control register (LCDC)
LCDC specifies the LCD source clock and LCD clock.
The frame frequency is determined according to the LCD clock and the number of time slices.
LCDC is set using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDC to 00H.
Figure 17-7. Format of LCD Clock Control Register
Address: LCDCTL's 02H
After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
LCDC
0
0
0
0
LCDC3
LCDC2
LCDC1
LCDC0
LCDC3
LCDC2
LCD source clock (fLCD) selection
0
×
fPCL (Clock generated by clock output controller)
1
0
fPCL/2
1
1
fPCL/22
LCDC1
LCDC0
Note
LCD clock (LCDCL) selection
6
0
0
fLCD/2
0
1
fLCD/27
1
0
fLCD/28
1
1
fLCD/29
Note Specify an LCD source clock (fLCD) frequency of at least 32 kHz.
Cautions 1. Bits 4 to 7 must be set to 0.
2. Before changing the LCDC setting, be sure to stop voltage boosting (VLCON = 0).
3. Set the frame frequency to 128 Hz or lower.
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CHAPTER 17 LCD CONTROLLER/DRIVER
(4)
LCD voltage boost control register 0 (VLCG0)
VLCG0 controls the voltage boost level during the voltage boost operation.
VLCG0 is set with an 8-bit memory manipulation instruction.
Reset signal generation sets VLCG0 to 00H.
Figure 17-8. Format of LCD Voltage Boost Control Register 0
Address: LCDCTL's 03H
After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
VLCG0
CTSEL1
CTSEL0
0
0
0
0
0
GAIN
Note1
GAIN
Reference voltage (VLC2) level selection
0
1.5 V (specification of the LCD panel used is 4.5 V.)
1
1.0 V (specification of the LCD panel used is 3 V.)
CTSEL1
Contrast adjustment (TYP.)
CTSEL0
VLC0
Note2
VLC1
VLC2
GAIN = 0
GAIN = 1
GAIN = 0
GAIN = 1
GAIN = 0
GAIN = 1
1
0
4.89 V
3.39 V
3.27 V
2.27 V
1.63 V
1.13 V
1
1
4.71 V
3.21 V
3.13 V
2.13 V
1.57 V
1.07 V
0
0
4.50 V
3.00 V
3.00 V
2.00 V
1.50 V
1.00 V
0
1
4.29 V
2.79 V
2.87 V
1.87 V
1.43 V
0.93 V
Notes 1. Select the settings according to the specifications of the LCD panel that is used.
2. Set these bits so that LVDD after voltage boosting becomes 2.0 to 5.5 V.
Cautions 1. Bits 1 to 5 must be set to 0.
2. Before changing the VLCG0 setting, be sure to stop voltage boosting (VLCON = 0).
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CHAPTER 17 LCD CONTROLLER/DRIVER
(5)
Clock output selection register (CKS)
CKS enables/disables the clock output (PCL) to the LCD controller/driver, and sets the output clock.
CKS is set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets CKS to 00H.
Figure 17-9. Format of Clock Output Selection Register
Address: FF40H
After reset: 00H
R/W
Symbol
7
6
5
3
2
1
0
CKS
0
0
0
CLOE
CCS3
CCS2
CCS1
CCS0
CLOE
PM140
Specification of enable/disable for clock output
to LCD controller/driver
0
Clock output to LCD controller/driver enabled
Other than above
Clock output to LCD controller/driver disabled
1
CCS3
CCS2
CCS1
Note
PCL output clock selection
CCS0
fSUB =
fPRS =
fPRS =
32.768 kHz
10 MHz
20 MHz
6
0
1
1
0
fPRS/2
0
1
1
1
fPRS/27
1
0
0
0
fSUB
Other than above
Note
-
156.25 kHz 312.5 kHz
78.125 kHz 156.25 kHz
32.768 kHz
-
Setting prohibited
Enabling/disabling the PCL clock output is specified by combining the PM140 settings (see (7) Port
mode register 14 (PM14)).
Cautions 1. Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
2. Bits 5 to 7 must be set to 0.
Remarks 1. fPRS: Peripheral hardware clock oscillation frequency
2. fSUB: Subsystem clock oscillation frequency
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CHAPTER 17 LCD CONTROLLER/DRIVER
(6)
Port register 13 (P13)
P13 controls the reset for the LCD controller/driver.
When using the LCD controller/driver, set P130 to 1.
P13 is set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets P13 to 00H.
Figure 17-10. Format of Port Register 13
Address: FF0DH
After reset: 00H (Output latch) R/W
Symbol
7
6
5
4
3
2
1
0
P13
0
0
0
0
0
0
0
P130
LCD controller/driver reset control
P130
0
Reset status set
1
Reset status released
(7) Port mode register 14 (PM14)
PM14 controls the clock output to the LCD controller/driver.
When using the LCD controller/driver, set PM140 to 0.
PM14 is set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM14 to FFH.
Figure 17-11. Format of Port Mode Register 14
Address: FF2EH
After reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
PM14
1
1
1
1
1
1
1
PM140
PM140
Clock output control to LCD controller/driver
0
Clock output to LCD controller/driver enabled
1
Clock output to LCD controller/driver disabled
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CHAPTER 17 LCD CONTROLLER/DRIVER
17.4 Setting LCD Controller/Driver
Set the LCD controller/driver using the following procedure.
(1) Voltage boosting method
• Operation flow for transition of reset status to display status in LCD controller/driver
Set P130 = 1 to release the reset status.
Set the output clock using the clock output selection register (CKS).
Set PM140 = 0 to set output mode.
Set CLOE (bit 4 of CKS) to 1 to enable the clock output.
Set MDSET1 (bit 1 of LCDMD) to 1 to set the internal voltage boosting method
(initial setting: external resistance division method)
Set the initial values to the LCD display data area (bits 0 to 3) in the LCD display RAM.
Set the display mode using LCDM0, LCDM1, and LCDM2 (bits 0, 1, and 2 of LCD display mode register
(LCDM)) (1/2 bias mode and static mode cannot be set).
Set the LCD clock using LCD clock control register (LCDC).
Set the voltage boost level and contrasts using LCD voltage boost control register 0 (VLCG0).
GAIN = 0: VLC0 = 4.5 V, VLC1 = 3 V, VLC2 = 1.5 V
GAIN = 1: VLC0 = 3 V, VLC1 = 2 V, VLC2 = 1 V
Set VLCON (bit 5 of LCDM) to 1 to enable voltage boosting.
Wait for voltage boost wait time (tVAWAIT) from setting of VLCON (see CHAPTER 27 ELECTRICAL
SPECIFICATIONS).
Set SCOC (bit 6 of LCDM) to 1 to output the deselect voltage.
Set LCDON (bit 7 of LCDM) to 1 and set data to the data memory in accordance with the display
contents, after the output corresponding to each data memory is started.
Subsequent to this procedure, set the data to be displayed in the data memory.
2
Remark The register can be set in 1-bit units because the I C bus is used for setting.
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CHAPTER 17 LCD CONTROLLER/DRIVER
(2) Resistance division method
• Operation flow for transition of reset status to display status in LCD controller/driver
Set P130 = 1 to release the reset status.
Set the output clock using the clock output selection register (CKS).
Set PM140 = 0 to set output mode.
Set CLOE (bit 4 of CKS) to 1 to enable the clock output.
Set to the internal voltage boosting method using MDSET0 and MDSET1 (bit 0 and 1 of LCDMD).
(MDSET0, MDSET1 = 0, 0: External resistance division method,
MDSET0, MDSET1 = 0, 1: Internal resistance division method)
Set the initial values to the LCD display data area (bits 0 to 3) in the LCD display RAM.
Set the display mode using LCDM0, LCDM1, and LCDM2 (bits 0, 1, and 2 of LCD display mode register
(LCDM)).
Set the LCD clock using LCD clock control register (LCDC).
Set SCOC (bit 6 of LCDM) to 1 to output the deselect voltage.
Set LCDON (bit 7 of LCDM) to 1 and set data to the data memory in accordance with the display
contents, after the output corresponding to each data memory is started.
Subsequent to this procedure, set the data to be displayed in the data memory.
2
Remark The register can be set in 1-bit units because the I C bus is used for setting.
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CHAPTER 17 LCD CONTROLLER/DRIVER
17.5 LCD Display Data Memory
The LCD display data memory is mapped at addresses 00H to 13H of LCDSEG. Data in the LCD display data
memory can be displayed on the LCD panel using the LCD controller/driver.
Figure 17-12 shows the relationship between the contents of the LCD display data memory and the
segment/common outputs.
Figure 17-12. Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs
Address
b7
b6
b5
b4
b3
b2
b1
b0
LCDSEG's 13H
S19
LCDSEG's 12H
S18
LCDSEG's 11H
S17
LCDSEG's 10H
S16
LCDSEG's 02H
S2
LCDSEG's 01H
S1
LCDSEG's 00H
S0
COM3
COM2
COM1
COM0
Caution No memory is allocated to the higher 4 bits of the LCD display data memory. Be sure to set
there bits to 0.
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CHAPTER 17 LCD CONTROLLER/DRIVER
17.6 Common and Segment Signals
Each pixel of the LCD panel turns on when the potential difference between the corresponding common and
segment signals becomes higher than a specific voltage (LCD drive voltage, VLCD). The pixels turn off when the
potential difference becomes lower than VLCD.
Applying DC voltage to the common and segment signals of an LCD panel causes deterioration. To avoid this
problem, this LCD panel is driven by AC voltage.
(1)
Common signals
Each common signal is selected sequentially according to a specified number of time slices at the timing
listed in Table 17-3. In the static display mode, the same signal is output to COM0 to COM3.
In the two-time-slice mode, leave the COM2 and COM3 pins open. In the three-time-slice mode, leave the
COM3 pin open.
Table 17-3. COM Signals
COM Signal
COM0
COM1
COM2
COM3
Number of Time Slices
Static display mode
Open
Two-time-slice mode
Open
Open
Three-time-slice mode
Four-time-slice mode
(2)
Segment signals
The segment signals correspond to 20 bytes of LCD display data memory (00H to 13H of LCDSEG). Bits 0,
1, 2, and 3 of each byte are read in synchronization with COM0, COM1, COM2, and COM3, respectively. If a
bit is 1, it is converted to the select voltage, and if it is 0, it is converted to the deselect voltage. The
conversion results are output to the segment pins (S0 to S19).
Check, with the information given above, what combination of front-surface electrodes (corresponding to the
segment signals) and rear-surface electrodes (corresponding to the common signals) forms display patterns
in the LCD display data memory, and write the bit data that corresponds to the desired display pattern on a
one-to-one basis.
LCD display data memory bits 1 to 3, bits 2 and 3, and bit 3 are not used for LCD display in the static display,
two-time slot, and three-time slot modes, respectively. So these bits can be used for purposes other than
display.
LCD display data memory bits 4 to 7 are fixed to 0.
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CHAPTER 17 LCD CONTROLLER/DRIVER
(3)
Output waveforms of common and segment signals
The voltages listed in Table 17-4 are output as common and segment signals.
When both common and segment signals are at the select voltage, a display on-voltage of ±VLCD is obtained.
The other combinations of the signals correspond to the display off-voltage.
Table 17-4. LCD Drive Voltage
(a) Static display mode
Segment Signal
Select Signal Level
Deselect Signal Level
LVSS/VLC0
VLC0/LVSS
Common Signal
VLC0/LVSS
–VLCD/+VLCD
0 V/0 V
(b) 1/2 bias method
Segment Signal
Select Signal Level
Deselect Signal Level
LVSS/VLC0
VLC0/LVSS
Common Signal
Select signal level
Deselect signal level
VLC0/LVSS
VLC1 = VLC2
–VLCD/+VLCD
–
1
2
VLCD/+
1
2
0 V/0 V
VLCD
+
1
2
VLCD/–
1
2
VLCD
(c) 1/3 bias method
Segment Signal
Select Signal Level
Deselect Signal Level
LVSS/VLC0
VLC1/VLC2
Common Signal
Select signal level
VLC0/LVSS
–VLCD/+VLCD
Deselect signal level
VLC2/VLC1
–
440
1
3
VLCD/+
1
3
–
VLCD
User’s Manual U17734EJ2V0UD
–
1
3
1
3
VLCD/+
VLCD/+
1
3
1
3
VLCD
VLCD
CHAPTER 17 LCD CONTROLLER/DRIVER
Figure 17-13 shows the common signal waveforms, and Figure 17-14 shows the voltages and phases of the
common and segment signals.
Figure 17-13. Common Signal Waveforms
(a) Static display mode
VLC0
COMn
VLCD
(Static display)
LVSS
TF = T
T: One LCD clock period
TF: Frame frequency
(b) 1/2 bias method
VLC0
COMn
VLC2
VLCD
(Two-time slot mode)
LVSS
TF = 2 × T
VLC0
COMn
VLC2
VLCD
(Three-time slot mode)
LVSS
TF = 3 × T
T: One LCD clock period
TF: Frame frequency
(c) 1/3 bias method
VLC0
COMn
VLC1
VLCD
VLC2
LVSS
(Three-time slot mode)
TF = 3 × T
VLC0
COMn
VLC1
(Four-time slot mode)
VLC2
LVSS
VLCD
TF = 4 × T
T: One LCD clock period
TF: Frame frequency
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CHAPTER 17 LCD CONTROLLER/DRIVER
Figure 17-14. Voltages and Phases of Common and Segment Signals
(a) Static display mode
Select
Deselect
VLC0
VLCD
Common signal
LVSS
VLC0
VLCD
Segment signal
LVSS
T
T
T: One LCD clock period
(b) 1/2 bias method
Select
Deselect
VLC0
VLC2
Common signal
VLCD
LVSS
VLC0
Segment signal
VLC2
VLCD
LVSS
T
T
T: One LCD clock period
(c) 1/3 bias method
Select
Deselect
VLC0
VLC1
VLC2
Common signal
VLCD
LVSS
VLC0
VLC1
VLC2
Segment signal
LVSS
T
T
T: One LCD clock period
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VLCD
CHAPTER 17 LCD CONTROLLER/DRIVER
17.7 Display Modes
17.7.1 Static display example
Figure 17-16 shows how the two-digit LCD panel having the display pattern shown in Figure 17-15 is connected to
the segment signals (S0 to S15) and the common signal (COM0) of the 78K0/LE2 chip. This example displays data
"12." in the LCD panel. The contents of the display data memory (addresses 00H to 0FH of LCDSEG) correspond to
this display.
The following description focuses on numeral "2." (
) displayed in the first second digit. To display "2." in the
LCD panel, it is necessary to apply the select or deselect voltage to the S0 to S7 pins according to Table 17-5 at the
timing of the common signal COM0; see Figure 17-15 for the relationship between the segment signals and LCD
segments.
Table 17-5. Select and Deselect Voltages (COM0)
Segment
S0
S1
S2
S3
S4
S5
S6
S7
Select
Deselect
Select
Select
Deselect
Select
Select
Select
Common
COM0
According to Table 17-5, it is determined that the bit-0 pattern of the display data memory locations (00H to 07H of
LCDSEG) must be 10110111.
Figure 17-17 shows the LCD drive waveforms of S3 and S4, and COM0. When the select voltage is applied to S3
at the timing of COM0, an alternate rectangle waveform, +VLCD/−VLCD, is generated to turn on the corresponding LCD
segment.
COM1 to COM3 are supplied with the same waveform as for COM0. So, COM0 to COM3 may be connected
together to increase the driving capacity.
Figure 17-15. Static LCD Display Pattern and Electrode Connections
S8n+3
S8n+4
S8n+2
S8n+5
S8n+6
COM0
S8n+1
S8n
S8n+7
Remark
n = 0, 1
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CHAPTER 17 LCD CONTROLLER/DRIVER
Figure 17-16. Example of Connecting Static LCD Panel
Timing Strobe
COM 3
COM 2
COM 1
4
5
6
7
8
9
A
B
C
D
E
F
Bit 1
Bit 0
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S 10
S 11
S 12
S 13
S 14
S 15
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LCD panel
Data memory address
3
0 0 0 0 0 1 1 0 1 1 1 0 1 1 0 1
2
× × × × × × × × × × × × × × × ×
× × × × × × × × × × × × × × × ×
× × × × × × × × × × × × × × × ×
Bit 3
Bit 2
COM 0
LCDSEG's 00H
1
444
Can be connected
together
CHAPTER 17 LCD CONTROLLER/DRIVER
Figure 17-17. Static LCD Drive Waveform Examples
TF
VLC0
COM0
LVSS
VLC0
S3
LVSS
VLC0
S4
LVSS
+VLCD
COM0-S3
0
-VLCD
+VLCD
COM0-S4
0
-VLCD
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CHAPTER 17 LCD CONTROLLER/DRIVER
17.7.2 Two-time-slice display example
Figure 17-19 shows how the 5-digit LCD panel having the display pattern shown in Figure 17-18 is connected to
the segment signals (S0 to S19) and the common signals (COM0 and COM1) of the 78K0/LE2 chip. This example
displays data "12345." in the LCD panel. The contents of the display data memory (addresses 00H to 13H of
LCDSEG) correspond to this display.
The following description focuses on numeral "3" (
) displayed in the third digit. To display "3" in the LCD panel,
it is necessary to apply the select or deselect voltage to the S8 to S11 pins according to Table 17-6 at the timing of the
common signals COM0 and COM1; see Figure 17-18 for the relationship between the segment signals and LCD
segments.
Table 17-6. Select and Deselect Voltages (COM0 and COM1)
Segment
S8
S9
S10
S11
COM0
Select
Select
Deselect
Deselect
COM1
Deselect
Select
Select
Select
Common
According to Table 17-6, it is determined that the display data memory location (0BH of LCDSEG) that
corresponds to S11 must contain xx10.
Figure 17-20 shows examples of LCD drive waveforms between the S11 signal and each common signal. When
the select voltage is applied to S11 at the timing of COM1, an alternate rectangle waveform, +VLCD/−VLCD, is generated
to turn on the corresponding LCD segment.
;;;;;
;;;
Figure 17-18. Two-Time-Slice LCD Display Pattern and Electrode Connections
S4n+2
S4n+1
;;;
;;;;;;;
S4n+3
Remark
446
COM0
S4n
n = 0 to 4
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CHAPTER 17 LCD CONTROLLER/DRIVER
Timing strobe
Figure 17-19. Example of Connecting Two-Time-Slice LCD Panel
COM 3
COM 2
COM 1
Open
4
5
6
7
8
9
A
B
C
D
E
F
LCDSEG's 10H
1
2
3
Bit 1
Bit 2
Bit 0
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S 10
S 11
LCD panel
3
0 0 0 0 1 1 1 0 1 1 1 0 0 0 1 0 1 1 1 1
0 0 1 1 1 0 1 0 0 0 1 1 0 1 1 1 0 1 0 1
2
× × × × × × × × × × × × × × × × × × × ×
1
× × × × × × × × × × × × × × × × × × × ×
Bit 3
COM 0
LCDSEG's 00H
Data memory address
Open
S 12
S 13
S 14
S 15
S 16
S 17
S 18
S 19
×: Can always be used to store any data because the two-time-slice mode is being used.
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CHAPTER 17 LCD CONTROLLER/DRIVER
Figure 17-20. Two-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method)
TF
VLC0
VLC1,2
COM0
LVSS
VLC0
VLC1,2
COM1
LVSS
VLC0
VLC1,2
S11
LVSS
+VLCD
+1/2VLCD
COM0-S11
0
-1/2VLCD
-VLCD
+VLCD
+1/2VLCD
COM1-S11
0
-1/2VLCD
-VLCD
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CHAPTER 17 LCD CONTROLLER/DRIVER
17.7.3 Three-time-slice display example
Figure 17-22 shows how the 6-digit LCD panel having the display pattern shown in Figure 17-21 is connected to
the segment signals (S0 to S17) and the common signals (COM0 to COM2) of the 78K0/LE2 chip. This example
displays data "123456." in the LCD panel. The contents of the display data memory (addresses 00H to 11H of
LCDSEG) correspond to this display.
The following description focuses on numeral "6." (
) displayed in the first digit. To display "6." in the LCD panel,
it is necessary to apply the select or deselect voltage to the S0 to S2 pins according to Table 17-7 at the timing of the
common signals COM0 to COM2; see Figure 17-21 for the relationship between the segment signals and LCD
segments.
Table 17-7. Select and Deselect Voltages (COM0 to COM2)
Segment
S0
S1
S2
COM0
Deselect
Select
Select
COM1
Select
Select
Select
COM2
Select
Select
−
Common
According to Table 17-7, it is determined that the display data memory location (00H of LCDSEG) that
corresponds to S0 must contain x110.
Figures 17-23 and 17-24 show examples of LCD drive waveforms between the S0 signal and each common signal
in the 1/2 and 1/3 bias methods, respectively. When the select voltage is applied to S0 at the timing of COM1 or
COM2, an alternate rectangle waveform, +VLCD/−VLCD, is generated to turn on the corresponding LCD segment.
;;
;;
;;
;
;;;
Figure 17-21. Three-Time-Slice LCD Display Pattern and Electrode Connections
COM0
S3n+1
S3n+2
Remark
n = 0 to 5
;;
;;;
;;
;;;;;
;;
;;
;; ;;
S3n
COM1
COM2
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CHAPTER 17 LCD CONTROLLER/DRIVER
Figure 17-22. Example of Connecting Three-Time-Slice LCD Panel
Timing strobe
COM 3
COM 2
COM 1
4
5
6
7
8
9
A
B
C
D
E
F
LCDSEG's 10H
1
Bit 2
Bit 1
Bit 0
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S 10
S 11
LCD panel
3
0 0 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 0
2
× × × × × × × × × × × × × × × × × ×
1
x’ 0 0 x’ 1 0 x’ 1 0 x’ 0 0 x’ 1 0 x’ 1 1
Bit 3
COM 0
LCDSEG's 00H
Data memory address
Open
S 12
S 13
S 14
S 15
S 16
S 17
×’: Can be used to store any data because there is no corresponding segment in the LCD panel.
×: Can always be used to store any data because the three-time-slice mode is being used.
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CHAPTER 17 LCD CONTROLLER/DRIVER
Figure 17-23. Three-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method)
TF
VLC0
VLC1,2
COM0
LVSS
VLC0
VLC1,2
COM1
LVSS
VLC0
VLC1,2
COM2
LVSS
VLC0
VLC1,2
S0
LVSS
+VLCD
+1/2VLCD
COM0-S0
0
-1/2VLCD
-VLCD
+VLCD
+1/2VLCD
COM1-S0
0
-1/2VLCD
-VLCD
+VLCD
+1/2VLCD
COM2-S0
0
-1/2VLCD
-VLCD
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CHAPTER 17 LCD CONTROLLER/DRIVER
Figure 17-24. Three-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method)
TF
VLC0
VLC1
COM0
VLC2
LVSS
VLC0
VLC1
COM1
VLC2
LVSS
VLC0
VLC1
COM2
VLC2
LVSS
VLC0
VLC1
S0
VLC2
LVSS
+VLCD
+1/3VLCD
COM0-S0
0
-1/3VLCD
-VLCD
+VLCD
+1/3VLCD
0
COM1-S0
-1/3VLCD
-VLCD
+VLCD
+1/3VLCD
0
COM2-S0
-1/3VLCD
-VLCD
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CHAPTER 17 LCD CONTROLLER/DRIVER
17.7.4 Four-time-slice display example
Figure 17-26 shows how the 10-digit LCD panel having the display pattern shown in Figure 17-25 is connected to
the segment signals (S0 to S19) and the common signals (COM0 to COM3) of the 78K0/LE2 chip. This example
displays data "123456.7890" in the LCD panel. The contents of the display data memory (addresses 00H to 13H of
LCDSEG) correspond to this display.
The following description focuses on numeral "6." (
) displayed in the fifth digit. To display "6." in the LCD panel,
it is necessary to apply the select or deselect voltage to the S8 and S9 pins according to Table 17-8 at the timing of
the common signals COM0 to COM3; see Figure 17-25 for the relationship between the segment signals and LCD
segments.
Table 17-8. Select and Deselect Voltages (COM0 to COM3)
Segment
S8
S9
COM0
Select
Select
COM1
Deselect
Select
COM2
Select
Select
COM3
Select
Select
Common
According to Table 17-8, it is determined that the display data memory location (08H of LCDSEG) that
corresponds to S8 must contain 1101.
Figure 17-27 shows examples of LCD drive waveforms between the S8 signal and each common signal. When
the select voltage is applied to S8 at the timing of COM0, an alternate rectangle waveform, +VLCD/−VLCD, is generated
to turn on the corresponding LCD segment.
Figure 17-25. Four-Time-Slice LCD Display Pattern and Electrode Connections
S2n
;;
;;;;;;
;
COM0
COM1
COM2
COM3
S2n+1
Remark
n = 0 to 9
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CHAPTER 17 LCD CONTROLLER/DRIVER
Figure 17-26. Example of Connecting Four-Time-Slice LCD Panel
Timing strobe
COM 3
COM 2
COM 1
2
3
Data memory address
4
5
6
7
8
9
A
B
C
D
E
F
LCDSEG's 10H
1
2
3
454
Bit 1
Bit 2
Bit 0
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S 10
S 11
S 12
S 13
S 14
S 15
S 16
S 17
S 18
S 19
User’s Manual U17734EJ2V0UD
LCD panel
1
0 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1
0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
LCDSEG's 00H
0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0
0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1
Bit 3
COM 0
CHAPTER 17 LCD CONTROLLER/DRIVER
Figure 17-27. Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method)
TF
VLC0
VLC1
COM0
VLC2
LVSS
VLC0
VLC1
COM1
VLC2
LVSS
VLC0
VLC1
COM2
VLC2
LVSS
VLC0
VLC1
COM3
VLC2
LVSS
VLC0
VLC1
S8
VLC2
LVSS
+VLCD
+1/3VLCD
COM0-S8
0
-1/3VLCD
-VLCD
+VLCD
+1/3VLCD
0
COM1-S8
-1/3VLCD
-VLCD
Remark
The waveforms for COM2 to S8 and COM3 to S8 are omitted.
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CHAPTER 17 LCD CONTROLLER/DRIVER
17.8 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2
With the 78K0/LE2, a LCD drive power supply can be generated using either of three types of methods: internal
resistance division method, external resistance division method, or internal voltage boosting method.
17.8.1 Internal resistance division method
The 78K0/LE2 incorporates voltage divider resistors for generating LCD drive power supplies. Using internal
voltage divider resistors, a LCD drive power supply that meet each bias method listed in Table 17-9 can be generated,
without using external voltage divider resistors.
Table 17-9. LCD Drive Voltages (with On-Chip Voltage Divider Resistors)
Bias Method
No Bias (Static)
1/2 Bias Method
1/3 Bias Method
VLCD
VLCD
VLCD
LCD Drive Voltage Pin
VLC0
VLC1
VLC2
2
3
1
3
VLCD
1
2
VLCD
Note
VLCD
2
3
1
3
Note For the 1/2 bias method, it is necessary to connect the VLC1 and VLC2 pins externally.
Figure 17-28 shows examples of generating LCD drive voltages internally according to Table 17-9.
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VLCD
VLCD
CHAPTER 17 LCD CONTROLLER/DRIVER
Figure 17-28. Examples of LCD Drive Power Connections (Internal Resistance Division Method)
(a) 1/3 bias method and static display mode
VLCD
VLC0
R
VLC1
R
VLC2
R
LVSS
(b) 1/2 bias method
VLCD
VLC0
R
VLC1
R
VLC2
R
LVSS
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CHAPTER 17 LCD CONTROLLER/DRIVER
17.8.2 External resistance division method
The 78K0/LE2 can also use external voltage divider resistors for generating LCD drive power supplies, without
using internal resistors. Figure 17-29 shows examples of LCD drive voltage connection, corresponding to each bias
method.
Figure 17-29. Examples of LCD Drive Power Connections (External Resistance Division Method)
(a) Static display mode
(b) Static display mode
(VLCD = VLC0 = VLC1 = VLC2)
(VLC1 = VLC2 = LVSS = GND)
VLCD
VLCD
VLC0
VLC0
VLC1
VLC1
VLC2
VLC2
LVSS
LVSS
(c) 1/2 bias method
(d) 1/3 bias method
VLCD
VLC0
VLCD
VLC0
R
VLC1
R
VLC1
R
VLC2
VLC2
R
LVSS
R
LVSS
Remark Both (a) and (b) connection can be used in the static display mode.
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CHAPTER 17 LCD CONTROLLER/DRIVER
17.8.3 Internal voltage boosting method
The 78K0/LE2 contains a booster circuit (×3 only) to generate a supply voltage to drive the LCD. The internal LCD
reference voltage is output from the VLC2 pin. A voltage two times higher than that on VLC2 is output from the VLC1 pin
and a voltage three times higher than that on VLC2 is output from the VLC0 pin.
The LCD reference voltage (VLC2) can be specified by setting LCD boost control register 0 (VLCG0).
The 78K0/LE2 requires an external capacitor (0.47 to 1 μF: recommended) when the internal voltage boosting
method is selected.
Table 17-10. Output Voltages of VLC0 to VLC2 Pins
VLCG0
GAIN = 0
GAIN = 1
LCD drive power supply pin
Cautions
1.
VLC0
4.5 V
3.0 V
VLC1
3.0 V
2.0 V
VLC2 (LCD reference voltage)
1.5 V
1.0 V
When using the LCD function, do not leave the VLC0, VLC1, and VLC2 pins open. Refer to
Figure 17-30 for connection.
2.
Since the LCD drive voltage is separate from the main power supply, a constant voltage
can be supplied regardless of VDD and LVDD fluctuation.
Figure 17-30. Example of Connecting Pins for LCD Driver
VLC0
VLC1
VLC2
C2
C3
C4
CAPH
C1
CAPL
C1 = C2 = C3 = C4 = 0.47 μF
External pin
Remark
Use a capacitor with as little leakage as possible.
In addition, make C1 a nonpolar capacitor.
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CHAPTER 18 INTERRUPT FUNCTIONS
18.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group
and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H).
Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If
two or more interrupt requests, each having the same priority, are simultaneously generated, then they are
processed according to the priority of vectored interrupt servicing. For the priority order, see Table 18-1.A
standby release signal is generated and STOP and HALT modes are released.
External interrupt requests and internal interrupt requests are provided as maskable interrupts.
External: 6, internal: 16
(2) Software interrupt
This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts
are disabled. The software interrupt does not undergo interrupt priority control.
18.2 Interrupt Sources and Configuration
The 78K0/LE2 has a total of 23 interrupt sources, including maskable interrupts and software interrupts. In addition,
they also have up to four reset sources (see Table 18-1).
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Table 18-1. Interrupt Source List
Interrupt
Type
Default
Interrupt Source
Note 1
Priority
Name
Trigger
Internal/
Vector
Basic
External
Table
Configuration
Address
Maskable
Note 3
Type
Note 2
0
INTLVI
Low-voltage detection
Internal
0004H
(A)
1
INTP0
Pin input edge detection
External
0006H
(B)
2
INTP1
0008H
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTSRE6
UART6 reception error generation
8
INTSR6
End of UART6 reception
0014H
Internal
0012H
9
INTST6
End of UART6 transmission
0016H
10
INTCSI10/
End of CSI10 communication/end of UART0
0018H
INTST0
transmission
INTTMH1
Match between TMH1 and CMP01
11
(A)
001AH
(when compare register is specified)
12
INTTMH0
Match between TMH0 and CMP00
001CH
(when compare register is specified)
13
INTTM50
Match between TM50 and CR50
001EH
(when compare register is specified)
14
INTTM000
Match between TM00 and CR000
0020H
(when compare register is specified),
TI010 pin valid edge detection
(when capture register is specified)
15
INTTM010
Match between TM00 and CR010
0022H
(when compare register is specified),
TI000 pin valid edge detection
(when capture register is specified)
16
INTAD
End of A/D conversion
0024H
17
INTSR0
End of UART0 reception or reception error generation
0026H
18
INTWTI
Watch timer reference time interval signal
0028H
19
INTTM51
Match between TM51 and CR51
002AH
(when compare register is specified)
20
INTWT
Watch timer overflow
002EH
21
INTIIC0
End of IIC0 communication
0034H
Software
−
BRK
BRK instruction execution
−
003EH
(C)
Reset
−
RESET
Reset input
−
0000H
−
POC
Power-on clear
LVI
Low-voltage detection
WDT
WDT overflow
Notes 1.
2.
3.
4.
Note 4
The default priority determines the sequence of processing vectored interrupts if two or more maskable
interrupts occur simultaneously. Zero indicates the highest priority and 21 indicates the lowest priority.
Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 18-1.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1.
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CHAPTER 18 INTERRUPT FUNCTIONS
Figure 18-1. Basic Configuration of Interrupt Function
(A) Internal maskable interrupt
Internal bus
MK
Interrupt
request
IE
PR
ISP
Priority controller
IF
Vector table
address generator
Standby release signal
(B) External maskable interrupt (INTP0 to INTP5)
Internal bus
External interrupt edge
enable register
(EGP, EGN)
Interrupt
request
Edge
detector
MK
IF
IE
PR
ISP
Vector table
address generator
Priority controller
Standby release signal
(C) Software interrupt
Internal bus
Interrupt
request
462
IF:
Interrupt request flag
IE:
Interrupt enable flag
ISP:
In-service priority flag
MK:
Interrupt mask flag
PR:
Priority specification flag
Priority controller
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Vector table
address generator
CHAPTER 18 INTERRUPT FUNCTIONS
18.3 Registers Controlling Interrupt Functions
The following 6 types of registers are used to control the interrupt functions.
• Interrupt request flag register (IF0L, IF0H, IF1L, IF1H)
• Interrupt mask flag register (MK0L, MK0H, MK1L, MK1H)
• Priority specification flag register (PR0L, PR0H, PR1L, PR1H)
• External interrupt rising edge enable register (EGP)
• External interrupt falling edge enable register (EGN)
• Program status word (PSW)
Table 18-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding
to interrupt request sources.
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CHAPTER 18 INTERRUPT FUNCTIONS
Table 18-2. Flags Corresponding to Interrupt Request Sources
Interrupt
Interrupt Request Flag
Source
Interrupt Mask Flag
Register
Register
LVIIF
INTP0
PIF0
PMK0
PPR0
INTP1
PIF1
PMK1
PPR1
INTP2
PIF2
PMK2
PPR2
INTP3
PIF3
PMK3
PPR3
INTP4
PIF4
PMK4
PPR4
INTP5
PIF5
PMK5
PPR5
INTSRE6
SREIF6
SREMK6
SREPR6
SRIF6
INTST6
STIF6
INTCSI10
CSIIF10
IF0H
LVIMK
MK0L
Register
INTLVI
INTSR6
IF0L
Priority Specification Flag
SRMK6
MK0H
STMK6
DUALIF0
CSIMK10
Note 1
LVIPR
SRPR6
DUALMK0
CSIPR10
STIF0
STMK0
STPR0
INTTMH1
TMIFH1
TMMKH1
TMPRH1
INTTMH0
TMIFH0
TMMKH0
TMPRH0
INTTM50
TMIF50
TMMK50
TMPR50
INTTM000
TMIF000
TMMK000
TMPR000
INTTM010
TMIF010
INTAD
ADIF
INTSR0
SRIF0
SRMK0
SRPR0
INTWTI
WTIIF
WTIMK
WTIPR
INTTM51
TMIF51
TMMK51
TMPR51
INTWT
WTIF
WTMK
WTPR
INTIIC0
IICIF0
Notes 1.
2.
464
TMMK010
ADMK
IICMK0
TMPR010
MK1L
MK1H
ADPR
IICPR0
If either interrupt source INTCSI10 or INTST0 is generated, these flags are set (1).
Both interrupt sources INTCSI10 and INTST0 are supported.
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DUALPR0
Note 2
INTST0
IF1H
PR0H
STPR6
Note 2
IF1L
PR0L
PR1L
PR1H
CHAPTER 18 INTERRUPT FUNCTIONS
(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt
routine is entered.
IF0L, IF0H, IF1L, and IF1H are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H, and
IF1L and IF1H are combined to form 16-bit registers IF0 and IF1, they are set by a 16-bit memory manipulation
instruction.
Reset signal generation sets these registers to 00H.
Figure 18-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H)
Address: FFE0H After reset: 00H R/W
Symbol
IF0L
SREIF6
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
LVIIF
Address: FFE1H
Symbol
IF0H
After reset: 00H
R/W
TMIF010
TMIF000
TMIF50
TMIFH0
TMIFH1
DUALIF0
STIF6
SRIF6
CSIIF10
STIF0
Address: FFE2H
Symbol
IF1L
Address: FFE3H
After reset: 00H
R/W
4
0
0
WTIF
0
TMIF51
WTIIF
SRIF0
ADIF
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
IF1H
0
0
0
0
0
0
0
IICIF0
XXIFX
Interrupt request flag
0
No interrupt request signal is generated
1
Interrupt request is generated, interrupt request status
Cautions 1. Be sure to clear bits 4, 6 and 7 of IF1L to 0.
2. Be sure to clear bits 1 to 7 of IF1H to 0.
3. When operating a timer, serial interface, or A/D converter after standby release, operate it
once after clearing the interrupt request flag. An interrupt request flag may be set by noise.
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CHAPTER 18 INTERRUPT FUNCTIONS
Cautions 4. When manipulating a flag of the interrupt request flag register, use a 1-bit memory
manipulation instruction (CLR1). When describing in C language, use a bit manipulation
instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler
must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction such
as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of another bit of the same interrupt request flag register
(IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is cleared to
0 at “mov IF0L, a”.
Therefore, care must be exercised when using an 8-bit memory
manipulation instruction in C language.
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(2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and
MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit
memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 18-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H)
Address: FFE4H
Symbol
MK0L
After reset: FFH
R/W
SREMK6
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
LVIMK
Address: FFE5H
After reset: FFH
R/W
Symbol
MK0H
TMMK010
TMMK000
TMMK50
TMMKH0
TMMKH1
DUALMK0
STMK6
SRMK6
CSIMK0
STMK0
Address: FFE6H
After reset: FFH
R/W
Symbol
7
6
4
MK1L
1
1
WTMK
1
TMMK51
WTIMK
SRMK0
ADMK
Address: FFE7H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
MK1H
1
1
1
1
1
1
1
IICMK0
XXMKX
Interrupt servicing control
0
Interrupt servicing enabled
1
Interrupt servicing disabled
Cautions 1. Be sure to set bits 4, 6 and 7 of MK1L to 1.
2. Be sure to set bits 1 to 7 of MK1H to 1.
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CHAPTER 18 INTERRUPT FUNCTIONS
(3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)
The priority specification flag registers are used to set the corresponding maskable interrupt priority order.
PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H,
and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory
manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 18-4. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H)
Address: FFE8H
Symbol
PR0L
R/W
SREPR6
PPR5
PPR4
PPR3
PPR2
PPR1
PPR0
LVIPR
Address: FFE9H
Symbol
PR0H
After reset: FFH
After reset: FFH
R/W
TMPR010
TMPR000
TMPR50
TMPRH0
TMPRH1
DUALPR0
STPR6
SRPR6
CSIPR10
STPR0
Address: FFEAH
Symbol
PR1L
Address: FFEBH
After reset: FFH
R/W
4
1
1
WTPR
1
TMPR51
WTIPR
SRPR0
ADPR
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
PR1H
1
1
1
1
1
1
1
IICPR0
XXPRX
Priority level selection
0
High priority level
1
Low priority level
Cautions 1. Be sure to set bits 4, 6 and 7 of PR1L to 1.
2. Be sure to set bits 1 to 7 of PR1H to 1.
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(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN)
These registers specify the valid edge for INTP0 to INTP5.
EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to 00H.
Figure 18-5. Format of External Interrupt Rising Edge Enable Register (EGP)
and External Interrupt Falling Edge Enable Register (EGN)
Address: FF48H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
EGP
0
0
EGP5
EGP4
EGP3
EGP2
EGP1
EGP0
Address: FF49H
After reset: 00H
Symbol
7
6
R/W
5
4
3
2
1
0
EGN
0
0
EGN5
EGN4
EGN3
EGN2
EGN1
EGN0
EGPn
EGNn
0
0
Edge detection disabled
0
1
Falling edge
1
0
Rising edge
1
1
Both rising and falling edges
INTPn pin valid edge selection (n = 0 to 7)
Table 18-3 shows the ports corresponding to EGPn and EGNn.
Table 18-3. Ports Corresponding to EGPn and EGNn
Detection Enable Register
Edge Detection Port
Interrupt Request Signal
EGP0
EGN0
P120
INTP0
EGP1
EGN1
P30
INTP1
EGP2
EGN2
P31
INTP2
EGP3
EGN3
P32
INTP3
EGP4
EGN4
P33
INTP4
EGP5
EGN5
P16
INTP5
Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be
detected when the external interrupt function is switched to the port function.
Remark
n = 0 to 5
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CHAPTER 18 INTERRUPT FUNCTIONS
(5) Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for an
interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple
interrupt servicing are mapped to the PSW.
Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed,
the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt
request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are
transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction.
They are restored from the stack with the RETI, RETB, and POP PSW instructions.
RESET input sets PSW to 02H.
Figure 18-6. Format of Program Status Word
PSW
2
0
After reset
IE
Z
RBS1
AC
RBS0
0
ISP
CY
02H
Used when normal instruction is executed
ISP
470
Priority of interrupt currently being serviced
0
High-priority interrupt servicing (low-priority
interrupt disabled)
1
Interrupt request not acknowledged, or lowpriority interrupt servicing (all maskable
interrupts enabled)
IE
Interrupt request acknowledgment enable/disable
0
Disabled
1
Enabled
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CHAPTER 18 INTERRUPT FUNCTIONS
18.4 Interrupt Servicing Operations
18.4.1 Maskable interrupt acknowledgement
A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag
corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are
in the interrupt enabled state (when the IE flag is set to 1).
However, a low-priority interrupt request is not
acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). The times from
generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in Table 18-4
below.
For the interrupt request acknowledgement timing, see Figures 18-8 and 18-9.
Table 18-4. Time from Generation of Maskable Interrupt Until Servicing
Note
Minimum Time
Maximum Time
When ××PR = 0
7 clocks
32 clocks
When ××PR = 1
8 clocks
33 clocks
Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer.
Remark
1 clock: 1/fCPU (fCPU: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same
priority level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 18-7 shows the interrupt request acknowledgement algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is the loaded into
the PC and branched.
Restoring from an interrupt is possible by using the RETI instruction.
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CHAPTER 18 INTERRUPT FUNCTIONS
Figure 18-7. Interrupt Request Acknowledgement Processing Algorithm
Start
No
××IF = 1?
Yes (interrupt request generation)
No
××MK = 0?
Yes
Interrupt request held pending
Yes (High priority)
××PR = 0?
No (Low priority)
Yes
Any high-priority
interrupt request among those
simultaneously generated
with ××PR = 0?
Any high-priority
interrupt request among
those simultaneously generated
with ××PR = 0?
Yes
Interrupt request held pending
No
No
No
IE = 1?
Yes
Interrupt request held pending
Interrupt request held pending
Any high-priority
interrupt request among
those simultaneously
generated?
No
IE = 1?
Vectored interrupt servicing
Yes
ISP = 1?
Yes
Yes
Interrupt request held pending
No
Interrupt request held pending
No
Interrupt request held pending
Vectored interrupt servicing
××IF:
Interrupt request flag
××MK: Interrupt mask flag
××PR: Priority specification flag
IE:
Flag that controls acknowledgement of maskable interrupt request (1 = Enable, 0 = Disable)
ISP:
Flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt
servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing)
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Figure 18-8. Interrupt Request Acknowledgement Timing (Minimum Time)
6 clocks
CPU processing
Instruction
PSW and PC saved,
jump to interrupt
servicing
Instruction
Interrupt servicing
program
××IF
(××PR = 1)
8 clocks
××IF
(××PR = 0)
7 clocks
Remark
1 clock: 1/fCPU (fCPU: CPU clock)
Figure 18-9. Interrupt Request Acknowledgement Timing (Maximum Time)
CPU processing
Instruction
25 clocks
6 clocks
Divide instruction
PSW and PC saved,
jump to interrupt
servicing
Interrupt servicing
program
××IF
(××PR = 1)
33 clocks
××IF
(××PR = 0)
32 clocks
Remark
1 clock: 1/fCPU (fCPU: CPU clock)
18.4.2 Software interrupt request acknowledgement
A software interrupt acknowledge is acknowledged by BRK instruction execution. Software interrupts cannot be
disabled.
If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program
status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH,
003FH) are loaded into the PC and branched.
Restoring from a software interrupt is possible by using the RETB instruction.
Caution Do not use the RETI instruction for restoring from the software interrupt.
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18.4.3 Multiple interrupt servicing
Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupt servicing does not occur unless the interrupt request acknowledgement enabled state is selected
(IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (IE = 0).
Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during
interrupt servicing to enable interrupt acknowledgement.
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to
interrupt priority control. Two types of priority control are available: default priority control and programmable priority
control. Programmable priority control is used for multiple interrupt servicing.
In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt
currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority
lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged
for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled
state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the
pending interrupt request is acknowledged following execution of at least one main processing instruction execution.
Table 18-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 18-10
shows multiple interrupt servicing examples.
Table 18-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing
During Interrupt Servicing
Multiple Interrupt Request
PR = 0
IE = 1
IE = 0
IE = 1
IE = 0
ISP = 0
{
×
×
×
{
ISP = 1
{
×
{
×
{
{
×
{
×
{
Software interrupt
Remarks 1.
Interrupt
PR = 1
Request
Interrupt Being Serviced
Maskable interrupt
Software
Maskable Interrupt Request
: Multiple interrupt servicing enabled
2. ×: Multiple interrupt servicing disabled
3. ISP and IE are flags contained in the PSW.
ISP = 0: An interrupt with higher priority is being serviced.
ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower
priority is being serviced.
IE = 0:
Interrupt request acknowledgement is disabled.
IE = 1:
Interrupt request acknowledgement is enabled.
4. PR is a flag contained in PR0L, PR0H, PR1L, and PR1H.
PR = 0: Higher priority level
PR = 1: Lower priority level
474
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Figure 18-10. Examples of Multiple Interrupt Servicing (1/2)
Example 1. Multiple interrupt servicing occurs twice
Main processing
INTxx servicing
INTyy servicing
IE = 0
EI
IE = 0
IE = 0
EI
INTxx
(PR = 1)
INTzz servicing
EI
INTyy
(PR = 0)
INTzz
(PR = 0)
RETI
IE = 1
RETI
IE = 1
RETI
IE = 1
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple
interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be
issued to enable interrupt request acknowledgment.
Example 2. Multiple interrupt servicing does not occur due to priority control
Main processing
INTxx servicing
INTyy servicing
IE = 0
EI
EI
INTxx
(PR = 0)
INTyy
(PR = 1)
RETI
IE = 1
1 instruction execution
IE = 0
RETI
IE = 1
Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower
than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending,
and is acknowledged following execution of one main processing instruction.
PR = 0: Higher priority level
PR = 1: Lower priority level
IE = 0:
Interrupt request acknowledgment disabled
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Figure 18-10. Examples of Multiple Interrupt Servicing (2/2)
Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled
Main processing
INTxx servicing INTyy servicing
IE = 0
EI
INTyy
(PR = 0)
INTxx
(PR = 0)
RETI
IE = 1
1 instruction execution
IE = 0
RETI
IE = 1
Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt
request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request
is held pending, and is acknowledged following execution of one main processing instruction.
PR = 0: Higher priority level
IE = 0:
476
Interrupt request acknowledgement disabled
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18.4.4 Interrupt request hold
There are instructions where, even if an interrupt request is issued for them while another instruction is being
executed, request acknowledgement is held pending until the end of execution of the next instruction.
These
instructions (interrupt request hold instructions) are listed below.
• MOV PSW, #byte
• MOV A, PSW
• MOV PSW, A
• MOV1 PSW. bit, CY
• MOV1 CY, PSW. bit
• AND1 CY, PSW. bit
• OR1 CY, PSW. bit
• XOR1 CY, PSW. bit
• SET1 PSW. bit
• CLR1 PSW. bit
• RETB
• RETI
• PUSH PSW
• POP PSW
• BT PSW. bit, $addr16
• BF PSW. bit, $addr16
• BTCLR PSW. bit, $addr16
• EI
• DI
• Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, MK0L, MK0H, MK1L, MK1H, PR0L, PR0H, PR1L, and
PR1H registers.
Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However,
the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared.
Therefore, even if a maskable interrupt request is generated during execution of the BRK
instruction, the interrupt request is not acknowledged.
Figure 18-11 shows the timing at which interrupt requests are held pending.
Figure 18-11. Interrupt Request Hold
CPU processing
Instruction N
Instruction M
PSW and PC saved, jump
to interrupt servicing
Interrupt servicing
program
××IF
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instruction other than interrupt request hold instruction
3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).
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CHAPTER 19 STANDBY FUNCTION
19.1 Standby Function and Configuration
19.1.1 Standby function
The standby function is designed to reduce the operating current of the system. The following two modes are
available.
(1) HALT mode
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the
high-speed system clock oscillator, internal high-speed oscillator, internal low-speed oscillator, or subsystem
clock oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the
operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting
operation immediately upon interrupt request generation and carrying out intermittent operations frequently.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and
internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating
current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is
released when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately
upon interrupt request generation.
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is
set are held. The I/O port output latches and output buffer statuses are also held.
Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The
subsystem clock oscillation cannot be stopped. The HALT mode can be used when the CPU
is operating on either the main system clock or the subsystem clock.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation
operating with main system clock before executing STOP instruction.
3. The following sequence is recommended for operating current reduction of the A/D converter
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute
the STOP instruction.
19.1.2 Registers controlling standby function
The standby function is controlled by the following two registers.
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
Remark
478
For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
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CHAPTER 19 STANDBY FUNCTION
(1) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1
clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock,
the X1 clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of
MOC register) = 1 clear OSTC to 00H.
Figure 19-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H
After reset: 00H
R
Symbol
7
6
5
4
3
2
1
0
OSTC
0
0
0
MOST11
MOST13
MOST14
MOST15
MOST16
MOST11
MOST13
MOST14
MOST15
MOST16
Oscillation stabilization time status
fX = 10 MHz
1
1
1
0
0
1
0
0
1
0
0
1
0
0
0
fX = 20 MHz
11
204.8 μs min. 102.4 μs min.
13
819.2 μs min. 409.6 μs min.
14
1.64 ms min. 819.2 μs min.
15
3.27 ms min. 1.64 ms min.
16
6.55 ms min. 3.27 ms min.
2 /fX min.
2 /fX min.
2 /fX min.
1
1
1
1
0
2 /fX min.
1
1
1
1
1
2 /fX min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
2. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
3. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark
fX: X1 clock oscillation frequency
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(2) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP
mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired
oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can
be checked up to the time set using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets OSTS to 05H.
Figure 19-2. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H
After reset: 05H
R/W
Symbol
7
6
5
4
3
2
1
0
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Oscillation stabilization time selection
fX = 10 MHz
0
0
0
1
1
204.8 μs
102.4 μs
13
819.2 μs
409.6 μs
14
1.64 ms
819.2 μs
15
3.27 ms
1.64 ms
16
6.55 ms
3.27 ms
2 /fX
0
2 /fX
0
1
1
2 /fX
1
0
0
2 /fX
1
0
1
2 /fX
Other than above
fX = 20 MHz
11
Setting prohibited
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
2. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
3. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
4. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark
480
fX: X1 clock oscillation frequency
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CHAPTER 19 STANDBY FUNCTION
19.2 Standby Function Operation
19.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU
clock before the setting was the high-speed system clock, internal high-speed oscillation clock, or subsystem
clock.
The operating statuses in the HALT mode are shown below.
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Table 19-1. Operating Statuses in HALT Mode (1/2)
HALT Mode Setting
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
Internal High-Speed
Oscillation Clock (fRH)
Item
System clock
When CPU Is Operating on
X1 Clock (fX)
When CPU Is Operating on
External Main System Clock
(fEXCLK)
Clock supply to the CPU is stopped
Main system clock
Subsystem clock
fRH
Operation continues (cannot
be stopped)
Status before HALT mode was set is retained
fX
Status before HALT mode
was set is retained
Operation continues (cannot
be stopped)
fEXCLK
Operates or stops by external clock input
fXT
Status before HALT mode was set is retained
fEXCLKS
Operates or stops by external clock input
fRL
Status before HALT mode
was set is retained
Operation continues (cannot
be stopped)
Status before HALT mode was set is retained
CPU
Operation stopped
Flash memory
Operation stopped
RAM
Status before HALT mode was set is retained
Port (latch)
Status before HALT mode was set is retained
16-bit timer/event counter 00
Operable
8-bit timer/event
counter
50
8-bit timer
H0
51
H1
Watch timer
Watchdog timer
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Clock output
Operable
A/D converter
Serial interface
UART0
UART6
CSI10
IIC0
LCD controller/driver
Power-on-clear function
Low-voltage detection function
External interrupt
Remark fRH:
fX:
Internal high-speed oscillation clock
X1 clock
fEXCLK:
External main system clock
fXT:
XT1 clock
fEXCLKS: External subsystem clock
fRL:
482
Internal low-speed oscillation clock
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Table 19-1. Operating Statuses in HALT Mode (2/2)
HALT Mode Setting
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
When CPU Is Operating on XT1 Clock (fXT)
When CPU Is Operating on External
Subsystem Clock (fEXCLKS)
Item
System clock
Clock supply to the CPU is stopped
Main system clock
Status before HALT mode was set is retained
fRH
fX
Subsystem clock
fEXCLK
Operates or stops by external clock input
fXT
Operation continues (cannot be stopped)
Status before HALT mode was set is retained
fEXCLKS
Operates or stops by external clock input
Operation continues (cannot be stopped)
fRL
Status before HALT mode was set is retained
CPU
Operation stopped
Flash memory
Operation stopped
RAM
Status before HALT mode was set is retained
Port (latch)
Status before HALT mode was set is retained
Note
16-bit timer/event counter 00
8-bit timer/event
50
Note
counter
51
Note
8-bit timer
H0
Operable
H1
Watch timer
Watchdog timer
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Clock output
Operable
A/D converter
Serial interface
Operable. However, operation disabled when peripheral hardware clock (fPRS) is stopped.
UART0
Operable
UART6
CSI10
IIC0
Note
Note
LCD controller/driver
Power-on-clear function
Low-voltage detection function
External interrupt
Note When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been
stopped, do not start operation of these functions on the external clock input from peripheral hardware pins.
Remark fRH:
fX:
fEXCLK:
fXT:
fEXCLKS:
fRL:
Internal high-speed oscillation clock
X1 clock
External main system clock
XT1 clock
External subsystem clock
Internal low-speed oscillation clock
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(2) HALT mode release
The HALT mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the HALT mode is released. If interrupt
acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is
disabled, the next address instruction is executed.
Figure 19-3. HALT Mode Release by Interrupt Request Generation
HALT
instruction
Interrupt
request
Wait
Standby
release signal
Status of CPU
Operating mode
HALT mode
Wait
Operating mode
Oscillation
High-speed system clock,
internal high-speed oscillation clock,
or subsystem clock
Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby
mode is acknowledged.
2. The wait time is as follows:
• When vectored interrupt servicing is carried out:
8 or 9 clocks
• When vectored interrupt servicing is not carried out: 2 or 3 clocks
484
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(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 19-4. HALT Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
HALT
instruction
Reset signal
Status of CPU
High-speed
system clock
(X1 oscillation)
Normal operation
(high-speed
system clock)
HALT mode
Reset
Reset processing
period (20 μs (TYP.))
Normal operation
(internal high-speed
oscillation clock)
Oscillation Oscillation
stopped stopped
Oscillates
Oscillates
Oscillation stabilization time
(211/fX to 216/fX)
Starting X1 oscillation is
specified by software.
(2) When internal high-speed oscillation clock is used as CPU clock
HALT
instruction
Reset signal
Normal operation
(internal high-speed
oscillation clock)
Status of CPU
Internal high-speed
oscillation clock
HALT mode
Oscillates
Reset
Reset processing
period (20 μ s (TYP.))
Oscillation
stopped
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Wait for oscillation
accuracy stabilization
(3) When subsystem clock is used as CPU clock
HALT
instruction
Reset signal
Status of CPU
Subsystem clock
(XT1 oscillation)
Normal operation
(subsystem clock)
HALT mode
Oscillates
Reset
Normal operation mode
Reset processing
(internal high-speed
period (20 μ s (TYP.))
oscillation clock)
Oscillation Oscillation
stopped
stopped Oscillates
Starting XT1 oscillation is
specified by software.
Remark fX: X1 clock oscillation frequency
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Table 19-2. Operation in Response to Interrupt Request in HALT Mode
Release Source
Maskable interrupt
MK××
PR××
IE
ISP
0
0
0
×
request
Operation
Next address
instruction execution
0
0
1
×
0
1
0
1
Next address
0
1
×
0
instruction execution
0
1
1
1
Interrupt servicing
Interrupt servicing
execution
execution
Reset
1
×
×
×
HALT mode held
−
−
×
×
Reset processing
×: don’t care
19.2.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the main system clock.
Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is
immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after
execution of the STOP instruction and the system returns to the operating mode as soon as the
wait time set using the oscillation stabilization time select register (OSTS) has elapsed.
The operating statuses in the STOP mode are shown below.
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Table 19-3. Operating Statuses in STOP Mode
STOP Mode Setting
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
Internal High-Speed
Oscillation Clock (fRH)
Item
System clock
When CPU Is Operating on
X1 Clock (fX)
When CPU Is Operating on
External Main System Clock
(fEXCLK)
Clock supply to the CPU is stopped
Main system clock
fRH
Stopped
fX
fEXCLK
Subsystem clock
Input invalid
fXT
Status before STOP mode was set is retained
fEXCLKS
Operates or stops by external clock input
fRL
Status before STOP mode was set is retained
CPU
Operation stopped
Flash memory
Operation stopped
RAM
Status before STOP mode was set is retained
Port (latch)
Status before STOP mode was set is retained
16-bit timer/event counter 00
Operation stopped
8-bit timer/event
counter
50
Operable only when TI50 is selected as the count clock
51
Operable only when TI51 is selected as the count clock
8-bit timer
H0
Operable only when TM50 output is selected as the count clock during 8-bit timer/event counter
50 operation
H1
Operable only when fRL, fRL/2 , fRL/2 is selected as the count clock
7
9
Watch timer
Operable only when subsystem clock is selected as the count clock
Watchdog timer
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Clock output
Operable only when subsystem clock is selected as the count clock
A/D converter
Operation stopped
Serial interface
UART6
Operable only when TM50 output is selected as the serial clock during 8-bit timer/event counter
50 operation
CSI10
Operable only when external clock is selected as the serial clock
UART0
IIC0
LCD controller/driver
Operable only when subsystem clock is selected as the count clock
Power-on-clear function
Operable
Low-voltage detection function
External interrupt
Remark fRH:
Internal high-speed oscillation clock
fX:
X1 clock
fEXCLK:
External main system clock
fXT:
XT1 clock
fEXCLKS: External subsystem clock
fRL:
Internal low-speed oscillation clock
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Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral
hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is
released, restart the peripheral hardware.
2. Even if “internal low-speed oscillator can be stopped by software” is selected by the option
byte, the internal low-speed oscillation clock continues in the STOP mode in the status before
the STOP mode is set. To stop the internal low-speed oscillator’s oscillation in the STOP mode,
stop it by software and then execute the STOP instruction.
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the
internal high-speed oscillation clock before the next execution of the STOP instruction. Before
changing the CPU clock from the internal high-speed oscillation clock to the high-speed system
clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time
with the oscillation stabilization time counter status register (OSTC).
4. If the STOP instruction is executed with AMPH set to 1 when the internal high-speed oscillation
clock or external main system clock is used as the CPU clock, the internal high-speed
oscillation clock or external main system clock is supplied to the CPU 5 μs (MIN.) after the STOP
mode has been released.
(2) STOP mode release
Figure 19-5. Operation Timing When STOP Mode Is Released
STOP mode release
STOP mode
High-speed system
clock (X1 oscillation)
Internal high-speed
oscillation clock
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
Wait for oscillation
accuracy
stabilization
HALT status
(oscillation stabilization time set by OSTS)
Automatic selection
Internal high-speed
oscillation clock
5 μs (TYP.)
High-speed system clock
Note
Clock switched
by software
Note When AMPH = 1
The STOP mode can be released by the following two sources.
488
High-speed system clock
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CHAPTER 19 STANDBY FUNCTION
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the STOP mode is released.
After the oscillation
stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried
out. If interrupt acknowledgment is disabled, the next address instruction is executed.
Figure 19-6. STOP Mode Release by Interrupt Request Generation
(1) When high-speed system clock is used as CPU clock
Wait
(set by OSTS)
STOP
instruction
Standby release signal
Status of CPU
High-speed
system clock
(X1 oscillation)
Operating mode
(high-speed
system clock)
Oscillation stabilization wait
(HALT mode status)
STOP mode
Oscillation stopped
Oscillates
Operating mode
(high-speed
system clock)
Oscillates
Oscillation stabilization time (set by OSTS)
(2) When internal high-speed oscillation clock is used as CPU clock
STOP
instruction
Standby release signal
Status of CPU
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock)
STOP mode
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Oscillation stopped
Oscillates
Wait for oscillation
accuracy
stabilization
Remark The broken lines indicate the case when the interrupt request that has released the standby mode
is acknowledged.
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CHAPTER 19 STANDBY FUNCTION
(b) Release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 19-7. STOP Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
STOP
instruction
Reset signal
Status of CPU
STOP mode
Reset
Reset processing
period (20 μs (TYP.))
Normal operation
(internal high-speed
oscillation clock)
Oscillation stopped
Oscillation Oscillation
stopped stopped
Oscillates
Normal operation
(high-speed
system clock)
High-speed
system clock
(X1 oscillation)
Oscillates
Oscillation stabilization time
(211/fX to 216/fX)
Starting X1 oscillation is
specified by software.
(2) When internal high-speed oscillation clock is used as CPU clock
STOP
instruction
Reset signal
Status of CPU
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock)
Reset
Reset processing
period (20 μs (TYP.))
STOP mode
Oscillation
Oscillation stopped stopped
Oscillates
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Wait for oscillation
accuracy
stabilization
Remark fX: X1 clock oscillation frequency
Table 19-4. Operation in Response to Interrupt Request in STOP Mode
Release Source
Maskable interrupt
MK××
PR××
IE
ISP
0
0
0
×
request
Operation
Next address
instruction execution
0
0
1
×
Interrupt servicing
execution
0
1
0
1
Next address
0
1
×
0
instruction execution
0
1
1
1
Interrupt servicing
execution
Reset
1
×
×
×
STOP mode held
−
−
×
×
Reset processing
×: don’t care
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CHAPTER 20 RESET FUNCTION
The following four operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets have no functional differences. In both cases, program execution starts at the address
at 0000H and 0001H when the reset signal is generated.
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
circuit voltage detection, and each item of hardware is set to the status shown in Tables 20-1 and 20-2. Each pin is
high impedance during reset signal generation or during the oscillation stabilization time just after a reset release.
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high
level is input to the RESET pin and program execution is started with the internal high-speed oscillation clock after
reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the
internal high-speed oscillation clock (see Figures 20-2 to 20-4) after reset processing. Reset by POC and LVI circuit
power supply detection is automatically released when VDD ≥ VPOC or VDD ≥ VLVI after the reset, and program
execution starts using the internal high-speed oscillation clock (see CHAPTER 21 POWER-ON-CLEAR CIRCUIT
and CHAPTER 22 LOW-VOLTAGE DETECTOR) after reset processing.
Cautions 1. For an external reset, input a low level for 10 μs or more to the RESET pin.
2. During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and internal
low-speed oscillation clock stop oscillating. External main system clock input and external
subsystem clock input become invalid.
3. When the STOP mode is released by a reset, the STOP mode contents are held during reset
input. However, the port pins become high-impedance.
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492
Figure 20-1. Block Diagram of Reset Function
Internal bus
Reset control flag
register (RESF)
WDTRF
Set
LVIRF
Set
Watchdog timer reset signal
Clear
Reset signal to LVIM/LVIS register
Power-on-clear circuit reset signal
Low-voltage detector reset signal
Caution An LVI circuit internal reset does not reset the LVI circuit.
Remarks 1. LVIM: Low-voltage detection register
2. LVIS: Low-voltage detection level selection register
Reset signal
CHAPTER 20 RESET FUNCTION
User’s Manual U17734EJ2V0UD
RESET
Clear
CHAPTER 20 RESET FUNCTION
Figure 20-2. Timing of Reset by RESET Input
Wait for oscillation
accuracy
stabilization
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
High-speed system clock
(when X1 oscillation is selected)
CPU clock
Reset
processing
(20 μs (TYP.))
Reset period
(oscillation stop)
Normal operation
Normal operation
(internal high-speed oscillation clock)
RESET
Internal reset signal
Delay
Delay
(5 μ s (TYP.))
Hi-Z
Port pin
Reset signal to
LCD controller/driver
Note
Note Set P130 (bit 0 of port mode register 13) to 1 by software.
Figure 20-3. Timing of Reset Due to Watchdog Timer Overflow
Wait for oscillation
accuracy
stabilization
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
High-speed system clock
(when X1 oscillation is selected)
CPU clock
Normal operation
Reset period
(oscillation stop)
Reset
processing
(20 μs (TYP.))
Normal operation
(internal high-speed oscillation clock)
Watchdog timer
overflow
Internal reset signal
Hi-Z
Port pin
Reset signal to
LCD controller/driver
Note
Note Set P130 (bit 0 of port mode register 13) to 1 by software.
Caution A watchdog timer internal reset resets the watchdog timer.
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CHAPTER 20 RESET FUNCTION
Figure 20-4. Timing of Reset in STOP Mode by RESET Input
Wait for oscillation
accuracy
stabilization
STOP instruction execution
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
High-speed system clock
(when X1 oscillation is selected)
CPU clock
Normal
operation
Stop status
(oscillation stop)
Reset period
(oscillation stop)
Reset
processing
Normal operation
(internal high-speed oscillation clock)
(20 μs (TYP.))
RESET
Internal reset signal
Delay
Delay
(5 μs (TYP.))
Port pin
Hi-Z
Reset signal to
LCD controller/driver
Note
Note Set P130 (bit 0 of port mode register 13) to 1 by software.
Remark For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 21 POWERON-CLEAR CIRCUIT and CHAPTER 22 LOW-VOLTAGE DETECTOR.
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CHAPTER 20 RESET FUNCTION
Table 20-1. Operation Statuses During Reset Period
Item
During Reset Period
System clock
Clock supply to the CPU is stopped.
Main system clock
Subsystem clock
fRH
Operation stopped
fX
Operation stopped (pin is I/O port mode)
fEXCLK
Clock input invalid (pin is I/O port mode)
fXT
Operation stopped (pin is I/O port mode)
fEXCLKS
Clock input invalid (pin is I/O port mode)
fRL
Operation stopped
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event counter 00
8-bit timer/event
50
counter
51
8-bit timer
H0
H1
Watch timer
Watchdog timer
Clock output
A/D converter
Serial interface
UART0
UART6
CSI10
IIC0
LCD controller/driver
Power-on-clear function
Operable
Low-voltage detection function
Operation stopped
External interrupt
Remark fRH:
Internal high-speed oscillation clock
fX:
X1 oscillation clock
fEXCLK:
External main system clock
fXT:
XT1 oscillation clock
fEXCLKS: External subsystem clock
fRL:
Internal low-speed oscillation clock
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CHAPTER 20 RESET FUNCTION
Table 20-2. Hardware Statuses After Reset Acknowledgment (1/3)
Hardware
After Reset
Note 1
Acknowledgment
Program counter (PC)
The contents of the
reset vector table
(0000H, 0001H) are
set.
Stack pointer (SP)
Undefined
Program status word (PSW)
02H
RAM
Data memory
Undefined
Note 2
General-purpose registers
Undefined
Note 2
Port registers (P0 to P3, P12, P13) (output latches)
00H
Port mode registers (PM0 to PM3, PM6, PM7, PM12, PM14)
FFH
Pull-up resistor option registers (PU0, PU1, PU3, PU12)
00H
Internal memory size switching register (IMS)
CFH
Note 3
Clock operation mode select register (OSCCTL)
00H
Processor clock control register (PCC)
01H
Internal oscillation mode register (RCM)
80H
Main OSC control register (MOC)
80H
Main clock mode register (MCM)
00H
Oscillation stabilization time counter status register (OSTC)
00H
Oscillation stabilization time select register (OSTS)
05H
16-bit timer/event
counters 00
Timer counters 00 (TM00)
0000H
Capture/compare registers 000, 010 (CR000, CR010)
0000H
Notes 1.
Mode control registers 00 (TMC00)
00H
Prescaler mode registers 00 (PRM00)
00H
Capture/compare control registers 00 (CRC00)
00H
Timer output control registers 00 (TOC00)
00H
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
2.
When a reset is executed in the standby mode, the pre-reset status is held even after reset.
3.
Regardless of the internal memory capacity, the initial values of the internal memory size switching
register (IMS) of all products in the 78K0/LE2 are fixed (IMS = CFH).
Therefore, set the value
corresponding to each product as indicated below.
Flash Memory Version
IMS
(78K0/LE2)
μPD78F0361
04H
μPD78F0362
C6H
μPD78F0363, 78F0363D
Note4
4.
C8H
The ROM and RAM capacities of the products with the on-chip debug function can be debugged
according to the debug target products. Set IMS according to the debug target products.
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Table 20-2. Hardware Statuses After Reset Acknowledgment (2/3)
Hardware
Status After Reset
Acknowledgment
8-bit timer/event counters
50, 51
8-bit timers H0, H1
Timer counters 50, 51 (TM50, TM51)
00H
Compare registers 50, 51 (CR50, CR51)
00H
Timer clock selection registers 50, 51 (TCL50, TCL51)
00H
Mode control registers 50, 51 (TMC50, TMC51)
00H
Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11)
00H
Mode registers (TMHMD0, TMHMD1)
00H
Note 2
Carrier control register 1 (TMCYC1)
00H
Watch timer
Operation mode register (WTM)
00H
Clock output controller
Clock output selection register (CKS)
00H
Watchdog timer
Enable register (WDTE)
1AH/9AH
A/D converter
10-bit A/D conversion result register (ADCR)
0000H
8-bit A/D conversion result register (ADCRH)
00H
Mode register (ADM)
00H
Analog input channel specification register (ADS)
00H
A/D port configuration register (ADPC)
00H
Receive buffer register 0 (RXB0)
FFH
Transmit shift register 0 (TXS0)
FFH
Asynchronous serial interface operation mode register 0 (ASIM0)
01H
Serial interface UART0
Serial interface UART6
Serial interfaces CSI10
Notes 1.
Note 1
Asynchronous serial interface reception error status register 0 (ASIS0)
00H
Baud rate generator control register 0 (BRGC0)
1FH
Receive buffer register 6 (RXB6)
FFH
Transmit buffer register 6 (TXB6)
FFH
Asynchronous serial interface operation mode register 6 (ASIM6)
01H
Asynchronous serial interface reception error status register 6 (ASIS6)
00H
Asynchronous serial interface transmission status register 6 (ASIF6)
00H
Clock selection register 6 (CKSR6)
00H
Baud rate generator control register 6 (BRGC6)
FFH
Asynchronous serial interface control register 6 (ASICL6)
16H
Input switch control register (ISC)
00H
Transmit buffer registers 10 (SOTB10)
00H
Serial I/O shift registers 10 (SIO10)
00H
Serial operation mode registers 10 (CSIM10)
00H
Serial clock selection registers 10 (CSIC10)
00H
Note 3
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
2.
8-bit timer H1 only.
3.
The reset value of WDTE is determined by the option byte setting.
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CHAPTER 20 RESET FUNCTION
Table 20-2. Hardware Statuses After Reset Acknowledgment (3/3)
Status After Reset
Hardware
Acknowledgment
Serial interface IIC0
LCD controller/driver
Shift register 0 (IIC0)
00H
Control register 0 (IICC0)
00H
Slave address register 0 (SVA0)
00H
Clock selection register 0 (IICCL0)
00H
Function expansion register 0 (IICX0)
00H
Status register 0 (IICS0)
00H
Flag register 0 (IICF0)
00H
LCD mode setting register (LCDMD)
00H
LCD display mode register (LCDM)
00H
LCD clock control register (LCDC)
00H
LCD voltage boost control register 0 (VLCG0)
00H
Reset function
Reset control flag register (RESF)
00H
Low-voltage detector
Low-voltage detection register (LVIM)
00H
Low-voltage detection level selection register (LVIS)
00H
Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H)
00H
Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H)
FFH
Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L,
FFH
Interrupt
Note 1
Note 2
Note 2
Note 2
PR1H)
Notes 1.
External interrupt rising edge enable register (EGP)
00H
External interrupt falling edge enable register (EGN)
00H
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
2.
These values vary depending on the reset source.
Reset Source
RESET Input
Reset by POC
Reset by WDT
Reset by LVI
Register
RESF
WDTRF bit
Cleared (0)
Cleared (0)
LVIRF bit
LVIM
Cleared (00H)
Cleared (00H)
Set (1)
Held
Held
Set (1)
Cleared (00H)
Held
LVIS
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CHAPTER 20 RESET FUNCTION
20.1 Register for Confirming Reset Source
Many internal reset generation sources exist in the 78K0/LE2. The reset control flag register (RESF) is used to
store which source has generated the reset request.
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H.
Figure 20-5. Format of Reset Control Flag Register (RESF)
Address: FFACH
After reset: 00H
Note
R
Symbol
7
6
5
4
3
2
1
0
RESF
0
0
0
WDTRF
0
0
0
LVIRF
WDTRF
Internal reset request by watchdog timer (WDT)
0
Internal reset request is not generated, or RESF is cleared.
1
Internal reset request is generated.
LVIRF
Internal reset request by low-voltage detector (LVI)
0
Internal reset request is not generated, or RESF is cleared.
1
Internal reset request is generated.
Note The value after reset varies depending on the reset source.
Caution Do not read data by a 1-bit memory manipulation instruction.
The status of RESF when a reset request is generated is shown in Table 20-3.
Table 20-3. RESF Status When Reset Request Is Generated
Reset Source
RESET Input
Reset by POC
Reset by WDT
Reset by LVI
Flag
WDTRF
LVIRF
Cleared (0)
Cleared (0)
Set (1)
Held
Held
Set (1)
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CHAPTER 21 POWER-ON-CLEAR CIRCUIT
21.1 Functions of Power-on-Clear Circuit
The power-on-clear circuit (POC) has the following functions.
• Generates internal reset signal at power on.
In the 1.59 V POC mode (option byte: POCMODE = 0), the reset signal is released when the supply voltage
(VDD) exceeds 1.59 V ±0.15 V.
In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the reset signal is released when the supply
voltage (VDD) exceeds 2.7 V ±0.2 V.
• Compares supply voltage (VDD) and detection voltage (VPOC = 1.59 V ±0.15 V), generates internal reset signal
when VDD < VPOC, and releases reset when VDD ≥ VPOC.
Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF)
is cleared to 00H.
Remark The 78K0/LE2 incorporates multiple hardware functions that generate an internal reset signal. A flag
that indicates the reset source is located in the reset control flag register (RESF) for when an internal
reset signal is generated by the watchdog timer (WDT) or low-voltage-detector (LVI). RESF is not
cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT or LVI.
For details of RESF, see CHAPTER 20 RESET FUNCTION.
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CHAPTER 21 POWER-ON-CLEAR CIRCUIT
21.2 Configuration of Power-on-Clear Circuit
The block diagram of the power-on-clear circuit is shown in Figure 21-1.
Figure 21-1. Block Diagram of Power-on-Clear Circuit
VDD
VDD
+
Internal reset signal
−
Reference
voltage
source
21.3 Operation of Power-on-Clear Circuit
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
• An internal reset signal is generated on power application.
When the supply voltage (VDD) exceeds the
detection voltage (VPOC = 1.59 V ±0.15 V), the reset status is released.
• The supply voltage (VDD) and detection voltage (VPOC = 1.59 V ±0.15 V) are compared. When VDD < VPOC, the
internal reset signal is generated. It is released when VDD ≥ VPOC.
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
• An internal reset signal is generated on power application.
When the supply voltage (VDD) exceeds the
detection voltage (VDDPOC = 2.7 V ±0.2 V), the reset status is released.
• The supply voltage (VDD) and detection voltage (VPOC = 1.59 V ±0.15 V) are compared. When VDD < VPOC, the
internal reset signal is generated. It is released when VDD ≥ VPOC.
The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is
shown below.
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CHAPTER 21 POWER-ON-CLEAR CIRCUIT
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (1/2)
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
Set LVI to be
used for interrupt
Set LVI to be
used for reset
Set LVI to be
used for reset
VLVI
Supply voltage
(VDD)
1.8 VNote 1
VPOC = 1.59 V (TYP.)
0.5 V/ms (MAX.)
Note 2
0V
Wait for oscillation
accuracy
stabilization
Wait for oscillation
accuracy
stabilization
Wait for oscillation
accuracy
stabilization
Internal high-speed
oscillation clock (fRH)
Starting oscillation is
specified by software.
Starting oscillation is
specified by software.
High-speed
system clock (fXH)
(when X1 oscillation
is selected)
Operation
CPU
stops
Wait for voltage
stabilization
(3.24 ms (TYP.))
Normal operation Reset period
(internal high-speed (oscillation
oscillation clock)Note 3 stop)
Reset processing (20 μs (TYP.))
Starting oscillation is
specified by software.
Normal operation Reset period Wait for voltage
stabilization
(internal high-speed (oscillation
(3.24 ms (TYP.))
oscillation clock)Note 3 stop)
Reset processing (20 μs (TYP.))
Normal operation
(internal high-speed
oscillation clock)Note 3
Operation stops
Reset processing (20 μs (TYP.))
Internal reset signal
Notes 1.
The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
2.
If the voltage rises to 1.8 V at a rate slower than 0.5 V/ms (MAX.) on power application, input a low
level to the RESET pin after power application and before the voltage reaches 1.8 V, or set the 2.7
V/1.59 V POC mode by using an option byte (POCMODE = 1).
3.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 22
LOW-VOLTAGE DETECTOR).
Remark
VLVI: LVI detection voltage
VPOC: POC detection voltage
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CHAPTER 21 POWER-ON-CLEAR CIRCUIT
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (2/2)
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
Set LVI to be
used for reset
Set LVI to be
used for interrupt
Wait for oscillation
accuracy
stabilization
Wait for oscillation
accuracy
stabilization
Set LVI to be
used for reset
VLVI
Supply voltage 2.7 V (TYP.)
(VDD)
1.8 VNote 1
VPOC = 1.59 V (TYP.)
0V
Wait for oscillation
accuracy
stabilization
Internal high-speed
oscillation clock (fRH)
Starting oscillation is
specified by software.
High-speed
system clock (fXH)
(when X1 oscillation
is selected)
CPU
Normal operation Reset period
(internal high-speed (oscillation
stop)
oscillation clock)Note 2
Operation
stops
Reset processing (20 μs (TYP.))
Starting oscillation is
specified by software.
Starting oscillation is
specified by software.
Normal operation
(internal high-speed
oscillation clock)Note 2
Reset processing (20 μs (TYP.))
Reset period
(oscillation
stop)
Normal operation
(internal high-speed
oscillation clock)Note 2
Operation stops
Reset processing (20 μs (TYP.))
Internal reset signal
Notes 1.
The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
2.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 22
LOW-VOLTAGE DETECTOR).
Remark
VLVI: LVI detection voltage
VPOC: POC detection voltage
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CHAPTER 21 POWER-ON-CLEAR CIRCUIT
21.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection
voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
Figure 21-3. Example of Software Processing After Reset Release (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Reset
Initialization
processing
; Check the reset sourceNote 2
Initialize the port.
Power-on-clear
; fPRS = Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default)
Source: fPRS (8.4 MHz (MAX.))/212,
where comparison value = 102: ≅ 50 ms
Timer starts (TMHE1 = 1).
Setting 8-bit timer H1
(to measure 50 ms)
Clearing WDT
Note 1
No
50 ms has passed?
(TMIFH1 = 1?)
Yes
; Setting of division ratio of system clock,
such as setting of timer or A/D converter
Initialization
processing
Notes 1.
2.
504
If reset is generated again during this period, initialization processing is not started.
A flowchart is shown on the next page.
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CHAPTER 21 POWER-ON-CLEAR CIRCUIT
Figure 21-3. Example of Software Processing After Reset Release (2/2)
• Checking reset source
Check reset source
WDTRF of RESF
register = 1?
Yes
No
Reset processing by
watchdog timer
LVIRF of RESF
register = 1?
Yes
No
Reset processing by
low-voltage detector
Power-on-clear/external
reset generated
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CHAPTER 22 LOW-VOLTAGE DETECTOR
22.1 Functions of Low-Voltage Detector
The low-voltage detector (LVI) has the following functions.
• Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or
internal reset signal when VDD < VLVI. Detection levels (16 levels) of supply voltage can be changed by software.
• Compares a voltage input from an external input pin (EXLVI) with the detection voltage (VEXLVI = 1.21 V (TYP.)),
and generates an internal interrupt signal or internal reset signal when EXLVI < VEXLVI.
• The supply voltage (VDD) or voltage input from an external input pin (EXLVI) can be selected by software.
• Interrupt or reset function can be selected by software.
• Operable in STOP mode.
When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if
reset occurs. For details of RESF, see CHAPTER 20 RESET FUNCTION.
22.2 Configuration of Low-Voltage Detector
The block diagram of the low-voltage detector is shown in Figure 22-1.
Figure 22-1. Block Diagram of Low-Voltage Detector
VDD
N-ch
Internal reset signal
Selector
EXLVI/P120/
INTP0
+
Selector
Low-voltage detection
level selector
VDD
−
INTLVI
Reference
voltage
source
4
LVION LVISEL LVIMD
LVIS3 LVIS2 LVIS1 LVIS0
Low-voltage detection level
selection register (LVIS)
Low-voltage detection register
(LVIM)
Internal bus
506
LVIF
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CHAPTER 22 LOW-VOLTAGE DETECTOR
22.3 Registers Controlling Low-Voltage Detector
The low-voltage detector is controlled by the following registers.
• Low-voltage detection register (LVIM)
• Low-voltage detection level selection register (LVIS)
• Port mode register 12 (PM12)
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CHAPTER 22 LOW-VOLTAGE DETECTOR
(1) Low-voltage detection register (LVIM)
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets LVIM to 00H.
Figure 22-2. Format of Low-Voltage Detection Register (LVIM)
Address: FFBEH
After reset: 00H
R/WNote 1
Symbol
6
5
4
3
LVIM
LVION
0
0
0
0
LVISEL
LVIMD
LVIF
Notes 2, 3
LVION
Enables low-voltage detection operation
0
Disables operation
1
Enables operation
Note 2
LVISEL
Voltage detection selection
0
Detects level of supply voltage (VDD)
1
Detects level of input voltage from external input pin (EXLVI)
Note 2
LVIMD
Low-voltage detection operation mode selection
0
• LVISEL = 0: Generates interrupt signal when supply voltage (VDD) < detection voltage
(VLVI)
• LVISEL = 1: Generates interrupt signal when input voltage from external input pin
(EXLVI) < detection voltage (VEXLVI)
1
• LVISEL = 0: Generates internal reset signal when supply voltage (VDD) < detection
voltage (VLVI)
• LVISEL = 1: Generates internal reset signal when input voltage from external input pin
(EXLVI) < detection voltage (VEXLVI)
Note 4
LVIF
Low-voltage detection flag
0
• LVISEL = 0: Supply voltage (VDD) ≥ detection voltage (VLVI), or when operation is
disabled
• LVISEL = 1: Input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI),
or when operation is disabled
1
• LVISEL = 0: Supply voltage (VDD) < detection voltage (VLVI)
• LVISEL = 1: Input voltage from external input pin (EXLVI) < detection voltage (VEXLVI)
Notes 1.
2.
Bit 0 is read-only.
LVION, LVIMD, and LVISEL are cleared to 0 in the case of a reset other than an LVI reset.
These are not cleared to 0 in the case of an LVI reset.
3.
When LVION is set to 1, operation of the comparator in the LVI circuit is started.
Use
software to wait for an operation stabilization time (10 μs (MAX.)) when LVION is set to 1 until
the voltage is confirmed at LVIF.
4.
The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and
LVIMD = 0.
Cautions 1. To stop LVI, follow either of the procedures below.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
2. Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
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(2) Low-voltage detection level selection register (LVIS)
This register selects the low-voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation input sets LVIS to 00H.
Figure 22-3. Format of Low-Voltage Detection Level Selection Register (LVIS)
Address: FFBFH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
LVIS
0
0
0
0
LVIS3
LVIS2
LVIS1
LVIS0
LVIS3
LVIS2
LVIS1
LVIS0
0
0
0
0
VLVI0 (4.24 V ±0.1 V)
0
0
0
1
VLVI1 (4.09 V ±0.1 V)
0
0
1
0
VLVI2 (3.93 V ±0.1 V)
0
0
1
1
VLVI3 (3.78 V ±0.1 V)
0
1
0
0
VLVI4 (3.62 V ±0.1 V)
0
1
0
1
VLVI5 (3.47 V ±0.1 V)
0
1
1
0
VLVI6 (3.32 V ±0.1 V)
0
1
1
1
VLVI7 (3.16 V ±0.1 V)
1
0
0
0
VLVI8 (3.01 V ±0.1 V)
1
0
0
1
VLVI9 (2.85 V ±0.1 V)
1
0
1
0
VLVI10 (2.70 V ±0.1 V)
1
0
1
1
VLVI11 (2.55 V ±0.1 V)
1
1
0
0
VLVI12 (2.39 V ±0.1 V)
1
1
0
1
VLVI13 (2.24 V ±0.1 V)
1
1
1
0
VLVI14 (2.08 V ±0.1 V)
1
1
1
1
VLVI15 (1.93 V ±0.1 V)
Detection level
Cautions 1. Be sure to clear bits 4 to 7 to 0.
2. Do not change the value of LVIS during LVI operation.
3. When an input voltage from the external input pin (EXLVI) is detected, the detection
voltage (VEXLVI = 1.21 V (TYP.)) is fixed. Therefore, setting of LVIS is not necessary.
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CHAPTER 22 LOW-VOLTAGE DETECTOR
(3) Port mode register 12 (PM12)
When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this
time, the output latch of P120 may be 0 or 1.
PM12 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM12 to FFH.
Figure 22-4. Format of Port Mode Register 12 (PM12)
Address: FF2CH
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM12
1
1
1
PM124
PM123
PM122
PM121
PM120
PM12n
P12n pin I/O mode selection (n = 0 to 4)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
22.4 Operation of Low-Voltage Detector
The low-voltage detector can be used in the following two modes.
(1) Used as reset
• If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI), generates an internal reset
signal when VDD < VLVI, and releases internal reset when VDD ≥ VLVI.
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI = 1.21
V (TYP.)), generates an internal reset signal when EXLVI < VEXLVI, and releases internal reset when EXLVI ≥
VEXLVI.
(2) Used as interrupt
• If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt
signal (INTLVI) when VDD < VLVI.
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI = 1.21
V (TYP.)), and generates an interrupt signal (INTLVI) when EXLVI < VEXLVI.
Remark LVISEL: Bit 2 of low-voltage detection register (LVIM)
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22.4.1 When used as reset
(1) When detecting level of supply voltage (VDD)
• When starting operation
Mask the LVI interrupt (LVIMK = 1).
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
(VDD)) (default value).
Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection
register (LVIS).
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
Use software to wait for an operation stabilization time (10 μs (MAX.)).
Wait until it is checked that (supply voltage (VDD) ≥ detection voltage (VLVI)) by bit 0 (LVIF) of LVIM.
Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (VDD) < detection
voltage (VLVI)).
Figure 22-5 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers
in this timing chart correspond to to above.
Cautions 1. must always be executed. When LVIMK = 0, an interrupt may occur immediately
after the processing in .
2. If supply voltage (VDD) ≥ detection voltage (VLVI) when LVIMD is set to 1, an internal reset
signal is not generated.
• When stopping operation
Either of the following procedures must be executed.
•
When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
•
When using 1-bit memory manipulation instruction:
Clear LVIMD to 0 and then LVION to 0.
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Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Detects Level of Supply Voltage (VDD)) (1/2)
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
Supply voltage (VDD)
VLVI
VPOC = 1.59 V (TYP.)
Time
LVIMK flag Note 1
(set by software) H
LVISEL flag
(set by software) L
LVION flag
(set by software)
Not cleared
Not cleared
Clear
Wait time
LVIF flag
LVIMD flag
(set by software)
Clear
Note 2
Not cleared
Not cleared
Clear
LVIRF flagNote 3
LVI reset signal
Cleared by
software
Cleared by
software
POC reset signal
Internal reset signal
Notes 1.
2.
3.
The LVIMK flag is set to “1” by reset signal generation.
The LVIF flag may be set (1).
LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 20 RESET
FUNCTION.
Remark
to in Figure 22-5 above correspond to to in the description of “When starting
operation” in 22.4.1 (1) When detecting level of supply voltage (VDD).
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Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Detects Level of Supply Voltage (VDD)) (2/2)
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
Supply voltage (VDD)
VLVI
2.7 V (TYP.)
VPOC = 1.59 V (TYP.)
Time
LVIMK flag
(set by software)
HNote 1
LVISEL flag
(set by software)
L
LVION flag
(set by software)
Not cleared
Not cleared
Clear
Wait time
LVIF flag
LVIMD flag
(set by software)
Clear
Note 2
Not cleared
Not cleared
Clear
LVIRF flagNote 3
LVI reset signal
Cleared by
software
Cleared by
software
POC reset signal
Internal reset signal
Notes 1.
2.
3.
The LVIMK flag is set to “1” by reset signal generation.
The LVIF flag may be set (1).
LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 20
RESET FUNCTION.
Remark
to in Figure 22-5 above correspond to to in the description of “When starting
operation” in 22.4.1 (1) When detecting level of supply voltage (VDD).
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CHAPTER 22 LOW-VOLTAGE DETECTOR
(2) When detecting level of input voltage from external input pin (EXLVI)
• When starting operation
Mask the LVI interrupt (LVIMK = 1).
Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from
external input pin (EXLVI)).
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
Use software to wait for an operation stabilization time (10 μs (MAX.)Note).
Wait until it is checked that (input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI =
1.21 V (TYP.))) by bit 0 (LVIF) of LVIM.
Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when input voltage from external input pin
(EXLVI) < detection voltage (VEXLVI = 1.21 V (TYP.))).
Figure 22-6 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers
in this timing chart correspond to to above.
Cautions 1. must always be executed. When LVIMK = 0, an interrupt may occur immediately
after the processing in .
2. If input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI = 1.21 V (TYP.))
when LVIMD is set to 1, an internal reset signal is not generated.
3. Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
• When stopping operation
Either of the following procedures must be executed.
•
When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
•
When using 1-bit memory manipulation instruction:
Clear LVIMD to 0 and then LVION to 0.
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Figure 22-6. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Detects Level of Input Voltage from External Input Pin (EXLVI))
Input voltage from
external input pin (EXLVI)
LVI detection voltage
(VEXLVI)
Time
LVIMK flag
(set by software)
LVISEL flag
(set by software)
HNote 1
Not cleared
Not cleared
Not cleared
Not cleared
Not cleared
Not cleared
Not cleared
Not cleared
LVION flag
(set by software)
Wait time
LVIF flag
LVIMD flag
(set by software)
Note 2
Not cleared
LVIRF flagNote 3
LVI reset signal
Cleared by
software
Cleared by
software
Internal reset signal
Notes 1.
The LVIMK flag is set to “1” by reset signal generation.
2.
The LVIF flag may be set (1).
3.
LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 20
RESET FUNCTION.
Remark
to in Figure 22-6 above correspond to to in the description of “When starting
operation” in 22.4.1 (2) When detecting level of input voltage from external input pin (EXLVI).
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CHAPTER 22 LOW-VOLTAGE DETECTOR
22.4.2 When used as interrupt
(1) When detecting level of supply voltage (VDD)
• When starting operation
Mask the LVI interrupt (LVIMK = 1).
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
(VDD)) (default value).
Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection
register (LVIS).
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
Use software to wait for an operation stabilization time (10 μs (MAX.)).
Confirm that “supply voltage (VDD) ≥ detection voltage (VLVI)” at bit 0 (LVIF) of LVIM.
Clear the interrupt request flag of LVI (LVIIF) to 0.
Release the interrupt mask flag of LVI (LVIMK).
Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when supply voltage (VDD) < detection
voltage (VLVI)) (default value).
Execute the EI instruction (when vector interrupts are used).
Figure 22-7 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to to above.
• When stopping operation
Either of the following procedures must be executed.
•
When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
•
When using 1-bit memory manipulation instruction:
Clear LVION to 0.
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Figure 22-7. Timing of Low-Voltage Detector Interrupt Signal Generation
(Detects Level of Supply Voltage (VDD)) (1/2)
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
Supply voltage (VDD)
VLVI
VPOC = 1.59 V (TYP.)
Time
LVIMK flag
(set by software)
Note 1
LVISEL flag
(set by software)
Cleared by software
L
LVION flag
(set by software)
Wait time
LVIF flag
Note 2
INTLVI
Note 2
LVIIF flag
Note 2
LVIMD flag
(set by software) L
Cleared by software
Internal reset signal
Notes 1.
2.
Remark
The LVIMK flag is set to “1” by reset signal generation.
The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
to in Figure 22-7 above correspond to to in the description of “When starting
operation” in 22.4.2 (1) When detecting level of supply voltage (VDD).
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CHAPTER 22 LOW-VOLTAGE DETECTOR
Figure 22-7. Timing of Low-Voltage Detector Interrupt Signal Generation
(Detects Level of Supply Voltage (VDD)) (2/2)
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
Supply voltage (VDD)
VLVI
2.7 V(TYP.)
VPOC = 1.59 V (TYP.)
Time
LVIMK flag
(set by software)
Note 1
LVISEL flag
(set by software)
Cleared by software
L
LVION flag
(set by software)
Wait time
LVIF flag
Note 2
INTLVI
Note 2
LVIIF flag
LVIMD flag
(set by software)
Note 2
Cleared by software
L
Internal reset signal
Notes 1.
2.
Remark
The LVIMK flag is set to “1” by reset signal generation.
The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
to in Figure 22-7 above correspond to to in the description of “When starting
operation” in 22.4.2 (1) When detecting level of supply voltage (VDD).
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CHAPTER 22 LOW-VOLTAGE DETECTOR
(2) When detecting level of input voltage from external input pin (EXLVI)
• When starting operation
Mask the LVI interrupt (LVIMK = 1).
Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from
external input pin (EXLVI)).
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
Use software to wait for an operation stabilization time (10 μs (MAX.)).
Confirm that “input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI = 1.21 V (TYP.)” at
bit 0 (LVIF) of LVIM.
Clear the interrupt request flag of LVI (LVIIF) to 0.
Release the interrupt mask flag of LVI (LVIMK).
Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when supply voltage (VDD) < detection
voltage (VLVI)) (default value).
Execute the EI instruction (when vector interrupts are used).
Figure 22-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to to above.
Caution Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
• When stopping operation
Either of the following procedures must be executed.
•
When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
•
When using 1-bit memory manipulation instruction:
Clear LVION to 0.
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CHAPTER 22 LOW-VOLTAGE DETECTOR
Figure 22-8. Timing of Low-Voltage Detector Interrupt Signal Generation
(Detects Level of Input Voltage from External Input Pin (EXLVI))
Input voltage from
external input pin (EXLVI)
VEXLVI
Time
LVIMK flag
(set by software)
Note 1
Cleared by software
LVISEL flag
(set by software)
LVION flag
(set by software)
Wait time
LVIF flag
Note 2
INTLVI
Note 2
LVIIF flag
Note 2
LVIMD flag
(set by software) L
Cleared by software
Notes 1.
2.
Remark
The LVIMK flag is set to “1” by reset signal generation.
The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
to in Figure 22-8 above correspond to to in the description of “When starting
operation” in 22.4.2 (1) When detecting level of supply voltage (VDD).
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22.5 Cautions for Low-Voltage Detector
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage
(VLVI), the operation is as follows depending on how the low-voltage detector is used.
(1) When used as reset
The system may be repeatedly reset and released from the reset status.
In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set
by taking action (1) below.
(2) When used as interrupt
Interrupt requests may be frequently generated. Take (b) of action (2) below.
In this system, take the following actions.
(1) When used as reset
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports (see Figure 22-9).
(2) When used as interrupt
(a) Check that “supply voltage (VDD) ≥ detection voltage (VLVI)” in the servicing routine of the LVI interrupt by
using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 0 (LVIIF) of interrupt request flag
register 0L (IF0L) to 0.
(b) In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait
for the supply voltage fluctuation period, check that “supply voltage (VDD) ≥ detection voltage (VLVI)” using the
LVIF flag, and clear the LVIIF flag to 0.
Remark If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above
words change as follows.
• Supply voltage (VDD)
→ Input voltage from external input pin (EXLVI)
Note
• Detection voltage (VLVI) → Detection voltage (VEXLVI = 1.21 V )
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CHAPTER 22 LOW-VOLTAGE DETECTOR
Figure 22-9. Example of Software Processing After Reset Release (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
Reset
; Check the reset sourceNote
Initialize the port.
Initialization
processing
LVI reset
; Setting of detection level by LVIS
The low-voltage detector operates (LVION = 1).
Setting LVI
; fPRS = Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default)
Source: fPRS (8.4 MHz (MAX.))/212,
Where comparison value = 102: ≅ 50 ms
Timer starts (TMHE1 = 1).
Setting 8-bit timer H1
(to measure 50 ms)
Clearing WDT
Detection
voltage or higher
(LVIF = 0?)
Yes
No
LVIF = 0
Restarting timer H1
(TMHE1 = 0 → TMHE1 = 1)
No
; The low-voltage detection flag is cleared.
; The timer counter is cleared and the timer is started.
50 ms has passed?
(TMIFH1 = 1?)
Yes
Initialization
processing
; Setting of division ratio of system clock,
such as setting of timer or A/D converter
Note A flowchart is shown on the next page.
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Figure 22-9. Example of Software Processing After Reset Release (2/2)
• Checking reset source
Check reset source
WDTRF of RESF
register = 1?
Yes
No
Reset processing by
watchdog timer
LVIRF of RESF
register = 1?
No
Yes
Power-on-clear/external
reset generated
Reset processing by
low-voltage detector
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CHAPTER 23 OPTION BYTE
23.1
Functions of Option Bytes
The flash memory at 0080H to 0084H of the 78K0/LE2 is an option byte area. When power is turned on or when
the device is restarted from the reset status, the device automatically references the option bytes and sets specified
functions. When using the product, be sure to set the following functions by using the option bytes.
When the boot swap operation is used during self-programming, 0080H to 0084H are switched to 1080H to 1084H.
Therefore, set values that are the same as those of 0080H to 0084H to 1080H to 1084H in advance.
(1) 0080H/1080H
{ Internal low-speed oscillator operation
• Can be stopped by software
• Cannot be stopped
{ Watchdog timer interval time setting
{ Watchdog timer counter operation
• Enabled counter operation
• Disabled counter operation
{ Watchdog timer window open period setting
(2) 0081H/1081H
{ Selecting POC mode
• During 2.7 V/1.59 V POC mode operation (POCMODE = 1)
The device is in the reset state upon power application and until the supply voltage reaches 2.7 V (TYP.). It
is released from the reset state when the voltage exceeds 2.7 V (TYP.). After that, POC is not detected at
2.7 V but is detected at 1.59 V (TYP.).
If the supply voltage rises to 1.8 V after power application at a pace slower than 0.5 V/ms (MAX.), use of the
2.7 V/1.59 V POC mode is recommended.
• During 1.59 V POC mode operation (POCMODE = 0)
The device is in the reset state upon power application and until the supply voltage reaches 1.59 V (TYP.).
It is released from the reset state when the voltage exceeds 1.59 V (TYP.). After that, POC is detected at
1.59 V (TYP.), in the same manner as on power application.
(3) 0084H/1084H
{ On-chip debug operation control
• Disabling on-chip debug operation
• Enabling on-chip debug operation and erasing data of the flash memory in case authentication of the onchip debug security ID fails
• Enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of
the on-chip debug security ID fails
Cautions 1. Be sure to set 00H (disabling on-chip debug operation) to 0084H for products not equipped
with the on-chip debug function (μPD78F0361, 78F0362, and 78F0363). Also set 00H to
1084H because 0084H and 1084H are switched at boot swapping.
2. To use the on-chip debug function with products equipped with the on-chip debug function
(μPD78F0363D), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to
1084H because 0084H and 1084H are switched at boot swapping.
Caution Be sure to set 00H to 0082H and 0083H (0082H/1082H and 0083H/1083H when the boot swap
function is used).
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23.2
Format of Option Byte
The format of the option byte is shown below.
Figure 23-1. Format of Option Byte (1/2)
Note
Address: 0080H/1080H
7
6
5
4
3
2
1
0
0
WINDOW1
WINDOW0
WDTON
WDCS2
WDCS1
WDCS0
LSROSC
WINDOW1
WINDOW0
0
0
25%
0
1
50%
1
0
75%
1
1
100%
WDTON
Watchdog timer window open period
Operation control of watchdog timer counter/illegal access detection
0
Counter operation disabled (counting stopped after reset), illegal access detection operation
disabled
1
Counter operation enabled (counting started after reset), illegal access detection operation enabled
WDCS2
WDCS1
WDCS0
Watchdog timer overflow time
10
0
0
0
2 /fRL (3.88 ms)
0
0
1
2 /fRL (7.76 ms)
0
1
0
2 /fRL (15.52 ms)
0
1
1
2 /fRL (31.03 ms)
1
0
0
2 /fRL (62.06 ms)
1
0
1
2 /fRL (124.12 ms)
1
1
0
2 /fRL (248.24 ms)
1
1
1
2 /fRL (496.48 ms)
LSROSC
11
12
13
14
15
16
17
Internal low-speed oscillator operation
0
Can be stopped by software (stopped when 1 is written to bit 0 (LSRSTOP) of RCM register)
1
Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit)
Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the
boot swap operation.
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is
prohibited.
2. The watchdog timer does not stop during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
3. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of
the internal oscillation mode register (RCM).
When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is
supplied to 8-bit timer H1 even in the HALT/STOP mode.
4. Be sure to clear bit 7 to 0.
Remarks 1.
2.
fRL: Internal low-speed oscillation clock frequency
( ): fRL = 264 kHz (MAX.)
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CHAPTER 23 OPTION BYTE
Figure 23-1. Format of Option Byte (2/2)
Notes 1, 2
Address: 0081H/1081H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
POCMODE
POCMODE
Notes 1.
POC mode selection
0
1.59 V POC mode (default)
1
2.7 V/1.59 V POC mode
POCMODE can only be written by using a dedicated flash programmer. It cannot be set during selfprogramming or boot swap operation during self-programming (at this time, 1.59 V POC mode (default)
is set). However, because the value of 1081H is copied to 0081H during the boot swap operation, it is
recommended to set a value that is the same as that of 0081H to 1081H when the boot swap function
is used.
2.
To change the setting for the POC mode, set the value to 0081H again after batch erasure (chip
erasure) of the flash memory. The setting cannot be changed after the memory of the specified block
is erased.
Caution Be sure to clear bits 7 to 1 to 0.
Note
Address: 0082H/1082H, 0083H/1083H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Note Be sure to set 00H to 0082H and 0083H, as these addresses are reserved areas. Also set 00H to 1082 and
1083H because 0082H and 0083H are switched with 1082H and 1083H when the boot swap operation is
used.
Notes1, 2
Address: 0084H/1084H
Notes 1.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
OCDEN1
OCDEN0
OCDEN1
OCDEN0
0
0
Operation disabled
0
1
Setting prohibited
1
0
Operation enabled. Does not erase data of the flash memory in case authentication
of the on-chip debug security ID fails.
1
1
Operation enabled. Erases data of the flash memory in case authentication of the
on-chip debug security ID fails.
On-chip debug operation control
Be sure to set 00H (on-chip debug operation disabled) to 0084H for products not equipped with the onchip debug function (μPD78F0361, 78F0362, and 78F0363). Also set 00H to 1084H because 0084H
and 1084H are switched at boot swapping.
2.
To use the on-chip debug function with products equipped with the on-chip debug function
(μPD78F0363D), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to 1084H
because 0084H and 1084H are switched at boot swapping.
Remark
For the on-chip debug security ID, see CHAPTER 25 ON-CHIP DEBUG FUNCTION (μPD78F0363D
ONLY).
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CHAPTER 23 OPTION BYTE
Here is an example of description of the software for setting the option bytes.
OPT
CSEG
OPTION: DB
AT 0080H
30H
; Enables watchdog timer operation (illegal access detection operation),
; Window open period of watchdog timer: 50%,
; Overflow time of watchdog timer: 210/fRL,
; Internal low-speed oscillator can be stopped by software.
Remark
DB
00H
; 1.59 V POC mode
DB
00H
; Reserved area
DB
00H
; Reserved area
DB
00H
; On-chip debug operation disabled
Referencing of the option byte is performed during reset processing. For the reset processing timing,
see CHAPTER 20 RESET FUNCTION.
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CHAPTER 24 FLASH MEMORY
The 78K0/LE2 incorporates the flash memory to which a program can be written, erased, and overwritten while
mounted on the board.
24.1 Internal Memory Size Switching Register
The internal memory capacity can be selected using the internal memory size switching register (IMS).
IMS is set by an 8-bit memory manipulation instruction.
Reset signal generation sets IMS to CFH.
Caution Be sure to set each product to the values shown in Table 24-1 after a reset release.
Figure 24-1. Format of Internal Memory Size Switching Register (IMS)
Address: FFF0H
After reset: CFH
Symbol
7
6
5
4
3
2
1
0
RAM2
RAM1
RAM0
0
ROM3
ROM2
ROM1
ROM0
RAM2
RAM1
RAM0
0
0
0
768 bytes
1
1
0
1024 bytes
IMS
R/W
Other than above
Internal high-speed RAM capacity selection
Setting prohibited
ROM3
ROM2
ROM1
ROM0
0
1
0
0
16 KB
0
1
1
0
24 KB
1
0
0
0
32 KB
Other than above
Internal ROM capacity selection
Setting prohibited
Caution To set the memory size, set IMS and then IXS. Set the memory size so that the internal ROM and
internal expansion RAM areas do not overlap.
Table 24-1. Internal Memory Size Switching Register Settings
Flash Memory Versions (78K0/LE2)
μPD78F0361
04H
μPD78F0362
C6H
μPD78F0363, 78F0363DNote
C8H
Note
IMS Setting
The ROM and RAM capacities of the products with the on-chip debug function can be
debugged according to the debug target products. Set IMS according to the debug target
products.
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CHAPTER 24 FLASH MEMORY
24.2 Writing with Flash Programmer
Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer.
(1) On-board programming
The contents of the flash memory can be rewritten after the 78K0/LE2 has been mounted on the target system.
The connectors that connect the dedicated flash programmer must be mounted on the target system.
(2) Off-board programming
Data can be written to the flash memory with a dedicated program adapter (FA series) before the 78K0/LE2 is
mounted on the target system.
Remark
The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.
Table 24-2. Wiring Between 78K0/LE2 and Dedicated Flash Programmer
Pin Configuration of Dedicated Flash Programmer
Signal Name
I/O
With CSI10
Pin Function
Pin Name
With UART6
Pin No.
Pin Name
Pin No.
SI/RxD
Input
Receive signal
SO10/P12
48
TxD6/P13
47
SO/TxD
Output
Transmit signal
SI10/RxD0/P11
49
RxD6/P14
46
SCK
Output
Transfer clock
SCK10/TxD0/P10
50
RESET
64
RESET
64
Mode signal
FLMD0
3
FLMD0
3
VDD voltage generation/
VDD
8
VDD
8
Clock to 78K0/LE2
/RESET
Output
Reset signal
FLMD0
Output
VDD
I/O
power monitoring
−
Notes 1.
2.
−
EXCLK/X2/P122
Output
GND
−
−
−
CLK
Ground
Note 1
Note 2
4
LVDD
39
LVDD
39
AVREF
51
AVREF
51
VSS
7
VSS
7
LVSS
38
LVSS
38
AVSS
52
AVSS
52
Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used.
Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. When
using the clock out of the flash programmer, connect CLK and EXCLK of the programmer.
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CHAPTER 24 FLASH MEMORY
Examples of the recommended connection when using the adapter for flash memory writing are shown below.
Figure 24-2. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode
VDD (2.7 to 5.5 V)
GND
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND
VDD
VDD2
SI
SO
SCK
CLK
/RESET FLMD0
WRITER INTERFACE
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CHAPTER 24 FLASH MEMORY
Figure 24-3. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode
VDD (2.7 to 5.5 V)
GND
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND
VDD
VDD2
SI
SO
SCK
CLK
/RESET FLMD0
WRITER INTERFACE
User’s Manual U17734EJ2V0UD
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CHAPTER 24 FLASH MEMORY
24.3 Programming Environment
The environment required for writing a program to the flash memory of the 78K0/LE2 is illustrated below.
Figure 24-4. Environment for Writing Program to Flash Memory
FLMD0
VDD
XXX YYY
XXXXXX
XXXX
XXXX YYYY
Axxxx
Bxxxxx
Cxxxxxx
STATVE
PG-FP4 (Flash Pro4)
VSS
XXXXX
RS-232C
USB
RESET
Dedicated flash
programmer
CSI10/UART6
78K0/LE2
Host machine
A host machine that controls the dedicated flash programmer is necessary.
To interface between the dedicated flash programmer and the 78K0/LE2, CSI10 or UART6 is used for manipulation
such as writing and erasing.
To write the flash memory off-board, a dedicated program adapter (FA series) is
necessary.
24.4 Communication Mode
Communication between the dedicated flash programmer and the 78K0/LE2 is established by serial
communication via CSI10 or UART6 of the 78K0/LE2.
(1) CSI10
Transfer rate: 2.4 kHz to 2.5 MHz
Figure 24-5. Communication with Dedicated Flash Programmer (CSI10)
FLMD0
VDD
GND
STATVE
PG-FP4 (Flash Pro4)
Dedicated flash
programmer
532
VDD/LVDD/AVREF
VSS/LVSS/AVSS
XXXXXX
XXXX
Bxxxxx
Cxxxxxx
XXXXX
XXX YYY
XXXX YYYY
Axxxx
FLMD0
/RESET
RESET
SI/RxD
SO10
SO/TxD
SI10
SCK
SCK10
User’s Manual U17734EJ2V0UD
78K0/LE2
CHAPTER 24 FLASH MEMORY
(2) UART6
Transfer rate: 115200 bps
Figure 24-6. Communication with Dedicated Flash Programmer (UART6)
FLMD0
VDD
GND
VDD/LVDD/AVREF
VSS/LVSS/AVSS
XXXXXX
/RESET
XXXX
Bxxxxx
Cxxxxxx
XXXXX
STATVE
XXX YYY
XXXX YYYY
Axxxx
FLMD0
PG-FP4 (Flash Pro4)
Dedicated flash
programmer
RESET
SI/RxD
TxD6
SO/TxD
RxD6
CLK
78K0/LE2
EXCLK
If FlashPro4 is used as the dedicated flash programmer, FlashPro4 generates the following signal for the 78K0/LE2.
For details, refer to the FlashPro4 manual.
Table 24-3. Pin Connection
FlashPro4
Signal Name
I/O
78K0/LE2
Pin Function
Pin Name
FLMD0
Output
Mode signal
FLMD0
VDD
I/O
VDD voltage generation/power monitoring
VDD, LVDD, AVREF
−
GND
Ground
VSS, LVSS, AVSS
CLK
Output
Clock output to 78K0/LE2
EXCLK
/RESET
Output
Reset signal
RESET
SI/RxD
Input
Receive signal
SO10/TxD6
SO/TxD
Output
Transmit signal
SI10/RxD6
SCK
Output
Transfer clock
SCK10
Notes 1.
2.
Connection
CSI10
×
Note 1
UART6
{
Note 2
×
Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used.
Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. When
using the clock out of the flash programmer, connect CLK and EXCLK of the programmer.
Remark
: Be sure to connect the pin.
{: The pin does not have to be connected if the signal is generated on the target board.
×: The pin does not have to be connected.
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CHAPTER 24 FLASH MEMORY
24.5 Handling of Pins on Board
To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on
the target system. First provide a function that selects the normal operation mode or flash memory programming
mode on the board.
When the flash memory programming mode is set, all the pins not used for programming the flash memory are in
the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately
after reset, the pins must be handled as described below.
24.5.1 FLMD0 pin
In the normal operation mode, 0 V is input to the FLMD0 pin. In the flash memory programming mode, the VDD
write voltage is supplied to the FLMD0 pin. An FLMD0 pin connection example is shown below.
Figure 24-7. FLMD0 Pin Connection Example
78K0/LE2
Dedicated flash memory
programmer connection pin
FLMD0
10 kΩ (recommended)
24.5.2 Serial interface pins
The pins used by each serial interface are listed below.
Table 24-4. Pins Used by Each Serial Interface
Serial Interface
Pins Used
CSI10
SO10, SI10, SCK10
UART6
TxD6, RxD6
To connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on
the board, care must be exercised so that signals do not collide or that the other device does not malfunction.
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CHAPTER 24 FLASH MEMORY
(1) Signal collision
If the dedicated flash programmer (output) is connected to a pin (input) of a serial interface connected to another
device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other
device, or make the other device go into an output high-impedance state.
Figure 24-8. Signal Collision (Input Pin of Serial Interface)
78K0/LE2
Signal collision
Input pin
Dedicated flash programmer
connection pin
Other device
Output pin
In the flash memory programming mode, the signal output by the device
collides with the signal sent from the dedicated flash programmer.
Therefore, isolate the signal of the other device.
(2) Malfunction of other device
If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface
connected to another device (input), a signal may be output to the other device, causing the device to malfunction.
To avoid this malfunction, isolate the connection with the other device.
Figure 24-9. Malfunction of Other Device
78K0/LE2
Pin
Dedicated flash programmer
connection pin
Other device
Input pin
If the signal output by the 78K0/LE2 in the flash memory programming
mode affects the other device, isolate the signal of the other device.
78K0/LE2
Pin
Dedicated flash programmer
connection pin
Other device
Input pin
If the signal output by the dedicated flash programmer in the flash memory
programming mode affects the other device, isolate the signal of the other
device.
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CHAPTER 24 FLASH MEMORY
24.5.3 RESET pin
If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset
signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the
reset signal generator.
If the reset signal is input from the user system while the flash memory programming mode is set, the flash
memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash
programmer.
Figure 24-10. Signal Collision (RESET Pin)
78K0/LE2
Signal collision
RESET
Dedicated flash programmer
connection signal
Reset signal generator
Output pin
In the flash memory programming mode, the signal output by the reset
signal generator collides with the signal output by the dedicated flash
programmer. Therefore, isolate the signal of the reset signal generator.
24.5.4 Port pins
When the flash memory programming mode is set, all the pins not used for flash memory programming enter the
same status as that immediately after reset. If external devices connected to the ports do not recognize the port
status immediately after reset, the port pin must be connected to VDD or VSS via a resistor.
24.5.5 REGC pin
Connect the REGC pin to GND via a capacitor (0.47 to 1 μF: recommended) in the same manner as during normal
operation.
24.5.6 Other signal pins
Connect X1 and X2 in the same status as in the normal operation mode when using the on-board clock.
To input the operating clock from the programmer, however, connect the clock out of the programmer to EXCLK.
Cautions 1. Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used.
2. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used.
24.5.7 Power supply
To use the supply voltage output of the flash programmer, connect the VDD pin to VDD of the flash programmer, and
the VSS pin to GND of the flash programmer.
However, be sure to connect the VDD and VSS pins to VDD and GND of the flash programmer to use the power
monitor function with the flash programmer.
To use the on-board supply voltage, connect in compliance with the normal operation mode.
Supply the same other power supplies (LVDD, LVSS, AVREF, and AVSS) as those in the normal operation mode.
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24.6 Programming Method
24.6.1 Controlling flash memory
The following figure illustrates the procedure to manipulate the flash memory.
Figure 24-11. Flash Memory Manipulation Procedure
Start
FLMD0 pulse supply
Flash memory programming
mode is set
Selecting communication mode
Manipulate flash memory
No
End?
Yes
End
24.6.2 Flash memory programming mode
To rewrite the contents of the flash memory by using the dedicated flash programmer, set the 78K0/LE2 in the
flash memory programming mode. To set the mode, set the FLMD0 pin to VDD and clear the reset signal.
Change the mode by using a jumper when writing the flash memory on-board.
Figure 24-12. Flash Memory Programming Mode
VDD
5.5 V
0V
VDD
RESET
0V
FLMD0 pulse
VDD
FLMD0
0V
Flash memory programming mode
Table 24-5. Relationship Between FLMD0 Pin and Operation Mode After Reset Release
FLMD0
0
VDD
Operation Mode
Normal operation mode
Flash memory programming mode
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CHAPTER 24 FLASH MEMORY
24.6.3 Selecting communication mode
In the 78K0/LE2, a communication mode is selected by inputting pulses (up to 11 pulses) to the FLMD0 pin after
the dedicated flash memory programming mode is entered.
These FLMD0 pulses are generated by the flash
programmer.
The following table shows the relationship between the number of pulses and communication modes.
Table 24-6. Communication Modes
Communication
Mode
Standard Setting
Port
Speed
Note 1
On Target
Note 3
UART
(UART6)
UART-ch0
115200 bps
3-wire serial I/O
(CSI10)
SIO-ch0
2.4 kHz to 2.5
MHz
Optional
Pins Used
Frequency
Multiply
Rate
1 to 20
Note 2
MHz
1.0
TxD6, RxD6
SO10, SI10,
SCK10
Peripheral Number of
Clock
FLMD0
Pulses
fX
0
fEXCLK
3
fRH
8
Notes 1. Selection items for Standard settings on FlashPro4.
2. The possible setting range differs depending on the voltage. For details, refer to the chapter of electrical
specifications.
3. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART
communication, thoroughly evaluate the slew as well as the baud rate error.
Caution When UART6 is selected, the receive clock is calculated based on the reset command sent from the
dedicated flash programmer after the FLMD0 pulse has been received.
Remark
fX:
X1 clock
fEXCLK: External main system clock
fRH:
538
Internal high-speed oscillation clock
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CHAPTER 24 FLASH MEMORY
24.6.4 Communication commands
The 78K0/LE2 communicates with the dedicated flash programmer by using commands. The signals sent from the
flash programmer to the 78K0/LE2 are called commands, and the signals sent from the 78K0/LE2 to the dedicated
flash programmer are called response.
XXXX XXXXXX
Axxxx
Bxxxxx
Cxxxxxx
XXXXX
XXX YYY
XXXX YYYY
Figure 24-13. Communication Commands
STATVE
PG-FP4 (Flash Pro4)
Command
Response
78K0/LE2
Dedicated flash
programmer
The flash memory control commands of the 78K0/LE2 are listed in the table below. All these commands are
issued from the programmer and the 78K0/LE2 perform processing corresponding to the respective commands.
Table 24-7. Flash Memory Control Commands
Classification
Command Name
Verify
Function
Compares the contents of the entire memory
Batch verify command
with the input data.
Erase
Batch erase command
Erases the contents of the entire memory.
Blank check
Batch blank check command
Checks the erasure status of the entire memory.
Data write
High-speed write command
Writes data by specifying the write address and
number of bytes to be written, and executes a
verify check.
Writes data from the address following that of
Successive write command
the high-speed write command executed
immediately before, and executes a verify
check.
System setting, control
Status read command
Obtains the operation status
Oscillation frequency setting command
Sets the oscillation frequency
Erase time setting command
Sets the erase time for batch erase
Write time setting command
Sets the write time for writing data
Baud rate setting command
Sets the baud rate when UART is used
Silicon signature command
Reads the silicon signature information
Reset command
Escapes from each status
The 78K0/LE2 return a response for the command issued by the dedicated flash programmer. The response
names sent from the 78K0/LE2 are listed below.
Table 24-8. Response Names
Response Name
Function
ACK
Acknowledges command/data.
NAK
Acknowledges illegal command/data.
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CHAPTER 24 FLASH MEMORY
24.7 Security Settings
The operations shown below can be performed using the security setting command. The security setting is valid
when the programming mode is set next.
• Disabling batch erase (chip erase)
Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is
prohibited by this setting. Once execution of the batch erase (chip erase) command is prohibited, all of the
prohibition settings can no longer be cancelled.
Caution After the security setting for the batch erase is set, erasure cannot be performed for the device.
In addition, even if a write command is executed, data different from that which has already
been written to the flash memory cannot be written, because the erase command is disabled.
• Disabling block erase
Execution of the block erase command for a specific block in the flash memory is prohibited by this setting. This
prohibition setting can be cancelled using the batch erase (chip erase) command.
• Disabling write
Execution of the write and block erase commands for entire blocks in the flash memory is prohibited by this
setting. This prohibition setting can be cancelled using the batch erase (chip erase) command.
• Disabling rewriting boot cluster 0
Execution of the batch erase (chip erase) command, block erase command, and write command on boot cluster
0 (0000H to 0FFFH) in the flash memory is prohibited by this setting.
Caution If a security setting that rewrites boot cluster 0 has been applied, boot cluster 0 of that device
will not be rewritten.
The batch erase (chip erase), block erase, write commands, and rewriting boot cluster 0 are enabled by the default
setting when the flash memory is shipped. The above security settings are only possible for on-board/off-board
programming. Each security setting can be used in combination.
Table 24-9 shows the relationship between the erase and write commands when the 78K0/LE2 security function is
enabled.
Table 24-9. Relationship Between Commands When Security Function Is Enabled
Command
Security Setting
Batch Erase (Chip
Block Erase
Erase) Command
Command
Disabling batch erase (chip erase)
Invalid
Disabling block erase
Valid
Invalid
Disabling write
Write Command
Valid
Note
Valid
Invalid
Disabling rewriting boot cluster 0
Invalid
Note Since the erase command is disabled, data different from that which has already been written to the
flash memory cannot be written.
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CHAPTER 24 FLASH MEMORY
Table 24-10 shows the relationship between the security setting and the operation in each programming mode.
Table 24-10. Relationship Between Security Setting and Operation In Each Programming Mode
Programming Mode
Security Setting
On-Board/Off-Board Programming
Security Setting
Disabling batch erase (chip erase) Enabled
Security Operation
Note 1
Valid
Self Programming
Security Setting
Security Operation
Note 2
Disabled
Invalid
Enabled
Valid
Disabling block erase
Disabling write
Disabling rewriting boot cluster 0
Notes 1. Execution of each command is prohibited by the security setting.
2. Execution of self programming command is possible regardless of the security setting.
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CHAPTER 24 FLASH MEMORY
24.8 Flash Memory Programming by Self-Writing
The 78K0/LE2 supports a self-programming function that can be used to rewrite the flash memory via a user
program. Because this function allows a user application to rewrite the flash memory by using the 78K0/Kx2 selfprogramming sample library, it can be used to upgrade the program in the field.
If an interrupt occurs during self-programming, self-programming can be temporarily stopped and interrupt
servicing can be executed. To execute interrupt servicing, restore the normal operation mode after self-programming
has been stopped, and execute the EI instruction.
After the self-programming mode is later restored, self-
programming can be resumed.
Remark
For details of the self-programming function and the 78K0/Kx2 self-programming library, refer to
78K0/Kx2 Flash Memory Self Programming User’s Manual (U17516E).
Cautions 1. The self-programming function cannot be used when the CPU operates with the subsystem
clock.
2. Input a high level to the FLMD0 pin during self-programming.
3. Be sure to execute the DI instruction before starting self-programming.
The self-programming function checks the interrupt request flags (IF0L, IF0H, IF1L, and IF1H).
If an interrupt request is generated, self-programming is stopped.
4. Self-programming is also stopped by an interrupt request that is not masked even in the DI
status. To prevent this, mask the interrupt by using the interrupt mask flag registers (MK0L,
MK0H, MK1L, and MK1H).
5. Self-programming is executed with the internal high-speed oscillation clock.
If the CPU
operates with the X1 clock or external main system clock, the oscillation stabilization wait
time of the internal high-speed oscillation clock elapses during self-programming.
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User’s Manual U17734EJ2V0UD
CHAPTER 24 FLASH MEMORY
The procedure of self-programming is illustrated below.
Figure 24-14. Self-Programming Procedure
Start self-programming
Secure entry RAM area
Set parameters
to entry RAM
Entry program
(user program)
FLMD0 pin = High level
Execute DI instruction
Execute library and access
flash memory according to
parameter contents
Library
Interrupt request
EI execution instruction
Interrupt servicing
No interrupt request
Entry program
(user program)
Check library return value
Self-programming
stopped
FLMD0 pin = Low level
End of self-programming
User’s Manual U17734EJ2V0UD
543
CHAPTER 24 FLASH MEMORY
24.8.1 Boot swap function
If rewriting the boot area has failed during self-programming due to a power failure or some other cause, the data
in the boot area may be lost and the program may not be restarted by resetting.
The boot swap function is used to avoid this problem.
Before erasing boot cluster 0Note, which is a boot program area, by self-programming, write a new boot program to
boot cluster 1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and
boot cluster 0 by using the set information function of the firmware of the 78K0/LE2, so that boot cluster 1 is used as a
boot area. After that, erase or write the original boot program area, boot cluster 0.
As a result, even if a power failure occurs while the boot programming area is being rewritten, the program is
executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next.
If the program has been correctly written to boot cluster 0, restore the original boot area by using the set
information function of the firmware of the 78K0/LE2.
Note A boot cluster is a 4 KB area and boot clusters 0 and 1 are swapped by the boot swap function.
Boot cluster 0 (0000H to 0FFFH): Original boot program area
Boot cluster 1 (1000H to 1FFFH): Area subject to boot swap function
Figure 24-15. Boot Swap Function
XXXXH
User program
Self-programming
to boot cluster 1
User program
Execution of boot
swap by firmware
User program
2000H
Boot
User program
New boot program
(boot cluster 1)
Boot program
(boot cluster 0)
Boot program
(boot cluster 0)
1000H
0000H
New boot program
(boot cluster 1)
Boot
Boot program
(boot cluster 0)
Boot
XXXXH
Self-programming
to boot cluster 0
User program
Execution of boot
swap by firmware
User program
2000H
1000H
0000H
544
New boot program
(boot cluster 1)
New boot program
(boot cluster 1)
Boot
New boot program
(boot cluster 0)
User’s Manual U17734EJ2V0UD
New boot program
(boot cluster 0)
Boot
CHAPTER 24 FLASH MEMORY
Figure 24-16. Example of Executing Boot Swapping
Block number
Boot
cluster 1
Boot
cluster 0
7
6
5
4
3
2
1
0
Program
Program
Program
Program
Boot program
Boot program
Boot program
Boot program
1000H
0000H
Erasing block 4
Erasing block 5
Erasing block 6
Erasing block 7
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Program
Program
Program
Boot program
Boot program
Boot program
Boot program
Program
Program
Boot program
Boot program
Boot program
Boot program
Program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Booted by boot cluster 0
Writing blocks 5 to 7
7 New boot program
6 New boot program
5 New boot program
4 New boot program
3 Boot program
2 Boot program
1 Boot program
0 Boot program
Boot swap
7
6
5
4
3
2
1
0
New boot program
New boot program
New boot program
New boot program
Boot program
Boot program
Boot program
Boot program
0000H
1000H
Erasing block 0
Erasing block 1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
New boot program
New boot program
New boot program
New boot program
Boot program
Boot program
Boot program
New boot program
New boot program
New boot program
New boot program
Boot program
Boot program
Booted by boot cluster 1
Erasing block 2
Erasing block 3
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
New boot program
New boot program
New boot program
New boot program
Boot program
New boot program
New boot program
New boot program
New boot program
Writing blocks 0 to 3
7
6
5
4
3
2
1
0
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
Boot swap canceled
7 New boot program
6 New boot program
5 New boot program
4 New boot program 1 0 0 0 H
3 New boot program
2 New boot program
1 New boot program
0 New boot program 0 0 0 0 H
Booted by boot cluster 0
User’s Manual U17734EJ2V0UD
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CHAPTER 25 ON-CHIP DEBUG FUNCTION (μPD78F0363D ONLY)
The μPD78F0363D uses the VDD, FLMD0, RESET, OCD0A/X1 (or OCD1A/P31), OCD0B/X2 (or OCD1B/P32), and
VSS pins to communicate with the host machine via an on-chip debug emulator (QB-78K0MINI). Whether OCD0A/X1
and OCD1A/P31, or OCD0B/X2 and OCD1B/P32 are used can be selected.
Caution
The μPD78F0363D has an on-chip debug function. Do not use this product for mass production
because its reliability cannot be guaranteed after the on-chip debug function has been used,
given the issue of the number of times the flash memory can be rewritten. NEC Electronics does
not accept complaints concerning this product.
Figure 25-1. Connection Example of QB-78K0MINI and μPD78F0363D
(When OCD0A/X1 and OCD0B/X2 Are Used)
μPD78F0363D
QB-78K0MINI target connector
FLMD0
FLMD0
Note
Target reset
RESET_IN
RESET
RESET_OUT
X1
OCD0A/X1
X2
OCD0B/X2
GND
GND
VDD
VDD
P31
Note
Note Make pull-down resistor 470 Ω or more.
Cautions 1. Input the clock from the OCD0A/X1 pin during on-chip debugging.
2. Control the OCD0A/X1 and OCD0B/X2 pins by externally pulling down the OCD1A/P31 pin.
546
User’s Manual U17734EJ2V0UD
CHAPTER 25 ON-CHIP DEBUG FUNCTION (μPD78F0363D ONLY)
Figure 25-2. Connection Example of QB-78K0MINI and μPD78F0363D
(When OCD1A and OCD1B Are Used)
μPD78F0363D
QB-78K0MINI target connector
FLMD0
FLMD0
Note
Target reset
RESET_IN
RESET
RESET_OUT
X1
OCD1A/P31
Note
X2
OCD1B/P32
GND
GND
VDD
VDD
X1
X2
Note Make pull-down resistor 470 Ω or more.
25.1 On-Chip Debug Security ID
The μPD78F0363D has an on-chip debug operation control flag in the flash memory at 0084H (see CHAPTER 23
OPTION BYTE) and an on-chip debug security ID setting area at 0085H to 008EH.
When the boot swap function is used, also set a value that is the same as that of 1084H and 1085H to 108EH in
advance, because 0084H, 0085H to 008EH and 1084H, and 1085H to 108EH are switched.
For details on the on-chip debug security ID, refer to the QB-78K0MINI User’s Manual (U17029E).
Table 25-1. On-Chip Debug Security ID
Address
0085H to 008EH
On-Chip Debug Security ID
Any ID code of 10 bytes
1085H to 108EH
User’s Manual U17734EJ2V0UD
547
CHAPTER 26 INSTRUCTION SET
This chapter lists each instruction set of the 78K0/LE2 in table form. For details of each operation and operation
code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E).
26.1 Conventions Used in Operation List
26.1.1 Operand identifiers and specification methods
Operands are written in the “Operand” column of each instruction in accordance with the specification method of
the instruction operand identifier (refer to the assembler specifications for details). When there are two or more
methods, select one of them. Uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as
they are. Each symbol has the following meaning.
• #: Immediate data specification
• !:
Absolute address specification
• $: Relative address specification
• [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
write the #, !, $, and [ ] symbols.
For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for specification.
Table 26-1. Operand Identifiers and Specification Methods
Identifier
Specification Method
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
rp
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
sfr
Special function register symbol
sfrp
Special function register symbol (16-bit manipulatable register even addresses only)
saddr
FE20H to FF1FH Immediate data or labels
saddrp
FE20H to FF1FH Immediate data or labels (even address only)
addr16
0000H to FFFFH Immediate data or labels
Note
Note
(Only even addresses for 16-bit data transfer instructions)
addr11
0800H to 0FFFH Immediate data or labels
addr5
0040H to 007FH Immediate data or labels (even address only)
word
16-bit immediate data or label
byte
8-bit immediate data or label
bit
3-bit immediate data or label
RBn
RB0 to RB3
Note Addresses from FFD0H to FFDFH cannot be accessed with these operands.
Remark
548
For special function register symbols, see Table 3-6 Special Function Register List.
User’s Manual U17734EJ2V0UD
CHAPTER 26 INSTRUCTION SET
26.1.2 Description of operation column
A:
A register; 8-bit accumulator
X:
X register
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
AX register pair; 16-bit accumulator
BC:
BC register pair
DE:
DE register pair
HL:
HL register pair
PC:
Program counter
SP:
Stack pointer
PSW:
Program status word
CY:
Carry flag
AC:
Auxiliary carry flag
Z:
Zero flag
RBS:
Register bank select flag
IE:
Interrupt request enable flag
( ):
Memory contents indicated by address or register contents in parentheses
XH, XL: Higher 8 bits and lower 8 bits of 16-bit register
∧:
Logical product (AND)
∨:
Logical sum (OR)
∨:
Exclusive logical sum (exclusive OR)
⎯⎯
:
Inverted data
addr16: 16-bit immediate data or label
jdisp8:
Signed 8-bit data (displacement value)
26.1.3 Description of flag operation column
(Blank): Not affected
0:
Cleared to 0
1:
Set to 1
×:
Set/cleared according to the result
R:
Previously saved value is restored
User’s Manual U17734EJ2V0UD
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CHAPTER 26 INSTRUCTION SET
26.2 Operation List
Instruction
Group
8-bit data
Mnemonic
MOV
transfer
XCH
Notes 1.
Operands
Clocks
Bytes
Note 1
Note 2
Z AC CY
r, #byte
2
4
−
r ← byte
saddr, #byte
3
6
7
(saddr) ← byte
sfr, #byte
3
−
7
sfr ← byte
A, r
Note 3
1
2
−
A←r
r, A
Note 3
1
2
−
r←A
A, saddr
2
4
5
A ← (saddr)
saddr, A
2
4
5
(saddr) ← A
A, sfr
2
−
5
A ← sfr
sfr, A
2
−
5
sfr ← A
A, !addr16
3
8
9
A ← (addr16)
!addr16, A
3
8
9
(addr16) ← A
PSW, #byte
3
−
7
PSW ← byte
A, PSW
2
−
5
A ← PSW
PSW, A
2
−
5
PSW ← A
A, [DE]
1
4
5
A ← (DE)
[DE], A
1
4
5
(DE) ← A
A, [HL]
1
4
5
A ← (HL)
[HL], A
1
4
5
(HL) ← A
A, [HL + byte]
2
8
9
A ← (HL + byte)
[HL + byte], A
2
8
9
(HL + byte) ← A
A, [HL + B]
1
6
7
A ← (HL + B)
[HL + B], A
1
6
7
(HL + B) ← A
A, [HL + C]
1
6
7
A ← (HL + C)
[HL + C], A
1
6
7
(HL + C) ← A
1
2
−
A↔r
A, r
Note 3
Flag
Operation
A, saddr
2
4
6
A ↔ (saddr)
A, sfr
2
−
6
A ↔ (sfr)
A, !addr16
3
8
10
A ↔ (addr16)
A, [DE]
1
4
6
A ↔ (DE)
A, [HL]
1
4
6
A ↔ (HL)
A, [HL + byte]
2
8
10
A ↔ (HL + byte)
A, [HL + B]
2
8
10
A ↔ (HL + B)
A, [HL + C]
2
8
10
A ↔ (HL + C)
×
×
×
×
×
×
When the internal high-speed RAM area is accessed or for an instruction with no data access
2.
When an area except the internal high-speed RAM area is accessed
3.
Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
550
User’s Manual U17734EJ2V0UD
CHAPTER 26 INSTRUCTION SET
Instruction
Group
Mnemonic
Operands
Clocks
Bytes
Note 1
16-bit data
MOVW
transfer
3
6
−
rp ← word
saddrp, #word
4
8
10
(saddrp) ← word
sfrp, #word
4
−
10
sfrp ← word
AX, saddrp
2
6
8
AX ← (saddrp)
saddrp, AX
2
6
8
(saddrp) ← AX
AX, sfrp
2
−
8
AX ← sfrp
sfrp, AX
2
−
8
sfrp ← AX
4
−
AX ← rp
AX, rp
Note 3
1
rp, AX
Note 3
1
4
−
rp ← AX
3
10
12
AX ← (addr16)
3
10
12
(addr16) ← AX
1
4
−
AX ↔ rp
2
4
−
A, CY ← A + byte
×
×
×
3
6
8
(saddr), CY ← (saddr) + byte
×
×
×
2
4
−
A, CY ← A + r
×
×
×
2
4
−
r, CY ← r + A
×
×
×
!addr16, AX
XCHW
AX, rp
ADD
A, #byte
operation
Note 3
saddr, #byte
A, r
Note 4
r, A
ADDC
A, saddr
2
4
5
A, CY ← A + (saddr)
×
×
×
A, !addr16
3
8
9
A, CY ← A + (addr16)
×
×
×
A, [HL]
1
4
5
A, CY ← A + (HL)
×
×
×
A, [HL + byte]
2
8
9
A, CY ← A + (HL + byte)
×
×
×
A, [HL + B]
2
8
9
A, CY ← A + (HL + B)
×
×
×
A, [HL + C]
2
8
9
A, CY ← A + (HL + C)
×
×
×
A, #byte
2
4
−
A, CY ← A + byte + CY
×
×
×
3
6
8
(saddr), CY ← (saddr) + byte + CY
×
×
×
2
4
−
A, CY ← A + r + CY
×
×
×
2
4
−
r, CY ← r + A + CY
×
×
×
saddr, #byte
A, r
Note 4
r, A
Notes 1.
Z AC CY
Note 2
rp, #word
AX, !addr16
8-bit
Flag
Operation
A, saddr
2
4
5
A, CY ← A + (saddr) + CY
×
×
×
A, !addr16
3
8
9
A, CY ← A + (addr16) + C
×
×
×
A, [HL]
1
4
5
A, CY ← A + (HL) + CY
×
×
×
A, [HL + byte]
2
8
9
A, CY ← A + (HL + byte) + CY
×
×
×
A, [HL + B]
2
8
9
A, CY ← A + (HL + B) + CY
×
×
×
A, [HL + C]
2
8
9
A, CY ← A + (HL + C) + CY
×
×
×
When the internal high-speed RAM area is accessed or for an instruction with no data access
2.
When an area except the internal high-speed RAM area is accessed
3.
Only when rp = BC, DE or HL
4.
Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
User’s Manual U17734EJ2V0UD
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CHAPTER 26 INSTRUCTION SET
Instruction
Group
Mnemonic
Operands
Clocks
Bytes
Note 1
8-bit
SUB
operation
2
4
−
A, CY ← A − byte
×
×
×
saddr, #byte
3
6
8
(saddr), CY ← (saddr) − byte
×
×
×
2
4
−
A, CY ← A − r
×
×
×
r, A
2
4
−
r, CY ← r − A
×
×
×
A, saddr
2
4
5
A, CY ← A − (saddr)
×
×
×
Note 3
A, !addr16
3
8
9
A, CY ← A − (addr16)
×
×
×
A, [HL]
1
4
5
A, CY ← A − (HL)
×
×
×
A, [HL + byte]
2
8
9
A, CY ← A − (HL + byte)
×
×
×
A, [HL + B]
2
8
9
A, CY ← A − (HL + B)
×
×
×
A, [HL + C]
2
8
9
A, CY ← A − (HL + C)
×
×
×
A, #byte
2
4
−
A, CY ← A − byte − CY
×
×
×
saddr, #byte
3
6
8
(saddr), CY ← (saddr) − byte − CY
×
×
×
2
4
−
A, CY ← A − r − CY
×
×
×
r, A
2
4
−
r, CY ← r − A − CY
×
×
×
A, saddr
2
4
5
A, CY ← A − (saddr) − CY
×
×
×
A, !addr16
3
8
9
A, CY ← A − (addr16) − CY
×
×
×
A, [HL]
1
4
5
A, CY ← A − (HL) − CY
×
×
×
A, [HL + byte]
2
8
9
A, CY ← A − (HL + byte) − CY
×
×
×
A, r
AND
Note 3
A, [HL + B]
2
8
9
A, CY ← A − (HL + B) − CY
×
×
×
A, [HL + C]
2
8
9
A, CY ← A − (HL + C) − CY
×
×
×
A, #byte
2
4
−
A ← A ∧ byte
×
3
6
8
(saddr) ← (saddr) ∧ byte
×
2
4
−
A←A∧r
×
2
4
−
r←r∧A
×
saddr, #byte
A, r
r, A
Notes 1.
Z AC CY
Note 2
A, #byte
A, r
SUBC
Flag
Operation
Note 3
A, saddr
2
4
5
A ← A ∧ (saddr)
×
A, !addr16
3
8
9
A ← A ∧ (addr16)
×
A, [HL]
1
4
5
A ← A ∧ (HL)
×
A, [HL + byte]
2
8
9
A ← A ∧ (HL + byte)
×
A, [HL + B]
2
8
9
A ← A ∧ (HL + B)
×
A, [HL + C]
2
8
9
A ← A ∧ (HL + C)
×
When the internal high-speed RAM area is accessed or for an instruction with no data access
2.
When an area except the internal high-speed RAM area is accessed
3.
Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
552
User’s Manual U17734EJ2V0UD
CHAPTER 26 INSTRUCTION SET
Instruction
Group
Mnemonic
Operands
Clocks
Bytes
Note 1
8-bit
OR
operation
2
4
−
A ← A ∨ byte
×
saddr, #byte
3
6
8
(saddr) ← (saddr) ∨ byte
×
2
4
−
A←A∨r
×
r, A
2
4
−
r←r∨A
×
A, saddr
2
4
5
A ← A ∨ (saddr)
×
Note 3
A, !addr16
3
8
9
A ← A ∨ (addr16)
×
A, [HL]
1
4
5
A ← A ∨ (HL)
×
A, [HL + byte]
2
8
9
A ← A ∨ (HL + byte)
×
A, [HL + B]
2
8
9
A ← A ∨ (HL + B)
×
A, [HL + C]
2
8
9
A ← A ∨ (HL + C)
×
A, #byte
2
4
−
A ← A ∨ byte
×
saddr, #byte
3
6
8
(saddr) ← (saddr) ∨ byte
×
2
4
−
A←A∨r
×
r, A
2
4
−
r←r∨A
×
A, saddr
2
4
5
A ← A ∨ (saddr)
×
A, !addr16
3
8
9
A ← A ∨ (addr16)
×
A, [HL]
1
4
5
A ← A ∨ (HL)
×
A, [HL + byte]
2
8
9
A ← A ∨ (HL + byte)
×
A, r
CMP
Note 3
A, [HL + B]
2
8
9
A ← A ∨ (HL + B)
×
A, [HL + C]
2
8
9
A ← A ∨ (HL + C)
×
A, #byte
2
4
−
A − byte
×
×
×
3
6
8
(saddr) − byte
×
×
×
2
4
−
A−r
×
×
×
2
4
−
r−A
×
×
×
saddr, #byte
A, r
r, A
Notes 1.
Z AC CY
Note 2
A, #byte
A, r
XOR
Flag
Operation
Note 3
A, saddr
2
4
5
A − (saddr)
×
×
×
A, !addr16
3
8
9
A − (addr16)
×
×
×
A, [HL]
1
4
5
A − (HL)
×
×
×
A, [HL + byte]
2
8
9
A − (HL + byte)
×
×
×
A, [HL + B]
2
8
9
A − (HL + B)
×
×
×
A, [HL + C]
2
8
9
A − (HL + C)
×
×
×
When the internal high-speed RAM area is accessed or for an instruction with no data access
2.
When an area except the internal high-speed RAM area is accessed
3.
Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
User’s Manual U17734EJ2V0UD
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CHAPTER 26 INSTRUCTION SET
Instruction
Group
Mnemonic
Operands
Clocks
Bytes
Note 1
Note 2
Flag
Operation
Z AC CY
16-bit
ADDW
AX, #word
3
6
−
AX, CY ← AX + word
×
×
×
operation
SUBW
AX, #word
3
6
−
AX, CY ← AX − word
×
×
×
CMPW
AX, #word
3
6
−
AX − word
×
×
×
Multiply/
MULU
X
2
16
−
AX ← A × X
divide
DIVUW
C
2
25
−
AX (Quotient), C (Remainder) ← AX ÷ C
Increment/
INC
decrement
DEC
INCW
Rotate
r
1
2
−
r←r+1
×
×
saddr
2
4
6
(saddr) ← (saddr) + 1
×
×
r
1
2
−
r←r−1
×
×
saddr
2
4
6
(saddr) ← (saddr) − 1
×
×
rp
1
4
−
rp ← rp + 1
DECW
rp
1
4
−
rp ← rp − 1
ROR
A, 1
1
2
−
(CY, A7 ← A0, Am − 1 ← Am) × 1 time
×
ROL
A, 1
1
2
−
(CY, A0 ← A7, Am + 1 ← Am) × 1 time
×
RORC
A, 1
1
2
−
(CY ← A0, A7 ← CY, Am − 1 ← Am) × 1 time
×
ROLC
A, 1
1
2
−
(CY ← A7, A0 ← CY, Am + 1 ← Am) × 1 time
×
ROR4
[HL]
2
10
12
A3 − 0 ← (HL)3 − 0, (HL)7 − 4 ← A3 − 0,
(HL)3 − 0 ← (HL)7 − 4
ROL4
[HL]
2
10
12
A3 − 0 ← (HL)7 − 4, (HL)3 − 0 ← A3 − 0,
(HL)7 − 4 ← (HL)3 − 0
BCD
ADJBA
adjustment
ADJBS
Bit
MOV1
manipulate
Notes 1.
2.
2
4
−
Decimal Adjust Accumulator after Addition
×
×
×
×
×
2
4
−
Decimal Adjust Accumulator after Subtract
CY, saddr.bit
3
6
7
CY ← (saddr.bit)
×
CY, sfr.bit
3
−
7
CY ← sfr.bit
×
CY, A.bit
2
4
−
CY ← A.bit
×
CY, PSW.bit
3
−
7
CY ← PSW.bit
×
CY, [HL].bit
2
6
7
CY ← (HL).bit
×
saddr.bit, CY
3
6
8
(saddr.bit) ← CY
sfr.bit, CY
3
−
8
sfr.bit ← CY
A.bit, CY
2
4
−
A.bit ← CY
PSW.bit, CY
3
−
8
PSW.bit ← CY
[HL].bit, CY
2
6
8
(HL).bit ← CY
×
×
×
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
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CHAPTER 26 INSTRUCTION SET
Instruction
Group
Mnemonic
Operands
Clocks
Bytes
Note 1
Bit
AND1
manipulate
OR1
XOR1
SET1
CLR1
Notes 1.
2.
Flag
Operation
Z AC CY
Note 2
CY, saddr.bit
3
6
7
CY ← CY ∧ (saddr.bit)
×
CY, sfr.bit
3
−
7
CY ← CY ∧ sfr.bit
×
CY, A.bit
2
4
−
CY ← CY ∧ A.bit
×
CY, PSW.bit
3
−
7
CY ← CY ∧ PSW.bit
×
CY, [HL].bit
2
6
7
CY ← CY ∧ (HL).bit
×
CY, saddr.bit
3
6
7
CY ← CY ∨ (saddr.bit)
×
CY, sfr.bit
3
−
7
CY ← CY ∨ sfr.bit
×
CY, A.bit
2
4
−
CY ← CY ∨ A.bit
×
CY, PSW.bit
3
−
7
CY ← CY ∨ PSW.bit
×
CY, [HL].bit
2
6
7
CY ← CY ∨ (HL).bit
×
CY, saddr.bit
3
6
7
CY ← CY ∨ (saddr.bit)
×
CY, sfr.bit
3
−
7
CY ← CY ∨ sfr.bit
×
CY, A.bit
2
4
−
CY ← CY ∨ A.bit
×
CY, PSW. bit
3
−
7
CY ← CY ∨ PSW.bit
×
CY, [HL].bit
2
6
7
CY ← CY ∨ (HL).bit
×
saddr.bit
2
4
6
(saddr.bit) ← 1
sfr.bit
3
−
8
sfr.bit ← 1
A.bit
2
4
−
A.bit ← 1
PSW.bit
2
−
6
PSW.bit ← 1
[HL].bit
2
6
8
(HL).bit ← 1
saddr.bit
2
4
6
(saddr.bit) ← 0
sfr.bit
3
−
8
sfr.bit ← 0
A.bit
2
4
−
A.bit ← 0
PSW.bit
2
−
6
PSW.bit ← 0
×
×
×
×
×
×
[HL].bit
2
6
8
(HL).bit ← 0
SET1
CY
1
2
−
CY ← 1
1
CLR1
CY
1
2
−
CY ← 0
0
NOT1
CY
1
2
−
CY ← CY
×
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
User’s Manual U17734EJ2V0UD
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CHAPTER 26 INSTRUCTION SET
Instruction
Group
Call/return
Mnemonic
CALL
Operands
!addr16
Clocks
Bytes
3
Note 1
Note 2
7
−
Operation
Flag
Z AC CY
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLF
!addr11
2
5
−
(SP − 1) ← (PC + 2)H, (SP − 2) ← (PC + 2)L,
PC15 − 11 ← 00001, PC10 − 0 ← addr11,
SP ← SP − 2
CALLT
[addr5]
1
6
−
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP − 2
BRK
1
6
−
(SP − 1) ← PSW, (SP − 2) ← (PC + 1)H,
(SP − 3) ← (PC + 1)L, PCH ← (003FH),
PCL ← (003EH), SP ← SP − 3, IE ← 0
RET
1
6
−
PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RETI
1
6
−
PCH ← (SP + 1), PCL ← (SP),
R R R
PSW ← (SP + 2), SP ← SP + 3
RETB
1
6
−
PCH ← (SP + 1), PCL ← (SP),
R R R
PSW ← (SP + 2), SP ← SP + 3
Stack
PUSH
manipulate
PSW
rp
1
1
2
−
4
−
(SP − 1) ← PSW, SP ← SP − 1
(SP − 1) ← rpH, (SP − 2) ← rpL,
SP ← SP − 2
POP
PSW
1
2
−
PSW ← (SP), SP ← SP + 1
rp
1
4
−
rpH ← (SP + 1), rpL ← (SP),
SP, #word
4
−
10
SP ← word
SP, AX
2
−
8
SP ← AX
R R R
SP ← SP + 2
MOVW
AX, SP
2
−
8
AX ← SP
Unconditional BR
!addr16
3
6
−
PC ← addr16
branch
$addr16
2
6
−
PC ← PC + 2 + jdisp8
−
PCH ← A, PCL ← X
AX
2
8
Conditional BC
$addr16
2
6
−
PC ← PC + 2 + jdisp8 if CY = 1
branch
BNC
$addr16
2
6
−
PC ← PC + 2 + jdisp8 if CY = 0
BZ
$addr16
2
6
−
PC ← PC + 2 + jdisp8 if Z = 1
BNZ
$addr16
2
6
−
PC ← PC + 2 + jdisp8 if Z = 0
Notes 1.
2.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
556
User’s Manual U17734EJ2V0UD
CHAPTER 26 INSTRUCTION SET
Instruction
Group
Mnemonic
Operands
Clocks
Bytes
Note 1
Z AC CY
Note 2
Conditional BT
saddr.bit, $addr16
3
8
9
PC ← PC + 3 + jdisp8 if (saddr.bit) = 1
branch
sfr.bit, $addr16
4
−
11
PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16
3
8
−
PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16
3
−
9
PC ← PC + 3 + jdisp8 if PSW.bit = 1
[HL].bit, $addr16
3
10
11
PC ← PC + 3 + jdisp8 if (HL).bit = 1
saddr.bit, $addr16
4
10
11
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16
4
−
11
PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16
3
8
−
PC ← PC + 3 + jdisp8 if A.bit = 0
BF
BTCLR
Flag
Operation
PSW.bit, $addr16
4
−
11
PC ← PC + 4 + jdisp8 if PSW. bit = 0
[HL].bit, $addr16
3
10
11
PC ← PC + 3 + jdisp8 if (HL).bit = 0
saddr.bit, $addr16
4
10
12
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
then reset (saddr.bit)
sfr.bit, $addr16
4
−
12
PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr16
3
8
−
PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr16
4
−
12
PC ← PC + 4 + jdisp8 if PSW.bit = 1
×
×
×
then reset PSW.bit
[HL].bit, $addr16
3
10
12
PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
DBNZ
B, $addr16
2
6
−
B ← B − 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16
2
6
−
C ← C −1, then
saddr, $addr16
3
8
10
(saddr) ← (saddr) − 1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
CPU
SEL
2
4
−
RBS1, 0 ← n
control
NOP
1
2
−
No Operation
EI
2
−
6
IE ← 1 (Enable Interrupt)
DI
2
−
6
IE ← 0 (Disable Interrupt)
HALT
2
6
−
Set HALT Mode
STOP
2
6
−
Set STOP Mode
Notes 1.
2.
RBn
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
User’s Manual U17734EJ2V0UD
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CHAPTER 26 INSTRUCTION SET
26.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand
#byte
A
rNote
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + byte] $addr16
1
None
[HL + B]
First Operand
A
r
[HL + C]
ADD
MOV
MOV
MOV
MOV
ADDC
XCH
XCH
XCH
XCH
SUB
ADD
ADD
ADD
SUBC
ADDC
ADDC ADDC
ADDC ADDC
AND
SUB
SUB
SUB
OR
SUBC
SUBC SUBC
SUBC SUBC
XOR
AND
AND
AND
AND
AND
CMP
OR
OR
OR
OR
OR
XOR
XOR
XOR
XOR
XOR
CMP
CMP
CMP
CMP
CMP
MOV
MOV
SUB
MOV
MOV
MOV
ROR
XCH
XCH
XCH
ROL
ADD
ADD
RORC
ROLC
SUB
MOV
INC
ADD
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
B, C
DBNZ
sfr
MOV
MOV
saddr
MOV
MOV
DBNZ
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV
PUSH
MOV
POP
[DE]
MOV
[HL]
MOV
ROR4
ROL4
[HL + byte]
MOV
[HL + B]
[HL + C]
X
MULU
C
DIVUW
Note Except “r = A”
558
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CHAPTER 26 INSTRUCTION SET
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
#word
AX
rp
Note
sfrp
saddrp
!addr16
SP
None
First Operand
AX
ADDW
MOVW
SUBW
XCHW
MOVW
MOVW
MOVW
MOVW
CMPW
rp
MOVW
MOVW
Note
INCW
DECW
PUSH
POP
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
SP
MOVW
MOVW
MOVW
Note Only when rp = BC, DE, HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
First Operand
A.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
sfr.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
saddr.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
PSW.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
[HL].bit
MOV1
BT
SET1
BF
CLR1
BTCLR
CY
MOV1
MOV1
MOV1
MOV1
MOV1
SET1
AND1
AND1
AND1
AND1
AND1
CLR1
OR1
OR1
OR1
OR1
OR1
NOT1
XOR1
XOR1
XOR1
XOR1
XOR1
User’s Manual U17734EJ2V0UD
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CHAPTER 26 INSTRUCTION SET
(4) Call instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand
AX
!addr16
!addr11
[addr5]
$addr16
First Operand
Basic instruction
BR
CALL
CALLF
CALLT
BR
BR
BC
BNC
BZ
BNZ
Compound
BT
instruction
BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
560
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CHAPTER 27 ELECTRICAL SPECIFICATIONS
Caution The μPD78F0363D has an on-chip debug function. Do not use this product for mass production
because its reliability cannot be guaranteed after the on-chip debug function has been used,
given the issue of the number of times the flash memory can be rewritten. NEC Electronics does
not accept complaints concerning this product.
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
VDD
VDD = LVDD
Ratings
Unit
−0.3 to +6.5
V
LVDD
VDD = LVDD
−0.3 to +6.5
V
VSS
VSS = LVSS
−0.3 to +0.3
V
LVSS
VSS = LVSS
−0.3 to +0.3
AVREF
AVSS
Input voltage
VI1
−0.3 to VDD + 0.3
V
Note
−0.3 to +0.3
P00, P01, P10 to P17, P20 to P24,
−0.3 to VDD + 0.3
V
V
Note
V
P30 to P33, P120 to P124,
X1, X2, XT1, XT2, FLMD0, RESET
VI2
Output voltage
VO1
SCL0, SDA0 (N-ch open drain)
P00, P01, P10 to P17, P20 to P24,
−0.3 to +6.5
−0.3 to VDD + 0.3
V
Note
V
P30 to P33, P120 to P124,
X1, X2, XT1, XT2, RESET
Analog input voltage
VO2
S0 to S19, COM0 to COM3
VAN
ANI0 to ANI4
−0.3 to VLC0 + 0.3
Note
−0.3 to AVREF + 0.3
Note
V
and −0.3 to VDD + 0.3
Note
−10
mA
Total of all pins P00, P01, P120
−25
mA
−80 mA
P10 to P17, P30 to P33
−55
mA
Per pin
P20 to P24
−0.5
mA
Total of all pins
−2
mA
Per pin
−1
mA
Total of all pins
−4
mA
Output current, high
IOH
Per pin
P00, P01, P10 to P17,
P30 to P33, P120
P121 to P124
Note Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
User’s Manual U17734EJ2V0UD
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CHAPTER 27 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C) (2/2)
Parameter
Output current, low
Symbol
IOL
Conditions
Per pin
P00, P01, P10 to P17,
Ratings
Unit
30
mA
P30 to P33, P120,
SCL0, SDA0
Total of all pins P00, P01, P120
200 mA
P10 to P17, P30 to P33,
60
mA
140
mA
1
mA
5
mA
4
mA
10
mA
−40 to +85
°C
−40 to +125
°C
SCL0, SDA0
Per pin
Total of all pins
Per pin
Total of all pins
Operating ambient
TA
temperature
Storage temperature
P20 to P24
P121 to P124
In normal operation mode
In flash memory programming mode
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark
562
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
User’s Manual U17734EJ2V0UD
CHAPTER 27 ELECTRICAL SPECIFICATIONS
X1 Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, VSS = LVSS = AVSS = 0 V)
Resonator
Recommended Circuit
VSS X1
X2
Conditions
4.0 V ≤ VDD ≤ 5.5 V
X1 clock
Ceramic
resonator
Parameter
MIN.
1.0
TYP.
MAX.
Unit
20.0
MHz
Note 2
oscillation
Note 1
frequency (fX)
C1
2.7 V ≤ VDD < 4.0 V
C2
1.8 V ≤ VDD < 2.7 V
resonator
4.0 V ≤ VDD ≤ 5.5 V
X1 clock
Crystal
VSS X1
X2
1.0
10.0
Note 2
1.0
5.0
1.0
20.0
MHz
Note 2
oscillation
Note 1
frequency (fX)
C1
2.7 V ≤ VDD < 4.0 V
1.0
10.0
Note 2
C2
1.8 V ≤ VDD < 2.7 V
1.0
5.0
Note1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. It is 2.0 MHz (MIN.) when programming on the board via UART6.
Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. Since the CPU is started by the internal high-speed oscillation clock after a reset release, check
the X1 clock oscillation stabilization time using the oscillation stabilization time counter status
register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register
and oscillation stabilization time select register (OSTS) after sufficiently evaluating the
oscillation stabilization time with the resonator to be used.
Remark
For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
User’s Manual U17734EJ2V0UD
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CHAPTER 27 ELECTRICAL SPECIFICATIONS
Internal Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, VSS = LVSS = AVSS = 0 V)
Resonator
Parameter
8 MHz internal oscillator
Conditions
Internal high-speed oscillation
RSTS = 1
Note
clock frequency (fRH)
1.8 V ≤ VDD < 2.7 V
TYP.
MAX.
Unit
7.6
8.0
8.4
MHz
7.6
8.0
10.4
MHz
RSTS = 0
2.48
5.6
9.86
MHz
Internal low-speed oscillation
2.7 V ≤ VDD ≤ 5.5 V
216
240
264
kHz
clock frequency (fRL)
1.8 V ≤ VDD < 2.7 V
192
240
264
kHz
240 kHz internal oscillator
2.7 V ≤ VDD ≤ 5.5 V
MIN.
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Remark
RSTS: Bit 7 of the internal oscillation mode register (RCM))
XT1 Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, VSS = LVSS = AVSS = 0 V)
Resonator
Crystal
resonator
Recommended Circuit
VSS XT2
XT1
Parameter
Conditions
XT1 clock oscillation
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
Note
frequency (fXT)
Rd
C4
C3
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and
is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore
required with the wiring method when the XT1 clock is used.
Remark
For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
564
User’s Manual U17734EJ2V0UD
CHAPTER 27 ELECTRICAL SPECIFICATIONS
DC Characteristics (1/5)
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, AVREF ≤ VDD, VSS = LVSS = AVSS = 0 V)
Parameter
Symbol
Note1
Output current, high
IOH1
Conditions
Per pin for P00, P01,
P10 to P17, P30 to P33,
P120
Total
Note3
of P00, P01, P120
Note3
Total
of P10 to P17,
P30 to P33
Total
IOH2
Output current, low
Note2
Note3
of all pins
Per pin for P20 to P24
IOH3
Per pin for P121 to P124
IOL1
Per pin for P00, P01,
P10 to P17, P30 to P33,
P120
Per pin for SCL0, SDA0
Total
Note3
of P00, P01, P120
Note3
Total
of P10 to P17,
P30 to P33, SCL0, SDA0
Total
Note3
of all pins
IOL2
Per pin for P20 to P24
IOL3
Per pin for P121 to P124
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
−3.0
mA
2.7 V ≤ VDD < 4.0 V
−2.5
mA
1.8 V ≤ VDD < 2.7 V
−1.0
mA
4.0 V ≤ VDD ≤ 5.5 V
−20.0
mA
2.7 V ≤ VDD < 4.0 V
−10.0
mA
1.8 V ≤ VDD < 2.7 V
−5.0
mA
4.0 V ≤ VDD ≤ 5.5 V
−30.0
mA
2.7 V ≤ VDD < 4.0 V
−19.0
mA
1.8 V ≤ VDD < 2.7 V
−10.0
mA
4.0 V ≤ VDD ≤ 5.5 V
−50.0
mA
2.7 V ≤ VDD < 4.0 V
−29.0
mA
1.8 V ≤ VDD < 2.7 V
−15.0
mA
AVREF = VDD
−0.1
mA
−0.1
mA
4.0 V ≤ VDD ≤ 5.5 V
8.5
mA
2.7 V ≤ VDD < 4.0 V
5.0
mA
1.8 V ≤ VDD < 2.7 V
2.0
mA
4.0 V ≤ VDD ≤ 5.5 V
15.0
mA
2.7 V ≤ VDD < 4.0 V
3.0
mA
1.8 V ≤ VDD < 2.7 V
0.6
mA
4.0 V ≤ VDD ≤ 5.5 V
20.0
mA
2.7 V ≤ VDD < 4.0 V
15.0
mA
1.8 V ≤ VDD < 2.7 V
9.0
mA
4.0 V ≤ VDD ≤ 5.5 V
45.0
mA
2.7 V ≤ VDD < 4.0 V
35.0
mA
1.8 V ≤ VDD < 2.7 V
20.0
mA
4.0 V ≤ VDD ≤ 5.5 V
65.0
mA
2.7 V ≤ VDD < 4.0 V
50.0
mA
1.8 V ≤ VDD < 2.7 V
29.0
mA
AVREF = VDD
0.4
mA
0.4
mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from VDD to an output
pin.
2. Value of current at which the device operation is guaranteed even if the current flows from an output pin to
GND.
3. Specification under conditions where the duty factor is 70% (time for which current is output is 0.7 × t and
time for which current is not output is 0.3 × t, where t is a specific time). The total output current of the pins
at a duty factor of other than 70% can be calculated by the following expression.
• Where the duty factor of IOH is n%: Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where the duty factor is 50%, IOH = 20.0 mA
Total output current of pins = (20.0 × 0.7)/(50 × 0.01) = 28.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
User’s Manual U17734EJ2V0UD
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CHAPTER 27 ELECTRICAL SPECIFICATIONS
DC Characteristics (2/5)
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, AVREF ≤ VDD, VSS = LVSS = AVSS = 0 V)
Parameter
Input voltage, high
Input voltage, low
Output voltage, high
Output voltage, low
MAX.
Unit
VIH1
Symbol
P12, P13, P15, P121 to P124
0.7VDD
VDD
V
VIH2
P00, P01, P10, P11, P14, P16, P17,
P30 to P33, P120, RESET
0.8VDD
VDD
V
VIH3
P20 to P24
0.7AVREF
AVREF
V
566
TYP.
VIH4
SCL0, SDA0
0.7VDD
6.0
V
P12, P13, P15, P121 to P124, SCL0, SDA0
0
0.3VDD
V
VIL2
P00, P01, P10, P11, P14, P16, P17,
P30 to P33, P120, RESET
0
0.2VDD
V
VIL3
P20 to P24
AVREF = VDD
0
0.3AVREF
V
VOH1
P00, P01,
P10 to P17,
P30 to P33, P120
4.0 V ≤ VDD ≤ 5.5 V,
IOH1 = −3.0 mA
VDD − 0.7
V
2.7 V ≤ VDD < 4.0 V,
IOH1 = −2.5 mA
VDD − 0.5
V
1.8 V ≤ VDD < 2.7 V,
IOH1 = −1.0 mA
VDD − 0.5
V
V
VOH2
P20 to P24
AVREF = VDD,
IOH2 = −0.1 mA
VDD − 0.5
P121 to P124
IOH2 = −0.1 mA
VDD − 0.5
VOL1
P00, P01,
P10 to P17,
P30 to P33, P120
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 8.5 mA
0.7
V
2.7 V ≤ VDD < 4.0 V,
IOL1 = 5.0 mA
0.7
V
1.8 V ≤ VDD < 2.7 V,
IOL1 = 2.0 mA
0.5
V
1.8 V ≤ VDD < 2.7 V,
IOL1 = 0.5 mA
0.4
V
P20 to P24
AVREF = VDD,
IOL2 = 0.4 mA
0.4
V
P121 to P124
IOL2 = 0.4 mA
0.4
V
SCL0, SDA0
4.0 V ≤ VDD ≤ 5.5 V,
IOL3 = 15 mA
2.0
V
4.0 V ≤ VDD ≤ 5.5 V,
IOL3 = 3.0 mA
0.4
V
2.7 V ≤ VDD < 4.0 V,
IOL3 = 3.0 mA
0.6
V
2.7 V ≤ VDD < 4.0 V,
IOL3 = 2.0 mA
0.4
V
1.8 V ≤ VDD < 2.7 V,
IOL3 = 0.6 mA
0.5
V
VOL3
Remark
AVREF = VDD
MIN.
VIL1
VOL2
Conditions
V
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
User’s Manual U17734EJ2V0UD
CHAPTER 27 ELECTRICAL SPECIFICATIONS
DC Characteristics (3/5)
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, AVREF ≤ VDD, VSS = LVSS = AVSS = 0 V)
Parameter
Input leakage current, high
Symbol
ILIH1
Conditions
P00, P01,
MIN.
TYP.
MAX.
Unit
VI = VDD
1
μA
P10 to P17,
P30 to P33, P120,
SCL0, SDA0,
FLMD0, RESET
ILIH2
P20 to P24
VI = AVREF = VDD
1
μA
ILIH3
P121 to 124
VI = VDD
I/O port mode
1
μA
OSC mode
20
μA
VI = VSS
−1
μA
VI = VSS,
−1
μA
I/O port mode
−1
μA
OSC mode
−20
μA
100
kΩ
(X1, X2, XT1, XT2)
Input leakage current, low
ILIL1
P00, P01,
P10 to P17,
P30 to P33, P120,
SCL0, SDA0,
FLMD0, RESET
ILIL2
P20 to P24
AVREF = VDD
ILIL3
P121 to 124
VI = VSS
(X1, X2, XT1, XT2)
Pull-up resistor
RU
VI = VSS
10
FLMD0 supply voltage
VIL
In normal operation mode
0
0.2VDD
V
VIH
In self-programming mode
0.8VDD
VDD
V
Remark
20
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
User’s Manual U17734EJ2V0UD
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CHAPTER 27 ELECTRICAL SPECIFICATIONS
DC Characteristics (4/5)
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, AVREF ≤ VDD, VSS = LVSS = AVSS = 0 V)
Parameter
Supply current
Symbol
IDD1
Conditions
Operating mode
Note 1
MIN.
Note 2
fXH = 20 MHz
,
VDD = 5.0 V
Notes 2, 3
fXH = 10 MHz
,
VDD = 5.0 V
Notes 2, 3
fXH = 10 MHz
,
VDD = 3.0 V
Notes 2, 3
fXH = 5 MHz
,
VDD = 3.0 V
Notes 2, 3
fXH = 5 MHz
,
VDD = 2.0 V
TYP.
MAX.
Unit
Square wave input
3.2
5.5
mA
Resonator connection
4.5
6.9
Square wave input
1.6
2.8
Resonator connection
2.3
3.9
Square wave input
1.5
2.7
fSUB = 32.768 kHz
,
VDD = 5.0 V
IDD2
HALT mode
Note 2
fXH = 20 MHz
,
VDD = 5.0 V
Notes 2, 3
fXH = 10 MHz
,
VDD = 5.0 V
Notes 2, 3
fXH = 5 MHz
,
VDD = 3.0 V
2.2
3.2
Square wave input
0.9
1.6
Resonator connection
1.3
2.0
Square wave input
0.7
1.4
Resonator connection
1.0
1.6
1.4
2.5
mA
Square wave input
6
25
μA
Resonator connection
15
30
Square wave input
0.8
2.6
Resonator connection
2.0
4.4
Square wave input
0.4
1.3
Resonator connection
1.0
2.4
Square wave input
0.2
0.65
Resonator connection
0.5
1.1
0.4
1.2
mA
Square wave input
3.0
22
μA
Resonator connection
fRH = 8 MHz, VDD = 5.0 V
fSUB = 32.768 kHz
VDD = 5.0 V
Note 5
IDD3
Notes 1.
STOP mode
Note 4
,
mA
Resonator connection
fRH = 8 MHz, VDD = 5.0 V
Note 4
mA
mA
mA
mA
mA
mA
12
25
VDD = 5.0 V
1
20
μA
VDD = 5.0 V, TA = −40 to +70°C
1
10
μA
Total current flowing into the internal power supply (VDD, AVREF), including the peripheral operation current
and the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. However, the
current flowing into the pull-up resistors and the output current of the port are not included.
Not including the operating current of the 8 MHz internal oscillator, and the current flowing into the A/D
converter, watchdog timer, LVI circuit and LCD controller/driver.
2.
3.
When AMPH (bit 0 of clock operation mode select register (OSCCTL)) = 0.
4.
Not including the operating current of the X1 oscillation, 8 MHz internal oscillator and 240 kHz internal
oscillator, and the current flowing into the A/D converter, watchdog timer, LVI circuit and LCD
controller/driver.
5.
Not including the operating current of the 240 kHz internal oscillator and XT1 oscillation, and the current
flowing into the A/D converter, watchdog timer, LVI circuit and LCD controller/driver.
Remarks 1. fXH:
High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fRH: Internal high-speed oscillation clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency or external subsystem clock
frequency)
568
User’s Manual U17734EJ2V0UD
CHAPTER 27 ELECTRICAL SPECIFICATIONS
DC Characteristics (5/5)
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, AVREF ≤ VDD, VSS = LVSS = AVSS = 0 V)
Parameter
A/D converter
Symbol
IADC
Conditions
MIN.
TYP.
MAX.
Unit
0.86
1.9
mA
5
10
μA
9
18
μA
LVDD = 5.0 V
150
330
μA
LVDD = 3.0 V
75
160
μA
LVDD = 5.0 V
2
36
μA
LVDD = 3.0 V
1.5
16
μA
LVDD = 5.0 V
5
45
μA
LVDD = 3.0 V
4
22
μA
LVDD = 5.0 V
0.1
5
μA
LVDD = 3.0 V
0.05
3
μA
2.3 V ≤ AVREF ≤ VDD
Note 1
During conversion at maximum speed
Note 2
During 240 kHz internal low-speed oscillation clock operation
operating current
Watchdog timer
IWDT
operating current
LVI operating
Note 3
ILVI
current
LCD operating
current
Note 4
When LCD (including booster circuit) is
stopped and IIC is operating
Note 4
When only LCD booster circuit is
operating and IIC is in standby status
ILCD1
ILCD2
Note 4
ILCD3
Note 4
ILCD4
Notes 1.
2.
3.
4.
When LCD display is operating and IIC
is in standby status
When LCD (including booster circuit) is
stopped and IIC is in standby status
This includes only the current that flows through the A/D converter. When the A/D converter is operating
in operation mode or HALT mode, the current value of the 78K0/LE2 is obtained by adding IADC to IDD1 or
IDD2.
This includes only the current that flows through the watchdog timer (including the operating current of the
240 kHz internal oscillator). When the watchdog timer is operating in HALT mode or STOP mode, the
current value of the 78K0/LE2 is obtained by adding IWDT to IDD2 or IDD3.
This includes only the current that flows through the LVI circuit. When the LVI circuit is operating in HALT
mode or STOP mode, the current value of the 78K0/LE2 is obtained by adding ILVI to IDD2 or IDD3.
This includes only the current that flows through the LCD controller/driver. The current value of the
78K0/LE2 is obtained by adding the LCD operating current (ILCD1, ILCD2, ILCD3, or ILCD4) to the supply
current (IDD1, IDD2, or IDD3).
User’s Manual U17734EJ2V0UD
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CHAPTER 27 ELECTRICAL SPECIFICATIONS
AC Characteristics
(1) Basic operation
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, AVREF ≤ VDD , VSS = LVSS = AVSS = 0 V)
Parameter
Instruction cycle (minimum
Symbol
TCY
instruction execution time)
Conditions
MIN.
fEXCLK
Unit
Main system clock (fXP)
4.0 V ≤ VDD ≤ 5.5 V
0.1
32
μs
2.7 V ≤ VDD < 4.0 V
0.2
32
μs
32
μs
Subsystem clock (fSUB) operation
frequency
MAX.
operation
1.8 V ≤ VDD < 2.7 V
External main system clock
TYP.
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
Note 1
0.4
125
μs
1.0
Note 2
20.0
MHz
1.0
Note 2
114
122
10.0
MHz
1.8 V ≤ VDD < 2.7 V
1.0
5.0
MHz
External main system clock
tEXCLKH,
4.0 V ≤ VDD ≤ 5.5 V
24
500
ns
input high-level width, low-level
tEXCLKL
2.7 V ≤ VDD < 4.0 V
48
500
ns
1.8 V ≤ VDD < 2.7 V
96
500
ns
35
kHz
width
External subsystem clock
fEXCLKS
32
32.768
External subsystem clock input
tEXCLKSH,
12
ns
high-level width, low-level width
tEXCLKSL
2/fsam +
μs
frequency
TI000, TI010
tTIH0,
input high-level width,
tTIL0
low-level width
4.0 V ≤ VDD ≤ 5.5 V
0.1
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
fTI5
Note 3
μs
2/fsam +
0.5
TI50, TI51 input frequency
μs
2/fsam +
0.2
Note 3
Note 3
4.0 V ≤ VDD ≤ 5.5 V
10
MHz
2.7 V ≤ VDD < 4.0 V
10
MHz
1.8 V ≤ VDD < 2.7 V
5
MHz
TI50, TI51 input high-level width, tTIH5,
4.0 V ≤ VDD ≤ 5.5 V
50
ns
low-level width
2.7 V ≤ VDD < 4.0 V
50
ns
1.8 V ≤ VDD < 2.7 V
100
ns
1
μs
10
μs
tTIL5
Interrupt input high-level width,
tINTH,
low-level width
tINTL
RESET low-level width
tRSL
Notes 1.
0.38 μs when operating with the 8 MHz internal oscillator.
2.
It is 2.0 MHz (MIN.) when programming on the board via UART6.
3.
Selection of fsam = fPRS, fPRS/4, fPRS/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler
mode registers 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam =
fPRS.
570
User’s Manual U17734EJ2V0UD
CHAPTER 27 ELECTRICAL SPECIFICATIONS
TCY vs. VDD (Main System Clock Operation)
100
32
10
Cycle time TCY [ μ s]
5.0
Guaranteed
operation range
2.0
1.0
0.4
0.2
0.1
0.01
0
1.0
2.0
1.8
3.0
4.0
5.0 5.5 6.0
2.7
Supply voltage VDD [V]
AC Timing Test Points (Excluding External Main System Clock and External Subsystem Clock)
VIH
VIH
Test points
VIL
VIL
External Main System Clock Timing, External Subsystem Clock Timing
1/fEXCLK
tEXCLKL
tEXCLKH
0.7VDD (MIN.)
0.3VDD (MAX.)
EXCLK
1/fEXCLKS
tEXCLKSL
tEXCLKSH
0.7VDD (MIN.)
0.3VDD (MAX.)
EXCLKS
User’s Manual U17734EJ2V0UD
571
CHAPTER 27 ELECTRICAL SPECIFICATIONS
TI Timing
tTIH0
tTIL0
TI000, TI010
1/fTI5
tTIL5
tTIH5
tINTL
tINTH
TI50, TI51
Interrupt Request Input Timing
INTP0 to INTP5
RESET Input Timing
tRSL
RESET
572
User’s Manual U17734EJ2V0UD
CHAPTER 27 ELECTRICAL SPECIFICATIONS
(2) Serial interface
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, VSS = LVSS = AVSS = 0 V)
(a) UART6 (Dedicated baud rate generator output)
Parameter
Symbol
Conditions
MIN.
TYP.
Transfer rate
MAX.
Unit
625
kbps
MAX.
Unit
625
kbps
(b) UART0 (Dedicated baud rate generator output)
Parameter
Symbol
Conditions
MIN.
TYP.
Transfer rate
(c) IIC0
Parameter
Symbol
SCL0 clock frequency
fSCL
Standard Mode
MIN.
MAX.
High-Speed Mode
MIN.
MAX.
Unit
0
100
0
400
kHz
tSU:STA
4.8
−
0.7
−
μs
Hold time
tHD:STA
4.1
−
0.7
−
μs
Hold time when SCL0 = “L”
tLOW
5.0
−
1.25
−
μs
Hold time when SCL0 = “H”
tHIGH
5.0
−
1.25
−
μs
tSU:DAT
0
−
0
−
μs
tHD:DAT
0.47
4.0
0.23
1.00
μs
Setup time of start/restart condition
Note 1
Data setup time (reception)
Note 2
Data hold time (transmission)
Notes 1.
2.
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
User’s Manual U17734EJ2V0UD
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CHAPTER 27 ELECTRICAL SPECIFICATIONS
(d) CSI10 (Master mode, SCK10... internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
200
ns
2.7 V ≤ VDD < 4.0 V
400
ns
1.8 V ≤ VDD < 2.7 V
600
ns
4.0 V ≤ VDD ≤ 5.5 V
tKCY1/2 −
ns
SCK10 cycle time
SCK10 high-/low-level width
tKCY1
tKH1,
Note 1
tKL1
20
2.7 V ≤ VDD < 4.0 V
tKCY1/2 −
ns
Note 1
30
1.8 V ≤ VDD < 2.7 V
tKCY1/2 −
ns
Note 1
60
4.0 V ≤ VDD ≤ 5.5 V
70
ns
2.7 V ≤ VDD < 4.0 V
100
ns
1.8 V ≤ VDD < 2.7 V
100
ns
SI10 setup time (to SCK10↑)
tSIK1
SI10 hold time (from SCK10↑)
tKSI1
Delay time from SCK10↓ to
tKSO1
30
ns
Note 2
C = 50 pF
40
ns
MAX.
Unit
SO10 output
Notes 1.
2.
This value is when high-speed system clock (fXH) is used.
C is the load capacitance of the SCK10 and SO10 output lines.
(e) CSI10 (Slave mode, SCK10... external clock input)
Parameter
SCK10 cycle time
SCK10 high-/low-level width
Symbol
Conditions
MIN.
TYP.
tKCY2
400
ns
tKH2,
tKCY2/2
ns
tKL2
SI10 setup time (to SCK10↑)
tSIK2
80
ns
SI10 hold time (from SCK10↑)
tKSI2
50
ns
Delay time from SCK10↓ to
SO10 output
tKSO2
C = 50 pF
Note
4.0 V ≤ VDD ≤ 5.5 V
120
ns
2.7 V ≤ VDD < 4.0 V
120
ns
1.8 V ≤ VDD < 2.7 V
180
ns
Note C is the load capacitance of the SO10 output line.
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User’s Manual U17734EJ2V0UD
CHAPTER 27 ELECTRICAL SPECIFICATIONS
Serial Transfer Timing
IIC0:
tLOW
SCL0
tHD:DAT
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:STA
SDA0
Stop
condition
Start
condition
Restart
condition
Stop
condition
CSI10:
tKCYm
tKLm
tKHm
SCK10
tSIKm
SI10
tKSIm
Input data
tKSOm
SO10
Remark
Output data
m = 1, 2
User’s Manual U17734EJ2V0UD
575
CHAPTER 27 ELECTRICAL SPECIFICATIONS
A/D Converter Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD, VSS = LVSS = AVSS = 0 V)
Parameter
Symbol
Resolution
Overall error
AINL
Conversion time
tCONV
Notes 1, 2
Zero-scale error
Full-scale error
EZS
Notes 1, 2
EFS
Note 1
Integral non-linearity error
Differential non-linearity error
Analog input voltage
2.
576
MIN.
RES
Notes 1, 2
Notes 1.
Conditions
ILE
Note 1
DLE
TYP.
MAX.
Unit
10
bit
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
2.3 V ≤ AVREF < 2.7 V
±1.2
%FSR
36.7
μs
4.0 V ≤ AVREF ≤ 5.5 V
6.1
2.7 V ≤ AVREF < 4.0 V
12.2
36.7
μs
2.3 V ≤ AVREF < 2.7 V
27
66.6
μs
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
2.3 V ≤ AVREF < 2.7 V
±0.6
%FSR
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
2.3 V ≤ AVREF < 2.7 V
±0.6
%FSR
4.0 V ≤ AVREF ≤ 5.5 V
±2.5
LSB
2.7 V ≤ AVREF < 4.0 V
±4.5
LSB
2.3 V ≤ AVREF < 2.7 V
±6.5
LSB
4.0 V ≤ AVREF ≤ 5.5 V
±1.5
LSB
2.7 V ≤ AVREF < 4.0 V
±2.0
LSB
2.3 V ≤ AVREF < 2.7 V
±2.0
LSB
AVREF
V
VAIN
AVSS
Excludes quantization error (±1/2 LSB).
This value is indicated as a ratio (%FSR) to the full-scale value.
User’s Manual U17734EJ2V0UD
CHAPTER 27 ELECTRICAL SPECIFICATIONS
LCD Characteristics (TA = −40 to +85°C, 2.0 V ≤ LVDD ≤ 5.5 V)
(1) Resistance division method
(a) Static display mode (2.0 V ≤ LVDD ≤ 5.5 V)
Parameter
LCD drive voltage
LCD divider resistor
Note 1
Symbol
Conditions
MIN.
VLCD
2.0
RLCD
60
TYP.
Unit
LVDD
V
150
kΩ
LCD output resistor
(Common)
Note 2
RODC
40
kΩ
LCD output resistor
(Segment)
Note 2
RODS
200
kΩ
Note 3
Pull-up resistor
between LVDD and VLC0
RLU
LVDD = 5.0 V, VLC0 = 3.0 V
100
MAX.
7.3
kΩ
(b) 1/3 bias method (2.5 V ≤ LVDD ≤ 5.5 V)
Parameter
LCD drive voltage
LCD divider resistor
Note 1
Symbol
Conditions
MIN.
VLCD
2.5
RLCD
60
TYP.
100
MAX.
Unit
LVDD
V
150
kΩ
LCD output resistor
(Common)
Note 2
RODC
40
kΩ
LCD output resistor
(Segment)
Note 2
RODS
200
kΩ
Note 3
Pull-up resistor
between LVDD and VLC0
RLU
LVDD = 5.0 V, VLC0 = 3.0 V
7.3
kΩ
(c) 1/2 bias method (2.7 V ≤ LVDD ≤ 5.5 V)
Parameter
LCD drive voltage
LCD divider resistor
Note 1
LCD output resistor
(Common)
Note 2
LCD output resistor
(Segment)
Note 2
Note 3
Pull-up resistor
between LVDD and VLC0
Notes 1.
2.
Symbol
Conditions
MIN.
MAX.
Unit
LVDD
V
150
kΩ
TA = −10 to +85°C
40
kΩ
TA = −40 to −10°C
60
kΩ
200
kΩ
VLCD
2.7
RLCD
60
RODC
TYP.
100
RODS
RLU
LVDD = 5.0 V, VLC0 = 3.0 V
7.3
kΩ
When internal resistors are connected only.
The output resistor is a resistor connected between one of the VLC0, VLC1, VLC2 and VSS pins, and either of
the SEG and COM pins.
3.
Remark
Disconnected when LCD mode is entered by setting the LCD mode setting register (LCDMD).
The figures in the above table indicate the values when a 0.47 μ F capacitor is connected between VLC0 to
VLC2 and GND.
User’s Manual U17734EJ2V0UD
577
CHAPTER 27 ELECTRICAL SPECIFICATIONS
(2) Internal voltage boosting method (1.8 V ≤ LVDD ≤ 5.5 V)
Parameter
Symbol
LCD output voltage variation range
VLCD2
Conditions
Note 1
C1 to C4
Note 2
= 0.47 μ F
GAIN = 0
MIN.
TYP.
MAX.
Unit
CTSEL1 = 0,
CTSEL0 = 1
1.35
1.43
1.51
V
CTSEL1 = 0,
CTSEL0 = 0
1.42
1.50
1.58
V
CTSEL1 = 1,
CTSEL0 = 1
1.48
1.57
1.66
V
CTSEL1 = 1,
CTSEL0 = 0
GAIN = 1
Doubler output voltage
Voltage boost wait time
Note 4
Note 3
1.63
Note 3
1.72
Note 3
V
CTSEL1 = 0,
CTSEL0 = 1
0.87
0.93
1.00
V
CTSEL1 = 0,
CTSEL0 = 0
0.94
1.00
1.06
V
CTSEL1 = 1,
CTSEL0 = 1
1.00
1.07
1.14
V
CTSEL1 = 1,
CTSEL0 = 0
1.06
1.13
1.20
V
C1 to C4
Note 1
= 0.47 μ F
2 VLCD2
V
VLCD0
C1 to C4
Note 1
= 0.47 μ F
3 VLCD2
V
tVAWAIT
GAIN = 1
VLCD1
Tripler output voltage
1.54
Note 2
Note 2
4.5 V ≤ LVDD ≤ 5.5 V
4
s
1.8 V ≤ LVDD < 4.5 V
0.5
s
0.5
s
GAIN = 0
LCD output resistor
Note 5
(Common)
RODC
40
kΩ
LCD output resistor
Note 5
(Segment)
RODS
200
kΩ
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VLC0 and GND
C3: A capacitor connected between VLC1 and GND
C4: A capacitor connected between VLC2 and GND
2. When the frame frequency is 128 Hz or lower, the SEG and COM pins are left open, and (LCDON, SCOC,
VLCON) = 111B.
3. When operating voltage range is 2.0 V ≤ LVDD < 5.5 V.
4. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled
(LCDON = 1).
5. The output resistor is a resistor connected between one of the VLC0, VLC1, VLC2 and VSS pins, and either of
the SEG and COM pins.
578
User’s Manual U17734EJ2V0UD
CHAPTER 27 ELECTRICAL SPECIFICATIONS
1.59 V POC Circuit Characteristics (TA = −40 to +85°C, VSS = LVSS = 0 V)
Parameter
Symbol
Detection voltage
VPOC
Power voltage rise inclination
tPTH
Minimum pulse width
tPW
Conditions
VDD: 0 V → change inclination of VPOC
MIN.
TYP.
MAX.
Unit
1.44
1.59
1.74
V
0.5
V/ms
200
μs
POC Circuit Timing
Supply voltage
(VDD)
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
tPW
tPTH
Time
Supply Voltage Rise Time (TA = −40 to +85°C, VSS = LVSS = 0 V)
Parameter
Maximum time to rise to 1.8 V (VDD (MIN.))
Symbol
MIN.
TYP.
POCMODE (option byte) = 0,
tPUP1
(VDD: 0 V → 1.8 V)
Maximum time to rise to 1.8 V (VDD (MIN.))
Conditions
MAX.
Unit
3.6
ms
1.9
ms
when RESET input is not used
POCMODE (option byte) = 0,
tPUP2
(releasing RESET input → VDD: 1.8 V)
when RESET input is used
Supply Voltage Rise Time Timing
• When RESET pin input is not used
• When RESET pin input is used
Supply voltage
(VDD)
Supply voltage
(VDD)
1.8 V
1.8 V
VPOC
Time
Time
tPUP1
RESET pin
tPUP2
2.7 V POC Circuit Characteristics (TA = −40 to +85°C, VSS = LVSS = 0 V)
Parameter
Detection voltage on application of supply
Symbol
VDDPOC
Conditions
POCMODE (option bye) = 1
MIN.
TYP.
MAX.
Unit
2.50
2.70
2.90
V
voltage
User’s Manual U17734EJ2V0UD
579
CHAPTER 27 ELECTRICAL SPECIFICATIONS
LVI Circuit Characteristics (TA = −40 to +85°C, VPOC ≤ VDD = LVDD ≤ 5.5 V, VSS = LVSS = 0 V)
Parameter
Detection
Symbol
Supply voltage level
voltage
External input pin
Note 1
Minimum pulse width
Conditions
MIN.
TYP.
MAX.
Unit
VLVI0
4.14
4.24
4.34
V
VLVI1
3.99
4.09
4.19
V
VLVI2
3.83
3.93
4.03
V
VLVI3
3.68
3.78
3.88
V
VLVI4
3.52
3.62
3.72
V
VLVI5
3.37
3.47
3.57
V
VLVI6
3.22
3.32
3.42
V
VLVI7
3.06
3.16
3.26
V
VLVI8
2.91
3.01
3.11
V
VLVI9
2.75
2.85
2.95
V
VLVI10
2.60
2.70
2.80
V
VLVI11
2.45
2.55
2.65
V
VLVI12
2.29
2.39
2.49
V
VLVI13
2.14
2.24
2.34
V
VLVI14
1.98
2.08
2.18
V
VLVI15
1.83
1.93
2.03
V
1.11
1.21
1.31
V
EXLVI
EXLVI < VDD, 1.8 V ≤ VDD ≤ 5.5 V
tLW
Operation stabilization wait time
Note 2
μs
200
tLWAIT
10
μs
Notes 1. The EXLVI/P120/INTP0 pin is used.
2. Time required from setting bit 7 (LVION) of the low-voltage detection register (LVIM) to 1 to operation
stabilization.
Remark
VLVI(n − 1) > VLVIn: n = 1 to 15
LVI Circuit Timing
Supply voltage
(VDD)
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
tLW
tLWAIT
LVION ← 1
580
User’s Manual U17734EJ2V0UD
Time
CHAPTER 27 ELECTRICAL SPECIFICATIONS
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)
Parameter
Data retention supply voltage
Symbol
Conditions
MIN.
VDDDR
1.44
TYP.
Note
MAX.
Unit
5.5
V
Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC
reset is effected, but data is not retained when a POC reset is effected.
Operation mode
STOP mode
Data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
Flash Memory Programming Characteristics
(TA = −40 to +85°C, 2.7 V ≤ VDD = LVDD ≤ 5.5 V, VSS = LVSS = AVSS = 0 V)
• Basic characteristics
Parameter
VDD supply current
Notes 1
Erase time
Symbol
IDD
Conditions
MIN.
fXP = 10 MHz (TYP.), 20 MHz (MAX.)
TYP.
MAX.
Unit
4.5
11.0
mA
All block
Teraca
20
200
ms
Block unit
Terasa
20
200
ms
Write time (in 8-bit units)
Twrwa
10
100
μs
Number of rewrites per chip
Cerwr
Retention: 10 years
100
Times
Note 2
1 erase + 1 write after erase = 1 rewrite
Notes 1.
2.
The prewrite time before erasure and the erase verify time (writeback time) are not included.
When a product is first written after shipment, “erase → write” and “write only” are both taken as one
rewrite.
Remarks 1. fXP: Main system clock oscillation frequency
2. For serial write operation characteristics, refer to 78K0/Lx2 Flash Memory Programming
(Programmer) Application Note (U18204E).
User’s Manual U17734EJ2V0UD
581
CHAPTER 28 PACKAGE DRAWINGS
64-PIN PLASTIC LQFP(FINE PITCH)(10x10)
HD
D
detail of lead end
48
33
49
A3
32
c
θ
E
L
Lp
HE
L1
(UNIT:mm)
17
64
1
16
ZE
e
ZD
b
x
M
S
A
ITEM
D
DIMENSIONS
10.00±0.20
E
10.00±0.20
HD
12.00±0.20
HE
12.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
b
A2
c
S
y
A1
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
582
User’s Manual U17734EJ2V0UD
L
0.25
0.22±0.05
0.145 +0.055
−0.045
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.50
x
0.08
y
0.08
ZD
1.25
ZE
1.25
P64GB-50-UEU-1
CHAPTER 28 PACKAGE DRAWINGS
64-PIN PLASTIC LQFP(12x12)
HD
D
detail of lead end
48
33
49
32
A3
c
θ
E
L
Lp
HE
L1
(UNIT:mm)
17
64
1
16
ZE
e
ZD
b
x
M
S
A
S
A1
S
NOTE
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
User’s Manual U17734EJ2V0UD
DIMENSIONS
12.00±0.20
E
12.00±0.20
HD
14.00±0.20
HE
14.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
A2
y
ITEM
D
0.25
b
0.32 +0.08
−0.07
c
0.145 +0.055
−0.045
L
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.65
x
0.13
y
0.10
ZD
ZE
1.125
1.125
P64GK-65-UET-1
583
CHAPTER 29 CAUTIONS FOR WAIT
29.1 Cautions for Wait
This product has two internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware.
Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data
may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes
processing, until the correct data is passed.
As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of
execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, see Table 291). This must be noted when real-time processing is performed.
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User’s Manual U17734EJ2V0UD
CHAPTER 29 CAUTIONS FOR WAIT
29.2 Peripheral Hardware That Generates Wait
Table 29-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait
clocks.
Table 29-1. Registers That Generate Wait and Number of CPU Wait Clocks
Peripheral
Register
Hardware
Serial interface
Access
Number of Wait Clocks
ASIS0
Read
1 clock (fixed)
ASIS6
Read
1 clock (fixed)
IICS0
Read
1 clock (fixed)
ADM
Write
1 to 5 clocks (when fAD = fPRS/2 is selected)
ADS
Write
1 to 7 clocks (when fAD = fPRS/3 is selected)
ADPC
Write
ADCR
Read
UART0
Serial interface
UART6
Serial interface
IIC0
A/D converter
1 to 9 clocks (when fAD = fPRS/4 is selected)
2 to 13 clocks (when fAD = fPRS/6 is selected)
2 to 17 clocks (when fAD = fPRS/8 is selected)
2 to 25 clocks (when fAD = fPRS/12 is selected)
The above number of clocks is when the same source clock is selected for fCPU and fPRS. The number of wait
clocks can be calculated by the following expression and under the following conditions.
• Number of wait clocks = {(1/fAD) × 2/(1/fCPU)} + 1
* Fraction is truncated if the number of wait clocks ≤ 0.5 and rounded up if the number of wait clocks > 0.5.
fAD:
A/D conversion clock frequency (fPRS/2 to fPRS/12)
fCPU:
CPU clock frequency
fPRS:
Peripheral hardware clock frequency
fXP:
Main system clock frequency
• Maximum number of times: Maximum speed of CPU (fXP), lowest speed of A/D conversion clock (fPRS/12)
• Minimum number of times: Minimum speed of CPU (fSUB/2), highest speed of A/D conversion clock (fPRS/2)
Caution When the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped,
do not access the registers listed above using an access method in which a wait request is issued.
Remark The clock is the CPU clock (fCPU).
User’s Manual U17734EJ2V0UD
585
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems that employ the 78K0/LE2.
Figure A-1 shows the development tool configuration.
• Support for PC98-NX series
Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX
series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles.
• WindowsTM
Unless otherwise specified, “Windows” means the following OSs.
• Windows 98
• Windows NTTM
• Windows 2000
• Windows XP
586
User’s Manual U17734EJ2V0UD
APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tool Configuration (1/2)
(1) When using the in-circuit emulator QB-78K0LX2
Software package
• Software package
Debugging software
Language processing software
• Assembler package
• Integrated debugger
• C compiler package
• Device file
• C library source fileNote 1
Control software
• Project manager
(Windows only)Note 2
Host machine
(PC or EWS)
USB interface cable
Power supply unit
In-circuit emulatorNote 3
Flash memory
write environment
Flash programmer
Emulation probe
Flash memory
write adapter
Flash memory
Target system
Notes 1.
2.
The C library source file is not included in the software package.
The project manager PM+ is included in the assembler package.
The PM+ is only used for Windows.
3.
In-circuit emulator QB-78K0LX2 is supplied with integrated debugger ID78K0-QB, simple flash memory
programmer PG-FPL3, power supply unit, and USB interface cable. Any other products are sold
separately.
User’s Manual U17734EJ2V0UD
587
APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tool Configuration (2/2)
(2) When using the on-chip debug emulator QB-78K0MINI
Software package
• Software package
Debugging software
Language processing software
• Assembler package
• Integrated debugger
• C compiler package
• Device file
• C library source fileNote 1
Control software
• Project manager
(Windows only)Note 2
Host machine (PC or EWS)
USB interface cable
Flash memory
writing environment
Flash programmer
On-chip debug emulatorNote 3
Flash memory
writing adapter
Connection cable
Flash memory
Target connector
Target system
Notes 1.
2.
The C library source file is not included in the software package.
The project manager PM+ is included in the assembler package.
PM+ is only used for Windows.
3.
On-chip debug emulator QB-78K0MINI is supplied with integrated debugger ID78K0-QB, USB
interface cable, and connection cable. Any other products are sold separately.
588
User’s Manual U17734EJ2V0UD
APPENDIX A DEVELOPMENT TOOLS
A.1 Software Package
SP78K0
Development tools (software) common to the 78K/0 Series are combined in this package.
78K/0 Series software package
Part number: μS××××SP78K0
Remark
×××× in the part number differs depending on the host machine and OS used.
μS××××SP78K0
××××
Host Machine
OS
AB17
PC-9800 series,
Windows (Japanese version)
BB17
IBM PC/AT compatibles
Windows (English version)
Supply Medium
CD-ROM
A.2 Language Processing Software
RA78K0
This assembler converts programs written in mnemonics into object codes executable
Assembler package
with a microcontroller.
This assembler is also provided with functions capable of automatically creating symbol
tables and branch instruction optimization.
This assembler should be used in combination with a device file (DF780397) (sold
separately).
This assembler package is a DOS-based application. It can also be used in Windows,
however, by using the Project Manager (included in assembler package) on Windows.
Part number: μS××××RA78K0
CC78K0
This compiler converts programs written in C language into object codes executable with
C compiler package
a microcontroller.
This compiler should be used in combination with an assembler package and device file
(both sold separately).
This C compiler package is a DOS-based application. It can also be used in Windows,
however, by using the Project Manager (included in assembler package) on Windows.
Part number: μS××××CC78K0
Note 1
DF780397
This file contains information peculiar to the device.
Device file
This device file should be used in combination with a tool (RA78K0, CC78K0, and
ID78K0-QB) (all sold separately).
The corresponding OS and host machine differ depending on the tool to be used.
Part number: μS××××DF780397
CC78K0-L
Note 2
This is a source file of the functions that configure the object library included in the C
C library source file
compiler package.
This file is required to match the object library included in the C compiler package to the
user’s specifications.
Part number: μS××××CC78K0-L
Notes 1.
2.
The DF780397 can be used in common with the RA78K0, CC78K0, and ID78K0-QB.
The CC78K0-L is not included in the software package (SP78K0).
User’s Manual U17734EJ2V0UD
589
APPENDIX A DEVELOPMENT TOOLS
Remark
×××× in the part number differs depending on the host machine and OS used.
μS××××RA78K0
μS××××CC78K0
μS××××CC78K0-L
××××
Host Machine
AB17
PC-9800 series,
BB17
IBM PC/AT compatibles
3P17
HP9000 series 700
3K17
Windows (Japanese version)
TM
SPARCstation
OS
TM
Supply Medium
CD-ROM
Windows (English version)
HP-UX
TM
SunOS
TM
TM
Solaris
(Rel. 10.10)
(Rel. 4.1.4)
(Rel. 2.5.1)
μS××××DF780397
××××
Host Machine
OS
AB13
PC-9800 series,
Windows (Japanese version)
BB13
IBM PC/AT compatibles
Windows (English version)
Supply Medium
3.5-inch 2HD FD
A.3 Control Software
PM+
This is control software designed to enable efficient user program development in the
Project manager
Windows environment. All operations used in development of a user program, such as
starting the editor, building, and starting the debugger, can be performed from the project
manager.
The project manager is included in the assembler package (RA78K0).
It can only be used in Windows.
A.4 Flash Memory Writing Tools
PG-FP4, FL-PR4
Flash memory programmer dedicated to microcontrollers with on-chip flash memory.
Flash memory programmer
PG-FPL3, FP-LITE3
Simple flash memory programmer dedicated to microcontrollers with on-chip flash
Simple flash memory programmer
memory.
FA-64GB-UEU-A
Flash memory writing adapter used connected to flash memory programmer.
FA-78F0363GB-UEU-MX
• FA-64GB-UEU-A, FA-78F0363GB-UEU-MX
FA-64GK-UET-A
: For 64-pin plastic LQFP (GB-UEU type)
FA-78F0363GK-UET-MX
Flash memory writing adapter
Remarks 1.
• FA-64GK-UET-A, FA-78F0363GK-UET-MX
: For 64-pin plastic LQFP (GK-UET type)
FL-PR4, FP-LITE3, FA-64GB-UEU-A, FA-78F0363GB-UEU-MX, FA-64GK-UET-A and
FA-78F0363GK-UET-MX are products of Naito Densei Machida Mfg. Co., Ltd.
TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.
2.
590
Use the latest version of the flash memory programming adapter.
User’s Manual U17734EJ2V0UD
APPENDIX A DEVELOPMENT TOOLS
A.5 Debugging Tools (Hardware)
A.5.1 When using in-circuit emulator QB-78K0LX2
Note
QB-78K0LX2
This in-circuit emulator serves to debug hardware and software when developing application
In-circuit emulator
systems using the 78K0/LX2. It corresponds to the integrated debugger (ID78K0-QB). This
emulator should be used in combination with a power supply unit and emulation probe, and the
USB is used to connect this emulator to the host machine.
QB-144-CA-01
Check pin adapter
This check pin adapter is used in waveform monitoring using the oscilloscope, etc.
QB-144-EP-01S
Emulation probe
This emulation probe is flexible type and used to connect the in-circuit emulator and target
system.
QB-64GB-EA-07T,
QB-64GK-EA-05T
Exchange adapter
This exchange adapter is used to perform pin conversion from the in-circuit emulator to target
connector.
• QB-64GB-EA-07T: 64-pin plastic LQFP (GB-UEU type)
• QB-64GK-EA-05T: 64-pin plastic LQFP (GK-UET type)
QB-64GB-YS-01T,
QB-64GK-YS-01T
Space adapter
This space adapter is used to adjust the height between the target system and in-circuit emulator.
• QB-64GB-YS-01T: 64-pin plastic LQFP (GB-UEU type)
• QB-64GK-YS-01T: 64-pin plastic LQFP (GK-UET type)
QB-64GB-YQ-01T,
QB-64GK-YQ-01T
YQ connector
This YQ connector is used to connect the target connector and exchange adapter.
• QB-64GB-YQ-01T: 64-pin plastic LQFP (GB-UEU type)
• QB-64GK-YQ-01T: 64-pin plastic LQFP (GK-UET type)
QB-64GB-HQ-01T,
QB-64GK-HQ-01T
Mount adapter
This mount adapter is used to mount the target device with socket.
• QB-64GB-HQ-01T: 64-pin plastic LQFP (GB-UEU type)
• QB-64GK-HQ-01T: 64-pin plastic LQFP (GK-UET type)
QB-64GB-NQ-01T,
QB-64GK-NQ-01T
Target connector
This target connector is used to mount on the target system.
• QB-64GB-NQ-01T: 64-pin plastic LQFP (GB-UEU type)
• QB-64GK-NQ-01T: 64-pin plastic LQFP (GK-UET type)
Note
The QB-78K0LX2 is supplied with integrated debugger ID78K0-QB, simple flash memory programmer PGFPL3, power supply unit, and USB interface cable.
Remark
The packed contents differ depending on the part number, as follows.
Packed Contents
Part Number
QB-78K0LX2-ZZZ
QB-78K0LX2-T64GB
QB-78K0LX2-T64GK
In-Circuit
Emulation
Emulator
Probe
QB-78K0LX2
Exchange Adapter
YQ Connector
Target Connector
None
QB-144-EP-01S
QB-64GB-EA-07T
QB-64GB-YQ-01T
QB-64GB-NQ-01T
QB-64GK-EA-05T
QB-64GK-YQ-01T
QB-64GK-NQ-01T
User’s Manual U17734EJ2V0UD
591
APPENDIX A DEVELOPMENT TOOLS
A.5.2 When using on-chip debug emulator QB-78K0MINI
Note
QB-78K0MINI
The on-chip debug emulator serves to debug hardware and software when developing
On-chip debug emulator
application systems using the 78K0/Lx2. It supports the integrated debugger (ID78K0QB) supplied with the QB-78K0MINI. This emulator uses a connection cable and a USB
interface cable that is used to connect the host machine.
Target connector specifications
Note
10-pin general-purpose connector (2.54 mm pitch)
The QB-78K0MINI is supplied with integrated debugger ID78K0-QB, USB interface cable, and connection
cable.
A.6 Debugging Tools (Software)
ID78K0-QB
This debugger supports the in-circuit emulators for the 78K/0 Series. The ID78K0-QB is
Integrated debugger
Windows-based software.
It has improved C-compatible debugging functions and can display the results of tracing
with the source program using an integrating window function that associates the source
program, disassemble display, and memory display with the trace result. It should be
used in combination with the device file (sold separately).
Part number: μS××××ID78K0-QB
Remark
×××× in the part number differs depending on the host machine and OS used.
μS××××ID78K0-QB
××××
592
Host Machine
OS
AB17
PC-9800 series,
Windows (Japanese version)
BB17
IBM PC/AT compatibles
Windows (English version)
User’s Manual U17734EJ2V0UD
Supply Medium
CD-ROM
APPENDIX B REGISTER INDEX
B.1 Register Index (In Alphabetical Order with Respect to Register Names)
[A]
A/D converter mode register (ADM)............................................................................................................................253
A/D port configuration register (ADPC) .................................................................................................................86, 259
Analog input channel specification register (ADS) ......................................................................................................258
Asynchronous serial interface control register 6 (ASICL6)..........................................................................................306
Asynchronous serial interface operation mode register 0 (ASIM0) .............................................................................276
Asynchronous serial interface operation mode register 6 (ASIM6) .............................................................................300
Asynchronous serial interface reception error status register 0 (ASIS0).....................................................................278
Asynchronous serial interface reception error status register 6 (ASIS6).....................................................................302
Asynchronous serial interface transmission status register 6 (ASIF6) ........................................................................303
[B]
Baud rate generator control register 0 (BRGC0).........................................................................................................279
Baud rate generator control register 6 (BRGC6).........................................................................................................305
[C]
Capture/compare control register 00 (CRC00)............................................................................................................133
Clock operation mode select register (OSCCTL) ..........................................................................................................93
Clock output selection register (CKS) .................................................................................................................248, 434
Clock selection register 6 (CKSR6).............................................................................................................................304
[E]
8-bit A/D conversion result register (ADCRH) .............................................................................................................257
8-bit timer compare register 50 (CR50).......................................................................................................................193
8-bit timer compare register 51 (CR51).......................................................................................................................193
8-bit timer counter 50 (TM50)......................................................................................................................................193
8-bit timer counter 51 (TM51)......................................................................................................................................193
8-bit timer H carrier control register 1 (TMCYC1)........................................................................................................216
8-bit timer H compare register 00 (CMP00) ................................................................................................................211
8-bit timer H compare register 01 (CMP01) ................................................................................................................211
8-bit timer H compare register 10 (CMP10) ................................................................................................................211
8-bit timer H compare register 11 (CMP11) ................................................................................................................211
8-bit timer H mode register 0 (TMHMD0) ....................................................................................................................212
8-bit timer H mode register 1 (TMHMD1) ....................................................................................................................212
8-bit timer mode control register 50 (TMC50) .............................................................................................................196
8-bit timer mode control register 51 (TMC51) .............................................................................................................196
External interrupt falling edge enable register (EGN)..................................................................................................469
External interrupt rising edge enable register (EGP)...................................................................................................469
[I]
IIC clock selection register 0 (IICCL0).........................................................................................................................362
IIC control register 0 (IICC0) .......................................................................................................................................353
IIC flag register 0 (IICF0) ............................................................................................................................................360
User’s Manual U17734EJ2V0UD
593
APPENDIX B REGISTER INDEX
IIC function expansion register 0 (IICX0) ....................................................................................................................363
IIC shift register 0 (IIC0) ..............................................................................................................................................350
IIC status register 0 (IICS0).........................................................................................................................................358
Input switch control register (ISC) ...............................................................................................................................308
Internal memory size switching register (IMS).............................................................................................................528
Internal oscillation mode register (RCM) .......................................................................................................................97
Interrupt mask flag register 0H (MK0H).......................................................................................................................467
Interrupt mask flag register 0L (MK0L) ........................................................................................................................467
Interrupt mask flag register 1H (MK1H).......................................................................................................................467
Interrupt mask flag register 1L (MK1L) ........................................................................................................................467
Interrupt request flag register 0H (IF0H) .....................................................................................................................465
Interrupt request flag register 0L (IF0L).......................................................................................................................465
Interrupt request flag register 1H (IF1H) .....................................................................................................................465
Interrupt request flag register 1L (IF1L).......................................................................................................................465
[L]
LCD clock control register (LCDC) ..............................................................................................................................432
LCD display mode register (LCDM) ............................................................................................................................431
LCD mode setting register (LCDMD) ..........................................................................................................................430
LCD voltage boost control register 0 (VLCG0) ............................................................................................................433
Low-voltage detection level selection register (LVIS)..................................................................................................509
Low-voltage detection register (LVIM).........................................................................................................................508
[M]
Main clock mode register (MCM) ..................................................................................................................................99
Main OSC control register (MOC) .................................................................................................................................98
[O]
Oscillation stabilization time counter status register (OSTC)...............................................................................100, 479
Oscillation stabilization time select register (OSTS)............................................................................................101, 480
[P]
Port mode register 0 (PM0) ...................................................................................................................................83, 137
Port mode register 1 (PM1) ...................................................................................................83, 198, 216, 280, 308, 334
Port mode register 2 (PM2) ...................................................................................................................................83, 260
Port mode register 3 (PM3) ...................................................................................................................................83, 198
Port mode register 6 (PM6) ...................................................................................................................................83, 365
Port mode register 7 (PM7) ...........................................................................................................................................83
Port mode register 12 (PM12) ...............................................................................................................................83, 510
Port mode register 14 (PM14) .............................................................................................................................249, 435
Port register 0 (P0)........................................................................................................................................................84
Port register 1 (P1)........................................................................................................................................................84
Port register 2 (P2)........................................................................................................................................................84
Port register 3 (P3)........................................................................................................................................................84
Port register 6 (P6)........................................................................................................................................................84
Port register 12 (P12) ....................................................................................................................................................84
Port register 13 (P13) ..................................................................................................................................................435
Prescaler mode register 00 (PRM00) ..........................................................................................................................136
594
User’s Manual U17734EJ2V0UD
APPENDIX B REGISTER INDEX
Priority specification flag register 0H (PR0H) ..............................................................................................................468
Priority specification flag register 0L (PR0L) ...............................................................................................................468
Priority specification flag register 1H (PR1H) ..............................................................................................................468
Priority specification flag register 1L (PR1L) ...............................................................................................................468
Processor clock control register (PCC) .........................................................................................................................95
Pull-up resistor option register 0 (PU0) .........................................................................................................................85
Pull-up resistor option register 1 (PU1) .........................................................................................................................85
Pull-up resistor option register 3 (PU3) .........................................................................................................................85
Pull-up resistor option register 12 (PU12) .....................................................................................................................85
[R]
Receive buffer register 0 (RXB0) ................................................................................................................................275
Receive buffer register 6 (RXB6) ................................................................................................................................299
Reset control flag register (RESF) ..............................................................................................................................499
[S]
Serial clock selection register 10 (CSIC10).................................................................................................................333
Serial I/O shift register 10 (SIO10) ..............................................................................................................................331
Serial operation mode register 10 (CSIM10)...............................................................................................................332
16-bit timer capture/compare register 000 (CR000)....................................................................................................128
16-bit timer capture/compare register 010 (CR010)....................................................................................................128
16-bit timer counter 00 (TM00)....................................................................................................................................128
16-bit timer mode control register 00 (TMC00) ...........................................................................................................131
16-bit timer output control register 00 (TOC00)...........................................................................................................134
Slave address register 0 (SVA0).................................................................................................................................350
[T]
10-bit A/D conversion result register (ADCR)..............................................................................................................256
Timer clock selection register 50 (TCL50) ..................................................................................................................194
Timer clock selection register 51 (TCL51) ..................................................................................................................194
Transmit buffer register 10 (SOTB10).........................................................................................................................331
Transmit buffer register 6 (TXB6)................................................................................................................................299
Transmit shift register 0 (TXS0) ..................................................................................................................................275
[W]
Watch timer operation mode register (WTM) ..............................................................................................................235
Watchdog timer enable register (WDTE) ....................................................................................................................241
User’s Manual U17734EJ2V0UD
595
APPENDIX B REGISTER INDEX
B.2 Register Index (In Alphabetical Order with Respect to Register Symbol)
[A]
ADCR:
10-bit A/D conversion result register........................................................................................................256
ADCRH:
8-bit A/D conversion result register..........................................................................................................257
ADM:
A/D converter mode register....................................................................................................................253
ADPC:
A/D port configuration register ...........................................................................................................86, 259
ADS:
Analog input channel specification register .............................................................................................258
ASICL6:
Asynchronous serial interface control register 6......................................................................................306
ASIF6:
Asynchronous serial interface transmission status register 6 ..................................................................303
ASIM0:
Asynchronous serial interface operation mode register 0........................................................................276
ASIM6:
Asynchronous serial interface operation mode register 6........................................................................300
ASIS0:
Asynchronous serial interface reception error status register 0...............................................................278
ASIS6:
Asynchronous serial interface reception error status register 6...............................................................302
[B]
BRGC0:
Baud rate generator control register 0 .....................................................................................................279
BRGC6:
Baud rate generator control register 6 .....................................................................................................305
[C]
CKS:
Clock output selection register ........................................................................................................248, 434
CKSR6:
Clock selection register 6 ........................................................................................................................304
CMP00:
8-bit timer H compare register 00 ............................................................................................................211
CMP01:
8-bit timer H compare register 01 ............................................................................................................211
CMP10:
8-bit timer H compare register 10 ............................................................................................................211
CMP11:
8-bit timer H compare register 11 ............................................................................................................211
CR000:
16-bit timer capture/compare register 000...............................................................................................128
CR010:
16-bit timer capture/compare register 010...............................................................................................128
CR50:
8-bit timer compare register 50................................................................................................................193
CR51:
8-bit timer compare register 51................................................................................................................193
CRC00:
Capture/compare control register 00 .......................................................................................................133
CSIC10:
Serial clock selection register 10 .............................................................................................................333
CSIM10:
Serial operation mode register 10............................................................................................................332
[E]
EGN:
External interrupt falling edge enable register .........................................................................................469
EGP:
External interrupt rising edge enable register ..........................................................................................469
[I]
IF0H:
Interrupt request flag register 0H .............................................................................................................465
IF0L:
Interrupt request flag register 0L .............................................................................................................465
IF1H:
Interrupt request flag register 1H .............................................................................................................465
IF1L:
Interrupt request flag register 1L .............................................................................................................465
IIC0:
IIC shift register 0 ....................................................................................................................................350
IICC0:
IIC control register 0 ................................................................................................................................353
IICCL0:
IIC clock selection register 0....................................................................................................................362
IICF0:
IIC flag register 0 .....................................................................................................................................360
596
User’s Manual U17734EJ2V0UD
APPENDIX B REGISTER INDEX
IICS0:
IIC status register 0 .................................................................................................................................358
IICX0:
IIC function expansion register 0.............................................................................................................363
IMS:
Internal memory size switching register ..................................................................................................528
ISC:
Input switch control register.....................................................................................................................308
[L]
LCDC:
LCD clock control register .......................................................................................................................432
LCDM:
LCD display mode register ......................................................................................................................431
LCDMD:
LCD mode setting register.......................................................................................................................430
LVIM:
Low-voltage detection register ................................................................................................................508
LVIS:
Low-voltage detection level selection register .........................................................................................509
[M]
MCM:
Main clock mode register ..........................................................................................................................99
MK0H:
Interrupt mask flag register 0H ................................................................................................................467
MK0L:
Interrupt mask flag register 0L.................................................................................................................467
MK1H:
Interrupt mask flag register 1H ................................................................................................................467
MK1L:
Interrupt mask flag register 1L.................................................................................................................467
MOC:
Main OSC control register .........................................................................................................................98
[O]
OSCCTL:
Clock operation mode select register ........................................................................................................93
OSTC:
Oscillation stabilization time counter status register ........................................................................100, 479
OSTS:
Oscillation stabilization time select register .....................................................................................101, 480
[P]
P0:
Port register 0............................................................................................................................................84
P1:
Port register 1............................................................................................................................................84
P2:
Port register 2............................................................................................................................................84
P3:
Port register 3............................................................................................................................................84
P6:
Port register 6............................................................................................................................................84
P12:
Port register 12..........................................................................................................................................84
P13:
Port register 13........................................................................................................................................435
PCC:
Processor clock control register ................................................................................................................95
PM0:
Port mode register 0..........................................................................................................................83, 137
PM1:
Port mode register 1.......................................................................................... 83, 198, 216, 280, 308, 334
PM2:
Port mode register 2..........................................................................................................................83, 260
PM3:
Port mode register 3..........................................................................................................................83, 198
PM6:
Port mode register 6..........................................................................................................................83, 365
PM7:
Port mode register 7..................................................................................................................................83
PM12:
Port mode register 12........................................................................................................................83, 510
PM14:
Port mode register 14......................................................................................................................249, 435
PR0H:
Priority specification flag register 0H .......................................................................................................468
PR0L:
Priority specification flag register 0L........................................................................................................468
PR1H:
Priority specification flag register 1H .......................................................................................................468
PR1L:
Priority specification flag register 1L........................................................................................................468
PRM00:
Prescaler mode register 00 .....................................................................................................................136
PU0:
Pull-up resistor option register 0................................................................................................................85
User’s Manual U17734EJ2V0UD
597
APPENDIX B REGISTER INDEX
PU1:
Pull-up resistor option register 1 ................................................................................................................85
PU3:
Pull-up resistor option register 3 ................................................................................................................85
PU12:
Pull-up resistor option register 12 ..............................................................................................................85
[R]
RCM:
Internal oscillation mode register ...............................................................................................................97
RESF:
Reset control flag register........................................................................................................................499
RXB0:
Receive buffer register 0 .........................................................................................................................275
RXB6:
Receive buffer register 6 .........................................................................................................................299
[S]
SIO10:
Serial I/O shift register 10 ........................................................................................................................331
SOTB10:
Transmit buffer register 10 ......................................................................................................................331
SVA0:
Slave address register 0..........................................................................................................................350
[T]
TCL50:
Timer clock selection register 50 .............................................................................................................194
TCL51:
Timer clock selection register 51 .............................................................................................................194
TM00:
16-bit timer counter 00.............................................................................................................................128
TM50:
8-bit timer counter 50...............................................................................................................................193
TM51:
8-bit timer counter 51...............................................................................................................................193
TMC00:
16-bit timer mode control register 00 .......................................................................................................131
TMC50:
8-bit timer mode control register 50 .........................................................................................................196
TMC51:
8-bit timer mode control register 51 .........................................................................................................196
TMCYC1:
8-bit timer H carrier control register 1 ......................................................................................................216
TMHMD0: 8-bit timer H mode register 0 ...................................................................................................................212
TMHMD1: 8-bit timer H mode register 1 ...................................................................................................................212
TOC00:
16-bit timer output control register 00 ......................................................................................................134
TXB6:
Transmit buffer register 6 ........................................................................................................................299
TXS0:
Transmit shift register 0 ...........................................................................................................................275
[V]
VLCG0:
LCD voltage boost control register 0 .......................................................................................................433
[W]
WDTE:
Watchdog timer enable register...............................................................................................................241
WTM:
Watch timer operation mode register.......................................................................................................235
598
User’s Manual U17734EJ2V0UD
APPENDIX C REVISION HISTORY
C.1 Major Revisions in This Edition
Page
Throughout
Description
Classification
Addition of P60 and P61 pins, port mode register 6 (PM6), and port register 6 (P6)
(b)
Extending value range of capacitor (“0.47 μF: target” → “0.47 to 1 μF: recommended)
(b)
CHAPTER 1 OUTLINE
p. 17
Deletion of description concerning production process division management from 1.1 Features
(d)
p. 18
Change of 1.3 Ordering Information
(d)
p. 21
Change of 1.5 78K0/Lx2 Series Lineup
(d)
p. 23
Change of 1.6 Block Diagram
(d)
p. 24
Deletion of description concerning production process division management from 1.7 Outline of
Functions
(d)
CHAPTER 3 CPU ARCHITECTURE
p. 37
Addition of Note to Table 3-1 Set Values of Internal Memory Size Switching Register (IMS)
(c)
p. 56
Addition of Note 3 to Table 3-6 Special Function Register List (3/3)
(c)
CHAPTER 11 CLOCK OUTPUT CONTROLLER
p. 248
Change of Figure 11-2 Format of Clock Output Selection Register (CKS)
(b)
CHAPTER 15 SERIAL INTERFACE CSI10
p. 333
Change of Figure 15-3 Format of Serial Clock Selection Register 10 (CSIC10)
(b)
CHAPTER 17 LCD CONTROLLER/DRIVER
p. 433
Change of Figure 17-8 Format of LCD Voltage Boost Control Register 0
(a)
p. 434
Addition of Caution 1 to Figure 17-9 Format of Clock Output Selection Register
(c)
p. 458
Change of Figure 17-29 Examples of LCD Drive Power Connections (External Resistance
Division Method)
(c)
CHAPTER 20 RESET FUNCTION
p. 496
Addition of Note 4 to Table 20-2 Hardware Statuses After Reset Acknowledgment (1/3)
(c)
CHAPTER 24 FLASH MEMORY
p. 528
Addition of Note to Table 24-1 Internal Memory Size Switching Register Settings
(c)
p. 534
Change of Figure 24-7 FLMD0 Pin Connection Example
(b)
CHAPTER 27 ELECTRICAL SPECIFICATIONS
p. 561
Change to formal spec from target spec
(b)
APPENDIX A DEVELOPMENT TOOLS
p. 590
Addition of FA-78F0363GB-UEU-MX and FA-78F0363GK-UET-MX to A.4 Flash Memory Writing
Tools
(d)
APPENDIX C REVISION HISTORY
p. 599
Remark
Addition of appendix
(c)
“Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
User’s Manual U17734EJ2V0UD
599
For further information,
please contact:
NEC Electronics Corporation
1753, Shimonumabe, Nakahara-ku,
Kawasaki, Kanagawa 211-8668,
Japan
Tel: 044-435-5111
http://www.necel.com/
[America]
[Europe]
[Asia & Oceania]
NEC Electronics America, Inc.
2880 Scott Blvd.
Santa Clara, CA 95050-2554, U.S.A.
Tel: 408-588-6000
800-366-9782
http://www.am.necel.com/
NEC Electronics (Europe) GmbH
Arcadiastrasse 10
40472 Düsseldorf, Germany
Tel: 0211-65030
http://www.eu.necel.com/
NEC Electronics (China) Co., Ltd
7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian
District, Beijing 100083, P.R.China
TEL: 010-8235-1155
http://www.cn.necel.com/
Hanover Office
Podbielski Strasse 166 B
30177 Hanover
Tel: 0 511 33 40 2-0
NEC Electronics Shanghai Ltd.
Room 2509-2510, Bank of China Tower,
200 Yincheng Road Central,
Pudong New Area, Shanghai P.R. China P.C:200120
Tel: 021-5888-5400
http://www.cn.necel.com/
Munich Office
Werner-Eckert-Strasse 9
81829 München
Tel: 0 89 92 10 03-0
Stuttgart Office
Industriestrasse 3
70565 Stuttgart
Tel: 0 711 99 01 0-0
United Kingdom Branch
Cygnus House, Sunrise Parkway
Linford Wood, Milton Keynes
MK14 6NP, U.K.
Tel: 01908-691-133
Succursale Française
9, rue Paul Dautier, B.P. 52180
78142 Velizy-Villacoublay Cédex
France
Tel: 01-3067-5800
Sucursal en España
Juan Esplandiu, 15
28007 Madrid, Spain
Tel: 091-504-2787
NEC Electronics Hong Kong Ltd.
12/F., Cityplaza 4,
12 Taikoo Wan Road, Hong Kong
Tel: 2886-9318
http://www.hk.necel.com/
Seoul Branch
11F., Samik Lavied’or Bldg., 720-2,
Yeoksam-Dong, Kangnam-Ku,
Seoul, 135-080, Korea
Tel: 02-558-3737
NEC Electronics Taiwan Ltd.
7F, No. 363 Fu Shing North Road
Taipei, Taiwan, R. O. C.
Tel: 02-2719-2377
NEC Electronics Singapore Pte. Ltd.
238A Thomson Road,
#12-08 Novena Square,
Singapore 307684
Tel: 6253-8311
http://www.sg.necel.com/
Tyskland Filial
Täby Centrum
Entrance S (7th floor)
18322 Täby, Sweden
Tel: 08 638 72 00
Filiale Italiana
Via Fabio Filzi, 25/A
20124 Milano, Italy
Tel: 02-667541
Branch The Netherlands
Limburglaan 5
5616 HR Eindhoven
The Netherlands
Tel: 040 265 40 10
G05.12A
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