User’s Manual
8
78K0/Kx2-L
User’s Manual: Hardware
8-Bit Single-Chip Microcontrollers
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
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website (http://www.renesas.com).
www.renesas.com
Rev.4.00
Sep 2010
Notice
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2.
3.
4.
5.
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All information included in this document is current as of the date this document is issued. Such information, however, is
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NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction.
If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
How to Use This Manual
Readers
This manual is intended for user engineers who wish to understand the functions of the
78K0/Kx2-L microcontrollers and design and develop application systems and programs for
these devices.
The target products are as follows.
• 78K0/KY2-L: μPD78F0550, 78F0551, 78F0552, 78F0555, 78F0556, 78F0557
• 78K0/KA2-L: μPD78F0560, 78F0561, 78F0562, 78F0565, 78F0566, 78F0567
• 78K0/KB2-L: μPD78F0571, 78F0572, 78F0573, 78F0576, 78F0577, 78F0578
• 78K0/KC2-L: μPD78F0581, 78F0582, 78F0583, 78F0586, 78F0587, 78F0588
Purpose
Organization
This manual is intended to give users an understanding of the functions described in the
Organization below.
The manual for the 78K0/Kx2-L microcontrollers is separated into two parts: this manual
and the instructions edition (common to the 78K0 microcontrollers).
•
•
•
•
•
How to Read This Manual
78K0/Kx2-L
78K/0 Series
User’s Manual
(This Manual)
User’s Manual
Instructions
Pin functions
Internal block functions
Interrupts
Other on-chip peripheral functions
Electrical specifications
• CPU functions
• Instruction set
• Explanation of each instruction
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark “” shows major
revised points. The revised points can be easily searched by copying an “” in the
PDF file and specifying it in the “Find what:” field.
• How to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a reserved
word in the RA78K0, and is defined as an sfr variable using the #pragma sfr directive
in the CC78K0.
• When you know a register name and want to confirm its details:
→ Refer to APPENDIX B REGISTER INDEX.
• To know details of the 78K0 microcontroller instructions:
→ Refer to the separate document 78K/0 Series Instructions User’s Manual
(U12326E).
Conventions
Related Documents
Data significance:
Active low representations:
Note:
Caution:
Remark:
Numerical representations:
Higher digits on the left and lower digits on the right
××× (overscore over pin and signal name)
Footnote for item marked with Note in the text
Information requiring particular attention
Supplementary information
...×××× or ××××B
Binary
...××××
Decimal
Hexadecimal ...××××H
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
78K0/Kx2-L User’s Manual
This manual
78K0/Kx2-L Application Note Setting for Low Power Consumption Operation
U19612E
78K/0 Series User’s Manual Instructions
U12326E
78K0 Microcontrollers User’s Manual Self Programming Library Type 01
U18274E
78K0 Microcontrollers Self Programming Library Type 01 Ver. 3.10 Operating Precautions (Notification
ZUD-CD-09-0122
Document)
78K0 Microcontrollers User’s Manual EEPROM™ Emulation Library Type 01
U18275E
78K0 Microcontrollers EEPROM Emulation Library Type 01 Ver.2.10 Operating Precautions (Notification
ZUD-CD-09-0165
Document)
Documents Related to Development Tools (Hardware) (User’s Manual)
Document Name
Document No.
QB-MINI2 On-Chip Debug Emulator with Programming Function
QB-Programmer Programming GUI
U18371E
Operation
U18527E
Documents Related to Flash Memory Programming (User’s Manual)
Document Name
PG-FP5 Flash Memory Programmer
Caution
Document No.
U18865E
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Documents Related to Development Tools (Software)
Document Name
RA78K0 Ver.3.80 Assembler Package User’s Manual
Note 1
Document No.
Operation
U17199E
Language
U17198E
Structured Assembly Language
Note 1
78K0 Assembler Package RA78K0 Ver.4.01 Operating Precautions (Notification Document)
CC78K0 Ver.3.70 C Compiler User’s Manual
Note 2
Operation
U17197E
ZUD-CD-07-0181-E
U17201E
Language
U17200E
Note 2
78K0 C Compiler CC78K0 Ver. 4.00 Operating Precautions (Notification Document)
ZUD-CD-07-0103-E
SM+ System Simulator User’s Manual
Operation
U18601E
User Open Interface
U18212E
ID78K0-QB Ver.2.94 Integrated Debugger User’s Manual
Operation
U18330E
ID78K0-QB Ver.3.00 Integrated Debugger User’s Manual
Operation
U18492E
PM plus Ver.5.20
Note 3
Note 4
PM+ Ver.6.30
Notes 1.
User’s Manual
U16934E
User’s Manual
U18416E
This document is installed into the PC together with the tool when installing RA78K0 Ver. 4.01.
For
descriptions not included in “78K0 Assembler Package RA78K0 Ver. 4.01 Operating Precautions”, refer to the
user’s manual of RA78K0 Ver. 3.80.
2.
This document is installed into the PC together with the tool when installing CC78K0 Ver. 4.00.
For
descriptions not included in “78K0 C Compiler CC78K0 Ver. 4.00 Operating Precautions”, refer to the user’s
manual of CC78K0 Ver. 3.70.
3.
PM plus Ver. 5.20 is the integrated development environment included with RA78K0 Ver. 3.80.
4.
PM+ Ver. 6.30 is the integrated development environment included with RA78K0 Ver. 4.01. Software tool
(assembler, C compiler, debugger, and simulator) products of different versions can be managed.
Other Documents
Document Name
Document No.
SEMICONDUCTOR SELECTION GUIDE − Products and Packages −
X13769X
Semiconductor Device Mount Manual
Note
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www2.renesas.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
All trademarks and registered trademarks are the property of their respective owners.
EEPROM is a trademark of Renesas Electronics Corporation.
Windows is a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States
and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
CONTENTS
CHAPTER 1 OUTLINE............................................................................................................................... 1
1.1 Features........................................................................................................................................... 1
1.2 Ordering Information...................................................................................................................... 4
1.3 Pin Configuration (Top View) ........................................................................................................ 6
1.3.1 78K0/KY2-L....................................................................................................................................... 6
1.3.2 78K0/KA2-L....................................................................................................................................... 7
1.3.3 78K0/KB2-L..................................................................................................................................... 11
1.3.4 78K0/KC2-L..................................................................................................................................... 12
1.4 Block Diagram .............................................................................................................................. 18
1.4.1 78K0/KY2-L..................................................................................................................................... 18
1.4.2 78K0/KA2-L..................................................................................................................................... 19
1.4.3 78K0/KB2-L..................................................................................................................................... 22
1.4.4 78K0/KC2-L..................................................................................................................................... 23
1.5 Outline of Functions..................................................................................................................... 24
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 26
2.1 Pin Function List .......................................................................................................................... 26
2.1.1 78K0/KY2-L..................................................................................................................................... 27
2.1.2 78K0/KA2-L..................................................................................................................................... 29
2.1.3 78K0/KB2-L..................................................................................................................................... 34
2.1.4 78K0/KC2-L..................................................................................................................................... 37
2.2 Description of Pin Functions ...................................................................................................... 42
2.2.1 P00 to P02 (port 0) .......................................................................................................................... 42
2.2.2 P10 to P17 (port 1) .......................................................................................................................... 43
2.2.3 P20 to P27 (port 2) .......................................................................................................................... 44
2.2.4 P30 to P37 (port 3) .......................................................................................................................... 45
2.2.5 P40 to P42 (port 4) .......................................................................................................................... 47
2.2.6 P60 to P63 (port 6) .......................................................................................................................... 48
2.2.7 P70 to P75 (port 7) .......................................................................................................................... 49
2.2.8 P120 to P125 (port 12) .................................................................................................................... 50
2.2.9 AVREF, AVSS, VDD, VSS ..................................................................................................................... 52
2.2.10 REGC, IC0, IC............................................................................................................................... 52
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 54
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 64
3.1 Memory Space .............................................................................................................................. 64
3.1.1 Internal program memory space ..................................................................................................... 69
3.1.2 Internal data memory space............................................................................................................ 71
3.1.3 Special function register (SFR) area ............................................................................................... 71
3.1.4 Data memory addressing ................................................................................................................ 72
3.2 Processor Registers..................................................................................................................... 76
3.2.1 Control registers .............................................................................................................................. 76
3.2.2 General-purpose registers............................................................................................................... 80
3.2.3 Special function registers (SFRs) .................................................................................................... 81
3.3 Instruction Address Addressing............................................................................................... 106
3.3.1 Relative addressing....................................................................................................................... 106
3.3.2 Immediate addressing ................................................................................................................... 107
3.3.3 Table indirect addressing .............................................................................................................. 108
3.3.4 Register addressing ...................................................................................................................... 109
3.4 Operand Address Addressing .................................................................................................. 109
3.4.1 Implied addressing ........................................................................................................................ 109
3.4.2 Register addressing ...................................................................................................................... 110
3.4.3 Direct addressing .......................................................................................................................... 111
3.4.4 Short direct addressing ................................................................................................................. 112
3.4.5 Special function register (SFR) addressing ................................................................................... 113
3.4.6 Register indirect addressing.......................................................................................................... 114
3.4.7 Based addressing.......................................................................................................................... 115
3.4.8 Based indexed addressing ............................................................................................................ 116
3.4.9 Stack addressing........................................................................................................................... 117
CHAPTER 4 PORT FUNCTIONS ......................................................................................................... 118
4.1 Port Functions ............................................................................................................................ 118
4.2 Port Configuration...................................................................................................................... 125
4.2.1 Port 0............................................................................................................................................. 126
4.2.2 Port 1............................................................................................................................................. 129
4.2.3 Port 2............................................................................................................................................. 141
4.2.4 Port 3............................................................................................................................................. 147
4.2.5 Port 4............................................................................................................................................. 152
4.2.6 Port 6............................................................................................................................................. 155
4.2.7 Port 7............................................................................................................................................. 160
4.2.8 Port 12........................................................................................................................................... 162
4.3 Registers Controlling Port Function ........................................................................................ 167
4.4 Port Function Operations .......................................................................................................... 185
4.4.1 Writing to I/O port .......................................................................................................................... 185
4.4.2 Reading from I/O port.................................................................................................................... 185
4.4.3 Operations on I/O port................................................................................................................... 185
4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function........... 186
4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 197
CHAPTER 5 CLOCK GENERATOR .................................................................................................... 198
5.1
5.2
5.3
5.4
Functions of Clock Generator................................................................................................... 198
Configuration of Clock Generator ............................................................................................ 199
Registers Controlling Clock Generator.................................................................................... 202
System Clock Oscillator ............................................................................................................ 213
5.4.1 X1 oscillator................................................................................................................................... 213
5.4.2 XT1 oscillator ................................................................................................................................ 213
5.4.3 When subsystem clock is not used ............................................................................................... 216
5.4.4 Internal high-speed oscillator ........................................................................................................ 216
5.4.5 Internal low-speed oscillator.......................................................................................................... 216
5.4.6 Prescaler ....................................................................................................................................... 216
5.5 Clock Generator Operation ....................................................................................................... 217
5.6 Controlling Clock........................................................................................................................ 220
5.6.1 Example of controlling high-speed system clock ........................................................................... 220
5.6.2 Example of controlling internal high-speed oscillation clock.......................................................... 223
5.6.3 Example of controlling subsystem clock........................................................................................ 226
5.6.4 Example of controlling internal low-speed oscillation clock ........................................................... 228
5.6.5 Clocks supplied to CPU and peripheral hardware ......................................................................... 229
5.6.6 CPU clock status transition diagram.............................................................................................. 230
5.6.7 Condition before changing CPU clock and processing after changing CPU clock ........................ 236
5.6.8 Time required for switchover of CPU clock and main system clock .............................................. 237
5.6.9 Conditions before clock oscillation is stopped ............................................................................... 239
5.6.10 Peripheral hardware and source clocks ...................................................................................... 240
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 ........................................................................... 241
6.1
6.2
6.3
6.4
Functions of 16-Bit Timer/Event Counter 00 ........................................................................... 241
Configuration of 16-Bit Timer/Event Counter 00..................................................................... 242
Registers Controlling 16-Bit Timer/Event Counter 00 ............................................................ 248
Operation of 16-Bit Timer/Event Counter 00............................................................................ 257
6.4.1 Interval timer operation.................................................................................................................. 257
6.4.2 Square-wave output operation ...................................................................................................... 260
6.4.3 External event counter operation .................................................................................................. 263
6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input ......................................... 267
6.4.5 Free-running timer operation......................................................................................................... 280
6.4.6 PPG output operation.................................................................................................................... 289
6.4.7 One-shot pulse output operation ................................................................................................... 293
6.4.8 Pulse width measurement operation ............................................................................................. 298
6.5 Special Use of TM00................................................................................................................... 306
6.5.1 Rewriting CR010 during TM00 operation ...................................................................................... 306
6.5.2 Setting LVS00 and LVR00 ............................................................................................................ 306
6.6 Cautions for 16-Bit Timer/Event Counter 00............................................................................ 308
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................... 313
7.1
7.2
7.3
7.4
Functions of 8-Bit Timer/Event Counters 50 and 51............................................................... 313
Configuration of 8-Bit Timer/Event Counters 50 and 51 ........................................................ 314
Registers Controlling 8-Bit Timer/Event Counters 50 and 51................................................ 318
Operations of 8-Bit Timer/Event Counters 50 and 51 ............................................................. 326
7.4.1 Operation as interval timer ............................................................................................................ 326
7.4.2 Operation as external event counter ............................................................................................. 328
7.4.3 Square-wave output operation ...................................................................................................... 329
7.4.4 PWM output operation................................................................................................................... 330
7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 ............................................................... 334
CHAPTER 8 8-BIT TIMERS H0 AND H1........................................................................................... 335
8.1
8.2
8.3
8.4
Functions of 8-Bit Timers H0 and H1 ....................................................................................... 335
Configuration of 8-Bit Timers H0 and H1 ................................................................................. 335
Registers Controlling 8-Bit Timers H0 and H1 ........................................................................ 339
Operation of 8-Bit Timers H0 and H1........................................................................................ 347
8.4.1 Operation as interval timer/square-wave output ............................................................................ 347
8.4.2 Operation as PWM output ............................................................................................................. 350
8.4.3 Carrier generator operation (8-bit timer H1 only)........................................................................... 356
CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 363
9.1
9.2
9.3
9.4
Functions of Watchdog Timer................................................................................................... 363
Configuration of Watchdog Timer ............................................................................................ 364
Register Controlling Watchdog Timer...................................................................................... 365
Operation of Watchdog Timer................................................................................................... 366
9.4.1 Controlling operation of watchdog timer ........................................................................................ 366
9.4.2 Setting overflow time of watchdog timer........................................................................................ 367
9.4.3 Setting window open period of watchdog timer ............................................................................. 368
CHAPTER 10 REAL-TIME COUNTER................................................................................................. 370
10.1
10.2
10.3
10.4
Functions of Real-Time Counter............................................................................................. 370
Configuration of Real-Time Counter ...................................................................................... 370
Registers Controlling Real-Time Counter.............................................................................. 372
Real-Time Counter Operation ................................................................................................. 386
10.4.1 Starting operation of real-time counter ........................................................................................ 386
10.4.2 Shifting to STOP mode after starting operation ........................................................................... 387
10.4.3 Reading/writing real-time counter................................................................................................ 388
10.4.4 Setting alarm of real-time counter ............................................................................................... 390
10.4.5 1 Hz output of real-time counter .................................................................................................. 391
10.4.6 32.768 kHz output of real-time counter ....................................................................................... 391
10.4.7 512 Hz, 16.384 kHz output of real-time counter .......................................................................... 392
10.4.8 Example of watch error correction of real-time counter ............................................................... 393
CHAPTER 11 CLOCK OUTPUT CONTROLLER ............................................................................... 398
11.1
11.2
11.3
11.4
Functions of Clock Output Controller .................................................................................... 398
Configuration of Clock Output Controller.............................................................................. 398
Registers Controlling Clock Output Controller..................................................................... 399
Operations of Clock Output Controller .................................................................................. 400
CHAPTER 12 A/D CONVERTER ......................................................................................................... 401
12.1
12.2
12.3
12.4
Function of A/D Converter....................................................................................................... 401
Configuration of A/D Converter .............................................................................................. 403
Registers Used in A/D Converter............................................................................................ 405
A/D Converter Operations ....................................................................................................... 422
12.4.1 Basic operations of A/D converter ............................................................................................... 422
12.4.2 Input voltage and conversion results ........................................................................................... 424
12.4.3 A/D converter operation mode .................................................................................................... 426
12.5 How to Read A/D Converter Characteristics Table............................................................... 428
12.6 Cautions for A/D Converter ..................................................................................................... 430
CHAPTER 13 OPERATIONAL AMPLIFIERS ...................................................................................... 434
13.1
13.2
13.3
13.4
Function of Operational Amplifier .......................................................................................... 434
Configuration of Operational Amplifier.................................................................................. 435
Registers Used in Operational Amplifier ............................................................................... 436
Operational Amplifier Operations........................................................................................... 445
13.4.1 Single AMP mode (operational amplifiers 0 and 1) ..................................................................... 445
13.4.2 PGA (Programmable gain amplifier) mode (operational amplifier 0 only).................................... 445
CHAPTER 14 SERIAL INTERFACE UART6 ...................................................................................... 446
14.1
14.2
14.3
14.4
Functions of Serial Interface UART6 ...................................................................................... 446
Configuration of Serial Interface UART6................................................................................ 451
Registers Controlling Serial Interface UART6....................................................................... 454
Operation of Serial Interface UART6 ...................................................................................... 465
14.4.1 Operation stop mode................................................................................................................... 465
14.4.2 Asynchronous serial interface (UART) mode .............................................................................. 466
14.4.3 Dedicated baud rate generator.................................................................................................... 480
14.4.4 Calculation of baud rate .............................................................................................................. 482
CHAPTER 15 SERIAL INTERFACE IICA ........................................................................................... 487
15.1
15.2
15.3
15.4
Functions of Serial Interface IICA........................................................................................... 487
Configuration of Serial Interface IICA .................................................................................... 490
Registers Controlling Serial Interface IICA............................................................................ 492
I2C Bus Mode Functions........................................................................................................... 505
15.4.1 Pin configuration ......................................................................................................................... 505
15.4.2 Setting transfer clock by using IICWL and IICWH registers ........................................................ 506
2
15.5 I C Bus Definitions and Control Methods .............................................................................. 507
15.5.1 Start conditions ........................................................................................................................... 507
15.5.2 Addresses ................................................................................................................................... 508
15.5.3 Transfer direction specification.................................................................................................... 508
15.5.4 Acknowledge (ACK) .................................................................................................................... 509
15.5.5 Stop condition ............................................................................................................................. 510
15.5.6 Wait ............................................................................................................................................. 511
15.5.7 Canceling wait ............................................................................................................................. 513
15.5.8 Interrupt request (INTIICA0) generation timing and wait control ................................................. 514
15.5.9 Address match detection method ................................................................................................ 515
15.5.10 Error detection........................................................................................................................... 515
15.5.11 Extension code.......................................................................................................................... 515
15.5.12 Arbitration.................................................................................................................................. 516
15.5.13 Wakeup function........................................................................................................................ 518
15.5.14 Communication reservation....................................................................................................... 521
15.5.15 Cautions .................................................................................................................................... 525
15.5.16 Communication operations........................................................................................................ 526
15.5.17 Timing of I2C interrupt request (INTIICA0) occurrence .............................................................. 534
15.6 Timing Charts ........................................................................................................................... 555
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 ................................................................ 562
16.1
16.2
16.3
16.4
Functions of Serial Interfaces CSI10 and CSI11 ................................................................... 562
Configuration of Serial Interfaces CSI10 and CSI11 ............................................................. 563
Registers Controlling Serial Interfaces CSI10 and CSI11 .................................................... 566
Operation of Serial Interfaces CSI10 and CSI11.................................................................... 576
16.4.1 Operation stop mode................................................................................................................... 576
16.4.2 3-wire serial I/O mode ................................................................................................................. 577
CHAPTER 17 INTERRUPT FUNCTIONS............................................................................................. 591
17.1 Interrupt Function Types ......................................................................................................... 591
17.2 Interrupt Sources and Configuration ..................................................................................... 591
17.3 Registers Controlling Interrupt Functions............................................................................. 596
17.4 Interrupt Servicing Operations ............................................................................................... 629
17.4.1 Maskable interrupt acknowledgment ........................................................................................... 629
17.4.2 Software interrupt request acknowledgment ............................................................................... 631
17.4.3 Multiple interrupt servicing........................................................................................................... 632
17.4.4 Interrupt request hold .................................................................................................................. 635
CHAPTER 18 KEY INTERRUPT FUNCTION ..................................................................................... 636
18.1 Functions of Key Interrupt ...................................................................................................... 636
18.2 Configuration of Key Interrupt ................................................................................................ 637
18.3 Register Controlling Key Interrupt ......................................................................................... 638
CHAPTER 19 STANDBY FUNCTION .................................................................................................. 639
19.1 Standby Function and Configuration ..................................................................................... 639
19.1.1 Standby function ......................................................................................................................... 639
19.1.2 Registers controlling standby function......................................................................................... 640
19.2 Standby Function Operation ................................................................................................... 642
19.2.1 HALT mode ................................................................................................................................. 642
19.2.2 STOP mode ................................................................................................................................ 647
CHAPTER 20 RESET FUNCTION........................................................................................................ 655
20.1 Register for Confirming Reset Source ................................................................................... 664
CHAPTER 21 POWER-ON-CLEAR CIRCUIT...................................................................................... 665
21.1
21.2
21.3
21.4
Functions of Power-on-Clear Circuit...................................................................................... 665
Configuration of Power-on-Clear Circuit ............................................................................... 666
Operation of Power-on-Clear Circuit ...................................................................................... 666
Cautions for Power-on-Clear Circuit ...................................................................................... 669
CHAPTER 22 LOW-VOLTAGE DETECTOR ....................................................................................... 671
22.1
22.2
22.3
22.4
Functions of Low-Voltage Detector........................................................................................ 671
Configuration of Low-Voltage Detector ................................................................................. 672
Registers Controlling Low-Voltage Detector......................................................................... 672
Operation of Low-Voltage Detector ........................................................................................ 676
22.4.1 When used as reset .................................................................................................................... 678
22.4.2 When used as interrupt ............................................................................................................... 683
22.5 Cautions for Low-Voltage Detector ........................................................................................ 688
CHAPTER 23 REGULATOR ................................................................................................................. 691
23.1 Regulator Overview.................................................................................................................. 691
23.2 Register Controlling Regulator ............................................................................................... 691
23.3 Cautions for Self Programming .............................................................................................. 692
CHAPTER 24 OPTION BYTE............................................................................................................... 693
24.1 Functions of Option Bytes ...................................................................................................... 693
24.2 Format of Option Byte.............................................................................................................. 694
CHAPTER 25 FLASH MEMORY .......................................................................................................... 699
25.1
25.2
25.3
25.4
Internal Memory Size Switching Register .............................................................................. 699
Writing with Flash Memory Programmer ............................................................................... 700
Programming Environment ..................................................................................................... 701
Connection of Pins on Board.................................................................................................. 702
25.4.1 TOOL pins ................................................................................................................................... 702
25.4.2 RESET pin .................................................................................................................................. 703
25.4.3 Port pins ...................................................................................................................................... 703
25.4.4 REGC pin .................................................................................................................................... 703
25.4.5 Other signal pins ......................................................................................................................... 703
25.4.6 Power supply............................................................................................................................... 703
25.4.7 On-board writing when connecting crystal/ceramic resonator ..................................................... 704
25.5 Programming Method .............................................................................................................. 705
25.5.1 Controlling flash memory............................................................................................................. 705
25.5.2 Flash memory programming mode.............................................................................................. 705
25.5.3 Communication commands ......................................................................................................... 705
25.6 Security Settings ...................................................................................................................... 707
25.7 Processing Time for Each Command When PG-FP5 Is Used (Reference)......................... 709
25.8 Flash Memory Programming by Self Programming ............................................................. 712
25.8.1 Register controlling self programming mode ............................................................................... 713
25.8.2 Flow of self programming (Rewriting Flash Memory) .................................................................. 713
25.8.3 Boot swap function ...................................................................................................................... 715
25.9 Creating ROM Code to Place Order for Previously Written Product .................................. 717
25.9.1 Procedure for using ROM code to place an order ....................................................................... 717
CHAPTER 26 ON-CHIP DEBUG FUNCTION ..................................................................................... 718
26.1 Connecting QB-MINI2 to 78K0/Kx2-L Microcontrollers ........................................................ 718
26.2 On-Chip Debug Security ID ..................................................................................................... 721
26.3 Securing of User Resources ................................................................................................... 722
CHAPTER 27 INSTRUCTION SET....................................................................................................... 723
27.1 Conventions Used in Operation List ...................................................................................... 723
27.1.1 Operand identifiers and specification methods............................................................................ 723
27.1.2 Description of operation column .................................................................................................. 724
27.1.3 Description of flag operation column ........................................................................................... 724
27.2 Operation List ........................................................................................................................... 725
27.3 Instructions Listed by Addressing Type................................................................................ 733
CHAPTER 28 ELECTRICAL SPECIFICATIONS ................................................................................. 736
CHAPTER 29 PACKAGE DRAWINGS ................................................................................................ 769
29.1
29.2
29.3
29.4
78K0/KY2-L................................................................................................................................ 769
78K0/KA2-L ............................................................................................................................... 770
78K0/KB2-L ............................................................................................................................... 773
78K0/KC2-L ............................................................................................................................... 774
CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS........................................................... 777
CHAPTER 31 CAUTIONS FOR WAIT................................................................................................. 778
31.1 Cautions for Wait...................................................................................................................... 778
31.2 Peripheral Hardware That Generates Wait ............................................................................ 779
APPENDIX A DEVELOPMENT TOOLS............................................................................................... 780
A.1 Software Package ...................................................................................................................... 783
A.2 Language Processing Software ............................................................................................... 783
A.3 Flash Memory Programming Tools.......................................................................................... 784
A.3.1 When using flash memory programmer PG-FP5 and FL-PR5...................................................... 784
A.3.2 When using on-chip debug emulator with programming function QB-MINI2................................. 784
A.4 Debugging Tools (Hardware).................................................................................................... 785
A.4.1 When using in-circuit emulator...................................................................................................... 785
A.4.2 When using on-chip debug emulator with programming function QB-MINI2................................. 785
A.5 Debugging Tools (Software)..................................................................................................... 785
APPENDIX B REGISTER INDEX ......................................................................................................... 786
B.1 Register Index (In Alphabetical Order with Respect to Register Names) ............................ 786
B.2 Register Index (In Alphabetical Order with Respect to Register Symbol)........................... 790
APPENDIX C REVISION HISTORY ..................................................................................................... 794
C.1 Major Revisions in This Edition ............................................................................................... 794
C.2 Revision History of Preceding Editions .................................................................................. 798
R01UH0028EJ0400
Rev.4.00
Sep 27, 2010
78K0/Kx2-L
RENESAS MCU
CHAPTER 1 OUTLINE
1.1 Features
{ 78K0 CPU core
{ I/O ports, ROM and RAM capacities
Item
I/O ports
Products
78K0/KY2-L (16 pins)
12 (CMOS I/O: 9, CMOS input: 3)
78K0/KA2-L (20 pins)
16 (CMOS I/O: 13, CMOS input: 3)
78K0/KA2-L (25 pins)
21 (CMOS I/O: 18, CMOS input: 3)
78K0/KA2-L (32 pins)
25 (CMOS I/O: 22, CMOS input: 3)
78K0/KB2-L (30 pins)
24 (CMOS I/O: 21, CMOS input: 3)
78K0/KC2-L (40 pins)
34 (CMOS I/O: 29, CMOS input: 5)
78K0/KC2-L (44 pins)
38 (CMOS I/O: 33, CMOS input: 5)
78K0/KC2-L (48 pins)
42 (CMOS I/O: 37, CMOS input: 5)
Program Memory
Data Memory (Internal
(Flash Memory)
High-Speed RAM)
4 KB to 16 KB
384 bytes to 768 bytes
8 KB to 32 KB
512 bytes to 1 KB
{ Low power consumption (VDD = 3.0 V)
• Internal high-speed oscillation mode:
220 μ A (TYP.) (at fCPU = 1 MHz operation)
• STOP mode:
0.58 μ A (TYP.) (at fIL = 30 kHz operation)
• Subsystem clock and HALT mode:
0.98 μ A (at fSUB = 32.768 kHz operation) ∗ 78K0/KC2-L only
{ Clock
• High-speed system clock … Selected from the following three sources
- Ceramic/crystal oscillator:
1 to 10 MHz
- External clock:
1 to 10 MHz
- Internal high-speed oscillator: 4 MHz ± 2 % (–20 to +70°C), or 8 MHz ± 3 %(–40 to +85°C)
• Low-speed system oscillator
30 kHz ± 10 % … Watchdog timer, timer clock in intermittent operation
• Subsystem clock:
Clock to operate the real-time counter mainly (32.768 kHz)
{ Power-on-clear (POC) circuit
{ Low-voltage detector (LVI) (An interrupt/reset (selectable) is generated when the detection voltage is reached))
• Detection voltage: Selectable from sixteen levels between 1.91 and 4.22 V
{ Single-power-supply flash memory
• Flash self programming enabled
• Software protection function: Protected from outside party copying (no flash reading command)
{ Safety function
• Watchdog timer operated by clock independent from CPU
… A hang-up can be detected even if the system clock stops
• Supply voltage drop detectable by LVI
… Appropriate processing can be executed before the supply voltage drops below the operation voltage
• Equipped with option byte function
… Important system operation settings set in hardware
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Sep 27, 2010
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78K0/Kx2-L
CHAPTER 1 OUTLINE
{ Timer
• 16-bit timer/event counter … PPG output, capture input, external event counter input
• 8-bit timer H …
PWM output
• 8-bit timer/event counter 5 … PWM output, external event counter input
• Watchdog timer …
Operable with low-speed internal oscillation clock
• Real-time counter …
Available to count up in year, month, week, day, hour, minute, and second units
Item
16-bit timer/event
8-bit timer
Products
78K0/KY2-L (16 pins)
1 ch
Real-time counter
78K0/KA2-L (25 pins)
78K0/KA2-L (32 pins)
–
1 ch
Timer H: 1 ch
Timer 5: 1 ch
78K0/KA2-L (20 pins)
Watchdog timer
counter
78K0/KB2-L (30 pins)
Timer H: 2 ch
78K0/KC2-L (40 pins)
Timer 5: 2 ch
1 ch
78K0/KC2-L (44 pins)
78K0/KC2-L (48 pins)
{ Serial interface
• UART … Asynchronous 2-wire serial interface
• IICA …
Clock synchronous 2-wire serial interface, multimaster supported, standby can be released upon
• CSI …
Clock synchronous 3-wire serial interface
address match in slave mode
Item
UART
IIC
CSI
Products
78K0/KY2-L (16 pins)
1 ch
1 ch
–
78K0/KA2-L (20 pins)
78K0/KA2-L (25 pins)
78K0/KA2-L (32 pins)
1 ch (CSI11
Note
)
78K0/KB2-L (30 pins)
1 ch (CSI10)
78K0/KC2-L (40 pins)
2 ch (CSI10, CSI11)
78K0/KC2-L (44 pins)
78K0/KC2-L (48 pins)
2 ch (CSI10, CSI11
Note
)
Note Can control by an enabled signal, when using CSI11 in the slave mode.
{ 10-bit resolution A/D conversion
• 78K0/KY2-L: 4 ch
• 78K0/KA2-L (20 pins): 6 ch, 78K0/KA2-L (25 pins): 7 ch
78K0/KA2-L (32 pins): 11 ch
• 78K0/KB2-L: 7 ch
• 78K0/KC2-L (40 pins): 10 ch, 78K0/KC2-L (44 pins, 48 pins): 11 ch
{ Operational amplifier (products with operational amplifier only)
• 78K0/KY2-L, 78K0/KA2-L: 1 ch
• 78K0/KB2-L, 78K0/KC2-L: 2 ch
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78K0/Kx2-L
CHAPTER 1 OUTLINE
{ On-chip debug function …Available to control for the target device, and to reference memory
{ Assembler and C language supported
{ Development tools
• Support for full-function emulator (IECUBE), and simplified emulator (MINICUBE2)
{ Power supply voltage: VDD = 1.8 to 5.5 V
{ Operating ambient temperature: TA = –40 to +85°C
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Sep 27, 2010
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78K0/Kx2-L
CHAPTER 1 OUTLINE
1.2 Ordering Information
[Part Number]
μ PD78F05 x y ΔΔ - ××× -AX
Semiconductor
-AX
x
F
Product contains no lead in any area (Terminal
free
finish is Ni/Pd/Au plating)
ΔΔ - ×××
Package Type
5
MA-FAA
16-pin plastic SSOP (5.72 mm (225))
6
MC-CAA
20-pin plastic SSOP (7.62 mm (300))
FC-2N2
25-pin plastic FLGA (3x3)
K8-3B4
32-pin plastic WQFN (5x5)
7
MC-CAB
30-pin plastic SSOP (7.62 mm (300))
8
K8-4B4
40-pin plastic WQFN (6x6)
GB-GAF
44-pin plastic LQFP (10x10)
GA-GAM
48-pin plastic LQFP (fine pitch) (7x7)
y
Product Type
Lead-
Flash Memory
High-speed RAM
Operational
Capacity
Capacity
amplifier
0
4 KB
384 bytes
Not
1
8 KB
512 bytes
mounted
2
16 KB
768 bytes
3
32 KB
1 KB
5
4 KB
384 bytes
6
8 KB
512 bytes
7
16 KB
768 bytes
8
32 KB
1 KB
Mounted
Flash memory version
[Example of Part Number]
μ PD78F05 5 0 MA-FAA -AX
Lead-free
16-pin plastic SSOP (5.72 mm)
High-speed RAM: 384 bytes, flash memory: 4 KB,
operational amplifier: not mounted
Flash memory version
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Sep 27, 2010
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78K0/Kx2-L
CHAPTER 1 OUTLINE
[List of Part Number]
78K0/Kx2-L
Package
Part Number
Microcontrollers
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
16-pin plastic SSOP
μPD78F0550MA-FAA-AX, 78F0551MA-FAA-AX, 78F0552MA-FAA-AX,
(5.72 mm (225))
78F0555MA-FAA-AX, 78F0556MA-FAA-AX, 78F0557MA-FAA-AX
20-pin plastic SSOP
μPD78F0560MC-CAA-AX, 78F0561MC-CAA-AX, 78F0562MC-CAA-AX,
(7.62 mm (300))
78F0565MC-CAA-AX, 78F0566MC-CAA-AX, 78F0567MC-CAA-AX
25-pin plastic FLGA
μPD78F0560FC-2N2-A, 78F0561FC-2N2-A, 78F0562FC-2N2-A,
(3x3)
78F0565FC-2N2-A, 78F0566FC-2N2-A, 78F0567FC-2N2-A
32-pin plastic
μPD78F0560K8-3B4-AX, 78F0561K8-3B4-AX, 78F0562K8-3B4-AX,
WQFN (5x5)
78F0565K8-3B4-AX, 78F0566K8-3B4-AX, 78F0567K8-3B4-AX
30-pin plastic SSOP
μPD78F0571MC-CAB-AX, 78F0572MC-CAB-AX, 78F0573MC-CAB-AX,
(7.62 mm (300))
78F0576MC-CAB-AX, 78F0577MC-CAB-AX, 78F0578MC-CAB-AX
40-pin plastic
μPD78F0581K8-4B4-AX, 78F0582K8-4B4-AX, 78F0583K8-4B4-AX,
WQFN (6x6)
78F0586K8-4B4-AX, 78F0587K8-4B4-AX, 78F0588K8-4B4-AX
44-pin plastic LQFP
μPD78F0581GB-GAF-AX, 78F0582GB-GAF-AX, 78F0583GB-GAF-AX,
(10x10)
78F0586GB-GAF-AX, 78F0587GB-GAF-AX, 78F0588GB-GAF-AX
48-pin plastic LQFP
μPD78F0581GA-GAM-AX, 78F0582GA-GAM-AX, 78F0583GA-GAM-AX,
(fine pitch) (7x7)
78F0586GA-GAM-AX, 78F0587GA-GAM-AX, 78F0588GA-GAM-AX
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Sep 27, 2010
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78K0/Kx2-L
CHAPTER 1 OUTLINE
1.3 Pin Configuration (Top View)
1.3.1 78K0/KY2-L
• 16-pin plastic SSOP (5.72 mm (225))
P60/SCLA0/TxD6
1
16
AVREF
P61/SDAA0/RxD6
2
15
ANI0/P20/AMP0-Note
RESET/P125
3
14
ANI1/P21/AMP0OUTNote/PGAINNote
P122/X2/EXCLK/TOOLD0
4
13
ANI2/P22/AMP0+Note
P121/X1/TOOLC0
5
12
ANI3/P23
REGC
6
11
P00/TI000/INTP0
VSS
7
10
VDD
8
9
P30/TOH1/TI51/INTP1
Amplifier Input
P121, P122, P125 :
Port 12
Amplifier Output
REGC :
Regulator Capacitance
Programmable Gain
RESET :
Reset
Amplifier Input
RxD6 :
Receive Data
Analog Input
SCLA0 :
Serial Clock Input/Output
Note
AMP0-
, AMP0+
AMP0OUT
Note
PGAIN
Note
Note
:
:
:
ANI0 to ANI3 :
AVREF :
P01/TO00/TI010
Analog Reference
SDAA0 :
Serial Data Input/Output
Voltage
TI000, TI010, TI51 :
Timer Input
External Clock Input
TO00, TOH1 :
Timer Output
(Main System Clock)
TOOLC0 :
Clock Input for Tool
External Interrupt
TOOLD0 :
Data Input/Output for Tool
Input
TxD6 :
Transmit Data
P00, P01 :
Port 0
VDD :
Power Supply
P20 to P23 :
Port 2
VSS :
Ground
P30 :
Port 3
X1, X2 :
P60, P61 :
Port 6
EXCLK :
INTP0, INTP1 :
Crystal Oscillator
(Main System Clock)
Note μPD78F0555, 78F0556, 78F0557 (products with operational amplifier) only
Cautions 1. VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to
a stabilized GND (= 0 V).
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 are set in the
analog input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
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Sep 27, 2010
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78K0/Kx2-L
CHAPTER 1 OUTLINE
1.3.2 78K0/KA2-L
(1) 20-pin plastic SSOP (7.62 mm (300))
ANI5/P25
1
20
AVREF
ANI4/P24
2
19
ANI0/P20/AMP0-Note
P60/SCLA0/TxD6
3
18
ANI1/P21/AMP0OUTNote/PGAINNote
P61/SDAA0/RxD6
4
17
ANI2/P22/AMP0+Note
ANI3/P23
RESET/P125
5
16
P122/X2/EXCLK/TOOLD0
6
15
P00/TI000/INTP0
P121/X1/TOOLC0
7
14
P01/TI010/TO00
REGC
8
13
P30/TOH1/TI51/INTP1
VSS
9
12
P31/INTP2/TOOLC1
VDD
10
11
P32/INTP3/TOOLD1
Note
AMP0-
, AMP0+
AMP0OUT
Note
PGAIN
Note
Note
:
:
:
ANI0 to ANI5 :
AVREF :
Amplifier Input
P121, P122, P125 :
Port 12
Amplifier Output
REGC :
Regulator Capacitance
Programmable Gain
RESET :
Reset
Amplifier Input
RxD6 :
Receive Data
Analog Input
SCLA0 :
Serial Clock Input/Output
Analog Reference
SDAA0 :
Serial Data Input/Output
Voltage
TI000, TI010, TI51 :
Timer Input
External Clock Input
TO00, TOH1 :
Timer Output
(Main System Clock)
TOOLC0, TOOLC1 :
Clock Input for Tool
External Interrupt
TOOLD0, TOOLD1 :
Data Input/Output for Tool
Input
TxD6 :
Transmit Data
P00, P01 :
Port 0
VDD :
Power Supply
P20 to P25 :
Port 2
VSS :
Ground
P30 to P32 :
Port 3
X1, X2 :
P60, P61 :
Port 6
EXCLK :
INTP0 to INTP3 :
Crystal Oscillator
(Main System Clock)
Note μPD78F0565, 78F0566, 78F0567 (products with operational amplifier) only
Cautions 1. VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to
a stabilized GND (= 0 V).
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 to ANI5/P25 are set
in the analog input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
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78K0/Kx2-L
CHAPTER 1 OUTLINE
(2) 25-pin plastic FLGA (3x3) (1/2)
Bottom View
Top View
INDEX MARK
INDEX MARK
A
B
C
D
E
1
2
3
1
A
4
5
5
2
VDD
VSS
4
3
2
3
RESET/ P125
1
4
5
P61/RXD6
ANI4/P24
/SDAA0
B
REGC
C
P35/SCK11
D
P33
P121/X1/TOOLC0
P122/X2/EXCLK
(/TI000)(/INTP0)
/TOOLD0
P60/TXD6/SCLA0
ANI6/P26
P36/SI11
P37/SO11
P02/SSI11/INTP5
ANI5/P25
P00/TI000/INTP0
ANI3/P23
ANI2/P22
ANI0/P20
/AMP0+
(/TOH1)(/TI51)
E
P34/INTP4
(/TOH1)(/TI51)
P32/INTP3
/TOOLD1
P31/INTP2
/TOOLC1
Note
/AMP0-
Note
AVREF
ANI1/P21/
Note
AMP0OUT
Note
/PGAIN
AMP0-
Note
, AMP0+
Note
: Amplifier Input
RxD6
: Receive Data
: Amplifier Output
SCK11
: Serial Clock Input/Output
: Programmable Gain
SCLA0
: Serial Clock Input/Output
Amplifier Input
SDAA0
: Serial Data Input/Output
ANI0 to ANI6
: Analog Input
SI11
: Serial Data Input
AVREF
: Analog Reference Voltage
SO11
: Serial Data Output
EXCLK
: External Clock Input
SSI11
: Serial Interface Chip
AMP0OUT
Note
Note
PGAIN
(Main System Clock)
Select Input
INTP0, INTP2 to INTP5 : External Interrupt Input
TI000, TI51
: Timer Input
P00, P02
: Port 0
TOH1
: Timer Output
P20 to P26
: Port 2
TOOLC0, TOOLC1
: Clock Input for Tool
P31 to P37
: Port 3
TOOLD0, TOOLD1
: Data Input/Output for Tool
P60, P61
: Port 6
TxD6
: Transmit Data
P121, P122, P125
: Port 12
VDD
: Power Supply
REGC
: Regulator Capacitance
VSS
: Ground
RESET
: Reset
X1, X2
: Crystal Oscillator
(Main System Clock)
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78K0/Kx2-L
CHAPTER 1 OUTLINE
(2) 25-pin plastic FLGA (3x3) (2/2)
Note μPD78F0565, 78F0566, 78F0567 (products with operational amplifier) only
Cautions 1. VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to
a stabilized GND (= 0 V).
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 to ANI6/P26 are set
in the analog input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
5. Set P30 and P01 to output mode (PM30 = PM01 = 0) by using software after release of reset.
Remark
Functions in parentheses ( ) in the figure above can be assigned by setting the port alternate switch control
register (MUXSEL).
P32/INTP3/TOOLD1
P31/INTP2/TOOLC1
P01/TI010/TO00
ANI3/P23
ANI2/P22/AMP0+Note
ANI1/P21/AMP0OUTNote/PGAINNote
AVREF
ANI0/P20/AMP0−Note
(3) 32-pin plastic WQFN (5x5) (1/2)
32 31 30 29 28 27 26 25
AVSS
1
24
P33
IC0
2
23
P34/INTP4(/TOH1)
ANI7/P27
3
22
P35/SCK11
ANI8/P70
4
21
P36/SI11
ANI9/P71
5
20
P37/SO11
ANI10/P72
6
19
VDD
ANI6/P26
7
18
IC0
ANI5/P25
8
17
VSS
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
REGC
P121/X1(/TI000)(/INTP0)/TOOLC0
P122/X2/EXCLK/TOOLD0
RESET(/TI000)(/INTP0)/P125
P02/SSI11/INTP5
P61/RxD6/SDAA0
ANI4/P24
9 10 11 12 13 14 15 16
P60/TxD6/SCLA0
9
78K0/Kx2-L
CHAPTER 1 OUTLINE
(3) 32-pin plastic WQFN (5x5) (2/2)
AMP0-
Note
, AMP0+
Note
: Amplifier Input
RESET
: Amplifier Output
RxD6
: Receive Data
: Programmable Gain
SCK11
: Serial Clock Input/Output
Amplifier Input
SCLA0
: Serial Clock Input/Output
ANI0 to ANI10
: Analog Input
SDAA0
: Serial Data Input/Output
AVREF
: Analog Reference Voltage
SI11
: Serial Data Input
AVSS
: Analog Ground
SO11
: Serial Data Output
: External Clock Input
SSI11
: Serial Interface Chip
AMP0OUT
Note
Note
PGAIN
EXCLK
(Main System Clock)
IC0
: Internally Connected
: Reset
Select Input
TI000, TI010
: Timer Input
INTP0, INTP2 to INTP5 : External Interrupt Input
TO00, TOH1
: Timer Output
P01, P02
: Port 0
TOOLC0, TOOLC1
: Clock Input for Tool
P20 to P27
: Port 2
TOOLD0, TOOLD1
: Data Input/Output for Tool
P31 to P37
: Port 3
TxD6
: Transmit Data
P60, P61
: Port 6
VDD
: Power Supply
P70 to P72
: Port 7
VSS
: Ground
P121, P122, P125
: Port 12
X1, X2
: Crystal Oscillator
REGC
: Regulator Capacitance
(Main System Clock)
Note μPD78F0565, 78F0566, 78F0567 (products with operational amplifier) only
Cautions 1. Connect directly IC0 (Internally Connected) to VSS .
2. VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to
a stabilized GND (= 0 V).
3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
4. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, ANI3/P23 to ANI7/P27, and
ANI8/P70 to ANI10/P72 are set in the analog input mode after release of reset.
5. RESET/P125 immediately after release of reset is set in the external reset input.
6. Set P30 to output mode (PM30 = 0) by using software after release of reset.
Remark
Functions in parentheses ( ) in the figure above can be assigned by setting the port alternate switch control
register (MUXSEL).
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
10
78K0/Kx2-L
CHAPTER 1 OUTLINE
1.3.3 78K0/KB2-L
• 30-pin plastic SSOP (7.62 mm (300))
ANI1/P21/AMP0OUTNote/PGAINNote
1
30
ANI2/P22/AMP0+Note
Note
2
29
ANI3/P23
P01/TI010/TO00
3
28
AVSS
P00/TI000
4
27
AVREF
P120/INTP0/EXLVI
5
26
P10/SCK10/ANI8/AMP1-Note
RESET/P125
6
25
P11/SI10/ANI9/AMP1OUTNote
IC
7
24
P12/SO10/ANI10/AMP1+Note
P122/X2/EXCLK/TOOLD0
8
23
P13/TxD6
P121/X1/TOOLC0
9
22
P14/RxD6
REGC
10
21
P15/TOH0
VSS
11
20
P16/TOH1/INTP5
VDD
12
19
P17/TI50/TO50
P60/SCLA0/INTP11
13
18
P30/INTP1
P61/SDAA0/INTP10
14
17
P31/INTP2/TOOLC1
P33/TI51/TO51/INTP4
15
16
P32/INTP3/TOOLD1
ANI0/P20/AMP0-
Note
AMP0-
Note
AMP1-
, AMP0+
Note
, AMP1+
Note
AMP0OUT
Note
,
AMP1OUT
Note
:
Note
PGAIN
,
:
:
P20 to P23 :
Port 2
P30 to P33 :
Port 3
P60, P61 :
Port 6
Amplifier Output
P120 to P122, P125 :
Port 12
Programmable Gain
REGC :
Regulator Capacitance
Amplifier Input
RESET :
Reset
RxD6 :
Receive Data
Amplifier Input
ANI0 to ANI3,
ANI8 to ANI10 :
Analog Input
SCLA0, SCK10 :
Serial Clock Input/Output
AVREF :
Analog Reference
SDAA0 :
Serial Data Input/Output
Voltage
SI10 :
Serial Data Input
AVSS :
Analog Ground
SO10 :
Serial Data Output
EXCLK :
External Clock Input
TI000, TI010, TI50, TI51 :
Timer Input
(Main System Clock)
TO00, TO50, TO51,
External potential Input
TOH0, TOH1 :
Timer Output
for Low-voltage detector
TOOLC0, TOOLC1 :
Clock Input for Tool
EXLVI :
IC :
Internally Connected
INTP0 to INTP5,
TOOLD0, TOOLD1 :
Data Input/Output for Tool
TxD6 :
Transmit Data
INTP10, INTP11 :
External Interrupt Input
VDD :
Power Supply
P00, P01 :
Port 0
VSS :
Ground
P10 to P17 :
Port 1
X1, X2 :
Crystal Oscillator
(Main System Clock)
Note
μPD78F0576, 78F0577, 78F0578 (products with operational amplifier) only
Cautions 1. Leave the IC (Internally Connected) pin open.
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 are set in the
analog input mode, P10/ANI8/AMP1-/SCK10, P11/ANI9/AMP1OUT/SI10, and
P12/ANI10/AMP1+/SO10 are set in the digital input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
11
78K0/Kx2-L
CHAPTER 1 OUTLINE
1.3.4 78K0/KC2-L
AVSS
ANI6/P26
ANI5/P25
ANI4/P24
ANI3/P23
ANI2/P22/AMP0+Note
ANI1/P21/AMP0OUTNote/PGAINNote
ANI0/P20/AMP0−Note
P01/TI010/TO00
P00/TI000
(1) 40-pin plastic WQFN (6x6) (1/2)
40 39 38 37 36 35 34 33 32 31
P120/INTP0/EXLVI
1
30
AVREF
RESET/P125
2
29
P10/SCK10/ANI8/AMP1−Note
P124/XT2/EXCLKS
3
28
P11/SI10/ANI9/AMP1OUTNote
P123/XT1
4
27
P12/SO10/ANI10/AMP1+Note
IC
5
26
P13/TxD6
P122/X2/EXCLK/TOOLD0
6
25
P14/RxD6
P121/X1/TOOLC0
7
24
P15/TOH0
REGC
8
23
P16/TOH1/INTP5
VSS
9
22
P17/TI50/TO50
VDD
10
21
P30/INTP1
Note
P31/INTP2/TOOLC1
P70/KR0
P32/INTP3/TOOLD1
P71/KR1
P72/KR2
P73/KR3
P33/TI51/TO51/INTP4
P62/SO11/INTP9
P61/SDAA0/SI11/INTP10
11 12 13 14 15 16 17 18 19 20
P60/SCLA0/SCK11/INTP11
μPD78F0586, 78F0587, 78F0588 (products with operational amplifier) only
Cautions 1. Leave the IC (Internally Connected) pin open.
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 to ANI6/P26 are set
in the analog input mode, P10/ANI8/AMP1-/SCK10, P11/ANI9/AMP1OUT/SI10, and
P12/ANI10/AMP1+/SO10 are set in the digital input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
5. Set P40, P41, and P63 to output mode (PM40 = PM41 = PM63 = 0) by using software after release
of reset.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
12
78K0/Kx2-L
CHAPTER 1 OUTLINE
(1) 40-pin plastic WQFN (6x6) (2/2)
AMP0-
Note
Note
Note
Note
, AMP0+
, AMP1+
AMP1-
AMP0OUT
Note
AMP1OUT
Note
,
: Amplifier Input
,
,
Note
PGAIN
: Amplifier Output
: Programmable Gain
Amplifier Input
ANI0 to ANI6, ANI8 to ANI10 : Analog Input
REGC
: Regulator Capacitance
RESET
: Reset
RxD6
: Receive Data
SCLA0, SCK10, SCK11
: Serial Clock Input/Output
SDAA0
: Serial Data Input/Output
SI10, SI11
: Serial Data Input
SO10, SO11
: Serial Data Output
TI000, TI010, TI50, TI51
: Timer Input
TO00, TO50, TO51,
: Timer Output
AVREF
: Analog Reference
AVSS
: Analog Ground
TOH0, TOH1
EXCLK
: External Clock Input
TOOLC0, TOOLC1
: Clock Input for Tool
(Main System Clock)
TOOLD0, TOOLD1
: Data Input/Output for Tool
Voltage
EXCLKS
: External Clock Input
(Subsystem Clock)
EXLVI
: External potential Input
for Low-voltage detector
IC
: Internally Connected
INTP0 to INTP5,
: External Interrupt
INTP9 to INTP11
KR0 to KR3
: Transmit Data
: Power Supply
VSS
: Ground
X1, X2
: Crystal Oscillator
XT1, XT2
: Crystal Oscillator
(Main System Clock)
Input
(Subsystem Clock)
: Key Return
P00, P01
: Port 0
P10 to P17
: Port 1
P20 to P26
: Port 2
P30 to P33
: Port 3
P60 to P62
: Port 6
P70 to P73
: Port 7
P120 to P125
: Port 12
Note
TxD6
VDD
μPD78F0586, 78F0587, 78F0588 (products with operational amplifier) only
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
13
78K0/Kx2-L
CHAPTER 1 OUTLINE
ANI7/P27
ANI6/P26
ANI5/P25
ANI4/P24
ANI3/P23
ANI2/P22/AMP0+Note
ANI1/P21/AMP0OUTNote/PGAINNote
ANI0/P20/AMP0-Note
P01/TI010/TO00
P00/TI000
P120/INTP0/EXLVI(/SO11)
(2) 44-pin plastic LQFP (10x10) (1/2)
44 43 42 41 40 39 38 37 36 35 34
P41/RTC1HZ(/SI11)
1
33
AVSS
P40/RTCCL/RTCDIV(/SCK11)
2
32
AVREF
RESET/P125
3
31
P10/SCK10/ANI8/AMP1-Note
P124/XT2/EXCLKS
4
30
P11/SI10/ANI9/AMP1OUTNote
P123/XT1
5
29
P12/SO10/ANI10/AMP1+Note
IC
6
28
P13/TxD6
P122/X2/EXCLK/TOOLD0
7
27
P14/RxD6
P121/X1/TOOLC0
8
26
P15/TOH0
REGC
9
25
P16/TOH1/INTP5
VSS
10
24
P17/TI50/TO50
VDD
11
23
P30/INTP1
Note
P31/INTP2/TOOLC1
P32/INTP3/TOOLD1
P70/KR0
P71/KR1
P72/KR2
P73/KR3
P33/TI51/TO51/INTP4
P63/INTP8
P62/SO11/INTP9
P61/SDAA0/SI11/INTP10
P60/SCLA0/SCK11/INTP11
12 13 14 15 16 17 18 19 20 21 22
μPD78F0586, 78F0587, 78F0588 (products with operational amplifier) only
Cautions 1. Leave the IC (Internally Connected) pin open.
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 to ANI7/P27 are set
in the analog input mode, P10/ANI8/AMP1-/SCK10, P11/ANI9/AMP1OUT/SI10, and
P12/ANI10/AMP1+/SO10 are set in the digital input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
Remark
Functions in parentheses ( ) in the figure above can be assigned by setting the port alternate switch control
register (MUXSEL).
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
14
78K0/Kx2-L
CHAPTER 1 OUTLINE
(2) 44-pin plastic LQFP (10x10) (2/2)
Note
AMP0-
Note
AMP1-
, AMP0+
Note
, AMP1+
Note
AMP0OUT
Note
AMP1OUT
Note
Note
PGAIN
,
:
Amplifier Input
,
:
:
REGC:
Regulator Capacitance
RESET :
Reset
RTC1HZ :
Real-time Counter
Amplifier Output
Correction Clock (1 Hz)
Programmable Gain
Output
Amplifier Input
RTCCL :
Real-time Counter
ANI0 to ANI10 :
Analog Input
Clock (32 kHz Original
AVREF :
Analog Reference
Oscillation) Output
Voltage
AVSS :
Analog Ground
EXCLK :
External Clock Input
EXCLKS :
EXLVI :
IC :
RTCDIV :
Real-time Counter
Clock (32 kHz Divided
Frequency) Output
(Main System Clock)
RxD6 :
Receive Data
External Clock Input
SCLA0, SCK10, SCK11 :
Serial Clock Input/Output
(Subsystem Clock)
SDAA0 :
Serial Data Input/Output
External potential Input
SI10, SI11 :
Serial Data Input
for Low-voltage detector
SO10, SO11 :
Serial Data Output
Internally Connected
TI000, TI010, TI50, TI51 :
Timer Input
INTP0 to INTP5,
TO00, TO50, TO51,
INTP8 to INTP11 :
External Interrupt Input
TOH0, TOH1 :
Timer Output
KR0 to KR3 :
Key Return
TOOLC0, TOOLC1 :
Clock Input for Tool
P00, P01 :
Port 0
TOOLD0, TOOLD1 :
Data Input/Output for Tool
P10 to P17 :
Port 1
TxD6 :
Transmit Data
P20 to P27 :
Port 2
VDD :
Power Supply
P30 to P33 :
Port 3
VSS :
Ground
P40, P41 :
Port 4
X1, X2 :
Crystal Oscillator
P60 to P63 :
Port 6
P70 to P73 :
Port 7
P120 to P125 :
Port 12
Note
(Main System Clock)
XT1, XT2 :
Crystal Oscillator
(Subsystem Clock)
μPD78F0586, 78F0587, 78F0588 (products with operational amplifier) only
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
15
78K0/Kx2-L
CHAPTER 1 OUTLINE
VDD
VSS
REGC
P121/X1/TOOLC0
P122/X2/EXCLK/TOOLD0
IC
P123/XT1
P124/XT2/EXCLKS
RESET/P125
P40/RTCCL/RTCDIV(/SCK11)
P41/RTC1HZ(/SI11)
P120/INTP0/EXLVI(/SO11)
(3) 48-pin plastic LQFP (fine pitch) (7x7) (1/2)
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
P42/PCL/SSI11/INTP6
P00/TI000
P01/TI010/TO00
P02/INTP7
ANI0/P20/AMP0-Note
ANI1/P21/AMP0OUTNote/PGAINNote
ANI2/P22/AMP0+Note
ANI3/P23
ANI4/P24
ANI5/P25
ANI6/P26
ANI7/P27
P31/INTP2/TOOLC1
P30/INTP1
P17/TI50/TO50
P16/TOH1/INTP5
P15/TOH0
P14/RxD6
P13/TxD6
P12/SO10/ANI10/AMP1+Note
P11/SI10/ANI9/AMP1OUTNote
P10/SCK10/ANI8/AMP1-Note
AVREF
AVSS
P60/SCLA0/SCK11/INTP11
P61/SDAA0/SI11/INTP10
P62/SO11/INTP9
P63/INTP8
P33/TI51/TO51/INTP4
P75/KR5
P74/KR4
P73/KR3
P72/KR2
P71/KR1
P70/KR0
P32/INTP3/TOOLD1
Note
μPD78F0586, 78F0587, 78F0588 (products with operational amplifier) only
Cautions 1. Leave the IC (Internally Connected) pin open.
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 to ANI7/P27 are set
in the analog input mode, P10/ANI8/AMP1-/SCK10, P11/ANI9/AMP1OUT/SI10, and
P12/ANI10/AMP1+/SO10 are set in the digital input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
Remark
Functions in parentheses ( ) can be assigned by setting the port alternate switch control register (MUXSEL).
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
16
78K0/Kx2-L
CHAPTER 1 OUTLINE
(3) 48-pin plastic LQFP (fine pitch) (7x7) (2/2)
Note
AMP0-
Note
AMP1-
, AMP0+
Note
, AMP1+
Note
AMP0OUT
Note
AMP1OUT
Note
Note
PGAIN
,
:
,
REGC :
Regulator Capacitance
Amplifier Input
RESET :
Reset
Amplifier Output
RTC1HZ :
Real-time Counter
:
:
Correction Clock (1 Hz)
Programmable Gain
Amplifier Input
Output
RTCCL :
Real-time Counter
ANI0-ANI10 :
Analog Input
Clock (32 kHz Original
AVREF :
Analog Reference
Oscillation) Output
Voltage
AVSS :
Analog Ground
EXCLK :
External Clock Input
RTCDIV :
Real-time Counter
Clock (32 kHz Divided
Frequency) Output
(Main System Clock)
RxD6 :
Receive Data
External Clock Input
SCLA0, SCK10, SCK11 :
Serial Clock Input/Output
(Subsystem Clock)
SDAA0 :
Serial Data Input/Output
External potential Input
SI10, SI11 :
Serial Data Input
for Low-voltage detector
SO10, SO11 :
Serial Data Output
IC :
Internally Connected
SSI11 :
Serial Interface Chip
INTP0 to INTP11 :
External Interrupt
Input
TI000, TI010, TI50, TI51 :
KR0 to KR5 :
Key Return
TO00, TO50, TO51,
P00 to P02 :
Port 0
TOH0, TOH1 :
Timer Output
P10 to P17 :
Port 1
TOOLC0, TOOLC1 :
Clock Input for Tool
EXCLKS :
EXLVI :
Select Input
Timer Input
P20 to P27 :
Port 2
TOOLD0, TOOLD1 :
Data Input/Output for Tool
P30 to P33 :
Port 3
TxD6 :
Transmit Data
P40 to P42 :
Port 4
VDD :
Power Supply
P60 to P63 :
Port 6
VSS :
Ground
P70 to P75 :
Port 7
X1, X2 :
P120 to P125 :
Port 12
PCL :
Programmble Clock
XT1, XT2 :
Output
Note
Crystal Oscillator
(Main System Clock)
Crystal Oscillator
(Subsystem Clock)
μPD78F0586, 78F0587, 78F0588 (products with operational amplifier) only
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
17
78K0/Kx2-L
CHAPTER 1 OUTLINE
1.4 Block Diagram
1.4.1 78K0/KY2-L
TO00/TI010/P01
TI000/P00
RxD6/P61
16-bit TIMER/
EVENT COUNTER 00
TI51/P30
PORT 0
2
P00, P01
PORT 2
4
P20 to P23
8-bit TIMER 51
PORT 3
TOH1/P30
8-bit TIMER H1
INTERNAL
LOW-SPEED
OSCILLATOR
WATCHDOG TIMER
RxD6/P61
TxD6/P60
SERIAL
INTERFACE UART6
LINSEL
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA
AVREF
78K/0
CPU
CORE
FLASH
MEMORY
PORT 6
2
P60, P61
PORT 12
3
P121, P122, P125
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
ON-CHIP DEBUG
INTERNAL
HIGH-SPEED
RAM
4
SYSTEM
CONTROL
INTERNAL
HIGH-SPEED
OSCILLATOR
AMP0OUTNote/PGAINNote/P21
AMP0+Note/P22
Note
AMP0-
/P20
RxD6/P61
INTP0/P00
INTP1/P30
POC/LVI
CONTROL
RESET CONTROL
A/D CONVERTER
ANI0/P20 to ANI3/P23
P30
OPERATIONAL
AMPLIFIER 0Note
VOLTAGE
REGULATOR
TOOLC0/X1
TOOLD0/X2
RESET/P125
X1/P121
X2/EXCLK/P122
REGC
INTERRUPT
CONTROL
VDD
VSS
Note μPD78F0555, 78F0556, 78F0557 (products with operational amplifier) only
Cautions 1. VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to
a stabilized GND (= 0 V).
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 are set in the
analog input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
18
78K0/Kx2-L
CHAPTER 1 OUTLINE
1.4.2 78K0/KA2-L
(1) 20-pin products
TO00/TI010/P01
TI000/P00
RxD6/P61
16-bit TIMER/
EVENT COUNTER 00
PORT 0
2
P00, P01
PORT 2
6
P20 to P25
PORT 3
3
P30 to P32
PORT 6
2
P60, P61
PORT 12
3
P121, P122, P125
8-bit TIMER 51
TI51/P30
TOH1/P30
8-bit TIMER H1
INTERNAL
LOW-SPEED
OSCILLATOR
WATCHDOG TIMER
RxD6/P61
TxD6/P60
SERIAL
INTERFACE UART6
LINSEL
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA
AVREF
78K/0
CPU
CORE
FLASH
MEMORY
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
POC/LVI
CONTROL
RESET CONTROL
ON-CHIP DEBUG
INTERNAL
HIGH-SPEED
RAM
SYSTEM
CONTROL
A/D CONVERTER
ANI0/P20 to ANI5/P25
6
INTERNAL
HIGH-SPEED
OSCILLATOR
AMP0OUTNote/PGAINNote/P21
RESET/P125
X1/P121
X2/EXCLK/P122
OPERATIONAL
AMPLIFIER 0Note
AMP0+Note/P22
AMP0-Note/P20
VOLTAGE
REGULATOR
RxD6/P61
INTP0/P00
INTP1/P30, INTP2/P31, INTP3/P32
TOOLC0/X1, TOOLC1/P31
TOOLD0/X2, TOOLD1/P32
3
REGC
INTERRUPT
CONTROL
VDD
VSS
Note μPD78F0565, 78F0566, 78F0567 (products with operational amplifier) only
Cautions 1. VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to
a stabilized GND (= 0 V).
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 to ANI5/P25 are set
in the analog input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
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78K0/Kx2-L
CHAPTER 1 OUTLINE
(2) 25-pin products
TI000/P00
16-bit TIMER/
EVENT COUNTER 00
(TI000)/P121
PORT 0
2
P00, P02
PORT 2
7
P20-P26
PORT 3
7
P31-P37
PORT 6
2
P60, P61
PORT 12
3
P121, P122, P125
RxD6/P61
8-bit TIMER/
EVENT COUNTER 51
(TI51)/P00
(TI51)/P34
(TOH1)/P00
(TOH1)/P34
8-bit TIMER H1
INTERNAL
LOW-SPEED
OSCILLATOR
WATCHDOG TIMER
RxD6/P61
TxD6/P60
SERIAL
INTERFACE UART6
LINSEL
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA
SCK11/P35
SI11/P36
SO11/P37
SERIAL
INTERFACE CSI11
78K/0
CPU
CORE
FLASH
MEMORY
RxD6/P61
INTP0/P00
(INTP0)/P121
INTERRUPT
CONTROL
4
INTERNAL
HIGH-SPEED
RAM
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
INTP2/P31, INTP3/P32,
INTP4/P34, INTP5/P02
POC/LVI
CONTROL
RESET CONTROL
ON-CHIP DEBUG
AVREF
TOOLC0/X1, TOOLC1/P31
TOOLD0/X2, TOOLD1/P32
A/D CONVERTER
ANI0/P20-ANI6/P26
7
SYSTEM
CONTROL
AMP0OUTNote/PGAINNote/P21
AMP0+Note/P22
AMP0-Note/P20
REGC
OPERATIONAL
AMPLIFIER 0Note
INTERNAL
HIGH-SPEED
OSCILLATOR
RESET/P125
X1/P121
X2/EXCLK/P122
VOLTAGE
REGULATOR
VDD
VSS
Note μPD78F0565, 78F0566, 78F0567 (products with operational amplifier) only
Cautions 1. VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to
a stabilized GND (= 0 V).
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 to ANI6/P26 are set
in the analog input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
5. Set P30 and P01 to output mode (PM30 = PM01 = 0) by using software after release of reset.
Remark
Functions in parentheses ( ) in the figure above can be assigned by setting the port alternate switch control
register (MUXSEL).
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78K0/Kx2-L
CHAPTER 1 OUTLINE
(3) 32-pin products
TO00/TI010/P01
(TI000)/P121
(TI000)/P125
RxD6/P61
16-bit TIMER/
EVENT COUNTER 00
PORT 0
2
P01, P02
PORT 2
8
P20-P27
PORT 3
7
P31-P37
PORT 6
2
P60, P61
PORT 7
3
P70-P72
PORT 12
3
P121, P122, P125
8-bit TIMER/
EVENT COUNTER 51
(TOH1)/P34
8-bit TIMER H1
INTERNAL
LOW-SPEED
OSCILLATOR
WATCHDOG TIMER
RxD6/P61
TxD6/P60
SERIAL
INTERFACE UART6
LINSEL
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA
SCK11/P35
SI11/P36
SO11/P37
SERIAL
INTERFACE CSI11
AVREF
AVSS
ANI0/P20-ANI7/P27,
11
ANI8/P70-ANI10/P72
78K/0
CPU
CORE
FLASH
MEMORY
AMP0-Note/P20
REGC
INTP2/P31, INTP3/P32,
INTP4/P34, INTP5/P02
4
INTERNAL
HIGH-SPEED
RAM
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
POC/LVI
CONTROL
RESET CONTROL
ON-CHIP DEBUG
TOOLC0/X1, TOOLC1/P31
TOOLD0/X2, TOOLD1/P32
A/D CONVERTER
SYSTEM
CONTROL
AMP0OUTNote/PGAINNote/P21
AMP0+Note/P22
RxD6/P61
(INTP0)/P121
(INTP0)/P125
INTERRUPT
CONTROL
OPERATIONAL
AMPLIFIER 0Note
INTERNAL
HIGH-SPEED
OSCILLATOR
RESET/P125
X1/P121
X2/EXCLK/P122
VOLTAGE
REGULATOR
VDD
VSS
IC0
Note μPD78F0565, 78F0566, 78F0567 (products with operational amplifier) only
Cautions 1. Connect directly IC0 (Internally Connected) to VSS .
2. VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to
a stabilized GND (= 0 V).
3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
4. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, ANI3/P23 to ANI7/P27, and
ANI8/P70 to ANI10/P72 are set in the analog input mode after release of reset.
5. RESET/P125 immediately after release of reset is set in the external reset input.
6. Set P30 to output mode (PM30 = 0) by using software after release of reset.
Remark
Functions in parentheses ( ) in the figure above can be assigned by setting the port alternate switch control
register (MUXSEL).
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78K0/Kx2-L
CHAPTER 1 OUTLINE
1.4.3 78K0/KB2-L
TO00/TI010/P01
TI000/P00
RxD6/P14
16-bit TIMER/
EVENT COUNTER 00
TI50/TO50/P17
8-bit TIMER/
EVENT COUNTER 50
TI51/TO51/P33
8-bit TIMER/
EVENT COUNTER 51
TOH0/P15
8-bit TIMER H0
78K/0
CPU
CORE
TOH1/P16
FLASH
MEMORY
PORT 0
2
P00, P01
PORT 1
8
P10 to P17
PORT 2
4
P20 to P23
PORT 3
4
P30 to P33
PORT 6
2
P60, P61
PORT 12
WATCHDOG TIMER
RxD6/P14
TxD6/P13
SERIAL
INTERFACE UART6
LINSEL
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA
SCK10/P10
SI10/P11
SO10/P12
SERIAL
INTERFACE CSI10
INTERNAL
HIGH-SPEED
RAM
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
POC/LVI
CONTROL
EXLVI/P120
RESET CONTROL
ON-CHIP DEBUG
SYSTEM
CONTROL
HIGH-SPEED
OSCILLATOR
TOOLC0/X1, TOOLC1/P31
TOOLD0/X2, TOOLD1/P32
RESET/P125
X1/P121
X2/EXCLK/P122
A/D CONVERTER
7
VOLTAGE
REGULATOR
AMP0OUTNote/PGAINNote/P21
AMP0+
7
INTP0/P120
INTP1/P30 to INTP4/P33,
INTP5/P16, INTP10/P61,
INTP11/P60
RxD6/P14
INTERRUPT
CONTROL
INTERNAL
Note
P121, P122, P125
8-bit TIMER H1
INTERNAL
LOW-SPEED
OSCILLATOR
AVREF
AVSS
ANI0/P20 to ANI3/P23,
ANI8/P10 to ANI10/P12
P120
3
REGC
OPERATIONAL
AMPLIFIER 0Note
/P22
AMP0-Note/P20
AMP1OUTNote/P11
OPERATIONAL
AMPLIFIER 1Note
AMP1+Note/P12
AMP1-Note/P10
RxD6/P14
INTP0/P120
INTP1/P30 to INTP4/P33,
INTP5/P16, INTP10/P61,
INTP11/P60
Note
INTERRUPT
CONTROL
7
VDD
VSS
IC
μPD78F0576, 78F0577, 78F0578 (products with operational amplifier) only
Cautions 1. Leave the IC (Internally Connected) pin open.
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 are set in the
analog input mode, P10/ANI8/AMP1-/SCK10, P11/ANI9/AMP1OUT/SI10, and
P12/ANI10/AMP1+/SO10 are set in the digital input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
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Sep 27, 2010
22
78K0/Kx2-L
CHAPTER 1 OUTLINE
1.4.4 78K0/KC2-L
TO00/TI010/P01
TI000/P00
RxD6/P14
16-bit TIMER/
EVENT COUNTER 00
TI50/TO50/P17
8-bit TIMER/
EVENT COUNTER 50
TI51/TO51/P33
8-bit TIMER/
EVENT COUNTER 51
TOH0/P15
FLASH
MEMORY
WATCHDOG TIMER
RTCCLNote 3/RTCDIVNote 3/P40Note 3
RTC1HZNote 3/P41Note 3
SDAA0/P61
SCLA0/P60
P00, P01, P02Note 1
PORT 1
8
P10 to P17
PORT 2
8
P20 to P26, P27Note 3
PORT 3
4
P30 to P33
3
P40, P41, P42Note 1
PORT 6
4
P60 to P62, P63Note 3
PORT 7
6
P70 to P73, P74Note 1, P75Note 1
3
8-bit TIMER H1
INTERNAL
LOW-SPEED
OSCILLATOR
RxD6/P14
TxD6/P13
3
PORT 4
8-bit TIMER H0
78K/0
CPU
CORE
TOH1/P16
PORT 0
PORT 12
SCK11/P60
(SCK11/) P40
SI11/P61
(SI11/) P41
SO11/P62
(SO11/) P120
INTERRUPT
CONTROL
REALTIME
COUNTER
11
CLOCK OUTPUT
CONTROLNote 1
SERIAL
INTERFACE UART6
LINSEL
SERIAL
INTERFACE IICA
SERIAL
INTERFACE CSI10
INTP0/P120
INTP1/P30 to INTP4/P33,
INTP5/P16,
INTP6Note 1/P42Note 1, INTP7Note 1/P02Note 1,
INTP8/P63Note 3 to INTP11/P60
PCLNote 1/P42Note 1
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
POC/LVI
CONTROL
6
EXLVI/P120
KR0 to KR3, KR4Note 1, KR5Note 1
RESET CONTROL
ON-CHIP DEBUG
TOOLC0/X1, TOOLC1/P31
TOOLD0/X2, TOOLD1/P32
SERIAL
INTERFACE CSI11
SYSTEM
CONTROL
SSI11Note 1/P42Note 1
AVREF
AVSS
ANI0/P20 to ANI7/P27Note 3, 11
ANI8/P10 to ANI10/P12
P121 to P125
RxD6/P14
INTERNAL
HIGH-SPEED
RAM
KEY RETURN
SCK10/P10
SI10/P11
SO10/P12
P120
5
INTERNAL
A/D CONVERTER
HIGH-SPEED
OSCILLATOR
RESET/P125
X1/P121
X2/EXCLK/P122
XT1/P123
XT2/EXCLKS/P124
AMP0OUTNote 2/PGAINNote 2/P21
AMP0+Note 2/P22
AMP0-Note 2/P20
OPERATIONAL
AMPLIFIER 0Note 2
VOLTAGE
REGULATOR
REGC
AMP1OUTNote 2/P11
AMP1+Note 2/P12
AMP1-Note 2/P10
OPERATIONAL
AMPLIFIER 1Note 2
VDD
Notes 1.
VSS
IC
48-pin products only
2.
μPD78F0586, 78F0587, 78F0588 (products with operational amplifier) only
3.
44-pin and 48-pin products only
Cautions 1. Leave the IC (Internally Connected) pin open.
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 to ANI7/P27 are set
in the analog input mode, P10/ANI8/AMP1-/SCK10, P11/ANI9/AMP1OUT/SI10, and
P12/ANI10/AMP1+/SO10 are set in the digital input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.
5. For 40-pin products, set P40, P41, and P63 to output mode (PM40 = PM41 = PM63 = 0) by using
software after release of reset.
Remark
Functions in parentheses ( ) in the figure above can be assigned by setting the port alternate switch control
register (MUXSEL).
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Sep 27, 2010
23
78K0/Kx2-L
CHAPTER 1 OUTLINE
1.5 Outline of Functions
(1/2)
Item
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
(μPD78F055x)
(μPD78F056x)
(μPD78F057x)
(μPD78F058x)
16 Pins
Internal Flash memory
memory (self-programming
supported )
High-Speed RAM
Clock
Main
Memory space
20
Pins
25
Pins
32
Pins
30 Pins
4 KB to 16 KB
8 KB to 32 KB
384 bytes to 768 bytes
512 bytes to 1 KB
40
Pins
44
Pins
64 KB
High-speed system
(crystal/ceramic
oscillation, external
clock input)
1 to 10 MHz: VDD = 2.7 to 5.5 V/1 to 5 MHz: VDD = 1.8 to 5.5 V
Internal highspeed oscillation
4 MHz ± 2 % (TA = –20 to +70°C), or 8 MHz ± 3 % (TA = –40 to +85°C): VDD = 1.8 to 5.5 V
Subsystem (crystal
oscillation, external
clock input)
Internal low-speed
oscillation
48
Pins
32.768 kHz (TYP.):
–
VDD = 1.8 to 5.5 V
30 kHz ± 10 %: VDD = 2.7 to 5.5 V, 30 kHz ± 15 %: VDD = 1.8 to 5.5 V
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Instruction set
• 8-bit operation, 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
Timer
I/O ports (total)
12
16
21
25
24
34
38
42
CMOS I/O
9
13
18
22
21
29
33
37
CMOS input
3
3
3
3
3
5
5
5
16 bits (TM0)
1 ch (PPG output: 1, capture input: 2)
8 bits (TM5)
1 ch
2 ch (PWM output: 2)
8 bits (TMH)
1 ch (PWM output: 1)
2 ch (PWM output: 2)
Watchdog (WDT)
1 ch
1 ch
1 ch (RTC
(RTC
output: 2)
Real-time counter
–
output
: None)
Clock output
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Sep 27, 2010
–
–
–
1
24
78K0/Kx2-L
CHAPTER 1 OUTLINE
(2/2)
Item
Serial
UART
interface
IICA
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
(μPD78F055x)
(μPD78F056x)
(μPD78F057x)
(μPD78F058x)
16 Pins
20
Pins
–
–
32
Pins
30 Pins
40
Pins
44
Pins
48
Pins
1 ch
1 ch
CSI
10-bit A/D converter
25
Pins
4 ch
6 ch
Note
1 ch (CSI11
7 ch
)
11 ch
Note
1 ch (CSI10)
2 ch (CSI10, CSI11
)
7 ch
10 ch
11 ch
11 ch
11
13
4
6
(AVREF = 1.8 to 5.5 V)
Operational amplifier
(Products with operational
amplifier)
1 ch (VDD = 2.2 to 5.5 v)
Vectored interrupt External
Internal sources
Internal
2
4
5
5
8
10
10
10
11
11
13
17
2 ch (VDD = 2.2 to 5.5 v)
Key interrupt
Reset
–
4
• Reset using RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-clear
• Internal reset by low-voltage detector
On-chip debug function
Provided
Power supply voltage
VDD = 1.8 to 5.5 V
Operating ambient
temperature
TA = –40 to +85°C
Package
16-pin plastic SSOP
• 20-pin plastic SSOP
30-pin plastic SSOP
(5.72 mm (225))
(7.62 mm (300))
(7.62 mm (300))
• 25-pin plastic FLGA
(3x3)
• 32-pin plastic WQFN
(5x5)
• 40-pin plastic WQFN
(6x6)
• 44-pin plastic LQFP
(10x10)
• 48-pin plastic LQFP
(fine pitch) (7x7)
Note The 78K0/KA2-L (25-pin and 32-pin products) and 78K0/KC2-L (48-pin products) can be controlled by an enabled
signal, when using CSI11 in the slave mode.
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25
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
There are two types of pin I/O buffer power supplies: AVREF and VDD. The relationship between these power supplies
and the pins is shown below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply
Corresponding Pins
Note
AVREF
P20 to P27
VDD
Pins other than P20 to P27
Note
Note
78K0/KY2-L:
P20 to P23
78K0/KA2-L (20 pins):
P20 to P25
78K0/KA2-L (25 pins):
P20 to P26
78K0/KA2-L (32 pins):
P20 to P27, P70 to P72
78K0/KB2-L:
P20 to P23
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
78K0/KC2-L (40 pins):
P20 to P26
78K0/KC2-L (44 pins, 48 pins):
P20 to P27
26
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
2.1.1 78K0/KY2-L
(1) Port functions: 78K0/KY2-L
Function Name
P00
I/O
I/O
Function
Port 0.
After Reset
Input port
2-bit I/O port.
P01
Alternate Function
TI000/INTP0
TO00/TI010
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P20
I/O
Port 2.
Analog input
4-bit I/O port.
P21
ANI0/AMP0-
Note
ANI1/AMP0OUT
Input/output can be specified in 1-bit units.
Note
/
Note
PGAIN
P22
ANI2/AMP0+
P23
ANI3
Note
P30
I/O
Port 3.
1-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TOH1/TI51/INTP1
P60
I/O
Port 6.
Input port
SCLA0/TxD6
2-bit I/O port.
Input/output can be specified in 1-bit units.
P61
SDAA0/RxD6
Input can be set to SMBus input buffer in 1-bit units.
Output can be set to N-ch open-drain output (VDD
tolerance).
Use of an on-chip pull-up resistor can be specified by a
software setting.
P121
P122
P125
Input
Port 12.
Input port
3-bit input-only port.
For only P125, use of an on-chip pull-up resistor can be
specified by a software setting.
X1/TOOLC0
X2/EXCLK/TOOLD0
Reset input
RESET
Note μPD78F0555, 78F0556, and 78F0557 (products with operational amplifier) only
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78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
(2) Non-port functions : 78K0/KY2-L
Function Name
ANI0
I/O
Input
Function
A/D converter analog input
After Reset
Analog input
Alternate Function
P20/AMP0-
Note
Note
P21/AMP0OUT
ANI1
/
Note
PGAIN
ANI2
P22/AMP0+
ANI3
Note
P23
Note
Input
AMP0-
AMP0+
Operational amplifier 0 input
Analog input
Note
AMP0OUT
Note
PGAIN
P20/ANI0
P22/ANI2
Note
Output
Operational amplifier 0 output
Input
PGA (programmable gain amplifier) input
P21/ANI1/PGAIN
Analog input
P21/ANI1/
AMP0OUT
INTP0
Input
External interrupt request input for which the valid edge
Input port
(rising edge, falling edge, or both rising and falling
INTP1
Note
Note
P00/TI000
P30/TOH1/TI51
edges) can be specified
−
REGC
RESET
Input
System reset input
Reset input
Input port
RxD6
Input
Serial data input to UART6
TxD6
Output
Serial data output from UART6
SCLA0
I/O
Clock input/output for I C
2
Input port
Serial data I/O for I C
Input
TI010
External count clock input to 16-bit timer/event counter
00
Capture trigger input to capture registers (CR000,
CR010) of 16-bit timer/event counter 00
−
P125
P61/SDAA0
P60/SCLA0
2
SDAA0
TI000
−
Connecting regulator output (2.0 V/2.4 V) stabilization
capacitance for internal operation.
Connect to VSS via a capacitor (0.47 to 1 μF).
P60/TxD6
P61/RxD6
Input port
Capture trigger input to capture register (CR000) of 16bit timer/event counter 00
P00/INTP0
P01/TO00
TI51
Input
External count clock input to 8-bit timer/event counter 51
Input port
P30/TOH1/INTP1
TO00
Output
16-bit timer/event counter 00 output
Input port
P01/TI010
TOH1
Output
8-bit timer H1 output
Input port
P30/TI51/INTP1
Connecting resonator for main system clock
Input port
P121/TOOLC0
External clock input for main system clock
Input port
−
X1
X2
EXCLK
P122/EXCLK/TOOLD0
Input
−
VDD
AVREF
P122/X2/TOOLD0
−
Positive power supply for pins other than port 2
−
A/D converter reference voltage input and positive power
supply for port 2 and A/D converter
−
VSS
−
Ground potential
TOOLC0
Input
Clock input for flash memory programmer/on-chip
debugger
TOOLD0
I/O
Data I/O for flash memory programmer/on-chip debugger
Input port
−
P121/X1
P122/X2/EXCLK
Note μPD78F0555, 78F0556, and 78F0557 (products with operational amplifier) only
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28
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
2.1.2 78K0/KA2-L
(1) Port functions: 78K0/KA2-L (20 pins)
Function Name
P00
I/O
Function
Port 0.
I/O
After Reset
Input port
2-bit I/O port.
P01
Alternate Function
TI000/INTP0
TO00/TI010
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P20
Port 2.
I/O
Analog input
6-bit I/O port.
P21
ANI0/AMP0-
Note
ANI1/AMP0OUT
Input/output can be specified in 1-bit units.
ANI2/AMP0+
P23
ANI3
P24
ANI4
P25
Note
ANI5
I/O
P31
P32
P60
/
PGAIN
P22
P30
Note
Note
I/O
Port 3.
3-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
Port 6.
Input port
TOH1/TI51/INTP1
INTP2/TOOLC1
INTP3/TOOLD1
SCLA0/TxD6
2-bit I/O port.
Input/output can be specified in 1-bit units.
P61
SDAA0/RxD6
Input can be set to SMBus input buffer in 1-bit units.
Output can be set to N-ch open-drain output (VDD
tolerance).
Use of an on-chip pull-up resistor can be specified by a
software setting.
P121
Input
Port 12.
Input port
3-bit input-only port.
P122
X2/EXCLK/TOOLD0
For only P125, use of an on-chip pull-up resistor can be
P125
X1/TOOLC0
specified by a software setting.
Reset input
RESET
Note μPD78F0565, 78F0566, and 78F0567 (products with operational amplifier) only
(2) Non-port functions : 78K0/KA2-L (20 pins) (1/2)
Function Name
ANI0
I/O
Input
Function
A/D converter analog input
After Reset
Analog input
ANI1
Alternate Function
P20/AMP0-
Note
Note
P21/AMP0OUT
/
Note
PGAIN
ANI2
P22/AMP0+
ANI3
P23
ANI4
P24
ANI5
P25
Note
Note μPD78F0565, 78F0566, and 78F0567 (products with operational amplifier) only
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Sep 27, 2010
29
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
(2) Non-port functions: 78K0/KA2-L (20 pins) (2/2)
Function Name
Note
Input
AMP0-
AMP0+
I/O
Function
Operational amplifier 0 input
After Reset
Analog input
Note
AMP0OUT
Note
PGAIN
Alternate Function
P20/ANI0
P22/ANI2
Note
Output
Operational amplifier 0 output
Input
PGA (programmable gain amplifier) input
P21/ANI1/PGAIN
Analog input
P21/ANI1/
AMP0OUT
INTP0
Input
External interrupt request input for which the valid edge
Input port
(rising edge, falling edge, or both rising and falling
INTP1
P32/TOOLD1
−
REGC
−
Connecting regulator output (2.0 V/2.4 V) stabilization
capacitance for internal operation.
Connect to VSS via a capacitor (0.47 to 1 μF).
Input
System reset input
Reset input
RxD6
Input
Serial data input to UART6
Input port
TxD6
Output
Serial data output from UART6
SCLA0
I/O
Clock input/output for I C
2
Input port
Serial data I/O for I C
Input
TI010
External count clock input to 16-bit timer/event counter
00
Capture trigger input to capture registers (CR000,
CR010) of 16-bit timer/event counter 00
−
P125
P61/SDAA0
P60/SCLA0
2
SDAA0
TI000
P00/TI000
P31/TOOLC1
INTP3
RESET
Note
P30/TOH1/TI51
edges) can be specified
INTP2
Note
P60/TxD6
P61/RxD6
Input port
Capture trigger input to capture register (CR000) of 16bit timer/event counter 00
P00/INTP0
P01/TO00
TI51
Input
External count clock input to 8-bit timer/event counter 51
Input port
P30/TOH1/INTP1
TO00
Output
16-bit timer/event counter 00 output
Input port
P01/TI010
TOH1
Output
8-bit timer H1 output
Input port
P30/TI51/INTP1
Connecting resonator for main system clock
Input port
P121/TOOLC0
External clock input for main system clock
Input port
−
X1
X2
EXCLK
P122/EXCLK/TOOLD0
Input
−
VDD
AVREF
−
Input
TOOLC1
TOOLD0
−
Positive power supply for pins other than port 2
−
A/D converter reference voltage input and positive power
supply for port 2 and A/D converter
VSS
TOOLC0
P122/X2/TOOLD0
I/O
−
Ground potential
Clock input for flash memory programmer/on-chip
debugger
Input port
Data I/O for flash memory programmer/on-chip debugger
TOOLD1
−
P121/X1
P31/INTP2
P122/X2/EXCLK
P32/INTP3
Note μPD78F0565, 78F0566, and 78F0567 (products with operational amplifier) only
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Sep 27, 2010
30
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
(3) Port functions: 78K0/KA2-L (25, 32 pins)
Function Name
P00
P01
Note 1
I/O
I/O
Note 2
Function
Port 0.
After Reset
Input port
Alternate Function
TI000
Note 1
/INTP0
2-bit I/O port.
(/TOH1)
Input/output can be specified in 1-bit units.
TO00
Note 1
Note 1
(/TI51)
Note 2
/TI010
Note 1
Note 2
Use of an on-chip pull-up resistor can be specified by a
P02
SSI11/INTP5
software setting.
I/O
P20
Port 2.
Analog input
8-bit I/O port.
P21
ANI0/AMP0-
Note 3
ANI1/AMP0OUT
Input/output can be specified in 1-bit units.
PGAIN
P22
ANI2/AMP0+
P23
ANI3
P24
ANI4
P25
ANI5
P26
P27
Note 3
/
Note 3
Note 3
ANI6
Note 2
ANI7
I/O
P31
P32
P33
P34
Port 3.
7-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
Note 2
INTP2/TOOLC1
INTP3/TOOLD1
−
INTP4(/TOH1)
(/TI51)
Note 1
P35
SCK11
P36
SI11
P37
SO11
I/O
P60
Port 6.
Input port
2-bit I/O port.
P61
TxD6/SCLA0
RxD6/SDAA0
Input/output can be specified in 1-bit units.
Input can be set to SMBus input buffer in 1-bit units.
Output can be set to N-ch open-drain output (VDD
tolerance).
Use of an on-chip pull-up resistor can be specified by a
software setting.
P70
Note 2
P71
Note 2
P72
I/O
Analog input
3-bit I/O port.
Input/output can be specified in 1-bit units.
Note 2
P121
Port 7.
Input
Port 12.
Input port
ANI9
Note 2
Note 2
X1/TOOLC0
(/TI000)(/INTP0)
For only P125, use of an on-chip pull-up resistor can be
X2/EXCLK/
specified by a software setting.
TOOLD0
Reset input
P125
Note 2
ANI10
3-bit I/O port.
P122
ANI8
RESET(/TI000)
(/INTP0)
Note 2
Note 2
Notes 1. 25-pin products only
2. 32-pin products only
3. μPD78F0565, 78F0566, and 78F0567 (products with operational amplifier) only
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
31
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
(4) Non-port functions: 78K0/KA2-L (25, 32 pins) (1/2)
Function Name
I/O
Input
ANI0
Function
A/D converter analog input
After Reset
Analog input
Alternate Function
P20/AMP0-
Note 3
Note 3
P21/AMP0OUT
ANI1
/
Note 3
PGAIN
ANI2
P22/AMP0+
ANI3 to ANI6
P23 to P26
ANI7
Note 2
P27
Note 2
ANI8
Note 2
P70
Note 2
ANI9
Note 2
P71
Note 2
P72
Note 2
ANI10
Note 2
AMP0-
Note 3
AMP0+
PGAIN
Input
Operational amplifier 0 input
Analog input
Note 3
AMP0OUT
Note 3
Note 3
P20/ANI0
P22/ANI2
Output
Operational amplifier 0 output
Analog input
P21/ANI1/PGAIN
Input
PGA (programmable gain amplifier) input
Analog input
P21/ANI1/
AMP0OUT
INTP0
Note 1
Note 3
Input
(INTP0)
External interrupt request input for which the valid edge
Input port
P00
Note 3
Note 3
Note 1
/TI000
Note 1
Note 1
(rising edge, falling edge, or both rising and falling
(/TOH1)
edges) can be specified
P121/X1/TOOLC0
(/TI51)
Note 1
(/TI000)
(INTP0)
Note 2
RESET/P125
(/TI000)
Note 2
INTP2
P31/TOOLC1
INTP3
P32/TOOLD1
INTP4
P34/I(/TOH1)(/TI51)
INTP5
P02/SSI11
−
REGC
Connecting regulator output (2.0 V/2.4 V) stabilization
capacitance for internal operation.
Connect to VSS via a capacitor (0.47 to 1 μF).
−
−
RESET
Input
System reset input
Reset input
P125(/TI000)
Note 2
(/INTP0)
RxD6
Input
Serial data input to UART6
Input port
P61/SDAA0
TxD6
Output
Serial data output from UART6
SCLA0
I/O
Clock input/output for I C
SDAA0
2
Note 1
Note 2
P60/SCLA0
Input port
2
Serial data I/O for I C
P60/TxD6
P61/RxD6
Notes 1. 25-pin products only
2. 32-pin products only
3. μPD78F0565, 78F0566, and 78F0567 (products with operational amplifier) only
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
32
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
(4) Non-port functions: 78K0/KA2-L (25, 32 pins) (2/2)
Function Name
I/O
Function
After Reset
Alternate Function
SCK11
I/O
Clock input/output for CSI10
SI11
Input
Serial data input to CSI10
P36
SO11
Output
Serial data output from CSI10
P37
Input
Chip select input to CSI11
Input
External count clock input to 16-bit timer/event counter
00
Capture trigger input to capture registers (CR000,
CR010) of 16-bit timer/event counter 00
SSI11
Note 1
TI000
(TI000)
Input port
P35
P02/INTP5
Input port
P00
Note 1
/INTP0
(/TOH1)
Note 1
Note 1
(/TI51)
Note 1
P121/TOOLC0
(/INTP0)
(TI000)
Note 2
RESET/P125
(/INTP0)
TI010
Note 2
(TI50)
Note 1
TO00
Note 2
(TOH1)
Capture trigger input to capture register (CR000) of 16bit timer/event counter 00
P01
/TO00
Note 2
Input
External count clock input to 8-bit timer/event counter 51
Input port
P34/INTP4(/TOH1)
Output
16-bit timer/event counter 00 output
Input port
P01
Output
8-bit timer H1 output
Input port
P34/INTP4(/TI51)
Connecting resonator for main system clock
Input port
P121/TOOLC0
−
X1
X2
Note 2
/TI010
Note 2
Note 1
P122/EXCLK/TOOLD0
EXCLK
Input
−
VDD
AVREF
−
AVSS
External clock input for main system clock
Positive power supply for pins other than port 2
Input port
P122/X2/TOOLD0
−
−
−
−
A/D converter reference voltage input and positive power
supply for port 2 and A/D converter
VSS
Note 2
TOOLC0
Ground potential. For 32-pin products, ground potential
for pins other than port 2
Ground potential for port 2 and A/D converter
Input
Clock input for flash memory programmer/on-chip
debugger
Input port
TOOLD0
P31/INTP2
I/O
Data I/O for flash memory programmer/on-chip debugger
P122/X2/EXCLK
TOOLD1
Note 2
P121/X1
(/TI000) (/INTP0)
TOOLC1
IC0
Note 2
Note 2
P32/INTP3
−
Internally connected. Connect directly to VSS.
−
−
Notes 1. 25-pin products only
2. 32-pin products only
3. μPD78F0565, 78F0566, and 78F0567 (products with operational amplifier) only
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Sep 27, 2010
33
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
2.1.3 78K0/KB2-L
(1) Port functions: 78K0/KB2-L
Function Name
P00
I/O
I/O
Function
Port 0.
After Reset
Input port
2-bit I/O port.
P01
Alternate Function
TI000
TI010/TO00
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P10
I/O
Port 1.
Input port
8-bit I/O port.
P11
/SCK10
Note
ANI10/AMP1+
Use of an on-chip pull-up resistor can be specified by a
P13
Note
ANI9/AMP1OUT /SI10
Input/output can be specified in 1-bit units.
P12
ANI8/AMP1-
RxD6
P15
TOH0
P16
TOH1/INTP5
P17
TI50/TO50
I/O
Port 2.
Analog input
4-bit I/O port.
P21
ANI0/AMP0-
Note
ANI1/AMP0OUT
Input/output can be specified in 1-bit units.
P23
ANI3
P31
P32
P33
P60
I/O
Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
Port 6.
Input port
Note
INTP1
INTP2/TOOLC1
INTP3/TOOLD1
TI51/TO51/INTP4
2-bit I/O port.
P61
/
PGAIN
ANI2/AMP0+
I/O
Note
Note
P22
P30
/SO10
TxD6
software setting.
P14
P20
Note
SCLA0/INTP11
SDAA0/INTP10
Input/output can be specified in 1-bit units.
Input can be set to SMBus input buffer in 1-bit units.
Output can be set to N-ch open-drain output (VDD
tolerance).
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
P121
P122
I/O
Input
Port 12.
EXLVI/INTP0
X1/TOOLC0
For only P120 and P125, use of an on-chip pull-up resistor
X2/EXCLK/TOOLD0
can be specified by a software setting.
P125
Note
Input port
1-bit I/O port and 3-bit input port.
Reset input
RESET
μPD78F0576, 78F0577, and 78F0578 (products with operational amplifier) only
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
34
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
(2) Non-port functions: 78K0/KB2-L (1/2)
Function Name
ANI0
I/O
Input
Function
A/D converter analog input
After Reset
Analog input
Alternate Function
P20/AMP0-
Note
Note
P21/AMP0OUT
ANI1
/
Note
PGAIN
ANI2
P22/AMP0+
ANI3
P23
Input port
ANI8
Note
Note
P10/SCK10/AMP1-
ANI9
P11/SI10/AMP1OUT
ANI10
P12/SO10/AMP1+
Note
AMP0-
AMP0+
Input
Analog input
P20/ANI0
Operational amplifier 1 input
Input port
P10/ANI8/SCK10
Note
P12/ANI10/SO10
AMP0OUT
Note
AMP1OUT
Note
Note
Note
P22/ANI2
Note
AMP1-
AMP1+
Operational amplifier 0 input
Note
Note
Output
Operational amplifier 0 output
Analog input
P21/ANI1/PGAIN
Operational amplifier 1 output
Input port
P11/ANI9/SI10
Note
PGAIN
Input
PGA (programmable gain amplifier) input
Analog input
P21/ANI1/AMP0OUT
EXLVI
Input
Potential input for external low-voltage detection
Input port
P120/INTP0
INTP0
Input
External interrupt request input for which the valid edge
Input port
P120/EXLVI
(rising edge, falling edge, or both rising and falling
INTP1
P30
edges) can be specified
INTP2
P31/TOOLC1
INTP3
P32/TOOLD1
INTP4
P33/TI51/TO51
INTP5
P16/TOH1
INTP10
P61/SDAA0
INTP11
P60/SCLA0
−
REGC
RESET
RxD6
System reset input
Reset input
P125
Input
Serial data input to UART6
Input port
P14
Output
Serial data output from UART6
I/O
Clock input/output for I C
Note
−
Input
SCLA0
SDAA0
−
Connecting regulator output (2.0 V/2.4 V) stabilization
capacitance for internal operation.
Connect to VSS via a capacitor (0.47 to 1 μF).
TxD6
2
Note
P13
Input port
2
Serial data I/O for I C
P60/INTP11
P61/INTP10
μPD78F0576, 78F0577, and 78F0578 (products with operational amplifier) only
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
35
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
(2) Non-port functions: 78K0/KB2-L (2/2)
Function Name
I/O
Function
After Reset
Alternate Function
I/O
Clock input/output for CSI10
SI10
Input
Serial data input to CSI10
P11/ANI9/AMP1OUT
SO10
Output
Serial data output from CSI10
P12/ANI10/AMP1+
TI000
Input
External count clock input to 16-bit timer/event counter
00
Capture trigger input to capture registers (CR000,
CR010) of 16-bit timer/event counter 00
TI010
Input port
Input port
Capture trigger input to capture register (CR000) of 16bit timer/event counter 00
Input
TI50
TI51
External count clock input to 8-bit timer/event counter 50
P10/ANI8/AMP1-
Note
SCK10
P00
Input port
P17/TO50
P33/TO51/INTP4
TO00
Output
16-bit timer/event counter 00 output
Input port
P01/TI010
TO50
Output
8-bit timer/event counter 50 output
Input port
P17/TI50
Input port
P15
TO51
8-bit timer/event counter 51 output
Output
TOH1
8-bit timer H0 output
P33/TI51/INTP4
8-bit timer H1 output
−
X1
P16/INTP5
Connecting resonator for main system clock
Input port
External clock input for main system clock
Input port
X2
Input
−
VDD
AVREF
Positive power supply for pins other than port 2
P122/X2/TOOLD0
−
−
−
−
A/D converter reference voltage input and positive power
supply for port 2 and A/D converter
−
VSS
AVSS
Ground potential for pins other than port 2
Ground potential for port 2 and A/D converter
TOOLC0
Input
Clock input for flash memory programmer/on-chip
debugger
I/O
Data I/O for flash memory programmer/on-chip debugger
TOOLC1
TOOLD0
Input port
P121/X1
P31/INTP2
P122/X2/EXCLK
TOOLD1
Note
P121/TOOLC0
P122/EXCLK/TOOLD0
EXCLK
IC
Note
P01/TO00
External count clock input to 8-bit timer/event counter 51
TOH0
Note
P32/INTP3/TOH1
−
Internally connected. Leave open.
−
−
μPD78F0576, 78F0577, and 78F0578 (products with operational amplifier) only
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
36
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
2.1.4 78K0/KC2-L
(1) Port functions: 78K0/KC2-L (1/2)
Function Name
P00
I/O
I/O
Function
Port 0.
After Reset
Input port
3-bit I/O port.
P01
Alternate Function
TI000
TI010/TO00
Input/output can be specified in 1-bit units.
P02
Note 1
Note 1
INTP7
Use of an on-chip pull-up resistor can be specified by a
software setting.
P10
I/O
P11
Port 1.
Input port
Note 2
/
8-bit I/O port.
SCK10
Input/output can be specified in 1-bit units.
ANI9/AMP1OUT
Use of an on-chip pull-up resistor can be specified by a
SI10
Note 2
software setting.
P12
ANI8/AMP1-
ANI10/AMP1+
/
Note 2
/
SO10
P13
TxD6
P14
RxD6
P15
TOH0
P16
TOH1/INTP5
P17
TI50/TO50
I/O
P20
Port 2.
Analog input
8-bit I/O port.
P21
ANI0/AMP0-
Note 2
ANI1/AMP0OUT
Input/output can be specified in 1-bit units.
ANI2/AMP0+
P23
ANI3
P24
ANI4
P25
ANI5
P26
ANI7
I/O
P31
P32
P33
P41
Note 3
Note 3
I/O
Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 4.
Note 3
Input port
Note 3
INTP1
INTP2/TOOLC1
INTP3/TOOLD1
TI51/TO51/INTP4
Input port
RTCCL
Note 3
/
Note 3
3-bit I/O port.
RTCDIV
Input/output can be specified in 1-bit units.
(/SCK11)
Use of an on-chip pull-up resistor can be specified by a
RTC1HZ
software setting.
P42
Note 2
ANI6
Note 3
P30
P40
/
PGAIN
P22
P27
Note 2
Note 2
(/SI11)
Note 3
Note 3
Note 3
Note 1
Note 1
PCL
INTP6
/SSI11
Note 1
/
Note 1
Notes 1. 48-pin products only
2. μPD78F0586, 78F0587, and 78F0588 (products with operational amplifier) only
3. 44-pin and 48-pin products only
Remark
Functions in parentheses ( ) can be assigned by setting the port alternate switch control register (MUXSEL).
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Sep 27, 2010
37
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
(1) Port functions: 78K0/KC2-L (2/2)
Function Name
I/O
Port 6.
I/O
P60
P61
After Reset
Input port
SCLA0/SCK11/
INTP11
Input/output can be specified in 1-bit units.
SDAA0/SI11/INTP10
SO11/INTP9
1-bit units.
Note 3
Alternate Function
4-bit I/O port.
Input of P60 and P61 can be set to SMBus input buffer in
P62
P63
Function
INTP8
Output of P60 to P63 can be set to N-ch open-drain output
Note 3
(VDD tolerance).
Use of an on-chip pull-up resistor can be specified by a
software setting.
P70
Port 7.
I/O
Input port
6-bit I/O port.
P71
KR1
Input/output can be specified in 1-bit units.
P72
KR2
Use of an on-chip pull-up resistor can be specified by a
P73
KR0
KR3
software setting.
P74
Note 1
KR4
Note 1
P75
Note 1
KR5
Note 1
P120
Port 12.
I/O
Input port
1-bit I/O port and 5-bit input port.
Input
P121
EXLVI/INTP0
(/SO11)
For only P120 and P125, use of an on-chip pull-up resistor
Note 3
X1/TOOLC0
can be specified by a software setting.
P122
X2/EXCLK/TOOLD0
P123
XT1
P124
XT2/EXCLKS
P125
Reset input
RESET
(2) Non-port functions : 78K0/KC2-L (1/4)
Function Name
I/O
Input
ANI0
Function
A/D converter analog input
After Reset
Analog input
Alternate Function
P20/AMP0-
Note 2
Note 2
ANI1
P21/AMP0OUT
/
Note 2
PGAIN
ANI2
P22/AMP0+
ANI3
P23
ANI4
P24
ANI5
P25
ANI6
ANI7
Note 2
P26
Note 3
P27
Note 3
Notes 1. 48-pin products only
2. μPD78F0586, 78F0587, and 78F0588 (products with operational amplifier) only
3. 44-pin and 48-pin products only
Remark
Functions in parentheses ( ) can be assigned by setting the port alternate switch control register (MUXSEL).
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port functions : 78K0/KC2-L (2/4)
Function Name
ANI8
I/O
Input
Function
A/D converter analog input
After Reset
Input port
Alternate Function
Note 2
P10/SCK10/AMP1P11/SI10/
ANI9
AMP1OUT
Note 2
Note 2
ANI10
P12/SO10/AMP1+
Note 2
Operational amplifier 0 input
AMP0-
AMP0+
Operational amplifier 1 input
AMP1-
Input port
Note 2
AMP0OUT
Note 2
AMP1OUT
Note 2
Note 2
PGAIN
P20/ANI0
P22/ANI2
Note 2
AMP1+
Analog input
Note 2
P10/ANI8/SCK10
P12/ANI10/SO10
Output
Input
Operational amplifier 0 output
Analog input
P21/ANI1/PGAIN
Operational amplifier 1 output
Input port
P11/ANI9/SI10
PGA (programmable gain amplifier) input
Analog input
P21/ANI1/
AMP0OUT
EXLVI
Input
Potential input for external low-voltage detection
Input port
Input
INTP1
External interrupt request input for which the valid edge
Input port
Note 2
P120/INTP0
(/SO11)
INTP0
Note 3
P120/EXLVI
(rising edge, falling edge, or both rising and falling
(/SO11)
edges) can be specified
P30
Note 3
INTP2
P31/TOOLC1
INTP3
P32/TOOLD1
INTP4
P33/TI51/TO51
INTP5
P16/TOH1
INTP6
Note 1
Note 2
P42
Note 1
/PCL
SSI11
Note 1
/
Note 1
INTP7
Note 1
P02
Note 1
INTP8
Note 3
P63
Note 3
INTP9
P62/SO11
INTP10
P61/SDAA0/SI11
INTP11
P60/SCLA0/SCK11
Notes 1. 48-pin products only
2. μPD78F0586, 78F0587, and 78F0588 (products with operational amplifier) only
3. 44-pin and 48-pin products only
Remark
Functions in parentheses ( ) can be assigned by setting the port alternate switch control register (MUXSEL).
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port functions : 78K0/KC2-L (3/4)
Function Name
Input
KR0 to KR3
KR4
Note 1
PCL
Note 1
, KR5
I/O
Function
Key interrupt input
After Reset
Input port
Note 1
Output
Clock output (for output of high-speed system clock,
Input port
subsystem clock)
RTCDIV
RTCCL
Note 3
Output
Note 3
RTC1HZ
Note 3
−
REGC
Alternate Function
P70 to P73
P74
Note 1
P42
Note 1
, P75
/SSI11
INTP6
Real-time counter clock (32 kHz divided frequency)
Input port
P40
Note 3
Real-time counter clock (32 kHz original oscillation)
P40
/RTCDIV
(/SCK11)
Real-time counter correction clock (1 Hz) output
P41
Note 3
System reset input
Reset input
P125
RxD6
Input
Serial data input to UART6
Input port
P14
Serial data output from UART6
Clock input/output for I C
2
2
(/SI11)
Note 3
−
Input
Output
Note 3
Note 3
−
RESET
I/O
Note 3
Note 3
Note 3
output
SCLA0
/
/RTCCL
(/SCK11)
TxD6
Note 1
Note 1
output
Connecting regulator output (2.0 V/2.4V) stabilization
capacitance for internal operation.
Connect to VSS via a capacitor (0.47 to 1 μF).
Note 1
Input port
P13
Input port
P60/SCK11/INTP11
SDAA0
I/O
Serial data I/O for I C
Input port
P61/SI11/INTP10
SCK10
I/O
Clock input/output for CSI10
Input port
P10/ANI8/AMP1-
Clock input/output for CSI11
Input port
P60/SCLA0/INTP11
SCK11
(SCK11)
Note 3
SI10
Note 3
SI11
(SI11)
P11/ANI9/
Note 2
AMP1OUT
Serial data input to CSI11
Input port
P61/SDAA0/INTP10
TI000
TI010
/RTC1HZ
Note 3
Input port
P12/ANI10/AMP1+
Serial data output from CSI11
Input port
P62/INTP9
Input
Chip select input to CSI11
Input port
P42
/PCL
Note 1
INTP6
Input
External count clock input to 16-bit timer/event counter
00
Capture trigger input to capture registers (CR000,
CR010) of 16-bit timer/event counter 00
Input port
P00
Note 3
Note 1
Note 3
Serial data output from CSI10
SO11
SSI11
Input port
P41
Output
(SO11)
/
Serial data input to CSI10
Note 3
SO10
Note 3
/RTCCL
P40
Note 3
RTCDIV
Input
Note 2
Note 2
P120/INTP0/EXLVI
Capture trigger input to capture register (CR000) of 16bit timer/event counter 00
Note 1
Note 1
/
P01/TO00
Notes 1. 48-pin products only
2. μPD78F0586, 78F0587, and 78F0588 (products with operational amplifier) only
3. 44-pin and 48-pin products only
Remark
Functions in parentheses ( ) can be assigned by setting the port alternate switch control register (MUXSEL).
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port functions: 78K0/KC2-L (4/4)
Function Name
TI50
I/O
Input
TI51
External count clock input to 8-bit timer/event counter 50
After Reset
Input port
External count clock input to 8-bit timer/event counter 51
TO00
Output
TO50
Output
TO51
TOH0
Function
16-bit timer/event counter 00 output
Input port
8-bit timer/event counter 50 output
Input port
TOH1
8-bit timer H0 output
−
Connecting resonator for main system clock
Input port
P15
Input port
P121/TOOLC0
P122/EXCLK/TOOLD0
Input
External clock input for main system clock
Input port
P122/X2/TOOLD0
−
Connecting resonator for subsystem clock
Input port
P123
External clock input for subsystem clock
Input port
XT1
XT2
EXCLKS
P17/TI50
P16/INTP5
X2
EXCLK
P01/TI010
P33/TI51/INTP4
8-bit timer H1 output
X1
P17/TO50
P33/TO51/INTP4
8-bit timer/event counter 51 output
Output
Alternate Function
P124/EXCLKS
Input
P124/XT2
VDD
−
Positive power supply for pins other than port 2
−
−
AVREF
−
A/D converter reference voltage input and positive power
supply for port 2 and A/D converter
−
−
VSS
−
Ground potential for pins other than port 2
−
−
AVSS
TOOLC0
Ground potential for port 2 and A/D converter
Input
Clock input for flash memory programmer/on-chip
debugger
I/O
Data I/O for flash memory programmer/on-chip debugger
TOOLC1
TOOLD0
Input port
P31/INTP2
P122/X2/EXCLK
TOOLD1
IC
P121/X1
P32/INTP3
−
Internally connected. Leave open.
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−
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CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
Remark
The pins mounted depend on the product. Refer to 1.3 Pin Configuration (Top View) and 2.1 Pin
Function List.
2.2.1 P00 to P02 (port 0)
P00 to P02 function as an I/O port. These pins also function as timer I/O, external interrupt request input, and chip
select input of serial interface.
The timer I/O can be assigned to P00 of the 78K0/KA2-L (25-pin products) by setting the port alternate switch control
register (MUXSEL).
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
(μPD78F057x)
(μPD78F056x)
(μPD78F057x)
(μPD78F058x)
16 Pins
20 Pins
25 Pins
P00/TI000/
P00/TI000/
P00/TI000/
INTP0
INTP0
INTP0(/TOH1)
32 Pins
40 Pins
44 Pins
48 Pins
P00/TI000
P00/TI000
P00/TI000
P00/TI000
P01/TO00/
P01/TO00/
P01/TO00/
P01/TO00
P01/TO00/
TI010
TI010
TI010
/TI010
TI010
−
−
−
30 Pins
(/TI51)
P01/TO00/
P01/TO00/
TI010
TI010
−
−
−
P02/SSI11/
P02/SSI11/
INTP5
INTP5
−
P02/INTP7
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 to P02 function as an I/O port. P00 to P02 can be set to input or output port in 1-bit units using port mode
register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
(2) Control mode
P00 to P02 function as timer I/O, external interrupt request input, and chip select input of serial interface.
(a) TI000
This is a pin for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a
capture trigger signal to the capture registers (CR000, CR010) of 16-bit timer/event counter 00.
(b) TI010
This is a pin for inputting a capture trigger signal to the capture register (CR000) of 16-bit timer/event counter 00.
(c) TO00
This is a timer output pin of 16-bit timer/event counter 00.
(d) INTP0, INTP5, INTP7
These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
(e) TOH1
This is a timer output pin of 8-bit timer H1
(f) TI51
This is a pin for inputting an external count clock to 8-bit timer/event counter 51.
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CHAPTER 2 PIN FUNCTIONS
(g) SSI11
This is a chip select input pin of serial interface CSI11.
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an I/O port. These pins also function as pins for A/D converter analog input, operational
amplifier I/O, external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
(μPD78F055x)
(μPD78F056x)
(μPD78F057x)
(μPD78F058x)
16 Pins
20, 25, 32 Pins
30 Pins
40, 44, 48 Pins
−
−
P10/ANI8/AMP1-
Note
/SCK10
Note
P10/ANI8/AMP1-
Note
−
−
P11/ANI9/AMP1OUT
−
−
P12/ANI10/AMP1+
−
−
P13/TxD6
P13/TxD6
−
−
P14/RxD6
P14/RxD6
−
−
P15/TOH0
P15/TOH0
−
−
P16/TOH1/INTP5
P16/TOH1/INTP5
−
−
P17/TI50/TO50
P17/TI50/TO50
Note
/SI10
/SO10
/SCK10
P11/ANI9/AMP1OUT
P12/ANI10/AMP1+
Note
Note
/SI10
/SO10
Note Products with operational amplifier only
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an I/O port. P10 to P17 can be set to input or output port in 1-bit units using port mode
register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
(2) Control mode
P10 to P17 function as A/D converter analog input, operational amplifier I/O, external interrupt request input, serial
interface data I/O, clock I/O, and timer I/O.
(a) ANI8 to ANI10
These are A/D converter analog input pins. When using these pins as analog input pins, refer to (5) ANI0/P20
to ANI7/P27, ANI8/P10 to ANI10/P12 in 12.6 Cautions for A/D Converter.
Cautions 1. ANI8/P10 to ANI10/P12 are set in the digital input mode after release of reset.
2. Make the AVREF pin the same potential as the VDD pin when ANI8 to ANI10 are used.
(b) AMP1+, AMP1These are operational amplifier 1 input pins.
(c) AMP1OUT
This is an operational amplifier 1 output pin.
(d) SI10
This is a serial data input pin of serial interface CSI10.
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CHAPTER 2 PIN FUNCTIONS
(e) SO10
This is a serial data output pin of serial interface CSI10.
(f) SCK10
This is a serial clock I/O pin of serial interface CSI10.
(g) RxD6
This is a serial data input pin of serial interface UART6.
(h) TxD6
This is a serial data output pin of serial interface UART6.
(i)
TI50
This is a pin for inputting an external count clock to 8-bit timer/event counter 50.
(j)
TO50
This is a timer output pin of 8-it timer/event counter 50.
(k) TOH0, TOH1
These are a timer output pins of 8-bit timers H0 and H1.
(l)
INTP5
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and
falling edges) can be specified.
2.2.3 P20 to P27 (port 2)
P20 to P27 function as an I/O port. These pins also function as pins for A/D converter analog input, operational
amplifier I/O, and PGA input.
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
(μPD78F055x)
(μPD78F056x)
(μPD78F057x)
(μPD78F058x)
16 Pins
20 Pins
25 Pins
32 Pins
P20/ANI0/
Note
AMP0-
P20/ANI0/
Note
AMP0-
P20/ANI0/
Note
AMP0-
P20/ANI0/
Note
AMP0-
P21/ANI1/
Note
AMP0OUT /
P21/ANI1/
Note
AMP0OUT /
P21/ANI1/
Note
AMP0OUT /
P21/ANI1/
Note
AMP0OUT /
PGAIN
Note
PGAIN
Note
PGAIN
Note
PGAIN
Note
30 Pins
40 Pins
44 Pins
48 Pins
P20/ANI0/
Note
AMP0-
P20/ANI0/
Note
AMP0-
P20/ANI0/
Note
AMP0-
P20/ANI0/
Note
AMP0-
P21/ANI1/
Note
AMP0OUT /
P21/ANI1/
Note
AMP0OUT /
P21/ANI1/
Note
AMP0OUT /
P21/ANI1/
Note
AMP0OUT /
PGAIN
Note
PGAIN
Note
PGAIN
Note
PGAIN
Note
P22/ANI2/
Note
AMP0+
P22/ANI2/
Note
AMP0+
P22/ANI2/
Note
AMP0+
P22/ANI2/
Note
AMP0+
P22/ANI2/
Note
AMP0+
P22/ANI2/
Note
AMP0+
P22/ANI2/
Note
AMP0+
P22/ANI2/
Note
AMP0+
P23/ANI3
P23/ANI3
P23/ANI3
P23/ANI3
P23/ANI3
P23/ANI3
P23/ANI3
P23/ANI3
−
P24/ANI4
P24/ANI4
P24/ANI4
−
P24/ANI4
P24/ANI4
P24/ANI4
−
P25/ANI5
P25/ANI5
P25/ANI5
−
P25/ANI5
P25/ANI5
P25/ANI5
P26/ANI6
P26/ANI6
−
P26/ANI6
P26/ANI6
P26/ANI6
P27/ANI7
−
P27/ANI7
P27/ANI7
−
−
−
−
−
−
Note Products with operational amplifier only
The following operation modes can be specified in 1-bit units.
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CHAPTER 2 PIN FUNCTIONS
(1) Port mode
P20 to P27 function as an I/O port. P20 to P27 can be set to input or output port in 1-bit units using port mode
register 2 (PM2).
(2) Control mode
P20 to P27 function as A/D converter analog input, operational amplifier I/O, and PGA input.
(a) ANI0 to ANI7
These are A/D converter analog input pins. When using these pins as analog input pins, refer to (5) ANI0/P20
to ANI7/P27 and ANI8/P10 to ANI10/P12 in 12.6 Cautions for A/D Converter.
(b) AMP0+, AMP0These are operational amplifier 0 input pins.
(c) AMP0OUT
This is an operational amplifier 0 output pin.
(d) PGAIN
This is a PGA (Programmable gain amplifier) input pin.
Caution ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset.
2.2.4 P30 to P37 (port 3)
P30 to P37 function as an I/O port. These pins also function as pins for external interrupt request input, timer I/O, clock
input and data I/O for flash memory programmer/on-chip debugger, and clock I/O and data I/O for serial interface.
The timer I/O can be assigned to P34 of the 78K0/KA2-L (25-pin and 32-pin products) by setting the port alternate
switch control register (MUXSEL).
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
(μPD78F055x)
(μPD78F056x)
(μPD78F057x)
(μPD78F058x)
16 Pins
20 Pins
P30/TOH1/
P30/TOH1/
TI51/INTP1
TI51/INTP1
−
−
−
−
25 Pins
32 Pins
−
−
30 Pins
40 Pins
44 Pins
48 Pins
P30/INTP1
P30/INTP1
P30/INTP1
P30/INTP1
P31/INTP2/
P31/INTP2/
P31/INTP2/
P31/INTP2/
P31/INTP2/
P31/INTP2/
P31/INTP2/
TOOLC1
TOOLC1
TOOLC1
TOOLC1
TOOLC1
TOOLC1
TOOLC1
P32/INTP3/
P32/INTP3/
P32/INTP3/
P32/INTP3/
P32/INTP3/
P32/INTP3/
P32/INTP3/
TOOLD1
TOOLD1
TOOLD1
TOOLD1
TOOLD1
TOOLD1
TOOLD1
P33
P33
P33/TI51/
P33/TI51/
P33/TI51/
P33/TI51/
TO51/INTP4
TO51/INTP4
TO51/INTP4
TO51/INTP4
−
−
−
−
P35/SCK11
−
−
−
−
−
−
P34/INTP4
P34/INTP4
(/TOH1)
(/TOH1)
(/TI51)
−
−
−
−
P36/SI11
P36/SI11
−
−
−
−
−
−
P37/SO11
P37/SO11
−
−
−
−
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CHAPTER 2 PIN FUNCTIONS
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P37 function as an I/O port. P30 to P37 can be set to input or output port in 1-bit units using port mode
register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
(2) Control mode
P30 to P37 function as external interrupt request input, timer I/O, clock input and data I/O for flash memory
programmer/on-chip debugger, and clock I/O and data I/O for serial interface.
(a) INTP1 to INTP4
These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
(b) TI51
This is an external count clock input pin to 8-bit timer/event counter 51.
(c) TO51
This is a timer output pin from 8-bit timer/event counter 51.
(d) TOH1
This is a timer output pin of 8-bit timer H1.
(e) TOOLC1
This is a clock input pin for flash memory programmer/on-chip debugger.
(f)
TOOLD1
This is a data I/O pin for flash memory programmer/on-chip debugger.
(g) SCK11
This is a serial clock I/O pin of serial interface CSI11.
(h) SI11
This is a serial data input pin of serial interface CSI11.
(i)
SO11
This is a serial data output pin of serial interface CSI11.
Remark
For how to connect a flash memory programmer using TOOLC1/P31, TOOLD1/P32, refer to CHAPTER 25
FLASH MEMORY. For how to connect TOOLC1/P31, TOOLD1/P32 and an on-chip debug emulator, refer
to CHAPTER 26 ON-CHIP DEBUG FUNCTION.
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CHAPTER 2 PIN FUNCTIONS
2.2.5 P40 to P42 (port 4)
P40 to P42 function as an I/O port. These pins also function as pins for external interrupt request input, real-time
counter clock output, real-time counter correction clock output, and chip select input of serial interface.
The clock I/O and data input of the serial interface can be assigned to P40 and P41 of the 78K0/KC2-L (44-pin and 48pin products) respectively by setting the port alternate switch control register (MUXSEL).
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
(μPD78F057x)
(μPD78F056x)
(μPD78F057x)
(μPD78F058x)
16 Pins
20, 25, 32 Pins
30 Pins
40 Pins
−
−
−
−
−
−
−
−
−
−
−
−
44 Pins
48 Pins
P40/RTCCL/
P40/RTCCL/
RTCDIV(/SCK11)
RTCDIV(/SCK11)
P41/RTC1HZ
P41/RTC1HZ
(/SI11)
(/SI11)
−
P42/PCL/SSI11/
INTP6
Remark
Functions in parentheses ( ) can be assigned by setting the port alternate switch control register (MUXSEL).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P40 to P42 function as an I/O port. P40 to P42 can be set to input or output port in 1-bit units using port mode
register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).
(2) Control mode
P40 to P42 function as external interrupt request input, real-time counter clock output, real-time counter correction
clock output, and serial interface clock I/O, data input, and chip select input.
(a) RTCDIV
This is the real-time counter clock (32 kHz division) output pin.
(b) RTCCL
This is the real-time counter clock (32 kHz original oscillation) output pin.
(c) RTC1HZ
This is the real-time counter correction clock (1 Hz) output pin.
(d) INTP6
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and
falling edges) can be specified.
(e) PCL
This is a clock output pin.
(f) SCK11
This is a serial clock I/O pin of serial interface CSI11.
(g) SI11
This is a serial data input pin of serial interface CSI11.
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CHAPTER 2 PIN FUNCTIONS
(h) SSI11
This is a chip select input pin of serial interface CSI11.
2.2.6 P60 to P63 (port 6)
P60 to P63 function as an I/O port. These pins also function as pins for serial interface data I/O, clock I/O, and external
interrupt request input.
Input to the P60 and P61 pins can be specified through a normal input buffer or an SMBus input buffer in 1-bit units,
using port input mode register 6 (PIM6).
Output from the P60 to P63 pins can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance) in
1-bit units, using port output mode register 6 (POM6).
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
(μPD78F055x)
(μPD78F056x)
(μPD78F057x)
(μPD78F058x)
16 Pins
20, 25, 32 Pins
30 Pins
P60/SCLA0/TxD6
P61/SDAA0/RxD6
P60/SCLA0/TxD6
P61/SDAA0/RxD6
P60/SCLA0/INTP11
P61/SDAA0/INTP10
−
−
−
−
−
−
40 Pins
44, 48 Pins
P60/SCLA0/SCK11/
P60/SCLA0/SCK11/
INTP11
INTP11
P61/SDAA0/SI11/
P61/SDAA0/SI11/
INTP10
INTP10
P62/SO11/INTP9
P62/SO11/INTP9
−
P63/INTP8
The following operation modes can be specified in 1-bit units.
(1) Port mode
P60 to P63 function as an I/O port. P60 to P63 can be set to input port or output port in 1-bit units using port mode
register 6 (PM6). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 6 (PU6).
(2) Control mode
P60 to P63 function as serial interface data I/O and clock I/O.
(a) SDAA0
This is a serial data I/O pin for serial interface IICA.
(b) SCLA0
This is a serial clock I/O pin for serial interface IICA.
(c) RxD6
This is a serial data input pin for serial interface UART6.
(d) TxD6
This is a serial data output pin for serial interface UART6.
(e) SCK11
This is a serial clock I/O pin for serial interface CSI11.
(f) SI11
This is a serial data input pin for serial interface CSI11.
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(g) SO11
This is a serial data output pin for serial interface CSI11.
(h) INTP8 to INTP11
These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
2.2.7 P70 to P75 (port 7)
P70 to P75 function as an I/O port. These pins also function as pins for A/D converter analog input and key interrupt
input pins.
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
(μPD78F057x)
(μPD78F056x)
(μPD78F057x)
(μPD78F058x)
16 Pins
20, 25 Pins
32 Pins
30 Pins
40, 44 Pins
48 Pins
−
−
P70/ANI8
−
P70/KR0
P70/KR0
−
−
P71/ANI9
−
P71/KR1
P71/KR1
−
−
P72/ANI10
−
P72/KR2
P72/KR2
−
−
−
−
P73/KR3
P73/KR3
−
−
−
−
−
P74/KR4
−
−
−
−
−
P75/KR5
The following operation modes can be specified in 1-bit units.
(1) Port mode
P70 to P75 function as an I/O port. P70 to P75 can be set to input or output port in 1-bit units using port mode
register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7) in
78K0/KC2-L.
(2) Control mode
P70 to P75 function as pins for A/D converter analog input and key interrupt input pins.
(a) ANI8 to ANI10
These are the A/D converter analog input pins. When using this pin as analog input pin, refer to (5) ANI0/P20 to
ANI7/P27, ANI8/P10 to ANI10/P12, and ANI8/P70 to ANI10/P72 in 12.6 Cautions for A/D Converter.
(b) KR0 to KR5
These are the key interrupt input pins
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2.2.8 P120 to P125 (port 12)
P120 functions as an I/O port. P121 to P125 function as an Input port. These pins also function as pins for external
interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock,
connecting resonator for subsystem clock, external clock input for main system clock, external clock input for subsystem
clock, external reset input, and clock input and data I/O for flash memory programmer/on-chip debugger.
Set bit 5 (RSTM) of the reset pin mode register (RSTMASK) to 1 when using P125/RESET as an input port, and clear
RSTM to 0 when using P125/RESET as an external reset input.
Furthermore, the timer input and external interrupt request input can be assigned to P121 of the 78K0/KA2-L (25-pin
products) and P121 and P125 of the 78K0/KA2-L (32-pin products) by setting the port alternate switch control register
(MUXSEL). The data output of the serial interface can be assigned to P120 of the 78K0/KC2-L (44-pin and 48-pin
products) by setting the port alternate switch control register (MUXSEL).
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
(μPD78F055x)
(μPD78F056x)
(μPD78F057x)
(μPD78F058x)
16 Pins
20 Pins
25 Pins
32 Pins
−
−
−
−
30 Pins
40 Pins
44, 48 Pins
P120/EXLVI/
P120/EXLVI/
P120/EXLVI/
INTP0
INTP0
INTP0(/SO11)
P121/X1/
P121/X1/
P121/X1/
P121/X1/
P121/X1/
P121/X1/
P121/X1/
TOOLC0
TOOLC0
TOOLC0
TOOLC0
TOOLC0
TOOLC0
TOOLC0
(/TI000)
(/TI000)
(/INTP0)
(/INTP0)
P122/X2/
P122/X2/
P122/X2/
P122/X2/
P122/X2/
P122/X2/
P122/X2/
EXCLK/
EXCLK/
EXCLK/
EXCLK/
EXCLK/
EXCLK/
EXCLK/
TOOLD0
TOOLD0
TOOLD0
TOOLD0
TOOLD0
TOOLD0
TOOLD0
−
−
−
−
−
P123/XT1
P123/XT1
−
−
−
−
−
P124/XT2/
P124/XT2/
EXCLKS
EXCLKS
P125/RESET
P125/RESET
P125/RESET
P125/RESET
P125/RESET
P125/RESET
P125/RESET
(/TI000)
(/INTP0)
Remark
Functions in parentheses ( ) can be assigned by setting the port alternate switch control register (MUXSEL).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P120 to P125 function as an I/O port. P120 to P125 can be set to input or output port using port mode register 12
(PM12). Only for P120 and P125, use of an on-chip pull-up resistor can be specified by pull-up resistor option register
12 (PU12).
(2) Control mode
P120 to P125 function as pins for external interrupt request input, potential input for external low-voltage detection,
connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main
system clock, external clock input for subsystem clock, external reset input, and clock input and data I/O for flash
memory programmer/on-chip debugger.
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(a) INTP0
This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling edge, or
both rising and falling edges) can be specified.
(b) EXLVI
This is a potential input pin for external low-voltage detection.
(c) X1, X2
These are pins for connecting a resonator for main system clock.
(d) EXCLK
This is an external clock input pin for main system clock.
(e) XT1, XT2
These are pins for connecting a resonator for subsystem clock.
(f) EXCLKS
This is an external clock input pin for subsystem clock.
(g) SO11
This is a serial data output pin of serial interface CSI11.
(h) RESET
This is an active-low system reset input pin.
(i)
TOOLC0
This is a clock input pin for flash memory programmer/on-chip debugger.
(j)
TOOLD0
This is a data I/O pin for flash memory programmer/on-chip debugger.
(k) TI000
This is a pin for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a
capture trigger signal to the capture registers (CR000, CR010) of 16-bit timer/event counter 00.
Caution
Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset
signal is generated during low level input, the reset status continues until the input rises to the
high level.
Remark
For how to connect a flash memory programmer using TOOLC0/X1, TOOLD0/X2, refer to CHAPTER 25
FLASH MEMORY. For how to connect TOOLC0/X1, TOOLD0/X2 and an on-chip debug emulator, refer to
CHAPTER 26 ON-CHIP DEBUG FUNCTION.
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2.2.9 AVREF, AVSS, VDD, VSS
These are the power supply/ground pins.
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
(μPD78F055x)
(μPD78F056x)
(μPD78F057x)
(μPD78F058x)
16 Pins
20, 25, 32 Pins
30 Pins
40, 44, 48 Pins
AVREF
AVREF
−
−
AVREF
AVREF
AVSS
AVSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
(a) AVREF
This is the A/D converter reference voltage input pin and the positive power supply pin of port 2 and A/D
converter.
This is also the positive power supply pin of port 7 in the 78K0/KA2-L (32 pins).
When the A/D converter is not used, connect this pin directly to VDDNote.
Note Make the AVREF pin the same potential as the VDD pin when port 2 is used as a digital port.
(b) AVSS
This is a ground potential pin of A/D converter and port 2. Even when the A/D converter is not used, always use
this pin with the same potential as the VSS pin.
(c) VDD
VDD is a positive power supply pin.
(d) VSS
Note
VSS is a ground potential pin
.
Note In the 78K0/KY2-L and 78K0/KA2-L, VSS functions alternately as the ground potential of the A/D converter.
Be sure to connect VSS to a stabilized GND (= 0 V).
2.2.10 REGC, IC0, IC
This is a pin for connecting regulator output stabilization capacitance for internal operation and an internally connected
pin.
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
(μPD78F055x)
(μPD78F056x)
(μPD78F057x)
(μPD78F058x)
30 Pins
40, 44, 48 Pins
16 Pins
REGC
20, 25 Pins
REGC
−
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REGC
REGC
REGC
IC0
IC
IC
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CHAPTER 2 PIN FUNCTIONS
(a) REGC
This is a pin for connecting regulator output (2.0 V/2.4 V) stabilization capacitance for internal operation. Connect
this pin to VSS via a capacitor (0.47 to 1 μF). However, when using the STOP mode that has been entered since
operation of the internal high-speed oscillation clock and external main system clock, 0.47 μF is recommended.
Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
REGC
VSS
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
(b) IC0
This is an internally connected pin. Connect directly to VSS.
(c) IC
This is an internally connected pin. Leave open.
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2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Tables 2-2 to 2-6 show the types of pin I/O circuits and the recommended connections of unused pins.
Refer to Figure 2-1 for the configuration of the I/O circuit of each type.
Table 2-2. Pin I/O Circuit Types (78K0/KY2-L)
Pin Name
I/O Circuit Type
5-AQ
P00/TI000/INTP0
I/O
Input:
I/O
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P01/TO00/TI010
ANI0/P20/AMP0-
Recommended Connection of Unused Pins
Note 1
ANI1/P21/AMP0OUT
11-P
Note 1
/
Independently connect to AVREF or VSS via a resistor.
11-O
Note 1
PGAIN
ANI2/P22/AMP0+
Note 1
Leave open.
Note 2
11-N
ANI3/P23
11-G
P30/TOH1/TI51/INTP1
5-AQ
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P60/SCLA0/TxD6
5-AS
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave this pin open at low-level output after clearing
P61/SDAA0/RxD6
the output latch of the port to 0.
P121/X1/TOOLC0
Note 3
Input
37-A
Independently connect to VDD or VSS via a resistor.
P122/X2/EXCLK/
TOOLD0
Note 3
RESET/P125
42-A
Connect directly to VDD or via a resistor.
−
AVREF
−
Connect directly to VDD.
Notes 1. μPD78F0555, 78F0556, and 78F0557 (products with operational amplifier) only
2. If this pin is left open when specified as an analog input pin, the input voltage level might become undefined. It
is therefore recommended to leave this pin open after specifying it as a digital output pin.
3. Use recommended connection above in input port mode (refer to Figure 5-3 Format of Clock Operation
Mode Select Register (OSCCTL)) when these pins are not used.
Cautions 1. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 are set in the analog
input mode after release of reset.
2. Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset
signal is generated during low level input, the reset status continues until the input rises to the high
level.
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Table 2-3. Pin I/O Circuit Types (78K0/KA2-L (20-pin products))
Pin Name
I/O Circuit Type
5-AQ
P00/TI000/INTP0
I/O
Input:
I/O
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P01/TO00/TI010
ANI0/P20/AMP0-
Recommended Connection of Unused Pins
Note 1
ANI1/P21/AMP0OUT
11-P
Note 1
Independently connect to AVREF or VSS via a resistor.
11-O
/
PGAINNote 1
ANI2/P22/AMP0+
Leave open.
Note 1
Note 2
11-N
11-G
ANI3/P23
ANI4/P24
ANI5/P25
P30/TOH1/TI51/INTP1
5-AQ
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P31/INTP2/TOOLC1
P32/TOH1/INTP3/TOOLD1
P60/SCLA0/TxD6
5-AS
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave this pin open at low-level output after clearing
P61/SDAA0/RxD6
the output latch of the port to 0.
P121/X1/TOOLC0
Note 3
P122/X2/EXCLK/TOOLD0
RESET/P125
37-A
Input
Independently connect to VDD or VSS via a resistor.
42-A
Input
Connect directly to VDD or via a resistor.
Note 3
−
AVREF
−
Connect directly to VDD.
Notes 1. μPD78F0565, 78F0566, and 78F0567 (products with operational amplifier) only
2. If this pin is left open when specified as an analog input pin, the input voltage level might become undefined. It
is therefore recommended to leave this pin open after specifying it as a digital output pin.
3. Use recommended connection above in input port mode (refer to Figure 5-3 Format of Clock Operation
Mode Select Register (OSCCTL)) when these pins are not used.
Cautions 1. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 to ANI5/P25 are set in
the analog input mode after release of reset.
2. Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset
signal is generated during low level input, the reset status continues until the input rises to the high
level.
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Table 2-4. Pin I/O Circuit Types (78K0/KA2-L (25-pin and 32-pin products))
Pin Name
P00
Note 1
/TI000
INTP0
P01
/
I/O
I/O
5-AQ
Note 1
Note 2
/TO00
TI010
I/O Circuit Type
Note 1
Recommended Connection of Unused Pins
Input:
Independently connect to VDD or VSS via a resistor.
Output:
Leave open.
Note 2
/
Note 2
P02/SSI11/INTP5
ANI0/P20/AMP0- Note 3
ANI1/P21/AMP0OUT
PGAIN
Note 3
/
11-P
11-O
Independently connect to AVREF or VSS via a resistor.
Note 3
ANI2/P22/AMP0+
Note 3
ANI3/P23 to ANI6/P26
ANI7/P27
Leave open. Note 4
11-N
11-G
Note 2
5-AQ
P31/INTP2/TOOLC1
P32/TOH1/INTP3/TOOLD1
Input:
Independently connect to VDD or VSS via a resistor.
Output:
Leave open.
P33
P34/INTP4
(/TOH1)(/TI51)Note 1
P35/SCK11
P36/SI11
P37/SO11
P60/SCLA0/TxD6
5-AS
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave this pin open at low-level output after clearing
P61/SDAA0/RxD6
the output latch of the port to 0.
ANI8
Note 2
Note 2
ANI9
Note 2
Note 2
/P70
ANI10
/P71
Note 2
/P72
11-G
Independently connect to AVREF or VSS via a resistor.
Note 2
Leave open. Note 4
P121/X1/TOOLC0 Note 5
Input
37-A
Independently connect to VDD or VSS via a resistor.
(/TI000)(/INTP0)
P122/X2/EXCLK/
TOOLD0 Note 5
42-A
RESET/P125
(/TI000)
Note 2
(/INTP0)
Connect directly to VDD or via a resistor.
Note 2
−
AVREF
−
Connect directly to VDD.
Notes 1. 25-pin products only
2. 32-pin products only
3. μPD78F0565, 78F0566, and 78F0567 (products with operational amplifier) only
4. If this pin is left open when specified as an analog input pin, the input voltage level might become undefined. It
is therefore recommended to leave this pin open after specifying it as a digital output pin.
5. Use recommended connection above in input port mode (refer to Figure 5-3 Format of Clock Operation
Mode Select Register (OSCCTL)) when these pins are not used.
Cautions 1. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, ANI3/P23 to ANI5/P25, and ANI8/P70
to ANI10/P72 are set in the analog input mode after release of reset.
2. Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset signal
is generated during low level input, the reset status continues until the input rises to the high level.
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Table 2-5. Pin I/O Circuit Types (78K0/KB2-L)
Pin Name
I/O Circuit Type
P00/TI000
I/O
Input:
I/O
5-AQ
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P01/TO00/TI010
P10/ANI8/ANP1-
Recommended Connection of Unused Pins
Note 1
/SCK10
P11/ANI9/ANP1OUT
P12/ANI10/ANP1+
Note 1
/SI10
Note 1
/SO10
11-L
11-M
11-K
P13/TxD6
5-AG
P14/RxD6
5-AQ
P15/TOH0
5-AG
P16/TOH1/INTP5
5-AQ
P17/TI50/TO50
ANI0/P20/AMP0-
Note 1
ANI1/P21/AMP0OUT
Note 1
/
11-P
11-O
Independently connect to AVREF or AVSS via a resistor.
Note 1
PGAIN
ANI2/P22/AMP0+
Leave open.
Note 1
Note 2
11-N
ANI3/P23
11-G
P30/INTP1
5-AQ
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P31/INTP2/TOOLC1
P32/INTP3/TOOLD1
P33/TI51/TO51/INTP4
P60/SCLA0/INTP11
5-AS
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave this pin open at low-level output after clearing
P61/SDAA0/INTP10
the output latch of the port to 0.
5-AQ
P120/EXLVI/INTP0
P121/X1/TOOLC0
Note 3
P122/X2/EXCLK/TOOLD0
RESET/P125
Independently connect to VDD or VSS via a resistor.
37-A
Input
42-A
Input
Note 3
Connect directly to VDD or via a resistor.
AVREF
−
−
Connect directly to VDD.
AVSS
−
−
Connect directly to VSS.
Note 4
Notes 1. μPD78F0576, 78F0577, and 78F0578 (products with operational amplifier) only
2. If this pin is left open when specified as an analog input pin, the input voltage level might become undefined. It
is therefore recommended to leave this pin open after specifying it as a digital output pin.
3. Use recommended connection above in input port mode (refer to Figure 5-3 Format of Clock Operation
Mode Select Register (OSCCTL)) when these pins are not used.
4. When port 2 is used as the digital port pins, make AVREF the same potential as VDD.
Cautions 1. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 are set in the analog
input mode, P10/ANI8/AMP1-/SCK10, P11/ANI9/AMP1OUT/SI10, and P12/ANI10/AMP1+/SO10 are set
in the digital input mode after release of reset.
2. Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset
signal is generated during low level input, the reset status continues until the input rises to the high
level.
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Table 2-6. Pin I/O Circuit Types (78K0/KC2-L) (1/2)
Pin Name
I/O Circuit Type
5-AQ
P00/TI000
Note 1
/INTP7
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P01/TO00/TI010
P02
I/O
Note 1
P10/ANI8/ANP1-
Note 2
/SCK10
P11/ANI9/ANP1OUT
P12/ANI10/ANP1+
Note 2
/SI10
Note 2
/SO10
11-L
11-M
11-K
P13/TxD6
5-AG
P14/RxD6
5-AQ
P15/TOH0
5-AG
P16/TOH1/INTP5
5-AQ
P17/TI50/TO50
ANI0/P20/AMP0-
Note 2
ANI1/P21/AMP0OUT
Note 2
/
11-P
< Digital input setting>
11-O
Independently connect to AVREF or AVSS via a resistor.
Note 2
PGAIN
ANI2/P22/AMP0+
Leave open.
Note 2
11-G
ANI3/P23 to ANI6/P26
ANI7
Note 4
/P27
Note 3
11-N
Note 4
5-AQ
P30/INTP1
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P31/INTP2/TOOLC1
P32/INTP3/TOOLD1
P33/TI51/TO51/INTP4
P40
Note 4
RTCDIV
P41
/
Note 4
(/SCK11)
Note 4
/RTC1HZ
Note 1
INTP6
Note 4
Note 4
Note 4
(/SI11)
P42
Note 4
/RTCCL
/PCL
Note 1
/SSI11
Note 1
/
Note 1
Notes 1. 48-pin products only
2. μPD78F0586, 78F0587, and 78F0588 (products with operational amplifier) only
3. If this pin is left open when specified as an analog input pin, the input voltage level might become undefined. It
is therefore recommended to leave this pin open after specifying it as a digital output pin.
4. 44-pin and 48-pin products only
Caution ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 to ANI7/P27 are set in the
analog input mode, P10/ANI8/AMP1-/SCK10, P11/ANI9/AMP1OUT/SI10, and P12/ANI10/AMP1+/SO10 are
set in the digital input mode after release of reset.
Remark
Functions in parentheses ( ) in the table above can be assigned by setting the port alternate switch control
register (MUXSEL).
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Table 2-6. Pin I/O Circuit Types (78K0/KC2-L) (2/2)
Pin Name
I/O Circuit Type
P60/SCLA0/SCK11/INTP11
I/O
Input:
I/O
5-AS
Note 3
/INTP8
the output latch of the port to 0.
5-AR
P62/SO11/INTP9
Independently connect to VDD or VSS via a resistor.
Output: Leave this pin open at low-level output after clearing
P61/SDAA0/SI11/INTP10
P63
Recommended Connection of Unused Pins
Note 3
Input:
5-AQ
P70/KR0
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P71/KR1
P72/KR2
P73/KR3
P74
Note 1
Note 1
P75
Note 1
Note 1
/KR4
/KR5
P120/EXLVI/INTP0
(/SO11)
Independently connect to VDD or VSS via a resistor.
Note 3
P121/X1/TOOLC0
Note 2
37-A
Input
42-A
Input
P122/X2/EXCLK/
TOOLD0
Note 2
P123/XT1
Note 2
P124/XT2/EXCLKS
RESET/P125
Note 2
Connect directly to VDD or via a resistor.
AVREF
−
−
Connect directly to VDD.
AVSS
−
−
Connect directly to VSS.
Note 4
Notes 1. 48-pin products only
2. Use recommended connection above in input port mode (refer to Figure 5-4 Format of Clock Operation
Mode Select Register (OSCCTL)) when these pins are not used.
3. 44-pin and 48-pin products only
4. When port 2 is used as the digital port pins, make AVREF the same potential as VDD.
Caution Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset signal
is generated during low level input, the reset status continues until the input rises to the high level.
Remark
Functions in parentheses ( ) in the table above can be assigned by setting the port alternate switch control
register (MUXSEL).
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (1/4)
Type 5-AG
Type 5-AR
VDD
VDD
pullup
enable
pullup
enable
P-ch
P-ch
VDD
data
VDD
CMOS/N-ch OD
data
P-ch
P-ch
IN/OUT
IN/OUT
output
disable
output
disable
N-ch
N-ch
VSS
VSS
input
enable
input
enable
Type 5-AQ
Type 5-AS
VDD
VDD
pullup
enable
pullup
enable
P-ch
P-ch
VDD
VDD
data
CMOS/N-ch OD
data
IN/OUT
P-ch
IN/OUT
output
disable
P-ch
N-ch
output
disable
N-ch
SCHMIT
VSS
VSS
input
enable
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SMBus I/O buffer
input enable
PIM
60
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (2/4)
Type 11-G
Type 11-L
VDD
pullup
enable
P-ch
AVREF
VDD
data
P-ch
data
P-ch
IN/OUT
output
disable
IN/OUT
N-ch
output
disable
N-ch
AVSS
P-ch
Comparator
AVSS
+
P-ch
Comparator
_
+
N-ch
_
Series resistor string voltage
N-ch
AVSS
VREF
(Threshold voltage)
AVSS
input enable
input enable
+
OP
AMP
_
Type 11-K
Type 11-M
VDD
VDD
pullup
enable
pullup
enable
P-ch
P-ch
VDD
VDD
data
data
P-ch
P-ch
IN/OUT
IN/OUT
output
disable
N-ch
output
disable
N-ch
AVSS
AVSS
P-ch
P-ch
Comparator
Comparator
+
+
_
_
N-ch
N-ch
VREF
(Threshold voltage)
VREF
(Threshold voltage)
AVSS
AVSS
input enable
input enable
+
OP
AMP
_
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OP
_AMP
61
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (3/4)
Type 11-N
Type 11-P
AVREF
AVREF
data
data
P-ch
P-ch
IN/OUT
output
disable
IN/OUT
output
disable
N-ch
N-ch
AVSS
AVSS
P-ch
P-ch
Comparator
Comparator
+
+
_
_
N-ch
N-ch
VREF
(Threshold voltage)
VREF
(Threshold voltage)
AVSS
AVSS
input enable
input enable
+
+
OP
AMP
_
OP
AMP
_
Type 11-O
Type 37-A
AVREF
data
P-ch
IN/OUT
output
disable
N-ch
X2,
XT2
input
enable
AVSS
P-ch
Comparator
+
_
N-ch
AVSS
P-ch
N-ch
VREF
(Threshold voltage)
input enable
_
PGA
+
+
OP
_AMP
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Sep 27, 2010
input
enable
X1,
XT1
62
78K0/Kx2-L
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (4/4)
Type 42-A
VDD
pullup
enable
P-ch
IN
input enable
SCHMIT
reset
reset mask
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CHAPTER 3 CPU ARCHITECTURE
CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
Products in the 78K0/Kx2-L microcontrollers can access a 64 KB memory space. Figures 3-1 to 3-4 show the memory
maps.
Caution Reset signal generation makes the setting of the ROM area undefined. Therefore, set the value
corresponding to each product as indicated below after release of reset.
Table 3-1. Set Values of Internal Memory Size Switching Register (IMS)
IMS
Products
ROM Capacity
Internal High-Speed
RAM Capacity
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
μPD78F0550,
μPD78F0560,
−
−
61H
4 KB
384 bytes
78F0555
78F0565
μPD78F0551,
μPD78F0561,
μPD78F0571,
μPD78F0581,
42H
8 KB
512 bytes
78F0556
78F0566
78F0576
78F0586
μPD78F0552,
μPD78F0562,
μPD78F0572,
μPD78F0582,
04H
16 KB
768 bytes
78F0557
78F0567
78F0577
78F0587
μPD78F0573,
μPD78F0583,
C8H
32 KB
1 KB
78F0578
78F0588
−
−
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-1. Memory Map (μPD78F0550, 78F0555, 78F0560, 78F0565)
FFFFH
Special function registers
(SFR)
256 × 8 bits
FF00H
FEFFH
General-purpose
registers
32 × 8 bits
FEE0H
FEDFH
Internal high-speed RAM
384 × 8 bits
FD80H
FD7FH
0FFFH
CALLF entry area
2048 × 8 bits
Data memory
space
0800H
07FFH
Program area
1905 × 8 bits
008FH
008EH
Reserved
0085H
0084H
0080H
007FH
Boot cluster 0Note
Option byte area
5 × 8 bits
CALLT table area
64 × 8 bits
1000H
0FFFH
Program
memory space
On-chip debug security
ID setting area
10 × 8 bits
0040H
003FH
Flash memory
4096 × 8 bits
Vector table area
64 × 8 bits
0000H
0000H
Note Writing boot cluster 0 can be prohibited depending on the setting of security (refer to 25.6 Security Settings).
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
refer to Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
0FFFH
0C00H
0BFFH
0800H
07FFH
0400H
03FFH
0000H
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Block 02H
Block 01H
Block 00H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-2. Memory Map (μPD78F0551, 78F0556, 78F0561, 78F0566, 78F0571, 78F0576, 78F0581, 78F0586)
FFFFH
Special function registers
(SFR)
256 × 8 bits
1FFFH
1FFFH
Program area
FF00H
FEFFH
General-purpose
registers
32 × 8 bits
FEE0H
FEDFH
108FH
108EH
1085H
1084H
1080H
107FH
Internal high-speed RAM
512 × 8 bits
On-chip debug security
ID setting areaNote 1
10 × 8 bits
Boot cluster 1
Option byte areaNote 1
5 × 8 bits
Program area
1000H
0FFFH
FD00H
FCFFH
CALLF entry area
2048 × 8 bits
Data memory
space
0800H
07FFH
Program area
1905 × 8 bits
Reserved
008FH
008EH
0085H
0084H
0080H
007FH
2000H
1FFFH
Program
memory space
On-chip debug security
ID setting areaNote 1
10 × 8 bits
Boot cluster 0Note 2
Option byte areaNote 1
5 × 8 bits
CALLT table area
64 × 8 bits
0040H
003FH
Flash memory
8192 × 8 bits
Vector table area
64 × 8 bits
0000H
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security IDs
to 0085H to 008EH.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the on-chip
debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (refer to 25.6
Security
Settings).
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
refer to Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
1FFFH
Block 07H
1C00H
1BFFH
0800H
07FFH
0400H
03FFH
0000H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-3. Memory Map (μPD78F0552, 78F0557, 78F0562, 78F0567, 78F0572, 78F0577, 78F0582, 78F0587)
FFFFH
3FFFH
Special function registers
(SFR)
256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
1FFFH
Program area
General-purpose
registers
32 × 8 bits
108FH
108EH
1085H
1084H
Internal high-speed RAM
768 × 8 bits
On-chip debug security
ID setting areaNote 1
10 × 8 bits
Option byte areaNote 1
5 × 8 bits
1080H
107FH
Program area
1000H
0FFFH
FC00H
FBFFH
Boot cluster 1
CALLF entry area
2048 × 8 bits
Data memory
space
0800H
07FFH
Program area
1905 × 8 bits
Reserved
008FH
008EH
0085H
0084H
0080H
007FH
On-chip debug security
ID setting areaNote 1
10 × 8 bits
Option byte areaNote 1
5 × 8 bits
4000H
3FFFH
Program
memory space
Boot cluster 0Note 2
CALLT table area
64 × 8 bits
0040H
003FH
Flash memory
16384 × 8 bits
Vector table area
64 × 8 bits
0000H
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security IDs
to 0085H to 008EH.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the on-chip
debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (refer to 25.6
Security
Settings).
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
refer to Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
3FFFH
Block 0FH
3C00H
3BFFH
0800H
07FFH
0400H
03FFH
0000H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-4. Memory Map (μPD78F0573, 78F0578, 78F0583, 78F0588)
FFFFH
7FFFH
Special function registers
(SFR)
256 × 8 bits
FF00H
FEFFH
1FFFH
Program area
General-purpose
registers
32 × 8 bits
FEE0H
FEDFH
108FH
108EH
On-chip debug security
ID setting areaNote 1
10 × 8 bits
1085H
1084H
Option byte areaNote 1
5 × 8 bits
1080H
107FH
Internal high-speed RAM
1024 × 8 bits
Program area
1000H
0FFFH
FB00H
FAFFH
Boot cluster 1
CALLF entry area
2048 × 8 bits
Data memory
space
0800H
07FFH
Program area
1905 × 8 bits
Reserved
008FH
008EH
On-chip debug security
ID setting areaNote 1
10 × 8 bits
0085H
0084H
0080H
007FH
Option byte areaNote 1
5 × 8 bits
8000H
7FFFH
Program
memory space
Boot cluster 0Note 2
CALLT table area
64 × 8 bits
0040H
003FH
Flash memory
32768 × 8 bits
Vector table area
64 × 8 bits
0000H
0000H
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security IDs
to 0085H to 008EH.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the on-chip
debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (refer to 25.6
Security
Settings).
Remark
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
refer to Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
7FFFH
Block 1FH
7C00H
7BFFH
0800H
07FFH
0400H
03FFH
0000H
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78K0/Kx2-L
CHAPTER 3 CPU ARCHITECTURE
Correspondence between the address values and block numbers in the flash memory are shown below.
Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory
Address Value
Block Number
Address Value
Block Number
0000H to 03FFH
00H
4000H to 43FFH
10H
0400H to 07FFH
01H
4400H to 47FFH
11H
0800H to 0BFFH
02H
4800H to 4BFFH
12H
0C00H to 0FFFH
03H
4C00H to 4FFFH
13H
1000H to 13FFH
04H
5000H to 53FFH
14H
1400H to 17FFH
05H
5400H to 57FFH
15H
1800H to 1BFFH
06H
5800H to 5BFFH
16H
1C00H to 1FFFH
07H
5C00H to 5FFFH
17H
2000H to 23FFH
08H
6000H to 63FFH
18H
2400H to 27FFH
09H
6400H to 67FFH
19H
2800H to 2BFFH
0AH
6800H to 6BFFH
1AH
2C00H to 2FFFH
0BH
6C00H to 6FFFH
1BH
3000H to 33FFH
0CH
7000H to 73FFH
1CH
3400H to 37FFH
0DH
7400H to 77FFH
1DH
3800H to 3BFFH
0EH
7800H to 7BFFH
1EH
3C00H to 3FFFH
0FH
7C00H to 7FFFH
1FH
Remark
μPD78F05x0, 78F05x5 (x = 5, 6):
μPD78F05x1, 78F05x6 (x = 5 to 8):
μPD78F05x2, 78F05x7 (x = 5 to 8):
μPD78F05x3, 78F05x8 (x = 7, 8):
Block numbers 00H to 03H
Block numbers 00H to 07H
Block numbers 00H to 0FH
Block numbers 00H to 1FH
3.1.1 Internal program memory space
The internal program memory space stores the program and table data. Normally, it is addressed with the program
counter (PC).
78K0/Kx2-L microcontrollers incorporate internal ROM (flash memory), as shown below.
Table 3-3. Internal ROM Capacity
Product
78K0/KY2-L
78K0/KA2-L
Internal ROM
78K0/KB2-L
78K0/KC2-L
−
−
Structure
Capacity
μPD78F0550,
μPD78F0560,
78F0555
78F0565
μPD78F0551,
μPD78F0561,
μPD78F0571,
μPD78F0581,
8192 × 8 bits
78F0556
78F0566
78F0576
78F0586
(0000H to 1FFFH)
μPD78F0552,
μPD78F0562,
μPD78F0572,
μPD78F0582,
16384 × 8 bits
78F0557
78F0567
78F0577
78F0587
(0000H to 3FFFH)
−
−
μPD78F0573,
μPD78F0583,
32768 × 8 bits
78F0578
78F0588
(0000H to 7FFFH)
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Flash memory
4096 × 8 bits
(0000H to 0FFFH)
69
78K0/Kx2-L
CHAPTER 3 CPU ARCHITECTURE
The internal program memory space is divided into the following areas.
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon
reset or generation of each interrupt request are stored in the vector table area.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses.
Table 3-4. Vector Table
Vector Table
Address
Interrupt Source
78K0/
KY2-L
78K0/KA2-L
78K0/
KB2-L
78K0/KC2-L
16 Pins
20 Pins
25 Pins
32 Pins
30 Pins
40 Pins
44 Pins
48 Pins
0000H
RESET input,
POC, LVI, WDT
√
√
√
√
√
√
√
√
0004H
INTLVI
√
√
√
√
√
√
√
√
0006H
INTP0
√
√
√
√
√
√
√
√
0008H
INTP1
√
√
−
−
√
√
√
√
000AH
INTP2
−
√
√
√
√
√
√
√
000CH
INTP3
−
√
√
√
√
√
√
√
000EH
INTP4
−
−
√
√
√
√
√
√
0010H
INTP5
−
−
√
√
√
√
√
√
0012H
INTSRE6
√
√
√
√
√
√
√
√
0014H
INTSR6
√
√
√
√
√
√
√
√
0016H
INTST6
√
√
√
√
√
√
√
√
0018H
INTCSI10
−
−
−
−
√
√
√
√
INTCSI11
−
−
√
√
−
−
−
−
001AH
INTTMH1
√
√
√
√
√
√
√
√
001CH
INTTMH0
−
−
−
−
√
√
√
√
001EH
INTTM50
−
−
−
−
√
√
√
√
0020H
INTTM000
√
√
√
√
√
√
√
√
0022H
INTTM010
√
√
√
√
√
√
√
√
0024H
INTAD
√
√
√
√
√
√
√
√
0026H
INTP6
−
−
−
−
−
−
−
√
0028H
INTRTCI
−
−
−
−
−
√
√
√
002AH
INTTM51
√
√
√
√
√
√
√
√
002CH
INTKR
−
−
−
−
−
√
√
√
002EH
INTRTC
−
−
−
−
−
√
√
√
0030H
INTP7
−
−
−
−
−
−
−
√
0032H
INTP8
−
−
−
−
−
−
√
√
0034H
INTIICA0
√
√
√
√
√
√
√
√
0036H
INTCSI11
−
−
−
−
−
√
√
√
0038H
INTP9
−
−
−
−
−
√
√
√
003AH
INTP10
−
−
−
−
√
√
√
√
003CH
INTP11
−
−
−
−
√
√
√
√
003EH
BRK
√
√
√
√
√
√
√
√
Remark
√: Mounted, −: Not mounted
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CHAPTER 3 CPU ARCHITECTURE
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) Option byte area
A 5-byte area of 0080H to 0084H and 1080H to 1084H can be used as an option byte area. Set the option byte at
0080H to 0084H when the boot swap is not used, and at 0080H to 0084H and 1080H to 1084H when the boot swap is
used. For details, refer to CHAPTER 24 OPTION BYTE.
(4) On-chip debug security ID setting area
A 10-byte area of 0085H to 008EH and 1085H to 108EH can be used as an on-chip debug security ID setting area.
Set the on-chip debug security ID of 10 bytes at 0085H to 008EH when the boot swap is not used and at 0085H to
008EH and 1085H to 108EH when the boot swap is used. For details, refer to CHAPTER 26 ON-CHIP DEBUG
FUNCTION.
(5) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
3.1.2 Internal data memory space
78K0/Kx2-L microcontrollers incorporate the following RAMs.
(1) Internal high-speed RAM
Table 3-5. Internal High-Speed RAM Capacity
Internal High-Speed
Product
78K0/KY2-L
78K0/KA2-L
78K0/KB2-L
78K0/KC2-L
−
−
RAM
μPD78F0550,
μPD78F0560,
78F0555
78F0565
μPD78F0551,
μPD78F0561,
μPD78F0571,
μPD78F0581,
512 × 8 bits
78F0556
78F0566
78F0576
78F0586
(FD00H to FEFFH)
μPD78F0552,
μPD78F0562,
μPD78F0572,
μPD78F0582,
768 × 8 bits
78F0557
78F0567
78F0577
78F0587
(FC00H to FEFFH)
−
−
μPD78F0573,
μPD78F0583,
1024 × 8 bits
78F0578
78F0588
(FB00H to FEFFH)
384 × 8 bits
(FD80H to FEFFH)
The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit
registers per bank.
This area cannot be used as a program area in which instructions are written and executed.
The internal high-speed RAM can also be used as a stack memory.
3.1.3 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to
Tables 3-6 to 3-9 Special Function Register List in 3.2.3 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
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3.1.4 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the
register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
78K0/Kx2-L microcontrollers, based on operability and other considerations.
For areas containing data memory in
particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose
registers are available for use. Figures 3-5 to 3-8 show correspondence between data memory and addressing. For
details of each addressing mode, refer to 3.4 Operand Address Addressing.
Figure 3-5. Correspondence Between Data Memory and Addressing
(μPD78F0550, 78F0555, 78F0560, 78F0565)
FFFFH
Special function registers
(SFR)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
FE20H
FE1FH
General-purpose
registers
32 × 8 bits
Register addressing
Short direct
addressing
Internal high-speed RAM
384 × 8 bits
FD80H
FC7FH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
1000H
0FFFH
Flash memory
4096 × 8 bits
0000H
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Figure 3-6. Correspondence Between Data Memory and Addressing
(μPD78F0551, 78F0556, 78F0561, 78F0566, 78F0571, 78F0576, 78F0581, 78F0586)
FFFFH
Special function registers
(SFR)
256 × 8 bits
SFR addressing
General-purpose
registers
32 × 8 bits
Register addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
Short direct
addressing
Internal high-speed RAM
512 × 8 bits
FE20H
FE1FH
FD00H
FCFFH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
2000H
1FFFH
Flash memory
8192 × 8 bits
0000H
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Figure 3-7. Correspondence Between Data Memory and Addressing
(μPD78F0552, 78F0557, 78F0562, 78F0567, 78F0572, 78F0577, 78F0582, 78F0587)
FFFFH
Special function registers
(SFR)
256 x 8 bits
SFR addressing
General-purpose
registers
32 x 8 bits
Register addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
Short direct
addressing
Internal high-speed RAM
768 x 8 bits
FE20H
FE1FH
FC00H
FBFFH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
4000H
3FFFH
Flash memory
16384 x 8 bits
0000H
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Figure 3-8. Correspondence Between Data Memory and Addressing
(μPD78F0573, 78F0578, 78F0583, 78F0588)
FFFFH
Special function registers
(SFR)
256 × 8 bits
SFR addressing
General-purpose
registers
32 × 8 bits
Register addressing
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
Short direct
addressing
Internal high-speed RAM
1024 × 8 bits
FE20H
FE1FH
Direct addressing
FB00H
FAFFH
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
8000H
7FFFH
Flash memory
32768 × 8 bits
0000H
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3.2 Processor Registers
The 78K0/Kx2-L microcontrollers incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched.
When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-9. Format of Program Counter
0
15
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are stored in the stack area upon vectored interrupt request acknowledge or PUSH
PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions.
Reset signal generation sets PSW to 02H.
Figure 3-10. Format of Program Status Word
7
PSW
IE
0
Z
RBS1
AC
RBS0
0
ISP
CY
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled
with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority
specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
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(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is
stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-level
vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H) (refer to
17.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged. Actual
request acknowledgment is controlled by the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon
rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area
can be set as the stack area.
Figure 3-11. Format of Stack Pointer
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the
stack memory.
Each stack operation saves/restores data as shown in Figures 3-12 and 3-13.
Caution Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before
using the stack.
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Figure 3-12. Data to Be Saved to Stack Memory
(a) PUSH rp instruction (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
Register pair higher
FEDEH
Register pair lower
(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
PC15 to PC8
FEDEH
PC7 to PC0
(c) Interrupt, BRK instructions (when SP = FEE0H)
SP
SP
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FEE0H
FEDDH
FEE0H
FEDFH
PSW
FEDEH
PC15 to PC8
FEDDH
PC7 to PC0
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-13. Data to Be Restored from Stack Memory
(a) POP rp instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
Register pair higher
FEDEH
Register pair lower
(b) RET instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
PC15 to PC8
FEDEH
PC7 to PC0
(c) RETI, RETB instructions (when SP = FEDDH)
SP
SP
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FEE0H
FEDDH
FEE0H
FEDFH
PSW
FEDEH
PC15 to PC8
FEDDH
PC7 to PC0
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CHAPTER 3 CPU ARCHITECTURE
3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX,
BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4register bank configuration, an efficient program can be created by switching between a register for normal processing and
a register for interrupts for each bank.
Figure 3-14. Configuration of General-Purpose Registers
(a) Function name
16-bit processing
8-bit processing
FEFFH
H
Register bank 0
HL
L
FEF8H
D
Register bank 1
DE
E
FEF0H
B
BC
Register bank 2
C
FEE8H
A
AX
Register bank 3
X
FEE0H
15
0
7
0
(b) Absolute name
16-bit processing
8-bit processing
FEFFH
R7
Register bank 0
RP3
R6
FEF8H
R5
Register bank 1
RP2
R4
FEF0H
R3
RP1
Register bank 2
R2
FEE8H
R1
RP0
Register bank 3
R0
FEE0H
15
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CHAPTER 3 CPU ARCHITECTURE
3.2.3 Special function registers (SFRs)
Unlike a general-purpose register, each special function register has a special function.
SFRs are allocated to the FF00H to FFFFH area.
Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit
manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When specifying an address, describe an even address.
Tables 3-6 to 3-9 give lists of the special function registers. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined as
an sfr variable using the #pragma sfr directive in the CC78K0. When using the RA78K0, ID78K0-QB, and system
simulator, symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding special function register can be read or written.
R/W: Read/write enable
R:
Read only
W:
Write only
• Manipulatable bit units
Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon reset signal generation.
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Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
FF00H
P0
−
FF01H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
P01
P00
−
−
−
−
−
−
−
page
Address
Reference
Table 3-6. Special Function Register List: 78K0/KY2-L (1/4)
1
8
16
R/W
√
√
−
00H
172
−
−
−
−
−
−
−
FF02H
P2
0
0
0
0
P23
P22
P21
P20
R/W
√
√
−
00H
172
FF03H
P3
0
0
0
0
0
0
0
P30
R/W
√
√
−
00H
172
FF04H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF05H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
P61
P60
R/W
√
√
−
00H
172
FF07H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF08H
AD ADCRL
−
−
−
−
−
−
−
−
R
−
√
−
00H
411
FF09H
CR
0
0
0
0
0
0
−
−
R
−
−
√
0000H
410
FF0AH
RXB6
−
−
−
−
−
−
−
−
R
−
√
−
FFH
452
FF0BH
TXB6
−
−
−
−
−
−
−
−
R/W
−
√
−
FFH
453
FF0CH
P12
0
0
P125
0
0
P122
P121
0
R
√
√
−
00H
172
FF0DH
ADCRH
−
−
−
−
−
−
−
−
R
−
√
−
00H
411
FF0EH
ADS
0
Note
0
0
0
0
R/W
√
√
−
00H
412, 439
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R
−
−
√
0000H
243
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
−
−
√
0000H
244
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
−
−
√
0000H
244
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF06H
P6
−
FF0FH
FF10H
TM00
FF11H
FF12H
CR000
FF13H
FF14H
CR010
FF15H
FF16H to
−
FF19H
FF1AH
CMP01
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
338
FF1BH
CMP11
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
338
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF1CH to
−
FF1EH
FF1FH
TM51
−
−
−
−
−
−
−
−
R
−
√
−
00H
317
FF20H
PM0
1
1
1
1
1
1
PM01
PM00
R/W
√
√
−
FFH
167, 256
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
1
1
PM23
PM22
PM21
PM20
√
√
−
−
FF21H
FF22H
FF23H
PM2
PM3
1
1
1
1
1
1
1
PM30
FF24H
−
−
−
−
−
−
−
−
−
FF25H
−
−
−
−
−
−
−
−
−
R/W
R/W
−
FFH
167, 415,
440
√
√
−
−
−
−
−
−
−
−
−
−
−
FFH
167, 324,
345
Note This bit is incorporated only in products with operational amplifier.
Remark For a bit name enclosed in angle brackets (), the bit name is defined as a reserved word in the RA78K0, and
is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
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Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
FF26H
PM6
FF27H
−
FF28H
ADM0
FF29H
−
7
6
5
4
3
2
1
0
1
1
1
1
1
1
PM61
PM60
−
−
−
−
−
−
−
0
FR2
FR1
FR0
LV1
−
−
−
−
−
−
1
8
16
R/W
√
√
−
FFH
−
−
−
−
−
−
−
LV0
R/W
√
√
−
00H
405
−
−
−
−
−
−
−
FF2AH
POM6
0
0
0
0
0
0
FF2BH
FPCTL
0
0
0
0
0
0
0
FF2CH
−
−
−
−
−
−
−
−
0
0
RSTM
0
0
0
0
FF2DH
FF2EH
RSTMASK
ADPC0
FF30H
FF31H
FF32H
FF33H
FF34H
−
00H
R/W
√
√
−
00H
713
−
−
−
−
−
−
−
0
R/W
√
√
−
00H
504
180
181, 413,
R/W
√
√
−
−
−
−
−
−
−
−
PU00
R/W
√
√
−
00H
177
−
−
−
−
−
−
−
−
−
−
−
−
−
PU30
R/W
√
√
−
00H
177
−
−
−
−
−
−
−
PU61
PU60
R/W
√
√
−
00H
177
−
−
−
−
−
−
−
−
−
0
0
R/W
√
√
−
20H
177
0
−
−
−
−
−
−
−
0
0
0
0
0
0
PU01
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
−
−
−
−
−
−
−
0
0
0
0
0
0
−
−
−
−
−
−
−
180, 464,
√
0
PU3
504, 573
√
0
PU0
167, 463,
R/W
POM61 POM60
0
−
FF2FH
page
Address
Reference
Table 3-6. Special Function Register List: 78K0/KY2-L (2/4)
ADPCS3 ADPCS2 ADPCS1 ADPCS0
00H
437
FF35H
FF36H
PU6
FF37H to
−
FF3BH
FF3CH
PU12
0
0
PU125
0
0
0
FF3DH
RMC
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
691
FF3EH
PIM6
0
0
0
0
0
0
PIM61
PIM60
R/W
√
√
−
00H
179, 503
FF3FH
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF40H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
317
FF41H
CR51
−
FF42H
FF43H
TMC51
FF44H to
−
FF47H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
R/W
√
√
−
00H
320
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF48H
EGPCTL0
0
0
0
0
0
0
EGP1
EGP0
R/W
√
√
−
00H
619
FF49H
EGNCTL0
0
0
0
0
0
0
EGN1
EGN0
R/W
√
√
−
00H
619
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
ISC1
ISC0
R/W
√
√
−
00H
463
PS61
PS60
CL6
SL6
ISRM6
R/W
√
√
−
01H
454
FF4AH to
−
FF4EH
FF4FH
ISC
FF50H
ASIM6
Remark For a bit name enclosed in angle brackets (), the bit name is defined as a reserved word in the RA78K0, and
is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
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Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
−
FF53H
ASIS6
0
0
0
0
0
PE6
FE6
FF54H
−
−
−
−
−
−
−
−
FF55H
ASIF6
0
0
0
0
0
0
FF56H
CKSR6
0
0
0
0
TPS63
TPS62
FF57H
BRGC6
FF51H
page
Address
Reference
Table 3-6. Special Function Register List: 78K0/KY2-L (3/4)
1
8
16
−
−
−
−
−
−
OVE6
R
−
√
−
00H
457
−
−
−
−
−
−
−
TXBF6 TXSF6
R
−
√
−
00H
458
TPS61 TPS60
R/W
−
√
−
00H
458
MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60
R/W
−
√
−
FFH
460
16H
461
FF52H
FF58H
ASICL6
FF59H to
−
FF5FH
FF60H
SBTT6 SBL62
Note1
AMP0M
FF61H to
−
FF6BH
FF6CH
TMHMD1
FF6DH
TMCYC1
−
−
−
−
SBL61
SBL60
DIR6
TXDLV6
R/W
√
√
−
−
−
−
−
−
−
−
−
AMP0
AMP0
VG1
VG0
R/W
√
√
−
00H
436
−
−
−
−
−
−
−
−
R/W
√
√
−
00H
339
R/W
√
√
−
00H
343
−
−
−
−
−
−
R/W
√
√
−
00H
318
−
−
−
−
−
−
0
0
0
0
−
−
−
−
CKS12 CKS11 CKS10
TMMD
TMMD
0
0
0
0
0
RMC1
−
−
−
−
−
−
−
FF8CH
TCL51
0
0
0
0
0
FF8DH
−
−
−
−
−
−
−
−
−
−
−
−
−
WDTE
−
−
−
−
−
−
−
−
R/W
−
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
R/W
√
√
−
00H
202
0
R/W
√
√
−
R/W
√
√
−
00H
209
R/W
√
√
−
80H
208
R
√
√
−
00H
210, 640
R/W
−
√
−
05H
211, 641
−
√
−
00H
490
−
√
−
00H
490
FF6EH to
FF8BH
to FF98H
FF99H
FF9AH to
FF9EH
FF9FH
OSCCTL
FFA0H
RCM
0
0
0
0
FFA1H
MCM
0
0
0
0
0
FFA2H
MOC
0
0
0
0
FFA3H
OSTC
0
0
0
NRZB1
−
−
TCL512 TCL511 TCL510
0
0
0
MOST11 MOST13 MOST14 MOST15 MOST16
FFA4H
OSTS
0
0
0
0
0
FFA5H
IICA
OSTS2 OSTS1 OSTS0
−
−
−
−
−
−
−
−
R/W
FFA6H
SVA0
−
−
−
−
−
−
−
0
R/W
1AH/
Note2
9AH
Note3
80H
365
207
Notes 1. This register is incorporated only in products with operational amplifier.
2. The reset value of WDTE is determined by setting of option byte.
3. The value of this register is 00H immediately after a reset release but automatically changes to 80H after
oscillation accuracy stabilization of high-speed internal oscillator has been waited.
Remark For a bit name enclosed in angle brackets (), the bit name is defined as a reserved word in the RA78K0,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
84
78K0/Kx2-L
CHAPTER 3 CPU ARCHITECTURE
Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
7
6
5
4
3
2
1
0
1
8
16
page
Address
Reference
Table 3-6. Special Function Register List: 78K0/KY2-L (4/4)
FFA7H
IICACTL0
R/W
√
√
−
00H
492
FFA8H
IICACTL1
R/W
√
√
−
00H
501
FFA9H
IICAF0
R/W
√
√
−
00H
499
FFAAH
IICAS0
R
√
√
−
00H
497
FFABH
−
−
−
−
−
−
−
R
−
√
−
FFACH
−
RESF
0
0
−
0
0
−
0
0
−
WDTRF
0
−
0
0
−
0
0
0
−
0
−
LVIRF
Note1
00H
664
FFADH
IICWL
−
−
−
−
−
−
−
−
R/W
−
√
−
FFH
503
FFAEH
IICWH
−
−
−
−
−
−
−
−
R/W
−
√
−
FFH
503
FFAFH
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
√
√
−
00H
248
PRM001 PRM000
R/W
√
√
−
00H
253
CRC002 CRC001 CRC000
R/W
√
√
−
00H
249
TOC004 TOC001
R/W
√
√
−
00H
251
to FFB9H
FFBAH
TMC00
0
0
0
0
FFBBH
PRM00
ES110
ES100
ES010
ES000
0
0
0
0
0
FFBCH
CRC00
0
FFBDH
TOC00
0
TMC003 TMC002 TMC001
0
FFBEH
LVIM
0
0
0
0
0
R/W
√
√
−
00H
FFBFH
LVIS
0
0
0
0
LVIS3
LVIS2
LVIS1
LVIS0
R/W
√
√
−
00H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
R/W
√
√
00H
598
0
0
0
R/W
√
√
00H
598
FFC0H to
−
FFDFH
FFE0H
IF0L
IF0
FFE1H
IF0H
FFE2H
IF1L
0
0
0
0
0
0
R/W
√
√
IF1H
0
0
0
0
0
0
0
R/W
√
√
1
1
1
1
R/W
√
√
IF1
FFE3H
FFE4H
MK0L
MK0
FFE5H
MK0H
1
1
1
R/W
√
√
FFE6H
MK1L
1
1
1
1
1
1
R/W
√
√
FFE7H
MK1H
1
1
1
1
1
1
1
R/W
√
√
FFE8H
PR0L
1
1
1
1
R/W
√
√
1
1
1
R/W
√
√
MK1
PR0
FFE9H
PR0H
FFF0H
FFFBH
PCC
Notes 1.
2.
3.
4.
Remark
598
FFH
606
FFH
606
FFH
606
FFH
606
FFH
613
FFH
613
FFH
613
FFH
613
−
1
1
1
1
1
R/W
√
√
1
1
1
1
1
1
R/W
√
√
−
−
−
−
−
−
−
−
−
−
−
−
−
RAM2
RAM1
RAM0
0
ROM3
ROM2
ROM1
ROM0
R/W
−
√
−
CFH
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
PCC2
PCC1
PCC0
R/W
√
√
−
01H
204
−
FFFAH
√
598
1
IMS
FFF1H to
√
00H
00H
1
−
FFEFH
√
675
PR1L
PR1
FFECH to
√
672
Note3
PR1H
FFEAH
FFEBH
√
Note2
√
Note4
699
The reset value of RESF varies depending on the reset source.
The reset values of LVIM vary depending on the reset source and setting of option byte.
The reset values of LVIS vary depending on the reset source.
Reset signal generation makes the setting of the ROM area undefined. Therefore, set the value
corresponding to each product as indicated in Table 3-1 after release of reset.
For a bit name enclosed in angle brackets (), the bit name is defined as a reserved word in the RA78K0,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
85
78K0/Kx2-L
CHAPTER 3 CPU ARCHITECTURE
Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
FF00H
P0
−
FF01H
7
6
5
4
3
2
1
0
0
0
0
0
0
0
P01
P00
−
−
−
−
−
−
−
page
Address
Reference
Table 3-7. Special Function Register List: 78K0/KA2-L (20-pin products) (1/4)
1
8
16
R/W
√
√
−
00H
172
−
−
−
−
−
−
−
FF02H
P2
0
0
P25
P24
P23
P22
P21
P20
R/W
√
√
−
00H
172
FF03H
P3
0
0
0
0
0
P32
P31
P30
R/W
√
√
−
00H
172
FF04H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF05H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
P61
P60
R/W
√
√
−
00H
172
FF07H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF08H
AD ADCRL
−
−
−
−
−
−
−
−
R
−
√
−
00H
411
FF09H
CR
0
0
0
0
0
0
−
−
R
−
−
√
0000H
410
FF0AH
RXB6
−
−
−
−
−
−
−
−
R
−
√
−
FFH
452
FF0BH
TXB6
−
−
−
−
−
−
−
−
R/W
−
√
−
FFH
453
FF0CH
P12
0
0
P125
0
0
P122
P121
0
R
√
√
−
00H
172
FF0DH
ADCRH
−
−
−
−
−
−
−
−
R
−
√
−
00H
411
FF0EH
ADS
0
Note
0
0
0
R/W
√
√
−
00H
412, 439
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R
−
−
√
0000H
243
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
−
−
√
0000H
244
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
−
−
√
0000H
244
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF06H
P6
−
FF0FH
FF10H
TM00
FF11H
FF12H
CR000
FF13H
FF14H
CR010
FF15H
FF16H to
−
FF19H
FF1AH
CMP01
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
338
FF1BH
CMP11
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
338
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF1CH to
−
FF1EH
FF1FH
TM51
−
−
−
−
−
−
−
−
R
−
√
−
00H
317
FF20H
PM0
1
1
1
1
1
1
PM01
PM00
R/W
√
√
−
FFH
167, 256
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
PM25
PM24
PM23
PM22
PM21
PM20
√
√
−
FFH
167, 415,
−
FF21H
FF22H
FF23H
PM2
PM3
1
1
1
1
1
PM32
PM31
PM30
FF24H
−
−
−
−
−
−
−
−
−
FF25H
−
−
−
−
−
−
−
−
−
R/W
R/W
440
√
√
−
FFH
−
−
−
−
−
−
−
−
−
−
167, 324,
345
−
Note This bit is incorporated only in products with operational amplifier.
Remark For a bit name enclosed in angle brackets (), the bit name is defined as a reserved word in the RA78K0, and
is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
86
78K0/Kx2-L
CHAPTER 3 CPU ARCHITECTURE
Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
FF26H
PM6
FF27H
−
FF28H
ADM0
FF29H
−
7
6
5
4
3
2
1
0
1
1
1
1
1
1
PM61
PM60
−
−
−
−
−
−
−
0
FR2
FR1
FR0
LV1
−
−
−
−
−
−
1
8
16
R/W
√
√
−
FFH
−
−
−
−
−
−
−
LV0
R/W
√
√
−
00H
405
−
−
−
−
−
−
−
FF2AH
POM6
0
0
0
0
0
0
FF2BH
FPCTL
0
0
0
0
0
0
0
FF2CH
−
−
−
−
−
−
−
−
0
0
RSTM
0
0
0
0
FF2DH
FF2EH
RSTMASK
ADPC0
FF30H
FF31H
FF32H
FF33H
FF34H
−
00H
R/W
√
√
−
00H
713
−
−
−
−
−
−
−
0
R/W
√
√
−
00H
504
180
181, 413,
R/W
√
√
−
−
−
−
−
−
−
−
PU00
R/W
√
√
−
00H
177
−
−
−
−
−
−
−
−
−
−
−
−
−
PU30
R/W
√
√
−
00H
177
−
−
−
−
−
−
−
PU61
PU60
R/W
√
√
−
00H
177
−
−
−
−
−
−
−
−
−
0
0
R/W
√
√
−
20H
177
−
−
−
−
−
−
0
0
0
0
0
0
PU01
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
PU32
PU31
−
−
−
−
−
−
−
0
0
0
0
0
0
−
−
−
−
−
−
−
180, 464,
√
−
PU3
504, 573
√
0
PU0
167, 463,
R/W
POM61 POM60
0
−
FF2FH
page
Address
Reference
Table 3-7. Special Function Register List: 78K0/KA2-L (20-pin products) (2/4)
ADPCS5 ADPCS4 ADPCS3 ADPCS2 ADPCS1 ADPCS0
00H
437
FF35H
FF36H
PU6
FF37H to
−
FF3BH
FF3CH
PU12
0
0
PU125
0
0
0
FF3DH
RMC
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
691
FF3EH
PIM6
0
0
0
0
0
0
PIM61
PIM60
R/W
√
√
−
00H
179, 503
FF3FH
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF40H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
317
FF41H
CR51
FF42H
−
FF43H
TMC51
FF44H to
−
FF47H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
R/W
√
√
−
00H
320
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF48H
EGPCTL0
0
0
0
0
EGP3
EGP2
EGP1
EGP0
R/W
√
√
−
00H
619
FF49H
EGNCTL0
0
0
0
0
EGN3
EGN2
EGN1
EGN0
R/W
√
√
−
00H
619
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
ISC1
ISC0
R/W
√
√
−
00H
463
PS61
PS60
CL6
SL6
ISRM6
R/W
√
√
−
01H
454
FF4AH to
−
FF4EH
FF4FH
ISC
FF50H
ASIM6
Remark For a bit name enclosed in angle brackets (), the bit name is defined as a reserved word in the RA78K0, and
is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
87
78K0/Kx2-L
CHAPTER 3 CPU ARCHITECTURE
Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
−
FF53H
ASIS6
0
0
0
0
0
PE6
FE6
FF54H
−
−
−
−
−
−
−
FF55H
ASIF6
0
0
0
0
0
0
FF56H
CKSR6
0
0
0
0
FF57H
BRGC6
FF51H
page
Address
Reference
Table 3-7. Special Function Register List: 78K0/KA2-L (20-pin products) (3/4)
1
8
16
−
−
−
−
−
−
OVE6
R
−
√
−
00H
457
−
−
−
−
−
−
−
−
TXBF6
TXSF6
R
−
√
−
00H
458
TPS63 TPS62 TPS61 TPS60
R/W
−
√
−
00H
458
MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60
R/W
−
√
−
FFH
460
16H
461
FF52H
FF58H
ASICL6
FF59H to
−
FF5FH
FF60H
SBTT6 SBL62
Note1
AMP0M
FF61H to
−
FF6BH
FF6CH
TMHMD1
FF6DH
TMCYC1
−
−
DIR6
TXDLV6
R/W
√
√
−
−
−
−
−
−
−
−
AMP0
AMP0
VG1
VG0
R/W
√
√
−
00H
436
−
−
−
−
−
−
−
−
R/W
√
√
−
00H
339
−
−
−
−
0
0
0
0
−
−
−
−
CKS12 CKS11 CKS10
TMMD
TMMD
0
0
0
0
RMC1
NRZB1
R/W
√
√
−
00H
343
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
TCL51
0
0
0
0
0
TCL512
R/W
√
√
−
00H
318
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
WDTE
−
−
−
−
−
−
−
−
R/W
−
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
R/W
√
√
−
00H
202
0
R/W
√
√
−
R/W
√
√
−
00H
209
R/W
√
√
−
80H
208
R
√
√
−
00H
210, 640
FF8BH
FF8DH to
FF98H
FF99H
−
SBL60
0
FF6EH to
FF8CH
−
SBL61
−
FF9AH to
FF9EH
FF9FH
OSCCTL
FFA0H
RCM
0
0
0
0
FFA1H
MCM
0
0
0
0
0
FFA2H
MOC
0
0
0
0
FFA3H
OSTC
0
0
0
TCL511 TCL510
0
0
0
MOST11 MOST13 MOST14 MOST15 MOST16
1AH/
Note2
9AH
Note3
80H
365
207
FFA4H
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
R/W
−
√
−
05H
211, 641
FFA5H
IICA
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
490
FFA6H
SVA0
−
−
−
−
−
−
−
0
R/W
−
√
−
00H
490
Notes 1. This register is incorporated only in products with operational amplifier.
2. The reset value of WDTE is determined by setting of option byte.
3. The value of this register is 00H immediately after a reset release but automatically changes to 80H after
oscillation accuracy stabilization of high-speed internal oscillator has been waited.
Remark For a bit name enclosed in angle brackets (), the bit name is defined as a reserved word in the RA78K0,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
88
78K0/Kx2-L
CHAPTER 3 CPU ARCHITECTURE
Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
7
6
5
4
3
2
1
0
1
8
16
page
Address
Reference
Table 3-7. Special Function Register List: 78K0/KA2-L (20-pin products) (4/4)
IICACTL0
R/W
√
√
−
00H
492
FFA8H
IICACTL1
R/W
√
√
−
00H
501
FFA9H
IICAF0
R/W
√
√
−
00H
499
FFAAH
IICAS0
R
√
√
−
00H
497
FFABH
−
−
−
−
−
−
−
R
−
√
−
FFA7H
FFACH
−
RESF
0
0
−
0
0
−
0
0
−
WDTRF
0
−
0
0
−
0
0
0
−
0
−
LVIRF
Note1
00H
664
FFADH
IICWL
−
−
−
−
−
−
−
−
R/W
−
√
−
FFH
503
FFAEH
IICWH
−
−
−
−
−
−
−
−
R/W
−
√
−
FFH
503
FFAFH
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
√
√
−
00H
248
PRM001 PRM000
R/W
√
√
−
00H
253
CRC002 CRC001 CRC000
R/W
√
√
−
00H
249
TOC004 TOC001
R/W
√
√
−
00H
251
to FFB9H
FFBAH
TMC00
0
0
0
0
FFBBH
PRM00
ES110
ES100
ES010
ES000
0
0
0
0
0
FFBCH
CRC00
0
FFBDH
TOC00
0
TMC003 TMC002 TMC001
0
FFBEH
LVIM
0
0
0
0
0
R/W
√
√
−
00H
FFBFH
LVIS
0
0
0
0
LVIS3
LVIS2
LVIS1
LVIS0
R/W
√
√
−
00H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
IF0L
0
0
R/W
√
√
00H
598
IF0H
R/W
√
√
00H
598
FFC0H to
−
FFDFH
FFE0H
IF0
FFE1H
FFE2H
0
0
0
IF1L
0
0
0
0
0
0
R/W
√
√
IF1H
0
0
0
0
0
0
0
R/W
√
√
1
1
R/W
√
√
IF1
FFE3H
FFE4H
MK0L
MK0
FFE5H
MK0H
1
1
1
R/W
√
√
FFE6H
MK1L
1
1
1
1
1
1
R/W
√
√
FFE7H
MK1H
1
1
1
1
1
1
1
R/W
√
√
FFE8H
PR0L
1
1
R/W
√
√
R/W
√
√
MK1
PR0
FFE9H
FFEAH
PR0H
1
1
1
PR1L
1
1
1
1
1
1
R/W
√
√
PR1H
1
1
1
1
1
1
1
R/W
√
√
−
−
−
−
−
−
−
−
−
−
−
RAM2
RAM1
RAM0
0
ROM3
ROM2
ROM1
ROM0
R/W
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
PCC2
PCC1
PCC0
R/W
PR1
FFEBH
FFECH to
−
FFEFH
FFF0H
IMS
FFF1H to
−
FFFAH
FFFBH
PCC
Notes 1.
2.
3.
4.
Remark
√
√
√
√
√
Note2
672
Note3
675
00H
598
00H
598
FFH
606
FFH
606
FFH
606
FFH
606
FFH
613
FFH
613
FFH
613
FFH
613
−
−
−
√
−
CFH
−
−
−
−
−
√
√
−
01H
204
√
Note4
699
The reset value of RESF varies depending on the reset source.
The reset values of LVIM vary depending on the reset source and setting of option byte.
The reset values of LVIS vary depending on the reset source.
Reset signal generation makes the setting of the ROM area undefined. Therefore, set the value
corresponding to each product as indicated in Table 3-1 after release of reset.
For a bit name enclosed in angle brackets (), the bit name is defined as a reserved word in the RA78K0,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
89
78K0/Kx2-L
CHAPTER 3 CPU ARCHITECTURE
Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
P0
7
6
5
4
3
2
1
0
0
0
0
0
0
P02
P01
P00
Note 2
Note 1
FF00H
−
FF01H
FF02H
P2
page
Address
Reference
Table 3-8. Special Function Register List: 78K0/KA2-L (25-pin and 32-pin products) (1/5)
1
8
16
R/W
√
√
−
00H
172
−
−
−
−
−
−
−
−
−
−
−
−
−
−
P27
P26
P25
P24
P23
P22
P21
P20
R/W
√
√
−
00H
172
P37
P36
P35
P34
P33
P32
P31
0
R/W
√
√
−
Note 2
FF03H
P3
00H
172
FF04H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF05H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF06H
P6
FF07H
P7
FF08H
Note 2
AD ADCRL
0
0
0
0
0
0
P61
P60
R/W
√
√
−
00H
172
0
0
0
0
0
P72
P71
P70
R/W
√
√
−
00H
172
Note 2
Note 2
Note 2
−
−
−
R
−
√
−
00H
411
−
−
−
−
−
−
−
FF09H
CR
0
0
0
0
0
0
−
R
−
√
0000H
410
FF0AH
RXB6
−
−
−
−
−
−
−
−
R
−
√
−
FFH
452
FF0BH
TXB6
−
−
−
−
−
−
−
−
R/W
−
√
−
FFH
453
FF0CH
P12
0
0
P125
0
0
P122
P121
0
R
√
√
−
00H
172
FF0DH
ADCRH
−
−
−
−
−
−
−
−
R
−
√
−
00H
411
FF0EH
ADS
0
Note 3
0
0
R/W
√
√
−
00H
412, 439
FF0FH
SIO11
−
−
−
−
−
−
−
−
R
−
√
−
00H
566
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R
−
−
√
0000H
243
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
−
−
√
0000H
244
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
−
−
√
0000H
244
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF10H
TM00
FF11H
FF12H
CR000
FF13H
FF14H
CR010
FF15H
FF16H to
−
Note 3
FF19H
FF1AH
CMP01
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
338
FF1BH
CMP11
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
338
−
−
−
−
−
−
−
−
−
−
−
−
−
−
317
FF1CH to
−
FF1EH
FF1FH
TM51
−
−
−
−
−
−
−
−
R
−
√
−
00H
FF20H
PM0
1
1
1
1
1
PM02
PM01
PM00
R/W
√
√
−
FFH
Note 2
Note 1
−
FF21H
FF22H
PM2
167, 256
−
−
−
−
−
−
−
−
−
−
−
−
−
−
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
R/W
√
√
−
FFH
167, 415,
Note 2
440
Notes 1. 25-pin products only
2. 32-pin products only
3. This bit is incorporated only in products with operational amplifier.
Remark For a bit name enclosed in angle brackets (), the bit name is defined as a reserved word in the RA78K0,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
90
78K0/Kx2-L
CHAPTER 3 CPU ARCHITECTURE
Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
FF23H
PM3
7
6
5
4
3
2
1
0
PM37
PM36
PM35
PM34
PM33
PM32
PM31
1
1
8
16
R/W
√
√
−
FFH
page
Address
Reference
Table 3-8. Special Function Register List: 78K0/KA2-L (25-pin and 32-pin products) (2/5)
167, 324,
345
FF24H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF25H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
1
1
1
1
PM61
PM60
R/W
√
√
−
FFH
P72
P71
P70
R/W
√
√
−
00H
167
1
1
1
1
1
Note 2
Note 2
Note 2
0
FR2
FR1
FR0
LV1
LV0
R/W
√
√
−
00H
405
−
−
−
−
−
−
−
−
√
√
−
00H
FF26H
FF27H
PM6
Note2
P7
FF28H
ADM0
FF29H
−
−
−
−
−
−
−
FF2AH
POM6
0
0
0
0
0
0
FF2BH
FPCTL
0
0
0
0
0
0
0
FF2CH
−
−
−
−
−
−
−
−
0
0
RSTM
0
0
0
0
FF2DH
RSTMASK
FF2EH
ADPC0
POM61 POM60
ADPCS7
Note 2
R/W
167, 463,
ADPCS6 ADPCS5 ADPCS4 ADPCS3 ADPCS2 ADPCS1 ADPCS0
R/W
181, 413,
ADPC1
FF2FH
FF30H
ADPCS10 ADPCS9 ADPCS8
Note 2
PU0
0
0
0
0
0
0
0
0
0
0
PU02
Note 2
R/W
Note 2
Note 2
PU01
PU00
Note 2
Note 1
R/W
√
√
437
−
00H
−
00H
177
FF31H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF32H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
PU37
PU36
PU35
PU34
PU33
PU32
PU31
0
R/W
√
√
−
00H
177
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
PU61
PU60
R/W
√
√
−
00H
177
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
R/W
√
√
−
20H
177
FF3BH
FF3CH
PU12
0
0
PU125
0
0
0
FF3DH
RMC
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
691
FF3EH
PIM6
0
0
0
0
0
0
PIM61
PIM60
R/W
√
√
−
00H
179, 503
−
FF3FH
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF40H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
317
FF41H
Notes
CR51
1. 25-pin products only
2. 32-pin products only
3. This bit is incorporated only in products with operational amplifier.
Remark
For a bit name enclosed in angle brackets (), the bit name is defined as a reserved word in the RA78K0, and
is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
91
78K0/Kx2-L
CHAPTER 3 CPU ARCHITECTURE
Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
FF42H
−
FF43H
TMC51
FF44H to
−
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
0
0
0
0
0
0
−
−
−
−
−
−
page
Address
Reference
Table 3-8. Special Function Register List: 78K0/KA2-L (25-pin and 32-pin products) (3/5)
1
8
16
−
−
−
−
−
−
0
R/W
√
√
−
00H
320
−
−
−
−
−
−
−
−
FF47H
FF48H
EGPCTL0
0
0
EGP5
EGP4
EGP3
EGP2
0
EGP0
R/W
√
√
−
00H
619
FF49H
EGNCTL0
0
0
EGN5
EGN4
EGN3
EGN2
0
EGN0
R/W
√
√
−
00H
619
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
ISC1
ISC0
R/W
√
√
−
00H
463
PS61
PS60
CL6
SL6
ISRM6
R/W
√
√
−
01H
454
−
−
−
−
−
−
−
−
−
−
−
FF4AH to
−
FF4EH
FF4FH
ISC
FF50H
ASIM6
FF51H
−
−
−
−
FF52H
FF53H
ASIS6
0
0
0
0
0
PE6
FE6
OVE6
R
−
√
−
00H
457
FF54H
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF55H
ASIF6
0
0
0
0
0
0
R
−
√
−
00H
458
TPS61 TPS60
R/W
−
√
−
00H
458
FF56H
CKSR6
FF57H
BRGC6
MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60
R/W
−
√
−
FFH
460
FF58H
ASICL6
SBTT6 SBL62
FF59H to
−
0
0
−
−
0
0
TPS63
TPS62
TXBF6 TXSF6
SBL61
SBL60
DIR6
TXDLV6
R/W
√
√
−
16H
461
−
−
−
−
−
−
−
−
R/W
√
√
−
00H
436
−
−
−
−
−
−
R/W
√
√
−
00H
339
−
−
−
−
0
0
0
0
−
−
−
−
FF5FH
FF60H
FF61H to
AMP0M
Note 1
−
−
−
−
−
FF6BH
FF6CH
TMHMD1
FF6DH
TMCYC1
FF6EH to
FF7BH
FF7CH
FF7DH to
CKS12 CKS11 CKS10
TMMD
TMMD
0
0
0
0
0
RMC1
NRZB1
R/W
√
√
−
00H
343
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
565
−
−
−
−
−
−
−
−
−
−
−
−
−
−
11
SSE11
DIR11
0
0
0
R/W
√
√
−
00H
566
0
0
0
R/W
√
√
−
00H
569
−
−
−
−
−
−
−
−
−
−
−
−
TCL51
0
0
0
0
0
R/W
√
√
−
00H
318
−
SOTB11
−
FF87H
FF88H
CSIM11
FF89H
CSIC11
FF8AH to
CKP11 DAP11
CSOT
11
CKS10 CKS10 CKS10
2
1
0
−
−
−
FF8BH
FF8CH
TCL512 TCL511 TCL510
Notes
1. This bit is incorporated only in products with operational amplifier y
Remark
2. The reset value of WDTE is determined by setting of option byte.
For a bit name enclosed in angle brackets (), the bit name is defined as a reserved word in the RA78K0, and is
defined as an sfr variable using the #pragma sfr directive in the CC78K0.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
92
78K0/Kx2-L
CHAPTER 3 CPU ARCHITECTURE
Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
−
WDTE
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
FF8DH to
FF98H
FF99H
FF9AH to
FF9EH
FF9FH
OSCCTL
FFA0H
RCM
0
0
0
0
FFA1H
MCM
0
0
0
0
0
FFA2H
MOC
0
0
0
0
1
8
16
−
−
−
−
−
R/W
−
√
−
−
−
−
−
−
−
−
−
0
0
R/W
√
√
−
00H
202
R/W
√
√
−
R/W
√
√
−
00H
209
R/W
√
√
−
80H
208
0
page
Address
Reference
Table 3-8. Special Function Register List: 78K0/KA2-L (25-pin and 32-pin products) (4/5)
0
0
−
1AH/
Note1
9AH
Note2
80H
−
365
207
R
√
√
−
00H
210, 640
R/W
−
√
−
05H
211, 641
−
R/W
−
√
−
00H
490
0
R/W
−
√
−
00H
490
R/W
√
√
−
00H
492
R/W
√
√
−
00H
501
R/W
√
√
−
00H
499
R
√
√
−
00H
497
−
−
−
−
−
−
FFA3H
OSTC
0
0
0
FFA4H
OSTS
0
0
0
0
0
FFA5H
IICA
−
−
−
−
−
−
−
FFA6H
SVA0
−
−
−
−
−
−
−
FFA7H
IICACTL0
FFA8H
IICACTL1
FFA9H
IICAF0
FFAAH
IICAS0
FFABH
−
−
0
−
0
−
MOST11 MOST13 MOST14 MOST15 MOST16
0
−
0
−
OSTS2 OSTS1 OSTS0
0
−
0
0
−
−
FFACH
RESF
0
0
0
WDTRF
0
0
0
LVIRF
R
−
√
−
FFADH
IICWL
−
−
−
−
−
−
−
−
R/W
−
√
−
FFH
503
√
−
FFH
503
Note3
00H
664
FFAEH
IICWH
−
−
−
−
−
−
−
−
R/W
−
FFAFH
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FFBAH
TMC00
0
0
0
0
R/W
√
√
−
00H
248
FFBBH
PRM00
ES110
ES100
ES010
ES000
0
PRM001 PRM000
R/W
√
√
−
00H
253
FFBCH
CRC00
0
0
0
0
0
CRC002 CRC001 CRC000
R/W
√
√
−
00H
249
TOC00
R/W
√
√
00H
251
FFBEH
LVIM
0
0
0
0
0
R/W
√
√
FFBFH
LVIS
0
0
0
0
LVIS3
LVIS2
R/W
√
√
to FFB9H
Note4
0
TMC003 TMC002 TMC001
0
LVIS1
LVIS0
−
−
00H
Note5
−
00H
Note6
672
675
Notes 1. The reset value of WDTE is determined by setting of option byte.
2. The value of this register is 00H immediately after a reset release but automatically changes to 80H after
oscillation accuracy stabilization of high-speed internal oscillator has been waited.
3. The reset value of RESF varies depending on the reset source.
4. 32-pin products only
5. The reset values of LVIM vary depending on the reset source and setting of option byte.
6. The reset value of LVIS varies depending on the reset source.
Remark For a bit name enclosed in angle brackets (), the bit name is defined as a reserved word in the RA78K0,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
93
78K0/Kx2-L
CHAPTER 3 CPU ARCHITECTURE
Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
FFC0H to
−
FFDFH
FFE0H
IF0L
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
0
1
8
16
−
−
−
−
R/W
√
√
R/W
√
√
IF0
IF0H
FFE1H
FFE2H
0
0
IF1L
0
0
0
0
0
0
R/W
√
√
IF1H
0
0
0
0
0
0
0
R/W
√
√
R/W
√
√
IF1
FFE3H
MK0L
FFE4H
MK0
MK1L
1
MK1H
1
1
R/W
√
√
−
R/W
10>
