User’s Manual
16
78K0R/Lx3
User’s Manual: Hardware
16-Bit Single-Chip Microcontrollers
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represents information on the product at the time of publication and is subject to change by
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website (http://www.renesas.com).
www.renesas.com
Rev.5.01
Jun 2011
Notice
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All information included in this document is current as of the date this document is issued. Such information, however, is
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NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction.
If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
How to Use This Manual
Readers
This manual is intended for user engineers who wish to understand the functions of the
78K0R/Lx3 microcontrollers and design and develop application systems and programs for
these devices.
The target products are as follows.
• 78K0R/LF3: μPD78F1500A, 78F1501A, 78F1502A, 78F1510A, 78F1512A
• 78K0R/LG3: μPD78F1503A, 78F1504A, 78F1505A, 78F1513A, 78F1515A
• 78K0R/LH3: μPD78F1506A, 78F1507A, 78F1508A, 78F1516A, 78F1518A
Purpose
This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization
The manual for the 78K0R/Lx3 microcontrollers is separated into two parts: this manual and
the instructions edition (common to the 78K0R Microcontroller Series).
78K0R/Lx3
78K0R Microcontrollers
Preliminary User’s Manual
User’s Manual
(This Manual)
Instructions
• Pin functions
• CPU functions
• Internal block functions
• Instruction set
• Interrupts
• Explanation of each instruction
• Other on-chip peripheral functions
• Electrical specifications
How to Read This Manual
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark “” shows major
revised points. The revised points can be easily searched by copying an “” in the
PDF file and specifying it in the “Find what.” field.
• How to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a reserved
word in the RA78K0R, and is defined as an sfr variable using the #pragma sfr
directive in the CC78K0R.
• To know details of the 78K0R Series instructions:
→ Refer to the separate document 78K0R Microcontrollers Instructions User’s
Manual (R01US0029E).
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note:
Footnote for item marked with Note in the text
Caution:
Information requiring particular attention
Remark:
Supplementary information
...×××× or ××××B
Numerical representations: Binary
...××××
Decimal
Hexadecimal
Related Documents
...××××H
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
78K0R/Lx3 User’s Manual Hardware
This manual
78K0R Microcontrollers Instructions User’s Manual
R01US0029E
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name
CC78K0R Ver. 2.00 C Compiler
RA78K0R Ver. 1.20 Assembler Package
SM+ System Simulator
Document No.
Operation
U18549E
Language
U18548E
Operation
U18547E
Language
U18546E
Operation
U18601E
User Open Interface
U18212E
PM+ Ver. 6.30
U18416E
ID78K0R-QB Ver. 3.20 Integrated Debugger
Operation
U17839E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name
Document No.
QB-78K0RLX3 In-Circuit Emulator
U19336E
QB-MINI2 On-Chip Debug Emulator with Programming Function
U18371E
Documents Related to Flash Memory Programming (User’s Manuals)
Document Name
Document No.
PG-FP5 Flash Memory Programmer
QB-Programmer Programming GUI
R20UT0008E
Operation
U18527E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
Other Documents
Document Name
Document No.
RENESAS MICROCOMPUTER GENERAL CATALOG
R01CS0001E
SEMICONDUCTOR SELECTION GUIDE − Products and Packages −
X13769X
Semiconductor Device Mount Manual
Note
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.renesas.com/prod/package/manual/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
All trademarks and registered trademarks are the property of their respective owners.
EEPROM is a trademark of Renesas Electronics Corporation.
Windows is a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States
and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
CONTENTS
CHAPTER 1 OUTLINE............................................................................................................................... 1
1.1 Features........................................................................................................................................... 1
1.2 Ordering Information...................................................................................................................... 3
1.3 Pin Configuration (Top View) ........................................................................................................ 4
1.3.1 78K0R/LF3 ........................................................................................................................................ 4
1.3.2 78K0R/LG3 ....................................................................................................................................... 7
1.3.3 78K0R/LH3...................................................................................................................................... 10
1.4 Block Diagram .............................................................................................................................. 13
1.4.1 78K0R/LF3 ...................................................................................................................................... 13
1.4.2 78K0R/LG3 ..................................................................................................................................... 15
1.4.3 78K0R/LH3...................................................................................................................................... 17
1.5 Outline of Functions..................................................................................................................... 19
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 23
2.1 Pin Function List .......................................................................................................................... 23
2.1.1 78K0R/LF3 ...................................................................................................................................... 24
2.1.2 78K0R/LG3 ..................................................................................................................................... 30
2.1.3 78K0R/LH3...................................................................................................................................... 36
2.2 Description of Pin Functions ...................................................................................................... 43
2.2.1 P00 to P02 ...................................................................................................................................... 43
2.2.2 P10 to P17 ...................................................................................................................................... 44
2.2.3 P20 to P27 ...................................................................................................................................... 46
2.2.4 P30 to P34 ...................................................................................................................................... 47
2.2.5 P40, P41 ......................................................................................................................................... 48
2.2.6 P50 to P57 ...................................................................................................................................... 49
2.2.7 P60, P61 ......................................................................................................................................... 50
2.2.8 P70 to P77 ...................................................................................................................................... 51
2.2.9 P80 to P87 ...................................................................................................................................... 52
2.2.10 P90 to P97 .................................................................................................................................... 53
2.2.11 P100 to P102 ................................................................................................................................ 54
2.2.12 P110, P111 ................................................................................................................................... 54
2.2.13 P120 to P124 ................................................................................................................................ 55
2.2.14 P130.............................................................................................................................................. 56
2.2.15 P140 to P147 ................................................................................................................................ 56
2.2.16 P150 to P152, P157 ...................................................................................................................... 57
2.2.17 COM0 to COM7............................................................................................................................. 57
2.2.18 SEGxx ........................................................................................................................................... 57
2.2.19 VLC0 to VLC3 ............................................................................................................................... 57
2.2.20 VREFOUT/AVREFP (μ PD78F150xA only).................................................................................. 58
2.2.21 AVREF (μ PD78F151xA only) ....................................................................................................... 58
2.2.22 RESET .......................................................................................................................................... 58
2.2.23 REGC............................................................................................................................................ 58
2.2.24 FLMD0 .......................................................................................................................................... 58
2.2.25 AVDD0, AVDD1, AVDD, EVDD1, AVSS, EVDD, EVSS, VDD, VSS ............................................. 59
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 60
2.3.1 78K0R/LF3 ...................................................................................................................................... 60
2.3.2 78K0R/LG3 ..................................................................................................................................... 63
2.3.3 78K0R/LH3...................................................................................................................................... 66
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 74
3.1 Memory Space .............................................................................................................................. 74
3.1.1 Internal program memory space ..................................................................................................... 79
3.1.2 Mirror area....................................................................................................................................... 81
3.1.3 Internal data memory space............................................................................................................ 83
3.1.4 Special function register (SFR) area ............................................................................................... 84
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ...................... 84
3.1.6 Data memory addressing ................................................................................................................ 85
3.2 Processor Registers..................................................................................................................... 88
3.2.1 Control registers .............................................................................................................................. 88
3.2.2 General-purpose registers............................................................................................................... 90
3.2.3 ES and CS registers........................................................................................................................ 92
3.2.4 Special function registers (SFRs) .................................................................................................... 93
3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) .......................... 99
3.3 Instruction Address Addressing............................................................................................... 108
3.3.1 Relative addressing....................................................................................................................... 108
3.3.2 Immediate addressing ................................................................................................................... 108
3.3.3 Table indirect addressing .............................................................................................................. 109
3.3.4 Register direct addressing............................................................................................................. 110
3.4 Addressing for Processing Data Addresses ........................................................................... 111
3.4.1 Implied addressing ........................................................................................................................ 111
3.4.2 Register addressing ...................................................................................................................... 111
3.4.3 Direct addressing .......................................................................................................................... 112
3.4.4 Short direct addressing ................................................................................................................. 113
3.4.5 SFR addressing ............................................................................................................................ 114
3.4.6 Register indirect addressing.......................................................................................................... 115
3.4.7 Based addressing.......................................................................................................................... 116
3.4.8 Based indexed addressing ............................................................................................................ 119
3.4.9 Stack addressing........................................................................................................................... 120
CHAPTER 4 PORT FUNCTIONS ......................................................................................................... 121
4.1 Port Functions ............................................................................................................................ 121
4.2 Port Configuration...................................................................................................................... 129
4.2.1 Port 0............................................................................................................................................. 130
4.2.2 Port 1............................................................................................................................................. 133
4.2.3 Port 2............................................................................................................................................. 138
4.2.4 Port 3............................................................................................................................................. 142
4.2.5 Port 4............................................................................................................................................. 144
4.2.6 Port 5............................................................................................................................................. 146
4.2.7 Port 6............................................................................................................................................. 150
4.2.8 Port 7............................................................................................................................................. 151
4.2.9 Port 8............................................................................................................................................. 156
4.2.10 Port 9........................................................................................................................................... 162
4.2.11 Port 10......................................................................................................................................... 165
4.2.12 Port 11......................................................................................................................................... 167
4.2.13 Port 12......................................................................................................................................... 168
4.2.14 Port 13......................................................................................................................................... 172
4.2.15 Port 14......................................................................................................................................... 173
4.2.16 Port 15......................................................................................................................................... 176
4.3 Registers Controlling Port Function ........................................................................................ 180
4.4 Port Function Operations .......................................................................................................... 197
4.4.1 Writing to I/O port .......................................................................................................................... 197
4.4.2 Reading from I/O port.................................................................................................................... 197
4.4.3 Operations on I/O port................................................................................................................... 197
4.4.4 Connecting to external device with different power potential (2.5 V, 3 V)...................................... 198
4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function........... 200
4.6 Cautions on 1-bit Manipulation Instruction for Port Register n (Pn) .................................... 205
CHAPTER 5 CLOCK GENERATOR .................................................................................................... 206
5.1
5.2
5.3
5.4
Functions of Clock Generator................................................................................................... 206
Configuration of Clock Generator ............................................................................................ 207
Registers Controlling Clock Generator.................................................................................... 209
System Clock Oscillator ............................................................................................................ 222
5.4.1 X1 oscillator................................................................................................................................... 222
5.4.2 XT1 oscillator ................................................................................................................................ 222
5.4.3 Internal high-speed oscillator ........................................................................................................ 226
5.4.4 Internal low-speed oscillator.......................................................................................................... 226
5.4.5 Prescaler ....................................................................................................................................... 226
5.5 Clock Generator Operation ....................................................................................................... 227
5.6 Controlling Clock........................................................................................................................ 232
5.6.1 Example of controlling high-speed system clock ........................................................................... 232
5.6.2 Example of controlling internal high-speed oscillation clock.......................................................... 235
5.6.3 Example of controlling subsystem clock........................................................................................ 237
5.6.4 Example of controlling internal low-speed oscillation clock ........................................................... 239
5.6.5 CPU clock status transition diagram.............................................................................................. 240
5.6.6 Condition before changing CPU clock and processing after changing CPU clock ........................ 247
5.6.7 Time required for switchover of CPU clock and main system clock .............................................. 249
5.6.8 Conditions before clock oscillation is stopped ............................................................................... 250
CHAPTER 6 TIMER ARRAY UNIT...................................................................................................... 251
6.1 Functions of Timer Array Unit................................................................................................... 253
6.1.1 Functions of each channel when it operates independently .......................................................... 253
6.1.2 Functions of each channel when it operates with another channel ............................................... 254
6.1.3 LIN-bus supporting function (channel 7 of timer array unit 0 only) ................................................ 254
6.2 Configuration of Timer Array Unit ............................................................................................ 255
6.3 Registers Controlling Timer Array Unit.................................................................................... 261
6.4 Channel Output (TOpq pin) Control ......................................................................................... 289
6.4.1 TOpq pin output circuit configuration............................................................................................. 289
6.4.2 TOpq Pin Output Setting ............................................................................................................... 290
6.4.3 Cautions on Channel Output Operation ........................................................................................ 291
6.4.4 Collective manipulation of TOpq bits ............................................................................................. 294
6.4.5 Timer Interrupt and TOpq Pin Output at Operation Start............................................................... 295
6.5 Channel Input Control................................................................................................................ 296
6.5.1 Edge detection circuit .................................................................................................................... 296
6.6 Basic Function of Timer Array Unit .......................................................................................... 297
6.6.1 Overview of single-operation function and combination operation function................................... 297
6.6.2 Basic rules of combination operation function ............................................................................... 297
6.6.3 Applicable range of basic rules of combination operation function ................................................ 298
6.7 Operation of Timer Array Unit as Independent Channel ........................................................ 299
6.7.1 Operation as interval timer/square wave output ............................................................................ 299
6.7.2 Operation as external event counter ............................................................................................. 306
6.7.3 Operation as frequency divider ..................................................................................................... 310
6.7.4 Operation as input pulse interval measurement ............................................................................ 315
6.7.5 Operation as input signal high-/low-level width measurement....................................................... 319
6.8 Operation of Plural Channels of Timer Array Unit .................................................................. 323
6.8.1 Operation as PWM function .......................................................................................................... 323
6.8.2 Operation as one-shot pulse output function................................................................................. 330
6.8.3 Operation as multiple PWM output function .................................................................................. 337
CHAPTER 7 REAL-TIME COUNTER................................................................................................... 345
7.1
7.2
7.3
7.4
Functions of Real-Time Counter............................................................................................... 345
Configuration of Real-Time Counter ........................................................................................ 345
Registers Controlling Real-Time Counter................................................................................ 347
Real-Time Counter Operation ................................................................................................... 362
7.4.1 Starting operation of real-time counter .......................................................................................... 362
7.4.2 Shifting to STOP mode after starting operation............................................................................. 363
7.4.3 Reading/writing real-time counter.................................................................................................. 364
7.4.4 Setting alarm of real-time counter ................................................................................................. 366
7.4.5 1 Hz output of real-time counter .................................................................................................... 367
7.4.6 32.768 kHz output of real-time counter ......................................................................................... 367
7.4.7 512 Hz or 16.384 kHz output of real-time counter ......................................................................... 368
7.4.8 Example of watch error correction of real-time counter ................................................................. 369
CHAPTER 8 WATCHDOG TIMER ....................................................................................................... 374
8.1
8.2
8.3
8.4
Functions of Watchdog Timer................................................................................................... 374
Configuration of Watchdog Timer ............................................................................................ 375
Register Controlling Watchdog Timer...................................................................................... 376
Operation of Watchdog Timer................................................................................................... 377
8.4.1 Controlling operation of watchdog timer ........................................................................................ 377
8.4.2 Setting overflow time of watchdog timer........................................................................................ 378
8.4.3 Setting window open period of watchdog timer ............................................................................. 379
8.4.4 Setting watchdog timer interval interrupt ....................................................................................... 380
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER................................................. 381
9.1
9.2
9.3
9.4
Functions of Clock Output/Buzzer Output Controller ............................................................ 381
Configuration of Clock Output/Buzzer Output Controller...................................................... 382
Registers Controlling Clock Output/Buzzer Output Controller ............................................. 382
Operations of Clock Output/Buzzer Output Controller .......................................................... 384
9.4.1 Operation as output pin ................................................................................................................. 384
CHAPTER 10 12-BIT A/D CONVERTER (μ PD78F150xA),
10-BIT A/D CONVERTER (μ PD78F151xA) .................................................................. 385
10.1 Function of A/D Converter....................................................................................................... 385
10.2 Configuration of A/D Converter .............................................................................................. 388
10.3 Registers Used in A/D Converter............................................................................................ 390
10.4 A/D Converter Operations ....................................................................................................... 403
10.4.1 Basic operations of A/D converter ............................................................................................... 403
10.4.2 Input voltage and conversion results ........................................................................................... 405
10.4.3 A/D converter operation modes................................................................................................... 406
10.5 How to Read A/D Converter Characteristics Table............................................................... 412
10.6 Cautions for A/D Converter ..................................................................................................... 414
CHAPTER 11 D/A CONVERTER (μ PD78F150xA only) .................................................................... 418
11.1
11.2
11.3
11.4
Function of D/A Converter....................................................................................................... 418
Configuration of D/A Converter .............................................................................................. 418
Registers Used in D/A Converter............................................................................................ 420
Operation of D/A Converter..................................................................................................... 423
11.4.1 Operation in normal mode........................................................................................................... 423
11.4.2 Operation in real-time output mode ............................................................................................. 423
11.5 Cautions for D/A Converter ..................................................................................................... 424
CHAPTER 12 OPERATIONAL AMPLIFIER (μ PD78F150xA only).................................................... 425
12.1
12.2
12.3
12.4
Function of Operational Amplifier .......................................................................................... 425
Configuration of Operational Amplifier.................................................................................. 425
Amplifier Registers Used in Operational Amplifier............................................................... 427
Operational Amplifier Operations........................................................................................... 433
12.4.1 Single AMP Mode........................................................................................................................ 433
CHAPTER 13 VOLTAGE REFERENCE (μ PD78F150xA only)........................................................... 434
13.1
13.2
13.3
13.4
Function of Voltage Reference ............................................................................................... 434
Configuration of Voltage Reference ....................................................................................... 434
Amplifier Registers Used in Voltage Reference.................................................................... 435
Voltage Reference Operations ................................................................................................ 437
13.4.1 Reference voltage output mode .................................................................................................. 437
13.5 Cautions for Voltage Reference.............................................................................................. 437
CHAPTER 14 SERIAL ARRAY UNIT.................................................................................................. 438
14.1 Functions of Serial Array Unit................................................................................................. 439
14.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20) .......................................................................... 439
14.1.2 UART (UART0, UART1, UART2, UART3) .................................................................................. 439
14.1.3 Simplified I2C (IIC10, IIC20)......................................................................................................... 440
14.2 Configuration of Serial Array Unit .......................................................................................... 441
14.3 Registers Controlling Serial Array Unit.................................................................................. 446
14.4 Operation stop mode ............................................................................................................... 469
14.4.1 Stopping the operation by units ................................................................................................... 469
14.4.2 Stopping the operation by channels ............................................................................................ 470
14.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) Communication ................... 472
14.5.1 Master transmission .................................................................................................................... 473
14.5.2 Master reception.......................................................................................................................... 482
14.5.3 Master transmission/reception .................................................................................................... 488
14.5.4 Slave transmission ...................................................................................................................... 496
14.5.5 Slave reception ........................................................................................................................... 505
14.5.6 Slave transmission/reception ...................................................................................................... 511
14.5.7 Calculating transfer clock frequency............................................................................................ 520
14.6 Operation of UART (UART0, UART1, UART2, UART3) Communication ............................. 522
14.6.1 UART transmission ..................................................................................................................... 523
14.6.2 UART reception........................................................................................................................... 533
14.6.3 LIN transmission.......................................................................................................................... 540
14.6.4 LIN reception............................................................................................................................... 543
14.6.5 Calculating baud rate .................................................................................................................. 548
14.7 Operation of Simplified I2C (IIC10, IIC20) Communication ................................................... 552
14.7.1 Address field transmission .......................................................................................................... 553
14.7.2 Data transmission........................................................................................................................ 558
14.7.3 Data reception ............................................................................................................................. 561
14.7.4 Stop condition generation............................................................................................................ 565
14.7.5 Calculating transfer rate .............................................................................................................. 566
14.8 Processing Procedure in Case of Error ................................................................................. 569
14.9 Relationship Between Register Settings and Pins ............................................................... 571
CHAPTER 15 SERIAL INTERFACE IICA ........................................................................................... 578
15.1
15.2
15.3
15.4
Functions of Serial Interface IICA........................................................................................... 578
Configuration of Serial Interface IICA .................................................................................... 581
Registers Controlling Serial Interface IICA............................................................................ 584
I2C Bus Mode Functions........................................................................................................... 596
15.4.1 Pin configuration ......................................................................................................................... 596
15.4.2 Setting transfer clock by using IICWL and IICWH registers ........................................................ 597
2
15.5 I C Bus Definitions and Control Methods .............................................................................. 598
15.5.1 Start conditions ........................................................................................................................... 598
15.5.2 Addresses ................................................................................................................................... 599
15.5.3 Transfer direction specification.................................................................................................... 599
15.5.4 Acknowledge (ACK) .................................................................................................................... 600
15.5.5 Stop condition ............................................................................................................................. 601
15.5.6 Wait ............................................................................................................................................. 602
15.5.7 Canceling wait ............................................................................................................................. 604
15.5.8 Interrupt request (INTIICA) generation timing and wait control ................................................... 605
15.5.9 Address match detection method ................................................................................................ 606
15.5.10 Error detection........................................................................................................................... 606
15.5.11 Extension code.......................................................................................................................... 606
15.5.12 Arbitration.................................................................................................................................. 607
15.5.13 Wakeup function........................................................................................................................ 609
15.5.14 Communication reservation....................................................................................................... 612
15.5.15 Cautions .................................................................................................................................... 616
15.5.16 Communication operations........................................................................................................ 617
15.5.17 Timing of I2C interrupt request (INTIICA) occurrence ................................................................ 625
15.6 Timing Charts ........................................................................................................................... 646
CHAPTER 16 LCD CONTROLLER/DRIVER ....................................................................................... 661
16.1
16.2
16.3
16.4
16.5
Functions of LCD Controller/Driver........................................................................................ 661
Configuration of LCD Controller/Driver ................................................................................. 665
Registers Controlling LCD Controller/Driver......................................................................... 667
LCD Display Data Memory....................................................................................................... 675
Setting LCD Controller/Driver ................................................................................................. 678
16.6 Common and Segment Signals .............................................................................................. 680
16.7 Display Modes .......................................................................................................................... 687
16.7.1 Static display example................................................................................................................. 687
16.7.2 Two-time-slice display example .................................................................................................. 690
16.7.3 Three-time-slice display example ................................................................................................ 693
16.7.4 Four-time-slice display example .................................................................................................. 697
16.7.5 Eight-time-slice display example ................................................................................................. 700
16.8 Supplying LCD Drive Voltages VLC0, VLC1, VLC2, and VLC3 ............................................ 703
16.8.1 External resistance division method ............................................................................................ 703
16.8.2 Internal voltage boosting method ................................................................................................ 704
16.8.3 Capacitor split method................................................................................................................. 705
16.9 Selection of LCD Display Data ................................................................................................ 706
16.9.1 A-pattern area and B-pattern area data display .......................................................................... 706
16.9.2 Blinking display (Alternately displaying A-pattern and B-pattern area data) ................................ 707
CHAPTER 17 MULTIPLIER/DIVIDER ................................................................................................... 708
17.1
17.2
17.3
17.4
Functions of Multiplier/Divider ............................................................................................. 708
Configuration of Multiplier/Divider ....................................................................................... 708
Register Controlling Multiplier/Divider ................................................................................ 713
Operations of Multiplier/Divider............................................................................................ 714
17.4.1
Multiplication operation............................................................................................................ 714
17.4.2
Division operation .................................................................................................................... 715
CHAPTER 18 DMA CONTROLLER ..................................................................................................... 717
18.1
18.2
18.3
18.4
Functions of DMA Controller .................................................................................................. 717
Configuration of DMA Controller ............................................................................................ 718
Registers Controlling DMA Controller ................................................................................... 721
Operation of DMA Controller................................................................................................... 724
18.4.1 Operation procedure ................................................................................................................... 724
18.4.2 Transfer mode ............................................................................................................................. 725
18.4.3 Termination of DMA transfer ....................................................................................................... 725
18.5 Example of Setting of DMA Controller ................................................................................... 725
18.5.1 CSI consecutive transmission ..................................................................................................... 725
18.5.2 CSI master reception................................................................................................................... 727
18.5.3 CSI transmission/reception ......................................................................................................... 729
18.5.4 Consecutive capturing of A/D conversion results ........................................................................ 731
18.5.5 UART consecutive reception + ACK transmission ...................................................................... 733
18.5.6 Holding DMA transfer pending by DWAITn ................................................................................. 735
18.5.7 Forced termination by software ................................................................................................... 736
18.6 Cautions on Using DMA Controller ........................................................................................ 738
CHAPTER 19 INTERRUPT FUNCTIONS.............................................................................................. 740
19.1
19.2
19.3
19.4
Interrupt Function Types ......................................................................................................... 740
Interrupt Sources and Configuration ..................................................................................... 741
Registers Controlling Interrupt Functions............................................................................. 746
Interrupt Servicing Operations ............................................................................................... 764
19.4.1 Maskable interrupt acknowledgment ........................................................................................... 764
19.4.2 Software interrupt request acknowledgment ............................................................................... 766
19.4.3 Multiple interrupt servicing........................................................................................................... 767
19.4.4 Interrupt request hold .................................................................................................................. 770
CHAPTER 20 KEY INTERRUPT FUNCTION ..................................................................................... 771
20.1 Functions of Key Interrupt ...................................................................................................... 771
20.2 Configuration of Key Interrupt ................................................................................................ 771
20.3 Register Controlling Key Interrupt ......................................................................................... 772
CHAPTER 21 STANDBY FUNCTION .................................................................................................. 773
21.1 Standby Function and Configuration ..................................................................................... 773
21.1.1 Standby function ......................................................................................................................... 773
21.1.2 Registers controlling standby function......................................................................................... 773
21.2 Standby Function Operation ................................................................................................... 776
21.2.1 HALT mode ................................................................................................................................. 776
21.2.2 STOP mode ................................................................................................................................ 782
CHAPTER 22 RESET FUNCTION........................................................................................................ 788
22.1 Register for Confirming Reset Source ................................................................................... 797
CHAPTER 23 POWER-ON-CLEAR CIRCUIT...................................................................................... 798
23.1
23.2
23.3
23.4
Functions of Power-on-Clear Circuit...................................................................................... 798
Configuration of Power-on-Clear Circuit ............................................................................... 799
Operation of Power-on-Clear Circuit ...................................................................................... 799
Cautions for Power-on-Clear Circuit ...................................................................................... 802
CHAPTER 24 LOW-VOLTAGE DETECTOR ....................................................................................... 804
24.1
24.2
24.3
24.4
Functions of Low-Voltage Detector........................................................................................ 804
Configuration of Low-Voltage Detector ................................................................................. 805
Registers Controlling Low-Voltage Detector......................................................................... 805
Operation of Low-Voltage Detector ........................................................................................ 810
24.4.1 When used as reset .................................................................................................................... 811
24.4.2 When used as interrupt ............................................................................................................... 817
24.5 Cautions for Low-Voltage Detector ........................................................................................ 823
CHAPTER 25 REGULATOR ................................................................................................................. 827
25.1 Regulator Overview.................................................................................................................. 827
25.2 Registers Controlling Regulator ............................................................................................. 827
CHAPTER 26 OPTION BYTE............................................................................................................... 829
26.1 Functions of Option Bytes ...................................................................................................... 829
26.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H) ....................................................... 829
26.1.2 On-chip debug option byte (000C3H/ 010C3H)........................................................................... 830
26.2 Format of User Option Byte .................................................................................................... 830
26.3 Format of On-chip Debug Option Byte................................................................................... 832
26.4 Setting of Option Byte.............................................................................................................. 833
CHAPTER 27 FLASH MEMORY .......................................................................................................... 834
27.1 Writing with Flash Memory Programmer ............................................................................... 834
27.2 Programming Environment ..................................................................................................... 834
27.3 Communication Mode .............................................................................................................. 835
27.4 Connection of Pins on Board.................................................................................................. 837
27.4.1 FLMD0 pin................................................................................................................................... 837
27.4.2 TOOL0 pin................................................................................................................................... 838
27.4.3 RESET pin .................................................................................................................................. 838
27.4.4 Port pins ...................................................................................................................................... 838
27.4.5 REGC pin .................................................................................................................................... 838
27.4.6 X1 and X2 pins ............................................................................................................................ 838
27.4.7 Power supply............................................................................................................................... 839
27.5 Registers Controlling Flash Memory...................................................................................... 839
27.6 Programming Method .............................................................................................................. 840
27.6.1 Controlling flash memory............................................................................................................. 840
27.6.2 Flash memory programming mode.............................................................................................. 840
27.6.3 Selecting communication mode .................................................................................................. 841
27.6.4 Communication commands ......................................................................................................... 841
27.7 Security Settings ...................................................................................................................... 843
27.8 Flash Memory Programming by Self-Programming ............................................................. 845
27.8.1 Boot swap function ...................................................................................................................... 847
27.8.2 Flash shield window function....................................................................................................... 849
27.9 Creating ROM Code to Place Order for Previously Written Product .................................. 850
27.9.1
Procedure for using ROM code to place an order ................................................................... 850
CHAPTER 28 ON-CHIP DEBUG FUNCTION ..................................................................................... 851
28.1 Connecting QB-MINI2 to 78K0R/Lx3 microcontrollers ......................................................... 851
28.2 On-Chip Debug Security ID ..................................................................................................... 852
28.3 Securing of User Resources ................................................................................................... 852
CHAPTER 29 BCD CORRECTION CIRCUIT ..................................................................................... 854
29.1 BCD Correction Circuit Function............................................................................................ 854
29.2 Registers Used by BCD Correction Circuit ........................................................................... 854
29.3 BCD Correction Circuit Operation .......................................................................................... 855
CHAPTER 30 INSTRUCTION SET........................................................................................................ 857
30.1 Conventions Used in Operation List ...................................................................................... 857
30.1.1 Operand identifiers and specification methods............................................................................ 857
30.1.2 Description of operation column .................................................................................................. 858
30.1.3 Description of flag operation column ........................................................................................... 859
30.1.4 PREFIX instruction ...................................................................................................................... 859
30.2 Operation List ........................................................................................................................... 860
CHAPTER 31 ELECTRICAL SPECIFICATIONS ................................................................................. 877
CHAPTER 32 PACKAGE DRAWINGS ................................................................................................. 934
32.1
32.2
32.3
78K0R/LF3............................................................................................................................... 934
78K0R/LG3 .............................................................................................................................. 936
78K0R/LH3 .............................................................................................................................. 937
CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS........................................................... 938
APPENDIX A DEVELOPMENT TOOLS............................................................................................... 940
A.1 Software Package ...................................................................................................................... 943
A.2 Language Processing Software ............................................................................................... 943
A.3 Flash Memory Programming Tools.......................................................................................... 944
A.3.1 When using flash memory programmer PG-FP5 and FL-PR5...................................................... 944
A.3.2 When using on-chip debug emulator with programming function QB-MINI2................................. 944
A.4 Debugging Tools (Hardware).................................................................................................... 945
A.4.1 When using in-circuit emulator QB-78K0RLX3 ............................................................................. 945
A.4.2 When using on-chip debug emulator with programming function QB-MINI2................................. 946
A.5 Debugging Tools (Software)..................................................................................................... 946
APPENDIX B REGISTER INDEX ......................................................................................................... 947
B.1 Register Index (In Alphabetical Order with Respect to Register Names) ............................ 947
B.2 Register Index (In Alphabetical Order with Respect to Register Symbol)........................... 952
APPENDIX C LIST OF CAUTIONS ..................................................................................................... 957
APPENDIX D REVISION HISTORY ..................................................................................................... 996
D.1 Major Revisions in This Edition ............................................................................................... 996
D.2 Revision History of Preceding Editions ................................................................................ 1000
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Rev.5.01
Jun 20, 2011
78K0R/Lx3
RENESAS MCU
CHAPTER 1 OUTLINE
The 78K0R/Lx3 microcontrollers are 16-bit single-chip microcontrollers that include the 78K0R CPU core and
peripheral functions such as ROM/RAM, LCD controller/driver, A/D converter, D/A converter, operational amplifier,
multifunctional serial interfaces, multifunctional timers, real-time counter, and watchdog timer.
1.1 Features
{ Minimum instruction execution time can be changed from high speed (0.05 μs: @ 20 MHz operation with high-speed
system clock) to ultra low-speed (61 μs: @ 32.768 kHz operation with subsystem clock)
{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
{ ROM, RAM capacities
Program Memory
Data Memory
78K0R/LF3
78K0R/LG3
78K0R/LH3
(ROM)
(RAM)
80 pins
100 pins
128 pins
64 KB
4 KB
μ PD78F1500A,
μ PD78F1503A,
μ PD78F1506A,
μ PD78F1510A
μ PD78F1513A
μ PD78F1516A
96 KB
6 KB
μ PD78F1501A
μ PD78F1504A
μ PD78F1507A
128 KB
7 KB
μ PD78F1502A,
μ PD78F1505A,
μ PD78F1508A,
μ PD78F1512A
μ PD78F1515A
μ PD78F1518A
{ On-chip internal high-speed oscillation clock
• 20 MHz internal high-speed s oscillation clock: 20 MHz ± 2.4 %
• 8 MHz internal high-speed s oscillation clock: 8 MHz ± 2 % (when 1.8 V≤VDD Use this pin as a port pin (P40).
(b) In normal operation mode and when on-chip debugging is enabled (OCDENSET = 1) by an
option byte (000C3H)
=> Connect this pin to VDD via an external resistor, and always input a high level to the pin
before reset release.
(c) When on-chip debug function is used, or in write mode of flash memory programmer
=> Use this pin as TOOL0.
Directly connect this pin to the on-chip debug emulator or a flash memory programmer,
or pull it up by connecting it to VDD via an external resistor.
2.2.6 P50 to P57
P50 to P57 function as an I/O port. This port can also be used for serial interface data I/O, timer input, and segment
output of LCD controller/driver.
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P50/RxD3/SEGxx
√ (xx = 30)
√ (xx = 39)
√ (xx = 53)
P51/TxD3/SEGxx
√ (xx = 29)
√ (xx = 38)
√ (xx = 52)
P52/TI02/SEGxx
√ (xx = 28)
√ (xx = 37)
√ (xx = 51)
P53/TI04/SEGxx
√ (xx = 27)
√ (xx = 36)
√ (xx = 50)
P54/SEGxx
√ (xx = 26)
√ (xx = 35)
√ (xx = 49)
P55/SEGxx
√ (xx = 25)
√ (xx = 34)
√ (xx = 48)
P56/SEGxx
√ (xx = 24)
√ (xx = 33)
√ (xx = 47)
P57/SEGxx
√ (xx = 23)
√ (xx = 32)
√ (xx = 46)
The following operation modes can be specified in 1-bit units.
(1) Port mode
P50 to P57 function as an I/O port. P50 to P57 can be set to input or output port in 1-bit units using port mode
register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5).
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CHAPTER 2 PIN FUNCTIONS
(2) Control mode
P50 to P57 function as serial interface data I/O, timer input, and segment output of LCD controller/driver.
(a) RxD3
This is a serial data input pin of serial interface UART3.
(b) TxD3
This is a serial data output pin of serial interface UART3.
(c) TI02, TI04
These are the timer input pins of 16-bit timers 02 and 04.
(d) SEGxx
This is a segment output pin of LCD controller/driver.
2.2.7 P60, P61
P60 and P61 function as an I/O port. This port can also be used for s serial interface IICA data I/O and clock I/O.
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P60/SCL0
−
√
P61/SDA0
−
√
The following operation modes can be specified in 1-bit units.
(1) Port mode
P60 and P61 function as an I/O port. P60 and P61 can be set to input port or output port in 1-bit units using port
mode register 6 (PM6).
Output of P60 and P61 is N-ch open-drain output (6 V tolerance).
(2) Control mode
P60 and P61 function as serial interface IICA clock I/O and data I/O.
(a) SCL0
This is a serial clock I/O pin of serial interface IICA.
(b) SDA0
This is a serial data I/O pin of serial interface IICA.
Caution When using P60/SCL0 and P61/SDA0 as a general-purpose port, stop the operation of serial
interface IICA.
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CHAPTER 2 PIN FUNCTIONS
2.2.8 P70 to P77
P70 to P77 function as an I/O port. This port can also be used for key return input, serial interface clock I/O, and data
I/O.
Input to the P75, and P76 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
port input mode register 7 (PIM7).
Output from the P75, and P77 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port
output mode register 7 (POM7).
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P70/KR0
−
√
P71/KR1
−
√
P72/KR2
−
√
P73/KR3
−
√
P74/KR4
−
√
P75/SCK01
−
√
P76/KR6/SI01
−
√
P77/KR7/SO01
−
√
The following operation modes can be specified in 1-bit units.
(1) Port mode
P70 to P77 function as an I/O port. P70 to P77 can be set to input or output port in 1-bit units using port mode
register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
(2) Control mode
P70 to P77 function as key interrupt input, serial interface clock I/O, and data I/O.
(a) KR0 to KR7
These are the key return input pins
(b) SCK01
This is a clock I/O pin of serial interface CSI01.
(c) SI01
This is a serial data input pin of serial interface CSI01.
(d) SO01
This is a serial data output pin of serial interface CSI01.
Caution To use P75/SCK01/KR5, P76/SI01/KR6, and P77/SO01/KR7, as a general-purpose port, note the serial
array unit 0 setting. For details, refer to Table 14-6 Relationship Between Register Settings and Pins
(Channel 1 of unit 0: CSI01, UART0 Reception).
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CHAPTER 2 PIN FUNCTIONS
2.2.9 P80 to P87
P80 to P87 function as an I/O port. This port can also be used for serial interface clock I/O, data I/O, timer I/O, and
external interrupt request input.
Output from the P80 and P82 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port
output mode register 8 (POM8).
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P80/SCK00/INTP11
−
√
√
P81/RxD0/SI00/INTP9
−
√
√
P82/TxD0/SO00
−
√
√
P83
−
−
√
P84/TO10/TI10
−
−
√
P85/TO11/TI11
−
−
√
P86/TO12/TI12
−
−
√
P87/TO13/TI13
−
−
√
The following operation modes can be specified in 1-bit units.
(1) Port mode
P80 to P87 function as an I/O port. P80 to P87 can be set to input or output port in 1-bit units using port mode
register 8 (PM8). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 8 (PU8).
(2) Control mode
P80 to P87 function as serial interface clock I/O, data I/O, timer I/O, and external interrupt request input.
(a) SCK00
This is a clock I/O pin of serial interface CSI00.
(b) SI00
This is a serial data input pin of serial interface CSI00.
(c) SO00
This is a serial data output pin of serial interface CSI00.
(d) RxD0
This is a serial data input pin for serial interface UART0.
(e) TxD0
This is a serial data output pin for serial interface UART0.
(f) TI10 to TI13
These are the timer input pins of 16-bit timers 10 to 13.
(g) TO10 to TO13
These are the timer output pins of 16-bit timers 10 to 13.
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CHAPTER 2 PIN FUNCTIONS
(h) INTP9, INTP11
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
Caution To use P80/SCK00/INTP11, P81/RxD0/SI00/INTP9, and P82/SO00/TxD0, as a general-purpose port,
note the serial array unit 0 setting. For details, refer to Table 14-5 Relationship Between Register
Settings and Pins (Channel 0 of unit 0: CSI00, UART0 Reception).
2.2.10 P90 to P97
P90 to P97 function as an I/O port. This port can also be used for segment output of LCD controller/driver.
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P90/SEGxx
√ (xx = 22)
√ (xx = 31)
√ (xx = 45)
P91/SEGxx
√ (xx = 21)
√ (xx = 30)
√ (xx = 44)
P92/SEGxx
√ (xx = 20)
√ (xx = 29)
√ (xx = 43)
P93/SEGxx
−
√ (xx = 28)
√ (xx = 42)
P94/SEGxx
−
√ (xx = 27)
√ (xx = 41)
P95/SEGxx
−
√ (xx = 26)
√ (xx = 40)
P96/SEGxx
−
√ (xx = 25)
√ (xx = 39)
P97/SEGxx
−
√ (xx = 24)
√ (xx = 38)
The following operation modes can be specified in 1-bit units.
(1) Port mode
P90 to P97 function as an I/O port. P90 to P97 can be set to input or output port in 1-bit units using port mode
register 9 (PM9). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 9 (PU9).
(2) Control mode
P90 to P97 function as segment output of LCD controller/driver (SEGxx).
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CHAPTER 2 PIN FUNCTIONS
2.2.11 P100 to P102
P100 to P102 function as an I/O port. This port can also be used for segment output of LCD controller/driver.
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P100/SEGxx
√ (xx = 11)
√ (xx = 15)
√ (xx = 29)
P101/SEGxx
−
−
√ (xx = 28)
P102/SEGxx
−
−
√ (xx = 27)
The following operation modes can be specified in 1-bit units.
(1) Port mode
P100 to P102 function as an I/O port. P100 to P102 can be set to input or output port in 1-bit units using port mode
register 10 (PM10). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 10 (PU10).
(2) Control mode
P100 to P102 function as segment output of LCD controller/driver (SEGxx).
2.2.12 P110, P111
P110 and P111 function as an I/O port. This port can also be used for D/A converter analog output.
μ PD78F150xA
μ PD78F151xA
78K0R/LF3
78K0R/LG3
78K0R/LH3
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins)
(100 pins)
(128 pins)
(80 pins)
(100 pins)
(128 pins)
P110/ANO0
√
P110
P111/ANO1
√
P111
The following operation modes can be specified in 1-bit units.
(1) Port mode
P110 and P111 function as an I/O port. P110 and P111 can be set to input or output port in 1-bit units using port
mode register 11 (PM11).
(2) Control mode
P110 and P111 function as D/A converter analog output (ANO0, ANO1).
Caution When using at least one port of P110/ANO0 and P111/ANO1 as a digital port, set AVDD1 to the same
potential as EVDD or VDD.
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2.2.13 P120 to P124
P120 function as an I/O port. P121 to P124 function as an input port. These pins also function as potential input for
external low-voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock,
external clock input for main system clock, and external interrupt request input.
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P120/INTP0/EXLVI
√
P121/X1
√
P122/X2/EXCLK
√
P123/XT1
√
P124/XT2
√
The following operation modes can be specified in 1-bit units.
(1) Port mode
P120 functions as an I/O port. P120 can be set to input port or output port using port mode register 12 (PM12). Use
of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
P121 to P124 function as an input port.
(2) Control mode
P120 to P124 function as potential input for external low-voltage detection, connecting resonator for main system
clock, connecting resonator for subsystem clock, external clock input for main system clock, and external interrupt
request input.
(a) EXLVI
This is a potential input pin for external low-voltage detection.
(b) X1, X2
These are the pins for connecting a resonator for main system clock.
(c) EXCLK
This is an external clock input pin for main system clock.
(d) XT1, XT2
These are the pins for connecting a resonator for subsystem clock.
(e) INTP0
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and
falling edges) can be specified.
Caution The function setting on P121 to P124 is available only once after the reset release. The port once
set for connection to an oscillator cannot be used as an input port unless the reset is performed.
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2.2.14 P130
P130 functions as an output port.
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
√
P130
Remark
The P130 pin outputs a low level when it is used as a port function pin and a reset is effected. If P130 is set
to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU
reset signal (see the figure for Remark in 4.2.14 Port 13).
2.2.15 P140 to P147
P140 to P147 function as an I/O port. This port can also be used for segment output of LCD controller/driver.
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P140/SEGxx
√ (xx = 19)
√ (xx = 23)
√ (xx = 37)
P141/SEGxx
√ (xx = 18)
√ (xx = 22)
√ (xx = 36)
P142/SEGxx
√ (xx = 17)
√ (xx = 21)
√ (xx = 35)
P143/SEGxx
√ (xx = 16)
√ (xx = 20)
√ (xx = 34)
P144/SEGxx
√ (xx = 15)
√ (xx = 19)
√ (xx = 33)
P145/SEGxx
√ (xx = 14)
√ (xx = 18)
√ (xx = 32)
P146/SEGxx
√ (xx = 13)
√ (xx = 17)
√ (xx = 31)
P147/SEGxx
√ (xx = 12)
√ (xx = 16)
√ (xx = 30)
The following operation modes can be specified in 1-bit units.
(1) Port mode
P140 to P147 function as an I/O port. P140 to P147 can be set to input or output port in 1-bit units using port mode
register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14).
(2) Control mode
P140 to P147 function as segment output of LCD controller/driver (SEGxx).
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2.2.16 P150 to P152, P157
P150 to P152 and P157 function as an I/O port. This port can also be used for A/D converter analog input, reference
voltage input, and operational amplifier input.
μ PD78F150xA
μ PD78F151xA
78K0R/LF3
78K0R/LG3
78K0R/LH3
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins)
(100 pins)
(128 pins)
(80 pins)
(100 pins)
(128 pins)
P150/ANI8/AMP2+
−
√
−
P150/ANI8
P151/ANI9
−
√
−
√
P152/ANI10
−
√
−
P157/ANI15/AVREFM
√
√
P157/ANI15
The following operation modes can be specified in 1-bit units.
(1) Port mode
P150 to P152 and P157 function as an I/O port. P150 to P152 and P157 can be set to input or output port in 1-bit
units using port mode register 15 (PM15).
(2) Control mode
P150 to P152 and P157 function as A/D converter analog input, reference voltage input, and operational amplifier
input.
(a) ANI8 to ANI10, ANI15
These are A/D converter analog input pins.
(b) AVREFM
This is the pin that inputs the negative reference voltage of A/D converter.
(c) AMP2+
This is the pin that the input voltage on the positive side of operational amplifier 2.
Cautions 1. P150/ANI8/AMP2+ to P152/ANI10 and P157/ANI15/AVREFM are set in the digital input (generalpurpose port) mode after release of reset.
2. When using at least one port of P150/ANI8/AMP2+ to P152/ANI10 and P157/ANI15/AVREFM as a
digital port, set AVDD0 to the same potential as EVDD or VDD.
2.2.17 COM0 to COM7
These are common outputs of LCD controller/driver.
2.2.18 SEGxx
These are segment outputs of LCD controller/driver.
Remark
78K0R/LF3: SEG0 to SEG30
78K0R/LG3: SEG0 to SEG39
78K0R/LH3: SEG0 to SEG53
2.2.19 VLC0 to VLC3
These are the pins for inputting a power supply voltage pin for driving the LCD.
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2.2.20 VREFOUT/AVREFP (μ PD78F150xA only)
VREFOUT is an analog reference voltage output pin for voltage reference.
AVREFP is the pin that inputs the positive reference voltage of the A/D converter and D/A converter.
2.2.21 AVREF (μ PD78F151xA only)
AVREF is the pin that inputs the positive reference voltage of the A/D converter.
2.2.22 RESET
This is the active-low system reset input pin.
When the external reset pin is not used, connect this pin directly to EVDD or via a resistor.
When the external reset pin is used, design the circuit based on VDD.
2.2.23 REGC
This is the pin for connecting regulator output (2.4 V) stabilization capacitance for internal operation. Connect this pin
to VSS via a capacitor (0.47 to 1 μF).
Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
REGC
VSS
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
2.2.24 FLMD0
This is a pin for setting flash memory programming mode.
Perform either of the following processing.
(a) In normal operation mode
It is recommended to leave this pin open during normal operation.
The FLMD0 pin must always be kept at the VSS level before reset release but does not have to be pulled down
externally because it is internally pulled down by reset. However, pulling it down must be kept selected (i.e.,
FLMDPUP = “0”, default value) by using bit 7 (FLMDPUP) of the background event control register (BECTL) (see
27.5 (1) Back ground event control register). To pull it down externally, use a resistor of 200 kΩ or smaller.
Self programming and the rewriting of flash memory with the programmer can be prohibited using hardware, by
directly connecting this pin to the VSS pin.
(b) In self programming mode
It is recommended to leave this pin open when using the self programming function. To pull it down externally,
use a resistor of 100 kΩ to 200 kΩ.
In the self programming mode, the setting is switched to pull up in the self programming library.
(c) In flash memory programming mode
Directly connect this pin to a flash memory programmer when data is written by the flash memory programmer.
This supplies a writing voltage of the VDD level to the FLMD0 pin.
The FLMD0 pin does not have to be pulled down externally because it is internally pulled down by reset. To pull
it down externally, use a resistor of 1 kΩ to 200 kΩ.
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2.2.25 AVDD0, AVDD1, AVDD, EVDD1, AVSS, EVDD, EVSS, VDD, VSS
(1) AVDD0 (μ PD78F150xA only)
This is the ground potential pin of A/D converter, operational amplifier, voltage reference, P20 to P27, P150 to P152
and P157.
When using at least one port of ports 2 and 15 as a digital port, or when not using the A/D converter, operational
amplifier, or voltage reference, set AVDD0 to the same potential as EVDD or VDD.
(2) AVDD1 (μ PD78F150xA only)
This is the ground potential pin of D/A converter, P110 and P111.
When using at least one port of ports 11 as a digital port, or when not using the D/A converter set AVDD1 to the same
potential as EVDD or VDD.
(3) AVDD (μ PD78F151xA only)
This is the ground potential pin of A/D converter, P20 to P27, P150 to P152 and P157.
When using at least one port of ports 2 and 15 as a digital port, or when not using the A/D converter, set AVDD to the
same potential as EVDD or VDD.
(4) EVDDI (μ PD78F151xA only)
This is the ground potential pin of P110 and P111.
When using at least one port of ports 11 as a digital port, set EVDD1 to the same potential as EVDD or VDD.
(5) AVSS
This is the ground potential pin of A/D converter, D/A converter, operational amplifier, voltage reference, P20 to P27,
P110, P111, P150 to P152, and P157. Even when the A/D converter, D/A converter, operational amplifier, and
voltage reference is not used, always use this pin with the same potential as EVSS and VSS.
(6) EVDD
This is the positive power supply pin for ports other than P20 to P27, P110, P111, P150 to P152, and P157 as well as
for the RESET and FLMD0 pins.
(7) EVSS
This is the ground potential pin for ports other than P20 to P27, P110, P111, P150 to P152, and P157 as well as for
the RESET and FLMD0 pins.
(8) VDD
This is the positive power supply pin other than ports, RESET, and FLMD0 pins.
(9) VSS
This is the ground potential pin other than ports, RESET, and FLMD0 pins.
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2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
2.3.1 78K0R/LF3
Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins.
Table 2-2. Connection of Unused Pins (78K0R/LF3) (1/3)
Pin Name
P00/CAPH
I/O Circuit Type
I/O
I/O
12-H
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P01/CAPL
P02/VLC3
5-AT
P10/SCK20/SCL20
5-AN
P11/SI20/RxD2/SDA20/
INTP6
P12/SO20/TxD2/TO02
5-AG
P13/SO10/TxD1/TO04
P14/SI10/RxD1/SDA10/
5-AN
INTP4
P15/SCK10/SCL10/INTP7
P20/ANI0/AMP0-
Note 1, 2
P21/ANI1/AMP0O
P22/ANI2/AMP0+
P23/ANI3/AMP1-
Note 1, 2
Note 1, 2
P24/ANI4/AMP1O
P25/ANI5/AMP1+
P26/ANI6
Note 1, 2
Note 1, 2
Note 1, 2
Note 1, 2
P30/TI03/TO00/RTC1HZ/
11-P
Note 3
Input:
11-S
Note 3
Output: Leave open.
11-N
Note 3
11-P
Note 3
11-S
Note 3
11-N
Note 3
11-G
Note 3
8-R
Input:
Independently connect to AVDD0 or AVSS via a resistor.
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
INTP1
P31/TI00/TO03/RTCDIV/
RTCCL/PCLBUZ1/INTP2
P32/TI01/TO01/INTP5/
PCLBUZ0
P33/TI07/TO07/INTP3
P40/TOOL0
Pull this pin up (pulling it down is prohibited).
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P41/TOOL1
5-AG
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P50/SEG30/RxD3
17-Q
P51/SEG29/TxD3
17-P
P52/SEG28/TI02
17-Q
P53/SEG27/TI04
P54/SEG26 to P57/SEG23
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Leave open.
17-P
Notes 1. P20/ANI0/AMP0- to P26/ANI6 are set in the digital input port mode after release of reset.
2.
3.
AMPxx applies to μ PD78F150xA only.
μ PD78F151xA corresponds to type 11-G.
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Table 2-2. Connection of Unused Pins (78K0R/LF3) (2/3)
Pin Name
I/O
I/O Circuit Type
P90/SEG22 to P92/SEG20
I/O
17-P
Recommended Connection of Unused Pins
Input:
P100/SEG11
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Leave open.
P110/ANO0
Note 3
P111/ANO1
Note 3
,
12-A
Note 4
Input:
Independently connect to AVDD1 or AVSS via a resistor.
Output: Leave open.
P120/INTP0/EXLVI
8-R
Input:
I/O
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Note 1
P121/X1
P122/X2/EXCLK
P123/XT1
Note 1
P124/XT2
Note 1
37-C
Input
Independently connect to EVDD or EVSS via a resistor.
Note 1
37-A
P130
3-C
Output
Leave open.
P140/SEG19 to P147/SEG12
17-P
I/O
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Leave open.
P157/ANI15/AVREFM
Note 2, 3
11-T
Note 5
Input:
I/O
Independently connect to AVDD0 or AVSS via a resistor.
Output: Leave open.
SEG0/COM4 to SEG3/COM7
18-F
SEG4 to SEG10
17-T
COM0 to COM3
18-E
−
VLC0 to VLC2
Notes 1.
Output
Leave open.
−
Use recommended connection above in input port mode (see Figure 5-2 Format of Clock Operation Mode
Control Register (CMC)) when these pins are not used.
2.
P157/ANI15/AVREFM is set in the digital input port mode after release of reset.
3.
ANOx and AVREFM apply to μ PD78F150xA only.
4. μ PD78F151xA corresponds to type 5.
5.
μ PD78F151xA corresponds to type 11-G.
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Table 2-2. Connection of Unused Pins (78K0R/LF3) (3/3)
Pin Name
AVDD0
Note 1
, AVDD
I/O Circuit Type
I/O
−
Note 2
−
Recommended Connection of Unused Pins
Make this pin the same potential as EVDD or VDD.
Make this pin to have a potential where 2.3 V ≤ AVDD0 ≤
VDD.
AVDD1
−
Note 1
−
Make this pin the same potential as EVDD or VDD.
Make this pin to have a potential where 2.3 V ≤ AVDD1 ≤
VDD.
EVDD1
Note 2
Make this pin the same potential as EVDD or VDD.
AVSS
VREFOUT
AVREF
Note 1
/AVREFP
Note 1
,
−
Make this pin the same potential as the EVSS or VSS.
−
−
Make this pin the same potential as the AVDD0, EVDD or VDD.
−
Leave open or connect to VSS via a resistor of 100 kΩ or more.
Note 2
FLMD0
2-W
RESET
2
Input
−
REGC
−
Notes 1.
Dedicated to μ PD78F150xA
2.
Dedicated to μ PD78F151xA
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Connect directly to EVDD or via a resistor.
Connect to VSS via capacitor (0.47 to 1 μF).
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2.3.2 78K0R/LG3
Table 2-3 shows the types of pin I/O circuits and the recommended connections of unused pins.
Table 2-3. Connection of Unused Pins (78K0R/LG3) (1/3)
Pin Name
I/O Circuit Type
12-H
P00/CAPH
I/O
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P01/CAPL
P02/VLC3
5-AT
P10/SCK20/SCL20
5-AN
P11/SI20/RxD2/SDA20/
INTP6
P12/SO20/TxD2/TO02
5-AG
P13/SO10/TxD1/TO04
P14/SI10/RxD1/SDA10/
5-AN
INTP4
P15/SCK10/SCL10/INTP7
P16/TI05/TO05/INTP10
P20/ANI0/AMP0-
Note 1, 2
P21/ANI1/AMP0O
P22/ANI2/AMP0+
P23/ANI3/AMP1-
Note 1, 2
Note 1, 2
P24/ANI4/AMP1O
P25/ANI5/AMP1+
P26/ANI6/AMP2-
Note 1, 2
Note 1, 2
Note 1, 2
Note 1, 2
P27/ANI7/AMP2O
Note 1, 2
P30/TI03/TO00/RTC1HZ/
8-R
11-P
Note 3
Input:
11-S
Note 3
Output: Leave open.
11-N
Note 3
11-P
Note 3
11-S
Note 3
11-N
Note 3
11-P
Note 3
11-S
Note 3
8-R
Input:
Independently connect to AVDD0 or AVSS via a resistor.
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
INTP1
P31/TI00/TO03/RTCDIV/
RTCCL/PCLBUZ1/INTP2
P32/TI01/TO01/INTP5/
PCLBUZ0
P33/TI07/TO07/INTP3
P34/TI06/TO06/INTP8
P40/TOOL0
8-R
Pull this pin up (pulling it down is prohibited).
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P41/TOOL1
5-AG
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Notes 1. P20/ANI0/AMP0- to P27/ANI7/ANP2O are set in the digital input port mode after release of reset.
2.
AMPxx applies to μ PD78F150xA only.
3.
μ PD78F151xA corresponds to type 11-G.
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Table 2-3. Connection of Unused Pins (78K0R/LG3) (2/3)
Pin Name
P50/SEG39/RxD3
17-Q
P51/SEG38/TxD3
17-P
P52/SEG37/TI02
I/O
I/O Circuit Type
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
17-Q
P53/SEG36/TI04
Leave open.
P54/SEG35 to P57/SEG32
17-P
P60/SCL0
13-R
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P61/SDA0
P80/SCK00/INTP11
8-R
P81/RxD0/SI00/INTP9
P82/SO00/TxD0
5-AG
P90/SEG31 to P97/SEG24
17-P
Input:
P100/SEG15
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Leave open.
P110/ANO0
Note 1
P111/ANO1
Note 1
,
Input:
12-A
Independently connect to AVDD1 or AVSS via a resistor.
Output: Leave open.
P120/INTP0/EXLVI
Input:
8-R
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Note 3
P121/X1
P122/X2/EXCLK
P123/XT1
Note 3
P124/XT2
Note 3
37-C
Input
Independently connect to EVDD or EVSS via a resistor.
Note 3
37-A
P130
3-C
Output
Leave open.
P140/SEG23 to P147/SEG16
17-P
I/O
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Leave open.
Notes 1.
ANOx and AVREFM apply to μ PD78F150xA only.
2. μ PD78F151xA corresponds to type 5.
3.
Use recommended connection above in input port mode (see Figure 5-2 Format of Clock Operation Mode
Control Register (CMC)) when these pins are not used.
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Table 2-3. Connection of Unused Pins (78K0R/LG3) (3/3)
Pin Name
P150/ANI8/AMP2+
P151/ANI9
I/O Circuit Type
Note 1
Note 1
P152/ANI10
11-N
I/O
Recommended Connection of Unused Pins
Input:
I/O
Independently connect to AVDD0 or AVSS via a resistor.
Output: Leave open.
11-G
Note 1
P157/ANI15/AVREFM
Note 1, 2
11-T
SEG0/COM4 to SEG3/COM7
18-F
SEG4 to SEG14
17-T
COM0 to COM3
18-E
Note 3
Output
VLC0 to VLC2
−
−
AVDD0
−
−
Leave open.
Make this pin the same potential as EVDD or VDD.
Make this pin to have a potential where 2.3 V ≤ AVDD0 ≤ VDD.
−
AVDD1
−
Make this pin the same potential as EVDD or VDD.
Make this pin to have a potential where 2.3 V ≤ AVDD1 ≤ VDD.
AVSS
−
−
Make this pin the same potential as the EVSS or VSS.
VREFOUT/AVREFP
−
−
Make this pin the same potential as the AVDD0, EVDD or VDD.
−
Leave open or connect to VSS via a resistor of 100 kΩ or more.
FLMD0
2-W
RESET
2
Input
−
REGC
Notes 1.
−
Connect directly to EVDD or via a resistor.
Connect to VSS via capacitor (0.47 to 1 μF).
P150/ANI8/AMP2+ to P152/ANI10 and P157/ANI15/AVREFM are set in the digital input port mode after release
of reset.
2.
ANOx and AVREFM apply to μ PD78F150xA only.
3.
μ PD78F151xA corresponds to type 11-G.
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2.3.3 78K0R/LH3
Table 2-4 to shows the types of pin I/O circuits and the recommended connections of unused pins.
Table 2-4. Connection of Unused Pins (78K0R/LH3) (1/3)
Pin Name
I/O Circuit Type
12-H
P00/CAPH
I/O
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P01/CAPL
P02/VLC3
5-AT
P10/SCK20/SCL20
5-AN
P11/SI20/RxD2/SDA20/
INTP6
P12/SO20/TxD2/TO02
5-AG
P13/SO10/TxD1/TO04
P14/SI10/RxD1/SDA10/
5-AN
INTP4
P15/SCK10/SCL10/INTP7
P16/TI05/TO05/INTP10
8-R
P17
5-AG
P20/ANI0/AMP0-
Note 1, 2
P21/ANI1/AMP0O
P22/ANI2/AMP0+
P23/ANI3/AMP1-
Note 1, 2
P24/ANI4/AMP1O
P25/ANI5/AMP1+
P26/ANI6/AMP2-
Note 1, 2
Note 1, 2
Note 1, 2
Note 1, 2
Note 1, 2
P27/ANI7/AMP2O
Note 1, 2
P30/TI03/TO00/RTC1HZ/
Note 3
Input:
11-S
Note 3
Output: Leave open.
11-N
Note 3
11-P
Note 3
11-S
Note 3
11-N
Note 3
11-P
Note 3
11-S
Note 3
11-P
8-R
Input:
Independently connect to AVDD0 or AVSS via a resistor.
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
INTP1
P31/TI00/TO03/RTCDIV/
RTCCL/PCLBUZ1/INTP2
P32/TI01/TO01/INTP5/
PCLBUZ0
P33/TI07/TO07/INTP3
P34/TI06/TO06/INTP8
P40/TOOL0
8-R
Pull this pin up (pulling it down is prohibited).
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P41/TOOL1
5-AG
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Notes 1.
2.
3.
P20/ANI0/AMP0- to P27/ANI7/ANP2O are set in the digital input port mode after release of reset.
AMPxx applies to μ PD78F150xA only.
μ PD78F151xA corresponds to type 11-G.
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Table 2-4. Connection of Unused Pins (78K0R/LH3) (2/3)
Pin Name
P50/SEG53/RxD3
17-Q
P51/SEG52/TxD3
17-P
P52/SEG51/TI02
I/O
I/O Circuit Type
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
17-Q
P53/SEG50/TI04
Leave open.
P54/SEG49 to P57/SEG46
17-P
P60/SCL0
13-R
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P61/SDA0
P70/KR0 to P74/KR4
8-R
P75/KR5/SCK01
5-AN
P76/KR6/SI01
P77/KR7/SO01
8-R
P80/SCK00/INTP11
P81/RxD0/SI00/INTP9
P82/SO00/TxD0
5-AG
P83
P84/TI10/TO10
8-R
P85/TI11/TO11
P86/TI12/TO12
P87/TI13/TO13
P90/SEG45 to P97/SEG38
17-P
Input:
P100/SEG29 to P102/SEG27
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Leave open.
P110/ANO0
Note 1
P111/ANO1
Note 1
,
12-A
Note 2
Input:
Independently connect to AVDD1 or AVSS via a resistor.
Output: Leave open.
P120/INTP0/EXLVI
8-R
I/O
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Note 3
P121/X1
P122/X2/EXCLK
P123/XT1
Note 3
P124/XT2
Note 3
37-C
Input
Independently connect to EVDD or EVSS via a resistor.
Note 3
37-A
P130
3-C
Output
Leave open.
P140/SEG37 to P147/SEG30
17-P
I/O
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Leave open.
Notes 1.
ANOx applies to μ PD78F150xA only.
2.
μ PD78F151xA corresponds to type 5.
3.
Use recommended connection above in input port mode (see Figure 5-2 Format of Clock Operation Mode
Control Register (CMC)) when these pins are not used.
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Table 2-4. Connection of Unused Pins (78K0R/LH3) (3/3)
Pin Name
P150/ANI8/AMP2+
P151/ANI9
Note 1
P152/ANI10
I/O
I/O Circuit Type
Note 1
11-N
11-G
Recommended Connection of Unused Pins
Input:
I/O
Independently connect to AVDD0 or AVSS via a resistor.
Output: Leave open.
Note 3
Note 1
P157/ANI15/AVREFM
Note 1, 2
11-T
SEG0/COM4 to SEG3/COM7
18-F
SEG4 to SEG26
17-T
COM0 to COM3
18-E
Output
VLC0 to VLC2
−
−
AVDD0
−
−
Leave open.
Make this pin the same potential as EVDD or VDD.
Make this pin to have a potential where 2.3 V ≤ AVDD0 ≤ VDD.
−
AVDD1
−
Make this pin the same potential as EVDD or VDD.
Make this pin to have a potential where 2.3 V ≤ AVDD1 ≤ VDD.
AVSS
−
−
Make this pin the same potential as the EVSS or VSS.
VREFOUT/AVREFP
−
−
Make this pin the same potential as the AVDD0, EVDD or VDD.
−
Leave open or connect to VSS via a resistor of 100 kΩ or more.
FLMD0
2-W
RESET
2
Input
−
REGC
Notes 1.
−
Connect directly to EVDD or via a resistor.
Connect to VSS via capacitor (0.47 to 1 μF).
P150/ANI8/AMP2+ to P152/ANI10 and P157/ANI15/AVREFM are set in the digital input port mode after release
of reset.
2.
AVREFM applies to μ PD78F150xA only.
3.
μ PD78F151xA corresponds to type 11-G.
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Figure 2-1. Pin I/O Circuit List (1/5)
Type 2
Type 2-W
VDD
IN
P-ch
pull-up
enable
N-ch
pull-down
enable
VSS
Schmitt-triggered input with hysteresis characteristics
IN
Schmitt-triggered input with hysteresis characteristics
Type 3-C
Type 5
EVDD
EVDD
pullup
enable
P-ch
P-ch
EVDD
data
OUT
data
P-ch
IN/OUT
N-ch
output
disable
N-ch
EVSS
EVSS
input
enable
Type 5-AN
Type 5-AG
EVDD
pull-up
enable
EVDD
P-ch
EVDD
data
pullup
enable
P-ch
P-ch
EVDD
IN/OUT
output
disable
N-ch
data
P-ch
EVSS
CMOS
IN/OUT
output
disable
N-ch
EVSS
TTL
input
characteristic
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Figure 2-1. Pin I/O Circuit List (2/5)
Type 5-AT
Type 11-S
AVDD0
EVDD
data
P-ch
pullup
enable
P-ch
IN/OUT
output
disable
EVDD
N-ch
AVSS
data
P-ch
P-ch
Comparator
+
IN/OUT
_
output
disable
N-ch
N-ch
VREF
(Threshold voltage)
AVSS
EVSS
input
enable
input enable
+
OP
VLC3
_AMP
Type 8-R
Type 11-G
AVDD0
EVDD
Data
P-ch
pullup
enable
P-ch
IN/OUT
Output
disable
EVDD
data
N-ch
AVSS
P-ch
P-ch
Comparator
+
IN/OUT
_
N-ch
output
disable
N-ch
Series resistor string voltage
AVSS
EVSS
Input enable
Type 11-N
Type 11-P
AVREF
AVREF
data
data
P-ch
P-ch
IN/OUT
output
disable
N-ch
IN/OUT
output
disable
N-ch
AVSS
AVSS
P-ch
P-ch
Comparator
Comparator
+
+
_
_
N-ch
N-ch
VREF
(Threshold voltage)
VREF
(Threshold voltage)
AVSS
AVSS
input enable
input enable
+
OP
AMP
_
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Figure 2-1. Pin I/O Circuit List (3/5)
Type 11-T
Type 12-H
AVDD0
EVDD
data
P-ch
IN/OUT
output
disable
pullup
enable
P-ch
N-ch
EVDD
data
AVSS
P-ch
P-ch
Comparator
IN/OUT
+
_
N-ch
output
disable
VREF
(Threshold voltage)
N-ch
EVSS
AVSS
input
enable
input enable
P-ch
P-ch
AVREFM
CAPH, CAPL
N-ch
N-ch
Type 12-A
Type 17-P
EVDD
AVDD1
data
pullup
enable
P-ch
P-ch
IN/OUT
output
disable
EVDD
N-ch
data
P-ch
IN/OUT
AVSS
output
disable
N-ch
input
enable
EVSS
input
enable
P-ch
analog output voltage
N-ch
P-ch
VLC0
P-ch
Type 13-R
VLC1
N-ch
P-ch
SEG data
N-ch
IN/OUT
data
output disable
VLC2
P-ch
N-ch
N-ch
EVSS
VLC3
P-ch
N-ch
N-ch
VSS
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Figure 2-1. Pin I/O Circuit List (4/5)
Type 17-Q
Type 17-T
EVDD
pullup
enable
VLC0
P-ch
P-ch
EVDD
data
VLC1
N-ch
P-ch
P-ch
IN/OUT
SEG data
output
disable
OUT
N-ch
N-ch
EVSS
VLC2
input
enable
P-ch
N-ch
VLC0
VLC3
P-ch
N-ch
P-ch
VLC1
N-ch
P-ch
N-ch
SEG data
VSS
N-ch
VLC2
P-ch
Type 18-E
N-ch
P-ch
VLC3
P-ch
VLC0
N-ch
P-ch
VLC1
N-ch
N-ch
P-ch
N-ch
N-ch
P-ch
VSS
OUT
COM data
P-ch
VLC2
N-ch
P-ch
VLC3
N-ch
N-ch
VSS
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Figure 2-1. Pin I/O Circuit List (5/5)
Type 18-F
Type 37-A
P-ch
VLC0
XT2
P-ch
input
enable
VLC1
N-ch
COM data
N-ch
P-ch
P-ch
N-ch
N-ch
P-ch
XT1
P-ch
VLC2
input
enable
N-ch
P-ch
Type 37-C
VLC3
N-ch
N-ch
OUT
VSS
X2
input
enable
VLC0
P-ch
VLC1
P-ch
P-ch
N-ch
N-ch
SEG data
X1
N-ch
P-ch
input
enable
VLC2
N-ch
P-ch
VLC3
N-ch
N-ch
VSS
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CHAPTER 3 CPU ARCHITECTURE
CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
Products in the 78K0R/Lx3 microcontrollers can access a 1 MB memory space. Figures 3-1 to 3-3 show the memory
maps.
Figure 3-1. Memory Map (μPD78F1500A, 78F1503A, 78F1506A, 78F1510A, 78F1513A, 78F1516A)
0FFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNote 1
4 KB
Program area
FEF00H
FEEFFH
Mirror
55.75 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
F0000H
EFFFFH
Extended special
function register (2nd SFR)
2 KB
01FFFH
010CEH
010CDH
010C4H
010C3H
010C0H
010BFH
01080H
0107FH
Data memory
space
On-chip debug security
ID setting areaNote 2
10 bytes
Option byte areaNote 2
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
10000H
0FFFFH
Program
memory
space
Option byte areaNote 2
4 bytes
Boot cluster 0Note 3
CALLT table area
64 bytes
Vector table area
128 bytes
Flash memory
64 KB
00000H
On-chip debug security
ID setting areaNote 2
10 bytes
00000H
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.7 Security Setting).
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Figure 3-2. Memory Map (μPD78F1501A, 78F1504A, 78F1507A)
17FFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNote 1
6 KB
Program area
FE700H
FE6FFH
Mirror
53.75 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
F0000H
EFFFFH
Extended special
function register (2nd SFR)
2 KB
01FFFH
010CEH
010CDH
010C4H
010C3H
010C0H
010BFH
01080H
0107FH
Data memory
space
On-chip debug security
ID setting areaNote 2
10 bytes
Option byte areaNote 2
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
18000H
17FFFH
Program
memory
space
00080H
0007FH
Flash memory
96 KB
00000H
On-chip debug security
ID setting areaNote 2
10 bytes
Option byte areaNote 2
4 bytes
Boot cluster 0Note 3
CALLT table area
64 bytes
Vector table area
128 bytes
00000H
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.7 Security Setting).
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Figure 3-3. Memory Map (μPD78F1502A, 78F1505A, 78F1508A, 78F1512A, 78F1515A, 78F1518A)
1FFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNote 1
7 KB
FE300H
FE2FFH
FDF00H
FDEFFH
F1000H
F0FFFH
Reserved
01FFFH
Mirror
51.75 KB
Reserved
F0800H
F07FFH
F0000H
EFFFFH
Program area
Extended special
function register (2nd SFR)
2 KB
010CEH
010CDH
010C4H
010C3H
010C0H
010BFH
01080H
0107FH
Data memory
space
On-chip debug security
ID setting areaNote 2
10 bytes
Option byte areaNote 2
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
20000H
1FFFFH
00080H
0007FH
Program
memory
space
Flash memory
128 KB
00000H
On-chip debug security
ID setting areaNote 2
10 bytes
Option byte areaNote 2
4 bytes
Boot cluster 0Note 3
CALLT table area
64 bytes
Vector table area
128 bytes
00000H
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.7 Security Setting).
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Remark
CHAPTER 3 CPU ARCHITECTURE
The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see
Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory.
0FFFFH
Block 3FH
0FC00H
0FBFFH
007FFH
00400H
003FFH
Block 01H
Block 00H
1 KB
00000H
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Correspondence between the address values and block numbers in the flash memory are shown below.
Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory
Address Value
Block
Address Value
Block
Address Value
Block
Address Value
Block
Number
Number
Number
Number
00000H to 003FFH
00H
08000H to 083FFH
20H
10000H to 103FFH
40H
18000H to 183FFH
60H
00400H to 007FFH
01H
08400H to 087FFH
21H
10400H to 107FFH
41H
18400H to 187FFH
61H
00800H to 00BFFH
02H
08800H to 08BFFH
22H
10800H to 10BFFH
42H
18800H to 18BFFH
62H
00C00H to 00FFFH
03H
08C00H to 08FFFH
23H
10C00H to 10FFFH
43H
18C00H to 18FFFH
63H
01000H to 013FFH
04H
09000H to 093FFH
24H
11000H to 113FFH
44H
19000H to 193FFH
64H
01400H to 017FFH
05H
09400H to 097FFH
25H
11400H to 117FFH
45H
19400H to 197FFH
65H
01800H to 01BFFH
06H
09800H to 09BFFH
26H
11800H to 11BFFH
46H
19800H to 19BFFH
66H
01C00H to 01FFFH
07H
09C00H to 09FFFH
27H
11C00H to 11FFFH
47H
19C00H to 19FFFH
67H
02000H to 023FFH
08H
0A000H to 0A3FFH
28H
12000H to 123FFH
48H
1A000H to 1A3FFH
68H
02400H to 027FFH
09H
0A400H to 0A7FFH
29H
12400H to 127FFH
49H
1A400H to 1A7FFH
69H
02800H to 02BFFH
0AH
0A800H to 0ABFFH
2AH
12800H to 12BFFH
4AH
1A800H to 1ABFFH
6AH
02C00H to 02FFFH
0BH
0AC00H to 0AFFFH
2BH
12C00H to 12FFFH
4BH
1AC00H to 1AFFFH
6BH
03000H to 033FFH
0CH
0B000H to 0B3FFH
2CH
13000H to 133FFH
4CH
1B000H to 1B3FFH
6CH
03400H to 037FFH
0DH
0B400H to 0B7FFH
2DH
13400H to 137FFH
4DH
1B400H to 1B7FFH
6DH
03800H to 03BFFH
0EH
0B800H to 0BBFFH
2EH
13800H to 13BFFH
4EH
1B800H to 1BBFFH
6EH
03C00H to 03FFFH
0FH
0BC00H to 0BFFFH
2FH
13C00H to 13FFFH
4FH
1BC00H to 1BFFFH
6FH
04000H to 043FFH
10H
0C000H to 0C3FFH
30H
14000H to 143FFH
50H
1C000H to 1C3FFH
70H
04400H to 047FFH
11H
0C400H to 0C7FFH
31H
14400H to 147FFH
51H
1C400H to 1C7FFH
71H
04800H to 04BFFH
12H
0C800H to 0CBFFH
32H
14800H to 14BFFH
52H
1C800H to 1CBFFH
72H
04C00H to 04FFFH
13H
0CC00H to 0CFFFH
33H
14C00H to 14FFFH
53H
1CC00H to 1CFFFH
73H
05000H to 053FFH
14H
0D000H to 0D3FFH
34H
15000H to 153FFH
54H
1D000H to 1D3FFH
74H
05400H to 057FFH
15H
0D400H to 0D7FFH
35H
15400H to 157FFH
55H
1D400H to 1D7FFH
75H
05800H to 05BFFH
16H
0D800H to 0DBFFH
36H
15800H to 15BFFH
56H
1D800H to 1DBFFH
76H
05C00H to 05FFFH
17H
0DC00H to 0DFFFH
37H
15C00H to 15FFFH
57H
1DC00H to 1DFFFH
77H
06000H to 063FFH
18H
0E000H to 0E3FFH
38H
16000H to 163FFH
58H
1E000H to 1E3FFH
78H
06400H to 067FFH
19H
0E400H to 0E7FFH
39H
16400H to 167FFH
59H
1E400H to 1E7FFH
79H
06800H to 06BFFH
1AH
0E800H to 0EBFFH
3AH
16800H to 16BFFH
5AH
1E800H to 1EBFFH
7AH
06C00H to 06FFFH
1BH
0EC00H to 0EFFFH
3BH
16C00H to 16FFFH
5BH
1EC00H to 1EFFFH
7BH
07000H to 073FFH
1CH
0F000H to 0F3FFH
3CH
17000H to 173FFH
5CH
1F000H to 1F3FFH
7CH
07400H to 077FFH
1DH
0F400H to 0F7FFH
3DH
17400H to 177FFH
5DH
1F400H to 1F7FFH
7DH
07800H to 07BFFH
1EH
0F800H to 0FBFFH
3EH
17800H to 17BFFH
5EH
1F800H to 1FBFFH
7EH
07C00H to 07FFFH
1FH
0FC00H to 0FFFFH
3FH
17C00H to 17FFFH
5FH
1FC00H to 1FFFFH
7FH
Remark
μPD78F1500A, 78F1503A, 78F1506A, 78F1510A, 78F1513A, 78F1516A: Block numbers 00H to 3FH
μPD78F1501A, 78F1504A, 78F1507A: Block numbers 00H to 5FH
μPD78F1502A, 78F1505A, 78F1508A, 78F1512A, 78F1515A, 78F1518A: Block numbers 00H to 7FH
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3.1.1 Internal program memory space
The internal program memory space stores the program and table data. Normally, it is addressed with the program
counter (PC).
78K0R/Lx3 microcontrollers products incorporate internal ROM (flash memory), as shown below.
Table 3-2. Internal ROM Capacity
Part Number
Internal ROM
Structure
μPD78F1500A, 78F1503A, 78F1506A,
Flash
78F1510A, 78F1513A, 78F1516A
memory
Capacity
65536 × 8 bits (00000H to 0FFFFH)
μPD78F1501A, 78F1504A, 78F1507A
98303 × 8 bits (00000H to 17FFFH)
μPD78F1502A, 78F1505A, 78F1508A,
131071 × 8 bits (00000H to 1FFFFH)
78F1512A, 78F1515A, 78F1518A
The internal program memory space is divided into the following areas.
(1) Vector table area
The 128-byte area 00000H to 0007FH is reserved as a vector table area. The program start addresses for branch
upon reset or generation of each interrupt request are stored in the vector table area. Furthermore, the interrupt jump
address is a 64 K address of 00000H to 0FFFFH, because the vector code is assumed to be 2 bytes.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses.
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Table 3-3. Vector Table
Vector Table
Interrupt Source
LF3
LG3
LH3
Address
00000H
Vector Table
Interrupt Source
LF3
LG3
LH3
Address
RESET input, POC, LVI,
√
√
√
WDT, TRAP
00030H
INTTM02
√
√
√
00032H
INTTM03
√
√
√
00004H
INTWDTI
√
√
√
00034H
INTAD
√
√
√
00006H
INTLVI
√
√
√
00036H
INTRTC
√
√
√
00008H
INTP0
√
√
√
00038H
INTRTCI
√
√
√
0000AH
INTP1
√
√
√
0003AH
INTKR
−
−
√
0000CH
INTP2
√
√
√
0003CH
INTST2
√
√
√
0000EH
INTP3
√
√
√
INTCSI20
√
√
√
00010H
INTP4
√
√
√
INTIIC20
√
√
√
00012H
INTP5
√
√
√
0003EH
INTSR2
√
√
√
00014H
INTST3
√
√
√
00040H
INTSRE2
√
√
√
00016H
INTSR3
√
√
√
00042H
INTTM04
√
√
√
00018H
INTSRE3
√
√
√
00044H
INTTM05
√
√
√
0001AH
INTDMA0
√
√
√
00046H
INTTM06
√
√
√
0001CH
INTDMA1
√
√
√
00048H
INTTM07
√
√
√
0001EH
INTST0
−
√
√
0004AH
INTP6
√
√
√
INTCSI00
−
√
√
0004CH
INTP7
√
√
√
INTSR0
−
√
√
0004EH
INTP8
−
√
√
INTCSI01
−
−
√
00050H
INTP9
−
√
√
00022H
INTSRE0
√
√
√
00052H
INTP10
−
√
√
00024H
INTST1
√
√
√
00054H
INTP11
−
√
√
INTCSI10
√
√
√
00056H
INTTM10
√
√
√
INTIIC10
√
√
√
00058H
INTTM11
√
√
√
00026H
INTSR1
√
√
√
0005AH
INTTM12
√
√
√
00028H
INTSRE1
√
√
√
0005CH
INTTM13
√
√
√
0002AH
INTIICA
−
√
√
0005EH
INTMD
√
√
√
0002CH
INTTM00
√
√
√
0007EH
BRK
√
√
√
0002EH
INTTM01
√
√
√
00020H
(2) CALLT instruction table area
The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set
the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is of 2 bytes).
To use the boot swap function, set a CALLT instruction table also at 01080H to 010BFH.
(3) Option byte area
A 4-byte area of 000C0H to 000C3H can be used as an option byte area. Set the option byte at 010C0H to 010C3H
when the boot swap is used. For details, see CHAPTER 26 OPTION BYTE.
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(4) On-chip debug security ID setting area
A 10-byte area of 000C4H to 000CDH and 010C4H to 010CDH can be used as an on-chip debug security ID setting
area. Set the on-chip debug security ID of 10 bytes at 000C4H to 000CDH when the boot swap is not used and at
000C4H to 000CDH and 010C4H to 010CDH when the boot swap is used. For details, see CHAPTER 28 ON-CHIP
DEBUG FUNCTION.
3.1.2 Mirror area
The μPD78F1500A, 78F1503A, 78F01506A, 78F1510A, 78F1513A, and 78F1516A mirror the data flash area of
00000H to 0FFFFH, to F0000H to FFFFFH (the data flash area to be mirrored is set by the processor mode control
register (PMC)).
The μPD78F1501A, 78F1502A, 78F1504A, 78F1505A, 78F1507A, 78F1508A, 78F1512A, 78F1515A, and 78F1518A
mirror the data flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to F0000H to FFFFFH (the data flash area to be
mirrored is set by the processor mode control register (PMC)).
By reading data from F0000H to FFFFFH, an instruction that does not have the ES registers as an operand can be
used, and thus the contents of the data flash can be read with the shorter code. However, the data flash area is not
mirrored to the SFR, extended SFR, RAM, and use prohibited areas.
The mirror area can only be read and no instruction can be fetched from this area.
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The following show examples.
Example 1 μPD78F1500A, 78F1503A, 78F1506A,
Example 2 μPD78F1502A, 78F1505A, 78F1508A,
78F1510A, 78F1513A, 78F1516A
78F1512A, 78F1515A, 78F1518A
(Flash memory: 64 KB, RAM: 4 KB)
(Flash memory: 128 KB, RAM: 7 KB)
Setting MAA = 0
Setting MAA = 1
FFFFFH
FFFFFH
Special-function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
FEF00H
FEEFFH
Special-function register (SFR)
256 bytes
FFF00H
FFEFFH
General-purpose register
32 bytes
FFEE0H
FFEDFH
RAM
4 KB
General-purpose register
32 bytes
RAM
7 KB
FE300H
FE2FFH
FDF00H
FDEFFH
Flash memory
(same data as 01000H to 0EEFFH)
F1000H
F0FFFH
F1000H
F0FFFH
Reserved
Flash memory
(same data as 11000H to 1DEFFH)
Reserved
Reserved
F0800H
F07FFH
F0800H
F07FFH
Extended special
function register (2nd SFR)
2 KB
Extended special
function register (2nd SFR)
2 KB
F0000H
EFFFFH
F0000H
EFFFFH
Reserved
Mirror
Mirror
For example, 15432H is mirrored to
F5432H. Data can therefore be read by
MOV A, !5432H, instead of MOV ES,
#01H and MOV A, ES:!5432H.
20000H
1FFFFH
Reserved
For example, 02345H is mirrored to
F2345H. Data can therefore be read by
MOV A, !2345H, instead of MOV ES,
#00H and MOV A, ES:!2345H.
Flash memory
1DF00H
1DEFFH
Flash memory
11000H
10FFFH
10000H
0FFFFH
Flash memory
0EF00H
0EEFFH
Flash memory
Flash memory
01000H
00FFFH
Flash memory
00000H
Remark
00000H
MAA: Bit 0 of the processor mode control register (PMC).
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PMC register is described below.
• Processor mode control register (PMC)
This register selects the flash memory space for mirroring to area from F0000H to FFFFFH.
PMC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 3-4. Format of Configuration of Processor Mode Control Register (PMC)
Address: FFFFEH After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
PMC
0
0
0
0
0
0
0
MAA
MAA
Selection of flash memory space for mirroring to area from F0000H to FFFFFH
0
00000H to 0FFFFH is mirrored to F0000H to FFFFFH
1
10000H to 1FFFFH is mirrored to F0000H to FFFFFH
Cautions 1. Set PMC only once during the initial settings prior to operating the DMA controller. Rewriting
PMC other than during the initial settings is prohibited.
2. After setting PMC, wait for at least one instruction and access the mirror area.
3. When the μPD78F1500A, 78F1503A, 78F1506A, 78F1510A, 78F1513A, and 78F1516A (flash
memory size: 64 KB) are used, be sure to set bit 0 (MAA) of this register to 0.
3.1.3 Internal data memory space
78K0R/Lx3 microcontrollers products incorporate the following RAMs.
Table 3-4. Internal RAM Capacity
Part Number
Internal RAM
μPD78F1500A, 78F1503A, 78F1506A, 78F1510A, 78F1513A, 78F1516A
4096 × 8 bits (FEF00H to FFEFFH)
μPD78F1501A, 78F1504A, 78F1507A
6144 × 8 bits (FE700H to FFEFFH)
μPD78F1502A, 78F1505A, 78F1508A, 78F1512A, 78F1515A, 78F1518A
7168 × 8 bits (FE300H to FFEFFH)
The internal RAM can be used as a data area and a program area where instructions are written and executed. Four
general-purpose register banks consisting of eight 8-bit registers per bank are assigned to the 32-byte area of FFEE0H to
FFEFFH of the internal RAM area. However, instructions cannot be executed by using general-purpose registers.
The internal RAM is used as a stack memory.
Cautions 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
2. While using the self-programming function, the area of FFE20H to FFEFFH cannot be used as a
stack memory.
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3.1.4 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH.
Caution Do not access addresses to which SFRs are not assigned.
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area
On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area F0000H to F07FFH.
SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses
the 2nd SFR area, however, is 1 byte longer than an instruction that accesses the SFR area.
Caution Do not access addresses to which 2nd SFRs are not assigned.
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3.1.6 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the
register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
78K0R/Lx3 microcontrollers, based on operability and other considerations.
For areas containing data memory in
particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose
registers are available for use. Figures 3-5 to 3-7 show correspondence between data memory and addressing.
Figure 3-5. Correspondence Between Data Memory and Addressing
(μPD78F1500A, 78F1503A, 78F1506A, 78F1510A, 78F1513A, 78F1516A)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
FEF00H
FEEFFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
4 KB
Mirror
55.75 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Extended special
function register (2nd SFR)
2 KB
F0000H
EFFFFH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
10000H
0FFFFH
Flash memory
64 KB
00000H
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Figure 3-6. Correspondence Between Data Memory and Addressing (μPD78F1501A, 78F1504A, 78F1507A)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
FE700H
FE6FFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
6 KB
Mirror
53.75 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
F0000H
EFFFFH
Extended special
function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
18000H
17FFFH
Flash memory
96 KB
00000H
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Figure 3-7. Correspondence Between Data Memory and Addressing
(μPD78F1502A, 78F1505A, 78F1508A, 78F1512A, 78F1515A, 78F1518A)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
FE300H
FE2FFH
FDF00H
FDEFFH
F1000H
F0FFFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
7 KB
Reserved
Mirror
51.75 KB
Reserved
F0800H
F07FFH
Extended special
function register (2nd SFR)
2 KB
F0000H
EFFFFH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Reserved
20000H
1FFFFH
Flash memory
128 KB
00000H
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3.2 Processor Registers
The 78K0R/Lx3 microcontrollers products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 20-bit register that holds the address information of the next program to be executed.
In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched.
When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-8. Format of Program Counter
19
0
PC
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are stored in the stack area upon interrupt request generation or PUSH PSW
instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions.
Reset signal generation sets PSW to 06H.
Figure 3-9. Format of Program Status Word
7
PSW
IE
0
Z
RBS1
AC
RBS0
ISP1
ISP0
CY
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled
with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for various interrupt sources, and a priority
specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0, RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is
stored.
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(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.
(e) In-service priority flags (ISP1, ISP0)
This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests
specified lower than the value of ISP0 and ISP1 by a priority specification flag register (PRn0L, PRn0H, PRn1L,
PRn1H, PRn2L, PRn2H) (see 19.3 (3)) can not be acknowledged. Actual request acknowledgment is controlled
by the interrupt enable flag (IE).
Remark n = 0, 1
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon
rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be set as
the stack area.
Figure 3-10. Format of Stack Pointer
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the
stack memory.
Each stack operation saves data as shown in Figure 3-11.
Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP
before using the stack.
2. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as a stack area.
3. While using the self-programming function, the area of FFE20H to FFEFFH cannot be used as a
stack memory.
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Figure 3-11. Data to Be Saved to Stack Memory
PUSH rp instruction
SP←SP−2
↑
SP−2
↑
SP−1
↑
SP →
Register pair lower
Register pair higher
CALL, CALLT instructions
(4-byte stack)
SP←SP−4
↑
SP−4
↑
SP−3
↑
SP−2
↑
SP−1
↑
SP →
PC7 to PC0
PC15 to PC8
PC19 to PC16
00H
PUSH PSW instruction
SP←SP−2
↑
SP−2
↑
SP−1
↑
SP →
00H
PSW
Interrupt, BRK instruction
(4-byte stack)
SP←SP−4
↑
SP−4
↑
SP−3
↑
SP−2
↑
SP−1
↑
SP →
PC7 to PC0
PC15 to PC8
PC19 to PC16
PSW
3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX,
BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4register bank configuration, an efficient program can be created by switching between a register for normal processing and
a register for interrupts for each bank.
Caution It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
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Figure 3-12. Configuration of General-Purpose Registers
(a) Function name
16-bit processing
8-bit processing
FFEFFH
H
Register bank 0
HL
L
FFEF8H
D
Register bank 1
DE
E
FFEF0H
B
BC
Register bank 2
C
FFEE8H
A
AX
Register bank 3
X
FFEE0H
15
0
7
0
(b) Absolute name
16-bit processing
8-bit processing
FFEFFH
R7
Register bank 0
RP3
R6
FFEF8H
R5
Register bank 1
RP2
R4
FFEF0H
R3
RP1
Register bank 2
R2
FFEE8H
R1
RP0
Register bank 3
R0
FFEE0H
15
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3.2.3 ES and CS registers
The ES register is used for data access and the CS register is used to specify the higher address when a branch
instruction is executed.
The default value of the ES register after reset is 0FH, and that of the CS register is 00H.
Figure 3-13. Configuration of ES and CS Registers
ES
CS
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5
4
3
2
1
0
0
0
0
0
ES3
ES2
ES1
ES0
7
6
5
4
3
2
1
0
0
0
0
0
CS3
CP2
CP1
CP0
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3.2.4 Special function registers (SFRs)
Unlike a general-purpose register, each SFR has a special function.
SFRs are allocated to the FFF00H to FFFFFH area.
SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This
manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This
manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When
specifying an address, describe an even address.
Table 3-5 gives a list of the SFRs. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0R, and is defined as
an sfr variable using the #pragma sfr directive in the CC78K0R. When using the RA78K0R, ID78K0R-QB, and SM+
for 78K0R, symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon reset signal generation.
Caution Do not access addresses to which SFRs are not assigned.
Remark
For extended SFRs (2nd SFRs), see 3.2.5 Extended special function registers (2nd SFRs: 2nd Special
Function Registers).
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CHAPTER 3 CPU ARCHITECTURE
Table 3-5. SFR List (1/5)
78K0R/LF3
78K0R/LG3
78K0R/LH3
FFF00H
Port register 0
P0
R/W
√
√
−
00H
√
√
√
FFF01H
Port register 1
P1
R/W
√
√
−
00H
√
√
√
FFF02H
Port register 2
P2
R/W
√
√
−
00H
√
√
√
FFF03H
Port register 3
P3
R/W
√
√
−
00H
√
√
√
FFF04H
Port register 4
P4
R/W
√
√
−
00H
√
√
√
FFF05H
Port register 5
P5
R/W
√
√
−
00H
√
√
√
FFF06H
Port register 6
P6
R/W
√
√
−
00H
−
√
√
FFF07H
Port register 7
P7
R/W
√
√
−
00H
−
−
√
FFF08H
Port register 8
P8
R/W
√
√
−
00H
−
√
√
FFF09H
Port register 9
P9
R/W
√
√
−
00H
√
√
√
FFF0AH
Port register 10
P10
R/W
√
√
−
00H
√
√
√
FFF0BH
Port register 11
P11
R/W
√
√
−
00H
√
√
√
FFF0CH
Port register 12
P12
R/W
√
√
−
Undefined
√
√
√
FFF0DH
Port register 13
P13
R/W
√
√
−
00H
√
√
√
FFF0EH
Port register 14
P14
R/W
√
√
−
00H
√
√
√
FFF0FH
Port register 15
P15
R/W
√
√
−
00H
√
√
√
FFF10H
Serial data register 00
TXD0/
R/W
−
√
√
0000H
−
√
√
−
−
−
√
√
−
√
−
√
√
−
−
−
√
√
−
√
−
−
−
√
−
−
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit
After Reset
Range
SDR00
1-bit
8-bit
16-bit
SIO00
−
FFF11H
FFF12H
Serial data register 01
RXD0/
SDR01
R/W
√
0000H
SIO01
−
FFF13H
FFF14H
Serial data register 12
TXD3
FFF16H
Serial data register 13
RXD3
R/W
SDR13
R/W
−
FFF17H
FFF18H
SDR12
−
FFF15H
√
√
0000H
0000H
√
√
√
√
√
√
√
√
√
√
√
√
Timer data register 00
TDR00
R/W
−
−
√
0000H
√
√
√
Timer data register 01
TDR01
R/W
−
−
√
0000H
√
√
√
FFF19H
FFF1AH
FFF1BH
FFF1EH
FFF1FH
12-bit A/D conversion result register
Note
ADCR
8-bit A/D conversion result register ADCRH
R
−
−
√
0000H
√
√
√
R
−
√
−
00H
√
√
√
FFF20H
Port mode register 0
PM0
R/W
√
√
−
FFH
√
√
√
FFF21H
Port mode register 1
PM1
R/W
√
√
−
FFH
√
√
√
FFF22H
Port mode register 2
PM2
R/W
√
√
−
FFH
√
√
√
FFF23H
Port mode register 3
PM3
R/W
√
√
−
FFH
√
√
√
FFF24H
Port mode register 4
PM4
R/W
√
√
−
FFH
√
√
√
FFF25H
Port mode register 5
PM5
R/W
√
√
−
FFH
√
√
√
FFF26H
Port mode register 6
PM6
R/W
√
√
−
FFH
−
√
√
FFF27H
Port mode register 7
PM7
R/W
√
√
−
FFH
−
−
√
Note
For μ PD78F151xA, 10-bit A/D conversion result register is applied.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-5. SFR List (2/5)
78K0R/LF3
78K0R/LG3
78K0R/LH3
FFF28H
Port mode register 8
PM8
R/W
√
√
−
FFH
−
√
√
FFF29H
Port mode register 9
PM9
R/W
√
√
−
FFH
√
√
√
FFF2AH
Port mode register 10
PM10
R/W
√
√
−
FFH
√
√
√
FFF2BH
Port mode register 11
PM11
R/W
√
√
−
FFH
√
√
√
FFF2CH
Port mode register 12
PM12
R/W
√
√
−
FFH
√
√
√
FFF2EH
Port mode register 14
PM14
R/W
√
√
−
FEH
√
√
√
FFF2FH
Port mode register 15
PM15
R/W
√
√
−
FFH
√
√
√
FFF30H
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit
After
Range
Reset
1-bit
8-bit
16-bit
A/D converter mode register
ADM
R/W
√
√
−
00H
√
√
√
FFF31H
Analog input channel specification register
ADS
R/W
√
√
−
00H
√
√
√
FFF32H
A/D converter mode register 1
ADM1
R/W
√
√
−
00H
√
√
√
FFF33H
FFF36H
FFF37H
FFF38H
OAC
R/W
√
√
−
00H
√
√
√
Analog reference voltage control register
ADVRC
R/W
√
√
−
00H
√
√
√
Key return mode register
KRM
R/W
√
√
−
00H
−
−
√
Operational amplifier control register
Note
External interrupt rising edge enable register 0
EGP0
R/W
√
√
−
00H
√
√
√
FFF39H
External interrupt falling edge enable register 0
EGN0
R/W
√
√
−
00H
√
√
√
FFF3AH
External interrupt rising edge enable register 1
EGP1
R/W
√
√
−
00H
−
√
√
FFF3BH
External interrupt falling edge enable register 1
EGN1
R/W
√
√
−
00H
−
√
√
FFF3CH
Input switch control register
ISC
R/W
√
√
−
00H
√
√
√
FFF3EH
Timer input select register 0
TIS0
R/W
√
√
−
00H
√
√
√
FFF3FH
Timer input select register 1
TIS1
R/W
√
√
−
00H
√
√
√
FFF40H
LCD mode register
LCDMD
R/W
√
√
−
00H
√
√
√
FFF41H
LCD display mode register
LCDM
R/W
√
√
−
00H
√
√
√
FFF42H
LCD clock control register 0
LCDC0
R/W
√
√
−
00H
√
√
√
FFF43H
LCD boost level control register
VLCD
R/W
√
√
−
0FH
√
√
√
Serial data register 02
TXD1/ SDR02
R/W
−
√
√
0000H
√
√
√
−
−
√
√
√
−
√
√
√
√
−
−
√
√
√
−
√
√
√
√
−
−
√
√
√
−
√
FFF44H
SIO10
−
FFF45H
FFF46H
Serial data register 03
RXD1
SDR03
R/W
Serial data register 10
TXD2/ SDR10
R/W
−
FFF47H
FFF48H
√
0000H
√
0000H
SIO20
−
FFF49H
FFF4AH
√
√
√
√
√
√
√
−
00H
−
√
√
√
−
00H
−
√
√
FFF4BH
−
−
−
FFF50H
IICA shift register
IICA
R/W
−
FFF51H
IICA status register
IICS
R
√
SDR11
R/W
IICF
IICA flag register
FFF58H D/A D/A conversion value setting register 0 Note DACS0 DACS
R/W
√
√
−
00H
−
√
√
R/W
−
√
−
00H
√
√
√
FFF59H conversion value setting register W0 Note
R/W
−
−
√
0000H
√
√
√
R/W
−
√
−
00H
√
√
√
R/W
−
−
√
0000H
√
√
√
FFF5AH D/A
Note
−
W0
D/A conversion value setting register 1 Note DACS1 DACS
FFF5BH conversion value setting register W1 Note
0000H
RXD2
FFF52H
√
Serial data register 11
−
W1
Dedicated to μ PD78F150xA.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-5. SFR List (3/5)
78K0R/LF3
78K0R/LG3
78K0R/LH3
FFF5CH D/A converter mode register
DAM
R/W
√
√
−
00H
√
√
√
FFF64H
Timer data register 02
TDR02
R/W
−
−
√
0000H
√
√
√
Timer data register 03
TDR03
R/W
−
−
√
0000H
√
√
√
Timer data register 04
TDR04
R/W
−
−
√
0000H
√
√
√
Timer data register 05
TDR05
R/W
−
−
√
0000H
√
√
√
Timer data register 06
TDR06
R/W
−
−
√
0000H
√
√
√
Timer data register 07
TDR07
R/W
−
−
√
0000H
√
√
√
Timer data register 10
TDR10
R/W
−
−
√
0000H
√
√
√
Timer data register 11
TDR11
R/W
−
−
√
0000H
√
√
√
Timer data register 12
TDR12
R/W
−
−
√
0000H
√
√
√
Timer data register 13
TDR13
R/W
−
−
√
0000H
√
√
√
Sub-count register
RSUBC
R
−
−
√
0000H
√
√
√
Second count register
SEC
R/W
−
√
−
00H
√
√
√
Minute count register
MIN
R/W
−
√
−
00H
√
√
√
√
√
√
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
After
1-bit
8-bit
16-bit
Reset
FFF65H
FFF66H
FFF67H
FFF68H
FFF69H
FFF6AH
FFF6BH
FFF6CH
FFF6DH
FFF6EH
FFF6FH
FFF70H
FFF71H
FFF72H
FFF73H
FFF74H
FFF75H
FFF76H
FFF77H
FFF90H
FFF91H
FFF92H
FFF93H
FFF94H
Hour count register
HOUR
R/W
−
√
−
FFF95H
Note
12H
Week count register
WEEK
R/W
−
√
−
00H
√
√
√
FFF96H
Day count register
DAY
R/W
−
√
−
01H
√
√
√
FFF97H
Month count register
MONTH
R/W
−
√
−
01H
√
√
√
FFF98H
Year count register
YEAR
R/W
−
√
−
00H
√
√
√
FFF99H
Watch error correction register
SUBCUD
R/W
−
√
−
00H
√
√
√
FFF9AH
Alarm minute register
ALARMWM
R/W
−
√
−
00H
√
√
√
FFF9BH
Alarm hour register
ALARMWH
R/W
−
√
−
12H
√
√
√
FFF9CH
Alarm week register
ALARMWW
R/W
−
√
−
00H
√
√
√
Note The value of this register is 00H if the AMPM bit (bit 3 of the RTCC0 register) is set to 1 after reset.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-5. SFR List (4/5)
78K0R/LF3
78K0R/LG3
78K0R/LH3
Real-time counter control register 0
RTCC0
R/W
√
√
−
00H
√
√
√
FFF9EH
Real-time counter control register 1
RTCC1
R/W
√
√
−
00H
√
√
√
FFF9FH
Real-time counter control register 2
RTCC2
R/W
√
√
−
00H
√
√
√
FFFA0H
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit
After Reset
Range
FFF9DH
1-bit
8-bit
16-bit
Clock operation mode control register
CMC
R/W
−
√
−
00H
√
√
√
FFFA1H
Clock operation status control register
CSC
R/W
√
√
−
C0H
√
√
√
FFFA2H
Oscillation stabilization time counter status
OSTC
R
√
√
−
00H
√
√
√
register
Oscillation stabilization time select register
OSTS
R/W
−
√
−
07H
√
√
√
FFFA4H
Clock control register
CKC
R/W
√
√
−
09H
√
√
√
FFFA5H
Clock output select register 0
CKS0
R/W
√
√
−
00H
√
√
√
FFFA6H
Clock output select register 1
CKS1
R/W
√
√
−
00H
√
√
√
Reset control flag register
RESF
R
−
√
−
Undefined
√
√
√
FFFA3H
FFFA8H
Note 1
Low-voltage detection register
LVIM
R/W
√
√
−
00HNote 2
√
√
√
FFFAAH Low-voltage detection level select register
LVIS
R/W
√
√
−
0EHNote 3
√
√
√
√
√
√
FFFA9H
FFFABH Watchdog timer enable register
WDTE
R/W
−
√
−
FFFB0H
1A/9A
Note 4
DMA SFR address register 0
DSA0
R/W
−
√
−
00H
√
√
√
FFFB1H
DMA SFR address register 1
DSA1
R/W
−
√
−
00H
√
√
√
FFFB2H
DMA RAM address register 0L
DRA0L DRA0
R/W
−
√
√
00H
√
√
√
FFFB3H
00H
√
√
√
√
00H
√
√
√
00H
√
√
√
00H
√
√
√
00H
√
√
√
00H
√
√
√
00H
√
√
√
DMA RAM address register 0H
DRA0H
R/W
−
√
FFFB4H
DMA RAM address register 1L
DRA1L DRA1
R/W
−
√
FFFB5H
DMA RAM address register 1H
DRA1H
R/W
−
√
FFFB6H
DMA byte count register 0L
DBC0L DBC0
R/W
−
√
FFFB7H
DMA byte count register 0H
DBC0H
R/W
−
√
√
FFFB8H
DMA byte count register 1L
DBC1L DBC1
R/W
−
√
FFFB9H
DMA byte count register 1H
DBC1H
R/W
−
√
FFFBAH DMA mode control register 0
DMC0
R/W
√
√
−
00H
√
√
√
FFFBBH DMA mode control register 1
DMC1
R/W
√
√
−
00H
√
√
√
FFFBCH DMA operation control register 0
DRC0
R/W
√
√
−
00H
√
√
√
FFFBDH DMA operation control register 1
DRC1
R/W
√
√
−
00H
√
√
√
FFFBEH Back ground event control register
BECTL
R/W
√
√
−
00H
√
√
√
√
FFFC0H
−
PFCMD
−
−
−
−
Undefined
√
√
√
FFFC2H
−
PFS
Note 5
−
−
−
−
Undefined
√
√
√
FFFC4H
−
FLPMCNote 5
Undefined
√
√
√
Note 5
−
−
−
−
Notes 1. The reset value of RESF varies depending on the reset source.
2. The reset value of LVIM varies depending on the reset source and the setting of the option byte.
3. The reset value of LVIS varies depending on the reset source.
4. The reset value of WDTE is determined by the setting of the option byte.
5. Do not directly operate this SFR, because it is to be used in the self programming library.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-5. SFR List (5/5)
Interrupt request flag register 2
IF2L
FFFD1H
IF2H
FFFD4H
Interrupt mask flag register 2
MK2L
IF2
R/W
MK2
R/W
MK2H
FFFD5H
FFFD8H
R/W
Priority specification flag register 02
PR02L PR02
FFFD9H
PR02H
FFFDCH Priority specification flag register 12
PR12L PR12
FFFDDH
PR12H
FFFE0H
Interrupt request flag register 0L
IF0L
FFFE1H
Interrupt request flag register 0H
IF0H
FFFE2H
Interrupt request flag register 1L
IF1L
FFFE3H
Interrupt request flag register 1H
IF1H
FFFE4H
Interrupt mask flag register 0L
MK0L
FFFE5H
IF0
R/W
R/W
Manipulable Bit Range
After
1-bit
8-bit
16-bit
Reset
78K0R/LH3
Symbol
78K0R/LG3
FFFD0H
Special Function Register (SFR) Name
78K0R/LF3
Address
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
FFFFH
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
R/W
√
√
R/W
√
√
R/W
√
√
R/W
√
√
MK0
R/W
√
√
R/W
√
√
MK1
R/W
√
√
IF1
Interrupt mask flag register 0H
MK0H
FFFE6H
Interrupt mask flag register 1L
MK1L
FFFE7H
Interrupt mask flag register 1H
MK1H
R/W
√
√
FFFE8H
Priority specification flag register 00L
PR00L PR00
R/W
√
√
FFFE9H
Priority specification flag register 00H
PR00H
R/W
√
√
FFFEAH Priority specification flag register 01L
PR01L PR01
R/W
√
√
FFFEBH Priority specification flag register 01H
PR01H
R/W
√
√
FFFECH Priority specification flag register 10L
PR10L PR10
R/W
√
√
FFFEDH Priority specification flag register 10H
PR10H
R/W
√
√
FFFEEH Priority specification flag register 11L
PR11L PR11
R/W
√
√
FFFEFH
Priority specification flag register 11H
FFFF0H Multiplication/division data register A (L)
√
FFFFH
√
√
√
√
√
√
√
√
√
√
FFFFH
√
√
√
√
00H
√
√
√
00H
√
√
√
√
√
√
√
√
00H
√
√
√
00H
√
√
√
FFH
√
√
√
FFH
√
√
√
FFH
√
√
√
FFH
√
√
√
FFH
√
√
√
FFH
√
√
√
FFH
√
√
√
FFH
√
√
√
FFH
√
√
√
FFH
√
√
√
√
FFH
√
√
√
FFH
√
√
√
√
√
√
√
PR11H
R/W
√
√
MDAL/MULA
R/W
−
−
√
0000H
MDAH/MULB
R/W
−
−
√
0000H
√
√
√
MDBH/MULOH
R/W
−
−
√
0000H
√
√
√
MDBL/MULOL
R/W
−
−
√
0000H
√
√
√
FFFF1H
FFFF2H Multiplication/division data register A (H)
FFFF3H
FFFF4H Multiplication/division data register B (H)
FFFF5H
FFFF6H Multiplication/division data register B (L)
FFFF7H
Remark
For extended SFRs (2nd SFRs), see Table 3-6 Extended SFR (2nd SFR) List.
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CHAPTER 3 CPU ARCHITECTURE
3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)
Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function.
Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to
FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than
an instruction that accesses the SFR area.
Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation
instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (!addr16.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (!addr16). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (!addr16). When
specifying an address, describe an even address.
Table 3-6 gives a list of the extended SFRs. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of an extended SFR. It is a reserved word in the RA78K0R, and is defined as an sfr
variable using the #pragma sfr directive in the CC78K0R. When using the RA78K0R, ID78K0R-QB, and SM+ for
78K0R, symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding extended SFR can be read or written.
R/W: Read/write enable
R:
Read only
W:
Write only
• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon reset signal generation.
Caution Do not access addresses to which 2nd SFRs are not assigned.
Remark
For SFRs in the SFR area, see 3.2.4 Special function registers (SFRs).
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (1/8)
78K0R/LF3
78K0R/LG3
78K0R/LH3
F0017H
A/D port configuration register
ADPC
R/W
−
√
−
10H
√
√
√
F0030H
Pull-up resistor option register 0
PU0
R/W
√
√
−
00H
√
√
√
F0031H
Pull-up resistor option register 1
PU1
R/W
√
√
−
00H
√
√
√
F0033H
Pull-up resistor option register 3
PU3
R/W
√
√
−
00H
√
√
√
F0034H
Pull-up resistor option register 4
PU4
R/W
√
√
−
00H
√
√
√
F0035H
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit
After Reset
Range
1-bit
8-bit
16-bit
Pull-up resistor option register 5
PU5
R/W
√
√
−
00H
√
√
√
F0037H
Pull-up resistor option register 7
PU7
R/W
√
√
−
00H
−
−
√
F0038H
Pull-up resistor option register 8
PU8
R/W
√
√
−
00H
−
√
√
F0039H
Pull-up resistor option register 9
PU9
R/W
√
√
−
00H
√
√
√
F003AH
Pull-up resistor option register 10
PU10
R/W
√
√
−
00H
√
√
√
F003CH
Pull-up resistor option register 12
PU12
R/W
√
√
−
00H
√
√
√
F003EH
Pull-up resistor option register 14
PU14
R/W
√
√
−
00H
√
√
√
F0041H
Port input mode register 1
PIM1
R/W
√
√
−
00H
√
√
√
F0047H
Port input mode register 7
PIM7
R/W
√
√
−
00H
−
−
√
F0051H
Port output mode register 1
POM1
R/W
√
√
−
00H
√
√
√
F0057H
Port output mode register 7
POM7
R/W
√
√
−
00H
−
−
√
F0058H
Port output mode register 8
POM8
R/W
√
√
−
00H
−
√
√
F0060H
Noise filter enable register 0
NFEN0
R/W
√
√
−
00H
√
√
√
F0061H
Noise filter enable register 1
NFEN1
R/W
√
√
−
00H
√
√
√
F0062H
Noise filter enable register 2
NFEN2
R/W
√
√
−
00H
−
−
√
F0080H
Port function register
PFALL
R/W
√
√
−
00H
√
√
√
F0081H
Segment enable register
SEGEN
R/W
√
√
−
00H
√
√
√
Multiplication/division data register C (L)
MDCL
R
−
−
√
0000H
√
√
√
Multiplication/division data register C (H)
MDCH
R
−
−
√
0000H
√
√
√
F00E0H
F00E1H
F00E2H
F00E3H
Multiplication/division control register
MDUC
R/W
√
√
−
00H
√
√
√
F00F0H
Peripheral enable register 0
PER0
R/W
√
√
−
00H
√
√
√
F00F3H
Operation speed mode control register
OSMC
R/W
−
√
−
00H
√
√
√
F00F4H
Regulator mode control register
RMC
R/W
−
√
−
00H
√
√
√
F00F6H
20 MHz internal high-speed oscillation
control register
DSCCTL
R/W
√
√
−
00H
√
√
√
F00FEH
BCD adjust result register
BCDADJ
R
−
√
−
Undefined
√
√
√
F0100H
Serial status register 00
SSR00L SSR00
R
−
√
√
0000H
−
√
√
−
−
−
√
√
Serial status register 01
SSR01L SSR01
−
√
√
0000H
−
−
F00E8H
−
F0101H
F0102H
−
F0103H
F0104H
Serial status register 02
SSR02L SSR02
R
−
F0105H
Serial status register 03
SSR03L SSR03
F0107H
−
F0108H
Serial flag clear trigger register 00
SIR00L
F0106H
R
F0109H
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SIR00
R
R/W
−
√
−
−
−
√
−
−
−
√
−
−
√
0000H
√
0000H
√
0000H
−
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
√
−
√
√
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (2/8)
R/W
−
F010BH
F010CH
SIR01L SIR01
R/W
Serial flag clear trigger register 02
SIR02L SIR02
R/W
−
F010DH
Manipulable Bit Range
After
1-bit
8-bit
16-bit
Reset
78K0R/LH3
Serial flag clear trigger register 01
Symbol
78K0R/LG3
F010AH
Special Function Register (SFR) Name
78K0R/LF3
Address
−
√
√
0000H
−
√
√
−
−
−
√
√
−
√
√
√
√
−
−
√
√
√
−
√
√
√
√
0000H
√
√
√
−
√
0020H
−
√
√
−
−
√
0020H
−
√
√
R/W
−
−
√
0020H
√
√
√
SMR03
R/W
−
−
√
0020H
√
√
√
SCR00
R/W
−
−
√
0087H
−
√
√
SCR01
R/W
−
−
√
0087H
−
√
√
SCR02
R/W
−
−
√
0087H
√
√
√
SCR03
R/W
−
−
√
0087H
√
√
√
SE0
R
√
√
√
0000H
√
√
√
−
−
√
√
√
SS0
R/W
√
√
√
0000H
√
√
√
−
−
√
√
√
√
√
√
√
√
√
√
√
SIR03L SIR03
−
−
Serial mode register 00
SMR00
R/W
−
Serial mode register 01
SMR01
R/W
Serial mode register 02
SMR02
Serial mode register 03
F0118H
Serial communication operation setting
F0119H
register 00
F011AH
Serial communication operation setting
F011BH
register 01
F011CH
Serial communication operation setting
F011DH
register 02
F011EH
Serial communication operation setting
F011FH
register 03
F0120H
Serial channel enable status register 0
SE0L
Serial channel start register 0
SS0L
F0110H
R/W
−
F010FH
0000H
√
Serial flag clear trigger register 03
F010EH
√
F0111H
F0112H
F0113H
F0114H
F0115H
F0116H
F0117H
−
F0121H
F0122H
−
F0123H
F0124H
Serial channel stop register 0
ST0L
ST0
R/W
−
F0125H
√
√
−
−
−
√
0000H
√
0000H
√
√
√
√
−
√
0F0FH
√
√
√
√
√
√
0000H
√
√
√
−
−
√
√
√
−
√
√
√
√
−
−
√
√
√
R
−
√
√
√
−
−
R
−
√
−
−
Serial clock select register 0
SPS0L SPS0
F0127H
−
−
−
F0128H
Serial output register 0
SO0
R/W
−
Serial output enable register 0
SOE0L SOE0
R/W
F0126H
√
R/W
F0129H
F012AH
−
F012BH
F0134H
Serial output level register 0
F0140H
SOL0
Serial status register 10
SSR10L SSR10
Serial status register 11
SSR11L SSR11
R/W
−
F0141H
F0142H
SOL0L
−
F0135H
F0143H
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Jun 20, 2011
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√
0000H
√
0000H
√
√
√
√
√
0000H
√
√
√
√
√
√
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (3/8)
SSR12L SSR12
Serial status register 13
SSR13L SSR13
Serial flag clear trigger register 10
SIR10L SIR10
R/W
−
Serial flag clear trigger register 11
SIR11L SIR11
Serial flag clear trigger register 13
SIR13L SIR13
R/W
−
F014BH
F014EH
R
−
F0149H
F014AH
R
−
F0147H
F0148H
R/W
R/W
−
F014FH
Manipulable Bit Range
After
1-bit
8-bit
16-bit
Reset
78K0R/LH3
Serial status register 12
F0145H
F0146H
Symbol
78K0R/LG3
F0144H
Special Function Register (SFR) Name
78K0R/LF3
Address
−
√
√
0000H
√
√
√
−
−
√
√
√
−
√
√
0000H
√
√
√
−
−
√
√
√
√
√
√
√
√
√
√
√
−
√
−
−
−
√
−
−
−
√
−
−
√
0000H
√
0000H
√
√
√
√
√
0000H
√
√
√
√
√
√
Serial mode register 10
SMR10
R/W
−
−
√
0020H
√
√
√
Serial mode register 11
SMR11
R/W
−
−
√
0020H
√
√
√
Serial mode register 12
SMR12
R/W
−
−
√
0020H
√
√
√
Serial mode register 13
SMR13
R/W
−
−
√
0020H
√
√
√
F0158H
Serial communication operation setting
SCR10
R/W
−
−
√
0087H
√
√
√
F0159H
register 10
F015AH
Serial communication operation setting
SCR11
R/W
−
−
√
0087H
√
√
√
F015BH
register 11
F015CH
Serial communication operation setting
SCR12
R/W
−
−
√
0087H
√
√
√
F015DH
register 12
F015EH
Serial communication operation setting
SCR13
R/W
−
−
√
0087H
√
√
√
F015FH
register 13
F0160H
Serial channel enable status register 1
√
0000H
√
√
√
√
√
√
√
√
F0150H
F0151H
F0152H
F0153H
F0154H
F0155H
F0156H
F0157H
F0162H
SS1L
Serial channel stop register 1
ST1L
Serial clock select register 1
SPS1L SPS1
SS1
R/W
ST1
R/W
−
R/W
−
F0167H
F0168H
R
−
F0165H
F0166H
SE1
Serial channel start register 1
F0163H
F0164H
SE1L
−
F0161H
√
√
−
−
√
√
−
−
√
√
−
−
−
√
−
−
√
0000H
√
√
√
√
√
0000H
√
√
√
√
√
√
√
0000H
√
√
√
√
√
√
Serial output register 1
SO1
R/W
−
−
√
0F0FH
√
√
√
Serial output enable register 1
SOE1L SOE1
R/W
√
√
√
0000H
√
√
√
−
−
√
√
√
F0169H
F016AH
F016BH
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (4/8)
R/W
Manipulable Bit Range
After
1-bit
8-bit
16-bit
Reset
78K0R/LH3
Symbol
78K0R/LG3
F0174H
Special Function Register (SFR) Name
78K0R/LF3
Address
−
√
√
0000H
√
√
√
√
√
√
√
√
√
Serial output level register 1
SOL1L SOL1
F0175H
−
−
−
F0180H
Timer counter register 00
TCR00
R
−
−
√
FFFFH
Timer counter register 01
TCR01
R
−
−
√
FFFFH
√
√
√
Timer counter register 02
TCR02
R
−
−
√
FFFFH
√
√
√
Timer counter register 03
TCR03
R
−
−
√
FFFFH
√
√
√
Timer counter register 04
TCR04
R
−
−
√
FFFFH
√
√
√
Timer counter register 05
TCR05
R
−
−
√
FFFFH
√
√
√
Timer counter register 06
TCR06
R
−
−
√
FFFFH
√
√
√
Timer counter register 07
TCR07
R
−
−
√
FFFFH
√
√
√
Timer mode register 00
TMR00
R/W
−
−
√
0000H
√
√
√
Timer mode register 01
TMR01
R/W
−
−
√
0000H
√
√
√
Timer mode register 02
TMR02
R/W
−
−
√
0000H
√
√
√
Timer mode register 03
TMR03
R/W
−
−
√
0000H
√
√
√
Timer mode register 04
TMR04
R/W
−
−
√
0000H
√
√
√
Timer mode register 05
TMR05
R/W
−
−
√
0000H
√
√
√
Timer mode register 06
TMR06
R/W
−
−
√
0000H
√
√
√
Timer mode register 07
TMR07
R/W
−
−
√
0000H
√
√
√
Timer status register 00
TSR00L TSR00
R
−
√
√
0000H
√
√
√
−
−
√
√
√
R
−
√
√
√
√
−
−
√
√
√
R
−
√
√
√
√
−
−
√
√
√
R/W
F0181H
F0182H
F0183H
F0184H
F0185H
F0186H
F0187H
F0188H
F0189H
F018AH
F018BH
F018CH
F018DH
F018EH
F018FH
F0190H
F0191H
F0192H
F0193H
F0194H
F0195H
F0196H
F0197H
F0198H
F0199H
F019AH
F019BH
F019CH
F019DH
F019EH
F019FH
F01A0H
−
F01A1H
F01A2H
Timer status register 01
TSR01L TSR01
Timer status register 02
TSR02L TSR02
−
F01A3H
F01A4H
F01A5H
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√
0000H
√
0000H
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (5/8)
TSR03L TSR03
Timer status register 04
TSR04L TSR04
TSR05L TSR05
F01ACH Timer status register 06
TSR06L TSR06
Timer status register 07
TE0L
Timer channel start register 0
TS0L
Timer channel stop register 0
√
√
0000H
√
√
√
−
−
√
√
√
R
−
√
√
0000H
√
√
√
−
−
√
√
√
R
−
√
√
√
−
−
R
−
√
−
−
−
√
R
TE0
R
TS0
R/W
TT0L
TT0
R/W
−
Timer clock select register 0
TPS0L TPS0
Timer output register 0
TO0L
R/W
−
F01B7H
TO0
R/W
−
F01B9H
Timer output enable register 0
TOE0L TOE0
R/W
−
F01BBH
F01BCH Timer output level register 0
TOL0L TOL0
R/W
−
F01BDH
F01BEH
−
−
F01B5H
F01BAH
R
−
F01B3H
F01B8H
TSR07L TSR07
Timer channel enable status register 0
F01B1H
F01B6H
Reset
−
F01AFH
F01B4H
16-bit
−
F01ADH
F01B2H
8-bit
−
F01ABH
F01B0H
1-bit
−
Timer status register 05
F01AEH
After
R/W
−
F01A9H
F01AAH
Manipulable Bit Range
78K0R/LH3
Timer status register 03
F01A7H
F01A8H
Symbol
78K0R/LG3
F01A6H
Special Function Register (SFR) Name
78K0R/LF3
Address
Timer output mode register 0
TOM0L TOM0
R/W
−
F01BFH
−
−
√
√
−
−
√
√
−
−
√
√
−
−
−
√
−
−
−
√
−
−
√
√
−
−
−
√
−
−
−
√
−
−
√
0000H
−
−
√
√
√
0000H
−
√
√
−
√
√
√
√
√
√
√
√
√
√
√
0000H
√
0000H
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0000H
√
0000H
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0000H
√
0000H
√
√
√
√
√
0000H
√
√
√
√
√
√
Timer counter register 10
TCR10
R
−
−
√
FFFFH
√
√
√
Timer counter register 11
TCR11
R
−
−
√
FFFFH
√
√
√
Timer counter register 12
TCR12
R
−
−
√
FFFFH
√
√
√
Timer counter register 13
TCR13
R
−
−
√
FFFFH
√
√
√
Timer mode register 10
TMR10
R/W
−
−
√
0000H
√
√
√
F01CAH Timer mode register 11
TMR11
R/W
−
−
√
0000H
√
√
√
TMR12
R/W
−
−
√
0000H
√
√
√
F01C0H
F01C1H
F01C2H
F01C3H
F01C4H
F01C5H
F01C6H
F01C7H
F01C8H
F01C9H
F01CBH
F01CCH Timer mode register 12
F01CDH
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Table 3-6. Extended SFR (2nd SFR) List (6/8)
TMR13
Manipulable Bit Range
After
1-bit
8-bit
16-bit
Reset
78K0R/LH3
F01CEH Timer mode register 13
Symbol
78K0R/LG3
Special Function Register (SFR) Name
78K0R/LF3
Address
R/W
−
−
√
0000H
√
√
√
R
−
√
√
0000H
−
−
√
−
−
−
−
√
−
√
−
−
√
−
−
−
−
√
R
−
√
−
√
−
−
R
−
√
−
−
R/W
F01CFH
F01D0H
Timer status register 10
−
F01D1H
F01D2H
Timer status register 11
Timer status register 12
TSR12L TSR12
Timer status register 13
TSR13L TSR13
−
F01D7H
F01D8H
Timer channel enable status register 1
F01DAH Timer channel start register 1
F01DCH Timer channel stop register 1
R
TS1L
TS1
R/W
TT1L
TT1
R/W
−
F01DDH
F01DEH Timer clock select register 1
TPS1L TPS1
R/W
−
F01DFH
Timer output register 1
TO1L
TO1
R/W
−
F01E1H
Timer output enable register 1
TOE1L TOE1
Timer output level register 1
TOL1L TOL1
R/W
−
F01E3H
F01E4H
TE1
−
F01DBH
F01E2H
TE1L
−
F01D9H
F01E0H
R
−
F01D5H
F01D6H
TSR11L TSR11
−
F01D3H
F01D4H
TSR10L TSR10
R/W
−
F01E5H
√
−
√
√
−
−
√
√
−
−
−
√
−
−
−
√
−
−
√
√
−
−
−
√
−
−
−
√
0000H
−
−
−
√
√
0000H
−
−
√
−
−
√
√
0000H
√
√
√
√
√
√
√
√
√
0000H
√
√
√
√
√
0000H
√
√
√
√
√
√
√
√
√
√
√
√
−
−
√
√
√
0000H
0000H
−
−
√
√
0000H
−
−
√
−
−
√
√
0000H
−
−
√
−
−
√
−
√
−
−
−
√
√
−
00H
−
√
√
√
√
−
00H
−
√
√
−
−
F0230H
IICA control register 0
IICCTL0
R/W
√
F0231H
IICA control register 1
IICCTL1
R/W
F0232H
−
√
0000H
TOM1L TOM1
F01E7H
0000H
√
Timer output mode register 1
F01E6H
R/W
√
−
√
IICA low-level width setting register
IICWL
R/W
−
√
−
FFH
−
√
√
F0233H
IICA high-level width setting register
IICWH
R/W
−
√
−
FFH
−
√
√
F0234H
Slave address register
SVA
R/W
−
√
−
00H
−
√
√
F0400H
LCD display data memory 0
SEG0
R/W
−
√
−
00H
√
√
√
F0401H
LCD display data memory 1
SEG1
R/W
−
√
−
00H
√
√
√
F0402H
LCD display data memory 2
SEG2
R/W
−
√
−
00H
√
√
√
F0403H
LCD display data memory 3
SEG3
R/W
−
√
−
00H
√
√
√
F0404H
LCD display data memory 4
SEG4
R/W
−
√
−
00H
√
√
√
F0405H
LCD display data memory 5
SEG5
R/W
−
√
−
00H
√
√
√
F0406H
LCD display data memory 6
SEG6
R/W
−
√
−
00H
√
√
√
F0407H
LCD display data memory 7
SEG7
R/W
−
√
−
00H
√
√
√
F0408H
LCD display data memory 8
SEG8
R/W
−
√
−
00H
√
√
√
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Table 3-6. Extended SFR (2nd SFR) List (7/8)
78K0R/LF3
78K0R/LG3
78K0R/LH3
F0409H
LCD display data memory 9
SEG9
R/W
−
√
−
00H
√
√
√
F040AH
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
After
1-bit
8-bit
16-bit
Reset
LCD display data memory 10
SEG10
R/W
−
√
−
00H
√
√
√
F040BH
LCD display data memory 11
SEG11
R/W
−
√
−
00H
√
√
√
F040CH
LCD display data memory 12
SEG12
R/W
−
√
−
00H
√
√
√
F040DH
LCD display data memory 13
SEG13
R/W
−
√
−
00H
√
√
√
F040EH
LCD display data memory 14
SEG14
R/W
−
√
−
00H
√
√
√
F040FH
LCD display data memory 15
SEG15
R/W
−
√
−
00H
√
√
√
F0410H
LCD display data memory 16
SEG16
R/W
−
√
−
00H
√
√
√
F0411H
LCD display data memory 17
SEG17
R/W
−
√
−
00H
√
√
√
F0412H
LCD display data memory 18
SEG18
R/W
−
√
−
00H
√
√
√
F0413H
LCD display data memory 19
SEG19
R/W
−
√
−
00H
√
√
√
F0414H
LCD display data memory 20
SEG20
R/W
−
√
−
00H
√
√
√
F0415H
LCD display data memory 21
SEG21
R/W
−
√
−
00H
√
√
√
F0416H
LCD display data memory 22
SEG22
R/W
−
√
−
00H
√
√
√
F0417H
LCD display data memory 23
SEG23
R/W
−
√
−
00H
√
√
√
F0418H
LCD display data memory 24
SEG24
R/W
−
√
−
00H
√
√
√
F0419H
LCD display data memory 25
SEG25
R/W
−
√
−
00H
√
√
√
F041AH
LCD display data memory 26
SEG26
R/W
−
√
−
00H
√
√
√
F041BH
LCD display data memory 27
SEG27
R/W
−
√
−
00H
√
√
√
F041CH
LCD display data memory 28
SEG28
R/W
−
√
−
00H
√
√
√
F041DH
LCD display data memory 29
SEG29
R/W
−
√
−
00H
√
√
√
F041EH
LCD display data memory 30
SEG30
R/W
−
√
−
00H
√
√
√
F041FH
LCD display data memory 31
SEG31
R/W
−
√
−
00H
−
√
√
F0420H
LCD display data memory 32
SEG32
R/W
−
√
−
00H
−
√
√
F0421H
LCD display data memory 33
SEG33
R/W
−
√
−
00H
−
√
√
F0422H
LCD display data memory 34
SEG34
R/W
−
√
−
00H
−
√
√
F0423H
LCD display data memory 35
SEG35
R/W
−
√
−
00H
−
√
√
F0424H
LCD display data memory 36
SEG36
R/W
−
√
−
00H
−
√
√
F0425H
LCD display data memory 37
SEG37
R/W
−
√
−
00H
−
√
√
F0426H
LCD display data memory 38
SEG38
R/W
−
√
−
00H
−
√
√
F0427H
LCD display data memory 39
SEG39
R/W
−
√
−
00H
−
√
√
F0428H
LCD display data memory 40
SEG40
R/W
−
√
−
00H
−
−
√
F0429H
LCD display data memory 41
SEG41
R/W
−
√
−
00H
−
−
√
F042AH
LCD display data memory 42
SEG42
R/W
−
√
−
00H
−
−
√
F042BH
LCD display data memory 43
SEG43
R/W
−
√
−
00H
−
−
√
F042CH
LCD display data memory 44
SEG44
R/W
−
√
−
00H
−
−
√
F042DH
LCD display data memory 45
SEG45
R/W
−
√
−
00H
−
−
√
F042EH
LCD display data memory 46
SEG46
R/W
−
√
−
00H
−
−
√
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Table 3-6. Extended SFR (2nd SFR) List (8/8)
78K0R/LF3
78K0R/LG3
78K0R/LH3
F042FH
LCD display data memory 47
SEG47
R/W
−
√
−
00H
−
−
√
F0430H
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
After
1-bit
8-bit
16-bit
Reset
LCD display data memory 48
SEG48
R/W
−
√
−
00H
−
−
√
F0431H
LCD display data memory 49
SEG49
R/W
−
√
−
00H
−
−
√
F0432H
LCD display data memory 50
SEG50
R/W
−
√
−
00H
−
−
√
F0433H
LCD display data memory 51
SEG51
R/W
−
√
−
00H
−
−
√
F0434H
LCD display data memory 52
SEG52
R/W
−
√
−
00H
−
−
√
F0435H
LCD display data memory 53
SEG53
R/W
−
√
−
00H
−
−
√
Remark
For SFRs in the SFR area, see Table 3-5 SFR List.
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CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
3.3.1 Relative addressing
[Function]
Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the
instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the program counter (PC)’s value
(the start address of the next instruction), and specifies the program address to be used as the branch destination.
Relative addressing is applied only to branch instructions.
Figure 3-14. Outline of Relative Addressing
PC
OP code
DISPLACE
8/16 bits
3.3.2 Immediate addressing
[Function]
Immediate addressing stores immediate data of the instruction word in the program counter, and specifies the
program address to be used as the branch destination.
For immediate addressing, CALL !!addr20 or BR !!addr20 is used to specify 20-bit addresses and CALL !addr16 or
BR !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses.
Figure 3-15. Example of CALL !!addr20/BR !!addr20
PC
OP code
Low Addr.
High Addr.
Seg Addr.
Figure 3-16. Example of CALL !addr16/BR !addr16
PC
PCS
PCH
PCL
OP code
0000
Low Addr.
High Addr.
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3.3.3 Table indirect addressing
[Function]
Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit
immediate data in the instruction word, stores the contents at that table address and the next address in the program
counter (PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied only for CALLT
instructions.
In the 78K0R microcontrollers, branching is enabled only to the 64 KB space from 00000H to 0FFFFH.
Figure 3-17. Outline of Table Indirect Addressing
OP code
Low Addr.
00000000
10
0
High Addr.
Table address
Memory
0000
PC
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PCL
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CHAPTER 3 CPU ARCHITECTURE
3.3.4 Register direct addressing
[Function]
Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair
(AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and
specifies the program address. Register direct addressing can be applied only to the CALL AX, BC, DE, HL, and BR
AX instructions.
Figure 3-18. Outline of Register Direct Addressing
OP code
rp
CS
PC
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CHAPTER 3 CPU ARCHITECTURE
3.4 Addressing for Processing Data Addresses
3.4.1 Implied addressing
[Function]
Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the
instruction word, without using any register specification field in the instruction word.
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format
is necessary.
Implied addressing can be applied only to MULU X.
Figure 3-19. Outline of Implied Addressing
OP code
A register
Memory
3.4.2 Register addressing
[Function]
Register addressing accesses a general-purpose register as an operand. The instruction word of 3-bit long is used
to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
rp
AX, BC, DE, HL
Figure 3-20. Outline of Register Addressing
OP code
Register
Memory
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3.4.3 Direct addressing
[Function]
Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target
address.
[Operand format]
Identifier
Description
ADDR16
Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable)
ES: ADDR16
Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register)
Figure 3-21. Example of ADDR16
FFFFFH
OP code
Low Addr.
Target memory
High Addr.
F0000H
Memory
Figure 3-22. Example of ES:ADDR16
FFFFFH
ES
OP code
Low Addr.
Target memory
High Addr.
00000H
Memory
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CHAPTER 3 CPU ARCHITECTURE
3.4.4 Short direct addressing
[Function]
Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of
addressing is applied only to the space from FFE20H to FFF1FH.
[Operand format]
Identifier
SADDR
Description
Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data
(only the space from FFE20H to FFF1FH is specifiable)
SADDRP
Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data (even address only)
(only the space from FFE20H to FFF1FH is specifiable)
Figure 3-23. Outline of Short Direct Addressing
OP code
FFF1FH
saddr
saddr
FFE20H
Memory
Remark SADDR and SADDRP are used to describe the values of addresses FE20H to FF1FH with 16-bit immediate
data (higher 4 bits of actual address are omitted), and the values of addresses FFE20H to FFF1FH with 20bit immediate data.
Regardless of whether SADDR or SADDRP is used, addresses within the space from FFE20H to FFF1FH
are specified for the memory.
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CHAPTER 3 CPU ARCHITECTURE
3.4.5 SFR addressing
[Function]
SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of
addressing is applied only to the space from FFF00H to FFFFFH.
[Operand format]
Identifier
SFR
SFRP
Description
SFR name
16-bit-manipulatable SFR name (even address only)
Figure 3-24. Outline of SFR Addressing
FFFFFH
OP code
SFR
FFF00H
SFR
Memory
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CHAPTER 3 CPU ARCHITECTURE
3.4.6 Register indirect addressing
[Function]
Register indirect addressing directly specifies the target addresses using the contents of the register pair specified
with the instruction word as an operand address.
[Operand format]
Identifier
Description
−
[DE], [HL] (only the space from F0000H to FFFFFH is specifiable)
−
ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register)
Figure 3-25. Example of [DE], [HL]
FFFFFH
OP code
rp
Target memory
F0000H
Memory
Figure 3-26. Example of ES:[DE], ES:[HL]
FFFFFH
ES
OP code
rp
Target memory
00000H
Memory
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CHAPTER 3 CPU ARCHITECTURE
3.4.7 Based addressing
[Function]
Based addressing uses the contents of a register pair specified with the instruction word as a base address, and 8bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target
address.
[Operand format]
Identifier
Description
−
[HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable)
−
word[B], word[C] (only the space from F0000H to FFFFFH is specifiable)
−
word[BC] (only the space from F0000H to FFFFFH is specifiable)
−
ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register)
−
ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register)
−
ES:word[BC] (higher 4-bit addresses are specified by the ES register)
Figure 3-27. Example of [SP+byte]
FFFFFH
SP
Target memory
F0000H
OP code
byte
Memory
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-28. Example of [HL + byte], [DE + byte]
FFFFFH
rp (HL/DE)
Target memory
F0000H
OP code
byte
Memory
Figure 3-29. Example of word[B], word[C]
FFFFFH
r (B/C)
Target memory
F0000H
OP code
Low Addr.
High Addr.
Memory
Figure 3-30. Example of word[BC]
FFFFFH
rp (BC)
Target memory
F0000H
OP code
Low Addr.
High Addr.
Memory
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-31. Example of ES:[HL + byte], ES:[DE + byte]
FFFFFH
ES
rp (HL/DE)
Target memory
OP code
00000H
byte
Memory
Figure 3-32. Example of ES:word[B], ES:word[C]
FFFFFH
ES
r (B/C)
Target memory
OP code
00000H
Low Addr.
Memory
High Addr.
Figure 3-33. Example of ES:word[BC]
FFFFFH
ES
rp (BC)
Target memory
OP code
00000H
Low Addr.
Memory
High Addr.
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CHAPTER 3 CPU ARCHITECTURE
3.4.8 Based indexed addressing
[Function]
Based indexed addressing uses the contents of a register pair specified with the instruction word as the base
address, and the content of the B register or C register similarly specified with the instruction word as offset address.
The sum of these values is used to specify the target address.
[Operand format]
Identifier
Description
−
[HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable)
−
ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register)
Figure 3-34. Example of [HL+B], [HL+C]
FFFFFH
OP code
rp (HL)
Target memory
F0000H
r (B/C)
Memory
Figure 3-35. Example of ES:[HL+B], ES:[HL+C]
FFFFFH
OP code
ES
rp (HL)
Target memory
00000H
r (B/C)
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CHAPTER 3 CPU ARCHITECTURE
3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing is automatically
employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is
saved/restored upon generation of an interrupt request.
Stack addressing is applied only to the internal RAM area.
[Operand format]
Identifier
−
Description
PUSH AX/BC/DE/HL
POP AX/BC/DE/HL
CALL/CALLT
RET
BRK
RETB
(Interrupt request generated)
RETI
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CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
There are four types of pin I/O buffer power supplies: AVDD0, AVDD, AVDD1, EVDD1, EVDD, and VDD. The relationship
between these power supplies and the pins is shown below.
Table 4-1. Pin I/O Buffer Power Supplies
Power Supply
Corresponding Pins
AVDD0, AVDD
P20 to P27, P150 to P152, P157
AVDD1, EVDD1
P110, P111
EVDD
• Port pins other than P20 to P27, P110, P111, P150 to P152, P157
• RESET, FLMD0 pins
VDD
Pins other than port , RESET, FLMD0 pins
78K0R/Lx3 products are provided with digital I/O ports, which enable variety of control operations. The functions of
each port are shown in Tables 4-2 to 4-4.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate
functions, see CHAPTER 2 PIN FUNCTIONS.
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Table 4-2. Port Functions (78K0R/LF3) (1/2)
Function Name
I/O
I/O
P00
Function
Port 0.
After Reset
Input port
3-bit I/O port.
P01
CAPH
CAPL
Input/output can be specified in 1-bit units.
P02
Alternate Function
VLC3
Use of an on-chip pull-up resistor can be specified by a software
setting.
P10
I/O
P11
Port 1.
Input port
SI20/RxD2/SDA20/
Input/output can be specified in 1-bit units.
INTP6
Input of P10, P11, P14 and P15 can be set to TTL buffer.
P12
SO20/TxD2/TO02
Output of P10 to P15 can be set to N-ch open-drain output (VDD
P13
tolerance).
SO10/TxD1/TO04
P14
Use of an on-chip pull-up resistor can be specified by a software
SI10/RxD1/SDA10/
setting.
INTP4
P15
SCK20/SCL20
6-bit I/O port.
SCK10/SCL10/INTP7
P20
I/O
P21
Port 2.
Digital input ANI0/AMP0- Note 1
7-bit I/O port.
port
ANI1/AMP0O
Input/output can be specified in 1-bit units.
P22
ANI2/AMP0+
Note 1
P23
ANI3/AMP1-
P24
ANI4/AMP1O
P25
ANI5/AMP1+
P26
Note 1
Note 1
Note 1
Note 1
ANI6
P30
I/O
P31
Port 3.
Input port
TI03/TO00/RTC1HZ/
4-bit I/O port.
INTP1
Input/output can be specified in 1-bit units.
TI00/TO03/RTCDIV/
Use of an on-chip pull-up resistor can be specified by a software
RTCCL/PCLBUZ1/
setting.
INTP2
TI01/TO01/INTP5/
P32
PCLBUZ0
P33
P40
TI07/TO07/INTP3
Note
I/O
Port 4.
Input port
TOOL0
2-bit I/O port.
Input/output can be specified in 1-bit units.
P41
Use of an on-chip pull-up resistor can be specified by a software
TOOL1
setting.
Notes 1.
2.
AMPxx applies to μ PD78F150xA only.
If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally.
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Table 4-2. Port functions (78K0R/LF3) (2/2)
Function Name
P50
I/O
I/O
Function
Port 5.
After Reset
Input port
8-bit I/O port.
P51
SEG28/TI02
Use of an on-chip pull-up resistor can be specified by a software
P53
SEG27/TI04
setting.
P54 to P57
P90 to P92
SEG30/RxD3
SEG29/TxD3
Input/output can be specified in 1-bit units.
P52
Alternate Function
SEG26 to SEG23
I/O
Port 9.
Input port
SEG22 to SEG20
Input port
SEG11
3-bit I/O port.
Inputs/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
P100
I/O
Port 10.
1-bit I/O port.
Inputs/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
P110
I/O
Port 11.
Input port
2-bit I/O port.
P111
ANO0
Note
ANO1
Note
Inputs/output can be specified in 1-bit units.
P120
P121
I/O
Input
Port 12.
Input port
1-bit I/O port and 4-bit input port.
INTP0/EXLVI
X1
For only P120, input/output can be specified in 1-bit units.
P122
For only P120, use of an on-chip pull-up resistor can be
X2/EXCLK
P123
specified by a software setting.
XT1
P124
P130
XT2
Output
Port 13.
Output port
−
1-bit output port.
P140 to P147
I/O
Port 14.
Input port
SEG19 to SEG12
Port 15.
Digital
ANI15/AVREFM
1-bit I/O port.
input port
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
P157
I/O
Note
Input/output can be specified in 1-bit units.
Note ANOx and AVREFM apply to μ PD78F150xA only.
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Table 4-3. Port functions (78K0R/LG3) (1/2)
Function Name
I/O
I/O
P00
Function
Port 0.
After Reset
Input port
3-bit I/O port.
P01
CAPH
CAPL
Input/output can be specified in 1-bit units.
P02
Alternate Function
VLC3
Use of an on-chip pull-up resistor can be specified by a software
setting.
I/O
P10
P11
Input port
SCK20/SCL20
7-bit I/O port.
SI20/RxD2/SDA20/
Input/output can be specified in 1-bit units.
INTP6
Input of P10, P11, P14 and P15 can be set to TTL buffer.
P12
Port 1.
SO20/TxD2/TO02
Output of P10 to P15 can be set to N-ch open-drain output (VDD
P13
tolerance).
SO10/TxD1/TO04
P14
Use of an on-chip pull-up resistor can be specified by a software
SI10/RxD1/SDA10/
setting.
INTP4
P15
SCK10/SCL10/INTP7
P16
TI05/TO05/INTP10
I/O
P20
P21
Port 2.
Digital input ANI0/AMP0- Note 1
8-bit I/O port.
port
ANI1/AMP0O
Input/output can be specified in 1-bit units.
P22
ANI2/AMP0+
Note 1
P23
ANI3/AMP1-
P24
ANI4/AMP1O
P25
ANI5/AMP1+
P26
ANI6/AMP2-
P27
ANI7/AMP2O
P30
I/O
P31
Port 3.
Input port
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
TI03/TO00/RTC1HZ/
5-bit I/O port.
INTP1
Input/output can be specified in 1-bit units.
TI00/TO03/RTCDIV/
Use of an on-chip pull-up resistor can be specified by a software
RTCCL/PCLBUZ1/
setting.
INTP2
TI01/TO01/INTP5/
P32
PCLBUZ0
P33
TI07/TO07/INTP3
P34
P40
TI06/TO06/INTP8
Note 2
I/O
Port 4.
Input port
TOOL0
2-bit I/O port.
Input/output can be specified in 1-bit units.
P41
Use of an on-chip pull-up resistor can be specified by a software
TOOL1
setting.
Notes 1.
2.
AMPxx applies to μ PD78F150xA only.
If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally.
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Table 4-3. Port functions (78K0R/LG3) (2/2)
Function Name
I/O
I/O
P50
Function
Port 5.
After Reset
Input port
8-bit I/O port.
P51
SEG37/TI02
Use of an on-chip pull-up resistor can be specified by a software
P53
SEG36/TI04
setting.
P54 to P57
SEG35 to SEG32
I/O
P60
SEG39/RxD3
SEG38/TxD3
Input/output can be specified in 1-bit units.
P52
Alternate Function
Port 6.
Input port
2-bit I/O port.
P61
SCL0
SDA0
Output is N-ch open-drain output (6 V tolerance).
Input/output can be specified in 1-bit units.
P80
I/O
Port 8.
Input port
3-bit I/O port.
P81
RxD0/SI00/INTP9
Inputs/output can be specified in 1-bit units.
P82
SCK00/INTP11
TxD0/SO00
Output of P80 and P82 can be set to N-ch open-drain output
(VDD tolerance).
Use of an on-chip pull-up resistor can be specified by a software
setting.
P90 to P97
I/O
Port 9.
Input port
SEG31 to SEG24
Input port
SEG15
8-bit I/O port.
Inputs/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
P100
I/O
Port 10.
1-bit I/O port.
Inputs/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
I/O
P110
Port 11.
Input port
2-bit I/O port.
P111
ANO0
Note
ANO1
Note
Inputs/output can be specified in 1-bit units.
P120
I/O
P121
Input
Port 12.
Input port
1-bit I/O port and 4-bit input port.
INTP0/EXLVI
X1
For only P120, input/output can be specified in 1-bit units.
P122
For only P120, use of an on-chip pull-up resistor can be
X2/EXCLK
P123
specified by a software setting.
XT1
P124
XT2
P130
Output
Port 13.
−
Output port
1-bit output port.
P140 to P147
I/O
Port 14.
Input port
SEG23 to SEG16
Port 15.
Digital
ANI8/AMP2+
4-bit I/O port.
input port
ANI9
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
P150
P151
P152
I/O
Input/output can be specified in 1-bit units.
ANI10
ANI15/AVREFM
P157
Note
Note
Note
ANOx, AMP2+, and AVREFM apply to μ PD78F150xA only.
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Table 4-4. Port functions (78K0R/LH3) (1/3)
Function Name
I/O
I/O
P00
Function
Port 0.
After Reset
Input port
3-bit I/O port.
P01
CAPH
CAPL
Input/output can be specified in 1-bit units.
P02
Alternate Function
VLC3
Use of an on-chip pull-up resistor can be specified by a software
setting.
I/O
P10
P11
Port 1.
Input port
SI20/RxD2/SDA20/
Input/output can be specified in 1-bit units.
INTP6
Input of P10, P11, P14 and P15 can be set to TTL buffer.
P12
SCK20/SCL20
8-bit I/O port.
SO20/TxD2/TO02
Output of P10 to P15 can be set to N-ch open-drain output (VDD
P13
tolerance).
SO10/TxD1/TO04
P14
Use of an on-chip pull-up resistor can be specified by a software
SI10/RxD1/SDA10/
setting.
INTP4
P15
SCK10/SCL10/INTP7
P16
TI05/TO05/INTP10
−
P17
I/O
P20
P21
Port 2.
Digital input ANI0/AMP0- Note 1
8-bit I/O port.
port
ANI1/AMP0O
Input/output can be specified in 1-bit units.
P22
ANI2/AMP0+
Note 1
P23
ANI3/AMP1-
P24
ANI4/AMP1O
P25
ANI5/AMP1+
P26
ANI6/AMP2-
P27
ANI7/AMP2O
I/O
P30
P31
Port 3.
Input port
Note 1
Note 1
Note
Note 1
Note 1
Note 1
TI03/TO00/RTC1HZ/
5-bit I/O port.
INTP1
Input/output can be specified in 1-bit units.
TI00/TO03/RTCDIV/
Use of an on-chip pull-up resistor can be specified by a software
RTCCL/PCLBUZ1/
setting.
INTP2
TI01/TO01/INTP5/
P32
PCLBUZ0
P33
TI07/TO07/INTP3
P34
P40
TI06/TO06/INTP8
Note 2
I/O
Port 4.
Input port
TOOL0
2-bit I/O port.
Input/output can be specified in 1-bit units.
P41
Use of an on-chip pull-up resistor can be specified by a software
TOOL1
setting.
Notes 1.
2.
AMPxx applies to μ PD78F150xA only.
If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally.
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Table 4-4. Port functions (78K0R/LH3) (2/3)
Function Name
I/O
I/O
P50
Function
Port 5.
After Reset
Input port
8-bit I/O port.
P51
SEG51/TI02
Use of an on-chip pull-up resistor can be specified by a software
P53
SEG50/TI04
setting.
P54 to P57
SEG49 to SEG46
I/O
P60
SEG53/RxD3
SEG52/TxD3
Input/output can be specified in 1-bit units.
P52
Alternate Function
Port 6.
Input port
2-bit I/O port.
P61
SCL0
SDA0
Output is N-ch open-drain output (6 V tolerance).
Input/output can be specified in 1-bit units.
P70 to P74
I/O
Port 7.
Input port
8-bit I/O port.
P75
KR5/SCK01
Input/output can be specified in 1-bit units.
P76
KR6/SI01
Input of P75 and P76 can be set to TTL buffer.
P77
KR0 to KR4
KR7/SO01
Output of P75 and P77 can be set to N-ch open-drain output
(VDD tolerance).
Use of an on-chip pull-up resistor can be specified by a software
setting.
I/O
P80
Port 8.
Input port
8-bit I/O port.
P81
RxD0/SI00/INTP9
Inputs/output can be specified in 1-bit units.
P82
TxD0/SO00
Output of P80 and P82 can be set to N-ch open-drain output
P83
(VDD tolerance).
P84
Use of an on-chip pull-up resistor can be specified by a software
−
TI10/TO10
setting.
P85
SCK00/INTP11
TI11/TO11
P86
TI12/TO12
P87
TI13/TO13
P90 to P97
I/O
Port 9.
Input port
SEG45 to SEG38
Input port
SEG29 to SEG27
8-bit I/O port.
Inputs/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
P100 to P102
I/O
Port 10.
3-bit I/O port.
Inputs/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
P110
I/O
P111
Port 11.
Input port
2-bit I/O port.
ANO0
Note
ANO1
Note
Inputs/output can be specified in 1-bit units.
P120
P121
I/O
Input
Port 12.
1-bit I/O port and 4-bit input port.
Input port
INTP0/EXLVI
X1
For only P120, input/output can be specified in 1-bit units.
P122
P123
For only P120, use of an on-chip pull-up resistor can be
specified by a software setting.
P124
Note
X2/EXCLK
XT1
XT2
ANOx applies to μ PD78F150xA only.
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Table 4-4. Port functions (78K0R/LH3) (3/3)
Function Name
P130
I/O
Output
Function
Port 13.
After Reset
Alternate Function
Output port
−
1-bit output port.
P140 to P147
I/O
Port 14.
Input port
SEG37 to SEG30
Port 15.
Digital
ANI8/AMP2+
4-bit I/O port.
input port
ANI9
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a software
setting.
P150
P151
I/O
Note
Input/output can be specified in 1-bit units.
P152
ANI10
P157
ANI15/AVREFM
Note
Note
AMP2+ and AVREFM apply to μ PD78F150xA only.
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4.2 Port Configuration
Ports include the following hardware.
Table 4-5. Port Configuration
Item
Control registers
Configuration
• 78K0R/LF3
Port mode registers (PMxx)
: PM0 to PM5, PM9 to PM12, PM14, PM15
Port registers (Pxx)
: P0 to P5, P9 to P15
Pull-up resistor option registers (PUxx)
: PU0, PU1, PU3 to PU5, PU9, PU10, PU12, PU14
Port input mode registers (PIM1)
Port output mode registers (POM1)
A/D port configuration register (ADPC)
Port function register (PFALL)
Input switch control register (ISC)
• 78K0R/LG3
Port mode registers (PMxx)
: PM0 to PM6, PM8 to PM12, PM14, PM15
Port registers (Pxx)
: P0 to P6, P8 to P15
Pull-up resistor option registers (PUxx)
: PU0, PU1, PU3 to PU5, PU8 to PU10, PU12, PU14
Port input mode registers (PIM1)
Port output mode registers (POM1, POM8)
A/D port configuration register (ADPC)
Port function register (PFALL)
Input switch control register (ISC)
• 78K0R/LH3
Port mode registers (PMxx)
: PM0 to PM12, PM14, PM15
Port registers (Pxx)
: P0 to P15
Pull-up resistor option registers (PUxx)
: PU0, PU1, PU3 to PU5, PU7 to PU10, PU12, PU14
Port input mode registers (PIM1, PIM7)
Port output mode registers (POM1, POM7, POM8)
A/D port configuration register (ADPC)
Port function register (PFALL)
Input switch control register (ISC)
Port
• 78K0R/LF3: Total: 51 (CMOS I/O: 46, CMOS output: 1, CMOS input: 4)
• 78K0R/LG3: Total: 67 (CMOS I/O: 60, CMOS output: 1, CMOS input: 4, N-ch open drain I/O: 2)
• 78K0R/LH3: Total: 83 (CMOS I/O: 76, CMOS output: 1, CMOS input: 4, N-ch open drain I/O: 2)
Pull-up resistor
• 78K0R/LF3: Total: 36
• 78K0R/LG3: Total: 46
• 78K0R/LH3: Total: 62
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4.2.1 Port 0
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P00/CAPH
√
P01/CAPL
√
P02/VLC3
√
Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port
mode register 0 (PM0). When the P00 to P02 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 0 (PU0).
This port can also be used for connecting a capacitor for LCD controller/driver, and power supply voltage pin for driving
the LCD.
Reset signal generation sets port 0 to input mode.
Figures 4-1 and 4-2 show block diagrams of port 0.
Caution To use P00/CAPH, P01/CAPL, and P02/VLC3 as a general-purpose port, set bit 5 (MDSET1) and bit 4
(MDSET0) of LCD mode register (LCDMD) to “0”, which is the same as their default status setting.
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Figure 4-1. Block Diagram of P00 and P01
EVDD
WRPU
PU0
PU00, PU01
P-ch
Selector
WRPORT
P0
Output latch
(P00, P01)
Selector
Internal bus
RD
WRPM
PM0
P00/CAPH,
P01/CAPL
PM00, PM01
CAPH, CAPL
WRLCDMD
LCDMD
MDSET1, MDSET0
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
LCDMD: LCD mode register
RD:
Read signal
WR××:
Write signal
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Figure 4-2. Block Diagram of P02
EVDD
WRPU
PU0
PU02
P-ch
Selector
RD
P0
Output latch
(P02)
Selector
Internal bus
WRPORT
WRPM
PM0
P02/VLC3
PM02
WRLCDM
VLC3
LCDM
LCDM0 to LCDM2
WRLCDMD
LCDMD
MDSET1, MDSET0
P0:
Port register 0
PU0:
Pull-up resistor option register 0
PM0:
Port mode register 0
LCDM:
LCD display mode register
LCDMD: LCD mode register
RD:
Read signal
WR××:
Write signal
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4.2.2 Port 1
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P10/SCK20/SCL20
√
P11/SI20/RxD2/SDA20/INTP6
√
P12/SO20/TxD2/TO02
√
P13/SO10/TxD1/TO04
√
P14/SI10/RxD1/SDA10/INTP4
√
P15/SCK10/SCL10/INTP7
√
P16/TI05/TO05/INTP10
−
√
√
P17
−
−
√
Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port
mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 1 (PU1).
Input to the P10, P11, P14, and P15 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit
units using port input mode register 1 (PIM1).
Output from the P10 to P15 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port
output mode register 1 (POM1).
This port can also be used for serial interface clock I/O, data I/O, timer I/O, and external interrupt request input,.
Reset signal generation sets port 1 to input mode.
Figures 4-3 to 4-6 show block diagrams of port 1.
Cautions 1.
To use P10/SCK20/SCL20 and P11/SI20/RxD2/SDA20/INTP6 as a general-purpose port, note the
serial array unit 1 setting. For details, refer to Table 14-9 Relationship Between Register Settings
and Pins (Channel 0 of unit 1: CSI20, UART2 Reception, IIC20).
2.
To use P12/TO02/SO20/TxD2 as a general-purpose port, set bit 2 (TO02) of timer output register 0
(TO0) and bit 2 (TOE02) of timer output enable register 0 (TOE0) to “0”, which is the same as
their default status setting. And as a general-purpose port, note the serial array unit 1 setting.
For details of serial array unit 1 setting, refer to Table 14-9 Relationship Between Register
Settings and Pins (Channel 0 of unit 1: CSI20, UART2 Reception, IIC20).
3.
To use P13/TO04/SO10/TxD1 as a general-purpose port, set bit 4 (TO04) of timer output register 0
(TO0) and bit 4 (TOE04) of timer output enable register 0 (TOE0) to “0”, which is the same as
their default status setting. And as a general-purpose port, note the serial array unit 0 setting.
For details of serial array unit 0 setting, refer to Table 14-7 Relationship Between Register
Settings and Pins (Channel 2 of unit 0: CSI10, UART1 Transmission, IIC10)
4.
To use P14/SI10/RxD1/SDA10/INTP4 and P15/SCK10/SCL10/INTP7 as a general-purpose port,
note the serial array unit 0 setting. For details, refer to Table 14-7 Relationship Between Register
Settings and Pins (Channel 2 of unit 0: CSI10, UART1 Transmission, IIC10)
5.
To use P16/TO05/TI05/INTP10 as a general-purpose port, set bit 5 (TO05) of timer output register
0 (TO0) and bit 5 (TOE05) of timer output enable register 0 (TOE0) to “0”, which is the same as
their default status setting.
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Figure 4-3. Block Diagram of P10, P11, P14, and P15
WRPIM
PIM1
PIM10, PIM11,
PIM14, PIM15
EVDD
WRPU
PU1
PU10, PU11,
PU14, PU15
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
WRPORT
TTL
P1
Output latch
(P10, P11,
P14, P15)
WRPOM
POM1
P10/SCK20/SCL20,
P11/SI20/RxD2/SDA20/INTP6,
P14/SI10/RxD1/SDA10/INTP4,
P15/SCK10/SCL10/INTP7
POM10, POM11,
POM14, POM15
WRPM
PM1
PM10, PM11,
PM14, PM15
Alternate
function
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PIM1:
Port input mode register 1
POM1: Port output mode register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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Figure 4-4. Block Diagram of P12 and P13
EVDD
WRPU
PU1
PU12, PU13
P-ch
Internal bus
Selector
RD
WRPORT
P1
Output latch
(P12, P13)
WRPOM
P12/SO20/TxD2/TO02,
P13/SO10/TxD1/TO04
POM1
POM12, POM13
WRPM
PM1
PM12, PM13
Alternate
function
(serial interface)
Alternate
function (timer)
P1:
Port register 1
PU1:
Pull-up resistor option register 1
POM1: Port output mode register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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Figure 4-5. Block Diagram of P16
EVDD
WRPU
PU1
PU16
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P1
Output latch
(P16)
P16/TI05/TO05/INTP10
WRPM
PM1
PM16
Alternate
function
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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Figure 4-6. Block Diagram of P17
EVDD
WRPU
PU1
PU17
P-ch
Internal bus
RD
Selector
WRPORT
P1
Output latch
(P17)
WRPM
P17
PM1
PM17
P1:
Port register 1
PU1:
Pull-up resistor option register 1
PM1:
Port mode register 1
RD:
Read signal
WR××: Write signal
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4.2.3 Port 2
μ PD78F150xA
μ PD78F151xA
78K0R/LF3
78K0R/LG3
78K0R/LH3
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins)
(100 pins)
(128 pins)
(80 pins)
(100 pins)
(128 pins)
P20/ANI0/AMP0-
√
P20/ANI0
P21/ANI1/AMP0O
√
P20/ANI1
P22/ANI2/AMP0+
√
P20/ANI2
P23/ANI3/AMP1-
√
P20/ANI3
P24/ANI4/AMP1O
√
P20/ANI4
P25/ANI5/AMP1+
√
P20/ANI5
P26/ANI6/AMP2-
P26/ANI6
√
P27/ANI7/AMP2O
−
√
P26/ANI6
−
P27/ANI7
Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port
mode register 2 (PM2).
This port can also be used for A/D converter analog input, and operational amplifier I/O.
To use P20/ANI0/AMP0- to P27/ANI7/AMP2O as digital input pins, set them in the digital I/O mode by using the A/D
port configuration register (ADPC) and in the input mode by using PM2. Use these pins starting from the lower bit.
To use P20/ANI0/AMP0- to P27/ANI7/AMP2O as digital output pins, set them in the digital I/O mode by using ADPC
and in the output mode by using PM2.
To use P20/ANI0/AMP0- to P27/ANI7/AMP2O as analog input pins, set them in the analog input mode by using the A/D
port configuration register (ADPC) and in the input mode by using PM2. Use these pins starting from the upper bit.
All P20/ANI0/AMP0- to P27/ANI7/AMP2O are set in the digital input mode when the reset signal is generated.
Figures 4-7 to 4-9 show block diagrams of port 2.
Caution Make the AVDD0 pin the same potential as the EVDD or VDD pin when port 2 is used as a digital port.
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Table 4-6. Setting Functions of ANI0/AMP0-/P20, ANI2/AMP0+/P22, ANI3/AMP1-/P23, ANI5/AMP1+/P25, and
ANI6/AMP2-/P26 Pins
ADPC
PM2 registers
OAENn bit
ADS register
ANI0/AMP0-/P20,
ANI2/AMP0+/P22, ANI3/AMP1-
register
/P23, ANI5/AMP1+/P25, and
ANI6/AMP2-/P26 Pins
Digital I/O
Input mode
selection
Output mode
Analog input
Input mode
0
−
Digital input
1
−
Setting prohibited
0
−
Digital output
1
−
Setting prohibited
0
Selects ANI.
selection
1
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
Operational amplifier input
−
Output mode
Analog input (to be converted)
−
Setting prohibited
Table 4-7. Setting Functions of ANI1/AMP0O/P21, ANI4/AMP1O/P24, and ANI7/AMP2O/P27 Pins
ADPC
PM2 register
OAENn bit
ADS register
ANI1/AMP0O/P21,
ANI4/AMP1O/P24, and
register
ANI7/AMP2O/P27 Pins
Digital I/O
Input mode
selection
Output mode
Analog input
Input mode
0
−
Digital input
1
−
Setting prohibited
0
−
Digital output
1
−
Setting prohibited
0
selection
1
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Operational amplifier output (to be
converted)
Does not select ANI.
Operational amplifier output (not to
be converted)
Output mode
Remark
78K0R/LF3:
−
−
Setting prohibited
n = 0, 1
78K0R/LG3, 78K0R/LH3: n = 0 to 2
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Figure 4-7. Block Diagram of P20, P23, and P26
Selector
RD
Internal bus
WRPORT
P2
Output latch
(P20, P23, P26)
P20/ANI0/AMP0-,
P23/ANI3/AMP1-,
P26/ANI6/AMP2-
WRPM
PM2
PM20, PM23,
PM26
A/D converter
Operational amplifier (-) input
P2:
Port register 2
PM2:
Port mode register 2
RD:
Read signal
WR××: Write signal
Figure 4-8. Block Diagram of P21, P24, and P27
Internal bus
Selector
RD
WRPORT
P2
Output latch
(P21, P24, P27)
WRPM
PM2
P21/ANI1/AMP0O,
P24/ANI4/AMP1O,
P27/ANI7/AMP2O
PM21, PM24,
PM27
A/D converter
Operational amplifier output
P2:
Port register 2
PM2:
Port mode register 2
RD:
Read signal
WR××: Write signal
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Figure 4-9. Block Diagram of P22 to P25
Selector
RD
Internal bus
WRPORT
P2
Output latch
(P22, P25)
P22/ANI2/AMP0+,
P25/ANI5/AMP1+
WRPM
PM2
PM22, PM25
A/D converter
Operational amplifier (+) input
P2:
Port register 2
PM2:
Port mode register 2
RD:
Read signal
WR××: Write signal
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4.2.4 Port 3
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
√
P30/TI03/TO00/RTC1HZ/
INTP1
√
P31/TI00/TO03/RTCDIV/
RTCCL/PCLBUZ1/INTP2
√
P32/TI01/TO01/PCLBUZ0/
INTP5
√
P33/TI07/TO07/INTP3
P34/TI06/TO06/INTP8
−
√
Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port
mode register 3 (PM3). When the P30 to P34 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 3 (PU3).
This port can also be used for timer I/O, real-time counter clock output, correction clock output, clock output/buzzer
output, and external interrupt request input.
Reset signal generation sets port 3 to input mode.
Figure 4-10 shows a block diagram of port 3.
Cautions 1.
To use P30/TO00/TI03/RTC1HZ/INTP1 as a general-purpose port, set bit 5 (RCLOE1) of real-time
counter control register 0 (RTCC0), bit 0 (TO00) of timer output register 0 (TO0) and bit 0 (TOE00)
of timer output enable register 0 (TOE0) to “0”, which is the same as their default status setting.
2.
To use P31/TO03/TI00/RTCDIV/RTCCL/PCLBUZ1/INTP2 as a general-purpose port, set bit 4
(RCLOE0) of real-time counter control register 0 (RTCC0), bit 6 (RCLOE2) of real-time counter
control register 2 (RTCC2), bit 3 (TO03) of timer output register 0 (TO0), bit 3 (TOE03) of timer
output enable register 0 (TOE0) and bit 7 of clock output select register 1 (CKS1) to “0”, which is
the same as their default status setting.
3.
To use P32/TO01/TI01/INTP5/PCLBUZ0 as a general-purpose port, set bit 1 (TO01) of timer output
register 0 (TO0), bit 1 (TOE01) of timer output enable register 0 (TOE0) and bit 7 of clock output
select register 0 (CKS0) to “0”, which is the same as their default status setting.
4.
To use P33/TO07/TI07/INTP3 and P34/TO06/TI06/INTP8 as a general-purpose port, set bit 7, 6
(TO07, TO06) of timer output register 0 (TO0), and bit 7, 6 (TOE07, TOE06) of timer output enable
register 0 (TOE0) to “0”, which is the same as their default status setting.
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Figure 4-10. Block Diagram of P30 to P34
EVDD
WRPU
PU3
PU30 to PU34
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P3
Output latch
(P30 to P34)
WRPM
PM3
P30/TI03/TO00/RTC1HZ/INTP1,
P31/TI00/TO03/RTCDIV/RTCCL/PCLBUZ1/INTP2,
P32/TI01/TO01/PCLBUZ0/INTP5,
P33/TI07/TO07/INTP3,
P34/TI06/TO06/INTP8
PM30 to PM34
Alternate
function
P3:
Port register 3
PU3:
Pull-up resistor option register 3
PM3:
Port mode register 3
RD:
Read signal
WR××: Write signal
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4.2.5 Port 4
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P40/TOOL0
√
P41/TOOL1
√
Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port
mode register 4 (PM4). When the P40 and P41 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 2 (PU2)Note.
This port can also be used for flash memory programmer/debugger data I/O and debugger clock output.
Reset signal generation sets port 4 to input mode.
Figure 4-11 shows a block diagram of port 4.
Note When a tool is connected, the P40 and P41 pins cannot be connected to a pull-up resistor.
Caution When a tool is connected, the P40 pin cannot be used as a port pin.
When the on-chip debug function is used, P41 pin can be used as follows by the mode setting on the
debugger.
• 1-line mode: can be used as a port (P41).
• 2-line mode: used as a TOOL1 pin and cannot be used as a port (P41).
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Figure 4-11. Block Diagram of P40, P41
EVDD
WRPU
PU4
PU40, PU41
P-ch
Alternate
function
Selector
WRPORT
P4
Output latch
(P40, P41)
WRPM
Selector
Internal bus
RD
P40/TOOL0,
P41/TOOL1
PM4
PM40, PM41
Alternate
function
P4:
Port register 4
PU4:
Pull-up resistor option register 4
PM4:
Port mode register 4
RD:
Read signal
WR××: Write signal
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4.2.6 Port 5
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P50/RxD3/SEGxx
√ (xx = 30)
√ (xx = 39)
√ (xx = 53)
P51/TxD3/SEGxx
√ (xx = 29)
√ (xx = 38)
√ (xx = 52)
P52/TI02/SEGxx
√ (xx = 28)
√ (xx = 37)
√ (xx = 51)
P53/TI04/SEGxx
√ (xx = 27)
√ (xx = 36)
√ (xx = 50)
P54/SEGxx
√ (xx = 26)
√ (xx = 35)
√ (xx = 49)
P55/SEGxx
√ (xx = 25)
√ (xx = 34)
√ (xx = 48)
P56/SEGxx
√ (xx = 24)
√ (xx = 33)
√ (xx = 47)
P57/SEGxx
√ (xx = 23)
√ (xx = 32)
√ (xx = 46)
Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port
mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 5 (PU5).
This port can also be used for serial interface data I/O, timer input and segment output of LCD controller/driver.
Reset signal generation sets port 5 to input mode.
Figures 4-12 to 4-14 show block diagrams of port 5.
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Figure 4-12. Block Diagram of P50, P52, and P53
EVDD
WRPU
PU5
PU50, PU52,
PU53
P-ch
WRISC
ISC
ISC2, ISC3,
ISC4
Alternate
function
Selector
WRPORT
P5
Output latch
(P50, P52, P53)
WRPM
Selector
Internal bus
RD
P50/SEGxx/RxD3,
P52/SEGxx/TI02,
P53/SEGxx/TI04
PM5
PM50, PM52,
PM53
LCD controller/driver
WRPF
PFALL
PF5L
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
PFALL: Port function register
ISC:
Input switch control register
RD:
Read signal
WR××: Write signal
Remark
78K0R/LF3: P50/SEG30/RxD3, P52/SEG28/TI02, P53/SEG27/TI04
78K0R/LG3: P50/SEG39/RxD3, P52/SEG37/TI02, P53/SEG36/TI04
78K0R/LH3: P50/SEG53/RxD3, P52/SEG51/TI02, P53/SEG50/TI04
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Figure 4-13. Block Diagram of P51
EVDD
WRPU
PU5
PU51
P-ch
Selector
RD
P5
Output latch
(P51)
WRPM
Selector
Internal bus
WRPORT
P51/SEGxx/TxD3
PM5
PM51
Alternate
function
LCD controller/driver
WRPF
PFALL
PF5L
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
PFALL: Port function register
RD:
Read signal
WR××: Write signal
Remark
78K0R/LF3: P51/SEG29/TxD3
78K0R/LG3: P51/SEG38/TxD3
78K0R/LH3: P51/SEG52/TxD3
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Figure 4-14. Block Diagram of P54 to P57
EVDD
WRPU
PU5
PU54 to PU57
P-ch
WRPORT
P5
Output latch
(P54 to P57)
Selector
Internal bus
Selector
RD
P54/SEGxx to
P57/SEGxx
WRPM
PM5
PM54 to PM57
LCD controller/driver
WRPF
PFALL
PF5H
P5:
Port register 5
PU5:
Pull-up resistor option register 5
PM5:
Port mode register 5
PFALL: Port function register
RD:
Read signal
WR××: Write signal
Remark
78K0R/LF3: P54/SEG26 to P57/SEG23
78K0R/LG3: P54/SEG35 to P57/SEG32
78K0R/LH3: P54/SEG53 to P57/SEG50
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4.2.7 Port 6
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P60/SCL0
−
√
P61/SDA0
−
√
Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port
mode register 6 (PM6).
The output is N-ch open-drain output (6 V tolerance).
This port can also be used for serial interface data I/O and clock I/O.
Reset signal generation sets port 6 to input mode.
Figure 4-15 shows a block diagram of port 6.
Caution When using P60/SCL0 and P61/SDA0 as a general-purpose port, stop the operation of serial interface
IICA.
Figure 4-15. Block Diagram of P60 and P61
Alternate
function
Selector
RD
Internal bus
WRPORT
P6
Output latch
(P60, P61)
P60/SCL0,
P61/SDA0
WRPM
PM6
PM60, PM61
Alternate
function
P6:
Port register 6
PM6:
Port mode register 6
RD:
Read signal
WR××: Write signal
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4.2.8 Port 7
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P70/KR0
−
√
P71/KR1
−
√
P72/KR2
−
√
P73/KR3
−
√
P74/KR4
−
√
P75/SCK01
−
√
P76/KR6/SI01
−
√
P77/KR7/SO01
−
√
Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port
mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 7 (PU7).
Input to the P75 and P76 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
port input mode register 7 (PIM7).
Output from the P75 and P77 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port
output mode register 7 (POM7).
This port can also be used for key return input, serial interface clock I/O, and data I/O.
Reset signal generation sets port 7 to input mode.
Figures 4-16 to 4-19 show block diagrams of port 7.
Caution To use P75/SCK01/KR5, P76/SI01/KR6, and P77/SO01/KR7, as a general-purpose port, note the serial
array unit 0 setting. For details, refer to Table 14-6 Relationship Between Register Settings and Pins
(Channel 1 of unit 0: CSI01, UART0 Reception).
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Figure 4-16. Block Diagram of P70 to P74
EVDD
WRPU
PU7
PU70 to PU74
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P7
Output latch
(P70 to P74)
P70/KR0 to P74/KR4
WRPM
PM7
PM70 to PM74
P7:
Port register 7
PU7:
Pull-up resistor option register 7
PM7:
Port mode register 7
RD:
Read signal
WR××: Write signal
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Figure 4-17. Block Diagram of P75
WRPIM
PIM7
PIM75
EVDD
WRPU
PU7
PU75
P-ch
Alternate
function
CMOS
Selector
Internal bus
RD
TTL
WRPORT
P7
Output latch
(P75)
P75/KR5/SCK01
WRPOM
POM7
POM75
WRPM
PM7
PM75
Alternate
function
P7:
Port register 7
PU7:
Pull-up resistor option register 7
PIM7:
Port input mode register 7
POM7: Port output mode register 7
PM7:
Port mode register 7
RD:
Read signal
WR××: Write signal
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Figure 4-18. Block Diagram of P76
WRPIM
PIM7
PIM76
EVDD
WRPU
PU7
PU76
P-ch
Internal bus
Alternate
function
CMOS
Selector
RD
TTL
WRPORT
P7
Output latch
(P76)
P76/KR6/SI01
WRPM
PM7
PM76
P7:
Port register 7
PU7:
Pull-up resistor option register 7
PIM7:
Port input mode register 7
PM7:
Port mode register 7
RD:
Read signal
WR××: Write signal
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Figure 4-19. Block Diagram of P77
EVDD
WRPU
PU77
PU77
RD
P-ch
Internal bus
Selector
Alternate
function
WRPORT
P7
Output latch
(P77)
P77/KR7/SO01
WRPOM
POM7
POM77
WRPM
PM7
PM77
Alternate
function
P7:
Port register 7
PU7:
Pull-up resistor option register 7
POM7: Port output mode register 7
PM7:
Port mode register 7
RD:
Read signal
WR××: Write signal
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4.2.9 Port 8
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P80/SCK00/INTP11
−
√
√
P81/RxD0/SI00/INTP9
−
√
√
P82/TxD0/SO00
−
√
√
P83
−
−
√
P84/TO10/TI10
−
−
√
P85/TO11/TI11
−
−
√
P86/TO12/TI12
−
−
√
P87/TO13/TI13
−
−
√
Port 8 is an I/O port with an output latch. Port 8 can be set to the input mode or output mode in 1-bit units using port
mode register 8 (PM8). When the P80 to P87 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 8 (PU8).
Output from the P80 and P82 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port
output mode register 8 (POM8).
This port can also be used for serial interface clock I/O, data I/O, timer I/O, and external interrupt request input.
Reset signal generation sets port 8 to input mode.
Figures 4-20 to 4-24 show block diagrams of port 8.
Caution To use P80/SCK00/INTP11, P81/RxD0/SI00/INTP9, and P82/SO00/TxD0, as a general-purpose port,
note the serial array unit 0 setting. For details, refer to Table 14-5 Relationship Between Register
Settings and Pins (Channel 0 of unit 0: CSI00, UART0 Reception).
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Figure 4-20. Block Diagram of P80
EVDD
WRPU
PU8
PU80
Alternate
function
Internal bus
Selector
RD
P-ch
WRPORT
P8
Output latch
(P80)
P80/SCK00/INTP11
WRPOM
POM8
POM80
WRPM
PM8
PM80
Alternate
function
P8:
Port register 8
PU8:
Pull-up resistor option register 8
POM8: Port output mode register 8
PM8:
Port mode register 8
RD:
Read signal
WR××: Write signal
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Figure 4-21. Block Diagram of P81
EVDD
WRPU
PU8
PU81
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P8
Output latch
(P81)
P81/RxD0/SI00/INTP9
WRPM
PM8
PM81
P8:
Port register 8
PU8:
Pull-up resistor option register 8
PM8:
Port mode register 8
RD:
Read signal
WR××: Write signal
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Figure 4-22. Block Diagram of P82
EVDD
WRPU
PU8
PU82
P-ch
Internal bus
Selector
RD
WRPORT
P8
Output latch
(P82)
P82/TxD0/SO00
WRPOM
POM8
POM82
WRPM
PM8
PM82
Alternate
function
P8:
Port register 8
PU8:
Pull-up resistor option register 8
POM8: Port output mode register 8
PM8:
Port mode register 8
RD:
Read signal
WR××: Write signal
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Figure 4-23. Block Diagram of P83
EVDD
WRPU
PU8
PU83
P-ch
Internal bus
RD
Selector
WRPORT
P8
Output latch
(P83)
WRPM
P83
PM8
PM83
P8:
Port register 8
PU8:
Pull-up resistor option register 8
PM8:
Port mode register 8
RD:
Read signal
WR××: Write signal
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Figure 4-24. Block Diagram of P84 to P87
EVDD
WRPU
PU8
PU84 to PU87
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P8
Output latch
(P84 to P87)
WRPM
PM8
P84/TI10/TO10,
P85/TI11/TO11,
P86/TI12/TO12,
P87/TI13/TO13
PM84 to PM87
Alternate
function
P8:
Port register 8
PU8:
Pull-up resistor option register 8
PM8:
Port mode register 8
RD:
Read signal
WR××: Write signal
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4.2.10 Port 9
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P90/SEGxx
√ (xx = 22)
√ (xx = 31)
√ (xx = 45)
P91/SEGxx
√ (xx = 21)
√ (xx = 30)
√ (xx = 44)
P92/SEGxx
√ (xx = 20)
√ (xx = 29)
√ (xx = 43)
P93/SEGxx
−
√ (xx = 28)
√ (xx = 42)
P94/SEGxx
−
√ (xx = 27)
√ (xx = 41)
P95/SEGxx
−
√ (xx = 26)
√ (xx = 40)
P96/SEGxx
−
√ (xx = 25)
√ (xx = 39)
P97/SEGxx
−
√ (xx = 24)
√ (xx = 38)
Port 9 is an I/O port with an output latch. Port 9 can be set to the input mode or output mode in 1-bit units using port
mode register 9 (PM9). When the P90 to P97 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 9 (PU9).
This port can also be used for segment output.
Reset signal generation sets port 9 to input mode.
Figures 4-25 and 4-26 show block diagrams of port 9.
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Figure 4-25. Block Diagram of P90 to P93
EVDD
WRPU
PU9
PU90 to PU93
P-ch
WRPORT
P9
Output latch
(P90 to P93)
Selector
Internal bus
Selector
RD
P90/SEGxx to
P93/SEGxx
WRPM
PM9
PM90 to PM93
LCD controller/driver
WRPF
PFALL
PF9L
P9:
Port register 9
PU9:
Pull-up resistor option register 9
PM9:
Port mode register 9
PFALL: Port function register
RD:
Read signal
WR××: Write signal
Remark
78K0R/LF3: P90/SEG22 to P92/SEG20
78K0R/LG3: P90/SEG31 to P93/SEG28
78K0R/LH3: P90/SEG45 to P93/SEG42
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Figure 4-26. Block Diagram of P94 to P97
EVDD
WRPU
PU9
PU94 to PU97
P-ch
WRPORT
P9
Output latch
(P94 to P97)
Selector
Internal bus
Selector
RD
P94/SEGxx to
P97/SEGxx
WRPM
PM9
PM94 to PM97
LCD controller/driver
WRPF
PFALL
PF9H
P9:
Port register 9
PU9:
Pull-up resistor option register 9
PM9:
Port mode register 9
PFALL: Port function register
RD:
Read signal
WR××: Write signal
Remark
78K0R/LG3: P94/SEG27 to P97/SEG24
78K0R/LH3: P94/SEG41 to P97/SEG38
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4.2.11 Port 10
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P100/SEGxx
√ (xx = 11)
√ (xx = 15)
√ (xx = 29)
P101/SEGxx
−
−
√ (xx = 28)
P102/SEGxx
−
−
√ (xx = 27)
Port 10 is an I/O port with an output latch. Port 10 can be set to the input mode or output mode in 1-bit units using port
mode register 10 (PM10). When the P100 to P102 pins are used as an input port, use of an on-chip pull-up resistor can
be specified in 1-bit units by pull-up resistor option register 10 (PU10).
This port can also be used for segment output.
Reset signal generation sets port 10 to input mode.
Figure 4-27 shows a block diagram of port 10.
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Figure 4-27. Block Diagram of P100 to P102
EVDD
WRPU
PU10
PU100 to PU102
P-ch
WRPORT
P10
Output latch
(P100 to P102)
Selector
Internal bus
Selector
RD
P100/SEGxx to
P102/SEGxx
WRPM
PM10
PM100 to PM102
LCD controller/driver
WRPF
PFALL
PF10
P10:
Port register 10
PU10:
Pull-up resistor option register 10
PM10:
Port mode register 10
PFALL: Port function register
RD:
Read signal
WR××: Write signal
Remark
78K0R/LF3: P100/SEG11
78K0R/LG3: P100/SEG15
78K0R/LH3: P100/SEG29 to P102/SEG27
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4.2.12 Port 11
μ PD78F150xA
μ PD78F151xA
78K0R/LF3
78K0R/LG3
78K0R/LH3
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins)
(100 pins)
(128 pins)
(80 pins)
(100 pins)
(128 pins)
P110/ANO0
√
P110
P111/ANO1
√
P111
Port 11 is an I/O port with an output latch. Port 11 can be set to the input mode or output mode in 1-bit units using port
mode register 11 (PM11).
This port can also be used for D/A converter analog output.
Reset signal generation sets port 11 to input mode.
Figure 4-28 shows a block diagram of port 11.
Caution Make the AVDD1 pin the same potential as the EVDD or VDD pin when port 11 is used as a digital port.
Figure 4-28. Block Diagram of P110, P111
Selector
RD
P11
Output latch
(P110, P111)
WRPM
PM11
Selector
Internal bus
WRPORT
P110/ANO0, P111/ANO1
PM110, PM111
WRDAM
D/A converter output
DAM
DACE0, DACE1
P11:
Port register 11
PM11:
Port mode register 11
DAM:
D/A converter mode register
RD:
Read signal
WR××: Write signal
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4.2.13 Port 12
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P120/INTP0/EXLVI
√
P121/X1
√
P122/X2/EXCLK
√
P123/XT1
√
P124/XT2
√
P120 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using
port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up
resistor option register 12 (PU12).
P121 to P124 are 4-bit input ports.
This port can also be used for external interrupt request input, potential input for external low-voltage detection,
connecting resonator for main system clock, connecting resonator for subsystem clock, and external clock input for main
system clock.
Reset signal generation sets port 12 to input mode.
Figures 4-29 to 4-31 show block diagrams of port 12.
Caution
The function setting on P121 to P124 is available only once after the reset release. The port once set
for connection to an oscillator cannot be used as an input port unless the reset is performed.
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Figure 4-29. Block Diagram of P120
EVDD
WRPU
PU12
PU120
P-ch
Alternate
function
Selector
Internal bus
RD
WRPORT
P12
Output latch
(P120)
P120/INTP0/EXLVI
WRPM
PM12
PM120
P12:
Port register 12
PU12:
Pull-up resistor option register 12
PM12:
Port mode register 12
RD:
Read signal
WR××: Write signal
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Figure 4-30. Block Diagram of P121 and P122
Clock generator
CMC
OSCSEL
RD
Internal bus
P122/X2/EXCLK
CMC
EXCLK, OSCSEL
RD
P121/X1
CMC:
Clock operation mode control register
RD:
Read signal
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Figure 4-31. Block Diagram of P123 and P124
Clock generator
CMC
OSCSELS
RD
Internal bus
P124/XT2
CMC
OSCSELS
RD
P123/XT1
CMC:
Clock operation mode control register
RD:
Read signal
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4.2.14 Port 13
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
√
P130
P130 is a port dedicated to 1-bit output and is provided with an output latch.
Figure 4-32 shows a block diagram of port 13.
Figure 4-32. Block Diagram of P130
Internal bus
RD
WRPORT
P13
Output latch
(P130)
P13:
Port register 13
RD:
Read signal
P130
WR××: Write signal
Remark
The P130 pin outputs a low level when it is used as a port function pin and a reset is effected. If P130 is set
to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU
reset signal.
Reset signal
P130
Set by software
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4.2.15 Port 14
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins: μ PD78F15x0A,
(100 pins: μ PD78F15x3A,
(128 pins: μ PD78F15x6A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
78F1507A, 78F15x8A)
P140/SEGxx
√ (xx = 19)
√ (xx = 23)
√ (xx = 37)
P141/SEGxx
√ (xx = 18)
√ (xx = 22)
√ (xx = 36)
P142/SEGxx
√ (xx = 17)
√ (xx = 21)
√ (xx = 35)
P143/SEGxx
√ (xx = 16)
√ (xx = 20)
√ (xx = 34)
P144/SEGxx
√ (xx = 15)
√ (xx = 19)
√ (xx = 33)
P145/SEGxx
√ (xx = 14)
√ (xx = 18)
√ (xx = 32)
P146/SEGxx
√ (xx = 13)
√ (xx = 17)
√ (xx = 31)
P147/SEGxx
√ (xx = 12)
√ (xx = 16)
√ (xx = 30)
Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port
mode register 14 (PM14). When the P140 to P147 pin is used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 14 (PU14).
This port can also be used for segment output.
Reset signal generation sets Port 14 to input mode.
Figures 4-33 and 4-34 show block diagrams of port 14.
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Figure 4-33. Block Diagram of P140 to P143
EVDD
WRPU
PU14
PU140 to PU143
P-ch
WRPORT
P14
Output latch
(P140 to P143)
Selector
Internal bus
Selector
RD
P140/SEGxx to
P143/SEGxx
WRPM
PM14
PM140 to PM143
LCD controller/driver
WRPF
PFALL
PF14L
P14:
Port register 14
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
PFALL: Port function register
RD:
Read signal
WR××: Write signal
Remark
78K0R/LF3: P140/SEG19 to P143/SEG16
78K0R/LG3: P140/SEG23 to P143/SEG20
78K0R/LH3: P140/SEG37 to P143/SEG34
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Figure 4-34. Block Diagram of P144 to P147
EVDD
WRPU
PU14
PU144 to PU147
P-ch
WRPORT
P14
Output latch
(P144 to P147)
Selector
Internal bus
Selector
RD
P144/SEGxx to
P147/SEGxx
WRPM
PM14
PM144 to PM147
LCD controller/driver
WRPF
PFALL
PF14H
P14:
Port register 14
PU14:
Pull-up resistor option register 14
PM14:
Port mode register 14
PFALL: Port function register
RD:
Read signal
WR××: Write signal
Remark
78K0R/LF3: P144/SEG15 to P147/SEG12
78K0R/LG3: P144/SEG19 to P147/SEG16
78K0R/LH3: P144/SEG33 to P147/SEG30
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4.2.16 Port 15
μ PD78F150xA
μ PD78F151xA
78K0R/LF3
78K0R/LG3
78K0R/LH3
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins)
(100 pins)
(128 pins)
(80 pins)
(100 pins)
(128 pins)
P150/ANI8/AMP2+
−
√
−
P150/ANI8
P151/ANI9
−
√
−
√
P152/ANI10
−
√
−
√
P157/ANI15/AVREFM
√
P157/ANI15
Port 15 is an I/O port with an output latch. Port 15 can be set to the input mode or output mode in 1-bit units using port
mode register 15 (PM15).
This port can also be used for A/D converter analog input, reference voltage input, and operational amplifier input.
To use P150/ANI8/AMP2+ to P152/ANI10, P157/ANI15/AVREFM as digital input pins, set them in the digital I/O mode by
using the A/D port configuration register (ADPC) and in the input mode by using PM15. Use these pins starting from the
lower bit.
To use P150/ANI8/AMP2+ to P152/ANI10, P157/ANI15/AVREFM as digital output pins, set them in the digital I/O mode
by using ADPC and in the output mode by using PM15.
All P150/ANI8/AMP2+ to P152/ANI10, P157/ANI15/AVREFM are set in the digital input mode when the reset signal is
generated.
Figures 4-35 to 4-37 show block diagrams of port 15.
Caution Make the AVDD0 pin the same potential as the EVDD or VDD pin when port 15 is used as a digital port.
Table 4-8. Setting Functions of ANI8/AMP2+/P150 Pins
ADPC register
PM2 and PM15
OAENn bit
ADS register
ANI8/AMP2+/P150 Pins
registers
Digital I/O
Input mode
selection
Output mode
Analog input
Input mode
0
−
Digital input
1
−
Setting prohibited
0
−
Digital output
1
−
Setting prohibited
0
selection
Selects ANI.
Analog input (to be A/D converted)
Does not select ANI.
Analog input (not to be A/D
converted)
1
Output mode
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Selects ANI.
Setting prohibited
Does not select ANI.
Operational amplifier input
−
Setting prohibited
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Table 4-9. Setting Functions of ANI9/P151 and ANI10/AM152 Pins
ADPC register
Digital I/O
selection
Analog input
PM15 register
ADS register
ANI9/P151 and ANI10/AM152 Pins
Input mode
−
Digital input
Output mode
−
Digital output
Input mode
selection
Selects ANI.
Analog input (to be A/D converted)
Does not select ANI.
Analog input (not to be A/D
converted)
−
Output mode
Setting prohibited
Table 4-10. Setting Functions of ANI15/AVREFM/P157 Pin
ADPC register
Digital I/O
PM15 register
Input mode
selection
Output mode
Analog input
Input mode
ADREF bit
ADS register
ANI15/AVREFM/P157 Pin
0
−
Digital input
1
−
Setting prohibited
0
−
Digital output
1
−
Setting prohibited
0
selection
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
−
1
Negative reference voltage input of
A/D converter
Output mode
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−
Setting prohibited
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Figure 4-35. Block Diagram of P150
Selector
RD
Internal bus
WRPORT
P15
Output latch
(P150)
P150/ANI8/AMP2+
WRPM
PM15
PM150
A/D converter
Operational amplifier (+) input
P15:
Port register 15
PM15:
Port mode register 15
RD:
Read signal
WR××: Write signal
Figure 4-36. Block Diagram of P151, P152
Internal bus
Selector
RD
WRPORT
P15
Output latch
(P151, P152)
P151/ANI9,
P152/ANI10
WRPM
PM15
PM151, PM152
A/D converter
P15:
Port register 15
PM15:
Port mode register 15
RD:
Read signal
WR××: Write signal
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Figure 4-37. Block Diagram of P157
Internal bus
Selector
RD
WRPORT
P15
Output latch
(P157)
P157/ANI15/AVREFM
WRPM
PM15
PM157
A/D converter
Operational amplifier (-) input
P15:
Port register 15
PM15:
Port mode register 15
RD:
Read signal
WR××: Write signal
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4.3 Registers Controlling Port Function
Port functions are controlled by the following eight types of registers.
• Port mode registers (PMxx)
• Port registers (Pxx)
• Pull-up resistor option registers (PUxx)
• Port input mode registers (PIMx)
• Port output mode registers (POMx)
• A/D port configuration register (ADPC)
• Port function register (PFALL)
• Input switch control register (ISC)
(1) Port mode registers (PMxx)
These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
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Figure 4-38 Format of Port Mode Register (78K0R/LF3)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM0
1
1
1
1
1
PM02
PM01
PM00
FFF20H
FFH
R/W
PM1
1
1
PM15
PM14
PM13
PM12
PM11
PM10
FFF21H
FFH
R/W
PM2
1
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22H
FFH
R/W
PM3
1
1
1
1
PM33
PM32
PM31
PM30
FFF23H
FFH
R/W
PM4
1
1
1
1
1
1
PM41
PM40
FFF24H
FFH
R/W
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FFF25H
FFH
R/W
PM9
1
1
1
1
1
PM92
PM91
PM90
FFF29H
FFH
R/W
PM10
1
1
1
1
1
1
1
PM100
FFF2AH
FFH
R/W
PM11
1
1
1
1
1
1
PM111
PM110
FFF2BH
FFH
R/W
PM12
1
1
1
1
1
1
1
PM120
FFF2CH
FFH
R/W
PM14
PM147
PM146
PM145
PM144
PM143
PM142
PM141
PM140
FFF2EH
FEH
R/W
PM15
PM157
1
1
1
1
1
1
1
FFF2FH
FFH
R/W
Pmn pin I/O mode selection
PMmn
(m = 0 to 5, 9 to 12, 14, 15; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Caution Be sure to set bits 3 to 7 of PM0, bits 6, 7 of PM1, bit 7 of PM2, bits 4 to 7 of PM3, bits 2 to 7 of
PM4, bits 3 to 7 of PM9, bits 1 to 7 of PM10, bits 2 to 7 of PM11, bits 1 to 7 of PM12, and bits 0 to
6 of PM15 to 1.
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Figure 4-39 Format of Port Mode Register (78K0R/LG3)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM0
1
1
1
1
1
PM02
PM01
PM00
FFF20H
FFH
R/W
PM1
1
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FFF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22H
FFH
R/W
PM3
1
1
1
PM34
PM33
PM32
PM31
PM30
FFF23H
FFH
R/W
PM4
1
1
1
1
1
1
PM41
PM40
FFF24H
FFH
R/W
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FFF25H
FFH
R/W
PM6
1
1
1
1
1
1
PM61
PM60
FFF26H
FFH
R/W
PM8
1
1
1
1
1
PM82
PM81
PM80
FFF28H
FFH
R/W
PM9
PM97
PM96
PM95
PM94
PM93
PM92
PM91
PM90
FFF29H
FFH
R/W
PM10
1
1
1
1
1
1
1
PM100
FFF2AH
FFH
R/W
PM11
1
1
1
1
1
1
PM111
PM110
FFF2BH
FFH
R/W
PM12
1
1
1
1
1
1
1
PM120
FFF2CH
FFH
R/W
PM14
PM147
PM146
PM145
PM144
PM143
PM142
PM141
PM140
FFF2EH
FEH
R/W
PM15
PM157
1
1
1
1
PM152
PM151
PM150
FFF2FH
FFH
R/W
Pmn pin I/O mode selection
PMmn
(m = 0 to 6, 8 to 12, 14, 15; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Caution Be sure to set bits 3 to 7 of PM0, bit 7 of PM1, bits 5 to 7 of PM3, bits 2 to 7 of PM4, bits 2 to 7 of
PM6, bits 3 to 7 of PM8, bits 1 to 7 of PM10, bits 2 to 7 of PM11, bits 1 to 7 of PM12, and bits 3 to
6 of PM15 to 1.
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Figure 4-40 Format of Port Mode Register (78K0R/LH3)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM0
1
1
1
1
1
PM02
PM01
PM00
FFF20H
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FFF21H
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22H
FFH
R/W
PM3
1
1
1
PM34
PM33
PM32
PM31
PM30
FFF23H
FFH
R/W
PM4
1
1
1
1
1
1
PM41
PM40
FFF24H
FFH
R/W
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FFF25H
FFH
R/W
PM6
1
1
1
1
1
1
PM61
PM60
FFF26H
FFH
R/W
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
FFF27H
FFH
R/W
PM8
PM87
PM86
PM85
PM84
PM83
PM82
PM81
PM80
FFF28H
FFH
R/W
PM9
PM97
PM96
PM95
PM94
PM93
PM92
PM91
PM90
FFF29H
FFH
R/W
PM10
1
1
1
1
1
PM102
PM101
PM100
FFF2AH
FFH
R/W
PM11
1
1
1
1
1
1
PM111
PM110
FFF2BH
FFH
R/W
PM12
1
1
1
1
1
1
1
PM120
FFF2CH
FFH
R/W
PM14
PM147
PM146
PM145
PM144
PM143
PM142
PM141
PM140
FFF2EH
FEH
R/W
PM15
PM157
1
1
1
1
PM152
PM151
PM150
FFF2FH
FFH
R/W
Pmn pin I/O mode selection
PMmn
(m = 0 to 12, 14, 15; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Caution Be sure to set bits 3 to 7 of PM0, bits 5 to 7 of PM3, bits 2 to 7 of PM4, bits 2 to 7 of PM6, bits 3
to 7 of PM10, bits 2 to 7 of PM11, bits 1 to 7 of PM12, and bits 3 to 6 of PM15 to 1.
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(2) Port registers (Pxx)
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
readNote.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Note It is always 0 and never a pin level that is read out if a port is read during the input mode when P2 and P15 are
set to function as an analog input for a A/D converter , and P11 are set to function as an analog input for a D/A
converter.
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Figure 4-41. Format of Port Register (78K0R/LF3)
Symbol
7
6
5
4
3
2
1
0
Address
P0
0
0
0
0
0
P02
P01
P00
FFF00H
00H (output latch) R/W
P1
0
0
P15
P14
P13
P12
P11
P10
FFF01H
00H (output latch) R/W
P2
0
P26
P25
P24
P23
P22
P21
P20
FFF02H
00H (output latch) R/W
P3
0
0
0
0
P33
P32
P31
P30
FFF03H
00H (output latch) R/W
P4
0
0
0
0
0
0
P41
P40
FFF04H
00H (output latch) R/W
P5
P57
P56
P55
P54
P53
P52
P51
P50
FFF05H
00H (output latch) R/W
P9
0
0
0
0
0
P92
P91
P90
FFF09H
00H (output latch) R/W
P10
0
0
0
0
0
0
0
P100
FFF0AH
00H (output latch) R/W
P11
0
0
0
0
0
0
P111
P110
FFF0BH
00H (output latch) R/W
P12
0
0
0
P124
P123
P122
P121
P120
FFF0CH
P13
0
0
0
0
0
0
0
P130
FFF0DH
00H (output latch) R/W
P14
P147
P146
P145
P144
P143
P142
P141
P140
FFF0EH
00H (output latch) R/W
P15
P157
0
0
0
0
0
0
0
FFF0FH
00H (output latch) R/W
Pmn
After reset
Undefined
R/W
R/W
Note
m = 0 to 5, 9 to 15 ; n = 0 to 7
Output data control (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Note P121 to P124 are read-only.
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Figure 4-42. Format of Port Register (78K0R/LG3)
Symbol
7
6
5
4
3
2
1
0
Address
P0
0
0
0
0
0
P02
P01
P00
FFF00H
00H (output latch) R/W
P1
0
P16
P15
P14
P13
P12
P11
P10
FFF01H
00H (output latch) R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FFF02H
00H (output latch) R/W
P3
0
0
0
P34
P33
P32
P31
P30
FFF03H
00H (output latch) R/W
P4
0
0
0
0
0
0
P41
P40
FFF04H
00H (output latch) R/W
P5
P57
P56
P55
P54
P53
P52
P51
P50
FFF05H
00H (output latch) R/W
P6
0
0
0
0
0
0
P61
P60
FFF06H
00H (output latch) R/W
P8
0
0
0
0
0
P82
P81
P80
FFF08H
00H (output latch) R/W
P9
P97
P96
P95
P94
P93
P92
P91
P90
FFF09H
00H (output latch) R/W
P10
0
0
0
0
0
0
0
P100
FFF0AH
00H (output latch) R/W
P11
0
0
0
0
0
0
P111
P110
FFF0BH
00H (output latch) R/W
P12
0
0
0
P124
P123
P122
P121
P120
FFF0CH
P13
0
0
0
0
0
0
0
P130
FFF0DH
00H (output latch) R/W
P14
P147
P146
P145
P144
P143
P142
P141
P140
FFF0EH
00H (output latch) R/W
P15
P157
0
0
0
0
P152
P151
P150
FFF0FH
00H (output latch) R/W
Pmn
After reset
Undefined
R/W
R/W
Note
m = 0 to 6, 8 to 15 ; n = 0 to 7
Output data control (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Note P121 to P124 are read-only.
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Figure 4-43. Format of Port Register (78K0R/LH3)
Symbol
7
6
5
4
3
2
1
0
Address
P0
0
0
0
0
0
P02
P01
P00
FFF00H
00H (output latch) R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FFF01H
00H (output latch) R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FFF02H
00H (output latch) R/W
P3
0
0
0
P34
P33
P32
P31
P30
FFF03H
00H (output latch) R/W
P4
0
0
0
0
0
0
P41
P40
FFF04H
00H (output latch) R/W
P5
P57
P56
P55
P54
P53
P52
P51
P50
FFF05H
00H (output latch) R/W
P6
0
0
0
0
0
0
P61
P60
FFF06H
00H (output latch) R/W
P7
P77
P76
P75
P74
P73
P72
P71
P70
FFF07H
00H (output latch) R/W
P8
P87
P86
P85
P84
P83
P82
P81
P80
FFF08H
00H (output latch) R/W
P9
P97
P96
P95
P94
P93
P92
P91
P90
FFF09H
00H (output latch) R/W
P10
0
0
0
0
0
P102
P101
P100
FFF0AH
00H (output latch) R/W
P11
0
0
0
0
0
0
P111
P110
FFF0BH
00H (output latch) R/W
P12
0
0
0
P124
P123
P122
P121
P120
FFF0CH
P13
0
0
0
0
0
0
0
P130
FFF0DH
00H (output latch) R/W
P14
P147
P146
P145
P144
P143
P142
P141
P140
FFF0EH
00H (output latch) R/W
P15
P157
0
0
0
0
P152
P151
P150
FFF0FH
00H (output latch) R/W
Pmn
After reset
Undefined
R/W
R/W
Note
m = 0 to 15 ; n = 0 to 7
Output data control (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Note P121 to P124 are read-only.
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(3) Pull-up resistor option registers (PUxx)
These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be
used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has
been specified in these registers. On-chip pull-up resistors cannot be connected to bits set to output mode and bits
used as alternate-function output pins, regardless of the settings of these registers.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-44. Format of Pull-up Resistor Option Register (78K0R/LF3)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PU0
0
0
0
0
0
PU02
PU01
PU00
F0030H
00H
R/W
PU1
0
0
PU15
PU14
PU13
PU12
PU11
PU10
F0031H
00H
R/W
PU3
0
0
0
0
PU33
PU32
PU31
PU30
F0033H
00H
R/W
PU4
0
0
0
0
0
0
PU41
PU40
F0034H
00H
R/W
PU5
PU57
PU56
PU55
PU54
PU53
PU52
PU51
PU50
F0035H
00H
R/W
PU9
0
0
0
0
0
PU92
PU91
PU90
F0039H
00H
R/W
PU10
0
0
0
0
0
0
0
PU100
F003AH
00H
R/W
PU12
0
0
0
0
0
0
0
PU120
F003CH
00H
R/W
PU14
PU147
PU146
PU145
PU144
PU143
PU142
PU141
PU140
F003EH
00H
R/W
Pmn pin on-chip pull-up resistor selection
PUmn
(m = 0, 1, 3 to 5, 9, 10, 12, 14 ; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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Figure 4-45. Format of Pull-up Resistor Option Register (78K0R/LG3)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PU0
0
0
0
0
0
PU02
PU01
PU00
F0030H
00H
R/W
PU1
0
PU16
PU15
PU14
PU13
PU12
PU11
PU10
F0031H
00H
R/W
PU3
0
0
0
PU34
PU33
PU32
PU31
PU30
F0033H
00H
R/W
PU4
0
0
0
0
0
0
PU41
PU40
F0034H
00H
R/W
PU5
PU57
PU56
PU55
PU54
PU53
PU52
PU51
PU50
F0035H
00H
R/W
PU8
0
0
0
0
0
PU82
PU81
PU80
F0038H
00H
R/W
PU9
PU97
PU96
PU95
PU94
PU93
PU92
PU91
PU90
F0039H
00H
R/W
PU10
0
0
0
0
0
0
0
PU100
F003AH
00H
R/W
PU12
0
0
0
0
0
0
0
PU120
F003CH
00H
R/W
PU14
PU147
PU146
PU145
PU144
PU143
PU142
PU141
PU140
F003EH
00H
R/W
Pmn pin on-chip pull-up resistor selection
PUmn
(m = 0, 1, 3 to 5, 8 to 10, 12, 14 ; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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Figure 4-46. Format of Pull-up Resistor Option Register (78K0R/LH3)
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PU0
0
0
0
0
0
PU02
PU01
PU00
F0030H
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
F0031H
00H
R/W
PU3
0
0
0
PU34
PU33
PU32
PU31
PU30
F0033H
00H
R/W
PU4
0
0
0
0
0
0
PU41
PU40
F0034H
00H
R/W
PU5
PU57
PU56
PU55
PU54
PU53
PU52
PU51
PU50
F0035H
00H
R/W
PU7
PU77
PU76
PU75
PU74
PU73
PU72
PU71
PU70
F0037H
00H
R/W
PU8
PU87
PU86
PU85
PU84
PU83
PU82
PU81
PU80
F0038H
00H
R/W
PU9
PU97
PU96
PU95
PU94
PU93
PU92
PU91
PU90
F0039H
00H
R/W
PU10
0
0
0
0
0
PU102
PU101
PU100
F003AH
00H
R/W
PU12
0
0
0
0
0
0
0
PU120
F003CH
00H
R/W
PU14
PU147
PU146
PU145
PU144
PU143
PU142
PU141
PU140
F003EH
00H
R/W
Pmn pin on-chip pull-up resistor selection
PUmn
(m = 0, 1, 3 to 5, 7 to 10, 12, 14 ; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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(4) Port input mode registers (PIMx)
PIM1 and PIM7 registers set the input buffer of P10, P11, P14, P15, P75, or P76 in 1-bit units.
TTL input buffer can be selected during serial communication with an external device of the different potential.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-47. Format of Port Input Mode Register
• 78K0R/LF3
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PIM1
0
0
PIM15
PIM14
0
0
PIM11
PIM10
F0041H
00H
R/W
• 78K0R/LG3
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PIM1
0
0
PIM15
PIM14
0
0
PIM11
PIM10
F0041H
00H
R/W
• 78K0R/LH3
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PIM1
0
0
PIM15
PIM14
0
0
PIM11
PIM10
F0041H
00H
R/W
PIM7
0
PIM76
PIM75
0
0
0
0
0
F0047H
00H
R/W
Pmn pin input buffer selection
PIMmn
(m = 1 and 7; n = 0, 1, 4 to 6)
0
Normal input buffer
1
TTL input buffer
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(5) Port output mode registers (POMx)
These registers set the output mode of P10 to P15, P75, P77, P80, or P82 in 1-bit units.
N-ch open drain output (VDD tolerance) mode can be selected during serial communication with an external device of
2
the different potential, and for the SDA10, SDA20 pin during simplified I C communication with an external device of
the same potential.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-48. Format of Port Output Mode Register
• 78K0R/LF3
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
POM1
0
0
POM15
POM14
POM13
POM12
POM11
POM10
F0051H
00H
R/W
• 78K0R/LG3
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
POM1
0
0
POM15
POM14
POM13
POM12
POM11
POM10
F0051H
00H
R/W
POM8
0
0
0
0
0
POM82
0
POM80
F0058H
00H
R/W
• 78K0R/LH3
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
POM1
0
0
POM15
POM14
POM13
POM12
POM11
POM10
F0051H
00H
R/W
POM7
POM77
0
POM75
0
0
0
0
0
F0057H
00H
R/W
POM8
0
0
0
0
0
POM82
0
POM80
F0058H
00H
R/W
Pmn pin output mode selection
POMmn
(m = 1, 7, and 8; n = 0 to 5 and 7)
0
Normal output mode
1
N-ch open-drain output (VDD tolerance) mode
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(6) A/D port configuration register (ADPC)
This
register
switches
the
ANI0/AMP0-/P20
to
ANI7/AMP2O/P27,
ANI8/AMP2+/P150
to
ANI10/P152,
ANI15/AVREFM/P157 pins to analog input or digital I/O of port.
ADPC can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 10H.
Figure 4-49. Format of A/D Port Configuration Register (ADPC)
Address: F0017H
After reset: 10H
R/W
Symbol
7
6
5
4
3
2
1
0
ADPC
0
0
0
ADPC4
ADPC3
ADPC2
ADPC1
ADPC0
ADP ADP ADP ADP ADP
C4
C3
C2
C1
Analog input (A)/digital I/O (D) switching
C0
Port 15
ANI15
ANI10
ANI9
/AVREFM
/P152
/P151
/P157
Port 2
ANI8
ANI7
ANI6
ANI5
ANI4
/AMP2+ /AMP2O /AMP2- /AMP1+ /AMP1O
ANI3
ANI2
ANI1
/AMP1- /AMP0+ /AMP0O
ANI0
/AMP0-
/P150
/P27
/P26
/P25
/P24
/P23
/P22
/P21
/P20
0
0
0
0
0
A
A
A
A
A
A
A
A
A
A
A
A
0
0
0
0
1
A
A
A
A
A
A
A
A
A
A
A
D
0
0
0
1
0
A
A
A
A
A
A
A
A
A
A
D
D
0
0
0
1
1
A
A
A
A
A
A
A
A
A
D
D
D
0
0
1
0
0
A
A
A
A
A
A
A
A
D
D
D
D
0
0
1
0
1
A
A
A
A
A
A
A
D
D
D
D
D
0
0
1
1
0
A
A
A
A
A
A
D
D
D
D
D
D
Note→
0
0
1
1
1
A
A
A
A
A
D
D
D
D
D
D
D
Note→
0
1
0
0
0
A
A
A
A
D
D
D
D
D
D
D
D
Note→
0
1
0
0
1
A
A
A
D
D
D
D
D
D
D
D
D
Note→
0
1
0
1
0
A
A
D
D
D
D
D
D
D
D
D
D
0
1
1
1
1
A
D
D
D
D
D
D
D
D
D
D
D
1
0
0
0
0
D
D
D
D
D
D
D
D
D
D
D
D
Other than the above
Note
Setting prohibited
This setting is prohibited for 78K0R/LF3.
Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode registers
2 and 15 (PM2, PM15).
2. Do not set the pin that is set by ADPC as digital I/O by analog input channel specification
register (ADS).
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(7) Port function register (PFALL)
This register sets whether to use pins P50 to P57, P90 to P97, P100 to P102, and P140 to P147 as port pins (other
than segment output pins) or segment output pins.
PFALL is set using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PFALL to 00H.
Remark The port pins to be used alternatively with the segment output pins vary, depending on the product.
• 78K0R/LF3:
P50 to P57, P90 to P92, P100, P140 to P147
• 78K0R/LG3:
P50 to P57, P90 to P97, P100, P140 to P147
• 78K0R/LH3:
P50 to P57, P90 to P97, P100 to P102, P140 to P147
Figure 4-50. Format of Port Function Register (PFALL) (1/2)
Address: F0080H
Symbol
PFALL
7
0
After reset: 00H
R/W
6
PF14H
5
4
PF14L
PF14H
PF10
3
Note
PF9H
2
1
0
PF9L
PF5H
PF5L
Port/segment outputs specification of the P144 to P147 pins
0
Used the P144 to P147 pins as port (other than segment output)
1
Used the P144 to P147 pins as segment output
PF14L
Port/segment outputs specification of the P140 to P143 pins
0
Used the P140 to P143 pins as port (other than segment output)
1
Used the P140 to P143 pins as segment output
PF10
Port/segment outputs specification of the P100 to P102 pins
0
Used the P100 to P102 pins as port (other than segment output)
1
Used the P100 to P102 pins as segment output
PF9H
Port/segment outputs specification of the P94 to P97 pins
0
Used the P94 to P97 pins as port (other than segment output)
1
Used the P94 to P97 pins as segment output
PF9L
Port/segment outputs specification of P90 to P93 pins
0
Used the P90 to P93 pins as port (other than segment output)
1
Used the P90 to P93 pins as segment output
Note 78K0R/LG3, 78K0R/LH3 only
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Figure 4-50. Format of Port Function Register (PFALL) (2/2)
PF5H
Port/segment outputs specification of the P54 to P57 pins
0
Used the P54 to P57 pins as port (other than segment output)
1
Used the P54 to P57 pins as segment output
PF5L
Caution
Port/segment outputs specification of P50 to P53 pins
0
Used the P50 to P53 pins as port (other than segment output)
1
Used the P50 to P53 pins as segment output
For 78K0R/LF3, bits 3 and 7 must be set to 0. For 78K0R/LG3 and 78K0R/LH3, bit 7 must be set to 0.
(8) Input switch control register (ISC)
Bits 0 and 1 of ISC are used for linking with an external interrupt or a timer array unit when performing a LIN-bus
communication operation with UART3.
When bit 0 is set to 1, the input signal of the serial data input (RXD3) pin is selected as an external interrupt (INTP0)
that can be used to detect a wakeup signal.
When bit 1 is set to 1, the input signal of the serial data input (RXD3) pin is selected as a timer input, so that the pulse
widths of a sync break field and a sync field can be measured by the timer.
Bits 2 to 4 of ISC are used to prevent through current from entering when using the TI04/SEGxx/P53,
TI02/SEGxx/P52, and RxD3/SEGxx/P50 pins as segment outputs or port outputs.
The segment output pins to be used alternatively with the TI04, TI02, and RxD3 pins are internally connected with a
Schmitt trigger buffer. When using these pins as segment outputs or port outputs, bits 2 to 4 of ISC must be set to 0
(prohibiting input to Schmitt trigger buffers) in order to prevent through current from entering.
ISC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Remark
The segment output pins to be used alternatively with the TI02, TI04, and RxD3 pins vary, depending on
the product.
• 78K0R/LF3:
TI04/SEG27/P53, TI02/SEG28/P52, RxD3/SEG30/P50
• 78K0R/LG3:
TI04/SEG36/P53, TI02/SEG37/P52, RxD3/SEG39/P50
• 78K0R/LH3:
TI04/SEG50/P53, TI02/SEG51/P52, RxD3/SEG53/P50
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Figure 4-51. Format of Input Switch Control Register (ISC)
Address: FFF3CH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ISC
0
0
0
ISC4
ISC3
ISC2
ISC1
ISC0
TI04/SEGxx/P53 schmitt trigger buffer control
ISC4
0
Disables input
1
Enables input
TI02/SEGxx/P52 schmitt trigger buffer control
ISC3
0
Disables input
1
Enables input
RxD3/SEGxx/P50 schmitt trigger buffer control
ISC2
0
Disables input
1
Enables input
Switching channel 7 input of timer array unit
ISC1
0
Uses the input signal of the TI07 pin as a timer input (normal operation).
1
Input signal of RXD3 pin is used as timer input (wakeup signal detection).
Switching external interrupt (INTP0) input
ISC0
0
Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
1
Uses the input signal of the RXD3 pin as an external interrupt
(to measure the pulse widths of the sync break field and sync field).
Caution Be sure to clear bits 5 to 7 to “0”.
To use the TI04/SEGxx/P53, TI02/SEGxx/P52, and RxD3/SEGxx/P50 pins, set the PF5L and ISCn (n = 2 to 4)
bits as follows, according to the function to be used.
PF5L
ISCn
0
0
Port output (default)
0
1
Port input, timer input, or serial data input
1
0
Segment output
1
1
Setting prohibited
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4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
4.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not
change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
4.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output latch
contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
The pin level is read and an operation is performed on its contents. The result of the operation is written to the output
latch, but since the output buffer is off, the pin status does not change.
The data of the output latch is cleared when a reset signal is generated.
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4.4.4 Connecting to external device with different power potential (2.5 V, 3 V)
When parts of ports 1, 7, and 8 operate with VDD = 4.0 V to 5.5 V, I/O connections with an external device that operates
on a 2.5V or 3 V power supply voltage are possible.
Regarding inputs, CMOS/TTL switching is possible on a bit-by-bit basis by port input mode registers (PIM1 and PIM7).
Moreover, regarding outputs, different power potentials can be supported by switching the output buffer to the N-ch
open drain (VDD withstand voltage) by the port output mode registers (POM1, POM7 and POM8).
(1) Setting procedure when using I/O pins of UART1, UART2 CSI00, CSI01, CSI10, and CSI20 functions
(a) Use as 2.5V or 3 V input port
After reset release, the port mode is the input mode (Hi-Z).
If pull-up is needed, externally pull up the pin to be used (on-chip pull-up resistor cannot be used).
In case of UART1:
P14
In case of UART2:
P11
In case of CSI01:
P75, P76
In case of CSI10:
P15, P14
In case of CSI20:
P10, P11
Set the corresponding bit of the PIMn register to 1 to switch to the TTL input buffer.
VIH/VIL operates on a 2.5V or 3 V operating voltage.
Remark
n = 1, 7
(b) Use as 2.5V or 3 V output port
After reset release, the port mode changes to the input mode (Hi-Z).
Pull up externally the pin to be used (on-chip pull-up resistor cannot be used).
In case of UART1:
P13
In case of UART2:
P12
In case of CSI00:
P80, P82
In case of CSI01:
P75, P77
In case of CSI10:
P15, P13
In case of CSI20:
P10, P12
Set the output latch of the corresponding port to 1.
Set the corresponding bit of the POMn register to 1 to set the N-ch open drain output (VDD withstand
voltage) mode.
Set the output mode by manipulating the PMn register.
At this time, the output data is high level, so the pin is in the Hi-Z state.
Operation is done only in the low level according to the operating status of the serial array unit.
Remark
n = 1, 7, 8
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(2) Setting procedure when using I/O pins of simplified IIC10, IIC20 functions
After reset release, the port mode is the input mode (Hi-Z).
Externally pull up the pin to be used (on-chip pull-up resistor cannot be used).
In case of simplified IIC10: P14, P15
In case of simplified IIC20: P11, P10
Set the output latch of the corresponding port to 1.
Set the corresponding bit of the POM1 register to 1 to set the N-ch open drain output (VDD withstand
voltage) mode.
Set the corresponding bit of the PM1 register to the output mode (data I/O is possible in the output mode).
At this time, the output data is high level, so the pin is in the Hi-Z state.
2
Enable the operation of the serial array unit and set the mode to the simplified I C mode.
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4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function
To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 4-11.
Table 4-11. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/5)
LH3
LG3
LF3
Pin Name
Alternate Function
Function Name
I/O
PFALL
ISC
(PFxxx)
(ISCx)
PM××
P××
√
√
√ P00
CAPH
Output
−
−
×
×
√
√
√ P01
CAPL
Output
−
−
×
×
√
√
√ P02
VLC3
I/O
−
−
×
×
√
√
√ P10
SCK20
Input
−
−
1
×
Output
−
−
0
1
√
√
√
√
√
−
√
√
√
√
√
√
√ P11
√ P12
√ P13
√ P14
√ P15
√ P16
Remark
SCL20
I/O
−
−
0
1
SI20
Input
−
−
1
×
RxD2
Input
−
−
1
×
SDA20
I/O
−
−
0
1
INTP6
Input
−
−
1
×
SO20
Output
−
−
0
1
TxD2
Output
−
−
0
1
TO02
Output
−
−
0
0
SO10
Output
−
−
0
1
TxD1
Output
−
−
0
1
TO04
Output
−
−
0
0
SI10
Input
−
−
1
×
RxD1
Input
−
−
1
×
SDA10
I/O
−
−
0
1
INTP4
Input
−
−
1
×
SCK10
Input
−
−
1
×
Output
−
−
0
1
SCL10
I/O
−
−
0
1
INTP7
Input
−
−
1
×
TI05
Input
−
−
1
×
TO05
Output
−
−
0
0
INTP10
Input
−
−
1
×
×:
don’t care
−:
Not applicable
PFALL: Port function register
ISC:
Input switch control register
PM××:
Port mode register
P××:
Port output latch
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Table 4-11. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/5)
LG3
√
LH3
LF3
√
Pin Name
PFALL
ISC
(PFxxx)
(ISCx)
Input
−
AMP1-, Input
Alternate Function
Function Name
√ P20 to 25
Note
ANI0-ANI5
AMP0-,
AMP0+,
I/O
PM××
P××
−
1
×
−
−
1
×
AMP1+
√
√
√ P26
√
√ P27
Note
−
−
√
√
√
√
−
√
√
√
√
√
Note
√ P30
√ P31
√ P32
√ P33
√ P34
Note
The
function
AMP0O, AMP1O
Output
−
−
1
×
ANI6
Input
−
−
1
×
AMP2-
Input
−
−
1
×
ANI7
Input
−
−
1
×
AMP2O
Output
−
−
1
×
TI03
Input
−
−
1
×
TO00
Output
−
−
0
0
RTC1HZ
Output
−
−
0
0
INTP1
Input
−
−
1
×
TI00
Input
−
−
1
×
TO03
Output
−
−
0
0
RTCDIV
Output
−
−
0
0
RTCCL
Output
−
−
0
0
PCLBUZ1
Output
−
−
0
0
INTP2
Input
−
−
1
×
TI01
Input
−
−
1
×
TO01
Output
−
−
0
0
INTP5
Input
−
−
1
×
PCLBUZ0
Output
−
−
0
0
TI07
Input
−
1
×
TO07
Output
−
−
0
0
INTP3
Input
−
−
1
×
TI06
Input
−
−
1
×
TO06
Output
−
−
0
0
INTP8
Input
−
−
1
×
of
the
P20/ANI0/AMP0-,
ISC1=0
P21/ANI1/AMP0O,
P22/ANI2/AMP0+,
P23/ANI3/AMP1-,
P24/ANI4/AMP1O, P25/ANI5/AMP1+, P26/ANI6 pins can be selected by using the A/D port configuration
register (ADPC), port mode register 2 (PM2), analog input channel specification register (ADS), and
operational amplifier control register (OAC). Refer to 4.2.3 Port 2.
Remark
×:
don’t care
−:
Not applicable
PFALL: Port function register
ISC:
Input switch control register
PM××:
Port mode register
P××:
Port output latch
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Table 4-11. Settings of Port Mode Register and Output Latch When Using Alternate Function (3/5)
LH3
LG3
LF3
Pin Name
Alternate Function
Function Name
I/O
PFALL
ISC
PM××
P××
(PFxxx)
(ISCx)
×
×
×
×
1
×
0
1
ISC3=1
1
×
√
√
√ P40
√
√
√ P41
√
√
√ P50
RxD3
Input
√
√
√ P51
TxD3
Output
√
√
√ P52
TI02
Input
√
√
√ P53
TI04
Input
ISC4=1
1
×
−
√
√ P60
SCL0
I/O
−
−
0
0
−
√
√ P61
SDA0
I/O
−
−
0
0
−
−
√ P70 to P74
KR0 to KR4
Input
−
−
1
×
−
−
√ P75
KR5
Input
−
−
1
×
SCK01
Input
−
−
1
×
Output
−
−
0
1
−
−
1
×
Note 1
Note 1
Note 1
Note 1
TOOL0
I/O
−
−
TOOL1
Output
−
−
PF5L=0
Note 2
ISC2=1
−
−
−
√ P76
KR6
Input
SI01
Input
−
−
1
×
−
−
√ P77
KR7
Input
−
−
1
×
SO01
Output
−
−
0
1
SCK00
Input
−
−
1
×
Output
−
−
0
1
INTP11
Input
−
−
1
×
RxD0
Input
−
−
1
×
SI00
Input
−
−
1
×
−
−
−
−
−
√
√
√
−
−
√ P80
√ P81
√ P82
√ P84
√ P85
INTP9
Input
−
−
1
×
TxD0
Output
−
−
0
1
SO00
Output
−
−
0
1
TI10
Input
−
−
1
×
TO10
Output
−
−
0
0
TI11
Input
−
−
1
×
TO11
Output
−
−
0
0
Notes 1. Refer to Table 4-11 Settings of Port Mode Register and Output Latch When Using Alternate Function
(5/5) about the segment output (SEGxx).
2. The RxD3 input can be set as the input source of an external interrupt input (INTP0) by setting ISC0 = 1.
The RxD3 input can be set as the input source of a timer input (TI07) by setting ISC1 = 1.
Remark
×:
don’t care
−:
Not applicable
PFALL: Port function register
ISC:
Input switch control register
PM××:
Port mode register
P××:
Port output latch
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Table 4-11. Settings of Port Mode Register and Output Latch When Using Alternate Function (4/5)
LH3
LG3
LF3
Pin Name
Alternate Function
Function Name
−
−
−
−
√ P86
√ P87
√
√
√ P110, P111
√
√
√ P120
√ P121
√
√
√ P122
−
1
×
TO12
Output
−
−
0
0
TI13
Input
−
−
1
×
TO13
Output
−
−
0
0
−
0
×
1
×
Output
−
Note 1
Input
−
Note 1
Input
ANO0, ANO1
Note 1
X1
Note 1
EXCLK
√
√ P123
√
√
√ P124
−
√
√ P150
−
√
√ P151, P152
√
√
√ P157
Note 2
Note 2
Note 2
(ISCx)
P××
−
X2
√
(PFxxx)
PM××
Input
EXLVI
√
ISC
TI12
INTP0
√
I/O
PFALL
Note 1
ISC0 = 0
−
−
1
×
−
−
−
×
×
−
−
−
×
×
−
−
×
×
Input
XT1
Note 1
−
−
−
×
×
XT2
Note 1
−
−
−
×
×
ANI8
Input
−
−
1
×
AMP2+
Input
−
−
1
×
ANI9, ANI10
Input
−
−
1
×
ANI15
Input
−
−
1
×
AVREFM
Input
−
−
1
×
Notes 1. To use the P121 to P124 pins for main system clock resonator connection (X1, X2), subsystem clock
resonator connection (XT1, XT2), or main system clock external clock input (EXCLK), the X1 oscillation
mode, XT1 oscillation mode, or external clock input mode must be set, respectively, by using the clock
operation mode control register (CMC). CMC can be written only once after reset release (for details, refer
to 5.3 (1) Clock operation mode control register (CMC)). The reset value of CMC is 00H (both P121 to
P124 are input port pins).
2. The P150/ANI8/AMP2+, P151/ANI9, P152/ANI10, P157/ANI15/AVREFM pins are as shown below depending
on the settings of the A/D port configuration register (ADPC), port mode register 2 (PM2), analog input
channel specification register (ADS), operational amplifier control register (OAC), and analog reference
voltage control register (ADVRC). Refer to 4.2.16 Port 15.
Remark
×:
don’t care
−:
Not applicable
PFALL: Port function register
ISC:
Input switch control register
PM××:
Port mode register
P××:
Port output latch
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Table 4-11. Settings of Port Mode Register and Output Latch When Using Alternate Function (5/5)
LG3
−
LH3
LF3
√
Pin Name
Alternate Function
Function Name
−
−
√
−
I/O
PFALL
ISC
(PFxxx)
(ISCx)
PM××
P××
×
×
×
×
− P50
Note
SEG30
Output
PF5L=1
P51
Note
SEG29
Output
PF5L=1
P52
Note
SEG28
Output
PF5L=1
ISC3 = 0
×
×
P53
Note
SEG27
Output
PF5L=1
ISC4 = 0
×
×
P54 to 57
SEG26 to SEG23
Output
PF5H=1
−
×
×
P90 to 92
SEG22 to SEG20
Output
PF9L=1
−
×
×
P140 to 143
SEG19 to SEG16
Output
PF14L=1
−
×
×
P144 to 147
SEG15 to SEG12
Output
PF14H=1
−
×
×
P100
ISC2 = 0
−
×
×
×
×
×
×
ISC3 = 0
×
×
ISC4 = 0
×
×
−
×
×
PF9L=1
−
×
×
Output
PF9H=1
−
×
×
SEG23 to SEG20
Output
PF14L=1
−
×
×
P144 to 147
SEG19 to SEG16
Output
PF14H=1
−
×
×
P100
SEG15
Output
PF10=1
−
×
×
√ P50
Note
SEG53
Output
PF5L=1
×
×
P51
Note
SEG52
Output
PF5L=1
×
×
P52
Note
SEG51
Output
PF5L=1
ISC3 = 0
×
×
P53
Note
SEG50
Output
PF5L=1
ISC4 = 0
×
×
P54 to 57
SEG49 to SEG46
Output
PF5H=1
−
×
×
P90 to 93
SEG45 to SEG42
Output
PF9L=1
−
×
×
P94 to 97
SEG41 to SEG38
Output
PF9H=1
−
×
×
P140 to 143
SEG37 to SEG34
Output
PF14L=1
−
×
×
P144 to 147
SEG33 to SEG30
Output
PF14H=1
−
×
×
P100 to 102
SEG29 to SEG27
Output
PF10=1
−
×
×
SEG11
Output
PF10=1
− P50
Note
SEG39
Output
PF5L=1
P51
Note
SEG38
Output
PF5L=1
P52
Note
SEG37
Output
PF5L=1
P53
Note
SEG36
Output
PF5L=1
P54 to 57
SEG35 to SEG32
Output
PF5H=1
P90 to 93
SEG31 to SEG28
Output
P94 to 97
SEG27 to SEG24
P140 to 143
−
ISC2 = 0
−
ISC2 = 0
−
Note For alternate function other than the segment output (SEGxx), refer to Table 4-11 Settings of Port Mode
Register and Output Latch When Using Alternate Function (3/5).
Remark
×:
don’t care
−:
Not applicable
PFALL: Port function register
ISC:
Input switch control register
PM××:
Port mode register
P××:
Port output latch
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4.6 Cautions on 1-bit Manipulation Instruction for Port Register n (Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output
latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port
latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level via a
1-bit manipulation instruction, the output latch value of port 1 is FFH.
Explanation:
The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output
latch and pin status, respectively.
A 1-bit manipulation instruction is executed in the following order in the 78K0R/Lx3 Microcontrollers.
The Pn register is read in 8-bit units.
The targeted one bit is manipulated.
The Pn register is written in 8-bit units.
In step , the output latch value (0) of P10, which is an output port, is read, while the pin statuses of
P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at this time,
the read value is FEH.
The value is changed to FFH by the manipulation in .
FFH is written to the output latch by the manipulation in .
Figure 4-52. Bit Manipulation Instruction (P10)
1-bit manipulation
instruction
(set1 P1.0)
is executed for P10
bit.
P10
Low-level output
P11 to P17
P10
High-level output
P11 to P17
Pin status: High-level
Port 1 output latch
0
0
0
Pin status: High-level
Port 1 output latch
0
0
0
0
0
1
1
1
1
1
1
1
1
1-bit manipulation instruction for P10 bit
Port register 1 (P1) is read in 8-bit units.
• In the case of P10, an output port, the value of the port output latch (0) is read.
• In the case of P11 to P17, input ports, the pin status (1) is read.
Set the P10 bit to 1.
Write the results of to the output latch of port register 1 (P1)
in 8-bit units.
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CHAPTER 5 CLOCK GENERATOR
5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three kinds of system clocks and clock oscillators are selectable.
(1) Main system clock
X1 oscillator
This circuit oscillates a clock of fX = 2 to 20 MHz by connecting a resonator to X1 and X2.
Oscillation can be stopped by executing the STOP instruction or setting of MSTOP (bit 7 of the clock
operation status control register (CSC)).
Internal high-speed oscillator
Note
This circuit oscillates clocks of fIH = 1 MHz (TYP.) or fIH = 8 MHz (TYP.). After a reset release, the CPU
always starts operating with this internal high-speed oscillation clock.
Oscillation can be stopped by
executing the STOP instruction or setting HIOSTOP (bit 0 of CSC).
Note
20 MHz internal high-speed oscillation clock oscillator
This circuit oscillates a clock of fIH20 = 20 MHz (TYP.). Oscillation can be started by setting bit 0 (DSCON) of
the 20 MHz internal high-speed oscillation control register (DSCCTL) to 1 with VDD ≥ 2.7 V. Oscillation can
be stopped by setting DSCON to 0.
Note To use the internal high-speed oscillation clock, use the option byte to set the frequency (1 MHz, 8
MHz, or 20 MHz) in advance (for details, see CHAPTER 26 OPTION BYTE). Also, the internal highspeed oscillator automatically starts oscillating after reset release. To use the 20 MHz internal highspeed oscillator to operate the microcontroller, oscillation is started by setting bit 0 (DSCON) of the 20
MHz internal high-speed oscillation control register (DSCCTL) to 1.
An external main system clock (fEX = 2 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An external
main system clock input can be disabled by executing the STOP instruction or setting of MSTOP.
As the main system clock, a high-speed system clock (X1 clock or external main system clock) or internal highspeed oscillation clock can be selected by setting of MCM0 (bit 4 of the system clock control register (CKC)).
Remark
fX :
X1 clock oscillation frequency
fIH:
Internal high-speed oscillation clock frequency
fIH20: 20 MHz internal high-speed oscillation clock frequency
fEX:
External main system clock frequency
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(2) Subsystem clock
• XT1 clock oscillator
This circuit oscillates a clock of fSUB = 32.768 kHz by connecting a 32.768 kHz resonator to XT1 and XT2.
Oscillation can be stopped by setting XTSTOP (bit 6 of CSC).
(3) Internal low-speed oscillation clock (clock for watchdog timer)
• Internal low-speed oscillator
This circuit oscillates a clock of fIL = 30 kHz (TYP.).
The internal low-speed oscillation clock cannot be used as the CPU clock. The only hardware that operates with
the internal low-speed oscillation clock is the watchdog timer.
Oscillation is stopped when the watchdog timer stops.
Remarks 1. fSUB: Subsystem clock frequency
fIL:
Internal low-speed oscillation clock frequency
2. The watchdog timer stops in the following cases.
• When bit 4 (WDTON) of an option byte (000C0H) = 0
• If the HALT or STOP instruction is executed when bit 4 (WDTON) of an option byte (000C0H) = 1 and
bit 0 (WDSTBYON) = 0
5.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item
Control registers
Configuration
Clock operation mode control register (CMC)
Clock operation status control register (CSC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
System clock control register (CKC)
20 MHz internal high-speed oscillation control register (DSCCTL)
Peripheral enable registers 0 (PER0)
Operation speed mode control register (OSMC)
Oscillators
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X1 oscillator
XT1 oscillator
Internal high-speed oscillator
Internal low-speed oscillator
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Internal bus
Clock operation mode
control register
(CMC)
Clock operation status
control register
(CSC)
AMPH EXCLK OSCSEL
Oscillation stabilization
time select register (OSTS)
System clock control
register (CKC)
CLS
OSTS2 OSTS1 OSTS0
MSTOP
CSS MCS MCM0 SDIV
MD
IV2
MD
IV1
MD
IV0
Standby control circuit
(see CHAPTER 24)
3
STOP mode
3
STOP mode
signal
fX
External input
clock
fEX
Oscillation stabilization time
counterstatus register
(OSTC)
fMX
Clock output/
buzzer output
Internal high-speed
oscillator
fMAIN/25
fIH1
fMAIN
fIH
Internal high-speed
oscillation (8 MHz (typ.))
fIH8
20 MHz internal
high-speed oscillator
Internal high-speed
oscillation (20 MHz (typ.))
Main system
clock source
selection
fIH20
fIH20
Option byte(000C0H)
WDTON
WDSTBYON
XT1/P123
Subsystem clock
oscillator
XT2//P124
Crystal
oscillation
fMAIN/23
fMAIN/22
fMAINC
fSUBC
Selection of
CPU clock and fCLK
peripheral
hardware clock
source
CPU
fMAIN/2
fMAIN
fSUB/2
fSUB
Internal low-speed
oscillator
Internal low-speed
oscillation (30 kHz (typ.))
fMAIN/24
Controller
Internal high-speed
oscillation (1 MHz (typ.))
Prescaler
Option byte(000C1H)
FRQSEL2,
FRQSEL1
High-speed system
clock oscillator
Crystal/ceramic
oscillation
Selector
X2/EXCLK
/P122
HALT mode
Normal operation
mode
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11 13 15 17 18
Selector
X1/P121
X1 oscillation
stabilization time counter
Prescaler
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Figure 5-1. Block Diagram of Clock Generator
fSUBC/2
Timer array unit 0
HALT/STOP mode signal
fIL
Watchdog timer
fSUB
SDIV
Real-time counter,
clock output/buzzer output
fXT
Clock operation mode
control register
(CMC)
XTSTOP HIOSTOP
Clock operation status
control register
(CSC)
DSCS SELDSC DSCON
20 MHz internal high-speed
oscillation control register
(DSCCTL)
Internal bus
RTC
EN
DAC
EN
ADC
EN
IICA
EN
SAU1
EN
SAU0
EN
TAU1
EN
TAU0
EN
Peripheral enable register 0
(PER0)
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CHAPTER 5 CLOCK GENERATOR
CLS
AMPHS1 AMPHS0 OSCSELS
Timer array unit 0
Timer array unit 1
Serial array unit 0
Serial array unit 1
Serial interface IICA
A/D converter, operational Amplifiers, voltage reference
D/A converter
Real-time counter
78K0R/Lx3
Remark
CHAPTER 5 CLOCK GENERATOR
fX:
X1 clock oscillation frequency
fIH:
Internal high-speed oscillation clock frequency
fIH1:
1 MHz internal high-speed oscillation clock frequency
fIH8:
8 MHz internal high-speed oscillation clock frequency
fIH20:
20 MHz internal high-speed oscillation clock frequency
fEX:
External main system clock frequency
fMX:
High-speed system clock frequency
fMAIN:
Main system clock frequency
fMAINC: Main system selection clock frequency
fXT:
XT1 clock oscillation frequency
fSUB:
Subsystem clock frequency
fSUBC: Subsystem selection clock frequency
fCLK:
CPU/peripheral hardware clock frequency
fIL:
Internal low-speed oscillation clock frequency
5.3 Registers Controlling Clock Generator
The following eight registers are used to control the clock generator.
• Clock operation mode control register (CMC)
• Clock operation status control register (CSC)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
• System clock control register (CKC)
• 20 MHz internal high-speed oscillation control register (DSCCTL)
• Peripheral enable register 0 (PER0)
• Operation speed mode control register (OSMC)
(1) Clock operation mode control register (CMC)
This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, and XT2/P124 pins, and
to select a gain of the oscillator.
CMC can be written only once by an 8-bit memory manipulation instruction after reset release. This register can be
read by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
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Figure 5-2. Format of Clock Operation Mode Control Register (CMC)
Address: FFFA0H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
CMC
EXCLK
OSCSEL
0
OSCSELS
0
AMPHS1
AMPHS0
AMPH
EXCLK
OSCSEL
0
0
Input port mode
Input port
0
1
X1 oscillation mode
Crystal/ceramic resonator connection
1
0
Input port mode
Input port
1
1
External clock input mode
Input port
OSCSELS
High-speed system clock
pin operation mode
Subsystem clock pin operation mode
X1/P121 pin
X2/EXCLK/P122 pin
External clock input
XT1/P123 pin
0
Input port mode
Input port
1
XT1 oscillation mode
Crystal resonator connection
AMPHS1
AMPHS0
0
0
Low-consumption oscillation
0
1
Normal oscillation
1
0
Super-low-consumption oscillation
1
1
AMPH
XT2/P124 pin
XT1 oscillator oscillation mode selection
Control of high-speed system clock oscillation frequency
0
2 MHz ≤ fMX ≤ 10 MHz
1
10 MHz < fMX ≤ 20 MHz
Remark fMX: High-speed system clock frequency
Cautions 1. CMC can be written only once after reset release, by an 8-bit memory manipulation
instruction.
2. After reset release, set CMC before X1 or XT1 oscillation is started as set by the
clock operation status control register (CSC).
3. Be sure to set AMPH to 1 if the X1 clock oscillation frequency exceeds 10 MHz.
4. To use CMC with its initial value (00H), be sure to set it to 00H after releasing reset in
order to prevent malfunction when a program loop occurs.
5. The XT1 oscillator is designed as a low-gain circuit for achieving low-power
consumption. Note the following points when designing the XT1 oscillator.
• The pins and circuit board include parasitic capacitance. Therefore, confirm that
there are no problems by performing oscillation evaluation on the circuit board to
be actually used.
• When low-consumption oscillation or super-low-consumption oscillation is
selected, lower power consumption than when selecting normal oscillation can
be achieved. However, in this case, the XT1 oscillation margin is reduced, so
perform sufficient oscillation evaluation of the resonator to be used for XT1
oscillation before using the resonator.
(Cautions are continued on the next page.)
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• Keep the wiring length between the XT1 and XT2 pins and resonator as short as
possible and parasitic capacitance and wire resistance as small as possible. This
is particularly important when super-low-consumption oscillation (AMPHS1 = 1) is
selected.
• Configure the circuit board by using material with little parasitic capacitance and
wire resistance.
• Place a ground pattern that has the same potential as VSS (if possible) around the
XT1 oscillator.
• Do not cross the signal lines between the XT1 and XT2 pins and the resonator
with other signal lines. Do not route the signal lines near a signal line through
which a high fluctuating current flows.
• Moisture absorption by the circuit board and condensation on the board in a
highly humid environment may cause the impedance between the XT1 and XT2
pins to drop and disable oscillation. When using the circuit board in such an
environment, prevent the circuit board from absorbing moisture by taking
measures such as coating the circuit board.
• Coat the surface of the circuit board by using material that does not generate
capacitance or leakage between the XT1 and XT2 pins.
(2) Clock operation status control register (CSC)
This register is used to control the operations of the high-speed system clock, internal high-speed oscillation clock,
and subsystem clock (except the 20 MHz internal high-speed oscillation clock and internal low-speed oscillation clock).
CSC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to C0H.
Figure 5-3. Format of Clock Operation Status Control Register (CSC)
Address: FFFA1H
After reset: C0H
R/W
Symbol
5
4
3
2
1
CSC
MSTOP
XTSTOP
0
0
0
0
0
HIOSTOP
MSTOP
High-speed system clock operation control
X1 oscillation mode
External clock input mode
0
X1 oscillator operating
External clock from EXCLK
pin is valid
1
X1 oscillator stopped
External clock from EXCLK
pin is invalid
XTSTOP
−
Subsystem clock operation control
XT1 oscillation mode
0
XT1 oscillator operating
1
XT1 oscillator stopped
HIOSTOP
Input port mode
Input port mode
−
Internal high-speed oscillation clock operation control
0
Internal high-speed oscillator operating
1
Internal high-speed oscillator stopped
Caution 1. After reset release, set the clock operation mode control register (CMC) before
starting X1 oscillation as set by MSTOP or XT1 oscillation as set by XTSTOP.
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Cautions 2. To start X1 oscillation as set by MSTOP, check the oscillation stabilization time of the
X1 clock by using the oscillation stabilization time counter status register (OSTC).
3. Do not stop the clock selected for the CPU peripheral hardware clock (fCLK) with the
OSC register.
4. The setting of the flags of the register to stop clock oscillation (invalidate the external
clock input) and the condition before clock oscillation is to be stopped are as follows.
Table 5-2. Condition Before Stopping Clock Oscillation and Flag Setting
Clock
X1 clock
External main system
clock
Condition Before Stopping Clock
(Invalidating External Clock Input)
CPU and peripheral hardware clocks operate with a clock
other than the high-speed system clock.
Setting of CSC
Register Flags
MSTOP = 1
• CLS = 0 and MCS = 0
• CLS = 1
Subsystem clock
CPU and peripheral hardware clocks operate with a clock
other than the subsystem clock.
Internal high-speed
oscillation clock
CPU and peripheral hardware clocks operate with a clock
other than the internal high-speed oscillator clock and 20
MHz internal high-speed oscillation clock.
XTSTOP = 1
(CLS = 0)
HIOSTOP = 1
• CLS = 0 and MCS = 1
• CLS = 1
(3) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case,
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or subsystem clock is being used
as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as
the CPU clock with the X1 clock oscillating.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset signal is generated, the STOP instruction and MSTOP (bit 7 of CSC register) = 1 clear OSTC to 00H.
Remark The oscillation stabilization time counter starts counting in the following cases.
• When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 → MSTOP = 0)
• When the STOP mode is released
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Figure 5-4. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H
Symbol
OSTC
After reset: 00H
7
6
5
R
4
3
2
1
0
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11
13
15
17
18
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11
13
15
17
18
Oscillation stabilization time status
fX = 10 MHz
25.6 μs max. 12.8 μs max.
8
25.6 μs min.
12.8 μs min.
9
51.2 μs min.
25.6 μs min.
10
102.4 μs min. 51.2 μs min.
11
204.8 μs min. 102.4 μs min.
13
819.2 μs min. 409.6 μs min.
15
3.27 ms min. 1.64 ms min.
17
13.11 ms min. 6.55 ms min.
18
26.21 ms min. 13.11 ms min.
0
0
0
0
0
0
0
0
2 /fX max.
1
0
0
0
0
0
0
0
2 /fX min.
1
1
0
0
0
0
0
0
2 /fX min.
1
1
1
0
0
0
0
0
2 /fX min.
1
1
1
1
0
0
0
0
2 /fX min.
1
1
1
1
1
0
0
0
2 /fX min.
1
1
1
1
1
1
0
0
fX = 20 MHz
8
2 /fX min.
1
1
1
1
1
1
1
0
2 /fX min.
1
1
1
1
1
1
1
1
2 /fX min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST8 and
remain 1.
2. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than the count value which is to be checked by the OSTC register after the
oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
3. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark
fX: X1 clock oscillation frequency
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(4) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using OSTS after
the STOP mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired
oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be
checked up to the time set using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets OSTS to 07H.
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Figure 5-5. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H
After reset: 07H
R/W
Symbol
7
6
5
4
3
2
1
0
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
0
0
0
2 /fX
0
0
1
2 /fX
0
1
0
2 /fX
0
1
1
2 /fX
Oscillation stabilization time selection
fX = 10 MHz
51.2 μs
25.6 μs
10
102.4 μs
51.2 μs
11
204.8 μs
102.4 μs
13
819.2 μs
409.6 μs
15
3.27 ms
1.64 ms
17
13.11 ms
6.55 ms
18
26.21 ms
13.11 ms
0
0
2 /fX
1
0
1
2 /fX
1
1
0
2 /fX
1
1
fX = 20 MHz
Setting prohibited
9
1
1
25.6 μs
8
2 /fX
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS
register before executing the STOP instruction.
2. Setting the oscillation stabilization time to 20 μs or less is prohibited.
3. To change the setting of the OSTS register, be sure to confirm that the counting
operation of the OSTC register has been completed.
4. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
5. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than the count value which is to be checked by the OSTC register after the
oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
6. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark fX: X1 clock oscillation frequency
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(5) System clock control register (CKC)
This register is used to select a CPU/peripheral hardware clock and a division ratio.
CKC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 09H.
Figure 5-6. Format of System Clock Control Register (CKC)
Address: FFFA4H
After reset: 09H
R/W
Note 1
Symbol
3
2
1
0
CKC
CLS
CSS
MCS
MCM0
SDIV
MDIV2
MDIV1
MDIV0
CLS
Status of CPU/peripheral hardware clock (fCLK)
0
Main system clock (fMAIN)
1
Subsystem clock (fSUB)
MCS
0
Status of Main system clock (fMAIN)
Internal high-speed oscillation clock (fIH) or 20 MHz internal high-speed oscillation clock
(fIH20)
1
CSS
High-speed system clock (fMX)
MCM0
SDIV
MDIV2
MDIV1
Selection of
MDIV0
CPU/peripheral
hardware clock (fCLK)
0
0
0
1
Note 4
1
×
Note 4
×
0
0
0
fIH
×
0
0
1
fIH/2 (default)
×
0
1
0
fIH/2
2
×
0
1
1
fIH/2
3
×
1
0
0
fIH/2
4 Note 2
×
1
0
1
fIH/2
5 Note 2
×
0
0
0
fMX
×
0
0
1
fMX/2
×
0
1
0
fMX/2
2
×
0
1
1
fMX/2
3
×
1
0
0
fMX/2
4
×
1
0
1
fMX/2
5 Note 3
0
×
×
×
fSUB
1
×
×
×
fSUB/2
Other than above
Setting prohibited
Notes 1. Bits 7 and 5 are read-only.
2. Setting is prohibited when fIH = 1 MHz.
3. Setting is prohibited when fMX < 4 MHz.
4. Changing the value of the MCM0 bit is prohibited while CSS is set to 1.
(Remarks and Cautions are listed on the next page.)
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Remarks 1. fIH:
Internal high-speed oscillation clock frequency
fIH20: 20 MHz Internal high-speed oscillation clock frequency
fMX: High-speed system clock frequency
fSUB Subsystem clock frequency
2. ×:
don’t care
Cautions 1. The clock set by CSS, MCM0, SDIV, and MDIV2 to MDIV0 is supplied to the CPU and
peripheral hardware. If the CPU clock is changed, therefore, the clock supplied to
peripheral hardware (except the real-time counter, timer array unit (when fSUB/2, fSUB/4,
the valid edge of TI0mn input, or the valid edge of INTRTCI is selected as the count
clock), clock output/buzzer output, and watchdog timer) is also changed at the same
time.
Consequently,
stop
each
peripheral
function
when
changing
the
CPU/peripheral operating hardware clock.
2. If the peripheral hardware clock is used as the subsystem clock, the operations of
the A/D converter and IICA are not guaranteed. For the operating characteristics of
the peripheral hardware, refer to the chapters describing the various peripheral
hardware as well as CHAPTER 31 ELECTRICAL SPECIFICATIONS.
The fastest instruction can be executed in 1 clock of the CPU clock in the 78K0R/Lx3 microcontrollers. Therefore, the
relationship between the CPU clock (fCLK) and the minimum instruction execution time is as shown in Table 5-3.
Table 5-3. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock
Minimum Instruction Execution Time: 1/fCLK
(Value set by the
SDIV, and MDIV2
to MDIV0 bits)
Subsystem Clock
Main System Clock (CSS = 0)
High-Speed System Clock
(MCM0 = 1)
Clock (MCM0 = 0)
At 10 MHz
At 20 MHz
At 8 MHz (TYP.)
At 20 MHz (TYP.)
Operation
Operation
Operation
Operation
fMAIN
0.1 μs
0.05 μs
fMAIN/2
0.2 μs
0.1 μs
(CSS = 1)
Internal High-Speed Oscillation
At 32.768 kHz Operation
0.125 μs (TYP.)
0.05 μs (TYP.)
−
0.25 μs (TYP.)
0.1 μs (TYP.)
−
(default)
fMAIN/2
2
0.4 μs
0.2 μs
0.5 μs (TYP.)
0.2 μs (TYP.)
−
fMAIN/2
3
0.8 μs
0.4 μs
1.0 μs (TYP.)
0.4 μs (TYP.)
−
fMAIN/2
4
1.6 μs
0.8 μs
2.0 μs (TYP.)
0.8 μs (TYP.)
−
fMAIN/2
5
3.2 μs
1.6 μs
4.0 μs (TYP.)
1.6 μs (TYP.)
−
fSUB
−
−
30.5 μs
fSUB/2
−
−
61 μs
Remark
fMAIN: Main system clock frequency (fIH ,fIH20, or fMX)
fSUB:
Subsystem clock frequency
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(6) 20 MHz internal high-speed oscillation control register (DSCCTL)
This register controls the 20 MHz internal high-speed oscillation clock (DSC) function.
It can be used to select whether to use the 20 MHz internal high-speed oscillation clock (fIH20) as a peripheral
hardware clock that supports 20 MHz.
DSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-7. Format of 20 MHz Internal High-Speed Oscillation Control Register (DSCCTL)
Address: F00F6H
After reset: 00H
R/W
Note
Symbol
7
6
5
4
1
DSCCTL
0
0
0
0
DSCS
SELDSC
0
DSCON
DSCS
20 MHz internal high-speed oscillation supply status flag
0
Not supplied
1
Supplied
SELDSC
0
Selection of 20 MHz internal high-speed oscillation for CPU/peripheral hardware clock (fCLK)
Does not select 20 MHz internal high-speed oscillation (clock selected by CKC register is
supplied to fCLK)
1
Selects 20 MHz internal high-speed oscillation (20 MHz internal high-speed oscillation is
supplied to fCLK)
DSCON
20 MHz internal high-speed oscillation clock (fIH20) operation enable/disable
0
Disables operation.
1
Enables operation.
Note Bit 3 is read-only.
Cautions 1. 20 MHz internal oscillation can only be used if VDD ≥ 2.7 V.
2. Set SELDSC when 100 μ s have elapsed after having set DSCON with VDD ≥ 2.7 V.
3. The internal high-speed oscillator must be operated (HIOSTOP = 0) when DSCON = 1.
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(7) Peripheral enable register 0 (PER0)
This register is used to enable or disable use of each peripheral hardware macro. Clock supply to the hardware that
is not used is also stopped so as to decrease the power consumption and noise.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears theses registers to 00H.
Figure 5-8. Format of Peripheral Enable Register 0 (PER0) (1/2)
Address: F00F0H
Symbol
PER0
After reset: 00H
RTCEN
DACEN
R/W
ADCEN
IICAEN
Note 1
SAU1EN
SAU0EN
TAU1EN
TAU0EN
Note 2
RTCEN
Control of real-time counter (RTC) input clock
Stops input clock supply.
0
• SFR used by the real-time counter (RTC) cannot be written.
• The real-time counter (RTC) is in the reset status.
Supplies input clock.
1
• SFR used by the real-time counter (RTC) can be read and written.
DACEN
Control of D/A converter input clock
Stops input clock supply.
0
• SFR used by the D/A converter cannot be written.
• The D/A converter is in the reset status.
Supplies input clock.
1
• SFR used by the D/A converter can be read and written.
ADCEN
Control of A/D converter, operational amplifier, and voltage reference input clock
Stops input clock supply.
0
• SFR used by the A/D converter, operational amplifier, and voltage reference cannot be
written.
• The A/D converter, operational amplifier, and voltage reference is in the reset status.
Supplies input clock.
1
• SFR used by the A/D converter, operational amplifier, and voltage reference can be read
and written.
IICAEN
Control of serial interface IICA input clock
Stops input clock supply.
0
• SFR used by the serial interface IICA cannot be written.
• The serial interface IICA is in the reset status.
Supplies input clock.
1
• SFR used by the serial interface IICA can be read and written.
Notes 1.
2.
78K0R/LG3, 78K0R/LH3 only
By using RTCEN, can supply and stop the clock that is used when accessing the real-time
counter (RTC) from the CPU. RTCEN cannot control supply of the operating clock (fSUB) to
RTC.
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Figure 5-8. Format of Peripheral Enable Register 0 (PER0) (2/2)
SAU1EN
0
Control of serial array unit 1 input clock
Stops input clock supply.
• SFR used by the serial array unit 1 cannot be written.
• The serial array unit is in the reset status.
1
Supplies input clock.
• SFR used by the serial array unit 1 can be read and written.
SAU0EN
0
Control of serial array unit 0 input clock
Stops input clock supply.
• SFR used by the serial array unit 0 cannot be written.
• The serial array unit 0 is in the reset status.
1
Supplies input clock.
• SFR used by the serial array unit 0 can be read and written.
TAU1EN
0
Control of timer array unit 1 input clock
Stops input clock supply.
• SFR used by timer array unit 1 cannot be written.
• Timer array unit 1 is in the reset status.
1
Supplies input clock.
• SFR used by timer array unit 1 can be read and written.
TAU0EN
0
Control of timer array unit 0 input clock
Stops input clock supply.
• SFR used by timer array unit 0 cannot be written.
• Timer array unit 0 is in the reset status.
1
Supplies input clock.
• SFR used by timer array unit 0 can be read and written.
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(8) Operation speed mode control register (OSMC)
This register is used to control the step-up circuit of the flash memory for high-speed operation.
If the microcontroller operates at a low speed with a system clock of 10 MHz or less, the power consumption can be
lowered by setting this register to the default value, 00H.
OSMC can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-9. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
OSMC
RTCLPC
0
0
0
0
0
FLPC
FSEL
RTCLPC
0
Setting in subsystem clock HALT mode
Enables subsystem clock supply to peripheral functions.
(See Table 21-1 Operating Statuses in HALT Mode (2/3) for the peripheral functions whose
operations are enabled.)
1
Stops subsystem clock supply to peripheral functions except real-time counter, clock
output/buzzer output, and LCD controller/driver.
FLPC
FSEL
fCLK frequency selection
0
0
Operates at a frequency of 10 MHz or less (default).
0
1
Operates at a frequency higher than 10 MHz.
1
0
Operates at a frequency of 1 MHz.
1
1
Setting prohibited
Cautions 1. Write “1” to FSEL before the following two operations.
• Changing the clock prior to dividing fCLK to a clock other than fIH.
• Operating the DMA controller.
2. The CPU waits (140.5 clock (fCLK)) when “1” is written to the FSEL bit.
Interrupt requests issued during a wait will be suspended.
However, counting the oscillation stabilization time of fX can continue even while the
CPU is waiting.
3. To increase fCLK to 10 MHz or higher, set FSEL to “1”, then change fCLK after two or
more clocks have elapsed.
4. Confirm that the clock is operating at 10 MHz or less before setting FSEL = 0.
5. To shift to STOP mode while VDD ≤ 2.7 V, set FSEL = 0 after setting fCLK to 10 MHz or
less.
6. The HALT mode current when operating on the subsystem clock can be reduced by
setting RTCLPC to 1. However, the clock cannot be supplied to peripheral functions
except the real-time counter in the subsystem clock HALT mode. Set bit 7 (RTCEN)
of PER0 to 1 and bits 0 to 6 of PER0 to 0 before setting the subsystem clock HALT
mode.
7. Once FLPC has been set from 0 to 1, setting it back to 0 from 1 other than by reset is
prohibited.
8. When setting FSEL to “1”, do so while RMC = 00H.
When setting FLPC to “1”, do so while RMC = 5AH.
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5.4 System Clock Oscillator
5.4.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or ceramic resonator (2 to 20 MHz) connected to the X1 and X2
pins.
An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as
follows.
• Crystal or ceramic oscillation: EXCLK, OSCSEL = 0, 1
• External clock input:
EXCLK, OSCSEL = 1, 1
When the X1 oscillator is not used, set the input port mode (EXCLK, OSCSEL = 0, 0).
When the pins are not used as input port pins, either, see Table 2-2 to 2-4 Connection of Unused Pins.
Figure 5-10 shows an example of the external circuit of the X1 oscillator.
Figure 5-10. Example of External Circuit of X1 Oscillator
(a) Crystal or ceramic oscillation
(b) External clock
VSS
X1
X2
External clock
EXCLK
Crystal resonator
or
ceramic resonator
Cautions are listed on the next page.
5.4.2 XT1 oscillator
The XT1 oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins.
To use the XT1 oscillator, set bit 4 (OSCSELS) of the clock operation mode control register (CMC) to 1.
When the XT1 oscillator is not used, set the input port mode (OSCSELS = 0).
When the pins are not used as input port pins, either, see Table 2-2 to 2-4 Connection of Unused Pins.
Figure 5-11 shows an example of the external circuit of the XT1 oscillator.
Figure 5-11. Example of External Circuit of XT1 Oscillator (Crystal Oscillation)
VSS
XT1
32.768
kHz
XT2
Cautions are listed on the next page.
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Caution 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the
broken lines in the Figures 5-10 and 5-11 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Note that the XT1 oscillator is designed as a low-gain circuit for achieving low-power consumption.
Note the following points when designing the XT1 oscillator.
• The pins and circuit board include parasitic capacitance. Therefore, confirm that there are no
problems by performing oscillation evaluation on the circuit board to be actually used.
• When low-consumption oscillation or super-low-consumption oscillation is selected, lower
power consumption than when selecting normal oscillation can be achieved. However, in this
case, the XT1 oscillation margin is reduced, so perform sufficient oscillation evaluation of the
resonator to be used for XT1 oscillation before using the resonator.
• Keep the wiring length between the XT1 and XT2 pins and resonator as short as possible and
parasitic capacitance and wire resistance as small as possible. This is particularly important
when super-low-consumption oscillation (AMPHS1 = 1) is selected.
• Configure the circuit board by using material with little parasitic capacitance and wire
resistance.
• Place a ground pattern that has the same potential as VSS (if possible) around the XT1 oscillator.
• Do not cross the signal lines between the XT1 and XT2 pins and the resonator with other signal
lines. Do not route the signal lines near a signal line through which a high fluctuating current
flows.
• Moisture absorption by the circuit board and condensation on the board in a highly humid
environment may cause the impedance between the XT1 and XT2 pins to drop and disable
oscillation. When using the circuit board in such an environment, prevent the circuit board
from absorbing moisture by taking measures such as coating the circuit board.
• Coat the surface of the circuit board by using material that does not generate capacitance or
leakage between the XT1 and XT2 pins.
Figure 5-12 shows examples of incorrect resonator connection.
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Figure 5-12. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
PORT
VSS
X1
X2
VSS
X1
X2
NG
NG
NG
(c) Signal lines of X1 and X2 cross
(d) Power supply/GND pattern exists underneath X1 and X2
wiring
VSS
VSS
X1
X1
X2
X2
Note
Power supply/GND pattern
Note Do not place a power supply/GND pattern underneath the wiring section (in broken lines above) of the X1 and
X2 pins and resonator in the multilayer board and double-sided board.
Do not configure a layout that may cause capacitance elements and affect the oscillation characteristics.
Remark
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors
in series on the XT2 side.
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Figure 5-12. Examples of Incorrect Resonator Connection (2/2)
(e) Wiring near high alternating current
(f) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
VDD
Pmn
X1
X2
High current
VSS
VSS
A
X1
B
X2
C
High current
(g) Signals are fetched
VSS
Remark
X1
X2
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors
in series on the XT2 side.
Caution 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting
in malfunctioning.
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5.4.3 Internal high-speed oscillator
The internal high-speed oscillator is incorporated in the 78K0R/Lx3 (1, 8 and 20 MHz (TYP.)). Oscillation can be
controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC) and bit 0 (DSCON) of the 20 MHz
internal high-speed oscillation control register (DSCCTL).
Caution To use the 1, 8, or 20 MHz internal high-speed oscillation clock, use the option byte to set the frequency
in advance (for details, see CHAPTER 26 OPTION BYTE).
Also, the internal high-speed oscillator
automatically starts oscillating after reset release. (If 8 MHz or 20 MHz is selected by using the option
byte, the microcontroller operates using the 8 MHz internal high-speed oscillator.) To use the 20 MHz
internal high-speed oscillator to operate the microcontroller, oscillation is started by setting bit 0
(DSCON) of the DSCCTL register to 1 with VDD ≥ 2.7 V.
5.4.4 Internal low-speed oscillator
The internal low-speed oscillator is incorporated in the 78K0R/Lx3 microcontrollers.
The internal low-speed oscillation clock is used only as the watchdog timer clock. The internal low-speed oscillation
clock cannot be used as the CPU clock.
After a reset release, the internal low-speed oscillator automatically starts oscillation, and the watchdog timer is driven
(30 kHz (TYP.)) if the watchdog timer operation is enabled by the option byte.
The internal low-speed oscillator continues oscillation except when the watchdog timer stops. When the watchdog
timer operates, the internal low-speed oscillation clock does not stop, even in case of a program loop.
5.4.5 Prescaler
The prescaler generates a CPU/peripheral hardware clock by dividing the main system clock and subsystem clock.
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5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
mode (see Figure 5-1).
• Main system clock fMAIN
• High-speed system clock fMX
X1 clock fX
External main system clock fEX
• Internal high-speed oscillation clock fIH
1 MHz internal high-speed oscillation clock fIH1
8 MHz internal high-speed oscillation clock fIH8
• 20 MHz internal high-speed oscillation clock fIH20
• Subsystem clock fSUB
• Subsystem selection clock fSUBC
• Internal low-speed oscillation clock fIL
• CPU/peripheral hardware clock fCLK
The CPU starts operation when the internal high-speed oscillator starts outputting after a reset release in the
78K0R/Lx3 microcontrollers, thus enabling the following.
(1) Enhancement of security function
When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is
damaged or badly connected and therefore does not operate after reset is released. However, the start clock of the
CPU is the internal high-speed oscillation clock, so the device can be started by the internal high-speed oscillation
clock after a reset release. As a result, reset sources can be detected by software and the minimum amount of safety
processing can be done during anomalies to ensure that the system terminates safely.
(2) Improvement of performance
Because the CPU can be started without waiting for the X1 clock oscillation stabilization time, the total performance
can be improved.
When the power supply voltage is turned on, the clock generator operation is shown in Figure 5-13 and Figure 5-14.
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Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On
(When LVI Default Start Function Stopped Is Set (Option Byte: LVIOFF = 1))
Power supply
voltage (VDD)
1.8 V
1.61 V
(TYP.)
0.5 V/ms
(MIN.)
0V
Internal reset signal
Switched by
software
Reset processing
(2.12 to 5.84 ms)
SELDSC = 1
1 or 8 MHz internal highspeed oscillation clock
CPU clock
20 MHz internal highspeed oscillation clock
1 or 8 MHz internal highspeed oscillation clock
High-speed
system clock
Subsystem
clock
Internal high-speed
oscillation clock (fIH)
High-speed
system clock (fMX)
(when X1 oscillation
selected)
Note 1
20 MHz internal
high-speed
oscillation clock (fIH20)
Subsystem clock (fSUB)
(when XT1 oscillation
selected)
DSCON = 1
is set by software.
X1 clock
oscillation stabilization timeNote 2
Starting X1 oscillation
is specified by software.
20 MHz internal high-speed oscillation clock
oscillation stabilization time : 100 μ s
Starting XT1 oscillation
is specified by software.
When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
When the power supply voltage exceeds 1.61 V (TYP.), the reset is released and the internal high-speed
oscillator automatically starts oscillation.
The CPU starts operation on the internal high-speed oscillation clock
Note 3
after a reset processing such as waiting
for the voltage of the power supply or regulator to stabilize has been performed after reset release.
Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 5.6.1 Example of controlling highspeed system clock and (1) in 5.6.3 Example of controlling subsystem clock).
When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see (3) in 5.6.1 Example of controlling high-speed system clock and (2) in 5.6.3
Example of controlling subsystem clock).
Switch to the 20 MHz internal high-speed oscillation clock by setting the DSCON bit (bit 0 of the 20 MHz internal
high-speed oscillation control register (DSCCTL)), waiting for 100 μs, and then setting the SELDSC bit to 1 by
using software Note 4.
(Notes and Cautions are listed on the next page.)
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Notes 1.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal highspeed oscillation clock.
2.
When releasing a reset, confirm the oscillation stabilization time for the X1 clock using the oscillation
stabilization time counter status register (OSTC).
3.
The microcontroller operates on the 8 MHz internal high-speed oscillation clock if 8 MHz or 20 MHz is
selected for the internal high-speed oscillator by using the option byte or on the 1 MHz internal high-speed
oscillation clock if 1 MHz is selected.
4.
If the internal high-speed oscillator is set to 1 MHz by using the option byte, the 20 MHz internal high-speed
oscillation clock cannot be used.
Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the
voltage reaches 1.8 V, input a low level to the RESET pin from power application until the voltage
reaches 1.8 V, or set the LVI default start function stopped by using the option byte (LVIOFF = 0)
(see Figure 5-14). By doing so, the CPU operates with the same timing as and thereafter in
Figure 5-13 after reset release by the RESET pin.
2. It is not necessary to wait for the oscillation stabilization time when an external clock input from
the EXCLK pin is used.
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Figure 5-14. Clock Generator Operation When Power Supply Voltage Is Turned On
(When LVI Default Start Function Enabled Is Set (Option Byte: LVIOFF = 0))
Power supply
voltage (VDD)
2.07 V
0V
Internal reset signal
Reset processing
(195 to 341 μs)
CPU clock
1 or 8 MHz internal highspeed oscillation clock
Switched by
software
SELDSC = 1
20 MHz internal highspeed oscillation clock
1 or 8 MHz internal highspeed oscillation clock
High-speed
system clock
Subsystem
clock
Internal high-speed
oscillation clock (fIH)
Note 1
High-speed
system clock (fMX)
(when X1 oscillation
selected)
20 MHz internal
high-speed
oscillation clock (fIH20)
DSCON = 1
is set by software.
Subsystem clock (fSUB)
(when XT1 oscillation
selected)
Starting X1 oscillation
is specified by software.
X1 clock
oscillation stabilization timeNote 2
20 MHz internal high-speed oscillation clock
oscillation stabilization time : 100 μ s
Starting XT1 oscillation
is specified by software.
When the power is turned on, an internal reset signal is generated by the low-voltage detector (LVI) circuit.
When the power supply voltage exceeds 2.07 V (TYP.), the reset is released and the internal high-speed
oscillator
Note 3
automatically starts oscillation.
After the reset is released and reset processing is performed, the CPU starts operation on the internal high-speed
oscillation clock
Note 3
.
Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 5.6.1 Example of controlling highspeed system clock and (1) in 5.6.3 Example of controlling subsystem clock).
Switch to oscillation using the 20 MHz internal high-speed oscillation clock after setting the DSCON bit to 1 by
using software.
When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see (3) in 5.6.1 Example of controlling high-speed system clock and (2) in 5.6.3
Example of controlling subsystem clock).
Switch to the 20 MHz internal high-speed oscillation clock after confirming that the power supply voltage is at
least 2.7 V, setting the DSCON bit (bit 0 of the 20 MHz internal high-speed oscillation control register (DSCCTL)),
waiting for 100 μs, and then setting the SELDSC bit to 1 by using software Note 4.
(Notes and Cautions are listed on the next page.)
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Notes 1.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal highspeed oscillation clock.
2.
When releasing a reset, confirm the oscillation stabilization time for the X1 clock using the oscillation
stabilization time counter status register (OSTC).
3.
The microcontroller operates on the 8 MHz internal high-speed oscillation clock if 8 MHz or 20 MHz is
selected for the internal high-speed oscillator by using the option byte or on the 1 MHz internal high-speed
oscillation clock if 1 MHz is selected.
4.
If the internal high-speed oscillator is set to 1 MHz by using the option byte, the 20 MHz internal high-speed
oscillation clock cannot be used.
Cautions 1. A voltage stabilization time (about 2.12 to 5.84 ms) is required after the supply voltage reaches
1.61 V (TYP.). If the time for the supply voltage to rise from 1.61 V (TYP.) to 2.07 V (TYP.) is
shorter than the voltage stabilization time, reset processing is entered after the voltage
stabilization time elapses.
2. It is not necessary to wait for the oscillation stabilization time when an external clock input from
the EXCLK pin is used.
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5.6 Controlling Clock
5.6.1 Example of controlling high-speed system clock
The following two types of high-speed system clocks are available.
• X1 clock:
Crystal/ceramic resonator is connected to the X1 and X2 pins.
• External main system clock: External clock is input to the EXCLK pin.
When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as input port pins.
Caution The X1/P121 and X2/EXCLK/P122 pins are in the input port mode after a reset release.
The following describes examples of setting procedures for the following cases.
(1) When oscillating X1 clock
(2) When using external main system clock
(3) When using high-speed system clock as CPU/peripheral hardware clock
(4) When stopping high-speed system clock
(1) Example of setting procedure when oscillating the X1 clock
Setting P121/X1 and P122/X2/EXCLK pins and setting oscillation frequency (CMC register)
• 2 MHz ≤ fX ≤ 10 MHz
EXCLK
OSCSEL
0
OSCSELS
0
AMPHS1
AMPHS0
AMPH
0
1
0
0/1
0
0/1
0/1
0
• 10 MHz < fX ≤ 20 MHz
EXCLK
OSCSEL
0
OSCSELS
0
AMPHS1
AMPHS0
AMPH
0
1
0
0/1
0
0/1
0/1
1
Remarks 1. fX: X1 clock oscillation frequency
2. For setting of the P123/XT1 and P124/XT2 pins, see 5.6.3
Example of controlling
subsystem clock.
Controlling oscillation of X1 clock (CSC register)
If MSTOP is cleared to 0, the X1 oscillator starts oscillating.
Waiting for the stabilization of the oscillation of X1 clock
Check the OSTC register and wait for the necessary time.
During the wait time, other software processing can be executed with the internal high-speed oscillation clock.
Cautions 1. The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the OSCSELS bit at the same time. For
OSCSELS bit, see 5.6.3 Example of controlling subsystem clock.
2. Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be
used (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
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(2) Example of setting procedure when using the external main system clock
Setting P121/X1 and P122/X2/EXCLK pins (CMC register)
EXCLK
OSCSEL
0
OSCSELS
0
AMPHS1
AMPHS0
AMPH
1
1
0
0/1
0
0/1
0/1
0/1
Remark For setting of the P123/XT1 and P124/XT2 pins, see 5.6.3 (1) Example of setting procedure
when oscillating the subsystem clock.
Controlling external main system clock input (CSC register)
When MSTOP is cleared to 0, the input of the external main system clock is enabled.
Cautions 1. The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the OSCSELS bits at the same time. For
OSCSELS bits, see 5.6.3 Example of controlling subsystem clock.
2. Set the external main system clock after the supply voltage has reached the operable voltage
of the clock to be used (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
(3) Example of setting procedure when using high-speed system clock as CPU/peripheral hardware clock
Setting high-speed system clock oscillationNote
(See 5.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting
procedure when using the external main system clock.)
Note The setting of is not necessary when high-speed system clock is already operating.
Setting the high-speed system clock as the source clock of the CPU/peripheral hardware clock and setting
the division ratio of the set clock (CKC register)
MCM0
MDIV2
MDIV1
Selection of CPU/Peripheral
MDIV0
Hardware Clock (fCLK)
1
0
0
0
fMX
0
0
1
fMX/2
0
1
0
fMX/2
2
0
1
1
fMX/2
3
1
0
0
fMX/2
4
1
0
1
fMX/2
5 Note
Note Setting is prohibited when fMX < 4 MHz.
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If some peripheral hardware macros are not used, supply of the input clock to each hardware macro can be
stopped.
(PER0 register)
RTCEN
DACEN
ADCEN
IICAEN
xxxEN
SAU1EN
SAU0EN
TAU1EN
TAU0EN
Input clock control
0
Stops input clock supply.
1
Supplies input clock.
Remark RTCEN:
DACEN:
Control of the real-time counter input clock
Control of the D/A converter input clock
ADCEN:
Control of the A/D converter and operational amplifier input clock
IICAEN:
Control of the serial interface IICA input clock
SAU1EN:
Control of the serial array unit 1 unit input clock
SAU0EN:
Control of the serial array unit 0 unit input clock
TAU1EN:
Control of the timer array unit 1 input clock
TAU0EN:
Control of the timer array unit 0 input clock
(4) Example of setting procedure when stopping the high-speed system clock
The high-speed system clock can be stopped (disabling clock input if the external clock is used) in the following two
ways.
• Executing the STOP instruction
• Setting MSTOP to 1
(a) To execute a STOP instruction
Setting to stop peripheral hardware
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that cannot be
used in STOP mode, see CHAPTER 21 STANDBY FUNCTION).
Setting the X1 clock oscillation stabilization time after STOP mode is released
If the X1 clock oscillates before the STOP mode is entered, set the value of the OSTS register before
executing the STOP instruction.
Executing the STOP instruction
When the STOP instruction is executed, the system is placed in the STOP mode and X1 oscillation is
stopped (the input of the external clock is disabled).
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(b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1
Confirming the CPU clock status (CKC register)
Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock.
When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the CPU
clock to the subsystem clock or internal high-speed oscillation clock.
CLS
MCS
0
0
CPU Clock Status
Internal high-speed oscillation clock or 20 MHz internal high-speed
oscillation clock
0
1
High-speed system clock
1
×
Subsystem clock
Setting of X1 clock oscillation stabilization time after restart of X1 clock oscillationNote
Prior to setting "1" to MSTOP, set the OSTS register to a value greater than the count value to be
confirmed with the OSTS register after X1 clock oscillation is restarted.
Stopping the high-speed system clock (CSC register)
When MSTOP is set to 1, X1 oscillation is stopped (the input of the external clock is disabled).
Note This setting is required to resume the X1 clock oscillation when the high-speed system clock is in the X1
oscillation mode.
This setting is not required in the external clock input mode.
Caution Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop
peripheral hardware that is operating on the high-speed system clock.
5.6.2 Example of controlling internal high-speed oscillation clock
The following describes examples of clock setting procedures for the following cases.
(1) When restarting oscillation of the internal high-speed oscillation clock
(2) When using internal high-speed oscillation clock as CPU/peripheral hardware clock
(3) When stopping the internal high-speed oscillation clock
(1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clockNote
Setting restart of oscillation of the internal high-speed oscillation clock (CSC register)
When HIOSTOP is cleared to 0, the internal high-speed oscillation clock restarts oscillation.
Note After a reset release, the internal high-speed oscillator automatically starts oscillating and the internal highspeed oscillation clock is selected as the CPU/peripheral hardware clock.
(2) Example of setting procedure when using internal high-speed oscillation clock as CPU/peripheral
hardware clock
Restarting oscillation of the internal high-speed oscillation clockNote
(See 5.6.2 (1) Example of setting procedure when restarting internal high-speed oscillation clock).
Note The setting of is not necessary when the internal high-speed oscillation clock is operating.
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Setting the internal high-speed oscillation clock as the source clock of the CPU/peripheral hardware clock
and setting the division ratio of the set clock (CKC register)
MCM0
MDIV2
MDIV1
MDIV0
Selection of CPU/Peripheral
Hardware Clock (fCLK)
0
0
0
0
fIH
0
0
1
fIH/2
0
1
0
fIH/2
2
0
1
1
fIH/2
3
1
0
0
fIH/2
4
Note
1
0
1
fIH/2
5
Note
Note Setting is prohibited when fIH = 1 MHz.
Caution If switching the CPU/peripheral hardware clock from the high-speed system clock to the
internal high-speed oscillation clock after restarting the internal high-speed oscillation
clock, do so after 10 μs or more have elapsed.
If the switching is made immediately after the internal high-speed oscillation clock is
restarted, the accuracy of the internal high-speed oscillation cannot be guaranteed for 10 μs.
(3) Example of setting procedure when stopping the internal high-speed oscillation clock
The internal high-speed oscillation clock can be stopped in the following two ways.
• Executing the STOP instruction
• Setting HIOSTOP to 1
(a) To execute a STOP instruction
Setting of peripheral hardware
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that cannot be
used in STOP mode, see CHAPTER 21 STANDBY FUNCTION).
Setting the X1 clock oscillation stabilization time after STOP mode is released
If the X1 clock oscillates before the STOP mode is entered, set the value of the OSTS register before
executing the STOP instruction.
Executing the STOP instruction
When the STOP instruction is executed, the system is placed in the STOP mode and internal high-speed
oscillation clock is stopped.
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(b) To stop internal high-speed oscillation clock by setting HIOSTOP to 1
Confirming the CPU clock status (CKC register)
Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed
oscillation clock.
When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so change
the CPU clock to the high-speed system clock or subsystem clock.
CLS
MCS
0
0
CPU Clock Status
Internal high-speed oscillation clock or 20 MHz internal high-speed
oscillation clock
0
1
High-speed system clock
1
×
Subsystem clock
Stopping the internal high-speed oscillation clock (CSC register)
When HIOSTOP is set to 1, internal high-speed oscillation clock is stopped.
Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition, stop
peripheral hardware that is operating on the internal high-speed oscillation clock.
5.6.3 Example of controlling subsystem clock
The subsystem clock can be oscillated by connecting a crystal resonator to the XT1 and XT2 pins.
When the subsystem clock is not used, the XT1/P123 and XT2/P124 pins can be used as input port pins.
Caution The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release.
The following describes examples of setting procedures for the following cases.
(1) When oscillating subsystem clock
(2) When using subsystem clock as CPU clock
(3) When stopping subsystem clock
Caution When the subsystem clock is used as the CPU clock, the subsystem clock is also supplied to the
peripheral hardware (except the real-time counter, timer array unit (when fSUB/2, fSUB/4, the valid edge
of TI0mn input, or the valid edge of INTRTCI is selected as the count clock), clock output/buzzer
output, and watchdog timer). At this time, the operations of the A/D converter and IICA are not
guaranteed.
For the operating characteristics of the peripheral hardware, refer to the chapters
describing the various peripheral hardware as well as CHAPTER 31 ELECTRICAL SPECIFICATIONS.
(1) Example of setting procedure when oscillating the subsystem clock
Setting P123/XT1 and P124/XT2 pins (CMC register)
EXCLK
OSCSEL
0
OSCSELS
0
AMPHS1
AMPHS0
AMPH
0/1
0/1
0
1
0
0/1
0/1
0/1
Remark For setting of the P121/X1 and P122/X2 pins, see 5.6.1 Example of controlling high-speed
system clock.
Controlling oscillation of subsystem clock (CSC register)
If XTSTOP is cleared to 0, the XT1 oscillator starts oscillating.
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Waiting for the stabilization of the subsystem clock oscillation
Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function.
Caution The CMC register can be written only once after reset release, by an 8-bit memory manipulation
instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the same time.
For EXCLK and OSCSEL bits, see 5.6.1 (1) Example of setting procedure when oscillating the X1
clock or 5.6.1 (2) Example of setting procedure when using the external main system clock.
(2) Example of setting procedure when using the subsystem clock as the CPU clock
Setting subsystem clock oscillationNote
(See 5.6.3 (1) Example of setting procedure when oscillating the subsystem clock.)
Note The setting of is not necessary when while the subsystem clock is operating.
Setting the subsystem clock as the source clock of the CPU/peripheral hardware clock and setting the
division ratio of the set clock (CKC register)
CSS
SDIV
Selection of CPU/Peripheral Hardware Clock (fCLK)
1
0
fSUB
1
fSUB/2
Caution When the subsystem clock is used as the CPU clock, the subsystem clock is also supplied to the
peripheral hardware (except the real-time counter, timer array unit (when fSUB/2, fSUB/4, the valid
edge of TI0mn input, or the valid edge of INTRTCI is selected as the count clock), clock
output/buzzer output, and watchdog timer). At this time, the operations of the A/D converter and
IICA are not guaranteed. For the operating characteristics of the peripheral hardware, refer to the
chapters describing the various peripheral hardware as well as CHAPTER 31 ELECTRICAL
SPECIFICATIONS.
(3) Example of setting procedure when stopping the subsystem clock
Confirming the CPU clock status (CKC register)
Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock.
When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal highspeed oscillation clock or high-speed system clock.
CLS
MCS
0
0
Internal high-speed oscillation clock or 20 MHz internal high-speed
oscillation clock
CPU Clock Status
0
1
High-speed system clock
1
×
Subsystem clock
Stopping the subsystem clock (CSC register)
When XTSTOP is set to 1, subsystem clock is stopped.
Cautions 1. Be sure to confirm that CLS = 0 when setting XTSTOP to 1. In addition, stop the peripheral
hardware if it is operating on the subsystem clock.
2. The subsystem clock oscillation cannot be stopped using the STOP instruction.
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5.6.4 Example of controlling internal low-speed oscillation clock
The internal low-speed oscillation clock cannot be used as the CPU clock. Used only as the watchdog timer clock.
The internal low-speed oscillator automatically starts oscillation after a reset release, and the watchdog timer is driven
(30 kHz (TYP.)) if the watchdog timer operation is enabled by the option byte.
The internal low-speed oscillator continues oscillation except when the watchdog timer stops. When the watchdog
timer operates, the internal low-speed oscillation clock does not stop even in case of a program loop.
(1) Example of setting procedure when stopping the internal low-speed oscillation clock
The internal low-speed oscillation clock can be stopped in the following two ways.
• Stop the watchdog timer in the HALT/STOP mode by the option byte (bit 0 (WDSTBYON) of 000C0H = 0), and
execute the HALT or STOP instruction.
• Stop the watchdog timer by the option byte (bit 4 (WDTON) of 000C0H = 0).
(2) Example of setting procedure when restarting oscillation of the internal low-speed oscillation clock
The internal low-speed oscillation clock can be restarted as follows.
• Release the HALT or STOP mode
(only when the watchdog timer is stopped in the HALT/STOP mode by the option byte (bit 0 (WDSTBYON) of
000C0H) = 0) and when the watchdog timer is stopped as a result of execution of the HALT or STOP instruction).
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5.6.5 CPU clock status transition diagram
Figure 5-15 shows the CPU clock status transition diagram of this product.
Figure 5-15. CPU Clock Status Transition Diagram
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation: Stops (input port mode)
DSC oscillation: Stops
Power ON
VDD < 1.61 V±0.09
(A)
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Cannot be selected by CPU
XT1 oscillation:
Cannot be selected by CPU
DSC oscillation: Operating
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Oscillatable
DSC oscillation: Operating
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Selectable by CPU
DSC oscillation: Selectable by CPU
Notes 2, 3
VDD ≥ 1.8 V
Note 1
(B)
CPU: Operating
with internal highspeed oscillation
(H)
CPU: Internal highspeed oscillation
→ STOP
(J)
(D)
(K)
CPU:
XT1 oscillation
→ HALT
(E)
CPU:
Operating with
XT1 oscillation
CPU: Internal highspeed oscillation
→ HALT
(C)
CPU: Operating
with X1 oscillation or
EXCLK input
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Operating
DSC oscillation: Stops
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Operating
DSC oscillation: Stops
Notes 1.
VDD ≥ 1.61 V±0.09
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation: Stops (input port mode)
DSC oscillation: Stops
CPU:
Operating with
DSC oscillation
CPU:
DSC oscillation
→ HALT
(G)
Reset release
(I)
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Oscillatable
DSC oscillation: Stops
CPU: X1
oscillation/EXCLK
input → STOP
(F)
CPU: X1
oscillation/EXCLK
input → HALT
Internal high-speed
oscillation: Selectable by CPU
X1 oscillation/EXCLK input:
Operating
XT1 oscillation:
Selectable by CPU
DSC oscillation: Stops
Internal high-speed
oscillation: Stops
X1 oscillation/EXCLK
input: Stops
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed
oscillation: Oscillatable
X1 oscillation/EXCLK input:
Operating
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input:
Stops
XT1 oscillation: Oscillatable
DSC oscillation: Stops
After reset release, an operation at one of the following operating frequencies is started, because fCLK = fIH/2
has been selected by setting the system clock control register (CKC) to 09H.
• When 1 MHz has been selected by using the option byte: 500 kHz (1 MHz/2)
• When 8 MHz or 20 MHz has been selected by using the option byte: 4 MHz (8 MHz/2)
2.
Specify 20 MHz internal oscillation after checking that VDD is at least 2.7 V.
3.
20 MHz internal oscillation cannot be used if 1 MHz internal oscillation is selected by using the option byte.
Remarks 1. If the low-power-supply detector (LVI) is set to ON by default by the option bytes, the reset will not be
released until the power supply voltage (VDD) exceeds 2.07 V±0.2 V.
After the reset operation, the status will shift to (B) in the above figure.
2. DSC: 20 MHz internal high-speed oscillation clock
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Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers.
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/6)
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
Status Transition
(A) → (B)
SFR Register Setting
SFR registers do not have to be set (default status after reset release).
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register
Note 1
CSC
OSMC
OSTC
CKC
Register
Register
Register
Register
Status Transition
EXCLK
OSCSEL
AMPH
MSTOP
FSEL
(A) → (B) → (C)
0
1
0
0
0
(X1 clock: 2 MHz ≤ fX ≤ 10 MHz)
(A) → (B) → (C)
Must be
1
checked
0
1
1
0
1
Note 2
(X1 clock: 10 MHz < fX ≤ 20 MHz)
(A) → (B) → (C)
MCM0
Must be
1
checked
1
×
1
0
0/1
Note 2
(external main clock)
Must
1
not be
checked
Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory
manipulation instruction after reset release.
2. FSEL = 1 when fCLK > 10 MHz
If a divided clock is selected and fCLK ≤ 10 MHz, use with FSEL = 0 is possible even if fX > 10 MHz.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 31 ELECTRICAL SPECIFICATIONS).
(3) CPU operating with subsystem clock (D) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register
Note
CSC
Waiting for
CKC
Register
Oscillation
Register
Status Transition
OSCSELS
AMPHS1
AMPHS0
XTSTOP
Stabilization
CSS
(A) → (B) → (D)
1
0/1
0/1
0
Necessary
1
Note The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release.
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
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Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/6)
(4) CPU operating with 20 MHz internal high-speed oscillation clock (J) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
Note
Waiting for Oscillation
DSCCTL Register
DSCON
Stabilization
SELDSC
1
Necessary
1
DSCCTL Register
(A) → (B) → (J)
(100 μs)
Note
Check that VDD ≥ 2.7 V and set DSCON = 1.
(5) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register
Note 1
OSTS
CSC
Register
Register
OSMC
OSTC
CKC
Register
Register
Regi
Status Transition
ster
(B) → (C)
EXCLK
OSCSEL
AMPH
0
1
0
MSTOP
FSEL
0
0
Note 2
0
1
1
Note 2
0
1
Note 3
1
Must be
1
checked
(X1 clock: 10 MHz < fX ≤ 20 MHz)
(B) → (C)
Must be
checked
(X1 clock: 2 MHz ≤ fX ≤ 10 MHz)
(B) → (C)
MCM0
1
1
×
Note 2
0
Must
0/1
1
not be
(external main clock)
checked
Unnecessary if these registers
Unnecessary if the CPU is operating with
are already set
the high-speed system clock
Notes 1. The CMC register can be changed only once after reset release. This setting is not necessary if it has
already been set.
2. Set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
3. FSEL = 1 when fCLK > 10 MHz
If a divided clock is selected and fCLK ≤ 10 MHz, use with FSEL = 0 is possible even if fX > 10 MHz.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. ×: don’t care
2. (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
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Table 5-4. CPU Clock Transition and SFR Register Setting Examples (3/6)
(6) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register
Note
CSC Register
Waiting for
CKC Register
XTSTOP
Oscillation
CSS
OSCSELS
Status Transition
Stabilization
(B) → (D)
1
0
Necessary
1
Unnecessary if the CPU is operating
with the subsystem clock
Note The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release.
(7) CPU clock changing from internal high-speed oscillation clock (B) to 20 MHz internal high-speed oscillation
clock (J)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
Note
Waiting for Oscillation
DSCCTL Register
DSCON
Stabilization
SELDSC
1
Necessary (100 μs)
1
DSCCTL Register
(B) → (J)
Unnecessary if the CPU is operating with the 20 MHz
internal high-speed oscillation clock
Note
Check that VDD ≥ 2.7 V and set DSCON = 1.
(8) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(C) → (B)
CSC Register
Oscillation accuracy
CKC Register
HIOSTOP
stabilization time
MCM0
0
10 μ s
0
Unnecessary if the
CPU is operating with
the internal highspeed oscillation
clock
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
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Table 5-4. CPU Clock Transition and SFR Register Setting Examples (4/6)
(9) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CSC Register
Waiting for Oscillation
CKC Register
XTSTOP
Stabilization
CSS
0
Necessary
1
Status Transition
(C) → (D)
Unnecessary if the CPU is operating with the
subsystem clock
(10) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(D) → (B)
CSC Register
CKC Register
HIOSTOP
MCM0
CSS
0
0
0
Unnecessary if the CPU
Unnecessary if this
is operating with the
register is already set
internal high-speed
oscillation clock
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
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Table 5-4. CPU Clock Transition and SFR Register Setting Examples (5/6)
(11) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
OSTS
CSC Register
Register
Status Transition
(D) → (C) (X1 clock: 2 MHz ≤
Note 1
OSMC
OSTC
Register
Register
MSTOP
FSEL
0
0
Must be
fX ≤ 10 MHz)
CKC Register
MCM0
CSS
1
0
1
0
1
0
checked
(D) → (C) (X1 clock: 10 MHz
Note 1
0
1
Note 2
Must be
< fX ≤ 20 MHz)
checked
(D) → (C) (external main
Note 1
0
0/1
Must not be
clock)
checked
Unnecessary if the CPU is operating with
the high-speed system clock
Unnecessary
if these
registers are
already set
Notes 1. Set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
2. FSEL = 1 when fCLK > 10 MHz
If a divided clock is selected and fCLK ≤ 10 MHz, use with FSEL = 0 is possible even if fX > 10 MHz.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 31 ELECTRICAL SPECIFICATIONS).
(12) CPU clock changing from 20 MHz internal high-speed oscillation clock (J) to internal high-speed oscillation
clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(J) → (B)
DSCCTL Register
SELDSC
DSCON
0
0
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
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Table 5-4. CPU Clock Transition and SFR Register Setting Examples (6/6)
(13) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
• HALT mode (K) set while CPU is operating with 20 MHz internal high-speed oscillation clock (J)
Status Transition
(B) → (E)
Setting
Executing HALT instruction
(C) → (F)
(D) → (G)
(J) → (K)
(14) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
(Setting sequence)
Status Transition
Setting
(B) → (H)
Stopping peripheral
(C) → (I)
functions that cannot
Sets the OSTS
operate in STOP
register
In X1 oscillation
External main
−
mode
Executing STOP
instruction
−
system clock
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
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5.6.6 Condition before changing CPU clock and processing after changing CPU clock
Condition before changing the CPU clock and processing after changing the CPU clock are shown below.
Table 5-5. Changing CPU Clock (1/2)
CPU Clock
Before Change
Condition Before Change
Processing After Change
After Change
Stabilization of X1 oscillation
Operating current can be reduced by
speed
• OSCSEL = 1, EXCLK = 0, MSTOP = 0
stopping internal high-speed oscillator
oscillation clock
• After elapse of oscillation stabilization time
(HIOSTOP = 1).
Internal high-
X1 clock
External main
Enabling input of external clock from
system clock
EXCLK pin
• OSCSEL = 1, EXCLK = 1, MSTOP = 0
Subsystem
Stabilization of X1 oscillation
clock
• OSCSELS = 1, XTSTOP = 0
−
• After elapse of oscillation stabilization time
20 MHz internal
Stabilization of DSC oscillation with 20
high-speed
MHz set by using the option byte
oscillation clock
−
• VDD ≥ 2.7 V
• After elapse of oscillation stabilization
time (100 μs) after setting to DSCON = 1
• SELDSC = 1
X1 clock
Internal high-
Oscillation of internal high-speed oscillator
X1 oscillation can be stopped (MSTOP =
speed oscillation
• HIOSTOP = 0
1).
clock
External main
Transition not possible
system clock
(To change the clock, set it again after
−
executing reset once.)
Subsystem
Stabilization of XT1 oscillation
X1 oscillation can be stopped (MSTOP =
clock
• OSCSELS = 1, XTSTOP = 0
1).
• After elapse of oscillation stabilization time
−
20 MHz internal
Transition cannot be performed unless the
high-speed
clock is changed to the internal high-speed
oscillation clock
oscillation clock once.
External main
Internal high-
Oscillation of internal high-speed oscillator
External main system clock input can
system clock
speed
• HIOSTOP = 0
be disabled (MSTOP = 1).
oscillation clock
X1 clock
Transition not possible
−
(To change the clock, set it again after
executing reset once.)
Subsystem
Stabilization of XT1 oscillation
External main system clock input can
clock
• OSCSELS = 1, XTSTOP = 0
be disabled (MSTOP = 1).
• After elapse of oscillation stabilization time
20 MHz internal
Transition cannot be performed unless the
high-speed
clock is changed to the internal high-speed
oscillation clock
oscillation clock once.
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Table 5-5. Changing CPU Clock (2/2)
CPU Clock
Before Change
Condition Before Change
Processing After Change
After Change
Subsystem
Internal high-
Oscillation of internal high-speed oscillator
XT1 oscillation can be stopped (XTSTOP
clock
speed
and selection of internal high-speed
= 1)
oscillation clock
oscillation clock as main system clock
• HIOSTOP = 0, MCS = 0
X1 clock
Stabilization of X1 oscillation and selection
of high-speed system clock as main
system clock
• OSCSEL = 1, EXCLK = 0, MSTOP = 0
• After elapse of oscillation stabilization time
• MCS = 1
External main
Enabling input of external clock from
system clock
EXCLK pin and selection of high-speed
system clock as main system clock
• OSCSEL = 1, EXCLK = 1, MSTOP = 0
• MCS = 1
−
20 MHz internal
Transition cannot be performed unless the
high-speed
clock is changed to the internal high-speed
oscillation clock
oscillation clock once.
20 MHz internal
Internal high-
• SELDSC = 0
20 MHz internal high-speed oscillation
high-speed
speed
(Set when changing the clock.)
clock can be stopped (DSCON = 0)
oscillation clock
oscillation clock
X1 clock
Transition cannot be performed unless the
−
clock is changed to the internal high-speed
oscillation clock once.
External main
Transition cannot be performed unless the
system clock
clock is changed to the internal high-speed
Subsystem
Transition cannot be performed unless the
clock
clock is changed to the internal high-speed
−
oscillation clock once.
−
oscillation clock once.
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5.6.7 Time required for switchover of CPU clock and main system clock
By setting bits 0 to 2, 4, and 6 (MDIV0 to MDIV2, SDIV, MCM0, CSS) of the system clock control register (CKC), the
CPU clock can be switched (between the main system clock and the subsystem clock), main system clock can be
switched (between the internal high-speed oscillation clock and the high-speed system clock), and the division ratio of the
main system clock can be changed.
The actual switchover operation is not performed immediately after rewriting to CKC; operation continues on the preswitchover clock for several clocks (see Table 5-6 to Table 5-9).
Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 7 (CLS) of
CKC. Whether the main system clock is operating on the high-speed system clock or internal high-speed oscillation clock
can be ascertained using bit 5 (MCS) of CKC.
When the CPU clock is switched, the peripheral hardware clock is also switched.
Internal high-speed oscillation clock
Table 5-6. Maximum Time Required for Main System Clock Switchover
Clock A
Switching directions
Clock B
fMAINC
Remark
see Table 5-7
fMAINC
(changing the division ratio)
fSUBC
fSUBC
fIH
fMX
see Table 5-8
fMAINC
fSUBC
see Table 5-9
Table 5-7. Maximum Number of Clocks Required in fMAINC ↔fMAINC (changing the division ratio),
fSUBC ↔fSUBC (changing the division ratio)
Set Value Before Switchover
Set Value After Switchover
Clock A
Clock B
Clock A
1 + fA/fB clock
Clock B
1 + fB/fA clock
Table 5-8. Maximum Number of Clocks Required in fIH ↔fMX
Set Value Before Switchover
Set Value After Switchover
MCM0
MCM0
0
1
(f MAIN = f IH )
(f MAIN = f MX )
0
f MX ≥f IH
(f MAIN = f IH )
f MX f SUBC
1
2 + fSUBC/fMAINC clock
(f CLK = f SUBC )
Remarks 1. The number of clocks listed in Table 5-7 to Table 5-9 is the number of CPU clocks before switchover.
2. Calculate the number of clocks in Table 5-7 to Table 5-9 by removing the decimal portion.
Example When switching the main system clock from the internal high-speed oscillation clock to the
high-speed system clock (@ oscillation with fIH = 8 MHz, fMX = 10 MHz)
1 + fIH/fMX = 1 + 8/10 = 1 + 0.8 = 1.8 → 2 clocks
5.6.8 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 5-10. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock
Conditions Before Clock Oscillation Is Stopped
Flag Settings of SFR
(External Clock Input Disabled)
Register
Internal high-speed
MCS = 1 or CLS = 1
oscillation clock
(The CPU is operating on a clock other than the internal high-speed
HIOSTOP = 1
oscillation clock)
X1 clock
MCS = 0 or CLS = 1
External main system clock
(The CPU is operating on a clock other than the high-speed system clock)
Subsystem clock
CLS = 0
MSTOP = 1
XTSTOP = 1
(The CPU is operating on a clock other than the subsystem clock)
20 MHz internal high-speed
SELDSC = 0
oscillation clock
(The main system clock is operating on a clock other than the 20 MHz
DSCON = 0
internal high-speed oscillation clock.)
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CHAPTER 6 TIMER ARRAY UNIT
Item
78K0R/LF3
78K0R/LG3
78K0R/LH3
80 pins
100 pins
128 pins
Timer array
0
8 ch (PWM output: 5)
8 ch (PWM output: 7)
8 ch (PWM output: 7)
unit
1
4 ch (PWM output: 0)
4 ch (PWM output: 0)
4 ch (PWM output: 3)
The 78K0R/Lx3 is provided with two timer array units. Time array unit 0 is provided with eight 16-bit timers and timer
array unit 1 is provided with four 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent
timer. In addition, two or more “channels” can be used to create a high-accuracy timer.
Independent Operation Function
Combination Operation Function
• Interval timer
• PWM output
• Square wave output
• One-shot pulse output
• Multiple PWM output
• External event counter
• Divider function
• Input pulse interval measurement
• Measurement of high-/low-level width of input signal
Channel 7 of timer array unit 0 can be used to realize LIN-bus reception processing in combination with UART3 of serial
array unit 1.
Cautions 1. Channel 5 of timer array unit 0 of the 78K0R/LF3 can be used only as an interval timer.
2. Channel 6 of timer array unit 0 of the 78K0R/LF3 can be used only as an interval timer, for PWM
output (master channel), and for one-shot pulse output (master channel when software trigger
start is selected).
3. Channels 0 to 3 of timer array unit 1 of the 78K0R/LF3 and 78K0R/LG3 can be used only as
interval timers.
4. Channels 1, 5 to 7 of timer array unit 0 and channels 0 to 3 of timer array unit 1 cannot be used as
frequency dividers.
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Whether each channel of the timer array unit is provided with timer I/O pins differs depending on the product.
Timer array unit n
Channel m
Input (TIpq) /
output (TOpq)
0
0
Timer I/O Pins of Each Product
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins)
(100 pins)
(128 pins)
Input
TI00/TO03/P31/RTCDIV/RTCCL/PCLBUZ1/INTP2
Output
TO00/TI03/P30RTC1HZ/INTP1
1
I/O
TI01/TO01/P32/PCLBUZ0/INTP5
2
Input
TI02/P52/SEGxx
(78K0R/LF3: xx = 28, 78K0R/LG3: xx = 37, 78K0R/LH3: xx = 51)
3
4
Output
TO02/P12/SO02/TxD2
Input
TI03/TO00/P30RTC1HZ/INTP1
Output
TO03/TI00/P31/RTCDIV/RTCCL/PCLBUZ1/INTP2
Input
TI04/P53/SEGxx
(78K0R/LF3: xx = 27, 78K0R/LG3: xx = 36, 78K0R/LH3: xx = 50)
Output
1
TO04/P13/SO10/TxD1
−
5
I/O
6
I/O
7
I/O
TI07/TO07/P33/INTP3
0
I/O
−
1
I/O
TI11/TO11/P85
2
I/O
TI12/TO12/P86
3
I/O
TI13/TO13/P87
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6.1 Functions of Timer Array Unit
The timer array unit has the following functions.
6.1.1 Functions of each channel when it operates independently
Independent operation functions are those functions that can be used for any channel regardless of the operation mode
of the other channel (for details, refer to 6.6.1 Overview of single-operation function and combination operation
function).
(1) Interval timer
Each timer of a unit can be used as a reference timer that generates an interrupt (INTTMmn) at fixed intervals.
(2) Square wave output
A toggle operation is performed each time INTTMpq is generated and a square wave with a duty factor of 50% is
output from a timer output pin (TOpq).
(3) External event counter
Each timer of a unit can be used as an event counter that generates an interrupt when the number of the valid
edges of a signal input to the timer input pin (TIpq) has reached a specific value.
(4) Divider function
A clock input from a timer input pin (TIpq) is divided and output from an output pin (TOpq).
(5) Input pulse interval measurement
Counting is started by the valid edge of a pulse signal input to a timer input pin (TIpq). The count value of the timer
is captured at the valid edge of the next pulse. In this way, the interval of the input pulse can be measured.
(6) Measurement of high-/low-level width of input signal
Counting is started by a single edge of the signal input to the timer input pin (TIpq), and the count value is captured
at the other edge. In this way, the high-level or low-level width of the input signal can be measured.
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
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6.1.2 Functions of each channel when it operates with another channel
Combination operation functions are those functions that are attained by using the master channel (mostly the
reference timer that controls cycles) and the slave channels (timers that operate following the master channel) in
combination (for details, refer to 6.6.1 Overview of single-operation function and combination operation function).
(1) PWM (Pulse Width Modulator) output
Two channels are used as a set to generate a pulse with a specified period and a specified duty factor.
(2) One-shot pulse output
Two channels are used as a set to generate a one-shot pulse with a specified delay time and a specified pulse
width.
(3) Multiple PWM (Pulse Width Modulator) output
By extending the PWM function and using one master channel and two or more slave channels, up to seven types
of PWM signals that have a specific period and a specified duty factor can be generated.
6.1.3 LIN-bus supporting function (channel 7 of timer array unit 0 only)
(1) Detection of wakeup signal
The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD3) of UART3 and the
count value of the timer is captured at the rising edge. In this way, a low-level width can be measured. If the lowlevel width is greater than a specific value, it is recognized as a wakeup signal.
(2) Detection of sync break field
The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD3) of UART3 after a
wakeup signal is detected, and the count value of the timer is captured at the rising edge. In this way, a low-level
width is measured. If the low-level width is greater than a specific value, it is recognized as a sync break field.
(3) Measurement of pulse width of sync field
After a sync break field is detected, the low-level width and high-level width of the signal input to the serial data
input pin (RxD3) of UART3 are measured. From the bit interval of the sync field measured in this way, a baud rate
is calculated.
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6.2 Configuration of Timer Array Unit
The timer array unit includes the following hardware.
Table 6-1. Configuration of Timer Array Unit
Item
Configuration
Timer/counter
Timer counter register mn (TCRmn)
Register
Timer data register mn (TDRmn)
Timer input
TIpq pin, RxD3 pin (for LIN-bus)
Timer output
TOpq pins, output controller
Control registers
• Peripheral enable register 0 (PER0)
• Timer clock select register m (TPSm)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer input select registers 0, 1 (TIS0, TIS1)
• Timer output enable register p (TOEp)
• Timer output register p (TOp)
• Timer output level register p (TOLp)
• Timer output mode register p (TOMp)
• Timer mode register mn (TMRmn)
• Timer status register pq (TSRpq)
• Input switch control register (ISC) (channel 7 of timer array unit 0 only)
• Noise filter enable registers 1, 2 (NFEN1, NFEN2)
• Port mode registers 1, 3, 5, 8 (PM1, PM3, PM5, PM8)
• Port registers 1, 3, 5, 8 (P1, P3, P5, P8)
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 0, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 0, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 0, 1, pq = 00 to 07, 10 to 13
Figures 6-1 and 6-2 show block diagrams.
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Figure 6-1. Block Diagram of Timer Array Unit 0
Timer clock select register 0 (TPS0)
Peripheral enable
register 0 TAU0EN
(PER0)
PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000
4
TE07
TE06
TE05
TE04
TE03
TE02
TE01
TE00
Timer channel
enable status
register 0 (TE0)
TS07
TS06
TS05
TS04
TS03
TS02
TS01
TS00
Timer channel
start register 0
(TS0)
TT07
TT06
TT05
TT04
TT03
TT02
TT01
TT00
Timer channel
stop register 0
(TT0)
4
fCLK
Prescaler
Timer input
TIS07 TIS06 TIS05 TIS04 TIS03 TIS02 TIS01 TIS00 select register 0
(TIS0)
fCLK/20 to fCLK/215
fCLK/20 to fCLK/215
0
Selector
Selector
0
RTCIS RTCIS
00
04
Bits 0 to 3 are used
by timer array unit 1
Timer input
select register 1
(TIS1)
Noise filter
TNFEN TNFEN TNFEN TNFEN TNFEN TNFEN TNFEN TNFEN enable register 1
01
00
02
04
03
07
06
05
(NFEN1)
Timer output
TOE07 TOE06 TOE05 TOE04 TOE03 TOE02 TOE01 TOE00 enable register 0
(TOE0)
TO07 TO06 TO05
TO04
TO03 TO02 TO01
TO00
Timer output
register 0
(TO0)
Timer output
TOM07 TOM06 TOM05 TOM04 TOM03 TOM02 TOM01 TOM00 mode register 0
(TOM0)
Timer output
TOL07 TOL06 TOL05 TOL04 TOL03 TOL02 TOL01 TOL00 level register 0
(TOL0)
3
RTC interval
interrupt
(INTRTCI)
: fXT/26 to fXT/212
TIS00, RTCIS00, SDIV
Selector
fSUBC/2
TO00
INTTM00
Noise elimination
enabled/disabled
TI00
Slave/master
controller
Channel 0
Noise elimination
enabled/disabled
Selector
fSUBC/2
TI01
(Timer
input pin)
MCK
Edge
detection
Selector
CK01
TCLK
Trigger
selection
Operating
clock selection
CK00
Count clock
selection
Trigger signal to slave channel
Clock signal to slave channel
Interrupt signal to slave channel
Timer controller
Mode
selection
Output
controller
Output latch
(P32)
TO01
(Timer
output pin)
PM32
Interrupt
controller
INTTM01
(Timer
interrupt)
Timer counter register 01 (TCR01)
Timer status
register 01 (TSR01)
TIS01
Timer data register 01 (TDR01)
Slave/master
controller
Overflow
OVF
01
TNFEN01
CKS01 CCS01
Channel 1
MAS
STS012 STS011 STS010 CIS011 CIS010 MD013 MD012 MD011 MD010
TER01
Timer mode register 01 (TMR01)
TO02
INTTM02
TI02
Channel 2
A/D converter
(ADTMD = 1, ADTRS = 0 setting)
TO03
INTTM03
TI03
Channel 3
RTC interval
interrupt
(INTRTCI)
: fXT/26 to fXT/212
3
TIS04, RTCIS04, SDIV
Selector
fSUBC/2
A/D converter
(ADTMD = 1, ADTRS = 1 setting)
TO04
Noise elimination
enabled/disabled
INTTM04
Channel 0 of the D/A converter
(DAMD0 = 1 setting)
TI04
Channel 4
TI05
Channel 5
INTTM05
Channel 6
INTTM06
TO05
Channel 1 of the D/A converter
(DAMD1 = 1 setting)
TO06
TI06
Selector
ISC1
TI07
RxD3
(Serial input pin)
TO07
INTTM07
Channel 7 (LIN-bus supported)
Remark Channels 5 and 6 of the 78K0R/LF3 are not provided with timer I/O pins (TI05/TO05, TI06/TO06).
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Figure 6-2. Block Diagram of Timer Array Unit 1
TE13
TE12
TE11
TE10
Timer channel
enable status
register 1 (TE1)
TS13
TS12
TS11
TS10
Timer channel
start register 1
(TS1)
TT13
TT12
TT11
TT10
Timer channel
stop register 1
(TT1)
Timer clock select register 1 (TPS1)
Peripheral enable
register 0 TAU1EN
(PER0)
PRS113 PRS112PRS111 PRS110 PRS103 PRS102PRS101 PRS100
4
4
fCLK
Prescaler
TIS13 TIS12 TIS11 TIS10
Noise filter
TNFEN TNFEN TNFEN TNFEN enable register 2
11
10
12
13
(NFEN2)
fCLK/20 to fCLK/215
fCLK/20 to fCLK/215
Timer output
TOE13 TOE12 TOE11 TOE10 enable register 1
(TOE1)
Selector
Selector
Timer input
select register 1
(TIS1)
TO13 TO12 TO11
TO10
Timer output
register 1
(TO1)
Timer output
TOM13 TOM12 TOM11 TOM10 mode register 1
(TOM1)
Timer output
TOL13 TOL12 TOL11 TOL10 level register 1
(TOL1)
TI10
TO10
Slave/master
controller
Channel 0
INTTM10
Operating
clock selection
CK11
Noise elimination
enabled/disabled
Selector
fSUBC/2
TI11
(Timer
input pin)
MCK
Edge
detection
TCLK
Trigger
selection
CK10
Count clock
selection
Trigger signal to slave channel
Clock signal to slave channel
Interrupt signal to slave channel
Timer controller
Mode
selection
Output
controller
Interrupt
controller
Output latch
(P85)
TO11
(Timer
output pin)
PM85
INTTM11
(Timer
interrupt)
Timer counter register 11 (TCR11)
Timer status
register 11 (TSR11)
TIS11
Timer data register 11 (TDR11)
Slave/master
controller
Overflow
OVF
11
TNFEN11
CKS11 CCS11
Channel 1
MAS
STS112 STS111 STS110 CIS111 CIS110 MD113 MD112 MD111 MD110
TER11
Timer mode register 11 (TMR11)
TO12
TI12
Channel 2
INTTM12
Channel 3
INTTM13
TO13
TI13
Remark
For the channels 0 to 3 of 78K0R/LF3 and 78K0R/LG3, the timer I/O pins (TI10/TO10 to TI13/TO13) are not
mounted.
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(1) Timer/counter register mn (TCRmn)
TCRmn is a 16-bit read-only register and is used to count clocks.
The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock.
Whether the counter is incremented or decremented depends on the operation mode that is selected by the
MDmn3 to MDmn0 bits of TMRmn.
Figure 6-3. Format of Timer/Counter Register mn (TCRmn)
Address: F0180H, F0181H (TCR00) to F018EH, F018FH (TCR07)
After reset: FFFFH
R
F01C0H, F01C1H (TCR10) to F01C6H, F01C7H (TCR13)
F0181H (TCR00)
15
14
13
12
11
F0180H (TCR00)
10
9
8
7
6
5
4
3
2
1
0
TCRmn
The count value can be read by reading TCRmn.
The count value is set to FFFFH in the following cases.
• When the reset signal is generated
• When the TAU0EN bit (TAU0) and TAU1EN bit (TAU1) of peripheral enable register 0 (PER0) is cleared
The count value is cleared to 0000H in the following cases.
• When the start trigger is input in the capture mode
• When capturing has been completed in the capture mode
• When counting of the slave channel has been completed in the PWM output mode
• When counting of the master/slave channel has been completed in the one-shot pulse output mode
• When counting of the slave channel has been completed in the multiple PWM output mode
Caution
The count value is not captured to TDRmn even when TCRmn is read.
Remark
mn: Unit number + Channel number
mn = 00 to 07, 10 to 13
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The TCRmn register read value differs as follows according to operation mode changes and the operating status.
Table 6-2. TCRmn Register Read Value in Various Operation Modes
Operation Mode
TCRmn Register Read Value
Count Mode
Operation mode
change after reset
Operation mode
change after count
operation paused
(TTmn = 1)
Note
Operation restart
after count operation
paused (TTmn = 1)
During start trigger
wait status after one
count
Interval timer
mode
Count down
FFFFH
Undefined
Stop value
−
Capture mode
Count up
0000H
Undefined
Stop value
−
Event counter
mode
Count down
FFFFH
Undefined
Stop value
−
One-count mode
Count down
FFFFH
Undefined
Stop value
FFFFH
Capture & onecount mode
Count up
0000H
Undefined
Stop value
Capture value of
TDRmn register + 1
Note The read values of the TCRmn register when TSmn has been set to "1" while TEmn = 0 are shown. The read value
is held in the TCRmn register until the count operation starts.
Remark
mn: Unit number + Channel number
mn = 00 to 07, 10 to 13
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(2) Timer data register mn (TDRmn)
This is a 16-bit register from which a capture function and a compare function can be selected.
The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0
bits of TMRmn.
The value of TDRmn can be changed at any time.
This register can be read or written in 16-bit units.
Reset signal generation clears this register to 0000H.
Figure 6-4. Format of Timer Data Register mn (TDRmn)
Address: FFF18H, FFF19H (TDR00), FFF1AH, FFF1BH (TDR01),
After reset: 0000H
R/W
FFF64H, FFF65H (TDR02) to FFF6EH, FFF6FH (TDR07)
FFF70H, FFF71H (TDR10) to FFF76H, FFF77H (TDR13)
FFF19H (TDR00)
15
14
13
12
11
FFF18H (TDR00)
10
9
8
7
6
5
4
3
2
1
0
TDRmn
(i) When TDRmn is used as compare register
Counting down is started from the value set to TDRmn. When the count value reaches 0000H, an interrupt
signal (INTTMmn) is generated. TDRmn holds its value until it is rewritten.
Caution
TDRmn does not perform a capture operation even if a capture trigger is input, when it is set
to the compare function.
(ii) When TDRpq is used as capture register
The count value of TCRpq is captured to TDRpq when the capture trigger is input.
A valid edge of the TIpq pin can be selected as the capture trigger. This selection is made by TMRpq.
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided
with timer I/O pins)
78K0R/LF3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
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6.3 Registers Controlling Timer Array Unit
Timer array unit is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• Timer clock select register m (TPSm)
• Timer mode register mn (TMRmn)
• Timer status register pq (TSRpq)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer input select registers 0, 1 (TIS0, TIS1)
• Timer output enable register p (TOEp)
• Timer output register p (TOp)
• Timer output level register p (TOLp)
• Timer output mode register p (TOMp)
• Input switch control register (ISC)
• Noise filter enable registers 1, 2 (NFEN1, NFEN2)
• Port mode registers 1, 3, 5, 8 (PM1, PM3, PM5, PM8)
• Port registers1, 3, 5, 8 (P1, P3, P5, P8)
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3:
m = 0, 1, mn = 00 to 07, 10 to 13, p = 0, pq = 00 to 04, 07
78K0R/LG3:
m = 0, 1, mn = 00 to 07, 10 to 13, p = 0, pq = 00 to 07
78K0R/LH3:
m = 0, 1, mn = 00 to 07, 10 to 13, p = 0, 1, pq = 00 to 07, 10 to 13
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(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that
is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit 0 is used, be sure to set bit 0 (TAU0EN) of this register to 1.
When the timer array unit 1 is used, be sure to set bit 1 (TAU1EN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution
When setting the timer array unit, be sure to set TAUmEN to 1 first. If TAUmEN = 0, writing to a
control register of the timer array unit is ignored, and all read values are default values.
Figure 6-5. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
Symbol
After reset: 00H
PER0
RTCEN
R/W
DACEN
ADCEN
TAUmEN
0
IICAEN
Note
SAU1EN
SAU0EN
TAU1EN
TAU0EN
Control of timer array unit m input clock
Stops supply of input clock.
• SFR used by the timer array unit m cannot be written.
• The timer array unit m is in the reset status.
1
Supplies input clock.
• SFR used by the timer array unit m can be read/written.
Note 78K0R/LG3, 78K0R/LH3 only
(2) Timer clock select register m (TPSm)
TPSm is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly
supplied to each channel. CKm1 is selected by bits 7 to 4 of TPSm, and CKm0 is selected by bits 3 to 0.
Rewriting of TPSm during timer operation is possible only in the following cases.
Rewriting of PRSm00 to PRSm03 bits: Possible only when all the channels set to CKSmn = 0 are in the operation
stopped state (TEmn = 0)
Rewriting of PRSm10 to PRSm13 bits: Possible only when all the channels set to CKSmn = 1 are in the operation
stopped state (TEmn = 0)
TPSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TPSm can be set with an 8-bit memory manipulation instruction with TPSmL.
Reset signal generation clears this register to 0000H.
Remark
mn: Unit number + Channel number
m = 0, 1, mn = 00 to 07, 10 to 13
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Figure 6-6. Format of Timer Clock Select Register m (TPSm)
Address: F01B6H, F01B7H (TPS0)
After reset: 0000H
R/W
F01DEH, F01DFH (TPS1)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TPSm
0
0
0
0
0
0
0
0
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
m13
m12
m11
m10
m03
m02
m01
m00
Selection of operation clock (CKmk)
PRS
PRS
PRS
PRS
mk3
mk2
mk1
mk0
0
0
0
0
fCLK
0
0
0
1
fCLK/2
0
0
0
0
0
1
1
1
0
0
1
0
fCLK = 2 MHz
fCLK = 5 MHz
Notes 1,2
fCLK = 10 MHz
fCLK = 20 MHz
2 MHz
5 MHz
10 MHz
20 MHz
1 MHz
2.5 MHz
5 MHz
10 MHz
fCLK/2
2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
fCLK/2
3
250 kHz
625 kHz
1.25 MHz
2.5 MHz
fCLK/2
4
125 kHz
312.5 kHz
625 kHz
1.25 MHz
0
1
0
1
fCLK/2
5
62.5 kHz
156.2 kHz
312.5 kHz
625 kHz
0
1
1
0
fCLK/2
6
31.25 kHz
78.1 kHz
156.2 kHz
312.5 kHz
fCLK/2
7
15.62 kHz
39.1 kHz
78.1 kHz
156.2 kHz
fCLK/2
8
7.81 kHz
19.5 kHz
39.1 kHz
78.1 kHz
fCLK/2
9
3.91 kHz
9.76 kHz
19.5 kHz
39.1 kHz
fCLK/2
10
1.95 kHz
4.88 kHz
9.76 kHz
19.5 kHz
fCLK/2
11
976 Hz
2.44 kHz
4.88 kHz
9.76 kHz
fCLK/2
12
488 Hz
1.22 kHz
2.44 kHz
4.88 kHz
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
fCLK/2
13
244 Hz
610 Hz
1.22 kHz
2.44 kHz
1
1
1
0
fCLK/2
14
122 Hz
305 Hz
610 Hz
1.22 kHz
fCLK/2
15
61 Hz
153 Hz
305 Hz
610 Hz
1
1
1
1
Notes 1. When changing the clock selected for fCLK (by changing the system clock control register (CKC) value),
stop the timer array unit (TT0 = 00FFH, TT1 = 000FH).
2. Only in the case of SDIV=0, CCSmn=1 and TISmn=1, continuously use of TAUm is allowed, even when
changing CPU clock. However, the following limitation is existing.
• When changing CPU clock, source clock decrease/increase occurs as follows.
Main clock → Subsystem clock (CSS = 0→1): −1 clock
Subsystem clock → Main clock (CSS = 1→0): +1 clock
Caution
Be sure to clear bits 15 to 8 to “0”.
Remarks 1. fCLK: CPU/peripheral hardware clock frequency
2. k = 0, 1
3. mn: Unit number + Channel number
m = 0, 1, mn = 00 to 07, 10 to 13
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(3) Timer mode register mn (TMRmn)
TMRmn sets an operation mode of channel n of timer array unit m. It is used to select an operation clock (MCK), a
count clock, whether the timer operates as the master or a slave, a start trigger and a capture trigger, the valid
edge of the timer input, and an operation mode (interval, capture, event counter, one-count, or capture & onecount).
Rewriting TMRmn is prohibited when the register is in operation (when TEm = 1). However, bits 7 and 6 (CISmn1,
CISmn0) can be rewritten even while the register is operating with some functions (when TEm = 1) (for details, see
6.7 Operation of Timer Array Unit as Independent Channel and 6.8 Operation of Plural Channels of Timer
Array Unit).
TMRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 6-7. Format of Timer Mode Register mn (TMRmn) (1/4)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
After reset: 0000H
R/W
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
Symbol
15
14
13
12
11
10
9
8
TMRmn
CKS
0
0
CCS
MAST
STS
STS
STS
mn
ERmn
mn2
mn1
mn0
mn
CKS
7
6
5
4
CIS
CIS
0
0
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
Selection of operation clock (MCK) of channel n
mn
0
Operation clock CKm0 set by TPSm register
1
Operation clock CKm1 set by TPSm register
Operation clock MCK is used by the edge detector. A count clock (TCLK) and a sampling clock are generated
depending on the setting of the CCSmn bit.
CCS
Selection of count clock (TCLK) of channel n
mn
0
1
Operation clock MCK specified by CKSmn bit
Valid edge of input signal input from TIpq pin, fSUB/2, fSUB/4, or INTRTC1 (the timer input used with channel x
is selected by using TISm register).
Count clock TCLK is used for the timer/counter, output controller, and interrupt controller.
If CCSmn = 1, use the count clock under the following condition.
• The frequency of the operating clock selected by using CKSmn ≥ The frequency of the clock selected by using
TISmn × 2
Caution Be sure to clear bits 14, 13, 5, and 4 to “0”.
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
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Figure 6-7. Format of Timer Mode Register mn (TMRmn) (2/4)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
After reset: 0000H
R/W
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
Symbol
15
14
13
12
11
10
9
8
TMRmn
CKS
0
0
CCS
MAST
STS
STS
STS
mn
ERmn
mn2
mn1
mn0
mn
MAS
7
6
5
4
CIS
CIS
0
0
mn1
mn0
3
2
1
0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
Selection of slave/master of channel n
TER
mn
0
Operates as slave channel with combination operation function.
1
Operates as master channel with combination operation function.
Only the even channel can be set as a master channel (MASTERmn = 1).
Be sure to use the odd channel as a slave channel (MASTERmn = 0).
Clear MASTERmn to 0 for a channel that is used with the independent operation function.
STS
STS
STS
mn2
mn1
mn0
0
0
0
Only software trigger start is valid (other trigger sources are unselected).
0
0
1
Valid edge of TIpq pin input signal, fSUB/2, fSUB/4, or INTRTC1 is used as both the start trigger
Setting of start trigger or capture trigger of channel n
and capture trigger.
0
1
0
Both the edges of TIpq pin input signal, fSUB/2, fSUB/4, or INTRTC1 are used as a start trigger
and a capture trigger.
1
0
0
Interrupt signal of the master channel is used (when the channel is used as a slave channel
with the combination operation function).
Other than above
Setting prohibited
CIS
CIS
Selection of valid edge of TIpq pin input signal , fSUB/2, fSUB/4, or INTRTC1
mn1
mn0
(the timer input used with channel x is selected by using TISm register).
0
0
Falling edge
0
1
Rising edge
1
0
Both edges (when low-level width is measured)
Start trigger: Falling edge, Capture trigger: Rising edge
1
1
Both edges (when high-level width is measured)
Start trigger: Rising edge, Capture trigger: Falling edge
If both the edges are specified when the value of the STSmn2 to STSmn0 bits is other than 010B, set the CISmn1
to CISmn0 bits to 10B.
Caution Be sure to clear bits 14, 13, 5, and 4 to “0”.
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
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Figure 6-7. Format of Timer Mode Register mn (TMRmn) (3/4)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
After reset: 0000H
R/W
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
Symbol
15
14
13
12
11
10
9
8
TMRmn
CKS
0
0
CCS
MAST
STS
STS
STS
mn
ERmn
mn2
mn1
mn0
mn
7
6
5
4
CIS
CIS
0
0
mn1
mn0
3
2
1
MD
MD
MD
MD
mn3
mn2
mn1
mn0
MD
MD
MD
MD
mn3
mn2
mn1
mn0
0
0
0
1/0
Interval timer mode
Counting down
Possible
0
1
0
1/0
Capture mode
Counting up
Possible
0
1
1
0
Event counter mode
Counting down
Possible
1
0
0
1/0
One-count mode
Counting down
Impossible
1
1
0
0
Capture & one-count mode
Counting up
Possible
Other than above
Operation mode of channel n
0
Count operation of TCR
Independent operation
Setting prohibited
The operation of MDmn0 bits varies depending on each operation mode (see following table).
Cautions 1. Be sure to clear bits 14, 13, 5, and 4 to “0”.
2. Channel 5 of timer array unit 0 and channels 0 to 3 of timer array unit 1 of the 78K0R/LF3 can
be set only to the interval mode.
3. Channel 6 of timer array unit 0 of the 78K0R/LF3 can be set only to the interval mode and
one-count mode (when using as master).
4. Channels 0 to 3 of timer array unit 1 of the 78K0R/LG3 can be set only to the interval mode.
Remark
mn: Unit number + Channel number
mn = 00 to 07, 10 to 13
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Figure 6-7. Format of Timer Mode Register mn (TMRmn) (4/4)
Operation mode
MD
(Value set by the MDmn3 to MDmn1 bits
mn0
Setting of starting counting and interrupt
(see table above))
• Interval timer mode
0
Timer interrupt is not generated when counting is started
(timer output does not change, either).
(0, 0, 0)
• Capture mode
1
(0, 1, 0)
Timer interrupt is generated when counting is started
(timer output also changes).
• Event counter mode
0
Timer interrupt is not generated when counting is started
(timer output does not change, either).
(0, 1, 1)
• One-count mode
0
Start trigger is invalid during counting operation.
1
Start trigger is valid during counting operation
At that time, interrupt is not generated, either.
(1, 0, 0)
Note
.
At that time, interrupt is also generated.
• Capture & one-count mode
0
Timer interrupt is not generated when counting is started
(timer output does not change, either).
(1, 1, 0)
Start trigger is invalid during counting operation.
At that time interrupt is not generated, either.
Other than above
Setting prohibited
Note If the start trigger (TSmn = 1) is issued during operation, the counter is cleared, an interrupt is
generated, and recounting is started.
Remark
mn: Unit number + Channel number
mn = 00 to 07, 10 to 13
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(4) Timer status register pq (TSRpq)
TSRpq indicates the overflow status of the counter of channel n.
TSRpq is valid only in the capture mode (MDpq3 to MDpq1 = 010B) and capture & one-count mode (MDpq3 to
MDpq1 = 110B). It will not be set in any other mode. See Table 6-3 for the operation of the OVFpq bit in each
operation mode and set/clear conditions.
TSRpq can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of TSRpq can be set with an 8-bit memory manipulation instruction with TSRpqL.
Reset signal generation clears this register to 0000H.
Figure 6-8. Format of Timer Status Register pq (TSRpq)
Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07)
After reset: 0000H
R
F01D0H, F01D1H (TSR10) to F01D6H, F01D7H (TSR13)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TSRpq
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OVF
pq
OVF
Counter overflow status of channel q
pq
0
Overflow does not occur.
1
Overflow occurs.
When OVFpq = 1, this flag is cleared (OVFpq = 0) when the next value is captured without overflow.
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
Table 6-3. OVFpq Bit Operation and Set/Clear Conditions in Each Operation Mode
Timer operation mode
OVFpq
Set/clear conditions
• Capture mode
clear
When no overflow has occurred upon capturing
• Capture & one-count mode
set
When an overflow has occurred upon capturing
• Interval timer mode
clear
• Event counter mode
• One-count mode
Remark
−
(Use prohibited, not set/cleared)
set
The OVFpq bit does not change immediately after the counter has overflowed, but changes upon the
subsequent capture.
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(5) Timer channel enable status register m (TEm)
TEm is used to enable or stop the timer operation of each channel.
When a bit of timer channel start register m (TSm) is set to 1, the corresponding bit of this register is set to 1.
When a bit of timer channel stop register m (TTm) is set to 1, the corresponding bit of this register is cleared to 0.
TEm can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of TEm can be set with a 1-bit or 8-bit memory manipulation instruction with TEmL.
Reset signal generation clears this register to 0000H.
Figure 6-9. Format of Timer Channel Enable Status Register m (TEm)
Address: F01B0H, F01B1H
After reset: 0000H
R
Symbol
15
14
13
12
11
10
9
8
TE0
0
0
0
0
0
0
0
0
Address: F01D8H, F01D9H
After reset: 0000H
7
6
5
4
2
1
0
TE07 TE06 TE05 TE04 TE03 TE02 TE01 TE00
R
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
TE1
0
0
0
0
0
0
0
0
0
0
0
0
TE
3
3
2
1
0
TE13 TE12 TE11 TE10
Indication of operation enable/stop status of channel n
mn
0
Operation is stopped.
1
Operation is enabled.
Remark
mn: Unit number + Channel number
m = 0, 1, mn = 00 to 07, 10 to 13
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(6) Timer channel start register m (TSm)
TSm is a trigger register that is used to clear a timer counter (TCRmn) and start the counting operation of each
channel.
When a bit (TSmn) of this register is set to 1, the corresponding bit (TEmn) of timer channel enable status register
m (TEm) is set to 1. TSmn is a trigger bit and cleared immediately when TEmn = 1.
TSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TSm can be set with a 1-bit or 8-bit memory manipulation instruction with TSmL.
Reset signal generation clears this register to 0000H.
Figure 6-10. Format of Timer Channel Start Register m (TSm)
Address: F01B2H, F01B3H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
TS0
0
0
0
0
0
0
0
0
Address: F01DAH, F01DBH
After reset: 0000H
R/W
7
6
5
4
2
1
0
TS07 TS06 TS05 TS04 TS03 TS02 TS01 TS00
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
TS1
0
0
0
0
0
0
0
0
0
0
0
0
TSmn
3
3
2
1
0
TS13 TS12 TS11 TS10
Operation enable (start) trigger of channel n
0
No trigger operation
1
TEmn is set to 1 and the count operation becomes enabled.
The TCRmn count operation start in the count operation enabled state varies depending on each operation
mode (see Table 6-4).
Caution
Be sure to clear bits 15 to 8 of TS0 and bits 15 to 4 of TS1 to “0”.
Remarks 1. When the TSm register is read, 0 is always read.
2. mn: Unit number + Channel number
m = 0, 1, mn = 00 to 07, 10 to 13
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Table 6-4. Operations from Count Operation Enabled State to TCRmn Count Start
Timer operation mode
• Interval timer mode
Operation when TSmn = 1 is set
No operation is carried out from start trigger detection (TSmn=1) until count clock
generation.
The first count clock loads the value of TDRmn to TCRmn and the subsequent
count clock performs count down operation (see 6.3 (6) (a) Start timing in
interval timer mode).
• Event counter mode
Writing 1 to TSmn bit loads the value of TDRmn to TCRmn.
The subsequent count clock performs count down operation.
The external trigger detection selected by STSmn2 to STSmn0 bits in the
TMRmn register does not start count operation (see 6.3 (6) (b) Start timing in
event counter mode).
• Capture mode
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCRmn and the subsequent count clock
performs count up operation (see 6.3 (6) (c) Start timing in capture mode).
• One-count mode
When TEmn = 0, writing 1 to TSmn bit sets the start trigger wait state.
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of TDRmn to TCRmn and the subsequent
count clock performs count down operation (see 6.3 (6) (d) Start timing in onecount mode).
• Capture & one-count mode
When TEmn = 0, writing 1 to TSmn bit sets the start trigger wait state.
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCRmn and the subsequent count clock
performs count up operation (see 6.3 (6) (e) Start timing in capture & onecount mode).
Cautions 1. Channel 5 of timer array unit 0 and channels 0 to 3 of timer array unit 1 of the 78K0R/LF3 can
be set only to the interval mode.
2. Channel 6 of timer array unit 0 of the 78K0R/LF3 can be set only to the interval mode and
one-count mode (when using as master).
3. Channels 0 to 3 of timer array unit 1 of the 78K0R/LG3 can be set only to the interval mode.
(a) Start timing in interval timer mode
Writing 1 to TSmn sets TEmn = 1
The write data to TSmn is held until count clock generation.
TCRmn holds the initial value until count clock generation.
On generation of count clock, the “TDRmn value” is loaded to TCRmn and count starts.
Remark
mn: Unit number + Channel number
mn = 00 to 07, 10 to 13
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Figure 6-11. Start Timing (In Interval Timer Mode)
fCLK
TSmn (write)
TEmn
Count clock
TSmn (write) hold signal
Start trigger detection signal
Initial value
TCRmn
TDRmn value
INTTMmn
When MDmn0 = 1 is set
Caution In the first cycle operation of count clock after writing TSmn, an error at a maximum of one clock
is generated since count start delays until count clock has been generated. When the information
on count start timing is necessary, an interrupt can be generated at count start by setting MDmn0
= 1.
Remark
mn: Unit number + Channel number
mn = 00 to 07, 10 to 13
(b) Start timing in event counter mode
While TEpq is set to 0, TCRpq holds the initial value.
Writing 1 to TSpq sets 1 to TEpq.
As soon as 1 has been written to TSpq and 1 has been set to TEpq, the "TDRpq value" is loaded to
TCRpq to start counting.
After that, the TCRpq value is counted down according to the count clock.
Figure 6-12. Start Timing (In Event Counter Mode)
fCLK
TSpq (write)
TEpq
Count clock
TSpq (write) hold signal
Start trigger detection signal
TCRpq
Remark
Initial value
TDRpq value
TDRpq value-1
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
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(c) Start timing in capture mode
Writing 1 to TSpq sets TEpq = 1
The write data to TSpq is held until count clock generation.
TCRpq holds the initial value until count clock generation.
On generation of count clock, 0000H is loaded to TCRpq and count starts.
Figure 6-13. Start Timing (In Capture Mode)
fCLK
TSpq (write)
TEpq
Count clock
TSpq (write) hold signal
Start trigger detection signal
TCRpq
Initial value
0000H
INTTMpq
When MDpq0 = 1 is set
Caution In the first cycle operation of count clock after writing TSpq, an error at a maximum of one clock is
generated since count start delays until count clock has been generated. When the information
on count start timing is necessary, an interrupt can be generated at count start by setting MDpq0
= 1.
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
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(d) Start timing in one-count mode
Writing 1 to TSpq sets TEpq = 1
Enters the start trigger input wait status, and TCRpq holds the initial value.
On start trigger detection, the “TDRpq value” is loaded to TCRpq and count starts.
Figure 6-14. Start Timing (In One-count Mode)
fCLK
TSpq (write)
TEpq
TIN edge detection signal
Count clock Note
TSpq (write) hold signal
Start trigger detection signal
TCRpq
Initial value
TDRpq value
Start trigger input wait status
Note When the one-count mode is set, the operation clock (MCK) is selected as count clock (CCSpq = 0).
Caution
An input signal sampling error is generated since operation starts upon start trigger detection
(The error is one count clock when TIpq is used).
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07, 06 (only when used as the master)
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
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(e) Start timing in capture & one-count mode
Writing 1 to TSpq sets TEpq = 1
Enters the start trigger input wait status, and TCRpq holds the initial value.
On start trigger detection, 0000H is loaded to TCRpq and count starts.
Figure 6-15. Start Timing (In Capture & One-count Mode)
fCLK
TSpq (write)
TEpq
TIN edge detection signal
Count clock Note
TSpq (write) hold signal
Start trigger detection signal
Initial value
TCRpq
0000H
Start trigger input wait status
Note When the capture & one-count mode is set, the operation clock (MCK) is selected as count clock (CCSpq =
0).
Caution An input signal sampling error is generated since operation starts upon start trigger detection
(The error is one count clock when TIpq is used).
(7) Timer channel stop register m (TTm)
TTm is a trigger register that is used to clear a timer counter (TCRmn) and start the counting operation of each
channel.
When a bit (TTmn) of this register is set to 1, the corresponding bit (TEmn) of timer channel enable status register
0 (TEm) is cleared to 0. TTmn is a trigger bit and cleared to 0 immediately when TEmn = 0.
TTm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TTm can be set with a 1-bit or 8-bit memory manipulation instruction with TTmL.
Reset signal generation clears this register to 0000H.
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided
with timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
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Figure 6-16. Format of Timer Channel Stop Register m (TTm)
Address: F01B4H, F01B5H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
TT0
0
0
0
0
0
0
0
0
Address: F01DCH, F01DDH
After reset: 0000H
R/W
7
6
5
4
15
14
13
12
11
10
9
8
7
6
5
4
TT1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
3
2
1
0
TT13 TT12 TT11 TT10
Operation stop trigger of channel n
0
No trigger operation
1
Operation is stopped (stop trigger is generated).
Caution
2
TT07 TT06 TT05 TT04 TT03 TT02 TT01 TT00
Symbol
TTmn
3
Be sure to clear bits 15 to 8 of TT0 and bits 15 to 4 of TT1 to “0”.
Remarks 1. When the TTm register is read, 0 is always read.
2. mn: Unit number + Channel number
m = 0, 1, mn = 00 to 07, 10 to 13
(8) Timer input select registers 0, 1 (TIS0, TIS1)
TIS0 and TIS1 use can be set to the input signal of a timer input pin (TIpq), half the frequency of the subsystem
clock (fSUB/2), one fourth the frequency of the subsystem clock (fSUB/4), or an RTC interval interrupt (INTRTCI) as
the timer input. The timer input can be selected for each channel.
TIS0 and TIS1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
Figure 6-17. Format of Timer Input Select Registers 0, 1 (TIS0, TIS1) (1/2)
• 78K0R/LF3
Address: FFF3EH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
TIS0
TIS07
0
0
TIS04
TIS03
TIS02
TIS01
TIS00
Address: FFF4EH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
TIS1
0
0
RTCIS04
RTCIS00
0
0
0
0
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Figure 6-17. Format of Timer Input Select Registers 0, 1 (TIS0, TIS1) (2/2)
• 78K0R/LG3
Address: FFF3EH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
TIS0
TIS07
TIS06
TIS05
TIS04
TIS03
TIS02
TIS01
TIS00
Address: FFF4EH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
TIS1
0
0
RTCIS04
RTCIS00
0
0
0
0
• 78K0R/LH3
Address: FFF3EH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
TIS0
TIS07
TIS06
TIS05
TIS04
TIS03
TIS02
TIS01
TIS00
Address: FFF4EH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
TIS1
0
0
RTCIS04
RTCIS00
TIS13
TIS12
TIS11
TIS10
• Channels 1 to 3 and 5 to 7 of timer array unit 0 and channels 0 to 3 of timer array unit 1
TISpq
SDIV
Selection of Timer input used with channel (pq = 01, 02, 03, 05, 06, 07, 10, 11, 12, 13)
0
×
Input signal of timer input pin (TIpq)
1
0
fSUB/2
1
fSUB/4
• Channels 0 and 4 of timer array unit 0
TISpq
RTCISpq
SDIV
0
×
×
Input signal of timer input pin (TIpq)
1
0
0
fSUB/2
1
fSUB/4
0
RTC Interval interrupt (INTRTCI)
1
Setting prohibited
1
Selection of Timer input used with channel (pq = 00, 04)
Caution When the LIN-bus communication function is used, select the input signal of the RxD3 pin by
setting ISC1 to 1 and TIS07 = 0.
Remarks 1. pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
2. ×: don’t care
3. fSUB: Subsystem select clock
4. SDIV: Bit 3 of the system clock control register (CKC)
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(9) Timer output enable register p (TOEp)
TOEp is used to enable or disable timer output of each channel.
Channel q for which timer output has been enabled becomes unable to rewrite the value of the TOpq bit of the timer
output register (TOp) described later by software, and the value reflecting the setting of the timer output function
through the count operation is output from the timer output pin (TOpq).
TOEp can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TOEp can be set with a 1-bit or 8-bit memory manipulation instruction with TOEpL.
Reset signal generation clears this register to 0000H.
Figure 6-18. Format of Timer Output Enable Register p (TOEp)
• 78K0R/LF3
Address: F01BAH, F01BBH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOE0
0
0
0
0
0
0
0
0
TOE
0
0
TOE
TOE
TOE
TOE
TOE
04
03
02
01
00
07
• 78K0R/LG3
Address: F01BAH, F01BBH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOE0
0
0
0
0
0
0
0
0
TOE
TOE
TOE
TOE
TOE
TOE
TOE
TOE
07
06
05
04
03
02
01
00
• 78K0R/LH3
Address: F01BAH, F01BBH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOE0
0
0
0
0
0
0
0
0
TOE
TOE
TOE
TOE
TOE
TOE
TOE
TOE
07
06
05
04
03
02
01
00
Address: F01E2H, F01E3H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOE1
0
0
0
0
0
0
0
0
0
0
0
0
TOE
TOE
TOE
TOE
13
12
11
10
TOE
Timer output enable/disable of channel q
pq
0
The TOpq operation stopped by count operation (timer channel output bit).
Writing to the TOpq bit is enabled.
The TOpq pin functions as data output, and it outputs the level set to the TOpq bit.
The output level of the TOpq pin can be manipulated by software.
1
The TOpq operation enabled by count operation (timer channel output bit).
Writing to the TOpq bit is disabled (writing is ignored).
The TOpq pin functions as timer output, and the TOEpq is set or reset depending on the timer operation.
The TOpq pin outputs the square-wave or PWM depending on the timer operation.
(Caution and Remark are given on the next page.)
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Cautions 1. For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOE0 to “0”.
2. For 78K0R/LG3, be sure to clear bits 15 to 8 of TOE0 to “0”.
3. For 78K0R/LH3, be sure to clear bit 15 to 8 of TOE0, bits 15 to 4 of TOE1 to “0”.
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
(10) Timer output register p (TOp)
TOp is a buffer register of timer output of each channel.
The value of each bit in this register is output from the timer output pin (TOpq) of each channel.
This register can be rewritten by software only when timer output is disabled (TOEpq = 0). When timer output is
enabled (TOEpq = 1), rewriting this register by software is ignored, and the value is changed only by the timer
operation.
To use the P30/TO00, P32/TO01, P12/TO02, P31/TO03, P13/TO04, P16/TO05, P34/TO06, P33/TO07, P84/TO10,
P85/TO11, P86/TO12, or P87/TO13 pin as a port function pin, set the corresponding TOpq bit to “0”.
TOp can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TOp can be set with an 8-bit memory manipulation instruction with TOpL.
Reset signal generation clears this register to 0000H.
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Figure 6-19. Format of Timer Output Register p (TOp)
• 78K0R/LF3
Address: F01B8H, F01B9H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TO0
0
0
0
0
0
0
0
0
TO0
0
0
TO0
TO0
TO0
TO0
TO0
4
3
2
1
0
7
• 78K0R/LG3
Address: F01B8H, F01B9H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TO0
0
0
0
0
0
0
0
0
TO0
TO0
TO0
TO0
TO0
TO0
TO0
TO0
7
6
5
4
3
2
1
0
• 78K0R/LH3
Address: F01B8H, F01B9H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TO0
0
0
0
0
0
0
0
0
TO0
TO0
TO0
TO0
TO0
TO0
TO0
TO0
7
6
5
4
3
2
1
0
Address: F01E0H, F01E1H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TO1
0
0
0
0
0
0
0
0
0
0
0
0
TO1
TO1
TO1
TO1
3
2
1
0
TO
Timer output of channel q
pq
0
Timer output value is “0”.
1
Timer output value is “1”.
Cautions 1. For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TO0 to “0”.
2. For 78K0R/LG3, be sure to clear bits 15 to 8 of TO0 to “0”.
3.
Remark
For 78K0R/LH3, be sure to clear bit 15 to 8 of TO0, bits 15 to 4 of TO1 to “0”.
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
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(11) Timer output level register p (TOLp)
TOLp is a register that controls the timer output level of each channel.
The setting of the inverted output of channel q by this register is reflected at the timing of set or reset of the timer
output signal while the timer output is enabled (TOEpq = 1) in the combination operation mode (TOMpq = 1). In
the toggle mode (TOMpq = 0), this register setting is invalid.
TOLp can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TOLp can be set with an 8-bit memory manipulation instruction with TOLpL.
Reset signal generation clears this register to 0000H.
Figure 6-20. Format of Timer Output Level Register p (TOLp)
• 78K0R/LF3
Address: F01BCH, F01BDH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOL0
0
0
0
0
0
0
0
0
TOL
0
0
TOL
TOL
TOL
TOL
TOL
04
03
02
01
00
07
• 78K0R/LG3
Address: F01BCH, F01BDH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOL0
0
0
0
0
0
0
0
0
TOL
TOL
TOL
TOL
TOL
TOL
TOL
TOL
07
06
05
04
03
02
01
00
• 78K0R/LH3
Address: F01BCH, F01BDH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOL0
0
0
0
0
0
0
0
0
TOL
TOL
TOL
TOL
TOL
TOL
TOL
TOL
07
06
05
04
03
02
01
00
Address: F01E4H, F01E5H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOL1
0
0
0
0
0
0
0
0
0
0
0
0
TOL
TOL
TOL
TOL
13
12
11
10
TOLpq
Control of timer output level of channel q
0
Positive logic output (active-high)
1
Inverted output (active-low)
Cautions 1. For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOL0 to “0”.
2. For 78K0R/LG3, be sure to clear bits 15 to 8 of TOL0 to “0”.
3.
For 78K0R/LH3, be sure to clear bit 15 to 8 of TOL0, bits 15 to 4 of TOL1 to “0”.
Remarks 1. If the value of this register is rewritten during timer operation, the timer output is inverted when the
timer output signal changes next, instead of immediately after the register value is rewritten.
2. pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
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(12) Timer output mode register p (TOMp)
TOMp is used to control the timer output mode of each channel.
When a channel is used for the combination operation function (PWM output, one-shot pulse output, or multiple
PWM output), set the corresponding bit of the slave channel to 1.
The setting of each channel q by this register is reflected at the timing when the timer output signal is set or reset
while the timer output is enabled (TOEpq = 1).
TOMp can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TOMp can be set with an 8-bit memory manipulation instruction with TOMpL.
Reset signal generation clears this register to 0000H.
Figure 6-21. Format of Timer Output Mode Register p (TOMp)
• 78K0R/LF3
Address: F01BEH, F01BFH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOM0
0
0
0
0
0
0
0
0
TOM
0
0
TOM
TOM
TOM
TOM
TOM
04
03
02
01
00
07
• 78K0R/LG3
Address: F01BEH, F01BFH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOM0
0
0
0
0
0
0
0
0
TOM
TOM
TOM
TOM
TOM
TOM
TOM
TOM
07
06
05
04
03
02
01
00
• 78K0R/LH3
Address: F01BEH, F01BFH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOM0
0
0
0
0
0
0
0
0
TOM
TOM
TOM
TOM
TOM
TOM
TOM
TOM
07
06
05
04
03
02
01
00
Address: F01E6H, F01E7H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOM1
0
0
0
0
0
0
0
0
0
0
0
0
TOM
TOM
TOM
TOM
13
12
11
10
TOM
Control of timer output mode of channel q
pq
0
Toggle mode (to produce toggle output by timer interrupt request signal (INTTMpq))
1
Combination operation mode (set by the timer interrupt request signal (INITTMpq) of the master channel,
and reset by the timer interrupt request signal (INITTMpr) of the slave channel)
Cautions 1. For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOM0 to “0”.
2. For 78K0R/LG3, be sure to clear bits 15 to 8 of TOM0 to “0”.
3. For 78K0R/LH3, be sure to clear bit 15 to 8 of TOM0, bits 15 to 4 of TOM1 to “0”.
(Remark is listed on the next page.)
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Remark
CHAPTER 6 TIMER ARRAY UNIT
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3:
• p = 0, q = 0 to 4, 7 (q = 0, 2, 4 for master channel)
q < r ≤ 7 (where r is a consecutive integer greater than q)
78K0R/LG3:
• p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel)
q < r ≤ 7 (where r is a consecutive integer greater than q)
78K0R/LH3:
• p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel)
q < r ≤ 7 (where r is a consecutive integer greater than q)
• p = 1, q = 0 to 3 (q = 0, 2 for master channel)
q < r ≤ 3 (where r is a consecutive integer greater than q)
(13) Input switch control register (ISC)
ISC is used to implement LIN-bus communication operation with channel 7 of timer array unit 0 in association with
serial array unit 1.
When bit 1 of this register is set to 1, the input signal of the serial data input pin (RxD3) is selected as a timer input
signal.
ISC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-22. Format of Input Switch Control Register (ISC)
Address: FFF3CH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ISC
0
0
0
ISC4
ISC3
ISC2
ISC1
ISC0
ISC1
Switching channel 7 input of timer array unit
0
Uses the input signal of the TI07 pin as a timer input (normal operation).
1
Input signal of RXD3 pin is used as timer input (wakeup signal detection).
Caution Be sure to clear bits 5 to 7 to “0”.
Remarks 1.
When the LIN-bus communication function is used, select the input signal of the RxD3 pin by setting
ISC1 to 1.
2.
Bits 0 and 2 to 4 of ISC are not used with TAU0.
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(14) Noise filter enable registers 1, 2 (NFEN1, NFEN2)
NFEN1 and NFEN2 are used to set whether the noise filter can be used for the timer input signal to each
channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the
CPU/peripheral hardware clock (fCLK). When the noise filter is OFF, only synchronization is performed with the
CPU/peripheral hardware clock (fCLK).
NFEN1, NFEN2 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
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Figure 6-23. Format of Noise Filter Enable Register 1 (NFEN1) (1/2)
• 78K0R/LF3
Address: F0061H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
NFEN1
TNFEN07
0
0
TNFEN04
TNFEN03
TNFEN02
TNFEN01
TNFEN00
• 78K0R/LG3, 78K0R/LH3
Address: F0061H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
NFEN1
TNFEN07
TNFEN06
TNFEN05
TNFEN04
TNFEN03
TNFEN02
TNFEN01
TNFEN00
Enable/disable using noise filter of TI07/TO07/P33/INTP3 pin or RxD3/P50/SEGz pin
Note
input signal
(78K0R/LF3: z = 30, 78K0R/LG3: z = 39, 78K0R/LH3: z = 53)
TNFEN07
0
Noise filter OFF
1
Noise filter ON
TNFEN06
Enable/disable using noise filter of TI06/TO06/P34/INTP8 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN05
Enable/disable using noise filter of TI05/TO05/P16/INTP10 pin input signal
0
Noise filter OFF
1
Noise filter ON
Enable/disable using noise filter of TI04/P53/SEGz pin input signal
TNFEN04
(78K0R/LF3: z = 27, 78K0R/LG3: z = 36, 78K0R/LH3: z = 50)
0
Noise filter OFF
1
Noise filter ON
TNFEN03
Enable/disable using noise filter of TI03/TO03/P30/RTC1HZ/INTP1 pin input signal
0
Noise filter OFF
1
Noise filter ON
Enable/disable using noise filter of TI02/P52/SEGz pin input signal
TNFEN02
(78K0R/LF3: z = 28, 78K0R/LG3: z = 37, 78K0R/LH3: z = 51)
0
Noise filter OFF
1
Noise filter ON
Note The applicable pin can be switched by setting ISC1 of the ISC register.
ISC1 = 0: Whether or not to use the noise filter of TI07 pin can be selected.
ISC1 = 1: Whether or not to use the noise filter of RxD3 pin can be selected.
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Figure 6-23. Format of Noise Filter Enable Register 1 (NFEN1) (2/2)
TNFEN01
Enable/disable using noise filter of TI01/TO01/P32/INTP5/PCLBUZ0 pin input signal
0
Noise filter OFF
1
Noise filter ON
Enable/disable using noise filter of TI00/TO03/P31/RTCDIV/RTCCL/PCLBUZ1/INTP2 pin
TNFEN00
input signal
0
Noise filter OFF
1
Noise filter ON
Figure 6-24. Format of Noise Filter Enable Register 2 (NFEN2)
Address: F0061H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
NFEN1
0
0
0
0
TNFEN13
TNFEN12
TNFEN11
TNFEN10
TNFEN13
Enable/disable using noise filter of TI13/TO13/P87 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN12
Enable/disable using noise filter of TI12/TO12/P86 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN11
Enable/disable using noise filter of TI11/TO11/P85 pin input signal
0
Noise filter OFF
1
Noise filter ON
TNFEN10
Enable/disable using noise filter of TI10/TO10/P84 pin input signal
0
Noise filter OFF
1
Noise filter ON
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(15) Port mode registers 1, 3, 5, 8 (PM1, PM3, PM5, PM8)
These registers set input/output of ports 1, 3, 5, and 8 in 1-bit units.
When using the P30/TO00/TI03/RTC1HZ/INTP1, P32/TO01/TI01/INTP5/PCLBUZ0, P12/TO02/SO02/TxD2,
P31/TO03/TI00/RTCDIV/RTCCL/PCLBUZ1/INTP2, P13/TO04/SO10/TxD1, P16/TO05/TI05/INTP10,
P34/TO06/TI06/INTP8, P33/TO07/TI07/INTP3, P84/TO10/TI10, P85/TO11/TI11, P86/TO12/TI12, and
P87/TO13/TI13 pins for timer output, set PM30, PM32, PM12, PM31, PM13, PM16, PM34, PM33, and PM84 to
PM87 and the output latches of P30, P32, P12, P31, P13, P16, P34, P33, and P84 to P87 to 0.
When using the P31/TI00/TO03/RTCDIV/RTCCL/PCLBUZ1/INTP2, P32/TI01/TO01/INTP5/PCLBUZ0,
P52/TI02/SEGz (78K0R/LF3: z = 28, 78K0R/LG3: z = 37, 78K0R/LH3: z = 51), P30/TI03/TO00/RTC1HZ/INTP1,
P53/TI04/SEGz (78K0R/LF3: z = 27, 78K0R/LG3: z = 36, 78K0R/LH3: z = 50), P16/TI05/TO05/INTP10,
P34/TI06/TO06/INTP8, P33/TI07/TO07/INTP3, P84/TI10/TO10, P85/TI11/TO11, P86/TI12/TO12, and
P87/TI13/TO13 pins for timer input, set PM31, PM32, PM52, PM30, PM53, PM16, PM34 PM33, and PM84 to
PM87 to 1. At this time, the output latches of P31, P32, P52, P30, P53, P16, P34, P33, and P84 to P87 may be 0
or 1.
PM1, PM3, PM5, and PM8 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
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Figure 6-25. Format of Port Mode Registers 1, 3, 5, 8 (PM1, PM3, PM5, PM8)
• 78K0R/LF3
Address: FFF21H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM1
1
1
PM15
PM14
PM13
PM12
PM11
PM10
Address: FFF23H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM3
1
1
1
1
PM33
PM32
PM31
PM30
Address: FFF25H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
• 78K0R/LG3
Address: FFF21H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM1
1
PM16
PM15
PM14
PM13
PM12
PM11
PM10
Address: FFF23H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM3
1
1
1
PM34
PM33
PM32
PM31
PM30
Address: FFF25H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
• 78K0R/LH3
Address: FFF21H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
Address: FFF23H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM3
1
1
1
PM34
PM33
PM32
PM31
PM30
Address: FFF25H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
Address: FFF28H
After reset: FEH
R/W
Symbol
7
6
5
4
3
2
1
0
PM8
PM87
PM86
PM85
PM84
PM83
PM82
PM81
PM80
PMmn
Pmn pin I/O mode selection (m = 1, 3, 5, 8; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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6.4 Channel Output (TOpq pin) Control
6.4.1 TOpq pin output circuit configuration
Figure 6-26. Output Circuit Configuration
TOp register
Controller
Interrupt signal of the master channel
(INTTMpq)
Interrupt signal of the slave channel
(INTTMpr)
Set
TOpq pin
Reset/toggle
TOLpq
TOMpq
Internal bus
TOEpq
TOpq write signal
The following describes the TOpq pin output circuit.
When TOMpq = 0 (toggle mode), the set value of the TOLp register is ignored and only INTTMpr (slave
channel timer interrupt) is transmitted to the TOp register.
When TOMpq = 1 (combination operation mode), both INTTMpq (master channel timer interrupt) and
INTTMpr (slave channel timer interrupt) are transmitted to the TOp register.
At this time, the TOLp register becomes valid and the signals are controlled as follows:
When TOLpq = 0: Forward operation (INTTMpq → set, INTTMpr → reset)
When TOLpq = 1: Reverse operation (INTTMpq → reset, INTTMpr → set)
When INTTMpq and INTTMpr are simultaneously generated, (0% output of PWM), INTTMpr (reset signal)
takes priority, and INTTMpq (set signal) is masked.
When TOEpq = 1, INTTMpq (master channel timer interrupt) and INTTMpr (slave channel timer interrupt) are
transmitted to the TOpq register. Writing to the TOp register (TOpq write signal) becomes invalid.
When TOEpq = 1, the TOpq pin output never changes with signals other than interrupt signals.
To initialize the TOpq pin output level, it is necessary to set TOEpq = 0 and to write a value to TOpq.
When TOEpq = 0, writing to TOpq bit to the target channel (TOpq signal) becomes valid. When TOEpq = 0,
neither INTTMpq (master channel timer interrupt) nor INTTMpr (slave channel timer interrupt) is transmitted
to TOpq register.
The TOp register can always be read, and the TOpq pin output level can be checked.
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CHAPTER 6 TIMER ARRAY UNIT
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3:
• p = 0, q = 0 to 4, 7 (q = 0, 2, 4 for master channel)
q < r ≤ 7 (where r is a consecutive integer greater than q)
78K0R/LG3:
• p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel)
q < r ≤ 7 (where r is a consecutive integer greater than q)
78K0R/LH3:
• p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel)
q < r ≤ 7 (where r is a consecutive integer greater than q)
• p = 1, q = 0 to 3 (q = 0, 2 for master channel)
q < r ≤ 3 (where r is a consecutive integer greater than q)
6.4.2 TOpq Pin Output Setting
The following figure shows the procedure and status transition of TOpq out put pin from initial setting to timer operation
start.
Figure 6-27. Status Transition from Timer Output Setting to Operation Start
TCRpq
Undefined value (FFFFH after reset)
(Counter)
Hi-Z
Timer alternate-function pin
Timer output signal
TOpq
TOEpq
Write operation enabled period to TOpq
Set the TOMpq
Set the TOLpq
Write operation disabled period to TOpq
Set the TOpq Set the TOEpq Set the port to Timer operation start
output mode
The operation mode of timer output is set.
• TOMpq bit (0: Toggle mode, 1: Combination operation mode)
• TOLpq bit (0: Forward output, 1: Reverse output)
The timer output signal is set to the initial status by setting TOpq.
The timer output operation is enabled by writing 1 to TOEpq (writing to TOpq is disabled).
The port I/O setting is set to output (see 6.3 (15) Port mode registers 1, 3, 5, 8).
The timer operation is enabled (TSpq = 1).
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
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6.4.3 Cautions on Channel Output Operation
(1) Changing values set in registers TOp,TOEp,TOLp, and TOMp during timer operation
Since the timer operations (operations of TCRpq and TDRpq) are independent of the TOpq output circuit and
changing the values set in TOp, TOEp, TOLp, and TOMp does not affect the timer operation, the values can be
changed during timer operation. To output an expected waveform from the TOpq pin by timer operation, however,
set TOp, TOEp, TOLp, and TOMp to the values stated in the register setting example of each operation.
When the values set in TOEp, TOLp, and TOMp (except for TOp) are changed close to the timer interrupt
(INTTMpq), the waveform output to the TOpq pin may be different depending on whether the values are changed
immediately before or immediately after the timer interrupt (INTTMpq) signal generation timing.
(2) Default level of TOpq pin and output level after timer operation start
The following figure shows the TOpq pin output level transition when writing has been done in the state of TOEpq =
0 before port output is enabled and TOEpq = 1 is set after changing the default level.
(a) When operation starts with TOMpq = 0 setting (toggle output)
The setting of TOLpq is invalid when TOMpq = 0. When the timer operation starts after setting the default level,
the toggle signal is generated and the output level of TOpq pin is reversed.
Figure 6-28. TOpq Pin Output Status at Toggle Output (TOMpq = 0)
TOEpq
Default level, TOLpq setting
TOpq = 0, TOLpq = 0
Hi-Z
TOpq = 1, TOLpq = 0
Hi-Z
TOpq = 0, TOLpq = 1
(Same output waveform as TOLpq = 0)
Hi-Z
TOpq = 1, TOLpq = 1
(Same output waveform as TOLpq = 0)
Hi-Z
Dependent on TOpq setting
Independent of TOLpq setting
Port output is enabled
Toggle
Toggle
Toggle
Toggle
Toggle
TOpq pin transition
Remarks 1. Toggle:
Reverse TOpq pin output status
2. pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
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(b) When operation starts with TOMpq = 1 setting (Combination operation mode (PWM output))
When TOMpq = 1, the active level is determined by TOLpq setting.
Figure 6-29. TOpq Pin Output Status at PWM Output (TOMpq = 1)
TOEpq
Default level, TOLpq setting
TOpq = 0, TOLpq = 0
(Active high)
Hi-Z
TOpq = 1, TOLpq = 0
(Active high)
Hi-Z
TOpq = 0, TOLpq = 1
(Active low)
Hi-Z
TOpq = 1, TOLpq = 1
(Active low)
Hi-Z
No change
Dependent on TOLpq setting
Dependent on TOpq setting
Port output is enabled
Set
Reset
Set
Reset
Set
TOpq pin transition
(3) Operation of TOpq pin in combination operation mode (TOMpq = 1)
(a) When TOLpq setting has been changed during timer operation
When the TOLpq setting has been changed during timer operation, the setting becomes valid at the generation
timing of TOpq change condition. Rewriting TOLpq does not change the output level of TOpq.
The following figure shows the operation when the value of TOLpq has been changed during timer operation
(TOMpq = 1).
Figure 6-30. Operation when TOLpq Has Been Changed during Timer Operation
Internal set signal
Internal reset signal
TOLpq
TOpq pin
TOpq does not change
Remarks 1. Set:
Reset:
Set/reset signals are inverted
The output signal of TOpq pin changes from inactive level to active level.
The output signal of TOpq pin changes from active level to inactive level.
2. pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
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(b) Set/reset timing
To realize 0%/100% output at PWM output, the TOpq pin/TOpq set timing at master channel timer interrupt
(INTTMpq) generation is delayed by 1 count clock by the slave channel timer interrupt (INTTMqr).
If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Figure 6-31 shows the set/reset operating statuses where the master/slave channels are set as follows.
• Master channel: TOEpq = 1, TOMpq = 0, TOLpq = 0
• Slave channel:
TOEpr = 1, TOMpr = 1, TOLpr = 0
Figure 6-31. Set/Reset Timing Operating Statuses
fCLK
Count clock
Master channel
INTTMpq
to_reset
(Internal signal)
TOpq pin/
TOpq
Toggle
to_set
(Internal signal)
Delays to_reset by 1 count
clock with slave channel
Slave channel
INTTMpr
to_reset
(Internal signal)
TOpr pin/
TOpr
Set
Reset
Remarks 1. to_reset: TOpq pin reset/toggle signal
to_set:
TOpq pin set signal
2. pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3:
• p = 0, q = 0 to 4, 7 (q = 0, 2, 4 for master channel)
q < r ≤ 7 (where r is a consecutive integer greater than q)
78K0R/LG3:
• p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel)
q < r ≤ 7 (where r is a consecutive integer greater than q)
78K0R/LH3:
• p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel)
q < r ≤ 7 (where r is a consecutive integer greater than q)
• p = 1, q = 0 to 3 (q = 0, 2 for master channel)
q < r ≤ 3 (where r is a consecutive integer greater than q)
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6.4.4 Collective manipulation of TOpq bits
In the TOp register, the setting bits for all the channels are located in one register in the same way as the TSp register
(channel start trigger). Therefore, TOpq of all the channels can be manipulated collectively. Only specific bits can also be
manipulated by setting the corresponding TOEpq = 0 to a target TOpq (channel output).
Figure 6-32. Example of TO0q Bits Collective Manipulation
Before writing
TO0
0
0
0
0
0
0
0
0
TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00
0
TOE0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
TOE07 TOE06 TOE05 TOE04 TOE03 TOE02 TOE01 TOE00
0
0
1
0
1
1
1
1
1
1
0
0
0
0
1
1
O
O
× O ×
×
×
×
Data to be written
0
0
0
0
0
0
0
0
After writing
TO0
0
0
0
0
0
0
0
0
TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00
1
1
1
0
0
0
1
0
Writing is done only to TOpq bits with TOEpq = 0, and writing to TOpq bits with TOEpq = 1 is ignored.
TOpq (channel output) to which TOEpq = 1 is set is not affected by the write operation. Even if the write operation is
done to TOpq, it is ignored and the output change by timer operation is normally done.
Figure 6-33. TOpq Pin Statuses by Collective Manipulation of TOpq Bits
Two or more TOpq output can
be changed simultaneously
TO07
Output does not change
when value does not
change
TO06
TO05
TO04
Writing to TOp bit
is ignored when TOEpq
=1
TO03
TO02
TO01
TO00
Before writing
Writing to TOp register
(Caution and Remark are given on the next page.)
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Caution When TOEpq = 1, even if the output by timer interrupt of each timer (INTTMpq) contends with
writing to TOpq, output is normally done to TOpq pin.
Remark pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
6.4.5 Timer Interrupt and TOpq Pin Output at Operation Start
In the interval timer mode or capture mode, the MDmn0 bit in the TMRmn register sets whether or not to generate a
timer interrupt at count start.
When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn) generation.
In the other modes, neither timer interrupt at count operation start nor TOpq output is controlled.
Figures 6-34 and 6-35 show operation examples when the interval timer mode (TOEmn = 1, TOMmn = 0) is set.
Figure 6-34. When MDmn0 is set to 1
TCRmn
TEmn
INTTMmn
TOpq
Count operation start
When MDmn0 is set to 1, a timer interrupt (INTTMmn) is output at count operation start, and TOpq performs a toggle
operation.
Figure 6-35. When MDmn0 is set to 0
TCRmn
TEmn
INTTMmn
TOpq
Count operation start
When MDmn0 is set to 0, a timer interrupt (INTTMmn) is not output at count operation start, and TOpq does not change
either. After counting one cycle, INTTMmn is output and TOpq performs a toggle operation.
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
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6.5 Channel Input Control
6.5.1 Edge detection circuit
(1) Edge detection basic operation timing
Edge detection circuit sampling is done in accordance with the operation clock (MCK).
Figure 6-36. Edge Detection Basic Operation Timing
fCLK
Operation clock (MCK)
Synchronized (noise filter)
internal TIpq signal
Rising edge detection
internal trigger
Falling edge detection
internal trigger
Remark pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
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6.6 Basic Function of Timer Array Unit
6.6.1 Overview of single-operation function and combination operation function
The timer array unit consists of several channels and has a single-operation function that allows each channel to
operate independently, and a combination operation function that uses two or more channels in combination.
The single-operation function can be used for any channel, regardless of the operation mode of the other channels.
The combination operation function is realized by combining a master channel (reference timer that mainly counts
periods) and a slave channel (timer that operates in accordance with the master channel), and several rules must be
observed when using this function.
6.6.2 Basic rules of combination operation function
The basic rules of using the combination operation function are as follows.
(1) Only an even channel (channel 0, 2, 4, etc.) can be set as a master channel.
(2) Any channel, except channel 0, can be set as a slave channel.
(3) The slave channel must be lower than the master channel.
Example: If channel 2 of TAU0 is set as a master channel, channel 3 or those that follow (channels 3, 4, etc. 5)
can be set as a slave channel.
If channel 2 of TAU1 is set as a master channel, channel 3 (because TAU1 is provided only with
channels up to channel 3) can be set as a slave channel.
(4) Two or more slave channels can be set for one master channel.
(5) When two or more master channels are to be used, slave channels with a master channel between them may not
be set.
Example: If channels 0 and 4 of TAU0 are set as master channels, channels 1 to 3 can be set as the slave
channels of master channel 0. Channels 5 to 7 cannot be set as the slave channels of master channel
0.
(6) The operating clock for a slave channel in combination with a master channel must be the same as that of the
master channel. The CKS bit (bit 15 of the TMRmn register) of the slave channel that operates in combination with
the master channel must be the same value as that of the master channel.
(7) A master channel can transmit INTTMmn (interrupt), start software trigger, and count clock to the lower channels.
(8) A slave channel can use the INTTMmn (interrupt), start software trigger, and count clock of the master channel, but
it cannot transmit its own INTTMmn (interrupt), start software trigger, and count clock to the lower channel.
(9) A master channel cannot use the INTTMmn (interrupt), start software trigger, and count clock from the higher
master channel.
(10) To simultaneously start channels that operate in combination, the TSmn bit of the channels in combination must be
set at the same time.
(11) During a counting operation, the TSmn bit of all channels that operate in combination or only the master channel
can be set. TSmn of only a slave channel cannot be set.
(12) To stop the channels in combination simultaneously, the TTmn bit of the channels in combination must be set at
the same time.
Remark
mn: Unit number + Channel number
mn = 00 to 07, 10 to 13
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6.6.3 Applicable range of basic rules of combination operation function
The rules of the combination operation function are applied in a channel group (a master channel and slave channels
forming one combination operation function).
If two or more channel groups that do not operate in combination are specified, the basic rules of the combination
operation function in 6.6.2 Basic rules of combination operation function do not apply to the channel groups.
Example
TAU0
CK00
Channel 0: Master
Channel group 1
(combination operation function)
Channel 1: Slave
Channel 2: Slave
Channel group 2
(combination operation function)
Channel 3: Single-operation function
CK01
Channel 4: Master
* The operating clock of channel group 1 may
be different from that of channel group 2.
Channel 5: Slave
Channel 6: Single-operation function
* A channel that singly operates may be
between channel group 1 and channel group
2.
Channel 7: Single-operation function
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6.7 Operation of Timer Array Unit as Independent Channel
6.7.1 Operation as interval timer/square wave output
(1) Interval timer
The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals.
The interrupt generation period can be calculated by the following expression.
Generation period of INTTMmn (timer interrupt) = Period of count clock × (Set value of TDRmn + 1)
(2) Operation as square wave output
TOpq performs a toggle operation as soon as INTTMpq has been generated, and outputs a square wave with a
duty factor of 50%.
The period and frequency for outputting a square wave from TOpq can be calculated by the following expressions.
• Period of square wave output from TOpq = Period of count clock × (Set value of TDRpq + 1) × 2
• Frequency of square wave output from TOpq = Frequency of count clock/{(Set value of TDRpq + 1) × 2}
The valid edge of TIpq pin input signal, the valid edge of fSUB/2, the valid edge of fSUB/4, or the valid edge of
INTRTC1 can be selected as the count clock, in addition to CKm0 and CKm1. Consequently, the interval timer can
be operated, regardless of the fCLK frequency (main system clock, subsystem clock).
When changing the clock selected as fCLK (changing the value of the system clock control register (CKC)), stop the
timer array units 0 and 1 (TAUS0, TAUS1) (TT0 = 00FFH, TT1 = 000FH) first.
Only in the case of SDIV=0, CCSmn=1 and TISmn=1, continuously use of TAUm is allowed, even when changing
CPU clock. However, the following limitation is existing.
• When changing CPU clock, source clock decrease/increase occurs as follows.
Main clock → Subsystem clock (CSS = 0→1): −1 clock
Subsystem clock → Main clock (CSS = 1→0): +1 clock
TCRmn operates as a down counter in the interval timer mode.
TCRmn loads the value of TDRmn at the first count clock after the channel start trigger bit (TSmn) is set to 1. If
MDmn0 of TMRmn = 0 at this time, INTTMmn is not output and TOpq is not toggled. If MDmn0 of TMRmn = 1,
INTTMmn is output and TOpq is toggled.
After that, TCRmn count down in synchronization with the count clock.
When TCRmn = 0000H, INTTMmn is output and TOpq is toggled at the next count clock. At the same time,
TCRmn loads the value of TDRmn again. After that, the same operation is repeated.
TDRmn can be rewritten at any time. The new value of TDRmn becomes valid from the next period.
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CKm1
Operation clock
Trigger selection
INTRTCINOTE
Timer input
selection
TIpq pin input
fSUB/2
fSUB/4
Edge selection
CKm0
Clock selection
Clock selection
Figure 6-37. Block Diagram of Operation as Interval Timer/Square Wave Output
TSmn
Timer counter
(TCRmn)
Output
controller
Data register
(TDRmn)
Interrupt
controller
TOpq pin
Interrupt signal
(INTTMmn)
Note Channels 0 and 4 of timer array unit 0 only
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
Figure 6-38. Example of Basic Timing of Operation as Interval Timer/Square Wave Output (MDmn0 = 1)
TSmn
TEmn
TCRmn
0000H
TDRmn
a
b
TOpq
INTTMmn
a+1
Remark
a+1
a+1
b+1
b+1
b+1
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
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Figure 6-39. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/3)
(1) When CKm0 or CKm1 is selected as count clock
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn
1/0
12
0
0
0
0
0
0
0
0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
0
0
0
0
1/0
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTMmn nor inverts
timer output when counting is started.
1: Generates INTTMmn and inverts timer
output when counting is started.
Selection of edge of timer input
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Cleared to 0 when independent function is selected.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channel n.
1: Selects CKm1 as operation clock of channel n.
(b) Timer output register p (TOp)
Bit q
TOp
TOpq
1/0
0: Outputs 0 from TOpq.
1: Outputs 1 from TOpq.
(c) Timer output enable register p (TOEp)
Bit q
TOEp
TOEpq
1/0
0: Stops the TOpq output operation by counting operation.
1: Enables the TOpq output operation by counting operation.
(d) Timer output level register p (TOLp)
Bit q
TOLp
TOLpq
0: Cleared to 0 when TOMpq = 0 (toggle mode)
0
(e) Timer output mode register p (TOMp)
Bit q
TOMp
TOMpq
0: Sets toggle mode.
0
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
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Figure 6-39. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/3)
Note
(2) When the timer input (TIpq pin input, fSUB/4, fSUB/2 or INTRTCI) is selected as count clock
Note The timer input is selected by using TISpq bit, SDIV bit, and RTCISpq bit.
(1/2)
For details, refer to
Figure 6-17 Format of Timer Input Select Registers 0, 1 (TIS0, TIS1).
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn
1/0
12
0
0
1
0
0
0
0
1/0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
1/0
0
0
0
1/0
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTMmn nor inverts
timer output when counting is started.
1: Generates INTTMmn and inverts timer
output when counting is started.
Selection of edge of timer input
00B: detects falling edge.
01B: detects rising edge.
10B: detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Cleared to 0 when independent function is selected.
Count clock selection
1: Selects timer input valid edge.
Operation clock selection
0: Selects CKm0 as operation clock of channel n.
1: Selects CKm1 as operation clock of channel n.
fCLK (no division) is selected as selected operation clock by TPSm register.
(b) Timer clock select register m (TPSm)
Bits 7 to 4, 3 to 0
TPSm
PRSmk3 to PRSmk0
0000
0000B: Selects fCLK (no division) as operation clock selected by CKSmn of TMRmn register.
k = 0 (bits 0 to 3) when CKm0 is selected and k = 1 (bits 4 to 7) when CKm1 is selected
(c) Timer output register p (TOp)
Bit q
TOp
Remark
TOpq
0: Outputs 0 from TOpq.
1/0
1: Outputs 1 from TOpq.
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
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Figure 6-39. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (3/3)
(2) When the timer input (TIpq pin input, fSUB/4, fSUB/2 or INTRTCI) is selected as count clock (2/2)
(e) Timer output enable register p (TOEp)
Bit q
TOEp
TOEpq
1/0
0: Stops the TOpq output operation by counting operation.
1: Enables the TOpq output operation by counting operation.
(f) Timer output level register p (TOLp)
Bit q
TOLp
TOLpq
0: Cleared to 0 when TOMpq = 0 (toggle mode)
0
(g) Timer output mode register p (TOMp)
Bit q
TOMp
TOMpq
0: Sets toggle mode.
0
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
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Figure 6-40. Operation Procedure of Interval Timer/Square Wave Output Function (1/2)
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAU0EN or TAU1EN bits of the PER0
register to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets the TPSm register.
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets the TMRmn register (determines operation mode of
Channel stops operating.
default
channel).
(Clock is supplied and some power is consumed.)
setting
If timer input is selected for the count clock, set the timer
input (TIpq pin input, fSUB/4, fSUB/2, or INTRTCI) by using
the TISpq, SDIV, and RTCISpq bits.
Sets interval (period) value to the TDRmn register.
To use the TOpq output
The TOmn pin goes into Hi-Z output state.
Clears the TOMpq bit of the TOMm register to 0
(toggle mode).
Clears the TOLpq bit to 0.
Sets the TOpq bit and determines default level of the
TOpq output.
The TOpq default setting level is output when the port mode
register is in the output mode and the port register is 0.
Sets TOEpq to 1 and enables operation of TOpq.
TOpq does not change because channel stops operating.
Clears the port register and port mode register to 0.
The TOpq pin outputs the TOpq set level.
Operation
Sets TOEpq to 1 (only when operation is resumed).
start
Sets the TSmn bit to 1.
TEmn = 1, and count operation starts.
The TSmn bit automatically returns to 0 because it is a
Value of TDRmn is loaded to TCRmn at the count clock
trigger bit.
input. INTTMmn is generated and TOpq performs toggle
Operation is resumed.
operation if the MDmn0 bit of the TMRmn register is 1.
During
Set values of TMRmn, TOMp, and TOLp registers cannot
Counter (TCRmn) counts down. When count value reaches
operation
be changed.
0000H, the value of TDRmn is loaded to TCRmn again and
Set value of the TDRmn register can be changed.
the count operation is continued. By detecting TCRmn =
The TCRmn register can always be read.
0000H, INTTMmn is generated and TOmn performs toggle
The TSRmn register is not used.
operation.
Set values of the TOp and TOEp registers can be
After that, the above operation is repeated.
changed.
Operation
stop
The TTmn bit is set to 1.
TCRmn holds count value and stops.
trigger bit.
The TOpq output is not initialized but holds current status.
TOEpq is cleared to 0 and value is set to TOp register.
Remark
TEmn = 0, and count operation stops.
The TTmn bit automatically returns to 0 because it is a
The TOpq pin outputs the TOpq set level.
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
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Figure 6-40. Operation Procedure of Interval Timer/Square Wave Output Function (2/2)
Software Operation
TAU stop
Hardware Status
To hold the TOpq pin output level
Clears TOpq bit to 0 after the value to
be held is set to the port register.
The TOpq pin output level is held by port function.
When holding the TOpq pin output level is not necessary
Switches the port mode register to input mode.
The TOpq pin output level goes into Hi-Z output state.
The TAU0EN or TAU1EN bits of the PER0 register
is cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TOpq bit is cleared to 0 and the TOpq pin is set to
port mode.)
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
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6.7.2 Operation as external event counter
The timer array unit can be used as an external event counter that counts the number of times the valid input edge
(external event) is detected in the TIpq pin. When a specified count value is reached, the event counter generates an
interrupt. The specified number of counts can be calculated by the following expression.
Specified number of counts = Set value of TDRpq + 1
TCRpq operates as a down counter in the event counter mode.
When the channel start trigger bit (TSpq) is set to 1, TCRpq loads the value of TDRpq.
TCRpq counts down each time the valid input edge of the TIpq pin has been detected. When TCRpq = 0000H, TCRpq
loads the value of TDRpq again, and outputs INTTMpq.
After that, the above operation is repeated.
TOpq must not be used because its waveform depends on the external event and irregular.
TDRpq can be rewritten at any time. The new value of TDRpq becomes valid during the next count period.
TSpq
Trigger selection
Edge
detection
TIpq pin
Clock selection
Figure 6-41. Block Diagram of Operation as External Event Counter
Timer counter
(TCRpq)
Data register
(TDRpq)
Interrupt
controller
Interrupt signal
(INTTMpq)
Remark pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
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Figure 6-42. Example of Basic Timing of Operation as External Event Counter
TSpq
TEpq
TIpq
3
2
TCRpq
0000H
TDRpq
3
1
0
2
1
0003H
2
0
1
2
0
1
0002H
INTTMpq
4 events
4 events
3 events
Remark pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
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Figure 6-43. Example of Set Contents of Registers in External Event Counter Mode
(a) Timer mode register pq (TMRpq)
15
TMRpq
14
13
CKSpq
1/0
0
0
12
11
CCSpq
MAS
TERpq
1
0
10
9
8
7
6
5
4
STSpq2 STSpq1 STSpq0 CISpq1 CISpq0
0
0
0
1/0
3
2
1
0
MDpq3 MDpq2 MDpq1 MDpq0
1/0
0
0
0
1
1
0
Operation mode of channel q
011B: Event count mode
Setting of operation when counting is started
0: Neither generates INTTMpq nor inverts
timer output when counting is started.
Selection of TIpq pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Cleared to 0 when independent function is selected.
Count clock selection
1: Selects the TIpq pin input valid edge.
Operation clock selection
0: Selects CKp0 as operation clock of channel q.
1: Selects CKp1 as operation clock of channel q.
(b) Timer output register p (TOp)
Bit q
TOp
TOpq
0: Outputs 0 from TOpq.
0
(c) Timer output enable register p (TOEp)
Bit q
TOEp
TOEpq
0: Stops the TOpq output operation by counting operation.
0
(d) Timer output level register p (TOLp)
Bit q
TOLp
TOLpq
0: Cleared to 0 when TOMpq = 0 (toggle mode).
0
(e) Timer output mode register p (TOMp)
Bit q
TOMp
TOMpq
0: Sets toggle mode.
0
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
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Figure 6-44. Operation Procedure When External Event Counter Function Is Used
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAU0EN or TAU1EN bits of the PER0
register to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets the TPSp register.
Determines clock frequencies of CKp0 and CKp1.
Channel
Sets the TMRpq register (determines operation mode of
Channel stops operating.
default
channel).
(Clock is supplied and some power is consumed.)
setting
Sets number of counts to the TDRpq register.
Clears the TOEpq bit of the TOEp register to 0.
Operation
Operation is resumed.
start
Sets the TSpq bit to 1.
The TSpq bit automatically returns to 0 because it is a
trigger bit.
TEpq = 1, and count operation starts.
Value of TDRpq is loaded to TCRpq and detection of
the TIpq pin input edge is awaited.
During
Set value of the TDRpq register can be changed.
Counter (TCRpq) counts down each time input edge of the
operation
The TCRpq register can always be read.
TIpq pin has been detected. When count value reaches
The TSRpq register is not used.
0000H, the value of TDRpq is loaded to TCRpq again, and
Set values of TMRpq, TOMp, TOLp, TOp, and TOEp
the count operation is continued. By detecting TCRpq =
registers cannot be changed.
0000H, the INTTMpq output is generated.
After that, the above operation is repeated.
Operation
stop
The TTpq bit is set to 1.
The TTpq bit automatically returns to 0 because it is a
TEpq = 0, and count operation stops.
TCRpq holds count value and stops.
trigger bit.
TAU stop
The TAU0EN or TAU1EN bits of the PER0 register is
cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
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6.7.3 Operation as frequency divider
The timer array unit can be used as a frequency divider that divides a clock input to the TIpq pin and outputs the result
from TOpq.
The divided clock frequency output from TOpq can be calculated by the following expression.
• When rising edge/falling edge is selected:
Divided clock frequency = Input clock frequency/{(Set value of TDRpq + 1) × 2}
• When both edges are selected:
Divided clock frequency ≅ Input clock frequency/(Set value of TDRpq + 1)
TCRpq operates as a down counter in the interval timer mode.
After the channel start trigger bit (TSpq) is set to 1, TCRpq loads the value of TDRpq when the TIpq valid edge is
detected. If MDpq0 of TMRpq = 0 at this time, INTTMpq is not output and TOpq is not toggled. If MDpq0 of TMRpq = 1,
INTTMpq is output and TOpq is toggled.
After that, TCRpq counts down at the valid edge of TIpq. When TCRpq = 0000H, it toggles TOpq. At the same time,
TCRpq loads the value of TDRpq again, and continues counting.
If detection of both the edges of TIpq is selected, the duty factor error of the input clock affects the divided clock period
of the TOpq output.
The period of the TOpq output clock includes a sampling error of one period of the operation clock.
Clock period of TOpq output = Ideal TOpq output clock period ± Operation clock period (error)
TDRpq can be rewritten at any time. The new value of TDRpq becomes valid during the next count period.
TSpq
Remark
Trigger selection
Edge
detection
TIpq pin
Clock selection
Figure 6-45. Block Diagram of Operation as Frequency Divider
Timer counter
(TCRpq)
Output
controller
TOpq pin
Data register
(TDRpq)
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
pq = 00, 02 to 04
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Figure 6-46. Example of Basic Timing of Operation as Frequency Divider (MDpq0 = 1)
TSpq
TEpq
TIpq
2
TCRpq
0000H
TDRpq
2
1
2
1
0
0002H
1
0
1
0
1
0
1
0
1
0
0
0001H
TOpq
INTTMpq
Divided
by 6
Remark
Divided
by 4
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
pq = 00, 02 to 04
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Figure 6-47. Example of Set Contents of Registers When Frequency Divider Is Used
(a) Timer mode register pq (TMRpq)
15
TMRpq
14
13
CKSpq
1/0
0
0
12
11
CCSpq
MAS
TERpq
1
0
10
9
8
7
6
5
4
0
0
STSpq2 STSpq1 STSpq0 CISpq1 CISpq0
0
0
0
1/0
3
2
1
0
MDpq3 MDpq2 MDpq1 MDpq0
1/0
0
0
0
1/0
Operation mode of channel q
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTMpq nor inverts
timer output when counting is started.
1: Generates INTTMpq and inverts timer
output when counting is started.
Selection of TIpq pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Cleared to 0 when independent function is selected.
Count clock selection
1: Selects the TIpq pin input valid edge.
Operation clock selection
0: Selects CKp0 as operation clock of channel q.
1: Selects CKp1 as operation clock of channel q.
(b) Timer output register p (TOp)
Bit q
TOp
TOpq
0: Outputs 0 from TOpq.
1/0
1: Outputs 1 from TOpq.
(c) Timer output enable register p (TOEp)
Bit q
TOEp
TOEpq
0: Stops the TOpq output operation by counting operation.
1: Enables the TOpq output operation by counting operation.
1/0
(d) Timer output level register p (TOLp)
Bit q
TOLp
TOLpq
0: Cleared to 0 when TOMpq = 0 (toggle mode)
0
(e) Timer output mode register p (TOMp)
Bit q
TOMp
TOMpq
0: Sets toggle mode.
0
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
pq = 00, 02 to 04
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Figure 6-48. Operation Procedure When Frequency Divider Function Is Used (1/2)
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAU0EN or TAU1EN bits of the PER0 register
to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets the TPSp register.
Determines clock frequencies of CKp0 and CKp1.
Channel
Sets the TMRpq register (determines operation mode of
Channel stops operating.
default
channel).
(Clock is supplied and some power is consumed.)
setting
Sets interval (period) value to the TDRpq register.
Clears the TOMpq bit of the TOMp register to 0 (toggle
The TOpq pin goes into Hi-Z output state.
mode).
Clears the TOLpq bit to 0.
Sets the TOpq bit and determines default level of the
TOpq output.
The TOpq default setting level is output when the port mode
register is in output mode and the port register is 0.
Sets TOEpq to 1 and enables operation of TOpq.
TOpq does not change because channel stops operating.
Clears the port register and port mode register to 0.
The TOpq pin outputs the TOpq set level.
Operation
Sets the TOEpq to 1 (only when operation is resumed).
start
Sets the TSpq bit to 1.
TEpq = 1, and count operation starts.
The TSpq bit automatically returns to 0 because it is a
Value of TDRpq is loaded to TCRpq at the count clock
trigger bit.
input. INTTMpq is generated and TOpq performs toggle
Operation is resumed.
operation if the MDpq0 bit of the TMRpq register is 1.
During
Set value of the TDRpq register can be changed.
Counter (TCRpq) counts down. When count value reaches
operation
The TCRpq register can always be read.
0000H, the value of TDRpq is loaded to TCRpq again, and
The TSRpq register is not used.
the count operation is continued. By detecting TCRpq =
Set values of TOp and TOEp registers can be changed.
0000H, INTTMpq is generated and TOpq performs toggle
Set values of TMRpq, TOMp, and TOLp registers cannot
operation.
be changed.
After that, the above operation is repeated.
The TTpq bit is set to 1.
TEpq = 0, and count operation stops.
Operation
stop
The TTpq bit automatically returns to 0 because it is a
TCRpq holds count value and stops.
trigger bit.
The TOpq output is not initialized but holds current status.
TOEpq is cleared to 0 and value is set to the TOp
register.
Remark
The TOpq pin outputs the TOpq set level.
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
pq = 00, 02 to 04
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Figure 6-48. Operation Procedure When Frequency Divider Function Is Used (2/2)
Software Operation
TAU stop
Hardware Status
To hold the TOpq pin output level
Clears TOpq bit to 0 after the value to
The TOpq pin output level is held by port function.
be held is set to the port register.
When holding the TOpq pin output level is not
The TOpq pin output level goes into Hi-Z output state.
necessary
Switches the port mode register to input mode.
The TAU0EN or TAU1EN bits of the PER0 register is
cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TOpq bit is cleared to 0 and the TOpq pin is set to
port mode).
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
pq = 00, 02 to 04
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6.7.4 Operation as input pulse interval measurement
The count value can be captured at the TIpq valid edge and the interval of the pulse input to TIpq can be measured.
The pulse interval can be calculated by the following expression.
TIpq input pulse interval = Period of count clock × ((10000H × TSRpq: OVF) + (Capture value of TDRpq + 1))
Caution The TIpq pin input is sampled using the operating clock selected with the CKSpq bit of the
TMRpq register, so an error equal to the number of operating clocks occurs.
TCRpq operates as an up counter in the capture mode.
When the channel start trigger (TSpq) is set to 1, TCRpq counts up from 0000H in synchronization with the count clock.
When the TIpq pin input valid edge is detected, the count value is transferred (captured) to TDRpq and, at the same
time, the counter (TCRpq) is cleared to 0000H, and the INTTMpq is output. If the counter overflows at this time, the
OVFpq bit of the TSRpq register is set to 1. If the counter does not overflow, the OVFpq bit is cleared. After that, the
above operation is repeated.
As soon as the count value has been captured to the TDRpq register, the OVFpq bit of the TSRpq register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVFpq bit
of the TSRpq register is set to 1. However, the OVFpq bit is configured as a cumulative flag, the correct interval value
cannot be measured if an overflow occurs more than once.
Set STSpq2 to STSpq0 of the TMRpq register to 001B to use the valid edges of TIpq as a start trigger and a capture
trigger.
When TEpq = 1, instead of the TIpq pin input, a software operation (TSpq = 1) can be used as a capture trigger.
CKp1
Operation clock
CKp0
Edge
detection
TIpq pin
TSpq
Remark
Trigger selection
Clock selection
Figure 6-49. Block Diagram of Operation as Input Pulse Interval Measurement
Timer counter
(TCRpq)
Data register
(TDRpq)
Interrupt
controller
Interrupt signal
(INTTMpq)
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3:
p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
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Figure 6-50. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDpq0 = 0)
TSpq
TEpq
TIpq
FFFFH
b
a
TCRpq
d
c
0000H
TDRpq
0000H
a
b
c
d
INTTMpq
OVFpq
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3:
pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
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Figure 6-51. Example of Set Contents of Registers to Measure Input Pulse Interval
(a) Timer mode register pq (TMRpq)
15
TMRpq
14
13
CKSpq
1/0
0
0
12
11
CCSpq
MAS
TERpq
0
0
10
9
8
7
6
5
4
0
0
STSpq2 STSpq1 STSpq0 CISpq1 CISpq0
0
0
1
1/0
1/0
3
2
1
0
MDpq3 MDpq2 MDpq1 MDpq0
0
1
0
1/0
Operation mode of channel q
010B: Capture mode
Setting of operation when counting is started
0: Does not generate INTTMpq when
counting is started.
1: Generates INTTMpq when counting is
started.
Selection of TIpq pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Capture trigger selection
001B: Selects the TIpq pin input valid edge.
Slave/master selection
0: Cleared to 0 when independent function is selected.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKp0 as operation clock of channel q.
1: Selects CKp1 as operation clock of channel q.
(b) Timer output register p (TOp)
Bit q
TOp
0: Outputs 0 from TOpq.
TOpq
0
(c) Timer output enable register p (TOEp)
Bit q
TOEp
TOEpq
0: Stops TOpq output operation by counting operation.
0
(d) Timer output level register p (TOLp)
Bit q
TOLp
TOLpq
0: Cleared to 0 when TOMpq = 0 (toggle mode).
0
(e) Timer output mode register p (TOMp)
Bit q
TOMp
TOMpq
0: Sets toggle mode.
0
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
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Figure 6-52. Operation Procedure When Input Pulse Interval Measurement Function Is Used
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAU0EN or TAU1EN bits of the PER0 register
Power-on status. Each channel stops operating.
to 1.
(Clock supply is started and writing to each register is
enabled.)
Sets the TPSp register.
Determines clock frequencies of CKp0 and CKp1.
Channel
Sets the TMRpq register (determines operation mode of
Channel stops operating.
default
channel).
(Clock is supplied and some power is consumed.)
Sets TSpq bit to 1.
TEpq = 1, and count operation starts.
setting
Operation
start
The TSpq bit automatically returns to 0 because it is a
TCRpq is cleared to 0000H at the count clock input.
trigger bit.
When the MDpq0 bit of the TMRpq register is 1,
Operation is resumed.
INTTMpq is generated.
During
Set values of only the CISpq1 and CISpq0 bits of the
Counter (TCRpq) counts up from 0000H. When the TIpq
operation
TMRpq register can be changed.
pin input valid edge is detected, the count value is
The TDRpq register can always be read.
transferred (captured) to TDRpq. At the same time,
The TCRpq register can always be read.
TCRpq is cleared to 0000H, and the INTTMpq signal is
The TSRpq register can always be read.
generated.
Set values of TOMp, TOLp, TOp, and TOEp registers
If an overflow occurs at this time, the OVFpq bit of the
cannot be changed.
TSRpq register is set; if an overflow does not occur, the
OVFpq bit is cleared.
After that, the above operation is repeated.
Operation
stop
TAU stop
The TTpq bit is set to 1.
TEpq = 0, and count operation stops.
The TTpq bit automatically returns to 0 because it is a
TCRpq holds count value and stops.
trigger bit.
The OVFpq bit of the TSRpq register is also held.
The TAU0EN or TAU1EN bits of the PER0 register is
cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3:
p = 0, pq = 00 to 04, 07
78K0R/LG3:
p = 0, pq = 00 to 07
78K0R/LH3:
p = 0, 1, pq = 00 to 07, 10 to 13
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6.7.5 Operation as input signal high-/low-level width measurement
By starting counting at one edge of TIpq and capturing the number of counts at another edge, the signal width (highlevel width/low-level width) of TIpq can be measured.
The signal width of TIpq can be calculated by the following
expression.
Signal width of TIpq input = Period of count clock × ((10000H × TSRpq: OVF) + (Capture value of TDRpq + 1))
Caution The TIpq pin input is sampled using the operating clock selected with the CKSpq bit of the
TMRpq register, so an error equal to the number of operating clocks occurs.
TCRpq operates as an up counter in the capture & one-count mode.
When the channel start trigger (TSpq) is set to 1, TEpq is set to 1 and the TIpq pin start edge detection wait status is
set.
When the TIpq start valid edge (rising edge of TIpq when the high-level width is to be measured) is detected, the
counter counts up in synchronization with the count clock. When the valid capture edge (falling edge of TIpq when the
high-level width is to be measured) is detected later, the count value is transferred to TDRpq and, at the same time,
INTTMpq is output. If the counter overflows at this time, the OVFpq bit of the TSRpq register is set to 1. If the counter
does not overflow, the OVFpq bit is cleared. TCRpq stops at the value “value transferred to TDRpq + 1”, and the TIpq pin
start edge detection wait status is set. After that, the above operation is repeated.
As soon as the count value has been captured to the TDRpq register, the OVFpq bit of the TSRpq register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVFpq bit
of the TSRpq register is set to 1. However, the OVFpq bit is configured as an integral flag, and the correct interval value
cannot be measured if an overflow occurs more than once.
Whether the high-level width or low-level width of the TIpq pin is to be measured can be selected by using the CISpq1
and CISpq0 bits of the TMRpq register.
Because this function is used to measure the signal width of the TIpq pin input, TSpq cannot be set to 1 while TEpq is 1.
CISpq1, CISpq0 of TMRpq = 10B: Low-level width is measured.
CISpq1, CISpq0 of TMRpq = 11B: High-level width is measured.
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
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CKp1
CKp0
TIpq pin
Remark
Edge
detection
Timer counter
(TCRpq)
Trigger selection
Operation clock
Clock selection
Figure 6-53. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement
Data register
(TDRpq)
Interrupt
controller
Interrupt signal
(INTTMpq)
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
Figure 6-54. Example of Basic Timing of Operation as Input Signal High-/Low-Level Width Measurement
TSpq
TEpq
TIpq
FFFFH
a
b
TCRpq
c
0000H
TDRpq
0000H
a
b
c
INTTMpq
OVFpq
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
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Figure 6-55. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width
(a) Timer mode register pq (TMRpq)
15
TMRpq
14
13
CKSpq
1/0
0
0
12
11
CCSpq
MAS
TERpq
0
0
10
9
8
7
6
5
4
0
0
STSpq2 STSpq1 STSpq0 CISpq1 CISpq0
0
1
0
1
3
2
1
0
MDpq3 MDpq2 MDpq1 MDpq0
1/0
1
1
0
0
Operation mode of channel q
110B: Capture & one-count
Setting of operation when counting is started
0: Does not generate INTTMpq when
counting is started.
Selection of TIpq pin input edge
10B: Both edges (to measure low-level width)
11B: Both edges (to measure high-level width)
Start trigger selection
010B: Selects the TIpq pin input valid edge.
Slave/master selection
0: Cleared to 0 when independent function is selected.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKp0 as operation clock of channel q.
1: Selects CKp1 as operation clock of channel q.
(b) Timer output register p (TOp)
Bit q
TOp
0: Outputs 0 from TOpq.
TOpq
0
(c) Timer output enable register p (TOEp)
Bit q
TOEp
TOEpq
0: Stops the TOpq output operation by counting operation.
0
(d) Timer output level register p (TOLp)
Bit q
TOLp
TOLpq
0: Cleared to 0 when TOMpq = 0 (toggle mode).
0
(e) Timer output mode register p (TOMp)
Bit q
TOMp
TOMpq
0: Sets toggle mode.
0
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
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Figure 6-56. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAU0EN or TAU1EN bits of the PER0 register
to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets the TPSp register.
Determines clock frequencies of CKp0 and CKp1.
Channel
Sets the TMRpq register (determines operation mode of
Channel stops operating.
default
channel).
(Clock is supplied and some power is consumed.)
setting
Clears TOEpq to 0 and stops operation of TOpq.
Operation
Sets the TSpq bit to 1.
start
The TSpq bit automatically returns to 0 because it is a
TEpq = 1, and the TIpq pin start edge detection wait
status is set.
Operation is resumed.
trigger bit.
Detects TIpq pin input count start valid edge.
Clears TCRpq to 0000H and starts counting up.
During
Set value of the TDRpq register can be changed.
When the TIpq pin start edge is detected, the counter
operation
The TCRpq register can always be read.
(TCRpq) counts up from 0000H. If a capture edge of the
The TSRpq register is not used.
TIpq pin is detected, the count value is transferred to
Set values of TMRpq, TOMp, TOLp, TOp, and TOEp
TDRpq and INTTMpq is generated.
registers cannot be changed.
If an overflow occurs at this time, the OVFpq bit of the
TSRpq register is set; if an overflow does not occur, the
OVFpq bit is cleared. TCRpq stops the count operation
until the next TIpq pin start edge is detected.
Operation
stop
TAU stop
The TTpq bit is set to 1.
TEpq = 0, and count operation stops.
TTpq bit automatically returns to 0 because it is a
TCRpq holds count value and stops.
trigger bit.
The OVFpq bit of the TSRpq register is also held.
The TAU0EN or TAU1EN bits of PER0 register is cleared
to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
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6.8 Operation of Plural Channels of Timer Array Unit
6.8.1 Operation as PWM function
Two channels can be used as a set to generate a pulse of any period and duty factor.
The period and duty factor of the output pulse can be calculated by the following expressions.
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period
Duty factor [%] = {Set value of TDRmp (slave)}/{Set value of TDRmn (master) + 1} × 100
0% output:
Set value of TDRmp (slave) = 0000H
100% output: Set value of TDRmp (slave) ≥ {Set value of TDRmn (master) + 1}
Remark
The duty factor exceeds 100% if the set value of TDRmp (slave) > (set value of TDRmn (master) + 1), it
summarizes to 100% output.
The master channel operates in the interval timer mode and counts the periods. When the channel start trigger (TSmn)
is set to 1, INTTMmn is output. TCRmn counts down starting from the loaded value of TDRmn, in synchronization with the
count clock. When TCRmn = 0000H, INTTMmn is output. TCRmn loads the value of TDRmn again. After that, it
continues the similar operation.
TCRmp of a slave channel operates in one-count mode, counts the duty factor, and outputs a PWM waveform from the
TOmp pin. TCRmp of the slave channel loads the value of TDRmp, using INTTMmn of the master channel as a start
trigger, and stops counting until the next start trigger (INTTMmn of the master channel) is input.
The output level of TOmp becomes active one count clock after generation of INTTMmn from the master channel, and
inactive when TCRmp = 0000H.
Caution
To rewrite both TDRmn of the master channel and TDRmp of the slave channel, a write access is
necessary two times. The timing at which the values of TDRmn and TDRmp are loaded to TCRmn and
TCRmp is upon occurrence of INTTMmn of the master channel. Thus, when rewriting is performed
split before and after occurrence of INTTMmn of the master channel, the TOmp pin cannot output the
expected waveform. To rewrite both TDRmn of the master and TDRmp of the slave, therefore, be sure
to rewrite both the registers immediately after INTTMmn is generated from the master channel.
Remarks 1.
78K0R/LF3:
2.
78K0R/LG3:
3.
78K0R/LH3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, and TO07 pins
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13 pins
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CKm1
Operation clock
CKm0
TSmn
Trigger selection
Master channel
(interval timer mode)
Clock selection
Figure 6-57. Block Diagram of Operation as PWM Function
Timer counter
(TCRmn)
Data register
(TDRmn)
Interrupt
controller
Timer counter
(TCRmp)
Output
controller
Data register
(TDRmp)
Interrupt
controller
Interrupt signal
(INTTMmn)
CKm1
Operation clock
Trigger selection
CKm0
Clock selection
Slave channel
(one-count mode)
Remarks 1.
TOmp pin
Interrupt signal
(INTTMmp)
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, and TO07 pins
2.
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
3.
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13 pins
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Figure 6-58. Example of Basic Timing of Operation as PWM Function
TSmn
TEmn
FFFFH
Master
channel
TCRmn
0000H
TDRmn
a
b
TOmn
INTTMmn
TSmp
TEmp
FFFFH
Slave
channel
TCRmp
0000H
TDRmp
c
d
TOmp
INTTMmp
a+1
c
Remarks 1.
a+1
c
b+1
d
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, and TO07 pins
2.
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
3.
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13 pins
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Figure 6-59. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn
1/0
12
0
0
0
0
1
0
0
0
0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
0
0
0
1
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
1: Generates INTTMmn when counting is started.
Selection of TImn pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
1: Channel 1 is set as master channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channel n.
1: Selects CKm1 as operation clock of channel n.
(b) Timer output register m (TOm)
Bit n
TOm
0: Outputs 0 from TOmn.
TOmn
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (toggle mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets toggle mode.
0
Remarks 1.
2.
3.
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, TO07, TI00 to TI04, and TI07 pins
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13, TI10 to TI13 pins
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Figure 6-60. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used
(a) Timer mode register mp (TMRmp)
15
TMRmp
14
13
11
10
9
8
7
6
5
4
0
0
MAS
CCSmp
STSmp2 STSmp1 STSmp0 CISmp1 CISmp0
TERmp
CKSmp
1/0
12
0
0
0
0
1
0
0
0
3
2
1
0
MDmp3 MDmp2 MDmp1 MDmp0
0
1
0
0
1
Operation mode of channel p
100B: One-count mode
Start trigger during operation
1: Trigger input is valid.
Selection of TImp pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
Slave/master selection
0: Channel 0 is set as slave channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channel p.
1: Selects CKm1 as operation clock of channel p.
* Make the same setting as master channel.
(b) Timer output register m (TOm)
Bit p
TOm
TOmp
0: Outputs 0 from TOmp.
1/0
1: Outputs 1 from TOmp.
(c) Timer output enable register m (TOEm)
Bit p
TOEm
TOEmp
1/0
0: Stops the TOmp output operation by counting operation.
1: Enables the TOmp output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit p
TOLm
TOLmp
0: Positive logic output (active-high)
1: Inverted output (active-low)
1/0
(e) Timer output mode register m (TOMm)
Bit p
TOMm
TOMmp
1: Sets the combination operation mode.
1
Remarks 1.
2.
3.
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, TO07, TI00 to TI04, and TI07 pins
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13, TI10 to TI13 pins
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Figure 6-61. Operation Procedure When PWM Function Is Used (1/2)
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAU0EN or TAU1EN bits of the PER0 register
to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets the TPSm register.
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets the TMRmn and TMRmp registers of two channels
Channel stops operating.
default
to be used (determines operation mode of channels).
(Clock is supplied and some power is consumed.)
setting
An interval (period) value is set to the TDRmn register of
the master channel, and a duty factor is set to the
TDRmp register of the slave channel.
Sets slave channel.
The TOmn pin goes into Hi-Z output state.
The TOMmp bit of the TOMn register is set to 1
(combination operation mode).
Sets the TOLmp bit.
Sets the TOmp bit and determines default level of the
TOmp output.
The TOmn default setting level is output when the port
mode register is in output mode and the port register is 0.
Sets TOEmp to 1 and enables operation of TOmp.
TOmp does not change because channel stops operating.
Clears the port register and port mode register to 0.
The TOmp pin outputs the TOmp set level.
Remarks 1.
78K0R/LF3:
2.
78K0R/LG3:
3.
78K0R/LH3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, and TO07 pins
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13 pins
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Figure 6-61. Operation Procedure When PWM Function Is Used (2/2)
Software Operation
Operation
Sets TOEmp (slave) to 1 (only when operation is
start
resumed).
Hardware Status
The TSmn (master) and TSmp (slave) bits of the TSm
register are set to 1 at the same time.
TEmn = 1, TEmp = 1
The TSmn and TSmp bits automatically return to 0
When the master channel starts counting, INTTMmn is
because they are trigger bits.
generated. Triggered by this interrupt, the slave
channel also starts counting.
Set values of the TMRmn and TMRmp registers and
The counter of the master channel loads the TDRmn
operation
TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be
value to TCRmn, and counts down. When the count
changed.
value reaches TCRmn = 0000H, INTTMmn output is
Set values of the TDRmn and TDRmp registers can be
generated. At the same time, the value of the TDRmn
changed after INTTMmn of the master channel is
register is loaded to TCRmn, and the counter starts
generated.
counting down again.
The TCRmn and TCRmp registers can always be read.
At the slave channel, the value of TDRmp is loaded to
The TSRmn and TSRmp registers are not used.
TCRmp, triggered by INTTMmn of the master channel,
Set values of the TOm and TOEm registers cannot be
and the counter starts counting down. The output level of
changed.
TOmp becomes active one count clock after generation of
Operation is resumed.
During
the INTTMmn output from the master channel. It
becomes inactive when TCRmp = 0000H, and the
counting operation is stopped.
After that, the above operation is repeated.
Operation
The TTmn (master) and TTmp (slave) bits are set to 1 at
stop
the same time.
TEmn, TEmp = 0, and count operation stops.
The TTmn and TTmp bits automatically return to 0
TCRmn and TCRmp hold count value and stops.
because they are trigger bits.
The TOmp output is not initialized but holds current
status.
TOEmp of slave channel is cleared to 0 and value is set
to the TOmp register.
TAU stop
The TOmp pin outputs the TOmp set level.
To hold the TOmp pin output levels
Clears TOmp bit to 0 after the value to
The TOmp pin output levels is held by port function.
be held is set to the port register.
When holding the TOmp pin output levels is not
necessary
Switches the port mode register to input mode.
The TOmp pin output levels go are into Hi-Z output state.
The TAU0EN or TAU1EN bits of the PER0 register is
cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set
to port mode.)
Remarks 1.
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, and TO07 pins
2.
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
3.
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13 pins
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6.8.2 Operation as one-shot pulse output function
A one-shot pulse with any delay pulse width can be generated by using two channels in combination and TImn pin
input or software manipulation (TSmn = 1).
The delay time and pulse width can be calculated by the following expressions.
Delay time = {Set value of TDRmn (master) + 2} × Count clock period
Pulse width = {Set value of TDRmp (slave)} × Count clock period
The Master channel operates in the one-count mode and counts the delays. TCRmn of the master channel starts
operating upon start trigger detection and TCRmn loads the value of TDRmn. TCRmn counts down from the value of
TDRmn it has loaded, in synchronization with the count clock. When TCRmn = 0000H, it outputs INTTMmn and stops
counting until the next start trigger is detected.
The slave channel operates in the one-count mode and counts the pulse width. TCRmp of the slave channel starts
operation using INTTMmn of the master channel as a start trigger, and loads the TDRmp value. TCRmp counts down
from the value of TDRmp it has loaded, in synchronization with the count value. When TCRmp = 0000H, it outputs
INTTMmp and stops counting until the next start trigger (INTTMmn of the master channel) is detected. The output level of
TOmp becomes active one count clock after generation of INTTMmn from the master channel, and inactive when TCRmp
= 0000H.
Instead of using the TImn pin input, a one-shot pulse can also be output using the software operation (TSmn = 1) as a
start trigger.
Caution The timing of loading of TDRmn of the master channel is different from that of TDRmp of the slave
channel. If TDRmn and TDRmp are rewritten during operation, therefore, an illegal waveform is output.
Be sure to rewrite TDRmn and TDRmp after INTTMmn of the channel to be rewritten is generated.
Remarks 1.
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, TO07, TI00 to TI04, and TI07 pins
• Channel 6 of timer array unit 0 can output a one-shot pulse only when software trigger start is selected
and it is used as the master channel (because the TI06 pin is not provided).
2.
78K0R/LG3:
3.
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13, TI10 to TI13 pins
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Figure 6-62. Block Diagram of Operation as One-Shot Pulse Output Function
CKm1
Operation clock
CKm0
TSmn
Edge
detection
TImn pin
Trigger selection
Clock selection
Master channel
(one-count mode)
Timer counter
(TCRmn)
Data register
(TDRmn)
Interrupt
controller
Timer counter
(TCRmp)
Output
controller
Data register
(TDRmp)
Interrupt
controller
Interrupt signal
(INTTMmn)
CKm1
Operation clock
Trigger selection
CKm0
Clock selection
Slave channel
(one-count mode)
Remarks 1.
TOmp pin
Interrupt signal
(INTTMmp)
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, TO07, TI00 to TI04, and TI07 pins
• Channel 6 of timer array unit 0 can output a one-shot pulse only when software trigger start is selected
and it is used as the master channel (because the TI06 pin is not provided).
2.
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
3.
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13, TI10 to TI13 pins
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Figure 6-63. Example of Basic Timing of Operation as One-Shot Pulse Output Function
(Start Trigger Tlmn Input Valid Edge)
TSmn
TEmn
TImn
Master
channel
FFFFH
TCRmn
0000H
TDRmn
a
TOmn
INTTMmn
TSmp
TEmp
FFFFH
Slave
channel
TCRmp
0000H
TDRmp
b
TOmp
INTTMmp
a+2
Remarks 1.
b
a+2
b
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, and TO07 pins
2.
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
3.
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13 pins
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Figure 6-64. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel)
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn
1/0
12
0
0
0
0
1
0
1
1/0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
1/0
1
0
0
0
Operation mode of channel n
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects the software trigger start.
001B: Selects the TImn pin input valid edge.
Slave/master selection
1: Channel 1 is set as master channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channels n.
1: Selects CKm1 as operation clock of channels n.
(b) Timer output register m (TOm)
Bit n
TOm
0: Outputs 0 from TOmn.
TOmn
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (toggle mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets toggle mode.
0
Remarks 1.
2.
3.
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, TO07, TI00 to TI04, and TI07 pins
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13, TI10 to TI13 pins
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Figure 6-65. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel)
(a) Timer mode register mp (TMRmp)
15
TMRmp
14
13
CKSmp
1/0
12
CCSmp
0
0
0
11
10
9
8
7
6
5
4
MAS
STSmp2 STSmp1 STSmp0 CISmp1 CISmp0
TERmp
0
1
0
0
0
3
2
1
0
MDmp3 MDmp2 MDmp1 MDmp0
0
0
0
1
0
0
0
Operation mode of channel p
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
Selection of TImp pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
Slave/master selection
0: Channel 0 is set as slave channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channel p.
1: Selects CKm1 as operation clock of channel p.
* Make the same setting as master channel.
(b) Timer output register m (TOm)
Bit p
TOm
TOmp
0: Outputs 0 from TOmp.
1/0
1: Outputs 1 from TOmp.
(c) Timer output enable register m (TOEm)
Bit p
TOEm
TOEmp
0: Stops the TOmp output operation by counting operation.
1: Enables the TOmp output operation by counting operation.
1/0
(d) Timer output level register m (TOLm)
Bit p
TOLm
TOLmp
0: Positive logic output (active-high)
1: Inverted output (active-low)
1/0
(e) Timer output mode register m (TOMm)
Bit p
TOMm
TOMmp
1: Sets the combination operation mode.
1
Remarks 1.
2.
3.
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, TO07, TI00 to TI04, and TI07 pins
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13, TI10 to TI13 pins
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Figure 6-66. Operation Procedure of One-Shot Pulse Output Function (1/2)
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAU0EN or TAU1EN bits of the PER0 register
to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets the TPSm register.
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets the TMRmn and TMRmp registers of two channels
Channel stops operating.
default
to be used (determines operation mode of channels).
(Clock is supplied and some power is consumed.)
setting
An output delay is set to the TDRmn register of the
master channel, and a pulse width is set to the TDRmp
register of the slave channel.
Sets slave channel.
The TOmn pin goes into Hi-Z output state.
The TOMmp bit of the TOMm register is set to 1
(combination operation mode).
Sets the TOLmp bit.
Sets the TOmp bit and determines default level of the
TOmp output.
The TOmn default setting level is output when the port
mode register is in output mode and the port register is 0.
Sets TOEmp to 1 and enables operation of TOmp.
TOmp does not change because channel stops operating.
Clears the port register and port mode register to 0.
The TOmp pin outputs the TOmp set level.
Remarks 1.
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, and TO07 pins
• Channel 6 of timer array unit 0 can output a one-shot pulse only when software trigger start is selected
and it is used as the master channel (because the TI06 pin is not provided).
2.
78K0R/LG3:
3.
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13 pins
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Figure 6-66. Operation Procedure of One-Shot Pulse Output Function (2/2)
Software Operation
Operation
Sets TOEmp (slave) to 1 (only when operation is
start
resumed).
Hardware Status
The TSmn (master) and TSmp (slave) bits of the TSm
register are set to 1 at the same time.
The TSmn and TSmp bits automatically return to 0
because they are trigger bits.
Detects the start trigger of master channel.
TEmn and TEmp are set to 1 and the master channel
enters the TImn input edge detection wait status.
Counter stops operating.
Master channel starts counting.
(The valid edge of the TImn pin input is detected or the
TSmn bit is set to 1.)
Set values of only the CISmn1 and CISmn0 bits of the
Master channel loads the value of TDRmn to TCRmn
operation
TMRmn register can be changed.
when the start trigger is detected, and the counter starts
Set values of the TMRmp, TDRmn, and TDRmp registers
counting down. When the count value reaches TCRmn =
and TOMmn, TOMmp, TOLmn, and TOLmp bits cannot
0000H, the INTTMmn output is generated, and the counter
be changed.
stops until the next valid edge is input to the TImn pin.
The TCRmn and TCRmp registers can always be read.
The slave channel, triggered by INTTMmn of the master
The TSRmn and TSRmp registers are not used.
channel, loads the value of TDRmp to TCRmp, and the
Set values of the TOm and TOEm registers can be
counter starts counting down. The output level of TOmp
changed.
becomes active one count clock after generation of
Operation is resumed.
During
INTTMmn from the master channel. It becomes inactive when
TCRmp = 0000H, and the counting operation is stopped.
After that, the above operation is repeated.
Operation
The TTmn (master) and TTmp (slave) bits are set to 1 at
stop
the same time.
TEmn, TEmp = 0, and count operation stops.
The TTmn and TTmp bits automatically return to 0
TCRmn and TCRmp hold count value and stops.
because they are trigger bits.
The TOmp output is not initialized but holds current
status.
TOEmp of slave channel is cleared to 0 and value is set
to the TOm register.
TAU stop
The TOmp pin outputs the TOmn set level.
To hold the TOmp pin output levels
Clears TOmp bit to 0 after the value to
The TOmp pin output levels is held by port function.
be held is set to the port register.
When holding the TOmp pin output levels is not
necessary
Switches the port mode register to input mode.
The TOmp pin output levels go are into Hi-Z output state.
The TAU0EN or TAU1EN bits of the PER0 register is
cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set to
port mode.)
Remarks 1.
2.
3.
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, and TO07 pins
• Channel 6 of timer array unit 0 can output a one-shot pulse only when software trigger start is selected
and it is used as the master channel (because the TI06 pin is not provided).
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13 pins
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6.8.3 Operation as multiple PWM output function
By extending the PWM function and using two or more slave channels, many PWM output signals can be produced.
For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the
following expressions.
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period
Duty factor 1 [%] = {Set value of TDRmp (slave 1)}/{Set value of TDRmn (master) + 1} × 100
Duty factor 2 [%] = {Set value of TDRmp (slave 2)}/{Set value of TDRmn (master) + 1} × 100
Remark
Although the duty factor exceeds 100% if the set value of TDRmp (slave 1) > {set value of TDRmn
(master) + 1} or if the {set value of TDRmq (slave 2)} > {set value of TDRmn (master) + 1}, it is
summarized into 100% output.
TCRmn of the master channel operates in the interval timer mode and counts the periods.
TCRmp of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM waveform from
the TOmp pin. TCRmp loads the value of TDRmp to TCRmp, using INTTMmn of the master channel as a start trigger,
and start counting down. When TCRmp = 0000H, TCRmp outputs INTTMmp and stops counting until the next start trigger
(INTTMmn of the master channel) has been input. The output level of TOmp becomes active one count clock after
generation of INTTMmn from the master channel, and inactive when TCRmp = 0000H.
In the same way as TCRmp of the slave channel 1, TCRmq of the slave channel 2 operates in one-count mode, counts
the duty factor, and outputs a PWM waveform from the TOmq pin. TCRmq loads the value of TDRmq to TCRmq, using
INTTMmn of the master channel as a start trigger, and starts counting down. When TCRmq = 0000H, TCRmq outputs
INTTMmq and stops counting until the next start trigger (INTTMmn of the master channel) has been input. The output
level of TOmq becomes active one count clock after generation of INTTMmn from the master channel, and inactive when
TCRmq = 0000H.
When channel 0 is used as the master channel as described above, up to seven types of PWM signals can be output at
the same time with timer array unit 0 and up to three types with timer array unit 1.
Caution To rewrite both TDRmn of the master channel and TDRmp of the slave channel 1, write access is
necessary at least twice. Since the values of TDRmn and TDRmp are loaded to TCRmn and TCRmp
after INTTMmn is generated from the master channel, if rewriting is performed separately before and
after generation of INTTMmn from the master channel, the TOmp pin cannot output the expected
waveform. To rewrite both TDRmn of the master and TDRmp of the slave, be sure to rewrite both the
registers immediately after INTTMmn is generated from the master channel (This applies also to
TDRmq of the slave channel 2) .
Remarks 1.
78K0R/LF3:
2.
78K0R/LG3:
3.
78K0R/LH3:
• m = 0, n = 0, 2, p = n+1, q = n+2, TO00 to TO04, and TO07 pins
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
• m = 1, n = 0, p = 1, q = 2, TO10 to TO13 pins
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CKm1
Operation clock
CKm0
TSmn
Trigger selection
Master channel
(interval timer mode)
Clock selection
Figure 6-67. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs)
Timer counter
(TCRmn)
Data register
(TDRmn)
Interrupt
controller
Timer counter
(TCRmp)
Output
controller
Data register
(TDRmp)
Interrupt
controller
Timer counter
(TCRmq)
Output
controller
Data register
(TDRmq)
Interrupt
controller
Interrupt signal
(INTTMmn)
CKm1
Operation clock
Trigger selection
CKm0
Clock selection
Slave channel 1
(one-count mode)
TOmp pin
Interrupt signal
(INTTMmp)
CKm1
Operation clock
Trigger selection
CKm0
Clock selection
Slave channel 2
(one-count mode)
Remarks 1.
TOmq pin
Interrupt signal
(INTTMmq)
78K0R/LF3:
• m = 0, n = 0, 2, p = n+1, q = n+2, TO00 to TO04, and TO07 pins
2.
78K0R/LG3:
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
3.
78K0R/LH3:
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
• m = 1, n = 0, p = 1, q = 2, TO10 to TO13 pins
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Figure 6-68. Example of Basic Timing of Operation as Multiple PWM Output Function (output two types of PWMs)
TSmn
TEmn
FFFFH
Master
channel
TCRmn
0000H
TDRmn
a
b
TOmn
INTTMmn
TSmp
TEmp
FFFFH
Slave
channel 1
TCRmp
0000H
TDRmp
c
d
TOmp
INTTMmp
a+1
a+1
c
c
b+1
d
d
TSmq
TEmq
FFFFH
Slave
channel 2
TCRmq
0000H
TDRmq
e
f
TOmq
INTTMmq
a+1
e
Remarks 1.
2.
3.
a+1
e
b+1
f
f
78K0R/LF3:
• m = 0, n = 0, 2, p = n+1, q = n+2, TO00 to TO04, and TO07 pins
78K0R/LG3:
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
78K0R/LH3:
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
• m = 1, n = 0, p = 1, q = 2, TO10 to TO13 pins
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Figure 6-69. Example of Set Contents of Registers When Multiple PWM Output Function (Master Channel) Is Used
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn
1/0
12
0
0
0
0
1
0
0
0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
0
0
0
0
1
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
1: Generates INTTMmn when counting is started.
Selection of TImn pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
1: Channel 1 is set as master channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channel n.
1: Selects CKm1 as operation clock of channel n.
(b) Timer output register m (TOm)
Bit n
TOm
0: Outputs 0 from TOmn.
TOmn
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (toggle mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets toggle mode.
0
Remarks 1.
2.
3.
78K0R/LF3:
• m = 0, n = 0, 2, TO00 to TO04, TO07, TI00 to TI04, and TI07 pins
78K0R/LG3:
• m = 0, n = 0, 2, 4, TO00 to TO07, and TI00 to TI07 pins
78K0R/LH3:
• m = 0, n = 0, 2, 4, TO00 to TO07, and TI00 to TI07 pins
• m = 1, n = 0, TO10 to TO13 , and TI10 to TI13 pins
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Figure 6-70. Example of Set Contents of Registers
When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs)
(a) Timer mode register mp, mq (TMRmp, TMRmq)
15
TMRmp
TMRmq
14
13
11
10
9
8
7
6
5
4
MAS
CCSmp
STSmp2 STSmp1 STSmp0 CISmp1 CISmp0
TERmp
CKSmp
1/0
0
0
15
14
13
CKSmq
1/0
12
0
12
CCSmq
0
0
0
1
0
0
0
0
0
0
11
10
9
8
7
6
5
4
MAS
STSmq2 STSmq1 STSmq0 CISmq1 CISmq0
TERmq
1
0
0
0
2
1
0
MDmp3 MDmp2 MDmp1 MDmp0
0
0
3
1
0
0
1
3
2
1
0
MDmq3 MDmq2 MDmq1 MDmq0
0
0
0
1
0
0
1
Operation mode of channel p, q
100B: One-count mode
Start trigger during operation
1: Trigger input is valid.
Selection of TImp and TImq pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
Slave/master selection
0: Channel 0 is set as slave channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CKm0 as operation clock of channel p, q.
1: Selects CKm1 as operation clock of channel p, q.
* Make the same setting as master channel.
(b) Timer output register m (TOm)
TOm
Bit q
Bit p
TOmq
TOmp
0: Outputs 0 from TOmp or TOmq.
1/0
1/0
1: Outputs 1 from TOmp or TOmq.
(c) Timer output enable register m (TOEm)
Bit q
TOEm
Bit p
TOEmq TOEmp
1/0
1/0
0: Stops the TOmp or TOmq output operation by counting operation.
1: Enables the TOmp or TOmq output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit q
TOLm
Bit p
TOLmq TOLmp
1/0
1/0
0: Positive logic output (active-high)
1: Inverted output (active-low)
(e) Timer output mode register m (TOMm)
Bit q
TOMm
Bit p
TOMmq TOMmp
1
1: Sets the combination operation mode.
1
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Remarks 1.
78K0R/LF3:
2.
78K0R/LG3:
3.
78K0R/LH3:
• m = 0, n = 0, 2, p = n+1, q = n+2, TO00 to TO04, and TO07 pins
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
• m = 1, n = 0, p = 1, q = 2, TO10 to TO13 pins
Figure 6-71. Operation Procedure When Multiple PWM Output Function Is Used (1/2)
Software Operation
Hardware Status
Power-off status
TAU
(Clock supply is stopped and writing to each register is
default
disabled.)
setting
Sets the TAU0EN or TAU1EN bits of the PER0 register
to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets the TPSm register.
Determines clock frequencies of CKm0 and CKm1.
Channel
Sets the TMRmn, TMRmp, and TMRmq registers of
Channel stops operating.
default
each channel to be used (determines operation mode of
(Clock is supplied and some power is consumed.)
setting
channels).
An interval (period) value is set to the TDRmn register of
the master channel, and a duty factor is set to the
TDRmp and TDRmq register of the slave channel.
Sets slave channel.
The TOmn pin goes into Hi-Z output state.
The TOMmp and TOMmq bits of the TOMm register
are set to 1 (combination operation mode).
Clears the TOLmp and TOLmq bits to 0.
Sets the TOmp and TOmq bits and determines default
level of the TOmp and TOmq outputs.
The TOmp and TOmq default setting levels are output
when the port mode register is in output mode and the port
register is 0.
Sets TOEmp or TOEmq to 1 and enables operation of
TOmp and TOmq.
TOmp or TOmq does not change because channel stops
operating.
Clears the port register and port mode register to 0.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
Remarks 1.
78K0R/LF3:
2.
78K0R/LG3:
3.
78K0R/LH3:
• m = 0, n = 0, 2, p = n+1, q = n+2, TO00 to TO04, and TO07 pins
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
• m = 1, n = 0, p = 1, q = 2, TO10 to TO13 pins
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Figure 6-71. Operation Procedure When Multiple PWM Output Function Is Used (2/2)
Software Operation
Hardware Status
Operation Sets TOEmp and TOEmq (slave) to 1 (only when
start
operation is resumed).
The TSmn bit (master), and TSmp and TSmq (slave) bits
of the TSm register are set to 1 at the same time.
TEmn = 1, TEmp, TEmq = 1
The TSmn, TSmp, and TSmq bits automatically return
When the master channel starts counting, INTTMmn is
to 0 because they are trigger bits.
generated. Triggered by this interrupt, the slave
channel also starts counting.
Set values of the TMRmn, TMRmp, and TMRmq registers
The counter of the master channel loads the TDRmn value
operation
and TOMmn, TOMmp, TOMmq, TOLmn, TOLmp, and
to TCRmn and counts down. When the count value
TOLmq bits cannot be changed.
reaches TCRmn = 0000H, INTTMmn output is generated.
Set values of the TDRmn, TDRmp, and TDRmq registers
At the same time, the value of the TDRmn register is loaded
can be changed after INTTMmn of the master channel is
to TCRmn, and the counter starts counting down again.
generated.
At the slave channel 1, the values of TDRmp are
The TCRmn, TCRmp, and TCRmq registers can always
transferred to TCRmp, triggered by INTTMmn of the master
be read.
channel, and the counter starts counting down. The output
The TSRmn, TSRmp, and TSRmq registers are not used.
levels of TOmp become active one count clock after
Set values of the TOm and TOEm registers can be
generation of the INTTMmn output from the master
changed.
channel. It becomes inactive when TCRmp = 0000H, and
Operation is resumed.
During
the counting operation is stopped.
At the slave channel 2, the values of TDRmq are
transferred to TDRmq, triggered by INTTMmn of the master
channel, and the counter starts counting down. The output
levels of TOmq become active one count clock after
generation of the INTTMmn output from the master
channel. It becomes inactive when TCRmq = 0000H, and
the counting operation is stopped.
After that, the above operation is repeated.
Operation The TTmn bit (master), TTmp, and TTmq (slave) bits are
set to 1 at the same time.
stop
TEmn, TEmp, and TEmq = 0, and count operation stops.
The TTmn, TTmp, and TTmq bits automatically return
TCRmn, TCRmp and TCRmq hold count value and stops.
to 0 because they are trigger bits.
The TOmp and TOmq outputs are not initialized but
holds current status.
TOEmp or TOEmq of slave channel is cleared to 0
and value is set to the TOmp and TOmq registers.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
TAU stop
To hold the TOmp and TOmq pins output levels
Clears TOmp and TOmq bits to 0 after
the value to be held is set to the port register.
When holding the TOmp and TOmq pins output levels is
The TOmp and TOmq pins output levels are held by port
function.
not necessary
Switches the port mode register to input mode.
The TOmp and TOmq pins output levels go into Hi-Z output
state.
The TAU0EN or TAU1EN bits of the PER0 register is
cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp and TOmq bits are cleared to 0 and the
TOmp and TOmq pins are set to port mode.)
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Remarks 1.
78K0R/LF3:
2.
78K0R/LG3:
3.
78K0R/LH3:
• m = 0, n = 0, 2, p = n+1, q = n+2, TO00 to TO04, and TO07 pins
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
• m = 0, n = 0, 2, 4, p = n+1, q = n+2, TO00 to TO07 pins
• m = 1, n = 0, p = 1, q = 2, TO10 to TO13 pins
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CHAPTER 7 REAL-TIME COUNTER
7.1 Functions of Real-Time Counter
The real-time counter is mounted onto all 78K0R/Lx3 microcontroller products.
The real-time counter has the following features.
• Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years.
• Constant-period interrupt function (period: 1 month to 0.5 seconds)
• Alarm interrupt function (alarm: week, hour, minute)
• Interval interrupt function
• Pin output function of 1 Hz
• Pin output function of 512 Hz or 16.384 kHz or 32.768 kHz
7.2 Configuration of Real-Time Counter
The real-time counter includes the following hardware.
Table 7-1. Configuration of Real-Time Counter
Item
Control registers
Configuration
Peripheral enable register 0 (PER0)
Real-time counter control register 0 (RTCC0)
Real-time counter control register 1 (RTCC1)
Real-time counter control register 2 (RTCC2)
Sub-count register (RSUBC)
Second count register (SEC)
Minute count register (MIN)
Hour count register (HOUR)
Day count register (DAY)
Week count register (WEEK)
Month count register (MONTH)
Year count register (YEAR)
Watch error correction register (SUBCUD)
Alarm minute register (ALARMWM)
Alarm hour register (ALARMWH)
Alarm week register (ALARMWW)
Port mode register 3
Port register 3
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Figure 7-1. Block Diagram of Real-Time Counter
Real-time counter control register 1 (RTCC1)
WALE
WALIE WAFG
RIFG
Real-time counter control register 0 (RTCC0)
RWST RWAIT
RTCE RCLOE1 RCLOE0 AMPM
CT2
CT1
CT0
fSUB
Alarm week
register
(ALARMWW)
(7-bit)
Alarm hour
register
(ALARMWH)
(6-bit)
Alarm minute
register
(ALARMWM)
(7-bit)
Output
latch (P30)
RTC1HZ/
TI03/TO00/
P30/INTP1
PM30
To LCD driver/controller
INTRTC
CT0 to CT2
Selector
RIFG
AMPM
RWST
1 day
1 month
Year count
register
(YEAR)
(8-bit)
Month count
register
(MONTH)
(5-bit)
Week count
register
(WEEK)
(3-bit)
Day count
register
(DAY)
(6-bit)
1 hour
Hour count
register
(HOUR)
(6-bit)
RWAIT
1 minute
Minute count
register
(MIN)
(7-bit)
Second
count
register
(SEC)
(7-bit)
0.5
seconds
Count clock
Sub-count = 32.768 kHz
register
(RSUBC)
fSUB
(16-bit)
Wait control
Count enable/
disable circuit
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
RTCE
Watch error
correction
register
(SUBCUD)
(8-bit)
Internal bus
Real-time counter control register 2 (RTCC2)
RINTE RCLOE2 RCKDIV
fSUB
ICT2
ICT1
12-bit counter
ICT0
RINTE
Selector
To cannels 0 or 4 of the TAU0
INTRTCI
RCKDIV
Selector
RCLOE2
Output
latch (P31)
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7.3 Registers Controlling Real-Time Counter
Timer real-time counter is controlled by the following 18 registers.
• Peripheral enable register 0 (PER0)
• Real-time counter control register 0 (RTCC0)
• Real-time counter control register 1 (RTCC1)
• Real-time counter control register 2 (RTCC2)
• Sub-count register (RSUBC)
• Second count register (SEC)
• Minute count register (MIN)
• Hour count register (HOUR)
• Day count register (DAY)
• Week count register (WEEK)
• Month count register (MONTH)
• Year count register (YEAR)
• Watch error correction register (SUBCUD)
• Alarm minute register (ALARMWM)
• Alarm hour register (ALARMWH)
• Alarm week register (ALARMWW)
• Port mode register 3 (PM3)
• Port register 3 (P3)
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(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that
is not used is stopped in order to reduce the power consumption and noise.
When the real-time counter is used, be sure to set bit 7 (RTCEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
Symbol
PER0
After reset: 00H
R/W
RTCEN
DACEN
ADCEN
IICAEN
Note1
SAU1EN
SAU0EN
TAU1EN
TAU0EN
Note2
RTCEN
Control of real-time counter (RTC) input clock
Stops supply of input clock.
0
• SFR used by the real-time counter (RTC) cannot be written.
• The real-time counter (RTC) is in the reset status.
Supplies input clock.
1
• SFR used by the real-time counter (RTC) can be read/written.
Notes 1.
2.
78K0R/LG3, 78K0R/LH3 only
By using RTCEN, can supply and stop the clock that is used when accessing the real-time
counter (RTC) from the CPU. RTCEN cannot control supply of the operating clock (fSUB) to
RTC.
Cautions 1.
When using the real-time counter, first set RTCEN to 1, while oscillation of the
subsystem clock (fSUB) is stable. If RTCEN = 0, writing to a control register of the
real-time counter is ignored, and, even if the register is read, only the default value is
read.
2. Clock supply to peripheral functions except the real-time counter can be stopped in
the HALT mode when operating on the subsystem clock by setting RTCLPC of the
operation speed mode control register (OSMC) to 1. In this case, set RTCEN to 1 and
bits 0 to 6 of PER0 to 0.
(2) Real-time counter control register 0 (RTCC0)
The RTCC0 register is an 8-bit register that is used to start or stop the real-time counter operation, control the
RTCCL and RTC1HZ pins, and set a 12- or 24-hour system and the constant-period interrupt function.
RTCC0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
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Figure 7-3. Format of Real-Time Counter Control Register 0 (RTCC0)
Address: FFF9DH
After reset: 00H
R/W
Symbol
6
3
2
1
0
RTCC0
RTCE
0
RCLOE1
RCLOE0
AMPM
CT2
CT1
CT0
RTCE
Real-time counter operation control
0
Stops counter operation.
1
Starts counter operation.
RCLOE1
RTC1HZ pin output control
0
Disables output of RTC1HZ pin (1 Hz).
1
Enables output of RTC1HZ pin (1 Hz).
RCLOE0
Note
RTCCL pin output control
0
Disables output of RTCCL pin (32 kHz).
1
Enables output of RTCCL pin (32 kHz).
AMPM
Selection of 12-/24-hour system
0
12-hour system (a.m. and p.m. are displayed.)
1
24-hour system
• To change the value of AMPM, set RWAIT (bit 0 of RTCC1) to 1, and re-set the hour count register (HOUR).
• Table 7-2 shows the displayed time digits that are displayed.
CT2
CT1
CT0
Constant-period interrupt (INTRTC) selection
0
0
0
Does not use constant-period interrupt function.
0
0
1
Once per 0.5 s (synchronized with second count up)
0
1
0
Once per 1 s (same time as second count up)
0
1
1
Once per 1 m (second 00 of every minute)
1
0
0
Once per 1 hour (minute 00 and second 00 of every hour)
1
0
1
Once per 1 day (hour 00, minute 00, and second 00 of every day)
1
1
×
Once per 1 month (Day 1, hour 00 a.m., minute 00, and second 00 of
every month)
When changing the values of CT2 to CT0 while the counter operates (RTCE = 1), rewrite the values of CT2 to CT0
after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, after rewriting the
values of CT2 to CT0, enable interrupt servicing after clearing the RIFG and RTCIF flags.
Note RCLOE0 and RCLOE2 must not be enabled at the same time.
Caution If RCLOE0 and RCLOE1 are changed when RTCE = 1, the last waveform of the 32.768 kHz and 1
Hz output signals may become short.
Remark ×: don’t care
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(3) Real-time counter control register 1 (RTCC1)
The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the
counter.
RTCC1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-4. Format of Real-Time Counter Control Register 1 (RTCC1) (1/2)
Address: FFF9EH
After reset: 00H
R/W
Symbol
5
2
RTCC1
WALE
WALIE
0
WAFG
RIFG
0
RWST
RWAIT
WALE
Alarm operation control
0
Match operation is invalid.
1
Match operation is valid.
When setting a value to the WALE bit while the counter operates (RTCE = 1) and WALIE = 1, rewrite the WALE bit
after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, clear the WAFG
and RTCIF flags after rewriting the WALE bit. When setting each alarm register (WALIE flag of RTCC1, the
ALARMWM register, the ALARMWH register, and the ALARMWW register), set match operation to be invalid (“0”)
for the WALE bit.
WALIE
Control of alarm interrupt (INTRTC) function operation
0
Does not generate interrupt on matching of alarm.
1
Generates interrupt on matching of alarm.
WAFG
Alarm detection status flag
0
Alarm mismatch
1
Detection of matching of alarm
This is a status flag that indicates detection of matching with the alarm. It is valid only when WALE = 1 and is set to
“1” one clock (32.768 kHz) after matching of the alarm is detected. This flag is cleared when “0” is written to it.
Writing “1” to it is invalid.
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Figure 7-4. Format of Real-Time Counter Control Register 1 (RTCC1) (2/2)
RIFG
Constant-period interrupt status flag
0
Constant-period interrupt is not generated.
1
Constant-period interrupt is generated.
This flag indicates the status of generation of the constant-period interrupt. When the constant-period interrupt is
generated, it is set to “1”.
This flag is cleared when “0” is written to it. Writing “1” to it is invalid.
RWST
Wait status flag of real-time counter
0
Counter is operating.
1
Mode to read or write counter value
This status flag indicates whether the setting of RWAIT is valid.
Before reading or writing the counter value, confirm that the value of this flag is 1.
RWAIT
Wait control of real-time counter
0
Sets counter operation.
1
Stops SEC to YEAR counters. Mode to read or write counter value
This bit controls the operation of the counter.
Be sure to write “1” to it to read or write the counter value.
Because RSUBC continues operation, complete reading or writing of it in 1 second, and clear this bit back to 0.
When RWAIT = 1, it takes up to 1 clock (32.768 kHz) until the counter value can be read or written.
If RSUBC overflows when RWAIT = 1, it counts up after RWAIT = 0. If the second count register is written,
however, it does not count up because RSUBC is cleared.
Caution If writing is performed to the RTCC1 register with a 1-bit manipulation instruction, the RIFG and
WAFG flags may be cleared. Therefore, to perform writing to the RIFG and WAFG flags, be sure
to use an 8-bit manipulation instruction. At this time, set 1 to the RIFG and WAFG flags to
invalidate writing and not to clear the RIFG and WAFG flags during writing. When the value may
be rewritten because the RIFG and WAFG flags are not being used, the RTCC1 register may be
written by using a 1-bit manipulation instruction.
Remark Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When using
these two types of interrupts at the same time, which interrupt occurred can be judged by checking the
fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon INTRTC
occurrence.
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(4) Real-time counter control register 2 (RTCC2)
The RTCC2 register is an 8-bit register that is used to control the interval interrupt function and the RTCDIV pin.
RTCC2 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-5. Format of Real-Time Counter Control Register 2 (RTCC2)
Address: FFF9FH
After reset: 00H
R/W
Symbol
4
3
2
1
0
RTCC2
RINTE
RCLOE2
RCKDIV
0
0
ICT2
ICT1
ICT0
RINTE
ICT2
ICT1
ICT0
0
×
×
×
Interval interrupt is not generated.
1
0
0
0
2 /fSUB (1.953125 ms)
1
0
0
1
2 /fSUB (3.90625 ms)
1
0
1
0
2 /fSUB (7.8125 ms)
1
0
1
1
2 /fSUB (15.625 ms)
1
1
0
0
2 /fSUB (31.25 ms)
1
1
0
1
2 /fSUB (62.5 ms)
1
1
1
×
2 /fSUB (125 ms)
RCLOE2
Note
Interval interrupt (INTRTCI) selection
6
7
8
9
10
11
12
RTCDIV pin output control
0
Disables output of RTCDIV pin
1
Enables output of RTCDIV pin
RCKDIV
Selection of RTCDIV pin output frequency
0
RTCDIV pin outputs 512 Hz (1.95 ms).
1
RTCDIV pin outputs 16.384 kHz (0.061 ms).
Note RCLOE0 and RCLOE2 must not be enabled at the same time.
Cautions 1.
2.
Change ICT2, ICT1, and ICT0 when RINTE = 0.
When the output from RTCDIV pin is stopped, the output continues after a maximum of two
clocks of fXT and enters the low level. While 512 Hz is output, and when the output is stopped
immediately after entering the high level, a pulse of at least one clock width of fSUB may be
generated.
3.
After the real-time counter starts operating, the output width of the RTCDIV pin may be
shorter than as set during the first interval period.
Remark fSUB: Subsystem clock frequency
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(5) Sub-count register (RSUBC)
The RSUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter. It takes
a value of 0000H to 7FFFH and counts 1 second with a clock of 32.768 kHz.
RSUBC can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Cautions 1. When a correction is made by using the SUBCUD register, the value may become 8000H or
more.
2. This register is also cleared by reset effected by writing the second count register.
3. The value read from this register is not guaranteed if it is read during operation, because a
value that is changing is read.
Figure 7-6. Format of Sub-Count Register (RSUBC)
Address: FFF90H
After reset: 0000H
R
Symbol
7
6
5
4
3
2
1
0
RSUBC
SUBC7
SUBC6
SUBC5
SUBC4
SUBC3
SUBC2
SUBC1
SUBC0
Address: FFF91H
After reset: 0000H
R
Symbol
7
6
5
4
3
2
1
0
RSUBC
SUBC15
SUBC14
SUBC13
SUBC12
SUBC11
SUBC10
SUBC9
SUBC8
(6) Second count register (SEC)
The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of
seconds.
It counts up when the sub-counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later.
Set a decimal value of 00 to 59 to this register in BCD code.
SEC can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-7. Format of Second Count Register (SEC)
Address: FFF92H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
SEC
0
SEC40
SEC20
SEC10
SEC8
SEC4
SEC2
SEC1
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(7) Minute count register (MIN)
The MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes.
It counts up when the second counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later.
Even if the second count register overflows while this register is being written, this register ignores the overflow and
is set to the value written. Set a decimal value of 00 to 59 to this register in BCD code.
MIN can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-8. Format of Minute Count Register (MIN)
Address: FFF93H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
MIN
0
MIN40
MIN20
MIN10
MIN8
MIN4
MIN2
MIN1
(8) Hour count register (HOUR)
The HOUR register is an 8-bit register that takes a value of 00 to 23, or 01 to 12 and 21 to 32 (decimal) and
indicates the count value of hours.
It counts up when the minute counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later.
Even if the minute count register overflows while this register is being written, this register ignores the overflow and
is set to the value written. Set a decimal value of 00 to 23, or 01 to 12 and 21 to 32 to this register in BCD code.
HOUR can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 12H.
However, the value of this register is 00H if the AMPM bit (bit 3 of the RTCC0 register) is set to 1 after reset.
Figure 7-9. Format of Hour Count Register (HOUR)
Address: FFF94H
After reset: 12H
R/W
Symbol
7
6
5
4
3
2
1
0
HOUR
0
0
HOUR20
HOUR10
HOUR8
HOUR4
HOUR2
HOUR1
Caution Bit 5 (HOUR20) of HOUR indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system is selected).
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Table 7-2. Displayed Time Digits
24-Hour Display (AMPM bit = 1)
12-Hour Display (AMPM bit = 0)
Time
HOUR Register
Time
HOUR Register
0
00H
0 a.m.
12H
1
01H
1 a.m.
01H
2
02H
2 a.m.
02H
3
03H
3 a.m.
03H
4
04H
4 a.m.
04H
5
05H
5 a.m.
05H
6
06H
6 a.m.
06H
7
07H
7 a.m.
07H
8
08H
8 a.m.
08H
9
09H
9 a.m.
09H
10
10H
10 a.m.
10H
11
11H
11 a.m.
11H
12
12H
0 p.m.
32H
13
13H
1 p.m.
21H
14
14H
2 p.m.
22H
15
15H
3 p.m.
23H
16
16H
4 p.m.
24H
17
17H
5 p.m.
25H
18
18H
6 p.m.
26H
19
19H
7 p.m.
27H
20
20H
8 p.m.
28H
21
21H
9 p.m.
29H
22
22H
10 p.m.
30H
23
23H
11 p.m.
31H
The HOUR register value is set to 12-hour display when the AMPM bit is “0” and to 24-hour display when the AMPM bit
is “1”.
In 12-hour display, the fifth bit of the HOUR register displays 0 for AM and 1 for PM.
(9) Day count register (DAY)
The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days.
It counts up when the hour counter overflows.
This counter counts as follows.
•
•
•
•
01 to 31 (January, March, May, July, August, October, December)
01 to 30 (April, June, September, November)
01 to 29 (February, leap year)
01 to 28 (February, normal year)
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later.
Even if the hour count register overflows while this register is being written, this register ignores the overflow and is
set to the value written. Set a decimal value of 01 to 31 to this register in BCD code.
DAY can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 01H.
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Figure 7-10. Format of Day Count Register (DAY)
Address: FFF96H
After reset: 01H
R/W
Symbol
7
6
5
4
3
2
1
0
DAY
0
0
DAY20
DAY10
DAY8
DAY4
DAY2
DAY1
(10) Week count register (WEEK)
The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of
weekdays.
It counts up in synchronization with the day counter.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Set a decimal value of 00 to 06 to this register in BCD code.
WEEK can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-11. Format of Week Count Register (WEEK)
Address: FFF95H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
WEEK
0
0
0
0
0
WEEK4
WEEK2
WEEK1
Caution The value corresponding to the month count register or the day count register is not stored in
the week count register automatically. After reset release, set the week count register as follow.
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WEEK
Sunday
00H
Monday
01H
Tuesday
02H
Wednesday
03H
Thursday
04H
Friday
05H
Saturday
06H
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(11) Month count register (MONTH)
The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of
months.
It counts up when the day counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Even if the day count register overflows while this register is being written, this register ignores the overflow
and is set to the value written. Set a decimal value of 01 to 12 to this register in BCD code. Set a decimal value of
01 to 12 to this register in BCD code.
MONTH can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 01H.
Figure 7-12. Format of Month Count Register (MONTH)
Address: FFF97H
After reset: 01H
R/W
Symbol
7
6
5
4
3
2
1
0
MONTH
0
0
0
MONTH10
MONTH8
MONTH4
MONTH2
MONTH1
(12) Year count register (YEAR)
The YEAR register is an 8-bit register that takes a value of 0 to 99 (decimal) and indicates the count value of years.
It counts up when the month counter overflows.
Values 00, 04, 08, …, 92, and 96 indicate a leap year.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Even if the month count register overflows while this register is being written, this register ignores the
overflow and is set to the value written. Set a decimal value of 00 to 99 to this register in BCD code. Set a decimal
value of 00 to 99 to this register in BCD code.
YEAR can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-13. Format of Year Count Register (YEAR)
Address: FFF98H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
YEAR
YEAR80
YEAR40
YEAR20
YEAR10
YEAR8
YEAR4
YEAR2
YEAR1
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(13) Watch error correction register (SUBCUD)
This register is used to correct the watch with high accuracy when it is slow or fast by changing the value
(reference value: 7FFFH) that overflows from the sub-count register (RSUBC) to the second count register.
Rewrite the SUBCUD register after disabling interrupt servicing INTRTC by using the interrupt mask flag register.
Furthermore, after rewriting the SUBCUD register, enable interrupt servicing after clearing the interrupt request
flag (RTCIF) and constant-period interrupt status flag (RIFG).
SUBCUD can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-14. Format of Watch Error Correction Register (SUBCUD)
Address: FFF99H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
SUBCUD
DEV
F6
F5
F4
F3
F2
F1
F0
DEV
Setting of watch error correction timing
0
Corrects watch error when the second digits are at 00, 20, or 40 (every 20 seconds).
1
Corrects watch error only when the second digits are at 00 (every 60 seconds).
Writing to the SUBCUD register at the following timing is prohibited.
• When DEV = 0 is set: For a period of SEC = 00H, 20H, 40H
• When DEV = 1 is set: For a period of SEC = 00H
F6
Setting of watch error correction value
0
Increases by {(F5, F4, F3, F2, F1, F0) – 1} × 2.
1
Decreases by {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} × 2.
When (F6, F5, F4, F3, F2, F1, F0) = (*, 0, 0, 0, 0, 0, *), the watch error is not corrected. * is 0 or 1.
/F5 to /F0 are the inverted values of the corresponding bits (000011 when 111100).
Range of correction value: (when F6 = 0) 2, 4, 6, 8, … , 120, 122, 124
(when F6 = 1) −2, −4, −6, −8, … , −120, −122, −124
The range of value that can be corrected by using the watch error correction register (SUBCUD) is shown below.
DEV = 0 (correction every 20 seconds)
DEV = 1 (correction every 60 seconds)
Correctable range
−189.2 ppm to 189.2 ppm
−63.1 ppm to 63.1 ppm
Maximum excludes
±1.53 ppm
±0.51 ppm
±3.05 ppm
±1.02 ppm
quantization error
Minimum resolution
Remark If a correctable range is −63.1 ppm or lower and 63.1 ppm or higher, set 0 to DEV.
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(14) Alarm minute register (ALARMWM)
This register is used to set minutes of alarm.
ALARMWM can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution
Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set,
the alarm is not detected.
Figure 7-15. Format of Alarm Minute Register (ALARMWM)
Address: FFF9AH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ALARMWM
0
WM40
WM20
WM10
WM8
WM4
WM2
WM1
(15) Alarm hour register (ALARMWH)
This register is used to set hours of alarm.
ALARMWH can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 12H.
However, the value of this register is 00H if the AMPM bit (bit 3 of the RTCC0 register) is set to 1 after reset.
Caution
Set a decimal value of 00 to 23, or 01 to 12 and 21 to 32 to this register in BCD code. If a value
outside the range is set, the alarm is not detected.
Figure 7-16. Format of Alarm Hour Register (ALARMWH)
Address: FFF9BH
After reset: 12H
R/W
Symbol
7
6
5
4
3
2
1
0
ALARMWH
0
0
WH20
WH10
WH8
WH4
WH2
WH1
Caution Bit 5 (WH20) of ALARMWH indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system is selected).
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(16) Alarm week register (ALARMWW)
This register is used to set date of alarm.
ALARMWW can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-17. Format of Alarm Week Register (ALARMWW)
Address: FFF9CH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ALARMWW
0
WW6
WW5
WW4
WW3
WW2
WW1
WW0
Here is an example of setting the alarm.
Time of Alarm
Day
12-Hour Display
Sunday Monday Tuesday Wednesday Thursday Friday Saturday Hour
Hour
24-Hour Display
Hour
Hour
10
1
Minute Minute
10
1
10
1
Minute Minute
10
1
W
W
W
W
W
W
W
W
W
W
W
W
W
W
0
1
2
3
4
5
6
Every day, 0:00 a.m.
1
1
1
1
1
1
1
1
2
0
0
0
0
0
0
Every day, 1:30 a.m.
1
1
1
1
1
1
1
0
1
3
0
0
1
3
0
Every day, 11:59 a.m.
1
1
1
1
1
1
1
1
1
5
9
1
1
5
9
Monday through
0
1
1
1
1
1
0
3
2
0
0
1
2
0
0
Sunday, 1:30 p.m.
1
0
0
0
0
0
0
2
1
3
0
1
3
3
0
Monday, Wednesday,
0
1
0
1
0
1
0
3
1
5
9
2
3
5
9
Friday, 0:00 p.m.
Friday, 11:59 p.m.
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(17) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P30/RTC1HZ/TO00/TI03/INTP1 pin for real-time counter correction clock output, the
P31/RTCDIV/RTCCL/TI00/TO03/PCLBUZ1/INTP2 pin for real-time counter clock output, set PM30, PM31 and the
output latches of P30, P31 to 0.
PM3 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM3 to FFH.
Figure 7-18. Format of Port Mode Register 3 (PM3)
• 78K0R/LF3
Address: FFF23H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM3
1
1
1
1
PM33
PM32
PM31
PM30
• 78K0R/LG3, 78K0R/LH3
Address: FFF23H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM3
1
1
1
PM34
PM33
PM32
PM31
PM30
PM3n
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P3n pin I/O mode selection (n = 0 to 4)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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7.4 Real-Time Counter Operation
7.4.1 Starting operation of real-time counter
Figure 7-19. Procedure for Starting Operation of Real-Time Counter
Start
RTCEN = 1Note1
RTCE = 0
Setting AMPM, CT2 to CT0
Supplies input clock.
Stops counter operation.
Selects 12-/24-hour system and interrupt (INTRTC).
Setting SEC (clearing RSUBC)
Sets second count register.
Setting MIN
Sets minute count register.
Setting HOUR
Sets hour count register.
Setting WEEK
Sets week count register.
Setting DAY
Setting MONTH
Setting YEAR
Sets month count register.
Sets year count register.
Clearing IF flags of interrupt
Clears interrupt request flags (RTCIF, RTCIIF).
Clearing MK flags of interrupt
Clears interrupt mask flags (RTCMK, RTCIMK).
RTCE = 1Note2
No
Sets day count register.
Starts counter operation.
INTRTC = 1?
Yes
Reading counter
Notes 1.
2.
First set RTCEN to 1, while oscillation of the subsystem clock (fSUB) is stable.
Confirm the procedure described in 7.4.2 Shifting to STOP mode after starting operation when shifting
to STOP mode without waiting for INTRTC = 1 after RTCE = 1.
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7.4.2 Shifting to STOP mode after starting operation
Perform one of the following processing when shifting to STOP mode immediately after setting RTCE to 1.
However, after setting RTCE to 1, this processing is not required when shifting to STOP mode after the first INTRTC
interrupt has occurred.
• Shifting to STOP mode when at least two subsystem clocks (fSUB) (about 62 μ s) have elapsed after setting RTCE to 1
(see Figure 7-20, Example 1).
• Checking by polling RWST to become 1, after setting RTCE to 1 and then setting RWAIT to 1. Afterward, setting
RWAIT to 0 and shifting to STOP mode after checking again by polling that RWST has become 0 (see Figure 7-20,
Example 2).
Figure 7-20. Procedure for Shifting to STOP Mode After Setting RTCE to 1
Example 2
Example 1
Sets to counter operation
RTCE = 1
RTCE = 1
Sets to counter operation
start
start
Sets to stop the SEC to YEAR
RWAIT = 1
Waiting at least for 2
STOP mode
counters, reads the counter
value, write mode
fSUB clocks
Shifts to STOP mode
No
RWST = 1 ?
Checks the counter wait status
Yes
RWAIT = 0
No
Sets the counter operation
RWST = 0 ?
Yes
STOP mode
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7.4.3 Reading/writing real-time counter
Read or write the counter after setting 1 to RWAIT first.
Figure 7-21. Procedure for Reading Real-Time Counter
Start
No
RWAIT = 1
Stops SEC to YEAR counters.
Mode to read and write count values
RWST = 1?
Checks wait status of counter.
Yes
Reading SEC
Reads second count register.
Reading MIN
Reads minute count register.
Reading HOUR
Reads hour count register.
Reading WEEK
Reads week count register.
Reading DAY
Reading MONTH
Reading YEAR
RWAIT = 0
No
Reads day count register.
Reads month count register.
Reads year count register.
Sets counter operation.
RWST = 0?Note
Yes
End
Note Be sure to confirm that RWST = 0 before setting STOP mode.
Caution Complete the series of operations of setting RWAIT to 1 to clearing RWAIT to 0 within 1 second.
Remark
SEC, MIN, HOUR, WEEK, DAY, MONTH, and YEAR may be read in any sequence.
All the registers do not have to be set and only some registers may be read.
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Figure 7-22. Procedure for Writing Real-Time Counter
Start
No
RWAIT = 1
Stops SEC to YEAR counters.
Mode to read and write count values
RWST = 1?
Checks wait status of counter.
Yes
Writing SEC
Writes second count register.
Writing MIN
Writes minute count register.
Writing HOUR
Writes hour count register.
Writing WEEK
Writes week count register.
Writing DAY
Writing MONTH
No
Writes day count register.
Writes month count register.
Writing YEAR
Writes year count register.
RWAIT = 0
Sets counter operation.
RWST = 0?Note
Yes
End
Note Be sure to confirm that RWST = 0 before setting STOP mode.
Caution Complete the series of operations of setting RWAIT to 1 to clearing RWAIT to 0 within 1 second.
Remark
SEC, MIN, HOUR, WEEK, DAY, MONTH, and YEAR may be written in any sequence.
All the registers do not have to be set and only some registers may be written.
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7.4.4 Setting alarm of real-time counter
Set time of alarm after setting 0 to WALE first.
Figure 7-23. Alarm Setting Procedure
Start
WALE = 0
Match operation of alarm is invalid.
WALIE = 1
Interrupt is generated when alarm matches.
Setting ALARMWM
Sets alarm minute register.
Setting ALARMWH
Sets alarm hour register.
Setting ALARMWW
Sets alarm week register.
WALE = 1
No
Match operation of alarm is valid.
INTRTC = 1?
Yes
WAFG = 1?
No
Match detection of alarm Yes
Alarm processing
Constant-period interrupt servicing
Remarks 1. ALARMWM, ALARMWH, and ALARMWW may be written in any sequence.
2. Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When using
these two types of interrupts at the same time, which interrupt occurred can be judged by checking the
fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon INTRTC
occurrence.
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7.4.5 1 Hz output of real-time counter
Figure 7-24. 1 Hz Output Setting Procedure
Start
RTCE = 0
RCLOE1 = 1
RTCE = 1
Stops counter operation.
Enables output of RTC1HZ pin (1 Hz).
Starts counter operation.
Output start from RTC1HZ pin
7.4.6 32.768 kHz output of real-time counter
Figure 7-25. 32.768 kHz Output Setting Procedure
Start
RTCE = 0
RCLOE0 = 1
RTCE = 1
Stops counter operation.
Enables output of RTCCL pin (32.768 kHz).
Starts counter operation.
32.768 kHz output start
from RTCCL pin
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7.4.7 512 Hz or 16.384 kHz output of real-time counter
Figure 7-26. 512 Hz or 16.384 kHz Output Setting Procedure
Start
RTCE = 0
512 Hz Output: RCKDIV = 0
16.384 kHz Output: RCKDIV = 1
RCLOE2 = 1
RTCE = 1
Stops counter operation.
Selects output frequency of
RTCDIV pin.
Output of RTCDIV pin is enabled.
Starts counter operation.
512 Hz or 16.384 kHz
output start from RTCDIV pin
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7.4.8 Example of watch error correction of real-time counter
The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction
register.
Example of calculating the correction value
The correction value used when correcting the count value of the sub-count register (RSUBC) is calculated by
using the following expression.
Set DEV to 0 when the correction range is −63.1 ppm or less, or 63.1 ppm or more.
(When DEV = 0)
Correction valueNote = Number of correction counts in 1 minute ÷ 3 = (Oscillation frequency ÷ Target frequency − 1)
¯ 32768 ¯ 60 ÷ 3
(When DEV = 1)
Correction valueNote = Number of correction counts in 1 minute = (Oscillation frequency ÷ Target frequency − 1) ¯
32768 ¯ 60
Note The correction value is the watch error correction value calculated by using bits 6 to 0 of the watch error
correction register (SUBCUD).
(When F6 = 0) Correction value = {(F5, F4, F3, F2, F1, F0) − 1} ¯ 2
(When F6 = 1) Correction value = − {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} ¯ 2
When (F6, F5, F4, F3, F2, F1, F0) is (*, 0, 0, 0, 0, 0, *), watch error correction is not performed. “*” is 0 or 1.
/F5 to /F0 are bit-inverted values (000011 when 111100).
Remarks 1.
2.
The correction value is 2, 4, 6, 8, … 120, 122, 124 or −2, −4, −6, −8, … −120, −122, −124.
The oscillation frequency is the subsystem clock (fSUB).
It can be calculated from the 32.768 kHz output frequency of the RTCCL pin or the output frequency of
the RTC1HZ pin ¯ 32768 when the watch error correction register is set to its initial value (00H).
3.
The target frequency is the frequency resulting after correction performed by using the watch error
correction register.
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Correction example
Example of correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz − 131.2 ppm)
[Measuring the oscillation frequency]
The oscillation frequencyNote of each product is measured by outputting about 32 kHz from the RTCCL pin or
outputting about 1 Hz from the RTC1HZ pin when the watch error correction register is set to its initial value (00H).
Note See 7.4.5 1 Hz output of real-time counter for the setting procedure of outputting about 1 Hz from the RTC1HZ
pin, and 7.4.6 32.768 kHz output of real-time counter for the setting procedure of outputting about 32 kHz from
the RTCCL pin.
[Calculating the correction value]
(When the output frequency from the RTCCL pin is 32772.3 Hz)
If the target frequency is assumed to be 32768 Hz (32772.3 Hz − 131.2 ppm), the correction range for −131.2 ppm is
−63.1 ppm or less, so assume DEV to be 0.
The expression for calculating the correction value when DEV is 0 is applied.
Correction value = Number of correction counts in 1 minute ÷ 3
= (Oscillation frequency ÷ Target frequency − 1) ¯ 32768 ¯ 60 ÷ 3
= (32772.3 ÷ 32768 − 1) ¯ 32768 ¯ 60 ÷ 3
= 86
[Calculating the values to be set to (F6 to F0)]
(When the correction value is 86)
If the correction value is 0 or more (when delaying), assume F6 to be 0.
Calculate (F5, F4, F3, F2, F1, F0) from the correction value.
{(F5, F4, F3, F2, F1, F0) − 1} ¯ 2
= 86
(F5, F4, F3, F2, F1, F0)
= 44
(F5, F4, F3, F2, F1, F0)
= (1, 0, 1, 1, 0, 0)
Consequently, when correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz − 131.2 ppm), setting the correction
register such that DEV is 0 and the correction value is 86 (bits 6 to 0 of SUBCUD: 0101100) results in 32768 Hz (0
ppm).
Figure 7-27 shows the operation when (DEV, F6, F5, F4, F3, F2, F1, F0) is (0, 0, 1, 0, 1, 1, 0, 0).
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Figure 7-27. Operation When (DEV, F6, F5, F4, F3, F2, F1, F0) = (0, 0, 1, 0, 1, 1, 0, 0)
7FFFH + 56H (86)
7FFFH + 56H (86)
7FFFH + 56H (86)
7FFFH+56H (86)
Count start
RSUBC
count value
SEC
0000H
8054H 8055H 0000H 0001H
00
01
7FFFH
0000H 0001H
19
7FFFH 0000H
8054H 8055H
20
0000H 0001H
39
7FFFH 0000H
8054H 8055H
40
0000H 0001H
59
7FFFH 0000H
8054H 8055H
00
CHAPTER 7 REAL-TIME COUNTER
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CHAPTER 7 REAL-TIME COUNTER
Correction example
Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm)
[Measuring the oscillation frequency]
The oscillation frequencyNote of each product is measured by outputting about 32 kHz from the RTCCL pin or
outputting about 1 Hz from the RTC1HZ pin when the watch error correction register is set to its initial value (00H).
Note See 7.4.5 1 Hz output of real-time counter for the setting procedure of outputting about 1 Hz from the RTC1HZ
pin, and 7.4.6 32.768 kHz output of real-time counter for the setting procedure of outputting about 32 kHz from
the RTCCL pin.
[Calculating the correction value]
(When the output frequency from the RTC1Hz pin is 0.9999817 Hz)
Oscillation frequency = 32768 ¯ 0.9999817 ≈ 32767.4 Hz
Assume the target frequency to be 32768 Hz (32767.4 Hz + 18.3 ppm) and DEV to be 1.
The expression for calculating the correction value when DEV is 1 is applied.
Correction value = Number of correction counts in 1 minute
= (Oscillation frequency ÷ Target frequency − 1) ¯ 32768 ¯ 60
= (32767.4 ÷ 32768 − 1) ¯ 32768 ¯ 60
= −36
[Calculating the values to be set to (F6 to F0)]
(When the correction value is −36)
If the correction value is 0 or less (when speeding up), assume F6 to be 1.
Calculate (F5, F4, F3, F2, F1, F0) from the correction value.
− {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} ¯ 2
= −36
(/F5, /F4, /F3, /F2, /F1, /F0)
= 17
(/F5, /F4, /F3, /F2, /F1, /F0)
= (0, 1, 0, 0, 0, 1)
(F5, F4, F3, F2, F1, F0)
= (1, 0, 1, 1, 1, 0)
Consequently, when correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm), setting the correction
register such that DEV is 1 and the correction value is −36 (bits 6 to 0 of SUBCUD: 1101110) results in 32768 Hz (0
ppm).
Figure 7-28 shows the operation when (DEV, F6, F5, F4, F3, F2, F1, F0) is (1, 1, 1, 0, 1, 1, 1, 0).
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Figure 7-28. Operation When (DEV, F6, F5, F4, F3, F2, F1, F0) = (1, 1, 1, 0, 1, 1, 1, 0)
7FFFH − 24H (36)
7FFFH − 24H (36)
Count start
RSUBC
count value
SEC
0000H
7FDAH 7FDBH 0000H 0001H
00
01
7FFFH
0000H 0001H
19
7FFFH 0000H 0001H
20
7FFFH
0000H 0001H
39
7FFFH 0000H 0001H
40
7FFFH
0000H 0001H
59
7FFFH 0000H
7FDAH 7FDBH
00
CHAPTER 7 REAL-TIME COUNTER
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CHAPTER 8 WATCHDOG TIMER
CHAPTER 8 WATCHDOG TIMER
8.1 Functions of Watchdog Timer
The watchdog timer is mounted onto all 78K0R/Lx3 microcontroller products.
The watchdog timer operates on the internal low-speed oscillation clock.
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset
signal is generated.
Program loop is detected in the following cases.
• If the watchdog timer counter overflows
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
• If data other than “ACH” is written to WDTE
• If data is written to WDTE during a window close period
When a reset occurs due to the watchdog timer, bit 4 (WDRF) of the reset control flag register (RESF) is set to 1. For
details of RESF, see CHAPTER 22 RESET FUNCTION.
When 75% of the overflow time is reached, an interval interrupt can be generated.
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8.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Table 8-1. Configuration of Watchdog Timer
Item
Configuration
Control register
Watchdog timer enable register (WDTE)
How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option
byte.
Table 8-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer
Option Byte (000C0H)
Watchdog timer interval interrupt
Bit 7 (WDTINT)
Window open period
Bits 6 and 5 (WINDOW1, WINDOW0)
Controlling counter operation of watchdog timer
Bit 4 (WDTON)
Overflow time of watchdog timer
Bits 3 to 1 (WDCS2 to WDCS0)
Controlling counter operation of watchdog timer
Bit 0 (WDSTBYON)
(in HALT/STOP mode)
Remark For the option byte, see CHAPTER 26 OPTION BYTE.
Figure 8-1. Block Diagram of Watchdog Timer
WDTINT of option
byte (000C0H)
Interval time controller
(Count value overflow time × 3/4)
Interval time interrupt
WDCS2 to WDCS0 of
option byte (000C0H)
fIL
Clock
input
controller
20-bit
counter
fIL/27 to fIL/217
Selector
Reset
output
controller
Count clear
signal
WINDOW1 and
WINDOW0 of option
byte (000C0H)
WDTON of option
byte (000C0H)
Overflow signal
Internal reset signal
Window size
decision signal
Window size check
Watchdog timer enable
register (WDTE)
Write detector to
WDTE except ACH
Internal bus
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8.3 Register Controlling Watchdog Timer
The watchdog timer is controlled by the watchdog timer enable register (WDTE).
(1) Watchdog timer enable register (WDTE)
Writing “ACH” to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 9AH or 1AHNote.
Figure 8-2. Format of Watchdog Timer Enable Register (WDTE)
Address: FFFABH
Symbol
After reset: 9AH/1AHNote
7
6
R/W
5
4
3
2
1
0
WDTE
Note The WDTE reset value differs depending on the WDTON setting value of the option byte (000C0H). To
operate watchdog timer, set WDTON to 1.
WDTON Setting Value
WDTE Reset Value
0 (watchdog timer count operation disabled)
1AH
1 (watchdog timer count operation enabled)
9AH
Cautions 1. If a value other than “ACH” is written to WDTE, an internal reset signal is generated.
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is
generated.
3. The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)).
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8.4 Operation of Watchdog Timer
8.4.1 Controlling operation of watchdog timer
1.
When the watchdog timer is used, its operation is specified by the option byte (000C0H).
• Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the
counter starts operating after a reset release) (for details, see CHAPTER 26).
WDTON
Watchdog Timer Counter
0
Counter operation disabled (counting stopped after reset)
1
Counter operation enabled (counting started after reset)
• Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H) (for details, see 8.4.2
and CHAPTER 26).
• Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (000C0H) (for
details, see 8.4.3 and CHAPTER 26).
2.
After a reset release, the watchdog timer starts counting.
3.
By writing “ACH” to WDTE after the watchdog timer starts counting and before the overflow time set by the option
byte, the watchdog timer is cleared and starts counting again.
4.
After that, write WDTE the second time or later after a reset release during the window open period. If WDTE is
written during a window close period, an internal reset signal is generated.
5.
If the overflow time expires without “ACH” written to WDTE, an internal reset signal is generated.
An internal reset signal is generated in the following cases.
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
• If data other than “ACH” is written to WDTE
Cautions 1. When data is written to WDTE for the first time after reset release, the watchdog timer is cleared
in any timing regardless of the window open time, as long as the register is written before the
overflow time, and the watchdog timer starts counting again.
2. If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow time may be
different from the overflow time set by the option byte by up to 2/fIL seconds.
3. The watchdog timer can be cleared immediately before the count value overflows.
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CHAPTER 8 WATCHDOG TIMER
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending
on the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
WDSTBYON = 0
In HALT mode
WDSTBYON = 1
Watchdog timer operation stops.
Watchdog timer operation continues.
In STOP mode
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short,
an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the
STOP mode release by an interval interrupt.
5. The watchdog timer continues its operation during self-programming of the flash memory and
EEPROMTM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
8.4.2 Setting overflow time of watchdog timer
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts
counting again by writing “ACH” to WDTE during the window open period before the overflow time.
The following overflow time is set.
Table 8-3. Setting of Overflow Time of Watchdog Timer
WDCS2
WDCS1
WDCS0
Overflow Time of Watchdog Timer
(fIL = 33 kHz (MAX.))
7
0
0
0
2 /fIL (3.88 ms)
0
0
1
2 /fIL (7.76 ms)
0
1
0
2 /fIL (15.52 ms)
0
1
1
2 /fIL (31.03 ms)
1
0
0
2 /fIL (124.12 ms)
1
0
1
2 /fIL (496.48 ms)
1
1
0
2 /fIL (992.97 ms)
1
1
1
2 /fIL (3971.88 ms)
8
9
10
12
14
15
17
Caution The watchdog timer continues its operation during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the overflow
time and window size taking this delay into consideration.
Remark
fIL: Internal low-speed oscillation clock frequency
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8.4.3 Setting window open period of watchdog timer
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte
(000C0H). The outline of the window is as follows.
• If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting again.
• Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal reset
signal is generated.
Example: If the window open period is 50%
Counting
starts
Overflow
time
Window close period (50%)
Window close period (50%)
Internal reset signal is generated
if "ACH" is written to WDTE.
Counting starts again when
"ACH" is written to WDTE.
Caution When data is written to WDTE for the first time after reset release, the watchdog timer is cleared in
any timing regardless of the window open time, as long as the register is written before the overflow
time, and the watchdog timer starts counting again.
The window open period to be set is as follows.
Table 8-4. Setting Window Open Period of Watchdog Timer
WINDOW1
WINDOW0
Window Open Period of Watchdog Timer
0
0
Setting prohibited
0
1
50%
1
0
75%
1
1
100%
Cautions 1. The watchdog timer continues its operation during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
2. When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100%
regardless of the values of WINDOW1 and WINDOW0.
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Remark If the overflow time is set to 210/fIL, the window close time and open time are as follows.
(2.7 V ≤ VDD ≤ 5.5 V)
Setting of Window Open Period
50%
75%
100%
Window close time
0 to 18.96 ms
0 to 9.48 ms
None
Window open time
18.96 to 31.03 ms
9.48 to 31.03 ms
0 to 31.03 ms
• Overflow time:
210/fIL (MAX.) = 210/33 kHz (MAX.) = 31.03 ms
• Window close time:
0 to 210/fIL (MIN.) × (1 − 0.5) = 0 to 210/27 kHz (MIN.) × 0.5 = 0 to 18.96 ms
• Window open time:
210/fIL (MIN.) × (1 − 0.5) to 210/fIL (MAX.) = 210/27 kHz (MIN.) × 0.5 to 210/33 kHz (MAX.)
= 18.96 to 31.03 ms
8.4.4 Setting watchdog timer interval interrupt
Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be
generated when 75% of the overflow time is reached.
Table 8-5. Setting of Watchdog Timer Interval Interrupt
WDTINT
Use of Watchdog Timer Interval Interrupt
0
Interval interrupt is used.
1
Interval interrupt is generated when 75% of overflow time is reached.
Caution When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short, an
overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP
mode release by an interval interrupt.
Remark
The watchdog timer continues counting even after INTWDTI is generated (until ACH is written to the WDTE
register). If ACH is not written to the WDTE register before the overflow time, an internal reset signal is
generated.
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CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
9.1 Functions of Clock Output/Buzzer Output Controller
The clock output/buzzer output controller is mounted onto all 78K0R/Lx3 microcontroller products.
The clock output controller is intended for carrier output during remote controlled transmission and clock output for
supply to peripheral ICs.
Buzzer output is a function to output a square wave of buzzer frequency.
One pin can be used to output a clock or buzzer sound.
Two output pins, PCLBUZ0 and PCLBUZ1, are available.
PCLBUZ0 outputs a clock selected by clock output select register 0 (CKS0).
PCLBUZ1 outputs a clock selected by clock output select register 1 (CKS1).
Figure 9-1 shows the block diagram of clock output/buzzer output controller.
Figure 9-1. Block Diagram of Clock Output/Buzzer Output Controller
Internal bus
Clock output select register 1 (CKS1)
PCLOE1
0
fMAIN
0
0
CSEL1 CCS12 CCS11 CCS10
Prescaler
PCLOE1
3
fMAIN/211 to fMAIN/213
fMAIN to fMAIN/24
Selector
5
Clock/buzzer
controller
PCLBUZ1Note/P31/
TI00/TO03/RTCDIV/
RTCCL/INTP2
fSUB to fSUB/27
Output latch
(P31)
fMAIN to fMAIN/24
fSUB to fSUB/27
8
fSUB
PCLOE0
PM31
Clock/buzzer
controller
PCLBUZ0Note/P32/
TI01/TO01/INTP5
8
PCLOE0
Prescaler
0
Selector
fMAIN/211 to fMAIN/213
0
0
Output latch
(P32)
PM32
CSEL0 CCS02 CCS01 CCS00
Clock output select register 0 (CKS0)
Internal bus
Note
The PCLBUZ0 and PCLBUZ1 pins can output a clock of up to 10 MHz at 2.7 V ≤ VDD. Setting a clock
exceeding 5 MHz at VDD < 2.7 V is prohibited.
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CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
9.2 Configuration of Clock Output/Buzzer Output Controller
The clock output/buzzer output controller includes the following hardware.
Table 9-1. Configuration of Clock Output/Buzzer Output Controller
Item
Control registers
Configuration
Clock output select registers 0, 1 (CKS0, CKS1)
Port mode register 3 (PM3)
Port register 3 (P3)
9.3 Registers Controlling Clock Output/Buzzer Output Controller
The following two registers are used to control the clock output/buzzer output controller.
• Clock output select registers 0, 1 (CKS0, CSK1)
• Port mode register 3 (PM3)
(1) Clock output select registers 0, 1 (CKS0, CKS1)
These registers set output enable/disable for clock output or for the buzzer frequency output pin
(PCLBUZ0/PCLBUZ1), and set the output clock.
Select the clock to be output from PCLBUZ0 by using CKS0.
Select the clock to be output from PCLBUZ1 by using CKS1.
CKS0 and CKS1 are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
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Figure 9-2. Format of Clock Output Select Register n (CKSn)
Address: FFFA5H (CKS0), FFFA6H (CKS1)
Symbol
CKSn
After reset: 00H
R/W
6
5
4
3
2
1
0
PCLOEn
0
0
0
CSELn
CCSn2
CCSn1
CCSn0
PCLOEn
PCLBUZn output enable/disable specification
0
Output disable (default)
1
Output enable
CSELn
0
CCSn2
0
CCSn1
0
CCSn0
0
PCLBUZn output clock selection
fMAIN
fMAIN =
fMAIN =
fMAIN =
5 MHz
10 MHz
20 MHz
5 MHz
Note
10 MHz
Setting
prohibited
0
0
0
1
fMAIN/2
0
0
1
0
fMAIN/2
0
1
1
Note
2.5 MHz
5 MHz
10 MHz
2
1.25 MHz
2.5 MHz
5 MHz
fMAIN/2
3
625 kHz
1.25 MHz
2.5 MHz
4
0
1
0
0
fMAIN/2
312.5 kHz
625 kHz
1.25 MHz
0
1
0
1
fMAIN/2
11
2.44 kHz
4.88 kHz
9.76 kHz
0
1
1
0
fMAIN/2
12
1.22 kHz
2.44 kHz
4.88 kHz
13
610 Hz
1.22 kHz
2.44 kHz
0
1
1
1
fMAIN/2
1
0
0
0
fSUB
1
0
0
1
fSUB/2
1
1
0
0
1
1
0
1
32.768 kHz
16.384 kHz
fSUB/2
2
8.192 kHz
fSUB/2
3
4.096 kHz
2.048 kHz
1
1
0
0
fSUB/2
4
1
1
0
1
fSUB/2
5
1.024 kHz
fSUB/2
6
512 Hz
fSUB/2
7
256 Hz
1
1
Note
0
1
1
1
1
0
1
Note
Setting an output clock exceeding 10 MHz is prohibited when 2.7 V ≤ VDD. Setting a clock exceeding 5 MHz at
VDD < 2.7 V is also prohibited.
Cautions 1. Change the output clock after disabling clock output (PCLOEn = 0).
2.
If the selected clock (fMAIN or fSUB) stops during clock output (PCLOEn = 1), the output becomes
undefined.
3.
To shift to STOP mode when the main system clock is selected (CSELn = 0), set PCLOEn = 0
before executing the STOP instruction. When the subsystem clock is selected (CSELn = 1),
PCLOEn = 1 can be set because the clock can be output in STOP mode.
Remarks 1. n = 0, 1
2. fMAIN: Main system clock frequency
3. fSUB: Subsystem clock frequency
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(2) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P31/PCLBUZ1/TI00/TO03/RTCDIV/RTCCL/INTP2 and P32/PCLBUZ0/TI01/TO01/INTP5 pins for
clock output/buzzer output, clear PM31 and PM32 and the output latches of P32 and P31 to 0.
PM3 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 9-3. Format of Port Mode Register 3 (PM3)
Address: FFF23H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM3
1
1
1
PM34
PM33
PM32
PM31
PM30
PM3n
P3n pin I/O mode selection (n = 0 to 4)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
9.4 Operations of Clock Output/Buzzer Output Controller
One pin can be used to output a clock or buzzer sound.
Two output pins, PCLBUZ0 and PCLBUZ1, are available.
PCLBUZ0 outputs a clock/buzzer selected by clock output select register 0 (CKS0).
PCLBUZ1 outputs a clock/buzzer selected by clock output select register 1 (CKS1).
9.4.1 Operation as output pin
PCLBUZn is output as the following procedure.
Select the output frequency with bits 0 to 3 (CCSn0 to CCSn2, CSELn) of the clock output select register (CKSn)
of the PCLBUZn pin (output in disabled status).
Set bit 7 (PCLOEn) of CKSn to 1 to enable clock/buzzer output.
Remark
The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or
disabling clock output (PCLOEn) is switched. At this time, pulses with a narrow width are not output. Figure
9-4 shows enabling or stopping output using PCLOEn and the timing of outputting the clock.
Figure 9-4. Remote Control Output Application Example
PCLOEn
1 clock elapsed
Clock output
Narrow pulses are not recognized
Remark
n = 0, 1
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CHAPTER 10 12-BIT A/D CONVERTER (μ PD78F150xA),
10-BIT A/D CONVERTER (μ PD78F151xA)
78K0R/Lx3
CHAPTER 10 12-BIT A/D CONVERTER (μ PD78F150xA), 10-BIT A/D CONVERTER (μ PD78F151xA)
μ PD78F150xA
Item
A/D converter
μ PD78F151xA
78K0R/LF3
78K0R/LG3
78K0R/LH3
78K0R/LF3
78K0R/LG3
78K0R/LH3
(80 pins)
(100 pins)
(128 pins)
(80 pins)
(100 pins)
(128 pins)
8 ch
Resolution
12 ch
12 bits
8 ch
12 ch
10 bits
10.1 Function of A/D Converter
The A/D converter is a 12-bit resolution or 10-bit resolution converter that converts analog input signals into digital
values, and consists of up to twelve channels of A/D converter analog inputs (ANI0 to ANI10, ANI15).
ANI1, ANI4, and ANI7 are alternatively used with operational amplifier 0, 1, and 2 outputs (AMP0O, AMP1O, and
AMP2O) as pin functions. Accordingly, operational amplifier outputs can be used as analog input sources.
The following four A/D converter operation modes are available.
• Software trigger mode (Continuous conversion mode)
• Software trigger mode (Single conversion mode)
• Timer trigger mode (Continuous conversion mode)
• Timer trigger mode (Single conversion mode)
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Figure 10-1. Block Diagram of 12-Bit A/D Converter (μ PD78F150xA)
Voltage reference
circuit
VRON, VRGV bit
VRSEL bit
ADREFP
AVREFP/VREFOUT
ADCS bit
Sample & hold circuit
ADREF bit
ADREFM
Selector
Successive approximation
register (SAR)
AVREFM/ANI15/P157
AVSS
INTAD
Controller
4
5
ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
ADS3
A/D port configuration
register (ADPC)
ADS2
ADS1
78K0R/LF3:
Timer trigger 0, 1
2
ADS0
ADTMD ADTRS
Analog input channel
specification register (ADS)
ANI0-ANI6, ANI15
78K0R/LG3, 78K0R/LH3: ANI0-ANI10, ANI15
A/D conversion result
register (ADCR)
5
ADCS ADSCM
A/D converter mode
register1 (ADM1)
Internal bus
Remark
Tap selector
Selector
AVSS
Series resistor string
AVDD0
A/D Voltage comparator
FR2
FR1
FR0
LV1
LV0
ADCE
A/D converter mode
register (ADM)
ADREF VRGV
VRON
Analog reference voltage control
register (ADVRC)
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10-BIT A/D CONVERTER (μ PD78F151xA)
ANI0/AMP0-/P20
ANI1/AMP0O/P21
ANI2/AMP0+/P22
ANI3/AMP1-/P23
ANI4/AMP1O/P24
ANI5/AMP1+/P25
ANI6/AMP2-/P26
ANI7/AMP2O/P27
ANI8/AMP2+/P150
ANI9/P151
ANI10/P152
ANI15/AVREFM/P157
78K0R/Lx3
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Figure 10-2.
Block Diagram of 10-Bit A/D Converter (μ PD78F151xA)
Voltage reference
circuit
VRON, VRGV bit
VRSEL bit
ADREFP
AVREFP/VREFOUT
ADCS bit
Sample & hold circuit
AVSS
Successive approximation
register (SAR)
ADREF bit
ADREFM
Selector
Tap selector
Selector
A/D Voltage comparator
Series resistor string
AVDD0
AVREFM/ANI15/P157
AVSS
INTAD
Controller
4
5
ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
ADS3
A/D port configuration
register (ADPC)
ADS2
ADS1
2
ADS0
ADTMD ADTRS
Analog input channel
specification register (ADS)
78K0R/LG3, 78K0R/LH3:
ANI0-ANI6, ANI15
ANI0-ANI10, ANI15
A/D conversion result
register (ADCR)
5
ADCS ADSCM
A/D converter mode
register1 (ADM1)
Internal bus
Remarks 78K0R/LF3:
Timer trigger 0, 1
FR2
FR1
FR0
LV1
LV0
ADCE
A/D converter mode
register (ADM)
VRGV
Analog reference voltage
control register (ADVRC)
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10-BIT A/D CONVERTER (μ PD78F151xA)
ANI0/AMP0-/P20
ANI1/AMP0O/P21
ANI2/AMP0+/P22
ANI3/AMP1-/P23
ANI4/AMP1O/P24
ANI5/AMP1+/P25
ANI6/AMP2-/P26
ANI7/AMP2O/P27
ANI8/AMP2+/P150
ANI9/P151
ANI10/P152
ANI15/AVREFM/P157
CHAPTER 10 12-BIT A/D CONVERTER (μ PD78F150xA),
10-BIT A/D CONVERTER (μ PD78F151xA)
78K0R/Lx3
10.2 Configuration of A/D Converter
The A/D converter includes the following hardware.
(1) ANI0 to ANI10, ANI15 pins
These are the analog input pins of the A/D converter. They input analog signals to be converted into digital signals.
Pins other than the one selected as the analog input pin can be used as I/O port pins.
Remark
78K0R/LF3:
ANI0-ANI6, ANI15
78K0R/LG3, 78K0R/LH3: ANI0-ANI10, ANI15
(2) Sample & hold circuit
The sample & hold circuit samples each of the analog input voltages sequentially sent from the input circuit, and
sends them to the A/D voltage comparator. This circuit also holds the sampled analog input voltage during A/D
conversion.
(3) Series resistor string
The series resistor string is connected between ADREFP and ADREFM, and generates a voltage to be compared with the
sampled voltage value.
Figure 10-3. Circuit Configuration of Series Resistor String
ADREFP
P-ch
ADCS
Series resistor string
ADREFM
(4) Voltage comparator
The voltage comparator compares the sampled voltage value and the output voltage of the series resistor string.
(5) Successive approximation register (SAR)
This register converts the result of comparison by the voltage comparator, starting from the most significant bit (MSB).
When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D conversion),
the contents of the SAR register are transferred to the A/D conversion result register (ADCR).
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10-BIT A/D CONVERTER (μ PD78F151xA)
78K0R/Lx3
(6) 12-bit A/D conversion result register, 10-bit A/D conversion result register (ADCR)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCR register holds the A/D conversion result in its lower 12 bits (the higher 4 bits
are fixed to 0). 10-bit A/D conversion result register does not fix its lower 2 bits.
(7) 8-bit A/D conversion result register (ADCRH)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result.
(8) Controller
This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well
as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller
generates INTAD.
(9) AVDD0, AVDD pin
This pin inputs an analog power to the A/D converter. When one or more of the pins of ports 2 and 15 are used as
the digital port pins, make AVDD0 the same potential as EVDD or VDD.
(10) AVSS pin
This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the VSS pin
even when the A/D converter is not used.
The ground potential (AVSS) can also be used as the negative reference voltage (ADREFM) of the A/D converter. To
use AVSS as ADREFM, clear the ADREF bit of the ADVRC register to 0.
(11) AVREFP/VREFOUT pin
This pin is used to externally input the reference voltage (AVREFP) of the A/D converter or output the voltage (VREFOUT)
generated by the voltage reference.
To use AVREFP as the positive reference voltage (ADREFP) of the A/D converter, clear the VRON bit of the ADVRC
register to 0. To use VREFOUT as ADREFP, set the VRON bit to 1.
The analog signal input to ANI0 to ANI10, ANI15 is converted into a digital signal, based on the voltage applied
across ADREFP and ADREFM.
(12) AVREFM pin
This pin is used to externally input the reference voltage (AVREFM) of the A/D converter. To use AVREFM as the
negative reference voltage (ADREFM) of the A/D converter, set the ADREF bit of the ADVRC register to 1.
Remark
78K0R/LF3:
ANI0-ANI6, ANI15
78K0R/LG3, 78K0R/LH3: ANI0-ANI10, ANI15
(13) AVREF pin
This pin is used to externally input the reference voltage.
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10-BIT A/D CONVERTER (μ PD78F151xA)
78K0R/Lx3
10.3 Registers Used in A/D Converter
The A/D converter uses the following ten registers.
• Peripheral enable register 0 (PER0)
• A/D converter mode register (ADM)
• A/D converter mode register 1 (ADM1)
• Analog reference voltage control register (ADVRC)
• 12-bit A/D conversion result register (ADCR) (μ PD78F150xA only)
• 10-bit A/D conversion result register (ADCR) (μ PD78F151xA only)
• 8-bit A/D conversion result register (ADCRH)
• Analog input channel specification register (ADS)
• A/D port configuration register (ADPC)
• Port mode registers 2, 15 (PM2, PM15)
(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that is
not used is stopped in order to reduce the power consumption and noise.
When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-4. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
Symbol
PER0
After reset: 00H
RTCEN
DACEN
ADCEN
0
R/W
ADCEN
IICAEN
Note
SAU1EN
SAU0EN
TAU1EN
TAU0EN
Control of A/D converter, operational amplifier, and voltage reference input clock
Stops supply of input clock.
• SFR used by the A/D converter, operational amplifier, and voltage reference cannot be written.
• The A/D converter, operational amplifier, and voltage reference is in the reset status.
1
Supplies input clock.
• SFR used by the A/D converter can, operational amplifier, and voltage reference can be
read/written.
Note 78K0R/LG3, 78K0R/LH3 only
Caution When setting the A/D converter, be sure to set ADCEN to 1 first. If ADCEN = 0, writing to a
control register of the A/D converter is ignored, and, even if the register is read, only the default
value is read.
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10-BIT A/D CONVERTER (μ PD78F151xA)
78K0R/Lx3
(2) A/D converter mode register (ADM)
This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
ADM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-5. Format of A/D Converter Mode Register (ADM)
Address: FFF30H
Symbol
ADM
After reset: 00H
6
ADCS
R/W
5
ADSCM
FR2
Note 1
FR1
Note 1
3
FR0
Note 1
2
LV1
A/D conversion operation control
ADCS
0
Stops conversion operation
1
Enables conversion operation
ADSCM
1
Note 1
LV0
Note 1
ADCE
Notes 2, 3, 4
A/D conversion operation mode specification
0
Continuous conversion mode
1
Single conversion mode
A/D voltage comparator operation control
ADCE
Notes 1.
4
0
Stops A/D voltage comparator operation
1
Enables A/D voltage comparator operation
Note 4
For details of FR2 to FR0, LV1, LV0, and A/D conversion, see Table 10-2
A/D Conversion Time
Selection.
2.
When using the A/D converter in timer trigger mode, do not set ADCS to 1. (ADCS automatically switches
to 1 when a timer trigger signal is generated.) However, ADCS may be set to 0 to stop A/D conversion.
3.
Read ADCS to determine whether A/D conversion is under execution.
4.
The operation of the A/D voltage comparator is controlled by ADCS and ADCE, and it takes 1 μs from
operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1 μs or more has elapsed
from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion
result. Otherwise, ignore data of the first conversion.
Table 10-1. Settings of ADCS and ADCE
ADCS
ADCE
A/D Conversion Operation
0
0
Stop status (DC power consumption path does not exist)
0
1
Conversion waiting mode (A/D voltage comparator operation, only comparator
consumes power)
1
0
Setting prohibited
1
1
Conversion mode (A/D voltage comparator operation)
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10-BIT A/D CONVERTER (μ PD78F151xA)
78K0R/Lx3
Figure 10-6. Timing Chart When A/D Voltage Comparator Is Used
A/D voltage comparator operation
ADCE
A/D voltage comparator
Conversion
operation
Conversion
waiting
Conversion
operation
Conversion
stopped
ADCS
Note
Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit
must be 1 μs or longer.
Cautions 1. A/D conversion must be stopped before rewriting bits ADSCM, FR0 to FR2, LV1, and LV0 to
values other than the identical data.
2 When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage mode (LV1 = 1,
LV0 = 0), enable the input gate voltage boost circuit for the A/D converter by using the analog
reference voltage control register (ADVRC), and then set ADCE and ADCS to 1. After the voltage
boost circuit stabilization time (10 μs) passes after the input gate voltage boost circuit for the A/D
converter has been enabled, set ADCS to 1.
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10-BIT A/D CONVERTER (μ PD78F151xA)
78K0R/Lx3
Table 10-2. A/D Conversion Time Selection
A/D Converter Mode Register (ADM)
FR2
FR1
FR0
0
0
0
0
0
1
LV1
0
Mode
Conversion Time Selection
LV0
0
Conversion
Clock (fAD)
fCLK =
fCLK =
fCLK =
fCLK =
1 MHz
8 MHz
10 MHz
20 MHz
Normal
240/fCLK Setting
30 μs
24 μs
12 μs
fCLK/12
mode 1
160/fCLK prohibited
20 μs
16 μs
8 μs
fCLK/8
120/fCLK
15 μs
12 μs
6 μs
fCLK/6
Note 1
0
1
0
0
1
1
100/fCLK
12.5 μs
10 μs
5 μs
fCLK/5
1
0
0
80/fCLK
10 μs
8 μs
Setting
fCLK/4
1
0
1
60/fCLK
7.5 μs
6 μs
prohibited
fCLK/3
1
1
0
40/fCLK
40 μs
5 μs
Setting
fCLK/2
20/fCLK
20 μs
Setting
prohibited
fCLK
1
1
1
prohibited
0
0
0
0
0
1
0
1
Normal
240/fCLK Setting
30 μs
24 μs
12 μs
fCLK/12
mode 2
160/fCLK prohibited
20 μs
16 μs
8 μs
fCLK/8
120/fCLK
15 μs
12 μs
6 μs
fCLK/6
Note 2
0
1
0
0
1
1
100/fCLK
12.5 μs
10 μs
5 μs
fCLK/5
1
0
0
80/fCLK
10 μs
8 μs
Setting
fCLK/4
prohibited
fCLK/3
1
0
1
60/fCLK
7.5 μs
6 μs
1
1
0
40/fCLK
40 μs
5 μs
Setting
fCLK/2
1
1
1
20/fCLK
20 μs
Setting
prohibited
fCLK
prohibited
0
0
0
0
0
1
0
Low
voltage
0
mode
1
1
1
0
0
0
0
1
0
1
1
Note 3
1
300/fCLK Setting
200/fCLK prohibited
37.5 μs
25 μs
30 μs
20 μs
Note 4
15 μs
Note 4
18.8 μs
Note 4
125/fCLK
15.6 μs
Note 4
12.5 μs
100/fCLK
12.5 μs
Note 4
10 μs
9.38 μs
Note 4
Note 4
150/fCLK
75/fCLK
1
1
0
50/fCLK
50 μs
6.25 μs
1
1
1
25/fCLK
25 μs
Setting
Note 4
Note 4
7.5 μs
Note 4
15 μs
Note 4
10 μs
Note 4
7.5 μs
Note 4
6.25 μs
Note 4
fCLK/12
fCLK/8
fCLK/6
fCLK/5
Setting
fCLK/4
prohibited
fCLK/3
Setting
fCLK/2
prohibited
fCLK
prohibited
Other than above
Notes 1.
Setting prohibited
Normal mode 1: 2.7 V ≤ AVDD0 ≤ 5.5 V, when operation of the input gate voltage boost circuit for the A/D
converter is stopped.
2.
Normal mode 2: 2.3 V ≤ AVDD0 ≤ 5.5 V, when operation of the input gate voltage boost circuit for the A/D
converter is operating.
3.
Low voltage mode: 1.8 V ≤ AVDD0 ≤ 5.5 V, when operation of the input gate voltage boost circuit for the A/D
converter is operating.
4.
When TA = 0 to 50°C and 2.3 V ≤ AVDD0 ≤ 3.6 V.
Caution When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage mode (LV1 = 1, LV0
= 0), enable the input gate voltage boost circuit for the A/D converter by using the analog reference
voltage control register (ADVRC), and then set ADCE and ADCS to 1. After the voltage boost circuit
stabilization time (10 μs) passes after the input gate voltage boost circuit for the A/D converter has
been enabled, set ADCS to 1.
Remark
fCLK: CPU/peripheral hardware clock frequency
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10-BIT A/D CONVERTER (μ PD78F151xA)
78K0R/Lx3
Figure 10-7. A/D Converter Sampling and A/D Conversion Timing
ADCS ← 1 or ADS rewrite
ADCS
Sampling
timing
INTAD
Wait period SAR
clear
Sampling
Successive conversion Transfer SAR
to ADCR, clear
INTAD
generation
Conversion time
Sampling
Conversion time
(3) A/D converter mode register 1 (ADM1)
This register sets the A/D conversion start trigger.
ADM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-8. Format of A/D Converter Mode Register 1 (ADM1)
Address: FFF32H
After reset: 00H
R/W
Symbol
6
5
4
3
2
1
0
ADM1
ADTMD
0
0
0
0
0
0
ADTRS
ADTMD
A/D trigger mode selection
0
Software trigger mode
1
Timer trigger mode (hardware trigger mode)
ADTRS
Timer trigger signal selection
0
INTTM02
1
INTTM03
Caution Rewriting ADM1 during A/D conversion is prohibited. Rewrite it when conversion operation is
stopped (ADCS = 0).
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(4) Analog reference voltage control register (ADVRC)
This register is used to select the reference voltage supplies of the A/D and D/A converters, control the operation of the input
gate voltage boost circuit for the A/D converter, and control the voltage reference (VR) operation.
The electrical specifications of the A/D converter can be maintained even during low-voltage operation thanks to the
operation of the input gate voltage boost circuit for the A/D converter.
ADVRC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-9. Format of Analog Reference Voltage Control Register (ADVRC)
Address: FFF36H
Symbol
ADVRC
After reset: 00H
7
R/W
6
ADREF
Note
ADREF
Note
5
0
0
4
0
AVSS
1
AVREFM (external voltage reference input)
Note
VRSEL
2
Note
0
1
VRGV
0
Note
VRON
Note
Negative reference voltage supply selection of A/D converter selection
0
VRSEL
3
VRGV
VRON
Note
Positive
reference voltage
supplies selection
of A/D and D/A
converters
Operation
control of
voltage
reference
Output
voltage
selection of
voltage
reference
Operation
control of input
gate voltage
boost circuit for
A/D converter
Relationship with
the conversion
mode used
2.5 V
Stops
operation
Can be set in
normal mode 1.
2.0 V
Enables
operation
Can be set in
normal mode 2
or low voltage
mode.
AVREFP
(external voltage
reference input)
Stops
operation
(Hi-Z)
VREFOUT
(voltage
reference output)
Stops
operation
(pull-down
output)
2.5 V
Stops
operation
1
Enables
operation
2.5 V
Enables
operation
1
0
Stops
operation
(pull-down
output)
2.0 V
1
1
Enables
operation
2.0 V
0
0
0
0
1
0
1
0
0
1
0
1
1
Other than the above
−
Can be set in
normal mode 2
or low voltage
mode.
−
Can be set in
normal mode 2
or low voltage
mode.
Setting prohibited
Note These bits can be set only for μ PD78F150xA. They are fixed “0” for μ PD78F151xA.
Caution 1. When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage mode (LV1 = 1,
LV0 = 0), enable the input gate voltage boost circuit for the A/D converter by using the analog
reference voltage control register (ADVRC), and then set ADCE and ADCS to 1. After the voltage
boost circuit stabilization time (10 μs) passes after the input gate voltage boost circuit for the A/D
converter has been enabled, set ADCS to 1.
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Cautions 2. To use voltage reference output to the positive reference voltage of the A/D converter, be sure to
set VRON to 1 after setting VRSEL to 1.
3. Do not change the output voltage of the reference voltage by using VRGV during the voltage
reference operation (VRON = 1).
Remark
The combinations of the selectable reference voltage supplies (positive side, negative side) of the A/D
converter are as follows, according to the ADREF, VRSEL and VRON settings.
Table 10-3. Settings of ADREF, VRSEL and VRON
ADREF
VRSEL
VRON
Positive reference voltage of A/D
Negative reference voltage of A/D
converter (ADREFP)
converter (ADREFM)
0
0
0
AVREFP
AVSS
0
1
1
VREFOUT (VR output)
AVSS
1
0
0
AVREFP
AVREFM
1
1
1
VREFOUT (VR output)
AVREFM
(5) 12-bit A/D conversion result register (ADCR) (μ PD78F150xA only)
This register is a 16-bit register that stores the A/D conversion result in the select mode. The higher 4 bits are fixed to
0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register. The
higher 4 bits of the conversion result are stored in FFF1FH and the lower 8 bits are stored in the FFF1EH.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 10-10. Format of 10-bit A/D Conversion Result Register (ADCR)
Address: FFF1EH, FFF1FH
FFF1FH
Symbol
ADCR
After reset: 0000H
0
0
0
R
FFF1EH
0
Caution When writing to A/D converter mode register (ADM), analog input channel specification register
(ADS), and A/D port configuration register (ADPC), the contents of ADCR may become undefined.
Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC.
Using timing other than the above may cause an incorrect conversion result to be read.
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78K0R/Lx3
(6) 10-bit A/D conversion result register (ADCR) (μ PD78F151xA only)
This register is a 16-bit register that stores the A/D conversion result in the select mode. The higher 4 bits are fixed to
0. The lower 2 bits are undefined. Each time A/D conversion ends, the conversion result is loaded from the
successive approximation register. The higher 4 bits of the conversion result are stored in FFF1FH and the lower 8
bits are stored in the FFF1EH.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 10-11. Format of 12-bit A/D Conversion Result Register (ADCR)
Address: FFF1EH, FFF1FH
R
FFF1FH
Symbol
ADCR
After reset: 0000H
0
0
0
FFF1EH
*
0
*
*: Undefined
Caution When writing to A/D converter mode register (ADM), analog input channel specification register
(ADS), and A/D port configuration register (ADPC), the contents of ADCR may become undefined.
Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC.
Using timing other than the above may cause an incorrect conversion result to be read.
(7) 8-bit A/D conversion result register (ADCRH)
This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 12-bit resolution are stored.
ADCRH can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-12. Format of 8-bit A/D Conversion Result Register (ADCRH)
Address: FFF1FHNote
R
FFF1FH
Symbol
ADCRH
After reset: 00H
0
0
0
FFF1EH
0
ADCRH
Note If address FFF1FH is read, the data of ADCRH (lower four bits of FFF1FH and higher four bits of FFF1EH) will
be read.
Caution When writing to A/D converter mode register (ADM), analog input channel specification register
(ADS), and A/D port configuration register (ADPC), the contents of ADCRH may become undefined.
Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC.
Using timing other than the above may cause an incorrect conversion result to be read.
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10-BIT A/D CONVERTER (μ PD78F151xA)
78K0R/Lx3
(8) Analog input channel specification register (ADS)
This register specifies the input channel of the analog voltage to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-13. Format of Analog Input Channel Specification Register (ADS)
Address: FFF31H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ADS
0
0
0
0
ADS3
ADS2
ADS1
ADS0
ADS3
ADS2
ADS1
ADS0
0
0
0
0
ANI0
0
0
0
1
ANI1
0
0
1
0
ANI2
0
0
1
1
ANI3
0
1
0
0
ANI4
0
1
0
1
ANI5
0
1
1
0
ANI6
Note →
0
1
1
1
ANI7
Note →
1
0
0
0
ANI8
Note →
1
0
0
1
ANI9
Note →
1
0
1
0
ANI10
1
1
1
1
ANI15
Other than the above
Analog input channel
Setting prohibited
Note This setting is prohibited for 78K0R/LF3.
Cautions 1. Be sure to clear bits 4 to 7 to “0”.
2 Set a channel to be used for A/D conversion in the input mode by using port mode registers 2
and 15 (PM2, PM15).
3. Do not set the pin that is set by ADPC as digital I/O by ADS.
4. When using an operational amplifier n, the output signal of an operational amplifier n can be
used as an analog input.
Remark
78K0R/LF3:
n = 0, 1
78K0R/LG3, 78K0R/LH3:
n = 0 to 2
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(9) A/D port configuration register (ADPC)
This register switches the ANI0/AMP0-/P20 to ANI7/AMP2O/P27, ANI8/AMP2+/P150 to ANI10/P152 and
ANI15/AVREFM/P157 pins to analog input of A/D converter or digital I/O of port.
ADPC can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 10H.
Remark
78K0R/LF3:
ANI0-ANI6, ANI15
78K0R/LG3, 78K0R/LH3:
ANI0-ANI10, ANI15
Figure 10-14. Format of A/D Port Configuration Register (ADPC)
Address: F0017H
After reset: 10H
R/W
Symbol
7
6
5
4
3
2
1
0
ADPC
0
0
0
ADPC4
ADPC3
ADPC2
ADPC1
ADPC0
ADP ADP ADP ADP ADP
C4
C3
C2
C1
Analog input (A)/digital I/O (D) switching
C0
Port 15
ANI15
ANI10
ANI9
/AVREFM
/P152
/P151
/P157
Port 2
ANI8
ANI7
ANI6
ANI5
ANI4
/AMP2+ /AMP2O /AMP2- /AMP1+ /AMP1O
ANI3
ANI2
ANI1
/AMP1- /AMP0+ /AMP0O
ANI0
/AMP0-
/P150
/P27
/P26
/P25
/P24
/P23
/P22
/P21
/P20
0
0
0
0
0
A
A
A
A
A
A
A
A
A
A
A
A
0
0
0
0
1
A
A
A
A
A
A
A
A
A
A
A
D
0
0
0
1
0
A
A
A
A
A
A
A
A
A
A
D
D
0
0
0
1
1
A
A
A
A
A
A
A
A
A
D
D
D
0
0
1
0
0
A
A
A
A
A
A
A
A
D
D
D
D
0
0
1
0
1
A
A
A
A
A
A
A
D
D
D
D
D
0
0
1
1
0
A
A
A
A
A
A
D
D
D
D
D
D
Note→
0
0
1
1
1
A
A
A
A
A
D
D
D
D
D
D
D
Note→
0
1
0
0
0
A
A
A
A
D
D
D
D
D
D
D
D
Note→
0
1
0
0
1
A
A
A
D
D
D
D
D
D
D
D
D
Note→
0
1
0
1
0
A
A
D
D
D
D
D
D
D
D
D
D
0
1
1
1
1
A
D
D
D
D
D
D
D
D
D
D
D
1
0
0
0
0
D
D
D
D
D
D
D
D
D
D
D
D
Other than the above
Setting prohibited
Note This setting is prohibited for 78K0R/LF3.
Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode registers 2
and 15 (PM2, PM15).
2. Do not set the pin that is set by ADPC as digital I/O by ADS.
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78K0R/Lx3
(10) Port mode registers 2, 15 (PM2, PM15)
When using ANI0/AMP0-/P20 to ANI7/AMP2O/P27, ANI8/AMP2+/P150 to ANI10/P152 and ANI15/AVREFM/P157 pins
for analog input port, set PM20 to PM27, PM150 to PM152, and P157 to 1. The output latches of P20 to P27, P150 to
P152 and P157 at this time may be 0 or 1.
If PM20 to PM27, PM150 to PM152 and PM157 are set to 0, they cannot be used as analog input port pins.
PM2 and PM15 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark
78K0R/LF3:
ANI0-ANI6, ANI15
78K0R/LG3, 78K0R/LH3:
ANI0-ANI10, ANI15
Caution If a pin is set as an analog input port, not the pin level but “0” is always read.
Figure 10-15. Formats of Port Mode Registers 2, 15 (PM2, PM15)
• 78K0R/LF3
Address: FFF22H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM2
1
PM26
PM25
PM24
PM23
PM22
PM21
PM20
Address: FFF2FH
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM15
PM157
1
1
1
1
1
1
1
• 78K0R/LG3, 78K0R/LH3
Address: FFF22H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
Address: FFF2FH
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM15
PM157
1
1
1
1
PM152
PM151
PM150
PMmn
Pmn pin I/O mode selection (mn = 20 to 27, 150 to 152, 157)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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78K0R/Lx3
The ANI0/AMP0-/P20 to ANI7/AMP2O/P27, ANI8/AMP2+/P150 to ANI10/P152 and ANI15/AVREFM/P157 pins are as
shown below depending on the settings of ADPC, ADS, PM2, PM15, OAENn bit and ADREF bit.
Caution
When an operational amplifier is used, pins AMPn+, AMPn−, and AMPnO are used, so the
alternative analog input functions cannot be used. The operational amplifier output signals,
however, can be used as analog inputs.
Table 10-4. Setting Functions of ANI0/AMP0-/P20, ANI2/AMP0+/P22, ANI3/AMP1-/P23, ANI5/AMP1+/P25,
ANI6/AMP2-/P26, and ANI8/AMP2+/P150 Pins
ADPC
PM2 and PM15
register
registers
OAENn bit
ADS register
ANI0/AMP0-/P20, ANI2/AMP0+/P22,
ANI3/AMP1-/P23, ANI5/AMP1+/P25,
ANI6/AMP2-/P26, and
ANI8/AMP2+/P150 Pins
Digital I/O
Input mode
selection
Output mode
Analog input
Input mode
0
−
Digital input
1
−
Setting prohibited
0
−
Digital output
1
−
Setting prohibited
0
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
Operational amplifier input
selection
1
−
Output mode
Remark
78K0R/LF3:
−
Setting prohibited
ANI0/AMP0-/P20, ANI2/AMP0+/P22, ANI3/AMP1-/P23,
ANI5/AMP1+/P25, n = 0, 1
78K0R/LG3, 78K0R/LH3:
ANI0/AMP0-/P20, ANI2/AMP0+/P22, ANI3/AMP1-/P23,
ANI5/AMP1+/P25, ANI6/AMP2-/P26, ANI8/AMP2+/P150, n = 0 to 2
Table 10-5. Setting Functions of ANI1/AMP0O/P21, ANI4/AMP1O/P24, and ANI7/AMP2O/P27 Pins
ADPC
PM2 register
OAENn bit
ADS register
ANI1/AMP0O/P21,
ANI4/AMP1O/P24, and
register
ANI7/AMP2O/P27 Pins
Digital I/O
Input mode
selection
Output mode
Analog input
Input mode
0
−
Digital input
1
−
Setting prohibited
0
−
Digital output
1
−
Setting prohibited
0
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Operational amplifier output (not to
selection
1
be converted)
Does not select ANI.
Operational amplifier output (to be
converted)
Output mode
Remark
−
−
Setting prohibited
78K0R/LF3:
ANI1/AMP0O/P21, ANI4/AMP1O/P24, n = 0, 1
78K0R/LG3, 78K0R/LH3:
ANI1/AMP0O/P21, ANI4/AMP1O/P24, and ANI7/AMP2O/P27, n = 0 to 2
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78K0R/Lx3
Table 10-6. Setting Functions of ANI9/P151 and ANI10/AM152 Pins
ADPC
PM15 register
ADS register
ANI9/P151 and ANI10/AM152 Pins
register
Digital I/O
selection
Analog input
Input mode
−
Digital input
Output mode
−
Digital output
Input mode
selection
Selects ANI.
Analog input (to be A/D converted)
Does not select ANI.
Analog input (not to be A/D
converted)
−
Output mode
Remark
Setting prohibited
78K0R/LF3:
ANI9/P151 and ANI10/AM152 are not mounted.
78K0R/LG3, 78K0R/LH3:
ANI9/P151, ANI10/AM152
Table 10-7. Setting Functions of ANI15/AVREFM/P157 Pin
ADPC
PM15 register
ADREF bit
ADS register
ANI15/AVREFM/P157 Pin
register
Digital I/O
Input mode
selection
Output mode
Analog input
Input mode
0
−
Digital input
1
−
Setting prohibited
0
−
Digital output
1
−
Setting prohibited
0
Selects ANI.
selection
Analog input (to be converted)
Does not select ANI.
−
1
Analog input (not to be converted)
Negative reference voltage input
of A/D converter
Output mode
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−
Setting prohibited
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CHAPTER 10 12-BIT A/D CONVERTER (μ PD78F150xA),
10-BIT A/D CONVERTER (μ PD78F151xA)
10.4 A/D Converter Operations
10.4.1 Basic operations of A/D converter
Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1 to start the supply of the input clock to the A/D
converter.
Set the A/D conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of A/D converter mode register
(ADM), and set the operation mode by using bit 6 (ADMD) of ADM.
Use bits 7, 3, 1, and 0 (ADREF, VRSEL, VRGV, and VRON) of the analog reference voltage control register
(ADVRC) to specify the reference voltage source of the A/D converter and the operation of the input gate voltage
boost circuit for the A/D converter.
Set bit 0 (ADCE) of ADM to 1 to start the operation of the A/D voltage comparator.
Set the channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and set
to input mode by using port mode registers (PM2 and PM15).
Select one channel for A/D conversion using the analog input channel specification register (ADS).
Use the A/D converter mode register 1 (ADM1) to set the trigger mode.
Start the conversion operation by setting bit 7 (ADCS) of ADM to 1, if the software trigger mode has been set in
step .
If timer trigger mode was specified in step , ADCS is automatically set to 1 and A/D conversion starts when
the timer trigger signal is detected.( to are operations performed by hardware.)
The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
sampled voltage is held until the A/D conversion operation has ended.
Bit 11 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2)
AVREF by the tap selector.
The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the
analog input is smaller than (1/2) AVREF, the MSB is reset to 0.
Next, bit 10 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series
resistor string voltage tap is selected according to the preset value of bit 9, as described below.
• Bit 11 = 1: (3/4) AVREF
• Bit 11 = 0: (1/4) AVREF
The voltage tap and sampled voltage are compared and bit 8 of SAR is manipulated as follows.
• Sampled voltage ≥ Voltage tap: Bit 10 = 1
• Sampled voltage < Voltage tap: Bit 10 = 0
Comparison is continued in this way up to bit 0 of SAR.
Upon completion of the comparison of 12 bits, an effective digital result value remains in SAR, and the result
value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
If single conversion mode has been set in step , ADCS is automatically cleared to 0 and enters a wait state
after the first A/D conversion ends.
If the continuous conversion mode has been set in step , repeat steps to . To stop the A/D
converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from . To start A/D conversion again when
ADCE = 0, set ADCE to 1, wait for 1 μs or longer, and start step . To change the channel to be A/D
converted, perform step .
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78K0R/Lx3
Cautions 1. Make sure the period of to is 1 μs or more.
2. To use an operational amplifier output for an analog input, start operating the operational
amplifier before setting the A/D conversion operation (see CHAPTER 12 OPERATIONAL
AMPLIFIER).
Furthermore, do not change the operational amplifier setting during the A/D
conversion operation.
3. To use an output voltage of the voltage reference for a positive reference voltage of A/D
converter, start operating the voltage reference before setting the A/D conversion operation (see
CHAPTER 13 VOLTAGE REFERENCE). Furthermore, do not change the voltage reference setting
during the A/D conversion operation.
4. When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage mode (LV1 = 1,
LV0 = 0), enable the input gate voltage boost circuit for the A/D converter by using the analog
reference voltage control register (ADVRC), and then set ADCE and ADCS to 1. After the voltage
boost circuit stabilization time (10 μs) passes after the input gate voltage boost circuit for the A/D
converter has been enabled, set ADCS to 1.
Remark
Two types of A/D conversion result registers are available.
Reset signal generation clears the A/D
conversion result register (ADCR, ADCRH) to 0000H or 00H.
• ADCR (16 bits): Store 12-bit A/D conversion value
• ADCRH (8 bits): Store 8-bit A/D conversion value
Figure 10-16. Basic Operation of A/D Converter
Conversion time
Sampling time
A/D converter
operation
SAR
Sampling
Undefined
ADCR
A/D conversion
Conversion
result
Conversion
result
INTAD
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10-BIT A/D CONVERTER (μ PD78F151xA)
78K0R/Lx3
10.4.2 Input voltage and conversion results
The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI10, ANI15) and the
theoretical A/D conversion result (stored in the 12-bit A/D conversion result register (ADCR)) is shown by the following
expression.
ADCR = INT (
VAIN
AVREF
× 4096 + 0.5)
or
(ADCR − 0.5) ×
where, INT( ):
AVREF
4096
≤ VAIN < (ADCR + 0.5) ×
AVREF
4096
Function which returns integer part of value in parentheses
VAIN:
Analog input voltage
AVREF:
Reference voltage of A/D converter
ADCR: 12-bit A/D conversion result register (ADCR) value
Remark
78K0R/LF3:
ANI0-ANI6, ANI15
78K0R/LG3, 78K0R/LH3: ANI0-ANI10, ANI15
Figure 10-16 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 10-17. Relationship Between Analog Input Voltage and A/D Conversion Result
SAR
A/D conversion
result
ADCR
4095
0FFFH
4094
0FFEH
4093
0FFDH
3
0003H
2
0002H
1
0001H
0
0000H
1
1
3
2
5
3
8192 4096 8192 4096 8192 4096
8187 4094 8189 4095 8191 1
8192 4096 8192 4096 8192
Input voltage/AVREF
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78K0R/Lx3
10.4.3 A/D converter operation modes
The following four A/D converter operation modes are available.
• Software trigger mode (Continuous conversion mode)
• Software trigger mode (Single conversion mode)
• Timer trigger mode (Continuous conversion mode)
• Timer trigger mode (Single conversion mode)
(1) Software trigger mode (Continuous conversion mode)
By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the
voltage, which is applied to the analog input pin specified by the analog input channel specification register
(ADS), is started.
When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result
register (ADCR, ADCRH), and an interrupt request signal (INTAD) is generated. When one A/D conversion has
been completed, the next A/D conversion operation is immediately started.
If 1 is written to ADCS during A/D conversion, the A/D conversion operation under execution is stopped and
restarted from the beginning. At this time, the conversion result immediately before is retained.
If ADS is rewritten during A/D conversion, the A/D conversion operation under execution is stopped and restarted
from the beginning. At this time, the conversion result immediately before is retained.
If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped.
At this time, the
conversion result immediately before is retained.
Figure 10-18. Software trigger mode (Continuous conversion mode)
ADCS = 1
ADCS = 1
ADCS = 0
ADCS
A/D conversion
is completed
A/D conversion
ANIn
ANIn
Rewriting ADS
ANIn
A/D conversion
is completed
ANIm
ANIm
Conversion operation
under execution is
stopped, and restarted
from the beginning
ADCR,
ADCRH
ANIn
Conversion operation
under execution is
stopped
ANIm
INTAD
Remark
78K0R/LF3:
n = 0 to 6, 15, m = 0 to 6, 15
78K0R/LG3, 78K0R/LH3:
n = 0 to 10, 15, m = 0 to 10, 15
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(2) Software trigger mode (Single conversion mode)
By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the
voltage, which is applied to the analog input pin specified by the analog input channel specification register
(ADS), is started.
When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result
register (ADCR, ADCRH), and an interrupt request signal (INTAD) is generated. When one A/D conversion has
been completed, ADCS is automatically cleared and an A/D conversion wait state is entered.
If 1 is written to ADCS during A/D conversion, the A/D conversion operation under execution is stopped and
restarted from the beginning. At this time, the conversion result immediately before is retained.
If ADS is rewritten during A/D conversion, the A/D conversion operation under execution is stopped and restarted
from the beginning. At this time, the conversion result immediately before is retained.
If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped.
At this time, the
conversion result immediately before is retained.
Figure 10-19. Software trigger mode (Single conversion mode)
ADCS = 1
ADCS = 1
ADCS = 1
ADCS = 1
ADCS = 0
ADCS
A/D conversion
is completed
Rewriting ADS
A/D conversion
is completed
A/D conversion
ANIn
Wait
state
ANIn
ANIn
ANIm
Wait AN
state Im
Conversion operation
under execution is
stopped, and restarted
from the beginning
ADCR,
ADCRH
ANIn
Conversion operation
under execution is
stopped
ANIm
INTAD
Remark
78K0R/LF3:
n = 0 to 6, 15, m = 0 to 6, 15
78K0R/LG3, 78K0R/LH3:
n = 0 to 10, 15, m = 0 to 10, 15
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(3) Timer trigger mode (Continuous conversion mode)
Timer trigger mode is set and a timer trigger wait state is entered by setting bit 7 (ADTMD) of A/D converter mode
register 1 (ADM1) to 1.
When the timer trigger signal is detected, bit 7 (ADCS) of the A/D converter mode register (ADM) is automatically
set to 1 and A/D conversion of the voltage applied to the analog input pin specified using the analog input
channel specification register (ADS) starts.
When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result
register (ADCR, ADCRH), and an interrupt request signal (INTAD) is generated. When one A/D conversion has
been completed, the next A/D conversion operation is immediately started.
If 1 is written to ADS during A/D conversion, the A/D conversion operation under execution is stopped and
restarted from the beginning. At this time, the conversion result immediately before is retained.
If a timer trigger signal is generated during A/D conversion, the A/D conversion operation under execution is
stopped and restarted from the beginning. At this time, the conversion result immediately before is retained.
If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped, and a timer trigger wait
state is entered. At this time, the conversion result immediately before is retained.
When 0 is written to ADTMD while A/D conversion operation is stopped (ADCS = 0), the software trigger mode is
set and A/D conversion operation is not started, even if a timer trigger signal is generated.
Figure 10-20. Timer trigger mode (Continuous conversion mode)
ADTMD = 1
ADTMD = 0
ADTMD
Timer trigger generation
Timer trigger generation
Note
Timer trigger
ADCS = 0
ADCS
A/D conversion
is completed
A/D conversion
Wait
state
ANIn
A/D conversion
is completed
A/D conversion
is completed
Rewriting ADS
ANIn
ANIn
ANIm
Conversion operation under
execution is stopped, and
restarted from the beginning
ADCR,
ADCRH
ANIn
ANIn
ANIm
ANIm
Conversion operation under
execution is stopped, and
restarted from the beginning
Wait
state
Conversion operation
under execution is
stopped
ANIm
INTAD
Note Leave at least enough time for A/D conversion to finish between each generation of the timer trigger signal.
Remark
78K0R/LF3:
n = 0 to 6, 15, m = 0 to 6, 15
78K0R/LG3, 78K0R/LH3:
n = 0 to 10, 15, m = 0 to 10, 15
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(4) Timer trigger mode (Single conversion mode)
Timer trigger mode is set and a timer trigger wait state is entered by setting bit 7 (ADTMD) of A/D converter mode
register 1 (ADM1) to 1.
When the timer trigger signal is detected, bit 7 (ADCS) of the A/D converter mode register (ADM) is automatically
set to 1 and A/D conversion of the voltage applied to the analog input pin specified using the analog input
channel specification register (ADS) starts.
When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result
register (ADCR, ADCRH), and an interrupt request signal (INTAD) is generated. When one A/D conversion has
been completed, ADCS is automatically cleared and a timer trigger wait state is entered.
Even if ADS is rewritten during an A/D conversion operation, the A/D conversion operation performed at that time
is continued. The channel will be switched when the next A/D conversion operation starts.
If a timer trigger signal is generated during A/D conversion, the A/D conversion operation under execution is
stopped and restarted from the beginning. At this time, the conversion result immediately before is retained.
When 0 is written to ADTMD while A/D conversion operation is stopped (ADCS = 0), the software trigger mode is
set and A/D conversion operation is not started, even if a timer trigger signal is generated.
Figure 10-21. Timer trigger mode (Single conversion mode)
ADTMD = 1
ADTMD = 0
Timer trigger generation
ADTMD
Timer trigger generation
Timer trigger generation
Timer trigger generation
Note
Timer trigger
ADCS
A/D conversion
is completed
A/D conversion
Wait
state
ANIn
ANIn
Wait state
Conversion is
not stopped
ADCR,
ADCRH
A/D conversion
is completed
Rewriting A/D conversion
is completed
ADS
ANIn
Wait state
ANIm
ANIm
Wait
state
Conversion operation
under execution is
stopped, and restarted
from the beginning
ANIn
ANIm
INTAD
Note Leave at least enough time for A/D conversion to finish between each generation of the timer trigger signal.
Remark
78K0R/LF3:
n = 0 to 6, 15, m = 0 to 6, 15
78K0R/LG3, 78K0R/LH3:
n = 0 to 10, 15, m = 0 to 10, 15
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The setting methods are described below.
Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1.
Select the conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of A/D converter mode register
(ADM), and select the operation mode by using bit 6 (ADSCM) of ADM.
Use bits 7, 3, 1, and 0 (ADREF, VRSEL, VRGV, and VRON) of the analog reference voltage control register
(ADVRC) to specify the reference voltage source of the A/D converter and the operation of the input gate
voltage boost circuit for the A/D converter.
Set bit 0 (ADCE) of ADM to 1.
Set the channel to be used in the analog input mode by using bits 4 to 0 (ADPC4 to ADPC0) of the A/D port
configuration register (ADPC), bits 7 to 0 (PM27 to PM20) of port mode register 2 (PM2), and bits 7, 2 to 0
(PM157, PM152 to PM150) of port mode register 15 (PM15).
Select a channel to be used by using bits 3 to 0 (ADS3 to ADS0) of the analog input channel specification
register (ADS).
Use bits 0 and 7 (ADTRS, ADTMD) of A/D converter mode register 1 (ADM1) to set the trigger mode.
In the software trigger mode
→ Start A/D conversion by setting bit 7 (ADCS) of ADM to 1.
In the timer trigger mode
→ ADCS is automatically set to 1 and A/D conversion starts when the timer trigger signal is generated.
When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
In the continuous conversion mode
→ Start the next A/D conversion automatically.
In the single conversion mode
→ ADCS is automatically cleared to 0 and the A/D converter goes on standby. To start A/D conversion
operation, go to step .
Note
Change the channel using bits 3 to 0 (ADS3 to ADS0) of ADS to start A/D conversion.
When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
Clear ADCS to 0.
In the software trigger mode
→ Clear ADCE to 0.
In the timer trigger mode
→ Clear ADCE and ADTMD to 0.
Clear bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 0.
Note When in timer trigger mode (single conversion mode), the A/D conversion operation is continued even if bits
3 to 0 of ADS are set during A/D conversion. The channel will be changed when the next A/D conversion
operation starts.
When in any other mode, A/D conversion operation is aborted after bits 3 to 0 of ADS have been set, and
A/D conversion operation is started from the beginning after the channel has been changed.
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Cautions 1. Make sure the period of to is 1 μs or more.
2. may be done between and .
3. can be omitted. However, ignore data of the first conversion after in this case.
4. The period from to differs from the conversion time set using bits 5 to 1 (FR2 to
FR0, LV1, LV0) of ADM. The period from to is the conversion time set using FR2
to FR0, LV1, and LV0.
5. To use an operational amplifier output for an analog input, start operating the operational
amplifier before setting the A/D conversion operation (see CHAPTER 12 OPERATIONAL
AMPLIFIER). Furthermore, do not change the operational amplifier setting during the A/D
conversion operation.
6. To use an output voltage of the voltage reference for a positive reference voltage of A/D
converter, start operating the voltage reference before setting the A/D conversion operation
(see CHAPTER 13 VOLTAGE REFERENCE).
Furthermore, do not change the voltage
reference setting during the A/D conversion operation.
7. When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage mode (LV1
= 1, LV0 = 0), enable the input gate voltage boost circuit for the A/D converter by using the
analog reference voltage control register (ADVRC), and then set ADCE and ADCS to 1. After
the voltage boost circuit stabilization time (10 μs) passes after the input gate voltage boost
circuit for the A/D converter has been enabled, set ADCS to 1.
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10.5 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained.
(1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage
per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is
expressed by %FSR (Full Scale Range).
1LSB is as follows when the resolution is 12 bits.
1LSB = 1/212 = 1/4096
= 0.024 %FSR
Accuracy has no relation to resolution, but is determined by overall error.
(2) Overall error
This shows the maximum error value between the actual measured value and the theoretical value.
Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these
express the overall error.
Note that the quantization error is not included in the overall error in the characteristics table.
(3) Quantization error
When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an analog
input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot be avoided.
Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity
error, and differential linearity error in the characteristics table.
Figure 10-22. Overall Error
Figure 10-23. Quantization Error
1......1
1......1
Overall
error
Digital output
Ideal line
Digital output
1/2LSB
Quantization error
1/2LSB
0......0
AVREF
0
Analog input
0......0
0
Analog input
AVREF
(4) Zero-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (1/2LSB) when the digital output changes from 0......000 to 0......001.
If the actual measurement value is greater than the theoretical value, it shows the difference between the actual
measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes
from 0……001 to 0……010.
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(5) Full-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111.
(6) Integral linearity error
This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses
the maximum value of the difference between the actual measurement value and the ideal straight line when the zeroscale error and full-scale error are 0.
(7) Differential linearity error
While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and
the ideal value.
Figure 10-24. Zero-Scale Error
Figure 10-25. Full-Scale Error
Full-scale error
Ideal line
011
010
001
Zero-scale error
Digital output (Lower 3 bits)
Digital output (Lower 3 bits)
111
000
111
110
101
Ideal line
000
0
1
2
3
AVREF
AVREF−3
0
Analog input (LSB)
AVREF−2
AVREF−1
AVREF
Analog input (LSB)
Figure 10-26. Integral Linearity Error
Figure 10-27. Differential Linearity Error
1......1
1......1
Ideal 1LSB width
Digital output
Digital output
Ideal line
Integral linearity
error
0......0
0
Analog input
Differential
linearity error
0......0
0
AVREF
Analog input
AVREF
(8) Conversion time
This expresses the time from the start of sampling to when the digital output is obtained.
The sampling time is included in the conversion time in the characteristics table.
(9) Sampling time
This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling
time
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10.6 Cautions for A/D Converter
(1) Operating current in STOP mode
Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of the A/D converter mode register
(ADM) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the A/D converter mode register (ADM)
to 0 at the same time.
When using normal mode 2 (LV1 = 0, LV0 = 1) or low voltage mode (LV1 = 1, LV0 = 0), clear bit 1 (VRGV) and bit 0
(VRON) of the analog reference voltage control register (ADVRC) to 0, and then shift to STOP mode.
To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start
operation.
(2) Input range of ANI0 to ANI10, ANI15
Observe the rated range of the ANI0 to ANI10, ANI15 input voltage. If a voltage of AVDD0 or higher and AVSS or lower
(even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that
channel becomes undefined. In addition, the converted values of the other channels may also be affected.
(3) Conflicting operations
Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR or ADCRH read by
instruction upon the end of conversion
ADCR or ADCRH read has priority. After the read operation, the new conversion result is written to ADCR or
ADCRH.
Conflict between ADCR or ADCRH write and A/D converter mode register (ADM) write, analog input channel
specification register (ADS), or A/D port configuration register (ADPC) write upon the end of conversion
ADM, ADS, or ADPC write has priority. ADCR or ADCRH write is not performed, nor is the conversion end
interrupt signal (INTAD) generated.
(4) Noise countermeasures
To maintain the 12-bit resolution, attention must be paid to noise input to the AVREFP pin and pins ANI0 to ANI10,
ANI15.
Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply.
The higher the output impedance of the analog input source, the greater the influence. To reduce the noise,
connecting external C as shown in Figure 10-26 is recommended.
Do not switch these pins with other pins during conversion.
The accuracy is improved if the HALT mode is set immediately after the start of conversion.
Remark
78K0R/LF3:
ANI0-ANI6, ANI15
78K0R/LG3, 78K0R/LH3:
ANI0-ANI10, ANI15
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Figure 10-28. Analog Input Pin Connection
If there is a possibility that noise equal to or higher than AVDD0 or
equal to or lower than AVSS may enter, clamp with a diode with a
small VF value (0.3 V or lower).
Reference
voltage
input
AVREFP
ANI0 to ANI10, ANI15
C = 100 to 1,000 pF
AVSS
VSS
(5) ANI0 to ANI10, ANI15
The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27).
The analog input pins (ANI8 to ANI10, ANI15) are also used as input port pins (P150 to P152, P157).
When A/D conversion is performed with any of ANI0 to ANI10, and ANI15 selected, do not access P20 to P27,
P150 to P152, and P157 while conversion is in progress; otherwise the conversion resolution may be degraded.
It is recommended to select pins used as P20 to P27, P150 to P152, and P157 starting with the ANI0/P20 that
is the furthest from AVDD0.
If the pins adjacent to the pins currently used for A/D conversion are used as digital I/O port, the expected value
of the A/D conversion may not be obtained due to coupling noise. Therefore, make sure that digital pulses are
not input to or output from the pins adjacent to the pin undergoing A/D conversion.
If any pin among pins of ports 2 and 15 is used as digital output port during A/D conversion, the expected value
of the A/D conversion may not be obtained due to coupling noise. Therefore, make sure that digital pulses are
not output to pins of ports 2 and 15 during A/D conversion.
(6) Input impedance of ANI0 to ANI10, ANI15 pins
This A/D converter charges a sampling capacitor for sampling during sampling time.
Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor
flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress,
and on the other states.
To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog
input source to within 1 kΩ, and to connect a capacitor of about 100 pF to the ANI0 to ANI10 and ANI15 pins (see
Figure 10-26).
Remark
78K0R/LF3:
ANI0-ANI6, ANI15
78K0R/LG3, 78K0R/LH3:
ANI0-ANI10, ANI15
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(7) AVREFP pin input impedance
A series resistor string of several tens of kΩ is connected between the AVREFP and AVREFM (or AVSS) pins.
Therefore, if the output impedance of the reference voltage supply is high, this will result in a series connection to the
series resistor string between the AVREFP and AVREFM (or AVSS) pins, resulting in a large reference voltage (AVREF)
error of A/D converter.
(8) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the prechange analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when
ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-change
analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.
Figure 10-29. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite
(start of ANIn conversion)
A/D conversion
ANIn
ADCR
ADS rewrite
(start of ANIm conversion)
ANIn
ANIn
ADIF is set but ANIm conversion
has not ended.
ANIm
ANIn
ANIm
ANIm
ANIm
ADIF
Remark
78K0R/LF3:
n = 0 to 6, 15, m = 0 to 6, 15
78K0R/LG3, 78K0R/LH3:
n = 0 to 10, 15, m = 0 to 10, 15
(9) Conversion results just after A/D conversion start
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS
bit is set to 1 within 1 μs after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take
measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result.
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(10) A/D conversion result register (ADCR, ADCRH) read operation
When a write operation is performed to A/D converter mode register (ADM), A/D converter mode register 1 (ADM1),
analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR
and ADCRH may become undefined. Read the conversion result following conversion completion before writing to
ADM, ADM1, ADS, or ADPC. Using a timing other than the above may cause an incorrect conversion result to be
read.
(11) Internal equivalent circuit
The equivalent circuit of the analog input block is shown below.
Figure 10-30. Internal Equivalent Circuit of ANIn Pin
R1
ANIn
C1
C2
Table 10-8. Resistance and Capacitance Values of Equivalent Circuit (Reference Values)
R1
C1
C2
11.5 kΩ
8.0 pF
8.0 pF
Remarks 1. The resistance and capacitance values shown in Table 10-8 are not guaranteed values.
2. 78K0R/LF3: n = 0 to 6, 15, 78K0R/LG3, 78K0R/LH3: n = 0 to 10, 15
(12) Rewriting DACSWn during A/D conversion
Rewriting DACSWn (n = 0, 1) during A/D conversion is prohibited when both the positive reference voltage of A/D
converter (ADREFP) and the positive reference voltage of the D/A converter (DAREFP) are the voltage reference output
(VREFOUT) (VRSEL = 1 and DAREF = 1). Rewrite it when conversion operation is stopped (ADCS = 0).
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CHAPTER 11 D/A CONVERTER (μ PD78F150xA only)
11.1 Function of D/A Converter
The D/A converter with two channels is mounted onto all 78K0R/Lx3 microcontroller products.
The D/A converter has the following features.
{ 12-bit resolution × 2 channels
{ R-2R ladder method
{ Output analog voltage
•
12-bit resolution: Reference voltage for D/A converter × m12/4096 (m12: Value set to DACSWn register)
•
8-bit resolution: Reference voltage for D/A converter × m8/256 (m8: Value set to DACSn register)
{ Supply voltage for D/A converter:
AVDD1
{ Ground for D/A converter:
AVSS
{ Positive reference voltage for D/A converter:
AVDD1, or AVREFP/VREFOUT
{ Negative reference voltage for D/A converter:
AVSS
{ Operation mode
•
Normal mode
•
Real-time output mode
Remark n = 0, 1
11.2 Configuration of D/A Converter
The D/A converter includes the following hardware.
Table 11-1. Configuration of D/A Converter
Item
Control registers
Configuration
Peripheral enable register 0 (PER0)
D/A converter mode register (DAM)
D/A conversion value setting registers W0, W1 (DACSW0, DACSW1)
D/A conversion value setting registers 0, 1 (DACS0, DACS1)
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Figure 11-1. Block Diagram of D/A Converter
Internal bus
Write signal of DACSW0 register
or write signal of DACS0
DAMD0
INTTM04 signal
DACE0
AVDD1
VRSEL bit
AVREFP/VREFOUT
Selector
ANO0/P110
Voltege reference
circuit
VRON, VRGV bit
D/A conversion value
setting register
(DACSW0 or DACS0)
DARES0
DAREFP
Selector
DAREFM
AVSS
ANO1/P111
Selector
Write signal of DACSW1 register
or write signal of DACS1
DACE1
DAMD1
D/A conversion value
setting register
(DACSW1 or DACS1)
INTTM05 signal
DAREF DACE1 DACE0 DARES1 DARES0 DAMD1 DAMD0
D/A converter mode register (DAM)
Internal bus
Remarks 1. INTTM04 and INTTM05 are timer trigger signals (interrupt signals from timer channels 5 and 6) that are
used in the real-time output mode.
2. Channels 0 and 1 of the D/A converter share the AVREF1 pin and the AVREFP/VREFOUT pin.
3. Channels 0 and 1 of the D/A converter share the AVSS pin. The AVSS pin is also shared with an A/D
converter, an operational amplifier, and a voltage reference.
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11.3 Registers Used in D/A Converter
The D/A converter uses the following four registers.
• Peripheral enable register 0 (PER0)
• D/A converter mode register (DAM)
• D/A conversion value setting registers W0, W1 (DACSW0, DACSW1)
• D/A conversion value setting registers 0, 1 (DACS0, DACS1)
(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that is
not used is stopped in order to reduce the power consumption and noise.
When the D/A converter is used, be sure to set bit 6 (DACEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Cautions When setting the D/A converter, be sure to set DACEN to 1 first. If DACEN = 0, writing to a
control register of the D/A converter is ignored, and, even if the register is read, only the default
value is read.
Figure 11-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
Symbol
PER0
After reset: 00H
RTCEN
R/W
DACEN
ADCEN
DACEN
0
IICAEN
Note
SAU1EN
SAU0EN
TAU1EN
TAU0EN
Control of D/A converter input clock
Stops supply of input clock.
• SFR used by the D/A converter cannot be written.
• The D/A converter is in the reset status.
1
Supplies input clock.
• SFR used by the D/A converter can be read/written.
Note 78K0R/LG3, 78K0R/LH3 only
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(2) D/A converter mode register (DAM)
This register controls the operation of the D/A converter.
DAM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-3. Format of D/A Converter Mode Register (DAM)
Address: FFF5CH
After reset: 00H
R/W
Symbol
7
6
3
2
1
0
DAM
0
DAREF
DACE1
DACE0
DARES1
DARES0
DAMD1
DAMD0
Note1
Positive reference voltage supply selection of D/A converter
DAREF
0
AVDD1 (power supply for D/A converter analog circuit)
1
VREFOUT (voltage reference output)
DACEn
/ AVREFP (external voltage reference input)
D/A conversion operation Control (n = 0, 1)
0
Stops conversion operation
1
Enables conversion operation
DARESn
D/A converter resolution selection (n = 0, 1)
0
8-bit
1
12-bit
DAMDn
Notes 1.
Note2
D/A converter operation mode selection (n = 0, 1)
0
Normal mode
1
Real-time output mode
The reference voltage of the D/A converter cannot be specified separately for each channel because it is
common to both channels.
2.
To use an output voltage of the voltage reference for the positive reference voltage of the D/A converter
(DAREFP), start operating the voltage reference before setting the D/A conversion operation (see CHAPTER
13 VOLTAGE REFERENCE). Furthermore, do not change the voltage reference setting during the D/A
conversion operation.
Remark
The positive reference voltage of the D/A converter is as follows, according to the DAREF, VRSEL and
VRON settings.
Table 11-2. Settings of DAREF, VRSEL and VRON
DAREF
VRSEL
VRON
Positive reference voltage of D/A converter (DAREFP)
0
×
×
AVDD1
1
0
0
AVREFP
1
1
1
VREFOUT
×: don’t care
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(3) D/A conversion value setting registers W0, W1 (DACSW0, DACSW1)
These registers are used to set an analog voltage value to be output to the ANO0 and ANO1 pins, when the D/A
converter is used.
DACSW0 and DACSW1 can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 0000H.
Figure 11-4. Format of D/A Conversion Value Setting Registers W0, W1 (DACSW0, DACSW1)
Address: FFF58H, FFF59H (DACSW0), FFF5AH, FFF5BH (DACSW1)
Symbol
15
14
13
12
DACSWn
0
0
0
0
11
10
9
8
After reset: 0000H
7
6
R/W
5
4
3
2
1
0
DACS DACS DACS DACS DACS DACS DACS DACS DACS DACS DACS DACS
Wn11
Wn10
Wn9
Wn8
Wn7
Wn6
Wn5
Wn4
Wn3
Wn2
Wn1
Wn0
Caution Rewriting DACSWn during A/D conversion is prohibited when both the positive reference voltage of
the A/D converter (ADREFP) and the positive reference voltage of the D/A converter (DAREFP) are the
voltage reference output (VREFOUT) (VRSEL = 1 and DAREF = 1). Rewrite it when conversion operation
is stopped (ADCS = 0).
Remarks 1. The relations between the resolutions and analog output voltages (VANOn) of the D/A converter are as
follows.
• 8-bit resolution (DARESn = 0) :
VANOn = Reference voltage for D/A converter × (DACSWn7 to DACSWn0) /256
• 12-bit resolution (DARESn = 1) :
VANOn = Reference voltage for D/A converter × (DACSWn11 to DACSWn0) /4096
2. n = 0, 1
(4) D/A conversion value setting registers 0, 1 (DACS0, DACS1)
These registers are used to set the analog voltage values to be output to the ANO0 and ANO1 pins when the D/A
converter is used at 8-bit resolution.
DACS0 and DACS1 can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 11-5. Format of D/A Conversion Value Setting Registers 0, 1 (DACS0, DACS1)
Address: FFF58H (DACS0), FFF5AH (DACS1)
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
DACSn
DACSn7
DACSn6
DACSn5
DACSn4
DACSn3
DACSn2
DACSn1
DACSn0
Remarks 1. The relations between the resolutions and analog output voltages (VANOn) of the D/A converter are as
follows.
• 8-bit resolution (DARESn = 0) :
VANOn = Reference voltage for D/A converter × (DACSn7 to DACSn0) /256
2. n = 0, 1
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11.4 Operation of D/A Converter
11.4.1 Operation in normal mode
D/A conversion is performed using write operation to the DACSn register as the trigger.
The setting method is
described below.
Set bit 6 (DACEN) of peripheral enable register 0 (PER0) to 1 to start the supply of the input clock to the D/A
converter.
Set the DAMDn bit of the D/A converter mode register (DAM) to 0 (normal mode).
Use the bit 6 (DAREF) of the DAM register to select the D/A converter reference voltage supply on the positive
side.
Use the DARESn bit of the DAM register to select the resolution of the D/A converter.
Set the analog voltage value to be output to the ANOn pin to the D/A conversion value setting register Wn
(DACSWn) or D/A conversion value setting register n (DACSn).
Steps and above constitute the initial settings.
Set the DACEn bit of the DAM register to 1 (D/A conversion enable).
After the wait time (20 μs or more) elapses, D/A conversion starts, and then, after the settling time (18 μs (max.))
elapses, the D/A converted analog voltage value is output from the ANOn pin.
To perform subsequent D/A conversions, write to the DACSWn or DACSn register.
The previous D/A conversion result is held until the next D/A conversion is performed.
When the DACEn bit of the DAM register is set to 0 (D/A conversion operation stop), D/A conversion stops, the
ANOn pin goes into a high-impedance state when the PM11n bit of the PM11 register = 1 (input mode), and the
ANOn pin outputs the set value of the P11 register when the PM11n bit = 0 (output mode).
Cautions 1. Even if 1, 0, and then 1 is set to the DACEn bit, there is a wait after 1 is set for the last time.
2. If the DACSWn or DACSn register is rewritten during the settling time, D/A conversion is aborted
and reconversion by using the rewritten values starts.
Remark
n = 0, 1
11.4.2 Operation in real-time output mode
D/A conversion is performed using the interrupt request signals (INTTM04 and INTTM05)
Note
of timer channels 4 and 5
as triggers.
The setting method is described below.
Note Channel 0 of the D/A converter: INTTM04
Channel 1 of the D/A converter: INTTM05
Set bit 6 (DACEN) of peripheral enable register 0 (PER0) to 1 to start the supply of the input clock to the D/A
converter.
Set the DAMDn bit of the D/A converter mode register (DAM) to 0 (normal mode).
Use the bit 6 (DAREF) of the DAM register to select the D/A converter reference voltage supply on the positive
side.
Use the DARESn bit of the DAM register to select the resolution of the D/A converter.
Set the analog voltage value to be output to the ANOn pin to the D/A conversion value setting register Wn
(DACSWn) or D/A conversion value setting register n (DACSn).
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Set the DACEn bit of the DAM register to 1 (D/A conversion enable).
After the wait time (20 μs or more) elapses, D/A conversion starts, and then, after the settling time (18 μs (max.))
elapses, the D/A converted analog voltage value is output from the ANOn pin.
Set the DAMDn bit of the DAM register to 1 (real-time output mode).
Steps to above constitute the initial settings.
Operate timer channel m.
Generation of the INTTM0m signals starts D/A conversion and the D/A converted analog voltage value will be
output from the ANOn pin after a settling time (18 μs (max.)) has elapsed.
Afterward, the value set to the DACSWn or DACSn register will be output at the generation timing of the
INTTM0m signals.
Set the analog voltage value to be output to the ANOn pin, to the DACSWn or DACSn register before performing
the next D/A conversion (INTTM0m signal are generated).
When the DACEn bit of the DAM register is set to 0 (D/A conversion operation stop), D/A conversion stops, the
ANOn pin goes into a high-impedance state when the PM11n bit of the PM11 register = 1 (input mode), and the
ANOn pin outputs the set value of the P11 register when the PM11n bit = 0 (output mode).
Cautions 1. Even if 1, 0, and then 1 is set to the DACEn bit, there is a wait after 1 is set for the last time.
2. Make the interval between each generation of the INTTM0m signal longer than the settling time. If
an INTTM0m signal is generated during the settling time, D/A conversion is aborted and
reconversion starts.
3. Even if the generation of the INTTM0m signal and rewriting the DACSWn or DACSn register
conflict, the D/A conversion result is output.
Remark
n = 0, 1
11.5 Cautions for D/A Converter
Observe the following cautions when using the D/A converter.
(1) The digital port I/O function, which is the alternate function of the ANO0 and ANO1 pins, does not operate during D/A
conversion.
When the P11 register is read during D/A conversion, 0 is read in input mode and the set value of the P11 register is
read in output mode. If the digital output mode is set, no output data is output to pins.
(2) The operation of the D/A converter continues in the HALT and STOP mode. To lower the power consumption,
therefore, clear the DACEn bit of the DAM register to 0 (D/A conversion stop), and execute HALT or STOP instruction.
(3) Rewriting DACSWn (n = 0, 1) during A/D conversion is prohibited when both the positive reference voltage of the A/D
converter (ADREFP) and the positive reference voltage of the D/A converter (DAREFP) are the voltage reference output
(VREFOUT) (VRSEL = 1 and DAREF = 1). Rewrite it when conversion operation is stopped (ADCS = 0).
Remark
n = 0, 1, m = 4, 5
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CHAPTER 12 OPERATIONAL AMPLIFIER (μ PD78F150xA only)
78K0R/LF3
78K0R/FG3
78K0R/LH3
(μPD78F150nA: n = 0 to 2)
(μPD78F150nA: n = 3 to 5)
(μPD78F150nA: n = 6 to 8)
80 pins
100 pins
128 pins
Item
Operational
2 ch (operational amplifiers 0, 1)
3 ch (operational amplifiers 0 to 2)
amplifier
12.1 Function of Operational Amplifier
Operational amplifiers are mounted onto products of 78K0R/Lx3 microcontrollers. The operational amplifiers have the
following modes.
• Single AMP mode
The difference in potential of analog voltages input from two pins (AMPn− and AMPn+ pins) is amplified and the
amplified voltage is output from the AMPnO pin.
The amplified voltage can be used as an analog input of the A/D converter, because the AMPnO pin is alternatively
used with analog input pin of the A/D converter.
Remark
78K0R/LF3:
n = 0, 1
78K0R/LG3, 78K0R/LH3:
n = 0 to 2
12.2 Configuration of Operational Amplifier
The operational amplifiers consist of the following hardware.
Table 12-1. Configuration of Operational Amplifiers
Item
Configuration
Operational amplifier input
AMPn- pin, AMPn+ pin
Operational amplifier output
AMPnO pin
Control registers
Peripheral enable register 0 (PER0)
Operational amplifier control register (OAC)
A/D configuration register (ADPC)
Port mode registers 2, 15 (PM2, PM15)
Remark
78K0R/LF3:
n = 0, 1
78K0R/LG3, 78K0R/LH3:
n = 0 to 2
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Figure 12-1. Block Diagram of Operational Amplifier
AMP0O/ANI1/P21
Operational amplifier 0
AMP0-/ANI0/P20
−
AMP0+/ANI2/P22
+
AMP0
To A/D converter
OAEN0 bit
AMP1O/ANI4/P24
Operational amplifier 1
AMP1-/ANI3/P23
−
AMP1+/ANI5/P25
+
AMP1
To A/D converter
OAEN1 bit
AMP2O/ANI7/P27
Operational amplifier 2
AMP2-/ANI6/P26
−
AMP2+/ANI8/P150
+
AMP2
To A/D converter
OAEN2 OAEN1 OAEN0
Operational amplifier control register (OAC)
Internal bus
Remark
78K0R/LF3:
Operational amplifiers 0, 1
78K0R/LG3, 78K0R/LH3:
Operational amplifiers 0 to 2
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12.3 Amplifier Registers Used in Operational Amplifier
The operational amplifiers use the following four registers.
• Peripheral enable register 0 (PER0)
• Operational amplifier control register (OAC)
• A/D port configuration register (ADPC)
• Port mode registers 2, 15 (PM2, PM15)
(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that is
not used is stopped in order to reduce the power consumption and noise.
When the operational amplifier is used, be sure to set bit 5 (ADCEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 12-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
Symbol
After reset: 00H
PER0
RTCEN
ADCEN
DACEN
R/W
ADCEN
IICAEN
Note
SAU1EN
SAU0EN
TAU1EN
TAU0EN
Control of A/D converter, operational amplifier, and voltage reference input clock
Stops input clock supply.
0
• SFR used by the A/D converter, operational amplifier, and voltage reference cannot be
written.
• The A/D converter, operational amplifier, and voltage reference is in the reset status.
Supplies input clock.
1
• SFR used by the A/D converter, operational amplifier, and voltage reference can be read
and written.
Note
78K0R/LG3, 78K0R/LH3 only
Caution When setting operational amplifier, be sure to set ADCEN to 1 first. If ADCEN = 0,
writing to a control register of operational amplifier is ignored, and, even if the register
is read, only the default value is read
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(2) Operational amplifier control register (OAC)
This register controls the operations of operational amplifiers 0 to 2.
OAC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Remark
78K0R/LF3:
Operational amplifiers 0, 1
78K0R/LG3, 78K0R/LH3:
Operational amplifiers 0 to 2
Figure 12-3. Format of Operational Amplifier Control Register (OAC)
Address: FFF33H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
OAC
0
0
0
0
0
OAEN2
OAEN1
OAEN0
OAEN2
Operational amplifier 2 operation control
0
Stops operational amplifier 2 operation
1
Enables operational amplifier 2 operation
OAEN1
Operational amplifier 1 operation control
0
Stops operational amplifier 1 operation
1
Enables operational amplifier 1 operation
OAEN0
Operational amplifier 1 operation control
0
Stops operational amplifier 0 operation
1
Enables operational amplifier 0 operation
Cautions 1. Use the ADPC register to specify as analog inputs the pins to be used with operational
amplifiers.
2. When using as digital inputs the pins of ports 2 and 15, which are not used with operational
amplifiers, when the operational amplifiers are used, make sure that the input levels are fixed.
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(3) A/D port configuration register (ADPC)
This register switches the ANI0/AMP0-/P20 to ANI7/AMP2O/P27, ANI8/AMP2+/P150 to ANI10/P152, and
ANI15/AVREFM/P157 pins to analog input of A/D converter or digital I/O of port. Set pins to be used with operational
amplifiers to the analog input.
ADPC can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 10H.
Remark
78K0R/LF3:
ANI0-ANI6, ANI15
78K0R/LG3, 78K0R/LH3:
ANI0-ANI10, ANI15
Figure 12-4. Format of A/D Port Configuration Register (ADPC)
Address: F0017H
After reset: 10H
R/W
Symbol
7
6
5
4
3
2
1
0
ADPC
0
0
0
ADPC4
ADPC3
ADPC2
ADPC1
ADPC0
ADP ADP ADP ADP ADP
C4
C3
C2
C1
Analog input (A)/digital I/O (D) switching
C0
Port 15
ANI15
ANI10
ANI9
/AVREFM
/P152
/P151
/P157
Port 2
ANI8
ANI7
ANI6
ANI5
ANI4
/AMP2+ /AMP2O /AMP2- /AMP1+ /AMP1O
ANI3
ANI2
ANI1
/AMP1- /AMP0+ /AMP0O
ANI0
/AMP0-
/P150
/P27
/P26
/P25
/P24
/P23
/P22
/P21
/P20
0
0
0
0
0
A
A
A
A
A
A
A
A
A
A
A
A
0
0
0
0
1
A
A
A
A
A
A
A
A
A
A
A
D
0
0
0
1
0
A
A
A
A
A
A
A
A
A
A
D
D
0
0
0
1
1
A
A
A
A
A
A
A
A
A
D
D
D
0
0
1
0
0
A
A
A
A
A
A
A
A
D
D
D
D
0
0
1
0
1
A
A
A
A
A
A
A
D
D
D
D
D
0
0
1
1
0
A
A
A
A
A
A
D
D
D
D
D
D
Note→
0
0
1
1
1
A
A
A
A
A
D
D
D
D
D
D
D
Note→
0
1
0
0
0
A
A
A
A
D
D
D
D
D
D
D
D
Note→
0
1
0
0
1
A
A
A
D
D
D
D
D
D
D
D
D
Note→
0
1
0
1
0
A
A
D
D
D
D
D
D
D
D
D
D
0
1
1
1
1
A
D
D
D
D
D
D
D
D
D
D
D
1
0
0
0
0
D
D
D
D
D
D
D
D
D
D
D
D
Other than the above
Setting prohibited
Note This setting is prohibited for 78K0R/LF3.
Caution Set pins to be used with operational amplifiers in the input mode by using port mode registers 2 and
15 (PM2, PM15).
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(4) Port mode registers 2, 15 (PM2, PM15)
When using ANI0/AMP0-/P20 to ANI7/AMP2O/P27, ANI8/AMP2+/P150 to ANI10/P152 and ANI15/AVREFM/P157 pins
for analog input port, set PM20 to PM27, PM150 to PM152, and P157 to 1. The output latches of P20 to P27, P150 to
P152 and P157 at this time may be 0 or 1.
If PM20 to PM27, PM150 to PM152 and PM157 are set to 0, they cannot be used as analog input port pins.
PM2 and PM15 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark
78K0R/LF3:
ANI0-ANI6, ANI15
78K0R/LG3, 78K0R/LH3:
ANI0-ANI10, ANI15
Caution If a pin is set as an analog input port, not the pin level but “0” is always read.
Figure 12-5. Formats of Port Mode Registers 2, 15 (PM2, PM15)
• 78K0R/LF3
Address: FFF22H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM2
1
PM26
PM25
PM24
PM23
PM22
PM21
PM20
Address: FFF2FH
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM15
PM157
1
1
1
1
1
1
1
• 78K0R/LG3, 78K0R/LH3
Address: FFF22H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
Address: FFF2FH
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM15
PM157
1
1
1
1
PM152
PM151
PM150
PMmn
Pmn pin I/O mode selection (mn = 20 to 27, 150 to 152, 157)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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The ANI0/AMP0-/P20 to ANI7/AMP2O/P27, ANI8/AMP2+/P150 to ANI10/P152 and ANI15/AVREFM/P157 pins are as
shown below depending on the settings of ADPC, ADS, PM2, PM15, OAENn bit and ADREF bit.
Table 12-2. Setting Functions of ANI0/AMP0-/P20, ANI2/AMP0+/P22, ANI3/AMP1-/P23, ANI5/AMP1+/P25,
ANI6/AMP2-/P26, and ANI8/AMP2+/P150 Pins
ADPC
PM2 and PM15
register
registers
OAENn bit
ANI0/AMP0-/P20,
ADS register
ANI2/AMP0+/P22, ANI3/AMP1/P23, ANI5/AMP1+/P25,
ANI6/AMP2-/P26, and
ANI8/AMP2+/P150 Pins
Digital I/O
Input mode
selection
Output mode
Analog input
Input mode
0
−
Digital input
1
−
Setting prohibited
0
−
Digital output
1
−
Setting prohibited
0
selection
1
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
Operational amplifier input
−
Output mode
Remark
Selects ANI.
78K0R/LF3:
−
Setting prohibited
ANI0/AMP0-/P20, ANI2/AMP0+/P22, ANI3/AMP1-/P23,
ANI5/AMP1+/P25, n = 0, 1
78K0R/LG3, 78K0R/LH3:
ANI0/AMP0-/P20, ANI2/AMP0+/P22, ANI3/AMP1-/P23,
ANI5/AMP1+/P25, ANI6/AMP2-/P26, ANI8/AMP2+/P150, n = 0 to 2
Caution When an operational amplifier is used, AMPn+, AMPn−, and AMPnO pins are used, so the alternative
analog input functions cannot be used.
Table 12-3. Setting Functions of ANI1/AMP0O/P21, ANI4/AMP1O/P24, and ANI7/AMP2O/P27 Pins
ADPC
PM2 register
OAENn bit
ANI1/AMP0O/P21,
ADS register
ANI4/AMP1O/P24, and
register
ANI7/AMP2O/P27 Pins
Digital I/O
Input mode
selection
Output mode
Analog input
Input mode
0
−
Digital input
1
−
Setting prohibited
0
−
Digital output
1
−
Setting prohibited
0
selection
1
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Operational amplifier output (not to
be converted)
Does not select ANI.
Operational amplifier output (to be
converted)
Output mode
Remark
−
−
Setting prohibited
78K0R/LF3:
ANI1/AMP0O/P21, ANI4/AMP1O/P24, n = 0, 1
78K0R/LG3, 78K0R/LH3:
ANI1/AMP0O/P21, ANI4/AMP1O/P24, and ANI7/AMP2O/P27, n = 0 to 2
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Caution When an operational amplifier is used, AMPn+, AMPn−, and AMPnO pins are used, so the alternative
analog input functions cannot be used. The operational amplifier output signals, however, can be
used as analog inputs.
Table 12-4. Setting Functions of ANI9/P151 and ANI10/AM152 Pins
ADPC
PM15 register
ADS register
ANI9/P151 and ANI10/AM152 Pins
register
Digital I/O
selection
Analog input
Input mode
−
Digital input
Output mode
−
Digital output
Input mode
selection
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
−
Output mode
Remark
Setting prohibited
78K0R/LF3:
ANI9/P151 and ANI10/AM152 are not mounted.
78K0R/LG3, 78K0R/LH3:
ANI9/P151, ANI10/AM152
Table 12-5. Setting Functions of ANI15/AVREFM/P157 Pin
ADPC
PM15 register
ADREF bit
ADS register
ANI15/AVREFM/P157 Pin
register
Digital I/O
Input mode
selection
Output mode
Analog input
Input mode
0
−
Digital input
1
−
Setting prohibited
0
−
Digital output
1
−
Setting prohibited
0
selection
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
−
1
Negative reference voltage input of
A/D converter
Output mode
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−
Setting prohibited
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12.4 Operational Amplifier Operations
The operational amplifiers 0 to 2 have the following mode.
• Single AMP mode (operational amplifiers 0 to 2)
12.4.1 Single AMP Mode
In single amplifier mode, the difference in potential of analog voltages input from two pins (AMPn− and AMPn+ pins) is
amplified and the amplified voltage is output from the AMPnO pin. The gain is determined by externally connecting a
resistor or the like.
The amplified voltage can be used as an analog input of the A/D converter, because the AMPnO pin is alternatively
used with analog input pin of the A/D converter.
The procedure for starting operation in single amplifier mode is described below.
Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1 to start the supply of the input clock to the operational
amplifier.
Use the A/D port configuration register (ADPC) to set the pins (AMPn−, AMPn+, AMPnO) to be used in single
amplifier mode as analog inputs.
Use the port mode register x (PMx) to set the pins (AMPn−, AMPn+, AMPnO) to be used in single amplifier mode to
input mode.
Set (1) the OAENn bit of operational amplifier control register (OAC) and enable operation in single amplifier mode.
Use software to wait until the operational amplifier stabilizes (turn-on time: 20 μs (MAX.)).
Caution To use as an input of the A/D converter a voltage that has been amplified in single amplifier mode,
enable operation in single amplifier mode before selecting an analog input channel by using the ADS
register.
Remark
78K0R/LF3:
n = 0, 1, x = 2
78K0R/LG3, 78K0R/LH3:
n = 0 to 2, x = 2, 15
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CHAPTER 13 VOLTAGE REFERENCE (μ PD78F150xA only)
13.1 Function of Voltage Reference
The voltage reference is mounted onto all 78K0R/Lx3 microcontroller products.
The Voltage Reference has the
following modes.
• Reference voltage output mode
A reference voltage is output from the VREFOUT pin. Furthermore, the generated reference voltage is supplied to the
internal A/D and D/A converters. 2.0 V (TYP.) or 2.5 V (TYP.) can be selected as the output voltage.
13.2 Configuration of Voltage Reference
The voltage reference consists of the following hardware.
Table 13-1. Configuration of Voltage Reference
Item
Configuration
Reference voltage output
VREFOUT pin
Control registers
Peripheral enable registers 0 (PER0)
Analog reference voltage control register (ADVRC)
Figure 13-1. Block Diagram of Voltage Reference
Positive reference voltage of A/D converter and D/A converter
VREFOUT/AVREFP
Voltage reference
circuit
VRON
VRSEL VRGV
Analog reference voltage control
register (ADVRC)
Internal bus
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13.3 Amplifier Registers Used in Voltage Reference
The voltage reference uses the following two registers.
• Peripheral enable register 0 (PER0)
• Analog reference voltage control register (ADVRC)
(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that is
not used is stopped in order to reduce the power consumption and noise.
When the voltage reference is used, be sure to set bit 5 (ADCEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
Symbol
After reset: 00H
PER0
RTCEN
ADCEN
DACEN
R/W
ADCEN
IICAEN
Note
SAU1EN
SAU0EN
TAU1EN
TAU0EN
Control of A/D converter, operational amplifier, and voltage reference input clock
Stops input clock supply.
0
• SFR used by the A/D converter, operational amplifier, and voltage reference cannot be
written.
• The A/D converter, operational amplifier, and voltage reference is in the reset status.
Supplies input clock.
1
• SFR used by the A/D converter, operational amplifier, and voltage reference can be read
and written.
Note
78K0R/LG3, 78K0R/LH3 only
Caution When setting voltage reference, be sure to set ADCEN to 1 first. If ADCEN = 0, writing to
a control register of voltage reference is ignored, and, even if the register is read, only
the default value is read.
(2) Analog reference voltage control register (ADVRC)
This register is used to select the reference voltage supplies of the A/D and D/A converters, control the operation of
the input gate voltage boost circuit for the A/D converter, and control the voltage reference (VR) operation.
ADVRC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
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Figure 13-3. Format of Analog Reference Voltage Control Register (ADVRC)
Address: FFF36H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ADVRC
ADREF
0
0
0
VRSEL
0
VRGV
VRON
ADREF
Negative reference voltage supply of A/D converter selection
0
AVSS
1
AVREFM (external voltage reference input)
VRSEL
VRGV
VRON
Positive reference
Operation
Output
Operation
Relationship with
voltage supplies
control of
voltage
control of
the conversion
selection of A/D
voltage
selection
input gate
mode used
and D/A
reference
of voltage
voltage
converters
reference
boost
circuit for
A/D
converter
0
0
0
1
0
0
AVREFP
Stops
(external voltage
operation
reference input)
(Hi-Z)
2.5 V
2.0 V
Stops
Can be set in
operation
normal mode 1.
Enables
Can be set in
operation
normal mode 2
or low voltage
mode.
1
0
0
VREFOUT
Stops
(voltage reference
operation
output)
(pull-down
2.5 V
−
Stops
operation
output)
1
0
Enables
1
2.5 V
operation
Enables
Can be set in
operation
normal mode 2
or low voltage
mode.
1
1
Stops
0
−
2.0 V
operation
(pull-down
output)
1
1
Enables
1
operation
2.0 V
Can be set in
normal mode 2
or low voltage
mode.
Other than the above
Setting prohibited
Cautions 1. During voltage reference operation, be sure to connect a tantalum capacitor (capacitance: 10
μF±30 %, ESR: 2 Ω (max.), ESL: 10 nH (max.)) and a ceramic capacitor (capacitance: 0.1 μF±30 %,
ESR: 2 Ω (max.), ESL: 10 nH (max.)) to the VREFOUT/AVREFP pin for stabilizing the reference voltage.
Furthermore, do not apply a voltage from the VREFOUT/AVREFP pin during voltage reference
operation.
2. To use voltage reference output (VREFOUT) to the positive reference voltage of the A/D converter
(ADREFP) and the positive reference voltage of the D/A converter (DAREFP), be sure to set VRON to
1 after setting VRSEL to 1.
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Cautions 3. Rewriting DACSWn (n = 0, 1) during A/D conversion is prohibited when both the positive
reference voltage of the A/D converter (ADREFP) and the positive reference voltage of the D/A
converter (DAREFP) are the voltage reference output (VREFOUT) (VRSEL = 1 and DAREF = 1).
Rewrite it when conversion operation is stopped (ADCS = 0).
4. Do not change the output voltage of the reference voltage by using VRGV during the voltage
reference operation (VRON = 1).
13.4 Voltage Reference Operations
The voltage reference has the following mode.
• Reference voltage output mode
A reference voltage is output from the VREFOUT pin. Furthermore, the generated reference voltage is supplied to the
internal A/D and D/A converters. 2.0 V (TYP.) or 2.5 V (TYP.) can be selected as the output voltage.
13.4.1 Reference voltage output mode
The procedure for starting operation is described below.
Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1 to start the supply of the input clock to the voltage
reference.
Set bit 3 (VRSEL) of the analog reference voltage control register (ADVRC) to 1. The positive reference voltage of
both the A/D and D/A converters or only the A/D converter is set to voltage reference output.
Specify the reference voltage value by using bit 1 (VRGV) of ADVRC.
Enable voltage reference operation by setting bit 0 (VRON) of ADVRC to 1.
Use software to wait until the voltage reference operation stabilizes (settling time: 17 ms (max.)).
13.5 Cautions for Voltage Reference
Observe the following cautions when using the voltage reference.
• The VREFOUT output voltage can be used only as the positive reference voltage of the internal A/D and D/A converters
of the microcontroller. Do not connect an external circuit other than a tantalum capacitor (capacitance: 10 μF±30 %,
ESR: 2 Ω (max.), ESL: 10 nH (max.)) and a ceramic capacitor (capacitance: 0.1 μF±30 %, ESR: 2 Ω (max.), ESL: 10
nH (max.)) to the VREFOUT pin for stabilizing the reference voltage.
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CHAPTER 14 SERIAL ARRAY UNIT
CHAPTER 14 SERIAL ARRAY UNIT
The serial array unit has four serial channels per unit and can use two or more of various serial interfaces (3-wire serial
2
(CSI), UART, and simplified I C) in combination.
Function assignment of each channel supported by the 78K0R/Lx3 microcontrollers is as shown below (channels 2 and
3 of unit 1 are dedicated to UART3 (supporting LIN-bus)).
• 78K0R/LF3
0
1
2
Used as CSI
Used as UART
Used as Simplified I C
2
CSI10
UART1
IIC10
3
−
0
CSI20
1
−
2
−
3
−
Unit
Channel
−
UART2
IIC20
−
UART3 (supporting LIN-bus)
−
−
• 78K0R/LG3
Unit
0
1
Channel
Used as CSI
Used as UART
0
CSI00
UART0
1
−
2
CSI10
3
−
0
CSI20
1
−
2
−
3
−
2
Used as Simplified I C
−
−
UART1
IIC10
−
UART2
IIC20
−
UART3 (supporting LIN-bus)
−
−
• 78K0R/LH3
0
1
2
Used as CSI
Used as UART
Used as Simplified I C
0
CSI00
UART0
−
1
CSI01
2
CSI10
3
−
0
CSI20
1
−
2
−
3
−
Unit
Channel
−
UART1
IIC10
−
UART2
IIC20
−
UART3 (supporting LIN-bus)
−
−
(Example of combination) When “UART0” is used for channels 0 and 1 of unit 0, CSI00 and CSI01 cannot be used,
but CSI10, UART1, or IIC10 can be used.
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CHAPTER 14 SERIAL ARRAY UNIT
14.1 Functions of Serial Array Unit
Each serial interface supported by the 78K0R/Lx3 microcontrollers has the following features.
14.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20)
This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines.
[Data transmission/reception]
• Data length of 7 or 8 bits
• Phase control of transmit/receive data
• MSB/LSB first selectable
• Level setting of transmit/receive data
[Clock control]
• Master/slave selection
• Phase control of I/O clock
• Setting of transfer period by prescaler and internal counter of each channel
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
[Error detection flag]
• Overrun error
14.1.2 UART (UART0, UART1, UART2, UART3)
This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception
(RXD) lines. It transmits or receives data in asynchronization with the party of communication (by using an internal baud
rate). Full-duplex UART communication can be realized by using two channels, one dedicated to transmission (even
channel) and the other to reception (odd channel).
[Data transmission/reception]
• Data length of 5, 7, or 8 bits
• Select the MSB/LSB first
• Level setting of transmit/receive data and select of reverse
• Parity bit appending and parity check functions
• Stop bit appending
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
• Error interrupt in case of framing error, parity error, or overrun error
[Error detection flag]
• Framing error, parity error, or overrun error
The LIN-bus is accepted in UART3 (2 and 3 channels of unit 1)
[LIN-bus functions]
• Wakeup signal detection
• Sync break field (SBF) detection
• Sync field measurement, baud rate calculation
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CHAPTER 14 SERIAL ARRAY UNIT
14.1.3 Simplified I2C (IIC10, IIC20)
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock
(SCL) and serial data (SDA). This simplified I2C is designed for single communication with a device such as EEPROM,
flash memory, or A/D converter, and therefore, it functions only as a master and does not have a function to detect wait
states.
Make sure by using software, as well as operating the control registers, that the AC specifications of the start and stop
conditions are observed.
[Data transmission/reception]
• Master transmission, master reception (only master function with a single master)
• ACK output functionNote and ACK detection function
• Data length of 8 bits (When an address is transmitted, the address is specified by the higher 7 bits, and the least
significant bit is used for R/W control.)
• Manual generation of start condition and stop condition
[Interrupt function]
• Transfer end interrupt
[Error detection flag]
• Parity error (ACK error)
[Functions not supported by simplified I2C]
• Slave transmission, slave reception
• Arbitration loss detection function
• Wait detection functions
Note An ACK is not output when the last data is being received by writing 0 to the SOEmn (SOEm register) bit
and stopping the output of serial communication data. See 14.7.3 (2) Processing flow for details.
Remarks 1. To use an I2C bus of full function, see CHAPTER 15 SERIAL INTERFACE IICA.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 02, 10
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14.2 Configuration of Serial Array Unit
Serial array unit includes the following hardware.
Table 14-1. Configuration of Serial Array Unit
Item
Configuration
Shift register
8 bits
Buffer register
Lower 8 bits of serial data register mn (SDRmn)
Serial clock I/O
SCK00, SCK01, SCK10, SCK20 pins (for 3-wire serial I/O), SCL10, SCL20 pins (for simplified
2
I C)
Serial data input
Note
SI00, SI01, SI10, SI20 pins (for 3-wire serial I/O), RXD0, RXD1, RXD2 pins (for UART),
RXD3 pin (for UART supporting LIN-bus)
Serial data output
SO00, SO01, SO10, SO20 pins (for 3-wire serial I/O), TXD0, TXD1, TXD2 pins (for UART),
TXD3 pin (for UART supporting LIN-bus), output controller
2
Serial data I/O
SDA10, SDA20 pins (for simplified I C)
Control registers
• Peripheral enable register 0 (PER0)
• Serial clock select register m (SPSm)
• Serial channel enable status register m (SEm)
• Serial channel start register m (SSm)
• Serial channel stop register m (STm)
• Serial output enable register m (SOEm)
• Serial output register m (SOm)
• Serial output level register m (SOLm)
• Input switch control register (ISC)
• Noise filter enable register 0 (NFEN0)
• Serial data register mn (SDRmn)
• Serial mode register mn (SMRmn)
• Serial communication operation setting register mn (SCRmn)
• Serial status register mn (SSRmn)
• Serial flag clear trigger register mn (SIRmn)
• Port input mode registers 1, 7 (PIM1, PIM7)
• Port output mode registers 1, 7, 8 (POM1, POM7, POM8)
• Port mode registers 1, 5, 7, 8 (PM1, PM5, PM7, PM8)
• Port registers 1, 5, 7, 8 (P1, P5, P7, P8)
Note The lower 8 bits of the serial data register mn (SDRmn) can be read or written as the following SFR, depending
on the communication mode.
• CSIp communication … SIOp (CSIp data register)
• UARTq reception … RXDq (UARTq receive data register)
• UARTq transmission … TXDq (UARTq transmit data register)
• IICr communication … SIOr (IICr data register)
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
p: CSI number (p = 00, 01, 10, 20), q: UART number (q = 0 to 3), r: IIC number (r = 10, 20)
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CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-1 shows the block diagram of serial array unit 0.
Figure 14-1. Block Diagram of Serial Array Unit 0
Noise filter enable
register 0 (NFEN0)
Serial output register 0 (SO0)
0
Peripheral enable
register 0 (PER0)
0
0
1
0
0
CKO02 CKO01 CKO00
0
0
Serial clock select register 0 (SPS0)
PRS
013
SAU0EN
PRS
012
PRS
011
PRS
002
PRS
003
PRS
010
4
PRS
001
PRS
000
4
fCLK
1
SO02 SO01
SO00
SNFEN SNFEN
10
00
SE03
SE02 SE01
SE00
Serial channel enable
status register 0 (SE0)
SS03
SS02 SS01
SS00
Serial channel start
register 0 (SS0)
ST03
ST02
ST00
Serial channel stop
register 0 (ST0)
0
ST01
0
SOE02 SOE01 SOE00
0
SOL02
Serial output enable
register 0 (SOE0)
Prescaler
fCLK/20 to
fCLK/211
fCLK/20 to fCLK/211
INTTM02
0
Serial output level
register 0 (SOL0)
SOL00
Selector
Selector
Serial data register 00 (SDR00)
CK00
(Clock division setting block)
Serial clock I/O pin
(when CSI00: SCK00)
SCK
Edge
detection
Output latch
(P82)
(Buffer register block)
Serial data output pin
(when CSI00: SO00)
(when UART0: TXD0)
TCLK
Shift register
Output
controller
Interrupt
controller
Communication controller
Noise
elimination
enabled/
disabled
Edge/level
detection
SNFEN00
CKS00 CCS00 STS00 MD002 MD001
Serial mode register 00 (SMR00)
Serial transfer end interrupt
(when CSI00: INTCSI00)
(when UART0: INTST0)
Serial flag clear trigger
register 00 (SIR00)
FECT PECT OVCT
00
00
00
Communication
status
Serial data input pin
(when CSI00: SI00)
(when UART0: RxD0)
Mode selection
CSI00 or UART0
(for transmission)
Output latch
(P80)
PM80
PM82
MCK
Clock controller
Selector
CK01
Selector
Channel 0
Clear
Error controller
Error
information
When UART0
TXE
00
RXE
00
DAP
00
CKP
00
EOC
00
PTC
001
PTC
000
DIR
00
SLC
001
SLC
000
DLS
002
DLS
001
DLS
000
Serial clock I/O pin
(when CSI01: SCK01)
Serial data input pin
(when CSI01: SI01)
Serial data input pin
(when CSI10: SI10)
(when IIC10: SDA10)
(when UART1: RXD1)
OVF
00
Serial data output pin
(when CSI01: SO01)
Mode selection
CSI01 or UART0
(for reception)
Edge/level
detection
Serial transfer end interrupt
(when CSI01: INTCSI01)
(when UART0: INTSR0)
Error controller
CK00
Channel 2
Noise
elimination
enabled/
disabled
PEF
00
Communication controller
CK01
Serial clock I/O pin
(when CSI10: SCK10)
(when IIC10: SCL10)
FEF
00
CK00
Channel 1
Selector
BFF
00
Serial status register 00 (SSR00)
Serial communication operation setting register 00 (SCR00)
CK01
TSF
00
Serial data output pin
(when CSI10: SO10)
(when IIC10: SDA10)
(when UART1: TXD1)
Communication controller
Serial transfer end interrupt
(when CSI10: INTCSI10)
(when IIC10: INTIIC10)
(when UART1: INTST1)
Mode selection
CSI10 or IIC10
or UART1
(for transmission)
Edge/level
detection
Serial transfer error interrupt
(INTSRE0)
SNFEN10
CK01
CK00
Channel 3
Communication controller
When UART1
Edge/level
detection
Mode selection
UART1
(for reception)
Serial transfer end interrupt
(when UART1: INTSR1)
Error controller
Serial transfer error interrupt
(INTSRE1)
Remarks 1. For 78K0R/LF3, the channels 0 and 1 are not mounted.
2. For 78K0R/LG3, CSI01 is not mounted.
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Figure 14-2 shows the block diagram of serial array unit 1.
Figure 14-2. Block Diagram of Serial Array Unit 1
Noise filter enable
register 0 (NFEN0)
Serial output register 1 (SO1)
0
Peripheral enable
register 0 (PER0)
0
0
0
1
1
1
CKO10
0
0
0
0
1
Serial clock select register 1 (SPS1)
PRS
113
SAU1EN
PRS
112
PRS
111
PRS
110
PRS
101
PRS
102
PRS
103
4
PRS
100
4
SNFEN SNFEN
30
20
SO10
SE12 SE11
SE10
Serial channel enable
status register 1 (SE1)
SS13
SS12 SS11
SS10
Serial channel start
register 1 (SS1)
ST13
ST12
ST11
ST10
Serial channel stop
register 1 (ST1)
0
SOE12
0
Serial output enable
SOE10 register 1 (SOE1)
0
SOL12
0
SOL10
fCLK/20 to
fCLK/211
fCLK/20 to fCLK/211
INTTM03
1
SE13
Prescaler
fCLK
SO12
Serial output level
register 1 (SOL1)
Selector
Selector
Serial data register 10 (SDR10)
CK11
(Clock division setting block)
Selector
CK10
Selector
Serial clock I/O pin
(when CSI20: SCK20)
(when IIC20: SCL20)
SCK
Edge
detection
Output latch
(P11 or P12)
(Buffer register block)
Serial data output pin
(when CSI20: SO20)
(when IIC20: SDA20)
(when UART2: TxD2)
TCLK
Shift register
Output
controller
Interrupt
controller
Communication controller
Noise
elimination
enabled/
disabled
Edge/level
detection
SNFEN20
CKS10 CCS10 STS10 MD102 MD101
Serial mode register 10 (SMR10)
Serial transfer end interrupt
(when CSI20: INTCSI20)
(when IIC20: INTIIC20)
(when UART2: INTST2)
Serial flag clear trigger
register 10 (SIR10)
FECT PECT OVCT
10
10
10
Communication
status
Serial data input pin
(when CSI20: SI20)
(when IIC20: SDA20)
(when UART2: RxD2)
Mode selection
CSI20 or IIC20
or UART2
(for transmission)
Output latch
(P10)
PM10
PM11 or PM12
MCK
Clock controller
Channel 0
Clear
Error controller
Error
information
TXE
10
RXE
10
DAP
10
CKP
10
EOC
10
PTC
101
PTC
100
DIR
10
SLC
101
SLC
100
Serial communication operation setting register 10 (SCR10)
CK11
DLS
101
DLS
100
TSF
10
BFF
10
FEF
10
PEF
10
OVF
10
Serial status register 10 (SSR10)
CK10
Channel 1
Communication controller
Mode selection
UART2
(for reception)
When UART2
Edge/level
detection
CK11
Serial transfer end interrupt
(when UART2: INTSR2)
Error controller
Serial transfer error interrupt
(INTSRE2)
CK10
Channel 2 (LIN-bus supported)
Serial data input pin
(when UART3: RxD3)
DLS
102
Communication controller
Serial data output pin
(when UART3: TXD3)
Mode selection
UART3
(for transmission)
Noise
elimination
enabled/
disabled
Serial transfer end interrupt
(when UART3: INTST3)
SNFEN30
CK11
CK10
Channel 3 (LIN-bus supported)
When UART3
Edge/level
detection
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Communication controller
Mode selection
UART3
(for reception)
Serial transfer end interrupt
(when UART3: INTSR3)
Error controller
Serial transfer error interrupt
(INTSRE3)
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CHAPTER 14 SERIAL ARRAY UNIT
(1) Shift register
This is an 8-bit register that converts parallel data into serial data or vice versa.
During reception, it converts data input to the serial pin into parallel data.
When data is transmitted, the value set to this register is output as serial data from the serial output pin.
The shift register cannot be directly manipulated by program.
To read or write the shift register, use the lower 8 bits of serial data register mn (SDRmn).
7
6
5
4
3
2
1
0
Shift register
(2) Lower 8 bits of the serial data register mn (SDRmn)
SDRmn is the transmit/receive data register (16 bits) of channel n. Bits 7 to 0 function as a transmit/receive buffer
register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (MCK).
When data is received, parallel data converted by the shift register is stored in the lower 8 bits. When data is to be
transmitted, set transmit to be transferred to the shift register to the lower 8 bits.
The data stored in the lower 8 bits of this register is as follows, depending on the setting of bits 0 to 2 (DLSmn0 to
DLSmn2) of the SCRmn register, regardless of the output sequence of the data.
• 5-bit data length (stored in bits 0 to 4 of SDRmn register) (settable in UART mode only)
• 7-bit data length (stored in bits 0 to 6 of SDRmn register)
• 8-bit data length (stored in bits 0 to 7 of SDRmn register)
SDRmn can be read or written in 16-bit units.
The lower 8 bits of SDRmn of SDRmn can be read or writtenNote as the following SFR, depending on the
communication mode.
• CSIp communication … SIOp (CSIp data register)
• UARTq reception … RXDq (UARTq receive data register)
Note Writing in 8-bit units is prohibited
• UARTq transmission … TXDq (UARTq transmit data register)
when the operation is stopped
• IICr communication … SIOr (IICr data register)
(SEmn = 0).
Reset signal generation clears this register to 0000H.
Remarks 1. After data is received, “0” is stored in bits 0 to 7 in bit portions that exceed the data length.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
p: CSI number (p = 00, 01, 10, 20), q: UART number (q = 0 to 3), r: IIC number (r = 10, 20)
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Figure 14-3. Format of Serial Data Register mn (SDRmn)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01),
After reset: 0000H
R/W
FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03),
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11),
FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13)
FFF10H (SDR00)
FFF11H (SDR00)
15
14
13
12
11
10
9
SDRmn
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
(m = 0, 1; n = 0 to 3)
Shift register
Caution
Be sure to clear bit 8 to “0”.
Remarks 1. For the function of the higher 7 bits of SDRmn, see 14.3 Registers Controlling Serial Array Unit.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
p: CSI number (p = 00, 01, 10, 20), q: UART number (q = 0 to 3), r: IIC number (r = 10, 20)
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14.3 Registers Controlling Serial Array Unit
Serial array unit is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• Serial clock select register m (SPSm)
• Serial mode register mn (SMRmn)
• Serial communication operation setting register mn (SCRmn)
• Serial data register mn (SDRmn)
• Serial status register mn (SSRmn)
• Serial flag clear trigger register mn (SIRmn)
• Serial channel enable status register m (SEm)
• Serial channel start register m (SSm)
• Serial channel stop register m (STm)
• Serial output enable register m (SOEm)
• Serial output level register m (SOLm)
• Serial output register m (SOm)
• Input switch control register (ISC)
• Noise filter enable register 0 (NFEN0)
• Port input mode registers 1, 7 (PIM1, PIM7)
• Port output mode registers 1, 7, 8 (POM1, POM7, POM8)
• Port mode registers 1, 5, 7, 8 (PM1, PM5, PM7, PM8)
• Port registers 1, 5, 7, 8 (P1, P5, P7, P8)
Remark
m: Unit number (m = 0, 1)
n: Channel number (n = 0 to 3)
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(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that
is not used is stopped in order to reduce the power consumption and noise.
When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of this register to 1.
When serial array unit 1 is used, be sure to set bit 3 (SAU1EN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 14-4. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
Symbol
PER0
After reset: 00H
R/W
RTCEN
DACEN
ADCEN
SAUmEN
0
IICAEN
Note
SAU1EN
SAU0EN
TAU1EN
TAU0EN
Control of serial array unit m input clock
Stops supply of input clock.
• SFR used by serial array unit m cannot be written.
• Serial array unit m is in the reset status.
1
Supplies input clock.
• SFR used by serial array unit m can be read/written.
Note 78K0R/LG3, 78K0R/LH3 only
Cautions 1. When setting serial array unit m, be sure to set SAUmEN to 1 first. If SAUmEN = 0, writing to a
control register of serial array unit m is ignored, and, even if the register is read, only the
default value is read (except for input switch control register (ISC), noise filter enable register
(NFEN0), port input mode registers (PIM1, PIM7), port output mode registers (POM1, POM7,
POM8), port mode registers (PM1, PM5, PM7, PM8), and port registers (P1, P5, P7, P8)).
2. After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Remark m: Unit number (m = 0, 1)
(2) Serial clock select register m (SPSm)
SPSm is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly
supplied to each channel. CKm1 is selected by bits 7 to 4 of SPSm, and CKm0 is selected by bits 3 to 0.
Rewriting SPSm is prohibited when the register is in operation (when SEmn = 1).
SPSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SPSm can be set with an 8-bit memory manipulation instruction with SPSmL.
Reset signal generation clears this register to 0000H.
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Figure 14-5. Format of Serial Clock Select Register m (SPSm)
Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1)
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPSm
0
0
0
0
0
0
0
0
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
m13
m12
m11
m10
m03
m02
m01
m00
PRS
PRS
PRS
PRS
mp3
mp2
mp1
mp0
0
0
0
0
fCLK
0
0
0
1
fCLK/2
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
Section of operation clock (CKmp)
fCLK = 2 MHz
fCLK = 5 MHz
Note 1
fCLK = 10 MHz
fCLK = 20 MHz
2 MHz
5 MHz
10 MHz
20 MHz
1 MHz
2.5 MHz
5 MHz
10 MHz
fCLK/2
2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
fCLK/2
3
250 kHz
625 kHz
1.25 MHz
2.5 MHz
fCLK/2
4
125 kHz
313 kHz
625 kHz
1.25 MHz
fCLK/2
5
62.5 kHz
156 kHz
313 kHz
625 kHz
fCLK/2
6
31.3 kHz
78.1 kHz
156 kHz
313 kHz
0
1
1
1
fCLK/2
7
15.6 kHz
39.1 kHz
78.1 kHz
156 kHz
1
0
0
0
fCLK/2
8
7.81 kHz
19.5 kHz
39.1 kHz
78.1 kHz
fCLK/2
9
3.91 kHz
9.77 kHz
19.5 kHz
39.1 kHz
fCLK/2
10
1.95 kHz
4.88 kHz
9.77 kHz
19.5 kHz
fCLK/2
11
977 Hz
2.44 kHz
4.88 kHz
9.77 kHz
1
1
1
1
0
0
0
1
0
1
1
1
Other than above
1
0
1
1
Note 2
INTTM02 if m = 0, INTTM03 if m = 1
Setting prohibited
Notes 1. When changing the clock selected for fCLK (by changing the system clock control register (CKC) value),
do so after having stopped (STm = 000FH) the operation of the serial array unit (SAUm). When selecting
INTTM02 and INTTM03 for the operation clock, also stop the timer array unit (TAU0) (TT0 = 00FFH).
2. SAUm can be operated at a fixed division ratio of the subsystem clock, regardless of the fCLK frequency
(main system clock, subsystem clock), by operating the interval timer for which fSUB/4 has been selected
as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of the TIS0 register to 1) and selecting
INTTM02 and INTTM03 by using the SPSm register in channels 2 and 3 of TAU0. When changing fCLK,
however, SAUm and TAU0 must be stopped as described in Note 1 above.
Cautions 1. Be sure to clear bits 15 to 8 to “0”.
2. After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Remarks 1. fCLK: CPU/peripheral hardware clock frequency
fSUB: Subsystem clock frequency
2. m: Unit number (m = 0, 1), p = 0, 1
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(3) Serial mode register mn (SMRmn)
SMRmn is a register that sets an operation mode of channel n. It is also used to select an operation clock (MCK),
specify whether the serial clock (SCK) may be input or not, set a start trigger, an operation mode (CSI, UART, or
I2C), and an interrupt source. This register is also used to invert the level of the receive data only in the UART
mode.
Rewriting SMRmn is prohibited when the register is in operation (when SEmn = 1). However, the MDmn0 bit can
be rewritten during operation.
SMRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to 0020H.
Figure 14-6. Format of Serial Mode Register mn (SMRmn) (1/2)
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03),
After reset: 0020H
R/W
F0150H, F0151H (SMR10), F0152H, F0153H (SMR11),
F0154H, F0155H (SMR12), F0156H, F0157H (SMR13)
Symbol
15
14
13
12
11
10
9
8
7
SMRmn
CKS
CCS
0
0
0
0
0
STS
0
mn
mn
CKS
mn
6
5
4
3
SIS
1
0
0
mn0
2
1
0
MD
MD
MD
mn2
mn1
mn0
Selection of operation clock (MCK) of channel n
mn
0
Prescaler output clock CKm0 set by SPSm register
1
Prescaler output clock CKm1 set by SPSm register
Operation clock MCK is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the
higher 7 bits of the SDRmn register, a transfer clock (TCLK) is generated.
CCS
Selection of transfer clock (TCLK) of channel n
mn
0
Divided operation clock MCK specified by CKSmn bit
1
Clock input from SCK pin (slave transfer in CSI mode)
Transfer clock TCLK is used for the shift register, communication controller, output controller, interrupt controller,
and error controller. When CCSmn = 0, the division ratio of MCK is set by the higher 7 bits of the SDRmn register.
STS
Selection of start trigger source
mn
2
0
Only software trigger is valid (selected for CSI, UART transmission, and simplified I C).
1
Valid edge of RXD pin (selected for UART reception)
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
Caution
Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 14-6. Format of Serial Mode Register mn (SMRmn) (2/2)
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03),
After reset: 0020H
R/W
F0150H, F0151H (SMR10), F0152H, F0153H (SMR11),
F0154H, F0155H (SMR12), F0156H, F0157H (SMR13)
Symbol
15
14
13
12
11
10
9
8
7
SMRmn
CKS
CCS
0
0
0
0
0
STS
0
mn
mn
mn
SIS
6
5
4
3
SIS
1
0
0
mn0
2
1
0
MD
MD
MD
mn2
mn1
mn0
Controls inversion of level of receive data of channel n in UART mode
mn0
Falling edge is detected as the start bit.
0
The input communication data is captured as is.
Rising edge is detected as the start bit.
1
The input communication data is inverted and captured.
MD
MD
mn2
mn1
0
0
CSI mode
0
1
UART mode
1
0
Simplified I C mode
1
1
Setting prohibited
Setting of operation mode of channel n
2
MD
Selection of interrupt source of channel n
mn0
0
Transfer end interrupt
1
Buffer empty interrupt
For successive transmission, the next transmit data is written by setting MDmn0 to 1 when SDRmn data has run
out.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(4) Serial communication operation setting register mn (SCRmn)
SCRmn is a communication operation setting register of channel n. It is used to set a data transmission/reception
mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data
length.
Rewriting SCRmn is prohibited when the register is in operation (when SEmn = 1).
SCRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to 0087H.
Figure 14-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/3)
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03),
After reset: 0087H
R/W
F0158H, F0159H (SCR10), F015AH, F015BH (SCR11),
F015CH, F015DH (SCR12), F015EH, F015FH (SCR13)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCRmn
TXE
RXE
DAP
CKP
0
EOC
PTC
PTC
DIR
0
SLC
SLC
0
DLS
DLS
DLS
mn
mn
mn
mn
mn
mn1
mn0
mn
mn1
mn0
mn2
mn1
mn0
TXE
RXE
mn
mn
0
0
Does not start communication.
0
1
Reception only
1
0
Transmission only
1
1
Transmission/reception
DAP
CKP
mn
mn
0
0
Setting of operation mode of channel n
Selection of data and clock phase in CSI mode
Type
SCKp
SOp
1
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SIp input timing
0
1
SCKp
SOp
2
SIp input timing
1
0
SCKp
SOp
3
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SIp input timing
1
1
SCKp
SOp
4
SIp input timing
2
Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode and simplified I C mode.
Caution
Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 20)
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Figure 14-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/3)
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03),
After reset: 0087H
R/W
F0158H, F0159H (SCR10), F015AH, F015BH (SCR11),
F015CH, F015DH (SCR12), F015EH, F015FH (SCR13)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCRmn
TXE
RXE
DAP
CKP
0
EOC
PTC
PTC
DIR
0
SLC
SLC
0
DLS
DLS
DLS
mn
mn
mn
mn
mn
mn1
mn0
mn
mn1
mn0
mn2
mn1
mn0
EOC
Selection of masking of error interrupt signal (INTSREx (x = 0 to 3))
mn
0
Masks error interrupt INTSREx (INTSRx is not masked).
1
Enables generation of error interrupt INTSREx (INTSRx is masked if an error occurs).
2
Set EOCmn = 0 in the CSI mode, simplified I C mode, and during UART transmission.
Note
Set EOCmn = 1 during UART reception.
PTC
PTC
mn1
mn0
0
0
Does not output the parity bit.
Receives without parity
0
1
Outputs 0 parity.
No parity judgment
1
0
Outputs even parity.
Judged as even parity.
1
1
Outputs odd parity.
Judges as odd parity.
Setting of parity bit in UART mode
Transmission
Reception
2
Be sure to set PTCmn1, PTCmn0 = 0, 0 in the CSI mode and simplified I C mode.
DIR
Selection of data transfer sequence in CSI and UART modes
mn
0
Inputs/outputs data with MSB first.
1
Inputs/outputs data with LSB first.
2
Be sure to clear DIRmn = 0 in the simplified I C mode.
SLC
SLC
mn1
mn0
0
0
No stop bit
0
1
Stop bit length = 1 bit
1
0
Stop bit length = 2 bits
1
1
Setting prohibited
Setting of stop bit in UART mode
When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely
transferred.
2
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception and in the simplified I C mode.
Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the CSI mode.
Note When using CSI01 not with EOC01 = 0, error interrupt INTSRE0 may be generated.
Caution
Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 14-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (3/3)
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03),
After reset: 0087H
R/W
F0158H, F0159H (SCR10), F015AH, F015BH (SCR11),
F015CH, F015DH (SCR12), F015EH, F015FH (SCR13)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCRmn
TXE
RXE
DAP
CKP
0
EOC
PTC
PTC
DIR
0
SLC
SLC
0
DLS
DLS
DLS
mn
mn
mn
mn
mn
mn1
mn0
mn
mn1
mn0
mn2
mn1
mn0
DLS
DLS
DLS
mn2
mn1
mn0
1
0
0
5-bit data length (stored in bits 0 to 4 of SDRmn register)
1
1
0
7-bit data length (stored in bits 0 to 6 of SDRmn register)
1
1
1
8-bit data length (stored in bits 0 to 7 of SDRmn register)
Setting of data length in CSI and UART modes
(settable in UART mode only)
Other than above
Setting prohibited
2
Be sure to set DLSmn0 = 1 in the simplified I C mode.
Caution
Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(5) Higher 7 bits of the serial data register mn (SDRmn)
SDRmn is the transmit/receive data register (16 bits) of channel n. Bits 7 to 0 function as a transmit/receive buffer
register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (MCK).
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating clock
by the higher 7 bits of SDRmn is used as the transfer clock.
For the function of the lower 8 bits of SDRmn, see 14.2 Configuration of Serial Array Unit.
SDRmn can be read or written in 16-bit units.
However, the higher 7 bits can be written or read only when the operation is stopped (SEmn = 0). During operation
(SEmn = 1), a value is written only to the lower 8 bits of SDRmn. When SDRmn is read during operation, 0 is
always read.
Reset signal generation clears this register to 0000H.
Figure 14-8. Format of Serial Data Register mn (SDRmn)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01),
After reset: 0000H
R/W
FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03),
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11),
FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13)
FFF11H (SDR00)
Symbol
15
14
13
12
11
10
9
SDRmn
FFF10H (SDR00)
8
7
6
5
4
3
2
1
0
0
SDRmn[15:9]
Transfer clock setting by dividing the operating clock (MCK)
0
0
0
0
0
0
0
MCK/2
0
0
0
0
0
0
1
MCK/4
0
0
0
0
0
1
0
MCK/6
0
0
0
0
0
1
1
MCK/8
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
0
MCK/254
1
1
1
1
1
1
1
MCK/256
Cautions 1. Be sure to clear bit 8 to “0”.
2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
3. Setting SDRmn[15:9] =
2
0000000B is prohibited when the simplified I C is used.
Set
SDRmn[15:9] to 0000001B or greater.
Remarks 1. For the function of the lower 8 bits of SDRmn, see 14.2 Configuration of Serial Array Unit.
2. m: Unit number (m = 0, 1)
n: Channel number (n = 0 to 3)
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(6) Serial status register mn (SSRmn)
SSRmn is a register that indicates the communication status and error occurrence status of channel n. The errors
indicated by this register are a framing error, parity error, and overrun error.
SSRmn can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of SSRmn can be set with an 8-bit memory manipulation instruction with SSRmnL.
Reset signal generation clears this register to 0000H.
Figure 14-9. Format of Serial Status Register mn (SSRmn) (1/2)
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03),
After reset: 0000H
R
F0140H, F0141H (SSR10), F0142H, F0143H (SSR11),
F0144H, F0145H (SSR12), F0146H, F0147H (SSR13)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSRmn
0
0
0
0
0
0
0
0
0
TSF
BFF
0
0
FEF
PEF
OVF
mn
mn
mn
mn
mn
Note
Note
Note
TSF
Communication status indication flag of channel n
mn
0
Communication is not under execution.
1
Communication is under execution.
Because this flag is an updating flag, it is automatically cleared when the communication operation is completed.
This flag is cleared also when the STmn/SSmn bit is set to 1.
BFF
Buffer register status indication flag of channel n
mn
0
Valid data is not stored in the SDRmn register.
1
Valid data is stored in the SDRmn register.
This is an updating flag. It is automatically cleared when transfer from the SDRmn register to the shift register is
completed. During reception, it is automatically cleared when data has been read from the SDRmn register. This
flag is cleared also when the STmn/SSmn bit is set to 1.
This flag is automatically set if transmit data is written to the SDRmn register when the TXEmn bit of the SCRmn
register = 1 (transmission or reception mode in each communication mode). It is automatically set if receive data is
stored in the SDRmn register when the RXEmn bit of the SCRmn register = 1 (transmission or reception mode in
each communication mode). It is also set in case of a reception error.
If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the register is
discarded and an overrun error (OVFmn = 1) is detected.
Note Only SSR12 register does not have FET12, PET12, and OVF12.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 14-9. Format of Serial Status Register mn (SSRmn) (2/2)
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03),
After reset: 0000H
R
F0140H, F0141H (SSR10), F0142H, F0143H (SSR11),
F0144H, F0145H (SSR12), F0146H, F0147H (SSR13)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSRmn
0
0
0
0
0
0
0
0
0
TSF
BFF
0
0
FEF
PEF
OVF
mn
mn
mn
mn
mn
Note
Note
Note
FEF
Framing error detection flag of channel n
mn
0
No error occurs.
1
A framing error occurs during UART reception.
A framing error occurs if the stop bit is not detected upon completion of UART reception.
This is a cumulative flag and is not cleared until 1 is written to the FECTmn bit of the SIRmn register.
PEF
Parity error detection flag of channel n
mn
0
Error does not occur.
1
A parity error occurs during UART reception or ACK is not detected during I C transmission.
2
• A parity error occurs if the parity of transmit data does not match the parity bit on completion of UART
reception.
• ACK is not detected if the ACK signal is not returned from the slave in the timing of ACK reception
2
during I C transmission.
This is a cumulative flag and is not cleared until 1 is written to the PECTmn bit of the SIRmn register.
OVF
Overrun error detection flag of channel n
mn
0
No error occurs.
1
An overrun error occurs.
• Receive data stored in the SDRmn register is not read and transmit data is written or the next receive
data is written.
• Transmit data is not ready for slave transmission or reception in the CSI mode.
This is a cumulative flag and is not cleared until 1 is written to the OVCTmn bit of the SIRmn register.
Note Only SSR12 register does not have FET12, PET12, and OVF12.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(7) Serial flag clear trigger register mn (SIRmn)
SIRmn is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn,
OVFmn) of serial status register mn is cleared to 0. Because SIRmn is a trigger register, it is cleared immediately
when the corresponding bit of SSRmn is cleared.
SIRmn can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SIRmn can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears this register to 0000H.
Figure 14-10. Format of Serial Flag Clear Trigger Register mn (SIRmn)
Address: F0108H, F0109H (SIR00) to F010EH, F010FH (SIR03),
After reset: 0000H
R/W
F0148H, F0149H (SIR10), F014AH, F014BH (SIR11),
F014EH, F014FH (SIR13)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIRmn
0
0
0
0
0
0
0
0
0
0
0
0
0
FEC
PEC
OVC
Tmn
Tmn
Tmn
FEC
Clear trigger of framing error of channel n
Tmn
0
No trigger operation
1
Clears the FEFmn bit of the SSRmn register to 0.
PEC
Clear trigger of parity error flag of channel n
Tmn
0
No trigger operation
1
Clears the PEFmn bit of the SSRmn register to 0.
OVC
Clear trigger of overrun error flag of channel n
Tmn
Caution
0
No trigger operation
1
Clears the OVFmn bit of the SSRmn register to 0.
Be sure to clear bits 15 to 3 to “0”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. When the SIRmn register is read, 0000H is always read.
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(8) Serial channel enable status register m (SEm)
SEm indicates whether data transmission/reception operation of each channel is enabled or stopped.
When 1 is written a bit of serial channel start register 0 (SSm), the corresponding bit of this register is set to 1.
When 1 is written a bit of serial channel stop register 0 (STm), the corresponding bit is cleared to 0.
Channel n that is enabled to operate cannot rewrite by software the value of CKOmn of the serial output register m
(SOm) to be described below, and a value reflected by a communication operation is output from the serial clock
pin.
Channel n that stops operation can set the value of CKOmn of the SOm register by software and output its value
from the serial clock pin. In this way, any waveform, such as that of a start condition/stop condition, can be created
by software.
SEm can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of SEm can be set with an 1-bit or 8-bit memory manipulation instruction with SEmL.
Reset signal generation clears this register to 0000H.
Figure 14-11. Format of Serial Channel Enable Status Register m (SEm)
Address: F0120H, F0121H (SE0), F0160H, F0161H (SE1)
After reset: 0000H
R
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SEm
0
0
0
0
0
0
0
0
0
0
0
0
SEm
SEm
SEm
SEm
3
2
1
0
SEm
Indication of operation enable/stop status of channel n
n
0
Operation stops (stops with the values of the control register and shift register, and the statuses of the serial
clock I/O pin, serial data output pin, and the FEF, PEF, and OVF error flags retained
1
Note
).
Operation is enabled.
Note Bits 6 and 5 (TSFmn, BFFmn) of the SSRmn register are cleared.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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CHAPTER 14 SERIAL ARRAY UNIT
(9) Serial channel start register m (SSm)
SSm is a trigger register that is used to enable starting communication/count by each channel.
When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is set to 1. Because SSmn is a trigger bit, it is cleared immediately when SEmn = 1.
SSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SSm can be set with an 1-bit or 8-bit memory manipulation instruction with SSmL.
Reset signal generation clears this register to 0000H.
Figure 14-12. Format of Serial Channel Start Register m (SSm)
Address: F0122H, F0123H (SS0), F0162H, F0163H (SS1)
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm
SSm
SSm
SSm
3
2
1
0
SSmn
Operation start trigger of channel n
0
No trigger operation
1
Sets SEmn to 1 and enters the communication wait status (if a communication operation is already under
execution, the operation is stopped and the start condition is awaited).
Caution
Be sure to clear bits 15 to 4 to “0”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. When the SSm register is read, 0000H is always read.
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CHAPTER 14 SERIAL ARRAY UNIT
(10) Serial channel stop register m (STm)
STm is a trigger register that is used to enable stopping communication/count by each channel.
When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is cleared to 0. Because STmn is a trigger bit, it is cleared immediately when SEmn = 0.
STm can set written by a 16-bit memory manipulation instruction.
The lower 8 bits of STm can be set with an 1-bit or 8-bit memory manipulation instruction with STmL.
Reset signal generation clears this register to 0000H.
Figure 14-13. Format of Serial Channel Stop Register m (STm)
Address: F0124H, F0125H (ST0), F0164H, F0165H (ST1)
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STm
0
0
0
0
0
0
0
0
0
0
0
0
STm
STm
STm
STm
3
2
1
0
STm
Operation stop trigger of channel n
n
0
No trigger operation
1
Clears SEmn to 0 and stops the communication operation.
(Stops with the values of the control register and shift register, and the statuses of the serial clock I/O pin,
Note
serial data output pin, and the FEF, PEF, and OVF error flags retained
.)
Note Bits 6 and 5 (TSFmn, BFFmn) of the SSRmn register are cleared.
Caution
Be sure to clear bits 15 to 4 to “0”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. When the STm register is read, 0000H is always read.
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(11) Serial output enable register m (SOEm)
SOEm is a register that is used to enable or stop output of the serial communication operation of each channel.
Channel n that enables serial output cannot rewrite by software the value of SOmn of the serial output register m
(SOm) to be described below, and a value reflected by a communication operation is output from the serial data
output pin.
For channel n, whose serial output is stopped, the SOmn value of the SOm register can be set by software, and
that value can be output from the serial data output pin. In this way, any waveform of the start condition and stop
condition can be created by software.
SOEm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SOEm can be set with an 1-bit or 8-bit memory manipulation instruction with SOEmL.
Reset signal generation clears this register to 0000H.
Figure 14-14. Format of Serial Output Enable Register m (SOEm)
Address: F012AH, F012BH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOE0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOE
SOE
SOE
02
01
00
Address: F016AH, F016BH
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOE1
0
0
0
0
0
0
0
0
0
0
0
0
0
SOE
0
SOE
12
SOE
10
Serial output enable/disable of channel n
mn
0
Stops output by serial communication operation.
1
Enables output by serial communication operation.
Caution
Be sure to clear bits 15 to 3 of SOE0, and bits 1 and 15 to 3 of SOE1 to “0”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2),
mn = 00 to 02, 10, 12
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CHAPTER 14 SERIAL ARRAY UNIT
(12) Serial output register m (SOm)
SOm is a buffer register for serial output of each channel.
The value of bit n of this register is output from the serial data output pin of channel n.
The value of bit (n + 8) of this register is output from the serial clock output pin of channel n.
SOmn of this register can be rewritten by software only when serial output is disabled (SOEmn = 0). When serial
output is enabled (SOEmn = 1), rewriting by software is ignored, and the value of the register can be changed only
by a serial communication operation.
CKOmn of this register can be rewritten by software only when the channel operation is stopped (SEmn = 0).
While channel operation is enabled (SEmn = 1), rewriting by software is ignored, and the value of CKOmn can be
changed only by a serial communication operation.
To use the P10/SCK20/SCL20, P11/SI20/SDA20/RxD2/INTP6, P12/SO20/TxD2/TO02, P13/SO10/TxD1/TO04,
P14/SI10/SDA10/RxD1/INTP4, P15/SCK10/SCL10/INTP7, P51/TxD3/SDGx (78K0R/LF3: x = 29, 78K0R/LG3: x =
38, 78K0R/LH3: x = 52), P75/SCK01/KR5, P77/SO01/KR7, P80/SCK00/INTP11, or P82/SO00/TxD0 pin as a port
function pin, set the corresponding CKOmn and SOmn bits to “1”.
SOm can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0F0FH.
Figure 14-15. Format of Serial Output Register m (SOm)
Address: F0128H, F0129H
After reset: 0F0FH
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SO0
0
0
0
0
1
CKO
CKO
CKO
0
0
0
0
1
SO
SO
SO
02
01
00
02
01
00
Address: F0168H, F0169H
After reset: 0F0FH
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SO1
0
0
0
0
1
1
1
CKO
0
0
0
0
1
SO
1
SO
10
CKO
12
10
Serial clock output of channel n
mn
0
Serial clock output value is “0”.
1
Serial clock output value is “1”.
SO
Serial data output of channel n
mn
Caution
0
Serial data output value is “0”.
1
Serial data output value is “1”.
Be sure to set bits 11 and 3 of SO0, and bits 11 to 9, 3, and 1 of SO1 to “1”. And be sure to clear
bits 15 to 12 and 7 to 4 of SOm to “0”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2),
mn = 00 to 02, 10, 12
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(13) Serial output level register m (SOLm)
SOLm is a register that is used to set inversion of the data output level of each channel.
2
This register can be set only in the UART mode. Be sure to set 0000H in the CSI mode and simplifies I C mode.
Inverting channel n by using this register is reflected on pin output only when serial output is enabled (SOEmn =
1). When serial output is disabled (SOEmn = 0), the value of the SOmn bit is output as is.
Rewriting SOLm is prohibited when the register is in operation (when SEmn = 1).
SOLm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SOLm can be set with an 8-bit memory manipulation instruction with SOLmL.
Reset signal generation clears this register to 0000H.
Figure 14-16. Format of Serial Output Level Register m (SOLm)
Address: F0134H, F0135H (SOL0), F0174H, F0175H (SOL1)
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOLm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOL
0
SOL
m2
SOL
m0
Selects inversion of the level of the transmit data of channel n in UART mode
mn
0
Communication data is output as is.
1
Communication data is inverted and output.
Caution
Be sure to clear bits 15 to 3, 1 to “0”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
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CHAPTER 14 SERIAL ARRAY UNIT
(14) Input switch control register (ISC)
ISC is used to realize a LIN-bus communication operation by UART3 in coordination with an external interrupt and
the timer array unit.
When bit 0 is set to 1, the input signal of the serial data input (RXD3) pin is selected as an external interrupt
(INTP0) that can be used to detect a wakeup signal.
When bit 1 is set to 1, the input signal of the serial data input (RXD3) pin is selected as a timer input, so that the
pulse widths of a sync break field and a sync field can be measured by the timer.
ISC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 14-17. Format of Input Switch Control Register (ISC)
Address: FFF3CH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ISC
0
0
0
ISC4
ISC3
ISC2
ISC1
ISC0
ISC1
Switching channel 7 input of timer array unit
0
Uses the input signal of the TI07 pin as a timer input (normal operation).
1
Input signal of RXD3 pin is used as timer input (wakeup signal detection).
ISC0
Switching external interrupt (INTP0) input
0
Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
1
Uses the input signal of the RXD3 pin as an external interrupt
(to measure the pulse widths of the sync break field and sync field).
Caution Be sure to clear bits 7 to 5 to “0”.
Remark
Bits 2 to 4 of ISC are not used with SAU1.
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CHAPTER 14 SERIAL ARRAY UNIT
(15) Noise filter enable register 0 (NFEN0)
NFEN0 is used to set whether the noise filter can be used for the input signal from the serial data input pin to each
channel.
Disable the noise filter of the pin used for CSI or simplified I2C communication, by clearing the corresponding bit of
this register to 0.
Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to
1.
When the noise filter is enabled, CPU/peripheral operating clock (fCLK) is synchronized with 2-clock match
detection.
NFEN0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 14-18. Format of Noise Filter Enable Register 0 (NFEN0)
Address: F0060H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
NFEN0
0
SNFEN30
0
SNFEN20
0
SNFEN10
0
SNFEN00
SNFEN30
Use of noise filter of RXD3/P50/SEGx (78K0R/LF3: x = 30, 78K0R/LG3: x = 39, 78K0R/LH3: x = 53) pin
0
Noise filter OFF
1
Noise filter ON
Set SNFEN30 to 1 to use the RXD3 pin.
Clear SNFEN30 to 0 to use the P50 or SEGx pins.
SNFEN20
Use of noise filter of RXD2/P11/SI20/SDA20/INTP6 pin
0
Noise filter OFF
1
Noise filter ON
Set SNFEN20 to 1 to use the RXD2 pin.
Clear SNFEN20 to 0 to use the P11, SI20, SDA20 or INTP6 pins.
SNFEN10
Use of noise filter of RXD1/P14/SI10/SDA10/INTP4 pin
0
Noise filter OFF
1
Noise filter ON
Set SNFEN10 to 1 to use the RXD1 pin.
Clear SNFEN10 to 0 to use the P14, SI10, SDA10 or INTP4 pins.
SNFEN00
Use of noise filter of RXD0/P80/SI00/INTP9 pin
0
Noise filter OFF
1
Noise filter ON
Set SNFEN00 to 1 to use the RXD0 pin.
Clear SNFEN00 to 0 to use the P80, SI00 or INTP9.
Caution
Be sure to clear bits 7, 5, 3, and 1 to “0”.
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(16) Port input mode registers 1, 7 (PIM1, PIM7)
These registers set the input buffer of P10, P11, P14, P15, P75, and P76 in 1-bit units.
PIM1 and PIM7 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 14-19. Format of Port Input Mode Registers 1, and 7 (PIM1, PIM7)
• 78K0R/LF3, 78K0R/LG3
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PIM1
0
0
PIM15
PIM14
0
0
PIM11
PIM10
F0041H
00H
R/W
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PIM1
0
0
PIM15
PIM14
0
0
PIM11
PIM10
F0041H
00H
R/W
PIM7
0
PIM76
PIM75
0
0
0
0
0
F0047H
00H
R/W
• 78K0R/LH3
Pmn pin input buffer selection
PIMmn
(m = 1 and 7; n = 0, 1, 4 to 6)
0
Normal input buffer
1
TTL input buffer
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(17) Port output mode registers 1, 7, 8 (POM1, POM7, POM8)
These registers set the output mode of P10 to P15, P75, P77, P80 and 82 in 1-bit units.
POM1, POM7, and POM8 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 14-20. Format of Port Output Mode Registers 1, 7, and 8 (POM1, POM7, POM8)
• 78K0R/LF3
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
POM1
0
0
POM15
POM14
POM13
POM12
POM11
POM10
F0051H
00H
R/W
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
POM1
0
0
POM15
POM14
POM13
POM12
POM11
POM10
F0051H
00H
R/W
POM8
0
0
0
0
0
POM82
0
POM80
F0058H
00H
R/W
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
POM1
0
0
POM15
POM14
POM13
POM12
POM11
POM10
F0051H
00H
R/W
POM7
POM77
0
POM75
0
0
0
0
0
F0057H
00H
R/W
POM8
0
0
0
0
0
POM82
0
POM80
F0058H
00H
R/W
• 78K0R/LG3
• 78K0R/LH3
Pmn pin output mode selection
POMmn
(m = 1, 7, and 8; n = 0 to 5 and 7)
0
Normal output mode
1
N-ch open-drain output (VDD tolerance) mode
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CHAPTER 14 SERIAL ARRAY UNIT
(18) Port mode registers 1, 5, 7, 8 (PM1, PM5, PM7, PM8)
These registers set input/output of ports 1, 5, 7 and 8 in 1-bit units.
When using the P10/SCK20/SCL20, P11/SI20/SDA20/RxD2/INTP6, P12/SO20/TxD2/TO02, P13/SO10/TxD1/TO04,
P14/SI10/SDA10/RxD1/INTP4, P15/SCK10/SCL10/INTP7, P51/TxD3/SEGx (78K0R/LF3: x = 29, 78K0R/LG3: x = 38,
78K0R/LH3: x = 52), P75/SCK01/KR5, P77/SO01/KR7, P80/SCK00/INTP11, and P82/SO00/TxD0 pins for serial data
output or serial clock output, clear the PM10, PM11, PM12, PM13, PM14, PM15, PM51, PM75, PM77, PM80, and
PM82 bits to 0, and set the output latches of P10, P11, P12, P13, P14, P15, P51, P75, P77, P80, and P82 to 1.
When using the P10/SCK20/SCL20, P11/SI20/SDA20/RxD2/INTP6, P14/SI10/SDA10/RxD1/INTP4,
P15/SCK10/SCL10/INTP7, P50/RxD3/SEGx (78K0R/LF3: x = 30, 78K0R/LG3: x = 39, 78K0R/LH3: x = 53),
P75/SCK01/KR5, P76/SI01/KR6, P80/SCK00/INTP11, and P81/SI00/RxD0/INTP9 pins for serial data input or serial
clock input, set the PM10, PM11, PM14, PM15, PM50, PM75, PM76, PM80, and PM81 bits to 1. At this time, the
output latches of P10, P11, P14, P15, P50, P75, P76, P80, and P81 may be 0 or 1.
PM1, PM5, PM7, and PM8 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 14-21. Format of Port Mode Registers 1, 5, 7, and 8 (PM1, PM5, PM7, PM8)
• 78K0R/LF3
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM1
1
1
PM15
PM14
PM13
PM12
PM11
PM10
FFF21H
FFH
R/W
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FFF25H
FFH
R/W
• 78K0R/LG3
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM1
1
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FFF21H
FFH
R/W
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FFF25H
FFH
R/W
PM8
1
1
1
1
1
PM82
PM81
PM80
FFF28H
FFH
R/W
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FFF21H
FFH
R/W
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FFF25H
FFH
R/W
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
FFF27H
FFH
R/W
PM8
PM87
PM86
PM85
PM84
PM83
PM82
PM81
PM80
FFF28H
FFH
R/W
• 78K0R/LH3
Pmn pin I/O mode selection
PMmn
(m = 1, 5, 7, 8; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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14.4 Operation stop mode
Each serial interface of serial array unit has the operation stop mode.
In this mode, serial communication cannot be executed, thus reducing the power consumption.
In addition, the P10/SCK20/SCL20, P11/SI20/SDA20/RxD2/INTP6, P12/SO20/TxD2/TO02, P13/SO10/TxD1/TO04,
P14/SI10/SDA10/RxD1/INTP4, P15/SCK10/SCL10/INTP7, P50/RxD3/SEGx (78K0R/LF3:
x = 30, 78K0R/LG3:
x = 39,
78K0R/LH3: x = 53), P51/TxD3/SEGx (78K0R/LF3: x = 29, 78K0R/LG3: x = 38, 78K0R/LH3: x = 52), P75/SCK01/KR5,
P76/SI01/KR6, P77/SO01/KR7, P80/SCK00/INTP11, P81/SI00/RxD0/INTP9, and P82/SO00/TxD0 pins can be used as
ordinary port pins in this mode.
14.4.1 Stopping the operation by units
The stopping of the operation by units is set by using peripheral enable register 0 (PER0).
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that is
not used is stopped in order to reduce the power consumption and noise.
To stop the operation of serial array unit 0, set bit 2 (SAU0EN) to 0.
To stop the operation of serial array unit 1, set bit 3 (SAU1EN) to 0.
Figure 14-22. Peripheral Enable Register 0 (PER0) Setting When Stopping the Operation by Units
(a) Peripheral enable register 0 (PER0) … Set only the bit of SAUm to be stopped to 0.
PER0
7
6
5
4
3
2
1
0
RTCEN
DACEN
ADCEN
IIC0EN
SAU1EN
SAU0EN
TAU1EN
TAU0EN
×
×
×
×
0/1
0/1
×
×
Control of SAUm input clock
0: Stops supply of input clock
1: Supplies input clock
Caution
If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and, even if the
register is read, only the default value is read (except for input switch control register (ISC), noise
filter enable register (NFEN0), port input mode registers (PIM1, PIM7), port output mode registers
(POM1, POM7, POM8), port mode registers (PM1, PM5, PM7, PM8), and port registers (P1, P5, P7,
P8)).
Remark
m: Unit number (m = 0, 1)
×: Bits not used with serial array units (depending on the settings of other peripheral functions)
0/1: Set to 0 or 1 depending on the usage of the user
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14.4.2 Stopping the operation by channels
The stopping of the operation by channels is set using each of the following registers.
Figure 14-23. Each Register Setting When Stopping the Operation by Channels (1/2)
Serial Channel Enable Status Register m (SEm) … This register indicates whether data
•
transmission/reception operation of each channel is enabled or stopped.
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
0
Sem
3
2
1
0
Sem3
Sem2
Sem1
Sem0
0/1
0/1
0/1
0/1
0: Operation stops
•
The Sem register is a read-only status register, whose operation is stopped by using the STm register.
With a channel whose operation is stopped, the value of CKOmn of the Som register can be set by software.
•
Serial channel stop register m (STm) … This register is a trigger register that is used to enable
stopping communication/count by each channel.
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
0
STm
3
2
1
0
STm3
STm2
STm1
STm0
0/1
0/1
0/1
0/1
1: Clears Semn to 0 and stops the communication operation
* Because STmn is a trigger bit, it is cleared immediately when SEmn = 0.
(c) Serial output enable register m (SOEm) … This register is a register that is used to enable or stop
output of the serial communication operation of each channel.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOE0
2
1
0
SOE02 SOE01 SOE00
0/1
0/1
0/1
1
0
0: Stops output by serial communication operation
* For channel n, whose serial output is stopped, the SO0n value of the SO0 register can be set by software.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOE1
2
SOE12
0/1
SOE10
0
0/1
0: Stops output by serial communication operation
* For channel n, whose serial output is stopped, the SO1n value of the SO1 register can be set by software.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
: Setting disabled (fixed by hardware), 0/1: Set to 0 or 1 depending on the usage of the user
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Figure 14-23. Each Register Setting When Stopping the Operation by Channels (2/2)
(d) Serial output register m (SOm) …This register is a buffer register for serial output of each channel.
15
14
13
12
11
0
0
0
0
1
SO0
10
9
8
7
6
5
4
3
0
0
0
0
1
CKO02 CKO01 CKO00
0/1
0/1
0/1
1: Serial clock output value is “1”
2
1
0
SO02
SO01
SO00
0/1
0/1
0/1
1: Serial data output value is “1”
* When using pins corresponding to each channel as port function pins, set the corresponding CKO0n and SO0n bits to “1”.
15
14
13
12
11
10
9
0
0
0
0
1
1
1
SO1
8
7
6
5
4
3
0
0
0
0
1
CKO10
1: Serial clock output value is “1”
0/1
2
1
SO12
0/1
0
SO10
1
0/1
1: Serial data output value is “1”
* When using pins corresponding to each channel as port function pins, set the corresponding CKO10 and SO1n bits to “1”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
: Setting disabled (fixed by hardware), 0/1: Set to 0 or 1 depending on the usage of the user
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14.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) Communication
This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines.
[Data transmission/reception]
• Data length of 7 or 8 bits
• Phase control of transmit/receive data
• MSB/LSB first selectable
• Level setting of transmit/receive data
[Clock control]
• Master/slave selection
• Phase control of I/O clock
• Setting of transfer period by prescaler and internal counter of each channel
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
[Error detection flag]
• Overrun error
The channels supporting 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20) are channels 0 to 2 of SAU0 and channel 0 of
SAU1.
0
1
2
Used as CSI
Used as UART
Used as Simplified I C
0
CSI00
UART0
−
1
CSI01
2
CSI10
3
−
0
CSI20
1
−
2
−
3
−
Unit
Channel
−
UART1
IIC10
−
UART2
IIC20
−
UART3 (supporting LIN-bus)
−
−
Remarks 1. For 78K0R/LF3, CSI00 and CSI01 are not mounted.
2. For 78K0R/LG3, CSI01 is not mounted.
3-wire serial I/O (CSI00, CSI01, CIS10, CSI20) performs the following six types of communication operations.
• Master transmission
(See 14.5.1.)
• Master reception
(See 14.5.2.)
• Master transmission/reception
(See 14.5.3.)
• Slave transmission
(See 14.5.4.)
• Slave reception
(See 14.5.5.)
• Slave transmission/reception
(See 14.5.6.)
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14.5.1 Master transmission
Master transmission is that the 78K0R/Lx3 microcontrollers output a transfer clock and transmit data to another device.
3-Wire Serial I/O
CSI00
CSI01
CSI10
CSI20
Target channel
Channel 0 of SAU0
Channel 1 of SAU0
Channel 2 of SAU0
Channel 0 of SAU1
Pins used
SCK00, SO00
SCK01, SO01
SCK10, SO10
SCK20, SO20
Interrupt
INTCSI00
INTCSI01
INTCSI10
INTCSI20
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag
None
Transfer data length
7 or 8 bits
Transfer rate
Max. fCLK/4 [MHz], Min. fCLK/(2 × 2 × 128) [MHz]
Data phase
11
Note
fCLK: System clock frequency
Selectable by DAPmn bit
• DAPmn = 0: Data output starts from the start of the operation of the serial clock.
• DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Clock phase
Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction
MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. For 78K0R/LF3, CSI00 and CSI01 are not mounted.
2. For 78K0R/LG3, CSI01 is not mounted.
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(1) Register setting
Figure 14-24. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O
(CSI00, CSI01, CSI10, CSI20)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15
14
13
12
11
0
0
0
0
1
SOm
10
9
8
7
6
5
4
3
0
0
0
0
1
CKOm2 CKOm1 CKOm0
0/1
0/1
0/1
2
1
0
SOm2
SOm1
SOm0
0/1
0/1
0/1
Communication starts when these bits are 1 if the data
phase is forward (CKPmn = 0). If the phase is reversed
(CKPmn = 1), communication starts when these bits are 0.
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
2
1
0
SOEm2 SOEm1 SOEm0
0/1
0/1
0/1
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
SSm2
SSm1
SSm0
×
0/1
0/1
0/1
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
STSmn
CKSmn CCSmn
0/1
0
0
SISm0
0
MDmn2 MDmn1 MDmn0
0
0
0
0/1
Operation mode of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(e) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
1
0
0/1
0/1
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0
0
0/1
5
4
3
SLCmn1 SLCmn0
2
1
0
DLSmn2 DLSmn1 DLSmn0
0
0
0
0
1
1
0/1
6
5
4
3
2
1
0
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15
14
13
12
11
10
9
8
7
SDRmn
Baud rate setting
0
Transmit data setting
SIOp
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
: Setting is fixed in the CSI master transmission mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Operation procedure
Figure 14-25. Initial Setting Procedure for Master Transmission
Starting initial setting
Setting PER0 register
Setting SPSm register
Release the serial array unit from the
reset status and start clock supply.
Set the prescaler.
Setting SMRmn register
Set an operation mode, etc.
Setting SCRmn register
Set a communication format.
Setting SDRmn register
Set a transfer baud rate.
Setting SOm register
Changing setting of SOEm register
Manipulate the SOmn and CKOmn bits
and set an initial output level.
Set the SOEmn bit to 1 and enable data
output of the target channel.
Enable data output and clock output of
Setting port
the target channel by setting a port
register and a port mode register.
Writing to SSm register
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set transmit data to the SIOp register (bits
Starting communication
7 to 0 of the SDRmn register) and start
communication.
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
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Figure 14-26. Procedure for Stopping Master Transmission
Starting setting to stop
Setting STm register
Write 1 to the STmn bit of the target
channel.
Changing setting of SOEm
register
Stopping communication
Set the SOEm register and stop the
output of the target channel
Stop communication in midway.
Remarks 1. Even after communication is stopped, the pin level is retained. To resume the operation, re-set the
SOm register (see Figure 14-27 Procedure for Resuming Master Transmission).
2. p: CSI number (p = 00, 01, 10, 20)
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Figure 14-27. Procedure for Resuming Master Transmission
Starting setting for resumption
Disable data output and clock output of
Port manipulation
(Essential)
the target channel by setting a port
register and a port mode register.
Change the setting if an incorrect division
(Selective)
Changing setting of SPSm register
ratio of the operation clock is set.
Change the setting if an incorrect
(Selective)
Changing setting of SDRmn register
(Selective)
Changing setting of SMRmn register
(Selective)
Changing setting of SCRmn register
transfer baud rate is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Change the setting if the setting of the
(Selective)
Clearing error flag
SCRmn register is incorrect.
Cleared by using SIRmn register if FEF,
PEF, or OVF flag remains set.
Set the SOEm register and stop the
(Selective)
Changing setting of SOEm register
(Selective)
Changing setting of SOm register
(Selective)
Changing setting of SOEm register
output of the target channel.
Manipulate the SOmn and CKOmn bits
and set an initial output level.
Set the SOEm register and enable data
output of the target channel.
Enable data output and clock output of
(Essential)
Port manipulation
the target channel by setting a port
register and a port mode register.
Set the SSmn bit of the target channel to
(Essential)
Writing to SSm register
(Essential)
Starting communication
1 to set SEmn = 1.
Sets transmit data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
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(3) Processing flow (in single-transmission mode)
Figure 14-28. Timing Chart of Master Transmission (in Single-Transmission Mode)
SSmn
STmn
SEmn
SDRmn
Transmit data 1
Transmit data 2
Transmit data 3
SCKp pin
SOp pin
Transmit data 1
Shift
register mn
INTCSIp
Transmit data 2
Transmit data 3
Shift operation
Shift operation
Shift operation
Data transmission (8-bit length)
Data transmission (8-bit length)
Data transmission (8-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 14-29. Flowchart of Master Transmission (in Single-Transmission Mode)
Starting CSI communication
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
SMRmn, SCRmn: Setting communication
SDRmn[15:9]:
Setting transfer rate
SOm, SOEm:
Setting output
Perform initial setting when SEmn = 0.
Port manipulation
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
Transfer end interrupt
generated?
No
Yes
No
Transmission completed?
Yes
Writing 1 to STmn bit
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
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(4) Processing flow (in continuous transmission mode)
Figure 14-30. Timing Chart of Master Transmission (in Continuous Transmission Mode)
SSmn
STmn
SEmn
SDRmn
Transmit data 1
Transmit data 2
Transmit data 3
SCKp pin
SOp pin
Transmit data 2
Transmit data 1
Shift
register mn
INTCSIp
Shift operation
Transmit data 3
Shift operation
Data transmission (8-bit length)
Shift operation
Data transmission (8-bit length)
Data transmission (8-bit length)
MDmn0
TSFmn
BFFmn
(Note)
Note When transmit data is written to the SDRmn register while BFFmn = 1, the transmit data is overwritten.
Caution
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the
transfer end interrupt of the last transmit data.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 14-31. Flowchart of Master Transmission (in Continuous Transmission Mode)
Starting CSI communication
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
SMRmn, SCRmn: Setting communication
SDRmn[15:9]:
Setting transfer rate
SOm, SOEm;
Setting output
Perform initial setting when SEmn = 0.
Select the buffer empty interrupt.
Port manipulation
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
No
Buffer empty interrupt
generated?
Yes
Yes
Transmitting next data?
No
Clearing 0 to MDmn0 bit
No
TSFmn = 1?
Yes
No
Transfer end interrupt
generated?
Yes
Yes
Writing 1 to MDmn0 bit
Communication continued?
No
Writing 1 to STmn bit
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Remark
to in the figure correspond to to in Figure 14-30
Timing Chart of Master
Transmission (in Continuous Transmission Mode).
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14.5.2 Master reception
Master reception is that the 78K0R/Lx3 microcontrollers output a transfer clock and receive data from other device.
3-Wire Serial I/O
CSI00
CSI01
CSI10
CSI20
Target channel
Channel 0 of SAU0
Channel 1 of SAU0
Channel 2 of SAU0
Channel 0 of SAU1
Pins used
SCK00, SI00
SCK01, SI01
SCK10, SI10
SCK20, SI20
Interrupt
INTCSI00
INTCSI01
INTCSI10
INTCSI20
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag
Overrun error detection flag (OVFmn) only
Transfer data length
7 or 8 bits
Transfer rate
Max. fCLK/4 [MHz], Min. fCLK/(2 × 2 × 128) [MHz]
Data phase
11
Note
fCLK: System clock frequency
Selectable by DAPmn bit
• DAPmn = 0: Data input starts from the start of the operation of the serial clock.
• DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Clock phase
Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction
MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. For 78K0R/LF3, CSI00 and CSI01 are not mounted.
2. For 78K0R/LG3, CSI01 is not mounted.
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(1) Register setting
Figure 14-32. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10, CSI20)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15
14
13
12
11
0
0
0
0
1
SOm
10
9
8
7
6
5
4
3
0
0
0
0
1
CKOm2 CKOm1 CKOm0
0/1
0/1
0/1
2
1
0
SOm2
SOm1
SOm0
×
×
×
Communication starts when these bits are 1 if the data
phase is forward (CKPmn = 0). If the phase is reversed
(CKPmn = 1), communication starts when these bits are 0.
(b) Serial output enable register m (SOEm) … Clears only the bits of the target channel to 0.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
2
1
0
SOEm2 SOEm1 SOEm0
0/1
0/1
0/1
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
SSm2
SSm1
SSm0
×
0/1
0/1
0/1
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
0
STSmn
0
SISmn0
0
MDmn2 MDmn1 MDmn0
0
0
0
0
Operation mode of channel n
0: Transfer end interrupt
(e) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
0
1
0/1
0/1
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0
0
0/1
5
4
3
SLCmn1 SLCmn0
2
1
0
DLSmn2 DLSmn1 DLSmn0
0
0
0
0
1
1
0/1
6
5
4
3
2
1
0
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15
14
13
12
11
10
9
8
7
SDRmn
Baud rate setting
0
Receive data register
(Write FFH as dummy data.)
SIOp
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
: Setting is fixed in the CSI master reception mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Operation procedure
Figure 14-33. Initial Setting Procedure for Master Reception
Starting initial setting
Setting PER0 register
Setting SPSm register
Release the serial array unit from the
reset status and start clock supply.
Set the prescaler.
Setting SMRmn register
Set an operation mode, etc.
Setting SCRmn register
Set a communication format.
Setting SDRmn register
Set a transfer baud rate.
Setting SOm register
Manipulate the CKOmn bit and set an
initial output level.
Enable clock output of the target channel
Setting port
by setting a port register and a port mode
register.
Writing to SSm register
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set dummy data to the SIOp register (bits
Starting communication
7 to 0 of the SDRmn register) and start
communication.
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Figure 14-34. Procedure for Stopping Master Reception
Starting setting to stop
Setting STm register
Stopping communication
Remark
Write 1 to the STmn bit of the target
channel.
Stop communication in midway.
Even after communication is stopped, the pin level is retained. To resume the operation, re-set the SOm
register (see Figure 14-35 Procedure for Resuming Master Reception).
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Figure 14-35. Procedure for Resuming Master Reception
Starting setting for resumption
Disable clock output of the target
Port manipulation
(Essential)
channel by setting a port register and a
port mode register.
Change the setting if an incorrect division
(Selective)
Changing setting of SPSm register
(Selective)
Changing setting of SDRmn register
(Selective)
Changing setting of SMRmn register
(Selective)
Changing setting of SCRmn register
(Selective)
Changing setting of SOm register
(Essential)
Changing setting of SOEm register
ratio of the operation clock is set.
Change the setting if an incorrect
transfer baud rate is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Change the setting if the setting of the
SCRmn register is incorrect.
Manipulate the CKOmn bit and set a
(Selective)
clock output level.
Clear the SOEm register to 0 and stop
data output of the target channel.
Clearing error flag
Cleared by using SIRmn register if FEF,
PEF, or OVF flag remains set.
Enable clock output of the target channel
(Essential)
Port manipulation
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to
(Essential)
Writing to SSm register
1 to set SEmn = 1.
Sets dummy data to the SIOp register
(Essential)
Starting communication
(bits 7 to 0 of the SDRmn register) and
start communication.
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(3) Processing flow (in single-reception mode)
Figure 14-36. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Dummy data for reception
Write
Receive data 1
Dummy data
Write
Read
Receive data 3
Receive data 2
Dummy data
Write
Read
Read
SCKp pin
SIp pin
Shift
register mn
INTCSIp
Receive data 1
Reception & shift operation
Data reception (8-bit length)
Receive data 2
Receive data 3
Reception & shift operation
Reception & shift operation
Data reception (8-bit length)
Data reception (8-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 14-37. Flowchart of Master Reception (in Single-Reception Mode)
Starting CSI communication
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
SMRmn, SCRmn: Setting communication
SDRmn[15:9]:
Setting transfer rate
SOm, SOEm:
Setting SCKp output
Perform initial setting when SEmn = 0.
Port manipulation
Writing 1 to SSmn bit
Writing dummy data to
SIOp (=SDRmn[7:0])
Starting reception
No
Transfer end interrupt
generated?
Yes
Reading
SIOp (= SDRmn[7:0])
register
No
Reception completed?
Yes
Writing 1 to STmn bit
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
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14.5.3 Master transmission/reception
Master transmission/reception is that the 78K0R/Lx3 microcontrollers output a transfer clock and transmit/receive data
to/from other device.
3-Wire Serial I/O
CSI00
CSI01
CSI10
CSI20
Target channel
Channel 0 of SAU0
Channel 1 of SAU0
Channel 2 of SAU0
Channel 0 of SAU1
Pins used
SCK00, SI00, SO00
SCK01, SI01, SO01
SCK10, SI10, SO10
SCK20, SI20, SO20
Interrupt
INTCSI00
INTCSI01
INTCSI10
INTCSI20
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag
Overrun error detection flag (OVFmn) only
Transfer data length
7 or 8 bits
Transfer rate
Max. fCLK/4 [MHz], Min. fCLK/(2 × 2 × 128) [MHz]
Data phase
Selectable by DAPmn bit
11
Note
fCLK: System clock frequency
• DAPmn = 0: Data I/O starts at the start of the operation of the serial clock.
• DAPmn = 1: Data I/O starts half a clock before the start of the serial clock operation.
Clock phase
Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction
MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. For 78K0R/LF3, CSI00 and CSI01 are not mounted.
2. For 78K0R/LG3, CSI01 is not mounted.
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(1) Register setting
Figure 14-38. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10, CSI20)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15
14
13
12
11
0
0
0
0
1
SOm
10
9
8
7
6
5
4
3
0
0
0
0
1
CKOm2 CKOm1 CKOm0
0/1
0/1
0/1
2
1
0
SOm2
SOm1
SOm0
0/1
0/1
0/1
Communication starts when these bits are 1 if the data
phase is forward (CKPmn = 0). If the phase is reversed
(CKPmn = 1), communication starts when these bits are 0.
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
2
1
0
SOEm2 SOEm1 SOEm0
0/1
0/1
0/1
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
SSm2
SSm1
SSm0
×
0/1
0/1
0/1
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
STSmn
CKSmn CCSmn
0/1
0
0
SISmn0
0
MDmn2 MDmn1 MDmn0
0
0
0
0/1
Operation mode of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(e) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
1
1
0/1
0/1
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0
0
0/1
5
4
3
SLCmn1 SLCmn0
2
1
0
DLSmn2 DLSmn1 DLSmn0
0
0
0
0
1
1
0/1
6
5
4
3
2
1
0
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15
14
13
12
11
10
9
8
7
SDRmn
Baud rate setting
0
Transmit data setting/receive data register
SIOp
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
: Setting is fixed in the CSI master transmission/reception mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Operation procedure
Figure 14-39. Initial Setting Procedure for Master Transmission/Reception
Starting initial setting
Setting PER0 register
Setting SPSm register
Release the serial array unit from the
reset status and start clock supply.
Set the prescaler.
Setting SMRmn register
Set an operation mode, etc.
Setting SCRmn register
Set a communication format.
Setting SDRmn register
Set a transfer baud rate.
Setting SOm register
Manipulate the SOmn and CKOmn bits
and set an initial output level.
Set the SOEmn bit to 1 and enable
Changing setting of SOEm register
data output of the target channel.
Enable data output and clock output of
Setting port
the target channel by setting a port
register and a port mode register.
Writing to SSm register
Set the SSmn bit of the target channel
to 1 to set SEmn = 1.
Set transmit data to the SIOp register
Starting communication
(bits 7 to 0 of the SDRmn register) and
start communication.
Caution After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Figure 14-40. Procedure for Stopping Master Transmission/Reception
Starting setting to stop
Setting STm register
Changing setting of SOEm
register
Stopping communication
Remark
Write 1 to the STmn bit of the target
channel.
Set the SOEm register and stop the
output of the target channel.
Stop communication in midway.
Even after communication is stopped, the pin level is retained. To resume the operation, re-set the SOm
register (see Figure 14-41 Procedure for Resuming Master Transmission/Reception).
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Figure 14-41. Procedure for Resuming Master Transmission/Reception
Starting setting for resumption
Disable data output and clock output of
Port manipulation
(Essential)
the target channel by setting a port
register and a port mode register.
Change the setting if an incorrect division
(Selective)
Changing setting of SPSm register
ratio of the operation clock is set.
Change the setting if an incorrect
(Selective)
Changing setting of SDRmn register
(Selective)
Changing setting of SMRmn register
(Selective)
Changing setting of SCRmn register
transfer baud rate is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Change the setting if the setting of the
SCRmn register is incorrect.
Cleared by using SIRmn register if FEF,
Clearing error flag
(Selective)
PEF, or OVF flag remains set.
Set the SOEm register and stop the
(Selective)
Changing setting of SOEm register
(Selective)
Changing setting of SOm register
(Selective)
Changing setting of SOEm register
output of the target channel.
Manipulate the SOmn and CKOmn bits
and set an initial output level.
Set the SOEm register and enable the
output of the target channel.
Enable data output and clock output of
(Essential)
Port manipulation
the target channel by setting a port
register and a port mode register.
Set the SSmn bit of the target channel to
(Essential)
Writing to SSm register
(Essential)
Starting communication
1 and set SEmn to 1.
Set transmit data to the SIOp register (bits 7
to 0 of the SDRmn register) and start
communication.
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(3) Processing flow (in single-transmission/reception mode)
Figure 14-42. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Transmit data 1
Write
Receive data 1
Transmit data 2
Write
Read
Receive data 3
Receive data 2
Transmit data 2
Write
Read
Read
SCKp pin
SIp pin
Shift
register mn
SOp pin
Receive data 1
Reception & shift operation
Transmit data 1
Receive data 2
Reception & shift operation
Transmit data 2
Receive data 3
Reception & shift operation
Transmit data 3
INTCSIp
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 14-43. Flowchart of Master Transmission/Reception (in Single- Transmission/Reception Mode)
Starting CSI communication
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
SMRmn, SCRmn:
Setting communication
SDRmn[15:9]:
Setting transfer rate
SOm, SOEm:
Setting output and SCKp output
Perform initial setting when SEmn = 0.
Port manipulation
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
Starting transmission/reception
Transfer end interrupt
generated?
No
Yes
Reading
SIOp (=SDRmn[7:0])
register
No
Transmission/reception
completed?
Yes
Writing 1 to STmn bit
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
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(4) Processing flow (in continuous transmission/reception mode)
Figure 14-44. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
Receive data 3
SDRmn
Transmit data 1 Transmit data 2 Receive data 1 Transmit data 3
Write
Write
Write
Read
Receive data 2
Read
Read
SCKp pin
SIp pin
Receive data 1
Shift
register mn
SOp pin
Receive data 3
Receive data 2
Reception & shift operation
Reception & shift operation
Reception & shift operation
Transmit data 2
Transmit data 1
Transmit data 3
INTCSIp
Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length)
MDmn0
TSFmn
BFFmn
(Note 1)
(Note 2)
(Note 2)
Notes 1. When transmit data is written to the SDRmn register while BFFmn = 1, the transmit data is overwritten.
2. The transmit data can be read by reading the SDRmn register during this period. At this time, the
transfer operation is not affected.
Caution
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the
transfer end interrupt of the last transmit data.
Remarks 1. to in the figure correspond to to in Figure 14-45
Flowchart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 14-45. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
Starting CSI communication
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
SMRmn, SCRmn:
Setting communication
SDRmn[15:9]:
Setting transfer rate
SOm, SOEm:
Setting output and SCKp output
Perform initial setting when SEmn = 0.
Select the buffer empty interrupt.
Port manipulation
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
No
Buffer empty interrupt
generated?
Yes
Reading receive data to
SIOp (=SDRmn[7:0])
Communication data
exists?
Yes
No
Clearing 0 to MDmn0 bit
TSFmn = 1?
No
Yes
Transfer end interrupt
generated?
No
Yes
Reading receive data to
SIOp (=SDRmn[7:0])
Yes
Writing 1 to MDmn0 bit
Communication continued?
No
Writing 1 to STmn bit
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Remark
to in the figure correspond to to in Figure 14-44
Timing Chart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode).
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14.5.4 Slave transmission
Slave transmission is that the 78K0R/Lx3 microcontrollers transmit data to another device in the state of a transfer clock
being input from another device.
3-Wire Serial I/O
CSI00
CSI01
CSI10
CSI20
Target channel
Channel 0 of SAU0
Channel 1 of SAU0
Channel 2 of SAU0
Channel 0 of SAU1
Pins used
SCK00, SO00
SCK01, SO01
SCK10, SO10
SCK20, SO20
Interrupt
INTCSI00
INTCSI01
INTCSI10
INTCSI20
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag
Overrun error detection flag (OVFmn) only
Transfer data length
7 or 8 bits
Transfer rate
Max. fMCK/6 [MHz]
Data phase
Selectable by DAPmn bit
Notes 1, 2
• DAPmn = 0: Data output starts from the start of the operation of the serial clock.
• DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Clock phase
Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction
MSB or LSB first
Notes 1. Because the external serial clock input to pins SCK00, SCK01, SCK10, and SCK20 is sampled internally and
used, the fastest transfer rate is fMCK/6 [MHz].
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. fMCK: Operation clock (MCK) frequency of target channel
2. For 78K0R/LF3, CSI00 and CSI01 are not mounted.
3. For 78K0R/LG3, CSI01 is not mounted.
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(1) Register setting
Figure 14-46. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O
(CSI00, CSI01, CSI10, CSI20)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15
14
13
12
11
0
0
0
0
1
SOm
10
9
8
7
6
5
4
3
0
0
0
0
1
CKOm2 CKOm1 CKOm0
×
×
×
2
1
0
SOm2
SOm1
SOm0
0/1
0/1
0/1
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
2
1
0
SOEm2 SOEm1 SOEm0
0/1
0/1
0/1
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
SSm2
SSm1
SSm0
×
0/1
0/1
0/1
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
1
STSmn
0
SISmn0
0
MDmn2 MDmn1 MDmn0
0
0
0
0/1
Operation mode of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(e) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
1
0
0/1
0/1
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0
0
0/1
5
4
3
SLCmn1 SLCmn0
2
1
0
DLSmn2 DLSmn1 DLSmn0
0
0
0
0
1
1
0/1
6
5
4
3
2
1
0
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15
14
13
12
11
10
9
8
7
SDRmn
Baud rate setting
0
Transmit data setting
SIOp
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
: Setting is fixed in the CSI slave transmission mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Operation procedure
Figure 14-47. Initial Setting Procedure for Slave Transmission
Starting initial setting
Setting PER0 register
Setting SPSm register
Release the serial array unit from the
reset status and start clock supply.
Set the prescaler.
Setting SMRmn register
Set an operation mode, etc.
Setting SCRmn register
Set a communication format.
Setting SDRmn register
Setting SOm register
Set bits 15 to 9 to 0000000B for baud
rate setting.
Manipulate the SOmn bit and set an
initial output level.
Set the SOEmn bit to 1 and enable data
Changing setting of SOEm register
output of the target channel.
Enable data output of the target channel
Setting port
by setting a port register and a port mode
register.
Writing to SSm register
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set transmit data to the SIOp register
Starting communication
(bits 7 to 0 of the SDRmn register) and
wait for a clock from the master.
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
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Figure 14-48. Procedure for Stopping Slave Transmission
Starting setting to stop
Setting STm register
Changing setting of SOEm
register
Stopping communication
Remark
Write 1 to the STmn bit of the target
channel.
Set the SOEm register and stop the
output of the target channel.
Stop communication in midway.
Even after communication is stopped, the pin level is retained. To resume the operation, re-set the SOm
register (see Figure 14-49 Procedure for Resuming Slave Transmission).
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Figure 14-49. Procedure for Resuming Slave Transmission
Starting setting for resumption
Stop the target for communication or wait
(Essential)
Manipulating target for communication
until the target completes its operation.
Disable data output of the target channel
(Selective)
Port manipulation
by setting a port register and a port
mode register.
Change the setting if an incorrect division
(Selective)
Changing setting of SPSm register
ratio of the operation clock is set.
Change the setting if the setting of the
(Selective)
Changing setting of SMRmn register
(Selective)
Changing setting of SCRmn register
SMRmn register is incorrect.
Change the setting if the setting of the
SCRmn register is incorrect.
Cleared by using SIRmn register if FEF,
(Selective)
Clearing error flag
PEF, or OVF flag remains set.
Set the SOEm register and stop the
(Selective)
Changing setting of SOEm register
(Selective)
Changing setting of SOm register
(Selective)
Changing setting of SOEm register
output of the target channel.
Manipulate the SOmn and CKOmn bits
and set an initial output level.
Set the SOEm register and enable the
output of the target channel.
Enable data output of the target channel
(Essential)
Port manipulation
by setting a port register and a port
mode register.
Set the SSmn bit of the target channel to
(Essential)
Writing to SSm register
(Essential)
Starting communication
1 to set SEmn = 1.
Set transmit data to the SIOp register (bits 7
to 0 of the SDRmn register) and wait for a
clock from the master.
(Essential)
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Starting target for communication
Start the target for communication.
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(3) Processing flow (in single-transmission mode)
Figure 14-50. Timing Chart of Slave Transmission (in Single-Transmission Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Transmit data 1
Transmit data 2
Transmit data 3
SCKp pin
SOp pin
Transmit data 1
Shift
register mn
INTCSIp
Shift operation
Data transmission (8-bit length)
Transmit data 2
Shift operation
Data transmission (8-bit length)
Transmit data 3
Shift operation
Data transmission (8-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 14-51. Flowchart of Slave Transmission (in Single-Transmission Mode)
Starting CSI communication
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
SMRmn, SCRmn: Setting communication
SDRmn[15:9]:
Setting transfer rate
SOm, SOEm:
Setting output
Perform initial setting when SEmn = 0.
Port manipulation
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
Transfer end interrupt
generated?
No
Yes
No
Transmission completed?
Yes
Writing 1 to STmn bit
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
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(4) Processing flow (in continuous transmission mode)
Figure 14-52. Timing Chart of Slave Transmission (in Continuous Transmission Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Transmit data 1
Transmit data 3
Transmit data 2
SCKp pin
SOp pin
Transmit data 1
Shift
register mn
INTCSIp
Transmit data 3
Transmit data 2
Shift operation
Shift operation
Data transmission (8-bit length)
Shift operation
Data transmission (8-bit length)
Data transmission (8-bit length)
MDmn0
TSFmn
BFFmn
(Note)
Note When transmit data is written to the SDRmn register while BFFmn = 1, the transmit data is overwritten.
Caution
The MDmn0 bit can be rewritten even during operation. However, rewrite it before transfer of the
last bit is started.
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Figure 14-53. Flowchart of Slave Transmission (in Continuous Transmission Mode)
Starting CSI communication
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
SMRmn, SCRmn:
Setting communication
SDRmn[15:9]:
Setting transfer rate
SOm, SOEm:
Setting output
Perform initial setting when SEmn = 0.
Select the buffer empty interrupt.
Port manipulation
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
No
Buffer empty interrupt
generated?
Yes
Yes
Transmitting next data?
No
Clearing 0 to MDmn0 bit
No
TSFmn = 1?
Yes
No
Transfer end interrupt
generated?
Yes
Writing 1 to MDmn0 bit
Yes
Communication continued?
No
Writing 1 to STmn bit
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Remark
to in the figure correspond to to in Figure 14-52
Timing Chart of Slave
Transmission (in Continuous Transmission Mode).
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14.5.5 Slave reception
Slave reception is that the 78K0R/Lx3 microcontrollers receive data from another device in the state of a transfer clock
being input from another device.
3-Wire Serial I/O
CSI00
CSI01
CSI10
CSI20
Target channel
Channel 0 of SAU0
Channel 1 of SAU0
Channel 2 of SAU0
Channel 0 of SAU1
Pins used
SCK00, SI00
SCK01, SI01
SCK10, SI10
SCK20, SI20
Interrupt
INTCSI00
INTCSI01
INTCSI10
INTCSI20
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag
Overrun error detection flag (OVFmn) only
Transfer data length
7 or 8 bits
Transfer rate
Max. fMCK/6 [MHz]
Data phase
Selectable by DAPmn bit
Notes 1, 2
• DAPmn = 0: Data input starts from the start of the operation of the serial clock.
• DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Clock phase
Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction
MSB or LSB first
Notes 1. Because the external serial clock input to pins SCK00, SCK01, SCK10, and SCK20 is sampled internally and
used, the fastest transfer rate is fMCK/6 [MHz].
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. fMCK: Operation clock (MCK) frequency of target channel
2. For 78K0R/LF3, CSI00 and CSI01 are not mounted.
3. For 78K0R/LG3, CSI01 is not mounted.
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(1) Register setting
Figure 14-54. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10, CSI20)
(a) Serial output register m (SOm)
15
14
13
12
11
0
0
0
0
1
SOm
10
9
8
7
6
5
4
3
0
0
0
0
1
CKOm2 CKOm1 CKOm0
×
×
×
2
1
0
SOm2
SOm1
SOm0
×
×
×
(b) Serial output enable register m (SOEm) … Clears only the bits of the target channel to 0.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
2
1
0
SOEm2 SOEm1 SOEm0
0/1
0/1
0/1
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
SSm2
SSm1
SSm0
×
0/1
0/1
0/1
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
1
STSmn
0
SISmn0
0
MDmn2 MDmn1 MDmn0
0
0
0
0
Operation mode of channel n
0: Transfer end interrupt
(e) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
0
1
0/1
0/1
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0
0
0/1
5
4
3
SLCmn1 SLCmn0
2
1
0
DLSmn2 DLSmn1 DLSmn0
0
0
0
0
1
1
0/1
6
5
4
3
2
1
0
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15
SDRmn
14
13
12
11
0000000
(baud rate setting)
10
9
8
7
0
Receive data register
SIOp
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
: Setting is fixed in the CSI slave reception mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Operation procedure
Figure 14-55. Initial Setting Procedure for Slave Reception
Starting initial settings
Setting PER0 register
Setting SPSm register
Release the serial array unit from the
reset status and start clock supply.
Set the prescaler.
Setting SMRmn register
Set an operation mode, etc.
Setting SCRmn register
Set a communication format.
Setting SDRmn register
Set bits 15 to 9 to 0000000B for baud
rate setting.
Enable data input and clock input of the
Setting port
target channel by setting a port register
and a port mode register.
Writing to SSm register
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Starting communication
Caution
Wait for a clock from the master.
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Figure 14-56. Procedure for Stopping Slave Reception
Starting setting to stop
Setting STm register
Stopping communication
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Write 1 to the STmn bit of the target
channel.
Stop communication in midway.
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Figure 14-57. Procedure for Resuming Slave Reception
Starting setting for resumption
(Essential)
Stop the target for communication or wait
Manipulating target for communication
until the target completes its operation.
Disable clock output of the target
(Essential)
Port manipulation
(Selective)
Changing setting of SPSm register
(Selective)
Changing setting of SMRmn register
(Selective)
Changing setting of SCRmn register
(Selective)
Changing setting of SDRmn register
(Selective)
Changing setting of SOm register
(Essential)
Changing setting of SOEm register
(Selective)
Clearing error flag
(Essential)
Port manipulation
channel by setting a port register and a
port mode register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Change the setting if the setting of the
SCRmn register is incorrect.
Change the setting if the setting of the
SDRmn register is incorrect.
Manipulate the CKOmn bit and enable
reception.
Clear the SOEm register to 0 and stop
data output of the target channel.
Cleared by using SIRmn register if FEF,
PEF, or OVF flag remains set.
Enable clock output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to
(Essential)
Writing to SSm register
1 to set SEmn = 1.
(Essential)
Starting communication
Wait for a clock from the master.
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(3) Processing flow (in single-reception mode)
Figure 14-58. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Receive data 3
Receive data 2
Receive data 1
Read
Read
Read
SCKp pin
SIp pin
Shift
register mn
INTCSIp
Receive data 1
Reception & shift operation
Data reception (8-bit length)
Receive data 2
Reception & shift operation
Data reception (8-bit length)
Receive data 3
Reception & shift operation
Data reception (8-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 14-59. Flowchart of Slave Reception (in Single-Reception Mode)
Starting CSI communication
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
SMRmn, SCRmn:
Setting communication
SDRmn[15:9]:
Setting transfer rate
SOm, SOEm:
Setting SCKp output
Perform initial setting when SEmn = 0.
Port manipulation
Writing 1 to SSmn bit
Starting reception
Transfer end interrupt
generated?
No
Yes
Reading
SIOp (=SDRmn[7:0])
register
No
Reception completed?
Yes
Writing 1 to STmn bit
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
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CHAPTER 14 SERIAL ARRAY UNIT
14.5.6 Slave transmission/reception
Slave transmission/reception is that the 78K0R/Lx3 microcontrollers transmit/receive data to/from another device in the
state of a transfer clock being input from another device.
3-Wire Serial I/O
CSI00
CSI01
CSI10
CSI20
Target channel
Channel 0 of SAU0
Channel 1 of SAU0
Channel 2 of SAU0
Channel 0 of SAU1
Pins used
SCK00, SI00, SO00
SCK01, SI01, SO01
SCK10, SI10, SO10
SCK20, SI20, SO20
Interrupt
INTCSI00
INTCSI01
INTCSI10
INTCSI20
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag
Overrun error detection flag (OVFmn) only
Transfer data length
7 or 8 bits
Transfer rate
Max. fMCK/6 [MHz]
Data phase
Selectable by DAPmn bit
Notes 1, 2
• DAPmn = 0: Data I/O starts from the start of the operation of the serial clock.
• DAPmn = 1: Data I/O starts half a clock before the start of the serial clock operation.
Clock phase
Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction
MSB or LSB first
Notes 1. Because the external serial clock input to pins SCK00, SCK01, SCK10, and SCK20 is sampled internally and
used, the fastest transfer rate is fMCK/6 [MHz].
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. fMCK: Operation clock (MCK) frequency of target channel
2. For 78K0R/LF3, CSI00 and CSI01 are not mounted.
3. For 78K0R/LG3, CSI01 is not mounted.
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(1) Register setting
Figure 14-60. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10, CSI20)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15
14
13
12
11
0
0
0
0
1
SOm
10
9
8
7
6
5
4
3
0
0
0
0
1
CKOm2 CKOm1 CKOm0
×
×
×
2
1
0
SOm2
SOm1
SOm0
0/1
0/1
0/1
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
2
1
0
SOEm2 SOEm1 SOEm0
0/1
0/1
0/1
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
SSm2
SSm1
SSm0
×
0/1
0/1
0/1
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
1
STSmn
0
SISmn0
0
MDmn2 MDmn1 MDmn0
0
0
0
0/1
Operation mode of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(e) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
1
1
0/1
0/1
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0
0
0/1
5
4
3
SLCmn1 SLCmn0
2
1
0
DLSmn2 DLSmn1 DLSmn0
0
0
0
0
1
1
0/1
6
5
4
3
2
1
0
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15
SDRmn
14
13
12
11
0000000
(baud rate setting)
10
9
8
7
0
Transmit data setting/receive data register
SIOp
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
: Setting is fixed in the CSI slave transmission/reception mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Operation procedure
Figure 14-61. Initial Setting Procedure for Slave Transmission/Reception
Starting initial setting
Setting PER0 register
Setting SPSm register
Release the serial array unit from the
reset status and start clock supply.
Set the prescaler.
Setting SMRmn register
Set an operation mode, etc.
Setting SCRmn register
Set a communication format.
Setting SDRmn register
Setting SOm register
Changing setting of SOEm register
Set bits 15 to 9 to 0000000B for baud
rate setting.
Manipulate the SOmn bit and set an
initial output level.
Set the SOEmn bit to 1 and enable data
output of the target channel.
Enable data output of the target channel
Setting port
by setting a port register and a port
mode register.
Writing to SSm register
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set transmit data to the SIOp register
Starting communication
(bits 7 to 0 of the SDRmn register) and
wait for a clock from the master.
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
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Figure 14-62. Procedure for Stopping Slave Transmission/Reception
Starting setting to stop
Setting STm register
Changing setting of SOEm
register
Stopping communication
Remark
Write 1 to the STmn bit of the target
channel.
Set the SOEm register and stop the
output of the target channel.
Stop communication in midway.
Even after communication is stopped, the pin level is retained. To resume the operation, re-set the SOm
register (see Figure 14-63 Procedure for Resuming Slave Transmission/Reception).
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Figure 14-63. Procedure for Resuming Slave Transmission/Reception
Starting setting for resumption
(Essential)
Manipulating target for communication
Stop the target for communication or wait
until the target completes its operation.
Disable data output of the target channel
Port manipulation
(Essential)
by setting a port register and a port
mode register.
(Selective)
Changing setting of SPSm register
(Selective)
Changing setting of SDRm register
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if an incorrect division
ratio of the operation clock is set.
(Selective)
Changing setting of SMRmn register
(Selective)
Changing setting of SCRmn register
Change the setting if the setting of the
SMRmn register is incorrect.
Change the setting if the setting of the
SCRmn register is incorrect.
Cleared by using SIRmn register if FEF,
Clearing error flag
(Selective)
(Selective)
Changing setting of SOEm register
PEF, or OVF flag remains set.
Set the SOEm register and stop the
output of the target channel.
(Selective)
Changing setting of SOm register
(Selective)
Changing setting of SOEm register
Manipulate the SOmn bit and set an
initial output level.
Set the SOEm register and enable the
output of the target channel.
Enable data output of the target channel
(Essential)
Port manipulation
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to
(Essential)
Writing to SSm register
(Essential)
Starting communication
1 to set SEmn = 1.
Set transmit data to the SIOp register
(bits 7 to 0 of the SDRmn register) and
wait for a clock from the master.
(Essential)
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Start the target for communication.
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(3) Processing flow (in single-transmission/reception mode)
Figure 14-64. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
Receive data 1
SDRmn
Transmit data 1
Write
Receive data 2
Receive data 3
Transmit data 3
Transmit data 2
Write
Read
Write
Read
Read
SCKp pin
SIp pin
Shift
register mn
SOp pin
Receive data 1
Reception & shift operation
Transmit data 1
Receive data 2
Reception & shift operation
Transmit data 2
Receive data 3
Reception & shift operation
Transmit data 3
INTCSIp
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 14-65. Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode)
Starting CSI communication
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
SMRmn, SCRmn:
Setting communication
SDRmn[15:9]:
Setting transfer rate
SOm, SOEm:
Setting output
Perform initial setting when SEmn = 0.
Port manipulation
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
Starting transmission/reception
Transfer end interrupt
generated?
No
Yes
Reading
SIOp (=SDRmn[7:0])
register
Transmission/reception
completed?
No
Yes
Writing 1 to STmn bit
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
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(4) Processing flow (in continuous transmission/reception mode)
Figure 14-66. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type
1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Transmit data 1 Transmit data 2
Write
Write
Receive data 1 Transmit data 3
Write
Read
Receive data 3
Receive data 2
Read
Read
SCKp pin
SIp pin
Receive data 2
Receive data 1
Shift
register mn
SOp pin
Reception & shift operation
Receive data 3
Reception & shift operation
Reception & shift operation
Transmit data 1
Transmit data 2
Transmit data 3
INTCSIp
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length) Data transmission/reception (8-bit length)
MDmn0
TSFmn
BFFmn
(Note 1)
(Note 2)
(Note 2)
Notes 1. When transmit data is written to the SDRmn register while BFFmn = 1, the transmit data is overwritten.
2. The transmit data can be read by reading the SDRmn register during this period. At this time, the
transfer operation is not affected.
Caution
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the
transfer end interrupt of the last transmit data.
Remarks 1. to in the figure correspond to to in Figure 14-67
Flowchart of Slave
Transmission/Reception (in Continuous Transmission/Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 14-67. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
Starting CSI communication
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
SMRmn, SCRmn:
Setting communication
SDRmn[15:9]:
Setting transfer rate
SOm, SOEm:
Setting output
Perform initial setting when SEmn = 0.
Select the buffer empty interrupt.
Port manipulation
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
No
Buffer empty interrupt
generated?
Yes
Reading receive data to
SIOp (=SDRmn[7:0])
Communication data
exists?
Yes
No
Clearing 0 to MDmn0 bit
TSFmn = 1?
No
Yes
Transfer end interrupt
generated?
No
Yes
Writing 1 to MDmn0 bit
Reading receive data to
SIOp (=SDRmn[7:0])
Yes
Communication continued?
No
Writing 1 to STmn bit
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Remark
to in the figure correspond to to in Figure 14-66
Timing Chart of Slave
Transmission/Reception (in Continuous Transmission/Reception Mode).
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14.5.7 Calculating transfer clock frequency
The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20) communication can be calculated by
the following expressions.
(1) Master
(Transfer clock frequency) = {Operation clock (MCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz]
(2) Slave
(Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}
Note
[Hz]
Note The permissible maximum frequency is the smaller of fCLK/6 and fMCK/2.
Remarks 1. The value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000000B to
1111111B) and therefore is 0 to 127.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
The operation clock (MCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode
register mn (SMRmn).
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Table 14-2. Selection of operation clock
SMRmn
SPSm Register
Operation Clock (MCK)
Note1
Register
CKSmn
PRS PRS PRS PRS PRS PRS PRS PRS
fCLK = 20 MHz
m13
m12
m11
m10
m03
m02
m01
m00
X
X
X
X
0
0
0
0
fCLK
X
X
X
X
0
0
0
1
fCLK/2
X
X
X
X
0
0
1
0
fCLK/2
2
5 MHz
fCLK/2
3
2.5 MHz
1.25 MHz
0
X
X
X
X
0
0
1
1
20 MHz
10 MHz
X
X
X
X
0
1
0
0
fCLK/2
4
X
X
X
X
0
1
0
1
fCLK/2
5
625 kHz
fCLK/2
6
313 kHz
156 kHz
X
X
X
X
0
1
1
0
X
X
X
X
0
1
1
1
fCLK/2
7
X
X
X
X
1
0
0
0
fCLK/2
8
78.1 kHz
fCLK/2
9
39.1 kHz
19.5 kHz
9.77 kHz
X
X
X
X
1
0
0
1
X
X
X
X
1
0
1
0
fCLK/2
10
X
X
X
X
1
0
1
1
fCLK/2
11
X
X
X
X
1
1
1
1
INTTM02 if m = 0,
INTTM03 if m = 1
1
Note2
0
0
0
0
X
X
X
X
fCLK
0
0
0
1
X
X
X
X
fCLK/2
0
0
1
0
X
X
X
X
fCLK/2
2
5 MHz
fCLK/2
3
2.5 MHz
1.25 MHz
0
0
1
1
X
X
X
X
20 MHz
10 MHz
0
1
0
0
X
X
X
X
fCLK/2
4
0
1
0
1
X
X
X
X
fCLK/2
5
625 kHz
fCLK/2
6
313 kHz
156 kHz
0
1
1
0
X
X
X
X
0
1
1
1
X
X
X
X
fCLK/2
7
1
0
0
0
X
X
X
X
fCLK/2
8
78.1 kHz
fCLK/2
9
39.1 kHz
19.5 kHz
9.77 kHz
1
0
0
1
X
X
X
X
1
0
1
0
X
X
X
X
fCLK/2
10
1
0
1
1
X
X
X
X
fCLK/2
11
1
1
1
1
X
X
X
X
INTTM02 if m = 0,
INTTM03 if m = 1
Other than above
Note2
Setting prohibited
Notes 1. When changing the clock selected for fCLK (by changing the system clock control register (CKC) value),
do so after having stopped (STm = 000FH) the operation of the serial array unit (SAUm). When
selecting INTTM02 and INTTM03 for the operation clock, also stop the timer array unit (TAU0) (TT0 =
00FFH).
2. SAUm can be operated at a fixed division ratio of the subsystem clock, regardless of the fCLK frequency
(main system clock, subsystem clock), by operating the interval timer for which fSUB/4 has been
selected as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of the TIS0 register to 1) and
selecting INTTM02 and INTTM03 by using the SPSm register in channels 2 and 3 of TAU0. When
changing fCLK, however, SAUm and TAU0 must be stopped as described in Note 1 above.
Remarks 1. X: Don’t care
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
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14.6 Operation of UART (UART0, UART1, UART2, UART3) Communication
This is a start-stop synchronization function using two lines: serial data transmission (TxD) and serial data reception
(RxD) lines. It transmits or receives data in asynchronization with the party of communication (by using an internal baud
rate). Full-duplex UART communication can be realized by using two channels, one dedicated to transmission (even
channel) and the other to reception (odd channel).
[Data transmission/reception]
• Data length of 5, 7, or 8 bits
• Select the MSB/LSB first
• Level setting of transmit/receive data and select of reverse
• Parity bit appending and parity check functions
• Stop bit appending
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
• Error interrupt in case of framing error, parity error, or overrun error
[Error detection flag]
• Framing error, parity error, or overrun error
The LIN-bus is supported in UART3 (2, 3 channels of unit 1)
[LIN-bus functions]
• Wakeup signal detection
External interrupt (INTP0) or timer array unit (TAU) is
• Sync break field (SBF) detection
• Sync field measurement, baud rate calculation
used.
UART0 uses channels 0 and 1 of SAU0.
UART1 uses channels 2 and 3 of SAU0.
UART2 uses channels 0 and 1 of SAU1.
UART3 uses channels 2 and 3 of SAU1.
0
1
Caution
2
Used as CSI
Used as UART
Used as Simplified I C
0
CSI00
UART0
−
1
CSI01
2
CSI10
3
−
0
CSI20
1
−
2
−
3
−
Unit
Channel
−
UART1
IIC10
−
UART2
IIC20
−
UART3 (supporting LIN-bus)
−
−
When using serial array units 0 and 1 as UARTs, the channels of both the transmitting side (evennumber channel) and the receiving side (odd-number channel) can be used only as UARTs.
Remark For 78K0R/LF3, UART0 is not mounted.
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UART performs the following four types of communication operations.
• UART transmission
(See 14.6.1.)
• UART reception
(See 14.6.2.)
• LIN transmission (UART3 only) (See 14.6.3.)
• LIN reception (UART 3 only)
(See 14.6.4.)
14.6.1 UART transmission
UART transmission is an operation to transmit data from the 78K0R/Lx3 microcontrollers to another device
asynchronously (start-stop synchronization).
Of two channels used for UART, the even channel is used for UART transmission.
UART
UART0
UART1
UART2
UART3
Target channel
Channel 0 of SAU0
Channel 2 of SAU0
Channel 0 of SAU1
Channel 2 of SAU1
Pins used
TxD0
TxD1
TxD2
TxD3
Interrupt
INTST0
INTST1
INTST2
INTST3
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag
None
Transfer data length
5, 7, or 8 bits
Transfer rate
Max. fMCK/6 [bps] (SDRmn [15:9] = 2 or more), Min. fCLK/(2 × 2 × 128) [bps]
Data phase
11
Note
Forward output (default: high level)
Reverse output (default: low level)
Parity bit
The following selectable
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
Stop bit
The following selectable
• Appending 1 bit
• Appending 2 bits
Data direction
MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. fMCK: Operation clock (MCK) frequency of target channel
fCLK: System clock frequency
2. For 78K0R/LF3, UART0 is not mounted.
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(1) Register setting
Figure 14-68. Example of Contents of Registers for UART Transmission of UART
(UART0, UART1, UART2, UART3) (1/2)
(a) Serial output register m (SOm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
0
0
0
0
1
SOm
10
9
8
7
6
5
4
3
2
1
SOm2
SOm1
SOm0
0
0
0
0
1
0/1Note
×
0/1Note
CKOm2 CKOm1 CKOm0
×
×
×
0
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
2
1
0
SOEm2 SOEm1 SOEm0
0/1
×
0/1
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
0
SSm
3
2
1
0
SSm3
SSm2
SSm1
SSm0
×
0/1
×
0/1
1
0
(d) Serial output level register m (SOLm) … Sets only the bits of the target channel.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOLm
2
SOLm2
SOLm0
0/1
0
0/1
2
1
0
0: Forward (normal) transmission
1: Reverse transmission
(e) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
0
8
7
STSmn
0
6
5
4
3
1
0
0
SISmn0
0
0
MDmn2 MDmn1 MDmn0
0
1
0/1
Operation mode of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
Note Before transmission is started, be sure to set to 1 when the SOLmn bit of the target channel is set to 0, and
set to 0 when the SOLmn bit of the target channel is set to 1. The value varies depending on the
communication data during communication operation.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3)
: Setting is fixed in the UART transmission mode,
: Setting disabled (fixed by hardware)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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Figure 14-68. Example of Contents of Registers for UART Transmission of UART
(UART0, UART1, UART2, UART3) (2/2)
(f) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
1
0
0
0
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0/1
0/1
0/1
5
4
3
SLCmn1 SLCmn0
0
0/1
0/1
2
1
0
DLSmn2 DLSmn1 DLSmn0
0
1
0/1
0/1
Setting of parity bit
Setting of stop bit
00B: No parity
01B: Appending 1 bit
10B: Appending 2 bits
01B: 0 parity
10B: Even parity
11B: Odd parity
(g) Serial data register mn (SDRmn) (lower 8 bits: TXDq)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDRmn
Baud rate setting
0
Transmit data setting
TXDq
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3)
: Setting is fixed in the UART transmission mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Operation procedure
Figure 14-69. Initial Setting Procedure for UART Transmission
Starting initial setting
Setting PER0 register
Setting SPSm register
Release the serial array unit from the
reset status and start clock supply.
Set the prescaler.
Setting SMRmn register
Set an operation mode, etc.
Setting SCRmn register
Set a communication format.
Setting SDRmn register
Set a transfer baud rate.
Changing setting of SOLm register
Set an output data level.
Setting SOm register
Manipulate the SOmn bit and set an
initial output level.
Set the SOEmn bit to 1 and enable data
Changing setting of SOEm register
output of the target channel.
Enable data output of the target channel
Setting port
by setting a port register and a port mode
register.
Writing to SSm register
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set transmit data to the TXDq register (bits
Starting communication
7 to 0 of the SDRmn register) and start
communication.
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
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Figure 14-70. Procedure for Stopping UART Transmission
Starting setting to stop
Setting STm register
Changing setting of SOEm
register
Stopping communication
Remark
Write 1 to the STmn bit of the target
channel.
Set the SOEmn bit to 0 and stop the
output.
Stop communication in midway.
Even after communication is stopped, the pin level is retained. To resume the operation, re-set the SOm
register (see Figure 14-71 Procedure for Resuming UART Transmission).
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Figure 14-71. Procedure for Resuming UART Transmission
Starting setting for resumption
Disable data output of the target channel
(Essential)
Port manipulation
(Selective)
Changing setting of SPSm register
(Selective)
Changing setting of SDRm register
(Selective)
Changing setting of SMRmn register
(Selective)
Changing setting of SCRmn register
(Selective)
Changing setting of SOLmn register
(Essential)
Changing setting of SOEm register
(Essential)
Changing setting of SOm register
(Essential)
Changing setting of SOEm register
by setting a port register and a port mode
register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if an incorrect
transfer baud rate is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Change the setting if the setting of the
SCRmn register is incorrect.
Change the setting if the setting of the
SOLmn register is incorrect.
Clear the SOEmn bit to 0 and stop
output.
Manipulate the SOmn bit and set an
initial output level.
Set the SOEmn bit to 1 and enable
output.
Enable data output of the target channel
(Essential)
Port manipulation
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to
(Essential)
Writing to SSm register
(Essential)
Starting communication
1 to set SEmn = 1.
Sets transmit data to the TXDq register
(bits 7 to 0 of the SDRmn register) and
start communication.
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(3) Processing flow (in single-transmission mode)
Figure 14-72. Timing Chart of UART Transmission (in Single-Transmission Mode)
SSmn
STmn
SEmn
SDRmn
TxDq pin
Shift
register mn
Transmit data 1
ST
Transmit data 1
Transmit data 2
P SP
Shift operation
ST Transmit data 2
Transmit data 3
P SP
Shift operation
ST
Transmit data 3
P SP
Shift operation
INTSTq
Data transmission (7-bit length)
Data transmission (7-bit length)
Data transmission (7-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3)
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Figure 14-73. Flowchart of UART Transmission (in Single-Transmission Mode)
Starting UART communication
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
SMRmn, SCRmn:
Setting communication
SDRmn[15:9]:
Setting transfer rate
SOLmn:
Setting output data level
SOm, SOEm:
Setting output
Perform initial setting when SEmn = 0.
Port manipulation
Writing 1 to SSmn bit
Writing transmit data to
TXDq (=SDRmn[7:0])
Transfer end interrupt
generated?
No
Yes
Transmission completed?
No
Yes
Writing 1 to STmn bit
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
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(4) Processing flow (in continuous transmission mode)
Figure 14-74. Timing Chart of UART Transmission (in Continuous Transmission Mode)
SSmn
STmn
SEmn
SDRmn
Transmit data 1
TxDq pin
ST
Shift
register mn
Transmit data 3
Transmit data 2
Transmit data 1
P SP ST
Shift operation
Transmit data 2
P SP ST
Shift operation
Transmit data 3
P SP
Shift operation
INTSTq
Data transmission (7-bit length)
Data transmission (7-bit length)
Data transmission (7-bit length)
MDmn0
TSFmn
BFFmn
(Note)
Note When transmit data is written to the SDRmn register while BFFmn = 1, the transmit data is overwritten.
Caution
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the
transfer end interrupt of the last transmit data.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3)
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Figure 14-75. Flowchart of UART Transmission (in Continuous Transmission Mode)
Starting UART communication
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
SMRmn, SCRmn: Setting communication
Perform initial setting when SEmn = 0.
SDRmn[15:9]:
Setting transfer rate
SOLmn:
Setting output data level
SOm, SOEm:
Setting output
Select the buffer empty interrupt.
Port manipulation
Writing 1 to SSmn bit
Writing transmit data to
TXDq (=SDRmn[7:0])
No
Buffer empty interrupt
generated?
Yes
Yes
Transmitting next data?
No
Clearing 0 to MDmn0 bit
No
TSFmn = 1?
Yes
Transfer end interrupt
generated?
No
Yes
Writing 1 to MDmn0 bit
Yes
Communication continued?
No
Writing 1 to STmn bit
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Caution After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Remark
to in the figure correspond to to in Figure 14-74
Timing Chart of UART
Transmission (in Continuous Transmission Mode).
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14.6.2 UART reception
UART reception is an operation wherein the 78K0R/Lx3 microcontrollers asynchronously receive data from another
device (start-stop synchronization).
For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both
the odd- and even-numbered channels must be set.
UART
UART0
UART1
UART2
UART3
Target channel
Channel 1 of SAU0
Channel 3 of SAU0
Channel 1 of SAU1
Channel 3 of SAU1
Pins used
RxD0
RxD1
RxD2
RxD3
Interrupt
INTSR0
INTSR1
INTSR2
INTSR3
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error interrupt
INTSRE0
INTSRE1
Error detection flag
• Framing error detection flag (FEFmn)
INTSRE2
INTSRE3
• Parity error detection flag (PEFmn)
• Overrun error detection flag (OVFmn)
Transfer data length
5, 7 or 8 bits
Transfer rate
Max. fMCK/6 [bps] (SDRmn [15:9] = 2 or more), Min. fCLK/(2 × 2 × 128) [bps]
Data phase
11
Note
Forward output (default: high level)
Reverse output (default: low level)
Parity bit
The following selectable
• No parity bit (no parity check)
• Appending 0 parity (no parity check)
• Appending even parity
• Appending odd parity
Stop bit
Appending 1 bit
Data direction
MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. fMCK: Operation clock (MCK) frequency of target channel
fCLK: System clock frequency
2. For 78K0R/LF3, UART0 is not mounted.
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(1) Register setting
Figure 14-76. Example of Contents of Registers for UART Reception of UART
(UART0, UART1, UART2, UART3) (1/2)
(a) Serial output register m (SOm)
15
14
13
12
11
0
0
0
0
1
SOm
10
9
8
7
6
5
4
3
0
0
0
0
1
CKOm2 CKOm1 CKOm0
×
×
×
2
1
0
SOm2
SOm1
SOm0
×
×
×
(b) Serial output enable register m (SOEm) … Sets the bits of the target channel to 0.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
2
1
0
SOEm2 SOEm1 SOEm0
×
×
0/1
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel is 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
SSm2
SSm1
SSm0
0/1
×
0/1
×
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
0
STSmn
1
SISmn0
0
0/1
MDmn2 MDmn1 MDmn0
0: Forward (normal) reception
1: Reverse reception
0
1
0
Operation mode of channel n
0: Transfer end interrupt
(e) Serial mode register mr (SMRmr)
15
SMRmr
14
13
12
11
10
9
0
0
0
0
0
CKSmr CCSmr
0/1
0
8
7
STSmr
0
6
5
4
3
1
0
0
SISmr0
0
0
2
1
0
MDmr2 MDmr1 MDmr0
Same setting value as CKSmn
0
1
0/1
Operation mode of channel r
0: Transfer end interrupt
1: Buffer empty interrupt
(f) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
0
Caution
Remark
1
0
0
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
1
0/1
0/1
5
4
3
SLCmn1 SLCmn0
0/1
0
0
1
2
1
0
DLSmn2 DLSmn1 DLSmn0
0
1
0/1
0/1
For the UART reception, be sure to set SMRmr of channel r that is to be paired with channel n.
m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), r: Channel number (r = n − 1),
q: UART number (q = 0 to 3)
: Setting is fixed in the UART reception mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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Figure 14-76. Example of Contents of Registers for UART Reception of UART
(UART0, UART1, UART2, UART3) (2/2)
(g) Serial data register mn (SDRmn) (lower 8 bits: RXDq)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDRmn
Baud rate setting
0
Receive data register
RXDq
Caution
For the UART reception, be sure to set SMRmr of channel r that is to be paired with channel n.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), r: Channel number (r = n − 1),
q: UART number (q = 0 to 3)
: Setting is fixed in the UART reception mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Operation procedure
Figure 14-77. Initial Setting Procedure for UART Reception
Starting initial setting
Setting PER0 register
Setting SPSm register
Setting SMRmn and SMRmr registers
Setting SCRmn register
Setting SDRmn register
Writing to SSm register
Starting communication
Caution
Release the serial array unit from the
reset status and start clock supply.
Set the prescaler.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
The start bit is detected.
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Figure 14-78. Procedure for Stopping UART Reception
Starting setting to stop
Setting STm register
Stopping communication
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Write 1 to the STmn bit of the target
channel.
Stop communication in midway.
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Figure 14-79. Procedure for Resuming UART Reception
Starting setting for resumption
Stop the target for communication or wait
(Essential)
Manipulating target for communication
(Selective)
Changing setting of SPSm register
(Selective)
Changing setting of SDRmn register
until the target completes its operation.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if an incorrect
Changing setting of SMRmn
(Selective)
and SMRmr registers
transfer baud rate is set.
Change the setting if the setting of the
SMRmn and SMRmr registers is incorrect.
Change the setting if the setting of the
(Selective)
Changing setting of SCRmn register
(Essential)
Changing setting of SOEm register
(Selective)
Clearing error flag
(Essential)
Writing to SSm register
1 to set SEmn = 1.
(Essential)
Starting communication
The start bit is detected.
SCRmn register is incorrect.
Clear the SOEm register to 0 and stop
data output of the target channel.
Cleared by using SIRm register if FEF,
PEF, or OVF flag remains set.
Set the SSmn bit of the target channel to
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(3) Processing flow
Figure 14-80. Timing Chart of UART Reception
SSmn
STmn
SEmn
Receive data 3
SDRmn
RxDq pin
Shift
register mn
Receive data 2
Receive data 1
ST
Receive data 1
Shift operation
P SP
ST Receive data 2
P SP
Shift operation
ST
Receive data 3
P SP
Shift operation
INTSRq
Data reception (7-bit length)
Data reception (7-bit length)
Data reception (7-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), q: UART number (q = 0 to 3)
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Figure 14-81. Flowchart of UART Reception
Starting UART communication
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
SMRmn, SMRmr, SCRmn: Setting communication
Perform initial setting when
SEmn = 0.
SDRmn[15:9]:
Setting transfer rate
SOm:
Set CKOmn and SOmn bits to 1
Port manipulation
Writing 1 to SSmn bit
Detecting start bit
Starting reception
Transfer end interrupt
generated?
No
Yes
Error interrupt generated?
No
Yes
Reading RXDq register
(SDRmn[7:0])
Reception completed?
Error processing
No
Yes
Writing 1 to STmn bit
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of UART communication
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
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14.6.3 LIN transmission
Of UART transmission, UART3 supports LIN communication.
For LIN transmission, channel 2 of unit 1 (SAU1) is used.
UART
Support of LIN communication
UART0
UART1
UART2
Not supported
Not supported
Not supported
UART3
Supported
Target channel
−
−
−
Channel 2 of SAU1
Pins used
−
−
−
TxD3
Interrupt
−
−
−
INTST3
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer
mode) can be selected.
Error detection flag
None
Transfer data length
8 bits
Transfer rate
Max. fMCK/6 [bps] (SDRmn [15:9] = 2 or more), Min. fCLK/(2 × 2 × 128) [bps]
Data phase
11
Note
Forward output (default: high level)
Reverse output (default: low level)
Parity bit
The following selectable
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
Stop bit
The following selectable
• Appending 1 bit
• Appending 2 bits
Data direction
MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. fMCK: Operation clock (MCK) frequency of target channel
fCLK: System clock frequency
2. For 78K0R/LF3, UART0 is not mounted.
LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol designed to
reduce the cost of an automobile network.
Communication of LIN is single-master communication and up to 15 slaves can be connected to one master.
The slaves are used to control switches, actuators, and sensors, which are connected to the master via LIN.
Usually, the master is connected to a network such as CAN (Controller Area Network).
A LIN bus is a single-wire bus to which nodes are connected via transceiver conforming to ISO9141.
According to the protocol of LIN, the master transmits a frame by attaching baud rate information to it. A slave receives
this frame and corrects a baud rate error from the master. If the baud rate error of a slave is within ±15%, communication
can be established.
Figure 14-82 outlines a transmission operation of LIN.
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Figure 14-82. Transmission Operation of LIN
Wakeup signal
frame
Sync break
field
Sync field
8 bitsNote 1
13-bit SBF
transmissionNote 2
55H
transmission
Identification Data field
field
Data field
Checksum
field
LIN Bus
Data
Data
Data
Data
transmission transmission transmission transmission
TXD3
(output)
INTST3Note 3
Notes 1. The baud rate is set so as to satisfy the standard of the wakeup signal and data of 00H is transmitted.
2. A sync break field is defined to have a width of 13 bits and output a low level. Where the baud rate for main
transfer is N [bps], therefore, the baud rate of the sync break field is calculated as follows.
(Baud rate of sync break field) = 9/13 × N
By transmitting data of 00H at this baud rate, a sync break field is generated.
3. INTST3 is output upon completion of transmission.
INTST3 is also output when SBF transmission is
executed.
Remark
The interval between fields is controlled by software.
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Figure 14-83. Flowchart for LIN Transmission
Starting LIN communication
Setting baud rate
Writing 1 to SS12
Setting transfer data 00H
Transmitting wakeup
signal frame
Wakeup signal frame
Transfer end interrupt
generated?
Setting transfer data 00H
Transmitting
sync break field
Sync break field
Transfer end interrupt
generated?
Writing 1 to ST12
Setting baud rate
Writing 1 to SS12
Transmitting 55H
Receiving data
Sync field
Identification field
Data field
Checksum field
End of LIN communication
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14.6.4 LIN reception
Of UART reception, UART3 supports LIN communication.
For LIN reception, channel 3 of unit 1 (SAU1) is used.
UART
Support of LIN communication
UART0
UART1
UART2
Not supported
Not supported
Not supported
UART3
Supported
Target channel
−
−
−
Channel 3 of SAU1
Pins used
−
−
−
RxD3
Interrupt
−
−
−
INTSR3
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
−
Error interrupt
Error detection flag
−
−
INTSRE3
• Framing error detection flag (FEF13)
• Parity error detection flag (PEF13)
• Overrun error detection flag (OVF13)
Transfer data length
8 bits
Transfer rate
Max. fMCK/6 [bps] (SDRmn [15:9] = 2 or more), Min. fCLK/(2 × 2 × 128) [bps]
Data phase
11
Note
Forward output (default: high level)
Reverse output (default: low level)
Parity bit
The following selectable
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
Stop bit
The following selectable
• Appending 1 bit
• Appending 2 bits
Data direction
MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. fMCK: Operation clock (MCK) frequency of target channel
fCLK: System clock frequency
2. For 78K0R/LF3, UART0 is not mounted.
Figure 14-84 outlines a reception operation of LIN.
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Figure 14-84. Reception Operation of LIN
Wakeup signal
frame
Sync break
field
Sync field
13-bit SBF
reception
SF
reception
Identification Data filed
field
Data filed Checksum
field
LIN Bus
ID
reception
Data
reception
Data
reception
RXD3 (input)
Disable
Data
reception
Enable
Reception interrupt
(INTSR3)
Edge detection
(INTP0)
Capture
timer
Disable
Enable
Here is the flow of signal processing.
The wakeup signal is detected by detecting an interrupt edge (INTP0) on a pin. When the wakeup signal is
detected, enable reception of UART3 (RXE13 = 1) and wait for SBF reception.
When the start bit of SBF is detected, reception is started and serial data is sequentially stored in the RXD3
register (= bits 7 to 0 of the serial data register 13 (SDR13)) at the set baud rate. When the stop bit is detected,
the reception end interrupt request (INTSR3) is generated. When data of low levels of 11 bits or more is detected
as SBF, it is judged that SBF reception has been correctly completed. If data of low levels of less than 11 bits is
detected as SBF, it is judged that an SBF reception error has occurred, and the system returns to the SBF
reception wait status.
When SBF reception has been correctly completed, start channel 7 of the timer array unit and measure the bit
interval (pulse width) of the sync field (see 6.7.5
Operation as input signal high-/low-level width
measurement).
Calculate a baud rate error from the bit interval of sync field (SF). Stop UART3 once and adjust (re-set) the baud
rate.
The checksum field should be distinguished by software. In addition, processing to initialize UART3 after the
checksum field is received and to wait for reception of SBF should also be performed by software.
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Figure 14-85 shows the configuration of a port that manipulates reception of LIN.
The wakeup signal transmitted from the master of LIN is received by detecting an edge of an external interrupt (INTP0).
The length of the sync field transmitted from the master can be measured by using the external event capture operation of
the timer array unit (TAU) to calculate a baud-rate error.
By controlling switch of port input (ISC0/ISC1), the input source of port input (RxD3) for reception can be input to the
external interrupt pin (INTP0) and timer array unit (TAU).
Figure 14-85. Port Configuration for Manipulating Reception of LIN
P50/RxD3
Selector
RXD3 input
Port mode
(PM50)
Output latch
(P50)
P120/INTP0
Selector
Selector
Port mode
(PM120)
Output latch
(P120)
INTP0 input
Port input
switch control
(ISC0)
0: Selects INTP0 (P120)
1: Selects RxD3 (P50)
P33/TI07
Selector
Selector
Port mode
(PM33)
Output latch
(P33)
Remark
Channel 7 input of TAU
Port input
switch control
(ISC1)
0: Selects TI07 (P33)
1: Selects RxD3 (P50)
ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (See Figure 14-17.)
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The peripheral functions used for the LIN communication operation are as follows.
• External interrupt (INTP0); Wakeup signal detection
Usage: To detect an edge of the wakeup signal and the start of communication
• Channel 7 of timer array unit (TAU); Baud rate error detection
Usage: To detect the length of the sync field (SF) and divide it by the number of bits in order to detect an error (The
interval of the edge input to RxD3 is measured in the capture mode.)
• Channels 2 and 3 (UART3) of serial array unit 1 (SAU1)
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Figure 14-86. Flowchart of LIN Reception
Starting LIN communication
Setting TAU in capture
mode (to measure
low-level width)
Detecting low-level width
Wakeup signal frame
Wakeup detected?
Detecting low-level width
Sync break field
SBF detected?
INTP0,
TAU
Stopping operation
Setting TAU in capture
mode (to measure
low-/high-level width)
Detecting low-level width
Detecting high-level width
Sync field
Detecting low-level width
Detecting high-level width
Calculating baud rate
Setting UART reception mode
Writing 1 to SS13
SAU
Receiving data
For
details,
See
Identification field
Data field
Checksum field
Writing 1 to ST13
Figure
14-81
End of LIN communication
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14.6.5 Calculating baud rate
(1) Baud rate calculation expression
The baud rate for UART (UART0, UART1, UART2, UART3) communication can be calculated by the following
expressions.
(Baud rate) = {Operation clock (MCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [bps]
Caution
Setting SDRmn [15:9] = (0000000B, 0000001B) is prohibited.
Remarks 1.
When UART is used, the value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn
register (0000010B to 1111111B) and therefore is 2 to 127.
2.
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
The operation clock (MCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial
mode register mn (SMRmn).
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Table 14-3. Selection of operation clock
SMRmn
SPSm Register
Operation Clock (MCK)
Note1
Register
CKSmn
PRS PRS PRS PRS PRS PRS PRS PRS
fCLK = 20 MHz
m13
m12
m11
m10
m03
m02
m01
m00
X
X
X
X
0
0
0
0
fCLK
X
X
X
X
0
0
0
1
fCLK/2
X
X
X
X
0
0
1
0
fCLK/2
2
5 MHz
fCLK/2
3
2.5 MHz
1.25 MHz
0
X
X
X
X
0
0
1
1
20 MHz
10 MHz
X
X
X
X
0
1
0
0
fCLK/2
4
X
X
X
X
0
1
0
1
fCLK/2
5
625 kHz
fCLK/2
6
313 kHz
156 kHz
X
X
X
X
0
1
1
0
X
X
X
X
0
1
1
1
fCLK/2
7
X
X
X
X
1
0
0
0
fCLK/2
8
78.1 kHz
fCLK/2
9
39.1 kHz
19.5 kHz
9.77 kHz
X
X
X
X
1
0
0
1
X
X
X
X
1
0
1
0
fCLK/2
10
X
X
X
X
1
0
1
1
fCLK/2
11
X
X
X
X
1
1
1
1
INTTM02 if m = 0,
INTTM03 if m = 1
1
Note2
0
0
0
0
X
X
X
X
fCLK
0
0
0
1
X
X
X
X
fCLK/2
0
0
1
0
X
X
X
X
fCLK/2
2
5 MHz
fCLK/2
3
2.5 MHz
1.25 MHz
0
0
1
1
X
X
X
X
20 MHz
10 MHz
0
1
0
0
X
X
X
X
fCLK/2
4
0
1
0
1
X
X
X
X
fCLK/2
5
625 kHz
fCLK/2
6
313 kHz
156 kHz
0
1
1
0
X
X
X
X
0
1
1
1
X
X
X
X
fCLK/2
7
1
0
0
0
X
X
X
X
fCLK/2
8
78.1 kHz
fCLK/2
9
39.1 kHz
19.5 kHz
9.77 kHz
1
0
0
1
X
X
X
X
1
0
1
0
X
X
X
X
fCLK/2
10
1
0
1
1
X
X
X
X
fCLK/2
11
1
1
1
1
X
X
X
X
INTTM02 if m = 0,
INTTM03 if m = 1
Other than above
Note2
Setting prohibited
Notes 1. When changing the clock selected for fCLK (by changing the system clock control register (CKC) value),
do so after having stopped (STm = 000FH) the operation of the serial array unit (SAUm). When
selecting INTTM02 and INTTM03 for the operation clock, also stop the timer array unit (TAU0) (TT0 =
00FFH).
2. SAUm can be operated at a fixed division ratio of the subsystem clock, regardless of the fCLK frequency
(main system clock, subsystem clock), by operating the interval timer for which fSUB/4 has been
selected as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of the TIS0 register to 1) and
selecting INTTM02 and INTTM03 by using the SPSm register in channels 2 and 3 of TAU0. When
changing fCLK, however, SAUm and TAU0 must be stopped as described in Note 1 above.
Remarks 1. X: Don’t care
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(2) Baud rate error during transmission
The baud rate error of UART (UART0, UART1, UART2, UART3) communication during transmission can be
calculated by the following expression. Make sure that the baud rate at the transmission side is within the
permissible baud rate range at the reception side.
(Baud rate error) = (Calculated baud rate value) ÷ (Target baud rate) × 100 − 100 [%]
Here is an example of setting a UART baud rate at fCLK = 20 MHz.
UART Baud Rate
(Target Baud Rate)
fCLK = 20 MHz
Operation Clock (MCK)
Calculated Baud Rate
Error from Target Baud Rate
64
300.48 bps
+0.16 %
64
600.96 bps
+0.16 %
64
1201.92 bps
+0.16 %
64
2403.85 bps
+0.16 %
64
4807.69 bps
+0.16 %
4
64
9615.38 bps
+0.16 %
fCLK/2
3
64
19230.8 bps
+0.16 %
fCLK/2
3
39
31250.0 bps
±0.0 %
38400 bps
fCLK/2
2
64
38461.5 bps
+0.16 %
76800 bps
fCLK/2
64
76923.1 bps
+0.16 %
153600 bps
fCLK
64
153846 bps
+0.16 %
312500 bps
fCLK
31
312500 bps
±0.0 %
fCLK/2
9
fCLK/2
8
fCLK/2
7
fCLK/2
6
4800 bps
fCLK/2
5
9600 bps
fCLK/2
300 bps
600 bps
1200 bps
2400 bps
19200 bps
31250 bps
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(3) Permissible baud rate range for reception
The permissible baud rate range for reception during UART (UART0, UART1, UART2, UART3) communication can
be calculated by the following expression. Make sure that the baud rate at the transmission side is within the
permissible baud rate range at the reception side.
2 × k × Nfr
(Maximum receivable baud rate) =
× Brate
2 × k × Nfr − k + 2
2 × k × (Nfr − 1)
(Minimum receivable baud rate) =
× Brate
2 × k × Nfr − k − 2
Brate: Calculated baud rate value at the reception side (See 14.6.5 (1) Baud rate calculation expression.)
k:
SDRmn[15:9] + 1
Nfr:
1 data frame length [bits]
= (Start bit) + (Data length) + (Parity bit) + (Stop bit)
Figure 14-87. Permissible Baud Rate Range for Reception (1 Data Frame Length = 11 Bits)
Latch
timing
Data frame length
of SAU
Start
bit
Bit 0
Bit 1
Bit 7
Parity
bit
Stop
bit
FL
1 data frame (11 × FL)
Permissible minimum
data frame length
Start
bit
Bit 0
Bit 1
Parity
bit
Bit 7
Stop
bit
(11 × FL) min.
Permissible maximum
data frame length
Start
bit
Bit 0
Bit 1
Bit 7
Parity
bit
Stop
bit
(11 × FL) max.
As shown in Figure 14-87, the timing of latching receive data is determined by the division ratio set by bits 15 to 9
of the serial data register mn (SDRmn) after the start bit is detected. If the last data (stop bit) is received before this
latch timing, the data can be correctly received.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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2
14.7 Operation of Simplified I C (IIC10, IIC20) Communication
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock
(SCL) and serial data (SDA). This communication function is designed to execute single communication with devices such
as EEPROM, flash memory, and A/D converter, and therefore, can be used only by the master and does not have a wait
detection function. Make sure by using software, as well as operating the control registers, that the AC specifications of
the start and stop conditions are observed.
[Data transmission/reception]
• Master transmission, master reception (only master function with a single master)
• ACK output functionNote and ACK detection function
• Data length of 8 bits
(When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is
used for R/W control.)
• Manual generation of start condition and stop condition
[Interrupt function]
• Transfer end interrupt
[Error detection flag]
• Parity error (ACK error)
* [Functions not supported by simplified I2C]
• Slave transmission, slave reception
• Arbitration loss detection function
• Wait detection function
Note An ACK is not output when the last data is being received by writing 0 to the SOEmn (SOEm register) bit and
stopping the output of serial communication data. See 14.7.3 (2) Processing flow for details.
Remarks 1. To use the full-function I2C bus, see CHAPTER 15 SERIAL INTERFACE IICA.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
The channels supporting simplified I2C (IIC10, IIC20) are channel 2 of SAU0 and channel 0 of SAU1.
0
1
2
Used as CSI
Used as UART
Used as Simplified I C
0
CSI00
UART0
−
1
CSI01
2
CSI10
3
−
0
CSI20
1
−
2
−
3
−
Unit
Channel
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IIC10
−
UART2
IIC20
−
UART3 (supporting LIN-bus)
−
−
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Simplified I2C (IIC10, IIC20) performs the following four types of communication operations.
• Address field transmission
(See 14.7.1.)
• Data transmission
(See 14.7.2.)
• Data reception
(See 14.7.3.)
• Stop condition generation
(See 14.7.4.)
14.7.1 Address field transmission
Address field transmission is a transmission operation that first executes in I2C communication to identify the target for
transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in
one frame.
2
Simplified I C
Target channel
IIC10
Channel 2 of SAU0
Pins used
SCL10, SDA10
Interrupt
INTIIC10
Note
IIC20
Channel 0 of SAU1
SCL20, SDA20
Note
INTIIC20
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag
Parity error detection flag (PEFmn)
Transfer data length
8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as R/W
control)
Transfer rate
Max. fCLK/4 [MHz] (SDRmn [15:9] = 1 or more)
fCLK: System clock frequency
2
However, the following condition must be satisfied in each mode of I C.
• Max. 400 kHz (first mode)
• Max. 100 kHz (standard mode)
Data level
Forward output (default: high level)
Parity bit
No parity bit
Stop bit
Appending 1 bit (for ACK reception timing)
Data direction
MSB first
Note To perform communication via simplified I2C, set the data I/O pins (SDA10, SDA20) in the N-ch open-drain output
(VDD tolerance) mode (POM14 = 1, POM11 = 1) by using the port output mode register 1 (POM1) (see 4.3
Registers Controlling Port Function for details). When communicating with an external device with a different
potential, set the N-ch open-drain output (VDD tolerance) mode (POM15 = 1, POM10 = 1) also for the clock
input/output pins (SCL10, SCL20) (see 4.4.4 Connecting to external device with different potential (2.5 V, 3 V)
for details).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
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(1) Register setting
Figure 14-88. Example of Contents of Registers for Address Field Transmission of Simplified I2C (IIC10, IIC20)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15
14
13
12
11
0
0
0
0
1
SOm
10
9
8
7
6
5
4
3
0
0
0
0
1
CKOm2 CKOm1 CKOm0
0/1
×
0/1
2
1
0
SOm2
SOm1
SOm0
0/1
×
0/1
Start condition is generated by manipulating the SOmn bit.
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
2
1
0
SOEm2 SOEm1 SOEm0
×
0/1
0/1
SOEmn = 0 until the start condition is generated, and SOEmn =
1 after generation.
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel is 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
SSm2
SSm1
SSm0
×
0/1
×
0/1
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
0
STSmn
0
SISmn0
0
MDmn2 MDmn1 MDmn0
0
1
0
0
Operation mode of channel n
0: Transfer end interrupt
(e) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
1
0
0
0
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0
0
0
5
4
3
SLCmn1 SLCmn0
0
0
1
2
1
0
DLSmn2 DLSmn1 DLSmn0
0
1
1
1
Setting of stop bit
01B: Appending 1 bit (ACK)
Setting of parity bit
00B: No parity
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDRmn
Baud rate setting
0
Transmit data setting (address + R/W)
SIOr
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
: Setting is fixed in the IIC mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Operation procedure
Figure 14-89. Initial Setting Procedure for Address Field Transmission
Starting initial setting
Setting PER0 register
Setting SPSm register
Release the serial array unit from the
reset status and start clock supply.
Set the prescaler.
Setting SMRmn register
Set an operation mode, etc.
Setting SCRmn register
Set a communication format.
Setting SDRmn register
Set a transfer baud rate.
Setting SOm register
Setting port
Setting SOm register
Manipulate the SOmn and CKOmn bits
and set an initial output level.
Enable data output, clock output, and the N-ch
open-drain output (VDD tolerance) mode of the
target channel by setting a port register, a port
mode register, and a port output mode register.
Clear the SOmn bit to 0 to generate the
start condition.
Secure a wait time so that the specifications of
Wait
Setting SOm register
Changing setting of SOEm register
2
I C on the slave side are satisfied.
Clear the CKOmn bit to 0 to lower the
clock output level.
Set the SOEmn bit to 1 and enable data
output of the target channel.
Writing to SSm register
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set address and R/W to the SIOr register
Starting communication
(bits 7 to 0 of the SDRmn register) and
start communication.
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
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(3) Processing flow
Figure 14-90. Timing Chart of Address Field Transmission
SSmn
SEmn
SOEmn
Address field transmission
SDRmn
SCLr output
CKOmn
bit manipulation
SDAr output
D7
D6
D5
D4
D3
D2
D1
SOmn bit manipulation
R/W
Address
SDAr input
Shift
register mn
D7
D6
D5
D4
D0
D3
D2
D1
D0
ACK
Shift operation
INTIICr
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
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Figure 14-91. Flowchart of Address Field Transmission
Starting IIC communication
SMRmn, SCRmn:
Setting communication
SPSm, SDRmn[15:9]: Setting transfer rate
Writing 0 to SOmn bit
Perform initial setting
when SEmn = 0.
Writing 0 to CKOmn bit
Writing 1 to SOEmn bit
Writing 1 to SSmn bit
Writing address and R/W
data to SIOr (SDRmn[7:0])
Transfer end interrupt
generated?
No
Yes
Parity error (ACK error) flag
PEFmn = 1 ?
Yes
No
ACK reception error
Address field
transmission completed
To data transmission flow
and data reception flow
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14.7.2 Data transmission
Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field.
After all data are transmitted to the slave, a stop condition is generated and the bus is released.
2
Simplified I C
Target channel
IIC10
Channel 2 of SAU0
Pins used
SCL10, SDA10
Interrupt
INTIIC10
Note
IIC20
Channel 0 of SAU1
SCL20, SDA20
Note
INTIIC20
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag
Parity error detection flag (PEFmn)
Transfer data length
8 bits
Transfer rate
Max. fCLK/4 [MHz] (SDRmn [15:9] = 1 or more)
fCLK: System clock frequency
2
However, the following condition must be satisfied in each mode of I C.
• Max. 400 kHz (first mode)
• Max. 100 kHz (standard mode)
Data level
Forward output (default: high level)
Parity bit
No parity bit
Stop bit
Appending 1 bit (for ACK reception timing)
Data direction
MSB first
Note To perform communication via simplified I2C, set the data I/O pins (SDA10, SDA20) in the N-ch open-drain output
(VDD tolerance) mode (POM14 = 1, POM11 = 1) by using the port output mode register 1 (POM1) (see 4.3
Registers Controlling Port Function for details). When communicating with an external device with a different
potential, set the N-ch open-drain output (VDD tolerance) mode (POM15 = 1, POM10 = 1) also for the clock
input/output pins (SCL10, SCL20) (see 4.4.4 Connecting to external device with different potential (2.5 V, 3 V)
for details).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
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(1) Register setting
Figure 14-92. Example of Contents of Registers for Data Transmission of Simplified I2C (IIC10, IIC20)
(a) Serial output register m (SOm) … Do not manipulate this register during data
transmission/reception.
15
14
13
12
11
0
0
0
0
1
SOm
10
9
8
7
6
5
4
3
2
1
SOm2
SOm1
SOm0
0
0
0
0
1
0/1Note
×
0/1Note
CKOm2 CKOm1 CKOm0
0/1Note
×
0/1Note
0
(b) Serial output enable register m (SOEm) … Do not manipulate this register during data
transmission/reception.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
2
1
0
SOEm2 SOEm1 SOEm0
0/1
×
0/1
(c) Serial channel start register m (SSm) … Do not manipulate this register during data
transmission/reception.
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
0
SSm
3
2
1
0
SSm3
SSm2
SSm1
SSm0
×
0/1
×
0/1
1
0
(d) Serial mode register mn (SMRmn) … Do not manipulate this register during data
transmission/reception.
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
0
8
7
STSmn
0
6
5
4
3
1
0
0
SISmn0
0
0
2
MDmn2 MDmn1 MDmn0
1
0
0
(e) Serial communication operation setting register mn (SCRmn) … Do not manipulate the bits of this
register, except the TXEmn and
RXEmn bits, during data
transmission/reception.
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
1
0
0
0
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0
0
0
5
4
3
SLCmn1 SLCmn0
2
1
0
DLSmn2 DLSmn1 DLSmn0
0
0
1
0
1
1
1
6
5
4
3
2
1
0
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15
14
13
12
11
10
9
8
7
SDRmn
Baud rate setting
0
Transmit data setting
SIOr
Note The value varies depending on the communication data during communication operation.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
: Setting is fixed in the IIC mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Processing flow
Figure 14-93. Timing Chart of Data Transmission
SSmn
SEmn
SOEmn
“L”
“H”
“H”
Transmit data 1
SDRmn
SCLr output
SDAr output
D7
D6
D5
D4
D3
D2
D1
D0
SDAr input
D7
D6
D5
D4
D3
D2
D1
D0
Shift
register mn
ACK
Shift operation
INTIICr
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
Figure 14-94. Flowchart of Data Transmission
Address field
transmission completed
Starting data transmission
Writing data to SIOr
(SDRmn[7:0])
Transfer end interrupt
generated?
No
Yes
Parity error (ACK error) flag
PEFmn = 1 ?
Yes
No
ACK reception error
No
Data transfer completed?
Yes
Data transmission
completed
Stop condition generation
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14.7.3 Data reception
Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field.
After all data are received to the slave, a stop condition is generated and the bus is released.
2
Simplified I C
Target channel
IIC10
Channel 2 of SAU0
Pins used
SCL10, SDA10
Interrupt
INTIIC10
Note
IIC20
Channel 0 of SAU1
SCL20, SDA20
Note
INTIIC20
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag
None
Transfer data length
8 bits
Transfer rate
Max. fCLK/4 [MHz] (SDRmn [15:9] = 1 or more)
fCLK: System clock frequency
2
However, the following condition must be satisfied in each mode of I C.
• Max. 400 kHz (first mode)
• Max. 100 kHz (standard mode)
Data level
Forward output (default: high level)
Parity bit
No parity bit
Stop bit
Appending 1 bit (ACK transmission)
Data direction
MSB first
Note To perform communication via simplified I2C, set the data I/O pins (SDA10, SDA20) in the N-ch open-drain output
(VDD tolerance) mode (POM14 = 1, POM11 = 1) by using the port output mode register 1 (POM1) (see 4.3
Registers Controlling Port Function for details). When communicating with an external device with a different
potential, set the N-ch open-drain output (VDD tolerance) mode (POM15 = 1, POM10 = 1) also for the clock
input/output pins (SCL10, SCL20) (see 4.4.4 Connecting to external device with different potential (2.5 V, 3 V)
for details).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
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(1) Register setting
Figure 14-95. Example of Contents of Registers for Data Reception of Simplified I2C (IIC10, IIC20)
(a) Serial output register m (SOm) … Do not manipulate this register during data
transmission/reception.
15
14
13
12
11
0
0
0
0
1
SOm
10
9
8
7
6
5
4
3
2
1
SOm2
SOm1
SOm0
0
0
0
0
1
0/1Note
×
0/1Note
CKOm2 CKOm1 CKOm0
0/1Note
×
0/1Note
0
(b) Serial output enable register m (SOEm) … Do not manipulate this register during data
transmission/reception.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
2
1
0
SOEm2 SOEm1 SOEm0
0/1
×
0/1
(c) Serial channel start register m (SSm) … Do not manipulate this register during data
transmission/reception.
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
0
SSm
3
2
1
0
SSm3
SSm2
SSm1
SSm0
×
0/1
×
0/1
1
0
(d) Serial mode register mn (SMRmn) … Do not manipulate this register during data
transmission/reception.
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
0
8
7
STSmn
0
6
5
4
3
1
0
0
SISmn0
0
0
2
MDmn2 MDmn1 MDmn0
1
0
0
(e) Serial communication operation setting register mn (SCRmn) … Do not manipulate the bits of this
register, except the TXEmn and
RXEmn bits, during data
transmission/reception.
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
0
1
0
0
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0
0
0
5
4
3
SLCmn1 SLCmn0
2
1
0
DLSmn2 DLSmn1 DLSmn0
0
0
1
0
1
1
1
6
5
4
3
2
1
0
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15
14
13
12
11
10
9
8
7
SDRmn
Baud rate setting
0
Dummy transmit data setting (FFH)
SIOr
Note The value varies depending on the communication data during communication operation.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
: Setting is fixed in the IIC mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Processing flow
Figure 14-96. Timing Chart of Data Reception
(a) When starting data reception
SSmn
STmn
SEmn
SOEmn
“H”
TXEmn,
TXEmn = 1 / RXEmn = 0
RXEmn
TXEmn = 0 / RXEmn = 1
SDRmn
Dummy data (FFH)
Receive data
SCLr output
SDAr output
ACK
D7
SDAr input
D6
D5
D4
Shift
register mn
D3
D2
D1
D0
Shift operation
INTIICr
TSFmn
(b) When receiving last data
STmn
SEmn
SOEmn
TXEmn,
RXEmn
Output is enabled by serial
communication operation
Output is stopped by serial communication operation
TXEmn = 0 / RXEmn = 1
SDRmn
Dummy data (FFH)
Dummy data (FFH) Receive data
Receive data
SCLr output
SDAr output
SDAr input
ACK
D2
Shift
register mn
D1
D0
Shift operation
NACK
D7
D6
D5
D4
D3
D2
D1
D0
Shift operation
INTIICr
TSFmn
Reception of last byte
SOmn bit
SOmn bit
manipulation manipulation
IIC operation stop CKOmn bit
manipulation
Stop condition
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
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Figure 14-97. Flowchart of Data Reception
Address field transmission completed
Writing 1 to STmn bit
Writing 0 to TXEmn bit, and 1 to RXEmn bit
Writing 1 to SSmn bit
Starting data reception
Last byte received?
No
Yes
Writing 0 to SOEmn bit
(Stopping output by serial
communication operation)
Writing dummy data (FFH)
to SIOr (SDRmn[7:0])
Transfer end interrupt
generated?
No
Yes
Reading SIOr (SDRmn[7:0])
No
Data transfer completed?
Yes
Data reception
completed
Stop condition generation
Caution
ACK is also output when the last data is received. Communication is then completed by setting
“1” to the STmn bit to stop operation and generating a stop condition.
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14.7.4 Stop condition generation
After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released.
(1) Processing flow
Figure 14-98. Timing Chart of Stop Condition Generation
Note During the receive operation, the SOEmn bit is set to 0 before receiving the last data.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
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Figure 14-99. Flowchart of Stop Condition Generation
Completion of data
transmission/data reception
Starting generation of stop condition.
Writing 1 to STmn bit to clear
SEmn to 0.
Writing 0 to SOEmn bit
Writing 0 to SOmn bit
Writing 1 to CKOmn bit
Secure a wait time so that the specifications of
Wait
2
I C on the slave side are satisfied.
Writing 1 to SOmn bit
End of IIC communication
14.7.5 Calculating transfer rate
The transfer rate for simplified I2C (IIC10, IIC20) communication can be calculated by the following expressions.
(Transfer rate) = {Operation clock (MCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2
Caution
Setting SDRmn [15:9] = 0000000B is prohibited. Set SDRmn[15:9] to 0000001B or greater.
Remarks 1. The value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000000B to
1111111B) and therefore is 0 to 127.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
The operation clock (MCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode
register mn (SMRmn).
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Table 14-4. Selection of operation clock
SMRmn
SPSm Register
Operation Clock (MCK)
Note1
Register
CKSmn
PRS PRS PRS PRS PRS PRS PRS PRS
fCLK = 20 MHz
m13
m12
m11
m10
m03
m02
m01
m00
X
X
X
X
0
0
0
0
fCLK
X
X
X
X
0
0
0
1
fCLK/2
X
X
X
X
0
0
1
0
fCLK/2
2
5 MHz
fCLK/2
3
2.5 MHz
1.25 MHz
0
X
X
X
X
0
0
1
1
20 MHz
10 MHz
X
X
X
X
0
1
0
0
fCLK/2
4
X
X
X
X
0
1
0
1
fCLK/2
5
625 kHz
fCLK/2
6
313 kHz
156 kHz
X
X
X
X
0
1
1
0
X
X
X
X
0
1
1
1
fCLK/2
7
X
X
X
X
1
0
0
0
fCLK/2
8
78.1 kHz
fCLK/2
9
39.1 kHz
19.5 kHz
9.77 kHz
X
X
X
X
1
0
0
1
X
X
X
X
1
0
1
0
fCLK/2
10
X
X
X
X
1
0
1
1
fCLK/2
11
X
X
X
X
1
1
1
1
INTTM02 if m = 0,
INTTM03 if m = 1
1
Note2
0
0
0
0
X
X
X
X
fCLK
0
0
0
1
X
X
X
X
fCLK/2
0
0
1
0
X
X
X
X
fCLK/2
2
5 MHz
fCLK/2
3
2.5 MHz
1.25 MHz
0
0
1
1
X
X
X
X
20 MHz
10 MHz
0
1
0
0
X
X
X
X
fCLK/2
4
0
1
0
1
X
X
X
X
fCLK/2
5
625 kHz
fCLK/2
6
313 kHz
156 kHz
0
1
1
0
X
X
X
X
0
1
1
1
X
X
X
X
fCLK/2
7
1
0
0
0
X
X
X
X
fCLK/2
8
78.1 kHz
fCLK/2
9
39.1 kHz
19.5 kHz
9.77 kHz
1
0
0
1
X
X
X
X
1
0
1
0
X
X
X
X
fCLK/2
10
1
0
1
1
X
X
X
X
fCLK/2
11
1
1
1
1
X
X
X
X
INTTM02 if m = 0,
INTTM03 if m = 1
Other than above
Note2
Setting prohibited
Notes 1. When changing the clock selected for fCLK (by changing the system clock control register (CKC) value),
do so after having stopped (STm = 000FH) the operation of the serial array unit (SAUm). When
selecting INTTM02 and INTTM03 for the operation clock, also stop the timer array unit (TAU0) (TT0 =
00FFH).
2. SAUm can be operated at a fixed division ratio of the subsystem clock, regardless of the fCLK frequency
(main system clock, subsystem clock), by operating the interval timer for which fSUB/4 has been
selected as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of the TIS0 register to 1) and
selecting INTTM02 and INTTM03 by using the SPSm register in channels 2 and 3 of TAU0. When
changing fCLK, however, SAUm and TAU0 must be stopped as described in Note 1 above.
Remarks 1. X: Don’t care
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
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Here is an example of setting an IIC transfer rate where MCK = fCLK = 20 MHz.
IIC Transfer Mode
(Desired Transfer Rate)
fCLK = 20 MHz
Operation Clock (MCK)
SDRmn[15:9]
Calculated
Error from Desired Transfer
Transfer Rate
Rate
100 kHz
fCLK
99
100 kHz
0.0%
400 kHz
fCLK
24
400 kHz
0.0%
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14.8 Processing Procedure in Case of Error
The processing procedure to be followed if an error of each type occurs is described in Figures 14-100 to 14-102.
Figure 14-100. Processing Procedure in Case of Parity Error or Overrun Error
Software Manipulation
Reads SDRmn register.
Hardware Status
Remark
BFF = 0, and channel n is enabled to
This is to prevent an overrun error if
receive data.
the next reception is completed
during error processing.
Reads SSRmn register.
Error type is identified and the read
value is used to clear error flag.
Writes SIRmn register.
Error flag is cleared.
Error can be cleared only during
reading, by writing the value read
from the SSRmn register to the
SIRmn register without modification.
Figure 14-101. Processing Procedure in Case of Framing Error
Software Manipulation
Reads SDRmn register.
Hardware Status
Remark
BFF = 0, and channel n is enabled to
This is to prevent an overrun error if
receive data.
the next reception is completed
during error processing.
Reads SSRmn register.
Error type is identified and the read
value is used to clear error flag.
Writes SIRmn register.
Error flag is cleared.
Error can be cleared only during
reading, by writing the value read
from the SSRmn register to the
SIRmn register without modification.
Sets STmn bit to 1.
SEmn = 0, and channel n stops
operation.
Synchronization with other party of
Synchronization with the other party
communication
of communication is re-established
and communication is resumed
because it is considered that a
framing error has occurred because
the start bit has been shifted.
Sets SSmn bit to 1.
SEmn = 1, and channel n is enabled to
operate.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 14-102. Processing Procedure in Case of Parity Error (ACK error) in Simplified I2C Mode
Software Manipulation
Reads SDRmn register.
Hardware Status
Remark
BFF = 0, and channel n is enabled to
This is to prevent an overrun error if
receive data.
the next reception is completed
during error processing.
Reads SSRmn register.
Error type is identified and the read
value is used to clear error flag.
Writes SIRmn register.
Error flag is cleared.
Error can be cleared only during
reading, by writing the value read
from the SSRmn register to the
SIRmn register without modification.
Sets STmn bit to 1.
SEmn = 0, and channel n stops
Slave is not ready for reception
operation.
because ACK is not returned.
Therefore, a stop condition is
created, the bus is released, and
communication is started again from
the start condition. Or, a restart
condition is generated and
Creates stop condition.
transmission can be redone from
address transmission.
Creates start condition.
Sets SSmn bit to 1.
Remark
SEmn = 1, and channel n is enabled to
operate.
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 02, 10
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14.9 Relationship Between Register Settings and Pins
Tables 14-5 to 14-12 show the relationship between register settings and pins for each channel of serial array units 0
and 1.
Table 14-5. Relationship between register settings and pins (Channel 0 of unit 0: CSI00, UART0 transmission)
SE MD MD SOE SO CKO TXE RXE PM P80 PM P81 PM P82
00 002 001
00
00
00
00
00
80
81
Note1
0
Note2
Operation mode
82
SCK00/
SI00/RxD0/
SO00/
INTP11
/P80
INTP9/
Note2
P81
TxD0/P82
Operation stop
INTP11/
INTP9/P81
P82
mode
P80
Note2
0
0
0
0
1
1
0
0
×
×
×
Note3
Note3
Note3
×
×
×
Note3 Note3 Note3
1
Pin Function
RxD0/
INTP9/P81
1
0
0
0
1
1
0
1
1
×
1
×
×
×
Note3 Note3
1
0/1
1
1
0
1
×
Note4
1
0/1
1
1
1
1
×
×
×
Note3
Note3
1
×
0
0
1
1
Note4
Slave CSI00
SCK00
reception
(input)
SI00
P82
INTP9/P81
SO00
SI00
SO00
SI00
P82
INTP9/P81
SO00
SI00
SO00
INTP11/
RxD0/
TxD0
P80
INTP9/P81
Slave CSI00
SCK00
transmission
(input)
Slave CSI00
SCK00
transmission/
(input)
reception
0
1
0/1
0
1
0
1
1
×
1
1
0/1
0/1
Note4
Note4
0/1
0/1
Note4
Note4
0/1
1
×
×
Note3 Note3
Note4
1
0
0
1
×
×
0
1
Note3 Note3
1
1
0
1
1
×
0
1
Master CSI00
SCK00
reception
(output)
Master CSI00
SCK00
transmission
(output)
Master CSI00
SCK00
transmission/
(output)
reception
0
1
1
Note4
1
0
×
×
×
×
0
1
Note3 Note3 Note3 Note3
UART0
Note5
transmission
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
2. When channel 1 of unit 0 is set to UART0 reception, this pin becomes an RxD0 function pin (refer to Table 14-6).
In this case, operation stop mode or UART0 transmission must be selected for channel 0 of unit 0.
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 14.3 (12) Serial output register
m (SOm).
5. When using UART0 transmission and reception in a pair, set channel 1 of unit 0 to UART0 reception (refer to
Table 14-6).
Remarks 1. X: Don’t care
2. For 78K0R/LF3, the channel 0 of unit 0 is not mounted.
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Table 14-6. Relationship between register settings and pins (Channel 1 of unit 0: CSI01, UART0 reception)
SE MD MD SOE SO01 CKO TXE RXE PM P75
01 012 011 01
01
01
01
75
0
0
0
1
1
0
0
×
×
Note3 Note3
0
P76 PM P77 PM P81 Operation
77
76
Note1
0
PM
×
Note3
81
Note2
mode
Note2
×
×
×
×
×
Note3 Note3 Note3 Note3 Note3
1
Pin Function
SCK01/
SI01/
KR5/
P75
KR6/
P76
SO01/ RxD0/SI00/
KR7/
P77
Operation
KR5/
KR6/P76 KR7/
stop
P75
P77
INTP9/
Note2
P81
SI00/
INTP9/P80
mode
1
0
0
0
1
1
0
1
1
×
1
×
×
×
×
×
Note3 Note3 Note3 Note3
Slave
SCK01
CSI01
(input)
SI01
KR7/
SI00/
P77
INTP9/P80
reception
1
0/1
1
1
0
1
×
Note4
×
×
Note3
Note3
0
1
×
×
Note3 Note3
Slave
SCK01 KR6/P76 SO01
CSI01
(input)
SI00/
INTP9/P80
transmission
1
0/1
1
1
1
1
×
1
×
0
1
Note4
×
×
Note3 Note3
Slave
SCK01
CSI01
(input)
SI01
SO01
SI00/
INTP9/P80
transmission
/reception
0
1
0/1
0
1
0
1
1
×
Note4
×
×
×
×
Note3 Note3 Note3 Note3
Master
SCK01
CSI01
(output)
SI01
KR7/
SI00/
P77
INTP9/P80
reception
1
0/1
0/1
Note4
Note4
0/1
0/1
Note4
Note4
1
0
0
1
×
×
Note3
Note3
1
×
0
1
×
×
Note3 Note3
Master
SCK01 KR6/P76 SO01
CSI01
(output)
SI00/
INTP9/P80
transmission
1
1
1
0
1
0
1
×
×
Note3 Note3
Master
SCK01
CSI01
(output)
SI01
SO01
SI00/
INTP9/P80
transmission
/reception
0
1
0
1
1
0
1
×
×
Note3 Note3
×
Note3
×
×
×
Note3 Note3 Note3
1
×
UART0
KR5/
KR6/P76 KR7/
reception
P75
P77
RxD0
Note5, 6
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
2. When channel 1 of unit 0 is set to UART0 reception, this pin becomes an RxD0 function pin. In this case, set
channel 0 of unit 0 to operation stop mode or UART0 transmission (refer to Table 14-5).
When channel 0 of unit 0 is set to CSI00, this pin cannot be used as an RxD0 function pin. In this case, set
channel 1 of unit 0 to operation stop mode or CSI01.
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 14.3 (12) Serial output register
m (SOm).
5. When using UART0 transmission and reception in a pair, set channel 0 of unit 0 to UART0 transmission (refer to
Table 14-5).
6. The SMR00 register of channel 0 of unit 0 must also be set during UART0 reception. For details, refer to 14.5.2
(1) Register setting.
Remarks 1. X: Don’t care
2. For 78K0R/LF3, the channel 1 of unit 0 is not mounted.
3. For 78K0R/LG3, CSI01 is not mounted.
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Table 14-7. Relationship between register settings and pins
(Channel 2 of unit 0: CSI10, UART1 transmission, IIC10)
SE MD MD SOE SO CKO TXE RXE PM P15 PM14 P14 PM13 P13
Note2
Note2
02 022 021 02 02 02 02 02 15
Operation mode
SCK10/ SI10/SDA10/ SO10/
TxD1/
SCL10/
RxD1/INTP4
Note2
TO04/P13
INTP7/P15
/P14
Note1
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
×
×
×
×
×
×
Note3
Note3
Note3
Note3
Note3
Note3
0
1
1
0/1
1
0
1
1
0
1
1
×
×
Note4
1
1
×
×
×
Note3
Note3
1
1
1
1
×
1
×
0/1
0
1
0
1
1
×
0/1
×
×
Note3
Note3
0
1
Note4
1
1
1
0/1
0/1
Note4
Note4
0/1
0/1
Note4
Note4
0/1
1
1
0
1
1
1
0
Note4
0
1
1
0
0
1
1
1
0
INTP7/P15
INTP4/P14
TO04/P13
RxD1/INTP4/
P14
0
0
Slave CSI10
reception
SCK10
(input)
SI10
TO04/P13
1
Slave CSI10
transmission
SCK10
(input)
INTP4/P14
SO10
1
Slave CSI10
transmission /reception
SCK10
(input)
SI10
SO10
Master CSI10
reception
SCK10
(output)
SI10
TO04/P13
Note4
1
Operation stop
mode
INTP4/P14
1
0
Pin Function
0
0/1
0/1
Note6
Note6
0/1
0/1
Note4
Note4
0/1
0/1
Note4
Note4
0/1
0/1
Note4
Note4
0/1
0/1
Note7
Note7
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
SCK10
(output)
SI10
SO10
Master CSI10
transmission /reception
0
1
UART1
Note5
transmission
×
0
1
0
1
1
SO10
1
Note3
0
INTP4/P14
0
×
1
SCK10
(output)
×
Note3
0
Master CSI10
transmission
1
×
1
1
×
Note3
Note3
0
0
×
×
1
×
Note3
Note3
Note3
0
×
Note3
0
0
0
0
1
1
1
1
×
×
Note3
Note3
×
×
Note3
Note3
×
×
Note3
Note3
×
×
Note3
Note3
×
×
Note3
Note3
INTP7/P15 RxD1/INTP4/
P14
TxD1
SCL10
SDA10
TO04/P13
IIC10 address field
transmission
SCL10
SDA10
TO04/P13
IIC10 data
transmission
SCL10
SDA10
TO04/P13
IIC10 data
reception
SCL10
SDA10
TO04/P13
IIC10
stop condition
SCL10
SDA10
TO04/P13
IIC10
start condition
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
2. When channel 3 of unit 0 is set to UART1 reception, this pin becomes an RxD1 function pin (refer to Table 14-8).
In this case, operation stop mode or UART1 transmission must be selected for channel 2 of unit 0.
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 14.3 (12) Serial output register
m (SOm).
5. When using UART1 transmission and reception in a pair, set channel 3 of unit 0 to UART1 reception (refer to
Table 14-8).
6. Set the CKO02 bit to 1 before a start condition is generated. Clear the SO02 bit from 1 to 0 when the start
condition is generated.
7. Set the CKO02 bit to 1 before a stop condition is generated. Clear the SO02 bit from 0 to 1 when the stop
condition is generated.
Remark X: Don’t care
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Table 14-8. Relationship between register settings and pins (Channel 3 of unit 0: UART1 reception)
SE03
Note1
MD032
MD031
TXE03
RXE03
PM14
Note2
P14
Note2
Operation
mode
0
0
1
0
0
×
Note3
×
Note3
Pin Function
RxD1/SI10/SDA10/INTP4/
Note2
P14
Operation
SI10/SDA10/INTP4/P14
stop mode
1
0
1
0
1
1
×
UART1
Note2
RxD1
reception
Note4, 5
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
2. When channel 3 of unit 0 is set to UART1 reception, this pin becomes an RxD1 function pin. In this case, set
channel 2 of unit 0 to operation stop mode or UART1 transmission (refer to Table 14-7).
When channel 2 of unit 0 is set to CSI10 or IIC10, this pin cannot be used as an RxD1 function pin. In this case,
set channel 3 of unit 0 to operation stop mode.
3. This pin can be set as a port function pin.
4. When using UART1 transmission and reception in a pair, set channel 2 of unit 0 to UART1 transmission (refer to
Table 14-7).
5. The SMR02 register of channel 2 of unit 0 must also be set during UART1 reception. For details, refer to 14.5.2
(1) Register setting.
Remark X: Don’t care
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Table 14-9. Relationship between register settings and pins
(Channel 0 of unit 1: CSI20, UART2 transmission, IIC20)
SE MD MD SOE SO CKO TXE RXE PM P10
10 102 101 10 10 10 10 10 10
Note1
0
1
PM P11 PM
Note2
11
12
P12
0
0
0
1
1
0
0
0
0
1
1
0
0
×
×
×
×
×
×
Note3
Note3
Note3
Note3
Note3
Note3
0
1
1
1
0/1
1
0
1
1
0
1
1
×
×
1
×
×
×
Note3
Note3
1
1
1
1
×
1
×
0/1
0
1
0
1
1
×
0/1
×
×
Note3
Note3
0
1
Note4
1
1
1
0/1
0/1
Note4
Note4
0/1
0/1
Note4
Note4
0/1
1
1
0
1
1
1
0
Note4
1
1
0
0
1
1
1
0
P10
INTP6/P11
TO02/P12
RxD2/INTP6/
P11
0
0
Slave CSI20
reception
SCK20
(input)
SI20
TO02/P12
1
Slave CSI20
transmission
SCK20
(input)
INTP6/P11
SO20
1
Slave CSI20
transmission/reception
SCK20
(input)
SI20
SO20
Master CSI20
reception
SCK20
(output)
SI20
TO02/P12
Note4
1
Operation stop
mode
INTP6/P11
Note4
0
Pin Function
SO20/
SCK20/
SI20/SDA20/
TxD2/
SCL20/P10 RxD2/INTP6/
Note2
TO02/P12
P11
Note2
1
0
Operation mode
0
0/1
0/1
Note6
Note6
0/1
0/1
Note4
Note4
0/1
0/1
Note4
Note4
0/1
0/1
Note4
Note4
0/1
0/1
Note7
Note7
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
Master CSI20
transmission/reception
SCK20
(output)
SI20
SO20
0
1
UART2
Note5
transmission
P10
RxD2/INTP6/
P11
TxD2
IIC20
SCL20
SDA20
TO02/P12
IIC20 address field
transmission
SCL20
SDA20
TO02/P12
IIC20 data
transmission
SCL20
SDA20
TO02/P12
IIC20 data
reception
SCL20
SDA20
TO02/P12
IIC20
stop condition
SCL20
SDA20
TO02/P12
×
0
1
0
1
1
SO20
1
Note3
0
INTP6/P11
0
×
1
SCK20
(output)
×
Note3
0
Master CSI20
transmission
1
×
1
1
×
Note3
Note3
0
0
×
×
1
×
Note3
Note3
Note3
0
×
Note3
0
0
0
0
1
1
1
1
×
×
Note3
Note3
×
×
Note3
Note3
×
×
Note3
Note3
×
×
Note3
Note3
×
×
Note3
Note3
start condition
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
2. When channel 1 of unit 1 is set to UART2 reception, this pin becomes an RxD2 function pin (refer to Table 1410). In this case, operation stop mode or UART2 transmission must be selected for channel 0 of unit 1.
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 14.3 (12) Serial output register
m (SOm).
5. When using UART2 transmission and reception in a pair, set channel 1 of unit 1 to UART2 reception (refer to
Table 14-10).
6. Set the CKO10 bit to 1 before a start condition is generated. Clear the SO10 bit from 1 to 0 when the start
condition is generated.
7. Set the CKO10 bit to 1 before a stop condition is generated. Clear the SO10 bit from 0 to 1 when the stop
condition is generated.
Remark X: Don’t care
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Table 14-10. Relationship between register settings and pins (Channel 1 of unit 1: UART2 reception)
SE11
Note1
MD112
MD111
TXE11
RXE11
PM11
Note2
P11
Note2
Operation
mode
Pin Function
SI20/SDA20/RxD2/
INTP6/P11
0
0
1
0
0
×
Note3
×
Note3
Operation
Note2
SI20/SDA20/INTP6/P11
stop mode
1
0
1
0
1
1
×
UART2
RxD2
reception
Note4, 5
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
2. When channel 1 of unit 1 is set to UART2 reception, this pin becomes an RxD2 function pin. In this case, set
channel 0 of unit 1 to operation stop mode or UART2 transmission (refer to Table 14-9).
When channel 0 of unit 1 is set to CSI20 or IIC20, this pin cannot be used as an RxD2 function pin. In this case,
set channel 1 of unit 1 to operation stop mode.
3. This pin can be set as a port function pin.
4. When using UART2 transmission and reception in a pair, set channel 0 of unit 1 to UART2 transmission (refer to
Table 14-9).
5. The SMR10 register of channel 0 of unit 1 must also be set during UART2 reception. For details, refer to 14.5.2
(1) Register setting.
Remark X: Don’t care
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Table 14-11. Relationship between register settings and pins (Channel 2 of unit 1: UART3 transmission)
SE12
MD122
MD121
SOE12
SO12
TXE12
RXE12
PM51
P51
Note1
Operation
mode
0
0
1
1
0
0
1
1
1
0/1
Note3
0
×
×
Note2
Note2
0
1
0
1
0
Pin Function
TxD3/SEG52/P51
Operation
SEG52/P51
stop mode
TxD3
UART3
transmission
Note4
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
2. This pin can be set as a port function pin.
3. This is 0 or 1, depending on the communication operation. For details, refer to 14.3 (12) Serial output register
m (SOm).
4. When using UART3 transmission and reception in a pair, set channel 3 of unit 1 to UART3 reception (refer to
Table 14-12).
Remark X: Don’t care
Table 14-12. Relationship between register settings and pins (Channel 3 of unit 1: UART3 reception)
SE13
Note1
MD132
MD131
TXE13
RXE13
PM50
P50
Operation
mode
0
0
1
0
0
×
Note2
×
Note2
Pin Function
RxD3/SEG53/P50
Operation
SEG53/P50
stop
mode
1
0
1
0
1
1
×
UART3
RxD3
reception
Note3, 4
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
2. This pin can be set as a port function pin.
3. When using UART3 transmission and reception in a pair, set channel 2 of unit 1 to UART3 transmission (refer to
Table 14-11).
4. The SMR12 register of channel 2 of unit 1 must also be set during UART3 reception. For details, refer to 14.5.2
(1) Register setting.
Remark X: Don’t care
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CHAPTER 15 SERIAL INTERFACE IICA
CHAPTER 15 SERIAL INTERFACE IICA
Item
Serial interface
78K0R/LF3
78K0R/LG3
78K0R/LH3
80 pins
100 pins
128 pins
−
1 ch
IICA
15.1 Functions of Serial Interface IICA
Serial interface IICA has the following three modes.
(1) Operation stop mode
This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
(2) I2C bus mode (multimaster supported)
This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a serial
data bus (SDA0) line.
This mode complies with the I2C bus format and the master device can generated “start condition”, “address”,
“transfer direction specification”, “data”, and “stop condition” data to the slave device, via the serial data bus. The
slave device automatically detects these received status and data by hardware. This function can simplify the part
of application program that controls the I2C bus.
Since the SCL0 and SDA0 pins are used for open drain outputs, IICA requires pull-up resistors for the serial clock
line and the serial data bus line.
(3) Wakeup mode
The STOP mode can be released by generating an interrupt request signal (INTIICA) when an extension code from
the master device or a local address has been received while in STOP mode. This can be set by using the WUP bit
of IICA control register 1 (IICCTL1).
Figure 15-1 shows a block diagram of serial interface IICA.
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Figure 15-1. Block Diagram of Serial Interface IICA
Internal bus
IICA status register (IICS)
WUP
MSTS ALD EXC COI TRC ACKD STD SPD
IICA control register 0
(IICCTL0)
Sub-circuit
for standby
IICE LREL WREL SPIE WTIM ACKE STT
SPT
Filter
Slave address
register (SVA)
SDA0/
P61
DFC
IICA shift
register (IICA)
Output
latch
(P61)
PM61
D Q
Stop
condition
generator
SO latch
IICWL
Data hold
time correction
circuit
TRC
N-ch opendrain output
Set
Match
signal
Noise
eliminator
Start
condition
generator
Clear
ACK
generator
Output control
Wakeup
controller
ACK detector
Start condition
detector
Filter
Stop condition
detector
SCL0/
P60
Noise
eliminator
DFC
Interrupt request
signal generator
Serial clock
counter
Serial clock
controller
INTIICA
IICS.MSTS, EXC, COI
Serial clock
wait controller
N-ch opendrain output
IICA shift register (IICA)
Bus status
detector
IICCTL0.STT, SPT
PM60
Output fCLK
latch
(P60)
IICA low-level width
setting register (IICWL)
Counter
IICS.MSTS, EXC, COI
Match signal
IICA high-level width
setting register (IICWH)
WUP
CLD
DAD
SMC
DFC
IICA control register 1
(IICCTL1)
STCF
IICBSY STCEN IICRSV
IICA flag register
(IICF)
Internal bus
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Figure 15-2 shows a serial bus configuration example.
Figure 15-2. Serial Bus Configuration Example Using I2C Bus
+ VDD + VDD
Master CPU1
SDA0
Slave CPU1
Address 0
SCL0
Serial data bus
Serial clock
SDA0
Slave CPU2
SCL0
SDA0
SCL0
SDA0
SCL0
SDA0
SCL0
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Address 1
Slave CPU3
Address 2
Slave IC
Address 3
Slave IC
Address N
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CHAPTER 15 SERIAL INTERFACE IICA
15.2 Configuration of Serial Interface IICA
Serial interface IICA includes the following hardware.
Table 15-1. Configuration of Serial Interface IICA
Item
Configuration
Registers
IICA shift register (IICA)
Slave address register (SVA)
Control registers
Peripheral enable register 0 (PER0)
IICA control register 0 (IICCTL0)
IICA status register (IICS)
IICA flag register (IICF)
IICA control register 1 (IICCTL1)
IICA low-level width setting register (IICWL)
IICA high-level width setting register (IICWH)
Port mode register 6 (PM6)
Port register 6 (P6)
(1) IICA shift register (IICA)
IICA is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock.
IICA can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing and reading operations to IICA.
Cancel the wait state and start data transfer by writing data to IICA during the wait period.
IICA can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears IICA to 00H.
Figure 15-3. Format of IICA Shift Register (IICA)
Address: FFF50H
Symbol
After reset: 00H
7
6
5
R/W
4
3
2
1
0
IICA
Cautions 1. Do not write data to IICA during data transfer.
2. Write or read IICA only during the wait period. Accessing IICA in a communication state other
than during the wait period is prohibited. When the device serves as the master, however,
IICA can be written only once after the communication trigger bit (STT) is set to 1.
3. When communication is reserved, write data to IICA after the interrupt triggered by a stop
condition is detected.
(2) Slave address register (SVA)
This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode.
SVA can be set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STD = 1 (while the start condition is detected).
Reset signal generation clears SVA to 00H.
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Figure 15-4. Format of Slave Address Register (SVA)
Address: F0234H
Symbol
7
SVA
A6
After reset: 00H
6
A5
R/W
5
A4
4
A3
3
A2
2
A1
1
A0
0
Note
0
Note Bit 0 is fixed to 0.
(3) SO latch
The SO latch is used to retain the SDA0 pin’s output level.
(4) Wakeup controller
This circuit generates an interrupt request (INTIICA) when the address received by this register matches the
address value set to the slave address register (SVA) or when an extension code is received.
(5) Serial clock counter
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify
that 8-bit data was transmitted or received.
(6) Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIICA).
An I2C interrupt request is generated by the following two triggers.
• Falling edge of eighth or ninth clock of the serial clock (set by WTIM bit)
• Interrupt request generated when a stop condition is detected (set by SPIE bit)
Remark
WTIM bit:
Bit 3 of IICA control register 0 (IICCTL0)
SPIE bit:
Bit 4 of IICA control register 0 (IICCTL0)
(7) Serial clock controller
In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock.
(8) Serial clock wait controller
This circuit controls the wait timing.
(9) ACK generator, stop condition detector, start condition detector, and ACK detector
These circuits generate and detect each status.
(10) Data hold time correction circuit
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
(11) Start condition generator
This circuit generates a start condition when the STT bit is set to 1.
However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released (IICBSY
bit = 1), start condition requests are ignored and the STCF bit is set to 1.
(12) Stop condition generator
This circuit generates a stop condition when the SPT bit is set to 1.
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(13) Bus status detector
This circuit detects whether or not the bus is released by detecting start conditions and stop conditions.
However, as the bus status cannot be detected immediately following operation, the initial status is set by the
STCEN bit.
Remark
STT bit:
Bit 1 of IICA control register 0 (IICCTL0)
SPT bit:
Bit 0 of IICA control register 0 (IICCTL0)
IICRSV bit: Bit 0 of IICA flag register (IICF)
IICBSY bit:
Bit 6 of IICA flag register (IICF)
STCF bit:
Bit 7 of IICA flag register (IICF)
STCEN bit: Bit 1 of IICA flag register (IICF)
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15.3 Registers Controlling Serial Interface IICA
Serial interface IICA is controlled by the following eight registers.
• Peripheral enable register 0 (PER0)
• IICA control register 0 (IICCTL0)
• IICA flag register (IICF)
• IICA status register (IICS)
• IICA control register 1 (IICCTL1)
• IICA low-level width setting register (IICWL)
• IICA high-level width setting register (IICWH)
• Port mode register 6 (PM6)
• Port register 6 (P6)
(1) Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When serial interface IICA is used, be sure to set bit 4 (IICAEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 15-5. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
After reset: 00H
R/W
Symbol
PER0
RTCEN
DACEN
ADCEN
IICAEN
0
IICAEN
Note
SAU1EN
SAU0EN
TAU1EN
TAU0EN
Control of serial interface IICA input clock
Stops supply of input clock.
• SFR used by serial interface IICA cannot be written.
• Serial interface IICA is in the reset status.
1
Supplies input clock.
• SFR used by serial interface IICA can be read/written.
Note 78K0R/LG3, 78K0R/LH3 only
Caution
When setting serial interface IICA, be sure to set IICAEN to 1 first. If IICAEN = 0, writing to a
control register of serial interface IICA is ignored, and, even if the register is read, only the
default value is read.
(2) IICA control register 0 (IICCTL0)
This register is used to enable/stop I2C operations, set wait timing, and set other I2C operations.
IICCTL0 can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE, WTIM, and ACKE
bits while IICE bit = 0 or during the wait period. These bits can be set at the same time when the IICE bit is set
from “0” to “1”.
Reset signal generation clears this register to 00H.
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Figure 15-6. Format of IICA Control Register 0 (IICCTL0) (1/4)
Address: F0230H
After reset: 00H
R/W
Symbol
IICCTL0
IICE
LREL
WREL
SPIE
WTIM
ACKE
STT
SPT
2
IICE
I C operation enable
Note 1
0
Stop operation. Reset the IICA status register (IICS)
1
Enable operation.
. Stop internal operation.
Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level.
Condition for clearing (IICE = 0)
Condition for setting (IICE = 1)
• Cleared by instruction
• Set by instruction
• Reset
Notes 2,3
LREL
Exit from communications
0
Normal operation
1
This exits from the current communications and sets standby mode. This setting is automatically cleared
to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCL0 and SDA0 lines are set to high impedance.
The following flags of IICA control register 0 (IICCTL0) and IICA status register (IICS) are cleared to 0.
• STT • SPT • MSTS • EXC • COI • TRC • ACKD • STD
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL = 0)
Condition for setting (LREL = 1)
• Automatically cleared after execution
• Set by instruction
• Reset
WREL
Notes 2,3
Wait cancellation
0
Do not cancel wait
1
Cancel wait. This setting is automatically cleared after wait is canceled.
When WREL is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC =
1), the SDA0 line goes into the high impedance state (TRC = 0).
Condition for clearing (WREL = 0)
Condition for setting (WREL = 1)
• Automatically cleared after execution
• Set by instruction
• Reset
Notes 1. The IICS register, the STCF and IICBSY bits of the IICF register, and the CLD and DAD
bits of the IICCTL1 register are reset.
2. The signal of this bit is invalid while IICE is 0.
3. When the LREL and WREL bits are read, 0 is always read.
Caution
If the operation of I2C is enabled (IICE = 1) when the SCL0 line is at high level, the SDA0 line
is at low level, and DFC of the IICCTL1 register is 1, a start condition will be inadvertently
detected immediately. Immediately after enabling I2C to operate (IICE = 1), set LREL (1) by
using a 1-bit memory manipulation instruction.
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Figure 15-6. Format of IICA Control Register 0 (IICCTL0) (2/4)
SPIE
Note 1
Enable/disable generation of interrupt request when stop condition is detected
0
Disable
1
Enable
If WUP of the IICCTL1 register is 1, no stop condition interrupt will be generated even if SPIE = 1.
Condition for clearing (SPIE = 0)
Condition for setting (SPIE = 1)
• Cleared by instruction
• Set by instruction
• Reset
WTIM
Note 1
0
Control of wait and interrupt request generation
Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
1
Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of
this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is
inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local
address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ACK) is issued. However,
when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM = 0)
Condition for setting (WTIM = 1)
• Cleared by instruction
• Set by instruction
• Reset
Notes 1, 2
ACKE
Acknowledgment control
0
Disable acknowledgment.
1
Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level.
Condition for clearing (ACKE = 0)
Condition for setting (ACKE = 1)
• Cleared by instruction
• Set by instruction
• Reset
Notes 1. The signal of this bit is invalid while IICE is 0. Set this bit during that period.
2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledgment is generated
regardless of the set value.
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Figure 15-6. Format of IICA Control Register 0 (IICCTL0) (3/4)
Note
Start condition trigger
STT
0
Do not generate a start condition.
1
When bus is released (in standby state, when IICBSY = 0):
If this bit is set (1), a start condition is generated (startup as the master).
When a third party is communicating:
• When communication reservation function is enabled (IICRSV = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus is released.
• When communication reservation function is disabled (IICRSV = 1)
Even if this bit is set (1), the STT bit is cleared and the STT clear flag (STCF) is set (1). No start
condition is generated.
In the wait state (when master device):
Generates a restart condition after releasing the wait.
Cautions concerning set timing
• For master reception:
Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE
has been cleared to 0 and slave has been notified of final reception.
• For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1
during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as SPT.
• Setting STT to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (STT = 0)
Condition for setting (STT = 1)
• Cleared by setting STT to 1 while communication
• Set by instruction
reservation is prohibited.
• Cleared by loss in arbitration
• Cleared after start condition is generated by master
device
• Cleared by LREL = 1 (exit from communications)
• When IICE = 0 (operation stop)
• Reset
Note The signal of this bit is invalid while IICE0 is 0.
Remarks 1. Bit 1 (STT) becomes 0 when it is read after data setting.
2. IICRSV: Bit 0 of IIC flag register (IICF)
STCF:
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Figure 15-6. Format of IICA Control Register 0 (IICCTL0) (4/4)
SPT
Stop condition trigger
0
Stop condition is not generated.
1
Stop condition is generated (termination of master device’s transfer).
Cautions concerning set timing
• For master reception:
Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when ACKE has been cleared to 0 and slave
has been notified of final reception.
• For master transmission: A stop condition cannot be generated normally during the acknowledge period.
Therefore, set it during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as STT.
• SPT can be set to 1 only when in master mode.
• When WTIM has been cleared to 0, if SPT is set to 1 during the wait period that follows output of eight clocks, note
that a stop condition will be generated during the high-level period of the ninth clock. WTIM should be changed from
0 to 1 during the wait period following the output of eight clocks, and SPT should be set to 1 during the wait period
that follows the output of the ninth clock.
• Setting SPT to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (SPT = 0)
Condition for setting (SPT = 1)
• Cleared by loss in arbitration
• Set by instruction
• Automatically cleared after stop condition is detected
• Cleared by LREL = 1 (exit from communications)
• When IICE = 0 (operation stop)
• Reset
Caution
When bit 3 (TRC) of the IICA status register (IICS) is set to 1, WREL is set to 1 during the
ninth clock and wait is canceled, after which TRC is cleared and the SDA0 line is set to high
impedance. Release the wait performed while the TRC bit is 1 (transmission status) by
writing to the IICA shift register.
Remark
Bit 0 (SPT) becomes 0 when it is read after data setting.
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(3) IICA status register (IICS)
This register indicates the status of I2C.
IICS is read by a 1-bit or 8-bit memory manipulation instruction only when STT = 1 and during the wait period.
Reset signal generation clears this register to 00H.
Caution
Reading the IICS register while the address match wakeup function is enabled (WUP = 1) in STOP
mode is prohibited. When the WUP bit is changed from 1 to 0 (wakeup operation is stopped),
regardless of the INTIICA interrupt request, the change in status is not reflected until the next
start condition or stop condition is detected. To use the wakeup function, therefore, enable (SPIE
= 1) the interrupt generated by detecting a stop condition and read the IICS register after the
interrupt has been detected.
Remark
STT: bit 1 of IICA control register 0 (IICCTL0)
WUP: bit 7 of IICA control register 1 (IICCTL1)
Figure 15-7. Format of IICA Status Register (IICS) (1/3)
Address: FFF51H
After reset: 00H
R
Symbol
IICS
MSTS
ALD
EXC
COI
TRC
ACKD
STD
SPD
MSTS
Master status check flag
0
Slave device status or communication standby status
1
Master device communication status
Condition for clearing (MSTS = 0)
Condition for setting (MSTS = 1)
• When a stop condition is detected
• When ALD = 1 (arbitration loss)
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Reset
• When a start condition is generated
ALD
Detection of arbitration loss
0
This status means either that there was no arbitration or that the arbitration result was a “win”.
1
This status indicates the arbitration result was a “loss”. MSTS is cleared.
Condition for clearing (ALD = 0)
Condition for setting (ALD = 1)
Note
• Automatically cleared after IICS is read
• When IICE changes from 1 to 0 (operation stop)
• Reset
EXC
• When the arbitration result is a “loss”.
Detection of extension code reception
0
Extension code was not received.
1
Extension code was received.
Condition for clearing (EXC = 0)
Condition for setting (EXC = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Reset
• When the higher four bits of the received address
data is either “0000” or “1111” (set at the rising edge
of the eighth clock).
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other than
IICS. Therefore, when using the ALD bit, read the data of this bit before the data of the other bits.
Remark
LREL:
IICE:
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Figure 15-7. Format of IICA Status Register (IICS) (2/3)
COI
Detection of matching addresses
0
Addresses do not match.
1
Addresses match.
Condition for clearing (COI = 0)
Condition for setting (COI = 1)
• When a start condition is detected
• When the received address matches the local
• When a stop condition is detected
• Cleared by LREL = 1 (exit from communications)
address (slave address register (SVA))
(set at the rising edge of the eighth clock).
• When IICE changes from 1 to 0 (operation stop)
• Reset
TRC
Detection of transmit/receive status
0
Receive status (other than transmit status). The SDA0 line is set for high impedance.
1
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at
the falling edge of the first byte’s ninth clock).
Condition for clearing (TRC = 0)
Condition for setting (TRC = 1)
• When a stop condition is detected
• Cleared by LREL = 1 (exit from communications)
• When the IICE bit changes from 1 to 0 (operation
stop)
Note
• Cleared by WREL = 1 (wait cancel)
• When the ALD bit changes from 0 to 1 (arbitration
loss)
• Reset
• When not used for communication (MSTS, EXC, COI = 0)
• When “1” is output to the first byte’s LSB (transfer
direction specification bit)
• When a start condition is detected
• When a start condition is generated
• When 0 (master transmission) is output to the LSB
(transfer direction specification bit) of the first byte
(during address transfer)
• When 1 (slave transmission) is input to the LSB
(transfer direction specification bit) of the first byte
from the master (during address transfer)
• When “0” is input to the first byte’s LSB (transfer
direction specification bit)
Note When bit 3 (TRC) of the IICA status register (IICS) is set to 1 (transmission status), bit 5 (WREL) of
IICA control register 0 (IICCTL0) is set to 1 during the ninth clock and wait is canceled, after which
the TRC bit is cleared (reception status) and the SDA0 line is set to high impedance. Release the
wait performed while the TRC bit is 1 (transmission status) by writing to the IICA shift register.
Remark
LREL:
Bit 6 of IICA control register 0 (IICCTL0)
IICE:
Bit 7 of IICA control register 0 (IICCTL0)
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Figure 15-7. Format of IICA Status Register (IICS) (3/3)
ACKD
Detection of acknowledge (ACK)
0
Acknowledge was not detected.
1
Acknowledge was detected.
Condition for clearing (ACKD = 0)
Condition for setting (ACKD = 1)
• When a stop condition is detected
• After the SDA0 line is set to low level at the rising
• At the rising edge of the next byte’s first clock
edge of SCL0’s ninth clock
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Reset
STD
Detection of start condition
0
Start condition was not detected.
1
Start condition was detected. This indicates that the address transfer period is in effect.
Condition for clearing (STD = 0)
Condition for setting (STD = 1)
• When a stop condition is detected
• When a start condition is detected
• At the rising edge of the next byte’s first clock
following address transfer
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Reset
SPD
Detection of stop condition
0
Stop condition was not detected.
1
Stop condition was detected. The master device’s communication is terminated and the bus is
released.
Condition for clearing (SPD = 0)
Condition for setting (SPD = 1)
• At the rising edge of the address transfer byte’s first
• When a stop condition is detected
clock following setting of this bit and detection of a
start condition
• When IICE changes from 1 to 0 (operation stop)
• Reset
Remark
LREL:
Bit 6 of IICA control register 0 (IICCTL0)
IICE:
Bit 7 of IICA control register 0 (IICCTL0)
(4) IICA flag register (IICF)
This register sets the operation mode of I2C and indicates the status of the I2C bus.
IICF can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STCF and IICBSY bits are readonly.
The IICRSV bit can be used to enable/disable the communication reservation function.
STCEN can be used to set the initial value of the IICBSY bit.
IICRSV and STCEN can be written only when the operation of I2C is disabled (bit 7 (IICE) of IICA control register 0
(IICCTL0) = 0). When operation is enabled, the IICF register can be read.
Reset signal generation clears this register to 00H.
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Figure 15-8. Format of IICA Flag Register (IICF)
Address: FFF52H
After reset: 00H
R/WNote
Symbol
5
4
3
2
IICF
STCF
IICBSY
0
0
0
0
STCEN
IICRSV
STT clear flag
STCF
0
Generate start condition
1
Start condition generation unsuccessful: clear STT flag
Condition for clearing (STCF = 0)
Condition for setting (STCF = 1)
• Cleared by STT = 1
• When IICE = 0 (operation stop)
• Reset
• Generating start condition unsuccessful and STT
cleared to 0 when communication reservation is
disabled (IICRSV = 1).
I2C bus status flag
IICBSY
0
Bus release status (communication initial status when STCEN = 1)
1
Bus communication status (communication initial status when STCEN = 0)
Condition for clearing (IICBSY = 0)
Condition for setting (IICBSY = 1)
• Detection of stop condition
• When IICE = 0 (operation stop)
• Reset
• Detection of start condition
• Setting of IICE when STCEN = 0
STCEN
Initial start enable trigger
0
After operation is enabled (IICE = 1), enable generation of a start condition upon detection of
a stop condition.
1
After operation is enabled (IICE = 1), enable generation of a start condition without detecting
a stop condition.
Condition for clearing (STCEN = 0)
Condition for setting (STCEN = 1)
• Cleared by instruction
• Detection of start condition
• Reset
• Set by instruction
IICRSV
Communication reservation function disable bit
0
Enable communication reservation
1
Disable communication reservation
Condition for clearing (IICRSV = 0)
Condition for setting (IICRSV = 1)
• Cleared by instruction
• Reset
• Set by instruction
Note Bits 6 and 7 are read-only.
Cautions 1. Write to STCEN only when the operation is stopped (IICE = 0).
2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus status
when STCEN = 1, when generating the first start condition (STT = 1), it is necessary to
verify that no third party communications are in progress in order to prevent such
communications from being destroyed.
3. Write to IICRSV only when the operation is stopped (IICE = 0).
Remark
STT: Bit 1 of IICA control register 0 (IICCTL0)
IICE: Bit 7 of IICA control register 0 (IICCTL0)
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(5) IICA control register 1 (IICCTL1)
This register is used to set the operation mode of I2C and detect the statuses of the SCL0 and SDA0 pins.
IICCTL1 can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD and DAD bits are readonly.
Set the IICCTL1 register, except the WUP bit, while operation of I2C is disabled (bit 7 (IICE) of IICA control register
0 (IICCTL0) is 0).
Reset signal generation clears this register to 00H.
Figure 15-9. Format of IICA Control Register 1 (IICCTL1) (1/2)
Address: F0231H
After reset: 00H
R/W
Note 1
Symbol
7
6
1
0
IICCTL1
WUP
0
CLD
DAD
SMC
DFC
0
0
WUP
Control of address match wakeup
0
Stops operation of address match wakeup function in STOP mode.
1
Enables operation of address match wakeup function in STOP mode.
To shift to STOP mode when WUP = 1, execute the STOP instruction at least three clocks after setting (1) the
WUP bit (see Figure 15-22 Flow When Setting WUP = 1).
Clear (0) the WUP bit after the address has matched or an extension code has been received. The subsequent
communication can be entered by the clearing (0) WUP bit. (The wait must be released and transmit data must
be written after the WUP bit has been cleared (0).)
The interrupt timing when the address has matched or when an extension code has been received, while WUP
= 1, is identical to the interrupt timing when WUP = 0. (A delay of the difference of sampling by the clock will
occur.) Furthermore, when WUP = 1, a stop condition interrupt is not generated even if the SPIE bit is set to 1.
When WUP = 0 is set by a source other than an interrupt from serial interface IICA, operation as the master
device cannot be performed until the subsequent start condition or stop condition is detected. Do not output a
start condition by setting (1) the STT bit, without waiting for the detection of the subsequent start condition or
stop condition.
Condition for clearing (WUP = 0)
Condition for setting (WUP = 1)
• Cleared by instruction (after address match or
• Set by instruction (when the MSTS, EXC, and COI
extension code reception)
bits are “0”, and the STD bit also “0” (communication
Note 2
not entered))
Notes 1. Bits 4 and 5 are read-only.
2. The status of the IICA status register (IICS) must be checked and the WUP bit must be set
during the period shown below.
SCL0
SDA0
A6
A5
A4
A3
A2
A1
A0
R/W
The maximum time from reading IICS to setting
WUP is the period from to .
Check the IICS operation status and set
WUP during this period.
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Figure 15-9. Format of IICA Control Register 1 (IICCTL1) (2/2)
CLD
Detection of SCL0 pin level (valid only when IICE = 1)
0
The SCL0 pin was detected at low level.
1
The SCL0 pin was detected at high level.
Condition for clearing (CLD = 0)
Condition for setting (CLD = 1)
• When the SCL0 pin is at low level
• When the SCL0 pin is at high level
• When IICE = 0 (operation stop)
• Reset
DAD
Detection of SDA0 pin level (valid only when IICE = 1)
0
The SDA0 pin was detected at low level.
1
The SDA0 pin was detected at high level.
Condition for clearing (DAD = 0)
Condition for setting (DAD = 1)
• When the SDA0 pin is at low level
• When the SDA0 pin is at high level
• When IICE = 0 (operation stop)
• Reset
SMC
Operation mode switching
0
Operates in standard mode.
1
Operates in fast mode.
DFC
Digital filter operation control
0
Digital filter off.
1
Digital filter on.
Digital filter can be used only in fast mode.
In fast mode, the transfer clock does not vary, regardless of the DFC bit being set (1) or cleared (0).
The digital filter is used for noise elimination in fast mode.
Remark
IICE: Bit 7 of IICA control register 0 (IICCTL0)
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(6) IICA low-level width setting register (IICWL)
This register is used to set the low-level width of the SCL0 pin signal that is output by serial interface IICA.
The IICWL register can be set by an 8-bit memory manipulation instruction.
Set the IICWL register while operation of I2C is disabled (bit 7 (IICE) of IICA control register 0 (IICCTL0) is 0).
Reset signal generation sets this register to FFH.
Figure 15-10. Format of IICA Low-Level Width Setting Register (IICWL)
Address: F0232H
Symbol
After reset: FFH R/W
7
6
5
4
3
2
1
0
IICWL
(7) IICA high-level width setting register (IICWH)
This register is used to set the high-level width of the SCL0 pin signal that is output by serial interface IICA.
The IICWH register can be set by an 8-bit memory manipulation instruction.
Set the IICWH register while operation of I2C is disabled (bit 7 (IICE) of IICA control register 0 (IICCTL0) is 0).
Reset signal generation sets this register to FFH.
Figure 15-11. Format of IICA High-Level Width Setting Register (IICWH)
Address: F0233H
Symbol
After reset: FFH R/W
7
6
5
4
3
2
1
0
IICWH
Remark
For how to set the transfer clock by using the IICWL and IICWH registers, see 15.4.2 Setting
transfer clock by using IICWL and IICWH registers.
(8) Port mode register 6 (PM6)
This register sets the input/output of port 6 in 1-bit units.
When using the P60/SCL0 pin as clock I/O and the P61/SDA0 pin as serial data I/O, clear PM60 and PM61, and
the output latches of P60 and P61 to 0.
Set IICE (bit 7 of IICA control register 0 (IICCTL0)) to 1 before setting the output mode because the P60/SCL0 and
P61/SDA0 pins output a low level (fixed) when IICE is 0.
PM6 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 15-12. Format of Port Mode Register 6 (PM6)
Address: FFF26H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM6
1
1
1
1
1
1
PM61
PM60
PM6n
P6n pin I/O mode selection (n = 0, 1)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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15.4 I2C Bus Mode Functions
15.4.1 Pin configuration
The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows.
(1) SCL0....... This pin is used for serial clock input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
(2) SDA0 ...... This pin is used for serial data input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up
resistor is required.
Figure 15-13. Pin Configuration Diagram
Slave device
VDD
Master device
SCL0
SCL0
Clock output
(Clock output)
VDD
VSS
VSS
(Clock input)
Clock input
SDA0
SDA0
Data output
Data output
VSS
Data input
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15.4.2 Setting transfer clock by using IICWL and IICWH registers
(1) Setting transfer clock on master side
fCLK
Transfer clock = IICWL + IICWH + fCLK (tR + tF)
At this time, the optimal setting values of IICWL and IICWH are as follows.
(The fractional parts of all setting values are rounded up.)
• When the fast mode
0.52
× fCLK
Transfer clock
0.48
IICWH = (
− tR − tF) × fCLK
Transfer clock
IICWL =
• When the standard mode
0.47
× fCLK
Transfer clock
0.53
IICWH = (
− tR − tF) × fCLK
Transfer clock
IICWL =
(2) Setting IICWL and IICWH on slave side
(The fractional parts of all setting values are truncated.)
• When the fast mode
IICWL = 1.3 μs × fCLK
IICWH = (1.2 μs − tR − tF) × fCLK
• When the standard mode
IICWL = 4.7 μs × fCLK
IICWH = (5.3 μs − tR − tF) × fCLK
Caution Note the minimum fCLK operation frequency when setting the transfer clock. The minimum fCLK
operation frequency for serial interface IICA is determined according to the mode.
Remarks 1.
Fast mode:
fCLK = 3.5 MHz (MIN.)
Standard mode:
fCLK = 1 MHz (MIN.)
Calculate the rise time (tR) and fall time (tF) of the SDA0 and SCL0 signals separately, because they
differ depending on the pull-up resistance and wire load.
2.
IICWL: IICA low-level width setting register
IICWH: IICA high-level width setting register
tF:
SDA0 and SCL0 signal falling times
tR:
SDA0 and SCL0 signal rising times
fCLK:
CPU/peripheral hardware clock frequency
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15.5 I2C Bus Definitions and Control Methods
The following section describes the I2C bus’s serial data communication format and the signals used by the I2C bus.
Figure 15-14 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I2C
bus’s serial data bus.
Figure 15-14. I2C Bus Serial Data Transfer Timing
SCL0
1-7
8
9
1-8
9
1-8
9
ACK
Data
ACK
SDA0
Start
condition
Address R/W ACK
Data
Stop
condition
The master device generates the start condition, slave address, and stop condition.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that
receives 8-bit data).
The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0’s low
level period can be extended and a wait can be inserted.
15.5.1 Start conditions
A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level. The
start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device when
starting a serial transfer. When the device is used as a slave, start conditions can be detected.
Figure 15-15. Start Conditions
SCL0
H
SDA0
A start condition is output when bit 1 (STT) of IICA control register 0 (IICCTL0) is set (1) after a stop condition has been
detected (SPD: Bit 0 of the IICA status register (IICS) = 1). When a start condition is detected, bit 1 (STD) of IICS is set
(1).
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15.5.2 Addresses
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the
master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data
matches the data values stored in the slave address register (SVA). If the address data matches the SVA values, the
slave device is selected and communicates with the master device until the master device generates a start condition or
stop condition.
Figure 15-16. Address
SCL0
1
2
3
4
5
6
7
8
SDA0
A6
A5
A4
A3
A2
A1
A0
R/W
9
Address
Note
INTIICA
Note INTIICA is not issued if data other than a local address or extension code is received during slave device
operation.
Addresses are output when a total of 8 bits consisting of the slave address and the transfer direction described in
15.5.3 Transfer direction specification are written to the IICA shift register (IICA). The received addresses are written
to IICA.
The slave address is assigned to the higher 7 bits of IICA.
15.5.3 Transfer direction specification
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction.
When this transfer direction specification bit has a value of “0”, it indicates that the master device is transmitting data to
a slave device. When the transfer direction specification bit has a value of “1”, it indicates that the master device is
receiving data from a slave device.
Figure 15-17. Transfer Direction Specification
SCL0
1
2
3
4
5
6
7
8
SDA0
A6
A5
A4
A3
A2
A1
A0
R/W
9
Transfer direction specification
INTIICA
Note
Note INTIICA is not issued if data other than a local address or extension code is received during slave device
operation.
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15.5.4 Acknowledge (ACK)
ACK is used to check the status of serial data at the transmission and reception sides.
The reception side returns ACK each time it has received 8-bit data.
The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side,
it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been detected
can be checked by using bit 2 (ACKD) of the IICA status register (IICS).
When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a slave
does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops transmission.
If ACK is not returned, the possible causes are as follows.
Reception was not performed normally.
The final data item was received.
The reception side specified by the address does not exist.
To generate ACK, the reception side makes the SDA0 line low at the ninth clock (indicating normal reception).
Automatic generation of ACK is enabled by setting bit 2 (ACKE) of IICA control register 0 (IICCTL0) to 1. Bit 3 (TRC) of
the IICS register is set by the data of the eighth bit that follows 7-bit address information. Usually, set ACKE to 1 for
reception (TRC = 0).
If a slave can receive no more data during reception (TRC = 0) or does not require the next data item, then the slave
must inform the master, by clearing ACKE to 0, that it will not receive any more data.
When the master does not require the next data item during reception (TRC = 0), it must clear ACKE to 0 so that ACK
is not generated. In this way, the master informs a slave at the transmission side that it does not require any more data
(transmission will be stopped).
Figure 15-18. ACK
SCL0
1
2
3
4
5
6
7
8
9
SDA0
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
When the local address is received, ACK is automatically generated, regardless of the value of ACKE. When an
address other than that of the local address is received, ACK is not generated (NACK).
When an extension code is received, ACK is generated if ACKE is set to 1 in advance.
How ACK is generated when data is received differs as follows depending on the setting of the wait timing.
• When 8-clock wait state is selected (bit 3 (WTIM) of IICCTL0 register = 0):
By setting ACKE to 1 before releasing the wait state, ACK is generated at the falling edge of the eighth clock of the
SCL0 pin.
• When 9-clock wait state is selected (bit 3 (WTIM) of IICCTL0 register = 1):
ACK is generated by setting ACKE to 1 in advance.
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15.5.5 Stop condition
When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition.
A stop condition is a signal that the master device generates to the slave device when serial transfer has been
completed. When the device is used as a slave, stop conditions can be detected.
Figure 15-19. Stop Condition
SCL0
H
SDA0
A stop condition is generated when bit 0 (SPT) of IICA control register 0 (IICCTL0) is set to 1. When the stop condition
is detected, bit 0 (SPD) of the IICA status register (IICS) is set to 1 and INTIICA is generated when bit 4 (SPIE) of IICCTL0
is set to 1.
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15.5.6 Wait
The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive
data (i.e., is in a wait state).
Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been
canceled for both the master and slave devices, the next data transfer can begin.
Figure 15-20. Wait (1/2)
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(master transmits, slave receives, and ACKE = 1)
Master
Master returns to high
impedance but slave
is in wait state (low level).
IICA
Wait after output
of ninth clock
IICA data write (cancel wait)
SCL0
6
7
8
9
1
2
3
Slave
Wait after output
of eighth clock
FFH is written to IICA or WREL is set to 1
IICA
SCL0
ACKE
H
Transfer lines
Wait from slave
SCL0
6
7
8
SDA0
D2
D1
D0
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D5
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Figure 15-20. Wait (2/2)
(2) When master and slave devices both have a nine-clock wait
(master transmits, slave receives, and ACKE = 1)
Master
Master and slave both wait
after output of ninth clock
IICA data write (cancel wait)
IICA
6
SCL0
7
8
9
1
2
3
Slave
FFH is written to IICA or WREL is set to 1
IICA
SCL0
ACKE
H
Wait from
master and
slave
Transfer lines
SCL0
6
7
8
9
SDA0
D2
D1
D0
ACK
Wait from slave
1
D7
2
3
D6
D5
Generate according to previously set ACKE value
Remark
ACKE:
Bit 2 of IICA control register 0 (IICCTL0)
WREL:
Bit 5 of IICA control register 0 (IICCTL0)
A wait may be automatically generated depending on the setting of bit 3 (WTIM) of IICA control register 0 (IICCTL0).
Normally, the receiving side cancels the wait state when bit 5 (WREL) of the IICCTL0 register is set to 1 or when FFH is
written to the IICA shift register (IICA), and the transmitting side cancels the wait state when data is written to the IICA
register.
• By setting bit 1 (STT) of IICCTL0 to 1
• By setting bit 0 (SPT) of IICCTL0 to 1
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15.5.7 Canceling wait
The I2C usually cancels a wait state by the following processing.
• Writing data to IICA shift register (IICA)
• Setting bit 5 (WREL) of IICA control register 0 (IICCTL0) (canceling wait)
• Setting bit 1 (STT) of IICCTL0 register (generating start condition)Note
• Setting bit 0 (SPT) of IICCTL0 register (generating stop condition)Note
Note Master only
When the above wait canceling processing is executed, the I2C cancels the wait state and communication is resumed.
To cancel a wait state and transmit data (including addresses), write the data to IICA.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL) of IICA control register
0 (IICCTL0) to 1.
To generate a restart condition after canceling a wait state, set bit 1 (STT) of IICCTL0 to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT) of IICCTL0 to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to IICA after canceling a wait state by setting WREL to 1, an incorrect value may be
output to SDA0 because the timing for changing the SDA0 line conflicts with the timing for writing IICA.
In addition to the above, communication is stopped if IICE is cleared to 0 when communication has been aborted, so
that the wait state can be canceled.
If the I2C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL) of IICCTL0,
so that the wait state can be canceled.
Caution
If a processing to cancel a wait state executed when WUP (bit 7 of IICA control register 1 (IICCTL1)) =
1, the wait state will not be canceled.
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15.5.8 Interrupt request (INTIICA) generation timing and wait control
The setting of bit 3 (WTIM) of IICA control register 0 (IICCTL0) determines the timing by which INTIICA is generated
and the corresponding wait control, as shown in Table 15-2.
Table 15-2. INTIICA Generation Timing and Wait Control
WTIM
During Slave Device Operation
Address
0
1
9
Notes 1, 2
9
Notes 1, 2
Data Reception
8
Note 2
9
Note 2
During Master Device Operation
Data Transmission
Address
Data Reception
Data Transmission
8
Note 2
9
8
8
9
Note 2
9
9
9
Notes 1. The slave device’s INTIICA signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to the slave address register (SVA).
At this point, ACK is generated regardless of the value set to IICCTL0’s bit 2 (ACKE). For a slave device that
has received an extension code, INTIICA occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIICA is generated at the falling edge of the 9th
clock, but wait does not occur.
2. If the received address does not match the contents of the slave address register (SVA) and extension code
is not received, neither INTIICA nor a wait occurs.
Remark
The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and wait
control are both synchronized with the falling edge of these clock signals.
(1) During address transmission/reception
• Slave device operation:
Interrupt and wait timing are determined depending on the conditions described in
Notes 1 and 2 above, regardless of the WTIM bit.
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the
WTIM bit.
(2) During data reception
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM bit.
(3) During data transmission
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM bit.
(4) Wait cancellation method
The four wait cancellation methods are as follows.
• Writing data to IICA shift register (IICA)
• Setting bit 5 (WREL) of IICA control register 0 (IICCTL0) (canceling wait)
• Setting bit 1 (STT) of IICCTL0 register (generating start condition)Note
• Setting bit 0 (SPT) of IICCTL0 register (generating stop condition)Note
Note Master only.
When an 8-clock wait has been selected (WTIM = 0), the presence/absence of ACK generation must be
determined prior to wait cancellation.
(5) Stop condition detection
INTIICA is generated when a stop condition is detected (only when SPIE = 1).
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15.5.9 Address match detection method
In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address.
Address match can be detected automatically by hardware. An interrupt request (INTIICA) occurs when the address
set to the slave address register (SVA) matches the slave address sent by the master device, or when an extension code
has been received.
15.5.10 Error detection
In I2C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by the IICA shift register
(IICA) of the transmitting device, so the IICA data prior to transmission can be compared with the transmitted IICA data to
enable detection of transmission errors. A transmission error is judged as having occurred when the compared data
values do not match.
15.5.11 Extension code
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag (EXC)
is set to 1 for extension code reception and an interrupt request (INTIICA) is issued at the falling edge of the eighth
clock. The local address stored in the slave address register (SVA) is not affected.
(2) The settings below are specified if 11110xx0 is transferred from the master by using a 10-bit address transfer when
the SVA register is set to 11110xx0. Note that INTIICA occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC = 1
• Seven bits of data match:
Remark
COI = 1
EXC:
Bit 5 of IICA status register (IICS)
COI:
Bit 4 of IICA status register (IICS)
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code,
such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave device,
set bit 6 (LREL) of the IICA control register 0 (IICCTL0) to 1 to set the standby mode for the next communication
operation.
Table 15-3. Bit Definitions of Main Extension Code
Slave Address
R/W Bit
Description
0000 000
0
General call address
1111 0xx
0
10-bit slave address specification (for address authentication)
1111 0xx
1
10-bit slave address specification (for read command issuance
after address match)
Remark
For extension codes other than the above, refer to THE I2C-BUS SPECIFICATION published by NXP.
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15.5.12 Arbitration
When several master devices simultaneously generate a start condition (when STT is set to 1 before STD is set to 1),
communication among the master devices is performed as the number of clocks are adjusted until the data differs. This
kind of operation is called arbitration.
When one of the master devices loses in arbitration, an arbitration loss flag (ALD) in the IICA status register (IICS) is
set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high impedance,
which releases the bus.
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop
condition is detected, etc.) and the ALD = 1 setting that has been made by software.
For details of interrupt request timing, see 15.5.8 Interrupt request (INTIICA) generation timing and wait control.
Remark
STD:
Bit 1 of IICA status register (IICS)
STT:
Bit 1 of IICA control register 0 (IICCTL0)
Figure 15-21. Arbitration Timing Example
Master 1
SCL0
SDA0
Master 2
Hi-Z
Hi-Z
Master 1 loses arbitration
SCL0
SDA0
Transfer lines
SCL0
SDA0
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Table 15-4. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration
During address transmission
Interrupt Request Generation Timing
At falling edge of eighth or ninth clock following byte transfer
Note 1
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
Note 2
When stop condition is detected during data transfer
When stop condition is generated (when SPIE = 1)
When data is at low level while attempting to generate a restart
At falling edge of eighth or ninth clock following byte transfer
Note 1
condition
When stop condition is detected while attempting to generate a
When stop condition is generated (when SPIE = 1)
Note 2
restart condition
When data is at low level while attempting to generate a stop
At falling edge of eighth or ninth clock following byte transfer
Note 1
condition
When SCL0 is at low level while attempting to generate a
restart condition
Notes 1. When WTIM (bit 3 of IICA control register 0 (IICCTL0)) = 1, an interrupt request occurs at the falling edge of
the ninth clock. When WTIM = 0 and the extension code’s slave address is received, an interrupt request
occurs at the falling edge of the eighth clock.
2. When there is a chance that arbitration will occur, set SPIE = 1 for master device operation.
Remark
SPIE: Bit 4 of IICA control register 0 (IICCTL0)
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15.5.13 Wakeup function
The I2C bus slave function is a function that generates an interrupt request signal (INTIICA) when a local address and
extension code have been received.
This function makes processing more efficient by preventing unnecessary INTIICA signal from occurring when
addresses do not match.
When a start condition is detected, wakeup standby mode is set.
This wakeup standby mode is in effect while
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has
generated a start condition) to a slave device.
However, when a stop condition is detected, bit 4 (SPIE) of IICA control register 0 (IICCTL0) is set regardless of the
wakeup function, and this determines whether interrupt requests are enabled or disabled.
To use the wakeup function in the STOP mode, set WUP to 1. Addresses can be received regardless of the operation
clock. An interrupt request signal (INTIICA) is also generated when a local address and extension code have been
received. Operation returns to normal operation by using an instruction to clear (0) the WUP bit after this interrupt has
been generated.
Figure 15-22 shows the flow for setting WUP = 1 and Figure 15-23 shows the flow for setting WUP = 0 upon an
address match.
Figure 15-22. Flow When Setting WUP = 1
START
MSTS = STD = EXC = COI =0?
No
Yes
WUP = 1
Wait
Waits for 3 clocks.
STOP instruction execution
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Figure 15-23. Flow When Setting WUP = 0 upon Address Match (Including Extension Code Reception)
STOP mode state
No
INTIICA = 1?
Yes
WUP = 0
Wait
Waits for 5 clocks.
Reading IICS
Executes processing corresponding to the operation to be executed
after checking the operation state of serial interface IICA.
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Use the following flows to perform the processing to release the STOP mode other than by an interrupt request
(INTIICA) generated from serial interface IICA.
• Master device operation: Flow shown in Figure 15-24
• Slave device operation: Same as the flow in Figure 15-23
Figure 15-24. When Operating as Master Device after Releasing STOP Mode other than by INTIICA
START
SPIE = 1
WUP = 1
STOP instruction
STOP mode state
Releasing STOP mode
Releases STOP mode by an interrupt other than INTIICA.
WUP = 0
No
INTIICA = 1?
Yes
Wait
Generates a STOP condition or selects
as a slave device.
Waits for 5 clocks.
Reading IICS
Executes processing corresponding to the operation to be executed
after checking the operation state of serial interface IICA.
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15.5.14 Communication reservation
(1) When communication reservation function is enabled (bit 0 (IICRSV) of IICA flag register (IICF) = 0)
To start master device communications when not currently using a bus, a communication reservation can be made
to enable transmission of a start condition when the bus is released. There are two modes under which the bus is
not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released by setting bit 6 (LREL) of IICA control register 0 (IICCTL0) to 1 and saving communication).
If bit 1 (STT) of IICCTL0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition is
automatically generated and wait state is set.
If an address is written to the IICA shift register (IICA) after bit 4 (SPIE) of IICCTL0 was set to 1, and it was
detected by generation of an interrupt request signal (INTIICA) that the bus was released (detection of the stop
condition), then the device automatically starts communication as the master. Data written to IICA before the stop
condition is detected is invalid.
When STT has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
• If the bus has been released ........................................ a start condition is generated
• If the bus has not been released (standby mode)......... communication reservation
Check whether the communication reservation operates or not by using MSTS (bit 7 of the IICA status register
(IICS)) after STT is set to 1 and the wait time elapses.
Use software to secure the wait time calculated by the following expression.
Wait time from setting STT = 1 to checking the MSTS flag:
(IICWL setting value + IICWH setting value + 4 clocks) / fCLK + tF × 2
Remark
IICWL: IICA low-level width setting register
IICWH: IICA high-level width setting register
tF:
SDA0 and SCL0 signal falling times
fCLK:
CPU/peripheral hardware clock frequency
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Figure 15-25 shows the communication reservation timing.
Figure 15-25. Communication Reservation Timing
Program processing
Write to
IICA
STT = 1
CommuniHardware processing cation
reservation
SCL0
1
2
3
4
Set SPD
and
INTIICA
5
6
7
8
9
Set
STD
1
2
3
4
5
6
SDA0
Generate by master device with bus mastership
Remark
IICA:
IICA shift register
STT:
Bit 1 of IICA control register 0 (IICCTL0)
STD:
Bit 1 of IICA status register (IICS)
SPD:
Bit 0 of IICA status register (IICS)
Communication reservations are accepted via the timing shown in Figure 15-26. After bit 1 (STD) of the IICA
status register (IICS) is set to 1, a communication reservation can be made by setting bit 1 (STT) of IICA control
register 0 (IICCTL0) to 1 before a stop condition is detected.
Figure 15-26. Timing for Accepting Communication Reservations
SCL0
SDA0
STD
SPD
Standby mode (Communication can be reserved by setting STT to 1 during this period.)
Figure 15-27 shows the communication reservation protocol.
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Figure 15-27. Communication Reservation Protocol
DI
SET1 STT
Define communication
reservation
Wait
(Communication reservation)Note 2
MSTS = 0?
Yes
Sets STT flag (communication reservation)
Defines that communication reservation is in effect
(defines and sets user flag to any part of RAM)
Secures wait timeNote 1 by software.
Confirmation of communication reservation
No
(Generate start condition)
Cancel communication
reservation
MOV IICA, #××H
Clear user flag
IICA write operation
EI
Notes 1. The wait time is calculated as follows.
(IICWL setting value + IICWH setting value + 4 clocks) / fCLK + tF × 2
2. The communication reservation operation executes a write to the IICA shift register (IICA) when a stop
condition interrupt request occurs.
Remark STT:
Bit 1 of IICA control register 0 (IICCTL0)
MSTS: Bit 7 of IICA status register (IICS)
IICA:
IICA shift register
IICWL: IICA low-level width setting register
IICWH: IICA high-level width setting register
tF:
SDA0 and SCL0 signal falling times
fCLK:
CPU/peripheral hardware clock frequency
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(2) When communication reservation function is disabled (bit 0 (IICRSV) of IICA flag register (IICF) = 1)
When bit 1 (STT) of IICA control register 0 (IICCTL0) is set to 1 when the bus is not used in a communication
during bus communication, this request is rejected and a start condition is not generated. The following two
statuses are included in the status where bus is not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released by setting bit 6 (LREL) of IICCTL0 to 1 and saving communication)
To confirm whether the start condition was generated or request was rejected, check STCF (bit 7 of IICF). It takes
up to 5 clocks until STCF is set to 1 after setting STT = 1. Therefore, secure the time by software.
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15.5.15 Cautions
(1) When STCEN = 0
Immediately after I2C operation is enabled (IICE = 1), the bus communication status (IICBSY = 1) is recognized
regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a
master device communication mode, first generate a stop condition to release the bus, then perform master device
communication.
When using multiple masters, it is not possible to perform master device communication when the bus has not
been released (when a stop condition has not been detected).
Use the following sequence for generating a stop condition.
Set IICA control register 1 (IICCTL1).
Set bit 7 (IICE) of IICA control register 0 (IICCTL0) to 1.
Set bit 0 (SPT) of IICCTL0 to 1.
(2) When STCEN = 1
Immediately after I2C operation is enabled (IICE = 1), the bus released status (IICBSY = 0) is recognized
regardless of the actual bus status. To generate the first start condition (STT = 1), it is necessary to confirm that
the bus has been released, so as to not disturb other communications.
(3) If other I2C communications are already in progress
If I2C operation is enabled and the device participates in communication already in progress when the SDA0 pin is
low and the SCL0 pin is high, the macro of I2C recognizes that the SDA0 pin has gone low (detects a start
condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned, but this
interferes with other I2C communications. To avoid this, start I2C in the following sequence.
Clear bit 4 (SPIE) of IICCTL0 to 0 to disable generation of an interrupt request signal (INTIICA) when the stop
condition is detected.
Set bit 7 (IICE) of IICCTL0 to 1 to enable the operation of I2C.
Wait for detection of the start condition.
Set bit 6 (LREL) of IICCTL0 to 1 before ACK is returned (4 to 80 clocks after setting IICE to 1), to forcibly
disable detection.
(4) Setting STT and SPT (bits 1 and 0 of IICCTL0) again after they are set and before they are cleared to 0 is
prohibited.
(5) When transmission is reserved, set SPIE (bit 4 of IICTL0) to 1 so that an interrupt request is generated when the
stop condition is detected. Transfer is started when communication data is written to IICA after the interrupt request
is generated. Unless the interrupt is generated when the stop condition is detected, the device stops in the wait
state because the interrupt request is not generated when communication is started. However, it is not necessary
to set SPIE to 1 when MSTS (bit 7 of IICS) is detected by software.
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15.5.16 Communication operations
The following shows three operation procedures with the flowchart.
(1) Master operation in single master system
The flowchart when using the 78K0R/Lx3 microcontrollers as the master in a single master system is shown below.
This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings
at startup.
If communication with the slave is required, prepare the communication and then execute
communication processing.
(2) Master operation in multimaster system
In the I2C bus multimaster system, whether the bus is released or used cannot be judged by the I2C bus
specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a
certain period (1 frame), the 78K0R/Lx3 microcontrollers take part in a communication with bus released state.
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing.
The processing when the 78K0R/Lx3 microcontrollers loose in arbitration and are specified as the slave is omitted
here, and only the processing as the master is shown. Execute the initial settings at startup to take part in a
communication. Then, wait for the communication request as the master or wait for the specification as the slave.
The
actual
communication
is
performed
in
the
communication
processing,
and
it
supports
the
transmission/reception with the slave and the arbitration with other masters.
(3) Slave operation
An example of when the 78K0R/Lx3 microcontrollers are used as the I2C bus slave is shown below.
When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for the
INTIICA interrupt occurrence (communication waiting). When an INTIICA interrupt occurs, the communication
status is judged and its result is passed as a flag over to the main processing.
By checking the flags, necessary communication processing is performed.
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(1) Master operation in single-master system
Figure 15-28. Master Operation in Single-Master System
START
Initializing I2C busNote
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 15.3 (8) Port mode register 6 (PM6)).
Initial setting
Setting port
IICWL, IICWH ← XXH
Sets a transfer clock.
SVA ← XXH
Sets a local address.
IICF ← 0XH
Setting STCEN, IICRSV = 0
Sets a start condition.
IICCTL0 ← 0XX111XXB
ACKE = WTIM = SPIE = 1
IICCTL0 ← 1XX111XXB
IICE = 1
2
Set the port from input mode to output mode and enable the output of the I C bus
(see 15.3 (8) Port mode register 6 (PM6)).
Setting port
STCEN = 1?
Yes
No
SPT = 1
INTIICA
interrupt occurs?
Prepares for starting communication
(generates a stop condition).
No
Waits for detection of the stop condition.
Yes
STT = 1
Prepares for starting communication
(generates a start condition).
Writing IICA
Starts communication
(specifies an address and transfer
direction).
INTIICA
interrupt occurs?
No
Waits for detection of acknowledge.
Yes
No
ACKD = 1?
Yes
TRC = 1?
No
ACKE = 1
WTIM = 0
Communication processing
Yes
Writing IICA
Starts transmission.
WREL = 1
INTIICA
interrupt occurs?
No
Waits for data transmission.
INTIICA
interrupt occurs?
Yes
Yes
ACKD = 1?
No
Starts reception.
No
Waits for data
reception.
Reading IICA
Yes
No
End of transfer?
No
End of transfer?
Yes
Yes
Restart?
Yes
ACKE = 0
WTIM = WREL = 1
No
SPT = 1
INTIICA
interrupt occurs?
Yes
No
Waits for detection
of acknowledge.
END
2
Note Release (SCL0 and SDA0 pins = high level) the I C bus in conformance with the specifications of the product
that is communicating. If EEPROM is outputting a low level to the SDA0 pin, for example, set the SCL0 pin in
the output port mode, and output a clock pulse from the output port until the SDA0 pin is constantly at high level.
Remark Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
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(2) Master operation in multi-master system
Figure 15-29. Master Operation in Multi-Master System (1/3)
START
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 15.3 (8) Port mode register 6 (PM6)).
Setting port
IICWL, IICWH ← XXH
Selects a transfer clock.
SVA ← XXH
Sets a local address.
IICF ← 0XH
Setting STCEN and IICRSV
Sets a start condition.
IICCTL0 ← 0XX111XXB
ACKE = WTIM = SPIE = 1
IICCTL0 ← 1XX111XXB
IICE = 1
2
Set the port from input mode to output mode and enable the output of the I C bus
(see 15.3 (8) Port mode register 6 (PM6)).
Initial setting
Setting port
Checking bus statusNote
Releases the bus for a specific period.
Bus status is
being checked.
No
No
STCEN = 1?
INTIICA
interrupt occurs?
Prepares for starting
communication
(generates a stop condition).
SPT = 1
Yes
Yes
SPD = 1?
INTIICA
interrupt occurs?
No
Yes
Yes
Slave operation
SPD = 1?
No
Waits for detection
of the stop condition.
No
Yes
1
Waits for a communication
Slave operation
• Waiting to be specified as a slave by other master
• Waiting for a communication start request (depends on user program)
Master operation
starts?
No
(No communication start request)
Yes
(Communication start request)
SPIE = 0
INTIICA
interrupt occurs?
SPIE = 1
No
Waits for a communication request.
Yes
IICRSV = 0?
No
Slave operation
Yes
A
B
Enables reserving Disables reserving
communication.
communication.
Note Confirm that the bus is released (CLD bit = 1, DAD bit = 1) for a specific period (for example, for a period of one
frame). If the SDA0 pin is constantly at low level, decide whether to release the I2C bus (SCL0 and SDA0 pins =
high level) in conformance with the specifications of the product that is communicating.
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Figure 15-29. Master Operation in Multi-Master System (2/3)
A
Enables reserving communication.
Prepares for starting communication
(generates a start condition).
STT = 1
Secure wait timeNote by software.
Communication processing
Wait
MSTS = 1?
No
Yes
INTIICA
interrupt occurs?
No
Waits for bus release
(communication being reserved).
Yes
No
Wait state after stop condition
was detected and start condition
was generated by the communication
reservation function.
C
Yes
Slave operation
B
Disables reserving communication.
IICBSY = 0?
No
Yes
D
STT = 1
Communication processing
EXC = 1 or COI =1?
Prepares for starting communication
(generates a start condition).
WaitNote
STCF = 0?
No
Yes
INTIICA
interrupt occurs?
No
Waits for bus release
Yes
C
EXC = 1 or COI =1?
No
Detects a stop condition.
Yes
Slave operation
D
Note The wait time is calculated as follows.
(IICWL setting value + IICWH setting value + 4 clocks) / fCLK + tF × 2
Remark
IICWL: IICA low-level width setting register
IICWH: IICA high-level width setting register
tF:
SDA0 and SCL0 signal falling times
fCLK:
CPU/peripheral hardware clock frequency
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Figure 15-29. Master Operation in Multi-Master System (3/3)
C
Writing IICA
INTIICA
interrupt occurs?
Starts communication
(specifies an address and transfer direction).
No
Waits for detection of ACK.
Yes
MSTS = 1?
No
Yes
No
2
ACKD = 1?
Yes
TRC = 1?
No
ACKE = 1
WTIM = 0
Yes
Communication processing
WTIM = 1
WREL = 1
Writing IICA
INTIICA
interrupt occurs?
INTIICA
interrupt occurs?
No
Waits for data transmission.
Yes
MSTS = 1?
No
Waits for data reception.
Yes
MSTS = 1?
No
No
Yes
Yes
ACKD = 1?
Starts reception.
Starts transmission.
2
2
Reading IICA
No
Transfer end?
No
Yes
Yes
No
WTIM = WREL = 1
ACKE = 0
Transfer end?
Yes
Restart?
INTIICA
interrupt occurs?
No
No
Waits for detection of ACK.
Yes
SPT = 1
Yes
MSTS = 1?
STT = 1
END
Yes
No
2
Communication processing
C
2
EXC = 1 or COI = 1?
Yes
Slave operation
No
1
Does not participate
in communication.
Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
2. To use the device as a master in a multi-master system, read the MSTS bit each time interrupt INTIICA
has occurred to check the arbitration result.
3. To use the device as a slave in a multi-master system, check the status by using the IICS and IICF
registers each time interrupt INTIICA has occurred, and determine the processing to be performed next.
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(3) Slave operation
The processing procedure of the slave operation is as follows.
Basically, the slave operation is event-driven. Therefore, processing by the INTIICA interrupt (processing that must
substantially change the operation status such as detection of a stop condition during communication) is
necessary.
In the following explanation, it is assumed that the extension code is not supported for data communication. It is
also assumed that the INTIICA interrupt servicing only performs status transition processing, and that actual data
communication is performed by the main processing.
INTIICA
Flag
Interrupt servicing
Setting
Main processing
IICA
Data
Setting
Therefore, data communication processing is performed by preparing the following three flags and passing them to
the main processing instead of INTIICA.
Communication mode flag
This flag indicates the following two communication statuses.
• Clear mode:
Status in which data communication is not performed
• Communication mode: Status in which data communication is performed (from valid address detection to
stop condition detection, no detection of ACK from master, address mismatch)
Ready flag
This flag indicates that data communication is enabled. Its function is the same as the INTIICA interrupt for
ordinary data communication. This flag is set by interrupt servicing and cleared by the main processing.
Clear this flag by interrupt servicing when communication is started. However, the ready flag is not set by
interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted without the flag
being cleared (an address match is interpreted as a request for the next data).
Communication direction flag
This flag indicates the direction of communication. Its value is the same as TRC.
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The main processing of the slave operation is explained next.
Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute
communication by using the communication mode flag and ready flag (processing of the stop condition and start
condition is performed by an interrupt. Here, check the status by using the flags).
The transmission operation is repeated until the master no longer returns ACK. If ACK is not returned from the
master, communication is completed.
For reception, the necessary amount of data is received. When communication is completed, ACK is not returned
as the next data.
After that, the master generates a stop condition or restart condition.
Exit from the
communication status occurs in this way.
Figure 15-30. Slave Operation Flowchart (1)
START
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 15.3 (8) Port mode register 6 (PM6)).
Setting port
Initial setting
IICWL, IICWH ← XXH
Selects a transfer clock.
SVA ← XXH
Sets a local address.
IICF ← 0XH
Sets a start condition.
Setting IICRSV
IICCTL0 ← 0XX011XXB
ACKE = WTIM = 1, SPIE = 0
IICCTL0 ← 1XX011XXB
IICE = 1
Set the port from input mode to output mode and enable the output of the I2C bus
(see 15.3 (8) Port mode register 6 (PM6)).
Setting port
No
Communication
mode flag = 1?
Yes
Communication
direction flag = 1?
No
Yes
WREL = 1
Writing IICA
Communication processing
No
Communication
mode flag = 1?
Communication
mode flag = 1?
No
Yes
Yes
No
Starts
reception.
Starts
transmission.
Communication
direction flag = 0?
Communication
direction flag = 1?
No
Yes
No
Yes
No
Ready flag = 1?
Ready flag = 1?
Yes
Yes
Reading IICA
Clearing ready flag
Yes
Clearing ready flag
ACKD = 1?
No
Clearing communication
mode flag
WREL = 1
Remark
Conform to the specifications of the product that is in communication, regarding the transmission and
reception formats.
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An example of the processing procedure of the slave with the INTIICA interrupt is explained below (processing is
performed assuming that no extension code is used). The INTIICA interrupt checks the status, and the following
operations are performed.
Communication is stopped if the stop condition is issued.
If the start condition is issued, the address is checked and communication is completed if the address does
not match. If the address matches, the communication mode is set, wait is cancelled, and processing returns
from the interrupt (the ready flag is cleared).
For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I2C bus
remaining in the wait state.
Remark
to above correspond to to in Figure 15-31 Slave Operation Flowchart (2).
Figure 15-31. Slave Operation Flowchart (2)
INTIICA generated
Yes
Yes
SPD = 1?
No
STD = 1?
No
No
COI = 1?
Yes
Set ready flag
Communication direction flag
← TRC
Set communication mode flag
Clear ready flag
Clear communication direction
flag, ready flag, and
communication mode flag
Interrupt servicing completed
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15.5.17 Timing of I2C interrupt request (INTIICA) occurrence
The timing of transmitting or receiving data and generation of interrupt request signal INTIICA, and the value of the IICS
register when the INTIICA signal is generated are shown below.
Remark
ST:
Start condition
AD6 to AD0: Address
R/W:
Transfer direction specification
ACK:
Acknowledge
D7 to D0:
Data
SP:
Stop condition
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(1) Master device operation
(a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception)
(i) When WTIM = 0
SPT = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
D7 to D0
2
ACK
SP
3
4
5
1: IICS = 1000×110B
2: IICS = 1000×000B
3: IICS = 1000×000B (Sets WTIM to 1)Note
4: IICS = 1000××00B (Sets SPT to 1)Note
5: IICS = 00000001B
Note To generate a stop condition, set WTIM to 1 and change the timing for generating the INTIICA interrupt
request signal.
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1
SPT = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
D7 to D0
2
ACK
SP
3
4
1: IICS = 1000×110B
2: IICS = 1000×100B
3: IICS = 1000××00B (Sets SPT to 1)
4: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart)
(i) When WTIM = 0
STT = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
ST
2
3
1
SPT = 1
↓
AD6 to AD0 R/W ACK
D7 to D0
4
ACK
SP
5
6
7
1: IICS = 1000×110B
2: IICS = 1000×000B (Sets WTIM to 1)Note 1
3: IICS = 1000××00B (Clears WTIM to 0Note 2, sets STT to 1)
4: IICS = 1000×110B
5: IICS = 1000×000B (Sets WTIM to 1)Note 3
6: IICS = 1000××00B (Sets SPT to 1)
7: IICS = 00000001B
Notes 1. To generate a start condition, set WTIM to 1 and change the timing for generating the INTIICA
interrupt request signal.
2. Clear WTIM to 0 to restore the original setting.
3. To generate a stop condition, set WTIM to 1 and change the timing for generating the INTIICA
interrupt request signal.
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1
STT = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
ST
2
SPT = 1
↓
AD6 to AD0 R/W ACK
D7 to D0
3
ACK
SP
4
5
1: IICS = 1000×110B
2: IICS = 1000××00B (Sets STT to 1)
3: IICS = 1000×110B
4: IICS = 1000××00B (Sets SPT to 1)
5: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission)
(i) When WTIM = 0
SPT = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
D7 to D0
2
ACK
SP
3
4
5
1: IICS = 1010×110B
2: IICS = 1010×000B
3: IICS = 1010×000B (Sets WTIM to 1)Note
4: IICS = 1010××00B (Sets SPT to 1)
5: IICS = 00000001B
Note To generate a stop condition, set WTIM to 1 and change the timing for generating the INTIICA interrupt
request signal.
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1
SPT = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
D7 to D0
2
ACK
SP
3
4
1: IICS = 1010×110B
2: IICS = 1010×100B
3: IICS = 1010××00B (Sets SPT to 1)
4: IICS = 00001001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(2) Slave device operation (slave address data reception)
(a) Start ~ Address ~ Data ~ Data ~ Stop
(i) When WTIM = 0
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
D7 to D0
2
ACK
SP
3
4
1: IICS = 0001×110B
2: IICS = 0001×000B
3: IICS = 0001×000B
4: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
D7 to D0
2
ACK
SP
3
4
1: IICS = 0001×110B
2: IICS = 0001×100B
3: IICS = 0001××00B
4: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM = 0 (after restart, matches with SVA)
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
ST
AD6 to AD0 R/W ACK
2
D7 to D0
3
ACK
SP
4
5
1: IICS = 0001×110B
2: IICS = 0001×000B
3: IICS = 0001×110B
4: IICS = 0001×000B
5: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1 (after restart, matches with SVA)
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
ST
2
AD6 to AD0 R/W ACK
D7 to D0
3
ACK
SP
4
5
1: IICS = 0001×110B
2: IICS = 0001××00B
3: IICS = 0001×110B
4: IICS = 0001××00B
5: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop
(i) When WTIM = 0 (after restart, does not match address (= extension code))
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
ST
2
AD6 to AD0 R/W ACK
D7 to D0
3
ACK
SP
4
5
1: IICS = 0001×110B
2: IICS = 0001×000B
3: IICS = 0010×010B
4: IICS = 0010×000B
5: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1 (after restart, does not match address (= extension code))
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
ST
2
AD6 to AD0 R/W ACK
3
D7 to D0
4
ACK
SP
5
6
1: IICS = 0001×110B
2: IICS = 0001××00B
3: IICS = 0010×010B
4: IICS = 0010×110B
5: IICS = 0010××00B
6: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM = 0 (after restart, does not match address (= not extension code))
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
ST
AD6 to AD0 R/W ACK
2
D7 to D0
ACK
SP
3
4
1: IICS = 0001×110B
2: IICS = 0001×000B
3: IICS = 00000110B
4: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1 (after restart, does not match address (= not extension code))
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
ST
2
AD6 to AD0 R/W ACK
D7 to D0
3
ACK
SP
4
1: IICS = 0001×110B
2: IICS = 0001××00B
3: IICS = 00000110B
4: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(3) Slave device operation (when receiving extension code)
The device is always participating in communication when it receives an extension code.
(a) Start ~ Code ~ Data ~ Data ~ Stop
(i) When WTIM = 0
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
D7 to D0
2
ACK
SP
3
4
1: IICS = 0010×010B
2: IICS = 0010×000B
3: IICS = 0010×000B
4: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1
ST
AD6 to AD0 R/W ACK
1
D7 to D0
2
ACK
D7 to D0
3
ACK
SP
4
5
1: IICS = 0010×010B
2: IICS = 0010×110B
3: IICS = 0010×100B
4: IICS = 0010××00B
5: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM = 0 (after restart, matches SVA)
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
ST
AD6 to AD0 R/W ACK
2
D7 to D0
3
ACK
SP
4
5
1: IICS = 0010×010B
2: IICS = 0010×000B
3: IICS = 0001×110B
4: IICS = 0001×000B
5: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1 (after restart, matches SVA)
ST
AD6 to AD0 R/W ACK
1
D7 to D0
ACK
2
ST
3
AD6 to AD0 R/W ACK
D7 to D0
4
ACK
SP
5
6
1: IICS = 0010×010B
2: IICS = 0010×110B
3: IICS = 0010××00B
4: IICS = 0001×110B
5: IICS = 0001××00B
6: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop
(i) When WTIM = 0 (after restart, extension code reception)
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
ST
AD6 to AD0 R/W ACK
2
D7 to D0
3
ACK
SP
4
5
1: IICS = 0010×010B
2: IICS = 0010×000B
3: IICS = 0010×010B
4: IICS = 0010×000B
5: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1 (after restart, extension code reception)
ST
AD6 to AD0 R/W ACK
1
D7 to D0
ACK
2
ST
3
AD6 to AD0 R/W ACK
4
D7 to D0
5
ACK
SP
6
7
1: IICS = 0010×010B
2: IICS = 0010×110B
3: IICS = 0010××00B
4: IICS = 0010×010B
5: IICS = 0010×110B
6: IICS = 0010××00B
7: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM = 0 (after restart, does not match address (= not extension code))
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
ST
AD6 to AD0 R/W ACK
2
D7 to D0
ACK
SP
3
4
1: IICS = 00100010B
2: IICS = 00100000B
3: IICS = 00000110B
4: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1 (after restart, does not match address (= not extension code))
ST
AD6 to AD0 R/W ACK
1
D7 to D0
ACK
2
ST
3
AD6 to AD0 R/W ACK
D7 to D0
4
ACK
SP
5
1: IICS = 00100010B
2: IICS = 00100110B
3: IICS = 00100×00B
4: IICS = 00000110B
5: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(4) Operation without communication
(a) Start ~ Code ~ Data ~ Data ~ Stop
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
D7 to D0
ACK
SP
1
1: IICS = 00000001B
Remark
: Generated only when SPIE = 1
(5) Arbitration loss operation (operation as slave after arbitration loss)
When the device is used as a master in a multi-master system, read the MSTS bit each time interrupt request
signal INTIICA has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data
(i) When WTIM = 0
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
2
D7 to D0
ACK
3
SP
4
1: IICS = 0101×110B
2: IICS = 0001×000B
3: IICS = 0001×000B
4: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(ii) When WTIM = 1
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
ACK
2
SP
3
4
1: IICS = 0101×110B
2: IICS = 0001×100B
3: IICS = 0001××00B
4: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(b) When arbitration loss occurs during transmission of extension code
(i) When WTIM = 0
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
2
D7 to D0
ACK
3
SP
4
1: IICS = 0110×010B
2: IICS = 0010×000B
3: IICS = 0010×000B
4: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(ii) When WTIM = 1
ST
AD6 to AD0 R/W ACK
1
D7 to D0
ACK
2
D7 to D0
ACK
3
SP
4
5
1: IICS = 0110×010B
2: IICS = 0010×110B
3: IICS = 0010×100B
4: IICS = 0010××00B
5: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(6) Operation when arbitration loss occurs (no communication after arbitration loss)
When the device is used as a master in a multi-master system, read the MSTS bit each time interrupt request
signal INTIICA has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data (when WTIM = 1)
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
D7 to D0
ACK
SP
2
1: IICS = 01000110B
2: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
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(b) When arbitration loss occurs during transmission of extension code
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
D7 to D0
ACK
SP
1
2
1: IICS = 0110×010B
Sets LREL = 1 by software
2: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(c) When arbitration loss occurs during transmission of data
(i) When WTIM = 0
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
2
D7 to D0
ACK
SP
3
1: IICS = 10001110B
2: IICS = 01000000B
3: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
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(ii) When WTIM = 1
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
ACK
SP
2
3
1: IICS = 10001110B
2: IICS = 01000100B
3: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
(d) When loss occurs due to restart condition during data transfer
(i) Not extension code (Example: unmatches with SVA)
ST
AD6 to AD0 R/W ACK
D7 to Dn
ST
1
AD6 to AD0 R/W ACK
D7 to D0
2
ACK
SP
3
1: IICS = 1000×110B
2: IICS = 01000110B
3: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
n = 6 to 0
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(ii) Extension code
ST
AD6 to AD0 R/W ACK
D7 to Dn
ST
AD6 to AD0 R/W ACK
1
2
D7 to D0
ACK
SP
3
1: IICS = 1000×110B
2: IICS = 01100010B
Sets LREL = 1 by software
3: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
n = 6 to 0
(e) When loss occurs due to stop condition during data transfer
ST
AD6 to AD0 R/W ACK
D7 to Dn
SP
1
2
1: IICS = 10000110B
2: IICS = 01000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
n = 6 to 0
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(f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition
(i) When WTIM = 0
STT = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
2
D7 to D0
3
ACK
D7 to D0
ACK
SP
4
5
1: IICS = 1000×110B
2: IICS = 1000×000B (Sets WTIM to 1)
3: IICS = 1000×100B (Clears WTIM to 0)
4: IICS = 01000000B
5: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1
STT = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
2
ACK
D7 to D0
3
ACK
SP
4
1: IICS = 1000×110B
2: IICS = 1000×100B (Sets STT to 1)
3: IICS = 01000100B
4: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition
(i) When WTIM = 0
STT = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
2
SP
3
4
1: IICS = 1000×110B
2: IICS = 1000×000B (Sets WTIM to 1)
3: IICS = 1000××00B (Sets STT to 1)
4: IICS = 01000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1
STT = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
SP
2
3
1: IICS = 1000×110B
2: IICS = 1000××00B (Sets STT to 1)
3: IICS = 01000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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(h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition
(i) When WTIM = 0
SPT = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
1
ACK
2
D7 to D0
ACK
3
D7 to D0
ACK
SP
4
5
1: IICS = 1000×110B
2: IICS = 1000×000B (Sets WTIM to 1)
3: IICS = 1000×100B (Clears WTIM to 0)
4: IICS = 01000100B
5: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
(ii) When WTIM = 1
SPT = 1
↓
ST
AD6 to AD0 R/W ACK
D7 to D0
ACK
1
D7 to D0
2
ACK
D7 to D0
3
ACK
SP
4
1: IICS = 1000×110B
2: IICS = 1000×100B (Sets SPT to 1)
3: IICS = 01000100B
4: IICS = 00000001B
Remark
: Always generated
: Generated only when SPIE = 1
×:
Don’t care
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15.6 Timing Charts
When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several slave
devices as its communication partner.
After outputting the slave address, the master device transmits the TRC bit (bit 3 of the IICA status register (IICS)),
which specifies the data transfer direction, and then starts serial communication with the slave device.
Figures 15-32 and 15-33 show timing charts of the data communication.
The IICA shift register (IICA)’s shift operation is synchronized with the falling edge of the serial clock (SCL0). The
transmit data is transferred to the SO latch and is output (MSB first) via the SDA0 pin.
Data input via the SDA0 pin is captured into IICA at the rising edge of SCL0.
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Figure 15-32. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4)
(1) Start condition ~ address ~ data
Master side
Note 1
IICA
ACKD
(ACK detection)
WTIM
(8 or 9 clock wait)
H
ACKE
(ACK control)
H
MSTS
(communication status)
STT
(ST trigger)
SPT
(SP trigger)
WREL
(wait cancellation)
L
L
INTIICA
(interrupt)
TRC
(transmit/receive)
Start condition
Bus line
SCL0 (bus)
(clock line)
Note 2
SDA0 (bus)
(data line)
AD6
AD5
AD4
AD3
AD2
AD1
Slave address
AD0
W
D17
ACK
Slave side
IICA
ACKD
(ACK detection)
STD
(ST detection)
SPD
(SP detection)
WTIM
(8 or 9 clock wait)
H
ACKE
(ACK control)
H
MSTS
(communication status) L
WREL
(wait cancellation)
Note 3
INTIICA
(interrupt)
TRC
(transmit/receive)
L
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during master transmission.
2. Make sure that the time between the fall of the SDA0 pin signal and the fall of the SCL0 pin signal is at
least 4.0 μs when specifying standard mode and at least 0.6 μs when specifying fast mode.
3. To cancel slave wait, write “FFH” to IICA or set the WREL bit.
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The meanings of to in (1) Start condition ~ address ~ data in Figure 15-32 are explained below.
The start condition trigger is set by the master device (STT = 1) and a start condition (SDA0 = 0 and SCL0
= 1) is generated once the bus data line goes low (SDA0 = 0). When the start condition is subsequently
detected, the master device enters the master device communication status (MSTS = 1). The master
device is ready to communicate once the bus clock line goes low (SCL0 = 0) after the hold time has
elapsed.
The master device writes the address + W (transmission) to the IICA shift register (IICA) and transmits the
slave address.
If the address received matches the address of a slave deviceNote, that slave device sends an ACK by
hardware to the master device. The ACK is detected by the master device (ACKD = 1) at the rising edge of
the 9th clock.
The master device issues an interrupt (INTIICA: end of address transmission) at the falling edge of the 9th
clock, and the slave device whose address matched the transmitted slave address also issues an interrupt
(INTIICA: address match). The master device and slave device also set a wait status (SCL0 = 0)Note when
the addresses match.
The master device writes the data to transmit to the IICA register and releases the wait status that it set by
the master device.
If the slave device releases the wait status (WREL = 1), the master device starts transferring data to the
slave device.
Note If the transmitted address does not match the address of the slave device, the slave device does not return
an ACK to the master device (NACK: SDA0 = 1). The slave device also does not issue the INTIICA interrupt
(address match) and does not set a wait status. The master device, however, issues the INTIICA interrupt
(end of address transmission) regardless of whether it receives an ACK or NACK.
Remark to in Figure 15-32 represent the entire procedure for communicating data using the I2C bus.
Figure 15-32 (1) Start condition ~ address ~ data shows the processing from to , Figure 15-32
(2) Address ~ data ~ data shows the processing from to , and Figure 15-32 (3) Data ~ data ~
stop condition shows the processing from to .
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Figure 15-32. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/4)
(2) Address ~ data ~ data
Master side
IICA
Note 1
Note 1
ACKD
(ACK detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control)
H
H
MSTS
(communication status) H
STT
(ST trigger)
SPT
(SP trigger)
WREL
(wait cancellation)
L
L
L
INTIICA
(interrupt)
TRC
(transmit/receive)
H
Bus line
SCL0 (bus)
(clock line)
SDA0 (bus)
(data line)
W ACK
D 17
D16
D 15
D14
D 13
D12
D 11
D 27
D10 ACK
Slave side
IICA
ACKD
(ACK detection)
STD
(ST detection)
SPD
(SP detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control)
L
H
H
MSTS
(communication status) L
WREL
(wait cancellation)
Note 2
Note 2
INTIICA
(interrupt)
TRC
(transmit/receive)
L
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during master transmission.
2. To cancel slave wait, write “FFH” to IICA or set the WREL bit.
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The meanings of to in (2) Address ~ data ~ data in Figure 15-32 are explained below.
If the address received matches the address of a slave deviceNote, that slave device sends an ACK by
hardware to the master device. The ACK is detected by the master device (ACKD = 1) at the rising edge of
the 9th clock.
The master device issues an interrupt (INTIICA: end of address transmission) at the falling edge of the 9th
clock, and the slave device whose address matched the transmitted slave address also issues an interrupt
(INTIICA: address match). The master device and slave device also set a wait status (SCL0 = 0)Note when
the addresses match.
The master device writes the data to transmit to the IICA shift register (IICA) and releases the wait status
that it set by the master device.
If the slave device releases the wait status (WREL = 1), the master device starts transferring data to the
slave device.
When data transfer is complete, the slave device sends an ACK by hardware to the master device. The
ACK is detected by the master device (ACKD = 1) at the rising edge of the 9th clock.
The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
The master device writes the data to transmit to the IICA register and releases the wait status that it set by
the master device.
The slave device reads the received data and releases the wait status (WREL = 1). The master device then
starts transferring data to the slave device.
Note If the transmitted address does not match the address of the slave device, the slave device does not return
an ACK to the master device (NACK: SDA0 = 1). The slave device also does not issue the INTIICA interrupt
(address match) and does not set a wait status. The master device, however, issues the INTIICA interrupt
(end of address transmission) regardless of whether it receives an ACK or NACK.
Remark to in Figure 15-32 represent the entire procedure for communicating data using the I2C bus.
Figure 15-32 (1) Start condition ~ address ~ data shows the processing from to , Figure 15-32
(2) Address ~ data ~ data shows the processing from to , and Figure 15-32 (3) Data ~ data ~
stop condition shows the processing from to .
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Figure 15-32. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/4)
(3) Data ~ data ~ Stop condition
Master side
Note 1
IICA
ACKD
(ACK detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control)
H
H
MSTS
(communication status)
STT
(ST trigger)
L
SPT
(SP trigger)
WREL
(wait cancellation) L
INTIICA
(interrupt)
TRC
(transmit/receive)
Stop condition
Bus line
SCL0 (bus)
(clock line)
SDA0 (bus)
(data line)
D150 ACK
D167
D166
D165
D164
D163
D162
D161
D160 ACK
Slave side
Note 2
IICA
ACKD
(ACK detection)
STD
(ST detection)
L
SPD
(SP detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control)
H
H
MSTS
(communication status) L
WREL
(wait cancellation)
Note 3
Note 3
INTIICA
(interrupt)
TRC
(transmit/receive)
L
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during master transmission.
2. Make sure that the time between the rise of the SCL0 pin signal and the generation of the stop condition
after a stop condition has been issued is at least 4.0 μs when specifying standard mode and at least 0.6
μs when specifying fast mode.
3. To cancel slave wait, write “FFH” to IICA or set the WREL bit.
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The meanings of to in (3) Data ~ data ~ stop condition in Figure 15-32 are explained below.
When data transfer is complete, the slave device sends an ACK by hardware to the master device. The
ACK is detected by the master device (ACKD = 1) at the rising edge of the 9th clock.
The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
The master device writes the data to transmit to the IICA shift register (IICA) and releases the wait status
that it set by the master device.
The slave device reads the received data and releases the wait status (WREL = 1). The master device then
starts transferring data to the slave device.
When data transfer is complete, the slave device sends an ACK by hardware to the master device. The
ACK is detected by the master device (ACKD = 1) at the rising edge of the 9th clock.
The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
The slave device reads the received data and releases the wait status (WREL = 1).
After a stop condition trigger is set, the bus data line is cleared (SDA0 = 0) and the bus clock line is set
(SCL0 = 1). The stop condition is then generated by setting the bus data line (SDA0 = 1) after the stop
condition setup time has elapsed.
When a stop condition is generated, the slave device detects the stop condition and issues an interrupt
(INTIICA: stop condition).
Remark to in Figure 15-32 represent the entire procedure for communicating data using the I2C bus.
Figure 15-32 (1) Start condition ~ address ~ data shows the processing from to , Figure 15-32
(2) Address ~ data ~ data shows the processing from to , and Figure 15-32 (3) Data ~ data ~
stop condition shows the processing from to .
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Figure 15-32. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4)
(4) Data ~ restart condition ~ address
Master side
IICA
ACKD
(ACK detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control)
H
H
MSTS
(communication status) H
STT
(ST trigger)
SPT
(SP trigger)
L
WREL
(wait cancellation)
L
INTIICA
(interrupt)
TRC
(transmit/receive)
H
Bus line
Restart condition
SCL0 (bus)
(clock line)
SDA0 (bus)
(data line)
D13
D12
D11
D10 ACK
AD6
Note 1
Slave side
AD5
AD4
AD3
AD2
AD1
Slave address
IICA
ACKD
(ACK detection)
STD
(ST detection)
SPD
(SP detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control)
L
H
H
MSTS
(communication status) L
WREL
(wait cancellation)
Note 2
INTIICA
(interrupt)
TRC
(transmit/receive)
L
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Make sure that the time between the rise of the SCL0 pin signal and the generation of the start
condition after a restart condition has been issued is at least 4.7 μs when specifying standard mode and
at least 0.6 μs when specifying fast mode.
2. To cancel slave wait, write “FFH” to IICA or set the WREL bit.
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The following describes the operations in Figure 15-32 (4) Data ~ restart condition ~ address. After the operations
in steps and , the operations in steps to are performed. These steps return the processing to step
, the data transmission step.
When data transfer is complete, the slave device sends an ACK by hardware to the master device. The
ACK is detected by the master device (ACKD = 1) at the rising edge of the 9th clock.
The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
The slave device reads the received data and releases the wait status (WREL = 1).
The start condition trigger is set again by the master device (STT = 1) and a start condition (SDA0 = 0 and
SCL0 = 1) is generated once the bus clock line goes high (SCL0 = 1) and the bus data line goes low (SDA0
= 0) after the restart condition setup time has elapsed. When the start condition is subsequently detected,
the master device is ready to communicate once the bus clock line goes low (SCL0 = 0) after the hold time
has elapsed.
The master device writes the address + R/W (transmission) to the IICA shift register (IICA) and transmits
the slave address.
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Figure 15-33. Example of Slave to Master Communication
(When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3)
(1) Start condition ~ address ~ data
Master side
IICA
ACKD
(ACK detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control)
H
MSTS
(communication status)
STT
(ST trigger)
SPT
(SP trigger)
L
WREL
(wait cancellation)
Note 1
INTIICA
(interrupt)
TRC
(transmit/receive)
Start condition
Bus line
SCL0 (bus)
(clock line)
Note 2
SDA0 (bus)
(data line)
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Slave address
R
ACK
D17
Slave side
Note 3
IICA
ACKD
(ACK detection)
STD
(ST detection)
SPD
(SP detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control)
H
H
MSTS
(communication status) L
WREL
(wait cancellation)
L
INTIICA
(interrupt)
TRC
(transmit/receive)
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. To cancel master wait, write “FFH” to IICA or set the WREL bit.
2. Make sure that the time between the fall of the SDA0 pin signal and the fall of the SCL0 pin signal is at
least 4.0 μs when specifying standard mode and at least 0.6 μs when specifying fast mode.
3. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during slave transmission.
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The meanings of to in (1) Start condition ~ address ~ data in Figure 15-33 are explained below.
The start condition trigger is set by the master device (STT = 1) and a start condition (SDA0 = 0 and SCL0
= 1) is generated once the bus data line goes low (SDA0 = 0). When the start condition is subsequently
detected, the master device enters the master device communication status (MSTS = 1). The master
device is ready to communicate once the bus clock line goes low (SCL0 = 0) after the hold time has
elapsed.
The master device writes the address + W (transmission) to the IICA shift register (IICA) and transmits the
slave address.
If the address received matches the address of a slave deviceNote, that slave device sends an ACK by
hardware to the master device. The ACK is detected by the master device (ACKD = 1) at the rising edge of
the 9th clock.
The master device issues an interrupt (INTIICA: end of address transmission) at the falling edge of the 9th
clock, and the slave device whose address matched the transmitted slave address also issues an interrupt
(INTIICA: address match). The master device and slave device also set a wait status (SCL0 = 0)Note when
the addresses match.
The timing at which the master device sets the wait status changes to the 8th clock (WTIM = 0).
The slave device writes the data to transmit to the IICA register and releases the wait status that it set by
the slave device.
If the master device releases the wait status (WREL = 1), the slave device starts transferring data to the
master device.
Note If the transmitted address does not match the address of the slave device, the slave device does not return
an ACK to the master device (NACK: SDA0 = 1). The slave device also does not issue the INTIICA interrupt
(address match) and does not set a wait status. The master device, however, issues the INTIICA interrupt
(end of address transmission) regardless of whether it receives an ACK or NACK.
Remark to in Figure 15-33 represent the entire procedure for communicating data using the I2C bus.
Figure 15-33 (1) Start condition ~ address ~ data shows the processing from to , Figure 15-33
(2) Address ~ data ~ data shows the processing from to , and Figure 15-33 (3) Data ~ data ~
stop condition shows the processing from to .
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Figure 15-33. Example of Slave to Master Communication
(When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3)
(2) Address ~ data ~ data
Master side
IICA
ACKD
(ACK detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control)
H
MSTS
(communication status) H
STT
(ST trigger)
L
SPT
(SP trigger)
L
WREL
(wait cancellation)
Note 1
INTIICA
(interrupt)
TRC
(transmit/receive)
Note 1
L
Bus line
SCL0 (bus)
(clock line)
SDA0 (bus)
(data line)
D17
R ACK
D16
D15
D14
D13
D12
D11
D10
ACK
D27
Slave side
IICA
ACKD
(ACK detection)
Note 2
Note 2
STD
(ST detection)
SPD
(SP detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control)
L
H
H
MSTS
(communication status) L
WREL
(wait cancellation)
L
INTIICA
(interrupt)
TRC
(transmit/receive)
H
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. To cancel master wait, write “FFH” to IICA or set the WREL bit.
2. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during slave transmission.
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The meanings of to in (2) Address ~ data ~ data in Figure 15-33 are explained below.
If the address received matches the address of a slave deviceNote, that slave device sends an ACK by
hardware to the master device. The ACK is detected by the master device (ACKD = 1) at the rising edge of
the 9th clock.
The master device issues an interrupt (INTIICA: end of address transmission) at the falling edge of the 9th
clock, and the slave device whose address matched the transmitted slave address also issues an interrupt
(INTIICA: address match). The master device and slave device also set a wait status (SCL0 = 0)Note when
the addresses match.
The timing at which the master device sets the wait status changes to the 8th clock (WTIM = 0).
The slave device writes the data to transmit to the IICA shift register (IICA) and releases the wait status that
it set by the slave device.
If the master device releases the wait status (WREL = 1), the slave device starts transferring data to the
master device.
The master device sets a wait status (SCL0 = 0) at the falling edge of the 8th clock, and issues an interrupt
(INTIICA: end of transfer). The master device then sends an ACK by hardware to the slave device.
The master device reads the received data and releases the wait status (WREL = 1).
The ACK is detected by the slave device (ACKD = 1) at the rising edge of the 9th clock.
The slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and the slave device issue
an interrupt (INTIICA: end of transfer).
The slave device writes the data to transmit to the IICA register and releases the wait status that it set by
the slave device. The slave device then starts transferring data to the master device.
Note If the transmitted address does not match the address of the slave device, the slave device does not return
an ACK to the master device (NACK: SDA0 = 1). The slave device also does not issue the INTIICA interrupt
(address match) and does not set a wait status. The master device, however, issues the INTIICA interrupt
(end of address transmission) regardless of whether it receives an ACK or NACK.
Remark to in Figure 15-33 represent the entire procedure for communicating data using the I2C bus.
Figure 15-33 (1) Start condition ~ address ~ data shows the processing from to , Figure 15-33
(2) Address ~ data ~ data shows the processing from to , and Figure 15-33 (3) Data ~ data ~
stop condition shows the processing from to .
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Figure 15-33. Example of Slave to Master Communication
(When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3)
(3) Data ~ data ~ stop condition
Master side
IICA
ACKD
(ACK detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control)
MSTS
(communication status)
STT
(ST trigger)
L
SPT
(SP trigger)
WREL
(wait cancellation)
INTIICA
(interrupt)
TRC
(transmit/receive)
Note 1
Note 1
L
Bus line
Stop conditon
SCL0 (bus)
(clock line)
SDA0 (bus)
(data line)
D150
ACK
D167
D166
D165
D164
D163
D162
D161
D160
Note 2
NACK
Slave side
IICA
Note 3
ACKD
(ACK detection)
STD
(ST detection)
L
SPD
(SP detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control)
H
H
MSTS
(communication
status)
WREL
(wait cancellation)
L
Notes 1, 4
INTIICA
(interrupt)
TRC
(transmit/receive)
Note 4
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. To cancel a wait state, write “FFH” to IICA or set the WREL bit.
2. Make sure that the time between the rise of the SCL0 pin signal and the generation of the stop condition
after a stop condition has been issued is at least 4.0 μs when specifying standard mode and at least 0.6
μs when specifying fast mode.
3. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during slave transmission.
4. If a wait state during slave transmission is canceled by setting the WREL bit, the TRC bit will be cleared.
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The meanings of to in (3) Data ~ data ~ stop condition in Figure 15-33 are explained below.
The master device sets a wait status (SCL0 = 0) at the falling edge of the 8th clock, and issues an interrupt
(INTIICA: end of transfer). The master device then sends an ACK by hardware to the slave device.
The master device reads the received data and releases the wait status (WREL = 1).
The ACK is detected by the slave device (ACKD = 1) at the rising edge of the 9th clock.
The slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and the slave device issue
an interrupt (INTIICA: end of transfer).
The slave device writes the data to transmit to the IICA shift register (IICA) and releases the wait status that
it set by the slave device. The slave device then starts transferring data to the master device.
The master device issues an interrupt (INTIICA: end of transfer) at the falling edge of the 8th clock, and
sets a wait status (SCL0 = 0). Because ACK control (ACKE = 1) is performed, the bus data line is at the
low level (SDA0 = 0) at this stage.
The master device sets NACK as the response (ACKE = 0) and changes the timing at which it sets the wait
status to the 9th clock.
If the master device releases the wait status (WREL = 1), the slave device detects the NACK (ACK = 0) at
the rising edge of the 9th clock.
The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
When the master device issues a stop condition (SPT = 1), the bus data line is cleared (SDA0 = 0) and the
master device releases the wait status. The master device then waits until the bus clock line is set (SCL0 =
1).
The slave device acknowledges the NACK, halts transmission, and releases the wait status (WREL = 1) to
end communication. Once the slave device releases the wait status, the bus clock line is set (SCL0 = 1).
Once the master device recognizes that the bus clock line is set (SCL0 = 1) and after the stop condition
setup time has elapsed, the master device sets the bus data line (SDA0 = 1) and issues a stop condition.
The slave device detects the generated stop condition and both the master device and slave device issue
an interrupt (INTIICA: stop condition).
Remark to in Figure 15-33 represent the entire procedure for communicating data using the I2C bus.
Figure 15-33 (1) Start condition ~ address ~ data shows the processing from to , Figure 15-33
(2) Address ~ data ~ data shows the processing from to , and Figure 15-33 (3) Data ~ data ~
stop condition shows the processing from to .
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CHAPTER 16 LCD CONTROLLER/DRIVER
Item
78K0R/LF3
78K0R/LG3
78K0R/LH3
80 pins
100 pins
128 pins
LCD
Segment signal outputs: 31
Segment signal outputs: 40
Segment signal outputs: 54
Controller/driver
Common signal outputs: 8
Common signal outputs: 8
Common signal outputs: 8
16.1 Functions of LCD Controller/Driver
The functions of the LCD controller/driver in the 78K0R/Lx3 microcontrollers are as follows.
(1)
The LCD driver voltage generator can switch internal voltage boosting method, capacitor split method, and
(2)
Automatic output of segment and common signals based on automatic display data memory read
(3)
Six different display modes:
external resistance division method.
• Static
• 1/2 duty (1/2 bias)
• 1/3 duty (1/2 bias)
• 1/3 duty (1/3 bias)
• 1/4 duty (1/3 bias)
• 1/8 duty (1/4 bias)
(4)
Six different frame frequencies, selectable in each display mode
(5)
The reference voltage to be generated when operating the voltage boost circuit can be selected from 20 stages
(contrast adjustment).
(6)
The data display of the LCD display data memory can be selected from three types.
• Displaying an A-pattern area (lower four bits)
• Displaying a B-pattern area (higher four bits)
• Alternately displaying A-pattern and B-pattern areas (blinking display corresponding to the constant-period
interrupt (INTRTC) timing of the real-time counter (RTC))
(7)
78K0R/LF3:
Segment signal outputs: 31Note (SEG0 to SEG30),
Common signal outputs: 8 Note (COM0 to COM7)
78K0R/LG3:
Segment signal outputs: 40Note (SEG0 to SEG39),
Common signal outputs: 8 Note (COM0 to COM7)
78K0R/LH3:
Segment signal outputs: 54Note (SEG0 to SEG53),
Common signal outputs: 8 Note (COM0 to COM7)
Note The four segment signal outputs (SEG0 to SEG3) and four common signal outputs (COM4 to COM7) are
alternate-function pins. COM4 to COM7 can be used only when eight-time-slice mode is selected by the setting
of the LCD display mode register (LCDM).
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Table 16-1 lists the maximum number of pixels that can be displayed in each display mode.
Table 16-1. Maximum Number of Pixels (1/3)
(a) 78K0R/LF3
LCD Driver Voltage
Bias
Number of
Generator
Mode
Time Slices
−
External resistance
Static
Common Signals Used
Number of
Maximum Number of Pixels
Segments
COM0 (COM1 to COM3)
31
31 (31 segment signals,
Note 1
1 common signal)
division
1/2
2
COM0, COM1
62 (31 segment signals,
2 common signals)
1/3
3
COM0 to COM2
3
COM0 to COM2
4
COM0 to COM3
93 (31 segment signals,
3 common signals)
8
COM0 to COM7
27
1/3
3
COM0 to COM2
31
boosting
Note 5
93 (31 segment signals,
3 common signals)
4
COM0 to COM3
1/4
8
COM0 to COM7
27
3
COM0 to COM2
31
Note 4
216 (27 segment signals, 8
common signals)
1/3
Note 5
93 (31 segment signals,
3 common signals)
4
COM0 to COM3
2. 7-digit LCD panel, each digit having a 4-segment
Note 4
configuration.
configuration.
3. 11-digit LCD panel, each digit having a 3-segment
configuration.
4. 15-digit LCD panel, each digit having a 2-segment
configuration.
5. 27-digit LCD panel, each digit having a 1-segment
configuration.
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Note3
124 (31 segment signals, 4
common signals)
Notes 1. 3-digit LCD panel, each digit having an 8-segment
Note
124 (31 segment signals, 4
common signals)
Capacitor Split
Note 4
216 (27 segment signals, 8
common signals)
Internal voltage
Note 3
124 (31 segment signals, 4
common signals)
1/4
Note 2
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CHAPTER 16 LCD CONTROLLER/DRIVER
Table 16-1. Maximum Number of Pixels (2/3)
(b) 78K0R/LG3
LCD Driver Voltage
Bias
Number of
Generator
Mode
Time Slices
−
External resistance
Static
Common Signals Used
Number of
Maximum Number of Pixels
Segments
COM0 (COM1 to COM3)
40
40 (40 segment signals,
Note 1
1 common signal)
division
1/2
2
COM0, COM1
80 (40 segment signals,
2 common signals)
1/3
3
COM0 to COM2
3
COM0 to COM2
4
COM0 to COM3
120 (40 segment signals,
3 common signals)
8
COM0 to COM7
36
1/3
3
COM0 to COM2
40
boosting
Note 5
120 (40 segment signals,
3 common signals)
4
COM0 to COM3
1/4
8
COM0 to COM7
36
3
COM0 to COM2
40
Note 4
288 (36 segment signals, 8
common signals)
1/3
Note 5
120 (40 segment signals,
3 common signals)
4
COM0 to COM3
Note
160 (40 segment signals, 4
common signals)
Notes 1. 5-digit LCD panel, each digit having an 8-segment
configuration.
2. 10-digit LCD panel, each digit having a 4-segment
configuration.
3. 15-digit LCD panel, each digit having a 3-segment
configuration.
4. 20-digit LCD panel, each digit having a 2-segment
configuration.
5. 36-digit LCD panel, each digit having a 1-segment
configuration.
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Note3
160 (40 segment signals, 4
common signals)
capacitor split
Note 4
288 (36 segment signals, 8
common signals)
Internal voltage
Note 3
160 (40 segment signals, 4
common signals)
1/4
Note 2
Note 4
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CHAPTER 16 LCD CONTROLLER/DRIVER
Table 16-1. Maximum Number of Pixels (3/3)
(b) 78K0R/LG3
LCD Driver Voltage
Bias
Number of
Generator
Mode
Time Slices
−
External resistance
Static
Common Signals Used
Number of
Maximum Number of Pixels
Segments
COM0 (COM1 to COM3)
54
54 (54 segment signals,
Note 1
1 common signal)
division
1/2
2
COM0, COM1
108 (54 segment signals,
2 common signals)
1/3
3
COM0 to COM2
3
COM0 to COM2
4
COM0 to COM3
162 (54 segment signals,
3 common signals)
8
COM0 to COM7
50
1/3
3
COM0 to COM2
54
boosting
Note 5
162 (54 segment signals,
3 common signals)
4
COM0 to COM3
1/4
8
COM0 to COM7
50
3
COM0 to COM2
54
Note 4
400 (50 segment signals, 8
common signals)
1/3
Note 5
162 (54 segment signals,
3 common signals)
4
COM0 to COM3
Note
216 (54 segment signals, 4
common signals)
Notes 1. 6-digit LCD panel, each digit having an 8-segment
configuration.
2. 13-digit LCD panel, each digit having a 4-segment
configuration.
3. 20-digit LCD panel, each digit having a 3-segment
configuration.
4. 27-digit LCD panel, each digit having a 2-segment
configuration.
5. 50-digit LCD panel, each digit having a 1-segment
configuration.
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Note3
216 (54 segment signals, 4
common signals)
Capacitor Split
Note 4
400 (50 segment signals, 8
common signals)
Internal voltage
Note 3
216 (54 segment signals, 4
common signals)
1/4
Note 2
Note 4
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CHAPTER 16 LCD CONTROLLER/DRIVER
16.2 Configuration of LCD Controller/Driver
The LCD controller/driver consists of the following hardware.
Table 16-2. Configuration of LCD Controller/Driver
Item
Display outputs
Configuration
78K0R/LF3: 31 segment signals
Note
(SEG0 to SEG39), 8 common signals
Note
(SEG0 to SEG53), 8 common signals
78K0R/LG3: 40 segment signals
78K0R/LH3: 54 segment signals
Control registers
Note
(SEG0 to SEG30), 8 common signals
Note
(COM0 to COM7)
Note
(COM0 to COM7)
Note
(COM0 to COM7)
LCD mode register (LCDMD)
LCD display mode register (LCDM)
LCD clock control register 0 (LCDC0)
LCD boost level control register (VLCD)
Port function register (PFALL)
Segment enable register (SEGEN)
Input switch control register (ISC)
Note The four segment signal outputs (SEG0 to SEG3) and four common signal outputs (COM4 to COM7) are
alternate-function pins. COM4 to COM7 can be used only when eight-time-slice mode is selected by the setting
of the LCD display mode register (LCDM).
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Internal bus
LCD display mode
register (LCDM)
LCD clock control
register 0 (LCDC0)
LCD mode register
(LCDMD)
MDSET1 MDSET0
LCD boost level control
register (VLCD)
LCDC5 LCDC4 LCDC2 LCDC1 LCDC0 LCDON SCOC VLCON BLON LCDSEL LCDM2 LCDM1 LCDM0
fSUB
fCLK/26
fCLK/27
fCLK/28
2
3
2
2
Selector
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Figure 16-1. Block Diagram of LCD Controller/Driver
fLCD
VLCD4 VLCD3 VLCD2 VLCD1 VLCD0
3
Display data memory
00H
76543210
03H
76543210
04H
76543210
35H
76543210
5
Prescaler
fLCD
24
Clock genarator
for
capacitor split
Clock genarator
for voltage boost
Capacitor split
circuit
Voltage boost
circuit
fLCD
25
fLCD
26
fLCD
27
fLCD
28
fLCD
29
LCD LCDCL
clock
selector
Timing
controller
76543210
selector
VLCON
INTRTC
LCDON
76543210
selector
76543210
selector
LCDON
LCDON
Segment voltage
controller
LCD drive voltage controller
VLC2 VLC1 VLC0
Common voltage
controller
Segment
driver
Common driver
COM0
COM3 COM4/
SEG0
COM7/
SEG3
Remark 78K0R/LF3: 31 segment signals (SEG0 to SEG30), 8 common signals (COM0 to COM7)
78K0R/LG3: 40 segment signals (SEG0 to SEG39), 8 common signals (COM0 to COM7)
78K0R/LH3: 54 segment signals (SEG0 to SEG53), 8 common signals (COM0 to COM7)
Segment
driver
Segment
driver
Segment
driver
SEG4
SEG53
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CHAPTER 16 LCD CONTROLLER/DRIVER
CAPH CAPL
76543210
selector
LCDON
78K0R/Lx3
CHAPTER 16 LCD CONTROLLER/DRIVER
16.3 Registers Controlling LCD Controller/Driver
The following seven registers are used to control the LCD controller/driver.
• LCD mode register (LCDMD)
• LCD display mode register (LCDM)
• LCD clock control register 0 (LCDC0)
• LCD boost level control register (VLCD)
• Port function register (PFALL)
• Segment enable register (SEGEN)
• Input switch control register (ISC)
(1)
LCD mode register (LCDMD)
LCDMD sets the LCD drive voltage generator.
LCDMD is set using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets LCDMD to 00H.
Figure 16-2. Format of LCD Mode Register (LCDMD)
Address: FFF40H
After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
LCDMD
0
0
MDSET1
MDSET0
0
0
0
0
MDSET1
MDSET0
0
0
External resistance division method
0
1
Internal voltage boosting method
1
0
Capacitor split method
1
1
Setting prohibited
LCD drive voltage generator selection
Caution Bits 0 to 3, 6 and 7 must be set to 0.
(2)
LCD display mode register (LCDM)
LCDM is a register that enables/disables display operation, enables/disables voltage boost circuit or capacitor
split circuit operation, and sets the display data area and the display mode.
LCDM is set using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets LCDM to 00H.
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Figure 16-3. Format of LCD Display Mode Register (LCDM)
Address: FFF41H
After reset: 00H
R/W
Symbol
2
1
0
LCDM
LCDON
SCOC
VLCON
BLON
LCDSEL
LCDM2
LCDM1
LCDM0
LCDON
SCOC
0
0
Output ground level to segment/common pin
0
1
Display off (all segment outputs are deselected.)
1
0
Output ground level to segment/common pin
1
1
Display on
VLCON
LCD display enable/disable
Voltage boost circuit or capacitor split circuit operation enable/disable
0
Stops voltage boost circuit or capacitor split circuit operation
1
Enables voltage boost circuit or capacitor split circuit operation
BLON
LCDSEL
Display data area control
0
0
Displaying an A-pattern area data (lower four bits of LCD display data memory)
0
1
Displaying a B-pattern area data (higher four bits of LCD display data memory)
1
0
Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to
1
1
the constant-period interrupt (INTRTC) timing of the real-time counter (RTC))
LCDM2
LCDM1
LCDM0
LCD controller/driver display mode selection
External resistance
Internal voltage
division method
boosting method
Capacitor split method
Number of Bias mode Number of Bias mode Number of Bias mode
time slices
time slices
time slices
0
0
0
4
1/3
4
1/3
4
1/3
0
0
1
3
1/3
3
1/3
3
1/3
0
1
0
2
1/2
4
1/3
4
1/3
0
1
1
3
1/2
4
1/3
4
1/3
1
0
0
Static
1
1
1
8
4
1/3
Other than above
Setting prohibited
1/4
8
1/4
Setting prohibited
Cautions 1. When LCD display is not performed or necessary, set SCOC and VLCON to 0, in order to reduce
power consumption.
2. When the external resistance division method has been set (MDSET1 = MDSET0 = 0), do not set
VLCON to 1.
3. Set BLON and LCDSEL to 0 when 8 has been selected as the number of time slices for the
display mode.
4. To use the internal voltage boosting method, specify the reference voltage by using the VLCD
register (or perform a reset to use the default value of the reference voltage), wait for the
reference voltage setup time (2 ms (min.)), and then set VLCON to 1.
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Caution
5. To manipulate VLCON when using the internal voltage boosting method or capacitor split
method, follow the procedure below.
A. To stop the operation of the voltage boosting/capacitor split circuit after switching display
status from on to off:
1) Set to display off status by setting LCDON = 0.
2) Disable outputs of all the segment buffers and common buffers by setting SCOC = 0.
3) Stop the operation of the voltage boosting/capacitor split circuit by setting VLCON = 0.
B. To stop the operation of the voltage boosting/capacitor split circuit during display on status:
Setting prohibited. Be sure to stop the operation of the voltage boosting/capacitor split
circuit after setting display off.
C. To set display on from stop status of the voltage boosting/capacitor split circuit:
1) Start the operation of the voltage boosting/capacitor split circuit by setting VLCON = 1,
then wait for the voltage boosting/capacitor split wait time (see CHAPTER 31
ELECTRICAL SPECIFICATIONS).
2) Set all the segment buffers and common buffers to non-display output status by setting
SCOC = 1.
3) Set display on by setting LCDON = 1.
(3)
LCD clock control register (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock.
The frame frequency is determined according to the LCD clock and the number of time slices.
LCDC0 is set using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDC0 to 00H.
Figure 16-4. Format of LCD Clock Control Register (LCDC0)
Address: FFF42H
After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
LCDC0
0
0
LCDC5
LCDC4
0
LCDC2
LCDC1
LCDC0
LCDC5
LCDC4
0
0
fSUB
0
1
fCLK/26
1
0
fCLK/27
1
1
fCLK/28
LCDC2
LCDC1
LCD source clock (fLCD) selection
LCDC0
LCD clock (LCDCL) selection
4
0
0
0
fLCD/2
0
0
1
fLCD/25
0
1
0
fLCD/26
0
1
1
fLCD/27
1
0
0
fLCD/28
1
0
1
fLCD/29
Other than above
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Cautions 1. Bits 3, 6, and 7 must be set to 0.
2. Set the LCD clock (LCDCL) to no more than 512 Hz when the internal voltage boost method has
been set.
Remark
(4)
fCLK:
CPU/Peripheral hardware clock frequency
fSUB:
Subsystem clock frequency
LCD boost level control register (VLCD)
This register is used to select the reference voltage that is to be generated when operating the voltage boost
circuit (contrast adjustment). The reference voltage can be selected from 20 stages.
VLCD is set using an 8-bit memory manipulation instruction.
Reset signal generation sets VLCD to 0FH.
Figure 16-5. Format of LCD Boost Level Control Register (VLCD)
Address: FFF43H
After reset: 0FH
R/W
Symbol
7
6
5
4
3
2
1
0
VLCD
0
0
0
VLCD4
VLCD3
VLCD2
VLCD1
VLCD0
VLCD4
VLCD3
VLCD2
VLCD1
VLCD0
Reference voltage
selection
VLC0 voltage
1/3 bias
1/4 bias
(contrast adjustment)
0
0
0
0
0
1.75 V
5.25 V
Setting
0
0
0
0
1
1.70 V
5.10 V
prohibited
0
0
0
1
0
1.65 V
4.95 V
0
0
0
1
1
1.60 V
4.80 V
0
0
1
0
0
1.55 V
4.65 V
0
0
1
0
1
1.50 V
4.50 V
0
0
1
1
0
1.45 V
4.35 V
0
0
1
1
1
1.40 V
4.20 V
0
1
0
0
0
1.35 V
4.05 V
0
1
0
0
1
1.30 V
3.90 V
5.20 V
0
1
0
1
0
1.25 V
3.75 V
5.00 V
0
1
0
1
1
1.20 V
3.60 V
4.80 V
0
1
1
0
0
1.15 V
3.45 V
4.60 V
0
1
1
0
1
1.10 V
3.30 V
4.40 V
0
1
1
1
0
1.05 V
3.15 V
4.20 V
0
1
1
1
1
1.00 V
3.00 V
4.00 V
Note
(default)
1
0
0
0
0
0.95 V
2.85 V
3.80 V
1
0
0
0
1
0.90 V
2.70 V
3.60 V
1
0
0
1
0
0.85 V
2.55 V
3.40 V
1
0
0
1
1
0.80 V
2.40 V
3.20 V
Other than above
Setting prohibited
Note These settings are prohibited because VLC0 > 5.5 V.
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Cautions 1. The VLCD setting is valid only when the voltage boost circuit is operating.
2. Bits 5 to 7 must be set to 0.
3. Be sure to change the VLCD value after having stopped the operation of the voltage boost circuit
(VLCON = 0).
4. These values above may change after device evaluation.
5. To use the internal voltage boosting method, specify the reference voltage by using the VLCD
register (or perform a reset to use the default value of the reference voltage), wait for the reference
voltage setup time (2 ms (min.)), and then set VLCON to 1.
(5)
Port function register (PFALL)
This register sets whether to use pins P50 to P57, P90 to P97, P100 to P102, and P140 to P147 as port pins
(other than segment output pins) or segment output pins.
PFALL is set using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PFALL to 00H.
Remark The port pins to be used alternatively with the segment output pins vary, depending on the product.
• 78K0R/LF3:
P50 to P57, P90 to P92, P100, P140 to P147
• 78K0R/LG3:
P50 to P57, P90 to P97, P100, P140 to P147
• 78K0R/LH3:
P50 to P57, P90 to P97, P100 to P102, P140 to P147
Figure 16-6. Format of Port Function Register (PFALL) (1/2)
Address: F0080H
Symbol
7
PFALL
0
After reset: 00H
6
PF14H
R/W
5
4
PF14L
PF10
PF14H
3
Note
PF9H
2
1
0
PF9L
PF5H
PF5L
Port/segment outputs specification of the P144 to P147 pins
0
Used the P144 to P147 pins as port (other than segment output)
1
Used the P144 to P147 pins as segment output
PF14L
Port/segment outputs specification of the P140 to P143 pins
0
Used the P140 to P143 pins as port (other than segment output)
1
Used the P140 to P143 pins as segment output
PF10
Port/segment outputs specification of the P100 to P102 pins
0
Used the P100 to P102 pins as port (other than segment output)
1
Used the P100 to P102 pins as segment output
PF9H
Port/segment outputs specification of the P94 to P97 pins
0
Used the P94 to P97 pins as port (other than segment output)
1
Used the P94 to P97 pins as segment output
PF9L
Port/segment outputs specification of P90 to P93 pins
0
Used the P90 to P93 pins as port (other than segment output)
1
Used the P90 to P93 pins as segment output
Note 78K0R/LG3, 78K0R/LH3 only
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Figure 16-6. Format of Port Function Register (PFALL) (2/2)
PF5H
Port/segment outputs specification of the P54 to P57 pins
0
Used the P54 to P57 pins as port (other than segment output)
1
Used the P54 to P57 pins as segment output
PF5L
Caution
(6)
Port/segment outputs specification of P50 to P53 pins
0
Used the P50 to P53 pins as port (other than segment output)
1
Used the P50 to P53 pins as segment output
For 78K0R/LF3, bits 3 and 7 must be set to 0. For 78K0R/LG3 and 78K0R/LH3, bit 7 must be set to 0.
Segment enable register (SEGEN)
SEGEN is a register that is used to enable or disable segment output to segment output only pins.
SEGEN is set using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets SEGEN to 00H.
Remark The segment output only pins vary, depending on the product.
• 78K0R/LF3: SEG8 to SEG10
• 78K0R/LG3: SEG8 to SEG14
• 78K0R/LH3: SEG8 to SEG26
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Figure 16-7. Format of Segment Enable Register (SEGEN)
• 78K0R/LF3
Address: F0081H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
SEGEN
0
0
0
0
0
0
0
SEGEN0
• 78K0R/LG3
Address: F0081H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
SEGEN
0
0
0
0
0
0
SEGEN1
SEGEN0
• 78K0R/LH3
Address: F0081H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
SEGEN
0
0
0
SEGEN4
SEGEN3
SEGEN2
SEGEN1
SEGEN0
SEGENn
Output enable/disable to segment output only pins (n = 0 to 4)
0
Disables segment output
1
Enables segment output
Cautions 1. SEGEN can be written only once after reset release.
2. For 78K0R/LF3, bits 1 to 7 must be set to 0. For 78K0R/LG3, bits 2 to 7 must be set to 0. For
78K0R/LH3, bits 5 to 7 must be set to 0.
The segment output only pins operated by SEGEN4 to SEGEN0 are as follows.
SEGEN register
Segment output only pins
78K0R/LF3
78K0R/LG3
SEGE4
−
−
SEG24 to SEG26 pins
SEGE3
−
−
SEG20 to SEG23 pins
SEGE2
−
−
SEG16 to SEG19 pins
SEGE1
−
SEGE0
SEG8 to SEG10 pins
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SEG12 to SEG14 pins
SEG12 to SEG15 pins
SEG8 to SEG11 pins
SEG8 to SEG11 pins
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(7)
CHAPTER 16 LCD CONTROLLER/DRIVER
Input switch control register (ISC)
The segment output pins to be used alternatively with the TI04, TI02, and RxD3 pins are internally connected with
a Schmitt trigger buffer. To use these pins as segment outputs, input to the Schmitt trigger buffer must be
disabled, in order to prevent through-currents from entering.
ISC is set using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets ISC to 00H.
Remark
The segment output pins to be used alternatively with the TI02, TI04, and RxD3 pins vary, depending
on the product.
• 78K0R/LF3:
TI04/SEG27/P53, TI02/SEG28/P52, RxD3/SEG30/P50
• 78K0R/LG3:
TI04/SEG36/P53, TI02/SEG37/P52, RxD3/SEG39/P50
• 78K0R/LH3:
TI04/SEG50/P53, TI02/SEG51/P52, RxD3/SEG53/P50
Figure 16-8. Format of Input Switch Control Register (ISC)
Address: FFF3CH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ISC
0
0
0
ISC4
ISC3
ISC2
ISC1
ISC0
TI04/SEGxx/P53 schmitt trigger buffer control
ISC4
0
Disables input
1
Enables input
TI02/SEGxx/P52 schmitt trigger buffer control
ISC3
0
Disables input
1
Enables input
RxD3/SEGxx/P50 schmitt trigger buffer control
ISC2
0
Disables input
1
Enables input
Caution Be sure to clear bits 5 to 7 to “0”.
Remark
Bits 0 and 1 of ISC are not used with the LCD controller driver.
To use the TI04/SEGxx/P53, TI02/SEGxx/P52, and RxD3/SEGxx/P50 pins, set the PF5L and ISCn (n = 2 to 4)
bits as follows, according to the function to be used.
PF5L
ISCn
Pin function
0
0
Port output (default)
0
1
Port input, timer input, or serial data input
1
0
Segment output
1
1
Setting prohibited
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16.4 LCD Display Data Memory
The LCD display data memory is mapped at addresses F0400H to F041FH (78K0R/LF3), F0400H to F0427H
(78K0R/LG3) or F0400H to F0435H (78K0R/LH3). Data in the LCD display data memory can be displayed on the LCD
panel using the LCD controller/driver.
Figure 16-9 to 16-11 show the relationship between the contents of the LCD display data memory and the
segment/common outputs.
The areas not to be used for display can be used as normal RAM.
Figure 16-9. Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs
(78K0R/LF3)
(a) Static, 2-time-slice, 3-time-slice, and 4-time-slice
B-pattern area
b7
b6
b5
A-pattern area
b4
b3
b2
b1
b0
F041EH
F041DH
F041CH
SEG30
SEG29
SEG28
F0405H
F0404H
F0403H
F0402H
F0401H
F0400H
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
COM3
COM2
COM1
COM0
b2
b1
b0
(b) 8-time-slice
b7
b6
b5
b4
b3
F041EH
F041DH
F041CH
SEG30
SEG29
SEG28
F0405H
F0404H
F0403H
F0402H
F0401H
F0400H
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
Note The COM4 to COM7 pins and SEG0 to SEG3 pins are used alternatively. To use the LCD display data memory
when the number of time slices is eight, the area of F0400H to F0403H can be used for a purpose other than
display, because it is not used for LCD display.
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Figure 16-10. Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs
(78K0R/LG3)
(a) Static, 2-time-slice, 3-time-slice, and 4-time-slice
B-pattern area
b7
b6
b5
A-pattern area
b4
b3
b2
b1
b0
F0427H
F0426H
F0425H
SEG39
SEG38
SEG37
F0405H
F0404H
F0403H
F0402H
F0401H
F0400H
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
COM3
COM2
COM1
COM0
b2
b1
b0
(b) 8-time-slice
b7
b6
b5
b4
b3
F0427H
F0426H
F0425H
SEG39
SEG38
SEG37
F0405H
F0404H
F0403H
F0402H
F0401H
F0400H
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
Note The COM4 to COM7 pins and SEG0 to SEG3 pins are used alternatively. To use the LCD display data memory
when the number of time slices is eight, the area of F0400H to F0403H can be used for a purpose other than
display, because it is not used for LCD display.
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Figure 16-11. Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs
(78K0R/LH3)
(a) Static, 2-time-slice, 3-time-slice, and 4-time-slice
B-pattern area
b7
b6
b5
A-pattern area
b4
b3
b2
b1
b0
F0435H
F0434H
F0433H
SEG53
SEG52
SEG51
F0405H
F0404H
F0403H
F0402H
F0401H
F0400H
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
COM3
COM2
COM1
COM0
b2
b1
b0
(b) 8-time-slice
b7
b6
b5
b4
b3
F0435H
F0434H
F0433H
SEG53
SEG52
SEG51
F0405H
F0404H
F0403H
F0402H
F0401H
F0400H
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
Note The COM4 to COM7 pins and SEG0 to SEG3 pins are used alternatively. To use the LCD display data memory
when the number of time slices is eight, the area of F0400H to F0403H can be used for a purpose other than
display, because it is not used for LCD display.
To use the LCD display data memory when the number of time slices is static, two, three, or four, the lower four bits
and higher four bits of each address of the LCD display data memory become an A-pattern area and a B-pattern area,
respectively.
The correspondences between A-pattern area data and COM signals are as follows: bit 0 ⇔ COM0, bit 1 ⇔ COM1,
bit 2 ⇔ COM2, and bit 3 ⇔ COM3.
The correspondences between B-pattern area data and COM signals are as follows: bit 4 ⇔ COM0, bit 5 ⇔ COM1,
bit 6 ⇔ COM2, and bit 7 ⇔ COM3.
A-pattern area data will be displayed on the LCD panel when BLON = LCDSEL = 0 has been selected, and B-pattern
area data will be displayed on the LCD panel when BLON = 0 and LCDSEL = 1 have been selected.
When BLON = 1 has been selected, A-pattern and B-pattern areas will be alternately displayed, according to the
constant-period interrupt (INTRTC) timing of the real-time counter (RTC).
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Figure 16-12. Example of Display Data When Blinking Display Has Been Selected
When selecting blinking display (BLON = 1),
A-pattern and B-pattern areas are alternately displayed.
B-pattern area
b7
b6
A-pattern area
b5
b4
b3
b2
b1
b0
F0405H
F0404H
F0403H
F0402H
F0401H
F0400H
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
COM3
COM2
COM1
COM0
16.5 Setting LCD Controller/Driver
Set the LCD controller/driver using the following procedure.
(1) External resistance division method
Set the external resistance division method via the MDSET0 and MDSET1 bits (bits 4 and 5 of the LCDMD
register) (MDSET0 = MDSET1 = 0).
To use segment output only pins, use the SEGEN register to enable segment output to them.
To use segment output pins, which are alternatively used with port pins, use the PFALL register to set them
to segment output. In addition, to use the segment output pins, which are alternatively used with the TI04,
TI02, and RxD3 pins, use the ISC register to disable input to the Schmitt trigger buffer.
Set the display data in LCD display RAM.
Set the number of time slices and the bias mode via the LCDM0 to LCDM2 bits (bits 0 to 2 of the LCDM
register).
• When setting Static, 2-time-slice, 3-time-slice, or 4-time-slice → Go to step
• When setting 8-time-slice → Go to step
Select the display data area via the LCDSEL and BLON bits (bits 3 and 4 of the LCDM register).
Set the LCD source clock and LCD clock via the LCDC0 register.
Set (SCOC = 1) the SCOC bit (bit 6 of the LCDM register).
Non-selected waveforms are output from all the segment and common pins, and the non-display status is
entered.
Start output corresponding to each data memory by setting (LCDON = 1) the LCDON bit (bit 7 of the LCDM
register).
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(2) Internal voltage boosting method
Set the internal voltage boosting method via the MDSET0 and MDSET1 bits (bits 4 and 5 of the LCDMD
register) (MDSET0 = 1, MDSET1 = 0).
To use segment output only pins, use the SEGEN register to enable segment output to them.
To use segment output pins, which are alternatively used with port pins, use the PFALL register to set them
to segment output. In addition, to use the segment output pins, which are alternatively used with the TI04,
TI02, and RxD3 pins, use the ISC register to disable input to the Schmitt trigger buffer.
Set the display data in LCD display RAM.
Set the number of time slices and the bias mode via the LCDM0 to LCDM2 bits (bits 0 to 2 of the LCDM
register).
• When setting Static, 2-time-slice, 3-time-slice, or 4-time-slice → Go to step
• When setting 8-time-slice → Go to step
(Only 1/3 bias mode and 1/4 bias mode can be set for the internal voltage boost method.)
Select the display data area via the LCDSEL and BLON bits (bits 3 and 4 of the LCDM register).
Set the LCD source clock and LCD clock via the LCDC0 register.
Set the reference voltage (adjust the contrast) via the VLCD register.
Wait for the reference voltage setup time (2 ms (min.)) after setting of the VLCD register.
Set (VLCON = 1) the VLCON bit (bit 5 of the LCDM register) to start the voltage boost circuit operation.
Wait for the voltage boost wait time after setting of VLCON (see CHAPTER 31 ELECTRICAL
SPECIFICATIONS).
Set (SCOC = 1) the SCOC bit (bit 6 of the LCDM register).
Non-selected waveforms are output from all the segment and common pins, and the non-display status is
entered.
Start output corresponding to each data memory by setting (LCDON = 1) the LCDON bit (bit 7 of the LCDM
register).
Caution
When stopping the operation of the voltage boost circuit, be sure to set SCOC and LCDON to 0
before setting VLCON to 0.
(3) Capacitor split method
Set the capacitor split method via the MDSET0 and MDSET1 bits (bits 4 and 5 of the LCDMD register)
(MDSET0 = 0, MDSET1 = 1).
To use segment output only pins, use the SEGEN register to enable segment output to them.
To use segment output pins, which are alternatively used with port pins, use the PFALL register to set them
to segment output. In addition, to use the segment output pins, which are alternatively used with the TI04,
TI02, and RxD3 pins, use the ISC register to disable input to the Schmitt trigger buffer.
Set the display data in LCD display RAM.
Set the number of time slices and the bias mode via the LCDM0 to LCDM2 bits (bits 0 to 2 of the LCDM
register).
(Only 1/3 bias mode can be set for the capacitor split method)
Select the display data area via the LCDSEL and BLON bits (bits 3 and 4 of the LCDM register).
Set the LCD source clock and LCD clock via the LCDC0 register.
Set (VLCON = 1) the VLCON bit (bit 5 of the LCDM register) to start the voltage reduction circuit operation.
Wait for the voltage capacitor split wait time after setting of VLCON (see CHAPTER 31 ELECTRICAL
SPECIFICATIONS).
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Set (SCOC = 1) the SCOC bit (bit 6 of the LCDM register).
Non-selected waveforms are output from all the segment and common pins, and the non-display status is
entered.
Start output corresponding to each data memory by setting (LCDON = 1) the LCDON bit (bit 7 of the LCDM
register).
Caution
When stopping the operation of the capacitor split circuit, be sure to set SCOC and LCDON to 0
before setting VLCON to 0.
16.6 Common and Segment Signals
Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment
signals becomes higher than a specific voltage (LCD drive voltage, VLCD). The pixels turn off when the potential difference
becomes lower than VLCD.
Applying DC voltage to the common and segment signals of an LCD panel causes deterioration. To avoid this problem,
this LCD panel is driven by AC voltage.
(1)
Common signals
Each common signal is selected sequentially according to a specified number of time slices at the timing listed in
Table 16-3. In the static display mode, the same signal is output to COM0 to COM3.
In the two-time-slice mode, leave the COM2 and COM3 pins open. In the three-time-slice mode, leave the COM3
pin open.
Use the COM4 to COM7 pins other than in the eight-time-slice mode as open or segment pins.
Table 16-3. COM Signals
COM Signal
Number of
Time Slices
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
Note
Note
Note
Note
Open
Note
Note
Note
Note
Open
Note
Note
Note
Note
Note
Note
Note
Note
Static display mode
Two-time-slice mode
Open
Three-time-slice mode
Four-time-slice mode
Eight-time-slice mode
Note
Use the pins as open or segment pins.
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Segment signals
The segment signals correspond to the LCD display data memory (refer to 16.4 LCD Display Data Memory).
When the number of time slices is eight, bits 0 to 7 of each byte are read in synchronization with COM0 to COM7,
respectively. If a bit is 1, it is converted to the select voltage, and if it is 0, it is converted to the deselect voltage.
The conversion results are output to the segment pins (SEG4 to SEG53).
When the number of time slices is number other than eight, bits 0 to 3 of each byte in A-pattern area are read in
synchronization with COM0 to COM3, and bits 4 to 7 of each byte in B-pattern area are read in synchronization
with COM0 to COM3, respectively. If a bit is 1, it is converted to the select voltage, and if it is 0, it is converted to
the deselect voltage. The conversion results are output to the segment pins (SEG0 to SEG53).
Check, with the information given above, what combination of front-surface electrodes (corresponding to the
segment signals) and rear-surface electrodes (corresponding to the common signals) forms display patterns in
the LCD display data memory, and write the bit data that corresponds to the desired display pattern on a one-toone basis.
LCD display data memory bits 1 to 3, bits 2 and 3, bit 3, and F0400H to F0403H are not used for LCD display in
the static display, two-time slot, three-time slot, and eight-time slot modes, respectively. So these bits can be
used for purposes other than display.
Remark The mounted segment output pins vary depending on the product.
• 78K0R/LF3: SEG0 to SEG30
• 78K0R/LG3: SEG0 to SEG39
• 78K0R/LH3: SEG0 to SEG53
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Output waveforms of common and segment signals
The voltages listed in Table 16-4 are output as common and segment signals.
When both common and segment signals are at the select voltage, a display on-voltage of ±VLCD is obtained.
The other combinations of the signals correspond to the display off-voltage.
Table 16-4. LCD Drive Voltage
(a) Static display mode
Segment Signal
Select Signal Level
Deselect Signal Level
VSS/VLC0
VLC0/VSS
Common Signal
VLC0/VSS
–VLCD/+VLCD
0 V/0 V
(b) 1/2 bias method
Segment Signal
Select Signal Level
Deselect Signal Level
VSS/VLC0
VLC0/VSS
Common Signal
Select signal level
VLC0/VSS
–VLCD/+VLCD
Deselect signal level
VLC1 = VLC2
–
0 V/0 V
1
1
VLCD/+ VLCD
2
2
+
1
2
VLCD/–
1
2
VLCD
(c) 1/3 bias method
Segment Signal
Select Signal Level
Common Signal
Deselect Signal Level
VSS/VLC0
Select signal level
VLC0/VSS
–VLCD/+VLCD
Deselect signal level
VLC2/VLC1
–
1
3
VLCD/+
VLC1/VLC2
–
1
3
VLCD
+
1
3
1
3
VLCD/+
VLCD/–
1
3
1
3
VLCD
VLCD
(d) 1/4 bias method
Segment Signal
Select Signal Level
Deselect Signal Level
VLC0/VSS
VLC1/VLC2
Common Signal
Select signal level
VSS/VLC0
+VLCD/–VLCD
Deselect signal level
VLC1/VLC3
+
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VLCD/–
1
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+
VLCD
–
1
2
1
4
VLCD/–
VLCD/+
1
2
1
4
VLCD
VLCD
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Figure 16-13 shows the common signal waveforms, and Figure 16-14 shows the voltages and phases of the common
and segment signals.
Figure 16-13. Common Signal Waveforms (1/2)
(a) Static display mode
VLC0
COMn
VLCD
(Static display)
VSS
TF = T
T: One LCD clock period
TF: Frame frequency
(b) 1/2 bias method
VLC0
COMn
VLC2
VLCD
(Two-time slot mode)
VSS
TF = 2 × T
VLC0
COMn
VLC2
VLCD
(Three-time slot mode)
VSS
TF = 3 × T
T: One LCD clock period
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Figure 16-13. Common Signal Waveforms (2/2)
(c) 1/3 bias method
VLC0
COMn
VLC1
(Three-time slot mode)
VLC2
VSS
VLCD
TF = 3 × T
VLC0
COMn
VLC1
VLC2
VSS
(Four-time slot mode)
VLCD
TF = 4 × T
T: One LCD clock period
TF: Frame frequency
< Example of calculation of LCD frame frequency (When four-time slot mode is used) >
8
LCD clock:
32768/2 = 256 Hz (When setting to LCDC0 = 04H)
LCD frame frequency:
64 Hz
(d) 1/4 bias method
VLC0
VLC1
COMn
VLC2
VLCD
VLC3
(Eight-time slot mode)
VSS
TF = 8 × T
T: One LCD clock period
TF: Frame frequency
< Example of calculation of LCD frame frequency (When eight-time slot mode is used) >
8
LCD clock:
32768/2 = 256 Hz (When setting to LCDC0 = 04H)
LCD frame frequency:
32 Hz
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Figure 16-14. Voltages and Phases of Common and Segment Signals (1/2)
(a) Static display mode
Select
Deselect
VLC0
VLCD
Common signal
VSS
VLC0
VLCD
Segment signal
VSS
T
T
T: One LCD clock period
(b) 1/2 bias method
Select
Deselect
VLC0
VLC2
Common signal
VLCD
VSS
VLC0
Segment signal
VLC2
VLCD
VSS
T
T
T: One LCD clock period
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Figure 16-14. Voltages and Phases of Common and Segment Signals (2/2)
(c) 1/3 bias method
Select
Deselect
VLC0
VLC1
VLC2
Common signal
VLCD
VSS
VLC0
VLC1
VLC2
Segment signal
VLCD
VSS
T
T
T: One LCD clock period
(d) 1/4 bias method
Select
Deselect
VLC0
VLC1
VLC2
Common signal
VLCD
VLC3
VSS
VLC0
VLC1
VLC2
Segment signal
VLCD
VLC3
VSS
T
T
T
T
T: One LCD clock period
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16.7 Display Modes
16.7.1 Static display example
Figure 16-16 shows how the three-digit LCD panel having the display pattern shown in Figure 16-15 is connected to
the segment signals (SEG0 to SEG23) and the common signal (COM0). This example displays data "12.3" in the LCD
panel. The contents of the display data memory (F0400H to F0417H) correspond to this display.
The following description focuses on numeral "2." (
) displayed in the second digit. To display "2." in the LCD panel,
it is necessary to apply the select or deselect voltage to the SEG8 to SEG15 pins according to Table 16-5 at the timing of
the common signal COM0; see Figure 16-15 for the relationship between the segment signals and LCD segments.
Table 16-5. Select and Deselect Voltages (COM0)
Segment
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
Select
Deselect
Select
Select
Deselect
Select
Select
Select
Common
COM0
According to Table 16-5, it is determined that the bit-0 pattern of the display data memory locations (F0408H to
F040FH) must be 10110111.
Figure 16-17 shows the LCD drive waveforms of SEG11 and SEG12, and COM0. When the select voltage is applied
to SEG11 at the timing of COM0, an alternate rectangle waveform, +VLCD/−VLCD, is generated to turn on the corresponding
LCD segment.
COM1 to COM3 are supplied with the same waveform as for COM0. So, COM0 to COM3 may be connected together
to increase the driving capacity.
Figure 16-15. Static LCD Display Pattern and Electrode Connections
SEG8n+3
SEG8n+4
SEG8n+2
SEG8n+5
SEG8n+6
COM0
SEG8n+1
SEG8n
SEG8n+7
Remark
78K0R/LF3: n = 0 to 3
78K0R/LG3: n = 0 to 4
78K0R/LH3: n = 0 to 5
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Figure 16-16. Example of Connecting Static LCD Panel
Timing Strobe
COM 3
COM 2
COM 1
5
6
Data memory address
7
8
9
A
B
C
D
E
F
F0410H
1
2
3
4
5
6
7
Bit 1
Bit 0
SEG 0
SEG 1
SEG 2
SEG 3
SEG 4
SEG 5
SEG 6
SEG 7
SEG 8
SEG 9
SEG 10
SEG 11
SEG 12
SEG 13
LCD panel
4
0 0 0 0 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0
3
× × × × × × × × × × × × × × × × × × × × × × × ×
× × × × × × × × × × × × × × × × × × × × × × × ×
2
× × × × × × × × × × × × × × × × × × × × × × × ×
Bit 3
Bit 2
COM 0
F0400H
1
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together
SEG 14
SEG 15
SEG 16
SEG 17
SEG 18
SEG 19
SEG 20
SEG 21
SEG 22
SEG 23
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Figure 16-17. Static LCD Drive Waveform Examples
TF
VLC0
COM0
VSS
VLC0
SEG11
VSS
VLC0
SEG12
VSS
+VLCD
COM0-SEG11
0
-VLCD
+VLCD
COM0-SEG12
0
-VLCD
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16.7.2 Two-time-slice display example
Figure 16-19 shows how the 6-digit LCD panel having the display pattern shown in Figure 16-18 is connected to the
segment signals (SEG0 to SEG23) and the common signals (COM0 and COM1). This example displays data "12345.6" in
the LCD panel. The contents of the display data memory (F0400H to F0417H) correspond to this display.
The following description focuses on numeral "3" (
) displayed in the fourth digit. To display "3" in the LCD panel, it
is necessary to apply the select or deselect voltage to the SEG12 to SEG15 pins according to Table 16-6 at the timing of
the common signals COM0 and COM1; see Figure 16-18 for the relationship between the segment signals and LCD
segments.
Table 16-6. Select and Deselect Voltages (COM0 and COM1)
Segment
SEG12
SEG13
SEG14
SEG15
COM0
Select
Select
Deselect
Deselect
COM1
Deselect
Select
Select
Select
Common
According to Table 16-6, it is determined that the display data memory location (F040FH) that corresponds to SEG15
must contain xx10.
Figure 16-20 shows examples of LCD drive waveforms between the SEG15 signal and each common signal. When
the select voltage is applied to SEG15 at the timing of COM1, an alternate rectangle waveform, +VLCD/−VLCD, is generated
to turn on the corresponding LCD segment.
Figure 16-18. Two-Time-Slice LCD Display Pattern and Electrode Connections
SEG4n+2
SEG4n+3
SEG4n+1
COM0
SEG4n
COM1
Remark
78K0R/LF3: n = 0 to 6
78K0R/LG3: n = 0 to 9
78K0R/LH3: n = 0 to 12
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Timing strobe
Figure 16-19. Example of Connecting Two-Time-Slice LCD Panel
COM 3
COM 2
COM 1
Open
4
5
6
7
8
9
A
B
C
D
E
F
F0410H
1
2
3
4
5
6
7
Bit 1
Bit 0
SEG 0
SEG 1
SEG 2
SEG 3
SEG 4
SEG 5
SEG 6
SEG 7
SEG 8
SEG 9
SEG 10
SEG 11
SEG 12
SEG 13
LCD panel
3
0 0 0 0 1 1 1 0 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 0
0 0 1 1 1 0 1 0 0 0 1 1 0 1 1 1 0 1 0 1 1 1 0 1
2
× × × × × × × × × × × × × × × × × × × × × × × ×
1
× × × × × × × × × × × × × × × × × × × × × × × ×
Bit 3
Bit 2
COM 0
F0400H
Data memory address
Open
SEG 14
SEG 15
SEG 16
SEG 17
SEG 18
SEG 19
SEG 20
SEG 21
SEG 22
SEG 23
×: Can always be used to store any data because the two-time-slice mode is being used.
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Figure 16-20. Two-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method)
TF
VLC0
COM0
VLC1,2
VSS
VLC0
COM1
VLC1,2
VSS
VLC0
SEG15
VLC1,2
VSS
+VLCD
+1/2VLCD
COM0-SEG15
0
-1/2VLCD
-VLCD
+VLCD
+1/2VLCD
COM1-SEG15
0
-1/2VLCD
-VLCD
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16.7.3 Three-time-slice display example
Figure 16-22 shows how the 8-digit LCD panel having the display pattern shown in Figure 16-21 is connected to the
segment signals (SEG0 to SEG23) and the common signals (COM0 to COM2). This example displays data "123456.78"
in the LCD panel. The contents of the display data memory (addresses F0400H to F0417H) correspond to this display.
The following description focuses on numeral "6." (
) displayed in the third digit. To display "6." in the LCD panel, it
is necessary to apply the select or deselect voltage to the SEG6 to SEG8 pins according to Table 16-7 at the timing of the
common signals COM0 to COM2; see Figure 16-21 for the relationship between the segment signals and LCD segments.
Table 16-7. Select and Deselect Voltages (COM0 to COM2)
Segment
SEG6
SEG7
SEG8
COM0
Deselect
Select
Select
COM1
Select
Select
Select
COM2
Select
Select
−
Common
According to Table 16-7, it is determined that the display data memory location (F0406H) that corresponds to SEG6
must contain x110.
Figures 16-23 and 16-24 show examples of LCD drive waveforms between the SEG6 signal and each common signal
in the 1/2 and 1/3 bias methods, respectively. When the select voltage is applied to SEG6 at the timing of COM1 or COM2,
an alternate rectangle waveform, +VLCD/−VLCD, is generated to turn on the corresponding LCD segment.
Figure 16-21. Three-Time-Slice LCD Display Pattern and Electrode Connections
COM0
SEG3n+1
SEG3n+2
SEG3n
COM1
COM2
Remark
78K0R/LF3: n = 0 to 9
78K0R/LG3: n = 0 to 12
78K0R/LH3: n = 0 to 17
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Figure 16-22. Example of Connecting Three-Time-Slice LCD Panel
Timing strobe
COM 3
COM 2
COM 1
4
5
6
7
8
9
A
B
C
D
E
F
F0410H
1
2
3
4
5
6
7
SEG 0
SEG 1
SEG 2
SEG 3
SEG 4
SEG 5
SEG 6
SEG 7
SEG 8
SEG 9
SEG 10
SEG 11
SEG 12
SEG 13
SEG 14
LCD panel
Bit 3
3
x’ 0 0 x’ 1 0 x’ 1 0 x’ 0 0 x’ 1 0 x’ 1 1 x’ 0 0 x’ 1 0
0 0 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1
0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1
2
× × × × × × × × × × × × × × × × × × × × × × × ×
1
Bit 2
Bit 1
Bit 0
COM 0
F0400H
Data memory address
Open
SEG 15
SEG 16
SEG 17
SEG 18
SEG 19
SEG 20
SEG 21
SEG 22
SEG 23
×’: Can be used to store any data because there is no corresponding segment in the LCD panel.
×: Can always be used to store any data because the three-time-slice mode is being used.
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Figure 16-23. Three-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method)
TF
VLC0
COM0
VLC1,2
VSS
VLC0
COM1
VLC1,2
VSS
VLC0
COM2
VLC1,2
VSS
VLC0
SEG6
VLC1,2
VSS
+VLCD
+1/2VLCD
COM0-SEG6
0
-1/2VLCD
-VLCD
+VLCD
+1/2VLCD
COM1-SEG6
0
-1/2VLCD
-VLCD
+VLCD
+1/2VLCD
COM2-SEG6
0
-1/2VLCD
-VLCD
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Figure 16-24. Three-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method)
TF
VLC0
COM0
VLC1
VLC2
VSS
VLC0
COM1
VLC1
VLC2
VSS
VLC0
COM2
VLC1
VLC2
VSS
VLC0
SEG6
VLC1
VLC2
VSS
+VLCD
+1/3VLCD
COM0-SEG6
0
-1/3VLCD
-VLCD
+VLCD
+1/3VLCD
COM1-SEG6
0
-1/3VLCD
-VLCD
+VLCD
+1/3VLCD
COM2-SEG6
0
-1/3VLCD
-VLCD
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16.7.4 Four-time-slice display example
Figure 16-26 shows how the 12-digit LCD panel having the display pattern shown in Figure 16-25 is connected to the
segment signals (SEG0 to SEG23) and the common signals (COM0 to COM3).
This example displays data
"123456.789012" in the LCD panel. The contents of the display data memory (addresses F0400H to F0417H) correspond
to this display.
The following description focuses on numeral "6." (
) displayed in the seventh digit. To display "6." in the LCD panel,
it is necessary to apply the select or deselect voltage to the SEG12 and SEG13 pins according to Table 16-8 at the timing
of the common signals COM0 to COM3; see Figure 16-25 for the relationship between the segment signals and LCD
segments.
Table 16-8. Select and Deselect Voltages (COM0 to COM3)
Segment
SEG12
SEG13
COM0
Select
Select
COM1
Deselect
Select
COM2
Select
Select
COM3
Select
Select
Common
According to Table 16-8, it is determined that the display data memory location (F040CH) that corresponds to SEG12
must contain 1101.
Figure 16-27 shows examples of LCD drive waveforms between the SEG12 signal and each common signal. When
the select voltage is applied to SEG12 at the timing of COM0, an alternate rectangle waveform, +VLCD/−VLCD, is generated
to turn on the corresponding LCD segment.
Figure 16-25. Four-Time-Slice LCD Display Pattern and Electrode Connections
SEG2n
COM0
COM1
COM2
COM3
SEG2n+1
Remark
78K0R/LF3: n = 0 to 14
78K0R/LG3: n = 0 to 19
78K0R/LH3: n = 0 to 26
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Figure 16-26. Example of Connecting Four-Time-Slice LCD Panel
Timing strobe
COM 3
COM 2
COM 1
2
3
4
5
6
7
Data memory address
8
9
A
B
C
D
E
F
F0410H
1
2
3
4
5
6
7
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Bit 0
SEG 0
SEG 1
SEG 2
SEG 3
SEG 4
SEG 5
SEG 6
SEG 7
SEG 8
SEG 9
SEG 10
SEG 11
SEG 12
SEG 13
LCD panel
1
0 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 0 1 1 1
0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1
F0400H
0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0
0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0
Bit 3
Bit 2
COM 0
SEG 14
SEG 15
SEG 16
SEG 17
SEG 18
SEG 19
SEG 20
SEG 21
SEG 22
SEG 23
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Figure 16-27. Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method)
TF
VLC0
COM0
VLC1
VLC2
VSS
VLC0
COM1
VLC1
VLC2
VSS
VLC0
COM2
VLC1
VLC2
VSS
VLC0
COM3
VLC1
VLC2
VSS
VLC0
SEG12
VLC1
VLC2
VSS
+VLCD
+1/3VLCD
COM0-SEG12
0
-1/3VLCD
-VLCD
+VLCD
+1/3VLCD
COM1-SEG12
0
-1/3VLCD
-VLCD
Remark
The waveforms for COM2-SEG12 and COM3-SEG12 are omitted.
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16.7.5 Eight-time-slice display example
Figure 16-29 shows how the 15x8 dot LCD panel having the display pattern shown in Figure 16-28 is connected to the
segment signals (SEG4 to SEG18) and the common signals (COM0 to COM7). This example displays data "123" in the
LCD panel. The contents of the display data memory (addresses F0404H to F0412H) correspond to this display.
The following description focuses on numeral "3." (
) displayed in the first digit. To display "3." in the LCD panel, it is
necessary to apply the select or deselect voltage to the SEG4 to SEG8 pins according to Table 16-8 at the timing of the
common signals COM0 to COM7; see Figure 16-28 for the relationship between the segment signals and LCD segments.
Table 16-9. Select and Deselect Voltages (COM0 to COM7)
Segment
SEG4
SEG5
SEG6
SEG7
SEG8
COM0
Select
Select
Select
Select
Select
COM1
Deselect
Select
Deselect
Deselect
Deselect
COM2
Deselect
Deselect
Select
Deselect
Deselect
COM3
Deselect
Select
Deselect
Deselect
Deselect
COM4
Select
Deselect
Deselect
Deselect
Deselect
COM5
Select
Deselect
Deselect
Deselect
Select
COM6
Deselect
Select
Select
Select
Deselect
COM7
Deselect
Deselect
Deselect
Deselect
Deselect
Common
According to Table 16-9, it is determined that the display data memory location (F0404H) that corresponds to SEG4
must contain 00110001.
Figure 16-30 shows examples of LCD drive waveforms between the SEG4 signal and each common signal. When the
select voltage is applied to SEG4 at the timing of COM0, a waveform is generated to turn on the corresponding LCD
segment.
Figure 18-28. Eight-Time-Slice LCD Display Pattern and Electrode Connections
S S S S S
E E E E E
G G G G G
n+4 n+3 n+2 n+1
n
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
Remark
78K0R/LF3: n = 4 to 26
78K0R/LG3: n = 4 to 35
78K0R/LH3: n = 4 to 49
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6
7
8
9
A
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C
D
E
F0410H
F
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0 1 1 0 0 1 0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 1 1 1 0 1 1 1 1 1
0 0 1 0 0 0 0 0 1 0 0 0 0 1 0
0 0 1 0 0 0 0 0 0 1 0 0 1 0 0
0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
0 0 1 0 0 0 0 1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 0 1 1 1 1 1 0 1 1 1 0
SEG 9
SEG 10
SEG 11
SEG 12
LCD panel
Bit 1
Bit 0
Bit 3
Bit 2
Bit 5
Bit 4
Bit 7
Bit 6
Timing strobe
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CHAPTER 16 LCD CONTROLLER/DRIVER
Figure 18-29. Example of Connecting Eight-Time-Slice LCD Panel
COM 7
COM 6
COM 5
COM 3
COM 2
COM 1
COM 4
COM 0
SEG 4
SEG 5
SEG 6
SEG 7
SEG 8
SEG 13
SEG 14
SEG 15
SEG 16
SEG 17
SEG 18
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Figure 16-30. Eight-Time-Slice LCD Drive Waveform Examples (1/4 Bias Method)
TF
VLC0
VLC1
COM0
VLC2
VLC3
VSS
VLC0
VLC1
COM1
VLC2
VLC3
VSS
VLC0
VLC1
COM2
VLC2
VLC3
VSS
.
.
.
.
.
.
.
.
VLC0
VLC1
COM7
VLC2
VLC3
VSS
VLC0
VLC1
SEG4
VLC2
VLC3
VSS
+VLCD
+1/2VLCD
+1/4VLCD
COM0-SEG4
0
-1/4VLCD
-1/2VLCD
-VLCD
+VLCD
+1/2VLCD
+1/4VLCD
COM1-SEG4
0
-1/4VLCD
-1/2VLCD
-VLCD
Remark
The waveforms for COM3 to COM6, COM2-SEG4 to COM7-SEG4 are omitted.
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16.8 Supplying LCD Drive Voltages VLC0, VLC1, VLC2, and VLC3
With the 78K0R/Lx3 microcontrollers, a LCD drive power supply can be generated using either of three types of
methods: external resistance division method, internal voltage boosting method, or capacitor split method.
16.8.1 External resistance division method
The 78K0R/Lx3 microcontrollers can also use external voltage divider resistors for generating LCD drive power
supplies, without using internal resistors. Figure 16-31 shows examples of LCD drive voltage connection, corresponding to
each bias method.
Figure 16-31. Examples of LCD Drive Power Connections (External Resistance Division Method) (1/2)
(a) Static display mode
(b) 1/2 bias method
VDD
VDD
VLC0
VLC0
VLC1
VLC1Note1
VLC1
VLC2
VLC2Note1
VLC2
VLC3
VLC3/P02Note2
VLC0
VLC0
R
VLC1
VLC2
R
VSS
VSS
VLC0 = VDD
Notes 1. Connect VLC1 and VLC2 directly to GND or VLC0.
VLC3/
P02Note
VLC3
VSS
VSS
VLC0 = VDD
Note VLC3 can be used as port (P02).
2. VLC3 can be used as port (P02).
Caution To stabilize the potential of the VLC0 to VLC3 pins, it is recommended to connect a capacitor of about
0.1 μF between each of the pins from VLC0 to VLC3 and the GND pin as needed.
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Figure 16-31. Examples of LCD Drive Power Connections (External Resistance Division Method) (2/2)
(c) 1/3 bias method
(d) 1/4 bias method
VDD
VDD
VLC0
VLC0
VLC0
VLC0
R
R
VLC1
VLC1
VLC1
VLC1
R
R
VLC2
VLC2
VLC2
VLC2
R
R
VLC3/
P02Note
VLC3
VLC3
VLC3
R
VSS
VSS
VSS
VSS
VLC0 = VDD
VLC0 = VDD
Note VLC3 can be used as port (P02).
Caution To stabilize the potential of the VLC0 to VLC3 pins, it is recommended to connect a capacitor of
about 0.1 μF between each of the pins from VLC0 to VLC3 and the GND pin as needed.
16.8.2 Internal voltage boosting method
The 78K0R/Lx3 microcontrollers contain an internal voltage boost circuit for generating LCD drive power supplies. The
internal voltage boost circuit and external capacitors (0.47 μF±30%) are used to generate an LCD drive voltage. Only 1/3
bias mode or 1/4 bias mode can be set for the internal voltage boost method.
The LCD drive voltage of the internal voltage boost method can supply a constant voltage, regardless of changes in
VDD, because it is a power supply separate from the main unit.
In addition, a contrast can be adjusted by using the LCD boost level control register (VLCD).
Table 16-10. LCD Drive Voltages (Internal Voltage Boosting Method)
Bias Method
1/3 Bias Method
1/4 Bias Method
LCD Drive Voltage Pin
VLC0
3 x VLC2
4 x VLC3
VLC1
2 x VLC2
3 x VLC3
VLC2
LCD reference voltage
2 x VLC3
VLC3
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Figure 16-32. Examples of LCD Drive Power Connections (Internal Voltage Boosting Method)
(a) 1/3 bias method
(b) 1/4 bias method
VDD
VDD
Drive voltage
generator
3xVLC2
VLC0
4xVLC3
VLC0
2xVLC2
VLC1
3xVLC3
VLC1
2xVLC3
VLC2
Drive voltage
generator
VLC2
Internal reference
voltage generator
C2
VLC3/P02Note
C3
C4
VLC3
Internal reference
voltage generator
CAPH
CAPH
C2
C3
C4
C5
C1
C1
CAPL
CAPL
Remark Use a capacitor with as little leakage as possible.
Note VLC3 can be used as port (P02).
In addition, make C1 a nonpolar capacitor.
Remark Use a capacitor with as little leakage as possible.
In addition, make C1 a nonpolar capacitor.
16.8.3 Capacitor split method
The 78K0R/Lx3 microcontrollers contain an internal voltage reduction circuit for generating LCD drive power supplies.
The internal voltage reduction circuit and external capacitors (0.47 μF±30%) are used to generate an LCD drive voltage.
Only 1/3 bias mode can be set for the capacitor split method.
Different from the external resistance division method, there is always no current flowing with the capacitor split method,
so current consumption can be reduced.
Table 16-11. LCD Drive Voltages (Capacitor Split Method)
Bias Method
1/3 Bias Method
LCD Drive Voltage Pin
VLC0
VDD
VLC1
2/3 x VDD
VLC2
1/3 x VDD
VLC3
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Figure 16-33. Examples of LCD Drive Power Connections (Internal Voltage Boosting Method)
• 1/3 bias method
VDD
Drive voltage
generator
VDD
VLC0
2/3 x VDD
VLC1
1/3 x VDD
VLC2
VLC3/P02Note
CAPH
C2
C3
C1
CAPL
Note VLC3 can be used as port (P02).
Remark Use a capacitor with as little leakage as possible.
In addition, make C1 a nonpolar capacitor.
16.9 Selection of LCD Display Data
With the 78K0R/Lx3 microcontroller, to use the LCD display data memory when the number of time slices is static, two,
three, or four, the LCD display data can be selected from the following three types, according to the BLON and LCDSEL
bit settings.
• Displaying an A-pattern area data (lower four bits of LCD display data memory)
• Displaying a B-pattern area data (higher four bits of LCD display data memory)
• Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt
timing of the real-time counter (RTC))
Caution When the LCD display data memory is used when the number of time slices is eight, LCD display data
(A-pattern, B-pattern, or blinking display) cannot be selected.
16.9.1 A-pattern area and B-pattern area data display
When BLON = LCDSEL = 0, A-pattern area (lower four bits of the LCD display data memory) data will be output as the
LCD display data.
When BLON = 0, and LCDSEL = 1, B-pattern area (higher four bits of the LCD display data memory) data will be
output as the LCD display data.
Refer to 16.4 LCD Display Data Memory about the display area.
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16.9.2 Blinking display (Alternately displaying A-pattern and B-pattern area data)
When BLON = 1 has been set, A-pattern and B-pattern area data will be alternately displayed, according to the
constant-period interrupt (INTRTC) timing of the real-time counter (RTC). Refer to CHAPTER 7 REAL-TIME COUNTER
about the setting of the RTC constant-period interrupt (INTRTC) timing.
For blinking display of the LCD, set inverted values to the B-pattern area bits corresponding to the A-pattern area bits.
(Example: Set 1 to bit 0 of 00H, and set 0 to bit 4 of F0400H for blinking display.) When not setting blinking display of the
LCD, set the same values. (Example: Set 1 to bit 2 of F0402H, and set 1 to bit 6 of F0402H for lighting display.)
Figure 16-34. Example of LCD Display Data Setting During Pattern-Switching Display
B-pattern area
b7
b6
b5
F0405H
F0404H
F0403H
F0402H
F0401H
F0400H
A-pattern area
b4
b3
b2
b1
b0
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
Set 1 for lighting display.
COM3
COM2
COM1
COM0
COM3
COM2
COM1
COM0
Set inverted value for blinking display.
Refer to 16.4 LCD Display Data Memory about the display area.
Next, the timing operation of display switching is shown.
Figure 16-35. Switching Operation from A-Pattern Display to Blinking Display
RTC constant-period interrupt
(INTRTC)
BLON, LCDSEL bits
BLON = 0, LCDSEL = 0
Segment display
BLON = 1, LCDSEL = 0 or 1
Apattern
A-pattern
B-pattern
A-pattern
B-pattern
Blinking display always starts from an A pattern.
Figure 16-36. Switching Operation from Blinking Display to A-Pattern Display
RTC constant-period interrupt
(INTRTC)
BLON, LCDSEL bits
BLON = 1,
LCDSEL = 0 or 1
Segment display B-pattern
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CHAPTER 17 MULTIPLIER/DIVIDER
CHAPTER 17 MULTIPLIER/DIVIDER
17.1 Functions of Multiplier/Divider
The multiplier/divider is mounted onto all 78K0R/Lx3 microcontroller products.
The multiplier/divider has the following functions.
• 16 bits × 16 bits = 32 bits (multiplication)
• 32 bits ÷ 32 bits = 32 bits, 32-bit remainder (division)
17.2 Configuration of Multiplier/Divider
The multiplier/divider consists of the following hardware.
Table 17-1. Configuration of Multiplier/Divider
Item
Registers
Configuration
Multiplication/division data register A (L) (MDAL)
Multiplication/division data register A (H) (MDAH)
Multiplication/division data register B (L) (MDBL)
Multiplication/division data register B (H) (MDBH)
Multiplication/division data register C (L) (MDCL)
Multiplication/division data register C (H) (MDCH)
Control register
Multiplication/division control register (MDUC)
Figure 17-1 shows a block diagram of the multiplier/divider.
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Figure 17-1. Block Diagram of Multiplier/Divider
Internal bus
Division
result
(remainder)
Multiplication result
(product)
Multiplication/division data register B
MDBH
Multiplication/division data register C
MDCH
MDBL
MDCL
Division result
(quotient)
Multiplication/division data register A
MDAH
MDAL
Multiplication/division
control register (MDUC)
DIVMODE DIVST
Start
INTMD
Multiplicand
Divisor
Multiplier Dividend
Clear
Controller
Controller
Counter
fPRS
Multiplication/division block
Controller
Data flow during division
Data flow during multiplication
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(1) Multiplication/division data register A (MDAH, MDAL)
The MDAH and MDAL registers set the values that are used for a multiplication or division operation and store the
operation result. They set the multiplier and multiplicand data in the multiplication mode, and set the dividend data
in the division mode. Furthermore, the operation result (quotient) is stored in the MDAH and MDAL registers in the
division mode.
MDAH and MDAL can be set by a 16-bit manipulation instruction.
Reset signal generation clears these registers to 0000H.
Figure 17-2. Format of Multiplication/Division Data Register A (MDAH, MDAL)
Address: FFFF0H, FFFF1H, FFFF2H, FFFF3H
Symbol
MDAH
After reset: 0000H, 0000H R/W
FFFF3H
FFFF2H
MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH
15
14
13
11
10
9
8
7
6
5
4
FFFF1H
Symbol
MDAL
12
3
2
1
0
FFFF0H
MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Cautions 1. Do not rewrite the MDAH and MDAL values during division operation processing (while the
multiplication/division control register (MDUC) is 81H). The operation will be executed in this
case, but the operation result will be an undefined value.
2. The MDAH and MDAL values read during division operation processing (while MDUC is 81H)
will not be guaranteed.
The following table shows the functions of MDAH and MDAL during operation execution.
Table 17-2. Functions of MDAH and MDAL During Operation Execution
DIVMODE
0
Operation Mode
Multiplication mode
Setting
Operation Result
−
MDAH: Multiplier
MDAL: Multiplicand
1
Division mode
MDAH: Divisor (higher 16 bits)
MDAH: Division result (quotient)
Higher 16 bits
MDAL: Dividend (lower 16 bits)
MDAL: Division result (quotient)
Lower 16 bits
Remark
DIVMODE: Bit 7 of the multiplication/division control register (MDUC)
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(2) Multiplication/division data register B (MDBL, MDBH)
The MDBH and MDBL registers set the values that are used for multiplication or division operation and store the
operation result. They store the operation result (product) in the multiplication mode and set the divisor data in the
division mode.
MDBH and MDBL can be set by a 16-bit manipulation instruction.
Reset signal generation clears these registers to 0000H.
Figure 17-3. Format of Multiplication/Division Data Register B (MDBH, MDBL)
Address: FFFF4H, FFFF5H, FFFF6H, FFFF7H
Symbol
MDBH
FFFF7H
FFFF6H
MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH
15
14
13
Symbol
MDBL
After reset: 0000H, 0000H R/W
12
11
10
9
8
7
6
5
4
FFFF5H
3
2
1
0
FFFF4H
MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBHL MDBL MDBL MDBL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Cautions 1. Do not rewrite the MDBH and MDBL values during division operation processing (while the
multiplication/division control register (MDUC) is 81H).
The operation result will be an
undefined value.
2. Do not set MDBH and MDBL to 0000H in the division mode. If they are set, the operation
result will be an undefined value.
The following table shows the functions of MDBH and MDBL during operation execution.
Table 17-3. Functions of MDBH and MDBL During Operation Execution
DIVMODE
0
Operation Mode
Multiplication mode
Setting
Operation Result
−
MDBH: Multiplication result (product)
Higher 16 bits
MDBL: Multiplication result (product)
Lower 16 bits
1
Division mode
MDBH: Divisor (higher 16 bits)
−
MDBL: Dividend (lower 16 bits)
Remark
DIVMODE: Bit 7 of the multiplication/division control register (MDUC)
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(3) Multiplication/division data register C (MDCL, MDCH)
The MDCH and MDCL registers store remainder value of the operation result in the division mode. They are not
used in the multiplication mode.
MDCH and MDCL can be read by a 16-bit manipulation instruction.
Reset signal generation clears these registers to 0000H.
Figure 17-4. Format of Multiplication/Division Data Register C (MDCH, MDCL)
Address: F00E0H, F00E1H, F00E2H, F00E3H
Symbol
After reset: 0000H, 0000H R
F00E3H
MDCH
F00E2H
MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH
15
14
13
12
11
10
9
8
7
6
5
4
F00E1H
Symbol
MDCL
3
2
1
0
F00E0H
MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL
15
Caution
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
The MDCH and MDCL values read during division operation processing (while the
multiplication/division control register (MDUC) is 81H) will not be guaranteed.
Table 17-4. Functions of MDCH and MDCL During Operation Execution
DIVMODE
Operation Mode
Setting
Operation Result
−
0
Multiplication mode
−
1
Division mode
−
MDCH: Remainder (higher 16 bits)
MDCL: Remainder (lower 16 bits)
Remark
DIVMODE: Bit 7 of the multiplication/division control register (MDUC)
The register configuration differs between when multiplication is executed and when division is executed, as follows.
• Register configuration during multiplication
MDAL (bits 15 to 0) × MDAH (bits 15 to 0) = [MDBH (bits 15 to 0), MDBL (bits 15 to 0)]
• Register configuration during division
[MDAH (bits 15 to 0), MDAL (bits 15 to 0)] ÷ [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] =
[MDAH (bits 15 to 0), MDAL (bits 15 to 0)] ⋅⋅⋅ [MDCH (bits 15 to 0), MDCL (bits 15 to 0)]
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CHAPTER 17 MULTIPLIER/DIVIDER
17.3 Register Controlling Multiplier/Divider
The multiplier/divider is controlled by using the multiplication/division control register (MDUC).
(1) Multiplication/division control register (MDUC)
MDUC is an 8-bit register that controls the operation of the multiplier/divider.
MDUC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 17-5. Format of Multiplication/Division Control Register (MDUC)
Address: F00E8H
After reset: 00H
R/W
Symbol
6
5
4
3
2
1
MDUC
DIVMODE
0
0
0
0
0
0
DIVST
DIVMODE
Operation mode (multiplication/division) selection
0
Multiplication mode
1
Division mode
Note
DIVST
Division operation start/stop
0
Division operation processing complete
1
Starts division operation/division operation processing in progress
Note DIVST can only be set (1) in the division mode. In the division mode, division operation is started by setting
(1) DIVST.
DIVST is automatically cleared (0) when the operation ends.
In the multiplication mode,
operation is automatically started by setting the multiplier and multiplicand to MDAH and MDAL, respectively.
Cautions 1. Do not rewrite DIVMODE during operation processing (while DIVST is 1). If it is rewritten, the
operation result will be an undefined value.
2. DIVST cannot be cleared (0) by using software during division operation processing (while
DIVST is 1).
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17.4 Operations of Multiplier/Divider
17.4.1 Multiplication operation
• Initial setting
Set bit 7 (DIVMODE) of the multiplication/division control register (MDUC) to 0.
Set the multiplicand to the multiplication/division data register A (L) (MDAL).
Set the multiplier to the multiplication/division data register A (H) (MDAH).
(There is no preference in the order of executing steps and . Multiplication operation is automatically
started when the multiplier and multiplicand are set to MDAH and MDAL, respectively.)
• During operation processing
Wait for at least one clock. The operation will end when one clock has been issued.
• Operation end
Read the product (lower 16 bits) from the multiplication/division data register B (L) (MDBL).
Read the product (higher 16 bits) from the multiplication/division data register B (H) (MDBH).
(There is no preference in the order of executing steps and .)
• Next operation
To execute multiplication operation next, start from the “Initial setting” for multiplication operation.
To execute division operation next, start from the “Initial setting” in 17.4.2 Division operation.
Remark
Steps to correspond to to in Figure 17-6.
Figure 17-6. Timing Diagram of Multiplication Operation (0003H × 0002H)
Operation clock
DIVMODE
"0"
MDAH
Initial value = 0
MDAL
Initial value = 0
MDBH
Initial value = 0
0003H
FFFFH
0002H
0006H
FFFFH
1FFFEH
FFFE000H
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17.4.2 Division operation
• Initial setting
Set bit 7 (DIVMODE) of the multiplication/division control register (MDUC) to 1.
Set the dividend (higher 16 bits) to the multiplication/division data register A (H) (MDAH).
Set the dividend (lower 16 bits) to the multiplication/division data register A (L) (MDAL).
Set the divisor (higher 16 bits) to the multiplication/division data register B (H) (MDBH).
Set the divisor (lower 16 bits) to the multiplication/division data register B (L) (MDBL).
Set bit 0 (DIVST) of MDUC to 1.
(There is no preference in the order of executing steps to .)
• During operation processing
The operation will end when one of the following processing is completed.
• A wait of at least 16 clocks (The operation will end when 16 clocks have been issued.)
• A check whether DIVST has been cleared
• Generation of a division completion interrupt (INTMD)
(The read values of MDBL, MDBH, MDCH, and MDCL during operation processing are not guaranteed.)
• Operation end
DIVST is cleared (0) and an interrupt request signal (INTMD) is generated (end of operation).
Read the quotient (lower 16 bits) from MDAL.
Read the quotient (higher 16 bits) from MDAH.
Read the remainder (lower 16 bits) from multiplication/division data register C (L) (MDCL).
Read the remainder (higher 16 bits) from the multiplication/division data register C (H) (MDCH).
(There is no preference in the order of executing steps to .)
• Next operation
To execute multiplication operation next, start from the “Initial setting” in 17.4.1 Multiplication operation.
To execute division operation next, start from the “Initial setting” for division operation.
Remark
Steps to correspond to to in Figure 17-7.
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Figure 17-7. Timing Diagram of Division Operation (Example: 35 ÷ 6 = 5, Remainder 5)
Operation clock
DIVMODE
DIVST
Undefined
MDAH, MDAL
XXXX
XXXX
MDBH, MDBL
XXXX
XXXX
MDCH, MDCL
XXXX
XXXX
0
0000
0000
0000
0023
0000
0000
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0000 0000 0000 0000 0000 0002 0008 0023 008C 0230 08C0 2300 8C00 3000 C000
008C 0230 08C0 2300 8C00 3000 C000 0000 0000 0000 0000 0000 0000 0000 0001
0
0000
0005
0000
0006
0000
0000
0000 0000
0002 0002
0000
0005
INTMD
,
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CHAPTER 18 DMA CONTROLLER
CHAPTER 18 DMA CONTROLLER
The DMA (Direct Memory Access) controller is mounted onto all 78K0R/Lx3 microcontroller products.
Data can be automatically transferred between the peripheral hardware supporting DMA, SFRs, and internal RAM
without via CPU.
As a result, the normal internal operation of the CPU and data transfer can be executed in parallel with transfer
between the SFR and internal RAM, and therefore, a large capacity of data can be processed. In addition, real-time
control using communication, timer, and A/D can also be realized.
18.1 Functions of DMA Controller
{ Number of DMA channels: 2
{ Transfer unit: 8 or 16 bits
{ Maximum transfer unit: 1024 times
{ Transfer type:
2-cycle transfer (One transfer is processed in 2 clocks and the CPU stops during that
processing.)
{ Transfer mode: Single-transfer mode
{ Transfer target: Between SFR and internal RAM
{ Transfer request: Selectable from the following peripheral hardware interrupts
Peripheral hardware
78K0R/LF3
78K0R/LG3
78K0R/LH3
(μPD78F150nA: n = 0 to 2)
(μPD78F150nA: n = 3 to 5)
(μPD78F150nA: n = 6 to 8)
80 pins
100 pins
128 pins
Timer array
Channel 0
√
√
√
unit 0
Channel 1
√
√
√
Channel 4
√
√
√
Channel 5
√
√
√
Serial array
CSI00
−
√
√
unit 0
CSI01
−
−
√
CSI10
√
√
√
UART0
−
√
√
Serial array
UART1
√
√
√
IIC10
√
√
√
UART3
√
√
√
√
√
√
unit 1
A/D converter
√: Supported, −: Not supported
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Here are examples of functions using DMA.
• Successive transfer of serial interface
• Batch transfer of analog data
• Capturing A/D conversion result at fixed interval
• Capturing port value at fixed interval
18.2 Configuration of DMA Controller
The DMA controller includes the following hardware.
Table 18-1. Configuration of DMA Controller
Item
Configuration
• DMA SFR address registers 0, 1 (DSA0, DSA1)
Address registers
• DMA RAM address registers 0, 1 (DRA0, DRA1)
Count register
• DMA byte count registers 0, 1 (DBC0, DBC1)
Control registers
• DMA mode control registers 0, 1 (DMC0, DMC1)
• DMA operation control registers 0, 1 (DRC0, DRC1)
(1) DMA SFR address register n (DSAn)
This is an 8-bit register that is used to set an SFR address that is the transfer source or destination of DMA
channel n.
Set the lower 8 bits of the SFR addresses FFF00H to FFFFFHNote.
This register is not automatically incremented but fixed to a specific value.
In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.
DSAn can be read or written in 8-bit units. However, it cannot be written during DMA transfer.
Reset signal generation clears this register to 00H.
Note Except for address FFFFEH because the PMC register is allocated there.
Figure 18-1. Format of DMA SFR Address Register n (DSAn)
Address: FFFB0H (DSA0), FFFB1H (DSA1)
7
6
5
4
3
After reset: 00H
2
1
R/W
0
DSAn
Remark
n: DMA channel number (n = 0, 1)
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(2) DMA RAM address register n (DRAn)
This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA
channel n.
Addresses of the internal RAM area other than the general-purpose registers (FEF00H to FFEDFH in the case of
the μPD78F1500A, 78F1503A, and 78F1506A) can be set to this register.
Set the lower 16 bits of the RAM address.
This register is automatically incremented when DMA transfer has been started. It is incremented by +1 in the 8bit transfer mode and by +2 in the 16-bit transfer mode. DMA transfer is started from the address set to this
DRAn register. When the data of the last address has been transferred, DRAn stops with the value of the last
address +1 in the 8-bit transfer mode, and the last address +2 in the 16-bit transfer mode.
In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.
DRAn can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer.
Reset signal generation clears this register to 0000H.
Figure 18-2. Format of DMA RAM Address Register n (DRAn)
Address: FFFB2H, FFFB3H (DRA0), FFFB4H, FFFB5H (DRA1)
15
14
13
After reset: 0000H
R/W
DRA0H: FFFB3H
DRA0L: FFFB2H
DRA1H: FFFB5H
DRA1L: FFFB4H
12
11
10
9
8
7
6
5
4
3
2
1
0
DRAn
(n = 0, 1)
Remark
n: DMA channel number (n = 0, 1)
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(3) DMA byte count register n (DBCn)
This is a 10-bit register that is used to set the number of times DMA channel n executes transfer. Be sure to set
the number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times).
Each time DMA transfer has been executed, this register is automatically decremented. By reading this DBCn
register during DMA transfer, the remaining number of times of transfer can be learned.
DBCn can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer.
Reset signal generation clears this register to 0000H.
Figure 18-3. Format of DMA Byte Count Register n (DBCn)
Address: FFFB6H, FFFB7H (DBC0), FFFB8H, FFFB9H (DBC1)
DBCn
After reset: 0000H
R/W
DBC0H: FFFB7H
DBC0L: FFFB6H
DBC1H: FFFB9H
DBC1L: FFFB8H
15
14
13
12
11
10
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
(n = 0, 1)
DBCn[9:0] Number of Times of Transfer
Remaining Number of Times of Transfer
(When DBCn is Written)
(When DBCn is Read)
000H
1024
Completion of transfer or waiting for 1024 times of DMA transfer
001H
1
Waiting for remaining one time of DMA transfer
002H
2
Waiting for remaining two times of DMA transfer
003H
3
Waiting for remaining three times of DMA transfer
•
•
•
•
•
•
•
•
•
3FEH
1022
Waiting for remaining 1022 times of DMA transfer
3FFH
1023
Waiting for remaining 1023 times of DMA transfer
Cautions 1. Be sure to clear bits 15 to 10 to “0”.
2. If the general-purpose register is specified or the internal RAM space is exceeded as a
result of continuous transfer, the general-purpose register or SFR space are written or read,
resulting in loss of data in these spaces. Be sure to set the number of times of transfer that
is within the internal RAM space.
Remark
n: DMA channel number (n = 0, 1)
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18.3 Registers Controlling DMA Controller
DMA controller is controlled by the following registers.
• DMA mode control register n (DMCn)
• DMA operation control register n (DRCn)
Remark
n: DMA channel number (n = 0, 1)
(1) DMA mode control register n (DMCn)
DMCn is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer direction,
data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts DMA.
Rewriting bits 6, 5, and 3 to 0 of DMCn is prohibited during operation (when DSTn = 1).
DMCn can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 18-4. Format of DMA Mode Control Register n (DMCn) (1/2)
Address: FFFBAH (DMC0), FFFBBH (DMC1)
After reset: 00H
R/W
Symbol
3
2
1
0
DMCn
STGn
DRSn
DSn
DWAITn
IFCn3
IFCn2
IFCn1
IFCn0
STGn
Note 1
DMA transfer start software trigger
0
No trigger operation
1
DMA transfer is started when DMA operation is enabled (DENn = 1).
DMA transfer is started by writing 1 to STGn when DMA operation is enabled (DENn = 1).
When this bit is read, 0 is always read.
DRSn
Selection of DMA transfer direction
0
SFR to internal RAM
1
Internal RAM to SFR
DSn
Specification of transfer data size for DMA transfer
0
8 bits
1
16 bits
DWAITn
Note 2
Pending of DMA transfer
0
Executes DMA transfer upon DMA start request (not held pending).
1
Holds DMA start request pending if any.
DMA transfer that has been held pending can be started by clearing the value of DWAITn to 0.
It takes 2 clocks to actually hold DMA transfer pending when the value of DWAITn is set to 1.
Notes 1. The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values.
2. When DMA transfer is held pending while using both DMA channels, be sure to hold the DMA transfer
pending for both channels (by setting the DWAIT0 and DWAIT1 bits to 1).
Remark
n: DMA channel number (n = 0, 1)
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Figure 18-4. Format of DMA Mode Control Register n (DMCn) (2/2)
Address: FFFBAH (DMC0), FFFBBH (DMC1)
After reset: 00H
R/W
Symbol
3
2
1
0
DMCn
STGn
DRSn
DSn
DWAITn
IFCn3
IFCn2
IFCn1
IFCn0
IFCn
IFCn
IFCn
IFCn
3
2
1
0
Trigger signal
0
0
0
0
−
Selection of DMA start source
Note
LF3
LG3
LH3
√
√
√
Trigger contents
Disables DMA transfer by interrupt.
(Only software trigger is enabled.)
0
0
1
0
INTTM00
Timer channel 0 interrupt
√
√
√
0
0
1
1
INTTM01
Timer channel 1 interrupt
√
√
√
0
1
0
0
INTTM04
Timer channel 4 interrupt
√
√
√
0
1
0
1
INTTM05
Timer channel 5 interrupt
√
√
√
0
1
1
0
INTST0
UART0 transmission end interrupt
−
√
√
INTCSI00
CSI00 transfer end interrupt
−
√
√
0
1
1
1
INTSR0
UART0 reception end interrupt
−
√
√
INTCSI01
CSI01 transfer end interrupt
−
−
√
INTST1
UART1 transmission end interrupt
√
√
√
INTCSI10
CSI10 transfer end interrupt
√
√
√
INTIIC10
IIC10 transfer end interrupt
√
√
√
1
0
0
0
1
0
0
1
INTSR1
UART1 reception end interrupt
√
√
√
1
0
1
0
INTST3
UART3 transmission end interrupt
√
√
√
1
0
1
1
INTSR3
UART3 reception end interrupt
√
√
√
1
1
0
0
INTAD
A/D conversion end interrupt
√
√
√
Other than above
Setting prohibited
Note The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 values.
Remarks 1. n: DMA channel number (n = 0, 1)
2. √: Supported, −: Not supported
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(2) DMA operation control register n (DRCn)
DRCn is a register that is used to enable or disable transfer of DMA channel n.
Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1).
DRCn can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 18-5. Format of DMA Operation Control Register n (DRCn)
Address: FFFBCH (DRC0), FFFBDH (DRC1)
After reset: 00H
R/W
Symbol
6
5
4
3
2
1
DRCn
DENn
0
0
0
0
0
0
DSTn
DENn
DMA operation enable flag
0
Disables operation of DMA channel n (stops operating cock of DMA).
1
Enables operation of DMA channel n.
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
DSTn
DMA transfer mode flag
0
DMA transfer of DMA channel n is completed.
1
DMA transfer of DMA channel n is not completed (still under execution).
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
When a software trigger (STGn) or the start source trigger set by IFCn3 to IFCn0 is input, DMA transfer is started.
When DMA transfer is completed after that, this bit is automatically cleared to 0.
Write 0 to this bit to forcibly terminate DMA transfer under execution.
Cautions 1. The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is terminated
without waiting for generation of the interrupt (INTDMAn) of DMAn, therefore, set DSTn to 0
and then DENn to 0 (for details, refer to 18.5.7 Forced termination by software).
2. When the FSEL bit of the OSMC register has been set to 1, do not enable (DENn = 1) DMA
operation for at least three clocks after the setting.
Remark
n: DMA channel number (n = 0, 1)
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18.4 Operation of DMA Controller
18.4.1 Operation procedure
The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set
DENn to 1. Use 80H to write with an 8-bit manipulation instruction.
Set an SFR address, a RAM address, the number of times of transfer, and a transfer mode of DMA transfer to the
DSAn, DRAn, DBCn, and DMCn registers.
The DMA controller waits for a DMA trigger when DSTn = 1. Use 81H to write with an 8-bit manipulation
instruction.
When a software trigger (STGn) or a start source trigger specified by IFCn3 to IFCn0 is input, a DMA transfer is
started.
Transfer is completed when the number of times of transfer set by the DBCn register reaches 0, and transfer is
automatically terminated by occurrence of an interrupt (INTDMAn).
Stop the operation of the DMA controller by clearing DENn to 0 when the DMA controller is not used.
Figure 18-6. Operation Procedure
DENn = 1
Set by software program
Setting DSAn, DRAn, DBCn, and DMCn
DSTn = 1
DMA trigger = 1?
No
Yes
Transmitting DMA request
Receiving DMA acknowledge
Operation by DMA
DMA transfer
controller (hardware)
DRAn = DRAn + 1 (or + 2)
DBCn = DBCn − 1
No
DBCn = 0000H ?
Yes
DSTn = 0
INTDMAn = 1
DENn = 0
Remark
Set by software program
n: DMA channel number (n = 0, 1)
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18.4.2 Transfer mode
The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of the DMCn register.
DRSn
DSn
DMA Transfer Mode
0
0
Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1)
0
1
Transfer from SFR of 2-byte data (fixed address) to RAM (address is incremented by +2)
1
0
Transfer from RAM of 1-byte data (address is incremented by +1) to SFR (fixed address)
1
1
Transfer from RAM of 2-byte data (address is incremented by +2) to SFR (fixed address)
By using these transfer modes, up to 1024 bytes of data can be consecutively transferred by using the serial interface,
data resulting from A/D conversion can be consecutively transferred, and port data can be scanned at fixed time intervals
by using a timer.
18.4.3 Termination of DMA transfer
When DBCn = 00H and DMA transfer is completed, the DSTn bit is automatically cleared to 0. An interrupt request
(INTDMAn) is generated and transfer is terminated.
When the DSTn bit is cleared to 0 to forcibly terminate DMA transfer, the DBCn and DRAn registers hold the value
when transfer is terminated.
The interrupt request (INTDMAn) is not generated if transfer is forcibly terminated.
Remark
n: DMA channel number (n = 0, 1)
18.5 Example of Setting of DMA Controller
18.5.1 CSI consecutive transmission
A flowchart showing an example of setting for CSI consecutive transmission is shown below.
• Consecutive transmission of CSI10
• DMA channel 0 is used for DMA transfer.
• DMA start source: INTCSI10 (software trigger (STG0) only for the first start source)
• Interrupt of CSI10 is specified by IFC03 to IFC00 (bits 3 to 0 of the DMC0 register) = 1000B.
• Transfers FFB00H to FFBFFH (256 bytes) of RAM to FFF44H of the transmit buffer (SIO10) of CSI.
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Figure 18-7. Example of Setting for CSI Consecutive Transmission
Start
DEN0 = 1
DSA0 = 44H
DRA0 = FB00H
DBC0 = 0100H
DMC0 = 48H
Setting for CSI transfer
DST0 = 1
DMA is started.
STG0 = 1
INTCSI10 occurs.
User program
processing
DMA0 transfer
CSI
transmission
Occurrence of
INTDMA0
DST0 = 0Note
DEN0 = 0
RETI
Hardware operation
End
Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMA0 (INTDMA0), set DST0 to 0 and then DEN0 to 0 (for details, refer to 18.5.7
Forced termination by software).
The fist trigger for consecutive transmission is not started by the interrupt of CSI. In this example, it start by a software
trigger.
CSI transmission of the second time and onward is automatically executed.
A DMA interrupt (INTDMA0) occurs when the last transmit data has been written to the data register.
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18.5.2 CSI master reception
A flowchart showing an example of setting for CSI master reception is shown below.
• Master reception (256 bytes) of CSI00
• DMA channel 0 is used to read received data and DMA channel 1 is used to write dummy data.
• DMA start source: INTCSI00
(If the same start source is specified for DMA channels 0 and 1, the data of channel 0 is transferred, and then that of
channel 1.)
• Interrupt of CSI00 is specified by IFC03 to IFC00 = IFC13 to IFC10 (bits 3 to 0 of the DMCn register) = 0110B.
• Data is transferred (received) from FFF10H of the CSI data register (SIO00) to FF100H to FF1FFH of RAM (256
bytes). (In successive reception mode, the data that is to be received when the first buffer empty interrupt occurs is
invalid because the data has not been received.)
• Transfers dummy data FF101H to FF1FFH (255 bytes) of RAM to FFF10H of the data register (SIO00) of CSI.
(Dummy data is written to the first byte by using software (an instruction).)
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Figure 18-8. Example of Setting of Consecutively Capturing A/D Conversion Results
Start
DEN0 = 1
DEN1 = 1
DSA0 = 10H
DRA0 = F100H
DBC0 = 0100H
DMC0 = 06H
DSA1 = 10H
DRA1 = F101H
DBC1 = 00FFH
DMC1 = 46H
Setting for CSI transfer
DST0 = 1
DST1 = 1
Write dummy data to
SIO00 (= SDR00 [7:0])
INTCSI00 occurs.
User program
processing
INTDMA0 occurs.
INTDMA1 occurs.
DST0 = 0 Note
DST1 = 0 Note
DEN0 = 0
DEN1 = 0
RETI
RETI
DMA0 transfer CSI reception
DMA1 transfer Writing dummy data
Hardware operation
End
Note The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMAn (INTDMAn), set DSTn to 0 and then DENn to 0 (for details, refer to 18.5.7
Forcible termination by software).
Because no CSI interrupt is generated when reception starts during CSI master reception, dummy data is written using
software in this example.
The received data is automatically transferred from the first byte (In successive reception mode, the data that is to be
received when the first buffer empty interrupt occurs is invalid because the valid data has not been received.).
A DMA interrupt (INTDMA1) occurs when the last dummy data has been writing to the data register. A DMA interrupt
(INTDMA0) occurs when the last received data has been read from the data register. To restart the DMA transfer, the CSI
transfer must be completed.
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18.5.3 CSI transmission/reception
A flowchart showing an example of setting for CSI transmission/reception is shown below.
• Transmission/reception (256 bytes) of CSI00
• DMA channel 0 is used to read received data and DMA channel 1 is used to write transmit data.
• DMA start source: INTCSI00
(If the same start source is specified for DMA channels 0 and 1, the data of channel 0 is transferred, and then that of
channel 1)
• Interrupt of CSI00 is specified by IFC03 to IFC00 = IFC13 to IFC10 (bits 3 to 0 of the DMCn register) = 0110B.
• Data is transferred (received) from FFF10H of the CSI data register (SIO00) to FF100H to FF1FFH of RAM (256
bytes). (In successive transmission/reception mode, the data that is to be received when the first buffer empty
interrupt occurs is invalid because the data has not been received.)
• Transfers FF201H to FF2FFH (255 bytes) of RAM to FFF10H of the data register (SIO00) of CSI (transmission)
(Transmit data is written to the first byte by using software (an instruction).)
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Figure 18-9. Setting Example of CSI Transmission/reception
Start
DEN0 = 1
DEN1 = 1
DSA0 = 10H
DRA0 = F100H
DBC0 = 0100H
DMC0 = 06H
DSA1 = 10H
DRA1 = F201H
DBC1 = 00FFH
DMC1 = 46H
Setting for CSI transfer
DST0 = 1
DST1 = 1
Write transmit data to
SIO00 (= SDR00 [7:0])
INTCSI00 occurs.
User program
processing
INTDMA0 occurs.
INTDMA1 occurs.
DST0 = 0 Note
DST1 = 0 Note
DEN0 = 0
DEN1 = 0
RETI
RETI
DMA0 transfer CSI reception
DMA1 transfer CSI transmission
Hardware operation
End
Note The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMAn (INTDMAn), set DSTn to 0 and then DENn to 0 (for details, refer to 18.5.7
Forcible termination by software).
During CSI transfers, no CSI interrupt is generated when the transmitted data of the first byte is written. Therefore, the
transmitted data is written using software in this example. The data of the second and following bytes is automatically
transmitted.
The received data is automatically transferred from the first byte. (In successive transmission/reception, the data that is
to be received when the first buffer empty interrupt occurs is invalid because the valid data has not been received.)
A DMA interrupt (INTDMA1) occurs when the last transmit data has been writing to the data register. A DMA interrupt
(INTDMA0) occurs when the last received data has been read from the data register. To restart the DMA transfer, the CSI
transfer must be completed.
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18.5.4 Consecutive capturing of A/D conversion results
A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below.
• Consecutive capturing of A/D conversion results.
• DMA channel 1 is used for DMA transfer.
• DMA start source: INTAD
• Interrupt of A/D is specified by IFC13 to IFC10 (bits 3 to 0 of the DMC1 register) = 1100B.
• Transfers FFF1EH and FFF1FH (2 bytes) of the 12-bit A/D conversion result register to 512 bytes of FFCE0H to
FFEDFH of RAM.
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Figure 18-10. Example of Setting of Consecutively Capturing A/D Conversion Results
Start
DEN1 = 1
DSA1 = 1EH
DRA1 = FCE0H
DBC1 = 0100H
DMC1 = 2CH
DST1 = 1
Starting A/D conversion
INTAD occurs.
User program
processing
DMA1 transfer
INTDMA1 occurs.
DST1 = 0Note
DEN1 = 0
RETI
Hardware operation
End
Note The DST1 flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DEN1 flag is enabled only when DST1 = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMA1 (INTDMA1), set DST1 to 0 and then DEN1 to 0 (for details, refer to 18.5.7
Forced termination by software).
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CHAPTER 18 DMA CONTROLLER
18.5.5 UART consecutive reception + ACK transmission
A flowchart illustrating an example of setting for UART consecutive reception + ACK transmission is shown below.
• Consecutively receives data from UART0 and outputs ACK to P10 on completion of reception.
• DMA channel 0 is used for DMA transfer.
• DMA start source: Software trigger (DMA transfer on occurrence of an interrupt is disabled.)
• Transfers FFF12H of UART receive data register 0 (RXD0) to 64 bytes of FFE00H to FFE3FH of RAM.
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Figure 18-11. Example of Setting for UART Consecutive Reception + ACK Transmission
Start
INTSR0 interrupt routine
DEN0 = 1
DSA0 = 12H
STG0 = 1
DRA0 = FE00H
DBC0 = 0040H
DMC0 = 00H
DMA0 transfer
P10 = 1
Setting for UART reception
P10 = 0
DST0 = 1
INTSR0 occurs.
RETI
User program
processing
INTDMA0
occurs.
DST0 = 0
DEN0 = 0Note
RETI
Hardware operation
End
Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMA0 (INTDMA0), set DST0 to 0 and then DEN0 to 0 (for details, refer to 18.5.7
Forced termination by software).
Remark
This is an example where a software trigger is used as a DMA start source.
If ACK is not transmitted and if only data is consecutively received from UART, the UART reception end
interrupt (INTSR0) can be used to start DMA for data reception.
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CHAPTER 18 DMA CONTROLLER
18.5.6 Holding DMA transfer pending by DWAITn
When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of the
CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set system, a
DMA transfer can be held pending by setting the DWAITn bit to 1. The DMA transfer for a transfer trigger that occurred
while DMA transfer was held pending is executed after the pending status is canceled. However, because only one
transfer trigger can be held pending for each channel, even if multiple transfer triggers occur for one channel during the
pending status, only one DMA transfer is executed after the pending status is canceled.
To output a pulse with a width of 10 clocks of the operating frequency from the P10 pin, for example, the clock width
increases to 12 if a DMA transfer is started midway. In this case, the DMA transfer can be held pending by setting the
DWAITn bit to 1.
After setting the DWAITn bit to 1, it takes two clocks until a DMA transfer is held pending.
Figure 18-12. Example of Setting for Holding DMA Transfer Pending by DWAITn
Starting DMA transfer
Main program
DWAITn = 1
Wait for 2 clocks
P10 = 1
Wait for 9 clocks
P10 = 0
DWAITn = 0
Caution
When DMA transfer is held pending while using both DMA channels, be sure to held the DMA
transfer pending for both channels (by setting DWAIT0 and DWAIT1 to 1). If the DMA transfer of
one channel is executed while that of the other channel is held pending, DMA transfer might not be
held pending for the latter channel.
Remarks 1. n: DMA channel number (n = 0, 1)
2. 1 clock: 1/fCLK (fCLK: CPU clock)
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18.5.7 Forced termination by software
After DSTn is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and DSTn is set to 0.
To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn) of DMAn,
therefore, perform either of the following processes.
• Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software, confirm by polling
that the DSTn bit has actually been cleared to 0, and then set the DENn bit to 0 (use DRCn = 00H to write with an 8bit manipulation instruction).
• Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software and then set the
DENn bit to 0 (use DRCn = 00H to write with an 8-bit manipulation instruction) two or more clocks after.
• To forcibly terminate DMA transfer by software when using both DMA channels (by setting DSTn to 0), clear the
DSTn bit to 0 after the DMA transfer is held pending by setting the DWAIT0 and DWAIT1 bits of both channels to 1.
Next, clear the DWAIT0 and DWAIT1 bits of both channels to 0 to cancel the pending status, and then clear the
DENn bit to 0.
Figure 18-13. Forced Termination of DMA Transfer (1/2)
Example 1
Example 2
DSTn = 0
DSTn = 0
No
2 clock wait
DSTn = 0 ?
Yes
DENn = 0
DENn = 0
Remarks 1. n: DMA channel number (n = 0, 1)
2. 1 clock: 1/fCLK (fCLK: CPU clock)
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Figure 18-13. Forced Termination of DMA Transfer (2/2)
Example 3
• Procedure for forcibly terminating the DMA
transfer for one channel if both channels are used
• Procedure for forcibly terminating the DMA
transfer for both channels if both channels are used
DWAIT0 = 1
DWAIT0 = 1
DWAIT1 = 1
DWAIT1 = 1
DSTn = 0
DST0 = 0
DST1 = 0
DWAIT0 = 0
DWAIT1 = 0
DWAIT0 = 0
DWAIT1 = 0
DENn = 0
DEN0 = 0
DEN1 = 0
Caution In example 3, the system is not required to wait two clock cycles after the DWAITn bit is set to 1. In
addition, the system does not have to wait two clock cycles after clearing the DSTn bit to 0,
because more than two clock cycles elapse from when the DSTn bit is cleared to 0 to when the
DENn bit is cleared to 0.
Remarks 1. n: DMA channel number (n = 0, 1)
2. 1 clock: 1/fCLK (fCLK: CPU clock)
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18.6 Cautions on Using DMA Controller
(1) Priority of DMA
During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending
DMA transfer is started after the ongoing DMA transfer is completed. If two DMA requests are generated at the
same time, however, DMA channel 0 takes priority over DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA transfer takes precedence,
and then interrupt servicing is executed.
(2) DMA response time
The response time of DMA transfer is as follows.
Table 17-2. Response Time of DMA Transfer
Minimum Time
Response time
3 clocks
Maximum Time
Note
10 clocks
Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles.
Cautions 1. The above response time does not include the two clock cycles required for a DMA
transfer.
2. When executing a DMA pending instruction (see 18.6 (4)), the maximum response
time is extended by the execution time of that instruction to be held pending.
3. Do not specify successive transfer triggers for a channel within a period equal to the
maximum response time plus one clock cycle, because they might be ignored.
Remark
1 clock: 1/fCLK (fCLK: CPU clock)
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(3) Operation in standby mode
The DMA controller operates as follows in the standby mode.
Table 18-3. DMA Operation in Standby Mode
Status
DMA Operation
HALT mode
Normal operation
STOP mode
Stops operation.
If DMA transfer and STOP instruction execution contend, DMA transfer may be
damaged. Therefore, stop DMA before executing the STOP instruction.
(4) DMA pending instruction
Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions.
• CALL
!addr16
• CALL
$!addr20
• CALL
!!addr20
• CALL
rp
• CALLT
[addr5]
• BRK
• Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L, MK0H, MK1L, MK1H,
MK2L, MK2H, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L,
PR12H and PSW each.
(5) Operation if address in general-purpose register area or other than those of internal RAM area is specified
The address indicated by DRA0n is incremented during DMA transfer. If the address is incremented to an
address in the general-purpose register area or exceeds the area of the internal RAM, the following operation is
performed.
z In mode of transfer from SFR to RAM
The data of that address is lost.
z In mode of transfer from RAM to SFR
Undefined data is transferred to SFR.
In either case, malfunctioning may occur or damage may be done to the system. Therefore, make sure that the
address is within the internal RAM area other than the general-purpose register area.
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose registers
Internal RAM
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CHAPTER 19 INTERRUPT FUNCTIONS
CHAPTER 19 INTERRUPT FUNCTIONS
78K0R/LF3
78K0R/FG3
78K0R/LH3
80 pins
100 pins
128 pins
Maskable
External
30
33
33
interrupts
internal
8
12
13
19.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into four priority groups by setting the
priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H,
PR12L, PR12H).
Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If two
or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed
according to the priority of vectored interrupt servicing. For the priority order, see Table 19-1.
A standby release signal is generated and STOP and HALT modes are released.
External interrupt requests and internal interrupt requests are provided as maskable interrupts.
(2) Software interrupt
This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are
disabled. The software interrupt does not undergo interrupt priority control.
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19.2 Interrupt Sources and Configuration
The interrupt sources consist of maskable interrupts and software interrupts. In addition, they also have up to five reset
sources (see Table 19-1). The vector codes that store the program start address when branching due to the generation of
a reset or various interrupt requests are two bytes each, so interrupts jump to a 64 K address of 00000H to 0FFFFH.
Table 19-1. Interrupt Source List (1/3)
Interrupt
Type
Internal/
Basic
Default
Interrupt Source
Note 2
External Configuration Priority
Name
Type
Trigger
Vector
LF
LG
LH
Table
3
3
3
00004H
√
√
√
00006H
√
√
√
Address
Note 1
Maskable
Internal
(A)
0
INTWDTI
Watchdog timer interval
Note 3
(75% of overflow time)
External
Internal
(B)
(A)
INTLVI
Low-voltage detection
2
INTP0
Pin input edge detection
00008H
√
√
√
3
INTP1
0000AH
√
√
√
4
INTP2
0000CH
√
√
√
5
INTP3
0000EH
√
√
√
6
INTP4
00010H
√
√
√
7
INTP5
00012H
√
√
√
8
INTST3
End of UART3 transmission
00014H
√
√
√
9
INTSR3
End of UART3 reception
00016H
√
√
√
10
INTSRE3
UART3 reception error occurrence
00018H
√
√
√
11
INTDMA0
End of DMA0 transfer
0001AH
√
√
√
12
INTDMA1
End of DMA1 transfer
0001CH
√
√
√
13
INTST0
End of UART0 transmission
0001EH
−
√
√
INTCSI00
End of CSI00 communication
−
√
√
INTSR0
End of UART0 reception
−
√
√
INTCSI01
End of CSI01 communication
−
−
√
15
INTSRE0
CSI01/UART0 reception error occurrence
00022H
√
√
√
16
INTST1
End of UART1 transmission
00024H
√
√
√
√
√
√
14
Notes 1.
Note 4
1
00020H
INTCSI10
End of CSI10 communication
INTIIC10
End of IIC10 communication
√
√
√
17
INTSR1
End of UART1 reception
00026H
√
√
√
18
INTSRE1
UART1 reception error occurrence
00028H
√
√
√
19
INTIICA
End of IICA communication
0002AH
−
√
√
20
INTTM00
End of timer channel 0 count or capture
0002CH
√
√
√
The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 45 indicates the lowest priority.
2.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 19-1.
3.
When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
4.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
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Table 19-1. Interrupt Source List (2/3)
Interrupt
Type
Internal/
Basic
Default
Interrupt Source
Note 2
External Configuration Priority
Vector
LF
LG
LH
Table
3
3
3
Name
Trigger
21
INTTM01
End of timer channel 1 count or capture
0002EH
√
√
√
22
INTTM02
End of timer channel 2 count or capture
00030H
√
√
√
23
INTTM03
End of timer channel 3 count or capture
00032H
√
√
√
24
INTAD
End of A/D conversion
00034H
√
√
√
25
INTRTC
Fixed-cycle signal of real-time
00036H
√
√
√
00038H
√
√
√
Key return signal detection
0003AH
−
−
√
0003CH
Type
Address
Note 1
Maskable
Internal
(A)
counter/alarm match detection
26
INTRTCI
Interval signal detection of real-time
counter
External
(C)
27
INTKR
Internal
(A)
28
INTST2
End of UART2 transmission/
√
√
√
INTCSI20
End of CSI20 communication/
√
√
√
INTIIC20
End of IIC20 communication
√
√
√
29
INTSR2
End of UART2 reception
0003EH
√
√
√
30
INTSRE2
UART2 reception error occurrence
00040H
√
√
√
31
INTTM04
End of timer channel 4 count or capture
00042H
√
√
√
32
INTTM05
End of timer channel 5 count or capture
00044H
√
√
√
33
INTTM06
End of timer channel 6 count or capture
00046H
√
√
√
34
INTTM07
End of timer channel 7 count or capture
00048H
√
√
√
35
INTP6
Pin input edge detection
0004AH
√
√
√
36
INTP7
0004CH
√
√
√
37
INTP8
0004EH
−
√
√
38
INTP9
00050H
−
√
√
39
INTP10
00052H
−
√
√
40
INTP11
00054H
−
√
√
External
Notes 1.
(B)
The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 45 indicates the lowest priority.
2.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 19-1.
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Table 19-1. Interrupt Source List (3/3)
Interrupt
Type
Internal/
Basic
Default
Interrupt Source
Note 2
External Configuration Priority
Name
Type
Trigger
Vector
LF
LG
LH
Table
3
3
3
00056H
√
√
√
00058H
√
√
√
0005AH
√
√
√
0005CH
√
√
√
Address
Note 1
Maskable
Internal
(A)
41
INTTM10
End of timer channel 10 count or
capture
42
INTTM11
End of timer channel 11 count or
capture
43
INTTM12
End of timer channel 12 count or
capture
44
INTTM13
End of timer channel 13 count or
capture
45
INTMD
End of multiply/divide operation
0005EH
√
√
√
Software
−
(D)
−
BRK
Execution of BRK instruction
0007EH
√
√
√
Reset
−
−
−
RESET
RESET pin input
00000H
√
√
√
POC
Power-on-clear
√
√
√
√
√
√
√
√
√
√
√
√
LVI
Low-voltage detection
WDT
Overflow of watchdog timer
TRAP
Notes 1.
Note 3
Note 4
Execution of illegal instruction
The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 45 indicates the lowest priority.
2.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 19-1.
3.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1.
4.
When the instruction code in FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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Figure 19-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal maskable interrupt
Internal bus
MK
Interrupt
request
IE
PR1
PR0
ISP1
Vector table
address generator
Priority controller
IF
ISP0
Standby release
signal
(B) External maskable interrupt (INTPn)
Internal bus
External interrupt edge
enable register
(EGP, EGN)
Interrupt
request
Edge
detector
MK
IF
IE
PR1
PR0
Priority controller
ISP1
ISP0
Vector table
address generator
Standby release
signal
IF:
Interrupt request flag
IE:
Interrupt enable flag
ISP0:
In-service priority flag 0
ISP1:
In-service priority flag 1
MK:
Interrupt mask flag
PR0:
Priority specification flag 0
PR1:
Priority specification flag 1
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Figure 19-1. Basic Configuration of Interrupt Function (2/2)
(C) External maskable interrupt (INTKR)
Internal bus
Key return mode
register (KRM)
MK
IE
PR1
PR0
ISP1
ISP0
KRMn
KRn pin input
Key
interrupt
detector
Priority controller
IF
Vector table
address generator
Standby release
signal
(D) Software interrupt
Internal bus
Interrupt
request
IF:
Interrupt request flag
IE:
Interrupt enable flag
ISP0:
In-service priority flag 0
ISP1:
In-service priority flag 1
MK:
Interrupt mask flag
PR0:
Priority specification flag 0
PR1:
Priority specification flag 1
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CHAPTER 19 INTERRUPT FUNCTIONS
19.3 Registers Controlling Interrupt Functions
The following 6 types of registers are used to control the interrupt functions.
• Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)
• Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
• Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, PR12H)
• External interrupt rising edge enable registers (EGP0, EGP1)
• External interrupt falling edge enable registers (EGN0, EGN1)
• Program status word (PSW)
Table 19-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to
interrupt request sources.
Table 19-2. Flags Corresponding to Interrupt Request Sources (1/2)
LF3
LG3
LH3
Interrupt
Interrupt Request Flag
Source
Interrupt Mask Flag
Register
√
√
√
INTWDTI
WDTIIF
√
√
√
INTLVI
LVIIF
√
√
√
INTP0
√
√
√
√
√
√
IF0L
Priority Specification Flag
Register
MK0L
Register
WDTIPR0, WDTIPR1
PR00L,
LVIMK
LVIPR0, LVIPR1
PR10L
PIF0
PMK0
PPR00, PPR10
INTP1
PIF1
PMK1
PPR01, PPR11
√
INTP2
PIF2
PMK2
PPR02, PPR12
√
√
INTP3
PIF3
PMK3
PPR03, PPR13
√
√
√
INTP4
PIF4
PMK4
PPR04, PPR14
√
√
√
INTP5
PIF5
PMK5
PPR05, PPR15
√
√
√
INTST3
STIF3
√
√
√
INTSR3
SRIF3
√
√
√
INTSRE3
√
√
√
√
√
√
−
√
√
INTST0
−
√
√
INTCSI00
−
√
√
−
−
√
INTCSI01
√
√
√
INTSRE0
WDTIMK
STPR03, STPR13
PR00H,
SRMK3
SRPR03, SRPR13
PR10H
SREIF3
SREMK3
SREPR03, SREPR13
INTDMA0
DMAIF0
DMAMK0
DMAPR00, DMAPR10
INTDMA1
DMAIF1
DMAMK1
DMAPR01, DMAPR11
INTSR0
Note 1
Note 1
Note 2
Note 2
STIF0
IF0H
Note 1
CSIIF00
SRIF0
Note 1
Note 2
CSIIF01
SREIF0
Note 2
STMK3
STMK0
MK0H
Note 1
CSIMK00
SRMK0
Note 1
Note 2
CSIMK01
Note 2
SREMK0
STPR00, STPR10
Note 1
CSIPR000, CSIPR100
SRPR00, SRPR10
Note1
Note 2
CSIPR001, CSIPR101
Note2
SREPR00, SREPR10
Notes 1. Do not use UART0 and CSI00 at the same time because they share flags for the interrupt request sources.
If one of the interrupt sources INTST0 and INTCSI00 is generated, bit 5 of IF1H is set to 1. Bit 5 of MK0H,
PR00H, and PR10H supports these two interrupt sources.
2. Do not use UART0 and CSI01 at the same time because they share flags for the interrupt request sources.
If one of the interrupt sources INTSR0 and INTCSI01 is generated, bit 6 of IF0H is set to 1. Bit 6 of MK0H,
PR00H, and PR10H supports these two interrupt sources.
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Table 19-2. Flags Corresponding to Interrupt Request Sources (2/2)
LF3
LG3
LH3
Interrupt
Interrupt Request Flag
Source
√
√
√
√
√
√
INTCSI10
√
√
√
INTIIC10
√
√
√
√
√
−
INTST1
Note 1
Note 1
Note 1
Interrupt Mask Flag
Register
STIF1
Note 1
IF1L
Note 1
CSIIF10
Register
STMK1
Note 1
CSIMK10
Note 1
Priority Specification Flag
MK1L
Note 1
Register
STPR01, STPR11
Note 1
Note1
CSIPR010, CSIPR110
Note 1
IICMK10
INTSR1
SRIF1
SRMK1
SRPR01, SRPR11
√
INTSRE1
SREIF1
SREMK1
SREPR01, SREPR11
√
√
INTIICA
IICAIF
IICAMK
IICAPR0, IICAPR1
√
√
√
INTTM00
TMIF00
TMMK00
TMPR000, TMPR100
√
√
√
INTTM01
TMIF01
TMMK01
TMPR001, TMPR101
√
√
√
INTTM02
TMIF02
TMMK02
TMPR002, TMPR102
√
√
√
INTTM03
TMIF03
TMMK03
TMPR003, TMPR103
√
√
√
INTAD
ADIF
√
√
√
INTRTC
RTCIF
√
√
√
INTRTCI
−
−
√
INTKR
√
√
√
INTST2
√
√
√
INTCSI20
√
√
√
INTIIC20
√
√
√
√
√
√
√
Note 2
Note 2
Note 2
PR11L
Note 1
IICIF10
IICPR010, IICPR110
ADPR0, ADPR1
PR01H,
RTCMK
RTCPR0, RTCPR1
PR11H
RTCIIF
RTCIMK
RTCIPR0, RTCIPR1
KRIF
KRMK
KRPR0, KRPR1
STIF2
IF1H
PR01L,
Note 2
STMK2
Note 2
CSIIF20
MK1H
ADMK
Note 2
CSIMK20
Note 2
STPR02, STPR12
Note 2
Note 2
Note2
CSIPR020, CSIPR120
Note 2
Note 2
IICIF20
IICMK20
IICPR020, IICPR120
INTSR2
SRIF2
SRMK2
SRPR02, SRPR12
√
INTSRE2
SREIF2
SREMK2
SREPR02, SREPR12
√
√
INTTM04
TMIF04
√
√
INTTM05
TMIF05
√
√
√
INTTM06
TMIF06
√
√
√
INTTM07
√
√
√
√
√
−
TMMK04
TMPR004, TMPR104
TMPR005, TMPR105
PR02L,
TMMK06
TMPR006, TMPR106
PR12L
TMIF07
TMMK07
TMPR007, TMPR107
INTP6
PIF6
PMK6
PPR06, PPR16
√
INTP7
PIF7
PMK7
PPR07, PPR17
√
√
INTP8
PIF8
PMK8
PPR08, PPR18
−
√
√
INTP9
PIF9
PMK9
PPR09, PPR19
−
√
√
INTP10
PIF10
−
√
√
INTP11
PIF11
√
√
√
INTTM10
TMIF10
√
√
√
INTTM11
√
√
√
√
√
√
√
IF2L
TMMK05
MK2L
PMK10
PPR010, PPR110
PPR011, PPR111
PR02H,
TMMK10
TMPR010, TMPR110
PR12H
TMIF11
TMMK11
TMPR011, TMPR111
INTTM12
TMIF12
TMMK12
TMPR012, TMPR112
√
INTTM13
TMIF13
TMMK13
TMPR013, TMPR113
√
INTMD
MDIF
MDMK
MDPR0, MDPR1
IF2H
PMK11
MK2H
Notes 1. Do not use UART1, CSI10, and IIC10 at the same time because they share flags for the interrupt request
sources. If one of the interrupt sources INTST1, INTCSI10, and INTIIC10 is generated, bit 0 of IF1L is set to
1. Bit 0 of MK1L, PR01L, and PR11L supports these three interrupt sources.
2. Do not use UART2, CSI20, and IIC20 at the same time because they share flags for the interrupt request
sources. If one of the interrupt sources INTST2, INTCSI20, and INTIIC20 is generated, bit 4 of IF1H is set to
1. Bit 4 of MK1H, PR01H, and PR11H supports these three interrupt sources.
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CHAPTER 19 INTERRUPT FUNCTIONS
(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is
entered.
IF0L, IF0H, IF1L, IF1H, IF2L, and IF2H can be set by a 1-bit or 8-bit memory manipulation instruction. When IF0L
and IF0H, IF1L and IF1H, and IF2L and IF2H are combined to form 16-bit registers IF0, IF1, and IF2, they can be set
by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Cautions 1. When operating a timer, serial interface, or A/D converter after standby release, operate it once
after clearing the interrupt request flag. An interrupt request flag may be set by noise.
2. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation
instruction (CLR1). When describing in C language, use a bit manipulation instruction such as
“IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler must be a 1-bit memory
manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction such as
“IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of another bit of the same interrupt request flag register
(IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is cleared to 0
at “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit memory manipulation
instruction in C language.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
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CHAPTER 19 INTERRUPT FUNCTIONS
Figure 19-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (78K0R/LF3)
Address: FFFE0H
After reset: 00H
R/W
Symbol
IF0L
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
LVIIF
WDTIIF
Address: FFFE1H
After reset: 00H
R/W
Symbol
6
5
IF0H
SREIF0
0
0
DMAIF1
DMAIF0
SREIF3
SRIF3
STIF3
Address: FFFE2H
After reset: 00H
R/W
Symbol
3
IF1L
TMIF03
TMIF02
TMIF01
TMIF00
0
SREIF1
SRIF1
CSIIF10
IICIF10
STIF1
Address: FFFE3H
After reset: 00H
R/W
Symbol
3
IF1H
TMIF04
SREIF2
SRIF2
CSIIF20
0
RTCIIF
RTCIF
ADIF
IICIF20
STIF2
Address: FFFD0H
After reset: 00H
R/W
Symbol
7
6
5
IF2L
0
0
0
PIF7
PIF6
TMIF07
TMIF06
TMIF05
Address: FFFD1H
After reset: 00H
R/W
Symbol
7
6
0
IF2H
0
0
MDIF
TMIF13
TMIF12
TMIF11
TMIF10
0
XXIFX
Caution
Interrupt request flag
0
No interrupt request signal is generated
1
Interrupt request is generated, interrupt request status
Be sure to clear bits 5, 6 of IF0H, bit 3 of IF1L, bit 3 of IF1H, bits 5 to 7 of IF2L, bits 0, 6, 7 of IF2H to
0.
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CHAPTER 19 INTERRUPT FUNCTIONS
Figure 19-3. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (78K0R/LG3)
Address: FFFE0H
After reset: 00H
R/W
Symbol
IF0L
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
LVIIF
WDTIIF
Address: FFFE1H
After reset: 00H
R/W
Symbol
IF0H
SREIF0
SRIF0
CSIIF00
DMAIF1
DMAIF0
SREIF3
SRIF3
STIF3
STIF0
Address: FFFE2H
After reset: 00H
R/W
Symbol
IF1L
TMIF03
TMIF02
TMIF01
TMIF00
IICAIF
SREIF1
SRIF1
CSIIF10
IICIF10
STIF1
Address: FFFE3H
After reset: 00H
R/W
Symbol
3
IF1H
TMIF04
SREIF2
SRIF2
CSIIF20
0
RTCIIF
RTCIF
ADIF
IICIF20
STIF2
Address: FFFD0H
After reset: 00H
R/W
Symbol
IF2L
PIF10
PIF9
PIF8
PIF7
PIF6
TMIF07
TMIF06
TMIF05
Address: FFFD1H
After reset: 00H
R/W
Symbol
7
6
IF2H
0
0
MDIF
TMIF13
TMIF12
TMIF11
TMIF10
PIF11
XXIFX
Caution
Interrupt request flag
0
No interrupt request signal is generated
1
Interrupt request is generated, interrupt request status
Be sure to clear bit 3 of IF1H, bits 6, 7 of IF2H to 0.
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CHAPTER 19 INTERRUPT FUNCTIONS
Figure 19-4. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (78K0R/LH3)
Address: FFFE0H
After reset: 00H
R/W
Symbol
IF0L
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
LVIIF
WDTIIF
Address: FFFE1H
After reset: 00H
R/W
Symbol
IF0H
SREIF0
CSIIF01
CSIIF00
DMAIF1
DMAIF0
SREIF3
SRIF3
STIF3
SRIF0
STIF0
Address: FFFE2H
After reset: 00H
R/W
Symbol
IF1L
TMIF03
TMIF02
TMIF01
TMIF00
IICAIF
SREIF1
SRIF1
CSIIF10
IICIF10
STIF1
Address: FFFE3H
After reset: 00H
R/W
Symbol
IF1H
TMIF04
SREIF2
SRIF2
CSIIF20
KRIF
RTCIIF
RTCIF
ADIF
IICIF20
STIF2
Address: FFFD0H
After reset: 00H
R/W
Symbol
IF2L
PIF10
PIF9
PIF8
PIF7
PIF6
TMIF07
TMIF06
TMIF05
Address: FFFD1H
After reset: 00H
R/W
Symbol
7
6
IF2H
0
0
MDIF
TMIF13
TMIF12
TMIF11
TMIF10
PIF11
XXIFX
Caution
Interrupt request flag
0
No interrupt request signal is generated
1
Interrupt request is generated, interrupt request status
Be sure to clear bits 6, 7 of IF2H to 0.
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CHAPTER 19 INTERRUPT FUNCTIONS
(2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
MK0L, MK0H, MK1L, MK1H, MK2L, and MK2H can be set by a 1-bit or 8-bit memory manipulation instruction. When
MK0L and MK0H, MK1L and MK1H, and MK2L and MK2H are combined to form 16-bit registers MK0, MK1, and MK2,
they can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 19-5. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) (78K0R/LF3)
Address: FFFE4H
After reset: FFH
R/W
Symbol
MK0L
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
LVIMK
WDTIMK
Address: FFFE5H
After reset: FFH
R/W
Symbol
6
5
MK0H
SREMK0
1
1
DMAMK1
DMAMK0
SREMK3
SRMK3
STMK3
Address: FFFE6H
After reset: FFH
R/W
Symbol
3
MK1L
TMMK03
TMMK02
TMMK01
TMMK00
1
SREMK1
SRMK1
CSIMK10
IICMK10
STMK1
Address: FFFE7H
After reset: FFH
R/W
Symbol
3
MK1H
TMMK04
SREMK2
SRMK2
CSIMK20
1
RTCIMK
RTCMK
ADMK
IICMK20
STMK2
Address: FFFD4H
After reset: FFH
R/W
Symbol
7
6
5
MK2L
1
1
1
PMK7
PMK6
TMMK07
TMMK06
TMMK05
Address: FFFD5H
After reset: FFH
R/W
Symbol
7
6
0
MK2H
1
1
MDMK
TMMK13
TMMK12
TMMK11
TMMK10
1
XXMKX
Interrupt servicing control
0
Interrupt servicing enabled
1
Interrupt servicing disabled
Caution Be sure to set bits 5, 6 of MK0H, bit 3 of MK1L, bit 3 of MK1H, bits 5 to 7 of MK2L, bits 0, 6, 7 of MK2H
to 1.
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CHAPTER 19 INTERRUPT FUNCTIONS
Figure 19-6. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) (78K0R/LG3)
Address: FFFE4H
After reset: FFH
R/W
Symbol
MK0L
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
LVIMK
WDTIMK
Address: FFFE5H
After reset: FFH
R/W
Symbol
MK0H
SREMK0
SRMK0
CSIMK00
DMAMK1
DMAMK0
SREMK3
SRMK3
STMK3
STMK0
Address: FFFE6H
After reset: FFH
R/W
Symbol
MK1L
TMMK03
TMMK02
TMMK01
TMMK00
IICAMK
SREMK1
SRMK1
CSIMK10
IICMK10
STMK1
Address: FFFE7H
After reset: FFH
R/W
Symbol
3
MK1H
TMMK04
SREMK2
SRMK2
CSIMK20
1
RTCIMK
RTCMK
ADMK
IICMK20
STMK2
Address: FFFD4H
After reset: FFH
R/W
Symbol
MK2L
PMK10
PMK9
PMK8
PMK7
PMK6
TMMK07
TMMK06
TMMK05
Address: FFFD5H
After reset: FFH
R/W
Symbol
7
6
MK2H
1
1
MDMK
TMMK13
TMMK12
TMMK11
TMMK10
PMK11
XXMKX
Interrupt servicing control
0
Interrupt servicing enabled
1
Interrupt servicing disabled
Caution Be sure to set bit 3 of MK1H, bits 6, 7 of MK2H to 1.
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CHAPTER 19 INTERRUPT FUNCTIONS
Figure 19-7. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) (78K0R/LH3)
Address: FFFE4H
After reset: FFH
R/W
Symbol
MK0L
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
LVIMK
WDTIMK
Address: FFFE5H
After reset: FFH
R/W
Symbol
MK0H
SREMK0
CSIMK01
CSIMK00
DMAMK1
DMAMK0
SREMK3
SRMK3
STMK3
SRMK0
STMK0
Address: FFFE6H
After reset: FFH
R/W
Symbol
MK1L
TMMK03
TMMK02
TMMK01
TMMK00
IICAMK
SREMK1
SRMK1
CSIMK10
IICMK10
STMK1
Address: FFFE7H
After reset: FFH
R/W
Symbol
MK1H
TMMK04
SREMK2
SRMK2
CSIMK20
KRMK
RTCIMK
RTCMK
ADMK
IICMK20
STMK2
Address: FFFD4H
After reset: FFH
R/W
Symbol
MK2L
PMK10
PMK9
PMK8
PMK7
PMK6
TMMK07
TMMK06
TMMK05
Address: FFFD5H
After reset: FFH
R/W
Symbol
7
6
MK2H
1
1
MDMK
TMMK13
TMMK12
TMMK11
TMMK10
PMK11
XXMKX
Interrupt servicing control
0
Interrupt servicing enabled
1
Interrupt servicing disabled
Caution Be sure to set bits 6, 7 of MK2H to 1.
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CHAPTER 19 INTERRUPT FUNCTIONS
(3) Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, PR12H)
The priority specification flag registers are used to set the corresponding maskable interrupt priority level.
A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, or 2H).
PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, and PR12H can be set by
a 1-bit or 8-bit memory manipulation instruction. If PR00L and PR00H, PR01L and PR01H, PR02L and PR02H,
PR10L and PR10H, PR11L and PR11H, and PR12L and PR12H are combined to form 16-bit registers PR00, PR01,
PR02, PR10, PR11, and PR12, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 19-8. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (78K0R/LF3) (1/2)
Address: FFFE8H
After reset: FFH
R/W
Symbol
PR00L
PPR05
PPR04
PPR03
PPR02
PPR01
PPR00
LVIPR0
WDTIPR0
Address: FFFECH
After reset: FFH
R/W
Symbol
PR10L
PPR15
PPR14
PPR13
PPR12
PPR11
PPR10
LVIPR1
WDTIPR1
Address: FFFE9H
After reset: FFH
R/W
Symbol
6
5
PR00H
SREPR00
1
1
DMAPR01
DMAPR00
SREPR03
SRPR03
STPR03
Address: FFFEDH
After reset: FFH
R/W
Symbol
6
5
PR10H
SREPR10
1
1
DMAPR11
DMAPR10
SREPR13
SRPR13
STPR13
Address: FFFEAH
After reset: FFH
R/W
Symbol
3
PR01L
TMPR003
TMPR002
TMPR001
TMPR000
1
SREPR01
SRPR01
CSIPR010
IICPR010
STPR01
Address: FFFEEH
After reset: FFH
R/W
Symbol
3
PR11L
TMPR103
TMPR102
TMPR101
TMPR100
1
SREPR11
SRPR11
CSIPR110
IICPR110
STPR11
Caution Be sure to set bits 5, 6 of PR00H and PR10H, bit 3 of PR01L and PR11L to 1.
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Figure 19-8. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (78K0R/LF3) (2/2)
Address: FFFEBH
After reset: FFH
R/W
Symbol
3
PR01H
TMPR004
SREPR02
SRPR02
CSIPR020
1
RTCIPR0
RTCPR0
ADPR0
IICPR020
STPR02
Address: FFFEFH
After reset: FFH
R/W
Symbol
3
PR11H
TMPR104
SREPR12
SRPR12
CSIPR120
1
RTCIPR1
RTCPR1
ADPR1
IICPR120
STPR12
Address: FFFD8H
After reset: FFH
R/W
Symbol
7
6
5
PR02L
1
1
1
PPR07
PPR06
TMPR007
TMPR006
TMPR005
Address: FFFDCH
After reset: FFH
R/W
Symbol
7
6
5
PR12L
1
1
1
PPR17
PPR16
TMPR107
TMPR106
TMPR105
Address: FFFD9H
After reset: FFH
R/W
Symbol
7
6
0
PR02H
1
1
MDPR0
TMPR013
TMPR012
TMPR011
TMPR010
1
Address: FFFDDH
After reset: FFH
R/W
Symbol
7
6
0
PR12H
1
1
MDPR1
TMPR113
TMPR112
TMPR111
TMPR110
1
XXPR1X
XXPR0X
0
0
Specify level 0 (high priority level)
0
1
Specify level 1
1
0
Specify level 2
1
1
Specify level 3 (low priority level)
Priority level selection
Caution Be sure to set bit 3 of PR01H and PR11H, bits 5 to 7 of PR02L and PR12L, bits 0, 6, 7 of PR02H and
PR12H to 1.
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Figure 19-9. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (78K0R/LG3) (1/2)
Address: FFFE8H
After reset: FFH
R/W
Symbol
PR00L
PPR05
PPR04
PPR03
PPR02
PPR01
PPR00
LVIPR0
WDTIPR0
Address: FFFECH
After reset: FFH
R/W
Symbol
PR10L
PPR15
PPR14
PPR13
PPR12
PPR11
PPR10
LVIPR1
WDTIPR1
Address: FFFE9H
After reset: FFH
R/W
Symbol
PR00H
SREPR00
SRPR00
CSIPR000
DMAPR01
DMAPR00
SREPR03
SRPR03
STPR03
STPR00
Address: FFFEDH
After reset: FFH
R/W
Symbol
PR10H
SREPR10
SRPR10
CSIPR100
DMAPR11
DMAPR10
SREPR13
SRPR13
STPR13
STPR10
Address: FFFEAH
After reset: FFH
R/W
Symbol
PR01L
TMPR003
TMPR002
TMPR001
TMPR000
IICAPR0
SREPR01
SRPR01
CSIPR010
IICPR010
STPR01
Address: FFFEEH
After reset: FFH
R/W
Symbol
PR11L
TMPR103
TMPR102
TMPR101
TMPR100
IICAPR1
SREPR11
SRPR11
CSIPR110
IICPR110
STPR11
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Figure 19-9. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (78K0R/LG3) (2/2)
Address: FFFEBH
After reset: FFH
R/W
Symbol
3
PR01H
TMPR004
SREPR02
SRPR02
CSIPR020
1
RTCIPR0
RTCPR0
ADPR0
IICPR020
STPR02
Address: FFFEFH
After reset: FFH
R/W
Symbol
3
PR11H
TMPR104
SREPR12
SRPR12
CSIPR120
1
RTCIPR1
RTCPR1
ADPR1
IICPR120
STPR12
Address: FFFD8H
After reset: FFH
R/W
Symbol
PR02L
PPR010
PPR09
PPR08
PPR07
PPR06
TMPR007
TMPR006
TMPR005
Address: FFFDCH
After reset: FFH
R/W
Symbol
PR12L
PPR110
PPR19
PPR18
PPR17
PPR16
TMPR107
TMPR106
TMPR105
Address: FFFD9H
After reset: FFH
R/W
Symbol
7
6
PR02H
1
1
MDPR0
TMPR013
TMPR012
TMPR011
TMPR010
PPR011
Address: FFFDDH
After reset: FFH
R/W
Symbol
7
6
PR12H
1
1
MDPR1
TMPR113
TMPR112
TMPR111
TMPR110
PPR111
XXPR1X
XXPR0X
0
0
Specify level 0 (high priority level)
0
1
Specify level 1
1
0
Specify level 2
1
1
Specify level 3 (low priority level)
Priority level selection
Caution Be sure to set bit 3 of PR01H and PR11H, bits 6, 7 of PR02H and PR12H to 1.
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Figure 19-10. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (78K0R/LH3) (1/2)
Address: FFFE8H
After reset: FFH
R/W
Symbol
PR00L
PPR05
PPR04
PPR03
PPR02
PPR01
PPR00
LVIPR0
WDTIPR0
Address: FFFECH
After reset: FFH
R/W
Symbol
PR10L
PPR15
PPR14
PPR13
PPR12
PPR11
PPR10
LVIPR1
WDTIPR1
Address: FFFE9H
After reset: FFH
R/W
Symbol
PR00H
SREPR00
CSIPR001
CSIPR000
DMAPR01
DMAPR00
SREPR03
SRPR03
STPR03
SRPR00
STPR00
Address: FFFEDH
After reset: FFH
R/W
Symbol
PR10H
SREPR10
CSIPR101
CSIPR100
DMAPR11
DMAPR10
SREPR13
SRPR13
STPR13
SRPR10
STPR10
Address: FFFEAH
After reset: FFH
R/W
Symbol
PR01L
TMPR003
TMPR002
TMPR001
TMPR000
IICAPR0
SREPR01
SRPR01
CSIPR010
IICPR010
STPR01
Address: FFFEEH
After reset: FFH
R/W
Symbol
PR11L
TMPR103
TMPR102
TMPR101
TMPR100
IICAPR1
SREPR11
SRPR11
CSIPR110
IICPR110
STPR11
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Figure 19-10. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (78K0R/LH3) (2/2)
Address: FFFEBH
After reset: FFH
R/W
Symbol
PR01H
TMPR004
SREPR02
SRPR02
CSIPR020
KRPR0
RTCIPR0
RTCPR0
ADPR0
IICPR020
STPR02
Address: FFFEFH
After reset: FFH
R/W
Symbol
PR11H
TMPR104
SREPR12
SRPR12
CSIPR120
KRPR1
RTCIPR1
RTCPR1
ADPR1
IICPR120
STPR12
Address: FFFD8H
After reset: FFH
R/W
Symbol
PR02L
PPR010
PPR09
PPR08
PPR07
PPR06
TMPR007
TMPR006
TMPR005
Address: FFFDCH
After reset: FFH
R/W
Symbol
PR12L
PPR110
PPR19
PPR18
PPR17
PPR16
TMPR107
TMPR106
TMPR105
Address: FFFD9H
After reset: FFH
R/W
Symbol
7
6
PR02H
1
1
MDPR0
TMPR013
TMPR012
TMPR011
TMPR010
PPR011
Address: FFFDDH
After reset: FFH
R/W
Symbol
7
6
PR12H
1
1
MDPR1
TMPR113
TMPR112
TMPR111
TMPR110
PPR111
XXPR1X
XXPR0X
0
0
Specify level 0 (high priority level)
0
1
Specify level 1
1
0
Specify level 2
1
1
Specify level 3 (low priority level)
Priority level selection
Caution Be sure to set bits 6, 7 of PR02H and PR12H to 1.
(4) External interrupt rising edge enable registers (EGP0, EGP1), external interrupt falling edge enable registers
(EGN0, EGN1)
These registers specify the valid edge for INTP0 to INTP11.
EGP0, EGP1, EGN0, and EGN1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
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Figure 19-11. Format of External Interrupt Rising Edge Enable Registers (EGP0, EGP1) and External Interrupt
Falling Edge Enable Registers (EGN0, EGN1) (78K0R/LF3)
Address: FFF38H
Symbol
EGP0
After reset: 00H
6
5
4
3
2
1
0
EGP7
EGP6
EGP5
EGP4
EGP3
EGP2
EGP1
EGP0
Address: FFF39H
Symbol
EGN0
R/W
7
After reset: 00H
R/W
7
6
5
4
3
2
1
0
EGN7
EGN6
EGN5
EGN4
EGN3
EGN2
EGN1
EGN0
EGPn
EGNn
0
0
Edge detection disabled
0
1
Falling edge
1
0
Rising edge
1
1
Both rising and falling edges
INTPn pin valid edge selection (n = 0 to 7)
Figure 19-12. Format of External Interrupt Rising Edge Enable Registers (EGP0, EGP1) and External Interrupt
Falling Edge Enable Registers (EGN0, EGN1) (78K0R/LG3, 78K0R/LH3)
Address: FFF38H
Symbol
EGP0
After reset: 00H
7
6
5
4
3
2
1
0
EGP7
EGP6
EGP5
EGP4
EGP3
EGP2
EGP1
EGP0
Address: FFF39H
Symbol
EGN0
R/W
After reset: 00H
R/W
7
6
5
4
3
2
1
0
EGN7
EGN6
EGN5
EGN4
EGN3
EGN2
EGN1
EGN0
Address: FFF3AH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
EGP1
0
0
0
0
EGP11
EGP10
EGP9
EGP8
Address: FFF3BH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
EGN1
0
0
0
0
EGN11
EGN10
EGN9
EGN8
EGPn
EGNn
0
0
Edge detection disabled
0
1
Falling edge
1
0
Rising edge
1
1
Both rising and falling edges
INTPn pin valid edge selection (n = 0 to 11)
Table 19-3 shows the ports corresponding to EGPn and EGNn.
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Table 19-3. Ports Corresponding to EGPn and EGNn
Detection Enable Register
Edge Detection Port
Interrupt Request Signal
LF3
LG3
LH3
EGP0
EGN0
P120
INTP0
√
√
√
EGP1
EGN1
P30
INTP1
√
√
√
EGP2
EGN2
P31
INTP2
√
√
√
EGP3
EGN3
P33
INTP3
√
√
√
EGP4
EGN4
P14
INTP4
√
√
√
EGP5
EGN5
P32
INTP5
√
√
√
EGP6
EGN6
P11
INTP6
√
√
√
EGP7
EGN7
P15
INTP7
√
√
√
EGP8
EGN8
P34
INTP8
−
√
√
EGP9
EGN9
P81
INTP9
−
√
√
EGP10
EGN10
P16
INTP10
−
√
√
EGP11
EGN11
P80
INTP11
−
√
√
Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected
when the external interrupt function is switched to the port function.
Remark
n = 0 to 11
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(5) Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for an
interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls
multiple interrupt servicing are mapped to the PSW.
Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the
contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request
is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the
ISP0 and ISP1 flags. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are
restored from the stack with the RETI, RETB, and POP PSW instructions.
Reset signal generation sets PSW to 06H.
Figure 19-13. Configuration of Program Status Word
PSW
IE
Z
RBS1
AC
0
After reset
RBS0 ISP1
ISP0
CY
06H
Used when normal instruction is executed
ISP1
ISP0
0
0
Priority of interrupt currently being serviced
Enables interrupt of level 0
(while interrupt of level 1 or 0 is being serviced).
0
1
1
0
Enables interrupt of level 0 and 1
(while interrupt of level 2 is being serviced).
Enables interrupt of level 0 to 2
(while interrupt of level 3 is being serviced).
1
1
Enables all interrupts
(waits for acknowledgment of an interrupt).
IE
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0
Disabled
1
Enabled
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19.4 Interrupt Servicing Operations
19.4.1 Maskable interrupt acknowledgment
A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag
corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the
interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during
servicing of a higher priority interrupt request.
The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in
Table 19-4 below.
For the interrupt request acknowledgment timing, see Figures 19-15 and 19-16.
Table 19-4. Time from Generation of Maskable Interrupt Until Servicing
Minimum Time
Servicing time
9 clocks
Note
Maximum Time
14 clocks
Note If an interrupt request is generated just before the RET instruction, the wait time becomes longer.
Remark
1 clock: 1/fCLK (fCLK: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same priority
level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 19-14 shows the interrupt request acknowledgment algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC,
the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are
transferred to the ISP1 and ISP0 flags. The vector table data determined for each interrupt request is the loaded into the
PC and branched.
Restoring from an interrupt is possible by using the RETI instruction.
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Figure 19-14. Interrupt Request Acknowledgment Processing Algorithm
Start
No
××IF = 1?
Yes (interrupt request generation)
××MK = 0?
No
Yes
Interrupt request held pending
(××PR1, ××PR0)
≤ (ISP1, ISP0)
No (Low priority)
Interrupt request held pending
Higher priority
than other interrupt requests
simultaneously
generated?
No
Interrupt request held pending
Yes
Higher default priorityNote
than other interrupt requests
simultaneously
generated?
No
Interrupt request held pending
Yes
IE = 1?
Yes
No
Interrupt request held pending
Vectored interrupt servicing
××IF:
Interrupt request flag
××MK:
Interrupt mask flag
××PR0:
Priority specification flag 0
××PR1:
Priority specification flag 1
IE:
Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable)
ISP0, ISP1: Flag that indicates the priority level of the interrupt currently being serviced (see Figure 19-8)
Note For the default priority, refer to Table 19-1 Interrupt Source List.
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Figure 19-15. Interrupt Request Acknowledgment Timing (Minimum Time)
6 clocks
CPU processing
Instruction
Instruction
PSW and PC saved,
jump to interrupt
servicing
Interrupt servicing
program
××IF
9 clocks
Remark
1 clock: 1/fCLK (fCLK: CPU clock)
Figure 19-16. Interrupt Request Acknowledgment Timing (Maximum Time)
CPU processing
Instruction
6 clocks
6 clocks
RET instruction
PSW and PC saved,
jump to interrupt
servicing
Interrupt servicing
program
××IF
14 clocks
Remark
1 clock: 1/fCLK (fCLK: CPU clock)
19.4.2 Software interrupt request acknowledgment
A software interrupt acknowledge is acknowledged by BRK instruction execution.
Software interrupts cannot be
disabled.
If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program
status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH,
0007FH) are loaded into the PC and branched.
Restoring from a software interrupt is possible by using the RETB instruction.
Caution Do not use the RETI instruction for restoring from the software interrupt.
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19.4.3 Multiple interrupt servicing
Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE =
1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore,
to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to
enable interrupt acknowledgment.
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt
priority control. Two types of priority control are available: default priority control and programmable priority control.
Programmable priority control is used for multiple interrupt servicing.
In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently
being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that
of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt
servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they
have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is
acknowledged following execution of at least one main processing instruction execution.
Table 19-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 19-17
shows multiple interrupt servicing examples.
Table 19-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing
During Interrupt Servicing
Multiple Interrupt Request
Maskable Interrupt Request
Priority Level 0
(PR = 00)
Priority Level 2
(PR = 10)
Priority Level 3
(PR = 11)
IE = 1
IE = 0
IE = 1
IE = 0
IE = 1
IE = 0
IE = 1
IE = 0
ISP1 = 0
ISP0 = 0
{
×
×
×
×
×
×
×
{
ISP1 = 0
ISP0 = 1
{
×
{
×
×
×
×
×
{
ISP1 = 1
ISP0 = 0
{
×
{
×
{
×
×
×
{
ISP1 = 1
ISP0 = 1
{
×
{
×
{
×
{
×
{
{
×
{
×
{
×
{
×
{
Interrupt Being Serviced
Maskable interrupt
Priority Level 1
(PR = 01)
Software
Interrupt
Request
Software interrupt
Remarks 1. {: Multiple interrupt servicing enabled
2. ×: Multiple interrupt servicing disabled
3. ISP0, ISP1, and IE are flags contained in the PSW.
ISP1 = 0, ISP0 = 0: An interrupt of level 1 or level 0 is being serviced.
ISP1 = 0, ISP0 = 1: An interrupt of level 2 is being serviced.
ISP1 = 1, ISP0 = 0: An interrupt of level 3 is being serviced.
ISP1 = 1, ISP0 = 1: Wait for An interrupt acknowledgment.
IE = 0: Interrupt request acknowledgment is disabled.
IE = 1: Interrupt request acknowledgment is enabled.
4. PR is a flag contained in PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, and PR12H.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher priority level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 10: Specify level 2 with ××PR1× = 1, ××PR0× = 0
PR = 11: Specify level 1 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
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Figure 19-17. Examples of Multiple Interrupt Servicing (1/2)
Example 1. Multiple interrupt servicing occurs twice
Main processing
INTxx servicing
IE = 0
EI
INTyy servicing
IE = 0
IE = 0
EI
INTxx
(PR = 11)
INTzz servicing
EI
INTyy
(PR = 10)
INTzz
(PR = 01)
RETI
IE = 1
IE = 1
RETI
RETI
IE = 1
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt
servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable
interrupt request acknowledgment.
Example 2. Multiple interrupt servicing does not occur due to priority control
Main processing
EI
INTxx servicing
INTyy servicing
IE = 0
EI
INTxx
(PR = 10)
INTyy
(PR = 11)
RETI
IE = 1
1 instruction execution
IE = 0
RETI
IE = 1
Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than
that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is
acknowledged following execution of one main processing instruction.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher priority level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 10: Specify level 2 with ××PR1× = 1, ××PR0× = 0
PR = 11: Specify level 1 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
IE = 0:
Interrupt request acknowledgment is disabled
IE = 1:
Interrupt request acknowledgment is enabled.
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Figure 19-17. Examples of Multiple Interrupt Servicing (2/2)
Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled
Main processing
INTxx servicing INTyy servicing
IE = 0
EI
INTxx
(PR = 11)
INTyy
(PR = 00)
RETI
IE = 1
1 instruction execution
IE = 0
RETI
IE = 1
Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request
INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held
pending, and is acknowledged following execution of one main processing instruction.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher priority level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 10: Specify level 2 with ××PR1× = 1, ××PR0× = 0
PR = 11: Specify level 1 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
IE = 0:
Interrupt request acknowledgment is disabled
IE = 1:
Interrupt request acknowledgment is enabled.
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19.4.4 Interrupt request hold
There are instructions where, even if an interrupt request is issued for them while another instruction is being executed,
request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt
request hold instructions) are listed below.
• MOV PSW, #byte
• MOV PSW, A
• MOV1 PSW. bit, CY
• SET1 PSW. bit
• CLR1 PSW. bit
• RETB
• RETI
• POP PSW
• BTCLR PSW. bit, $addr8
• EI
• DI
• SKC
• SKNC
• SKZ
• SKNZ
• Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L, MK0H, MK1L, MK1H, MK2L, MK2H,
PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, and PR12H registers.
Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However, the
software interrupt activated by executing the BRK instruction causes the IE flag to be cleared.
Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction,
the interrupt request is not acknowledged.
Figure 19-18 shows the timing at which interrupt requests are held pending.
Figure 19-18. Interrupt Request Hold
CPU processing
Instruction N
Instruction M
PSW and PC saved, jump
to interrupt servicing
Interrupt servicing
program
××IF
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instruction other than interrupt request hold instruction
3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).
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CHAPTER 20 KEY INTERRUPT FUNCTION
Item
78K0R/LF3
78K0R/LG3
78K0R/LH3
80 pins
100 pins
128 pins
−
Key interrupt
8 ch
20.1 Functions of Key Interrupt
A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to
the key interrupt input pins (KR0 to KR7).
Table 20-1. Assignment of Key Interrupt Detection Pins
Flag
Description
KRM0
Controls KR0 signal in 1-bit units.
KRM1
Controls KR1 signal in 1-bit units.
KRM2
Controls KR2 signal in 1-bit units.
KRM3
Controls KR3 signal in 1-bit units.
KRM4
Controls KR4 signal in 1-bit units.
KRM5
Controls KR5 signal in 1-bit units.
KRM6
Controls KR6 signal in 1-bit units.
KRM7
Controls KR7 signal in 1-bit units.
20.2 Configuration of Key Interrupt
The key interrupt includes the following hardware.
Table 20-2. Configuration of Key Interrupt
Item
Control register
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Figure 20-1. Block Diagram of Key Interrupt
KR7
KR6
KR5
KR4
INTKR
KR3
KR2
KR1
KR0
KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0
Key return mode register (KRM)
20.3 Register Controlling Key Interrupt
(1) Key return mode register (KRM)
This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively.
KRM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 20-2. Format of Key Return Mode Register (KRM)
Address: FFF37H
R/W
7
6
5
4
3
2
KRM7
KRM6
KRM5
KRM4
KRM3
KRM2
Symbol
KRM
After reset: 00H
KRMn
0
KRM1
KRM0
Key interrupt mode control
0
Does not detect key interrupt signal
1
Detects key interrupt signal
Cautions 1. If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of the
corresponding pull-up resistor register 7 (PU7) to 1.
2. An interrupt will be generated if the target bit of the KRM register is set while a low level is being
input to the key interrupt input pin. To ignore this interrupt, set the KRM register after disabling
interrupt servicing by using the interrupt mask flag. Afterward, clear the interrupt request flag
and enable interrupt servicing after waiting for the key interrupt input low-level width (250 ns or
more).
3. The bits not used in the key interrupt mode can be used as normal ports.
Remark
n = 0 to 7
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CHAPTER 21 STANDBY FUNCTION
CHAPTER 21 STANDBY FUNCTION
21.1 Standby Function and Configuration
21.1.1 Standby function
The standby function is mounted onto all 78K0R/Lx3 microcontroller products.
The standby function reduces the operating current of the system, and the following two modes are available.
(1) HALT mode
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the highspeed system clock oscillator, internal high-speed oscillator, 20 MHz internal high-speed oscillator, or subsystem
clock oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the
operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting
operation immediately upon interrupt request generation and carrying out intermittent operations frequently.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and
internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating
current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released
when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately upon interrupt
request generation.
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set
are held. The I/O port output latches and output buffer statuses are also held.
Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The
STOP mode cannot be set while the CPU operates with the subsystem clock. The HALT mode
can be used when the CPU is operating on either the main system clock or the subsystem clock.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating
with main system clock before executing STOP instruction.
3. The following sequence is recommended for operating current reduction of the A/D converter
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter
mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the STOP
instruction.
4. It can be selected by the option byte whether the internal low-speed oscillator continues oscillating or
stops in the HALT or STOP mode. For details, see CHAPTER 26 OPTION BYTE.
5. The STOP instruction cannot be executed when the CPU operates on the 20 MHz internal highspeed oscillation clock. Be sure to execute the STOP instruction after shifting to internal highspeed oscillation clock operation.
21.1.2 Registers controlling standby function
The standby function is controlled by the following two registers.
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
Remark
For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
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(1) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case,
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or subsystem clock is being used
as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as
the CPU clock with the X1 clock oscillating.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, WDT, and executing an illegal instruction), the STOP
instruction and MSTOP (bit 7 of CSC register) = 1 clear this register to 00H.
Figure 21-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H
Symbol
OSTC
7
After reset: 00H
6
5
R
4
3
2
1
0
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11
13
15
17
18
MOST MOST MOST MOST MOST MOST MOST MOST
8
0
1
1
9
0
0
1
10
0
0
0
11
13
0
0
0
0
0
0
15
17
0
0
0
0
0
0
Oscillation stabilization time status
18
fX = 10 MHz
fX = 20 MHz
0
2 /fX max. 25.6 μs max.
12.8 μs max.
0
2 /fX min. 25.6 μs min.
12.8 μs min.
0
2 /fX min. 51.2 μs min.
25.6 μs min.
8
8
9
1
1
1
0
0
0
0
0
2 /fX min. 102.4 μs min. 51.2 μs min.
1
1
1
1
0
0
0
0
2 /fX min. 204.8 μs min. 102.4 μs min.
1
1
1
1
1
0
0
0
2 /fX min. 819.2 μs min. 409.6 μs min.
1
1
1
1
1
1
0
0
2 /fX min. 3.27 ms min.
10
11
13
15
1.64 ms min.
17
1
1
1
1
1
1
1
0
2 /fX min. 13.11 ms min. 6.55 ms min.
1
1
1
1
1
1
1
1
2 /fX min. 26.21 ms min. 13.11 ms min.
18
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST8 and
remain 1.
2. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by OSTS. If the STOP mode is entered and then released while the internal
high-speed oscillation clock is being used as the CPU clock, set the oscillation
stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set
by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
3. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark
fX: X1 clock oscillation frequency
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(2) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP
mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired
oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be
checked up to the time set using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 07H.
Figure 21-2. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H
After reset: 07H
R/W
Symbol
7
6
5
4
3
2
1
0
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
0
0
0
2 /fX
0
0
1
2 /fX
0
1
0
2 /fX
0
1
1
2 /fX
1
0
0
2 /fX
1
0
1
2 /fX
1
1
0
2 /fX
1
1
1
2 /fX
Oscillation stabilization time selection
fX = 10 MHz
25.6 μs
8
fX = 20 MHz
Setting prohibited
9
51.2 μs
25.6 μs
10
102.4 μs
51.2 μs
11
204.8 μs
102.4 μs
13
819.2 μs
409.6 μs
15
3.27 ms
1.64 ms
17
13.11 ms
6.55 ms
18
26.21 ms
13.11 ms
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before executing
the STOP instruction.
2. Setting the oscillation stabilization time to 20 μs or less is prohibited.
3. Before changing the setting of the OSTS register, confirm that the count operation of the OSTC
register is completed.
4. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time.
5. The oscillation stabilization time counter counts up to the oscillation stabilization time set by
OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation
clock is being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to
OSTC after STOP mode is released.
6. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation
starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark fX: X1 clock oscillation frequency
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21.2 Standby Function Operation
21.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU
clock before the setting was the high-speed system clock, internal high-speed oscillation clock, 20 MHz internal highspeed oscillation clock, or subsystem clock.
The operating statuses in the HALT mode are shown below.
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Table 21-1. Operating Statuses in HALT Mode (1/3)
HALT Mode Setting
Item
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
When CPU Is Operating on
When CPU Is Operating on
Internal High-Speed
X1 Clock (fX)
External Main System Clock
Oscillation Clock (fIH) or 20
(fEX)
MHz Internal High-Speed
Oscillation Clock (fIH20)
System clock
Clock supply to the CPU is stopped
Main system clock
fIH
Operation continues (cannot
Status before HALT mode was set is retained
be stopped)
fX
Status before HALT mode
Operation continues (cannot
was set is retained
be stopped)
fEX
Cannot operate
Cannot operate
Operation continues (cannot
be stopped)
Subsystem clock
fXT
fIL
Status before HALT mode was set is retained
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Oscillates
• WTON = 1 and WDSTBYON = 0: Stops
CPU
Operation stopped
Flash memory
Operation stopped
RAM
Status before HALT mode was set is retained at voltage higher than POC detection voltage.
Port (latch)
Status before HALT mode was set is retained
Timer array unit (TAU)
Operable
Real-time counter (RTC)
Watchdog timer
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Operates
• WTON = 1 and WDSTBYON = 0: Stops
Clock output/buzzer output
Operable
A/D converter
D/A converter
Operational amplifier
Voltage reference
Serial array unit (SAU)
Serial interface (IICA)
LCD controller/driver
Multiplier/divider
DMA controller
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt
Remarks 1.
fIH:
Internal high-speed oscillation clock,
fX:
X1 oscillation clock,
fXT: XT1 oscillation clock,
2.
fIH20:
20 MHz internal high-speed oscillation clock
fEX:
External main system clock
fIL:
Internal low-speed oscillation clock
The functions mounted depend on the product.
Refer to 1.4
Block Diagram and 1.5
Outline of
Functions.
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Table 21-1. Operating Statuses in HALT Mode (2/3)
HALT Mode Setting
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
Item
When CPU Is Operating on XT1 Clock (fXT)
System clock
Clock supply to the CPU is stopped
fIH
Main system clock
Status before HALT mode was set is retained
fX
Subsystem clock
fEX
Operates or stops by external clock input
fXT
Operation continues (cannot be stopped)
fIL
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Oscillates
• WTON = 1 and WDSTBYON = 0: Stops
CPU
Operation stopped
Flash memory
Operation stopped (wait state in low-power consumption mode)
RAM
Status before HALT mode was set is retained at voltage higher than POC detection voltage.
Port (latch)
Status before HALT mode was set is retained
Timer array unit (TAU)
Operable
Real-time counter (RTC)
Watchdog timer
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Operates
• WTON = 1 and WDSTBYON = 0: Stops
Clock output/buzzer output
Operable
A/D converter
Cannot operate
D/A converter
Operable
Operational amplifier
Voltage reference
Serial array unit (SAU)
Serial interface (IICA)
Cannot operate
LCD controller/driver
Operable
Multiplier/divider
DMA controller
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt
Remarks 1.
fIH:
Internal high-speed oscillation clock,
fX:
X1 oscillation clock,
fXT: XT1 oscillation clock,
2.
fIH20:
20 MHz internal high-speed oscillation clock
fEX:
External main system clock
fIL:
Internal low-speed oscillation clock
The functions mounted depend on the product.
Refer to 1.4
Block Diagram and 1.5
Outline of
Functions.
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Table 21-1. Operating Statuses in HALT Mode (3/3)
HALT Mode Setting
Item
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
When CPU Is Operating on XT1 Clock (fXT) (Subsystem Clock HALT Mode (RTCLPC = 1))
System clock
Clock supply to the CPU is stopped
fIH
Main system clock
Status before HALT mode was set is retained
fX
Subsystem clock
fEX
Operates or stops by external clock input
fXT
Operation continues (cannot be stopped)
fIL
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Oscillates
• WTON = 1 and WDSTBYON = 0: Stops
CPU
Operation stopped
Flash memory
Operation stopped (wait state in low-power consumption mode)
RAM
Status before HALT mode was set is retained at voltage higher than POC detection voltage.
Port (latch)
Status before HALT mode was set is retained
Timer array unit (TAU)
Cannot operate
Real-time counter (RTC)
Operable
Watchdog timer
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Operates
• WTON = 1 and WDSTBYON = 0: Stops
Clock output/buzzer output
Operable
A/D converter
Cannot operate
D/A converter
Operational amplifier
Voltage reference
Serial array unit (SAU)
Serial interface (IICA)
LCD controller/driver
Operable
Multiplier/divider
Operation stopped
DMA controller
Power-on-clear function
Operable
Low-voltage detection function
External interrupt
Key interrupt
Remarks 1.
fIH:
Internal high-speed oscillation clock,
fX:
X1 oscillation clock,
fXT: XT1 oscillation clock,
fIH20:
20 MHz internal high-speed oscillation clock
fEX:
External main system clock
fIL:
Internal low-speed oscillation clock
2.
RTCLPC: Bit 7 of the operation speed mode control register (OSMC).
3.
The functions mounted depend on the product.
Refer to 1.4
Block Diagram and 1.5
Outline of
Functions.
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(2) HALT mode release
The HALT mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is
enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address
instruction is executed.
Figure 21-3. HALT Mode Release by Interrupt Request Generation
Interrupt
request
HALT
instruction
Standby
release signal
Status of CPU
Operating mode
HALT mode
High-speed system clock,
internal high-speed oscillation clock,
20 MHz internal high-speed oscillation clock,
or subsystem clock
WaitNote
Operating mode
Oscillation
Note The wait time is as follows:
• When vectored interrupt servicing is carried out
When main system clock is used: 10 to 12 clocks
When subsystem clock is used:
8 to 10 clocks
• When vectored interrupt servicing is not carried out
When main system clock is used: 5 or 6 clocks
When subsystem clock is used:
Remark
3 or 4 clocks
The broken lines indicate the case when the interrupt request which has released the standby mode is
acknowledged.
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(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 21-4. HALT Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
HALT
instruction
Reset signal
Status of CPU
Normal operation
(high-speed
system clock)
High-speed
system clock
(X1 oscillation)
Reset
period
HALT mode
Reset processing
(about 2.1 to 5.8 ms)
Normal operation
(internal high-speed
oscillation clock)
Oscillation Oscillation
stopped stopped
Oscillates
Oscillates
Oscillation stabilization time
(28/fX to 211/fX, 213/fX, 215/fX, 217/fX, 218/fX)
Starting X1 oscillation is
specified by software.
(2) When internal high-speed oscillation clock or 20 MHz internal
high-speed oscillation clock is used as CPU clock
HALT
instruction
Reset signal
Normal operation
(internal high-speed
oscillation clock or
20 MHz internal
high-speed
Status of CPU
oscillation clock)
Internal high-speed oscillation clock
or 20 MHz internal high-speed
oscillation clock
HALT mode
Reset processing
(about 2.1 to 5.8 ms)
Normal operation
(internal high-speed
oscillation clock)
Reset
period
Oscillation
stopped
Oscillates
Oscillates
Wait for oscillation
accuracy stabilization
(3) When subsystem clock is used as CPU clock
HALT
instruction
Reset signal
Status of CPU
Subsystem clock
(XT1 oscillation)
Normal operation
(subsystem clock)
HALT mode
Oscillates
Reset
period
Reset processing
(about 2.1 to 5.8 ms)
Normal operation mode
(internal high-speed
oscillation clock)
Oscillation Oscillation
stopped
stopped Oscillates
Starting XT1 oscillation is
specified by software.
Remark fX: X1 clock oscillation frequency
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21.2.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the main system clock.
Cautions 1. Because the interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is
immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after
execution of the STOP instruction and the system returns to the operating mode as soon as the
wait time set using the oscillation stabilization time select register (OSTS) has elapsed.
2. The STOP instruction cannot be executed when the CPU operates on the 20 MHz internal highspeed oscillation clock. Be sure to execute the STOP instruction after shifting to internal highspeed oscillation clock operation.
The operating statuses in the STOP mode are shown below.
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Table 21-2. Operating Statuses in STOP Mode
STOP Mode Setting
Item
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
When CPU Is Operating on
When CPU Is Operating on
Internal High-Speed
X1 Clock (fX)
External Main System Clock
Oscillation Clock (fIH)
System clock
(fEX)
Clock supply to the CPU is stopped
fIH
Main system clock
Stopped
fX
fEX
Subsystem clock
fXT
Status before STOP mode was set is retained
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
fIL
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Oscillates
• WTON = 1 and WDSTBYON = 0: Stops
Operation stopped
CPU
Flash memory
RAM
Status before STOP mode was set is retained at voltage higher than POC detection voltage.
Port (latch)
Status before STOP mode was set is retained
Timer array unit (TAU)
Cannot operate
Real-time counter (RTC)
Operable
Watchdog timer
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Operates
• WTON = 1 and WDSTBYON = 0: Stops
Clock output/buzzer output
Operable only when subsystem clock is selected as the count clock
A/D converter
Operation stopped
D/A converter
Operable
Operational amplifier
Voltage reference
Serial array unit (SAU)
Cannot operate
Serial interface (IICA)
Wake-up by address match operable
LCD controller/driver
Operable only when subsystem clock is selected as LCD source clock
Multiplier/divider
Cannot operate
DMA controller
Power-on-clear function
Operable
Low-voltage detection function
External interrupt
Key interrupt
Remarks 1.
fIH:
Internal high-speed oscillation clock,
fEX: External main system clock,
fIL:
2.
f X:
X1 oscillation clock
fXT:
XT1 oscillation clock
Internal low-speed oscillation clock
The functions mounted depend on the product.
Refer to 1.4
Block Diagram and 1.5
Outline of
Functions.
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Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware
for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart
the peripheral hardware.
2. To stop the internal low-speed oscillation clock in the STOP mode, use an option byte to stop the
watchdog timer operation in the HALT/STOP mode (bit 0 (WDSTBYON) of 000C0H = 0), and then
execute the STOP instruction.
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the internal
high-speed oscillation clock before the next execution of the STOP instruction. Before changing the
CPU clock from the internal high-speed oscillation clock to the high-speed system clock (X1
oscillation) after the STOP mode is released, check the oscillation stabilization time with the
oscillation stabilization time counter status register (OSTC).
4. The STOP instruction cannot be executed when the CPU operates on the 20 MHz internal high-speed
oscillation clock. Be sure to execute the STOP instruction after shifting to internal high-speed
oscillation clock operation.
(2) STOP mode release
Figure 21-5. Operation Timing When STOP Mode Is Released (When Unmasked Interrupt Request
Is Generated)
STOP mode release
STOP mode
High-speed system
clock (X1 oscillation)
High-speed system
clock (external clock
input)
Internal high-speed
oscillation clock
Wait for oscillation accuracy stabilization
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
High-speed system
clock (external clock
input) is selected as
CPU clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
HALT status
(oscillation stabilization time set by OSTS)Note
High-speed system clock
Clock switched by software
High-speed system clock
Wait (2 clocks)
Supply of the CPU clock is stopped (about 23.3 to 30.7 μs)
Internal high-speed
oscillation clock
Wait (1 clock)
High-speed system clock
Clock switched by software
Supply of the CPU clock is stopped (about 23.3 to 30.7 μs)
Note
When the oscillation stabilization time set by OSTS is equal to or shorter than 61 μs, the HALT status is
retained to a maximum of "61μs + wait time."
The STOP mode can be released by the following two sources.
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(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization
time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt
acknowledgment is disabled, the next address instruction is executed.
Figure 21-6. STOP Mode Release by Interrupt Request Generation (1/2)
(1) When high-speed system clock (X1 oscillation) is used as CPU clock
Interrupt
request
STOP
instruction
Standby release signal
Status of CPU
Wait
(set by OSTS)
Normal operation
(high-speed
system clock)
STOP mode
Oscillates
Oscillation stopped
High-speed
system clock
(X1 oscillation)
Normal operation
(high-speed
system clock)
Oscillation stabilization wait
(HALT mode status)
Oscillates
Oscillation stabilization time (set by OSTS)
(2) When high-speed system clock (external clock input) is used as CPU clock
STOP
instruction
Interrupt
request
Standby release signal
Status of CPU
Normal operation
(high-speed
system clock)
STOP mode
Oscillates
Oscillation stopped
High-speed
system clock
(external clock input)
Supply of the CPU
clock is stopped
Wait
(about 23.3
(2 clocks)
to 30.7 μs)
Normal operation
(high-speed
system clock)
Oscillates
Remark The broken lines indicate the case when the interrupt request that has released the standby mode is
acknowledged.
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Figure 21-6. STOP Mode Release by Interrupt Request Generation (2/2)
(3) When internal high-speed oscillation clock is used as CPU clock
STOP
instruction
Interrupt
request
Standby release signal
Status of CPU
Normal operation
(internal high-speed
oscillation clock)
STOP mode
Supply of the CPU
clock is stopped
Normal operation
Wait
(about 23.3
(internal high-speed
(1 clock)
to 30.7 μs)
oscillation clock)
Oscillates
Oscillation stopped
Oscillates
Internal high-speed
oscillation clock
Wait for oscillation
accuracy stabilization
Remark The broken lines indicate the case when the interrupt request that has released the standby mode is
acknowledged.
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(b) Release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 21-7. STOP Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
STOP
instruction
Reset signal
Status of CPU
High-speed
system clock
(X1 oscillation)
Normal operation
(high-speed
system clock)
STOP mode
Oscillation stopped
Oscillates
Reset
period
Reset processing
(about 2.1 to 5.8 ms)
Normal operation
(internal high-speed
oscillation clock)
Oscillation Oscillation
stopped stopped
Oscillates
Oscillation stabilization time
(Checked by using OSTC register)
Starting X1 oscillation is
specified by software.
(2) When internal high-speed oscillation clock is used as CPU clock
STOP
instruction
Reset signal
Status of CPU
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock)
Oscillates
STOP mode
Reset
period
Oscillation
Oscillation stopped stopped
Reset processing
(about 2.1 to 5.8 ms)
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Wait for oscillation
accuracy stabilization
Remark fX: X1 clock oscillation frequency
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CHAPTER 22 RESET FUNCTION
The following five operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage of the low-voltage detector (LVI) or input voltage (EXLVI) from
external input pin, and detection voltage
(5) Internal reset by execution of illegal instructionNote
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is
generated.
A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI circuit
voltage detection or execution of illegal instructionNote, and each item of hardware is set to the status shown in Tables 22-1
and 22-2. Each pin is high impedance during reset signal generation or during the oscillation stabilization time just after a
reset release, except for P130, which is low-level output.
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is
input to the RESET pin and program execution is started with the internal high-speed oscillation clock after reset
processing. A reset by the watchdog timer is automatically released, and program execution starts using the internal highspeed oscillation clock (see Figures 22-2 to 22-4) after reset processing. Reset by POC and LVI circuit power supply
detection is automatically released when VDD ≥ VPOR or VDD ≥ VLVI after the reset, and program execution starts using the
internal high-speed oscillation clock (see CHAPTER 23
POWER-ON-CLEAR CIRCUIT and CHAPTER 24
LOW-
VOLTAGE DETECTOR) after reset processing.
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
Cautions 1. For an external reset, input a low level for 10 μs or more to the RESET pin
(To perform an external reset upon power application, a low level of at least 10 μs must be
continued during the period in which the supply voltage is within the operating range (VDD ≥ 1.8
V)).
2. During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and internal
low-speed oscillation clock stop oscillating. External main system clock input becomes invalid.
3. When the STOP mode is released by a reset, the RAM contents in the STOP mode are held during
reset input.
4. When reset is effected, port pin P140 is set to low-level output and other port pins become highimpedance, because each SFR and 2nd SFR are initialized.
Remark
VPOR: POC power supply rise detection voltage
VLVI:
LVI detection voltage
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Figure 22-1. Block Diagram of Reset Function
Internal bus
Reset control flag
register (RESF)
TRAP
WDRF
Set
LVIRF
Set
Watchdog timer reset signal
Clear Clear
Clear
Set
Reset signal by execution of illegal instruction
RESF register read signal
RESET
Reset signal to LVIM/LVIS register
Power-on clear circuit reset signal
Caution An LVI circuit internal reset does not reset the LVI circuit.
Remarks 1. LVIM: Low-voltage detection register
2. LVIS: Low-voltage detection level select register
Reset signal
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Low-voltage detector reset signal
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CHAPTER 22 RESET FUNCTION
Figure 22-2. Timing of Reset by RESET Input
Wait for oscillation
accuracy stabilization
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
High-speed system clock
(when X1 oscillation is selected)
CPU clock
Normal operation
(internal high-speed oscillation clock)
Reset period
(oscillation stop)
Normal operation
Reset processing
(about 2.1 to 5.8 ms)
RESET
Internal reset signal
Delay
Delay
(about 30 to 170 μs)
Port pin
(except P130)
Hi-Z
Port pin
(P130)
Note
Note Set P130 to high-level output by software.
Remark
When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
Figure 22-3. Timing of Reset Due to Watchdog Timer Overflow
Wait for oscillation
accuracy stabilization
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
High-speed system clock
(when X1 oscillation is selected)
CPU clock
Normal operation
Reset period
(oscillation stop)
Watchdog timer
overflow
Normal operation
(internal high-speed oscillation clock)
Reset processing
(about 195 to 322 μs)
Internal reset signal
Port pin
(except P130)
Hi-Z
Port pin
(P130)
Note
Note Set P130 to high-level output by software.
Caution A watchdog timer internal reset resets the watchdog timer.
Remark
When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
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Figure 22-4. Timing of Reset in STOP Mode by RESET Input
Wait for oscillation
accuracy stabilization
STOP instruction execution
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
High-speed system clock
(when X1 oscillation is selected)
CPU clock
Normal
operation
Stop status
(oscillation stop)
Reset period
(oscillation stop)
RESET
Normal operation
(internal high-speed oscillation clock)
Reset processing
(about 2.1 to 5.8 ms)
Internal reset signal
Delay
Port pin
(except P130)
Delay
(about 30 to 170 μs)
Hi-Z
Port pin
(P130)
Note
Note Set P130 to high-level output by software.
Remarks 1. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
2. For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 23 POWERON-CLEAR CIRCUIT and CHAPTER 24 LOW-VOLTAGE DETECTOR.
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Table 22-1. Operation Statuses During Reset Period
Item
During Reset Period
System clock
Clock supply to the CPU is stopped.
Main system clock
Subsystem clock
fIH
Operation stopped
fX
Operation stopped (X1 and X2 pins are input port mode)
fEX
Clock input invalid (pin is input port mode)
fXT
Operation stopped (XT1 and XT2 pins are input port mode)
fIL
Operation stopped
CPU
Flash memory
Operation stopped (The value, however, is retained when the voltage is at least the power-on-
RAM
clear detection voltage.)
Port (latch)
Set P130 to low-level output. The port pins except for P130 become high impedance.
Timer array unit (TAU)
Operation stopped
Real-time counter (RTC)
Watchdog timer
Clock output/buzzer output
A/D converter
D/A converter
Operational amplifier
Voltage reference
Serial array unit (SAU)
Serial interface (IICA)
LCD controller/driver
Operation stopped
(COM only pin, SEG only pin, COM/SEG alternate pin: GND output, SEG/general-purpose port
alternate pin: input port, VLC0 to VLC2 pins: high-impedance output, VLC3/P02 pin, CAPH/P00 pin,
CAPL/P01 pin: input port)
Multiplier/divider
Operation stopped
DMA controller
Power-on-clear function
Detection operation possible
Low-voltage detection function
Operation stopped (however, operation continues at LVI reset)
External interrupt
Operation stopped
Key interrupt
BCD correction circuit (BCD)
Remarks 1.
fIH:
Internal high-speed oscillation clock,
fEX: External main system clock,
fIL:
2.
f X:
X1 oscillation clock
fXT:
XT1 oscillation clock
Internal low-speed oscillation clock
The functions mounted depend on the product.
Refer to 1.4
Block Diagram and 1.5
Outline of
Functions.
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Table 22-2. Hardware Statuses After Reset Acknowledgment (1/4)
Hardware
After Reset
Note 1
Acknowledgment
Program counter (PC)
The contents of the
reset vector table
(0000H, 0001H) are set.
Stack pointer (SP)
Undefined
Program status word (PSW)
06H
RAM
Data memory
Undefined
Note 2
General-purpose registers
Undefined
Note 2
Port registers (P0 to P15) (output latches)
00H
Port mode registers (PM0 to PM12, PM14, PM15)
FFH
Port input mode registers 1, 7 (PIM1, PIM7)
00H
Port output mode registers 1, 7, 8 (POM1, POM7, POM8)
00H
Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7 to PU10, PU12, PU14)
00H
Clock operation mode control register (CMC)
00H
Clock operation status control register (CSC)
C0H
Processor mode control register (PMC)
00H
System clock control register (CKC)
09H
20 MHz internal high-speed oscillation control register (DSCCTL)
00H
Oscillation stabilization time counter status register (OSTC)
00H
Oscillation stabilization time select register (OSTS)
07H
Noise filter enable registers 0, 1 (NFEN0, NFEN1)
00H
Peripheral enable registers 0 (PER0)
00H
Operation speed mode control register (OSMC)
00H
Input switch control register (ISC)
00H
Timer array units
0, 1 (TAU0, TAU1)
Timer data registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (TDR00,
TDR01, TDR02, TDR03, TDR04, TDR05, TDR06, TDR07, TDR10, TDR11,
TDR12, TDR13)
0000H
Timer mode registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (TMR00,
TMR01, TMR02, TMR03, TMR04, TMR05, TMR06, TMR07, TMR10, TMR11,
TMR12, TMR13)
0000H
Timer status registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (TSR00,
TSR01, TSR02, TSR03, TSR04, TSR05, TSR06, TSR07, TSR10, TSR11,
TSR12, TSR13)
0000H
Timer input select register 0, 1 (TIS0, TIS1)
00H
Timer channel counter registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13
(TCR00, TCR01, TCR02, TCR03, TCR04, TCR05, TCR06, TCR07, TCR10,
TCR11, TCR12, TCR13)
FFFFH
Timer channel enable status registers 0, 1 (TE0, TE1)
0000H
Timer channel start trigger registers 0, 1 (TS0, TS1)
0000H
Notes 1.
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
2.
When a reset is executed in the standby mode, the pre-reset status is held even after reset.
Remark The SFR and 2nd SFR provided differ depending on the product. Refer to 3.2.4 Special function registers
(SFRs) and 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
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Table 22-2. Hardware Statuses After Reset Acknowledgment (2/4)
Hardware
Timer array units 0, 1
(TAU0, TAU1)
Real-time counter
Status After Reset
Note 1
Acknowledgment
Timer channel stop trigger registers 0, 1 (TT0, TT1)
0000H
Timer clock select registers 0, 1 (TPS0, TPS1)
0000H
Timer channel output registers 0, 1 (TO0, TO1)
0000H
Timer channel output enable registers 0, 1 (TOE0, TOE1)
0000H
Timer channel output level registers 0, 1 (TOL0, TOL1)
0000H
Timer channel output mode registers 0, 1 (TOM0, TOM1)
0000H
Sub-count register (RSUBC)
0000H
Second count register (SEC)
00H
Minute count register (MIN)
00H
Hour count register (HOUR)
12H
Week count register (WEEK)
00H
Day count register (DAY)
01H
Month count register (MONTH)
01H
Year count register (YEAR)
00H
Watch error correction register (SUBCUD)
00H
Alarm minute register (ALARMWM)
00H
Alarm hour register (ALARMWH)
12H
Alarm week register (ALARMWW)
00H
Real-time counter control register 0 (RTCC0)
00H
Real-time counter control register 1 (RTCC1)
00H
Real-time counter control register 2 (RTCC2)
00H
Clock output/buzzer
output controller
Clock output select registers 0, 1 (CKS0, CKS1)
00H
Watchdog timer
Enable register (WDTE)
1AH/9AH
A/D converter
10-bit A/D conversion result register (ADCR)
0000H
8-bit A/D conversion result register (ADCRH)
00H
A/D converter mode register (ADM)
00H
A/D converter mode register 1 (ADM1)
00H
Analog reference voltage control register (ADVRC)
00H
Analog input channel specification register (ADS)
00H
A/D port configuration register (ADPC)
10H
D/A conversion value setting registers W0, W1 (DACSW0, DACSW1)
0000H
8-bit D/A conversion value setting registers 0, 1 (DACS0, DACS1)
00H
D/A converter
D/A converter mode register (DAM)
00H
Operational amplifier
Operational amplifier control register (OAC)
00H
Voltage reference
Analog reference voltage control register (ADVRC)
00H
Notes 1.
Note 2
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
2.
The reset value of WDTE is determined by the option byte setting.
Remark The SFR and 2nd SFR mounted depend on the product. Refer to 3.2.4 Special function registers (SFRs)
and 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
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Table 22-2. Hardware Statuses After Reset Acknowledgment (3/4)
Hardware
Status After Reset
Acknowledgment
Serial array units 0, 1
(SAU0, SAU1)
Serial interface IICA
LCD controller/driver
Multiplier/divider
Key interrupt
Note
Serial data registers 00, 01, 02, 03, 10, 11, 12, 13 (SDR00, SDR01,
SDR02, SDR03, SDR10, SDR11, SDR12, SDR13)
0000H
Serial status registers 00, 01, 02, 03, 10, 11, 12, 13 (SSR00, SSR01,
SSR02, SSR03, SSR10, SSR11, SSR12, SSR13)
0000H
Serial flag clear trigger registers 00, 01, 02, 03, 10, 11, 13 (SIR00, SIR01,
SIR02, SIR03, SIR10, SIR11, SIR13)
0000H
Serial mode registers 00, 01, 02, 03, 10, 11, 12, 13 (SMR00, SMR01,
SMR02, SMR03, SMR10, SMR11, SMR12, SMR13)
0020H
Serial communication operation setting registers 00, 01, 02, 03, 10, 11, 12,
13 (SCR00, SCR01, SCR02, SCR03, SCR10, SCR11, SCR12,
SCR13)
0087H
Serial channel enable status registers 0, 1 (SE0, SE1)
0000H
Serial channel start trigger registers 0, 1 (SS0, SS1)
0000H
Serial channel stop trigger registers 0, 1 (ST0, ST1)
0000H
Serial clock select registers 0, 1 (SPS0, SPS1)
0000H
Serial output registers 0, 1 (SO0, SO1)
0F0FH
Serial output enable registers 0, 1 (SOE0, SOE1)
0000H
Shift register (IICA)
00H
Control register 0 (IICCTL0)
00H
Control register 1 (IICCTL1)
00H
Slave address register (SVA)
00H
IICA low-level width setting register 0 (IICWL)
FFH
IICA high-level width setting register 0 (IICWH)
FFH
Status register (IICS)
00H
Flag register (IICF)
00H
LCD mode register (LCDMD)
00H
LCD display mode register (LCDM)
00H
LCD clock control register 0 (LCDC0)
00H
LCD boost level control register (VLCD)
0FH
Port function register (PFALL)
00H
Segment enable register (SEGEN)
00H
Input switch control register (ISC)
00H
Multiplication/division data register A (MDAL, MDAH)
0000H
Multiplication/division data register B (MDBL, MDBH)
0000H
Multiplication/division data register C (MDCL, MDCH)
0000H
Multiplication/division control register (MDUC)
00H
Key return mode register (KRM)
00H
Note
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
Remark
The SFR and 2nd SFR mounted depend on the product. Refer to 3.2.4 Special function registers (SFRs)
and 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
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Table 22-2. Hardware Statuses After Reset Acknowledgment (4/4)
Status After Reset
Hardware
Acknowledgment
Note 2
Reset function
Reset control flag register (RESF)
Undefined
Low-voltage detector
Low-voltage detection register (LVIM)
00H
Low-voltage detection level select register (LVIS)
0EH
SFR address registers 0, 1 (DSA0, DSA1)
00H
RAM address registers 0L, 0H, 1L, 1H (DRA0L, DRA0H, DRA1L, DRA1H)
00H
Byte count registers 0L, 0H, 1L, 1H (DBC0L, DBC0H, DBC1L, DBC1H)
00H
DMA controller
Interrupt
Note 1
Note 3
Note 2
Mode control registers 0, 1 (DMC0, DMC1)
00H
Operation control registers 0, 1 (DRC0, DRC1)
00H
Request flag registers 0L, 0H, 1L, 1H, 2L, 2H (IF0L, IF0H, IF1L, IF1H,
00H
IF2L, IF2H)
Mask flag registers 0L, 0H, 1L, 1H, 2L, 2H (MK0L, MK0H, MK1L,
FFH
MK1H, MK2L, MK2H)
Priority specification flag registers 00L, 00H, 01L, 01H, 02L, 02H, 10L,
FFH
10H, 11L, 11H, 12L, 12H (PR00L, PR00H, PR01L, PR01H, PR10L,
PR10H, PR11L, PR11H, PR02L, PR02H, PR12L, PR12H)
External interrupt rising edge enable registers 0, 1 (EGP0, EGP1)
00H
External interrupt falling edge enable registers 0, 1 (EGN0, EGN1)
00H
Regulator
Regulator mode control register (RMC)
00H
BCD correction circuit
BCD correction result register (BCDADJ)
Undefined
(BCD)
Notes 1.
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
2.
These values vary depending on the reset source.
Reset Source
RESET Input
Reset by POC
TRAP bit
Remark
Reset by LVI
Set (1)
Held
Held
WDRF bit
Held
Set (1)
Held
LVIRF bit
Held
Held
Set (1)
Cleared (0EH)
Cleared (0EH)
Held
LVIS
3.
Reset by WDT
Illegal Instruction
Register
RESF
Reset by Execution of
Cleared (0)
Cleared (0EH)
Cleared (0)
Cleared (0EH)
This value varies depending on the reset source and the option byte.
The SFR and 2nd SFR mounted depend on the product. Refer to 3.2.4 Special function registers (SFRs)
and 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
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22.1 Register for Confirming Reset Source
Many internal reset generation sources exist in the 78K0R/Lx3 microcontrollers. The reset control flag register (RESF)
is used to store which source has generated the reset request.
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-clear (POC) circuit, and reading RESF clear TRAP, WDRF, and LVIRF.
Figure 22-5. Format of Reset Control Flag Register (RESF)
Address: FFFA8H
Symbol
RESF
After reset: Undefined
7
TRAP
6
Note 1
Undefined
4
Undefined
TRAP
Note 1
WDRF
3
2
1
Undefined
Undefined
Undefined
Internal reset request by execution of illegal instruction
0
Internal reset request is not generated, or RESF is cleared.
1
Internal reset request is generated.
WDRF
0
Note 1
LVIRF
Note 2
Internal reset request by watchdog timer (WDT)
0
Internal reset request is not generated, or RESF is cleared.
1
Internal reset request is generated.
LVIRF
Notes 1.
R
5
Internal reset request by low-voltage detector (LVI)
0
Internal reset request is not generated, or RESF is cleared.
1
Internal reset request is generated.
The value after reset varies depending on the reset source.
2.
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
Cautions 1. Do not read data by a 1-bit memory manipulation instruction.
2. Do not make a judgment based on only the read value of the RESF register 8-bit data, because
bits other than TRAP, WDRF, and LVIRF become undefined.
3. When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, LVIRF flag may
become 1 from the beginning depending on the power-on waveform.
The status of RESF when a reset request is generated is shown in Table 22-3.
Table 22-3. RESF Status When Reset Request Is Generated
Reset Source
RESET Input
Reset by POC
Reset by WDT
Reset by LVI
of Illegal Instruction
Flag
TRAP
Reset by Execution
Cleared (0)
Cleared (0)
Set (1)
Held
Held
WDRF
Held
Set (1)
Held
LVIRF
Held
Held
Set (1)
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CHAPTER 23 POWER-ON-CLEAR CIRCUIT
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
23.1 Functions of Power-on-Clear Circuit
The power-on-clear circuit (POC) is mounted onto all 78K0R/Lx3 microcontroller products.
The power-on-clear circuit has the following functions.
• Generates internal reset signal at power on.
The reset signal is released when the supply voltage (VDD) exceeds 1.61 V ±0.09 V.
Caution If the low-voltage detector (LVI) is set to ON by an option byte by default, the reset signal is not
released until the supply voltage (VDD) exceeds 2.07 V ±0.2 V.
• Compares supply voltage (VDD) and detection voltage (VPDR = 1.59 V ±0.09 V), generates internal reset signal when
VDD < VPDR.
Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is
cleared to 00H.
Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that
indicates the reset source is located in the reset control flag register (RESF) for when an internal reset
signal is generated by the watchdog timer (WDT), low-voltage-detector (LVI), or illegal instruction
execution. RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated
by WDT or LVI.
For details of RESF, see CHAPTER 22 RESET FUNCTION.
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23.2 Configuration of Power-on-Clear Circuit
The block diagram of the power-on-clear circuit is shown in Figure 23-1.
Figure 23-1. Block Diagram of Power-on-Clear Circuit
VDD
VDD
+
Internal reset signal
−
Reference
voltage
source
23.3 Operation of Power-on-Clear Circuit
• An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection
voltage (VPDR = 1.61 V ±0.09 V), the reset status is released.
Caution If the low-voltage detector (LVI) is set to ON by an option byte by default, the reset signal is not
released until the supply voltage (VDD) exceeds 2.07 V ±0.2 V.
• The supply voltage (VDD) and detection voltage (VPDR = 1.59 V ±0.09 V) are compared. When VDD < VPDR, the
internal reset signal is generated.
The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is shown
below.
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Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (1/2)
(1) When LVI is OFF upon power application (option byte: LVIOFF = 1)
Set LVI to be
used for reset
Set LVI to be
used for interrupt
Set LVI to be
used for reset
Supply voltage
(VDD)
VLVI
1.8 VNote 1
VPOR = 1.61 V (TYP.)
VPDR = 1.59 V (TYP.)
0.5 V/ms (MIN.)Note 2
0V
Wait for oscillation
accuracy stabilizationNote 3
Wait for oscillation
accuracy stabilizationNote 3
Wait for oscillation
accuracy stabilizationNote 4
Internal high-speed
oscillation clock (fIH)
Starting oscillation is
specified by software
High-speed
system clock (fMX)
(when X1 oscillation
is selected)
CPU
Reset processing
(about 2.1 to 5.8 ms)
Operation
stops
Starting oscillation is
specified by software
Reset
Normal operation
period
(internal high-speed (oscillation
Note 5
stop)
oscillation clock)
Normal operation
(internal high-speed
oscillation clock)Note 5
Starting oscillation is
specified by software
Reset
period
(oscillation
stop)
Reset processing
(about 2.1 to 5.8 ms)
Normal operation
(internal high-speed
oscillation clock)Note 5
Operation stops
Reset processing (about 195 to 322 ms)
Internal reset signal
Notes 1.
The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset state
when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the
RESET pin.
2.
If the rate at which the voltage rises to 1.8 V after power application is slower than 0.5 V/ms (MIN.), input a
low level to the RESET pin before the voltage reaches to 1.8 V, or set LVI to ON by default by using an
option byte (option byte: LVIOFF = 0).
3.
The reset processing time, such as when waiting for internal voltage stabilization, includes the oscillation
accuracy stabilization time of the internal high-speed oscillation clock.
4.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal highspeed oscillation clock.
5.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of
the stabilization time.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 24 LOWVOLTAGE DETECTOR).
Remark
VLVI:
LVI detection voltage
VPOR: POC power supply rise detection voltage
VPDR: POC power supply fall detection voltage
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Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (2/2)
(2) When LVI is ON upon power application (option byte: LVIOFF = 0)
Set LVI
(VLVI = 2.07 V)
to be used for
reset (default)
Supply voltage
(VDD)
Set LVI
(VLVI = 2.07 V)
to be used for
reset (default)
Set LVI to be
used for interrupt
Change LVI
detection
voltage (VLVI)
VLVI
VLVI = 2.07 V (TYP.)
1.8 VNote 1
VPOR = 1.61 V (TYP.)
VPDR = 1.59 V (TYP.)
0V
Wait for oscillation
accuracy stabilizationNote 3
Wait for oscillation
accuracy stabilizationNote 3
Wait for oscillation
accuracy stabilizationNote 3
Internal high-speed
oscillation clock (fIH)
CPU
Normal operation
(internal high-speed
oscillation clock)Note 2
Operation
stops
Note 4
Reset processing time
POC processing time
Starting oscillation is
specified by software
Starting oscillation is
specified by software
Starting oscillation is
specified by software
High-speed
system clock (fMX)
(when X1 oscillation
is selected)
Reset
period
(oscillation
stop)
Normal operation
(internal high-speed
oscillation clock)Note 2
Reset processing time
(about 195 to 322 μs)
Reset
period
(oscillation
stop)
Normal operation
(internal high-speed
oscillation clock)Note 2
Note 4
Operation stops
Reset processing time
POC processing time
Internal reset signal
Notes 1.
The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset state
when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the
RESET pin.
2.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of
the stabilization time.
3.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal high-
4.
The following times are required between reaching the POC detection voltage (1.59 V (TYP.)) and starting
speed oscillation clock.
normal operation.
• When the time to reach 2.07 V (TYP.) from 1.59 V (TYP.) is less than 5.8 ms:
A POC processing time of about 2.1 to 6.2 ms is required between reaching 1.59 V (TYP.) and starting
normal operation.
• When the time to reach 2.07 V (TYP.) from 1.59 V (TYP.) is greater than 5.8 ms:
A reset processing time of about 195 to 322 μs is required between reaching 2.07 V (TYP.) and starting
normal operation.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 24 LOWVOLTAGE DETECTOR).
Remark
VLVI:
LVI detection voltage
VPOR: POC power supply rise detection voltage
VPDR: POC power supply fall detection voltage
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23.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage
(VPOR, VPDR), the system may be repeatedly reset and released from the reset status. In this case, the time from release
of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software
counter that uses a timer, and then initialize the ports.
Figure 23-3. Example of Software Processing After Reset Release (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Reset
Initialization
processing
; Check the reset source, etc.Note 2
Power-on-clear
Setting timer array unit
(to measure 50 ms)
; fCLK = Internal high-speed oscillation clock (4.08 MHz (MAX.)) (default)
Source: fCLK (4.08 MHz (MAX.))/211,
where comparison value = 100: ≅ 50 ms
Timer starts (TS0n = 1).
Clearing WDT
Note 1
No
50 ms has passed?
(TMIF0n = 1?)
Yes
Initialization
processing
Notes 1.
2.
Remark
; Initial setting for port.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
If reset is generated again during this period, initialization processing is not started.
A flowchart is shown on the next page.
n = 0 to 7
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Figure 23-3. Example of Software Processing After Reset Release (2/2)
• Checking reset source
Check reset source
TRAP of RESF
register = 1?
Yes
No
Reset processing by
illegal instruction execution Note
WDRF of RESF
register = 1?
Yes
No
Reset processing by
watchdog timer
LVIRF of RESF
register = 1?
Yes
No
Reset processing by
low-voltage detector
Power-on-clear/external
reset generated
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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CHAPTER 24 LOW-VOLTAGE DETECTOR
24.1 Functions of Low-Voltage Detector
The low-voltage detector (LVI) is mounted onto all 78K0R/Lx3 microcontroller products.
The low-voltage detector has the following functions.
• The LVI circuit compares the supply voltage (VDD) with the detection voltage (VLVI) or the input voltage from an
external input pin (EXLVI) with the detection voltage (VEXLVI = 1.21 V ±0.1 V), and generates an internal reset or
internal interrupt signal.
• The low-voltage detector (LVI) can be set to ON by an option byte by default. If it is set to ON to raise the power
supply from the POC detection voltage (VPOR = 1.61 V (TYP.)) or lower, the internal reset signal is generated when
the supply voltage (VDD) < detection voltage (VLVI = 2.07 V ±0.2 V). After that, the internal reset signal is generated
when the supply voltage (VDD) < detection voltage (VLVI = 2.07 V ±0.1 V).
• The supply voltage (VDD) or the input voltage from the external input pin (EXLVI) can be selected to be detected by
software.
• A reset or an interrupt can be selected to be generated after detection by software.
• Detection levels (VLVI,16 levels) of supply voltage can be changed by software.
• Operable in STOP mode.
The reset and interrupt signals are generated as follows depending on selection by software.
Selection of Level Detection of Supply Voltage (VDD)
Selection Level Detection of Input Voltage from
(LVISEL = 0)
External Input Pin (EXLVI) (LVISEL = 1)
Selects reset (LVIMD = 1).
Selects interrupt (LVIMD = 0).
Selects reset (LVIMD = 1).
Selects interrupt (LVIMD = 0).
Generates an internal reset
Generates an internal interrupt
Generates an internal reset
Generates an internal interrupt
signal when VDD < VLVI and
signal when VDD drops lower
signal when EXLVI < VEXLVI
signal when EXLVI drops
releases the reset signal when
than VLVI (VDD < VLVI) or when
and releases the reset signal
lower than VEXLVI (EXLVI <
VDD ≥ VLVI.
VDD becomes VLVI or higher
when EXLVI ≥ VEXLVI.
(VDD ≥ VLVI).
VEXLVI) or when EXLVI
becomes VEXLVI or higher
(EXLVI ≥ VEXLVI).
Remark
LVISEL: Bit 2 of low-voltage detection register (LVIM)
LVIMD: Bit 1 of LVIM
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is
more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0 of LVIM).
When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset
occurs. For details of RESF, see CHAPTER 22 RESET FUNCTION.
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24.2 Configuration of Low-Voltage Detector
The block diagram of the low-voltage detector is shown in Figure 24-1.
Figure 24-1. Block Diagram of Low-Voltage Detector
VDD
N-ch
Internal reset signal
Selector
EXLVI/P120/
INTP0
+
Selector
Low-voltage detection
level selector
VDD
−
INTLVI
Reference
voltage
source
4
LVION LVISEL LVIMD
LVIS3 LVIS2 LVIS1 LVIS0
Low-voltage detection level
select register (LVIS)
LVIF
Low-voltage detection register
(LVIM)
Internal bus
24.3 Registers Controlling Low-Voltage Detector
The low-voltage detector is controlled by the following registers.
• Low-voltage detection register (LVIM)
• Low-voltage detection level select register (LVIS)
• Port mode register 12 (PM12)
(1) Low-voltage detection register (LVIM)
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
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Figure 24-2. Format of Low-Voltage Detection Register (LVIM)
After reset: 00HNote 1
Address: FFFA9H
R/WNote 2
Symbol
6
5
4
3
LVIM
LVION
0
0
0
0
LVISEL
LVIMD
LVIF
Notes 3, 4
LVION
Enables low-voltage detection operation
0
Disables operation
1
Enables operation
Note 3
LVISEL
Voltage detection selection
0
Detects level of supply voltage (VDD)
1
Detects level of input voltage from external input pin (EXLVI)
LVIMD
Note 3
0
Low-voltage detection operation mode (interrupt/reset) selection
• LVISEL = 0: Generates an internal interrupt signal when the supply voltage (VDD) drops
lower than the detection voltage (VLVI) (VDD < VLVI) or when VDD becomes
VLVI or higher (VDD ≥ VLVI).
• LVISEL = 1: Generates an interrupt signal when the input voltage from an external
input pin (EXLVI) drops lower than the detection voltage (VEXLVI) (EXLVI <
VEXLVI) or when EXLVI becomes VEXLVI or higher (EXLVI ≥ VEXLVI).
1
• LVISEL = 0: Generates an internal reset signal when the supply voltage (VDD) <
detection voltage (VLVI) and releases the reset signal when VDD ≥ VLVI.
• LVISEL = 1: Generates an internal reset signal when the input voltage from an
external input pin (EXLVI) < detection voltage (VEXLVI) and releases the
reset signal when EXLVI ≥ VEXLVI.
LVIF
0
Low-voltage detection flag
• LVISEL = 0: Supply voltage (VDD) ≥ detection voltage (VLVI), or when LVI operation is
disabled
• LVISEL = 1: Input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI),
or when LVI operation is disabled
1
• LVISEL = 0: Supply voltage (VDD) < detection voltage (VLVI)
• LVISEL = 1: Input voltage from external input pin (EXLVI) < detection voltage (VEXLVI)
Notes 1.
The reset value changes depending on the reset source and the setting of the option byte.
This register is not cleared (00H) by LVI reset.
It is set to “82H” when a reset signal other than LVI is applied if option byte LVIOFF = 0, and to “00H” if
option byte LVIOFF = 1.
2.
Bit 0 is read-only.
3.
LVION, LVIMD, and LVISEL are cleared to 0 in the case of a reset other than an LVI reset. These are not
cleared to 0 in the case of an LVI reset.
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Note
4.
CHAPTER 24 LOW-VOLTAGE DETECTOR
When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use software to wait for
the following periods of time, between when LVION is set to 1 and when the voltage is confirmed with
LVIF.
• Operation stabilization time (10 μs (MAX.))
• Minimum pulse width (200 μs (MIN.))
The LVIF value for these periods may be set/cleared regardless of the voltage level, and can therefore not
be used. Also, the LVIIF interrupt request flag may be set to 1 in these periods.
Cautions 1. To stop LVI, be sure to clear (0) LVION by using a 1-bit memory manipulation instruction.
2. Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
3. When LVI is used in interrupt mode (LVIMD = 0) and LVISEL is set to 0, an interrupt request
signal (INTLVI) that disables LVI operation (clears LVION) when the supply voltage (VDD) is less
than or equal to the detection voltage (VLVI) (if LVISEL = 1, input voltage of external input pin
(EXLVI) is less than or equal to the detection voltage (VEXLVI)) is generated and LVIIF may be set
to 1.
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(2) Low-voltage detection level select register (LVIS)
This register selects the low-voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation input sets this register to 0EH.
Figure 24-3. Format of Low-Voltage Detection Level Select Register (LVIS)
Address: FFFAAH
After reset: 0EH Note
R/W
Symbol
7
6
5
4
3
2
1
0
LVIS
0
0
0
0
LVIS3
LVIS2
LVIS1
LVIS0
LVIS3
LVIS2
LVIS1
LVIS0
0
0
0
0
VLVI0 (4.22 ±0.1 V)
0
0
0
1
VLVI1 (4.07 ±0.1 V)
0
0
1
0
VLVI2 (3.92 ±0.1 V)
0
0
1
1
VLVI3 (3.76 ±0.1 V)
0
1
0
0
VLVI4 (3.61 ±0.1 V)
0
1
0
1
VLVI5 (3.45 ±0.1 V)
0
1
1
0
VLVI6 (3.30 ±0.1 V)
0
1
1
1
VLVI7 (3.15 ±0.1 V)
1
0
0
0
VLVI8 (2.99 ±0.1 V)
1
0
0
1
VLVI9 (2.84 ±0.1 V)
1
0
1
0
VLVI10 (2.68 ±0.1 V)
1
0
1
1
VLVI11 (2.53 ±0.1 V)
1
1
0
0
VLVI12 (2.38 ±0.1 V)
1
1
0
1
VLVI13 (2.22 ±0.1 V)
1
1
1
0
VLVI14 (2.07 ±0.1 V)
1
1
1
1
VLVI15 (1.91 ±0.1 V)
Detection level
Note The reset value changes depending on the reset source.
If the LVIS register is reset by LVI, it is not reset but holds the current value. The value of this register is
reset to “0EH” if a reset other than by LVI is effected.
Cautions 1. Be sure to clear bits 4 to 7 to “0”.
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Cautions 2. Change the LVIS value with either of the following methods.
• When changing the value after stopping LVI
Stop LVI (LVION = 0).
Change the LVIS register.
Set to the mode used as an interrupt (LVIMD = 0).
Mask LVI interrupts (LVIMK = 1).
Enable LVI operation (LVION = 1).
Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
because an LVIIF flag may be set when LVI operation is enabled.
• When changing the value after setting to the mode used as an interrupt (LVIMD = 0)
Mask LVI interrupts (LVIMK = 1).
Set to the mode used as an interrupt (LVIMD = 0).
Change the LVIS register.
Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
because an LVIIF flag may be set when the LVIS register is changed.
3. When an input voltage from the external input pin (EXLVI) is detected, the detection
voltage (VEXLVI) is fixed. Therefore, setting of LVIS is not necessary.
(3) Port mode register 12 (PM12)
When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this time,
the output latch of P120 may be 0 or 1.
PM12 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 24-4. Format of Port Mode Register 12 (PM12)
Address: FFF2CH
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM12
1
1
1
1
1
1
1
PM120
PM120
P120 pin I/O mode selection
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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24.4 Operation of Low-Voltage Detector
The low-voltage detector can be used in the following two modes.
(1) Used as reset (LVIMD = 1)
• If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI), generates an internal reset signal
when VDD < VLVI, and releases internal reset when VDD ≥ VLVI.
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI), generates
an internal reset signal when EXLVI < VEXLVI, and releases internal reset when EXLVI ≥ VEXLVI.
Remark The low-voltage detector (LVI) can be set to ON by an option byte by default. If it is set to ON to raise
the power supply from the POC detection voltage (VPOR = 1.61 V (TYP.)) or lower, the internal reset
signal is generated when the supply voltage (VDD) < detection voltage (VLVI = 2.07 V ±0.2 V). After that,
the internal reset signal is generated when the supply voltage (VDD) < detection voltage (VLVI = 2.07 V
±0.1 V).
(2) Used as interrupt (LVIMD = 0)
• If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI). When VDD drops lower than VLVI
(VDD < VLVI) or when VDD becomes VLVI or higher (VDD ≥ VLVI), generates an interrupt signal (INTLVI).
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI = 1.21 V
±0.1 V). When EXLVI drops lower than VEXLVI (EXLVI < VEXLVI) or when EXLVI becomes VEXLVI or higher (EXLVI ≥
VEXLVI), generates an interrupt signal (INTLVI).
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is
more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0 of LVIM).
Remark LVIMD:
Bit 1 of low-voltage detection register (LVIM)
LVISEL: Bit 2 of LVIM
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24.4.1 When used as reset
(1) When detecting level of supply voltage (VDD)
(a) When LVI default start function stopped is set (LVIOFF = 1)
• When starting operation
Mask the LVI interrupt (LVIMK = 1).
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
Use software to wait for the following periods of time (Total 210 μs).
(VDD)) (default value).
register (LVIS).
• Operation stabilization time (10 μs (MAX.))
• Minimum pulse width (200 μs (MIN.))
Wait until it is checked that (supply voltage (VDD) ≥ detection voltage (VLVI)) by bit 0 (LVIF) of LVIM.
Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected).
Figure 24-5 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in
this timing chart correspond to to above.
Cautions 1. Be sure to execute . When LVIMK = 0, an interrupt may occur immediately after the
processing in .
2. If supply voltage (VDD) ≥ detection voltage (VLVI) when LVIMD is set to 1, an internal reset
signal is not generated.
• When stopping operation
Be sure to clear (0) LVIMD and then LVION by using a 1-bit memory manipulation instruction.
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Figure 24-5. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Bit: LVISEL = 0, Option Byte: LVIOFF = 1)
Set LVI to be
used for reset
Supply voltage (VDD)
VLVI
VPOR = 1.61 V (TYP.)
VPDR = 1.59 V (TYP.)
Time
LVIMK flag
(set by software)
H
LVISEL flag
(set by software)
L
Note 1
LVION flag
(set by software)
Not cleared
Not
cleared
Cleared
Wait time
LVIF flag
Cleared
Note 2
LVIMD flag
(set by software)
Not cleared
Not
cleared
Cleared
LVIRF flagNote 3
LVI reset signal
Cleared by
software
Cleared by
software
POC reset signal
Internal reset signal
Notes 1.
2.
3.
The LVIMK flag is set to “1” by reset signal generation.
The LVIIF flag of the interrupt request flag registers and the LVIF flag may be set (1).
LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 22 RESET
FUNCTION.
Remarks 1. to in Figure 24-5 above correspond to to in the description of “When starting
operation” in 24.4.1 (1) (a) When LVI default start function stopped is set (LVIOFF = 1).
2. VPOR: POC power supply rise detection voltage
VPDR: POC power supply fall detection voltage
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(b) When LVI default start function enabled is set (LVIOFF = 0)
• When starting operation
Start in the following initial setting state.
•
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation)
•
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (VDD))
•
Set the low-voltage detection level selection register (LVIS) to 0EH (default value: VLVI = 2.07 V ±0.1 V ).
•
Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected)
•
Set bit 0 (LVIF) of LVIM to 0 (“Supply voltage (VDD) ≥ detection voltage (VLVI)”)
Figure 24-6 shows the timing of the internal reset signal generated by the low-voltage detector.
• When stopping operation
Be sure to clear (0) LVIMD and then LVION by using a 1-bit memory manipulation instruction.
Caution Even when the LVI default start function is used, if it is set to LVI operation prohibition by the
software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts
after reset release. There is a period when low-voltage detection cannot be performed
normally, however, when a reset occurs due to WDT and illegal instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200 μs max.,
LVION = 1 is set upon reset occurrence, and the CPU starts operating without waiting for
the LVI stabilization time.
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Figure 24-6. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Bit: LVISEL = 0, Option Byte: LVIOFF = 0)
Interrupt operation mode is set
by setting LVIMD to 0
(LVI interrupt is masked)
Change LVI
detection
voltage (VLVI)
Reset mode is set
by setting LVIMD to 1
Supply voltage (VDD)
VLVI value after a change
VLVI = 2.07 V (TYP.)
VPOR = 1.61 V (TYP.)
VPDR = 1.59 V (TYP.)
Time
LVIMK flag
(set by software)
LVISEL flag
(set by software)
LVION flag
(set by software)
HNote 1
L
Not cleared
Not
cleared
H
LVIF flag
Cleared
LVIMD flag
(set by software)
Not
cleared
H
Not cleared
Cleared
Note 2
LVIRF flag
LVI reset signal
Cleared by
software
Cleared by
software
Cleared by
software
POC reset signal
Internal reset signal
Notes 1.
The LVIMK flag is set to “1” by reset signal generation.
2.
LVIRF is bit 0 of the reset control flag register (RESF).
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the LVIRF flag may become 1
from the beginning due to the power-on waveform.
For details of RESF, see CHAPTER 22 RESET FUNCTION.
Remark
VPOR: POC power supply rise detection voltage
VPDR: POC power supply fall detection voltage
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(2) When detecting level of input voltage from external input pin (EXLVI)
• When starting operation
Mask the LVI interrupt (LVIMK = 1).
Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from
external input pin (EXLVI)).
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
Use software to wait for the following periods of time (Total 210 μs).
• Operation stabilization time (10 μs (MAX.))
• Minimum pulse width (200 μs (MIN.))
Wait until it is checked that (input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI = 1.21 V
(TYP.))) by bit 0 (LVIF) of LVIM.
Set bit 1 (LVIMD) of LVIM to 1 (generates reset signal when the level is detected).
Figure 24-7 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in
this timing chart correspond to to above.
Cautions 1. Be sure to execute . When LVIMK = 0, an interrupt may occur immediately after the
processing in .
2. If input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI = 1.21 V (TYP.))
when LVIMD is set to 1, an internal reset signal is not generated.
3. Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
• When stopping operation
Be sure to clear (0) LVIMD and then LVION by using a 1-bit memory manipulation instruction.
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Figure 24-7. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Bit: LVISEL = 1)
Set LVI to be
used for reset
Input voltage from
external input pin (EXLVI)
VEXLVI
Time
LVIMK flag
(set by software)
HNote 1
LVISEL flag
(set by software)
Not cleared
Not cleared
Not cleared
LVION flag
(set by software)
Not cleared
Not cleared
Not cleared
Wait time
LVIF flag
Note 2
LVIMD flag
(set by software)
Not cleared
Not cleared
Not cleared
LVIRF flagNote 3
LVI reset signal
Cleared by
software
Cleared by
software
Internal reset signal
Notes 1.
The LVIMK flag is set to “1” by reset signal generation.
2.
The LVIIF flag of the interrupt request flag registers and the LVIF flag may be set (1).
3.
LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 22 RESET
FUNCTION.
Remark
to in Figure 24-7 above correspond to to in the description of “When starting operation” in
24.4.1 (2) When detecting level of input voltage from external input pin (EXLVI).
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24.4.2 When used as interrupt
(1) When detecting level of supply voltage (VDD)
(a) When LVI default start function stopped is set (LVIOFF = 1)
• When starting operation
Mask the LVI interrupt (LVIMK = 1).
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
(VDD)) (default value).
Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection
register (LVIS).
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
Use software to wait for the following periods of time (Total 210 μs).
• Operation stabilization time (10 μs (MAX.))
• Minimum pulse width (200 μs (MIN.))
Confirm that “supply voltage (VDD) ≥ detection voltage (VLVI)” when detecting the falling edge of VDD, or
“supply voltage (VDD) < detection voltage (VLVI)” when detecting the rising edge of VDD, at bit 0 (LVIF) of
LVIM.
Clear the interrupt request flag of LVI (LVIIF) to 0.
Release the interrupt mask flag of LVI (LVIMK).
Execute the EI instruction (when vector interrupts are used).
Figure 24-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this
timing chart correspond to to above.
• When stopping operation
Be sure to clear (0) LVION by using a 1-bit memory manipulation instruction.
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Figure 24-8. Timing of Low-Voltage Detector Interrupt Signal Generation
(Bit: LVISEL = 0, Option Byte: LVIOFF = 1)
Supply voltage (VDD)
VLVI
VPOR = 1.61 V (TYP.)
VPDR = 1.59 V (TYP.)
Note 3
Note 3
Time
LVIMK flag
(set by software)
Note 1
LVISEL flag
(set by software)
Cleared by software
L
LVION flag
(set by software)
Wait time
LVIF flag
Note 2
INTLVI
Note 2
LVIIF flag
Note 2
Cleared by software
LVIMD flag
(set by software) L
Internal reset signal
Notes 1.
The LVIMK flag is set to “1” by reset signal generation.
2.
The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
3.
If LVI operation is disabled when the supply voltage (VDD) is less than or equal to the detection voltage
(VLVI), an interrupt request signal (INTLVI) is generated and LVIIF may be set to 1.
Remarks 1. to in Figure 24-8 above correspond to to in the description of “When starting
operation” in 24.4.2 (1) (a) When LVI default start function stopped is set (LVIOFF = 1).
2. VPOR: POC power supply rise detection voltage
VPDR: POC power supply fall detection voltage
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(b) When LVI default start function enabled is set (LVIOFF = 0)
• When starting operation
Start in the following initial setting state.
•
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation)
•
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
•
Set the low-voltage detection level selection register (LVIS) to 0EH (default value: VLVI = 2.07 V ±0.1
•
Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected)
•
Set bit 0 (LVIF) of LVIM to 0 (Detects falling edge “Supply voltage (VDD) ≥ detection voltage (VLVI)”)
(VDD))
V ).
Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default
Release the interrupt mask flag of LVI (LVIMK).
Execute the EI instruction (when vector interrupts are used).
value).
Figure 24-9 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this
timing chart correspond to to above.
• When stopping operation
Be sure to clear (0) LVION by using a 1-bit memory manipulation instruction.
Cautions 1. Even when the LVI default start function is used, if it is set to LVI operation prohibition by the
software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts after
reset release. There is a period when low-voltage detection cannot be performed normally,
however, when a reset occurs due to WDT and illegal instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200 μs max.,
LVION = 1 is set upon reset occurrence, and the CPU starts operating without waiting for
the LVI stabilization time.
2. When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the LVIRF flag may
become 1 from the beginning due to the power-on waveform.
For details of RESF, see CHAPTER 22 RESET FUNCTION.
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Figure 24-9. Timing of Low-Voltage Detector Interrupt Signal Generation
(Bit: LVISEL = 0, Option Byte: LVIOFF = 0)
Mask LVI interrupts
(LVIMK = 1)
Change LVI
detection
voltage (VLVI)
Cancelling the
LVI interrupt mask
(LVIMK = 0)
Supply voltage (VDD)
VLVI value after a change
VLVI = 2.07 V (TYP.)
VPOR = 1.61 V (TYP.)
VPDR = 1.59 V (TYP.)
Note 2
Note 2
Time
LVIMK flag
(set by software)
Note 1
LVISEL flag
(set by software)
Cleared by software
L
LVION flag
(set by software)
LVIF flag
INTLVI
Note 3
LVIIF flag
Cleared by software
LVIMD flag
(set by software)
Internal reset signal
Notes 1.
2.
The LVIMK flag is set to “1” by reset signal generation.
If LVI operation is disabled when the supply voltage (VDD) is less than or equal to the detection voltage
(VLVI), an interrupt request signal (INTLVI) is generated and LVIIF may be set to 1.
3.
The LVIIF flag may be set when the LVI detection voltage is changed.
Remarks 1. to in Figure 24-9 above correspond to to in the description of “When starting
operation” in 24.4.2 (1) (b) When LVI default start function enabled is set (LVIOFF = 0).
2. VPOR: POC power supply rise detection voltage
VPDR: POC power supply fall detection voltage
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(2) When detecting level of input voltage from external input pin (EXLVI)
• When starting operation
Mask the LVI interrupt (LVIMK = 1).
Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from
external input pin (EXLVI)).
Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
Use software to wait for the following periods of time (Total 210 μs).
• Operation stabilization time (10 μs (MAX.))
• Minimum pulse width (200 μs (MIN.))
Confirm that “input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI = 1.21 V (TYP.))”
when detecting the falling edge of EXLVI, or “input voltage from external input pin (EXLVI) < detection
voltage (VEXLVI = 1.21 V (TYP.))” when detecting the rising edge of EXLVI, at bit 0 (LVIF) of LVIM.
Clear the interrupt request flag of LVI (LVIIF) to 0.
Release the interrupt mask flag of LVI (LVIMK).
Execute the EI instruction (when vector interrupts are used).
Figure 24-10 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this
timing chart correspond to to above.
Caution Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
• When stopping operation
Be sure to clear (0) LVION by using a 1-bit memory manipulation instruction.
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Figure 24-10. Timing of Low-Voltage Detector Interrupt Signal Generation
(Bit: LVISEL = 1)
Input voltage from
external input pin (EXLVI)
VEXLVI
Note 3
LVIMK flag
(set by software)
Note 3
Time
Note 1
Cleared by software
LVISEL flag
(set by software)
LVION flag
(set by software)
Wait time
LVIF flag
Note 2
INTLVI
Note 2
LVIIF flag
Note 2
LVIMD flag
(set by software)
Notes 1.
Cleared by software
L
The LVIMK flag is set to “1” by reset signal generation.
2.
The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
3.
If LVI operation is disabled when the input voltage of external input pin (EXLVI) is less than or equal to
the detection voltage (VEXLVI), an interrupt request signal (INTLVI) is generated and LVIIF may be set to 1.
Remark
to in Figure 24-10 above correspond to to in the description of “When starting operation” in
24.4.2 (2) When detecting level of input voltage from external input pin (EXLVI).
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24.5 Cautions for Low-Voltage Detector
(1) Measures method when supply voltage (VDD) frequently fluctuates in the vicinity of the LVI detection voltage
(VLVI)
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage
(VLVI), the operation is as follows depending on how the low-voltage detector is used.
Operation example 1: When used as reset
The system may be repeatedly reset and released from the reset status.
The time from reset release through microcontroller operation start can be set arbitrarily by the following
action.
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports (see Figure 24-11).
Remark If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above words
change as follows.
• Supply voltage (VDD)
→ Input voltage from external input pin (EXLVI)
• Detection voltage (VLVI) → Detection voltage (VEXLVI = 1.21 V)
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Figure 24-11. Example of Software Processing After Reset Release (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
Reset
; Check the reset source, etc.Note
Initialization
processing
LVI reset
; Setting of detection level by LVIS.
The low-voltage detector operates (LVION = 1).
Setting LVI
; fCLK = Internal high-speed oscillation clock (4.08 MHz (MAX.)) (default)
Source: fCLK (4.08 MHz (MAX.))/211,
where comparison value = 100: ≅ 50 ms
Timer starts (TS0n = 1).
Setting timer array unit
(to measure 50 ms)
Clearing WDT
Detection
voltage or higher
(LVIF = 0?)
Yes
No
Restarting timer array unit
(TT0n = 1 → TS0n = 1)
No
; The timer counter is cleared and the timer is started.
50 ms has passed?
(TMIF0n = 1?)
Yes
; Initial setting for port.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
Initialization
processing
Note A flowchart is shown on the next page.
Remarks 1.
If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above
words change as follows.
• Supply voltage (VDD)
→ Input voltage from external input pin (EXLVI)
• Detection voltage (VLVI) → Detection voltage (VEXLVI = 1.21 V)
2.
n = 0 to 7
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Figure 24-11. Example of Software Processing After Reset Release (2/2)
• Checking reset source
Check reset source
TRAP of RESF
register = 1?
Yes
No
Reset processing by
illegal instruction execution Note
WDRF of RESF
register = 1?
Yes
No
Reset processing by
watchdog timer
LVIRF of RESF
register = 1?
No
Yes
Power-on-clear/external
reset generated
Reset processing by
low-voltage detector
Note
When instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
Remark If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above words
change as follows.
• Supply voltage (VDD)
→ Input voltage from external input pin (EXLVI)
• Detection voltage (VLVI) → Detection voltage (VEXLVI = 1.21 V)
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Operation example 2: When used as interrupt
Interrupt requests may be generated frequently.
Take the following action.
Confirm that “supply voltage (VDD) ≥ detection voltage (VLVI)” when detecting the falling edge of VDD, or “supply
voltage (VDD) < detection voltage (VLVI)” when detecting the rising edge of VDD, in the servicing routine of the LVI
interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 1 (LVIIF) of interrupt request
flag register 0L (IF0L) to 0.
For a system with a long supply voltage fluctuation period near the LVI detection voltage, take the above action
after waiting for the supply voltage fluctuation time.
Remark If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above words
change as follows.
• Supply voltage (VDD)
→ Input voltage from external input pin (EXLVI)
• Detection voltage (VLVI) → Detection voltage (VEXLVI = 1.21 V)
(2) Delay from the time LVI reset source is generated until the time LVI reset has been generated or released
There is some delay from the time supply voltage (VDD) < LVI detection voltage (VLVI) until the time LVI reset has been
generated.
In the same way, there is also some delay from the time LVI detection voltage (VLVI) ≤ supply voltage (VDD) until the
time LVI reset has been released (see Figure 24-12).
Figure 24-12. Delay from the time LVI reset source is generated until the time LVI reset has been generated or released
Supply voltage (VDD)
VLVI
Time
LVIF flag
LVI reset signal
:
Minimum pulse width (200 μs (MIN.))
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CHAPTER 25 REGULATOR
CHAPTER 25 REGULATOR
25.1 Regulator Overview
All 78K0R/Lx3 microcontroller products contain a circuit for operating the device with a constant voltage. At this time, in
order to stabilize the regulator output voltage, connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
The regulator output voltage is normally 2.4 V (TYP.), and in the low-power consumption mode, 1.8 V (TYP.).
25.2 Registers Controlling Regulator
(1) Regulator mode control register (RMC)
This register sets the output voltage of the regulator.
RMC is set with an 8-bit memory manipulation instruction.
Reset input sets this register to 00H.
Figure 25-1. Format of Regulator Mode Control Register (RMC)
Address: F00F4H
Symbol
After reset: 00H
7
R/W
6
5
4
3
2
1
0
RMC
RMC[7:0]
Control of output voltage of regulator
5AH
Fixed to low-power consumption mode (1.8 V)
00H
Switches normal power mode (2.4 V) and low-power consumption mode (1.8 V) according to the
condition (refer to Table 25-1)
Other than
Setting prohibited
above
Cautions 1. The RMC register can be rewritten only in the low-power consumption mode (refer to Table
25-1). In other words, rewrite this register during CPU operation with the subsystem clock
(fXT) while the high-speed system clock (fMX), the high-speed internal oscillation clock, and the
20 MHz internal high-speed oscillation clock (fIH20) are both stopped.
2. When using the setting fixed to the low consumption current mode, the RMC register can be
used in the following cases.
fCLK ≤ 1 MHz and external oscillator (X1 clock (fX), external main system clock (fEX)) stop.
fCLK ≤ 1 MHz, fX/fEX ≤ 5 MHz and the internal high-speed oscillator stop.
Both the internal high-speed oscillator and external oscillator (fX/fEX ≤ 5 MHz) stop or either
one stops.
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Cautions 3. In low-power consumption mode, use the regulator with fCLK fixed to 1 MHz when executing
self programming.
4. A wait is required to change the operation speed mode control register (OSMC) after
changing the RMC register.
Wait for 2 ms by software when setting to low-power
consumption mode and 10 μs when setting to normal power mode, as described in the
procedure shown below.
• When setting to low-power consumption mode
Select a frequency of 1 MHz for fCLK.
Set RMC to 5AH (set the regulator to low-power consumption mode).
Wait for 2 ms.
Set FLPC and FSEL of OSMC to 1 and 0, respectively.
• When setting to normal power mode
Set RMC to 00H (set the regulator to normal power mode).
Wait for 10 μs.
Change FLPC and FSEL of OSMC.
Change the fCLK frequency.
Table 25-1. Regulator Output Voltage Conditions
Mode
Low-power
consumption mode
Output Voltage
1.8 V
Condition
In STOP mode (except during OCD mode)
When both the high-speed system clock (fMX), the high-speed internal
oscillation clock (fIH), and the 20 MHz internal high-speed oscillation clock
(fIH20) are stopped during CPU operation with the subsystem clock (fSUB)
When both the high-speed system clock (fMX), the high-speed internal
oscillation clock (fIH), and the 20 MHz internal high-speed oscillation clock
(fIH20) are stopped during the HALT mode when the CPU operation with the
subsystem clock (fSUB) has been set
Normal power mode
2.4 V
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CHAPTER 26 OPTION BYTE
CHAPTER 26 OPTION BYTE
26.1 Functions of Option Bytes
Addresses 000C0H to 000C3H of the flash memory of the 78K0R/Lx3 microcontrollers form an option byte area.
Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H).
Upon power application or resetting and starting, an option byte is automatically referenced and a specified function is
set. When using the product, be sure to set the following functions by using the option bytes.
To use the boot swap operation during self programming, 000C0H to 000C3H are replaced by 010C0H to 010C3H.
Therefore, set the same values as 000C0H to 000C3H to 010C0H to 010C3H.
Caution Be sure to set FFH to 000C2H (000C2H/010C2H when the boot swap operation is used).
26.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H)
(1) 000C0H/010C0H
{ Operation of watchdog timer
• Operation is stopped or enabled in the HALT or STOP mode.
{ Setting of interval time of watchdog timer
{ Operation of watchdog timer
• Operation is stopped or enabled.
{ Setting of window open period of watchdog timer
{ Setting of interval interrupt of watchdog timer
• Used or not used
Caution Set the same value as 000C0H to 010C0H when the boot swap operation is used because
000C0H is replaced by 010C0H.
(2) 000C1H/010C1H
{ Setting of LVI upon reset release (upon power application)
• LVI is ON or OFF by default upon reset release (reset by RESET pin excluding LVI, POC, WDT, or illegal
instructions).
{ Setting of internal high-speed oscillator frequency
• Select from 1 MHz, 8 MHz, or 20 MHz.
Caution Set the same value as 000C1H to 010C1H when the boot swap operation is used because
000C1H is replaced by 010C1H.
(3) 000C2H/010C2H
{ Be sure to set FFH, as these addresses are reserved areas.
Caution Set FFH to 010C2H when the boot swap operation is used because 000C2H is replaced by
010C2H.
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26.1.2 On-chip debug option byte (000C3H/ 010C3H)
{ Control of on-chip debug operation
• On-chip debug operation is disabled or enabled.
{ Handling of data of flash memory in case of failure in on-chip debug security ID authentication
• Data of flash memory is erased or not erased in case of failure in on-chip debug security ID
authentication.
Caution Set the same value as 000C3H to 010C3H when the boot swap operation is used because
000C3H is replaced by 010C3H.
26.2 Format of User Option Byte
The format of user option byte is shown below.
Figure 26-1. Format of User Option Byte (000C0H/010C0H) (1/2)
Note 1
Address: 000C0H/010C0H
7
6
5
4
3
2
1
0
WDTINIT
WINDOW1
WINDOW0
WDTON
WDCS2
WDCS1
WDCS0
WDSTBYON
WDTINIT
Use of interval interrupt of watchdog timer
0
Interval interrupt is not used.
1
Interval interrupt is generated when 75% of the overflow time is reached.
WINDOW1
WINDOW0
Watchdog timer window open period
0
0
Setting prohibited
0
1
50%
1
0
75%
1
1
100%
WDTON
Note 2
Operation control of watchdog timer counter
0
Counter operation disabled (counting stopped after reset)
1
Counter operation enabled (counting started after reset)
WDCS2
WDCS1
WDCS0
Watchdog timer overflow time
0
0
0
2 /fIL (3.88 ms)
0
0
1
2 /fIL (7.76 ms)
0
1
0
2 /fIL (15.52 ms)
0
1
1
2 /fIL (31.03 ms)
1
0
0
2 /fIL (124.12 ms)
1
0
1
2 /fIL (496.48 ms)
1
1
0
2 /fIL (992.97 ms)
1
1
1
2 /fIL (3971.88 ms)
(fIL = 33 kHz (MAX.))
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Figure 26-1. Format of User Option Byte (000C0H/010C0H) (2/2)
Note 1
Address: 000C0H/010C0H
7
6
5
4
3
2
1
0
WDTINIT
WINDOW1
WINDOW0
WDTON
WDCS2
WDCS1
WDCS0
WDSTBYON
WDSTBYON
Notes 1.
Operation control of watchdog timer counter (HALT/STOP mode)
Note 2
0
Counter operation stopped in HALT/STOP mode
1
Counter operation enabled in HALT/STOP mode
Set the same value as 000C0H to 010C0H when the boot swap operation is used because 000C0H is
replaced by 010C0H.
2.
The window open period is 100% when WDSTBYON = 0, regardless the value of WINDOW1 and
WINDOW0.
Caution The watchdog timer continues its operation during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the overflow
time and window size taking this delay into consideration.
Remark
fIL: Internal low-speed oscillation clock frequency
Figure 26-2. Format of User Option Byte (000C1H/010C1H)
Note 1
Address: 000C1H/010C1H
7
6
5
4
3
2
1
0
1
1
1
1
1
FRQSEL2
FRQSEL1
LVIOFF
FRQSEL2
FRQSEL1
0
1
8 MHz/20 MHz
1
0
1 MHz
1
1
8 MHz
Other than the above
Internal high-speed oscillator frequency
Note 3
Setting prohibited
LVIOFF
Notes 1.
Note 2
Setting of LVI on power application
0
LVI is ON by default (LVI default start function enabled) upon reset release (upon power
application)
1
LVI is OFF by default (LVI default start function stopped) upon reset release (upon power
application)
Set the same value as 000C1H to 010C1H when the boot swap operation is used because 000C1H is
replaced by 010C1H.
2.
When 8 MHz or 20 MHz has been selected, the 8 MHz internal high-speed oscillator automatically starts
oscillating after reset release.
To use the 20 MHz internal high-speed oscillator to operate the
microcontroller, oscillation is started by setting bit 0 (DSCON) of the 20 MHz internal high-speed oscillation
control register (DSCCTL) to 1 with VDD ≥ 2.7 V. The circuit cannot be changed to a 1 MHz internal highspeed oscillator while the microcontroller operates.
3.
When 1 MHz has been selected, the microcontroller operates on the 1 MHz internal high-speed oscillator
after reset release. The circuit cannot be changed to an 8 MHz or 20 MHz internal high-speed oscillator
while the microcontroller operates.
(Cautions are listed on the next page.)
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Cautions 1. Be sure to set bits 7 to 3 to “1”.
2.
Even when the LVI default start function is used, if it is set to LVI operation prohibition by the
software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts after reset
release. There is a period when low-voltage detection cannot be performed normally, however,
when a reset occurs due to WDT and illegal instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200 μs max., LVION =
1 is set upon reset occurrence, and the CPU starts operating without waiting for the LVI
stabilization time.
Figure 26-3. Format of Option Byte (000C2H/010C2H)
Note
Address: 000C2H/010C2H
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
Note Be sure to set FFH to 000C2H, as these addresses are reserved areas. Also set FFH to 010C2H when the boot
swap operation is used because 000C2H is replaced by 010C2H.
26.3 Format of On-chip Debug Option Byte
The format of on-chip debug option byte is shown below.
Figure 26-4. Format of On-chip Debug Option Byte (000C3H/010C3H)
Note
Address: 000C3H/010C3H
7
6
5
4
3
2
1
0
OCDENSET
0
0
0
0
1
0
OCDERSD
OCDENSET
OCDERSD
0
0
Disables on-chip debug operation.
0
1
Setting prohibited
1
0
Erases data of flash memory in case of failures in enabling on-chip debugging and
authenticating on-chip debug security ID.
1
1
Does not erases data of flash memory in case of failures in enabling on-chip
debugging and authenticating on-chip debug security ID.
Control of on-chip debug operation
Note Set the same value as 000C3H to 010C3H when the boot swap operation is used because 000C3H is replaced
by 010C3H.
Caution Bits 7 and 0 (OCDENSET and OCDERSD) can only be specified a value.
Be sure to set 000010B to bits 6 to 1.
Remark The value on bits 3 to 1 will be written over when the on-chip debug function is in use and thus it will become
unstable after the setting.
However, be sure to set the default values (0, 1, and 0) to bits 3 to 1 at setting.
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26.4 Setting of Option Byte
The user option byte and on-chip debug option byte can be set using the RA78K0R or PM+ linker option, in addition to
describing to the source. When doing so, the contents set by using the linker option take precedence, even if descriptions
exist in the source, as mentioned below.
See the RA78K0R Assembler Package User’s Manual for how to set the linker option.
A software description example of the option byte setting is shown below.
OPT
CSEG
OPT_BYTE
DB
36H
; Does not use interval interrupt of watchdog timer,
; Enables watchdog timer operation,
; Window open period of watchdog timer is 50%,
10
; Overflow time of watchdog timer is 2 /fIL,
; Stops watchdog timer operation during HALT/STOP mode
DB
0FBH
; Select 8 MHz or 20 MHz for internal high-speed oscillator
DB
0FFH
; Reserved area
DB
85H
; Stops LVI default start function
; Enables on-chip debug operation, does not erase flash memory
; data when security ID authorization fails
When the boot swap function is used during self programming, 000C0H to 000C3H is switched to 010C0H to 010C3H.
Describe to 010C0H to 010C3H, therefore, the same values as 000C0H to 000C3H as follows.
OPT2
CSEG
AT
DB
010C0H
36H
; Does not use interval interrupt of watchdog timer,
; Enables watchdog timer operation,
; Window open period of watchdog timer is 50%,
10
; Overflow time of watchdog timer is 2 /fIL,
; Stops watchdog timer operation during HALT/STOP mode
DB
0FBH
; Select 8 MHz or 20 MHz for internal high-speed oscillator
DB
0FFH
; Reserved area
DB
85H
; Stops LVI default start function
; Enables on-chip debug operation, does not erase flash memory
; data when security ID authorization fails
Caution To specify the option byte by using assembly language, use OPT_BYTE as the relocation attribute
name of the CSEG pseudo instruction. To specify the option byte to 010C0H to 010C3H in order to
use the boot swap function, use the relocation attribute AT to specify an absolute address.
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CHAPTER 27 FLASH MEMORY
The 78K0R/Lx3 microcontrollers incorporate the flash memory to which a program can be written, erased, and
overwritten while mounted on the board.
27.1 Writing with Flash Memory Programmer
Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.
(1) On-board programming
The contents of the flash memory can be rewritten after the 78K0R/Lx3 microcontrollers have been mounted on the
target system. The connectors that connect the dedicated flash memory programmer must be mounted on the target
system.
(2) Off-board programming
Data can be written to the flash memory with a dedicated program adapter (FA series) before the 78K0R/Lx3
microcontrollers are mounted on the target system.
Remark
The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.
27.2 Programming Environment
The environment required for writing a program to the flash memory of the 78K0R/Lx3 microcontrollers are illustrated
below.
Figure 27-1. Environment for Writing Program to Flash Memory
POWER
RS-232C
FLMD0
VDD
PASS
BUSY
NG
VSS
USB
START
PG-FP5
Host machine
RESET
TOOL0 (dedicated single-line UART)
78K0R/Lx3
microcontrollers
Dedicated flash
memory programmer
A host machine that controls the dedicated flash memory programmer is necessary.
To interface between the dedicated flash memory programmer and the 78K0R/Lx3 microcontrollers, the TOOL0 pin is
used for manipulation such as writing and erasing via a dedicated single-line UART. To write the flash memory off-board,
a dedicated program adapter (FA series) is necessary.
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27.3 Communication Mode
Communication between the dedicated flash memory programmer and the 78K0R/Lx3 microcontrollers is established
by serial communication using the TOOL0 pin via a dedicated single-line UART of the 78K0R/Lx3 microcontrollers.
Transfer rate: 115,200 bps to 1,000,000 bps
Figure 27-2. Communication with Dedicated Flash Memory Programmer
POWER
BUSY
PASS
NG
START
FLMD0
FLMD0
VDD
VDD/EVDD
GND
VSS/EVSS
/RESET
RESET
SI/RxD
TOOL0
78K0R/Lx3
microcontrollers
PG-FP5
Dedicated flash
memory programmer
SO/TxD
When using the FlashPro5 as the dedicated flash memory programmer, the FlashPro5 generates the following signals
for the 78K0R/Lx3 microcontrollers. For details, refer to the user’s manual for the FlashPro5.
Table 27-1. Pin Connection
FlashPro5
Signal Name
I/O
78K0R/Lx3 microcontrollers
Pin Function
Pin Name
FLMD0
Output
Mode signal
FLMD0
VDD
I/O
VDD voltage generation/power monitoring
VDD, EVDD, AVDD0, AVDD1
Ground
VSS, EVSS, AVSS
−
GND
CLK
Output
Clock output
/RESET
Output
Reset signal
RESET
SI/RxD
Input
Receive signal
TOOL0
SO/TxD
Output
Transmit signal
SCK
Output
Transfer clock
Remark
Connection
−
×
−
×
: Be sure to connect the pin.
×: The pin does not have to be connected.
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Examples of the recommended connection (μPD78F1508A) when using the adapter for flash memory writing are
shown below.
Figure 27-3. Example of Wiring Adapter for Flash Memory Writing (μPD78F1508A)
VDD(2.7 to 5.5 V)
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
GND
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
GND
VDD
VDD2
SI/RxDNotes 1, 2 SO/TxDNote 2
SCK
CLK
/RESET
FLMD0
WRITER INTERFACE
Notes 1.
2.
This pin is not required to be connected when using PG-FP5 or FL-PR5.
Connect SI/RxD or SO/TxD when using QB-MINI2.
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27.4 Connection of Pins on Board
To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be
provided on the target system.
First provide a function that selects the normal operation mode or flash memory
programming mode on the board.
When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the
same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after
reset, the pins must be handled as described below.
27.4.1 FLMD0 pin
(1) In flash memory programming mode
Directly connect this pin to a flash memory programmer when data is written by the flash memory programmer. This
supplies a writing voltage of the VDD level to the FLMD0 pin.
The FLMD0 pin does not have to be pulled down externally because it is internally pulled down by reset. To pull it
down externally, use a resistor of 1 kΩ to 200 kΩ.
(2) In normal operation mode
It is recommended to leave this pin open during normal operation.
The FLMD0 pin must always be kept at the VSS level before reset release but does not have to be pulled down
externally because it is internally pulled down by reset.
However, pulling it down must be kept selected (i.e.,
FLMDPUP = “0”, default value) by using bit 7 (FLMDPUP) of the background event control register (BECTL) (see 27.5
(1) Back ground event control register). To pull it down externally, use a resistor of 200 kΩ or smaller.
Self programming and the rewriting of flash memory with the programmer can be prohibited using hardware, by
directly connecting this pin to the VSS pin.
(3) In self programming mode
It is recommended to leave this pin open when using the self programming function. To pull it down externally, use a
resistor of 100 kΩ to 200 kΩ.
In the self programming mode, the setting is switched to pull up in the self programming library.
Figure 27-4. FLMD0 Pin Connection Example
78K0R/Lx3
microcontrollers
Dedicated flash memory programmer
connection pin
FLMD0
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27.4.2 TOOL0 pin
In the flash memory programming mode, connect this pin directly to the dedicated flash memory programmer or pull it
up by connecting it to EVDD via an external resistor.
When on-chip debugging is enabled in the normal operation mode, pull this pin up by connecting it to VDD via an
external resistor, and be sure to keep inputting the VDD level to the TOOL0 pin before reset is released (pulling down this
pin is prohibited).
Remark
The SAU and IICA pins are not used for communication between the 78K0R/Lx3 microcontrollers and
dedicated flash memory programmer, because single-line UART is used.
27.4.3 RESET pin
Signal conflict will occur if the reset signal of the dedicated flash memory programmer is connected to the RESET pin
that is connected to the reset signal generator on the board. To prevent this conflict, isolate the connection with the reset
signal generator.
The flash memory will not be correctly programmed if the reset signal is input from the user system while the flash
memory programming mode is set . Do not input any signal other than the reset signal of the dedicated flash memory
programmer.
Figure 27-5. Signal Conflict (RESET Pin)
78K0R/Lx3
microcontrollers
Signal conflict
Input pin
Dedicated flash memory programmer
connection pin
Another device
Output pin
In the flash memory programming mode, a signal output by another device
will conflict with the signal output by the dedicated flash memory
programmer. Therefore, isolate the signal of another device.
27.4.4 Port pins
When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same
status as that immediately after reset.
If external devices connected to the ports do not recognize the port status
immediately after reset, the port pin must be connected to VDD or VSS via a resistor.
27.4.5 REGC pin
Connect the REGC pin to GND via a capacitor (0.47 to 1 μF) in the same manner as during normal operation.
Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
27.4.6 X1 and X2 pins
Connect X1 and X2 in the same status as in the normal operation mode.
Remark
In the flash memory programming mode, the internal high-speed oscillation clock (fIH) is used.
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27.4.7 Power supply
To use the supply voltage output of the flash memory programmer, connect the VDD pin to VDD of the flash memory
programmer, and the VSS pin to GND of the flash memory programmer.
To use the on-board supply voltage, connect in compliance with the normal operation mode.
However, when using the on-board supply voltage, be sure to connect the VDD and VSS pins to VDD and GND of the
flash memory programmer to use the power monitor function with the flash memory programmer.
Supply the same other power supplies (EVDD, EVSS, AVDD0, AVDD1, and AVSS) as those in the normal operation mode.
27.5 Registers Controlling Flash Memory
(1) Background event control register (BECTL)
Even if the FLMD0 pin is not controlled externally, it can be controlled by software with the BECTL register to set the
self-programming mode.
However, depending on the processing of the FLMD0 pin, it may not be possible to set the self-programming mode by
software. When using BECTL, leaving the FLMD0 pin open is recommended. When pulling it down externally, use a
resistor with a resistance of 100 kΩ or more. In addition, in the normal operation mode, use BECTL with the pull
down selection. In the self-programming mode, the setting is switched to pull up in the self- programming library.
The BECTL register is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets this register to 00H.
Figure 27-6. Format of Background Event Control Register (BECTL)
Address: FFFBEH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
BECTL
FLMDPUP
0
0
0
0
0
0
0
FLMDPUP
Software control of FLMD0 pin
0
Selects pull-down
1
Selects pull-up
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27.6 Programming Method
27.6.1 Controlling flash memory
The following figure illustrates the procedure to manipulate the flash memory.
Figure 27-7. Flash Memory Manipulation Procedure
Start
Controlling FLMD0 pin and RESET pin
Flash memory programming
mode is set
Manipulate flash memory
End?
No
Yes
End
27.6.2 Flash memory programming mode
To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78K0R/Lx3
microcontrollers in the flash memory programming mode. To set the mode, set the FLMD0 pin and TOOL0 pin to VDD and
clear the reset signal.
Change the mode by using a jumper when writing the flash memory on-board.
Figure 27-8. Flash Memory Programming Mode
VDD
5.5 V
0V
VDD
RESET
0V
VDD
FLMD0
0V
VDD
TOOL0
0V
Flash memory programming mode
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Table 27-2. Relationship Between FLMD0 Pin and Operation Mode After Reset Release
FLMD0
Operation Mode
0
Normal operation mode
VDD
Flash memory programming mode
27.6.3 Selecting communication mode
Communication mode of the 78K0R/Lx3 microcontrollers as follows.
Table 27-3. Communication Modes
Communication
Mode
1-line mode
Standard Setting
Port
Speed
Note 2
UART-ch0
1 Mbps
Note 1
Pins Used
Frequency
Multiply Rate
−
−
TOOL0
(dedicated
single-line
UART)
Notes 1. Selection items for Standard settings on GUI of the flash memory programmer.
2. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART
communication, thoroughly evaluate the slew as well as the baud rate error.
27.6.4 Communication commands
The 78K0R/Lx3 microcontrollers communicate with the dedicated flash memory programmer by using commands. The
signals sent from the flash memory programmer to the 78K0R/Lx3 microcontrollers are called commands, and the signals
sent from the 78K0R/Lx3 microcontrollers to the dedicated flash memory programmer are called response.
Figure 27-9. Communication Commands
POWER
PASS
BUSY
NG
Command
Response
START
PG-FP5
78K0R/Lx3
microcontrollers
Dedicated flash
memory programmer
The flash memory control commands of the 78K0R/Lx3 microcontrollers are listed in the table below.
All these
commands are issued from the programmer, and the 78K0R/Lx3 microcontrollers perform processing corresponding to the
respective commands.
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Table 27-4. Flash Memory Control Commands
Classification
Verify
Command Name
Function
Compares the contents of a specified area of the flash memory with
Verify
data transmitted from the programmer.
Erase
Blank check
Chip Erase
Erases the entire flash memory.
Block Erase
Erases a specified area in the flash memory.
Block Blank Check
Checks if a specified block in the flash memory has been correctly
erased.
Write
Programming
Writes data to a specified area in the flash memory.
Getting information
Silicon Signature
Gets 78K0R/Lx3 microcontrollers information (such as the part number
and flash memory configuration).
Version Get
Gets the 78K0R/Lx3 microcontrollers firmware version.
Checksum
Gets the checksum data for a specified area.
Security
Security Set
Sets security information.
Others
Reset
Used to detect synchronization status of communication.
Baud Rate Set
Sets baud rate when UART communication mode is selected.
The 78K0R/Lx3 microcontrollers return a response for the command issued by the dedicated flash memory
programmer. The response names sent from the 78K0R/Lx3 microcontrollers are listed below.
Table 27-5. Response Names
Response Name
Function
ACK
Acknowledges command/data.
NAK
Acknowledges illegal command/data.
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27.7 Security Settings
The 78K0R/Lx3 microcontrollers support a security function that prohibits rewriting the user program written to the
internal flash memory, so that the program cannot be changed by an unauthorized person.
The operations shown below can be performed using the Security Set command. The security setting is valid when the
programming mode is set next.
• Disabling batch erase (chip erase)
Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is
prohibited by this setting during on-board/off-board programming. Once execution of the batch erase (chip erase)
command is prohibited, all of the prohibition settings (including prohibition of batch erase (chip erase)) can no longer
be cancelled.
Caution After the security setting for the batch erase is set, erasure cannot be performed for the device. In
addition, even if a write command is executed, data different from that which has already been
written to the flash memory cannot be written, because the erase command is disabled.
• Disabling block erase
Execution of the block erase command for a specific block in the flash memory is prohibited during on-board/off-board
programming. However, blocks can be erased by means of self programming.
• Disabling write
Execution of the write and block erase commands for entire blocks in the flash memory is prohibited during onboard/off-board programming. However, blocks can be written by means of self programming.
• Disabling rewriting boot cluster 0
Execution of the batch erase (chip erase) command, block erase command, and write command on boot cluster 0
(00000H to 00FFFH) in the flash memory is prohibited by this setting.
Caution If a security setting that rewrites boot cluster 0 has been applied, boot cluster 0 of that device will
not be rewritten, and the entire flash memory of the device will not be erased in batch.
The batch erase (chip erase), block erase, write commands, and rewriting boot cluster 0 are enabled by the default
setting when the flash memory is shipped. Security can be set by on-board/off-board programming and self programming.
Each security setting can be used in combination.
All the security settings are cleared by executing the batch erase (chip erase) command.
Table 27-6 shows the relationship between the erase and write commands when the 78K0R/Lx3 microcontrollers
security function is enabled.
Remark To prohibit writing and erasing during self-programming, use the flash sealed window function (see 27.8.2 for
detail).
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Table 27-6. Relationship Between Enabling Security Function and Command
(1) During on-board/off-board programming
Valid Security
Executed Command
Batch Erase (Chip Erase)
Prohibition of batch erase (chip erase)
Prohibition of block erase
Block Erase
Write
Note
Cannot be erased in batch
Blocks cannot be
Can be performed
Can be erased in batch.
erased.
Can be performed.
Prohibition of writing
.
Cannot be performed.
Prohibition of rewriting boot cluster 0
Cannot be erased in batch
Boot cluster 0 cannot be
Boot cluster 0 cannot be
erased.
written.
Note Confirm that no data has been written to the write area. Because data cannot be erased after batch erase
(chip erase) is prohibited, do not write data if the data has not been erased.
(2) During self programming
Valid Security
Executed Command
Block Erase
Prohibition of batch erase (chip erase)
Write
Blocks can be erased.
Can be performed.
Boot cluster 0 cannot be erased.
Boot cluster 0 cannot be written.
Prohibition of block erase
Prohibition of writing
Prohibition of rewriting boot cluster 0
Remark To prohibit writing and erasing during self-programming, use the flash sealed window function (see 27.8.2 for
detail).
Table 27-7. Setting Security in Each Programming Mode
(1) On-board/off-board programming
Security
Security Setting
How to Disable Security Setting
Prohibition of batch erase (chip erase)
Set via GUI of dedicated flash memory
Cannot be disabled after set.
Prohibition of block erase
programmer, etc.
Execute batch erase (chip erase)
Prohibition of writing
command
Prohibition of rewriting boot cluster 0
Cannot be disabled after set.
(2) Self programming
Security
Prohibition of batch erase (chip erase)
Security Setting
Set by using information library.
How to Disable Security Setting
Cannot be disabled after set.
Prohibition of block erase
Execute batch erase (chip erase)
Prohibition of writing
command during on-board/off-board
Prohibition of rewriting boot cluster 0
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CHAPTER 27 FLASH MEMORY
27.8 Flash Memory Programming by Self-Programming
The 78K0R/Lx3 microcontrollers support a self-programming function that can be used to rewrite the flash memory via
a user program.
Because this function allows a user application to rewrite the flash memory by using the 78K0R/Lx3
microcontrollers self-programming library, it can be used to upgrade the program in the field.
If an interrupt occurs during self-programming, self-programming can be temporarily stopped and interrupt servicing
can be executed. If an unmasked interrupt request is generated in the EI state, the request branches directly from the
self-programming library to the interrupt routine. After the self-programming mode is later restored, self-programming can
be resumed. However, the interrupt response time is different from that of the normal operation mode.
Cautions 1. The self-programming function cannot be used when the CPU operates with the subsystem clock.
2. In the self-programming mode, call the self-programming start library (FlashStart).
3. To prohibit an interrupt during self-programming, in the same way as in the normal operation
mode, execute the self-programming library in the state where the IE flag is cleared (0) by the DI
instruction. To enable an interrupt, clear (0) the interrupt mask flag to accept in the state where
the IE flag is set (1) by the EI instruction, and then execute the self-programming library.
4. In low-power-consumption mode, use the regulator with fCLK fixed to 1 MHz when executing self
programming. For details of the low-power-consumption mode, see CHAPTER 25 REGULATOR.
5. Disable DMA operation (DENn = 0) during the execution of self programming library
functions.
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CHAPTER 27 FLASH MEMORY
The following figure illustrates a flow of rewriting the flash memory by using a self programming library.
Figure 27-10. Flow of Self Programming (Rewriting Flash Memory)
Start of self programming
FlashStart
Setting operating environment
FlashEnv
CheckFLMD
FlashBlockBlankCheck
Normal completion?
No
Yes
FlashBlockErase
FlashWordWrite
FlashBlockVerify
Normal completion?
No
Yes
FlashBlockErase
FlashWordWrite
FlashBlockVerify
Normal completion?
No
Yes
Normal completion
Error
FlashEnd
End of self programming
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CHAPTER 27 FLASH MEMORY
27.8.1 Boot swap function
If rewriting the boot area failed by temporary power failure or other reasons, restarting a program by resetting or
overwriting is disabled due to data destruction in the boot area.
The boot swap function is used to avoid this problem.
Before erasing boot cluster 0Note, which is a boot program area, by self-programming, write a new boot program to boot
cluster 1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot
cluster 0 by using the set information function of the firmware of the 78K0R/Lx3 microcontrollers, so that boot cluster 1 is
used as a boot area. After that, erase or write the original boot program area, boot cluster 0.
As a result, even if a power failure occurs while the boot programming area is being rewritten, the program is executed
correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next.
Note A boot cluster is a 4 KB area and boot clusters 0 and 1 are swapped by the boot swap function.
Figure 27-11. Boot Swap Function
XXXXXH
User program
Self-programming
to boot cluster 1
Execution of boot
swap by firmware
User program
User program
Self-programming
to boot cluster 0
User program
02000H
User program
New boot program
(boot cluster 1)
Boot program
(boot cluster 0)
Boot program
(boot cluster 0)
Boot program
(boot cluster 0)
New boot program
(boot cluster 1)
01000H
00000H
Boot
Boot
New user program
(boot cluster 0)
Boot
New boot program
(boot cluster 1)
Boot
In an example of above figure, it is as follows.
Boot cluster 0: Boot program area before boot swap
Boot cluster 1: Boot program area after boot swap
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CHAPTER 27 FLASH MEMORY
Figure 27-12. Example of Executing Boot Swapping
Block number
Erasing block 4
Boot
cluster 1
Boot
cluster 0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Program
Program
Program
Program
Boot program
Boot program
Boot program
Boot program
01000H
00000H
Program
Program
Program
Boot program
Boot program
Boot program
Boot program
Erasing block 5
7
6
5
4
3
2
1
0
Program
Program
Boot program
Boot program
Boot program
Boot program
Erasing block 6
Program
7
6
5
4
3 Boot program
2 Boot program
1 Boot program
0 Boot program
Erasing block 7
7
6
5
4
3 Boot program
2 Boot program
1 Boot program
0 Boot program
Booted by boot cluster 0
Writing blocks 4 to 7
7 New boot program
6 New boot program
5 New boot program
4 New boot program
3 Boot program
2 Boot program
1 Boot program
0 Boot program
Boot swap
7
6
5
4
3
2
1
0
Boot program
Boot program
Boot program
Boot program
01000H
New boot program
New boot program
New boot program
New boot program 0 0 0 0 0 H
Erasing block 4
Erasing block 5
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Boot program
Boot program
Boot program
New boot program
New boot program
New boot program
New boot program
Boot program
Boot program
New boot program
New boot program
New boot program
New boot program
Booted by boot cluster 1
Erasing block 6
7
6
5
4
3
2
1
0
Boot program
New boot program
New boot program
New boot program
New boot program
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Erasing block 7
7
6
5
4
3
2
1
0
New boot program
New boot program
New boot program
New boot program
Writing blocks 4 to 7
7
6
5
4
3
2
1
0
New program
New program
New program
New program
01000H
New boot program
New boot program
New boot program
New boot program 0 0 0 0 0 H
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CHAPTER 27 FLASH MEMORY
27.8.2 Flash shield window function
The flash shield window function is provided as one of the security functions for self programming. It disables writing to
and erasing areas outside the range specified as a window only during self programming.
The window range can be set by specifying the start and end blocks. The window range can be set or changed during
both on-board/off-board programming and self programming.
Writing to and erasing areas outside the window range are disabled during self programming. During on-board/offboard programming, however, areas outside the range specified as a window can be written and erased.
Figure27-13. Flash Shield Window Setting Example
(Target Devices: μPD78F1500A, Start Block: 04H, End Block: 06H)
0FFFFH
Methods by which writing can be performed
Block 3FH
Flash shield
range
√: On-board/off-board programming
×: Self programming
Block 3EH
01C00H
01BFFH
Block 06H
(end block)
Window range
√: On-board/off-board programming
√: Self programming
Block 05H
Flash memory
area
01000H
00FFFH
Block 04H
(start block)
Block 03H
Block 02H
Flash shield
range
√: On-board/off-board programming
×: Self programming
Block 01H
00000H
Block 00H
Caution If the rewrite-prohibited area of the boot cluster 0 overlaps with the flash shield window range,
prohibition to rewrite the boot cluster 0 takes priority.
Table 27-8. Relationship between Flash Shield Window Function Setting/Change Methods and Commands
Programming conditions
Window Range
Execution Commands
Setting/Change Methods
Block erase
Write
Specify the starting and
Block erasing is enabled
Writing is enabled only
ending blocks by the set
only within the window
within the range of
information library.
range.
window range.
On-board/Off-board
Specify the starting and
Block erasing is enabled
Writing is enabled also
programming
ending blocks on GUI of
also outside the window
outside the window
dedicated flash memory
range.
range.
Self-programming
programmer, etc.
Remark See 27.7 Security Settings to prohibit writing/erasing during on-board/off-board programming.
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CHAPTER 27 FLASH MEMORY
27.9 Creating ROM Code to Place Order for Previously Written Product
Before placing an order with Renesas Electronics for a previously written product, the ROM code for the order must be
created.
To create the ROM code, use the Hex Consolidation Utility (hereafter abbreviated to HCU) on the finished programs
(hex files) and optional data (such as security settings for flash memory programs).
The HCU is a software tool that includes functions required for creating ROM code.
The HCU can be downloaded at the Renesas Electronics website.
(1) Website
http://www2.renesas.com/micro/en/ods/ → Click Version-up Service.
(2) Downloading the HCU
To download the HCU, click Software for previously written flash products and then HCU_GUI.
Remark For details about how to install and use the HCU, see the materials (the user’s manual) that comes with the
HCU at the above website.
27.9.1
Procedure for using ROM code to place an order
Use the HCU to create the ROM code by following the procedure below, and then place your order with Renesas
Electronics. For details, see the ROM Code Ordering Method Information (C10302J).
Customer
Renesas Electronics
Decide which product to order.
Send the order information.
Create the ROM
Renesas Electronics processes
the product name and number
and creates a record of the
transaction.
codeNote
Check the ROM order details and
generate the required data.
Renesas Electronics sends the order number
and other order-related information.
Send the data required for the ROM order.
Renesas Electronics processes
the ROM code.
Note Use the HCU to create the ROM code for the order.
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CHAPTER 28 ON-CHIP DEBUG FUNCTION
CHAPTER 28 ON-CHIP DEBUG FUNCTION
28.1 Connecting QB-MINI2 to 78K0R/Lx3 microcontrollers
Note 1
The 78K0R/Lx3 microcontrollers use the VDD, FLMD0, RESET, TOOL0, TOOL1
, and VSS pins to communicate with
the host machine via an on-chip debug emulator (QB-MINI2).
Caution
The 78K0R/Lx3 microcontrollers have an on-chip debug function, which is provided for development
and evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
Figure 28-1. Connection Example of QB-MINI2 and 78K0R/Lx3 microcontrollers
78K0R/Lx3
microcontrollers
QB-MINI2 target connector
FLMD0
FLMD0
RESET_IN
Target reset
RESET
RESET_OUT
EVDD
RXDNote 2
TOOL0
TXD
Note 2
CLK_IN
TOOL1Note 1
GND
VSS
VDD
VDD
Notes 1. Connection is not required for communication in 1-line mode but required for communication in 2-line mode.
At this time, perform necessary connections according to Table 2-2 Connection of Unused Pins since
TOOL1 is an unused pin when QB-MINI2 is unconnected.
2. Connecting the dotted line is not necessary since RXD and TXD are shorted within QB-MIN2. When using
the other flash memory programmer, RXD and TXD may not be shorted within the programmer. In this case,
they must be shorted on the target system.
Remark
The FLMD0 pin is recommended to be open for self-programming in on-chip debugging. To pull down
externally, use a resistor of 100 kΩ or more.
1-line mode (single line UART) using the TOOL0 pin or 2-line mode using the TOOL0 and TOOL1 pins is used for serial
communication For flash memory programming, 1-line mode is used. 1-line mode or 2-line mode is used for on-chip
debugging. Table 28-1 lists the differences between 1-line mode and 2-line mode.
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CHAPTER 28 ON-CHIP DEBUG FUNCTION
Table 28-1. Lists the Differences Between 1-line Mode and 2-line Mode.
Communicat
ion mode
1-line mode
Flash memory
programming
function
Available
Debugging function
• Pseudo real-time RAM monitor (RRM) function not supported.
• DMM function (rewriting memory in RUN) not supported.
• The debugger speed is two to four times slower than 2-line mode.
2-line mode
None
• Pseudo real-time RAM monitor (RRM) function supported
• DMM function (rewriting memory in RUN) supported
Remark 2-line mode is not used for flash programming, however, even if TOOL1 pin is connected with CLK_IN of QBMINI2, writing is performed normally with no problem.
28.2 On-Chip Debug Security ID
The 78K0R/Lx3 microcontrollers have an on-chip debug operation control bit in the flash memory at 000C3H (see
CHAPTER 26 OPTION BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third
parties from reading memory content.
When the boot swap function is used, also set a value that is the same as that of 010C3H and 010C4H to 010CDH in
advance, because 000C3H, 000C4H to 000CDH and 010C3H, and 010C4H to 010CDH are switched.
For details on the on-chip debug security ID, refer to the QB-MINI2 On-Chip Debug Emulator with Programming
Function User’s Manual (U18371E).
Table 28-2. On-Chip Debug Security ID
Address
000C4H to 000CDH
On-Chip Debug Security ID
Any ID code of 10 bytes
010C4H to 010CDH
28.3 Securing of User Resources
To perform communication between the 78K0R/Lx3 microcontrollers and QB-MINI2, as well as each debug function,
the securing of memory space must be done beforehand.
If Renesas Electronics assembler RA78K0R or compiler CC78K0R is used, the items can be set by using linker options.
(1) Securement of memory space
The shaded portions in Figure 28-2 are the areas reserved for placing the debug monitor program, so user
programs or data cannot be allocated in these spaces. When using the on-chip debug function, these spaces must
be secured so as not to be used by the user program. Moreover, this area must not be rewritten by the user
program.
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CHAPTER 28 ON-CHIP DEBUG FUNCTION
Figure 28-2. Memory Spaces Where Debug Monitor Programs Are Allocated
Internal ROM
Note 1
Internal RAM
(1 KB)
Stack area for debugging Internal RAM
(6 bytes) Note 3
area
02000H
Use prohibited
010D8H
010CEH
Debug monitor area
(10 bytes)
010C4H
Security ID area
(10 bytes)
Boot cruster 1
Internal ROM
area
On-chip debug option byte area
(1 byte)
010C3H
01002H
01000H
Debug monitor area
(2 bytes)
Note 2
: Area used for on-chip debugging
000D8H
000CEH
Debug monitor area
(10 bytes)
000C4H
Security ID area
(10 bytes)
Boot cruster 0
On-chip debug option byte area
(1 byte)
000C3H
00002H
00000H
Debug monitor area
(2 bytes)
Note 2
Notes 1. Address differs depending on products as follows.
Products
Internal ROM
Address
μ PD78F1500A, 78F1503A, 78F1506A, 78F1510A, 78F1513A, 78F1516A
64 KB
0FC00H to 0FFFFH
μ PD78F1501A, 78F1504A, 78F1507A
96 KB
17C00H to 17FFFH
μ PD78F1502A, 78F1505A, 78F1508A, 78F1512A, 78F1515A, 78F1518A
128 KB
1FC00H to 1FFFFH
2. In debugging, reset vector is rewritten to address allocated to a monitor program.
3. Since this area is allocated immediately before the stack area, the address of this area varies depending on
the stack increase and decrease. That is, 6 extra bytes are consumed for the stack area used.
For details of the way to secure of the memory space, refer to the QB-MINI2 On-Chip Debug Emulator with
Programming Function User’s Manual (U18371E).
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CHAPTER 29 BCD CORRECTION CIRCUIT
CHAPTER 29 BCD CORRECTION CIRCUIT
29.1 BCD Correction Circuit Function
The BCD correction circuit is mounted onto all 78K0R/Lx3 microcontroller products.
The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD
code with this circuit.
The decimal correction operation result is obtained by performing addition/subtraction having the A register as the
operand and then adding/ subtracting the BCDADJ register.
29.2 Registers Used by BCD Correction Circuit
The BCD correction circuit uses the following registers.
• BCD correction result register (BCDADJ)
(1) BCD correction result register (BCDADJ)
The BCDADJ register stores correction values for obtaining the add/subtract result as BCD code through
add/subtract instructions using the A register as the operand.
The value read from the BCDADJ register varies depending on the value of the A register when it is read and those
of the CY and AC flags.
BCDADJ is read by an 8-bit memory manipulation instruction.
Reset input sets this register to undefined.
Figure 29-1. Format of BCD Correction Result Register (BCDADJ)
Address: F00FEH
Symbol
After reset: undefined
7
6
R
5
4
3
2
1
0
BCDADJ
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CHAPTER 29 BCD CORRECTION CIRCUIT
29.3 BCD Correction Circuit Operation
The basic operation of the BCD correction circuit is as follows.
(1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a
BCD code value
The BCD code value to which addition is performed is stored in the A register.
By adding the value of the A register and the second operand (value of one more BCD code to be added) as
are in binary, the binary operation result is stored in the A register and the correction value is stored in the
BCDADJ register.
Decimal correction is performed by adding in binary the value of the A register (addition result in binary) and
the BCDADJ register (correction value), and the correction result is stored in the A register and CY register.
Caution
The value read from the BCDADJ register varies depending on the value of the A register
when it is read and those of the CY and AC flags. Therefore, execute the instruction
after the instruction instead of executing any other instructions. To perform BCD
correction in the interrupt enabled state, saving and restoring the A register is required
within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction.
An example is shown below.
Examples 1: 99 + 89 = 188
Instruction
A Register
CY Register
AC Flag
BCDADJ
Register
MOV A, #99H
;
99H
−
−
−
ADD A, #89H
;
22H
1
1
66H
ADD A, !BCDADJ
;
88H
1
0
−
A Register
CY Register
AC Flag
BCDADJ
Register
;
85H
−
−
−
ADD A, #15H
;
9AH
0
0
66H
ADD A, !BCDADJ
;
00H
1
1
−
A Register
CY Register
AC Flag
BCDADJ
Register
Examples 2: 85 + 15 = 100
Instruction
MOV A, #85H
Examples 3: 80 + 80 = 160
Instruction
MOV A, #80H
;
80H
−
−
−
ADD A, #80H
;
00H
1
0
60H
ADD A, !BCDADJ
;
60H
1
0
−
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CHAPTER 29 BCD CORRECTION CIRCUIT
(2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by
using a BCD code value
The BCD code value from which subtraction is performed is stored in the A register.
By subtracting the value of the second operand (value of BCD code to be subtracted) from the A register as is
in binary, the calculation result in binary is stored in the A register, and the correction value is stored in the
BCDADJ register.
Decimal correction is performed by subtracting the value of the BCDADJ register (correction value) from the A
register (subtraction result in binary) in binary, and the correction result is stored in the A register and CY
register.
Caution
The value read from the BCDADJ register varies depending on the value of the A register
when it is read and those of the CY and AC flags. Therefore, execute the instruction
after the instruction instead of executing any other instructions. To perform BCD
correction in the interrupt enabled state, saving and restoring the A register is required
within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction.
An example is shown below.
Example: 91 − 52 = 39
Instruction
A Register
CY Register
AC Flag
BCDADJ
Register
;
91H
−
−
−
SUB A, #52H
;
3FH
0
1
06H
SUB A, !BCDADJ
;
39H
0
0
−
MOV A, #91H
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CHAPTER 30 INSTRUCTION SET
CHAPTER 30 INSTRUCTION SET
This chapter lists the instructions in the 78K0R microcontroller instruction set. For details of each operation and
operation code, refer to the separate document 78K0R Microcontrollers Instructions User’s Manual (U17792E).
Remark
The shaded parts of the tables in Table 30-5 Operation List indicate the operation or instruction format that
is newly added for the 78K0R microcontrollers.
30.1 Conventions Used in Operation List
30.1.1 Operand identifiers and specification methods
Operands are described in the “Operand” column of each instruction in accordance with the description method of the
instruction operand identifier (refer to the assembler specifications for details). When there are two or more description
methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, !!, $, $!, [ ], and ES: are keywords and
are described as they are. Each symbol has the following meaning.
• #:
Immediate data specification
• !:
16-bit absolute address specification
• !!:
20-bit absolute address specification
• $:
8-bit relative address specification
• $!:
16-bit relative address specification
• [ ]:
Indirect address specification
• ES: Extension address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, !!, $, $!, [ ], and ES: symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 30-1. Operand Identifiers and Specification Methods
Identifier
Description Method
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
rp
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
sfr
Special-function register symbol (SFR symbol)
sfrp
Special-function register symbols (16-bit manipulatable SFR symbol. Even addresses only
saddr
FFE20H to FFF1FH Immediate data or labels
saddrp
FFE20H to FF1FH Immediate data or labels (even addresses only
addr20
00000H to FFFFFH Immediate data or labels
addr16
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions
addr5
0080H to 00BFH Immediate data or labels (even addresses only)
word
16-bit immediate data or label
byte
8-bit immediate data or label
bit
3-bit immediate data or label
RBn
RB0 to RB3
Note
Note
)
Note
)
Note
)
Bit 0 = 0 when an odd address is specified.
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CHAPTER 30 INSTRUCTION SET
30.1.2 Description of operation column
The operation when the instruction is executed is shown in the “Operation” column using the following symbols.
Table 30-2. Symbols in “Operation” Column
Symbol
Function
A
A register; 8-bit accumulator
X
X register
B
B register
C
C register
D
D register
E
E register
H
H register
L
L register
ES
ES register
CS
CS register
AX
AX register pair; 16-bit accumulator
BC
BC register pair
DE
DE register pair
HL
HL register pair
PC
Program counter
SP
Stack pointer
PSW
Program status word
CY
Carry flag
AC
Auxiliary carry flag
Z
Zero flag
RBS
Register bank select flag
IE
Interrupt request enable flag
()
Memory contents indicated by address or register contents in parentheses
X H, X L
16-bit registers: XH = higher 8 bits, XL = lower 8 bits
XS, XH, XL
20-bit registers: XS = (bits 19 to 16), XH = (bits 15 to 8), XL = (bits 7 to 0)
∧
Logical product (AND)
∨
Logical sum (OR)
∨
Exclusive logical sum (exclusive OR)
−
Inverted data
addr5
16-bit immediate data (even addresses only in 0080H to 00BFH)
addr16
16-bit immediate data
addr20
20-bit immediate data
jdisp8
Signed 8-bit data (displacement value)
jdisp16
Signed 16-bit data (displacement value)
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30.1.3 Description of flag operation column
The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols.
Table 30-3. Symbols in “Flag” Column
Symbol
Change of Flag Value
(Blank)
Unchanged
0
Cleared to 0
1
Set to 1
×
R
Set/cleared according to the result
Previously saved value is restored
30.1.4 PREFIX instruction
Instructions with “ES:” have a PREFIX operation code as a prefix to extend the accessible data area to the 1 MB space
(00000H to FFFFFH), by adding the ES register value to the 64 KB space from F0000H to FFFFFH. When a PREFIX
operation code is attached as a prefix to the target instruction, only one instruction immediately after the PREFIX operation
code is executed as the addresses with the ES register value added.
Table 30-4. Use Example of PREFIX Operation Code
Instruction
Opcode
1
2
3
!addr16
4
5
#byte
−
MOV !addr16, #byte
CFH
MOV ES:!addr16, #byte
11H
CFH
MOV A, [HL]
8BH
−
−
−
−
MOV A, ES:[HL]
11H
8BH
−
−
−
!addr16
#byte
Caution Set the ES register value with MOV ES, A, etc., before executing the PREFIX instruction.
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30.2 Operation List
Table 30-5. Operation List (1/17)
Instruction Mnemonic
Operands
Bytes
Group
Operation
Clocks
Note 1 Note 2
Z
8-bit data MOV
r, #byte
2
1
−
r ← byte
transfer
saddr, #byte
3
1
−
(saddr) ← byte
sfr, #byte
3
1
−
sfr ← byte
4
1
−
(addr16) ← byte
A, r
Note 3
1
1
−
A←r
r, A
Note 3
!addr16, #byte
Notes 1.
Flag
1
1
−
r←A
A, saddr
2
1
−
A ← (saddr)
saddr, A
2
1
−
(saddr) ← A
A, sfr
2
1
−
A ← sfr
sfr, A
2
1
−
sfr ← A
A, !addr16
3
1
4
A ← (addr16)
!addr16, A
3
1
−
(addr16) ← A
PSW, #byte
3
3
−
PSW ← byte
A, PSW
2
1
−
A ← PSW
PSW, A
2
3
−
PSW ← A
ES, #byte
2
1
−
ES ← byte
ES, saddr
3
1
−
ES ← (saddr)
A, ES
2
1
−
A ← ES
ES, A
2
1
−
ES ← A
CS, #byte
3
1
−
CS ← byte
A, CS
2
1
−
A ← CS
CS, A
2
1
−
CS ← A
A, [DE]
1
1
4
A ← (DE)
[DE], A
1
1
−
(DE) ← A
[DE + byte], #byte
3
1
−
(DE + byte) ← byte
A, [DE + byte]
2
1
4
A ← (DE + byte)
[DE + byte], A
2
1
−
(DE + byte) ← A
A, [HL]
1
1
4
A ← (HL)
[HL], A
1
1
−
(HL) ← A
[HL + byte], #byte
3
1
−
(HL + byte) ← byte
AC CY
×
×
×
×
×
×
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
2.
When the program memory area is accessed.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
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Table 30-5. Operation List (2/17)
Instruction Mnemonic
Operands
Bytes
Group
Operation
Clocks
Note 1 Note 2
Z
8-bit data MOV
A, [HL + byte]
2
1
4
A ← (HL + byte)
transfer
[HL + byte], A
2
1
−
(HL + byte) ← A
A, [HL + B]
2
1
4
A ← (HL + B)
[HL + B], A
2
1
−
(HL + B) ← A
A, [HL + C]
2
1
4
A ← (HL + C)
Notes 1.
2.
Flag
[HL + C], A
2
1
−
(HL + C) ← A
word[B], #byte
4
1
−
(B + word) ← byte
A, word[B]
3
1
4
A ← (B + word)
word[B], A
3
1
−
(B + word) ← A
word[C], #byte
4
1
−
(C + word) ← byte
A, word[C]
3
1
4
A ← (C + word)
word[C], A
3
1
−
(C + word) ← A
word[BC], #byte
4
1
−
(BC + word) ← byte
A, word[BC]
3
1
4
A ← (BC + word)
word[BC], A
3
1
−
(BC + word) ← A
[SP + byte], #byte
3
1
−
(SP + byte) ← byte
A, [SP + byte]
2
1
−
A ← (SP + byte)
[SP + byte], A
2
1
−
(SP + byte) ← A
B, saddr
2
1
−
B ← (saddr)
B, !addr16
3
1
4
B ← (addr16)
C, saddr
2
1
−
C ← (saddr)
C, !addr16
3
1
4
C ← (addr16)
X, saddr
2
1
−
X ← (saddr)
X, !addr16
3
1
4
X ← (addr16)
ES:!addr16, #byte
5
2
−
(ES, addr16) ← byte
A, ES:!addr16
4
2
5
A ← (ES, addr16)
ES:!addr16, A
4
2
−
(ES, addr16) ← A
A, ES:[DE]
2
2
5
A ← (ES, DE)
ES:[DE], A
2
2
−
(ES, DE) ← A
ES:[DE + byte],#byte
4
2
−
((ES, DE) + byte) ← byte
A, ES:[DE + byte]
3
2
5
A ← ((ES, DE) + byte)
ES:[DE + byte], A
3
2
−
((ES, DE) + byte) ← A
AC CY
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
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Table 30-5. Operation List (3/17)
Instruction Mnemonic
Operands
Bytes
Group
Operation
Clocks
Note 1 Note 2
Z
8-bit data MOV
A, ES:[HL]
2
2
5
A ← (ES, HL)
transfer
ES:[HL], A
2
2
−
(ES, HL) ← A
ES:[HL + byte],#byte
4
2
−
((ES, HL) + byte) ← byte
A, ES:[HL + byte]
3
2
5
A ← ((ES, HL) + byte)
ES:[HL + byte], A
3
2
−
((ES, HL) + byte) ← A
A, ES:[HL + B]
3
2
5
A ← ((ES, HL) + B)
ES:[HL + B], A
3
2
−
((ES, HL) + B) ← A
A, ES:[HL + C]
3
2
5
A ← ((ES, HL) + C)
ES:[HL + C], A
3
2
−
((ES, HL) + C) ← A
ES:word[B], #byte
5
2
−
((ES, B) + word) ← byte
A, ES:word[B]
4
2
5
A ← ((ES, B) + word)
ES:word[B], A
4
2
−
((ES, B) + word) ← A
ES:word[C], #byte
5
2
−
((ES, C) + word) ← byte
A, ES:word[C]
4
2
5
A ← ((ES, C) + word)
ES:word[C], A
4
2
−
((ES, C) + word) ← A
ES:word[BC], #byte
5
2
−
((ES, BC) + word) ← byte
A, ES:word[BC]
4
2
5
A ← ((ES, BC) + word)
ES:word[BC], A
4
2
−
((ES, BC) + word) ← A
B, ES:!addr16
4
2
5
B ← (ES, addr16)
C, ES:!addr16
4
2
5
C ← (ES, addr16)
4
2
5
X ← (ES, addr16)
1 (r = X)
2 (other
than r = X)
1
−
A ←→ r
A, saddr
3
2
−
A ←→ (saddr)
A, sfr
3
2
−
A ←→ sfr
A, !addr16
4
2
−
A ←→ (addr16)
A, [DE]
2
2
−
A ←→ (DE)
A, [DE + byte]
3
2
−
A ←→ (DE + byte)
A, [HL]
2
2
−
A ←→ (HL)
A, [HL + byte]
3
2
−
A ←→ (HL + byte)
A, [HL + B]
2
2
−
A ←→ (HL + B)
A, [HL + C]
2
2
−
A ←→ (HL + C)
X, ES:!addr16
XCH
Notes 1.
A, r
Note 3
Flag
AC CY
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
2.
When the program memory area is accessed.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
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Table 30-5. Operation List (4/17)
Instruction Mnemonic
Operands
Bytes
Group
Operation
Clocks
Note 1 Note 2
Flag
Z
AC CY
8-bit data XCH
A, ES:!addr16
5
3
−
A ←→ (ES, addr16)
transfer
A, ES:[DE]
3
3
−
A ←→ (ES, DE)
A, ES:[DE + byte]
4
3
−
A ←→ ((ES, DE) + byte)
A, ES:[HL]
3
3
−
A ←→ (ES, HL)
A, ES:[HL + byte]
4
3
−
A ←→ ((ES, HL) + byte)
A, ES:[HL + B]
3
3
−
A ←→ ((ES, HL) + B)
A, ES:[HL + C]
3
3
−
A ←→ ((ES, HL) + C)
A
1
1
−
A ← 01H
X
1
1
−
X ← 01H
B
1
1
−
B ← 01H
C
1
1
−
C ← 01H
saddr
2
1
−
(saddr) ← 01H
!addr16
3
1
−
(addr16) ← 01H
ES:!addr16
4
2
−
(ES, addr16) ← 01H
A
1
1
−
A ← 00H
X
1
1
−
X ← 00H
B
1
1
−
B ← 00H
C
1
1
−
C ← 00H
saddr
2
1
−
(saddr) ← 00H
!addr16
3
1
−
(addr16) ← 00H
ES:!addr16
4
2
−
(ES,addr16) ← 00H
[HL + byte], X
3
1
−
(HL + byte) ← X
×
×
ES:[HL + byte], X
4
2
−
(ES, HL + byte) ← X
×
×
rp, #word
3
1
−
rp ← word
saddrp, #word
4
1
−
(saddrp) ← word
sfrp, #word
4
1
−
sfrp ← word
AX, saddrp
2
1
−
AX ← (saddrp)
saddrp, AX
2
1
−
(saddrp) ← AX
AX, sfrp
2
1
−
AX ← sfrp
ONEB
CLRB
MOVS
16-bit
MOVW
data
transfer
2
1
−
sfrp ← AX
AX, rp
Note 3
1
1
−
AX ← rp
rp, AX
Note 3
1
1
−
rp ← AX
sfrp, AX
Notes 1.
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
2.
When the program memory area is accessed.
3.
Except rp = AX
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
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Table 30-5. Operation List (5/17)
Instruction Mnemonic
Operands
Bytes
Group
16-bit
Note 1 Note 2
MOVW
data
transfer
Notes 1.
2.
Operation
Clocks
Flag
Z
AX, !addr16
3
1
4
AX ← (addr16)
!addr16, AX
3
1
−
(addr16) ← AX
AX, [DE]
1
1
4
AX ← (DE)
[DE], AX
1
1
−
(DE) ← AX
AX, [DE + byte]
2
1
4
AX ← (DE + byte)
[DE + byte], AX
2
1
−
(DE + byte) ← AX
AX, [HL]
1
1
4
AX ← (HL)
[HL], AX
1
1
−
(HL) ← AX
AX, [HL + byte]
2
1
4
AX ← (HL + byte)
[HL + byte], AX
2
1
−
(HL + byte) ← AX
AX, word[B]
3
1
4
AX ← (B + word)
word[B], AX
3
1
−
(B + word) ← AX
AX, word[C]
3
1
4
AX ← (C + word)
word[C], AX
3
1
−
(C + word) ← AX
AX, word[BC]
3
1
4
AX ← (BC + word)
word[BC], AX
3
1
−
(BC + word) ← AX
AX, [SP + byte]
2
1
−
AX ← (SP + byte)
[SP + byte], AX
2
1
−
(SP + byte) ← AX
BC, saddrp
2
1
−
BC ← (saddrp)
BC, !addr16
3
1
4
BC ← (addr16)
DE, saddrp
2
1
−
DE ← (saddrp)
DE, !addr16
3
1
4
DE ← (addr16)
HL, saddrp
2
1
−
HL ← (saddrp)
HL, !addr16
3
1
4
HL ← (addr16)
AX, ES:!addr16
4
2
5
AX ← (ES, addr16)
ES:!addr16, AX
4
2
−
(ES, addr16) ← AX
AX, ES:[DE]
2
2
5
AX ← (ES, DE)
ES:[DE], AX
2
2
−
(ES, DE) ← AX
AX, ES:[DE + byte]
3
2
5
AX ← ((ES, DE) + byte)
ES:[DE + byte], AX
3
2
−
((ES, DE) + byte) ← AX
AX, ES:[HL]
2
2
5
AX ← (ES, HL)
ES:[HL], AX
2
2
−
(ES, HL) ← AX
AC CY
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
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Table 30-5. Operation List (6/17)
Instruction Mnemonic
Operands
Bytes
Group
16-bit
Note 1 Note 2
MOVW
data
transfer
3
2
5
AX ← ((ES, HL) + byte)
ES:[HL + byte], AX
3
2
−
((ES, HL) + byte) ← AX
AX, ES:word[B]
4
2
5
AX ← ((ES, B) + word)
ES:word[B], AX
4
2
−
((ES, B) + word) ← AX
AX, ES:word[C]
4
2
5
AX ← ((ES, C) + word)
ES:word[C], AX
4
2
−
((ES, C) + word) ← AX
AX, ES:word[BC]
4
2
5
AX ← ((ES, BC) + word)
ES:word[BC], AX
4
2
−
((ES, BC) + word) ← AX
BC, ES:!addr16
4
2
5
BC ← (ES, addr16)
DE, ES:!addr16
4
2
5
DE ← (ES, addr16)
4
2
5
HL ← (ES, addr16)
1
1
−
AX ←→ rp
AX, rp
ONEW
AX
1
1
−
AX ← 0001H
BC
1
1
−
BC ← 0001H
AX
1
1
−
AX ← 0000H
BC
1
1
−
BC ← 0000H
A, #byte
2
1
−
A, CY ← A + byte
×
×
×
3
2
−
(saddr), CY ← (saddr) + byte
×
×
×
2
1
−
A, CY ← A + r
×
×
×
r, A
2
1
−
r, CY ← r + A
×
×
×
A, saddr
2
1
−
A, CY ← A + (saddr)
×
×
×
ADD
saddr, #byte
A, r
Notes 1.
2.
AC CY
XCHW
CLRW
operation
Note 3
Flag
Z
AX, ES:[HL + byte]
HL, ES:!addr16
8-bit
Operation
Clocks
Note 4
A, !addr16
3
1
4
A, CY ← A + (addr16)
×
×
×
A, [HL]
1
1
4
A, CY ← A + (HL)
×
×
×
A, [HL + byte]
2
1
4
A, CY ← A + (HL + byte)
×
×
×
A, [HL + B]
2
1
4
A, CY ← A + (HL + B)
×
×
×
A, [HL + C]
2
1
4
A, CY ← A + (HL + C)
×
×
×
A, ES:!addr16
4
2
5
A, CY ← A + (ES, addr16)
×
×
×
A, ES:[HL]
2
2
5
A,CY ← A + (ES, HL)
×
×
×
A, ES:[HL + byte]
3
2
5
A,CY ← A + ((ES, HL) + byte)
×
×
×
A, ES:[HL + B]
3
2
5
A,CY ← A + ((ES, HL) + B)
×
×
×
A, ES:[HL + C]
3
2
5
A,CY ← A + ((ES, HL) + C)
×
×
×
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
3.
Except rp = AX
4.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
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Table 30-5. Operation List (7/17)
Instruction Mnemonic
Operands
Bytes
Group
8-bit
Note 1 Note 2
ADDC
operation
Z
AC CY
1
−
A, CY ← A + byte + CY
×
×
×
3
2
−
(saddr), CY ← (saddr) + byte + CY
×
×
×
2
1
−
A, CY ← A + r + CY
×
×
×
r, A
2
1
−
r, CY ← r + A + CY
×
×
×
A, saddr
2
1
−
A, CY ← A + (saddr) + CY
×
×
×
saddr, #byte
SUB
Flag
2
A, #byte
A, r
Note 3
A, !addr16
3
1
4
A, CY ← A + (addr16) + CY
×
×
×
A, [HL]
1
1
4
A, CY ← A + (HL) + CY
×
×
×
A, [HL + byte]
2
1
4
A, CY ← A + (HL + byte) + CY
×
×
×
A, [HL + B]
2
1
4
A, CY ← A + (HL + B) + CY
×
×
×
A, [HL + C]
2
1
4
A, CY ← A + (HL + C) + CY
×
×
×
A, ES:!addr16
4
2
5
A, CY ← A + (ES, addr16) + CY
×
×
×
A, ES:[HL]
2
2
5
A, CY ← A + (ES, HL) + CY
×
×
×
A, ES:[HL + byte]
3
2
5
A, CY ← A + ((ES, HL) + byte) + CY
×
×
×
A, ES:[HL + B]
3
2
5
A, CY ← A + ((ES, HL) + B) + CY
×
×
×
A, ES:[HL + C]
3
2
5
A, CY ← A + ((ES, HL) + C) + CY
×
×
×
A, #byte
2
1
−
A, CY ← A − byte
×
×
×
3
2
−
(saddr), CY ← (saddr) − byte
×
×
×
2
1
−
A, CY ← A − r
×
×
×
r, A
2
1
−
r, CY ← r − A
×
×
×
A, saddr
2
1
−
A, CY ← A − (saddr)
×
×
×
A, !addr16
3
1
4
A, CY ← A − (addr16)
×
×
×
A, [HL]
1
1
4
A, CY ← A − (HL)
×
×
×
A, [HL + byte]
2
1
4
A, CY ← A − (HL + byte)
×
×
×
A, [HL + B]
2
1
4
A, CY ← A − (HL + B)
×
×
×
A, [HL + C]
2
1
4
A, CY ← A − (HL + C)
×
×
×
A, ES:!addr16
4
2
5
A, CY ← A − (ES:addr16)
×
×
×
A, ES:[HL]
2
2
5
A, CY ← A − (ES:HL)
×
×
×
A, ES:[HL + byte]
3
2
5
A, CY ← A − ((ES:HL) + byte)
×
×
×
A, ES:[HL + B]
3
2
5
A, CY ← A − ((ES:HL) + B)
×
×
×
A, ES:[HL + C]
3
2
5
A, CY ← A − ((ES:HL) + C)
×
×
×
saddr, #byte
A, r
Notes 1.
Operation
Clocks
Note 3
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
2.
When the program memory area is accessed.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
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CHAPTER 30 INSTRUCTION SET
Table 30-5. Operation List (8/17)
Instruction Mnemonic
Operands
Bytes
Group
8-bit
Note 1 Note 2
SUBC
operation
Z
AC CY
1
−
A, CY ← A − byte − CY
×
×
×
3
2
−
(saddr), CY ← (saddr) − byte − CY
×
×
×
2
1
−
A, CY ← A − r − CY
×
×
×
r, A
2
1
−
r, CY ← r − A − CY
×
×
×
A, saddr
2
1
−
A, CY ← A − (saddr) − CY
×
×
×
saddr, #byte
AND
Flag
2
A, #byte
A, r
Note 3
A, !addr16
3
1
4
A, CY ← A − (addr16) − CY
×
×
×
A, [HL]
1
1
4
A, CY ← A − (HL) − CY
×
×
×
A, [HL + byte]
2
1
4
A, CY ← A − (HL + byte) − CY
×
×
×
A, [HL + B]
2
1
4
A, CY ← A − (HL + B) − CY
×
×
×
A, [HL + C]
2
1
4
A, CY ← A − (HL + C) − CY
×
×
×
A, ES:!addr16
4
2
5
A, CY ← A − (ES:addr16) − CY
×
×
×
A, ES:[HL]
2
2
5
A, CY ← A − (ES:HL) − CY
×
×
×
A, ES:[HL + byte]
3
2
5
A, CY ← A − ((ES:HL) + byte) − CY
×
×
×
A, ES:[HL + B]
3
2
5
A, CY ← A − ((ES:HL) + B) − CY
×
×
×
A, ES:[HL + C]
3
2
5
A, CY ← A − ((ES:HL) + C) − CY
×
×
×
A, #byte
2
1
−
A ← A ∧ byte
×
3
2
−
(saddr) ← (saddr) ∧ byte
×
2
1
−
A←A∧r
×
r, A
2
1
−
r←r∧A
×
A, saddr
2
1
−
A ← A ∧ (saddr)
×
A, !addr16
3
1
4
A ← A ∧ (addr16)
×
A, [HL]
1
1
4
A ← A ∧ (HL)
×
A, [HL + byte]
2
1
4
A ← A ∧ (HL + byte)
×
A, [HL + B]
2
1
4
A ← A ∧ (HL + B)
×
A, [HL + C]
2
1
4
A ← A ∧ (HL + C)
×
A, ES:!addr16
4
2
5
A ← A ∧ (ES:addr16)
×
A, ES:[HL]
2
2
5
A ← A ∧ (ES:HL)
×
A, ES:[HL + byte]
3
2
5
A ← A ∧ ((ES:HL) + byte)
×
A, ES:[HL + B]
3
2
5
A ← A ∧ ((ES:HL) + B)
×
A, ES:[HL + C]
3
2
5
A ← A ∧ ((ES:HL) + C)
×
saddr, #byte
A, r
Notes 1.
Operation
Clocks
Note 3
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
2.
When the program memory area is accessed.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
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Table 30-5. Operation List (9/17)
Instruction Mnemonic
Operands
Bytes
Group
8-bit
Note 1 Note 2
OR
operation
Z
1
−
A ← A ∨ byte
×
3
2
−
(saddr) ← (saddr) ∨ byte
×
2
1
−
A←A∨r
×
r, A
2
1
−
r←r∨A
×
A, saddr
2
1
−
A ← A ∨ (saddr)
×
saddr, #byte
XOR
Flag
2
A, #byte
A, r
Note 3
A, !addr16
3
1
4
A ← A ∨ (addr16)
×
A, [HL]
1
1
4
A ← A ∨ (HL)
×
A, [HL + byte]
2
1
4
A ← A ∨ (HL + byte)
×
A, [HL + B]
2
1
4
A ← A ∨ (HL + B)
×
A, [HL + C]
2
1
4
A ← A ∨ (HL + C)
×
A, ES:!addr16
4
2
5
A ← A ∨ (ES:addr16)
×
A, ES:[HL]
2
2
5
A ← A ∨ (ES:HL)
×
A, ES:[HL + byte]
3
2
5
A ← A ∨ ((ES:HL) + byte)
×
A, ES:[HL + B]
3
2
5
A ← A ∨ ((ES:HL) + B)
×
A, ES:[HL + C]
3
2
5
A ← A ∨ ((ES:HL) + C)
×
A, #byte
2
1
−
A ← A ∨ byte
×
3
2
−
(saddr) ← (saddr) ∨ byte
×
2
1
−
A←A∨r
×
r, A
2
1
−
r←r∨A
×
A, saddr
2
1
−
A ← A ∨ (saddr)
×
A, !addr16
3
1
4
A ← A ∨ (addr16)
×
A, [HL]
1
1
4
A ← A ∨ (HL)
×
A, [HL + byte]
2
1
4
A ← A ∨ (HL + byte)
×
A, [HL + B]
2
1
4
A ← A ∨ (HL + B)
×
A, [HL + C]
2
1
4
A ← A ∨ (HL + C)
×
A, ES:!addr16
4
2
5
A ← A ∨ (ES:addr16)
×
A, ES:[HL]
2
2
5
A ← A ∨ (ES:HL)
×
A, ES:[HL + byte]
3
2
5
A ← A ∨ ((ES:HL) + byte)
×
A, ES:[HL + B]
3
2
5
A ← A ∨ ((ES:HL) + B)
×
A, ES:[HL + C]
3
2
5
A ← A ∨ ((ES:HL) + C)
×
saddr, #byte
A, r
Notes 1.
Operation
Clocks
Note 3
AC CY
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
2.
When the program memory area is accessed.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
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CHAPTER 30 INSTRUCTION SET
Table 30-5. Operation List (10/17)
Instruction Mnemonic
Operands
Bytes
Group
8-bit
Note 1 Note 2
CMP
operation
CMPS
Z
AC CY
1
−
A − byte
×
×
×
3
1
−
(saddr) − byte
×
×
×
2
1
−
A−r
×
×
×
r, A
2
1
−
r−A
×
×
×
A, saddr
2
1
−
A − (saddr)
×
×
×
saddr, #byte
CMP0
Flag
2
A, #byte
A, r
Notes 1.
Operation
Clocks
Note 3
A, !addr16
3
1
4
A − (addr16)
×
×
×
A, [HL]
1
1
4
A − (HL)
×
×
×
A, [HL + byte]
2
1
4
A − (HL + byte)
×
×
×
A, [HL + B]
2
1
4
A − (HL + B)
×
×
×
A, [HL + C]
2
1
4
A − (HL + C)
×
×
×
!addr16, #byte
4
1
4
(addr16) − byte
×
×
×
A, ES:!addr16
4
2
5
A − (ES:addr16)
×
×
×
A, ES:[HL]
2
2
5
A − (ES:HL)
×
×
×
A, ES:[HL + byte]
3
2
5
A − ((ES:HL) + byte)
×
×
×
A, ES:[HL + B]
3
2
5
A − ((ES:HL) + B)
×
×
×
A, ES:[HL + C]
3
2
5
A − ((ES:HL) + C)
×
×
×
ES:!addr16, #byte
5
2
5
(ES:addr16) − byte
×
×
×
A
1
1
−
A − 00H
×
×
×
X
1
1
−
X − 00H
×
×
×
B
1
1
−
B − 00H
×
×
×
C
1
1
−
C − 00H
×
×
×
saddr
2
1
−
(saddr) − 00H
×
×
×
!addr16
3
1
4
(addr16) − 00H
×
×
×
ES:!addr16
4
2
5
(ES:addr16) − 00H
×
×
×
X, [HL + byte]
3
1
4
X − (HL + byte)
×
×
×
X, ES:[HL + byte]
4
2
5
X − ((ES:HL) + byte)
×
×
×
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
2.
When the program memory area is accessed.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
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CHAPTER 30 INSTRUCTION SET
Table 30-5. Operation List (11/17)
Instruction Mnemonic
Operands
Bytes
Group
16-bit
Note 1 Note 2
ADDW
operation
SUBW
CMPW
Multiply
Notes 1.
2.
Operation
Clocks
MULU
Flag
Z
AC CY
AX, #word
3
1
−
AX, CY ← AX + word
×
×
×
AX, AX
1
1
−
AX, CY ← AX + AX
×
×
×
AX, BC
1
1
−
AX, CY ← AX + BC
×
×
×
AX, DE
1
1
−
AX, CY ← AX + DE
×
×
×
AX, HL
1
1
−
AX, CY ← AX + HL
×
×
×
AX, saddrp
2
1
−
AX, CY ← AX + (saddrp)
×
×
×
AX, !addr16
3
1
4
AX, CY ← AX + (addr16)
×
×
×
AX, [HL+byte]
3
1
4
AX, CY ← AX + (HL + byte)
×
×
×
AX, ES:!addr16
4
2
5
AX, CY ← AX + (ES:addr16)
×
×
×
AX, ES: [HL+byte]
4
2
5
AX, CY ← AX + ((ES:HL) + byte)
×
×
×
AX, #word
3
1
−
AX, CY ← AX − word
×
×
×
AX, BC
1
1
−
AX, CY ← AX − BC
×
×
×
AX, DE
1
1
−
AX, CY ← AX − DE
×
×
×
AX, HL
1
1
−
AX, CY ← AX − HL
×
×
×
AX, saddrp
2
1
−
AX, CY ← AX − (saddrp)
×
×
×
AX, !addr16
3
1
4
AX, CY ← AX − (addr16)
×
×
×
AX, [HL+byte]
3
1
4
AX, CY ← AX − (HL + byte)
×
×
×
AX, ES:!addr16
4
2
5
AX, CY ← AX − (ES:addr16)
×
×
×
AX, ES: [HL+byte]
4
2
5
AX, CY ← AX − ((ES:HL) + byte)
×
×
×
AX, #word
3
1
−
AX − word
×
×
×
AX, BC
1
1
−
AX − BC
×
×
×
AX, DE
1
1
−
AX − DE
×
×
×
AX, HL
1
1
−
AX − HL
×
×
×
AX, saddrp
2
1
−
AX − (saddrp)
×
×
×
AX, !addr16
3
1
4
AX − (addr16)
×
×
×
AX, [HL+byte]
3
1
4
AX − (HL + byte)
×
×
×
AX, ES:!addr16
4
2
5
AX − (ES:addr16)
×
×
×
AX, ES: [HL+byte]
4
2
5
AX − ((ES:HL) + byte)
×
×
×
X
1
1
−
AX ← A × X
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
870
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CHAPTER 30 INSTRUCTION SET
Table 30-5. Operation List (12/17)
Instruction Mnemonic
Operands
Bytes
Group
Operation
Clocks
Note 1 Note 2
Flag
Z
AC CY
Increment/ INC
r
1
1
−
r←r+1
×
×
decrement
saddr
2
2
−
(saddr) ← (saddr) + 1
×
×
!addr16
3
2
−
(addr16) ← (addr16) + 1
×
×
(HL+byte) ← (HL+byte) + 1
×
×
(ES, addr16) ← (ES, addr16) + 1
×
×
DEC
ES:!addr16
4
3
−
ES: [HL+byte]
4
3
−
((ES:HL) + byte) ← ((ES:HL) + byte) + 1
×
×
r
1
1
−
r←r−1
×
×
saddr
2
2
−
(saddr) ← (saddr) − 1
×
×
!addr16
3
2
−
(addr16) ← (addr16) − 1
×
×
(HL+byte) ← (HL+byte) − 1
×
×
3
2
ES:!addr16
4
3
−
(ES, addr16) ← (ES, addr16) − 1
×
×
ES: [HL+byte]
4
3
−
((ES:HL) + byte) ← ((ES:HL) + byte) − 1
×
×
rp
1
1
−
rp ← rp + 1
saddrp
2
2
−
(saddrp) ← (saddrp) + 1
!addr16
3
2
−
(addr16) ← (addr16) + 1
[HL+byte]
3
2
−
(HL+byte) ← (HL+byte) + 1
ES:!addr16
4
3
−
(ES, addr16) ← (ES, addr16) + 1
ES: [HL+byte]
4
3
−
((ES:HL) + byte) ← ((ES:HL) + byte) + 1
rp
1
1
−
rp ← rp − 1
saddrp
2
2
−
(saddrp) ← (saddrp) − 1
!addr16
3
2
−
(addr16) ← (addr16) − 1
[HL+byte]
3
2
−
(HL+byte) ← (HL+byte) − 1
ES:!addr16
4
3
−
(ES, addr16) ← (ES, addr16) − 1
ES: [HL+byte]
4
3
−
((ES:HL) + byte) ← ((ES:HL) + byte) − 1
SHR
A, cnt
2
1
−
(CY ← A0, Am−1 ← Am, A7 ← 0) × cnt
×
SHRW
AX, cnt
2
1
−
(CY ← AX0, AXm−1 ← AXm, AX15 ← 0) × cnt
×
SHL
A, cnt
2
1
−
(CY ← A7, Am ← Am−1, A0 ← 0) × cnt
×
B, cnt
2
1
−
(CY ← B7, Bm ← Bm−1, B0 ← 0) × cnt
×
C, cnt
2
1
−
(CY ← C7, Cm ← Cm−1, C0 ← 0) × cnt
×
AX, cnt
2
1
−
(CY ← AX15, AXm ← AXm−1, AX0 ← 0) × cnt
×
BC, cnt
2
1
−
(CY ← BC15, BCm ← BCm−1, BC0 ← 0) × cnt
×
SAR
A, cnt
2
1
−
(CY ← A0, Am−1 ← Am, A7 ← A7) × cnt
×
SARW
AX, cnt
2
1
−
(CY ← AX0, AXm−1 ← AXm, AX15 ← AX15) × cnt
×
SHLW
2.
2
[HL+byte]
DECW
Notes 1.
3
−
INCW
Shift
[HL+byte]
−
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
3. cnt indicates the bit shift count.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
871
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CHAPTER 30 INSTRUCTION SET
Table 30-5. Operation List (13/17)
Instruction Mnemonic
Operands
Bytes
Group
Rotate
Bit
Note 1 Note 2
Z
AC CY
A, 1
2
1
−
(CY, A7 ← A0, Am−1 ← Am) × 1
×
ROL
A, 1
2
1
−
(CY, A0 ← A7, Am + 1 ← Am) × 1
×
RORC
A, 1
2
1
−
(CY ← A0, A7 ← CY, Am−1 ← Am) × 1
×
ROLC
A, 1
2
1
−
(CY ← A7, A0 ← CY, Am + 1 ← Am) × 1
×
ROLWC
AX,1
2
1
−
(CY ← AX15, AX0 ← CY, AXm + 1 ← AXm) × 1
×
BC,1
2
1
−
(CY ← BC15, BC0 ← CY, BCm + 1 ← BCm) × 1
×
CY, saddr.bit
3
1
−
CY ← (saddr).bit
×
CY, sfr.bit
3
1
−
CY ← sfr.bit
×
CY, A.bit
2
1
−
CY ← A.bit
×
CY, PSW.bit
3
1
−
CY ← PSW.bit
×
CY,[HL].bit
2
1
4
CY ← (HL).bit
×
saddr.bit, CY
3
2
−
(saddr).bit ← CY
sfr.bit, CY
3
2
−
sfr.bit ← CY
manipulate
AND1
OR1
2.
Flag
ROR
MOV1
Notes 1.
Operation
Clocks
A.bit, CY
2
1
−
A.bit ← CY
PSW.bit, CY
3
4
−
PSW.bit ← CY
[HL].bit, CY
2
2
−
(HL).bit ← CY
CY, ES:[HL].bit
3
2
5
CY ← (ES, HL).bit
ES:[HL].bit, CY
3
3
−
(ES, HL).bit ← CY
CY, saddr.bit
3
1
−
CY ← CY ∧ (saddr).bit
×
CY, sfr.bit
3
1
−
CY ← CY ∧ sfr.bit
×
CY, A.bit
2
1
−
CY ← CY ∧ A.bit
×
CY, PSW.bit
3
1
−
CY ← CY ∧ PSW.bit
×
CY,[HL].bit
2
1
4
CY ← CY ∧ (HL).bit
×
CY, ES:[HL].bit
3
2
5
CY ← CY ∧ (ES, HL).bit
×
CY, saddr.bit
3
1
−
CY ← CY ∨ (saddr).bit
×
CY, sfr.bit
3
1
−
CY ← CY ∨ sfr.bit
×
CY, A.bit
2
1
−
CY ← CY ∨ A.bit
×
CY, PSW.bit
3
1
−
CY ← CY ∨ PSW.bit
×
CY, [HL].bit
2
1
4
CY ← CY ∨ (HL).bit
×
CY, ES:[HL].bit
3
2
5
CY ← CY ∨ (ES, HL).bit
×
×
×
×
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
872
78K0R/Lx3
CHAPTER 30 INSTRUCTION SET
Table 30-5. Operation List (14/17)
Instruction Mnemonic
Operands
Bytes
Group
Bit
Note 1 Note 2
XOR1
manipulate
SET1
CLR1
Notes 1.
2.
Operation
Clocks
Flag
Z
AC CY
CY, saddr.bit
3
1
−
CY ← CY ∨ (saddr).bit
×
CY, sfr.bit
3
1
−
CY ← CY ∨ sfr.bit
×
CY, A.bit
2
1
−
CY ← CY ∨ A.bit
×
CY, PSW.bit
3
1
−
CY ← CY ∨ PSW.bit
×
CY, [HL].bit
2
1
4
CY ← CY ∨ (HL).bit
×
×
CY, ES:[HL].bit
3
2
5
CY ← CY ∨ (ES, HL).bit
saddr.bit
3
2
−
(saddr).bit ← 1
sfr.bit
3
2
−
sfr.bit ← 1
A.bit
2
1
−
A.bit ← 1
!addr16.bit
4
2
−
(addr16).bit ← 1
PSW.bit
3
4
−
PSW.bit ← 1
[HL].bit
2
2
−
(HL).bit ← 1
ES:!addr16.bit
5
3
−
(ES, addr16).bit ← 1
ES:[HL].bit
3
3
−
(ES, HL).bit ← 1
saddr.bit
3
2
−
(saddr.bit) ← 0
sfr.bit
3
2
−
sfr.bit ← 0
A.bit
2
1
−
A.bit ← 0
!addr16.bit
4
2
−
(addr16).bit ← 0
PSW.bit
3
4
−
PSW.bit ← 0
[HL].bit
2
2
−
(HL).bit ← 0
ES:!addr16.bit
5
3
−
(ES, addr16).bit ← 0
×
×
×
×
×
×
ES:[HL].bit
3
3
−
(ES, HL).bit ← 0
SET1
CY
2
1
−
CY ← 1
1
CLR1
CY
2
1
−
CY ← 0
0
NOT1
CY
2
1
−
CY ← CY
×
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
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Table 30-5. Operation List (15/17)
Instruction Mnemonic
Operands
Bytes
Group
Call/
Operation
Clocks
Note 1 Note 2
CALL
rp
2
3
−
Flag
Z
AC CY
(SP − 2) ← (PC + 2)S, (SP − 3) ← (PC + 2)H,
(SP − 4) ← (PC + 2)L, PC ← CS, rp,
return
SP ← SP − 4
$!addr20
3
3
−
(SP − 2) ← (PC + 3)S, (SP − 3) ← (PC + 3)H,
(SP − 4) ← (PC + 3)L, PC ← PC + 3 +
jdisp16,
SP ← SP − 4
!addr16
3
3
−
(SP − 2) ← (PC + 3)S, (SP − 3) ← (PC + 3)H,
(SP − 4) ← (PC + 3)L, PC ← 0000, addr16,
SP ← SP − 4
!!addr20
4
3
−
(SP − 2) ← (PC + 4)S, (SP − 3) ← (PC + 4)H,
(SP − 4) ← (PC + 4)L, PC ← addr20,
SP ← SP − 4
CALLT
[addr5]
2
5
−
(SP − 2) ← (PC + 2)S, (SP − 3) ← (PC + 2)H,
(SP − 4) ← (PC + 2)L , PCS ← 0000,
PCH ← (0000, addr5 + 1),
PCL ← (0000, addr5),
SP ← SP − 4
BRK
−
2
5
−
(SP − 1) ← PSW, (SP − 2) ← (PC + 2)S,
(SP − 3) ← (PC + 2)H, (SP − 4) ← (PC + 2)L,
PCS ← 0000,
PCH ← (0007FH), PCL ← (0007EH),
SP ← SP − 4, IE ← 0
RET
−
1
6
−
PCL ← (SP), PCH ← (SP + 1),
PCS ← (SP + 2), SP ← SP + 4
RETI
−
2
6
−
PCL ← (SP), PCH ← (SP + 1),
R
R
R
R
R
R
PCS ← (SP + 2), PSW ← (SP + 3),
SP ← SP + 4
RETB
−
2
6
−
PCL ← (SP), PCH ← (SP + 1),
PCS ← (SP + 2), PSW ← (SP + 3),
SP ← SP + 4
Notes 1.
2.
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
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CHAPTER 30 INSTRUCTION SET
Table 30-5. Operation List (16/17)
Instruction Mnemonic
Operands
Bytes
Group
Stack
Operation
Clocks
Note 1 Note 2
PUSH
PSW
2
1
−
Flag
Z
AC CY
(SP − 1) ← PSW, (SP − 2) ← 00H,
SP ← SP − 2
manipulate
rp
1
1
−
(SP − 1) ← rpH, (SP − 2)← rpL,
SP ← SP − 2
PSW
2
3
−
PSW ← (SP + 1), SP ← SP + 2
rp
1
1
−
rpL ← (SP), rpH ← (SP + 1), SP ← SP + 2
SP, #word
4
1
−
SP ← word
SP, AX
2
1
−
SP ← AX
AX, SP
2
1
−
AX ← SP
HL, SP
3
1
−
HL ← SP
BC, SP
3
1
−
BC ← SP
DE, SP
3
1
−
DE ← SP
ADDW
SP, #byte
2
1
−
SP ← SP + byte
SUBW
SP, #byte
2
1
−
SP ← SP − byte
BR
AX
2
3
−
PC ← CS, AX
$addr20
2
3
−
PC ← PC + 2 + jdisp8
$!addr20
3
3
−
PC ← PC + 3 + jdisp16
!addr16
3
3
−
PC ← 0000, addr16
!!addr20
4
3
POP
MOVW
Unconditio
nal branch
Conditional BC
branch
BNC
BZ
BNZ
BH
BNH
BT
$addr20
$addr20
$addr20
$addr20
$addr20
$addr20
saddr.bit, $addr20
sfr.bit, $addr20
A.bit, $addr20
PSW.bit, $addr20
[HL].bit, $addr20
ES:[HL].bit,
2
2
2
2
3
3
4
4
3
4
3
4
−
PC ← addr20
2/4
Note 3
−
PC ← PC + 2 + jdisp8 if CY = 1
2/4
Note 3
−
PC ← PC + 2 + jdisp8 if CY = 0
2/4
Note 3
−
PC ← PC + 2 + jdisp8 if Z = 1
2/4
Note 3
−
PC ← PC + 2 + jdisp8 if Z = 0
2/4
Note 3
−
PC ← PC+3+jdisp8 if (Z ∨ CY)=0
2/4
Note 3
−
PC ← PC+3+jdisp8 if (Z ∨ CY)=1
3/5
Note 3
−
PC ← PC + 4 + jdisp8 if (saddr).bit = 1
3/5
Note 3
−
PC ← PC + 4 + jdisp8 if sfr.bit = 1
3/5
Note 3
−
PC ← PC + 3 + jdisp8 if A.bit = 1
3/5
Note 3
−
PC ← PC + 4 + jdisp8 if PSW.bit = 1
3/5
Note 3
6/7
PC ← PC + 3 + jdisp8 if (HL).bit = 1
4/6
Note 3
7/8
PC ← PC + 4 + jdisp8
$addr20
Notes 1.
R
R
R
if (ES, HL).bit = 1
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
2.
When the program memory area is accessed.
3.
This indicates the number of clocks “when condition is not met/when condition is met”.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
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Table 30-5. Operation List (17/17)
Instruction Mnemonic
Operands
Bytes
Group
Condition
Operation
Clocks
Note 1 Note 2
BF
al branch
saddr.bit, $addr20
sfr.bit, $addr20
A.bit, $addr20
PSW.bit, $addr20
[HL].bit, $addr20
BTCLR
4
4
3
4
3
Z
3/5
Note 3
−
PC ← PC + 4 + jdisp8 if (saddr).bit = 0
3/5
Note 3
−
PC ← PC + 4 + jdisp8 if sfr.bit = 0
3/5
Note 3
−
PC ← PC + 3 + jdisp8 if A.bit = 0
3/5
Note 3
−
PC ← PC + 4 + jdisp8 if PSW.bit = 0
3/5
Note 3
6/7
PC ← PC + 3 + jdisp8 if (HL).bit = 0
7/8
PC ← PC + 4 + jdisp8 if (ES, HL).bit = 0
−
ES:[HL].bit, $addr20
4
4/6
Note 3
saddr.bit, $addr20
4
3/5
Note 3
3/5
Note 3
3/5
Note 3
3/5
Note 3
Flag
AC CY
PC ← PC + 4 + jdisp8 if (saddr).bit = 1
then reset (saddr).bit
sfr.bit, $addr20
4
−
PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr20
3
−
PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr20
4
−
PC ← PC + 4 + jdisp8 if PSW.bit = 1
×
×
×
then reset PSW.bit
[HL].bit, $addr20
3
3/5
Note 3
4/6
Note 3
−
PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
ES:[HL].bit, $addr20
4
−
PC ← PC + 4 + jdisp8 if (ES, HL).bit = 1
then reset (ES, HL).bit
Conditional SKC
skip
SKNC
−
2
1
−
Next instruction skip if CY = 1
−
2
1
−
Next instruction skip if CY = 0
SKZ
−
2
1
−
Next instruction skip if Z = 1
SKNZ
−
2
1
−
Next instruction skip if Z = 0
SKH
−
2
1
−
Next instruction skip if (Z ∨ CY) = 0
SKNH
−
2
1
−
Next instruction skip if (Z ∨ CY) = 1
2
1
−
RBS[1:0] ← n
CPU
SEL
control
NOP
−
1
1
−
No Operation
EI
−
3
4
−
IE ← 1(Enable Interrupt)
DI
−
3
4
−
IE ← 0(Disable Interrupt)
HALT
−
2
3
−
Set HALT Mode
STOP
−
2
3
−
Set STOP Mode
Notes 1.
RBn
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
2.
When the program memory area is accessed.
3.
This indicates the number of clocks “when condition is not met/when condition is met”.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
3. n indicates the number of register banks (n = 0 to 3)
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
Cautions 1. The 78K0R/Lx3 microcontrollers have an on-chip debug function, which is provided for
development and evaluation. Do not use the on-chip debug function in products designated for
mass production, because the guaranteed number of rewritable times of the flash memory may be
exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.
2. The pins mounted depend on the product.
Refer to 1.3
Pin Configuration (Top View) and
CHAPTER 2 PIN FUNCTIONS.
Absolute Maximum Ratings (TA = 25°C) (1/3)
Parameter
Supply voltage
Symbols
Conditions
Ratings
Unit
VDD
−0.5 to +6.5
V
EVDD
−0.5 to +6.5
V
VSS
−0.5 to +0.3
V
EVSS
−0.5 to +0.3
V
−0.5 to VDD +0.3
V
−0.5 to VDD +0.3Note 1
V
−0.5 to +0.3
V
Note 1
AVDD0,
AVDD
AVDD1,
EVDD1
AVSS
REGC pin input voltage VIREGC
−0.3 to +3.6
REGC
and −0.3 to VDD +0.3
Input voltage
VI1
P00 to P02, P10 to P17, P30 to P34, P40, P41,
P50 to P57, P70 to P77, P80 to P87, P90 to P97,
V
Note 2
−0.3 to EVDD +0.3
and −0.3 to VDD +0.3
V
Note 1
P100 to P102, P120 to P124, P140 to P147, EXCLK,
RESET, FLMD0
−0.3 to +6.5
V
P20 to P27, P150 to P152, P157 μ PD78F150xA
−0.3 to AVDD0 +0.3
and −0.3 to VDD +0.3Note 1
V
μ PD78F151xA
−0.3 to AVDD +0.3
and −0.3 to VDD +0.3Note 1
μ PD78F150xA
−0.3 to AVDD1 +0.3
and −0.3 to VDD +0.3Note 1
μ PD78F151xA
−0.3 to EVDD1 +0.3
and −0.3 to VDD +0.3Note 1
VI2
P60, P61 (N-ch open-drain)
VI3
VI4
P110, P111
V
Notes 1. Must be 6.5 V or lower.
2. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μ F).
This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C) (2/3)
Parameter
Symbols
Output voltage
VO1
Conditions
P00 to P02, P10 to P17, P30 to P34, P40, P41,
Ratings
Unit
−0.3 to EVDD +0.3
V
P50 to P57, P60, P61, P70 to P77, P80 to P87,
P90 to P97, P100 to P102, P120, P130, P140 to
P147
VO2
P20 to P27, P150 to P152, P157
−0.3 to AVDD0 +0.3
V
VO3
P110, P111
−0.3 to AVDD1 +0.3
V
SEG0 to SEG53, COM0
External resistance
−0.3 to VDD +0.3
V
to COM7
division method,
VO4
Note
capacitor split method
Internal voltage boosting
−0.3 to VLC0 +0.3
Note
V
method
Analog input voltage
VAI
ANI0 to ANI10, ANI15, AMP0+, AMP1+, AMP2+,
AMP0-, AMP1-, AMP2- (μ PD78F150xA)
ANI0 to ANI10, ANI15 (μ PD78F151xA)
Analog input reference
voltage
V
Note
−0.3 to AVDD +0.3
and −0.3 to VDD +0.3
Analog output voltage
−0.3 to AVDD0 +0.3
and −0.3 to VDD +0.3
V
Note
ANO0, ANO1
−0.3 to AVDD1 +0.3
Note
V
VAO2
AMP0O, AMP1O, AMP2O
−0.3 to AVDD0 +0.3
Note
V
AVREF
μ PD78F151xA
−0.3 to AVDD +0.3
Note
V
AVREFP
μ PD78F150xA
AVREFM
μ PD78F150xA
VAO1
−0.3 to AVDD0 +0.3
Note
V
−0.3 to AVDD0 +0.3
Note
V
and AVREFM≤ AVREFP
Output current, high
IOH1
Per pin
P00 to P02, P10-P17, P30 to P34,
−10
mA
−10
mA
−25
mA
−25
mA
P40, P41, P70 to P77, P80 to
P87, P120, P130
P50 to P57, P90 to P97,
P100 to P102, P140 to P147
Total of all pins
P00 to P02, P10-P17, P30 to P34,
−50 mA
P40, P41, P70 to P77, P80 to
P87, P120, P130
P50 to P57, P90 to P97, P100 to
P102, P140 to P147
IOH2
IOH3
Per pin
P20 to P27, P150 to P152,
−0.5
mA
Total of all pins
P157, P110, P111
−2
mA
Per pin
AMP0O, AMP1O, AMP2O
−1
mA
−3
mA
Total of all pins
Note Must be 6.5 V or lower.
Cautions 1. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
2. The value of the current that can be run per pin must satisfy the value of the current per pin and
the total value of the currents of all pins.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C) (3/3)
Parameter
Output current, low
Symbols
IOL1
Conditions
Per pin
Ratings
Unit
30
mA
P60, P61
30
mA
P50 to P57, P90 to P97, P100 to
10
mA
80
mA
P60, P61
60
mA
P50 to P57, P90 to P97, P100 to
25
mA
P00 to P02, P10-P17, P30 to P34,
P40, P41, P70 to P77, P80 to
P87, P120, P130
P102, P140 to P147
Total of all pins
P00 to P02, P10-P17, P30 to P34,
165 mA
P40, P41, P70 to P77, P80 to
P87, P120, P130
P102, P140 to P147
IOL2
IOL3
Per pin
P20 to P27, P150 to P152,
1
mA
Total of all pins
P157, P110, P111
5
mA
Per pin
AMP0O, AMP1O, AMP2O
1
mA
3
mA
−40 to +85
°C
−65 to +150
°C
Total of all pins
Operating ambient
TA
temperature
In normal operation mode
In flash memory programming mode
Storage temperature
Tstg
Cautions 1. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
2. The value of the current that can be run per pin must satisfy the value of the current per pin and the
total value of the currents of all pins.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
X1 Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVSS = 0 V)
Recommended
Resonator
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
MHz
Circuit
Ceramic resonator,
VSS X1
crystal resonator
C1
X2
X1 clock oscillation
Note
frequency (fX)
2.7 V ≤ VDD ≤ 5.5 V
2.0
20.0
1.8 V ≤ VDD < 2.7 V
2.0
5.0
C2
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above
figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. Since the CPU is started by the internal high-speed oscillation clock after a reset release, check
the X1 clock oscillation stabilization time using the oscillation stabilization time counter status
register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and
oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation
stabilization time with the resonator to be used.
Remark
For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
Internal Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVSS = 0 V)
Oscillators
Parameters
Conditions
MIN.
TYP.
MAX.
Unit
Internal high-
fIH1M
Low-power consumption mode
0.87
1
1.13
MHz
speed oscillation
fIH8M
2.7 V ≤ VDD ≤ 5.5 V
7.856
8
8.144
MHz
1.8 V ≤ VDD < 2.7 V, TA = −20 to +70°C
7.848
8
8.152
MHz
clock frequency
Note
fIH20M
Internal low-speed fIL
oscillation clock
frequency
1.8 V ≤ VDD < 2.7 V
7.84
8
8.16
MHz
2.7 V ≤ VDD ≤ 5.5 V
19.52
20
20.48
MHz
2.7 V ≤ VDD ≤ 5.5 V
27
30
33
kHz
1.8 V ≤ VDD < 2.7 V
25.5
30
34.5
kHz
25.5
30
34.5
kHz
Normal power mode
Low-power consumption mode
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
XT1 Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVSS = 0 V)
Resonator
Recommended
Items
Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
Circuit
Crystal resonator
XT1 clock oscillation
VSS XT2
XT1
Note
frequency (fXT)
Rd
C4
C3
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is
more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required
with the wiring method when the XT1 clock is used.
Remark
For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
Recommended oscillator circuit constants
(1) X1 oscillation: Ceramic resonator (AMPH = 0, RMC = 00H, TA = −40 to +85°C)
Manufacturer
Murata
Manufacturing
Part Number
SMD/
Frequency
Lead
(MHz)
Recommended Circuit Constants
Oscillation Voltage
Range
C1 (pF)
C2 (pF)
Rd (kΩ)
CSTCC2M00G56-R0
SMD
2.0
Internal (47)
Internal (47)
0
CSTCR4M00G55-R0
SMD
4.0
Internal (39)
Internal (39)
0
CSTLS4M00G56-B0
Lead
Internal (47)
Internal (47)
0
CSTCR4M19G55-R0
SMD
Internal (39)
Internal (39)
0
CSTLS4M19G56-B0
Lead
Internal (47)
Internal (47)
0
CSTCR4M91G55-R0
SMD
Internal (39)
Internal (39)
0
CSTLS4M91G53-B0
Lead
Internal (15)
Internal (15)
0
CSTCR5M00G55-R0
SMD
Internal (39)
Internal (39)
0
CSTLS5M00G53-B0
Lead
Internal (15)
Internal (15)
0
CSTCR6M00G53-R0
SMD
Internal (15)
Internal (15)
0
CSTLS6M00G53-B0
Lead
Internal (15)
Internal (15)
0
CSTCE8M00G55-R0
SMD
Internal (33)
Internal (33)
0
CSTLS8M00G53-B0
Lead
Internal (15)
Internal (15)
0
CSTCE8M38G55-R0
SMD
Internal (33)
Internal (33)
0
CSTLS8M38G53-B0
Lead
Internal (15)
Internal (15)
0
CSTCE10M0G52-R0
SMD
Internal (10)
Internal (10)
0
CSTLS10M0G53-B0
Lead
Internal (15)
Internal (15)
0
MIN. (V) MAX. (V)
1.8
5.5
Co., Ltd..
4.194
4.915
5.0
6.0
8.0
8.388
10.0
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer.
If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on the
implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator
characteristic.
Use the 78K0R/Lx3 so that the internal operation conditions are within the
specifications of the DC and AC characteristics.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
882
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) X1 oscillation: Ceramic resonator (AMPH = 1, RMC = 00H, TA = −40 to +85°C)
Manufacturer
Murata
Manufacturing
Part Number
SMD/
Frequency
Lead
(MHz)
Recommended Circuit Constants
Oscillation Voltage
Range
C1 (pF)
C2 (pF)
Rd (kΩ)
CSTCE12M0G55-R0
SMD
12.0
Internal (33)
Internal (33)
0
CSTCE16M0V53-R0
SMD
16.0
Internal (15)
Internal (15)
0
CSTLS16M0X51-B0
Lead
Internal (5)
Internal (5)
0
CSTCE20M0V53-R0
SMD
Internal (15)
Internal (15)
0
CSTLS20M0X51-B0
Lead
Internal (5)
Internal (5)
0
MIN. (V) MAX. (V)
1.8
5.5
Co., Ltd..
20.0
(3) X1 oscillation: Ceramic resonator (AMPH = 0, RMC = 5AH, TA = −40 to +85°C)
Manufacturer
Murata
Manufacturing
Part Number
SMD/
Frequency
Lead
(MHz)
Recommended Circuit Constants
Oscillation Voltage
Range
C1 (pF)
C2 (pF)
Rd (kΩ)
CSTCC2M00G56-R0
SMD
2.0
Internal (47)
Internal (47)
0
CSTCR4M00G55-R0
SMD
4.0
Internal (39)
Internal (39)
0
CSTLS4M00G53-B0
Lead
Internal (15)
Internal (15)
0
CSTCR4M19G55-R0
SMD
Internal (39)
Internal (39)
0
CSTLS4M19G53-B0
Lead
Internal (15)
Internal (15)
0
CSTCR4M91G53-R0
SMD
Internal (15)
Internal (15)
0
CSTLS4M91G53-B0
Lead
Internal (15)
Internal (15)
0
CSTCR5M00G53-R0
SMD
Internal (15)
Internal (15)
0
CSTLS5M00G53-B0
Lead
Internal (15)
Internal (15)
0
DCRHTC(P)2.00LL
Lead
2.0
Internal (30)
Internal (30)
−
4.0
Internal (30)
Internal (30)
−
MIN. (V) MAX. (V)
1.8
5.5
1.8
5.5
Co., Ltd..
TOKO, Inc.
DCRHTC(P)4.00LL
4.194
4.195
5.0
DECRHTC4.00
SMD
4.0
Internal (15)
Internal (15)
−
DCRHTC(P)5.00LL
Lead
5.0
Internal (30)
Internal (30)
−
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer.
If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on the
implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator
characteristic.
Use the 78K0R/Lx3 so that the internal operation conditions are within the
specifications of the DC and AC characteristics.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
883
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(4) XT1 oscillation: Crystal resonator (TA = −40 to +85°C)
Manufacturer
Part
SMD/
Frequency
Number
Lead
(MHz)
Load
Capacitance
XT1 oscllator
oscillation mode
Recommended Circuit
Oscillation
Constants
Voltage Range
Note 1
CL (pF)
Seiko
SSP-T7-F
Instruments
Note 2
Inc.
SSP-T7-FL
SMD
32.768
7.0
6.0
C3
C4
Rd
(pF)
(pF)
(kΩ)
Normal oscillation
10
10
0
Low power
9
8
0
4
3
0
Normal oscillation
20
20
0
Low power
9
8
0
4
3
0
MIN.
MAX.
(V)
(V)
1.8
5.5
consumption
oscillation
3.7
Ultra-low power
consumption
oscillation
VT-200-F
Lead
VT-200-FL
12.5
6.0
consumption
oscillation
3.7
Ultra-low power
consumption
oscillation
Notes 1. Set the XT1 oscillation mode by using bits AMPHS1 and AMPHS0 of the clock operation mode control
register (CMC).
2. Contact Seiko Instruments Inc. (http://www.sii-crystal.com) when using this resonator.
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Jun 20, 2011
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
DC Characteristics (1/11)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 1.8 V ≤ AVDD0 ≤ VDD,
1.8 V ≤ AVDD ≤ VDD, 1.8 V ≤ EVDD1 = VDD, VSS = EVSS = AVSS = 0 V)
Items
Symbol
Output current,
Note 1
high
IOH1
Conditions
Per pin for P00 to P02, P10 to P17,
P30 to P34, P40, P41, P70 to P77,
P80 to P87, P120, P130
Per pin for P50 to P57, P90 to P97,
P100 to P102, P140 to P147
IOH2
Notes 1.
MIN.
1.8 V ≤ AVDD1 ≤ VDD,
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
−3.0
mA
2.7 V ≤ VDD < 4.0 V
−1.0
mA
1.8 V ≤ VDD < 2.7 V
−1.0
mA
4.0 V ≤ VDD ≤ 5.5 V
−1.6
mA
2.7 V ≤ VDD < 4.0 V
−0.45
mA
1.8 V ≤ VDD < 2.7 V
−0.45
mA
Total of P00 to P02, P10 to P17, P30 4.0 V ≤ VDD ≤ 5.5 V
to P34, P40, P41, P70 to P77, P80 to 2.7 V ≤ VDD < 4.0 V
P87, P120, P130
1.8 V ≤ VDD < 2.7 V
Note 2
)
(When duty = 70%
−20.0
mA
−10.0
mA
−5.0
mA
Total of P50 to P57, P90 to P97,
P100 to P102, P140 to P147
Note 2
)
(When duty = 70%
4.0 V ≤ VDD ≤ 5.5 V
−12.8
mA
2.7 V ≤ VDD < 4.0 V
−3.6
mA
1.8 V ≤ VDD < 2.7 V
−3.6
mA
Total of all pins
Note 2
)
(When duty = 60%
4.0 V ≤ VDD ≤ 5.5 V
−32.8
mA
2.7 V ≤ VDD < 4.0 V
−13.6
mA
1.8 V ≤ VDD < 2.7 V
−8.6
mA
Per pin for P20 to P27, P150 to P152, P157
−0.1
mA
Per pin for P110, P111
−0.1
mA
Value of current at which the device operation is guaranteed even if the current flows from VDD pin to an
output pin.
2.
Specification under conditions where the duty factor is 60% or 70%.
The output current value that has changed the duty ratio can be calculated with the following expression
(when changing the duty factor from 70% to n%).
•Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 50% and IOH = −20.0 mA
Total output current of pins = (−20.0 × 0.7)/(50 × 0.01) = −28.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Caution P10 to P15, P75, P77, P80 and P82 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
DC Characteristics (2/11)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 1.8 V ≤ AVDD0 ≤ VDD,
1.8 V ≤ AVDD ≤ VDD, 1.8 V ≤ EVDD1 = VDD, VSS = EVSS = AVSS = 0 V)
Items
Symbol
Output current,
Note 1
low
IOL1
Conditions
Per pin for P00 to P02, P12, P13,
P16, P17, P30 to P34, P40, P41,
P70 to P77, P80 to P87, P120, P130
Per pin for P10, P11, P14, P15
Per pin for P60, P61
Per pin for P50 to P57, P90 to P97,
P100 to P102, P140 to P147
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
8.5
mA
2.7 V ≤ VDD < 4.0 V
1.0
mA
1.8 V ≤ VDD < 2.7 V
0.5
mA
4.0 V ≤ VDD ≤ 5.5 V
8.5
mA
2.7 V ≤ VDD < 4.0 V
1.5
mA
1.8 V ≤ VDD < 2.7 V
0.6
mA
4.0 V ≤ VDD ≤ 5.5 V
15.0
mA
2.7 V ≤ VDD < 4.0 V
3.0
mA
1.8 V ≤ VDD < 2.7 V
2.0
mA
4.0 V ≤ VDD ≤ 5.5 V
1.8
mA
2.7 V ≤ VDD < 4.0 V
0.8
mA
1.8 V ≤ VDD < 2.7 V
0.35
mA
4.0 V ≤ VDD ≤ 5.5 V
20.0
mA
2.7 V ≤ VDD < 4.0 V
15.0
mA
1.8 V ≤ VDD < 2.7 V
9.0
mA
Total of P60, P61
Note 2
(When duty = 70%
)
4.0 V ≤ VDD ≤ 5.5 V
30.0
mA
2.7 V ≤ VDD < 4.0 V
6.0
mA
1.8 V ≤ VDD < 2.7 V
4.0
mA
4.0 V ≤ VDD ≤ 5.5 V
14.4
mA
2.7 V ≤ VDD < 4.0 V
6.4
mA
1.8 V ≤ VDD < 2.7 V
2.8
mA
4.0 V ≤ VDD ≤ 5.5 V
64.4
mA
2.7 V ≤ VDD < 4.0 V
27.4
mA
1.8 V ≤ VDD < 2.7 V
15.8
mA
Per pin for P20 to P27, P150 to P152, P157
0.4
mA
Per pin for P110, P111
0.4
mA
Total of all pins
Note 2
(When duty = 70%
)
Notes 1.
TYP.
Total of P00 to P02, P10 to P17,
P30 to P34, P40, P41, P70 to P77,
P80 to P87, P120, P130
Note 2
)
(When duty = 70%
Total of P50 to P57, P90 to P97,
P100 to P102, P140 to P147
Note 2
(When duty = 70%
)
IOL2
MIN.
1.8 V ≤ AVDD1 ≤ VDD,
Value of current at which the device operation is guaranteed even if the current flows from an output pin to
VSS and AVSS pin.
2.
Specification under conditions where the duty factor is 60% or 70%.
The output current value that has changed the duty ratio can be calculated with the following expression
(when changing the duty factor from 70% to n%).
•Total output current of pins = (IOL × 0.7)/(n × 0.01)
Where n = 50% and IOL = 20.0 mA
Total output current of pins = (20.0 × 0.7)/(50 × 0.01) = 28.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
886
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
DC Characteristics (3/11)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 1.8 V ≤ AVDD0 ≤ VDD,
1.8 V ≤ AVDD ≤ VDD, 1.8 V ≤ EVDD1 = VDD, VSS = EVSS = AVSS = 0 V)
Items
Input voltage,
Symbol
VIH1
Conditions
MIN.
1.8 V ≤ AVDD1 ≤ VDD,
MAX.
Unit
0.7VDD
VDD
V
0.8VDD
VDD
V
2.2
VDD
V
2.0
VDD
V
1.6
VDD
V
μ PD78F150xA
0.7AVDD0
AVDD0
V
μ PD78F151xA
0.7AVDD
AVDD
V
μ PD78F150xA
0.7AVDD1
AVDD1
V
μ PD78F151xA
0.7EVDD1
EVDD1
V
P00 to P02, P12, P13, P17, P41, P51, P54 to P57, P82,
TYP.
P83, P90 to P97, P100 to P102, P123, P124, P140 to P147
high
VIH2
P10, P11, P14 to P16, P30 to P34,
Normal input buffer
P40, P50, P52, P53, P70 to P77,
P80, P81, P84 to P87, P120 to P122,
RESET
VIH3
P10, P11, P14, P15, P75, P76
TTL input buffer
4.0 V ≤ VDD ≤ 5.5 V
TTL input buffer
2.7 V ≤ VDD < 4.0 V
TTL input buffer
1.8 V ≤ VDD < 2.7 V
VIH4
VIH5
Note
P20 to P27, P150 to P152, P157
P110, P111
VIH6
P60, P61
VIH7
FLMD0
0.7VDD
0.9VDD
Note
6.0
V
VDD
V
Must be 0.9VDD or higher when used in the flash memory programming mode.
Caution The maximum value of VIH of pins P10 to P15, P75, P77, P80 and P82 is VDD, even in the N-ch opendrain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
887
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
DC Characteristics (4/11)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 1.8 V ≤ AVDD0 ≤ VDD,
1.8 V ≤ AVDD ≤ VDD, 1.8 V ≤ EVDD1 = VDD, VSS = EVSS = AVSS = 0 V)
Items
Input voltage,
Symbol
VIL1
Conditions
MIN.
1.8 V ≤ AVDD1 ≤ VDD,
MAX.
Unit
0
0.3VDD
V
Normal input buffer
0
0.2VDD
V
TTL input buffer
0
0.8
V
0
0.5
V
0
0.2
V
μ PD78F150xA
0
0.3AVDD0
V
μ PD78F151xA
0
0.3AVDD
V
μ PD78F150xA
0
0.3AVDD1
V
μ PD78F151xA
0
0.3EVDD1
V
0
0.3VDD
V
P00 to P02, P12, P13, P17, P41, P51, P54 to P57, P82,
TYP.
P83, P90 to P97, P100 to P102, P123, P124, P140 to P147
low
VIL2
P10, P11, P14 to P16, P30 to P34,
P40, P50, P52, P53, P70 to P77,
P80, P81, P84 to P87, P120 to P122,
RESET
VIL3
P10, P11, P14, P15, P75, P76
4.0 V ≤ VDD ≤ 5.5 V
TTL input buffer
2.7 V ≤ VDD < 4.0 V
TTL input buffer
1.8 V ≤ VDD < 2.7 V
VIL4
VIL5
VIL6
VIL7
P20 to P27, P150 to P152, P157
P110, P111
P60, P61
FLMD0
0
0.1VDD
Note
V
Note When disabling writing of the flash memory, connect the FLMD0 pin directly to VSS, and maintain a voltage less
than 0.1VDD.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
888
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
DC Characteristics (5/11)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 1.8 V ≤ AVDD0 ≤ VDD,
1.8 V ≤ AVDD ≤ VDD, 1.8 V ≤ EVDD1 = VDD, VSS = EVSS = AVSS = 0 V)
Items
Output voltage,
Symbol
VOH1
high
Conditions
MIN.
1.8 V ≤ AVDD1 ≤ VDD,
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V, VDD − 0.7
IOH1 = − 3.0 mA
V
P40, P41, P70 to P77, P80 to P87,
P120, P130
1.8 V ≤ VDD ≤ 5.5 V, VDD − 0.5
V
P00 to P02, P10 to P17, P30 to P34,
IOH1 = −1.0 mA
P50 to P57, P90 to P97,
P100 to P102, P140 to P147
4.0 V ≤ VDD ≤ 5.5 V, VDD − 0.7
IOH1 = − 1.6 mA
V
1.8 V ≤ VDD ≤ 5.5 V, VDD − 0.5
V
IOH1 = −0.45 mA
VOH2
P20 to P27, P150 to P152, P157
IOH2 = −0.1 mA
(μ PD78F150xA)
P20 to P27, P150 to P152, P157
IOH2 = −0.1 mA
P110, P111
(μ PD78F151xA)
AVDD
V
− 0.5
IOH2 = −0.1 mA
(μ PD78F150xA)
V
− 0.5
(μ PD78F151xA)
P110, P111
AVDD0
AVDD1
V
− 0.5
IOH2 = −0.1 mA
EVDD1
V
− 0.5
Caution
P10 to P15, P75, P77, P80 and P82 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
889
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
DC Characteristics (6/11)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 1.8 V ≤ AVDD0 ≤ VDD,
1.8 V ≤ AVDD ≤ VDD, 1.8 V ≤ EVDD1 = VDD, VSS = EVSS = AVSS = 0 V)
Items
Output voltage,
Symbol
VOL1
low
Conditions
MIN.
P00 to P02, P12, P13, P16, P17,
4.0 V ≤ VDD ≤ 5.5 V,
P30 to P34, P40, P41, P70 to P77,
IOL1 = 8.5 mA
P80 to P87, P120, P130
2.7 V ≤ VDD ≤ 5.5 V,
1.8 V ≤ AVDD1 ≤ VDD,
TYP.
MAX.
Unit
0.7
V
0.5
V
0.4
V
0.7
V
0.5
V
0.4
V
0.7
V
0.5
V
0.4
V
0.4
V
0.4
V
0.4
V
0.4
V
2.0
V
0.4
V
0.4
V
0.4
V
IOL1 = 1.0 mA
1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.5 mA
P10, P11, P14, P15
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 8.5 mA
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 1.5 mA
1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.6 mA
P50 to P57, P90 to P97, P100 to
4.0 V ≤ VDD ≤ 5.5 V,
P102, P140 to P147
IOL1 = 1.8 mA
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.8 mA
1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.35 mA
VOL2
VOL3
P20 to P27, P150 to P152, P157
AVDD0 ≤ 5.5 V,
(μ PD78F150xA)
IOL2 = 0.4 mA
P20 to P27, P150 to P152, P157
AVDD ≤ 5.5 V,
(μ PD78F151xA)
IOL2 = 0.4 mA
P110, P111
AVDD1 ≤ 5.5 V,
(μ PD78F150xA)
IOL2 = 0.4 mA
P110, P111
EVDD1 ≤ 5.5 V,
(μ PD78F151xA)
IOL2 = 0.4 mA
P60, P61
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 15.0 mA
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 5.0 mA
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 3.0 mA
1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 2.0 mA
Caution
P10 to P15, P75, P77, P80 and P82 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
890
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
DC Characteristics (7/11)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 1.8 V ≤ AVDD0 ≤ VDD,
1.8 V ≤ AVDD ≤ VDD, 1.8 V ≤ EVDD1 = VDD, VSS = EVSS = AVSS = 0 V)
Items
Input leakage
Symbol
ILIH1
Conditions
MAX.
Unit
VI = VDD
1
μA
VI = AVDD0
1
μA
VI = AVDD
1
μA
VI = AVDD1
1
μA
VI = EVDD1
1
μA
VI = VDD In input port
1
μA
10
μA
VI = VSS
−1
μA
P20 to P27, P150 to P152, P157
VI = VSS
−1
μA
P110, P111
VI = VSS
−1
μA
P121 to P124
VI = VSS
In input port
−1
μA
In resonator
−10
μA
100
kΩ
P00 to P02, P10 to P17, P30 to
MIN.
1.8 V ≤ AVDD1 ≤ VDD,
TYP.
P34, P40, P41, P50 to P57, P60,
current, high
P61, P70 to P77, P80 to P87,
P90 to P97, P100 to P102, P120,
P140 to P147, FLMD0, RESET
ILIH2
P20 to P27, P150 to P152, P157
(μ PD78F150xA)
P20 to P27, P150 to P152, P157
(μ PD78F151xA)
P110, P111
(μ PD78F150xA)
P110, P111
(μ PD78F151xA)
ILIH3
P121 to P124
(X1, X2, XT1, XT2)
In resonator
connection
Input leakage
ILIL1
P00 to P02, P10 to P17, P30 to
P34, P40, P41, P50 to P57, P60,
current, low
P61, P70 to P77, P80 to P87,
P90 to P97, P100 to P102, P120,
P140 to P147, FLMD0, RESET
ILIL2
ILIL3
(X1, X2, XT1, XT2)
connection
On-chip pll-up
RU
P00 to P02, P10 to P17, P30 to
VI = VSS, In input port
10
When enabling the self-programming mode setting with
100
20
P34, P40, P41, P50 to P57, P70
resistance
to P77, P80 to P87, P90 to P97,
P100 to P102, P120, P140 to
P147
FLMD0 pin
RFLMD0
external pull-
kΩ
software
down resistance
Note
Note It is recommended to leave the FLMD0 pin open. If the pin is required to be pulled down externally, set RFLMD0 to
100 kΩ or more.
78K0R/Lx3
microcontrollers
FLMD0 pin
RFLMD0
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
R01UH0004EJ0501 Rev.5.01
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
DC Characteristics (8/11)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 1.8 V ≤ AVDD0 ≤ VDD,
1.8 V ≤ AVDD ≤ VDD, 1.8 V ≤ EVDD1 = VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Symbol
Conditions
Supply
IDD1
Operating
current
Note 1
mode
fMX = 20 MHz, VDD = 5.0 V
MIN.
Note 2
fMX = 20 MHz, VDD = 3.0 V
Note 2
fMX = 10 MHz, VDD = 5.0 V
Notes 2, 3
fMX = 10 MHz, VDD = 3.0 V
Notes 2, 3
fMX = 5 MHz, VDD = 3.0 V
fMX = 5 MHz, VDD = 2.0 V
fIH = 20 MHz
fIH = 8 MHz
Notes 2, 3
Notes 2, 3
Note 4
Note 4
fIH = 1 MHz ,
RMC = 5AH, OSMC = 02H
TYP.
MAX.
Unit
Square wave input
5.5
7.7
mA
Resonator connection
5.8
8.0
mA
Square wave input
5.5
7.7
mA
Resonator connection
5.8
8.0
mA
Square wave input
3.2
4.6
mA
Resonator connection
3.3
4.7
mA
Square wave input
3.2
4.6
mA
Resonator connection
3.3
4.7
mA
Square wave input
1.8
2.7
mA
Resonator connection
1.9
2.8
mA
Square wave input
1.3
2.2
mA
Resonator connection
1.3
2.2
mA
VDD = 5.0 V
5.7
8.0
mA
VDD = 3.0 V
5.7
8.0
mA
VDD = 5.0 V
2.6
3.7
mA
VDD = 3.0 V
2.6
3.7
mA
VDD = 3.0 V
190
354
μA
Note 4
fSUB = 32.768 kHz,
TA = −40 to
VDD = 5.0 V
3.9
8.4
μA
FSEL = 0,
+50°C
VDD = 3.0 V
3.9
8.4
μA
VDD = 2.0 V
3.9
8.4
μA
TA = −40 to
VDD = 5.0 V
3.9
11.3
μA
+70°C
VDD = 3.0 V
3.9
11.3
μA
VDD = 2.0 V
3.9
11.3
μA
TA = −40 to
VDD = 5.0 V
3.9
14.6
μA
+85°C
VDD = 3.0 V
3.9
14.6
μA
VDD = 2.0 V
3.9
14.6
μA
SDIV = 1,
AMPHS1 = 1
1.8 V ≤ AVDD1 ≤ VDD,
Note 5
Notes 1. Total current flowing into VDD, EVDD, AVDD0 , AVDD1, AVDD, EVDD1, and VLC0 to VLC3, including the input leakage
current flowing when the level of the input pin is fixed to VDD or VSS, and excluding the current flowing into the realNote 6
, operational amplifier Note 6, voltage
time counter, watchdog timer, LVI circuit, A/D converter, D/A converter
Note 6
, LCD controller/driver, I/O port, and on-chip pull-up/pull-down resistors. The maximum values include
reference
the peripheral operation current.
2. When internal high-speed oscillator and subsystem clock are stopped.
3. When AMPH (bit 0 of clock operation mode control register (CMC)) = 0 and FLPC, FSEL (bits 1, 0 of operation
speed mode control register (OSMC)) = 0, 0.
4. When high-speed system clock and subsystem clock are stopped.
5. When internal high-speed oscillation, and high-speed system clock are stopped. When watchdog timer is
stopped.
6. Dedicated to μ PD78F150xA
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: Internal high-speed oscillation clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
R01UH0004EJ0501 Rev.5.01
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
DC Characteristics (9/11)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 1.8 V ≤ AVDD0 ≤ VDD,
1.8 V ≤ AVDD ≤ VDD, 1.8 V ≤ EVDD1 = VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Symbol
Conditions
Supply
IDD2
HALT
current
Note 1
mode
Note 2
fMX = 20 MHz, VDD = 5.0 V
fMX = 20 MHz, VDD = 3.0 V
Note 2
fMX = 10 MHz, VDD = 5.0 V
Notes 2, 3
fMX = 10 MHz, VDD = 3.0 V
Notes 2, 3
fMX = 5 MHz, VDD = 3.0 V
fMX = 5 MHz, VDD = 2.0 V
fIH = 20 MHz
fIH = 8 MHz
Notes 2, 3
Notes 2, 3
Note 4
Note 4
fIH = 1 MHz ,
RMC = 5AH, OSMC = 02H
MAX.
Unit
Square wave input
1.1
3.3
mA
Resonator connection
1.4
3.6
mA
Square wave input
1.1
3.3
mA
Resonator connection
1.4
3.6
mA
Square wave input
0.55
2.1
mA
Resonator connection
0.65
2.2
mA
Square wave input
0.55
2.1
mA
Resonator connection
0.65
2.2
mA
Square wave input
0.4
1.8
mA
Resonator connection
0.45
1.8
mA
Square wave input
0.26
1.3
mA
Resonator connection
0.31
1.4
mA
VDD = 5.0 V
1.3
3.6
mA
VDD = 3.0 V
1.3
3.6
mA
VDD = 5.0 V
0.45
1.8
mA
VDD = 3.0 V
0.45
1.8
mA
VDD = 3.0 V
45
153
μA
fSUB = 32.768 kHz,
TA = −40 to
VDD = 5.0 V
0.9
3.6
μA
RTCLPC = 1,
+50°C
VDD = 3.0 V
0.9
3.6
μA
VDD = 2.0 V
0.9
3.6
μA
TA = −40 to
VDD = 5.0 V
0.9
6.0
μA
+70°C
VDD = 3.0 V
0.9
6.0
μA
VDD = 2.0 V
0.9
6.0
μA
TA = −40 to
VDD = 5.0 V
0.9
8.8
μA
+85°C
VDD = 3.0 V
0.9
8.8
μA
VDD = 2.0 V
0.9
8.8
μA
SDIV = 1,
TYP.
Note 4
FSEL = 0,
AMPHS1 = 1
MIN.
1.8 V ≤ AVDD1 ≤ VDD,
Note 5
Notes 1. Total current flowing into VDD, EVDD, AVDD0, AVDD1, AVDD, EVDD1, and VLC0 to VLC3, including the input leakage
current flowing when the level of the input pin is fixed to VDD or VSS, and excluding the current flowing into the
Note 6
, operational amplifier Note 6, voltage
real-time counter, watchdog timer, LVI circuit, A/D converter, D/A converter
Note 6
, LCD controller/driver, I/O port, and on-chip pull-up/pull-down resistors. The maximum values
reference
include the peripheral operation current. During HALT instruction execution by flash memory.
2. When internal high-speed oscillator and subsystem clock are stopped.
3. When AMPH (bit 0 of clock operation mode control register (CMC)) = 0 and FLPC, FSEL (bits 1, 0 of operation
speed mode control register (OSMC)) = 0, 0.
4. When high-speed system clock and subsystem clock are stopped.
5. When internal high-speed oscillation, and high-speed system clock are stopped. When watchdog timer is
stopped. When real-time counter is operating.
6. Dedicated to μ PD78F150xA
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: Internal high-speed oscillation clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
R01UH0004EJ0501 Rev.5.01
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
DC Characteristics (10/11)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 1.8 V ≤ AVDD0 ≤ VDD,
1.8 V ≤ AVDD ≤ VDD, 1.8 V ≤ EVDD1 = VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Symbol
Note 1
Supply current
IDD3
RTC operating
IRTC
Notes 2, 3
Conditions
STOP mode
TYP.
MAX.
Unit
TA = −40 to +50°C
0.37
2.8
μA
TA = −40 to +70°C
0.37
5.2
μA
TA = −40 to +85°C
0.37
7.9
μA
VDD = 3.0 V
0.2
1
μA
VDD = 2.0 V
0.2
1
μA
0.31
0.35
μA
9
18
μA
AVDD0 = 5.0 V
1.7
3.4
mA
AVDD0 = 3.0 V
0.7
1.4
mA
Normal mode 2
AVDD0 = 2.3 V
0.5
1.2
mA
Low voltage mode
AVDD0 = 1.8 V
0.3
0.8
mA
Normal mode 1
AVDD = 5.0 V
1.7
3.4
mA
AVDD = 3.0 V
0.7
1.4
mA
Normal mode 2
AVDD = 2.3 V
0.5
1.2
mA
Low voltage mode
AVDD = 1.8 V
0.3
0.8
mA
0.3
0.8
mA
fSUB = 32.768 kHz
current
Watchdog timer
IWDT
Notes 3, 4
MIN.
1.8 V ≤ AVDD1 ≤ VDD,
fIL = 30 kHz
operating
current
LVI operating
ILVI
Note 5
current
A/D converter
IADC
Note 6
During conversion
operating
at maximum
current
speed
(μ PD78F150xA)
During conversion
Normal mode 1
at maximum
speed
(μ PD78F151xA)
50 pF per 1
Selecting Reference potential = AVDD1
operating
channel, ISOUCE =
Selecting Reference potential = VREFOUT
current
ISINK = 0 mA
D/A converter
Notes 1.
2.
3.
4.
5.
6.
7.
Note 7, 9
8.
9.
IDAC
Selecting Reference potential = AVREFP
0.3
0.3
Note 8
0.8
0.8
Note 8
mA
mA
Total current flowing into VDD, EVDD, AVDD0, AVDD1, AVDD, EVDD1, and VLC0 to VLC3, including the input
leakage current flowing when the level of the input pin is fixed to VDD or VSS, and excluding the current
flowing into the real-time counter, watchdog timer, LVI circuit, A/D converter, D/A converter, operational
amplifier, voltage reference, LCD controller/driver, I/O port, and on-chip pull-up/pull-down resistors. The
maximums values include the peripheral operation current and STOP leakage current. When subsystem
clock is stopped. When watchdog timer is stopped.
Current flowing only to the real-time counter (VDD pin) (excluding the operating current of the XT1 oscillator).
The current value of the 78K0R/Lx3 microcontrollers is the TYP. value, the sum of the TYP. values of either
IDD1 or IDD2, and IRTC, when the real-time counter operates in an operation mode or HALT mode. The IDD1
and IDD2 MAX. values also include the real-time counter operating current. When the real-time counter
operates during fCLK = fSUBC, the TYP. value of IDD2 includes the real-time counter operating current.
When internal high-speed oscillator and high-speed system clock are stopped.
Current flowing only to the watchdog timer (VDD pin) (including the operating current of the 30 kHz internal
oscillator). The current value of the 78K0R/Lx3 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT
when fCLK = fSUBC or when the watchdog timer operates in STOP mode.
Current flowing only to the LVI circuit (VDD pin). The current value of the 78K0R/Lx3 microcontrollers is the
sum of IDD1, IDD2 or IDD3 and ILVI when the LVI circuit operates in the operation mode, HALT mode or STOP
mode.
Current flowing only to the A/D converter (AVDD0 or (AVDD pin). The current value of the 78K0R/Lx3
microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode
or HALT mode.
Current flowing only to the D/A converter (AVDD1 pin). The current value of the 78K0R/Lx3 microcontrollers
is the sum of IDD1, IDD2 or IDD3 and IDAC when the D/A converter operates in an operation mode, HALT mode
or STOP mode.
Not including the current flowing to reference potential side.
Dedicated to μ PD78F150xA
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
894
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
DC Characteristics (11/11)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 1.8 V ≤ AVDD0 ≤ VDD,
1.8 V ≤ AVDD ≤ VDD, 1.8 V ≤ EVDD1 = VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Operational
Symbol
IAMP
Note 1, 6
amplifier
operating
current
Voltage
IVR1
Note 2, 6
reference
operating
current 1
Voltage
IVR2
Note 3, 6
reference
operating
current 2
Conditions
MIN.
1.8 V ≤ AVDD1 ≤ VDD,
TYP.
MAX.
Unit
AVDD0 = 5.0 V
OAIMI = 0
250
335
μA
AVDD0 = 3.0 V
OAIMI = 0
230
320
μA
AVDD0 = 2.3 V
OAIMI = 0
220
310
μA
19
38
μA
AVDD0 = 5.0 V
AVDD0 = 3.0 V
VR output = 2.5 V
9.5
25
μA
AVDD0 = 3.0 V
VR output = 2.0 V
9.5
25
μA
10
40
μA
VDD = 5.0 V
VDD = 3.0 V
VR output = 2.5 V
10
40
μA
VDD = 3.0 V
VR output = 2.0 V
10
40
μA
LCD operating
ILCD1
External
fLCD = fSUB,
VDD = 5.0 V
0.28
1.2
μA
current
Notes 4, 5
resistance
LCD panel not
VDD = 3.0 V
0.2
1.2
μA
VLCD = 01H
1.39
4.7
μA
VLCD = 0FH
0.94
3.1
μA
VLCD = 0AH
1.53
5.0
μA
division
method
ILCD2
Note4
connected,
LCD clock = 512 Hz
Internal
fLCD = fSUB,
voltage
LCD panel
boosting
method
not
1/3 bias
1/4 bias
connected,
LCD clock
= 512 Hz
ILCD3
Note4
Capacitor
fLCD = fSUB,
VDD = 5.0 V
0.56
2.0
μA
split method
LCD panel not
VDD = 3.0 V
0.36
1.7
μA
connected,
LCD clock = 512 Hz
Notes 1.
Current flowing only to the operational amplifier (AVDD0 pin).
The current value of the 78K0R/Lx3
microcontrollers is the sum of IDD1, IDD2 or IDD3 and IAMP when the operational amplifier operates in an operation
mode, HALT mode or STOP mode.
2.
Current flowing only to the voltage reference (AVDD0 pin). The current value of the 78K0R/Lx3 microcontrollers
is the sum of IDD1, IDD2 or IDD3 and IVR1 when the voltage reference circuit operates in an operation mode, HALT
mode or STOP mode.
3.
Current flowing only to the voltage reference or input gate voltage boost circuit for the A/D converter (VDD pin).
The current value of the 78K0R/Lx3 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IVR2 when the voltage
reference or boost circuit operates in an operation mode, HALT mode or STOP mode.
4.
Current flowing only to the LCD controller/driver (VDD pin).
The current value of the 78K0R/Lx3
microcontrollers is the sum of the LCD operating current (ILCD1, ILCD2 or ILCD3) to the supply current (IDD1, or
IDD2) when the LCD controller/driver operates in an operation mode or HALT mode.
5.
Not including the current that flows through the LCD divider resistor.
6.
Dedicated to μ PD78F150xA
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
895
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
AC Characteristics
(1) Basic operation (1/6)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 1.8 V ≤ AVDD0 ≤ VDD, 1.8 V ≤ AVDD1 ≤ VDD,
1.8 V ≤ AVDD ≤ VDD, 1.8 V ≤ EVDD1 = VDD, VSS = EVSS = AVSS = 0 V)
Items
Instruction cycle (minimum
Symbol
TCY
instruction execution time)
Conditions
MIN.
MAX.
Unit
0.05
8
μs
1.8 V ≤ VDD < 2.7 V
0.2
8
μs
Normal power 2.7 V ≤ VDD ≤ 5.5 V
0.1
8
μs
0.2
8
μs
1
8
μs
Main
Normal power 2.7 V ≤ VDD ≤ 5.5 V
system
mode,
TYP.
clock (fMAIN) FSEL = 1
operation
mode,
1.8 V ≤ VDD < 2.7 V
FSEL = 0
Low consumption power mode
Subsystem SDIV = 1
57.2
61
62.5
μs
clock (fSUB) SDIV = 0
operation
28.5
30.5
31.3
μs
0.05
1
μs
0.2
1
μs
1.15
μs
In the self
Normal power 2.7 V ≤ VDD ≤ 5.5 V
programmin mode,
g mode
1.8 V ≤ VDD < 2.7 V
FSEL = 1
Low consumption power mode
External main system clock
fEX
frequency
External main system clock input
tEXH, tEXL
high-level width, low-level width
Note
0.88
1
2.7 V ≤ VDD ≤ 5.5 V
2.0
20.0
MHz
1.8 V ≤ VDD < 2.7 V
2.0
5.0
MHz
2.7 V ≤ VDD ≤ 5.5 V
24
ns
1.8 V ≤ VDD < 2.7 V
96
ns
TI00 to TI07, TI10 to TI13 input
tTIH,
2/fMCK
ns
high-level width, low-level width
tTIL
+10
TO00 to TO07, TO10 to TO13
fTO
output frequency
PCLBUZ0, PCLBUZ1 output
fPCL
frequency
10
MHz
1.8 V ≤ VDD < 2.7 V
5
MHz
2.7 V ≤ VDD ≤ 5.5 V
10
MHz
1.8 V ≤ VDD < 2.7 V
5
MHz
1
μs
tKR
250
ns
tRSL
10
μs
Interrupt input high-level width,
tINTH,
low-level width
tINTL
Key return input low-level width
RESET low-level width
Note
2.7 V ≤ VDD ≤ 5.5 V
In low-power-consumption mode, use the regulator with fCLK fixed to 1 MHz when executing self programming.
Remarks 1. fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the TMRmn register. m: Unit number (m = 0, 1), n: Channel
number (n = 0 to 7))
2. For details on the normal power mode and low consumption power mode according to the regulator
output voltage, refer to CHAPTER 25 REGULATOR.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
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78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(1) Basic operation (2/6)
Minimum instruction execution time during main system clock operation (FSEL = 0, RMC = 00H)
10
8.0
4.0
Guaranteed range of
main system clock operation
(FSEL = 0, RMC = 00H)
Cycle time TCY [ μ s]
1.0
The range enclosed in dotted
lines applies when the internal
high-speed oscillation clock
(8MHz) is selected.
0.25
0.2
0.125
0.1
0.01
0
1.0
1.8
2.0 2.1
2.7
3.0
4.0
5.0
5.5
6.0
Supply voltage VDD [V]
Remark FSEL:
Bit 0 of the operation speed mode control register (OSMC)
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
897
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(1) Basic operation (3/6)
Minimum instruction execution time during main system clock operation (FSEL = 1, RMC = 00H)
10
8.0
Cycle time TCY [ μ s]
4.0
Guaranteed range of
main system clock operation
(FSEL = 1, RMC = 00H)
1.0
The range enclosed in dotted
lines applies when the internal
high-speed oscillation clock
(8MHz) is selected.
0.25
0.2
0.125
0.1
0.05
0.01
0
1.0
2.0
1.8
3.0
4.0
5.0
5.5
6.0
2.7
Supply voltage VDD [V]
Caution When VDD < 2.25 V and FSEL = 1, It is prohibited to release STOP mode during fEX operation or fIH
operation (This must not be performed even if the frequency is divided. The STOP mode may be
released during fX operation.).
Remarks 1.
2.
FSEL:
Bit 0 of the operation speed mode control register (OSMC)
f X:
X1 clock oscillation frequency
fIH:
Internal high-speed oscillation clock frequency
fEX:
External main system clock frequency
fMAIN:
Main system clock frequency
fSUB:
Subsystem clock frequency
fCLK:
CPU/peripheral hardware clock frequency
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
898
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(1) Basic operation (4/6)
Minimum instruction execution time during main system clock operation (FSEL = 0, RMC = 5AH)
10
8.0
Cycle time TCY [ μ s]
4.0
Guaranteed range of
main system clock operation
(FSEL = 0, RMC = 5AH)
The range enclosed in dotted lines applies
when the internal high-speed oscillation clock
(8MHz) is selected.
1.0
0.1
0.05
0.01
0
1.0
2.0
3.0
4.0
5.0
5.5
6.0
1.8
Supply voltage VDD [V]
Remarks 1.
2.
FSEL:
Bit 0 of the operation speed mode control register (OSMC)
The entire voltage range is 1 MHz (MAX.) when RMC is set to 5AH.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
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78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(1) Basic operation (5/6)
Minimum instruction execution time during self programming mode (RMC = 00H)
Cycle time TCY [ μ s]
2.0
1.0
Guaranteed range of self programming
mode (RMC = 00H)
The range enclosed in dotted lines applies
when the internal high-speed oscillation clock
(8MHz) is selected.
0.25
0.2
0.125
0.1
0.05
0.01
0
1.0
2.0
1.8
3.0
4.0
5.0
5.5
6.0
5.5
6.0
2.7
Supply voltage VDD [V]
Minimum instruction execution time during self programming mode (RMC = 5AH)
Cycle time TCY [ μ s]
2.0
1.0
Guaranteed range of self
programming mode (RMC = 5AH)
The dotted line indicates the
minimum instruction execution time
when the internal high-speed
oscillation clock (8MHz) is selected.
0.2
0.1
0.01
0
1.0
2.0
3.0
4.0
5.0
1.8
Supply voltage VDD [V]
Remark
The self programming function cannot be used when the CPU operates with the subsystem clock.
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(1) Basic operation (6/6)
AC Timing Test Points
VIH
VIH
Test points
VIL
VIL
External Main System Clock Timing
1/fEX
tEXL
tEXH
0.8VDD (MIN.)
EXCLK
0.2VDD (MAX.)
TI Timing
tTIL
tTIH
TI01 to TI07,
TI10 to TI13
Interrupt Request Input Timing
tINTH
tINTL
INTP0 to INTP11
Key Interrupt Input Timing
tKR
KR0 to KR7
RESET Input Timing
tRSL
RESET
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (1/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(a) During communication at same potential (UART mode) (dedicated baud rate generator output)
Parameter
Symbol
Conditions
MIN.
Transfer rate
fCLK = 20 MHz, fMCK = fCLK
TYP.
MAX.
Unit
fMCK/6
bps
3.3
Mbps
UART mode connection diagram (during communication at same potential)
Rx
TxDq
78K0R/Lx3
microcontrollers
User's device
Tx
RxDq
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Caution Select the normal input buffer for RxDq and the normal output mode for TxDq by using the PIMg and
POMx registers.
Remarks 1.
2.
q: UART number (q = 0 to 3), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2))
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (2/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(b) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
Parameter
Symbol
SCKp cycle time
tKCY1
Conditions
4.0 V ≤ VDD = EVDD ≤ 5.5 V
2.7 V ≤ VDD = EVDD < 4.0 V
1.8 V ≤ VDD = EVDD < 2.7 V
SCKp high-/low-level width
SIp setup time (to SCKp↑)
Note 2
SIp hold time (from SCKp↑)
Note 3
Delay time from SCKp↓ to
SOp output
Notes 1.
MIN.
TYP.
MAX.
Unit
200
Note 1
ns
300
Note 1
ns
600
Note 1
ns
tKH1,
4.0 V ≤ VDD = EVDD ≤ 5.5 V
tKCY1/2 − 20
ns
tKL1
2.7 V ≤ VDD = EVDD < 4.0 V
tKCY1/2 − 35
ns
1.8 V ≤ VDD = EVDD < 2.7 V
tKCY1/2 − 80
ns
4.0 V ≤ VDD = EVDD ≤ 5.5 V
70
ns
2.7 V ≤ VDD = EVDD < 4.0 V
100
ns
1.8 V ≤ VDD = EVDD < 2.7 V
190
ns
30
ns
tSIK1
tKSI1
tKSO1
Note 5
C = 30 pF
40
ns
Note 4
The value must also be 4/fCLK or more.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5.
C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for SIp and the normal output mode for SOp and SCKp by using the PIMg
and POMx registers.
Remarks 1.
2.
p: CSI number (p = 00, 01, 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (3/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(c) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
Parameter
SCKp cycle time
SCKp high-/low-level width
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
6/fMCK
ns
2.7 V ≤ VDD <
16 MHz < fMCK
8/fMCK
ns
4.0 V
fMCK ≤ 16 MHz
6/fMCK
ns
1.8 V ≤ VDD <
16 MHz < fMCK
8/fMCK
ns
2.7 V
fMCK ≤ 16 MHz
6/fMCK
ns
tKCY2/2
ns
tSIK2
80
ns
tKSI2
1/fMCK+50
ns
tKCY2
tKH2,
tKL2
SIp setup time
(to SCKp↑)
Note 1
SIp hold time
(from SCKp↑)
Note 2
Delay time from SCKp↓ to
SOp output
Notes 1.
tKSO2
Note 3
C = 30
Note 4
pF
4.0 V ≤ VDD = EVDD ≤ 5.5 V
2/fMCK+45
ns
2.7 V ≤ VDD = EVDD < 4.0 V
2/fMCK+57
ns
1.8 V ≤ VDD = EVDD < 2.7 V
2/fMCK+125
ns
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4.
C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for SIp and SCKp and the normal output mode for SOp by using the PIMg
and POMx registers.
Remarks 1.
2.
p: CSI number (p = 00, 01, 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register.
m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 2))
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (4/18)
CSI mode connection diagram (during communication at same potential)
SCK
SCKp
SIp
78K0R/Lx3
microcontrollers
SO
User's device
SI
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00, 01, 10, 20)
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (5/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
2
(d) During communication at same potential (simplified I C mode)
Parameter
SCLr clock frequency
Symbol
fSCL
Conditions
MIN.
2.7 V ≤ VDD = EVDD ≤ 5.5 V
MAX.
Unit
400
kHz
300
kHz
Rb = 3 kΩ, Cb = 100 pF
1.8 V ≤ VDD = EVDD ≤ 5.5 V
Rb = 5 kΩ, Cb = 100 pF
Hold time when SCLr = “L”
tLOW
2.7 V ≤ VDD = EVDD ≤ 5.5 V
1200
ns
1500
ns
1200
ns
1500
ns
1/fMCK+120
ns
1/fMCK+230
ns
Rb = 3 kΩ, Cb = 100 pF
1.8 V ≤ VDD = EVDD ≤ 5.5 V
Rb = 5 kΩ, Cb = 100 pF
Hold time when SCLr = “H”
tHIGH
2.7V ≤ VDD = EVDD ≤ 5.5 V
Rb = 3 kΩ, Cb = 100 pF
1.8 V ≤ VDD = EVDD ≤ 5.5 V
Rb = 5 kΩ, Cb = 100 pF
Data setup time (reception)
tSU:DAT
2.7V ≤ VDD = EVDD ≤ 5.5 V
Rb = 3 kΩ, Cb = 100 pF
1.8 V ≤ VDD = EVDD ≤ 5.5 V
Rb = 5 kΩ, Cb = 100 pF
Data hold time (transmission)
tHD:DAT
2.7V ≤ VDD = EVDD ≤ 5.5 V
0
660
ns
0
710
ns
Rb = 3 kΩ, Cb = 100 pF
1.8 V ≤ VDD = EVDD ≤ 5.5 V
Rb = 5 kΩ, Cb = 100 pF
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for SDAr and the
normal output mode for SCLr by using the PIMg and POMx registers.
Remarks 1.
Rb[Ω]:Communication line (SDAr) pull-up resistance,
Cb[F]: Communication line (SCLr, SDAr) load capacitance
2.
r: IIC number (r = 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2), mn = 02, 10)
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (6/18)
2
Simplified I C mode mode connection diagram (during communication at same potential)
VDD
Rb
SDA
SDAr
78K0R/Lx3
microcontrollers
User's device
SCL
SCLr
2
Simplified I C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD:DAT
Remarks 1.
tSU:DAT
Rb[Ω]:Communication line (SDAr) pull-up resistance,
Cb[F]: Communication line (SCLr, SDAr) load capacitance
2.
r: IIC number (r = 10, 20)
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (7/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(e) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (1/2)
Parameter
Transfer rate
Symbol
Conditions
reception
MIN.
TYP.
4.0 V ≤ VDD = EVDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
fCLK = 20 MHz,
MAX.
Unit
fMCK/6
bps
3.3
Mbps
fMCK/6
bps
3.3
Mbps
fMCK = fCLK
2.7 V ≤ VDD = EVDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V
fCLK = 20 MHz,
fMCK = fCLK
Caution
Select the TTL input buffer for RxDq and the N-ch open drain output (VDD tolerance) mode for TxDq by
using the PIMg and POMx registers.
Remarks 1. q: UART number (q = 0 to 3), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
2. Vb[V]: Communication line voltage
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register.
m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2))
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in UART mode.
4.0 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD = EVDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V: VIH = 2.0 V, VIL = 0.5 V
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (8/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(e) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (2/2)
Parameter
Transfer
Symbol
Conditions
transmission
rate
MIN.
TYP.
4.0 V ≤ VDD = EVDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
MAX.
Unit
Note 1
bps
2.8
fCLK = 16.8 MHz, fMCK = fCLK,
Note 2
Mbps
Cb = 50 pF, Rb = 1.4 kΩ, Vb =
2.7 V
2.7 V ≤ VDD = EVDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V
Note 3
1.2
fCLK = 19.2 MHz, fMCK = fCLK,
Note 4
bps
Mbps
Cb = 50 pF, Rb = 2.7 kΩ, Vb =
2.3 V
Notes 1.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ VDD = EVDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate =
2.2
Vb
{−Cb × Rb × ln (1−
1
Baud rate error (theoretical value) =
Transfer rate × 2
(
[bps]
)} × 3
−{
−Cb × Rb × ln (1 −
1
Transfer rate
2.2
Vb
)}
× 100 [%]
) ×Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
3.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD = EVDD < 4.0 V and 2.3 V ≤ Vb < 2.7 V
1
Maximum transfer rate =
2.0
Vb
{−Cb × Rb × ln (1−
1
Baud rate error (theoretical value) =
Transfer rate × 2
(
[bps]
)} × 3
−{
−Cb × Rb × ln (1 −
1
Transfer rate
2.0
Vb
)}
× 100 [%]
) ×Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for RxDq and the N-ch open drain output (VDD tolerance) mode for TxDq by
using the PIMg and POMx registers.
(Remarks are given on the next page.)
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (9/18)
Remarks 1.
Rb[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load
capacitance, Vb[V]: Communication line voltage
2.
q: UART number (q = 0 to 3) , g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2))
4. VOH and VoL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in UART mode.
4.0 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VOH = 2.2 V, VoL = 0.8 V
2.7 V ≤ VDD = EVDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V: VOH = 2.0 V, VoL = 0.5 V
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (10/18)
UART mode connection diagram (communication at different potential)
Vb
Rb
Rx
TxDq
78K0R/Lx3
microcontrollers
User's device
Tx
RxDq
UART mode bit width (communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Caution Select the TTL input buffer for RxDq and the N-ch open drain output (VDD tolerance) mode for TxDq by
using the PIMg and POMx registers.
Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage
2. q: UART number (q = 0 to 3) , g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (11/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(f)
Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(1/2)
Parameter
SCKp cycle time
Symbol
tKCY1
Conditions
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
MIN.
TYP.
MAX.
Unit
400
Note 1
ns
800
Note 1
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
SCKp high-level width
tKH1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
tKCY1/2 − 75
ns
tKCY1/2 −
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
SCKp low-level width
tKL1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
170
tKCY1/2 − 20
ns
tKCY1/2 − 35
ns
150
ns
275
ns
30
ns
30
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
SIp setup time
(to SCKp↑)
tSIK1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Note 2
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
SIp hold time
(from SCKp↑)
tKSI1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Note 2
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
Delay time from SCKp↓ to
SOp output
tKSO1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
120
ns
215
ns
Note 2
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
Notes 1. The value must also be 4/fCLK or more.
2. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1.
Caution Select the TTL input buffer for SIp and the N-ch open drain output (VDD tolerance) mode for SOp and
SCKp by using the PIMg and POMx registers.
Remarks 1. p: CSI number (p = 00, 01, 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
3. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance,
Cb[F]: Communication line (SIp, SOp, SCKp) load capacitance, Vb[V]: Communication line voltage
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD = EVDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V: VIH = 2.0 V, VIL = 0.5 V
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (12/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(f)
Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(2/2)
Parameter
Symbol
SIp setup time
(to SCKp↓)
tSIK1
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
70
ns
100
ns
30
ns
30
ns
Note
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD = EVDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
SIp hold time
(from SCKp↓)
4.0 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
tKSI1
Note
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD = EVDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
Delay time from
4.0 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
tKSO1
SCKp↑ to
40
ns
40
ns
Cb = 30 pF, Rb = 1.4 kΩ
SOp output
Note
2.7 V ≤ VDD = EVDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
Note
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
CSI mode connection diagram (communication at different potential)
Vb
Vb
Rb
SCKp
78K0R/Lx3 SIp
microcontrollers
SOp
Rb
SCK
SO
User's device
SI
Caution Select the TTL input buffer for SIp and the N-ch open drain output (VDD tolerance) mode for SOp and
SCKp by using the PIMg and POMx registers.
Remarks 1. p: CSI number (p = 00, 01, 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
3. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance,
Cb[F]: Communication line (SIp, SOp, SCKp) load capacitance, Vb[V]: Communication line voltage
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD = EVDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V: VIH = 2.0 V, VIL = 0.5 V
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (13/18)
CSI mode serial transfer timing (communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
CSI mode serial transfer timing (communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
Caution Select the TTL input buffer for SIp and the N-ch open drain output (VDD tolerance) mode for SOp and
SCKp by using the PIMg and POMx registers.
Remarks 1. p: CSI number (p = 00, 01, 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (14/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(g) Communication at different potential (2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
Parameter
SCKp cycle time
Symbol
tKCY2
SCKp high-/low-level
tKH2,
width
tKL2
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V,
13.6 MHz < fMCK
10/fMCK
ns
2.7 V ≤ Vb ≤ 4.0 V
6.8 MHz < fMCK ≤ 13.6 MHz
8/fMCK
ns
fMCK ≤ 6.8 MHz
6/fMCK
ns
2.7 V ≤ VDD < 4.0 V,
18.5 MHz < fMCK
16/fMCK
ns
2.3 V ≤ Vb ≤ 2.7 V
14.8 MHz < fMCK ≤ 18.5 MHz
14/fMCK
ns
11.1 MHz < fMCK ≤ 14.8 MHz
12/fMCK
ns
7.4 MHz < fMCK ≤ 11.1 MHz
10/fMCK
ns
3.7 MHz < fMCK ≤ 7.4 MHz
8/fMCK
ns
fMCK ≤ 3.7 MHz
6/fMCK
ns
fKCY2/2 −
ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
20
fKCY2/2 −
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
ns
35
SIp setup time
tSIK2
90
ns
tKSI2
1/fMCK + 50
ns
Note 1
(to SCKp↑)
SIp hold time
Note 2
(from SCKp↑)
Delay time from SCKp↓ to
SOp output
tKSO2
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
2/fMCK + 120
ns
2/fMCK + 230
ns
Note 3
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
Notes 1.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
CSI mode connection diagram (communication at different potential)
Vb
Rb
SCKp
78K0R/Lx3
SIp
microcontrollers
SOp
SCK
SO
User's device
SI
(Caution and Remark are given on the next page.)
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (15/18)
Caution
Select the TTL input buffer for SIp and SCKp and the N-ch open drain output (VDD tolerance) mode for
SOp by using the PIMg and POMx registers.
Remarks 1.
p: CSI number (p = 00, 01, 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
2.
Rb[Ω]:Communication line (SOp) pull-up resistance,
3.
fMCK: Serial array unit operation clock frequency
Cb[F]: Communication line (SOp, SCKp) load capacitance, Vb[V]: Communication line voltage
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 2))
4.
VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD = EVDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V: VIH = 2.0 V, VIL = 0.5 V
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (16/18)
CSI mode serial transfer timing (communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
Output data
SOp
CSI mode serial transfer timing (communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
SOp
Output data
Caution Select the TTL input buffer for SIp and SCKp and the N-ch open drain output (VDD tolerance) mode for
SOp by using the PIMg and POMx registers.
Remarks 1.
2.
p: CSI number (p = 00, 01, 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (17/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
2
(h) Communication at different potential (2.5 V, 3 V) (simplified I C mode)
Parameter
SCLr clock frequency
Symbol
fSCL
Conditions
MIN.
4.0 V ≤ VDD = EVDD ≤ 5.5 V,
MAX.
Unit
400
kHz
400
kHz
2.7 V ≤ Vb ≤ 4.0 V,
Rb = 1.4 kΩ, Cb = 100 pF
2.7 V ≤ VDD = EVDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Rb = 2.7 kΩ, Cb = 100 Pf
Hold time when SCLr = “L”
tLOW
4.0 V ≤ VDD = EVDD ≤ 5.5 V,
1275
ns
1275
ns
655
ns
655
ns
1/fMCK + 190
ns
1/fMCK + 190
ns
2.7 V ≤ Vb ≤ 4.0 V,
Rb = 1.4 kΩ, Cb = 100 pF
2.7 V ≤ VDD = EVDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Rb = 2.7 kΩ, Cb = 100 pF,
Hold time when SCLr = “H”
tHIGH
4.0 V ≤ VDD = EVDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Rb = 1.4 kΩ, Cb = 100 pF
2.7 V ≤ VDD = EVDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Rb = 2.7 kΩ, Cb = 100 pF
Data setup time (reception)
tSU:DAT
4.0 V ≤ VDD = EVDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Rb = 1.4 kΩ, Cb = 100 pF
2.7 V ≤ VDD = EVDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Rb = 2.7 kΩ, Cb = 100 pF
Data hold time (transmission)
tHD:DAT
4.0 V ≤ VDD = EVDD ≤ 5.5 V,
0
640
ns
0
660
ns
2.7 V ≤ Vb ≤ 4.0 V,
Rb = 1.4 kΩ, Cb = 100 pF
2.7 V ≤ VDD = EVDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V,
Rb = 2.7 kΩ, Cb = 100 pF
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for SDAr and the N-ch
open drain output (VDD tolerance) mode for SCLr by using the PIMg and POMx registers.
Remarks 1.
2.
3.
4.
Rb[Ω]:Communication line (SDAr, SCLr) pull-up resistance,
Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage
r: IIC number (r = 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2), mn = 02, 10)
VIH and VIL below are observation points for the AC characteristics of the serial array unit when
2
communicating at different potentials in simplified I C mode mode.
4.0 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD = EVDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V: VIH = 2.0 V, VIL = 0.5 V
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(2) Serial interface: Serial array unit (18/18)
2
Simplified I C mode connection diagram (communication at different potential)
Vb
Rb
Vb
Rb
SDA
SDAr
78K0R/Lx3
microcontrolles
User's device
SCL
SCLr
2
Simplified I C mode serial transfer timing (communication at different potential)
1/fSCL
tLOW
tHIGH
SCr
SDAr
tHD:DAT
tSU:DAT
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for SDAr and the N-ch
open drain output (VDD tolerance) mode for SCLr by using the PIMg and POMx registers.
Remarks 1.
2.
Rb[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Vb[V]: Communication line voltage
r: IIC number (r = 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(3) Serial interface: IICA
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(a) IICA
Parameter
Symbol
SCL0 clock frequency
fSCL
Conditions
Standard Mode
Fast mode: fCLK ≥3.5 MHz,
High-Speed Mode
MIN.
MAX.
MIN.
MAX.
0
100
0
400
Unit
kHz
Standard mode: fCLK ≥1 MHz
tSU:STA
4.7
0.6
μs
Hold time
tHD:STA
4.0
0.6
μs
Hold time when SCL0 = “L”
tLOW
4.7
1.3
μs
Hold time when SCL0 = “H”
tHIGH
4.0
0.6
μs
tSU:DAT
250
100
ns
Data hold time (transmission)
tHD:DAT
0
Setup time of stop condition
tSU:STO
4.0
0.6
μs
Bus-free time
tBUF
4.7
1.3
μs
Setup time of restart condition
Note 1
Data setup time (reception)
Note 2
Notes 1.
2.
Remark
3.45
0
0.9
μs
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
fCLK: CPU/peripheral hardware clock frequency
IICA serial transfer timing
tLOW
SCL0
tHD:DAT
tHD:STA
tHIGH
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDA0
tBUF
Stop
condition
Start
condition
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condition
Stop
condition
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(4) Serial interface: On-chip debug (UART)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(a) On-chip debug (UART)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
fCLK/6
bps
3.33
Mbps
2.7 V ≤ VDD = EVDD ≤ 5.5 V
10
MHz
1.8 V ≤ VDD = EVDD < 2.7 V
2.5
MHz
fCLK/2
Transfer rate
Flash memory programming mode
12
TYP.
(fCLK = 20 MHz, 2.7 V ≤ VDD = EVDD,
Cb = 50 pF)
TOOL1 output frequency
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
Analog Characteristics
(1) 12-bit A/D Converter (μ PD78F150xA)
(a) TA = 0 to 50°C, 1.8 V ≤ ADREFP ≤ AVDD0, 2.3 V ≤ AVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS = AVSS = ADREFM = 0 V
Parameter
Symbol
Resolution
Conditions
RES
Overall error
AINL
2.3 V ≤ ADREFP ≤ 3.6 V
Conversion time
tCONV
Normal mode 1, Normal mode 2
Note
MIN.
TYP.
MAX.
Unit
12
12
12
bit
±2.0
±6.0
LSB
±3.0
±6.0
LSB
5
50
μs
6.25
50
μs
1.8 V ≤ ADREFP < 2.3 V
Low voltage mode
Note
Zero-scale error
Full-scale error
Note
Note
Integral non-linearity error
Differential non-linearity error
Note
Reference voltage (high potential
EZS
±2.0
±4.0
LSB
EFS
±2.0
±4.0
LSB
ILE
±2.0
LSB
DLE
±1.0
LSB
1.8
AVDD0
V
ADREFM
ADREFP
V
200
μA
ADREFP
side)
Analog input voltage
VAIN
Reference supply current
IREF
46
(b) TA = −40 to +85°C , 1.8 V ≤ ADREFP ≤ AVDD0, 1.8 V ≤ AVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS = AVSS =
ADREFM = 0 V
Parameter
Symbol
Resolution
Conditions
MIN.
TYP.
MAX.
Unit
12
12
12
bit
3.6 V ≤ ADREFP ≤ 5.5 V
±2.0
±10.0
LSB
2.3 V ≤ ADREFP < 3.6 V
±2.0
±10.0
LSB
±3.0
RES
Note
Overall error
AINL
1.8 V ≤ ADREFP < 2.3 V
Conversion time
tCONV
Note
Zero-scale error
Full-scale error
Note
Note
Integral non-linearity error
Differential non-linearity error
Note
Reference voltage (high potential
±10.0
LSB
Normal mode 1, Normal mode 2
5
50
μs
Low voltage mode
21
50
μs
EZS
±2.0
±8.0
LSB
EFS
±2.0
±8.0
LSB
ILE
±6.0
LSB
DLE
±2.0
LSB
1.8
AVDD0
V
ADREFM
ADREFP
V
220
μA
ADREFP
side)
Analog input voltage
VAIN
Reference supply current
IREF
46
Note Excludes quantization error (±1/2 LSB).
Remarks 1. ADREFP is the input voltage from the AVREFP pin or the voltage generated by the voltage reference.
2. ADREFM is the input voltage from the AVREFM pin or the grand potential of A/D converter.
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(2) 10-bit A/D Converter (μ PD78F151xA)
(a) TA = 40 to +85°C, 1.8 V ≤ ADREF ≤ AVDD ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS = AVSS = 0 V
Parameter
Symbol
Resolution
Conditions
RES
Note
Overall error
AINL
Conversion time
tCONV
Note
Zero-scale error
Full-scale error
Note
Note
Integral non-linearity error
Differential non-linearity error
Note
Analog input voltage
MIN.
TYP.
MAX.
Unit
10
10
10
bit
±0.4
%FSR
Normal mode 1, Normal mode 2
5
50
μs
Low voltage mode
21
50
μs
EZS
±0.4
%FSR
EFS
±0.4
%FSR
ILE
±2.5
LSB
DLE
±1.5
LSB
ADREF
V
MAX.
Unit
AVDD0
V
VAIN
AVss
Note Excludes quantization error (±1/2 LSB).
(3) Operational amplifier (μ PD78F150xA)
(TA = −40 to +85°C, 2.3 V ≤ AVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS =AVSS = 0 V)
Parameter
Common-mode input voltage
Symbol
VIAMP
Conditions
AVDD0 = 3.0 V
MIN.
TYP.
0
−0.6
Input offset voltage
VIOAMP
Maximum output voltage
VOHAMP
±10
AVDD0 = 3.0 V/2.3 V, ISOURCE = −500 μA
AVDD0
mV
V
−0.2
(high level)
Maximum output voltage
VOLAMP
AVDD0 = 3.0 V/2.3 V, ISOURCE = 500 μA
0.1
V
(low level)
Open-loop gain
AVDD0 = 3.0 V
100
dB
GBW
GBW
AVDD0 = 3.0 V
3
MHz
Input noise spectral density
VNAMP
AVDD0 = 3.0 V, VIN = AVDD0/2
60
nV /
Hz
Slew rate
SRAMP
Turn on time
tONAMP
AVDD0 = 3.0 V
V/μs
2
20
μs
(4) Voltage Reference (μ PD78F150xA)
(TA = −40 to +85°C, 2.3 V ≤ AVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS =AVSS = 0 V)
Parameter
Output reference voltage
Symbol
VREFOUT
Conditions
VRGV = 0, 2.7 V ≤ AVDD0 ≤ 5.5 V,
MIN.
TYP.
MAX.
Unit
2.45
2.5
2.55
V
1.96
2
2.04
V
TA = 25°C
VRGV = 1, 2.3 V ≤ AVDD0 ≤ 5.5 V,
TA = 25°C
Temperature coefficient
Settling time
40
ppm/°C
17
ms
Caution Connect the VREFOUT pin to GND via a tantalum capacitor (capacitance: 10 μF±30 %, ESR: 2 Ω (max.),
ESL: 10 nH (max.)) and a ceramic capacitor (capacitance: 0.1 μF±30 %, ESR: 2 Ω (max.), ESL: 10 nH
(max.)).
Remark The settling time of the VR circuit is the time required until the reference voltage output voltage reaches the
values above.
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CHAPTER 31 ELECTRICAL SPECIFICATIONS
(5) D/A Converter (μ PD78F150xA)
(a) TA = 0 to 50°C, 1.8 V ≤ DAREFP ≤ AVDD1, 2.3 V ≤ AVDD1 = VDD ≤ 3.6 V, VSS = EVSS = AVSS = 0 V
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
12
12
12
bit
18
μs
Resolution
RES
Settling time
tSET
Off-set error
EO
±5
±10
mV
Gain error
EG
±5
±10
mV
Integral non-linearity error
ILE
ISOURCE = ISINK = 0 mA,
±2.0
±4.0
LSB
Differential non-linearity error
DLE
0.1 V ≤ ANOn ≤ AVDD1−0.1 V (n = 0, 1)
±2.0
LSB
D/A output resistance value
RO
0 V ≤ ANOn ≤ 0.3 V or
150
250
Ω
5
10
Ω
0.1
mA
0.1
mA
AVDD1−0.3 V ≤ ANOn ≤ AVDD1 (n = 0, 1)
0.3 V ≤ ANOn ≤ AVDD1−0.3 V (n = 0, 1)
Output source current
ISOURCE
Output sink current
ISINK
0.3 V ≤ ANOn ≤ AVDD1−0.3 V (n = 0, 1)
(b) TA = −40 to +85°C, 1.8 V ≤ DAREFP ≤ AVDD1, 2.3 V ≤ AVDD1 = VDD ≤ 5.5 V, VSS = EVSS = AVSS = 0 V
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
12
12
12
bit
18
μs
Resolution
RES
Settling time
tSET
Off-set error
EO
±5
±20
mV
Gain error
EG
±5
±20
mV
Integral non-linearity error
ILE
ISOURCE = ISINK = 0 mA,
±6.0
±12.0
LSB
Differential non-linearity error
DLE
0.1 V ≤ ANOn ≤ AVDD1−0.1 V (n = 0, 1)
±8.0
LSB
D/A output resistance value
RO
0 V ≤ ANOn ≤ 0.3 V or
150
250
Ω
5
20
Ω
0.1
mA
0.1
mA
AVDD1−0.3 V ≤ ANOn ≤ AVDD1 (n = 0, 1)
0.3 V ≤ ANOn ≤ AVDD1−0.3 V (n = 0, 1)
Output source current
ISOURCE
Output sink current
ISINK
0.3 V ≤ ANOn ≤ AVDD1−0.3 V (n = 0, 1)
Remarks 1. Use the D/A converter under the condition of the Output load capacitance (C) = 50 pF (max.).
2. DAREFP is the input voltage from the AVREFP pin, the voltage generated by the voltage reference, or the
input voltage from the AVDD1 pin. It is selected as the positive reference voltage of the D/A converter.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
924
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
LCD Characteristics (1/4)
(1) Resistance division method
(a) Static display mode (TA = −40 to +85°C, VLCD (MIN.) ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VLCD
MIN.
TYP.
2.0
MAX.
Unit
VDD
V
LCD output resistor
(Common)
Note
RODC
IO = ±5 μA
40
kΩ
LCD output resistor
(Segment)
Note
ROCS
IO = ±1 μA
200
kΩ
(b) 1/2 bias method, 1/4 bias method (TA = −40 to +85°C, VLCD (MIN.) ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VLCD
MIN.
TYP.
2.7
MAX.
Unit
VDD
V
LCD output resistor
(Common)
Note
RODC
IO = ±5 μA
40
kΩ
LCD output resistor
(Segment)
Note
ROCS
IO = ±1 μA
200
kΩ
MAX.
Unit
VDD
V
(c) 1/3 bias method (TA = −40 to +85°C, VLCD (MIN.) ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VLCD
MIN.
2.5
TYP.
LCD output resistor
(Common)
Note
RODC
IO = ±5 μA
40
kΩ
LCD output resistor
(Segment)
Note
ROCS
IO = ±1 μA
200
kΩ
Note
The output resistor is a resistor connected between one of the VLC0, VLC1, VLC2, VLC3 and VSS pins, and either of the
SEG and COM pins.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
925
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
LCD Characteristics (2/4)
(2) Internal voltage boosting method (1/2)
(a) 1/3 bias method (TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
LCD output voltage variation range
VLCD2
Conditions
Note 1
C1 to C4
Note 2
= 0.47 μF
Doubler output voltage
VLCD1
C1 to C4
Note 1
Tripler output voltage
VLCD0
C1 to C4
Note 1
Reference voltage setup time
Voltage boost wait time
Note 2
Note 3
tVAWAIT2
tVAWAIT1
VDD > VLC0
MIN.
TYP.
MAX.
Unit
VLCD = 00H
1.67
1.75
1.83
V
VLCD = 01H
1.62
1.70
1.78
V
VLCD = 02H
1.57
1.65
1.73
V
VLCD = 03H
1.52
1.60
1.68
V
VLCD = 04H
1.47
1.55
1.63
V
VLCD = 05H
1.42
1.50
1.58
V
VLCD = 06H
1.37
1.45
1.53
V
VLCD = 07H
1.32
1.40
1.48
V
VLCD = 08H
1.27
1.35
1.43
V
VLCD = 09H
1.22
1.30
1.375
V
VLCD = 0AH
1.17
1.25
1.33
V
VLCD = 0BH
1.12
1.20
1.28
V
VLCD = 0CH
1.07
1.15
1.23
V
VLCD = 0DH
1.02
1.10
1.18
V
VLCD = 0EH
0.97
1.05
1.13
V
VLCD = 0FH
0.92
1.00
1.08
V
VLCD = 10H
0.87
0.95
1.03
V
VLCD = 11H
0.82
0.90
0.98
V
VLCD = 12H
0.77
0.85
0.93
V
VLCD = 13H
0.72
0.80
0.88
V
= 0.47 μF
2 VLCD2
−0.1
2 VLCD2
2 VLCD2
V
= 0.47 μF
3 VLCD2
−0.15
3 VLCD2
3 VLCD2
V
2
ms
500
ms
5
s
LCD output resistor
Note 4
(Common)
RODC
IO = ±5 μA
40
kΩ
LCD output resistor
Note 4
(Segment)
ROCS
IO = ±1 μA
200
kΩ
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VLC0 and GND
C3: A capacitor connected between VLC1 and GND
C4: A capacitor connected between VLC2 and GND
C1 = C2 = C3 = C4 = 0.47 pF±30 %
2. This is the required wait time from when the reference voltage is specified by using the LVCD register (or the
register is reset to use the default value of the reference voltage) until voltage boosting is started (VLCON = 1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
4. The output resistor is a resistor connected between one of the VLC0, VLC1, VLC2 and VSS pins, and either of the
SEG and COM pins.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
926
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
LCD Characteristics (3/4)
(2) Internal voltage boosting method (2/2)
(b) 1/4 bias method (TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
LCD output voltage variation range
VLCD3
Conditions
Note 1
C1 to C5
Note 2
= 0.47 μF
MIN.
TYP.
MAX.
Unit
Note 5
1.67
1.75
1.83
V
Note 5
1.62
1.70
1.78
V
Note 5
1.57
1.65
1.73
V
Note 5
1.52
1.60
1.68
V
Note 5
1.47
1.55
1.63
V
Note 5
1.42
1.50
1.58
V
Note 5
1.37
1.45
1.53
V
Note 5
1.32
1.40
1.48
V
VLCD = 08H
Note 5
1.27
1.35
1.43
V
VLCD = 09H
1.22
1.30
1.375
V
VLCD = 0AH
1.17
1.25
1.33
V
VLCD = 0BH
1.12
1.20
1.28
V
VLCD = 0CH
1.07
1.15
1.23
V
VLCD = 0DH
1.02
1.10
1.18
V
VLCD = 0EH
0.97
1.05
1.13
V
VLCD = 0FH
0.92
1.00
1.08
V
VLCD = 10H
0.87
0.95
1.03
V
VLCD = 11H
0.82
0.90
0.98
V
VLCD = 12H
0.77
0.85
0.93
V
VLCD = 00H
VLCD = 01H
VLCD = 02H
VLCD = 03H
VLCD = 04H
VLCD = 05H
VLCD = 06H
VLCD = 07H
VLCD = 13H
Doubler output voltage
VLCD2
Tripler output voltage
VLCD1
Quadruply output voltage
Reference voltage setup time
Voltage boost wait time
VLCD0
Note 2
Note 3
0.72
0.80
0.88
V
C1 to C5
Note 1
= 0.47 μF
2 VLCD3−0.08
2 VLCD3
2 VLCD3
V
C1 to C5
Note 1
= 0.47 μF
3 VLCD3−0.12
3 VLCD3
3 VLCD3
V
C1 to C5
Note 1
= 0.47 μF
4 VLCD3−0.16
4 VLCD3
4 VLCD3
V
tVAWAIT2
2
ms
tVAWAIT1
500
ms
5
s
VDD > VLC0
LCD output resistor
Note 4
(Common)
RODC
IO = ±5 μA
40
kΩ
LCD output resistor
Note 4
(Segment)
ROCS
IO = ±1 μA
200
kΩ
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VLC0 and GND
C3: A capacitor connected between VLC1 and GND
C4: A capacitor connected between VLC2 and GND
C5: A capacitor connected between VLC3 and GND
C1 = C2 = C3 = C4 = C5 = 0.47 pF±30 %
2. This is the required wait time from when the reference voltage is specified by using the LVCD register (or the
register is reset to use the default value of the reference voltage) until voltage boosting is started (VLCON = 1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
4. The output resistor is a resistor connected between one of the VLC0, VLC1, VLC2, VLC3 and VSS pins, and either of
the SEG and COM pins.
5. These settings are prohibited because VLC0 > 5.5 V.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
927
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
LCD Characteristics (4/4)
(3) Capacitor split method
• 1/3 bias method (TA = −40 to +85°C, 2.2 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VLC0 voltage
VLC0
C1 to C4 = 0.47 μ F
VLC1 voltage
VLC1
C1 to C4 = 0.47 μ F
2/3 VLC0
−0.1
2/3 VLC0
2/3 VLC0
+0.1
V
VLC2 voltage
VLC2
C1 to C4 = 0.47 μ F
1/3 VLC0
−0.1
1/3 VLC0
1/3 VLC0
+0.1
V
Capacitor split wait time
Note 1
Note 3
Note 3
Note 3
tVAWAIT
VDD
V
100
ms
LCD output resistor
(Common)
Note 2
RODC
IO = ±5 μA
40
kΩ
LCD output resistor
(Segment)
Note 2
ROCS
IO = ±1 μA
200
kΩ
Notes 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).
2. The output resistor is a resistor connected between one of the VLC0, VLC1, VLC2 and VSS pins, and either of the
SEG and COM pins.
3. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VLC0 and GND
C3: A capacitor connected between VLC1 and GND
C4: A capacitor connected between VLC2 and GND
C1 = C2 = C3 = C4 = 0.47 pF±30 %
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
928
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
POC Circuit Characteristics (TA = −40 to +85°C, VSS = 0 V)
Parameter
Symbol
Detection voltage
Power supply voltage rise
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
1.52
1.61
1.70
V
VPDR
1.5
1.59
1.68
V
tPTH
Change inclination of VDD: 0 V → VPOR
0.5
V/ms
tPW
When the voltage drops
200
μs
inclination
Minimum pulse width
Detection delay time
μs
200
POC Circuit Timing
Supply voltage
(VDD)
Detection voltage VPOR (MAX.)
Detection voltage VPOR (TYP.)
Detection voltage VPOR (MIN.)
Detection voltage VPDR (MAX.)
Detection voltage VPDR (TYP.)
Detection voltage VPDR (MIN.)
tPTH
tPW
Time
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
929
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
Supply Voltage Rise Time (TA = −40 to +85°C, VSS = 0 V)
Parameter
Maximum time to rise to
1.8 V (VDD (MIN.))
Symbol
tPUP1
Note
1.8 V (VDD (MIN.))
Note
(releasing RESET input → VDD: 1.8 V)
Note
MIN.
LVI default start function stopped
TYP.
MAX.
Unit
3.6
ms
1.88
ms
is set (LVIOFF (Option Byte) = 1),
(VDD: 0 V → 1.8 V)
Maximum time to rise to
Conditions
when RESET input is not used
tPUP2
LVI default start function stopped
is set (LVIOFF (Option Byte) = 1),
when RESET input is used
Make sure to raise the power supply in a shorter time than this.
Supply Voltage Rise Time Timing
• When RESET pin input is not used
• When RESET pin input is used (when external reset is
released by the RESET pin, after POC has been
released)
Supply voltage
(VDD)
Supply voltage
(VDD)
1.8 V
1.8 V
0V
Time
POC internal
signal
0V
Time
POC internal
signal
tPUP1
RESET pin
tPUP2
Internal reset
signal
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
930
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
LVI Circuit Characteristics (TA = −40 to +85°C, VPDR ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Detection
Symbol
Supply voltage level
voltage
External input pin
Note 1
Power supply voltage
MIN.
TYP.
MAX.
Unit
VLVI0
4.12
4.22
4.32
V
VLVI1
3.97
4.07
4.17
V
VLVI2
3.82
3.92
4.02
V
VLVI3
3.66
3.76
3.86
V
VLVI4
3.51
3.61
3.71
V
VLVI5
3.35
3.45
3.55
V
VLVI6
3.20
3.30
3.40
V
VLVI7
3.05
3.15
3.25
V
VLVI8
2.89
2.99
3.09
V
VLVI9
2.74
2.84
2.94
V
VLVI10
2.58
2.68
2.78
V
VLVI11
2.43
2.53
2.63
V
VLVI12
2.28
2.38
2.48
V
VLVI13
2.12
2.22
2.32
V
VLVI14
1.97
2.07
2.17
V
VLVI15
1.81
1.91
2.01
V
VEXLVI
EXLVI < VDD, 1.8 V ≤ VDD ≤ 5.5 V
1.11
1.21
1.31
V
VPUPLVI
When LVI default start function enabled
1.87
2.07
2.27
V
is set
on power application
Minimum pulse width
Conditions
tLW
Detection delay time
Operation stabilization wait time
Note 2
μs
200
tLWAIT
200
μs
10
μs
Notes 1. The EXLVI/P120/INTP0 pin is used.
2. Time required from setting bit 7 (LVION) of the low-voltage detection register (LVIM) to 1 to operation
stabilization
Remark
VLVI (n − 1) > VLVIn: n = 1 to 15
LVI Circuit Timing
Supply voltage
(VDD)
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
tLW
tLWAIT
LVION ← 1
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
Time
931
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)
Parameter
Data retention supply voltage
Symbol
Conditions
VDDDR
MIN.
1.5
Note
TYP.
MAX.
Unit
5.5
V
Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC reset
is effected, but data is not retained when a POC reset is effected.
STOP mode
Operation mode
Data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
932
78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
Flash Memory Programming Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
VDD supply current
IDD
Typ. = 10 MHz, Max. = 20 MHz
Number of rewrites per chip
Cerwr
1 erase +
When a flash
Retention:
1 write
memory
15 years
after
programmer is
erase =
used, and the
1 rewrite
libraries provided
Note
by Renesas
TYP.
MAX.
Unit
6
20
mA
1000
Times
10000
Times
Electronics are
used
When the
Retention
EEPROM
:5 years
emulation libraries
provided by
Renesas
Electronics are
used
Note When a product is first written after shipment, “erase → write” and “write only” are both taken as one rewrite.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
933
78K0R/Lx3
CHAPTER 32 PACKAGE DRAWINGS
CHAPTER 32 PACKAGE DRAWINGS
32.1 78K0R/LF3
• μ PD78F1500AGC-GAD-AX, 78F1501AGC-GAD-AX, 78F1502AGC-GAD-AX,
78F1510AGC-GAD-AX, 78F1512AGC-GAD-AX
80-PIN PLASTIC LQFP (14x14)
HD
D
detail of lead end
60
61
A3
41
40
c
θ
E
L
Lp
HE
L1
(UNIT:mm)
80
1
21
20
ZE
e
ZD
b
x
M
S
A
ITEM
D
DIMENSIONS
14.00±0.20
E
14.00±0.20
HD
17.20±0.20
HE
17.20±0.20
A
1.70 MAX.
A1
0.125±0.075
A2
1.40±0.05
A3
0.25
b
A2
c
S
y
S
NOTE
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
A1
L
+0.08
0.30 −0.04
0.125 +0.075
−0.025
0.80
Lp
0.886±0.15
L1
θ
1.60±0.20
3° +5°
−3°
e
0.65
x
0.13
y
0.10
ZD
ZE
0.825
0.825
P80GC-65-GAD
934
78K0R/Lx3
CHAPTER 32 PACKAGE DRAWINGS
• μ PD78F1500AGK-GAK-AX, 78F1501AGK-GAK-AX, 78F1502AGK-GAK-AX,
78F1510AGK-GAK-AX, 78F1512AGK-GAK-AX
80-PIN PLASTIC LQFP (FINE PITCH) (12x12)
HD
detail of lead end
D
60
A3
41
c
61
40
θ
L
Lp
E
L1
HE
(UNIT:mm)
21
80
1
20
ZE
e
ZD
b
x
M
S
A
A2
S
y
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
A1
ITEM
D
DIMENSIONS
12.00±0.20
E
12.00±0.20
HD
14.00±0.20
HE
14.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
0.25
b
+0.07
0.20 −0.03
c
0.125 +0.075
−0.025
L
0.50
Lp
0.60±0.15
L1
θ
1.00±0.20
3° +5°
−3°
e
0.50
x
0.08
y
0.08
ZD
1.25
ZE
1.25
P80GK-50-GAK
935
78K0R/Lx3
CHAPTER 32 PACKAGE DRAWINGS
32.2 78K0R/LG3
• μ PD78F1503AGC-UEU-AX, 78F1504AGC-UEU-AX, 78F1505AGC-UEU-AX,
78F1513AGC-UEU-AX, 78F1515AGC-UEU-AX
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
HD
detail of lead end
D
L1
75
76
51
50
A3
c
θ
E
L
HE
Lp
(UNIT:mm)
26
25
100
1
ZE
e
b
ZD
x
M
S
A
A2
S
y
S
A1
ITEM
D
DIMENSIONS
14.00±0.20
E
14.00±0.20
HD
16.00±0.20
HE
16.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40± 0.05
A3
0.25
b
0.20 + 0.07
0.03
c
0.125 + 0.075
0.025
L
0.50
Lp
0.60±0.15
L1
e
1.00±0.20
3° + 5°
3°
0.50
x
0.08
y
0.08
ZD
1.00
θ
ZE
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
1.00
P100GC-50-UEU-1
936
78K0R/Lx3
CHAPTER 32 PACKAGE DRAWINGS
32.3 78K0R/LH3
• μ PD78F1506AGF-GAT-AX, 78F1507AGF-GAT-AX, 78F1508AGF-GAT-AX,
78F1516AGF-GAT-AX, 78F1518AGF-GAT-AX
128-PIN PLASTIC LQFP (FINE PITCH) (14x20)
HD
D
detail of lead end
102
103
65
64
A3
c
E
HE
θ
L
Lp
128
1
L1
39
38
ZE
ZD
b
x
M
S
(UNIT:mm)
e
A
A2
S
y
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
A1
ITEM
D
DIMENSIONS
20.00±0.20
E
14.00±0.20
HD
22.00±0.20
HE
16.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
0.25
b
0.20 +0.07
−0.03
c
0.125 +0.075
−0.025
L
0.50
Lp
0.60±0.15
L1
e
1.00±0.20
3° +5°
−3°
0.50
x
0.08
y
0.08
ZD
0.75
θ
ZE
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
0.75
P128GF-50-GAT
937
78K0R/Lx3
CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS
CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, please contact a Renesas Electronics
sales representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.renesas.com/prod/package/manual/index.html)
Table 33-1. Surface Mounting Type Soldering Conditions (1/2)
(1) 80-pin plastic LQFP (fine pitch) (12×12)
μ PD78F1500AGK-GAK-AX, 78F1501AGK-GAK-AX, 78F1502AGK-GAK-AX,
78F1510AGK-GAK-AX, 78F1512AGK-GAK-AX
100-pin plastic LQFP (fine pitch) (14x14)
μ PD78F1503AGC-UEU-AX, 78F1504AGC-UEU-AX, 78F1505AGC-UEU-AX,
78F1513AGC-UEU-AX, 78F1515AGC-UEU-AX
128-pin plastic LQFP (fine pitch) (14x20)
μ PD78F1506AGF-GAT-AX, 78F1507AGF-GAT-AX, 78F1508AGF-GAT-AX,
78F1516AGF-GAT-AX, 78F1518AGF-GAT-AX
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),
Note
Count: 3 times or less, Exposure limit: 7 days
10 to 72 hours)
Partial heating
Note
Recommended
Condition Symbol
IR60-107-3
(after that, prebake at 125°C for
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
−
After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution
The 78K0R/Lx3 microcontroller has an on-chip debug function, which is provided for development and
evaluation.
Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
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CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS
Table 33-1. Surface Mounting Type Soldering Conditions (2/2)
(2) 80-pin plastic LQFP (14×14)
μ PD78F1500AGC-GAD-AX, 78F1501AGC-GAD-AX, 78F1502AGC-GAD-AX,
78F1510AGC-GAD-AX, 78F1512AGC-GAD-AX
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),
Note
Count: 3 times or less, Exposure limit: 7 days
10 to 72 hours)
Wave soldering
IR60-107-3
(after that, prebake at 125°C for
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
WS60-107-1
Preheating temperature: 120°C max. (package surface temperature),
Note
Exposure limit: 7 days (after that, prebake at 125°C for 10 to 72 hours)
Partial heating
Note
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
−
After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution
The 78K0R/Lx3 microcontroller has an on-chip debug function, which is provided for development and
evaluation.
Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
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APPENDIX A DEVELOPMENT TOOLS
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems that employ the 78K0R/Lx3
microcontrollers.
Figure A-1 shows the development tool configuration.
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APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tool Configuration (1/2)
(1) When using the in-circuit emulator QB-78K0RLX3
Software package
• Software package
Debugging software
Language processing software
• Assembler package
• Integrated debuggerNote 3
• C compiler package
• System simulatorNote 4
• Device fileNote 1
Control software
• Project manager
(Windows only)Note 2
Host machine
(PC or EWS)
USB interface cableNote 3
Power supply unit
QB-78K0RLX3Note 3
Flash memory
programmerNote 3
Off-board
programming
Emulation probe
On-board
programming
Conversion adapter
Flash memory
write adapter
78K0R/Lx3
microcontrollers
Target connector
Target system
Notes 1.
Download the device file for 78K0R/Lx3 microcontrollers (DF781508) from the download site for
development tools (http://www2.renesas.com/micro/en/ods/index.html).
2.
The project manager PM+ is included in the assembler package.
The PM+ is only used for WindowsTM.
3.
In-circuit emulator QB-78K0RLX3 is supplied with integrated debugger ID78K0R-QB, on-chip debug
emulator with programming function QB-MINI2, and USB interface cable. Any other products are sold
separately.
4.
SM+ for 78K0R (instruction simulation version) is included in the software package. SM+ for 78K0R/Lx3
(instruction + peripheral simulation version)Note 5 is not included.
5.
Under development
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Figure A-1. Development Tool Configuration (2/2)
(2) When using the on-chip debug emulator with programming function QB-MINI2
Software package
• Software package
Debugging software
Language processing software
• Assembler package
• Integrated debuggerNote 1
• C compiler package
• System simulatorNote 4
• Device fileNote1
Control software
• Project manager
(Windows only)Note 2
Host machine
(PC or EWS)
USB interface cableNote 3
QB-MINI2Note 3
Connection cable
(16-pin cable)Note 3
Target connector
Target system
Notes 1.
2.
3.
4.
5.
Download the device file for 78K0R/Lx3 microcontrollers (DF781508) and the integrated debugger
ID78K0R-QB from the download site for development tools
(http://www2.renesas.com/micro/en/ods/index.html).
The project manager PM+ is included in the assembler package.
The PM+ is only used for Windows.
On-chip debug emulator QB-MINI2 is supplied with USB interface cable, connection cables (10-pin cable
and 16-pin cable), and 78K0-OCD board. Any other products are sold separately. In addition, download
the software for operating the QB-MINI2 from the download site for MINICUBE2
(http://www2.renesas.com/micro/en/development/asia/minicube2/minicube2.html).
SM+ for 78K0R (instruction simulation version) is included in the software package. SM+ for 78K0R/Lx3
Note 5
is not included.
(instruction + peripheral simulation version)
Under development
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APPENDIX A DEVELOPMENT TOOLS
A.1 Software Package
SP78K0R
Development tools (software) common to the 78K0R microcontrollers are combined in
78K0R microcontroller software
this package.
package
A.2 Language Processing Software
RA78K0R
This assembler converts programs written in mnemonics into object codes executable
Assembler package
with a microcontroller.
This assembler is also provided with functions capable of automatically creating symbol
tables and branch instruction optimization.
This assembler should be used in combination with a device file (DF781508).
This assembler package is a DOS-based application. It can also be used in Windows,
however, by using the Project Manager (included in assembler package) on Windows.
CC78K0R
This compiler converts programs written in C language into object codes executable with
C compiler package
a microcontroller.
This compiler should be used in combination with an assembler package and device file.
This C compiler package is a DOS-based application. It can also be used in Windows,
however, by using the Project Manager (included in assembler package) on Windows.
Note
DF781508
This file contains information peculiar to the device.
Device file
This device file should be used in combination with a tool (RA78K0R, CC78K0R,
ID78K0R-QB, and system simulator (SM+ for 78K0R and SM+ for 78K0R/Lx3)).
The corresponding OS and host machine differ depending on the tool to be used.
Note The DF781508 can be used in common with the RA78K0R, CC78K0R, ID78K0R-QB, and system simulator.
Download the DF781508 from the download site for development tools
(http://www2.renesas.com/micro/en/ods/).
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A.3 Flash Memory Programming Tools
A.3.1 When using flash memory programmer PG-FP5 and FL-PR5
PG-FP5, FL-PR5
Flash memory programmer dedicated to microcontrollers with on-chip flash memory.
Flash memory programmer
FA-78F1502GC-GAD-RX,
Flash memory programming adapter used connected to the flash memory programmer
FA-78F1502GK-GAK-RX,
for use.
FA-78F1505GC-UEU-RX,
FA-78F1508GF-GAT-RX
Flash memory programming adapter
Remarks 1. FL-PR5, FA-78F1502GC-GAD-RX, FA-78F1502GK-GAK-RX, FA-78F1505GC-UEU-RX, and FA78F1508GF-GAT-RX are products of Naito Densei Machida Mfg. Co., Ltd.
TEL: +81-42-750-4172 Naito Densei Machida Mfg. Co., Ltd.
2. Use the latest version of the flash memory programming adapter.
A.3.2 When using on-chip debug emulator with programming function QB-MINI2
QB-MINI2
This is a flash memory programmer dedicated to microcontrollers with on-chip flash
On-chip debug emulator with
memory. It is available also as on-chip debug emulator which serves to debug hardware
programming function
and software when developing application systems using the 78K0R/Lx3
microcontrollers. When using this as flash memory programmer, it should be used in
combination with a connection cable (16-pin cable) and a USB interface cable that is
used to connect the host machine.
Remark
Download the software for operating the QB-MINI2 from the download site for MINICUBE2
(http://www2.renesas.com/micro/en/development/asia/minicube2/minicube2.html).
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A.4 Debugging Tools (Hardware)
A.4.1 When using in-circuit emulator QB-78K0RLX3
QB-78K0RLX3
In-circuit emulator
This in-circuit emulator serves to debug hardware and software when developing application
systems using the 78K0R/Lx3 microcontrollers. It supports to the integrated debugger (ID78K0RQB). This emulator should be used in combination with a power supply unit and emulation probe,
and the USB is used to connect this emulator to the host machine.
QB-144-CA-01
Check pin adapter
This check pin adapter is used in waveform monitoring using the oscilloscope, etc.
QB-144-EP-02S
Emulation probe
This emulation probe is flexible type and used to connect the in-circuit emulator and target
system.
Note
This exchange adapter is used to perform pin conversion from the in-circuit emulator to target
connector.
Note
This space adapter is used to adjust the height between the target system and in-circuit emulator.
Note
This YQ connector is used to connect the target connector and exchange adapter.
Note
This mount adapter is used to mount the target device with socket.
Note
This target connector is used to mount on the target system.
QB-xxxx-EA-xxx
Exchange adapter
QB-xxxx-YS-xxx
Space adapter
QB-xxxx-YQ-xxx
YQ connector
QB-xxxx-HQ-xxx
Mount adapter
QB-xxxx-NQ-xxx
Target connector
Note The part numbers of the exchange adapter, space adapter, YQ connector, mount adapter, and target connector
and the packages of the target device are described below.
Package
78K0R/LF3
78K0R/LG3
78K0R/LH3
Remark
Exchange
Space
YQ
Mount
Target
Adapter
Adapter
Connector
Adapter
Connector
80-pin plastic
QB-80GC-
QB-80GC-
QB-80GC-
QB-80GC-
QB-80GC-
LQFP (GC-GAD type)
EA-09T
YS-01T
YQ-01T
HQ-01T
NQ-01T
80-pin plastic
QB-80GK-
QB-80GK-
QB-80GK-
QB-80GK-
QB-80GK-
LQFP (GK-GAK type)
EA-08T
YS-01T
YQ-01T
HQ-01T
NQ-01T
100-pin plastic
QB-100GC-
QB-100GC-
QB-100GC-
QB-100GC-
QB-100GC-
LQFP (GC-UEU type)
EA-08T
YS-01T
YQ-01T
HQ-01T
NQ-01T
128-pin plastic
QB-128GF-
QB-128GF-
QB-128GF-
QB-128GF-
QB-128GF-
LQFP (GF-GAT type)
EA-01T
YS-01T
YQ-01T
HQ-01T
NQ-01T
1. The QB-78K0RLX3 is supplied with an integrated debugger ID78K0R-QB, USB interface cable, and onchip debug emulator QB-MINI2.
When using the QB-MINI2 download the software for operating the QB-MINI2 from the download site for
development tools (http://www2.renesas.com/micro/en/ods/).
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Remark
2. The packed contents differ depending on the part number, as follows.
Packed Contents In-Circuit Emulator Emulation Probe
Exchange Adapter
YQ Connector
Target Connector
Part Number
QB-78K0RLX3-ZZZ
QB-78K0RLX3
QB-78K0RLX3-T80GC
None
QB-144-EP-02S
QB-78K0RLX3-T80GK
QB-80GK-EA-09T
QB-80GC-YQ-01T
QB-80GC-NQ-01T
QB-80GK-EA-08T
QB-80GK-YQ-01T
QB-80GK-NQ-01T
QB-100GC-NQ-01T
QB-78K0RLX3-T100GC
QB-100GC-EA-08T
QB-100GC-YQ-01T
QB-78K0RLX3-T128GF
QB-128GF-EA-01T
QB-128GF-YQ-01T QB-128GF-NQ-01T
A.4.2 When using on-chip debug emulator with programming function QB-MINI2
QB-MINI2
This on-chip debug emulator serves to debug hardware and software when developing
On-chip debug emulator with
application systems using the 78K0R/Lx3 microcontrollers. It is available also as flash
programming function
memory programmer dedicated to microcontrollers with on-chip flash memory. When
using this as on-chip debug emulator, it should be used in combination with a connection
cable (16-pin cable), and USB interface cable that is used to connect the host machine.
Remark
Download the software for operating the QB-MINI2 from the download site for MINICUBE2
(http://www2.renesas.com/micro/en/development/asia/minicube2/minicube2.html).
A.5 Debugging Tools (Software)
This debugger supports the in-circuit emulators for the 78K0R microcontrollers. The
ID78K0R-QB
Note 1
Integrated debugger
ID78K0R-QB is Windows-based software.
It has improved C-compatible debugging functions and can display the results of tracing
with the source program using an integrating window function that associates the source
program, disassemble display, and memory display with the trace result. It should be
used in combination with the device file (DF781508).
SM+ for 78K0R
System simulator is Windows-based software.
SM+ for 78K0R/Lx3
Note 2
System simulator
It is used to perform debugging at the C source level or assembler level while simulating
the operation of the target system on a host machine.
Use of system simulator allows the execution of application logical testing and
performance testing on an independent basis from hardware development, thereby
providing higher development efficiency and software quality.
System simulator should be used in combination with the device file (DF781508).
The following two types of system simulators supporting the 78K0R/Lx3 microcontrollers
are available.
• SM+ for 78K0R (instruction simulation version)
This can only simulate a CPU. It is included in the software package.
• SM+ for 78K0R/Lx3 (instruction + peripheral simulation version)
Note 1
This can simulate a CPU and peripheral hardware (ports, timers, serial interfaces,
etc.).
Notes 1.
Download the ID78K0R-QB from the download site for development tools
(http://www2.renesas.com/micro/en/ods/).
2.
Under development
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APPENDIX B REGISTER INDEX
APPENDIX B REGISTER INDEX
B.1 Register Index (In Alphabetical Order with Respect to Register Names)
A
A/D converter mode register (ADM) ........................................................................................................................... 391
A/D converter mode register 1 (ADM1) ...................................................................................................................... 394
A/D port configuration register (ADPC) ...................................................................................................... 193, 399, 429
Alarm hour register (ALARMWH) ............................................................................................................................... 359
Alarm minute register (ALARMWM) ........................................................................................................................... 359
Alarm week register (ALARMWW) ............................................................................................................................. 360
Analog input channel specification register (ADS)...................................................................................................... 398
Analog reference voltage control register (ADVRC) ........................................................................................... 395, 435
B
Background event control register (BECTL)............................................................................................................... 839
BCD correction result register (BCDADJ)................................................................................................................... 854
C
Clock operation mode control register (CMC) ............................................................................................................ 209
Clock operation status control register (CSC) ............................................................................................................ 211
Clock output selection register 0 (CKS0).................................................................................................................... 382
Clock output selection register 1 (CKS1).................................................................................................................... 382
D
D/A conversion value setting register 0 (DACS0)....................................................................................................... 422
D/A conversion value setting register 1 (DACS1)....................................................................................................... 422
D/A conversion value setting register W0 (DACSW0) ................................................................................................ 422
D/A conversion value setting register W1 (DACSW1) ................................................................................................ 422
D/A converter mode register (DAM) ........................................................................................................................... 421
Day count register (DAY) ........................................................................................................................................... 355
DMA byte count register n (DBCn) ............................................................................................................................. 720
DMA mode control register n (DMCn) ........................................................................................................................ 721
DMA operation control register n (DRCn)................................................................................................................... 723
DMA RAM address register n (DRAn)........................................................................................................................ 719
DMA SFR address register n (DSAn)......................................................................................................................... 718
E
8-bit A/D conversion result register (ADCRH) .................................................................................................... 389, 397
External interrupt falling edge enable register (EGN0) ............................................................................................... 760
External interrupt falling edge enable register (EGN1) ............................................................................................... 760
External interrupt rising edge enable register (EGP0) ................................................................................................ 760
External interrupt rising edge enable register (EGP1) ................................................................................................ 760
H
Hour count register (HOUR) ....................................................................................................................................... 354
I
IICA control register 0 (IICCTL0) ................................................................................................................................ 584
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IICA control register 1 (IICCLT1) ................................................................................................................................ 593
IICA flag register (IICF) .............................................................................................................................................. 591
IICA high-level width setting register (IICWH) ............................................................................................................ 595
IICA low-level width setting register (IICWL) .............................................................................................................. 595
IICA shift register (IICA) ............................................................................................................................................. 581
IICA status register (IICS) .......................................................................................................................................... 589
Input switch control register (ISC) .......................................................................................................195, 283, 464, 674
Interrupt mask flag register 0H (MK0H)...................................................................................................................... 752
Interrupt mask flag register 0L (MK0L) ....................................................................................................................... 752
Interrupt mask flag register 1H (MK1H)...................................................................................................................... 752
Interrupt mask flag register 1L (MK1L) ....................................................................................................................... 752
Interrupt mask flag register 2H (MK2H)...................................................................................................................... 752
Interrupt mask flag register 2L (MK2L) ....................................................................................................................... 752
Interrupt request flag register 0H (IF0H)..................................................................................................................... 748
Interrupt request flag register 0L (IF0L)...................................................................................................................... 748
Interrupt request flag register 1H (IF1H)..................................................................................................................... 748
Interrupt request flag register 1L (IF1L)...................................................................................................................... 748
Interrupt request flag register 2H (IF2H)..................................................................................................................... 748
Interrupt request flag register 2L (IF2L)...................................................................................................................... 748
K
Key return mode register (KRM)................................................................................................................................. 772
L
LCD boost level control register (VLCD) .................................................................................................................... 670
LCD clock control register (LCDC0) ........................................................................................................................... 669
LCD display mode register (LCDM)............................................................................................................................ 667
LCD mode register (LCDMD) ..................................................................................................................................... 667
Low-voltage detection level select register (LVIS)...................................................................................................... 808
Low-voltage detection register (LVIM)........................................................................................................................ 805
M
Minute count register (MIN) ........................................................................................................................................ 354
Month count register (MONTH) .................................................................................................................................. 357
Multiplication/division control register (MDUC) ........................................................................................................... 713
Multiplication/division data register A (MDAH) ........................................................................................................... 710
Multiplication/division data register A (MDAL) ............................................................................................................ 710
Multiplication/division data register B (MDBH) ........................................................................................................... 711
Multiplication/division data register B (MDBL) ............................................................................................................ 711
Multiplication/division data register C (MDCH) ........................................................................................................... 712
Multiplication/division data register C (MDCL)............................................................................................................ 712
N
Noise filter enable register 0 (NFEN0)........................................................................................................................ 465
Noise filter enable register 1 (NFEN1)........................................................................................................................ 284
Noise filter enable register 2 (NFEN2)........................................................................................................................ 284
O
Operation speed mode control register (OSMC) ........................................................................................................ 221
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Operational amplifier control register (OAC) .............................................................................................................. 428
Oscillation stabilization time counter status register (OSTC).............................................................................. 212, 774
Oscillation stabilization time select register (OSTS) ........................................................................................... 214, 775
P
Peripheral enable register 0 (PER0)............................................................219, 262, 348, 390, 420, 427, 435, 447, 584
Port function register (PFALL) ............................................................................................................................ 194, 671
Port input mode register 1 (PIM1) ...................................................................................................................... 191, 466
Port input mode register 7 (PIM7) ...................................................................................................................... 191, 466
Port mode register 0 (PM0) ........................................................................................................................................ 180
Port mode register 1 (PM1) ........................................................................................................................ 180, 287, 468
Port mode register 10 (PM10) .................................................................................................................................... 180
Port mode register 11 (PM11) .................................................................................................................................... 180
Port mode register 12 (PM12) ............................................................................................................................ 180, 809
Port mode register 14 (PM14) .................................................................................................................................... 180
Port mode register 15 (PM15) .................................................................................................................... 180, 400, 430
Port mode register 2 (PM2) ........................................................................................................................ 180, 400, 430
Port mode register 3 (PM3) .................................................................................................................180, 287, 361, 384
Port mode register 4 (PM4) ........................................................................................................................................ 180
Port mode register 5 (PM5) ........................................................................................................................ 180, 287, 468
Port mode register 6 (PM6) ................................................................................................................................ 180, 595
Port mode register 7 (PM7) ................................................................................................................................ 180, 468
Port mode register 8 (PM8) ........................................................................................................................ 180, 287, 468
Port mode register 9 (PM9) ........................................................................................................................................ 180
Port output mode register 1 (POM1) .................................................................................................................. 192, 467
Port output mode register 7 (POM7) .................................................................................................................. 192, 467
Port output mode register 8 (POM8) .................................................................................................................. 192, 467
Port register 0 (P0) ..................................................................................................................................................... 184
Port register 1 (P1) ..................................................................................................................................................... 184
Port register 10 (P10) ................................................................................................................................................. 184
Port register 11 (P11) ................................................................................................................................................. 184
Port register 12 (P12) ................................................................................................................................................. 184
Port register 13 (P13) ................................................................................................................................................. 184
Port register 14 (P14) ................................................................................................................................................. 184
Port register 15 (P15) ................................................................................................................................................. 184
Port register 2 (P2) ..................................................................................................................................................... 184
Port register 3 (P3) ..................................................................................................................................................... 184
Port register 4 (P4) ..................................................................................................................................................... 184
Port register 5 (P5) ..................................................................................................................................................... 184
Port register 6 (P6) ..................................................................................................................................................... 184
Port register 7 (P7) ..................................................................................................................................................... 184
Port register 8 (P8) ..................................................................................................................................................... 184
Port register 9 (P9) ..................................................................................................................................................... 184
Priority specification flag register 00H (PR00H) ......................................................................................................... 755
Priority specification flag register 00L (PR00L)........................................................................................................... 755
Priority specification flag register 01H (PR01H) ......................................................................................................... 755
Priority specification flag register 01L (PR01L)........................................................................................................... 755
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Priority specification flag register 02H (PR02H) ......................................................................................................... 755
Priority specification flag register 02L (PR02L)........................................................................................................... 755
Priority specification flag register 10H (PR10H) ......................................................................................................... 755
Priority specification flag register 10L (PR10L)........................................................................................................... 755
Priority specification flag register 11H (PR11H) ......................................................................................................... 755
Priority specification flag register 11L (PR11L)........................................................................................................... 755
Priority specification flag register 12H (PR12H) ......................................................................................................... 755
Priority specification flag register 12L (PR12L)........................................................................................................... 755
Processor mode control register (PMC) ....................................................................................................................... 83
Pull-up resistor option register 0 (PU0) ...................................................................................................................... 188
Pull-up resistor option register 1 (PU1) ...................................................................................................................... 188
Pull-up resistor option register 3 (PU3) ...................................................................................................................... 188
Pull-up resistor option register 4 (PU4) ...................................................................................................................... 188
Pull-up resistor option register 5 (PU5) ...................................................................................................................... 188
Pull-up resistor option register 7 (PU7) ...................................................................................................................... 188
Pull-up resistor option register 8 (PU8) ...................................................................................................................... 188
Pull-up resistor option register 9 (PU9) ...................................................................................................................... 188
Pull-up resistor option register 10 (PU10) .................................................................................................................. 188
Pull-up resistor option register 12 (PU12) .................................................................................................................. 188
Pull-up resistor option register 14 (PU14) .................................................................................................................. 188
R
Real-time counter control register 0 (RTCC0) ............................................................................................................ 348
Real-time counter control register 1 (RTCC1) ............................................................................................................ 350
Real-time counter control register 2 (RTCC2) ............................................................................................................ 352
Regulator mode control register (RMC)...................................................................................................................... 827
Reset control flag register (RESF).............................................................................................................................. 797
S
Second count register (SEC)...................................................................................................................................... 353
Segment enable register (SEGEN) ............................................................................................................................ 672
Serial channel enable status register m (SEm) .......................................................................................................... 458
Serial channel start register m (SSm)......................................................................................................................... 459
Serial channel stop register m (STm) ......................................................................................................................... 460
Serial clock select register m (SPSm) ........................................................................................................................ 447
Serial communication operation setting register mn (SCRmn) ................................................................................... 451
Serial data register mn (SDRmn) ............................................................................................................................... 454
Serial flag clear trigger register mn (SIRmn) .............................................................................................................. 457
Serial mode register mn (SMRmn) ............................................................................................................................. 449
Serial output enable register m (SOEm)..................................................................................................................... 461
Serial output level register m (SOLm) ........................................................................................................................ 463
Serial output register m (SOm)................................................................................................................................... 462
Serial status register mn (SSRmn) ............................................................................................................................. 455
Slave address register (SVA) ..................................................................................................................................... 581
Sub-count register (RSUBC) ...................................................................................................................................... 353
Successive approximation register (SAR) .................................................................................................................. 388
System clock control register (CKC)........................................................................................................................... 216
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T
10-bit A/D conversion result register (ADCR) ..................................................................................................... 389, 397
Timer channel enable status register m (TEm) .......................................................................................................... 269
Timer channel start register m (TSm)......................................................................................................................... 270
Timer channel stop register m (TTm) ......................................................................................................................... 275
Timer clock select register m (TPSm) ........................................................................................................................ 262
Timer data register mn (TDRmn)................................................................................................................................ 260
Timer input select register p (TISp) ............................................................................................................................ 276
Timer mode register mn (TMRmn) ............................................................................................................................. 264
Timer output enable register p (TOEp)....................................................................................................................... 278
Timer output level register p (TOLp)........................................................................................................................... 281
Timer output mode register p (TOMp) ........................................................................................................................ 282
Timer output register p (TOp) ..................................................................................................................................... 279
Timer status register pq (TSRpq) ............................................................................................................................... 268
Timer/counter register mn (TCRmn)........................................................................................................................... 258
12-bit A/D conversion result register (ADCR) ..................................................................................................... 389, 396
20 MHz internal high-speed oscillation control register (DSCCTL)............................................................................. 218
W
Watch error correction register (SUBCUD) ................................................................................................................ 358
Watchdog timer enable register (WDTE).................................................................................................................... 376
Week count register (WEEK) ..................................................................................................................................... 356
Y
Year count register (YEAR)........................................................................................................................................ 357
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APPENDIX B REGISTER INDEX
B.2 Register Index (In Alphabetical Order with Respect to Register Symbol)
A
ADCR: 12-bit A/D conversion result register ...................................................................................................... 389, 396
ADCRH: 8-bit A/D conversion result register...................................................................................................... 389, 397
ADM: A/D converter mode register............................................................................................................................. 391
ADM1: A/D converter mode register 1........................................................................................................................ 394
ADPC: A/D port configuration register........................................................................................................ 193, 399, 429
ADS: Analog input channel specification register ....................................................................................................... 398
ADVRC: Analog reference voltage control register ............................................................................................ 395, 435
ALARMWH: Alarm hour register................................................................................................................................. 359
ALARMWM: Alarm minute register............................................................................................................................. 359
ALARMWW: Alarm week register............................................................................................................................... 360
B
BCDADJ: BCD correction result register .................................................................................................................... 854
BECTL: Background event control register ................................................................................................................ 839
C
CKC: System clock control register ............................................................................................................................ 216
CKS0: Clock output selection register 0 ..................................................................................................................... 382
CKS1: Clock output selection register 1 ..................................................................................................................... 382
CMC: Clock operation mode control register.............................................................................................................. 209
CSC: Clock operation status control register.............................................................................................................. 211
D
DACS0: D/A conversion value setting register 0 ........................................................................................................ 422
DACS1: D/A conversion value setting register 1 ........................................................................................................ 422
DACSW0: D/A conversion value setting register W0 ................................................................................................. 422
DACSW1: D/A conversion value setting register W1 ................................................................................................. 422
DAM: D/A converter mode register............................................................................................................................. 421
DAY: Day count register............................................................................................................................................. 355
DBCn: DMA byte count register n .............................................................................................................................. 720
DMCn: DMA mode control register n.......................................................................................................................... 721
DSCCTL: 20 MHz internal high-speed oscillation control register ............................................................................. 218
DRAn: DMA RAM address register n ......................................................................................................................... 719
DRCn: DMA operation control register n .................................................................................................................... 723
DSAn: DMA SFR address register n .......................................................................................................................... 718
E
EGN0: External interrupt falling edge enable register ................................................................................................ 760
EGN1: External interrupt falling edge enable register ................................................................................................ 760
EGP0: External interrupt rising edge enable register ................................................................................................. 760
EGP1: External interrupt rising edge enable register ................................................................................................. 760
H
HOUR: Hour count register ........................................................................................................................................ 354
I
IF0H: Interrupt request flag register 0H ...................................................................................................................... 748
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APPENDIX B REGISTER INDEX
IF0L: Interrupt request flag register 0L ....................................................................................................................... 748
IF1H: Interrupt request flag register 1H ...................................................................................................................... 748
IF1L: Interrupt request flag register 1L ....................................................................................................................... 748
IF2H: Interrupt request flag register 2H ...................................................................................................................... 748
IF2L: Interrupt request flag register 2L ....................................................................................................................... 748
IICA: IICA shift register............................................................................................................................................... 581
IICCLT1: IICA control register 1 ................................................................................................................................. 593
IICCTL0: IICA control register 0 ................................................................................................................................. 584
IICF: IICA flag register................................................................................................................................................ 591
IICS: IICA status register............................................................................................................................................ 589
IICWH: IICA high-level width setting register.............................................................................................................. 595
IICWL: IICA low-level width setting register................................................................................................................ 595
ISC: Input switch control register.........................................................................................................195, 283, 464, 674
K
KRM: Key return mode register .................................................................................................................................. 772
L
LCDC0: LCD clock control register............................................................................................................................. 669
LCDM: LCD display mode register ............................................................................................................................. 667
LCDMD: LCD mode register ...................................................................................................................................... 667
LVIM: Low-voltage detection register ......................................................................................................................... 805
LVIS: Low-voltage detection level select register ....................................................................................................... 808
M
MDAH: Multiplication/division data register A............................................................................................................. 710
MDAL: Multiplication/division data register A ............................................................................................................. 710
MDBH: Multiplication/division data register B............................................................................................................. 711
MDBL: Multiplication/division data register B ............................................................................................................. 711
MDCH: Multiplication/division data register C ............................................................................................................ 712
MDCL: Multiplication/division data register C ............................................................................................................. 712
MDUC: Multiplication/division control register ............................................................................................................ 713
MIN: Minute count register ......................................................................................................................................... 354
MK0H: Interrupt mask flag register 0H ....................................................................................................................... 752
MK0L: Interrupt mask flag register 0L ........................................................................................................................ 752
MK1H: Interrupt mask flag register 1H ....................................................................................................................... 752
MK1L: Interrupt mask flag register 1L ........................................................................................................................ 752
MK2H: Interrupt mask flag register 2H ....................................................................................................................... 752
MK2L: Interrupt mask flag register 2L ........................................................................................................................ 752
MONTH: Month count register ................................................................................................................................... 357
N
NFEN0: Noise filter enable register 0 ......................................................................................................................... 465
NFEN1: Noise filter enable register 1 ......................................................................................................................... 284
NFEN2: Noise filter enable register 2 ......................................................................................................................... 284
O
OAC: Operational amplifier control register................................................................................................................ 428
OSMC: Operation speed mode control register ......................................................................................................... 221
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OSTC: Oscillation stabilization time counter status register ............................................................................... 212, 774
OSTS: Oscillation stabilization time select register ............................................................................................ 214, 775
P
P0: Port register 0 ...................................................................................................................................................... 184
P1: Port register 1 ...................................................................................................................................................... 184
P2: Port register 2 ...................................................................................................................................................... 184
P3: Port register 3 ...................................................................................................................................................... 184
P4: Port register 4 ...................................................................................................................................................... 184
P5: Port register 5 ...................................................................................................................................................... 184
P6: Port register 6 ...................................................................................................................................................... 184
P7: Port register 7 ...................................................................................................................................................... 184
P8: Port register 8 ...................................................................................................................................................... 184
P9: Port register 9 ...................................................................................................................................................... 184
P10: Port register 10 .................................................................................................................................................. 184
P11: Port register 11 .................................................................................................................................................. 184
P12: Port register 12 .................................................................................................................................................. 184
P13: Port register 13 .................................................................................................................................................. 184
P14: Port register 14 .................................................................................................................................................. 184
P15: Port register 15 .................................................................................................................................................. 184
PER0: Peripheral enable register 0 .............................................................219, 262, 348, 390, 420, 427, 435, 447, 584
PFALL: Port function register ............................................................................................................................. 194, 671
PIM1: Port input mode register 1........................................................................................................................ 191, 466
PIM7: Port input mode register 7........................................................................................................................ 191, 466
PM0: Port mode register 0 ......................................................................................................................................... 180
PM1: Port mode register 1 ......................................................................................................................... 180, 287, 468
PM2: Port mode register 2 ......................................................................................................................... 180, 400, 430
PM3: Port mode register 3 ..................................................................................................................180, 287, 361, 384
PM4: Port mode register 4 ......................................................................................................................................... 180
PM5: Port mode register 5 ......................................................................................................................... 180, 287, 468
PM6: Port mode register 6 ................................................................................................................................. 180, 595
PM7: Port mode register 7 ................................................................................................................................. 180, 468
PM8: Port mode register 8 ......................................................................................................................... 180, 287, 468
PM9: Port mode register 9 ......................................................................................................................................... 180
PM10: Port mode register 10 ..................................................................................................................................... 180
PM11: Port mode register 11 ..................................................................................................................................... 180
PM12: Port mode register 12 ............................................................................................................................. 180, 809
PM14: Port mode register 14 ..................................................................................................................................... 180
PM15: Port mode register 15 ..................................................................................................................... 180, 400, 430
PMC: Processor mode control register......................................................................................................................... 83
POM1: Port output mode register 1.................................................................................................................... 192, 467
POM7: Port output mode register 7.................................................................................................................... 192, 467
POM8: Port output mode register 8.................................................................................................................... 192, 467
PR00H: Priority specification flag register 00H........................................................................................................... 755
PR00L: Priority specification flag register 00L ............................................................................................................ 755
PR01H: Priority specification flag register 01H........................................................................................................... 755
PR01L: Priority specification flag register 01L ............................................................................................................ 755
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APPENDIX B REGISTER INDEX
PR02H: Priority specification flag register 02H........................................................................................................... 755
PR02L: Priority specification flag register 02L ............................................................................................................ 755
PR10H: Priority specification flag register 10H........................................................................................................... 755
PR10L: Priority specification flag register 10L ............................................................................................................ 755
PR11H: Priority specification flag register 11H........................................................................................................... 755
PR11L: Priority specification flag register 11L ............................................................................................................ 755
PR12H: Priority specification flag register 12H........................................................................................................... 755
PR12L: Priority specification flag register 12L ............................................................................................................ 755
PU0: Pull-up resistor option register 0........................................................................................................................ 188
PU1: Pull-up resistor option register 1........................................................................................................................ 188
PU3: Pull-up resistor option register 3........................................................................................................................ 188
PU4: Pull-up resistor option register 4........................................................................................................................ 188
PU5: Pull-up resistor option register 5........................................................................................................................ 188
PU7: Pull-up resistor option register 7........................................................................................................................ 188
PU8: Pull-up resistor option register 8........................................................................................................................ 188
PU9: Pull-up resistor option register 9........................................................................................................................ 188
PU10: Pull-up resistor option register 10.................................................................................................................... 188
PU12: Pull-up resistor option register 12.................................................................................................................... 188
PU14: Pull-up resistor option register 14.................................................................................................................... 188
R
RESF: Reset control flag register ............................................................................................................................... 797
RMC: Regulator mode control register ....................................................................................................................... 827
RSUBC : Sub-count register ...................................................................................................................................... 353
RTCC0: Real-time counter control register 0 ............................................................................................................. 348
RTCC1: Real-time counter control register 1 ............................................................................................................. 350
RTCC2: Real-time counter control register 2 ............................................................................................................. 352
S
SAR :Successive approximation register ................................................................................................................... 388
SCRmn: Serial communication operation setting register mn .................................................................................... 451
SDRmn: Serial data register mn................................................................................................................................. 454
SEC : Second count register ...................................................................................................................................... 353
SEGEN: Segment enable register.............................................................................................................................. 672
SEm: Serial channel enable status register m............................................................................................................ 458
SIRmn: Serial flag clear trigger register mn................................................................................................................ 457
SMRmn: Serial mode register mn .............................................................................................................................. 449
SOEm: Serial output enable register m ...................................................................................................................... 461
SOLm: Serial output level register m.......................................................................................................................... 463
SOm: Serial output register m .................................................................................................................................... 462
SPSm: Serial clock select register m.......................................................................................................................... 447
SSm: Serial channel start register m .......................................................................................................................... 459
SSRmn: Serial status register mn .............................................................................................................................. 455
STm: Serial channel stop register m .......................................................................................................................... 460
SUBCUD: Watch error correction register.................................................................................................................. 358
SVA: Slave address register ...................................................................................................................................... 581
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APPENDIX B REGISTER INDEX
T
TCRmn: Timer/counter register mn ............................................................................................................................ 258
TDRmn: Timer data register mn ................................................................................................................................. 260
TEm: Timer channel enable status register m ............................................................................................................ 269
TISp: Timer input select register p.............................................................................................................................. 276
TMRmn: Timer mode register mn............................................................................................................................... 264
TOEp: Timer output enable register p ........................................................................................................................ 278
TOLp: Timer output level register p ............................................................................................................................ 281
TOMp:Timer output mode register p .......................................................................................................................... 282
TOp: Timer output register p ...................................................................................................................................... 279
TPSm: Timer clock select register m.......................................................................................................................... 262
TSm: Timer channel start register m .......................................................................................................................... 270
TSRpq: Timer status register pq................................................................................................................................. 268
TTm: Timer channel stop register m........................................................................................................................... 275
V
VLCD: LCD boost level control register...................................................................................................................... 670
W
WDTE: Watchdog timer enable register ..................................................................................................................... 376
WEEK : Week count register ...................................................................................................................................... 356
Y
YEAR: Year count register ......................................................................................................................................... 357
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APPENDIX C LIST OF CAUTIONS
APPENDIX C LIST OF CAUTIONS
This appendix lists the cautions described in this document.
“Classification (hard/soft)” in the table is as follows.
Hard: Cautions for microcontroller internal/external hardware
Soft: Cautions for software such as register settings or programs
Classification
Hard
Chapter 1
Chapter
(1/39)
Function
Details of
Cautions
Page
Function
Outline
On-chip debug
The 78K0R/Lx3 microcontrollers have an on-chip debug function, which is provided p.3
function
for development and evaluation. Do not use the on-chip debug function in products
designated for mass production, because the guaranteed number of rewritable times
of the flash memory may be exceeded when this function is used, and product
reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for
problems occurring when the on-chip debug function is used.
AVSS, VSS
pp.4, 5
Make AVSS the same potential as VSS.
7, 8, 10,11
Soft
Chapter 2
REGC
Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF).
pp.4, 5
7, 8, 10,11
as a general-purpose port, set bit 5 p.43
Pin
P00/CAPH,
To use P00/CAPH, P01/CAPL, and P02/VLC3
functions
P01/CAPL,
(MDSET1) and bit 4 (MDSET0) of LCD mode register (LCDMD) to “0”, which is the
P02/VLC3
same as their default status setting.
P10/SCK20/
To use P10/SCK20/SCL20 and P11/SI20/RxD2/SDA20/INTP6 as a general-purpose p.45
SCL20,
port, note the serial array unit 1 setting. For details, refer to Table 14-9 Relationship
P11/SI20/RxD2/
Between Register Settings and Pins (Channel 0 of unit 1: CSI20, UART2 Reception,
SDA20/INTP6
IIC20).
P12/TO02/SO20 To use P12/TO02/SO20/TxD2 as a general-purpose port, set bit 2 (TO02) of timer p.45
/TxD2
output register 0 (TO0) and bit 2 (TOE02) of timer output enable register 0 (TOE0) to
“0”, which is the same as their default status setting. And as a general-purpose port,
note the serial array unit 1 setting. For details of serial array unit 1 setting, refer to
Table 14-9 Relationship Between Register Settings and Pins (Channel 0 of unit 1:
CSI20, UART2 Reception, IIC20).
P13/TO04/SO10 To use P13/TO04/SO10/TxD1 as a general-purpose port, set bit 4 (TO04) of timer p.45
/TxD1
output register 0 (TO0) and bit 4 (TOE04) of timer output enable register 0 (TOE0) to
“0”, which is the same as their default status setting. And as a general-purpose port,
note the serial array unit 0 setting. For details of serial array unit 0 setting, refer to
Table 14-7 Relationship Between Register Settings and Pins (Channel 2 of unit 0:
CSI10, UART1 Transmission, IIC10).
P14/SI10/RxD1/
To use P14/SI10/RxD1/SDA10/INTP4 and P15/SCK10/SCL10/INTP7 as a general- p.45
SDA10/INTP4,
purpose port, note the serial array unit 0 setting. For details, refer to Table 14-7
P15/SCK10/
Relationship Between Register Settings and Pins (Channel 2 of unit 0: CSI10,
SCL10/INTP7
UART1 Transmission, IIC10).
P16/TO05/TI05/
To use P16/TO05/TI05/INTP10 as a general-purpose port, set bit 5 (TO05) of timer p.45
INTP10
output register 0 (TO0) and bit 5 (TOE05) of timer output enable register 0 (TOE0) to
“0”, which is the same as their default status setting.
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APPENDIX C LIST OF CAUTIONS
Classification
Soft
Soft Hard
Chapter 2
Chapter
(2/39)
Function
Details of
Cautions
Page
Function
Pin
P20/ANI0/AMP0- P20/ANI0/AMP0- to P27/ANI7/ANP2O are set in the digital input (general-purpose p.46
functions
to
port) mode after release of reset.
P27/ANI7/ANP2O When using at least one port of ports P20/ANI0/AMP0- to P27/ANI7/ANP2O as a p.46
digital port, set AVDD0 to the same potential as EVDD or VDD.
P30/TO00/TI03/
To use P30/TO00/TI03/RTC1HZ/INTP1 as a general-purpose port, set bit 5 p.48
RTC1HZ/INTP1
(RCLOE1) of real-time counter control register 0 (RTCC0), bit 0 (TO00) of timer
output register 0 (TO0) and bit 0 (TOE00) of timer output enable register 0 (TOE0) to
“0”, which is the same as their default status setting.
P31/TO03/TI00/
To use P31/TO03/TI00/RTCDIV/RTCCL/PCLBUZ1/INTP2 as a general-purpose port, p.48
RTCDIV/RTCCL/ set bit 4 (RCLOE0) of real-time counter control register 0 (RTCC0), bit 6 (RCLOE2)
PCLBUZ1/INTP2 of real-time counter control register 2 (RTCC2), bit 3 (TO03) of timer output register 0
(TO0), bit 3 (TOE03) of timer output enable register 0 (TOE0) and bit 7 of clock
output select register 1 (CKS1) to “0”, which is the same as their default status
setting.
P32/TO01/TI01/
To use P32/TO01/TI01/INTP5/PCLBUZ0 as a general-purpose port, set bit 1 (TO01) p.48
INTP5/PCLBUZ0 of timer output register 0 (TO0), bit 1 (TOE01) of timer output enable register 0
(TOE0) and bit 7 of clock output select register 0 (CKS0) to “0”, which is the same as
Hard
their default status setting.
P33/TO07/TI07/
To use P33/TO07/TI07/INTP3 and P34/TO06/TI06/INTP8 as a general-purpose port, p.48
INTP3,
set bit 7, 6 (TO07, TO06) of timer output register 0 (TO0), and bit 7, 6 (TOE07,
P34/TO06/TI06/
TOE06) of timer output enable register 0 (TOE0) to “0”, which is the same as their
INTP8
P40/TOOL0
default status setting.
p.49
P60/SCL0,
When using P60/SCL0 and P61/SDA0 as a general-purpose port, stop the operation p.50
P61/SDA0
of serial interface IICA.
The function of the P40/TOOL0 pin varies as described in (a) to (c) below.
In the case of (b) or (c), make the specified connection.
(a) In normal operation mode and when on-chip debugging is disabled (OCDENSET
= 0) by an option byte (000C3H)
=> Use this pin as a port pin (P40).
(b) In normal operation mode and when on-chip debugging is enabled (OCDENSET
= 1) by an option byte (000C3H)
=> Connect this pin to VDD via an external resistor, and always input a high level
to the pin before reset release.
(c) When on-chip debug function is used, or in write mode of flash memory
programmer
=> Use this pin as TOOL0.
Directly connect this pin to the on-chip debug
emulator or a flash memory programmer, or pull it up by connecting it to VDD
Soft
via an external resistor.
P75/SCK01/KR5, To use P75/SCK01/KR5, P76/SI01/KR6, and P77/SO01/KR7, as a general-purpose p.51
port, note the serial array unit 0 setting. For details, refer to Table 14-6 Relationship
P76/SI01/KR6,
Between Register Settings and Pins (Channel 1 of unit 0: CSI01, UART0 Reception).
P77/SO01/KR7
P80/SCK00/
To use P80/SCK00/INTP11, P81/RxD0/SI00/INTP9, and P82/SO00/TxD0, as a p.53
INTP11,
general-purpose port, note the serial array unit 0 setting. For details, refer to Table
P81/RxD0/SI00/
14-5 Relationship Between Register Settings and Pins (Channel 0 of unit 0: CSI00,
INTP9,
UART0 Reception).
P82/SO00/TxD0
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APPENDIX C LIST OF CAUTIONS
Chapter
Classification
Chapter 2
Soft Hard
(3/39)
Function
Details of
Cautions
Page
Function
Pin
P110/ANO0,
When using at least one port of P110/ANO0 and P111/ANO1 as a digital port, set p.54
functions
P111/ANO1
P121 to P124
AVDD1 to the same potential as EVDD or VDD.
The function setting on P121 to P124 is available only once after the reset release. p.55
The port once set for connection to an oscillator cannot be used as an input port
Hard
unless the reset is performed.
P150/ANI8/
P150/ANI8/AMP2+ to P152/ANI10 and P157/ANI15/AVREFM are set in the digital input p.57
AMP2+ to
(general-purpose port) mode after release of reset.
P152/ANI10 and When using at least one port of P150/ANI8/AMP2+ to P152/ANI10 and p.57
P157/ANI15/
P157/ANI15/AVREFM as a digital port, set AVDD0 to the same potential as EVDD or VDD.
AVREFM
REGC
Keep the wiring length as short as possible for the broken-line part in the above p.58
Soft
Chapter 3
figure.
Memory
PMC: Processor
Set PMC only once during the initial settings prior to operating the DMA controller.
space
mode control
Rewriting PMC other than during the initial settings is prohibited.
register
After setting PMC, wait for at least one instruction and access the mirror area.
p.83
p.83
When the μPD78F1500A, 78F1503A, and 78F1506A (flash memory size: 64 KB) are p.83
used, be sure to set bit 0 (MAA) of this register to 0.
Internal data
It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for
pp.83,
memory space
fetching instructions or as a stack area.
89, 90
While using the self-programming function, the area of FFE20H to FFEFFH cannot
pp.83,
89
be used as a stack memory.
SFR: Special
Do not access addresses to which SFRs are not assigned.
pp.84,
93
Do not access addresses to which 2nd SFRs are not assigned.
pp.84,
99
p.89
function register
area
2nd SFR:
Extended special
Soft
Chapter 4
function register
Processor
SP: Stack
Since reset signal generation makes the SP contents undefined, be sure to initialize
registers
pointer
the SP before using the stack.
Port
P00/CAPH,
To use P00/CAPH, P01/CAPL, and P02/VLC3 as a general-purpose port, set bit 5 p.130
functions
P01/CAPL,
(MDSET1) and bit 4 (MDSET0) of LCD mode register (LCDMD) to “0”, which is the
P02/VLC3
same as their default status setting.
P10/SCK20/
To use P10/SCK20/SCL20 and P11/SI20/RxD2/SDA20/INTP6 as a general-purpose p.133
SCL20,
port, note the serial array unit 1 setting. For details, refer to Table 14-9 Relationship
P11/SI20/RxD2/
Between Register Settings and Pins (Channel 0 of unit 1: CSI20, UART2 Reception,
SDA20/INTP6
IIC20).
P12/TO02/SO20/ To use P12/TO02/SO20/TxD2 as a general-purpose port, set bit 2 (TO02) of timer p.133
TxD2
output register 0 (TO0) and bit 2 (TOE02) of timer output enable register 0 (TOE0) to
“0”, which is the same as their default status setting. And as a general-purpose port,
note the serial array unit 1 setting. For details of serial array unit 1 setting, refer to
Table 14-9 Relationship Between Register Settings and Pins (Channel 0 of unit 1:
CSI20, UART2 Reception, IIC20).
P13/TO04/SO10 To use P13/TO04/SO10/TxD1 as a general-purpose port, set bit 4 (TO04) of timer
/TxD1
p.133
output register 0 (TO0) and bit 4 (TOE04) of timer output enable register 0 (TOE0) to
“0”, which is the same as their default status setting. And as a general-purpose port,
note the serial array unit 0 setting. For details of serial array unit 0 setting, refer to
Table 14-7 Relationship Between Register Settings and Pins (Channel 2 of unit 0:
CSI10, UART1 Transmission, IIC10)
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APPENDIX C LIST OF CAUTIONS
Classification
Soft
Chapter 4
Chapter
(4/39)
Function
Details of
Cautions
Page
Function
Port
P14/SI10/RxD1/
To use P14/SI10/RxD1/SDA10/INTP4 and P15/SCK10/SCL10/INTP7 as a general- p.133
functions
SDA10/INTP4,
purpose port, note the serial array unit 0 setting. For details, refer to Table 14-7
P15/SCK10/SCL Relationship Between Register Settings and Pins (Channel 2 of unit 0: CSI10,
10/INTP7
UART1 Transmission, IIC10)
P16/TO05/TI05/
To use P16/TO05/TI05/INTP10 as a general-purpose port, set bit 5 (TO05) of timer
INTP10
output register 0 (TO0) and bit 5 (TOE05) of timer output enable register 0 (TOE0) to
p.133
Make the AVDD0 pin the same potential as the EVDD or VDD pin when port 2 is used as p.138
Soft Hard
“0”, which is the same as their default status setting.
Port 2
a digital port.
P30/TO00/TI03/
To use P30/TO00/TI03/RTC1HZ/INTP1 as a general-purpose port, set bit 5 p.142
RTC1HZ/INTP1
(RCLOE1) of real-time counter control register 0 (RTCC0), bit 0 (TO00) of timer
output register 0 (TO0) and bit 0 (TOE00) of timer output enable register 0 (TOE0) to
“0”, which is the same as their default status setting.
P31/TO03/TI00/
To use P31/TO03/TI00/RTCDIV/RTCCL/PCLBUZ1/INTP2 as a general-purpose port, p.142
RTCDIV/RTCCL/ set bit 4 (RCLOE0) of real-time counter control register 0 (RTCC0), bit 6 (RCLOE2) of
PCLBUZ1/INTP2 real-time counter control register 2 (RTCC2), bit 3 (TO03) of timer output register 0
(TO0), bit 3 (TOE03) of timer output enable register 0 (TOE0) and bit 7 of clock
output select register 1 (CKS1) to “0”, which is the same as their default status
setting.
P32/TO01/TI01/
To use P32/TO01/TI01/INTP5/PCLBUZ0 as a general-purpose port, set bit 1 (TO01) p.142
INTP5/PCLBUZ0 of timer output register 0 (TO0), bit 1 (TOE01) of timer output enable register 0
(TOE0) and bit 7 of clock output select register 0 (CKS0) to “0”, which is the same as
their default status setting.
P33/TO07/TI07/
To use P33/TO07/TI07/INTP3 and P34/TO06/TI06/INTP8 as a general-purpose port, p.142
INTP3,
set bit 7, 6 (TO07, TO06) of timer output register 0 (TO0), and bit 7, 6 (TOE07,
Hard
P34/TO06/TI06/I TOE06) of timer output enable register 0 (TOE0) to “0”, which is the same as their
NTP8
default status setting.
P40, P41
When a tool is connected, the P40 pin cannot be used as a port pin.
p.144
P60/SCL0,
When using P60/SCL0 and P61/SDA0 as a general-purpose port, stop the operation p.150
P61/SDA0
of serial interface IICA.
When the on-chip debug function is used, P41 pin can be used as follows by the
mode setting on the debugger.
• 1-line mode: can be used as a port (P41).
Soft
• 2-line mode: used as a TOOL1 pin and cannot be used as a port (P41).
P75/SCK01/KR5, To use P75/SCK01/KR5, P76/SI01/KR6 and P77/SO01/KR7, as a general-purpose p.151
P76/SI01/KR6,
port, note the serial array unit 0 setting. For details, refer to Table 14-6 Relationship
P77/SO01/KR7
Between Register Settings and Pins (Channel 1 of unit 0: CSI01, UART0 Reception).
P80/SCK00/
To use P80/SCK00/INTP11, P81/RxD0/SI00/INTP9 and P82/SO00/TxD0, as a p.156
INTP11,
general-purpose port, note the serial array unit 0 setting. For details, refer to Table
P81/RxD0/SI00/
14-5 Relationship Between Register Settings and Pins (Channel 0 of unit 0: CSI00,
INTP9,
UART0 Reception).
P82/SO00/TxD0
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Function
Port
Port 11
functions
Make the AVDD1 pin the same potential as the EVDD or VDD pin when port 11 is used p.167
as a digital port.
P121 to P124
The function setting on P121 to P124 is available only once after the reset release. p.168
The port once set for connection to an oscillator cannot be used as an input port
unless the reset is performed.
Port 15
Make the AVDD0 pin the same potential as the EVDD or VDD pin when port 15 is used p.176
Soft
as a digital port.
Port mode
Be sure to set bits 3 to 7 of PM0, bits 6, 7 of PM1, bit 7 of PM2, bits 4 to 7 of PM3, p.181
register
bits 2 to 7 of PM4, bits 3 to 7 of PM9, bits 1 to 7 of PM10, bits 2 to 7 of PM11, bits 1
(78K0R/LF3)
to 7 of PM12, and bits 0 to 6 of PM15 to 1.
Port mode
Be sure to set bits 3 to 7 of PM0, bit 7 of PM1, bits 5 to 7 of PM3, bits 2 to 7 of PM4, p.182
register
bits 2 to 7 of PM6, bits 3 to 7 of PM8, bits 1 to 7 of PM10, bits 2 to 7 of PM11, bits 1
(78K0R/LG3)
to 7 of PM12, and bits 3 to 6 of PM15 to 1.
Port mode
Be sure to set bits 3 to 7 of PM0, bits 5 to 7 of PM3, bits 2 to 7 of PM4, bits 2 to 7 of p.183
register
PM6, bits 3 to 7 of PM10, bits 2 to 7 of PM11, bits 1 to 7 of PM12, and bits 3 to 6 of
(78K0R/LH3)
PM15 to 1.
ADPC: A/D port
Set the channel used for A/D conversion to the input mode by using port mode p.193
configuration
registers 2 and 15 (PM2, PM15).
register
Do not set the pin that is set by ADPC as digital I/O by analog input channel p.193
specification register (ADS).
PFALL: Port
For 78K0R/LF3, bits 3 and 7 must be set to 0. For 78K0R/LG3 and 78K0R/LH3, bit 7 p.195
function register
must be set to 0.
p.196
1-bit
When a 1-bit manipulation instruction is executed on a port that provides both input p.205
manipulation
and output functions, the output latch value of an input port that is not subject to
ISC: Input switch Be sure to clear bits 5 to 7 to “0”.
Soft
Chapter 5
control register
instruction for
manipulation may be written in addition to the targeted bit.
port register n
recommended to rewrite the output latch when switching a port from input mode to
Therefore, it is
(Pn)
output mode.
Clock
CMC: Clock
CMC can be written only once after reset release, by an 8-bit memory manipulation p.210
generator
operation mode
instruction.
control register
After reset release, set CMC before X1 or XT1 oscillation is started as set by the p.210
clock operation status control register (CSC).
Be sure to set AMPH to 1 if the X1 clock oscillation frequency exceeds 10 MHz.
p.210
To use CMC with its initial value (00H), be sure to set it to 00H after releasing reset in p.210
order to prevent malfunction when a program loop occurs.
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Function
Clock
CMC: Clock
generator
operation mode
control register
The XT1 oscillator is designed as a low-gain circuit for achieving low-power pp.210,
consumption. Note the following points when designing the XT1 oscillator.
211
• The pins and circuit board include parasitic capacitance. Therefore, confirm that
there are no problems by performing oscillation evaluation on the circuit board to
be actually used.
• When low-consumption oscillation or super-low-consumption oscillation is
selected, lower power consumption than when selecting normal oscillation can be
achieved.
However, in this case, the XT1 oscillation margin is reduced, so
perform sufficient oscillation evaluation of the resonator to be used for XT1
oscillation before using the resonator.
• Keep the wiring length between the XT1 and XT2 pins and resonator as short as
possible and parasitic capacitance and wire resistance as small as possible. This
is particularly important when super-low-consumption oscillation (AMPHS1 = 1) is
selected.
• Configure the circuit board by using material with little parasitic capacitance and
wire resistance.
• Place a ground pattern that has the same potential as VSS (if possible) around the
XT1 oscillator.
• Do not cross the signal lines between the XT1 and XT2 pins and the resonator
with other signal lines. Do not route the signal lines near a signal line through
which a high fluctuating current flows.
• Moisture absorption by the circuit board and condensation on the board in a
highly humid environment may cause the impedance between the XT1 and XT2
pins to drop and disable oscillation. When using the circuit board in such an
environment, prevent the circuit board from absorbing moisture by taking
measures such as coating the circuit board.
• Coat the surface of the circuit board by using material that does not generate
Soft
capacitance or leakage between the XT1 and XT2 pins.
CSC: Clock
After reset release, set the clock operation mode control register (CMC) before p.211
operation status
starting X1 oscillation as set by MSTOP or XT1 oscillation as set by XTSTOP.
control register
To start X1 oscillation as set by MSTOP, check the oscillation stabilization time of the p.212
X1 clock by using the oscillation stabilization time counter status register (OSTC).
Do not stop the clock selected for the CPU peripheral hardware clock (fCLK) with the p.212
CSC register.
The setting of the flags of the register to stop clock oscillation (invalidate the external p.212
clock input) and the condition before clock oscillation is to be stopped are as follows.
OSTC:
After the above time has elapsed, the bits are set to 1 in order from MOST8 and p.213
Oscillation
remain 1.
stabilization time The oscillation stabilization time counter counts up to the oscillation stabilization time p.213
counter status
set by OSTS. In the following cases, set the oscillation stabilization time of OSTS to
register
the value greater than the count value which is to be checked by the OSTC register
after the oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
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Function
Clock
OSTC:
The X1 clock oscillation stabilization wait time does not include the time until clock p.213
generator
Oscillation
oscillation starts (“a” below).
stabilization time
counter status
Soft
register
OSTS:
To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS p.214
Oscillation
register before executing the STOP instruction.
stabilization time Setting the oscillation stabilization time to 20 μs or less is prohibited.
p.214
select register
To change the setting of the OSTS register, be sure to confirm that the counting p.214
operation of the OSTC register has been completed.
Do not change the value of the OSTS register during the X1 clock oscillation p.214
Soft Hard
stabilization time.
The oscillation stabilization time counter counts up to the oscillation stabilization time p.214
set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than the count value which is to be checked by the OSTC register after the
oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
The X1 clock oscillation stabilization wait time does not include the time until clock p.214
CKC: System
clock control
Soft
Hard
register
DSCCTL: 20
MHz internal
high-speed
oscillation
control register
OSMC:
oscillation starts (“a” below).
The clock set by CSS, MCM0, SDIV, and MDIV2 to MDIV0 is supplied to the CPU p.216
and peripheral hardware. If the CPU clock is changed, therefore, the clock supplied
to peripheral hardware (except the real-time counter, timer array unit (when fSUB/2,
fSUB/4, the valid edge of TI0mn input, or the valid edge of INTRTCI is selected as the
count clock), clock output/buzzer output, and watchdog timer) is also changed at the
same time. Consequently, stop each peripheral function when changing the
CPU/peripheral operating hardware clock.
If the peripheral hardware clock is used as the subsystem clock, the operations of the p.216
A/D converter and IICA are not guaranteed. For the operating characteristics of the
peripheral hardware, refer to the chapters describing the various peripheral hardware
as well as CHAPTER 31 ELECTRICAL SPECIFICATIONS.
20 MHz internal oscillation can only be used if VDD ≥ 2.7 V.
p.218
Set SELDSC when 100 μs have elapsed after having set DSCON with VDD ≥ 2.7 V.
p.218
The internal high-speed oscillator must be operated (HIOSTOP = 0) when DSCON = 1. p.218
p.221
p.221
To increase fCLK to 10 MHz or higher, set FSEL to “1”, then change fCLK after two or p.221
Write “1” to FSEL before the following two operations.
Operation speed • Changing the clock prior to dividing fCLK to a clock other than fIH.
mode control
• Operating the DMA controller.
register
The CPU waits (140.5 clock (fCLK)) when “1” is written to the FSEL bit.
Interrupt requests issued during a wait will be suspended.
However, counting the oscillation stabilization time of fX can continue even while the
CPU is waiting.
more clocks have elapsed.
Confirm that the clock is operating at 10 MHz or less before setting FSEL = 0.
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Function
To shift to STOP mode while VDD ≤ 2.7 V, set FSEL = 0 after setting fCLK to 10 MHz or p.221
Clock
OSMC:
generator
Operation speed less.
mode control
The HALT mode current when operating on the subsystem clock can be reduced by p.221
register
setting RTCLPC to 1. However, the clock cannot be supplied to peripheral functions
except the real-time counter in the subsystem clock HALT mode. Set bit 7 (RTCEN)
of PER0 to 1 and bits 0 to 6 of PER0 to 0 before setting the subsystem clock HALT
mode.
Once FLPC has been set from 0 to 1, setting it back to 0 from 1 other than by reset is p.221
prohibited.
p.221
When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed p.223
When setting FSEL to “1”, do so while RMC = 00H.
Hard
When setting FLPC to “1”, do so while RMC = 5AH.
X1/XT1
−
oscillator
by the broken lines in the Figures 5-10 and 5-11 to avoid an adverse effect from
wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a
signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Note that the XT1 oscillator is designed as a low-gain circuit for achieving low-power
consumption. Note the following points when designing the XT1 oscillator.
• The pins and circuit board include parasitic capacitance. Therefore, confirm that
there are no problems by performing oscillation evaluation on the circuit board to
be actually used.
• When low-consumption oscillation or super-low-consumption oscillation is selected,
lower power consumption than when selecting normal oscillation can be achieved.
However, in this case, the XT1 oscillation margin is reduced, so perform sufficient
oscillation evaluation of the resonator to be used for XT1 oscillation before using
the resonator.
• Keep the wiring length between the XT1 and XT2 pins and resonator as short as
possible and parasitic capacitance and wire resistance as small as possible. This
is particularly important when super-low-consumption oscillation (AMPHS1 = 1) is
selected.
• Configure the circuit board by using material with little parasitic capacitance and
wire resistance.
• Place a ground pattern that has the same potential as VSS (if possible) around the
XT1 oscillator.
• Do not cross the signal lines between the XT1 and XT2 pins and the resonator with
other signal lines. Do not route the signal lines near a signal line through which a
high fluctuating current flows.
• Moisture absorption by the circuit board and condensation on the board in a highly
humid environment may cause the impedance between the XT1 and XT2 pins to
drop and disable oscillation. When using the circuit board in such an environment,
prevent the circuit board from absorbing moisture by taking measures such as
coating the circuit board.
• Coat the surface of the circuit board by using material that does not generate
capacitance or leakage between the XT1 and XT2 pins.
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Function
−
X1/XT1
oscillator
When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with p.225
XT1, resulting in malfunctioning.
−
Internal
To use the 1, 8, or 20 MHz internal high-speed oscillation clock, use the option byte p.226
high-
to set the frequency in advance (for details, see CHAPTER 26 OPTION BYTE).
speed
Also, the internal high-speed oscillator automatically starts oscillating after reset
oscillator
release. (If 8 MHz or 20 MHz is selected by using the option byte, the microcontroller
operates using the 8 MHz internal high-speed oscillator.) To use the 20 MHz internal
high-speed oscillator to operate the microcontroller, oscillation is started by setting bit
0 (DSCON) of the DSCCTL register to 1 with VDD ≥ 2.7 V.
Clock
When LVI
If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application p.229
generator
default start
until the voltage reaches 1.8 V, input a low level to the RESET pin from power
operation
function stopped application until the voltage reaches 1.8 V, or set the LVI default start function
when
is set (option
stopped by using the option byte (LVIOFF = 0) (see Figure 5-14). By doing so, the
power
byte: LVIOFF =
CPU operates with the same timing as and thereafter in Figure 5-13 after reset
supply
1)
release by the RESET pin.
voltage is
It is not necessary to wait for the oscillation stabilization time when an external clock p.229
turned on
input from the EXCLK pin is used.
When LVI
A voltage stabilization time (about 2.12 to 5.84 ms) is required after the supply p.231
default start
voltage reaches 1.61 V (TYP.). If the time for the supply voltage to rise from 1.61 V
Soft
function enabled (TYP.) to 2.07 V (TYP.) is shorter than the voltage stabilization time, reset processing
is set (option
is entered after the voltage stabilization time elapses.
byte: LVIOFF =
It is not necessary to wait for the oscillation stabilization time when an external clock p.231
0)
input from the EXCLK pin is used.
Controlling X1/P121,
The X1/P121 and X2/EXCLK/P122 pins are in the input port mode after a reset p.232
high-
X2/EXCLK/P122 release.
speed
X1 clock
The CMC register can be written only once after reset release, by an 8-bit memory p.232
system
manipulation instruction.
clock
OSCSELS bit at the same time. For OSCSELS bit, see 5.6.3 Example of controlling
Therefore, it is necessary to also set the value of the
subsystem clock.
Set the X1 clock after the supply voltage has reached the operable voltage of the p.232
clock to be used (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
External main
The CMC register can be written only once after reset release, by an 8-bit memory p.233
system clock
manipulation instruction.
Therefore, it is necessary to also set the value of the
OSCSELS bits at the same time.
For OSCSELS bits, see 5.6.3 Example of
controlling subsystem clock.
Set the external main system clock after the supply voltage has reached the operable p.233
voltage
of
the
clock
to
be
used
(see
CHAPTER
31
ELECTRICAL
SPECIFICATIONS).
High-speed
Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, p.235
system clock
stop peripheral hardware that is operating on the high-speed system clock.
Controlling Internal high-
If switching the CPU/peripheral hardware clock from the high-speed system clock to p.236
internal
speed oscillation the internal high-speed oscillation clock after restarting the internal high-speed
high-
clock
oscillation clock, do so after 10 μs or more have elapsed.
speed
If the switching is made immediately after the internal high-speed oscillation clock is
oscillation
restarted, the accuracy of the internal high-speed oscillation cannot be guaranteed
clock
for 10 μs.
Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition, p.237
stop peripheral hardware that is operating on the internal high-speed oscillation clock.
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Function
Soft
Classification
Function
Subsystem XT1/P123,
clock
XT2/P124
Hard
Chapter 5
Chapter
(10/39)
control
Subsystem clock When the subsystem clock is used as the CPU clock, the subsystem clock is also pp.237,
The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release.
p.237
supplied to the peripheral hardware (except the real-time counter, timer array unit 238
(when fSUB/2, fSUB/4, the valid edge of TI0mn input, or the valid edge of INTRTCI is
selected as the count clock), clock output/buzzer output, and watchdog timer). At
this time, the operations of the A/D converter and IICA are not guaranteed. For the
operating characteristics of the peripheral hardware, refer to the chapters describing
the various peripheral hardware as well as CHAPTER 31 ELECTRICAL
Soft
SPECIFICATIONS.
The CMC register can be written only once after reset release, by an 8-bit memory p.238
manipulation instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the
same time.
For EXCLK and OSCSEL bits, see 5.6.1 (1) Example of setting
procedure when oscillating the X1 clock or 5.6.1 (2) Example of setting procedure
when using the external main system clock.
Be sure to confirm that CLS = 0 when setting XTSTOP to 1. In addition, stop the p.238
peripheral hardware if it is operating on the subsystem clock.
The subsystem clock oscillation cannot be stopped using the STOP instruction.
CPU clock
p.238
−
Set the clock after the supply voltage has reached the operable voltage of the clock pp.241
to be set (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
242, 245
−
Channel 5 of timer array unit 0 of the 78K0R/LF3 can be used only as an interval p.251
status
Soft
Chapter 6
transition
Timer
array unit
timer.
Channel 6 of timer array unit 0 of the 78K0R/LF3 can be used only as an interval p.251
timer, for PWM output (master channel), and for one-shot pulse output (master
channel when software trigger start is selected).
Channels 0 to 3 of timer array unit 1 of the 78K0R/LF3 and 78K0R/LG3 can be used p.251
only as interval timers.
Channels 1, 5 to 7 of timer array unit 0 and channels 0 to 3 of timer array unit 1 p.251
cannot be used as frequency dividers.
p.255
TDRmn: Timer
TDRmn does not perform a capture operation even if a capture trigger is input, when p.260
data register mn
it is set to the compare function.
PER0:
When setting the timer array unit, be sure to set TAUmEN to 1 first. If TAUmEN = 0, p.262
Peripheral
writing to a control register of the timer array unit is ignored, and all read values are
TCRmn:
The count value is not captured to TDRmn even when TCRmn is read.
Timer/counter
register mn
enable register 0 default values.
TPSm: Timer
Be sure to clear bits 15 to 8 to “0”.
p.268
clock select
register m
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Function
Timer
TMRmn: Timer
array unit
mode register
mn
Be sure to clear bits 14, 13, 5, and 4 to “0”.
pp.264
to 266
Channel 5 of timer array unit 0 and channels 0 to 3 of timer array unit 1 of the
pp.266,
271
78K0R/LF3 can be set only to the interval mode.
Channel 6 of timer array unit 0 of the 78K0R/LF3 can be set only to the interval mode pp.266,
and one-count mode (when using as master).
271
Channels 0 to 3 of timer array unit 1 of the 78K0R/LG3 can be set only to the interval pp.266,
mode.
271
p.270
Start Timing (In
In the first cycle operation of count clock after writing TSmn, an error at a maximum p.272
Interval Timer
of one clock is generated since count start delays until count clock has been
Mode)
generated. When the information on count start timing is necessary, an interrupt can
TSm: Timer
Be sure to clear bits 15 to 8 of TS0 and bits 15 to 4 of TS1 to “0”.
channel start
register m
be generated at count start by setting MDmn0 = 1.
Start Timing (In
In the first cycle operation of count clock after writing TSpq, an error at a maximum of p.273
Capture Mode)
one clock is generated since count start delays until count clock has been generated.
When the information on count start timing is necessary, an interrupt can be
generated at count start by setting MDpq0 = 1.
Start Timing (In An input signal sampling error is generated since operation starts upon start trigger pp.275,
One-count Mode detection (The error is one count clock when TIpq is used).
276
and In Capture &
One-count
Mode)
p.277
TISp: Timer
When the LIN-bus communication function is used, select the input signal of the p.279
input select
RxD3 pin by setting ISC1 to 1 and TIS07 = 0.
TTm: Timer
Be sure to clear bits 15 to 8 of TT0 and bits 15 to 4 of TT1 to “0”.
channel stop
register m
register p
TOEp: Timer
For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOE0 to “0”.
p.279
output enable
For 78K0R/LG3, be sure to clear bits 15 to 8 of TOE0 to “0”.
p.279
register p
For 78K0R/LH3, be sure to clear bit 15 to 8 of TOE0, bits 15 to 4 of TOE1 to “0”.
p.279
TOp: Timer
For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TO0 to “0”.
p.280
output register p
For 78K0R/LG3, be sure to clear bits 15 to 8 of TO0 to “0”.
p.280
For 78K0R/LH3, be sure to clear bit 15 to 8 of TO0, bits 15 to 4 of TO1 to “0”.
p.280
TOLp: Timer
For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOL0 to “0”.
p.281
output level
For 78K0R/LG3, be sure to clear bits 15 to 8 of TOL0 to “0”.
p.281
register p
For 78K0R/LH3, be sure to clear bit 15 to 8 of TOL0, bits 15 to 4 of TOL1 to “0”.
p.281
TOMp: Timer
For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOM0 to “0”.
p.282
output mode
For 78K0R/LG3, be sure to clear bits 15 to 8 of TOM0 to “0”.
p.282
register p
For 78K0R/LH3, be sure to clear bit 15 to 8 of TOM0, bits 15 to 4 of TOM1 to “0”.
p.282
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Chapter 6
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Function
Details of
Cautions
Page
Function
p.283
Changing values Since the timer operations (operations of TCRpq and TDRpq) are independent of the p.291
set in registers
TOpq output circuit and changing the values set in TOp, TOEp, TOLp, and TOMp
TOp,TOEp,
does not affect the timer operation, the values can be changed during timer
Timer
ISC: Input switch Be sure to clear bits 5 to 7 to “0”.
array unit
control register
TOLp, and
operation. To output an expected waveform from the TOpq pin by timer operation,
TOMp during
however, set TOp, TOEp, TOLp, and TOMp to the values stated in the register setting
timer operation
example of each operation.
When the values set in TOEp, TOLp, and TOMp (except for TOp) are changed close
to the timer interrupt (INTTMpq), the waveform output to the TOpq pin may be
different depending on whether the values are changed immediately before or
immediately after the timer interrupt (INTTMpq) signal generation timing.
TOpq pin and
The following figure shows the TOpq pin output level transition when writing has pp.291,
been done in the state of TOEpq = 0 before port output is enabled and TOEpq = 1 is 292
output level after
set after changing the default level.
timer operation
(a) When operation starts with TOMpq = 0 setting (toggle output)
Default level of
start
The setting of TOLpq is invalid when TOMpq = 0. When the timer operation
starts after setting the default level, the toggle signal is generated and the output
level of TOpq pin is reversed.
(b) When operation starts with TOMpq = 1 setting (Combination operation mode
(PWM output))
When TOMpq = 1, the active level is determined by TOLpq setting.
Operation of
(a) When TOLpq setting has been changed during timer operation
pp.291,
TOpq pin in
When the TOLpq setting has been changed during timer operation, the setting 293
combination
becomes valid at the generation timing of TOpq change condition. Rewriting
operation mode
TOLpq does not change the output level of TOpq.
(TOMpq = 1)
The following figure (Figure 6-30) shows the operation when the value of TOLpq
has been changed during timer operation (TOMpq = 1)
(b) Set/reset timing
To realize 0%/100% output at PWM output, the TOpq pin/TOpq set timing at
master channel timer interrupt (INTTMpq) generation is delayed by 1 count clock
by the slave channel timer interrupt (INTTMqr).
If the set condition and reset condition are generated at the same time, a higher
priority is given to the latter.
Figure 6-31 shows the set/reset operating statuses where the master/slave
channels are set as follows.
Collective
When TOEpq = 1, even if the output by timer interrupt of each timer (INTTMpq)
manipulation of
contends with writing to TOpq, output is normally done to TOpq pin.
p.295
TOpq bits
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Function
Operation of Input pulse
The TIpq pin input is sampled using the operating clock selected with the CKSpq bit
timer array
interval
of the TMRpq register, so an error equal to the number of operating clocks occurs.
unit as
measurement
independent Input signal
channel
high-/low-level
The TIpq pin input is sampled using the operating clock selected with the CKSpq bit
p.315
p.319
p.323
p.330
p.337
p.348
p.348
p.349
of the TMRpq register, so an error equal to the number of operating clocks occurs.
width
measurement
Operation
PWM function
To rewrite both TDRmn of the master channel and TDRmp of the slave channel, a
of plural
write access is necessary two times. The timing at which the values of TDRmn and
channels of
TDRmp are loaded to TCRmn and TCRmp is upon occurrence of INTTMmn of the
timer array
master channel. Thus, when rewriting is performed split before and after occurrence
unit
of INTTMmn of the master channel, the TOmp pin cannot output the expected
waveform. To rewrite both TDRmn of the master and TDRmp of the slave, therefore,
be sure to rewrite both the registers immediately after INTTMmn is generated from
the master channel.
One-shot pulse
The timing of loading of TDRmn of the master channel is different from that of
output function
TDRmp of the slave channel. If TDRmn and TDRmp are rewritten during operation,
therefore, an illegal waveform is output. Be sure to rewrite TDRmn and TDRmp after
INTTMmn of the channel to be rewritten is generated.
Multiple PWM
To rewrite both TDRmn of the master channel and TDRmp of the slave channel 1,
output function
write access is necessary at least twice. Since the values of TDRmn and TDRmp
are loaded to TCRmn and TCRmp after INTTMmn is generated from the master
channel, if rewriting is performed separately before and after generation of INTTMmn
from the master channel, the TOmp pin cannot output the expected waveform. To
rewrite both TDRmn of the master and TDRmp of the slave, be sure to rewrite both
the registers immediately after INTTMmn is generated from the master channel (This
Soft
Chapter 7
applies also to TDRmq of the slave channel 2).
Real-time
PER0:
When using the real-time counter, first set RTCEN to 1, while oscillation of the
counter
Peripheral
subsystem clock (fSUB) is stable. If RTCEN = 0, writing to a control register of the real-
enable register 0 time counter is ignored, and, even if the register is read, only the default value is read.
Clock supply to peripheral functions except the real-time counter can be stopped in
the HALT mode when operating on the subsystem clock by setting RTCLPC of the
operation speed mode control register (OSMC) to 1. In this case, set RTCEN to 1
and bits 0 to 6 of PER0 to 0.
RTCC0: Real-
If RCLOE0 and RCLOE1 are changed when RTCE = 1, the last waveform of the
time counter
32.768 kHz and 1 Hz output signals may become short.
control register 0
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Chapter 7
Chapter
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Real-time
RTCC1: Real-
If writing is performed to the RTCC1 register with a 1-bit manipulation instruction, the
counter
time counter
RIFG and WAFG flags may be cleared. Therefore, to perform writing to the RIFG and
Page
Function
p.351
control register 1 WAFG flags, be sure to use an 8-bit manipulation instruction. At this time, set 1 to the
RIFG and WAFG flags to invalidate writing and not to clear the RIFG and WAFG flags
during writing. When the value may be rewritten because the RIFG and WAFG flags
are not being used, the RTCC1 register may be written by using a 1-bit manipulation
Hard
instruction.
RTCC2: Real-
Change ICT2, ICT1, and ICT0 when RINTE = 0.
time counter
When the output from RTCDIV pin is stopped, the output continues after a maximum
p.352
p.352
control register 2 of two clocks of fXT and enters the low level. While 512 Hz is output, and when the
output is stopped immediately after entering the high level, a pulse of at least one
Soft
clock width of fSUB may be generated.
After the real-time counter starts operating, the output width of the RTCDIV pin may
p.352
RSUBC: Sub-
be shorter than as set during the first interval period.
When a correction is made by using the SUBCUD register, the value may become
p.353
count register
8000H or more.
This register is also cleared by reset effected by writing the second count register.
The value read from this register is not guaranteed if it is read during operation,
p.353
p.353
because a value that is changing is read.
HOUR: Hour
Bit 5 (HOUR20) of HOUR indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system
count register
is selected).
WEEK: Week
The value corresponding to the month count register or the day count register is not
count register
stored in the week count register automatically. After reset release, set the week
ALARMWM:
Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the
Alarm minute
range is set, the alarm is not detected.
p.354
p.356
count register as follow.
p.359
register
Alarm hour
Set a decimal value of 00 to 23, or 01 to 12 and 21 to 32 to this register in BCD code. p.359
If a value outside the range is set, the alarm is not detected.
register
Bit 5 (WH20) of ALARMWH indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour
ALARMWH:
p.359
system is selected).
Reading/writing
Complete the series of operations of setting RWAIT to 1 to clearing RWAIT to 0 within pp.364
, 365
Soft
Chapter 8
real-time counter 1 second.
Watchdog
WDTE:
If a value other than “ACH” is written to WDTE, an internal reset signal is generated.
timer
Watchdog timer
If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
enable register
signal is generated.
The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)).
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Watchdog
Controlling
When data is written to WDTE for the first time after reset release, the watchdog timer p.377
timer
operation
is cleared in any timing regardless of the window open time, as long as the register is
Function
written before the overflow time, and the watchdog timer starts counting again.
p.377
The watchdog timer can be cleared immediately before the count value overflows.
p.377
The operation of the watchdog timer in the HALT and STOP modes differs as follows
p.378
p.378
Setting overflow
The watchdog timer continues its operation during self-programming of the flash p.378
time
memory and EEPROM emulation. During processing, the interrupt acknowledge time
If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow time
may be different from the overflow time set by the option byte by up to 2/fIL seconds.
depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). (See
the table on page 378.)
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP
mode is released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU
starts operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer
overflow is short, an overflow occurs during the oscillation stabilization time, causing
a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization
time when operating with the X1 oscillation clock and when the watchdog timer is to
be cleared after the STOP mode release by an interval interrupt.
The watchdog timer continues its operation during self-programming of the flash
memory and EEPROM emulation. During processing, the interrupt acknowledge time
is delayed. Set the overflow time and window size taking this delay into
consideration.
is delayed.
Set the overflow time and window size taking this delay into
consideration.
Setting window
When data is written to WDTE for the first time after reset release, the watchdog p.379
open period
timer is cleared in any timing regardless of the window open time, as long as the
register is written before the overflow time, and the watchdog timer starts counting
again.
The watchdog timer continues its operation during self-programming of the flash p.379
memory and EEPROM emulation.
time is delayed.
During processing, the interrupt acknowledge
Set the overflow time and window size taking this delay into
consideration.
When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period p.379
is 100% regardless of the values of WINDOW1 and WINDOW0.
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Watchdog
Setting interval
When operating with the X1 oscillation clock after releasing the STOP mode, the
timer
interrupt
CPU starts operating after the oscillation stabilization time has elapsed.
Page
Function
p.380
Therefore, if the period between the STOP mode release and the watchdog timer
overflow is short, an overflow occurs during the oscillation stabilization time, causing
a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization
time when operating with the X1 oscillation clock and when the watchdog timer is to
Soft
Chapter 9
be cleared after the STOP mode release by an interval interrupt.
p.383
Clock
CKSn: Clock
Change the output clock after disabling clock output (PCLOEn = 0).
output/
output select
buzzer
registers n
If the selected clock (fMAIN or fSUB) stops during clock output (PCLOEn = 1), the output p.383
becomes undefined.
To shift to STOP mode when the main system clock is selected (CSELn = 0), set p.383
PCLOEn = 0 before executing the STOP instruction. When the subsystem clock is
output
controller
selected (CSELn = 1), PCLOEn = 1 can be set because the clock can be output in
Soft
Chapter 10
STOP mode.
A/D
PER0:
When setting the A/D converter, be sure to set ADCEN to 1 first. If ADCEN = 0, p.390
converter
Peripheral
writing to a control register of the A/D converter is ignored, and, even if the register is
enable register 0 read, only the default value is read.
ADM: A/D
converter mode
register
A/D conversion must be stopped before rewriting bits ADSCM, FR0 to FR2, LV1, and p.392
LV0 to values other than the identical data.
When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage pp.392
mode (LV1 = 1, LV0 = 0), enable the input gate voltage boost circuit for the A/D , 393
converter by using the analog reference voltage control register (ADVRC), and then
set ADCE and ADCS to 1. After the voltage boost circuit stabilization time (10 μs)
passes after the input gate voltage boost circuit for the A/D converter has been
enabled, set ADCS to 1.
ADM1: A/D
Rewriting ADM1 during A/D conversion is prohibited. Rewrite it when conversion
converter mode
operation is stopped (ADCS = 0).
p.394
register 1
ADVRC: Analog
When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage
reference
mode (LV1 = 1, LV0 = 0), enable the input gate voltage boost circuit for the A/D
voltage control
converter by using the analog reference voltage control register (ADVRC), and then
register
p.395
set ADCE and ADCS to 1. After the voltage boost circuit stabilization time (10 μs)
passes after the input gate voltage boost circuit for the A/D converter has been
enabled, set ADCS to 1.
To use voltage reference output to the positive reference voltage of the A/D
p.396
converter, be sure to set VRON to 1 after setting VRSEL to 1.
Do not change the output voltage of the reference voltage by using VRGV during the
p.396
voltage reference operation (VRON = 1).
A/D conversion
When writing to A/D converter mode register (ADM), analog input channel p.396
specification register (ADS), and A/D port configuration register (ADPC), the contents
result register
of ADCR may become undefined. Read the conversion result following conversion
ADCR: 12-bit
completion before writing to ADM, ADS, and ADPC. Using timing other than the
above may cause an incorrect conversion result to be read.
A/D conversion
When writing to A/D converter mode register (ADM), analog input channel p.397
specification register (ADS), and A/D port configuration register (ADPC), the contents
result register
of ADCRH may become undefined. Read the conversion result following conversion
ADCRH: 8-bit
completion before writing to ADM, ADS, and ADPC. Using timing other than the
above may cause an incorrect conversion result to be read.
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Function
p.398
A/D
ADS: Analog
Be sure to clear bits 4 to 7 to “0”.
converter
input channel
specification
Set a channel to be used for A/D conversion in the input mode by using port mode p.398
registers 2 and 15 (PM2, PM15).
register
Do not set the pin that is set by ADPC as digital I/O by ADS.
p.398
When using an operational amplifier n, the output signal of an operational amplifier n p.398
can be used as an analog input.
configuration
Set a channel to be used for A/D conversion in the input mode by using port mode p.399
registers 2 and 15 (PM2, PM15).
register
Do not set the pin that is set by ADPC as digital I/O by ADS.
PM2, PM15:
If a pin is set as an analog input port, not the pin level but “0” is always read.
Port mode
registers 2 and
When an operational amplifier is used, pins AMPn+, AMPn−, and AMPnO are used, p.401
so the alternative analog input functions cannot be used. The operational amplifier
15
output signals, however, can be used as analog inputs.
ADPC: A/D port
Basic operations Make sure the period of to is 1 μs or more.
of A/D converter
p.399
p.400
p.404
To use an operational amplifier output for an analog input, start operating the p.404
operational amplifier before setting the A/D conversion operation (see CHAPTER 12
OPERATIONAL AMPLIFIER). Furthermore, do not change the operational amplifier
setting during the A/D conversion operation.
To use an output voltage of the voltage reference for a positive reference voltage of p.404
the A/D converter, start operating the voltage reference before setting the A/D
conversion operation (see CHAPTER 13 VOLTAGE REFERENCE). Furthermore, do
not change the voltage reference setting during the A/D conversion operation.
When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage p.404
mode (LV1 = 1, LV0 = 0), enable the input gate voltage boost circuit for the A/D
converter by using the analog reference voltage control register (ADVRC), and then
set ADCE and ADCS to 1. After the voltage boost circuit stabilization time (10 μs)
passes after the input gate voltage boost circuit for the A/D converter has been
enabled, set ADCS to 1.
A/D conversion
Make sure the period of to is 1 μs or more.
operation
may be done between and .
p.411
p.411
can be omitted. However, ignore data of the first conversion after in this p.411
case.
The period from to differs from the conversion time set using bits 5 to 1 p.411
(FR2 to FR0, LV1, LV0) of ADM. The period from to is the conversion
time set using FR2 to FR0, LV1, and LV0.
To use an operational amplifier output for an analog input, start operating the p.411
operational amplifier before setting the A/D conversion operation (see CHAPTER 12
OPERATIONAL AMPLIFIER). Furthermore, do not change the operational amplifier
setting during the A/D conversion operation.
To use an output voltage of the voltage reference for a positive reference voltage of p.411
the A/D converter, start operating the voltage reference before setting the A/D
conversion operation (see CHAPTER 13 VOLTAGE REFERENCE). Furthermore, do
not change the voltage reference setting during the A/D conversion operation.
When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage p.411
mode (LV1 = 1, LV0 = 0), enable the input gate voltage boost circuit for the A/D
converter by using the analog reference voltage control register (ADVRC), and then
set ADCE and ADCS to 1. After the voltage boost circuit stabilization time (10 μs)
passes after the input gate voltage boost circuit for the A/D converter has been
enabled, set ADCS to 1.
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Function
A/D
Operating
Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of the
converter
current in STOP
A/D converter mode register (ADM) to 0). The operating current can be reduced by
mode
setting bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 at the same time.
p.414
When using normal mode 2 (LV1 = 0, LV0 = 1) or low voltage mode (LV1 = 1, LV0 =
0), clear bit 1 (VRGV) and bit 0 (VRON) of the analog reference voltage control
register (ADVRC) to 0, and then shift to STOP mode.
To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register
Hard
1L (IF1L) to 0 and start operation.
ANI0 to ANI10,
Observe the rated range of the ANI0 to ANI10, ANI15 input voltage. If a voltage of p.414
AVDD0 or higher and AVSS or lower (even in the range of absolute maximum ratings)
ANI15
is input to an analog input channel, the converted value of that channel becomes
Input range of
undefined. In addition, the converted values of the other channels may also be
Soft
affected.
Conflicting
Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR or
operations
ADCRH read by instruction upon the end of conversion
p.414
ADCR or ADCRH read has priority. After the read operation, the new conversion
result is written to ADCR or ADCRH.
Conflict between ADCR or ADCRH write and A/D converter mode register (ADM) p.414
write, analog input channel specification register (ADS), or A/D port configuration
register (ADPC) write upon the end of conversion
ADM, ADS, or ADPC write has priority. ADCR or ADCRH write is not performed, nor
Hard
is the conversion end interrupt signal (INTAD) generated.
Noise
To maintain the 12-bit resolution, attention must be paid to noise input to the AVREFP p.414
countermeasures pin and pins ANI0 to ANI10, ANI15.
Connect a capacitor with a low equivalent resistance and a good frequency
response to the power supply.
The higher the output impedance of the analog input source, the greater the
influence. To reduce the noise, connecting external C as shown in Figure 10-28
is recommended.
Do not switch these pins with other pins during conversion.
The accuracy is improved if the HALT mode is set immediately after the start of
Soft
conversion.
ANI0 to ANI10,
The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27).
ANI15
The analog input pins (ANI8 to ANI10, ANI15) are also used as input port pins (P150
p.415
to P152, P157).
When A/D conversion is performed with any of ANI0 to ANI10, and ANI15 selected,
do not access P20 to P27, P150 to P152, and P157 while conversion is in progress;
otherwise the conversion resolution may be degraded. It is recommended to select
pins used as P20 to P27, P150 to P152, and P157 starting with the ANI0/P20 that is
Hard
the furthest from AVDD0.
If the pins adjacent to the pins currently used for A/D conversion are used as digital p.415
I/O port, the expected value of the A/D conversion may not be obtained due to
coupling noise. Therefore, make sure that digital pulses are not input to or output
from the pins adjacent to the pin undergoing A/D conversion.
If any pin among pins of ports 2 and 15 is used as digital output port during A/D p.415
conversion, the expected value of the A/D conversion may not be obtained due to
coupling noise. Therefore, make sure that digital pulses are not output to pins of
ports 2 and 15 during A/D conversion.
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Chapter 10
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Details of
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Page
Function
A/D
Input impedance This A/D converter charges a sampling capacitor for sampling during sampling time.
converter
of ANI0 to
Therefore, only a leakage current flows when sampling is not in progress, and a
ANI10, ANI15
current that charges the capacitor flows during sampling. Consequently, the input
pins
impedance fluctuates depending on whether sampling is in progress, and on the
p.415
other states.
To make sure that sampling is effective, however, it is recommended to keep the
output impedance of the analog input source to within 1 kΩ, and to connect a
capacitor of about 100 pF to the ANI0 to ANI10 and ANI15 pins (see Figure 10-28).
AVREFP pin input
impedance
A series resistor string of several tens of kΩ is connected between the AVREFP and p.416
AVREFM (or AVSS) pins.
Therefore, if the output impedance of the reference voltage supply is high, this will
result in a series connection to the series resistor string between the AVREFP and
AVREFM (or AVSS) pins, resulting in a large reference voltage (AVREF) error of A/D
Soft
converter.
Interrupt request The interrupt request flag (ADIF) is not cleared even if the analog input channel p.416
flag (ADIF)
specification register (ADS) is changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D
conversion result and ADIF for the pre-change analog input may be set just before
the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read
immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the
post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D
conversion operation is resumed.
results just after
The first A/D conversion value immediately after A/D conversion starts may not fall p.416
within the rating range if the ADCS bit is set to 1 within 1 μs after the ADCE bit was
A/D conversion
set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as
start
polling the A/D conversion end interrupt request (INTAD) and removing the first
Conversion
A/D conversion
result register
(ADCR,
ADCRH) read
operation
conversion result.
When a write operation is performed to A/D converter mode register (ADM), A/D p.417
converter mode register 1 (ADM1), analog input channel specification register (ADS),
and A/D port configuration register (ADPC), the contents of ADCR and ADCRH may
become undefined. Read the conversion result following conversion completion
before writing to ADM, ADM1, ADS, or ADPC. Using a timing other than the above
may cause an incorrect conversion result to be read.
The equivalent circuit of the analog input block is shown below. (See Figure 10-30.) p.417
Internal
equivalent circuit
Rewriting DACSWn (n = 0, 1) during A/D conversion is prohibited when both the p.417
Rewriting
DACSWn during positive reference voltage of A/D converter (ADREFP) and the positive reference
A/D conversion voltage of the D/A converter (DAREF) are the voltage reference output (VREFOUT)
(VRSEL = 1 and DAREF = 1). Rewrite it when conversion operation is stopped
(ADCS = 0).
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Chapter 11
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Function
D/A
converter
PER0:
Peripheral
enable register 0
DACSW0,
DACSW1: D/A
conversion value
setting registers
W0 and W1
Operation of D/A
Converter
Operation in
normal mode
Operation in
real-time output
mode
When setting the D/A converter, be sure to set DACEN to 1 first. If DACEN = 0, p.420
writing to a control register of the D/A converter is ignored, and, even if the register is
read, only the default value is read.
Rewriting DACSWn during A/D conversion is prohibited when both the positive pp.422
reference voltage of the A/D converter (ADREFP) and the positive reference voltage of , 424
the D/A converter (DAREF) are the voltage reference output (VREFOUT) (VRSEL = 1 and
DAREF = 1). Rewrite it when conversion operation is stopped (ADCS = 0).
Even if 1, 0, and then 1 is set to the DACEn bit, there is a wait after 1 is set for the pp.423
last time.
, 424
If the DACSWn or DACSn register is rewritten during the settling time, D/A p.423
conversion is aborted and reconversion by using the rewritten values starts.
Make the interval between each generation of the INTTM0m signal longer than the p.424
settling time. If an INTTM0m signal is generated during the settling time, D/A
conversion is aborted and reconversion starts.
Even if the generation of the INTTM0m signal and rewriting the DACSWn or DACSn p.424
register conflict, the D/A conversion result is output.
The digital port I/O function, which is the alternate function of the ANO0 and ANO1 p.424
pins, does not operate during D/A conversion.
When the P11 register is read during D/A conversion, 0 is read in input mode and the
set value of the P11 register is read in output mode. If the digital output mode is set,
no output data is output to pins.
Soft
Chapter 12
Digital port I/O
function, which
is the alternate
function of the
ANO0, ANO1
pins
Operation of the The operation of the D/A converter continues in the HALT and STOP mode. To lower p.424
the power consumption, therefore, clear the DACEn bit of the DAM register to 0 (D/A
D/A converter
continues in the conversion stop), and execute HALT or STOP instruction.
HALT and STOP
mode
Operational PER0:
When setting operational amplifier, be sure to set ADCEN to 1 first. If ADCEN = 0, p.427
amplifier
writing to a control register of operational amplifier is ignored, and, even if the register
Peripheral
enable register 0 is read, only the default value is read.
OAC:
Use the ADPC register to specify as analog inputs the pins to be used with p.428
Operational
operational amplifiers.
amplifier control
When using as digital inputs the pins of ports 2 and 15, which are not used with p.428
register
operational amplifiers, when the operational amplifiers are used, make sure that the
input levels are fixed.
ADPC: A/D port
Set pins to be used with operational amplifiers in the input mode by using port mode p.429
configuration
registers 2 and 15 (PM2, PM15).
register
Hard
If a pin is set as an analog input port, not the pin level but “0” is always read.
When an operational amplifier is used, AMPn+, AMPn−, and AMPnO pins are used, pp.431
so the alternative analog input functions cannot be used. The operational amplifier , 432
Port mode
15
output signals, however, can be used as analog inputs.
Soft
p.430
PM2, PM15:
Single AMP
To use as an input of the A/D converter a voltage that has been amplified in single p.433
mode
amplifier mode, enable operation in single amplifier mode before selecting an analog
registers 2 and
Soft
Chapter 13
input channel by using the ADS register.
Voltage
PER0:
reference
Peripheral
When setting voltage reference, be sure to set ADCEN to 1 first. If ADCEN = 0, p.435
writing to a control register of voltage reference is ignored, and, even if the register is
enable register 0 read, only the default value is read.
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Function
Voltage
ADVRC: A/D
During voltage reference operation, be sure to connect a tantalum capacitor p.436
reference
reference
(capacitance: 10 μF±30 %, ESR: 2 Ω (max.), ESL: 10 nH (max.)) and a ceramic
voltage control
capacitor (capacitance: 0.1 μF±30 %, ESR: 2 Ω (max.), ESL: 10 nH (max.)) to the
register
VREFOUT/AVREFP pin for stabilizing the reference voltage. Furthermore, do not apply
a voltage from the VREFOUT/AVREFP pin during voltage reference operation.
To use voltage reference output (VREFOUT) to the positive reference voltage of the A/D p.436
converter (ADREFP) and the positive reference voltage of the the D/A converter
(DAREFP), be sure to set VRON to 1 after setting VRSEL to 1.
Rewriting DACSWn (n = 0, 1) during A/D conversion is prohibited when both the p.437
positive reference voltage of the A/D converter (ADREFP) and the positive reference
voltage fo the D/A converter (DAREFP) are the voltage reference output (VREFOUT)
(VRSEL = 1 and DAREF = 1). Rewrite it when conversion operation is stopped
(ADCS = 0).
Do not change the output voltage of the reference voltage by using VRGV during the p.437
Hard
voltage reference operation (VRON = 1).
VREFOUT pin
The VREFOUT output voltage can be used only as the positive reference voltage of the p.437
internal A/D and D/A converters of the microcontroller. Do not connect an external
circuit other than a tantalum capacitor (capacitance: 10 μF±30 %, ESR: 2 Ω (max.),
ESL: 10 nH (max.)) and a ceramic capacitor (capacitance: 0.1 μF±30 %, ESR: 2 Ω
Soft
Chapter 14
(max.), ESL: 10 nH (max.)) to the VREFOUT pin for stabilizing the reference voltage.
p.445
PER0:
When setting serial array unit m, be sure to set SAUmEN to 1 first. If SAUmEN = 0, p.447
Peripheral
writing to a control register of serial array unit m is ignored, and, even if the register is
Configuration SDRmn: Lower
of serial
8 bits of the
array unit
serial data
Be sure to clear bit 8 to “0”.
register mn
enable register 0 read, only the default value is read (except for input switch control register (ISC),
noise filter enable register (NFEN0), port input mode register (PIM1, PIM7), port
output mode register (POM1, POM7, POM8), port mode registers (PM1, PM5, PM7,
PM8), and port registers (P1, P5, P7, P8)).
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more p.447
clocks have elapsed.
p.448
SPSm: Serial
Be sure to clear bits 15 to 8 to “0”.
clock select
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more p.448
register m
clocks have elapsed.
SMRmn: Serial
Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
p.449
Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
pp.451
mode register
mn
SCRmn: Serial
communication
to 453
operation setting
register mn
SDRmn: Serial
Be sure to clear bit 8 to “0”.
p.454
data register mn
Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
p.454
Setting SDRmn[15:9] = 0000000B is prohibited when the simplified I C is used. Set p.454
2
SDRmn[15:9] to 0000001B or greater.
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Function
Be sure to clear bits 15 to 3 to “0”.
p.457
Be sure to clear bits 15 to 4 to “0”.
p.459
Be sure to clear bits 15 to 4 to “0”.
p.460
Be sure to clear bits 15 to 3 of SOE0, and bits 1 and 15 to 3 of SOE1 to “0”.
p.461
SOm: Serial
Be sure to set bits 11 and 3 of SO0, and bits 11 to 9, 3, and 1 of SO1 to “1”. And be p.462
output register
sure to clear bits 15 to 12 and 7 to 4 of SOm to “0”.
Configuration SIRmn: Serial
of serial array flag clear trigger
unit
register mn
SSm: Serial
channel start
register m
STm: Serial
channel stop
register m
SOEm: Serial
output enable
register m
m
SOLm: Serial
Be sure to clear bits 15 to 3, 1 to “0”.
p.463
Be sure to clear bits 7 to 5 to “0”.
p.464
Be sure to clear bits 7, 5, 3, and 1 to “0”.
p.465
output level
register m
ISC: Input
switch control
register
NFEN0: Noise
filter enable
register 0
Operation
Stopping the
If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and, p.469
stop mode
operation by
even if the register is read, only the default value is read (except for input switch
units
control register (ISC), noise filter enable register (NFEN0), port input mode register
(PIM1, PIM7), port output mode register (POM1, POM7, POM8), port mode registers
(PM1, PM5, PM7, PM8), and port registers (P1, P5, P7, P8)).
3-wire serial I/O Master
(CSI00, CSI01, transmission
CSI10, CSI20) Master
communication transmission (in
continuous
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more pp.475,
clocks have elapsed.
479, 481
The MDmn0 bit can be rewritten even during operation.
p.480
However, rewrite it before transfer of the last bit is started, so that it will be rewritten
before the transfer end interrupt of the last transmit data.
transmission mode)
Master
reception
Master
transmission/
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more pp.484,
clocks have elapsed.
487
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more pp.490,
clocks have elapsed.
493, 494
reception
Master
The MDmn0 bit can be rewritten even during operation.
transmission/
However, rewrite it before transfer of the last bit is started, so that it has been
reception (in
rewritten before the transfer end interrupt of the last transmit data.
p.495
continuous
transmission/
reception mode)
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Function
3-wire
serial Slave
I/O (CSI00,
transmission
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more pp.498,
clocks have elapsed.
502, 504
CSI01, CSI10, Slave transmission The MDmn0 bit can be rewritten even during operation. However, rewrite it before p.503
CSI20)
(in continuous
transfer of the last bit is started.
communication transmission mode)
Slave reception
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more pp.507,
clocks have elapsed.
510
Slave
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more pp.513,
clocks have elapsed.
517, 518
transmission/
reception
p.519
UART (UART0, UART
When using serial array units 0 and 1 as UARTs, the channels of both the p.522
UART1,
transmitting side (even-number channel) and the receiving side (odd-number
Slave
The MDmn0 bit can be rewritten even during operation.
transmission/
However, rewrite it before transfer of the last bit is started, so that it will be rewritten
reception (in
before the transfer end interrupt of the last transmit data.
continuous
transmission/
reception mode)
communication
UART2,
channel) can be used only as UARTs.
UART3)
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more pp.526,
clocks have elapsed.
530, 532
UART
communication transmission
UART
The MDmn0 bit can be rewritten even during operation.
transmission (in
However, rewrite it before transfer of the last bit is started, so that it has been
continuous
rewritten before the transfer end interrupt of the last transmit data.
p.531
transmission
mode)
UART reception
For the UART reception, be sure to set SMRmr of channel r that is to be paired with pp.534,
channel n.
535
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more pp.536,
clocks have elapsed.
539
Calculating baud Setting SDRmn [15:9] = (0000000B, 0000001B) is prohibited.
p.548
rate
Simplified
Address field
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more p.555
I C (IIC10,
transmission
clocks have elapsed.
IIC20)
Data reception
2
communication
ACK is also output when the last data is received. Communication is then completed p.564
by setting “1” to the STmn bit to stop operation and generating a stop condition.
Calculating baud Setting SDRmn [15:9] = 0000000B is prohibited. Set SDRmn[15:9] to 0000001B or p.566
rate
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Function
Serial
IICA: IICA shift
interface
register
IICA
Do not write data to IICA during data transfer.
p.581
Write or read IICA only during the wait period. Accessing IICA in a communication p.581
state other than during the wait period is prohibited. When the device serves as the
master, however, IICA can be written only once after the communication trigger bit
(STT) is set to 1.
When communication is reserved, write data to IICA after the interrupt triggered by a p.581
stop condition is detected.
When setting serial interface IICA, be sure to set IICAEN to 1 first. If IICAEN = 0,
PER0:
p.584
writing to a control register of serial interface IICA is ignored, and, even if the register
Peripheral
enable register 0 is read, only the default value is read.
2
If the operation of I C is enabled (IICE = 1) when the SCL0 line is at high level, the p.585
IICCTL0: IICA
SDA0
line
is
at
low
level, and DFC of the IICCTL1 register is 1, a start condition will
control register 0
2
be inadvertently detected immediately. Immediately after enabling I C to operate
(IICE = 1), set LREL (1) by using a 1-bit memory manipulation instruction.
When bit 3 (TRC) of the IICA status register (IICS) is set to 1, WREL is set to 1 p.588
during the ninth clock and wait is canceled, after which TRC is cleared and the SDA0
line is set to high impedance. Release the wait performed while the TRC bit is 1
(transmission status) by writing to the IICA shift register.
IICS: IICA status Reading the IICS register while the address match wakeup function is enabled (WUP p.589
= 1) in STOP mode is prohibited. When the WUP bit is changed from 1 to 0 (wakeup
register
operation is stopped), regardless of the INTIICA interrupt request, the change in
status is not reflected until the next start condition or stop condition is detected. To
use the wakeup function, therefore, enable (SPIE = 1) the interrupt generated by
detecting a stop condition and read the IICS register after the interrupt has been
detected.
Write to STCEN only when the operation is stopped (IICE = 0).
IICF: IICA flag
p.592
As the bus release status (IICBSY = 0) is recognized regardless of the actual bus p.592
status when STCEN = 1, when generating the first start condition (STT = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
Write to IICRSV only when the operation is stopped (IICE = 0).
p.592
Note the minimum fCLK operation frequency when setting the transfer clock. The p.597
Setting IICWL
minimum fCLK operation frequency for serial interface IICA is determined according to
and IICWH on
the mode.
slave side
Fast mode:
fCLK = 3.5 MHz (MIN.)
Standard mode:
fCLK = 1 MHz (MIN.)
If a processing to cancel a wait state executed when WUP (bit 7 of IICA control p.604
Canceling wait
register 1 (IICCTL1)) = 1, the wait state will not be canceled.
2
Immediately after I C operation is enabled (IICE = 1), the bus communication status p.616
When STCEN
(bit 1 of IICA flag (IICBSY = 1) is recognized regardless of the actual bus status. When changing from
register (IICF)) = a mode in which no stop condition has been detected to a master device
communication mode, first generate a stop condition to release the bus, then perform
0
master device communication.
When using multiple masters, it is not possible to perform master device
communication when the bus has not been released (when a stop condition has not
been detected).
Use the following sequence for generating a stop condition.
Set IICA control register 1 (IICCTL1).
Set bit 7 (IICE) of IICA control register 0 (IICCTL0) to 1.
Set bit 0 (SPT) of IICCTL0 to 1.
2
When STCEN = Immediately after I C operation is enabled (IICE = 1), the bus released status p.616
(IICBSY = 0) is recognized regardless of the actual bus status. To generate the first
1
start condition (STT = 1), it is necessary to confirm that the bus has been released,
so as to not disturb other communications.
register
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Function
2
2
Serial
If other I C
If I C operation is enabled and the device participates in communication already in p.616
interface
communications
progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I C
IICA
are already in
recognizes that the SDA0 pin has gone low (detects a start condition). If the value on
progress
the bus at this time can be recognized as an extension code, ACK is returned, but
2
2
2
this interferes with other I C communications. To avoid this, start I C in the following
sequence.
Clear bit 4 (SPIE) of IICCTL0 to 0 to disable generation of an interrupt request
signal (INTIICA) when the stop condition is detected.
2
Set bit 7 (IICE) of IICCTL0 to 1 to enable the operation of I C.
Wait for detection of the start condition.
Set bit 6 (LREL) of IICCTL0 to 1 before ACK is returned (4 to 80 clocks after
setting IICE to 1), to forcibly disable detection.
STT, SPT: Bits
Setting STT and SPT (bits 1 and 0 of IICCTL0) again after they are set and before p.616
1, 0 of IICA
they are cleared to 0 is prohibited.
control register 0
(IICCTL0)
Reserving
When transmission is reserved, set SPIE (bit 4 of IICTL0) to 1 so that an interrupt p.616
transmission
request is generated when the stop condition is detected. Transfer is started when
communication data is written to IICA after the interrupt request is generated. Unless
the interrupt is generated when the stop condition is detected, the device stops in the
wait state because the interrupt request is not generated when communication is
started. However, it is not necessary to set SPIE to 1 when MSTS (bit 7 of IICS) is
Soft
Chapter 16
detected by software.
LCD
p.667
LCDM: LCD
When LCD display is not performed or necessary, set SCOC and VLCON to 0, in p.668
display mode
order to reduce power consumption.
register
When the external resistance division method has been set (MDSET1 = MDSET0 = p.668
LCDMD: LCD
Bits 0 to 3, 6 and 7 must be set to 0.
controller/d mode register
river
0), do not set VLCON to 1.
Set BLON and LCDSEL to 0 when 8 has been selected as the number of time slices p.668
for the display mode.
To use the internal voltage boosting method, specify the reference voltage by using p.668
the VLCD register (or perform a reset to use the default value of the reference
voltage), wait for the reference voltage setup time (2 ms (min.)), and then set VLCON
to 1.
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Function
LCD
controller/d display mode
LCDM: LCD
To manipulate VLCON when using the internal voltage boosting method or capacitor p.669
split method, follow the procedure below.
river
A. To stop the operation of the voltage boosting/capacitor split circuit after switching
register
display status from on to off:
1)
Set to display off status by setting LCDON = 0.
2)
Disable outputs of all the segment buffers and common buffers by setting
3)
Stop the operation of the voltage boosting/capacitor split circuit by setting
SCOC = 0.
V LCON = 0.
B. To stop the operation of the voltage boosting/capacitor split circuit during display
on status:
Setting
prohibited.
Be
sure
to
stop
the
operation
of
the
voltage
boosting/capacitor split circuit after setting display off.
C. To set display on from stop status of the voltage boosting/capacitor split circuit:
1)
Start the operation of the voltage boosting/capacitor split circuit by setting
VLCON = 1, then wait for the voltage boosting/capacitor split wait time (see
CHAPTER 31 ELECTRICAL SPECIFICATIONS).
2)
Set all the segment buffers and common buffers to non-display output
3)
Set display on by setting LCDON = 1.
status by setting SCOC = 1.
LCDC0: LCD
Bits 3, 6, and 7 must be set to 0.
clock control
Set the LCD clock (LCDCL) to no more than 512 Hz when the internal voltage boost p.670
p.670
register 0
method has been set.
VLCD: LCD
The VLCD setting is valid only when the voltage boost circuit is operating.
p.671
boost level
Bits 5 to 7 must be set to 0.
p.671
control register
Be sure to change the VLCD value after having stopped the operation of the voltage p.671
boost circuit (VLCON = 0).
These values above may change after device evaluation.
p.671
To use the internal voltage boosting method, specify the reference voltage by using p.671
the VLCD register (or perform a reset to use the default value of the reference
voltage), wait for the reference voltage setup time (2 ms (min.)), and then set VLCON
to 1.
PFALL: Port
For 78K0R/LF3, bits 3 and 7 must be set to 0. For 78K0R/LG3 and 78K0R/LH3, bit 7 p.672
function register
must be set to 0.
SEGEN:
SEGEN can be written only once after reset release.
p.673
Segment enable For 78K0R/LF3, bits 1 to 7 must be set to 0. For 78K0R/LG3, bits 2 to 7 must be set p.673
register
to 0. For 78K0R/LH3, bits 5 to 7 must be set to 0.
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Function
LCD
p.674
When stopping the operation of the voltage boost circuit circuit, be sure to set SCOC p.679
ISC: Input switch Be sure to clear bits 5 to 7 to “0”.
controller/d control register
river
Internal voltage
boosting method and LCDON to 0 before setting VLCON to 0.
Capacitor split
When stopping the operation of the capacitor split circuit, be sure to set SCOC and p.680
method
LCDON to 0 before setting VLCON to 0.
External
To stabilize the potential of the VLC0 to VLC3 pins, it is recommended to connect a pp.703
resistance
capacitor of about 0.1 μF between each of the pins from VLC0 to VLC3 and the GND pin ,704
division method
as needed.
Selection of LCD When the LCD display data memory is used when the number of time slices is eight, p.706
Soft
Chapter 17
display data
Multiplier/d MDAH, MDAL:
ivider
LCD display data (A-pattern, B-pattern, or blinking display) cannot be selected.
Do not rewrite the MDAH and MDAL values during division operation processing p.711
Multiplication/divi (while the multiplication/division control register (MDUC) is 81H). The operation will
sion data
be executed in this case, but the operation result will be an undefined value.
register A
The MDAH and MDAL values read during division operation processing (while p.711
MDUC is 81H) will not be guaranteed.
MDBL, MDBH:
Do not rewrite the MDBH and MDBL values during division operation processing p.711
The operation
Multiplication/divi (while the multiplication/division control register (MDUC) is 81H).
sion data
result will be an undefined value.
register B
Do not set MDBH and MDBL to 0000H in the division mode. If they are set, the p.711
operation result will be an undefined value.
MDCL, MDCH:
The MDCH and MDCL values read during division operation processing (while the p.712
Multiplication/divi multiplication/division control register (MDUC) is 81H) will not be guaranteed.
sion data
register C
MDUC:
Do not rewrite DIVMODE during operation processing (while DIVST is 1). If it is p.713
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Chapter 18
Multiplication/divi rewritten, the operation result will be an undefined value.
sion control
DIVST cannot be cleared (0) by using software during division operation processing p.713
register
(while DIVST is 1).
DMA
DBCn: DMA
Be sure to clear bits 15 to 10 to “0”.
controller
byte count
p.720
If the general-purpose register is specified or the internal RAM space is exceeded as p.720
register n
a result of continuous transfer, the general-purpose register or SFR space are written
or read, resulting in loss of data in these spaces. Be sure to set the number of times
of transfer that is within the internal RAM space.
DRCn: DMA
The DSTn flag is automatically cleared to 0 when a DMA transfer is completed. p.723
operation control Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is
register n
terminated without waiting for generation of the interrupt (INTDMAn) of DMAn,
therefore, set DSTn to 0 and then DENn to 0 (for details, refer to 18.5.7 Forced
termination by software).
When the FSEL bit of the OSMC register has been set to 1, do not enable (DENn = p.723
1) DMA operation for at least three clocks after the setting.
transfer pending
When DMA transfer is held pending while using both DMA channels, be sure to held p.735
the DMA transfer pending for both channels (by setting DWAIT0 and DWAIT1 to 1).
by DWAITn
If the DMA transfer of one channel is executed while that of the other channel is held
Forced
termination of
In example 3, the system is not required to wait two clock cycles after the DWAITn bit p.737
is set to 1. In addition, the system does not have to wait two clock cycles after
DMA transfer
clearing the DSTn bit to 0, because more than two clock cycles elapse from when the
Holding DMA
pending, DMA transfer might not be held pending for the latter channel.
DSTn bit is cleared to 0 to when the DENn bit is cleared to 0.
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Function
DMA
Priority
controller
During DMA transfer, a request from the other DMA channel is held pending even if p.738
generated. The pending DMA transfer is started after the ongoing DMA transfer is
completed. If two DMA requests are generated at the same time, however, DMA
channel 0 takes priority over DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA
Hard
The response time of DMA transfer is as follows. (See Table 18-2.)
p.738
Soft
transfer takes precedence, and then interrupt servicing is executed.
Response time
Operation in
The DMA controller operates as follows in the standby mode.
p.739
DMA pending
Even if a DMA request is generated, DMA transfer is held pending immediately after p.739
instruction
the following instructions.
(See Table 18-3.)
standby mode
• CALL !addr16
• CALL $!addr20
• CALL !!addr20
• CALL rp
• CALLT [addr5]
• BRK
• Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L,
MK0H, MK1L, MK1H, MK2L, MK2H, PR00L, PR00H, PR01L, PR01H, PR02L,
PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H and PSW each.
Operation if
The address indicated by DRA0n is incremented during DMA transfer. If the address p.739
address in
is incremented to an address in the general-purpose register area or exceeds the
general-purpose area of the internal RAM, the following operation is performed.
register area or
other than those
of internal RAM
area is specified
z In mode of transfer from SFR to RAM
The data of that address is lost.
z In mode of transfer from RAM to SFR
Undefined data is transferred to SFR.
In either case, malfunctioning may occur or damage may be done to the system.
Therefore, make sure that the address is within the internal RAM area other than the
Soft
Chapter 19
general-purpose register area.
Interrupt
functions
When operating a timer, serial interface, or A/D converter after standby release, p.748
IF1H, IF2L, IF2H: operate it once after clearing the interrupt request flag. An interrupt request flag may
IF0L, IF0H, IF1L,
Interrupt request
be set by noise.
flag registers
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Function
When manipulating a flag of the interrupt request flag register, use a 1-bit memory p.748
When describing in C language, use a bit
Interrupt
IF0L, IF0H, IF1L,
functions
IF1H, IF2L, IF2H: manipulation instruction (CLR1).
Interrupt request
manipulation instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the
flag registers
compiled assembler must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation
instruction such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three
instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of another bit of the same interrupt request flag
register (IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the
flag is cleared to 0 at “mov IF0L, a”. Therefore, care must be exercised when using
an 8-bit memory manipulation instruction in C language.
Be sure to clear bits 5, 6 of IF0H, bit 3 of IF1L, bit 3 of IF1H, bits 5 to 7 of IF2L, bits 0, p.749
6, 7 of IF2H to 0. (78K0R/LF3)
Be sure to clear bit 3 of IF1H, bits 6, 7 of IF2H to 0. (78K0R/LG3)
Be sure to clear bits 6, 7 of IF2H to 0. (78K0R/LH3)
p.750
p.751
MK1L, MK1H,
Be sure to set bits 5, 6 of MK0H, bit 3 of MK1L, bit 3 of MK1H, bits 5 to 7 of MK2L, p.752
bits 0, 6, 7 of MK2H to 1. (78K0R/LF3)
MK2L, MK2H:
Be sure to set bit 3 of MK1H, bits 6, 7 of MK2H to 1. (78K0R/LG3)
Interrupt mask
Be sure to set bits 6, 7 of MK2H to 1. (78K0R/LH3)
MK0L, MK0H,
p.753
p.754
flag registers
PR00L, PR00H,
PR01L, PR01H,
PR02L, PR02H,
PR10L, PR10H,
Be sure to set bits 5, 6 of PR00H and PR10H, bit 3 of PR01L and PR11L to 1. p.755
(78K0R/LF3)
Be sure to set bit 3 of PR01H and PR11H, bits 5 to 7 of PR02L and PR12L, bits 0, 6, p.756
7 of PR02H and PR12H to 1. (78K0R/LF3)
PR12L, PR12H:
Be sure to set bit 3 of PR01H and PR11H, bits 6, 7 of PR02H and PR12H to 1. p.757
(78K0R/LG3)
Priority
Be sure to set bits 6, 7 of PR02H and PR12H to 1. (78K0R/LH3)
PR11L, PR11H,
p.758
specification flag
registers
EGP0, EGP1:
External
Select the port mode by clearing EGPn and EGNn to 0 because an edge may be p.762
detected when the external interrupt function is switched to the port function.
interrupt rising
edge enable
registers, EGN0,
EGN1: External
interrupt falling
edge enable
registers
Software
Do not use the RETI instruction for restoring from the software interrupt.
p.766
interrupt request
acknowledgment
BRK instruction
The BRK instruction is not one of the above-listed interrupt request hold instructions. p.770
However, the software interrupt activated by executing the BRK instruction causes
the IE flag to be cleared.
Therefore, even if a maskable interrupt request is
generated during execution of the BRK instruction, the interrupt request is not
acknowledged.
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Chapter 20
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Function
Key
interrupt
KRM: Key return If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of p.772
mode register
the corresponding pull-up resistor register 7 (PU7) to 1.
An interrupt will be generated if the target bit of the KRM register is set while a low p.772
level is being input to the key interrupt input pin. To ignore this interrupt, set the
function
KRM register after disabling interrupt servicing by using the interrupt mask flag.
Afterward, clear the interrupt request flag and enable interrupt servicing after waiting
for the key interrupt input low-level width (250 ns or more).
Soft
Chapter 21
The bits not used in the key interrupt mode can be used as normal ports.
−
Standby
function
p.772
The STOP mode can be used only when the CPU is operating on the main system p.773
clock. The STOP mode cannot be set while the CPU operates with the subsystem
clock. The HALT mode can be used when the CPU is operating on either the main
system clock or the subsystem clock.
When shifting to the STOP mode, be sure to stop the peripheral hardware operation p.773
operating with main system clock before executing STOP instruction.
The following sequence is recommended for operating current reduction of the A/D p.773
converter when the standby function is used: First clear bit 7 (ADCS) and bit 0
(ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion
operation, and then execute the STOP instruction.
It can be selected by the option byte whether the internal low-speed oscillator p.773
continues oscillating or stops in the HALT or STOP mode. For details, see
CHAPTER 26 OPTION BYTE.
The STOP instruction cannot be executed when the CPU operates on the 20 MHz p.773
internal high-speed oscillation clock. Be sure to execute the STOP instruction after
shifting to internal high-speed oscillation clock operation.
OSTC:
Oscillation
After the above time has elapsed, the bits are set to 1 in order from MOST8 and p.774
remain 1.
stabilization time The oscillation stabilization time counter counts up to the oscillation p.774
counter status
stabilization time set by OSTS. If the STOP mode is entered and then
register
released while the internal high-speed oscillation clock is being used as the
CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
Soft Hard
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock p.774
oscillation starts (“a” below).
OSTS:
To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
Oscillation
before executing the STOP instruction.
p.775
stabilization time Setting the oscillation stabilization time to 20 μs or less is prohibited.
p.775
select register
Before changing the setting of the OSTS register, confirm that the count operation of p.775
the OSTC register is completed.
Do not change the value of the OSTS register during the X1 clock oscillation p.775
stabilization time.
The oscillation stabilization time counter counts up to the oscillation stabilization time p.775
set by OSTS. If the STOP mode is entered and then released while the internal
high-speed oscillation clock is being used as the CPU clock, set the oscillation
stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
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Function
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Page
Function
Standby
OSTS:
function
Oscillation
The X1 clock oscillation stabilization wait time does not include the time until clock p.775
oscillation starts (“a” below).
stabilization time
select register
Soft
Chapter 21
Chapter
(31/39)
STOP mode
Because the interrupt request signal is used to clear the standby mode, if there is an p.782
interrupt source with the interrupt request flag set and the interrupt mask flag reset,
the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the
HALT mode immediately after execution of the STOP instruction and the system
returns to the operating mode as soon as the wait time set using the oscillation
stabilization time select register (OSTS) has elapsed.
The STOP instruction cannot be executed when the CPU operates on the 20 MHz pp.782
internal high-speed oscillation clock. Be sure to execute the STOP instruction after , 784
shifting to internal high-speed oscillation clock operation.
To use the peripheral hardware that stops operation in the STOP mode, and the p.784
peripheral hardware for which the clock that stops oscillating in the STOP mode after
the STOP mode is released, restart the peripheral hardware.
To stop the internal low-speed oscillation clock in the STOP mode, use an option p.784
byte to stop the watchdog timer operation in the HALT/STOP mode (bit 0
(WDSTBYON) of 000C0H = 0), and then execute the STOP instruction.
To shorten oscillation stabilization time after the STOP mode is released when the p.784
CPU operates with the high-speed system clock (X1 oscillation), temporarily switch
the CPU clock to the internal high-speed oscillation clock before the next execution
of the STOP instruction. Before changing the CPU clock from the internal highspeed oscillation clock to the high-speed system clock (X1 oscillation) after the
STOP mode is released, check the oscillation stabilization time with the oscillation
Hard
Chapter 22
stabilization time counter status register (OSTC).
−
Reset
For an external reset, input a low level for 10 μs or more to the RESET pin
p.788
(To perform an external reset upon power application, a low level of at least 10 μs
function
must be continued during the period in which the supply voltage is within the
operating range (VDD ≥ 1.8 V)).
During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and p.788
internal low-speed oscillation clock stop oscillating. External main system clock input
becomes invalid.
When the STOP mode is released by a reset, the RAM contents in the STOP mode p.788
are held during reset input.
Soft
When reset is effected, port pin P140 is set to low-level output and other port pins p.788
become high-impedance, because each SFR and 2nd SFR are initialized.
Block diagram of An LVI circuit internal reset does not reset the LVI circuit.
p.790
reset function
A watchdog timer internal reset resets the watchdog timer.
p.790
RESF: Reset
Do not read data by a 1-bit memory manipulation instruction.
p.797
control flag
Do not make a judgment based on only the read value of the RESF register 8-bit p.797
data, because bits other than TRAP, WDRF, and LVIRF become undefined.
Watchdog timer
overflow
register
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, LVIRF p.797
flag may become 1 from the beginning depending on the power-on waveform.
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Chapter 23
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Power-on-
Details of
Cautions
Page
Function
−
clear
If the low-voltage detector (LVI) is set to ON by an option byte by default, the reset pp.798,
799
signal is not released until the supply voltage (VDD) exceeds 2.07 V ±0.2 V.
circuit
If an internal reset signal is generated in the POC circuit, the reset control flag p.798
register (RESF) is cleared to 00H.
Timing of
Set the low-voltage detector by software after the reset status is released (see p.800
generation of
CHAPTER 24 LOW-VOLTAGE DETECTOR).
internal reset
signal (LVIOFF =
1)
Timing of
Set the low-voltage detector by software after the reset status is released (see p.801
generation of
CHAPTER 24 LOW-VOLTAGE DETECTOR).
internal reset
signal (LVIOFF =
0)
Cautions for
In a system where the supply voltage (VDD) fluctuates for a certain period in the p.802
power-on-clear
vicinity of the POC detection voltage (VPOR, VPDR), the system may be repeatedly
circuit
reset and released from the reset status. In this case, the time from release of reset
to the start of the operation of the microcontroller can be arbitrarily set by taking the
Soft
LVIM: Low-
voltage
voltage detection instruction.
Soft Hard
Chapter 24
following action.
Lowdetector
register
To stop LVI, be sure to clear (0) LVION by using a 1-bit memory manipulation p.807
p.807
When LVI is used in interrupt mode (LVIMD = 0) and LVISEL is set to 0, an interrupt p.807
Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
request signal (INTLVI) that disables LVI operation (clears LVION) when the supply
voltage (VDD) is less than or equal to the detection voltage (VLVI) (if LVISEL = 1, input
voltage of external input pin (EXLVI) is less than or equal to the detection voltage
(VEXLVI)) is generated and LVIIF may be set to 1.
LVIS: Low-
p.809
When an input voltage from the external input pin (EXLVI) is detected, the detection p.809
Be sure to clear bits 4 to 7 to “0”.
voltage detection Change the LVIS value with either of the following methods.
level select
• When changing the value after stopping LVI
register
p.808
Stop LVI (LVION = 0).
Change the LVIS register.
Set to the mode used as an interrupt (LVIMD = 0).
Mask LVI interrupts (LVIMK = 1).
Enable LVI operation (LVION = 1).
Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
because an LVIIF flag may be set when LVI operation is enabled.
• When changing the value after setting to the mode used as an interrupt (LVIMD =
0)
Mask LVI interrupts (LVIMK = 1).
Set to the mode used as an interrupt (LVIMD = 0).
Change the LVIS register.
Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
because an LVIIF flag may be set when the LVIS register is changed.
voltage (VEXLVI) is fixed. Therefore, setting of LVIS is not necessary.
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Function
Be sure to execute . When LVIMK = 0, an interrupt may occur immediately after p.811
the processing in .
Low-
Used as reset
voltage
(when detecting
detector
level of supply
If supply voltage (VDD) ≥ detection voltage (VLVI) when LVIMD is set to 1, an internal p.811
voltage (VDD))
reset signal is not generated.
(LVIOFF = 1)
(when detecting
Even when the LVI default start function is used, if it is set to LVI operation p.812
prohibition by the software, it operates as follows:
level of supply
• Does not perform low-voltage detection during LVION = 0.
voltage (VDD))
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
(LVIOFF = 0)
starts after reset release. There is a period when low-voltage detection cannot be
Used as reset
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200 μs
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
Used as reset
(when detecting
voltage from
If input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI = 1.21 V p.813
(TYP.)) when LVIMD is set to 1, an internal reset signal is not generated.
external input
Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
level of input
Soft Hard
Be sure to execute . When LVIMK = 0, an interrupt may occur immediately after p.813
the processing in .
p.813
pin (EXLVI))
Used as
interrupt (when
Even when the LVI default start function is used, if it is set to LVI operation p.819
prohibition by the software, it operates as follows:
detecting level of • Does not perform low-voltage detection during LVION = 0.
supply voltage
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
(VDD)) (LVIOFF =
starts after reset release. There is a period when low-voltage detection cannot be
0)
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200 μs
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the p.819
LVIRF flag may become 1 from the beginning due to the power-on waveform.
Hard
For details of RESF, see CHAPTER 22 RESET FUNCTION.
Used as
Input voltage from the external input pin (EXLVI) must be EXLVI < VDD.
p.821
interrupt (when
detecting level of
input voltage
from external
input pin
(EXLVI))
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Function
Lowvoltage
Cautions for low- In a system where the supply voltage (VDD) fluctuates for a certain period in the pp.823
voltage detector vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on to 825
how the low-voltage detector is used.
detector
Operation example 1: When used as reset
The system may be repeatedly reset and released from the reset status.
The time from reset release through microcontroller operation start can be set
arbitrarily by the following action.
After releasing the reset signal, wait for the supply voltage fluctuation period of each
system by means of a software counter that uses a timer, and then initialize the ports
(see Figure 24-11).
Operation example 2: When used as interrupt
Interrupt requests may be generated frequently.
Take the following action.
Confirm that “supply voltage (VDD) ≥ detection voltage (VLVI)” when detecting the
falling edge of VDD, or “supply voltage (VDD) < detection voltage (VLVI)” when detecting
the rising edge of VDD, in the servicing routine of the LVI interrupt by using bit 0
(LVIF) of the low-voltage detection register (LVIM). Clear bit 1 (LVIIF) of interrupt
request flag register 0L (IF0L) to 0.
For a system with a long supply voltage fluctuation period near the LVI detection
Hard
voltage, take the above action after waiting for the supply voltage fluctuation time.
There is some delay from the time supply voltage (VDD) < LVI detection voltage (VLVI) p.825
until the time LVI reset has been generated.
In the same way, there is also some delay from the time LVI detection voltage (VLVI)
Soft
Chapter 25
≤ supply voltage (VDD) until the time LVI reset has been released (see Figure 24-12).
Regulator
RMC: Regulator
The RMC register can be rewritten only in the low-power consumption mode (refer to p.827
mode control
Table 25-1). In other words, rewrite this register during CPU operation with the
register
subsystem clock (fXT) while the high-speed system clock (fMX), the high-speed
internal oscillation clock, and the 20 MHz internal high-speed oscillation clock (fIH20)
are both stopped.
When using the setting fixed to the low consumption current mode, the RMC register p.827
can be used in the following cases.
fCLK ≤ 1 MHz and external oscillator (X1 clock (fX), external main system clock (fEX))
stop..
fCLK ≤ 1 MHz, fX/fEX ≤ 5 MHz and the internal high-speed oscillator stop.
Both the internal high-speed oscillator and external oscillator (fX/fEX ≤ 5 MHz) stop or
either one stops.
In low-power consumption mode, use the regulator with fCLK fixed to 1 MHz when p.828
executing self programming.
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Regulator
Details of
Cautions
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Function
RMC: Regulator
A wait is required to change the operation speed mode control register (OSMC) after p.828
mode control
changing the RMC register. Wait for 2 ms by software when setting to low-power
register
consumption mode and 10 μs when setting to normal power mode, as described in
the procedure shown below.
• When setting to low-power consumption mode
Select a frequency of 1 MHz for fCLK.
Set RMC to 5AH (set the regulator to low-power consumption mode).
Wait for 2 ms.
Set FLPC and FSEL of OSMC to 1 and 0, respectively.
• When setting to normal power mode
Set RMC to 00H (set the regulator to normal power mode).
Wait for 10 μs.
Change FLPC and FSEL of OSMC.
Soft
Chapter 26
Change the fCLK frequency.
Option
000C2H/010C2H Be sure to set FFH to 000C2H (000C2H/010C2H when the boot swap operation is p.829
byte
used).
000C0H/010C0H Set the same value as 000C0H to 010C0H when the boot swap operation is used p.829
because 000C0H is replaced by 010C0H.
000C1H/010C1H Set the same value as 000C1H to 010C1H when the boot swap operation is used p.829
because 000C1H is replaced by 010C1H.
000C2H/010C2H Set FFH to 010C2H when the boot swap operation is used because 000C2H is p.829
replaced by 010C2H.
000C3H/010C3H Set the same value as 000C3H to 010C3H when the boot swap operation is used p.830
because 000C3H is replaced by 010C3H.
000C0H/010C0H The watchdog timer continues its operation during self-programming of the flash p.831
memory and EEPROM emulation. During processing, the interrupt acknowledge
time is delayed.
Set the overflow time and window size taking this delay into
consideration.
000C1H/010C1H Be sure to set bits 7 to 3 to “1”.
p.832
Even when the LVI default start function is used, if it is set to LVI operation p.832
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200 μs
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
p.832
Setting of option To specify the option byte by using assembly language, use OPT_BYTE as the p.833
000C3H/010C3H Bits 7 and 0 (OCDENSET and OCDERSD) can only be specified a value.
Be sure to set 000010B to bits 6 to 1.
byte
relocation attribute name of the CSEG pseudo instruction. To specify the option byte
to 010C0H to 010C3H in order to use the boot swap function, use the relocation
attribute AT to specify an absolute address.
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Chapter 27
Chapter
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Function
Details of
Cautions
Page
Function
Flash
Security settings
memory
After the security setting for the batch erase is set, erasure cannot be performed for p.843
the device. In addition, even if a write command is executed, data different from that
which has already been written to the flash memory cannot be written, because the
erase command is disabled.
If a security setting that rewrites boot cluster 0 has been applied, boot cluster 0 of p.843
that device will not be rewritten, and the entire flash memory of the device will not be
Soft
erased in batch.
Flash memory
The self-programming function cannot be used when the CPU operates with the p.845
programming by
subsystem clock.
self-
In the self-programming mode, call the self-programming start library (FlashStart).
programming
To prohibit an interrupt during self-programming, in the same way as in the normal p.845
p.845
operation mode, execute the self-programming library in the state where the IE flag
is cleared (0) by the DI instruction. To enable an interrupt, clear (0) the interrupt
mask flag to accept in the state where the IE flag is set (1) by the EI instruction, and
then execute the self-programming library.
In low-power-consumption mode, use the regulator with fCLK fixed to 1 MHz when p.845
executing self programming. For details of the low-power-consumption mode, see
CHAPTER 25 REGULATOR.
Disable DMA operation (DENn = 0) during the execution of self programming library p.845
functions.
Flash shield
Hard
Chapter 28
window function
If the rewrite-prohibited area of the boot cluster 0 overlaps with the flash shield p.849
window range, prohibition to rewrite the boot cluster 0 takes priority.
On-chip
Connecting QB-
debug
MINI2 to
The 78K0R/Lx3 microcontrollers have an on-chip debug function, which is provided p.851
for development and evaluation. Do not use the on-chip debug function in products
function
78K0R/Lx3
designated for mass production, because the guaranteed number of rewritable times
of the flash memory may be exceeded when this function is used, and product
reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for
Soft
Chapter 29
problems occurring when the on-chip debug function is used.
correction
The value read from the BCDADJ register varies depending on the value of the A p.855
register when it is read and those of the CY and AC flags. Therefore, execute the
circuit
instruction after the instruction instead of executing any other instructions.
BCD
Addition
To perform BCD correction in the interrupt enabled state, saving and restoring the A
register is required within the interrupt function. PSW (CY flag and AC flag) is
restored by the RETI instruction.
Subtraction
The value read from the BCDADJ register varies depending on the value of the A p.856
register when it is read and those of the CY and AC flags. Therefore, execute the
instruction after the instruction instead of executing any other instructions.
To perform BCD correction in the interrupt enabled state, saving and restoring the A
register is required within the interrupt function. PSW (CY flag and AC flag) is
Soft
Chapter 30
restored by the RETI instruction.
Instruction PREFIX
set
instruction
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Jun 20, 2011
Set the ES register value with MOV ES, A, etc., before executing the PREFIX p.859
instruction.
992
78K0R/Lx3
APPENDIX C LIST OF CAUTIONS
Classification
Hard
Chapter 31
Chapter
(37/39)
Function
Details of
Cautions
Page
Function
Electrical
−
specifications
The 78K0R/Lx3 microcontrollers have an on-chip debug function, which is provided p.877
for development and evaluation. Do not use the on-chip debug function in products
designated for mass production, because the guaranteed number of rewritable times
of the flash memory may be exceeded when this function is used, and product
reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for
problems occurring when the on-chip debug function is used.
The pins mounted depend on the product. Refer to 1.3 Pin Configuration (Top View) p.877
and CHAPTER 2 PIN FUNCTIONS.
Absolute
Product quality may suffer if the absolute maximum rating is exceeded even pp.878
maximum ratings momentarily for any parameter. That is, the absolute maximum ratings are rated to 880
values at which the product is on the verge of suffering physical damage, and
therefore the product must be used under conditions that ensure that the absolute
maximum ratings are not exceeded.
The value of the current that can be run per pin must satisfy the value of the current pp.879
per pin and the total value of the currents of all pins.
X1 oscillator
When using the X1 oscillator, wire as follows in the area enclosed by the broken lines p.880
characteristics
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current
flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Since the CPU is started by the internal high-speed oscillation clock after a reset p.880
release, check the X1 clock oscillation stabilization time using the oscillation
stabilization time counter status register (OSTC) by the user. Determine the
oscillation stabilization time of the OSTC register and oscillation stabilization time
select register (OSTS) after sufficiently evaluating the oscillation stabilization time
with the resonator to be used.
XT1 oscillator
When using the XT1 oscillator, wire as follows in the area enclosed by the broken p.881
characteristics
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current
flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
The XT1 oscillator is designed as a low-amplitude circuit for reducing power p.881
consumption, and is more prone to malfunction due to noise than the X1 oscillator.
Particular care is therefore required with the wiring method when the XT1 clock is
used.
oscillator circuit
The oscillator constants shown above are reference values based on evaluation in a pp.882
specific environment by the resonator manufacturer. If it is necessary to optimize the , 883
constants
oscillator characteristics in the actual application, apply to the resonator manufacturer
Recommended
for evaluation on the implementation circuit. The oscillation voltage and oscillation
frequency only indicate the oscillator characteristic. Use the 78K0R/Lx3 so that the
internal operation conditions are within the specifications of the DC and AC
characteristics.
R01UH0004EJ0501 Rev.5.01
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78K0R/Lx3
APPENDIX C LIST OF CAUTIONS
Classification
Hard
Function
Details of
Cautions
Page
Function
Electrical
DC
specifications characteristics
P10 to P15, P75, P77, P80 and P82 do not output high level in N-ch open-drain pp.885,
mode.
890
The maximum value of VIH of pins P10 to P15, P75, P77, P80 and P82 is VDD, even p.887
in the N-ch open-drain mode.
Soft
Chapter 31
Chapter
(38/39)
Minimum
When VDD < 2.25 V and FSEL = 1, It is prohibited to release STOP mode during fEX p.898
instruction
operation or fIH operation (This must not be performed even if the frequency is
execution time
divided. The STOP mode may be released during fX operation.).
during main
system clock
operation
During
Select the normal input buffer for RxDq and the normal output mode for TxDq by p.902
communication
using the PIMg and POMx registers.
at same potential
(UART mode)
(dedicated baud
rate generator
output)
During
Select the normal input buffer for SIp and the normal output mode for SOp and p.903
communication
SCKp by using the PIMg and POMx registers.
at same potential
(CSI mode)
(master mode,
SCKp... internal
clock output)
During
Select the normal input buffer for SIp and SCKp and the normal output mode for p.904
communication
SOp by using the PIMg and POMx registers.
at same potential
(CSI mode)
(slave mode,
SCKp... external
clock input)
During
Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode p.906
communication
for SDAr and the normal output mode for SCLr by using the PIMg and POMx
at same potential registers.
2
(simplified I C
mode)
During
communication
Select the TTL input buffer for RxDq and the N-ch open drain output (VDD tolerance) pp.908,
mode for TxDq by using the PIMg and POMx registers.
909, 911
at different
potential (2.5 V,
3 V) (UART
mode)
(dedicated baud
rate generator
output)
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APPENDIX C LIST OF CAUTIONS
Classification
Soft
Chapter 31
Chapter
(39/39)
Function
Details of
Cautions
Page
Function
Electrical
During
specifications communication
Select the TTL input buffer for SIp and the N-ch open drain output (VDD tolerance) pp.912
mode for SOp and SCKp by using the PIMg and POMx registers.
to 914
at different
potential (2.5 V,
3 V) (CSI mode)
(master mode,
SCKp... internal
clock output)
During
communication
Select the TTL input buffer for SIp and SCKp and the N-ch open drain output (VDD pp.916,
tolerance) mode for SOp by using the PIMg and POMx registers.
917
at different
potential (2.5 V,
3 V) (CSI mode)
(slave mode,
SCKp... external
clock input)
communication
Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for pp.918,
SDAr and the N-ch open drain output (VDD tolerance) mode for SCLr by using the 919
at different
PIMg and POMx registers.
During
potential (2.5 V,
3 V) (simplified
2
Hard
Chapter 33
Hard
I C mode)
VR circuit
Recommended
−
Connect the VREFOUT pin to GND via a tantalum capacitor (capacitance: 10 p.923
μF±30 %, ESR: 2 Ω (max.), ESL: 10 nH (max.)) and a ceramic capacitor
(capacitance: 0.1 μF±30 %, ESR: 2 Ω (max.), ESL: 10 nH (max.)).
The μPD78F1500A to 78F1508A have an on-chip debug function, which is provided pp.938,
soldering
for development and evaluation. Do not use the on-chip debug function in products 939
condition
designated for mass production, because the guaranteed number of rewritable times
of the flash memory may be exceeded when this function is used, and product
reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for
problems occurring when the on-chip debug function is used.
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
995
78K0R/Lx3
APPENDIX D REVISION HISTORY
APPENDIX D REVISION HISTORY
D.1 Major Revisions in This Edition
(1/3)
Page
Description
Classification
Major Revisions in Rev.5.01
CHAPTER 3 CPU ARCHITECTURE
p.95
Deletion of Note of analog reference voltage control register (ADVRC)
(a)
CHAPTER 10 12-BIT A/D CONVERTER (μ PD78F150xA), 10-BIT A/D CONVERTER (μ PD78F151xA)
p.387, 395
Change of the selectable bit in analog reference voltage control register (ADVRC) for
μ PD78F151xA to only the VRGV bit
(a)
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
Throughout
Deletion of Note of preliminary values
(c)
CHAPTER 24 LOW-VOLTAGE DETECTOR
Throughout
Deletion of Note of preliminary values
(c)
Major Revisions in Rev.5.00
Throughout
−
Addition of 78F1510A and 78F1512A to 78K0R/LF3 product series
(d)
−
Addition of 78F1513A and 78F1515A to 78K0R/LG3 product series
(d)
−
Addition of 78F1516A and 78F1518A to 78K0R/LH3 product series
(d)
CHAPTER 1 OUTLINE
p.2
Addition of 10-bit resolution A/D conversion (μ PD78F151xA only)
Addition of (μ PD78F150xA only) to 12-bit resolution A/D conversion, 12-bit resolution D/A
converter, Operational amplifier, and On-chip voltage reference (2.0 V/2.5V)
(d)
pp.4 to 5, 7
to 8, 10 to 11
Separation of (1) μ PD78F150xA and (2) μ PD78F151xA from each pin configuration
(d)
pp.6, 9, 12
Addition of AVREF, AVDD, and EVDD1 to each pin identification
(d)
pp.13 to 18
Separation of (1) μ PD78F150xA and (2) μ PD78F151xA from each block diagram
(d)
pp.19 to 22
Separation of (1) μ PD78F150xA and (2) μ PD78F151xA in 1.5 Outline of Functions
(d)
CHAPTER 2 PIN FUNCTIONS
pp.23, 62
Addition of AVDD and EVDD1
(d)
pp.24 to 26,
29 to 32,
35 to 38,
42 to 44,
47 to 56,
60 to 63,
65, 66, 68
Addition of Notes
(d)
pp.43 to 44,
47 to 56
Literal change of 78K0R/LF3 series; from 78F1500A and 78F1502A to 78F15x0A and 78F15x2A
Literal change of 78K0R/LG3 series; from 78F1503A and 78F1505A to 78F15x3A and 78F15x5A
Literal change of 78K0R/LH3 series; from 78F1506A and 78F1508A to 78F15x6A and 78F15x8A
(d)
p.46
Addition of μ PD78F151xA to Table in 2.2.3 P20 to P27
(d)
p.54
Addition of μ PD78F151xA to Table in 2.2.12 P110 to P111
(d)
p.57
Addition of μ PD78F151xA to Table in 2.2.16 P150 to P152, P157
(d)
p.58
Addition of (μ PD78F150xA only) to 2. 2. 20 VREFOUT/AVREFP
Addition of 2.2.21 AVREF (μ PD78F151xA only)
(d)
Remark
“Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
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APPENDIX D REVISION HISTORY
(2/3)
Page
Description
Classification
CHAPTER 3 CPU ARCHITECTURE (continuation)
p.59
Addition of (μ PD78F150xA only) to (1) AVDD0 and (2) AVDD1
Addition of (3) AVDD (μ PD78F151xA only) and (4) EVDD1 (μ PD78F151xA only)
(d)
p.69
Addition of Type 5
(d)
CHAPTER 3 CPU ARCHITECTURE
p.74
Addition of 78F1510A, 78F1513A, and 78F1516 to Figure 3-1. Memory Map
(d)
p.76
Addition of 78F1512A, 78F1515A, and 78F1518A to Figure 3-3. Memory Map
(d)
p.78
Addition of 78F1510A, 78F1513A, 78F1516 and 78F1512A, 78F1515A, 78F1518A to Remark
below Table 3-1. Correspondence Between Address Values and Block Numbers in Flash
Memory
(d)
p.79
Addition of 78F1510A, 78F1513A, 78F1516 and 78F1512A, 78F1515A, 78F1518A to Table 3-2.
Internal ROM Capacity
(d)
p.81
Addition of 78F1510A, 78F1513A, 78F1516 and 78F1512A, 78F1515A, 78F1518A to 3.1.2 Mirror
area
(d)
p.82
Addition of 78F1510A, 78F1513A, and 78F1516 to Example 1 and 78F1512A, 78F1515A, and
78F1518A to Example 2
(d)
p.83
Addition of 78F1510A, 78F1513A, 78F1516 and 78F1512A, 78F1515A, and 78F1518A to Table 34. Internal RAM Capacity
(d)
p.85
Addition of 78F1510A, 78F1513A, and 78F1516A to Figure 3-5. Correspondence Between
Data Memory and Addressing
(d)
p.87
Addition of 78F1512A, 78F1515A, and 78F1518A to Figure 3-7. Correspondence Between
Data Memory and Addressing
(d)
pp.94 to 95
Addition of Note to Table 3-5. SFR List
(d)
CHAPTER 4 PORT FUNCTIONS
p.121
Addition of AVDD and EVDD1
(d)
pp.122 to
128
Addition of Notes
(d)
p.138
Addition of μ PD78F151xA to Table in 4.2.3 Port 2
(d)
p.167
Addition of μ PD78F151xA to Table in 4.2.12 Port 11
(d)
p.176
Addition of μ PD78F151xA to Table in 4.2.16 Port 15
(d)
CHAPTER 10 12-BIT A/D CONVERTER (μ PD78F150xA), 10-BIT A/D CONVERTER (μ PD78F151xA)
p.385
Change of chapter title
(d)
Addition of μ PD78F151xA to Table
Addition of description of 10-bit resolution to 10.1 Function of A/D Converter
p.387
Addition of Figure 10−2. Block Diagram of 10-Bit A/D Converter (μ PD78F151xA)
(d)
p.389
Addition of 10-bit conversion result register to (6)
Addition of AVDD to (9)
Addition of AVREF to (13)
(d)
p.390
Addition of 10-bit conversion result register to 10.3 Registers Used in A/D Converter
(d)
p.395
Addition of (μ PD78F150xA only) to (4) Analog reference voltage control register (ADVRC)
(d)
p.396
Addition of (μ PD78F150xA only) to (5) 12-bit A/D conversion result register (ADCR)
(d)
p.397
Addition of (μ PD78F150xA only) to (6) 10-bit A/D conversion result register (ADCR)
(d)
p.412
Change of value of 1LSB in 10.5 (1) Resolution
(a)
Remark
“Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
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APPENDIX D REVISION HISTORY
(3/3)
Page
Description
Classification
CHAPTER 11 D/A CONVERTER (μ PD78F150xA only)
Addition of (μ PD78F150xA only) to chapter title
p.418
(d)
CHAPTER 12 OPERATIONAL AMPLIFIER (μ PD78F150xA only)
Addition of (μ PD78F150xA only) to chapter title
p.425
(d)
CHAPTER 13 VOLTAGE REFERENCE (μ PD78F150xA only)
Addition of (μ PD78F150xA only) to chapter title
p.434
(d)
CHAPTER 31 ELECTRICAL SPECIFICATIONS
Throughout
Addition of specifications of AVDD, EVDD1, and AVREF
(d)
pp.892, 893
Addition of AMPHS1 = 1 to Conditions of Supply current when fSUB = 32.768 kHz
(b)
p.894
Separation of μ PD78F150xA and μ PD78F151xA in P110, P111 of IADC Conditions
(d)
p.922
Addition of (μ PD78F150xA only) to (1) 12-bit A/D Converter
(d)
p.923
Addition of (μ PD78F150xA only) to (2) 10-bit A/D Converter
(d)
Addition of (μ PD78F150xA only) to (3) Operational amplifier
Addition of (μ PD78F150xA only) to (4) Voltage Reference
Addition of (μ PD78F150xA only) to (5) D/A Converter
p.924
(d)
CHAPTER 32 PACKAGE DRAWINGS
pp.934, 935
Addition of 78F1510AGC-GAD-AX and 78F1512AGC-GAD-AX to 78K0R/LF3 product series
(d)
p.936
Addition of 78F1513AGC-UEU-AX and 78F1515AGC-UEU-AX to 78K0R/LF3 product series
(d)
p.937
Addition of 78F1516AGF-GAT-AX and 78F1518AGF-GAT-AX to 78K0R/LH3 product series
(d)
CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS
p.938
Addition of 78F1510AGC-GAD-AX and 78F1512AGC-GAD-AX to 80 pins
(d)
Addition of 78F1513AGC-UEU-AX and 78F1515AGC-UEU-AX to 100 pins
Addition of 78F1516AGF-GAT-AX and 78F1518AGF-GAT-AX to 128 pins
Change of Caution: from “μ PD78F1503A to 78F1508A” to 78K0R/Lx3
p.939
Addition of 78F1510AGC-GAD-AX and 78F1512AGC-GAD-AX to 80 pins (14 x14)
(d)
Change of Caution: from “μ PD78F1503A to 78F1508A” to 78K0R/Lx3
Remark
“Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
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APPENDIX D REVISION HISTORY
D.2 Revision History of Preceding Editions
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
(1/14)
Edition
2nd Edition
Description
Modification of regulator output voltage of normal power mode
Chapter
Throughout
Addition of timer array unit 1
Modification of related documents
INTRODUCTION
Addition of 1.1 Features
CHAPTER 1 OUTLINE
Modification of 1.3.3 78K0R/LH3
Modification of 1.4.1 78K0R/LF3, 1.4.2 78K0R/LG3, and 1.4.3 78K0R/LH3
Modification of 1.5 Outline of Functions
Modification of 2.1.3 78K0R/LH3
CHAPTER 2 PIN
Addition of 2.2 Description of Pin Functions
FUNCTIONS
Modification of 2.3 Pin I/O Circuits and Recommended Connection of Unused
Pins
Modification of Table 3-3 Vector Table
Modification of 3.2.4 Special function registers (SFRs)
CHAPTER 3 CPU
ARCHITECTURE
Modification of 3.2.5 Extended special function registers (2nd SFRs: 2nd Special
Function Registers)
Modification of Table 4-4 Port functions (78K0R/LH3)
CHAPTER 4 PORT
Modification of 4.2 Port Configuration
FUNCTIONS
Addition of (7) Port function register (PFALL) and (8) Input switch control
register (ISC) to 4.3 Registers Controlling Port Function
Addition of 4.5 Settings of Port Mode Register and Output Latch When Using
Alternate Function
Modification of Figure 5-1 Block Diagram of Clock Generator
CHAPTER 5 CLOCK
Modification of Figure 5-2 Format of Clock Operation Mode Control Register
(CMC)
GENERATOR
Addition of Note 2 and Modification of Caution 1 in Figure 5-6. Format of System
Clock Control Register (CKC)
Modification of Table 5-3 Relationship Between CPU Clock and Minimum
Instruction Execution Time
Modification of Figure 5-7 Format of Peripheral Enable Register 0 (PER0)
Modification of Figure 5-8 Format of Operation Speed Mode Control Register
(OSMC)
Modification of Caution 1 in Figure 5-9 Example of External Circuit of X1
Oscillator and Figure 5-10 Example of External Circuit of XT1 Oscillator
(Crystal Oscillation)
Modification of Figure 5-12 Clock Generator Operation When Power Supply
Voltage Is Turned On (When LVI Default Start Function Stopped Is Set (Option
Byte: LVIOFF = 1)) and Figure 5-13 Clock Generator Operation When Power
Supply Voltage Is Turned On (When LVI Default Start Function Enabled Is Set
(Option Byte: LVIOFF = 0))
Modification of 5.6.1 Example of controlling high-speed system clock, 5.6.2
Example of controlling internal high-speed oscillation clock, and 5.6.3 Example
of controlling subsystem clock
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APPENDIX D REVISION HISTORY
(2/14)
Edition
2nd Edition
Description
Chapter
Modification of Table 5-5 Changing CPU Clock
CHAPTER 5 CLOCK
Modification of Table 5-6 Maximum Time Required for Main System Clock
Switchover, fSUBC ↔fSUBC, Table 5-7 Maximum Number of Clocks Required in
fMAINC ↔ fMAINC (changing the division ratio), fSUBC ↔ fSUBC (changing the division
ratio), and Table 5-9 Maximum Number of Clocks Required in fMAINC ↔ fSUBC
GENERATOR
(continuation)
Addition of chapter
CHAPTER 6 TIMER
ARRAY UNIT
Modification of Table 7-1 Configuration of Real-Time Counter
CHAPTER 7 REAL-
Modification of Figure 7-1 Block Diagram of Real-Time Counter
TIME COUNTER
Modification of Figure 7-2 Format of Peripheral Enable Register 0 (PER0)
Modification of Figure 7-3 Format of Real-Time Counter Control Register 0
(RTCC0)
Modification of Figure 7-4 Format of Real-Time Counter Control Register 1
(RTCC1)
Addition of Caution 3 to Figure 7-5 Format of Real-Time Counter Control
Register 2 (RTCC2)
Modification of (7) Minute count register (MIN) to (9) Day count register (DAY)
Modification of (11) Month count register (MONTH) to (13) Watch error correction
register (SUBCUD)
Addition of (17) Port mode register 3 (PM3)
Modification of Note 2 in Figure 7-19 Procedure for Starting Operation of RealTime Counter
Addition of 7.4.2 Shifting to STOP mode after starting operation
Addition of 7.4.8 Example of watch error correction of real-time counter
Modification of Figure 10-1 Block Diagram of A/D Converter
CHAPTER 10 A/D
Modification of Figure 10-3 Format of Peripheral Enable Register 0 (PER0)
CONVERTER
Addition of Note 1 to Figure 10-4 Format of A/D Converter Mode Register (ADM)
Addition of Table 10-2 A/D Conversion Time Selection
Modification of (4) Analog reference voltage control register (ADVRC)
Modification of Figure 10-10 Format of 8-bit A/D Conversion Result Register
(ADCRH)
Modification of Table 10-4. Setting Functions of ANI0/AMP0-/P20,
ANI2/AMP0+/P22, ANI3/AMP1-/P23, ANI5/AMP1+/P25, ANI6/AMP2-/P26, and
ANI8/AMP2+/P150 Pins, Table 10-5. Setting Functions of ANI1/AMP0O/P21,
ANI4/AMP1O/P24, and ANI7/AMP2O/P27 Pins, and Table 10-7. Setting
Functions of ANI15/AVREFM/P157 Pin
Addition of (12) Rewriting DACSWn during A/D conversion to 10.6 Cautions for
A/D Converter
Modification of Figure 11-1 Block Diagram of D/A Converter
CHAPTER 11 D/A
Modification of Figure 11-2 Format of Peripheral Enable Register 0 (PER0)
CONVERTER
Modification of Remark in Figure 11-3 Format of D/A Converter Mode Register
(DAM)
Addition of Caution to Figure 11-4 Format of D/A Conversion Value Setting
Registers W0 and W1 (DACSW0, DACSW1)
Addition of to 11.4.1 Operation in normal mode and 11.4.2 Operation in realtime output mode
Addition of (3) to 11.5 Cautions for D/A Converter
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APPENDIX D REVISION HISTORY
(3/14)
Edition
2nd Edition
Description
Chapter
Modification of Table 12-1 Configuration of Operational Amplifiers
CHAPTER 12
Addition of (1) Peripheral enable register 0 (PER0)
OPERATIONAL
AMPLIFIER
Modification of Table 12-2 Setting Functions of ANI0/AMP0-/P20,
ANI2/AMP0+/P22, ANI3/AMP1-/P23, ANI5/AMP1+/P25, ANI6/AMP2-/P26, and
ANI8/AMP2+/P150 Pins Table 12-3 Setting Functions of ANI1/AMP0O/P21,
ANI4/AMP1O/P24, and ANI7/AMP2O/P27 Pins, and Table 12-5 Setting Functions
of ANI15/AVREFM/P157 Pin
Addition of to 12.4.1 Single AMP Mode
Modification of Table 13-1 Configuration of Voltage Reference
CHAPTER 13
Modification of Figure 13-1 Block Diagram of Voltage Reference
VOLTAGE REFERENCE
Addition of (1) Peripheral enable register 0 (PER0)
Modification of (2) A/D reference voltage control register (ADVRC)
Modification of 13.4.1 Reference voltage output mode
Modification of Figure 14-4 Format of Peripheral Enable Register 0 (PER0)
Modification of Caution 2 in Figure 14-5 Format of Serial Clock Select Register m
(SPSm)
CHAPTER 14 SERIAL
ARRAY UNIT
Modification of Figure 14-22 Peripheral Enable Register 0 (PER0) Setting When
Stopping the Operation by Units
Modification of Caution in Figure 14-25 Initial Setting Procedure for Master
Transmission
Modification of Caution in Figure 14-29 Flowchart of Master Transmission (in
Single-Transmission Mode)
Modification of Caution in Figure 14-31 Flowchart of Master Transmission (in
Continuous Transmission Mode)
Modification of Caution in Figure 14-33 Initial Setting Procedure for Master
Reception
Modification of Caution in Figure 14-37 Flowchart of Master Reception (in SingleReception Mode)
Modification of Caution in Figure 14-39 Initial Setting Procedure for Master
Transmission/Reception
Modification of Caution in Figure 14-43 Flowchart of Master
Transmission/Reception (in Single- Transmission/Reception Mode)
Modification of Caution in Figure 14-45 Flowchart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode)
Modification of Caution in Figure 14-47 Initial Setting Procedure for Slave
Transmission
Modification of Caution in Figure 14-51 Flowchart of Slave Transmission (in
Single-Transmission Mode)
Modification of Caution in Figure 14-53 Flowchart of Slave Transmission (in
Continuous Transmission Mode)
Modification of Caution in Figure 14-55 Initial Setting Procedure for Slave
Reception
Modification of Caution in Figure 14-59 Flowchart of Slave Reception (in SingleReception Mode)
Modification of Caution in Figure 14-61 Initial Setting Procedure for Slave
Transmission/Reception
Modification of Caution in Figure 14-65 Flowchart of Slave
Transmission/Reception (in Single- Transmission/Reception Mode)
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APPENDIX D REVISION HISTORY
(4/14)
Edition
2nd Edition
Description
Modification of Caution in Figure 14-67 Flowchart of Slave
Transmission/Reception (in Continuous Transmission/Reception Mode)
Modification of Caution in Figure 14-69 Initial Setting Procedure for UART
Transmission
Chapter
CHAPTER 14 SERIAL
ARRAY UNIT
(continuation)
Modification of Caution in Figure 14-73 Flowchart of UART Transmission (in
Single-Transmission Mode)
Modification of Caution in Figure 14-75 Flowchart of UART Transmission (in
Continuous Transmission Mode)
Modification of Caution in Figure 14-77 Initial Setting Procedure for UART
Reception
Modification of Caution in Figure 14-81 Flowchart of UART Reception
Modification of Caution in Figure 14-89 Initial Setting Procedure for Address
Field Transmission
Modification of Figure 15-5 Format of Peripheral Enable Register 0 (PER0)
CHAPTER 15 SERIAL
Addition of 15.4.2 Setting transfer clock by using IICWL and IICWH registers
INTERFACE IICA
Addition of Caution to 15.5.7 Canceling wait
Modification of Table 15-3 Bit Definitions of Main Extension Code
Modification of Figure 15-23 Flow When Setting WUP = 0 upon Address Match
(Including Extension Code Reception) to Figure 15-25 When Operating as Slave
Device after Releasing STOP Mode other than by INTIICA (When Not Required
to Operate as Master Device)
Modification of Figure 15-33 Example of Master to Slave Communication and
Figure 15-34 Example of Slave to Master Communication
Modification of Figure 16-1 Block Diagram of LCD Controller/Driver
CHAPTER 16 LCD
Modification of Figure 16-5 Format of LCD boost level control register (VLCD)
CONTROLLER/DRIVER
Addition of Caution 1 to Figure 16-7 Format of Segment Enable Register
(SEGEN)
Modification of Figure 16-33 Examples of LCD Drive Power Connections
(Internal Voltage Boosting Method)
Modification of Figure 17-4 Format of Multiplication/Division Data Register C
(MDCH, MDCL)
CHAPTER 17
MULTIPLIER/DIVIDER
Modification of Table 18-2 Response Time of DMA Transfer
CHAPTER 18 DMA
CONTROLLER
Modification of Maskable interrupts
CHAPTER 19
Modification of Table 19-1 Interrupt Source List
INTERRUPT
FUNCTIONS
Modification of Figure 19-1 Basic Configuration of Interrupt Function
Modification of Table 19-2 Flags Corresponding to Interrupt Request Sources
Modification of Figure 19-2 Format of Interrupt Request Flag Registers (IF0L,
IF0H, IF1L, IF1H, IF2L, IF2H) (78K0R/LF3) to Figure 19-4 Format of Interrupt
Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (78K0R/LH3)
Modification of Figure 19-5 Format of Interrupt Mask Flag Registers (MK0L,
MK0H, MK1L, MK1H, MK2L, MK2H) (78K0R/LF3) to Figure 19-7 Format of
Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
(78K0R/LH3)
Modification of Figure 19-8 Format of Priority Specification Flag Registers
(PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H,
PR12L, PR12H) (78K0R/LF3) to Figure 19-10 Format of Priority Specification
Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H,
PR11L, PR11H, PR12L, PR12H) (78K0R/LH3)
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(5/14)
Edition
2nd Edition
Description
Chapter
Modification of Caution 2 in Figure 20-2 Format of Key Return Mode Register
(KRM)
CHAPTER 20 KEY
Addition of Table 21-1 Operating Statuses in HALT Mode (3/3)
CHAPTER 21
Modification of Note in Figure 21-3 HALT Mode Release by Interrupt Request
Generation
STANDBY FUNCTION
INTERRUPT
FUNCTION
Modification of Figure 21-4 HALT Mode Release by Reset
Modification of Figure 21-5 Operation Timing When STOP Mode Is Released
(When Unmasked Interrupt Request Is Generated)
Modification of Figure 21-6 STOP Mode Release by Interrupt Request Generation
Modification of Figure 21-7 STOP Mode Release by Reset
Modification of Figure 22-2 Timing of Reset by RESET Input to Figure 22-4
Timing of Reset in STOP Mode by RESET Input
CHAPTER 22 RESET
FUNCTION
Modification of Table 22-1 Operation Statuses During Reset Period
Modification of Table 22-2 Hardware Statuses After Reset Acknowledgment
Modification of Figure 23-2 Timing of Generation of Internal Reset Signal by
Power-on-Clear Circuit and Low-Voltage Detector
CHAPTER 23 POWER-
Modification of Caution 1 in Figure 24-2 Format of Low-Voltage Detection
Register (LVIM)
CHAPTER 24 LOW-
ON-CLEAR CIRCUIT
VOLTAGE DETECTOR
Modification of 24.4.1 When used as reset • When stopping operation
Modification of 24.4.2 When used as interrupt • When stopping operation
Modification of Cautions 1, 2 in Figure 25-1 Format of Regulator Mode Control
Register (RMC)
CHAPTER 25
REGULATOR
Modification of Caution 4 in 27.8 Flash Memory Programming by SelfProgramming
CHAPTER 27 FLASH
MEMORY
Absolute Maximum Ratings
CHAPTER 31
• Modification of Output voltage (VO4), Output current, high (IOH3), Output current,
low (IOL3)
ELECTRICAL
DC Characteristics
SPECIFICATIONS
(TARGET)
• Modification of Output current, high (IOH2), Output current, low (IOL2), Output
voltage, high (VOH2), Output voltage, low (VOL2), Supply current (IDD2), A/D
converter operating current (IADC), Operational amplifier operating current
(IAMP), Voltage reference operating current (IVR), LCD operating current (ILCD2,
ILCD3)
(1) Basic operation in AC Characteristics
• Modification of Instruction cycle
• Addition of Note
• Modification of Minimum instruction execution time during main system clock
operation (FSEL = 0, RMC = 00H) to Minimum instruction execution time
during self programming mode (RMC = 00H)
• Addition of Minimum instruction execution time during self programming
mode (RMC = 5AH)
(2) Serial interface: Serial array unit in AC Characteristics
• Modification of (d) Data hold time (transmission) in During communication at
2
same potential (simplified I C mode)
• Modification of (h) Data hold time (transmission) in Communication at different
2
potential (2.5 V, 3 V) (simplified I C mode)
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(6/14)
Edition
2nd Edition
Description
Chapter
(3) Serial interface: IICA in AC Characteristics
CHAPTER 31
• Modification of Table
ELECTRICAL
(3) Voltage Reference in Analog Characteristics
SPECIFICATIONS
• Addition of Remark
(TARGET)
(continuation)
(4) D/A Converter in Analog Characteristics
• Addition of Gain error (EG)
(2) Internal voltage boosting method in LCD Characteristics
• Modification of LCD output voltage variation range
(3) Capacitor split method in LCD Characteristics
• Modification of VLC0 voltage
Addition of chapter
APPENDIX A
DEVELOPMENT
TOOLS
Addition of chapter
APPENDIX B
REVISION HISTORY
3rd Edition
DF781508, QB-78K0RLX3: Under development → Under mass production
Throughout
Addition of QB-Programmer Programming GUI Operation User’s Manual to
Related Documents
INTRODUCTION
Modification of 1.1 Features
CHAPTER 1 OUTLINE
Modification of 2.2.21 RESET and 2.2.22 REGC
CHAPTER 2 PIN
FUNCTIONS
Addition of Note 1 to Figure 3-1 Memory Map (μPD78F1500, 78F1503, 78F1506)
CHAPTER 3 CPU
Addition of Note 1 to Figure 3-2 Memory Map (μPD78F1501, 78F1504, 78F1507)
ARCHITECTURE
Addition of Note 1 to and modification of Figure 3-3 Memory Map (μPD78F1502,
78F1505, 78F1508)
Modification of description in 3.1.1 (1) Vector table area
Modification of 3.1.2 Mirror area
Modification of description in and addition of Cautions 1, 2 to 3.1.3 Internal data
memory space
Modification of Figure 3-7 Correspondence Between Data Memory and
Addressing (μPD78F1502, 78F1505, 78F1508)
Addition of Cautions 2, 3 to 3.2.1 (3) Stack pointer (SP)
Modification of Figure 4-1 Block Diagram of P00 and P01
CHAPTER 4 PORT
Modification of Figure 4-2 Block Diagram of P02
FUNCTIONS
Modification of Figure 5-6 Format of System Clock Control Register (CKC)
CHAPTER 5 CLOCK
Modification of in 5.6.2 (2) Example of setting procedure when using internal
high-speed oscillation clock as CPU/peripheral hardware clock
GENERATOR
Modification of Table 5-4 CPU Clock Transition and SFR Register Setting
Examples
Modification of Table 5-8 Maximum Number of Clocks Required in fIH ↔fMX and
Table 5-9 Maximum Number of Clocks Required in fMAINC ↔fSUBC
Modification of Note 1 in Figure 6-6 Format of Timer Clock Select Register m
(TPSm)
CHAPTER 6 TIMER
ARRAY UNIT
Modification of Figure 6-7 Format of Timer Mode Register mn (TMRmn) (1/4)
Addition of description of Event counter mode to Table 6-4 Operations from Count
Operation Enabled State to TCRmn Count Start
Addition of description to 6.4.3
(1)
Changing values set in registers
TOp,TOEp,TOLp, and TOMp during timer operation
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APPENDIX D REVISION HISTORY
(7/14)
Edition
3rd Edition
Description
Chapter
Addition of description to 6.7.1 Operation as interval timer/square wave output
CHAPTER 6 TIMER
Modification of Figure 6-37 Block Diagram of Operation as Interval
Timer/Square Wave Output
ARRAY UNIT
Addition of (2) When the timer input (TIpq pin input, fSUB/4, fSUB/2 or INTRTCI) is
selected as count clock to Figure 6-39 Example of Set Contents of Registers
During Operation as Interval Timer/Square Wave Output
Modification of Figure 6-40 Operation Procedure of Interval Timer/Square Wave
Output Function (1/2)
Modification of Caution in Figure 7-3 Format of Real-Time Counter Control
Register 0 (RTCC0)
CHAPTER 7 REALTIME COUNTER
Addition of description to 7.3 (8) Hour count register (HOUR)
Addition of description to Figure 7-14 Format of Watch Error Correction Register
(SUBCUD)
Modification of Figure 7-26 512 Hz or 16.384 kHz Output Setting Procedure
Addition of Caution 3 to Figure 9-2 Format of Clock Output Select Register n
(CKSn)
CHAPTER 9 CLOCK
Modification of Remark in 9.4.1 Operation as output pin
OUTPUT
CONTROLLER
Modification of Figure 9-4 Remote Control Output Application Example
Addition of Notes 2, 3 to and modification of Cautions 1, 2 in Figure 10-4 Format
of A/D Converter Mode Register (ADM)
OUTPUT/BUZZER
CHAPTER 10 A/D
CONVERTER
Modification of Table 10-2 A/D Conversion Time Selection
Modification of description in 10.3 (4) Analog reference voltage control register
(ADVRC)
Modification of Figure 10-8 Format of Analog Reference Voltage Control
Register (ADVRC)
Addition of to and modification of and Caution 4 in 10.4.1 Basic
operations of A/D converter
Modification of Figure 10-16 Software trigger mode (Continuous conversion
mode)
Modification of Figure 10-17 Software trigger mode (Single conversion mode)
Modification of in 10.4.3 (3) Timer trigger mode (Continuous conversion
mode)
Modification of Figure 10-18 Timer trigger mode (Continuous conversion mode)
Modification of in and addition of to 10.4.3 (4) Timer trigger mode (Single
conversion mode)
Modification of Figure 10-19 Timer trigger mode (Single conversion mode)
Addition of to and modification of , and Caution 7 in setting methods of
10.4.3 A/D converter operation modes
Modification of 10.6 (1) Operating current in STOP mode and (12) Rewriting
DACSWn during A/D conversion
Modification of Figure 11-1 Block Diagram of D/A Converter
CHAPTER 11 D/A
Addition of Note 1 to and modification of Note 2 and Remark in Figure 11-3
Format of D/A Converter Mode Register (DAM)
CONVERTER
Modification of Caution in Figure 11-4 Format of D/A Conversion Value Setting
Registers W0 and W1 (DACSW0, DACSW1)
Modification of , in and addition of Cautions 1, 2 to 11.4.1 Operation in
normal mode
Modification of , , in and addition of Cautions 1 to 3 to 11.4.2
Operation in real-time output mode
Modification of (3) in 11.5 Cautions for D/A Converter
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(8/14)
Edition
3rd Edition
Description
Addition of to 12.4.1 Single AMP Mode
Chapter
CHAPTER 12
OPERATIONAL
AMPLIFIER
Modification of Figure 13-1 Block Diagram of Voltage Reference
CHAPTER 13
Modification of description in 13.3 (2) Analog reference voltage control register
(ADVRC)
VOLTAGE REFERENCE
Modification of Figure 13-3 Format of Analog Reference Voltage Control
Register (ADVRC)
Modification of to in 13.4.1 Reference voltage output mode
Addition of 13.5 Cautions for Voltage Reference
2
Addition of Note to 14.1.3 Simplified I C (IIC10, IIC20)
CHAPTER 14 SERIAL
Modification of Figure 14-1 Block Diagram of Serial Array Unit 0
ARRAY UNIT
Modification of Figure 14-2 Block Diagram of Serial Array Unit 1
Modification of Note 2 in Figure 14-5 Format of Serial Clock Select Register m
(SPSm)
Modification of description of and addition of Note to Figure 14-7 Format of Serial
Communication Operation Setting Register mn (SCRmn) (1/3)
Addition of Caution 3 to Figure 14-8 Format of Serial Data Register mn (SDRmn)
Addition of Note to Figure 14-9 Format of Serial Status Register mn (SSRmn)
Modification of Figure 14-10 Format of Serial Flag Clear Trigger Register mn
(SIRmn)
Modification of Figure 14-26 Procedure for Stopping Master Transmission
Modification of Figure 14-27 Procedure for Resuming Master Transmission
Modification of Figure 14-28 Timing Chart of Master Transmission (in SingleTransmission Mode)
Modification of Figure 14-30 Timing Chart of Master Transmission (in
Continuous Transmission Mode)
Modification of Figure 14-31 Flowchart of Master Transmission (in Continuous
Transmission Mode)
Modification of Figure 14-36 Timing Chart of Master Reception (in SingleReception Mode)
Modification of Figure 14-40 Procedure for Stopping Master
Transmission/Reception
Modification of Figure 14-41 Procedure for Resuming Master
Transmission/Reception
Modification of Figure 14-42 Timing Chart of Master Transmission/Reception (in
Single-Transmission/Reception Mode)
Modification of Figure 14-44 Timing Chart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode)
Modification of Figure 14-45 Flowchart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode)
Modification of 14.5.4 Slave transmission and Note 1
Modification of Figure 14-48 Procedure for Stopping Slave Transmission
Modification of Figure 14-49 Procedure for Resuming Slave Transmission
Modification of Figure 14-50 Timing Chart of Slave Transmission (in SingleTransmission Mode)
Modification of Figure 14-52 Timing Chart of Slave Transmission (in Continuous
Transmission Mode)
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(9/14)
Edition
3rd Edition
Description
Chapter
Modification of Figure 14-53 Flowchart of Slave Transmission (in Continuous
Transmission Mode)
CHAPTER 14 SERIAL
Modification of 14.5.5 Slave reception and Note 1
(continuation)
ARRAY UNIT
Modification of Figure 14-57 Procedure for Resuming Slave Reception
Modification of Figure 14-58 Timing Chart of Slave Reception (in SingleReception Mode)
Modification of 14.5.6 Slave transmission/reception and Note 1
Modification of Figure 14-62 Procedure for Stopping Slave
Transmission/Reception
Modification of Figure 14-63 Procedure for Resuming Slave
Transmission/Reception
Modification of Figure 14-64 Timing Chart of Slave Transmission/Reception (in
Single-Transmission/Reception Mode)
Modification of Figure 14-66 Timing Chart of Slave Transmission/Reception (in
Continuous Transmission/Reception Mode)
Modification of Figure 14-67 Flowchart of Slave Transmission/Reception (in
Continuous Transmission/Reception Mode)
Modification of Note 2 in Table 14-2 Selection of operation clock
Addition of Caution to 14.6 Operation of UART (UART0, UART1, UART2, UART3)
Communication
Modification of Figure 14-70 Procedure for Stopping UART Transmission
Modification of Figure 14-72 Timing Chart of UART Transmission (in SingleTransmission Mode)
Modification of Figure 14-74 Timing Chart of UART Transmission (in
Continuous Transmission Mode)
Modification and addition of description in 14.6.2 UART reception
Addition of description of Figure 14-76 Example of Contents of Registers for
UART Reception of UART (UART0, UART1, UART2, UART3)
Modification of Figure 14-80 Timing Chart of UART Reception
Modification of the transfer data length in 14.6.3 LIN transmission
Modification of Note 2 in Figure 14-82 Transmission Operation of LIN
Modification of the transfer data length in 14.6.4 LIN reception
Modification of Note 2 in Table 14-3 Selection of operation clock
2
Addition of Note to 14.7 Operation of Simplified I C (IIC10, IIC20)
Communication
Addition of Note, Remark and the description of the transfer rate to 14.7.1 Address
field transmission
Modification of Figure 14-89 Initial Setting Procedure for Address Field
Transmission
Modification of Figure 14-90 Timing Chart of Address Field Transmission
Addition of Note, Remark and the description of the transfer rate to 14.7.2 Data
transmission
Modification of Figure 14-93 Timing Chart of Data Transmission
Addition of Note, Remark and the description of the transfer rate to 14.7.3 Data
reception
Modification of Figure 14-96 Timing Chart of Data Reception
Modification of Figure 14-97 Flowchart of Data Reception
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APPENDIX D REVISION HISTORY
(10/14)
Edition
3rd Edition
Description
Chapter
Modification of and addition of Note to Figure 14-98 Timing Chart of Stop
Condition Generation
CHAPTER 14 SERIAL
Addition of Caution to 14.7.5 Calculating transfer rate
(continuation)
ARRAY UNIT
Modification of Note 2 in Table 14-4 Selection of operation clock
Addition of Caution 3 to Figure 15-3 Format of IICA Shift Register (IICA)
CHAPTER 15 SERIAL
Modification of description in 15.2 (2) Slave address register (SVA)
INTERFACE IICA
Modification of description in Figure 15-4 Format of Slave Address Register
(SVA)
Addition of Note 3 to and modification of Caution in Figure 15-6 Format of IICA
Control Register 0 (IICCTL0) (1/4)
Addition of description to Figure 15-6 Format of IICA Control Register 0
(IICCTL0) (2/4)
Modification of description in Figure 15-6 Format of IICA Control Register 0
(IICCTL0) (3/4)
Addition of description to Figure 15-9 Format of IICA Control Register 1
(IICCTL1) (1/2)
Modification of 15.4.2 (1) Setting transfer clock on master side
Modification of Figure 15-23 Flow When Setting WUP = 0 upon Address Match
(Including Extension Code Reception)
Modification of Figure 15-24 When Operating as Master Device after Releasing
STOP Mode other than by INTIICA and deletion of Figure 15-25 When Operating
as Slave Device after Releasing STOP Mode other than by INTIICA (When Not
Required to Operate as Master Device) in old edition
Modification of 15.5.14 (1) When communication reservation function is enabled
(bit 0 (IICRSV) of IICA flag register (IICF) = 0)
Modification of Note 1 in Figure 15-27 Communication Reservation Protocol
Modification of Note in Figure 15-29 Master Operation in Multi-Master System
(2/3)
Modification of Figure 16-1 Block Diagram of LCD Controller/Driver
CHAPTER 16 LCD
Addition of Caution 4 to and modification of Caution 5 in Figure 16-3 Format of
LCD Display Mode Register
CONTROLLER/DRIVER
Modification of Figure 16-4 Format of LCD Clock Control Register
Addition of Caution 5 to and modification of Figure 16-5 Format of LCD boost
level control register (VLCD)
Addition of to 16.5 (2) Internal voltage boosting method
Addition of Caution to Figure 16-31 Examples of LCD Drive Power Connections
(External Resistance Division Method)
Modification of description in 19.2 Interrupt Sources and Configuration
CHAPTER 19
INTERRUPT
FUNCTIONS
Modification of Table 21-2 Operating Statuses in STOP Mode
CHAPTER 21
STANDBY FUNCTION
Modification of Caution 1
CHAPTER 22 RESET
Modification of Figure 22-1 Block Diagram of Reset Function
FUNCTION
Modification of Table 22-1 Operation Statuses During Reset Period
Modification of Table 22-2 Hardware Statuses After Reset Acknowledgment
Modification of 22.1 Register for Confirming Reset Source
Modification of and addition of Caution 2 to Figure 22-5 Format of Reset Control
Flag Register (RESF)
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APPENDIX D REVISION HISTORY
(11/14)
Edition
3rd Edition
Description
Modification of Figure 23-1 Block Diagram of Power-on-Clear Circuit
Chapter
CHAPTER 23 POWERON-CLEAR CIRCUIT
Modification of Note 4 in Figure 24-2 Format of Low-Voltage Detection Register
(LVIM)
CHAPTER 24 LOWVOLTAGE DETECTOR
24.4.1 (1) When detecting level of supply voltage (VDD)
• Modification of in (a) When LVI default start function stopped is set
(LVIOFF = 1)
24.4.1 (2) When detecting level of input voltage from external input pin (EXLVI)
• Modification of
24.4.2 (1) When detecting level of supply voltage (VDD)
• Modification of in (a) When LVI default start function stopped is set
(LVIOFF = 1)
24.4.2 (2) When detecting level of input voltage from external input pin (EXLVI)
• Modification of
Modification of Figure 24-12 Delay from the time LVI reset source is generated
until the time LVI reset has been generated or released
Modification of 25.1 Regulator Overview
CHAPTER 25
Addition of Caution 1, 4 to Figure 25-1 Format of Regulator Mode Control
Register (RMC)
REGULATOR
Addition of 26.4 Setting of Option Byte
CHAPTER 26 OPTION
BYTE
Modification of 27.4.5 REGC pin
CHAPTER 27 FLASH
Addition of Caution 5 to 27.8 Flash Memory Programming by Self-Programming
MEMORY
Modification of 27.8.2 Flash shield window function
Modification of chapter
CHAPTER 31
ELECTRICAL
SPECIFICATIONS
(TARGET)
Addition of chapter
APPENDIX B
REGISTER INDEX
Addition of chapter
APPENDIX C LIST OF
CAUTIONS
Addition of D.2 Revision History of Preceding Editions
APPENDIX D
REVISION HISTORY
4th Edition
Change URL of Renesas Electronics website
Throughout
Change product names to A version (μPD78F150xA)
Deletion of target from the capacitance value of the capacitor connected to the
REGC pin
Change names of A/D conversion modes
•
conversion mode 1 → normal mode 1
•
conversion mode 2 → normal mode 2
•
conversion mode 3 → low voltage mode
Addition of description of 20 MHz internal high-speed oscillation clock oscillator
Change of 1.2 Ordering Information
CHAPTER 1 OUTLINE
Change the value of vectored interrupt sources of 78K0R/LF3
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APPENDIX D REVISION HISTORY
(12/14)
Edition
4th Edition
Description
Chapter
Change of description of the wait time of the FSEL
CHAPTER 5 CLOCK
Change of 5.4.3 Internal high-speed oscillator
GENERATOR
Change of Figure 5-13. Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte:
LVIOFF = 1)) and Figure 5-14. Clock Generator Operation When Power Supply
Voltage Is Turned On (When LVI Default Start Function Enabled Is Set (Option
Byte: LVIOFF = 0))
Change of 5.6.5 CPU clock status transition diagram
Change of 5.6.6 Condition before changing CPU clock and processing after
changing CPU clock
Change of 8.4.3 Setting window open period of watchdog timer
CHAPTER 8
WATCHDOG TIMER
Deletion of TBD from operation stabilization time 1 μs of A/D voltage comparator
Change of voltage boost circuit stabilization time (TBD) to (10 μs)
CHAPTER 10 A/D
CONVERTER
Addition of Note 4 to Table 10-2. A/D Conversion Time Selection
Deletion of TBD from the output impedance within 1 kΩ of the analog input source
Change of Table 10-8. Resistance and Capacitance Values of Equivalent Circuit
(Reference Values)
Change of wait time to 20 μs or more and deletion of TBD from the settling time (18
μs (MAX.))
CHAPTER 11 D/A
Change of turn-on time (TBD) to 20 μs (MAX.)
CHAPTER 12
CONVERTER
OPERATIONAL
AMPLIFIER
Change of Caution 3 of Figure 14-8. Format of Serial Data Register mn
(SDRmn)
CHAPTER 14 SERIAL
ARRAY UNIT
Change of Caution of 14.7.5 Calculating transfer rate
Addition of description to Caution of Figure 15-6. Format of IICA Control Register 0
(IICCTL0) (4/4)
CHAPTER 15 SERIAL
INTERFACE IICA
Addition of description to Note of Figure 15-7. Format of IICA Status Register
(IICS) (2/3)
Addition of Note to Figure 15-9. Format of IICA Control Register 1 (IICCTL1)
(1/2)
Change of 15.4.2 Setting transfer clock by using IICWL and IICWH registers
Change of 15.6 Timing Charts
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APPENDIX D REVISION HISTORY
(13/14)
Edition
4th Edition
Description
Chapter
Addition of example of calculation of LCD frame frequency to (c) and (d) of Figure
16-13. Common Signal Waveforms (2/2)
Change of Caution of Figure 16-31. Examples of LCD Drive Power Connections
(External Resistance Division Method)
CHAPTER 16 LCD
CONTROLLER/
DRIVER
Change the capacitance value of external capacitors to 0.47 μF±30% in 16.8.2
Internal voltage boosting method and 16.8.3 Capacitor split method
Addition of Note to Figure 18-4. Format of DMA Mode Control Register n
(DMCn) (1/2)
CHAPTER 18 DMA
CONTROLLER
Change of description of Figure 18-7. Example of Setting for CSI Consecutive
Transmission
Addition of 18.5.2 CSI master reception and 18.5.3 CSI transmission/reception
Change of 18.5.6 Holding DMA transfer pending by DWAITn and addition of
Caution
Change of 18.5.7 Forced termination by software
Change of 18.6 Cautions on Using DMA Controller
Change value of maskable interrupts of 78K0R/LF3
CHAPTER 19
INTERRUPT
FUNCTIONS
Change of Figure 26-1. Format of User Option Byte (000C0H/010C0H) (1/2)
CHAPTER 26 OPTION
Change of 26.4 Setting of Option Byte
BYTE
Addition of Figure 27-3. Example of Wiring Adapter for Flash Memory Writing
(μPD78F1508A)
CHAPTER 27 FLASH
MEMORY
Addition of 27.9 Creating ROM Code to Place Order for Previously Written
Product
Change of Examples 2 in 29.3 BCD Correction Circuit Operation
CHAPTER 29 BCD
CORRECTION
CIRCUIT
Change of Table 30-5. Operation List
CHAPTER 30
INSTRUCTION SET
Deletion of (TARGET)
CHAPTER 31
Change of analog output voltage, output current, high, and output current, low in
Absolute Maximum Ratings (TA = 25°C)
ELECTRICAL
SPECIFICATIONS
Change of Internal Oscillator Characteristics
Addition of Recommended oscillator circuit constants
Change of output voltage, low (VOL2), supply current, and operating current of DC
Characteristics
Change of Caution of (1) Basic operation (3/6) in AC Characteristics
Change of (b) During communication at same potential (CSI mode) (master
mode, SCKp... internal clock output) of (2) Serial interface: Serial array unit
(2/18) and addition of Note 1
Change of (c) During communication at same potential (CSI mode) (slave mode,
SCKp... external clock input) of (2) Serial interface: Serial array unit (3/18)
2
Change of (d) During communication at same potential (simplified I C mode) of
(2) Serial interface: Serial array unit (5/18)
Change of (f) Communication at different potential (2.5 V, 3 V) (CSI mode)
(master mode, SCKp... internal clock output) (1/2) of (2) Serial interface: Serial
array unit (11/18) and addition of Note 1
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1011
78K0R/Lx3
APPENDIX D REVISION HISTORY
(14/14)
Edition
4th Edition
Description
Chapter
Change of (f) Communication at different potential (2.5 V, 3 V) (CSI mode)
(master mode, SCKp... internal clock output) (2/2) of (2) Serial interface: Serial
array unit (12/18)
Change of (g) Communication at different potential (2.5 V, 3 V) (CSI mode)
(slave mode, SCKp... external clock input) of (2) Serial interface: Serial array
unit (14/18)
CHAPTER 31
ELECTRICAL
SPECIFICATIONS
(continuation)
2
Change of (h) Communication at different potential (2.5 V, 3 V) (simplified I C
mode) of (2) Serial interface: Serial array unit (17/18)
Change of Analog Characteristics
Addition of chapter
CHAPTER 33
RECOMMENDED
SOLDERING
CONDITIONS
Addition of part number of flash memory programming adapter
APPENDIX A
DEVELOPMENT
TOOLS
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
1012
78K0R/Lx3 User’s Manual: Hardware
Publication Date:
Rev.0.01
Rev.5.01
Apr 30, 2008
Jun 20, 2011
Published by:
Renesas Electronics Corporation
http://www.renesas.com
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Colophon 1.0
78K0R/Lx3
R01UH0004EJ0501
