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April 1st, 2010
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Notice
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All information included in this document is current as of the date this document is issued. Such information, however, is
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12.
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User’s Manual
78K0S/KY1+
8-bit Single-Chip Microcontrollers
μPD78F9210
μPD78F9210(A)
μPD78F9210(A2)
μPD78F9510
μPD78F9211
μPD78F9212
μPD78F9211(A) μPD78F9212(A)
μPD78F9211(A2) μPD78F9212(A2)
μPD78F9511
μPD78F9512
Document No. U16994EJ6V0UD00 (6th edition)
Date Published November 2009 NS
©
Printed in Japan
2004
[MEMO]
2
User’s Manual U16994EJ6V0UD
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected
wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH
(MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the
device when the input level is fixed, and also in the transition period when the input level passes through the
area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related
to unused pins must be judged separately for each device and according to related specifications governing
the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of
static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control
must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators
that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work benches
and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices
must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted
semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device.
Immediately after the power source is turned ON, devices with reset functions have not yet been initialized.
Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not
initialized until the reset signal is received. A reset operation must be executed immediately after power-on
for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for
each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while
the device is not powered. The current injection that results from input of such a signal or I/O pull-up power
supply may cause malfunction and the abnormal current that passes in the device at this time may cause
degradation of internal elements. Input of signals during the power off state must be judged separately for
each device and according to related specifications governing the device.
User’s Manual U16994EJ6V0UD
3
Windows is a registered trademark or a trademark of Microsoft Corporation in the United States and/or other
countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
• The information in this document is current as of November, 2009. The information is subject to change without notice. For
actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date
specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an
NEC Electronics sales representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC
Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
• NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the
use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual
property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in
semiconductor product operation and application examples. The incorporation of these circuits, software and information in
the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no
responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and
information.
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree
and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property
or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient
safety measures in their design, such as redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The
"Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality
assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its
quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in
a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual
equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anticrime systems, safety equipment and medical equipment (not specifically designed for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and
medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data
sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics,
they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a
given application.
(Note 1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned
subsidiaries.
(Note 2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined
above).
(M8E0909)
4
User’s Manual U16994EJ6V0UD
INTRODUCTION
Target Readers
This manual is intended for user engineers who wish to understand the functions of
the 78K0S/KY1+ in order to design and develop its application systems and
programs.
The target devices are the following subseries products.
• 78K0S/KY1+: μPD78F9210, 78F9211, 78F9212, 78F9210(A), 78F9211(A),
78F9212(A), 78F9210(A2), 78F9211(A2), 78F9212(A2), 78F9511,
78F9512
Purpose
This manual is intended to give users on understanding of the functions described in
the Organization below.
Organization
Two manuals are available for 78K0S/KY1+: this manual and the Instruction Manual
(common to the 78K/0S Series).
78K/0S Series
78K0S/KY1+
Instructions
User’s Manual
User’s Manual
• Pin functions
• CPU function
• Internal block functions
• Instruction set
• Interrupts
• Instruction description
• Other internal peripheral functions
• Electrical specifications
How to Use This Manual
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
◊ To understand the overall functions of 78K0S/KY1+
→ Read this manual in the order of the CONTENTS. The mark shows major
revised points. The revised points can be easily searched by copying an “”
in the PDF file and specifying it in the “Find what:” field.
◊ How to read register formats
→ For a bit number enclosed in angle brackets (), the bit name is defined as a
reserved word in the RA78K0S, and is defined as an sfr variable using the
#pragma sfr directive in the CC78K0S.
◊ To learn the detailed functions of a register whose register name is known
→ See APPENDIX B REGISTER INDEX.
◊ To learn the details of the instruction functions of the 78K/0S Series
→ Refer to 78K/0S Series Instructions User’s Manual (U11047E) separately
available.
◊ To learn the electrical specifications of the 78K0S/KY1+
→ See CHAPTER 19 and CHAPTER 20 ELECTRICAL SPECIFICATIONS.
User’s Manual U16994EJ6V0UD
5
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representation: ××× (overscore over pin or signal name)
Note:
Footnote for item marked with Note in the text
Caution:
Information requiring particular attention
Remark:
Supplementary information
Numerical representation: Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
78K0S/KY1+ User’s Manual
This manual
78K/0S Series Instructions User’s Manual
U11047E
Documents Related to Development Software Tools (User’s Manuals)
Document Name
RA78K0S Ver.2.00 Assembler Package
CC78K0S Ver.2.00 C Compiler
SM+ System Simulator
ID78K0S-QB Ver.3.00 Integrated Debugger
Document No.
Operation
U17391E
Language
U17390E
Structured Assembly Language
U17389E
Operation
U17416E
Language
U17415E
Operation
U18601E
User Open Interface
U18212E
Operation
U18493E
PM+ Ver.6.30
U18416E
Documents Related to Development Hardware Tools (User’s Manuals)
Document Name
Document No.
QB-78K0SKX1 In-Circuit Emulator
U18219E
QB-MINI2 On-Chip Debug Emulator with Programming Function
U18371E
Documents Related to Flash Memory Writing (User’s Manuals)
Document Name
Document No.
PG-FP5 Flash Memory Programmer
U18865E
QB-Programmer Programming GUI
Caution
Operation
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
6
U18527E
User’s Manual U16994EJ6V0UD
Other Related Documents
Document Name
Document No.
SEMICONDUCTOR SELECTION GUIDE - Products and Packages -
X13769X
Semiconductor Device Mount Manual
Note
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
User’s Manual U16994EJ6V0UD
7
CONTENTS
CHAPTER 1 OVERVIEW.........................................................................................................................14
1.1 Features .........................................................................................................................................14
1.2 Ordering Information....................................................................................................................16
1.3 Pin Configuration (Top View) ......................................................................................................17
1.3.1 μPD78F921x .....................................................................................................................................17
1.3.2 μPD78F951x .....................................................................................................................................19
1.4 78K0S/Kx1+ Product Lineup........................................................................................................20
1.5 Block Diagram...............................................................................................................................21
1.5.1 μPD78F921x .....................................................................................................................................21
1.5.2 μPD78F951x .....................................................................................................................................22
1.6 Functional Outline ........................................................................................................................23
CHAPTER 2 PIN FUNCTIONS ...............................................................................................................24
2.1 Pin Function List...........................................................................................................................24
2.1.1 μPD78F921x .....................................................................................................................................24
2.1.2 μPD78F951x .....................................................................................................................................26
2.2 Pin Functions ................................................................................................................................27
2.2.1 P20 to P23 (Port 2)............................................................................................................................27
2.2.2 P32 and P34 (Port 3).........................................................................................................................28
2.2.3 P40 to P47 (Port 4)............................................................................................................................28
2.2.4 RESET ..............................................................................................................................................28
2.2.5 X1 and X2..........................................................................................................................................28
2.2.6 VDD ....................................................................................................................................................28
2.2.7 VSS .....................................................................................................................................................28
2.3 Pin I/O Circuits and Connection of Unused Pins ......................................................................29
CHAPTER 3 CPU ARCHITECTURE ......................................................................................................32
3.1 Memory Space ..............................................................................................................................32
3.1.1 Internal program memory space........................................................................................................35
3.1.2 Internal data memory space ..............................................................................................................36
3.1.3 Special function register (SFR) area..................................................................................................36
3.1.4 Data memory addressing ..................................................................................................................36
3.2 Processor Registers.....................................................................................................................39
3.2.1 Control registers ................................................................................................................................39
3.2.2 General-purpose registers.................................................................................................................42
3.2.3 Special function registers (SFRs) ......................................................................................................43
3.3 Instruction Address Addressing.................................................................................................47
3.3.1 Relative addressing ...........................................................................................................................47
3.3.2 Immediate addressing .......................................................................................................................48
3.3.3 Table indirect addressing ..................................................................................................................48
3.3.4 Register addressing...........................................................................................................................49
8
User’s Manual U16994EJ6V0UD
3.4 Operand Address Addressing .................................................................................................... 50
3.4.1 Direct addressing .............................................................................................................................. 50
3.4.2 Short direct addressing ..................................................................................................................... 51
3.4.3 Special function register (SFR) addressing ....................................................................................... 52
3.4.4 Register addressing .......................................................................................................................... 53
3.4.5 Register indirect addressing.............................................................................................................. 54
3.4.6 Based addressing ............................................................................................................................. 55
3.4.7 Stack addressing............................................................................................................................... 56
CHAPTER 4 PORT FUNCTIONS........................................................................................................... 57
4.1 Functions of Ports........................................................................................................................ 57
4.2 Port Configuration........................................................................................................................ 58
4.2.1 Port 2 ................................................................................................................................................ 58
4.2.2 Port 3 ................................................................................................................................................ 65
4.2.3 Port 4 ................................................................................................................................................ 66
4.3 Registers Controlling Port Functions ........................................................................................ 67
4.4 Operation of Port Function.......................................................................................................... 72
4.4.1 Writing to I/O port .............................................................................................................................. 72
4.4.2 Reading from I/O port........................................................................................................................ 72
4.4.3 Operations on I/O port....................................................................................................................... 72
CHAPTER 5 CLOCK GENERATORS................................................................................................... 73
5.1 Functions of Clock Generators................................................................................................... 73
5.1.1 System clock oscillators .................................................................................................................... 73
5.1.2 Clock oscillator for interval time generation....................................................................................... 73
5.2 Configuration of Clock Generators ............................................................................................ 74
5.3 Registers Controlling Clock Generators.................................................................................... 76
5.4 System Clock Oscillators ............................................................................................................ 79
5.4.1 High-speed internal oscillator ............................................................................................................ 79
5.4.2 Crystal/ceramic oscillator .................................................................................................................. 79
5.4.3 External clock input circuit................................................................................................................. 81
5.4.4 Prescaler ........................................................................................................................................... 81
5.5 Operation of CPU Clock Generator ............................................................................................ 82
5.6 Operation of Clock Generator Supplying Clock to Peripheral Hardware............................... 88
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00............................................................................. 90
6.1
6.2
6.3
6.4
Functions of 16-bit Timer/Event Counter 00.............................................................................. 90
Configuration of 16-bit Timer/Event Counter 00 ....................................................................... 91
Registers to Control 16-bit Timer/Event Counter 00 ................................................................ 95
Operation of 16-bit Timer/Event Counter 00............................................................................101
6.4.1 Interval timer operation ................................................................................................................... 101
6.4.2 External event counter operation .................................................................................................... 103
6.4.3 Pulse width measurement operations ............................................................................................. 106
6.4.4 Square-wave output operation ........................................................................................................ 114
6.4.5 PPG output operations.................................................................................................................... 116
User’s Manual U16994EJ6V0UD
9
6.4.6 One-shot pulse output operation .....................................................................................................119
6.5 Cautions Related to 16-bit Timer/Event Counter 00................................................................124
CHAPTER 7 8-BIT TIMER H1 .............................................................................................................131
7.1
7.2
7.3
7.4
Functions of 8-bit Timer H1 .......................................................................................................131
Configuration of 8-bit Timer H1.................................................................................................131
Registers Controlling 8-bit Timer H1 ........................................................................................134
Operation of 8-bit Timer H1 .......................................................................................................136
7.4.1 Operation as interval timer/square-wave output ..............................................................................136
7.4.2 Operation as PWM output mode .....................................................................................................140
CHAPTER 8 WATCHDOG TIMER .......................................................................................................146
8.1
8.2
8.3
8.4
Functions of Watchdog Timer ...................................................................................................146
Configuration of Watchdog Timer ............................................................................................148
Registers Controlling Watchdog Timer....................................................................................149
Operation of Watchdog Timer ...................................................................................................151
8.4.1 Watchdog timer operation when “low-speed internal oscillator cannot be stopped” is selected by
option byte .....................................................................................................................................151
8.4.2
Watchdog timer operation when “low-speed internal oscillator can be stopped by software” is
selected by option byte ..................................................................................................................153
8.4.3 Watchdog timer operation in STOP mode (when “low-speed internal oscillator can be stopped by
software” is selected by option byte)..............................................................................................155
8.4.4 Watchdog timer operation in HALT mode (when “low-speed internal oscillator can be stopped by
software” is selected by option byte)..............................................................................................156
CHAPTER 9 A/D CONVERTER (μPD78F921x ONLY) .......................................................................157
9.1
9.2
9.3
9.4
Functions of A/D Converter .......................................................................................................157
Configuration of A/D Converter ................................................................................................159
Registers Used by A/D Converter .............................................................................................161
A/D Converter Operations .........................................................................................................166
9.4.1 Basic operations of A/D converter ...................................................................................................166
9.4.2 Input voltage and conversion results ...............................................................................................168
9.4.3 A/D converter operation mode.........................................................................................................169
9.5 How to Read A/D Converter Characteristics Table .................................................................171
9.6 Cautions for A/D Converter .......................................................................................................173
CHAPTER 10 INTERRUPT FUNCTIONS ............................................................................................177
10.1
10.2
10.3
10.4
Interrupt Function Types .........................................................................................................177
Interrupt Sources and Configuration......................................................................................177
Interrupt Function Control Registers .....................................................................................179
Interrupt Servicing Operation..................................................................................................182
10.4.1 Maskable interrupt request acknowledgment operation ................................................................182
10.4.2 Multiple interrupt servicing.............................................................................................................184
10.4.3 Interrupt request pending ..............................................................................................................186
10
User’s Manual U16994EJ6V0UD
CHAPTER 11 STANDBY FUNCTION..................................................................................................187
11.1 Standby Function and Configuration .....................................................................................187
11.1.1 Standby function ........................................................................................................................... 187
11.1.2 Registers used during standby...................................................................................................... 189
11.2 Standby Function Operation ...................................................................................................190
11.2.1 HALT mode ................................................................................................................................... 190
11.2.2 STOP mode .................................................................................................................................. 193
CHAPTER 12 RESET FUNCTION .......................................................................................................197
12.1 Register for Confirming Reset Source...................................................................................204
CHAPTER 13 POWER-ON-CLEAR CIRCUIT .....................................................................................205
13.1
13.2
13.3
13.4
Functions of Power-on-Clear Circuit...................................................................................... 205
Configuration of Power-on-Clear Circuit ...............................................................................206
Operation of Power-on-Clear Circuit...................................................................................... 206
Cautions for Power-on-Clear Circuit ...................................................................................... 207
CHAPTER 14 LOW-VOLTAGE DETECTOR.......................................................................................209
14.1
14.2
14.3
14.4
14.5
Functions of Low-Voltage Detector........................................................................................209
Configuration of Low-Voltage Detector .................................................................................209
Registers Controlling Low-Voltage Detector.........................................................................210
Operation of Low-Voltage Detector........................................................................................212
Cautions for Low-Voltage Detector ........................................................................................ 216
CHAPTER 15 OPTION BYTE ...............................................................................................................219
15.1 Functions of Option Byte ........................................................................................................219
15.2 Format of Option Byte .............................................................................................................220
15.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin (P34).............................221
CHAPTER 16 FLASH MEMORY..........................................................................................................222
16.1
16.2
16.3
16.4
16.5
16.6
Features.....................................................................................................................................222
Memory Configuration .............................................................................................................223
Functional Outline ....................................................................................................................223
Writing with Flash Memory Programmer ...............................................................................224
Programming Environment .....................................................................................................225
Processing of Pins on Board ..................................................................................................227
16.6.1 X1 and X2 pins.............................................................................................................................. 227
16.6.2 RESET pin .................................................................................................................................... 228
16.6.3 Port pins ........................................................................................................................................ 229
16.6.4 Power supply................................................................................................................................. 229
16.7 On-Board and Off-Board Flash Memory Programming........................................................230
16.7.1 Flash memory programming mode ............................................................................................... 230
16.7.2 Communication commands........................................................................................................... 230
16.7.3 Security settings............................................................................................................................ 231
User’s Manual U16994EJ6V0UD
11
16.8 Flash Memory Programming by Self Programming..............................................................232
16.8.1 Outline of self programming ..........................................................................................................232
16.8.2 Cautions on self programming function .........................................................................................235
16.8.3 Registers used for self programming function ...............................................................................235
16.8.4 Example of shifting normal mode to self programming mode ........................................................242
16.8.5 Example of shifting self programming mode to normal mode ........................................................245
16.8.6 Example of block erase operation in self programming mode .......................................................248
16.8.7 Example of block blank check operation in self programming mode .............................................251
16.8.8 Example of byte write operation in self programming mode ..........................................................254
16.8.9 Example of internal verify operation in self programming mode ....................................................257
16.8.10 Examples of operation when command execution time should be minimized in self programming
mode ...........................................................................................................................................261
16.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming
mode ...........................................................................................................................................268
CHAPTER 17 ON-CHIP DEBUG FUNCTION .......................................................................................279
17.1 Connecting QB-MINI2 to 78K0S/KY1+ ....................................................................................279
17.1.1 Connection of INTP1 pin ...............................................................................................................280
17.1.2 Connection of X1 and X2 pins .......................................................................................................281
17.2 Securing of user resources .....................................................................................................282
CHAPTER 18 INSTRUCTION SET OVERVIEW .................................................................................283
18.1 Operation ...................................................................................................................................283
18.1.1 Operand identifiers and description methods ................................................................................283
18.1.2 Description of “Operation” column .................................................................................................284
18.1.3 Description of “Flag” column..........................................................................................................284
18.2 Operation List ...........................................................................................................................285
18.3 Instructions Listed by Addressing Type ................................................................................290
CHAPTER 19 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) ................293
CHAPTER 20 ELECTRICAL SPECIFICATIONS ((A2) grade product)................................................305
CHAPTER 21 PACKAGE DRAWING ..................................................................................................319
CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS...........................................................323
APPENDIX A DEVELOPMENT TOOLS...............................................................................................325
A.1 Software Package ......................................................................................................................328
A.2 Language Processing Software ...............................................................................................328
A.3 Flash Memory Writing Tools .....................................................................................................329
A.3.1 When using flash memory programmer PG-FP5 and FL-PR5 ........................................................329
A.3.2 When using on-chip debug emulator with programming function QB-MINI2 ...................................329
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User’s Manual U16994EJ6V0UD
A.4 Debugging Tools (Hardware)....................................................................................................329
A.4.1 When using in-circuit emulator QB-78K0SKX1............................................................................... 329
A.4.2 When using on-chip debug emulator with programming function QB-MINI2................................... 330
A.5 Debugging Tools (Software).....................................................................................................331
APPENDIX B NOTES ON DESIGNING TARGET SYSTEM ................................................................332
APPENDIX C REGISTER INDEX.........................................................................................................334
C.1 Register Index (Register Name) ...............................................................................................334
C.2 Register Index (Symbol)............................................................................................................336
APPENDIX D LIST OF CAUTIONS.....................................................................................................338
APPENDIX E REVISION HISTORY .....................................................................................................353
E.1 Major Revisions in This Edition................................................................................................353
E.2 Revision History up to Previous Editions ...............................................................................354
User’s Manual U16994EJ6V0UD
13
CHAPTER 1 OVERVIEW
1.1 Features
O 78K0S CPU core
O ROM and RAM capacities
Item
Program Memory (Flash Memory)
Memory (Internal High-Speed RAM)
Part number
μPD78F9210, 78F9510
1 KB
μPD78F9211, 78F9511
2 KB
μPD78F9212, 78F9512
4 KB
128 bytes
O Minimum instruction execution time: 0.2 μs (with 10 MHz@4.0 to 5.5 V operation)
O Clock
• High-speed system clock … Selected from the following three sources
- Ceramic/crystal resonator:
2 to 10 MHz (Standard product, (A) grade product)
2 to 8 MHz ((A2) grade product)
- External clock:
2 to 10 MHz (Standard product, (A) grade product)
2 to 8 MHz ((A2) grade product)
- High-speed internal oscillator:
8 MHz ±3% (−10 to +70°C),
8 MHz ±5% (Standard product, (A) grade product: −40 to +85°C, (A2)
grade product: −40 to +125°C)
• Low-speed internal oscillator 240 kHz (TYP.) … Watchdog timer, timer clock in intermittent operation
O I/O ports: 14 (CMOS I/O: 13, CMOS input: 1)
O Timer: 3 channels
• 16-bit timer/event counter:
1 channel … Timer output × 1, capture input × 2
• 8-bit timer:
1 channel … PWM output × 1
• Watchdog timer:
1 channel … Operable with low-speed internal oscillation clock
O On-chip power-on-clear (POC) circuit (A reset is automatically generated when the voltage drops to 2.1 V (TYP.)
or below)
O 10-bit resolution A/D converter (μPD78F921x only): 4 channels
O On-chip low voltage detector (LVI) circuit (An interrupt/reset (selectable) is generated when the detection voltage
is reached)
• Detection voltage: Selectable from ten levels between 2.35 and 4.3 V
O Single-power-supply flash memory
• Flash self programming enabled
• Software protection function: Protected from outside party copying (no flash reading command)
• Time required for writing by dedicated flash memory programmer: Approximately 3 seconds (4 KB)
∗ Flash programming on mass production lines supported
O Safety function
• Watchdog timer operated by clock independent from CPU
… A hang-up can be detected even if the system clock stops
• Supply voltage drop detectable by LVI
… Appropriate processing can be executed before the supply voltage drops below the operation voltage
• Equipped with option byte function
… Important system operation settings set in hardware
O Assembler and C language supported
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User’s Manual U16994EJ6V0UD
CHAPTER 1 OVERVIEW
O Enhanced development environment
• Support for full-function emulator (IECUBE), simplified emulator (MINICUBE2), and simulator
O Supply voltage: VDD = 2.0 to 5.5 V
∗ Use these products in the following voltage range because the detection voltage (VPOC) of the POC circuit is
the supply voltage range.
Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to 5.5 V
O Operating temperature range:
• Standard product, (A) grade product: TA = −40 to +85°C
• (A2) grade product: TA = −40 to +125°C
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15
CHAPTER 1 OVERVIEW
1.2 Ordering Information
Part Number
μPD78F9 ××× - ×× (×) - ××× -×
Semiconductor component
-A
Lead-free
Product contains no lead in any area
(Terminal finish is Sn/Bi plating)
Product contains no lead in any area
-AX
(Terminal finish is Ni/Pd/Au plating)
Quality grades
Blank
Standard (for ordinary electronic systems)
(A)
Special (for high-reliability electronic systems)
(A2)
Package type
MA-FAA
16-pin Plastic SSOP
GR-JJG
CS-CAB
16-pin Plastic SDIP
FH-2A2
16-pin WLBGA
High-speed RAM
Flash memory
1 K bytes
128 bytes
210
510
A/D converter
Mounted
Not mounted
211
2 K bytes
Mounted
4 K bytes
Mounted
Not mounted
511
212
512
Not mounted
Product type
F
Flash memory versions
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
[Part number list]
16
μPD78F9210MA-FAA-AX
μPD78F9211MA-FAA-AX
μPD78F9212MA-FAA-AX
μPD78F9210MA(A)-FAA-AX
μPD78F9211GRMA(A)-FAA-AX
μPD78F9212MA(A)-FAA-AX
μPD78F9210MA(A2)-FAA-AX
μPD78F9211MA(A2)-FAA-AX
μPD78F9212MA(A2)-FAA-AX
μPD78F9210GR-JJG-A
μPD78F9211GR-JJG-A
μPD78F9212GR-JJG-A
μPD78F9210GR(A)-JJG-A
μPD78F9211GR(A)-JJG-A
μPD78F9212GR(A)-JJG-A
μPD78F9210GR(A2)-JJG-A
μPD78F9211GR(A2)-JJG-A
μPD78F9212GR(A2)-JJG-A
μPD78F9510GR-JJG-A
μPD78F9511GR-JJG-A
μPD78F9512GR-JJG-A
μPD78F9210CS-CAB-A
μPD78F9211CS-CAB-A
μPD78F9212CS-CAB-A
μPD78F9210FH-2A2-A
μPD78F9211FH-2A2-A
μPD78F9212FH-2A2-A
User’s Manual U16994EJ6V0UD
CHAPTER 1 OVERVIEW
1.3 Pin Configuration (Top View)
1.3.1 μPD78F921x
• 16-pin plastic SSOP
P20/ANI0/TI000/TOH1
1
16
P21/ANI1/TI010/TO00/INTP0
P41
2
15
P42
P40
3
14
P43
Note 1
4
13
P32/INTP1
Note 2
5
12
P34/RESET
P47
6
11
P44
P46
7
10
P45
P23/X1/ANI3
8
9
VSS
VDD
P22/X2/ANI2
• 16-pin plastic SDIP
P32/INTP1
1
16
P34/RESET
P43
2
15
P44
P42
3
14
P45
P21/ANI1/TI010/TO00/INTP0
4
13
P22/X2/ANI2
P20/ANI0/TI000/TOH1
5
12
P23/X1/ANI3
P41
6
11
P46
P40
7
10
P47
VSSNote 1
8
9
VDDNote 2
Notes 1. In μPD78F921x, VSS functions alternately as the ground potential of the A/D converter. Be sure to
connect VSS to a stabilized GND (= 0 V).
2. In μPD78F921x, VDD functions alternately as the A/D converter reference voltage input. When using the
A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V).
User’s Manual U16994EJ6V0UD
17
CHAPTER 1 OVERVIEW
• 16-pin WLBGA (2.24×1.93)
Top View
Bottom View
D
C
B
A
4
3
2
1
1
2
3
4
Index Mark
Pin No.
A1
Name
P20/ANI0/TI000/TOH1
Note1
Pin No.
Name
C1
P42
A2
VSS
C2
P43
A3
P47
C3
P34/RESET
A4
P23/X1/ANI3
C4
P45
B1
P41
D1
P21/ANI1/TI010/TO000/INTP0
B2
P40
D2
P32/INTP1
B3
VDD
D3
P44
B4
P46
D4
P22/X2/ANI2
Note2
Pin Name
ANI0 to ANI3:
Analog input
TI000, TI010:
Timer input
INTP0, INTP1:
External interrupt input
TO00, TOH1:
Timer output
P20 to P23:
Port 2
VDDNote 2:
Power supply
P32, P34:
Port 3
VSSNote 1:
Ground
P40 to P47:
Port 4
X1, X2:
Crystal oscillator (X1 input clock)
RESET:
Reset
Notes 1. In μPD78F921x, VSS functions alternately as the ground potential of the A/D converter. Be sure to
connect VSS to a stabilized GND (= 0 V).
2. In μPD78F921x, VDD functions alternately as the A/D converter reference voltage input. When using the
A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V).
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User’s Manual U16994EJ6V0UD
CHAPTER 1 OVERVIEW
1.3.2 μPD78F951x
• 16-pin plastic SSOP
P20/TI000/TOH1
1
16
P21/TI010/TO00/INTP0
P41
2
15
P42
P40
3
14
P43
VSS
4
13
P32/INTP1
VDD
5
12
P34/RESET
P47
6
11
P44
P46
7
10
P45
P23/X1
8
9
P22/X2
Pin Name
INTP0, INTP1:
External interrupt input
TI000, TI010:
Timer input
P20 to P23:
Port 2
TO00, TOH1:
Timer output
P32, P34:
Port 3
VDD:
Power supply
P40 to P47:
Port 4
VSS:
Ground
RESET:
Reset
X1, X2:
Crystal oscillator (X1 input clock)
User’s Manual U16994EJ6V0UD
19
CHAPTER 1 OVERVIEW
1.4 78K0S/Kx1+ Product Lineup
The following table shows the product lineup of the 78K0S/Kx1+.
Part Number
78K0S/KU1+
78K0S/KY1+
78K0S/KA1+
78K0S/KB1+
10 pins
16 pins
20 pins
30/32 pins
Item
Number of pins
Internal
memory
Flash memory
1 KB, 2 KB, 4 KB
2 KB
4 KB,
8 KB
4 KB, 8 KB
128 bytes
128
bytes
256
bytes
256 bytes
RAM
VDD = 2.0 to 5.5 V
Supply voltage
Note 1
0.20 μs (10 MHz, VDD = 4.0 to 5.5 V)
0.33 μs (6 MHz, VDD = 3.0 to 5.5 V)
0.40 μs (5 MHz, VDD = 2.7 to 5.5 V)
1.0 μs (2 MHz, VDD = 2.0 to 5.5 V)
Minimum instruction
execution time
High-speed internal oscillation (8 MHz (TYP.))
Note 2
Crystal/ceramic oscillation (2 to 10 MHz)
System clock
(oscillation frequency)
External clock input oscillation (2 to 10 MHz)
Clock for TMH1 and WDT
(oscillation frequency)
Port
Timer
Low-speed internal oscillation (240 kHz (TYP.))
CMOS I/O
7
13
15
24
CMOS input
1
1
1
1
CMOS output
−
−
1
1
1 ch
16-bit (TM0)
8-bit (TMH)
1 ch
−
8-bit (TM8)
1 ch
WDT
1 ch
−
Serial interface
LIN-Bus-supporting UART: 1 ch
Note 4
Note 4
A/D converter
10 bits: 4 ch (2.7 to 5.5 V)
Multiplier (8 bits × 8 bits)
Interrupts
−
5
Internal
External
Reset
Provided (selectable by software)
WDT
2.
3.
4.
5.
20
4
2.1 V (TYP.)
LVI
9
Provided
POC
Notes 1.
Provided
Note 5
2
RESET pin
Operating temperature range
Note 3
Provided
Standard product:
−40 to +85°C
Standard product, (A) grade product: −40 to +85°C
(A2) grade product: −40 to +125°C
Use these products in the following voltage range because the detection voltage (VPOC) of the power-onclear (POC) circuit is the supply voltage range.
Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to 5.5 V
μ PD78F950x does not support the crystal/ceramic oscillation.
The product without A/D converter (μ PD78F950x) in the 78K0S/KU1+ is not supported.
The product without A/D converter (μ PD78F95xx) is provided for the 78K0S/KU1+ and 78K0S/KY1+
respectively.
There are 2 and 4 factors for the products without A/D converter in the 78K0S/KU1+ and 78K0S/KY1+,
respectively.
User’s Manual U16994EJ6V0UD
CHAPTER 1 OVERVIEW
1.5 Block Diagram
1.5.1 μPD78F921x
TO00/TI010/P21
Port 2
16-bit timer/
event counter 00
TI000/P20
4
P32
Port 3
TOH1/P20
78K0S
CPU
core
8-bit timer H1
P20 to P23
P34
Flash
memory
Port 4
8
P40 to P47
Low-speed
internal
oscillator
ANI0/P20 to
ANI3/P23
INTP0/P21
INTP1/P32
4
Power on clear/
low voltage
indicator
A/D converter
Internal
high-speed
RAM
POC/LVI
control
Reset control
Interrupt
control
System
control
RESET/P34
X1/P23
X2/P22
VDDNote 1 VSSNote 2
High-speed
internal
oscillator
Notes 1. In μPD78F921x, VDD functions alternately as the A/D converter reference voltage input. When using the
A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V).
2. In μPD78F921x, VSS functions alternately as the ground potential of the A/D converter. Be sure to
connect VSS to a stabilized GND (= 0 V).
User’s Manual U16994EJ6V0UD
21
CHAPTER 1 OVERVIEW
1.5.2 μPD78F951x
TO00/TI010/P21
TI000/P20
Port 2
16-bit timer/
event counter 00
4
P32
Port 3
TOH1/P20
8-bit timer H1
78K0S
CPU
core
P20 to P23
P34
Flash
memory
Port 4
8
P40 to P47
Low-speed
internal
oscillator
Power on clear/
low voltage
indicator
Watchdog
timer
Internal
high-speed
RAM
INTP0/P21
INTP1/P32
POC/LVI
control
Reset control
Interrupt
control
System
control
RESET/P34
X1/P23
X2/P22
VDD
22
VSS
User’s Manual U16994EJ6V0UD
High-speed
internal
oscillator
CHAPTER 1 OVERVIEW
1.6 Functional Outline
μPD78F9210
μPD78F9510
Item
Internal
memory
Flash memory
1 KB
High-speed RAM
128 bytes
μPD78F9211
μPD78F9511
2 KB
Memory space
64 KB
X1 input clock (oscillation frequency)
Crystal/ceramic/external clock input:
μPD78F9212
μPD78F9512
4 KB
10 MHz (VDD = 2.0 to 5.5 V)
Internal
High speed (oscillation
oscillation
frequency)
clock
Low speed (for TMH1
Internal oscillation: 8 MHz (TYP.)
Internal oscillation: 240 kHz (TYP.)
and WDT)
General-purpose registers
8 bits × 8 registers
Instruction execution time
0.2 μs/0.4 μs/0.8 μs/1.6 μs/3.2 μs (X1 input clock: fX = 10 MHz)
I/O port
Total:
Timer
Timer output
14 pins
CMOS I/O:
13 pins
CMOS input:
1 pin
• 16-bit timer/event counter:
1 channel
• 8-bit timer (timer H1):
1 channel
• Watchdog timer:
1 channel
2 pins (PWM: 1 pin)
A/D converter (μPD78F921x only)
10-bit resolution × 4 channels
Vectored
External
2
Internal
μPD78F921x: 5, μPD78F951x: 4
interrupt sources
• Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-clear
Reset
• Internal reset by low-voltage detector
Supply voltage
Operating temperature range
VDD = 2.0 to 5.5 V
Note
Standard product, (A) grade product: −40 to +85°C
(A2) grade product: −40 to +125°C
Package
• 16-pin plastic SSOP
• 16-pin plastic SDIP
• 16-pin WLBGA (2.24 × 1.93)
Note
Use these products in the following voltage range because the detection voltage (VPOC) of the power-on-clear
(POC) circuit is the supply voltage range.
Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to 5.5 V
User’s Manual U16994EJ6V0UD
23
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
2.1.1 μPD78F921x
(1) Port pins
Pin Name
I/O
Function
After Reset
Alternate-Function
Pin
I/O
P20
Port 2.
Input
4-bit I/O port.
P21
ANI1/TI010/
Can be set to input or output mode in 1-bit units.
P22
Note
P23
Note
ANI0/TI000/TOH1
TO00/INTP0
An on-chip pull-up resistor can be connected by setting
software.
P32
I/O
Port 3
Can be set to input or output mode in
X2/ANI2
Note
X1/ANI3
Note
Input
INTP1
Input
RESET
1-bit units.
An on-chip pull-up resistor can be
connected by setting software.
P34
Note
Input
P40 to P47
I/O
Input only
Port 4.
Input
8-bit I/O port.
Can be set to input or output mode in 1-bit units.
An on-chip pull-up resistor can be connected by setting
software.
Note
For the setting method for pin functions, see CHAPTER 15 OPTION BYTE.
Caution The P22/X2/ANI2 and P23/X1/ANI3 pins are pulled down during reset.
24
User’s Manual U16994EJ6V0UD
Note
−
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Pin Name
I/O
Function
After Reset
AlternateFunction Pin
INTP0
Input
External interrupt input for which the valid edge (rising edge,
Input
P21/ANI1/TI010/
TO00
falling edge, or both rising and falling edges) can be specified
INTP1
P32
TI000
Input
External count clock input to 16-bit timer/event counter 00.
Input
P20/ANI0/TOH1
Capture trigger input to capture registers (CR000 and CR010) of
16-bit timer/event counter 00
TI010
TO00
Output
Capture trigger input to capture register (CR000) of 16-bit
P21/ANI1/TO00/
timer/event counter 00
INTP0
16-bit timer/event counter 00 output
Input
P21/ANI1/TI010/
INTP0
TOH1
Output
8-bit timer H1 output
Input
P20/ANI0/TI000
ANI0
Input
Analog input of A/D converter
Input
P20/TI000/TOH1
ANI1
P21/TI010/TO00/
INTP0
ANI2
Note
P22/X2
ANI3
Note
P23/X1
RESET
X1
Note
Note
Note
Note
Input
System reset input
Input
Input
Connection of crystal/ceramic oscillator for system clock
P34
Note
−
P23/ANI3
Note
−
P22/ANI2
Note
oscillation.
External clock input
X2
Note
−
Connection of crystal/ceramic oscillator for system clock
oscillation.
VDD
−
Positive power supply
−
−
VSS
−
Ground potential
−
−
Note
For the setting method for pin functions, see CHAPTER 15 OPTION BYTE.
Caution The P22/X2/ANI2 and P23/X1/ANI3 pins are pulled down during reset.
User’s Manual U16994EJ6V0UD
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CHAPTER 2 PIN FUNCTIONS
2.1.2 μPD78F951x
(1) Port pins
Pin Name
I/O
Function
After Reset
Alternate-Function
Pin
I/O
P20
Port 2.
TI000/TOH1
Input
4-bit I/O port.
P21
TI010/TO00/
Can be set to input or output mode in 1-bit units.
P22
Note
P23
Note
INTP0
An on-chip pull-up resistor can be connected by setting
Note
X2
software.
X1
P32
I/O
Port 3
Can be set to input or output mode in
Note
Input
INTP1
Input
RESET
1-bit units.
An on-chip pull-up resistor can be
connected by setting software.
P34
Note
Input
P40 to P47
I/O
Input only
Port 4.
Note
−
Input
8-bit I/O port.
Can be set to input or output mode in 1-bit units.
An on-chip pull-up resistor can be connected by setting
software.
(2) Non-port pins
Pin Name
I/O
Function
After Reset
AlternateFunction Pin
INTP0
Input
External interrupt input for which the valid edge (rising edge,
Input
P21 /TI010/
TO00
falling edge, or both rising and falling edges) can be specified
INTP1
P32
TI000
Input
External count clock input to 16-bit timer/event counter 00.
Input
P20 /TOH1
Capture trigger input to capture registers (CR000 and CR010) of
16-bit timer/event counter 00
TI010
TO00
Output
Capture trigger input to capture register (CR000) of 16-bit
P21/TO00/
timer/event counter 00
INTP0
16-bit timer/event counter 00 output
Input
P21/TI010/
INTP0
TOH1
RESET
X1
Note
Note
Output
8-bit timer H1 output
Input
P20/TI000
Input
System reset input
Input
P34
Note
Input
Connection of crystal/ceramic oscillator for system clock
−
P23
Note
−
P22
oscillation.
External clock input
X2
Note
−
Connection of crystal/ceramic oscillator for system clock
Note
oscillation.
VDD
−
Positive power supply
−
−
VSS
−
Ground potential
−
−
Note
For the setting method for pin functions, see CHAPTER 15 OPTION BYTE.
Caution The P22/X2 and P23/X1 pins are pulled down during reset.
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User’s Manual U16994EJ6V0UD
CHAPTER 2 PIN FUNCTIONS
2.2 Pin Functions
2.2.1 P20 to P23 (Port 2)
P20 to P23 constitute a 4-bit I/O port. In addition to the function as I/O port pins, these pins also have a function to
input an analog signal to the A/D converter, input/output a timer signal, and input an external interrupt request signal.
P22 and P23 also function as the X2/ANI2 and X1/ANI3, respectively. For the setting method for pin functions, see
CHAPTER 15 OPTION BYTE.
These pins can be set to the following operation modes in 1-bit units.
(1) Port mode
P20 to P23 function as a 4-bit I/O port. Each bit of this port can be set to the input or output mode by using
port mode register 2 (PM2). In addition, an on-chip pull-up resistor can be connected to the port by using pullup resistor option register 2 (PU2).
(2) Control mode
P20 to P23 function to input an analog signal to the A/D converter, input/output a timer signal, and input an
external interrupt request signal.
(a) ANI0 to ANI3 (μPD78F921x only)
These are the analog input pins of the A/D converter. When using these pins as analog input pins, refer
to 9.6 Cautions for A/D converter (5) ANI0/P20 to ANI3/P23.
(b) TI000
This pin inputs an external count clock to 16-bit timer/event counter 00, or a capture trigger signal to the
capture registers (CR000 and CR010) of 16-bit timer/event counter 00.
(c) TI010
This pin inputs a capture trigger signal to the capture register (CR000) of 16-bit timer/event counter 00.
(d) TO00
This pin outputs a signal from 16-bit timer/event counter 00.
(e) TOH1
This pin outputs a signal from 8-bit timer H1.
(f) INTP0
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
Caution
The P22/X2/ANI2 and P23/X1/ANI3 pins are pulled down during reset.
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CHAPTER 2 PIN FUNCTIONS
2.2.2 P32 and P34 (Port 3)
P32 is a 1-bit I/O port. In addition to the function as an I/O port pin, this pin also has a function to input an external
interrupt request signal.
P34 is a 1-bit input-only port. This pin is also used as a RESET pin, and when the power is turned on, this is the
reset function.
For the setting method for pin functions, see CHAPTER 15 OPTION BYTE.
When P34 is used as an input port pin, connect the pull-up resistor.
P32 and P34 can be set to the following operation modes in 1-bit units.
(1) Port mode
P32 functions as a 1-bit I/O port. This pin can be set to the input or output mode by using port mode register 3
(PM3). In addition, an on-chip pull-up resistor can be connected to the port by using pull-up resistor option
register 3 (PU3).
P34 functions as a 1-bit input-only port.
(2) Control mode
P32 functions as an external interrupt request input pin (INTP1) for which the valid edge (rising edge, falling
edge, or both rising and falling edges) can be specified.
2.2.3 P40 to P47 (Port 4)
P40 to P47 constitute an 8-bit I/O port. Each bit of this port can be set to the input or output mode by using port
mode register 4 (PM4). In addition, an on-chip pull-up resistor can be connected to the port by using pull-up resistor
option register 4 (PU4).
2.2.4 RESET
This pin inputs an active-low system reset signal.
When the power is turned on, this is the reset function,
regardless of the option byte setting.
2.2.5 X1 and X2
These pins connect an oscillator to oscillate the X1 input clock.
X1 and X2 also function as the P23/ANI3 and P22/ANI2, respectively. For the setting method for pin functions, see
CHAPTER 15 OPTION BYTE.
Supply an external clock to X1.
Caution The P22/X2/ANI2 and P23/X1/ANI3 pins are pulled down during reset.
2.2.6 VDD
This is the positive power supply pin.
In μPD78F921x, VDD functions alternately as the A/D converter reference voltage input. When using the A/D
converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V).
2.2.7 VSS
This is the ground pin.
In μPD78F921x, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a
stabilized GND (= 0 V).
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CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuits and Connection of Unused Pins
Table 2-1 shows I/O circuit type of each pin and the connections of unused pins.
For the configuration of the I/O circuit of each type, refer to Figures 2-1 and 2-2.
Table 2-1. Types of Pin I/O Circuits and Connection of Unused Pins (μPD78F921x)
Pin Name
P20/ANI0/TI000/TOH1
I/O Circuit Type
11
I/O
I/O
Recommended Connection of Unused Pin
Input:
Individually connect to VDD or VSS via resistor.
Output: Leave open.
P21/ANI1/TI010/TO00/
INTP0
36
P22/ANI2/X2
Input:
Individually connect to VSS via resistor.
Output: Leave open.
P23/ANI3/X1
P32/INTP1
8-A
Input:
Individually connect to VDD or VSS via resistor.
Output: Leave open.
P34/RESET
2
Input
P40 to P47
8-A
I/O
Connect to VDD via resistor.
Input:
Individually connect to VDD or VSS via resistor.
Output: Leave open.
Table 2-2. Types of Pin I/O Circuits and Connection of Unused Pins (μPD78F951x)
Pin Name
P20/TI000/TOH1
I/O Circuit Type
11-H
I/O
I/O
36-A
Individually connect to VDD or VSS via resistor.
Input:
Individually connect to VSS via resistor.
Output: Leave open.
P23/X1
P32/INTP1
Input:
Output: Leave open.
P21/TI010/TO00/INTP0
P22/X2
Recommended Connection of Unused Pin
8-A
Input:
Individually connect to VDD or VSS via resistor.
Output: Leave open.
P34/RESET
2
Input
Connect to VDD via resistor.
P40 to P47
8-A
I/O
Input:
Individually connect to VDD or VSS via resistor.
Output: Leave open.
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuits (1/2)
Type 11
Type 2
VDD
Pull up
enable
P-ch
VDD
Data
P-ch
IN/OUT
Output
disable
IN
N-ch
VSS
Comparator
P-ch
+
Schmitt-triggered input with hysteresis characteristics
N-ch
Comparison
voltage
VSS
Input
enable
Type 11-H
Type 8-A
VDD
VDD
Pull up
enable
Pull up
enable
P-ch
P-ch
VDD
Data
VDD
Data
IN/OUT
P-ch
IN/OUT
Output
disable
P-ch
Output
disable
N-ch
VSS
N-ch
Input
enable
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuits (2/2)
Type 36-A
Type 36
feedback
cut-off
Feedback
cut-off
P-ch
X1,
IN/OUT
OSC
enable
P-ch
X1,
IN/OUT
X2,
IN/OUT
OSC
enable
X2,
IN/OUT
VDD
pullup
enable
VDD
P-ch
Pull up
enable
VDD
P-ch
VDD
data
P-ch
Data
P-ch
output
disable
N-ch
Output
disable
N-ch
VSS
VSS
Comparator
P-ch
+
N-ch
Comparison
voltage
VDD
VSS
Pull up
enable
VDD
P-ch
VDD
pullup
enable
P-ch
Data
P-ch
Output
disable
N-ch
VDD
data
P-ch
VSS
output
disable
N-ch
VSS
Comparator
P-ch
+
N-ch
Comparison
voltage
VSS
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CHAPTER 3 CPU ARCHITECTURE
3.1
Memory Space
The 78K0S/KY1+ can access up to 64 KB of memory space. Figures 3-1 to 3-3 show the memory maps.
Figure 3-1. Memory Map (μPD78F9210, 78F9510)
FFFFH
Special function registers
(SFR)
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
128 × 8 bits
FE80H
FE7FH
Use prohibited
Data memory
space
03FFH
0400H
03FFH
Program area
Program memory
space
Flash memory
1,024 × 8 bits
0
0
0
0
082
081
080
07F
H
H
H
H
Protect byte area
Option byte area
CALLT table area
0040H
003FH
Program area
0014H
0013H
Vector table area
0000H
0000H
Remark
32
The option byte and protect byte are 1 byte each.
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-2. Memory Map (μPD78F9211, 78F9511)
FFFFH
Special function registers
(SFR)
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
128 × 8 bits
FE80H
FE7FH
Use prohibited
Data memory
space
07FFH
0800H
07FFH
Program area
Program memory
space
Flash memory
2,048 × 8 bits
0
0
0
0
082
081
080
07F
H
H
H
H
Protect byte area
Option byte area
CALLT table area
0040H
003FH
Program area
0014H
0013H
Vector table area
0000H
0000H
Remark
The option byte and protect byte are 1 byte each.
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-3. Memory Map (μPD78F9212, 78F9512)
FFFFH
Special function registers
(SFR)
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
128 × 8 bits
FE80H
FE7FH
Use prohibited
Data memory
space
0FFFH
1000H
0FFFH
Program area
Program memory
space
Flash memory
4,096 × 8 bits
0
0
0
0
082
081
080
07F
H
H
H
H
Protect byte area
Option byte area
CALLT table area
0040H
003FH
Program area
0014H
0013H
Vector table area
0000H
0000H
Remark
34
The option byte and protect byte are 1 byte each.
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CHAPTER 3 CPU ARCHITECTURE
3.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
The 78K0S/KY1+ provide the following internal ROMs (or flash memory) containing the following capacities.
Table 3-1. Internal ROM Capacity
Part Number
Internal ROM
Structure
μPD78F9210, 78F9510
Capacity
1,024 × 8 bits
Flash memory
μPD78F9211, 78F9511
2,048 × 8 bits
μPD78F9212, 78F9512
4,096 × 8 bits
The following areas are allocated to the internal program memory space.
(1)
Vector table area
The 20-byte area of addresses 0000H to 0013H is reserved as a vector table area. This area stores program
start addresses to be used when branching by RESET or interrupt request generation.
Of a
16-bit address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd
address.
Table 3-2. Vector Table
Vector Table Address
Vector Table Address
Interrupt Request
0000H
Reset
000CH
INTTMH1
0006H
INTLVI
000EH
INTTM000
0008H
INTP0
0010H
INTTM010
000AH
Interrupt Request
INTP1
0012H
Note
Note
INTAD
Note μPD78F921x only
(2)
CALLT instruction table area
The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of
addresses 0040H to 007FH.
(3)
Option byte area
The option byte area is the 1-byte area of address 0080H. For details, refer to CHAPTER 15 OPTION
BYTE.
(4)
Protect byte area
The protect byte area is the 1-byte area of address 0081H. For details, refer to CHAPTER 16 FLASH
MEMORY.
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CHAPTER 3 CPU ARCHITECTURE
3.1.2 Internal data memory space
128-byte internal high-speed RAM is provided in the 78K0S/KY1+.
The internal high-speed RAM can also be used as a stack memory.
3.1.3 Special function register (SFR) area
Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see
Table 3-3).
3.1.4 Data memory addressing
The 78K0S/KY1+ are provided with a wide range of addressing modes to make memory manipulation as efficient
as possible. The area (FE80H to FEFFH) which contains a data memory and the special function register (SFR) area
can be accessed using a unique addressing mode in accordance with each function. Figures 3-4 to 3-6 illustrate the
data memory addressing.
Figure 3-4. Data Memory Addressing (μPD78F9210, 78F9510)
FFFFH
Special function registers (SFR)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
Short direct addressing
Internal high-speed RAM
128 × 8 bits
FE80H
FE7FH
Direct addressing
Register indirect addressing
Based addressing
Use prohibited
0400H
03FFH
Flash memory
1,024 × 8 bits
0000H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-5. Data Memory Addressing (μPD78F9211, 78F9511)
FFFFH
Special function registers (SFR)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
Short direct addressing
Internal high-speed RAM
128 × 8 bits
FE80H
FE7FH
Direct addressing
Register indirect addressing
Based addressing
Use prohibited
0800H
07FFH
Flash memory
2,048 × 8 bits
0000H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-6. Data Memory Addressing (μPD78F9212, 78F9512)
FFFFH
Special function registers (SFR)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
Short direct addressing
Internal high-speed RAM
128 × 8 bits
FE80H
FE7FH
Direct addressing
Register indirect addressing
Based addressing
Use prohibited
1000H
0FFFH
Flash memory
4,096 × 8 bits
0000H
38
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CHAPTER 3 CPU ARCHITECTURE
3.2
Processor Registers
The 78K0S/KY1+ provide the following on-chip processor registers.
3.2.1 Control registers
The control registers have special functions to control the program sequence statuses and stack memory. The
control registers include a program counter, a program status word, and a stack pointer.
(1) Program counter (PC)
The program counter is a 16-bit register which holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to
be fetched. When a branch instruction is executed, immediate data or register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program
counter.
Figure 3-7. Program Counter Configuration
15
0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are stored in stack area upon interrupt request generation or PUSH PSW
instruction execution and are restored upon execution of the RETI and POP PSW instructions.
Reset signal generation sets PSW to 02H.
Figure 3-8. Program Status Word Configuration
7
PSW
IE
0
Z
0
AC
0
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1
CY
39
CHAPTER 3 CPU ARCHITECTURE
(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests are disabled.
When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with
an interrupt mask flag for various interrupt sources.
This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all
other cases.
(d) Carry flag (CY)
This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It
stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit
operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area (Other than the internal high-speed RAM area cannot be set as the stack
area).
Figure 3-9. Stack Pointer Configuration
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9
SP8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The SP is decremented before writing (saving) to the stack memory and is incremented after reading
(restoring) from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-10 and 3-11.
Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the
SP before using the stack memory.
2. Stack pointers can be set only to the high-speed RAM area, and only the lower 10 bits
can be actually set.
Thus, if the stack pointer is specified to 0FF00H, it is converted to 0FB00H in the highspeed RAM area, since 0FF00H is in the SFR area and not in the high-speed RAM area.
When the value is actually pushed onto the stack, 1 is subtracted from 0FB00H to
become 0FAFFH, but since that value is not in the high-speed RAM area, it is converted
to 0FEFFH, which is the same value as when 0FF00H is set to the stack pointer.
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-10. Data to Be Saved to Stack Memory
PUSH rp
instruction
Interrupt
CALL, CALLT
instructions
SP
SP
SP _ 2
SP
SP _ 2
SP _ 3
SP _ 3
PC7 to PC0
SP _ 2
Lower half
register pairs
SP _ 2
PC7 to PC0
SP _ 2
PC15 to PC8
SP _ 1
Upper half
register pairs
SP _ 1
PC15 to PC8
SP _ 1
PSW
SP
SP
SP
Figure 3-11. Data to Be Restored from Stack Memory
POP rp
instruction
SP
RET instruction
RETI instruction
SP
Lower half
register pairs
SP
PC7 to PC0
SP
PC7 to PC0
SP + 1
Upper half
register pairs
SP + 1
PC15 to PC8
SP + 1
PC15 to PC8
SP + 2
PSW
SP + 2
SP
SP + 2
SP
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41
CHAPTER 3 CPU ARCHITECTURE
3.2.2 General-purpose registers
A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H).
In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register
(AX, BC, DE, and HL).
Registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Figure 3-12. General-Purpose Register Configuration
(a) Function names
16-bit processing
8-bit processing
H
HL
L
D
DE
E
B
BC
C
A
AX
X
15
0
7
0
(b) Absolute names
16-bit processing
8-bit processing
R7
RP3
R6
R5
RP2
R4
R3
RP1
R2
R1
RP0
R0
15
42
0
7
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CHAPTER 3 CPU ARCHITECTURE
3.2.3 Special function registers (SFRs)
Unlike the general-purpose registers, each special function register has a special function.
The special function registers are allocated to the 256-byte area FF00H to FFFFH.
The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and
bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register
type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address and bit.
• 8-bit manipulation
Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This
manipulation can also be specified with an address.
• 16-bit manipulation
Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifying
an address, describe an even address.
Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows:
• Symbol
Indicates the addresses of the implemented special function registers. It is defined as a reserved word in the
RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. Therefore, these
symbols can be used as instruction operands if an assembler or integrated debugger is used.
• R/W
Indicates whether the special function register can be read or written.
R/W: Read/write
R:
Read only
W:
Write only
• Number of bits manipulated simultaneously
Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated.
• After reset
Indicates the status of the special function register when a reset is input.
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CHAPTER 3 CPU ARCHITECTURE
Symbol
Bit No.
R/W
Number of Bits
After
Manipulated
Reset
Simultaneously
−
FF00H,
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
0
0
0
0
P23
P22
P21
P20
1
8
16
−
−
−
−
−
−
R/W
√
√
−
00H
69
page
Address
Reference
Table 3-3. Special Function Registers (1/3)
FF01H
FF02H
P2
Note 1
FF03H
P3
0
0
0
P34
0
P32
0
0
√
√
−
00H
69
FF04H
P4
P47
P46
P45
P44
P43
P42
P41
P40
√
√
−
00H
69
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
−
√
−
00H
133
−
√
−
00H
133
−
−
−
−
−
−
−
√
0000H
92
−
−
√
0000H
92
−
−
√
0000H
94
−
−
√
Undefined
164
−
√
−
−
FF05H to
FF0DH
FF0EH
CMP01
−
−
FF0FH
CMP11
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
TM00
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
1
1
PM23
PM22
PM21
PM20
R/W
√
√
−
FFH
FF10H,
−
FF11H
FF12H
FF13H
CR000
FF14H
FF15H
CR010
FF16H
FF17H
FF18H
ADCR
Note 3
FF19H
FF1AH
ADCRH
R/W
R
Note 2
Note 2
Note 2
Note 2
165
Note 3
−
FF1BH
−
to FF21H
FF22H
PM2
68, 100,
136, 165
FF23H
PM3
FF24H
PM4
−
FF25H to
1
1
1
1
1
PM32
1
1
PM47
PM46
PM45
PM44
PM43
PM42
PM41
PM40
−
−
−
−
−
−
−
−
−
R/W
√
√
−
FFH
68
√
√
−
FFH
68
−
−
−
−
−
√
√
−
00H
71
√
√
−
00H
71
FF31H
FF32H
PU2
0
0
0
0
PU23
PU22
PU21
PU20
FF33H
PU3
0
0
0
0
0
PU32
0
0
FF34H
PU4
PU47
PU46
PU45
PU44
PU43
PU42
PU41
PU40
R/W
√
√
−
00H
71
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
1
1
R/W
−
√
−
67H
149
−
√
−
9AH
150
FF35H to
−
FF47H
FF48H
FF49H
WDTM
WDTE
−
−
WDCS WDCS WDCS WDCS WDCS
−
4
3
2
1
0
−
−
−
−
−
Notes 1. Only P34 is an input-only port.
2. A 16-bit access is possible only by the short direction addressing.
3. μPD78F921x only
Remark For a bit name enclosed in angle brackets (), the bit name is defined as a reserved word in the RA78K0S,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S.
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CHAPTER 3 CPU ARCHITECTURE
Symbol
R/W
Bit No.
Number of Bits
After
Manipulated
Reset
Simultaneously
FF50H
LVIM
7
6
5
4
3
2
1
0
1
8
16
FF51H
LVIS
0
0
0
0
LVIS3
LVIS2
00H
page
Address
Reference
Table 3-3. Special Function Registers (2/3)
210
Note 1
−
√
−
00H
211
Note 1
−
FF52H,
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
WDT
0
0
0
LVIRF
R
−
√
−
00H
−
FF53H
FF54H
RESF
−
−
−
−
−
−
−
−
LSRCM
0
0
0
0
0
0
0
FF55H to
204
Note 2
RF
−
−
−
−
−
−
−
−
FF59H to
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
TMC
TMC
TMC
0
0
PRM
PRM
√
√
−
00H
99
001
000
CRC
CRC
CRC
√
√
−
00H
97
002
001
000
√
√
−
00H
98
−
−
−
−
−
−
R/W
√
√
−
00H
FF5FH
FF60H
TMC00
FF61H
PRM00
FF62H
CRC00
FF63H
TOC00
ES110
0
0
ES100
0
ES010
0
−
−
−
−
−
−
−
−
−
TMHMD
1>
FF64H to
FF6FH
FF70H
1
FF71H to
E1>
−
2.1 V (TYP.)
Reset by
power-on-clear
Reset signal
Crystal/ceramic
oscillation selected
by option byte
Wait for clock
oscillation stabilization
Start with PCC = 02H,
PPCC = 02H
Clock division ratio
variable during
CPU operation
Interrupt
HALT
instruction
Interrupt
STOP
instruction
HALT
Remark PCC:
STOP
Processor clock control register
PPCC: Preprocessor clock control register
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CHAPTER 5 CLOCK GENERATORS
(3) External clock input circuit
If external clock input is selected by the option byte, the following is possible.
• High-speed operation
The accuracy of processing is improved as compared with high-speed internal oscillation (8 MHz (TYP.))
because an oscillation frequency of 2 MHz to 10 MHz can be selected and an external clock with a small
frequency deviation can be supplied.
• Improvement of expandability
If the external clock input circuit is selected as the oscillator, the X2 pin can be used as an I/O port pin. For
details, refer to CHAPTER 4 PORT FUNCTIONS.
Figures 5-12 and 5-13 show the timing chart and status transition diagram of default start by external clock input.
Figure 5-12. Timing of Default Start by External Clock Input
(a)
VDD
RESET
H
Internal reset
(b)
System clock
External clock input
PCC = 02H, PPCC = 02H
CPU clock
Option byte is read.
System clock is selected.
(Operation stopsNote)
Note Operation stop time is 277 μs (MIN.), 544 μs (TYP.), and 1.075 ms (MAX.).
(a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the
system clock.
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Figure 5-13. Status Transition of Default Start by External Clock Input
Power
application
VDD > 2.1 V (TYP.)
Reset by
power-on-clear
Reset signal
External clock input
selected by option byte
Start with PCC = 02H,
PPCC = 02H
Clock division ratio
variable during
CPU operation
Interrupt
HALT
instruction
Interrupt
STOP
instruction
HALT
Remark PCC:
STOP
Processor clock control register
PPCC: Preprocessor clock control register
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CHAPTER 5 CLOCK GENERATORS
5.6
Operation of Clock Generator Supplying Clock to Peripheral Hardware
The following two types of clocks are supplied to the peripheral hardware.
• Clock to peripheral hardware (fXP)
• Low-speed internal oscillation clock (fRL)
(1) Clock to peripheral hardware
The clock to the peripheral hardware is supplied by dividing the system clock (fX). The division ratio is selected
by the pre-processor clock control register (PPCC).
Three types of frequencies are selectable: “fX”, “fX/2”, and “fX/22”. Table 5-3 lists the clocks supplied to the
peripheral hardware.
Table 5-3. Clocks to Peripheral Hardware
PPCC1
PPCC0
Selection of clock to peripheral hardware (fXP)
0
0
fX
0
1
fX/2
1
0
fX/2
1
1
Setting prohibited
2
(2) Low-speed internal oscillation clock
The low-speed internal oscillator of the clock oscillator for interval time generation is always started after release
of reset, and oscillates at 240 kHz (TYP.).
It can be specified by the option byte whether the low-speed internal oscillator can or cannot be stopped by
software. If it is specified that the low-speed internal oscillator can be stopped by software, oscillation can be
started or stopped by using the low-speed internal oscillation mode register (LSRCM). If it is specified that it
cannot be stopped by software, the clock source of WDT is fixed to the low-speed internal oscillation clock (fRL).
The low-speed internal oscillator is independent of the CPU clock. If it is used as the source clock of WDT,
therefore, a hang-up can be detected even if the CPU clock is stopped. If the low-speed internal oscillator is used
as a count clock source of 8-bit timer H1, 8-bit timer H1 can operate even in the standby status.
Table 5-4 shows the operation status of the low-speed internal oscillator when it is selected as the source clock of
WDT and the count clock of 8-bit timer H1. Figure 5-14 shows the status transition of the low-speed internal
oscillator.
Table 5-4. Operation Status of Low-Speed Internal Oscillator
Option Byte Setting
Can be stopped by
software
LSRSTOP = 1
CPU Status
Operation mode
LSRSTOP = 0
LSRSTOP = 1
Standby
LSRSTOP = 0
Cannot be stopped
Operation mode
WDT Status
Stopped
Stopped
Operates
Operates
Stopped
Stopped
Stopped
Operates
Operates
Standby
88
TMH1 Status
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CHAPTER 5 CLOCK GENERATORS
Figure 5-14. Status Transition of Low-Speed Internal Oscillator
Power
application
VDD > 2.1 V (TYP.)
Reset by
power-on-clear
Reset signal
Select by option byte
if low-speed internal oscillator
can be stopped or not
Can be stopped
Cannot be stopped
Clock source of
WDT is selected
by softwareNote
Clock source of
WDT is fixed to fRL
Low-speed internal
oscillator can be stopped
Low-speed internal
oscillator cannot be stopped
LSRSTOP = 1
LSRSTOP = 0
Low-speed internal
oscillator stops
Note The clock source of the watchdog timer (WDT) is selected from fX or fRL, or it may be stopped. For details,
refer to CHAPTER 8 WATCHDOG TIMER.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.1
Functions of 16-bit Timer/Event Counter 00
16-bit timer/event counter 00 has the following functions.
(1) Interval timer
16-bit timer/event counter 00 generates interrupt requests at the preset time interval.
• Number of counts: 2 to 65536
(2) External event counter
16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of valid level
pulse width or more of a signal input externally.
• Valid level pulse width: 2/fXP or more
(3) Pulse width measurement
16-bit timer/event counter 00 can measure the pulse width of an externally input signal.
• Valid level pulse width: 2/fXP or more
(4) Square-wave output
16-bit timer/event counter 00 can output a square wave with any selected frequency.
• Cycle: (2 to 65536) × 2 × count clock cycle
(5) PPG output
16-bit timer/event counter 00 can output a square wave that have arbitrary cycle and pulse width.
• 1 < Pulse width < Cycle ≤ 65536
(6) One-shot pulse output
16-bit timer/event counter 00 can output a one-shot pulse for which output pulse width can be set to any
desired value.
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6.2
Configuration of 16-bit Timer/Event Counter 00
16-bit timer/event counter 00 consists of the following hardware.
Table 6-1. Configuration of 16-bit Timer/Event Counter 00
Item
Configuration
Timer counter
16-bit timer counter 00 (TM00)
Register
16-bit timer capture/compare registers 000, 010 (CR000, CR010)
Timer input
TI000, TI010
Timer output
TO00, output controller
Control registers
16-bit timer mode control register 00 (TMC00)
Capture/compare control register 00 (CRC00)
16-bit timer output control register 00 (TOC00)
Prescaler mode register 00 (PRM00)
Port mode register 2 (PM2)
Port register 2 (P2)
Port mode control register 2 (PMC2) (μPD78F921x only)
Figure 6-1 shows a block diagram of these counters.
Figure 6-1. Block Diagram of 16-bit Timer/Event Counter 00
Internal bus
Capture/compare control
register 00 (CRC00)
Selector
CRC002CRC001 CRC000
Noise
eliminator
INTP0/P21
Selector
to CR010
TI010/TO00/ANI1Note/
16-bit timer capture/compare
register 000 (CR000)
INTTM000
Match
Noise
eliminator
16-bit timer counter 00
(TM00)
Output
controller
TO00/TI010/ANI1Note/
INTP0/P21
Match
2
Output latch
(P21)
Noise
eliminator
TI000/ANI0Note/
TOH1/P20
Clear
PM21
16-bit timer capture/compare
register 010 (CR010)
Selector
fX
Selector
fXP
fXP/22
fXP/28
INTTM010
CRC002
PRM001 PRM000
Prescaler mode
register 00 (PRM00)
TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
16-bit timer output
16-bit timer mode
control register 00
control register 00
(TOC00)
(TMC00)
Internal bus
Note μPD78F921x only
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(1) 16-bit timer counter 00 (TM00)
TM00 is a 16-bit read-only register that counts count pulses.
The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read
during operation, input of the count clock is temporarily stopped, and the count value at that point is read.
Figure 6-2. Format of 16-bit Timer Counter 00 (TM00)
Address: FF12H, FF13H
Symbol
After reset: 0000H
R
FF13H
7
6
5
4
FF12H
3
2
1
0
7
6
5
4
3
2
1
0
TM00
The count value is reset to 0000H in the following cases.
If a reset signal is generated
If TMC003 and TMC002 are cleared
If the valid edge of TI000 is input in the clear & start mode entered by inputting the valid edge of TI000
If TM00 and CR000 match in the clear & start mode entered on a match between TM00 and CR000
If OSPT00 is set to 1 in the one-shot pulse output mode
Cautions 1. Even if TM00 is read, the value is not captured by CR010.
2. When TM00 is read, count misses do not occur, since the input of the count clock is
temporarily stopped and then resumed after the read.
(2) 16-bit timer capture/compare register 000 (CR000)
CR000 is a 16-bit register which has the functions of both a capture register and a compare register. Whether
it is used as a capture register or as a compare register is set by bit 0 (CRC000) of capture/compare control
register 00 (CRC00).
CR000 is set by 16-bit memory manipulation instruction.
A reset signal generation clears CR000 to 0000H.
Figure 6-3. Format of 16-bit Timer Capture/Compare Register 000 (CR000)
Address: FF14H, FF15H
Symbol
After reset: 0000H
R/W
FF15H
7
6
5
4
3
FF14H
2
1
0
7
6
5
4
3
2
1
0
CR000
• When CR000 is used as a compare register
The value set in CR000 is constantly compared with the 16-bit timer/counter 00 (TM00) count value, and an
interrupt request (INTTM000) is generated if they match. It can also be used as the register that holds the
interval time then TM00 is set to interval timer operation.
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• When CR000 is used as a capture register
It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the
TI000 or TI010 valid edge is performed by means of prescaler mode register 00 (PRM00) (refer to Table 62).
Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins
(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)
CR000 Capture Trigger
TI000 Pin Valid Edge
ES010
ES000
Falling edge
Rising edge
0
1
Rising edge
Falling edge
0
0
No capture operation
Both rising and falling edges
1
1
(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)
CR000 Capture Trigger
TI010 Pin Valid Edge
ES110
ES100
Falling edge
Falling edge
0
0
Rising edge
Rising edge
0
1
Both rising and falling edges
Both rising and falling edges
1
1
Remarks 1. Setting ES010, ES000 = 1, 0 and ES110, ES100 = 1, 0 is prohibited.
2. ES010, ES000:
Bits 5 and 4 of prescaler mode register 00 (PRM00)
ES110, ES100:
Bits 7 and 6 of prescaler mode register 00 (PRM00)
CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)
Cautions 1. Set CR000 to other than 0000H in the clear & start mode entered on match between TM00
and CR000.
This means a 1-pulse count operation cannot be performed when this
register is used as an external event counter. However, in the free-running mode and in
the clear & start mode using the valid edge of the TI000 pin, if CR000 is set to 0000H, an
interrupt request (INTTM000) is generated when CR000 changes from 0000H to 0001H
after an overflow (FFFFH).
2. If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), TM00
continues counting, overflows, and then starts counting from 0 again. If the new value of
CR000 is less than the old value, therefore, the timer must be reset to be restarted after
the value of CR000 is changed.
3. The value of CR000 after 16-bit timer/event counter 00 has stopped is not guaranteed.
4. The capture operation may not be performed for CR000 set in compare mode even if a
capture trigger is input.
5. When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a timer
output pin (TO00). When using P21 as the timer output pin (TO00), it cannot be used as
the input pin (TI010) of the valid edge.
6. If the register read period and the input of the capture trigger conflict when CR000 is
used as a capture register, the capture trigger input takes precedence and the read data
is undefined. Also, if the count stop of the timer and the input of the capture trigger
conflict, the capture trigger is undefined.
7. Changing the CR000 setting may cause a malfunction. To change the setting, refer to 6.5
Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare register
during timer operation.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(3) 16-bit timer capture/compare register 010 (CR010)
CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether
it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control
register 00 (CRC00).
CR010 is set by 16-bit memory manipulation instruction.
Reset signal generation clears CR010 to 0000H.
Figure 6-4. Format of 16-bit Timer Capture/Compare Register 010 (CR010)
Address: FF16H, FF17H
Symbol
After reset: 0000H
R/W
FF17H
7
6
5
4
FF16H
3
2
1
0
7
6
5
4
3
2
1
0
CR010
• When CR010 is used as a compare register
The value set in CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an
interrupt request (INTTM010) is generated if they match.
• When CR010 is used as a capture register
It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by
means of prescaler mode register 00 (PRM00) (refer to Table 6-3).
Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1)
CR010 Capture Trigger
TI000 Pin Valid Edge
ES010
ES000
Falling edge
Falling edge
0
0
Rising edge
Rising edge
0
1
Both rising and falling edges
Both rising and falling edges
1
1
Remarks 1. Setting ES010, ES000 = 1, 0 is prohibited.
2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00)
CRC002:
Bit 2 of capture/compare control register 00 (CRC00)
Cautions 1. In the free-running mode and in the clear & start mode using the valid edge of the TI000
pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated when CR010
changes from 0000H to 0001H after an overflow (FFFFH).
2. If the new value of CR010 is less than the value of 16-bit timer counter 00 (TM00), TM00
continues counting, overflows, and then starts counting from 0 again. If the new value of
CR010 is less than the old value, therefore, the timer must be reset to be restarted after
the value of CR010 is changed.
3. The value of CR010 after 16-bit timer/event counter 00 has stopped is not guaranteed.
4. The capture operation may not be performed for CR010 set in compare mode even if a
capture trigger is input.
5. If the register read period and the input of the capture trigger conflict when CR010 is
used as a capture register, the capture trigger input takes precedence and the read data
is undefined. Also, if the timer count stop and the input of the capture trigger conflict,
the capture data is undefined.
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Caution 6.
Changing the CR010 setting during TM00 operation may cause a malfunction. To change
the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing
compare register during timer operation.
6.3
Registers to Control 16-bit Timer/Event Counter 00
The following seven types of registers are used to control 16-bit timer/event counter 00.
• 16-bit timer mode control register 00 (TMC00)
• Capture/compare control register 00 (CRC00)
• 16-bit timer output control register 00 (TOC00)
• Prescaler mode register 00 (PRM00)
• Port mode register 2 (PM2)
• Port register 2 (P2)
• Port mode control register 2 (PMC2) (μPD78F921x only)
(1) 16-bit timer mode control register 00 (TMC00)
This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output
timing, and detects an overflow.
TMC00 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets the value of TMC00 to 00H.
Caution 16-bit timer counter 00 (TM00) starts operating as soon as values other than 0 and 0
(operation stop mode) are set to TMC002 and TMC003, respectively.
Set TMC002 and
TMC003 to 0 and 0 to stop operation.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-5. Format of 16-bit Timer Mode Control Register 00 (TMC00)
Address: FF60H
After reset: 00H
Symbol
7
6
5
4
TMC00
0
0
0
0
R/W
3
2
1
TMC003 TMC002 TMC001 OVF00
Operating mode and clear
TMC003 TMC002 TMC001
TO00 inversion timing selection
Interrupt request generation
mode selection
0
0
0
Operation stop
0
0
1
(TM00 cleared to 0)
0
1
0
Free-running mode
0
1
1
0
1
0
Clear & start occurs on valid
No change
Not generated
Match between TM00 and
< When operating as compare
CR000 or match between
register >
TM00 and CR010
Generated on match between
Match between TM00 and
TM00 and CR000, or match
CR000, match between TM00
between TM00 and CR010
and CR010 or TI000 pin valid
< When operating as capture
edge
register >
−
1
0
1
edge of TI000 pin
1
1
0
Clear & start occurs on match
Match between TM00 and
between TM00 and CR000
CR000 or match between
Generated on TI000 pin and
TI010 pin valid edge
TM00 and CR010
1
1
1
Match between TM00 and
CR000, match between TM00
and CR010 or TI000 pin valid
edge
OVF00
Overflow detection of 16-bit timer counter 00 (TM00)
0
Overflow not detected
1
Overflow detected
Cautions 1. The timer operation must be stopped before writing to bits other than the OVF00 flag.
2. If the timer is stopped, timer counts and timer interrupts do not occur, even if a signal is input to
the TI000/TI010 pins.
3. Except when the valid edge of the TI000 pin is selected as the count clock, stop the timer
operation before setting STOP mode or system clock stop mode; otherwise the timer may
malfunction when the system clock starts.
4. Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register 00 (PRM00) after
stopping the timer operation.
5. If the clear & start mode entered on a match between TM00 and CR000, clear & start mode at the
valid edge of the TI000 pin, or free-running mode is selected, when the set value of CR000 is
FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1.
6. Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes
0001H) after the occurrence of a TM00 overflow, the OVF00 flag is re-set and clearance becomes
invalid.
7. The capture operation is performed at the fall of the count clock. An interrupt request input
(INTTM0n0), however, occurs at the rise of the next count clock.
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Remark
TM00:
16-bit timer counter 00
CR000:
16-bit timer capture/compare register 000
CR010:
16-bit timer capture/compare register 010
(2) Capture/compare control register 00 (CRC00)
This register controls the operation of the 16-bit capture/compare registers (CR000, CR010).
CRC00 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets the value of CRC00 to 00H.
Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00)
Address: FF62H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
CRC00
0
0
0
0
0
CRC002
CRC001
CRC000
CRC002
CR010 operating mode selection
0
Operate as compare register
1
Operate as capture register
CRC001
CR000 capture trigger selection
0
Capture on valid edge of TI010 pin
1
Capture on valid edge of TI000 pin by reverse phase
CRC000
Note
CR000 operating mode selection
0
Operate as compare register
1
Operate as capture register
Note When the CRC001 bit value is 1, capture is not performed if both the rising and falling edges have been
selected as the valid edges of the TI000 pin.
Cautions 1. The timer operation must be stopped before setting CRC00.
2. When the clear & start mode entered on a match between TM00 and CR000 is selected by
16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a
capture register.
3. To ensure the reliability of the capture operation, the capture trigger requires a pulse
longer than two cycles of the count clock selected by prescaler mode register 00
(PRM00) (refer to Figure 6-18).
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(3) 16-bit timer output control register 00 (TOC00)
This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F
set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-shot
pulse output operation enable/disable, and output trigger of one-shot pulse by software.
TOC00 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets the value of TOC00 to 00H.
Figure 6-7. Format of 16-bit Timer Output Control Register 00 (TOC00)
Address: FF63H
After reset: 00H
R/W
Symbol
7
4
1
TOC00
0
OSPT00
OSPE00
TOC004
LVS00
LVR00
TOC001
TOE00
OSPT00
One-shot pulse output trigger control via software
0
No one-shot pulse output trigger
1
One-shot pulse output trigger
OSPE00
One-shot pulse output operation control
0
Successive pulse output mode
1
One-shot pulse output mode
TOC004
Note
Timer output F/F control using match of CR010 and TM00
0
Disables inversion operation
1
Enables inversion operation
LVS00
LVR00
0
0
No change
Timer output F/F status setting
0
1
Timer output F/F reset (0)
1
0
Timer output F/F set (1)
1
1
Setting prohibited
TOC001
Timer output F/F control using match of CR000 and TM00
0
Disables inversion operation
1
Enables inversion operation
TOE00
Timer output control
0
Disables output (output fixed to level 0)
1
Enables output
Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI000 pin valid edge. In the mode in which clear & start occurs on a match
between TM00 and CR000, one-shot pulse output is not possible because an overflow does not occur.
Cautions 1. Timer operation must be stopped before setting other than OSPT00.
2. If LVS00 and LVR00 are read, 0 is read.
3. OSPT00 is automatically cleared after data is set, so 0 is read.
4. Do not set OSPT00 to 1 other than in one-shot pulse output mode.
5. A write interval of two cycles or more of the count clock selected by prescaler mode register
00 (PRM00) is required, when OSPT00 is set to 1 successively.
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Caution
6. When TOE00 is 0, set TOE00, LVS00, and LVR00 at the same time with the 8-bit memory
manipulation instruction. When TOE00 is 1, LVS00 and LVR00 can be set with the 1-bit
memory manipulation instruction.
(4) Prescaler mode register 00 (PRM00)
This register is used to set the 16-bit timer counter 00 (TM00) count clock and the TI000, TI010 pin input valid
edges.
PRM00 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets the value of PRM00 to 00H.
Figure 6-8. Format of Prescaler Mode Register 00 (PRM00)
Address: FF61H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
PRM00
ES110
ES100
ES010
ES000
0
0
PRM001
PRM000
ES110
ES100
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES010
ES000
0
0
Falling edge
0
1
Rising edge
TI010 pin valid edge selection
TI000 pin valid edge selection
1
0
Setting prohibited
1
1
Both falling and rising edges
PRM001
PRM000
0
0
fXP (10 MHz)
0
1
fXP/2 (2.5 MHz)
1
0
fXP/2 (39.06 kHz)
1
1
TI000 pin valid edge
Count clock selection
2
8
Note
Remarks 1. fXP: Oscillation frequency of clock supplied to peripheral hardware
2. ( ): fXP = 10 MHz
Note The external clock requires a pulse longer than two cycles of the internal count clock (fXP).
Cautions 1. Always set data to PRM00 after stopping the timer operation.
2. If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start
mode and the capture trigger at the valid edge of the TI000 pin.
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Cautions 3. In the following cases, note with caution that the valid edge of the TI0n0 pin is detected.
Immediately after a system reset, if a high level is input to the TI0n0 pin, the
operation of 16-bit timer counter 00 (TM00) is enabled
→ If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is
enabled.
If the TM00 operation is stopped while the TI0n0 pin is at high level, TM00 operation
is then enabled after a low level is input to the TI0n0 pin
→ If the falling edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a falling edge is detected immediately after the TM00 operation is
enabled.
If the TM00 operation is stopped while the TI0n0 pin is at low level, TM00 operation
is then enabled after a high level is input to the TI0n0 pin
→ If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is
enabled.
4. The sampling clock used to eliminate noise differs when the valid edge of TI000 is used
as the count clock and when it is used as a capture trigger. In the former case, the count
clock is fXP, and in the latter case the count clock is selected by prescaler mode register
00 (PRM00). The capture operation is not performed until the valid edge is sampled and
the valid level is detected twice, thus eliminating noise with a short pulse width.
5. When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a timer
output pin (TO00). When using P21 as the timer output pin (TO00), it cannot be used as
the input pin (TI010) of the valid edge.
Remark
n = 0, 1
Note
(5) Port mode register 2 (PM2) and port mode control register 2 (PMC2)
When using the P21/TO00/TI010/ANI1/INTP0 pin for timer output, clear PM21, the output latch of P21, and
PMC21 to 0.
When using the P20/TI000/TOH1/ANI0 and P21/TO00/TI010/ANI1/INTP0 pins as a timer input, set PM20 and
PM21 to 1, and clear PMC20 and PMC21 to 0.
At this time, the output latches of P20 and P21 can be either 0 or 1.
PM2 and PMC2 are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets the value of PM2 to FFH, and clears the value of PMC2 to 00H.
Note μPD78F921x only
Figure 6-9. Format of Port Mode Register 2 (PM2)
Address: FF22H After reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
PM2
1
1
1
1
PM23
PM22
PM21
PM20
PM2n
100
P2n pin I/O mode selection (n = 0 to 3)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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Figure 6-10. Format of Port Mode Control Register 2 (PMC2) (μPD78F921x only)
Address: FF84H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
PMC2
0
0
0
0
PMC23
PMC22
PMC21
PMC20
PMC2n
6.4
Specification of operation mode (n = 0 to 3)
0
Port/Alternate-function (except A/D converter) mode
1
A/D converter mode
Operation of 16-bit Timer/Event Counter 00
6.4.1
Interval timer operation
Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown
in Figure 6-11 allows operation as an interval timer.
Setting
The basic operation setting procedure is as follows.
Set the CRC00 register (see Figure 6-11 for the set value).
Set any value to the CR000 register.
Set the count clock by using the PRM00 register.
Set the TMC00 register to start the operation (see Figure 6-11 for the set value).
Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the
setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare
register during timer operation.
Remark
For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS.
Interrupt requests are generated repeatedly using the count value set in 16-bit timer capture/compare register 000
(CR000) beforehand as the interval.
When the count value of 16-bit timer counter 00 (TM00) matches the value set to CR000, counting continues with
the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated.
The count clock of the 16-bit timer/event counter can be selected using bits 0 and 1 (PRM000, PRM001) of
prescaler mode register 00 (PRM00).
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Figure 6-11. Control Register Settings for Interval Timer Operation
(a) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
0/1
0/1
0
CR000 used as compare register
(b) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
PRM00
0/1
0/1
0/1
0/1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
(c) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
1
1
0/1
0
Clears and starts on match between TM00 and CR000.
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the
description of the respective control registers for details.
Figure 6-12. Interval Timer Configuration Diagram
16-bit timer capture/compare
register 000 (CR000)
INTTM000
Selector
fXP
fXP/22
fXP/28
TI000/ANI0/
TOH1/P20
16-bit timer counter 00
(TM00)
Noise
eliminator
Note
OVF00
Clear
circuit
fXP
Note OVF00 is set to 1 only when 16-bit timer capture/compare register 000 (CR000) is set to FFFFH.
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Figure 6-13. Timing of Interval Timer Operation
t
Count clock
TM00 count value
0000H
0001H
N
Timer operation enabled
CR000
0000H 0001H
N
Clear
N
0000H 0001H
N
Clear
N
N
N
INTTM000
Interrupt request generated
Remark
Interrupt request generated
Interval time = (N + 1) × t
N = 0001H to FFFFH (settable range)
When the compare register is changed during timer count operation, if the value after 16-bit timer capture/compare
register 000 (CR000) is changed is smaller than that of 16-bit timer counter 00 (TM00), TM00 continues counting,
overflows and then restarts counting from 0. Thus, if the value (M) after the CR000 change is smaller than that (N)
before the change, it is necessary to restart the timer after changing CR000.
Figure 6-14. Timing After Change of Compare Register During Timer Count Operation (N → M: N > M )
Count clock
N
CR000
TM00 count value
Remark
6.4.2
X–1
M
X
FFFFH
0000H
0001H
0002H
N>X>M
External event counter operation
Setting
The basic operation setting procedure is as follows.
Set the CRC00 register (see Figure 6-15 for the set value).
Set the count clock by using the PRM00 register.
Set any value to the CR000 register (0000H cannot be set).
Set the TMC00 register to start the operation (see Figure 6-15 for the set value).
Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control
register 2 (PMC2).
2. For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS.
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The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit
timer counter 00 (TM00).
TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input.
When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is
cleared to 0 and the interrupt request signal (INTTM000) is generated.
Input a value other than 0000H to CR000. (A count operation with a pulse cannot be carried out.)
The rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (ES000 and ES010) of
prescaler mode register 00 (PRM00).
Because an operation is carried out only when the valid edge of the TI000 pin is detected twice after sampling with
the internal clock (fXP), noise with a short pulse width can be removed.
Figure 6-15. Control Register Settings in External Event Counter Mode (with Rising Edge Specified)
(a) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
0/1
0/1
0
CR000 used as compare register
(b) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
PRM00
0/1
0/1
0
1
3
2
0
0
PRM001 PRM000
1
1
Selects external clock.
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
(c) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
1
1
0/1
0
Clears and starts on match between TM00 and CR000.
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter.
See the description of the respective control registers for details.
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Figure 6-16. External Event Counter Configuration Diagram
Internal bus
16-bit timer capture/compare
register 000 (CR000)
Match
INTTM000
Clear
fXP
OVF00Note
16-bit timer counter 00 (TM00)
Noise eliminator
Valid edge of TI000
Note OVF00 is 1 only when 16-bit timer capture/compare register 000 (CR000) is set to FFFFH.
Figure 6-17. External Event Counter Operation Timing (with Rising Edge Specified)
(1) INTTM000 generation timing immediately after operation starts
Counting is started after a valid edge is detected twice.
Timer operation starts
Count starts
TI000 pin input
1
TM00 count value
2
3
0000H 0001H 0002H 0003H
N–2
N–1
N
0000H 0001H 0002H
N
CR000
INTTM000
(2) INTTM000 generation timing after INTTM000 has been generated twice
TI000 pin input
TM00 count value
CR000
N
0000H 0001H 0002H 0003H 0004H
N–1
N
0000H 0001H 0002H 0003H
N
INTTM000
Caution When reading the external event counter count value, TM00 should be read.
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6.4.3
Pulse width measurement operations
It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer
counter 00 (TM00).
There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by
restarting the timer in synchronization with the edge of the signal input to the TI000 pin.
When an interrupt occurs, necessary pulse width is calculable by reading the valid value of the capture register.
The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by
prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating
noise with a short pulse width (see Figure 6-18).
Figure 6-18. CR010 Capture Operation with Rising Edge Specified
Count clock
TM00
N−3
N−2
N−1
N
N+1
TI000
Rising edge detection
N
CR010
INTTM010
Setting
The basic operation setting procedure is as follows.
Set the CRC00 register (see Figures 6-19, 6-22, 6-24, and 6-26 for the set value).
Set the count clock by using the PRM00 register.
Set the TMC00 register to start the operation (see Figures 6-19, 6-22, 6-24, and 6-26 for the set value).
Caution To use two capture registers, set the TI000 and TI010 pins.
Remarks 1. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 2 (PM2) and port mode
control register 2 (PMC2).
2. For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 10
INTERRUPT
FUNCTIONS.
(1) Pulse width measurement with free-running counter and one capture register
Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and
ES010) of PRM00.
When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the valid edge specified by
PRM00 is input, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an
external interrupt request signal (INTTM010) is set.
Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed
when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width.
Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter.
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Figure 6-19. Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register (When TI000 and CR010 Are Used)
(a) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
1
0/1
0
CR000 used as compare register
CR010 used as capture register
(b) Prescaler mode register 00 (PRM00)
ES101 ES100 ES010 ES000
PRM00
0/1
0/1
1
1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies both edges for pulse width detection.
Setting invalid (setting “10” is prohibited.)
(c) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
0
1
0/1
0
Free-running mode
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
Figure 6-20. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
fXP/22
fXP/28
TI000/ANI0/
TOH1/P20
Selector
fXP
16-bit timer/counter 00
(TM00)
16-bit timer capture/compare
register 010 (CR010)
INTTM010
Internal bus
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Figure 6-21. Timing of Pulse Width Measurement Operation by Free-Running Counter
and One Capture Register (with Both Edges Specified)
t
Count clock
TM00 count value
0000H 0001H
D0
D0 + 1
D1
D1 + 1
FFFFH 0000H
D2
D3
TI000 pin input
CR010 capture value
D0
D1
D2
D3
INTTM010
(D1 − D0) × t
(D2 − D1) × t
Note
(D3 − D2) × t
Note The carry flag is set to 1. Ignore this setting.
(2) Measurement of two pulse widths with free-running counter
When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously
measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin.
Specify both the rising and falling edges as the valid edges of the TI000 and TI010 pins, by using bits 4 and 5
(ES000 and ES010) and bits 6 and 7 (ES100 and ES110) of PRM00.
When the valid edge specified by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00) is
input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and
an interrupt request signal (INTTM010) is set.
Also, when the valid edge specified by bits 6 and 7 (ES100 and ES110) of PRM00 is input to the TI010 pin, the
value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal
(INTTM000) is set.
Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a
capture operation is only performed when a valid level of the TI000 or TI010 pin is detected twice, thus
eliminating noise with a short pulse width.
Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter.
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Figure 6-22. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter
(a) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
1
0
1
CR000 used as capture register
Captures valid edge of TI010 pin to CR000.
CR010 used as capture register
(b) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
PRM00
1
1
1
1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies both edges for pulse width detection.
Specifies both edges for pulse width detection.
(c) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
0
1
0/1
0
Free-running mode
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified)
t
Count clock
TM00 count value
0000H 0001H
D0
D0 + 1
D1
D1 + 1
FFFFH 0000H
D2
D2 + 1 D2 + 2
D3
TI000 pin input
CR010 capture value
D0
D1
D2
INTTM010
TI010 pin input
CR000 capture value
D1
D2 + 1
INTTM000
(D1 − D0) × t
(D2 − D1) × t Note
(D3 − D2) × t
((D2 + 1) − D1) × t Note
Note The carry flag is set to 1. Ignore this setting.
(3) Pulse width measurement with free-running counter and two capture registers
When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse
width of the signal input to the TI000 pin.
Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and
ES010) of PRM00.
When the rising or falling edge specified by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00
(PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010
(CR010) and an interrupt request signal (INTTM010) is set.
Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken
into 16-bit timer capture/compare register 000 (CR000).
Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a
capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating
noise with a short pulse width.
Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter.
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Figure 6-24. Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers (with Rising Edge Specified)
(a) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
1
1
1
CR000 used as capture register
Captures to CR000 at inverse edge
to valid edge of TI000Note.
CR010 used as capture register
(b) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
PRM00
0/1
0/1
0
1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
(c) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
0
1
0/1
0
Free-running mode
Note If the valid edge of TI000 is specified to be both the rising and falling edges, 16-bit timer capture/compare
register 000 (CR000) cannot perform the capture operation. When the CRC001 bit value is 1, the TM00
count value is not captured in the CR000 register when a valid edge of the TI010 pin is detected, but the
input from the TI010 pin can be used as an external interrupt source because INTTM000 is generated at
that timing.
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 6-25. Timing of Pulse Width Measurement Operation by Free-Running Counter
and Two Capture Registers (with Rising Edge Specified)
t
Count clock
TM00 count value
0000H 0001H
D0
D1
D0 + 1
D1 + 1
FFFFH 0000H
D2
D2 + 1
D3
TI000 pin input
CR010 capture value
D0
D2
CR000 capture value
D1
D3
INTTM010
(D1 − D0) × t
(D2 − D1) × t
Note
(D3 − D2) × t
Note The carry flag is set to 1. Ignore this setting.
(4) Pulse width measurement by means of restart
Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and
ES010) of PRM00.
When input of a valid edge to the TI000 pin is detected, the count value of 16-bit timer/counter 00 (TM00) is
taken into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to
the TI000 pin is measured by clearing TM00 and restarting the count.
Sampling is performed at the interval selected by prescaler mode register 00 (PRM00) and a capture operation
is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short
pulse width.
Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter.
Figure 6-26. Control Register Settings for Pulse Width Measurement by Means of Restart
(with Rising Edge Specified) (1/2)
(a) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
1
1
1
CR000 used as capture register
Captures to CR000 at inverse edge to valid edge of TI000Note.
CR010 used as capture register
Note If the valid edge of TI000 is specified to be both the rising and falling edges, 16-bit timer capture/compare
register 000 (CR000) cannot perform the capture operation.
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Figure 6-26. Control Register Settings for Pulse Width Measurement by Means of Restart
(with Rising Edge Specified) (2/2)
(b) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
PRM00
0/1
0/1
0
1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
(c) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
1
0
0/1
0
Clears and starts at valid edge of TI000 pin.
Figure 6-27. Timing of Pulse Width Measurement Operation by Means of Restart
(with Rising Edge Specified)
t
Count clock
TM00 count value
0000H 0001H
D0
0000H 0001H
D1
D2 0000H 0001H
TI000 pin input
CR010 capture value
D0
D2
D1
CR000 capture value
INTTM010
(D1 + 1) × t
(D2 + 1) × t
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4.4
Square-wave output operation
Setting
The basic operation setting procedure is as follows.
Set the count clock by using the PRM00 register.
Set the CRC00 register (see Figure 6-28 for the set value).
Set the TOC00 register (see Figure 6-28 for the set value).
Set any value to the CR000 register (0000H cannot be set).
Set the TMC00 register to start the operation (see Figure 6-28 for the set value).
Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the
setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare
register during timer operation.
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control
register 2 (PMC2).
2. For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS.
A square wave with any selected frequency can be output at intervals determined by the count value preset to 16bit timer capture/compare register 000 (CR000).
The TO00 pin output status is reversed at intervals determined by the count value preset to CR000 + 1 by setting
bit 0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a square wave
with any selected frequency to be output.
Figure 6-28. Control Register Settings in Square-Wave Output Mode (1/2)
(a) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
PRM00
0/1
0/1
0/1
0/1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
(b) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
0/1
0/1
0
CR000 used as compare register
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Figure 6-28. Control Register Settings in Square-Wave Output Mode (2/2)
(c) 16-bit timer output control register 00 (TOC00)
7
TOC00
0
OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
0
0
0
0/1
0/1
1
1
Enables TO00 output.
Inverts output on match between TM00 and CR000.
Specifies initial value of TO00 output F/F (setting “11” is prohibited).
Does not invert output on match between TM00 and CR010.
Disables one-shot pulse output.
(d) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
1
1
0
0
Clears and starts on match between TM00 and CR000.
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the
description of the respective control registers for details.
Figure 6-29. Square-Wave Output Operation Timing
Count clock
TM00 count value
CR000
0000H 0001H 0002H
N−1
N
0000H 0001H 0002H
N−1
N
0000H
N
INTTM000
TO00 pin output
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4.5
PPG output operations
Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown
in Figure 6-30 allows operation as PPG (Programmable Pulse Generator) output.
Setting
The basic operation setting procedure is as follows.
Set the CRC00 register (see Figure 6-30 for the set value).
Set any value to the CR000 register as the cycle.
Set any value to the CR010 register as the duty factor.
Set the TOC00 register (see Figure 6-30 for the set value).
Set the count clock by using the PRM00 register.
Set the TMC00 register to start the operation (see Figure 6-30 for the set value).
Caution Changing the CRC0n0 setting during TM00 operation may cause a malfunction. To change the
setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare
register during timer operation.
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control
register 2 (PMC2).
2. For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS.
3. n = 0 or 1
In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle
that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer
capture/compare register 000 (CR000), respectively.
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Figure 6-30. Control Register Settings for PPG Output Operation
(a) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
×
0
0
CR000 used as compare register
CR010 used as compare register
(b) 16-bit timer output control register 00 (TOC00)
7
TOC00
0
OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
0
0
1
0/1
0/1
1
1
Enables TO00 output.
Inverts output on match between TM00 and CR000.
Specifies initial value of TO00 output F/F (setting "11" is prohibited).
Inverts output on match between TM00 and CR010.
Disables one-shot pulse output.
(c) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
PRM00
0/1
0/1
0/1
0/1
3
2
0
0
PRM001 PRM000
0/1
0/1
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
(d) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001 OVF00
1
1
0
0
Clears and starts on match between TM00 and CR000.
Cautions 1. Values in the following range should be set to CR000 and CR010:
0000H < CR010 < CR000 ≤ FFFFH
2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of
(CR010 setting value + 1)/(CR000 setting value + 1).
Remark
×: Don’t care
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-31. Configuration Diagram of PPG Output
16-bit timer capture/compare
register 000 (CR000)
Selector
fXP
fXP/22
fXP/28
Noise
eliminator
Output controller
TI000/ANI0/
TOH1/P20
Clear
circuit
16-bit timer counter 00
(TM00)
fXP
16-bit timer capture/compare
register 010 (CR010)
Figure 6-32. PPG Output Operation Timing
t
Count clock
TM00 count value N
0000H 0001H
M−1
M
Clear
CR000 capture value
N
CR010 capture value
M
Pulse width: (M + 1) × t
1 cycle: (N + 1) × t
118
N
0000H 0001H
Clear
TO00
Remark
N−1
0000H < M < N ≤ FFFFH
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TO00/TI010/ANI1/
INTP0/P21
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4.6
One-shot pulse output operation
16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external
trigger (TI000 pin input).
Setting
The basic operation setting procedure is as follows.
Set the count clock by using the PRM00 register.
Set the CRC00 register (see Figures 6-33 and 6-35 for the set value).
Set the TOC00 register (see Figures 6-33 and 6-35 for the set value).
Set any value to the CR000 and CR010 registers (0000H cannot be set).
Set the TMC00 register to start the operation (see Figures 6-33 and 6-35 for the set value).
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control
register 2 (PMC2).
2. For how to enable the INTTM000 (if necessary, INTTM010) interrupt, see CHAPTER 10
INTERRUPT FUNCTIONS.
(1) One-shot pulse output with software trigger
A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),
capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in
Figure 6-33, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software.
By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes
active at the count value (N) set in advance to 16-bit timer capture/compare register 010 (CR010). After that,
the output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000
(CR000)Note.
Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00
register, the TMC003 and TMC002 bits of the TMC00 register must be cleared to 00.
Note The case where N < M is described here. When N > M, the output becomes active with the CR000
register and inactive with the CR010 register. Do not set N to M.
Cautions 1. Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To output the
one-shot pulse again, wait until the current one-shot pulse output is completed.
2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software
trigger, do not change the level of the TI000 pin or its alternate-function port pin.
Because the external trigger is valid even in this case, the timer is cleared and started even
at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a
pulse at an undesired timing.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-33. Control Register Settings for One-Shot Pulse Output with Software Trigger
(a) Prescaler mode register 00 (PRM00)
PRM00
ES110
ES100
ES010
ES000
3
2
0/1
0/1
0/1
0/1
0
0
PRM001 PRM010
0/1
0/1
Selects count clock.
Setting invalid
(setting “10” is prohibited.)
Setting invalid
(setting “10” is prohibited.)
(b) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
0
0/1
0
CR000 as compare register
CR010 as compare register
(c) 16-bit timer output control register 00 (TOC00)
7
TOC00
0
OSPT00 OSPE00 TOC004
0
1
1
LVS00
LVR00
TOC001
TOE00
0/1
0/1
1
1
Enables TO00 output.
Inverts output upon match
between TM00 and CR000.
Specifies initial value of
TO00 output F/F (setting “11” is prohibited.)
Inverts output upon match
between TM00 and CR010.
Sets one-shot pulse output mode.
Set to 1 for output.
(d) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001
0
1
0
OVF00
0
Free-running mode
Caution Do not set 0000H to the CR000 and CR010 registers.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-34. Timing of One-Shot Pulse Output Operation with Software Trigger
Set TMC00 to 04H
(TM00 count starts)
Count clock
TM00 count 0000H 0001H
N
N+1
0000H
N−1
N
M−1
M
M+1 M+2
CR010 set value
N
N
N
N
CR000 set value
M
M
M
M
OSPT00
INTTM010
INTTM000
TO00 pin output
Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop
mode) is set to the TMC003 and TMC002 bits.
Remark
N M, the output becomes active with the CR000
register and inactive with the CR010 register. Do not set N to M.
Caution Do not input the external trigger again while the one-shot pulse is output.
To output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-35. Control Register Settings for One-Shot Pulse Output with External Trigger
(with Rising Edge Specified)
(a) Prescaler mode register 00 (PRM00)
PRM00
ES110
ES100
ES010
ES000
3
2
0/1
0/1
0
1
0
0
PRM001 PRM000
0/1
0/1
Selects count clock
(setting “11” is prohibited).
Specifies the rising edge
for pulse width detection.
Setting invalid
(setting “10” is prohibited.)
(b) Capture/compare control register 00 (CRC00)
CRC00
7
6
5
4
3
0
0
0
0
0
CRC002 CRC001 CRC000
0
0/1
0
CR000 used as compare register
CR010 used as compare register
(c) 16-bit timer output control register 00 (TOC00)
7
TOC00
0
OSPT00 OSPE00 TOC004
0
1
1
LVS00
LVR00
TOC001
TOE00
0/1
0/1
1
1
Enables TO00 output.
Inverts output upon match
between TM00 and CR000.
Specifies initial value of
TO00 output F/F (setting “11” is prohibited.)
Inverts output upon match
between TM00 and CR010.
Sets one-shot pulse output mode.
(d) 16-bit timer mode control register 00 (TMC00)
TMC00
7
6
5
4
0
0
0
0
TMC003 TMC002 TMC001
OVF00
0
0
1
0
Clears and starts at
valid edge of TI000 pin.
Caution Do not set 0000H to the CR000 and CR010 registers.
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Figure 6-36. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)
When TMC00 is set to 08H
(TM00 count starts)
t
Count clock
TM00 count value 0000H 0001H
0000H
N
N+1 N+2
M−2 M−1
M
M+1 M+2
CR010 set value
N
N
N
N
CR000 set value
M
M
M
M
TI000 pin input
INTTM010
INTTM000
TO00 pin output
Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is
set to the TMC002 and TMC003 bits.
Remark
N
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