VF2510BGT

ICSVF2510 Integrated Circuit Systems, Inc. 3.3V Phase-Lock Loop Clock Driver General Description Features The ICSVF2510 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The ICSVF2510 operates at 3.3V VCC and drives up to ten clock loads. • One bank of ten outputs provide low-skew, low-jitter copies of CLKIN. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLKIN. Outputs can be enabled or disabled via control (OE) inputs. When the OE inputs are high, the outputs align in phase and frequency with CLKIN; when the OE inputs are low, the outputs are disabled to the logic low state. • • • • • • • Meets or exceeds PC133 registered DIMM specification1.1 Spread Spectrum Clock Compatible Distributes one clock input to one bank of ten outputs Operating frequency 20MHz to 200MHz External feedback input (FBIN) terminal is used to synchrionize the outputs to the clock input No external RC network required Operates at 3.3V Vcc Plastic 24-pin 173mil TSSOP package The ICSVF2510 does not require external RC filter components. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. The test mode shuts off the PLL and connects the input directly to the output buffer. This test mode, the ICSVF2510 can be use as low skew fanout clock buffer device. The ICSVF2510 comes in 24 pin 173mil Thin Shrink SmallOutline package (TSSOP) package. FBOUT CLK0 CLK1 CLK2 FBIN CLKIN PLL CLK3 CLK4 AGND VCC CLK0 CLK1 CLK2 GND GND CLK3 CLK4 VCC OE FBOUT 1 2 3 4 5 6 7 8 9 10 11 12 ICSVF2510 Pin Configuration Block Diagram 24 23 22 21 20 19 18 17 16 15 14 13 CLKIN AVCC VCC CLK9 CLK8 GND GND CLK7 CLK6 CLK5 VCC FBIN 24 Pin TSSOP AVCC CLK5 CLK6 CLK7 CLK8 CLK9 OE 0722A—05/07/03 4.40 mm. Body, 0.65 mm. Pitch ICSVF2510 Pin Descriptions PIN # 1 2, 10, 14 3 4 5 6, 7, 18, 19 8 9 PIN NAME AGND VCC CLK0 CLK1 CLK2 GND CLK3 CLK4 TYPE PWR PWR OUT OUT OUT PWR OUT OUT 11 OE1 12 13 15 16 17 20 21 22 FBOUT FBIN CLK5 CLK6 CLK7 CLK8 CLK9 VCC OUT IN OUT OUT OUT OUT OUT PWR 23 AVCC IN 24 CLKIN IN IN DESCRIPTION Analog Ground Power Supply (3.3V) Buffered clock output. Buffered clock output. Buffered clock output. Ground Buffered clock output. Buffered clock output. Output enable (has internal pull_up). When high, normal operation. When low, clock outputs are disabled to a logic low state. Feedback output Feedback input Buffered clock output. Buffered clock output. Buffered clock output. Buffered clock output. Buffered clock output. Power Supply (3.3V) digital supply. Analog power supply (3.3V). When input is ground PLL is off and bypassed. Clock input Note: 1. Weak pull-ups on these inputs Functionality INPUTS OUTPUTS OE AVCC CLK (9:0) FBOUT Source PLL Shutdown 0 1 3.33 3.33 0 Driven Driven Driven PLL PLL N N Buffer Mode 0 Driven Driven Driven 0 0 CLKIN 1 0 CLKIN Test mode: When AVCC is 0, shuts off the PLL and connects the input directly to the output buffers 0722A—05/07/03 2 Y Y ICSVF2510 Absolute Maximum Ratings Supply Voltage (AVCC) . . . . . . . . . . . . . . . . . Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . AVCC < (V cc + 0.7 V) 4.3 V GND –0.5 V to V cc + 0.5 V 0°C to +70°C –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - OUTPUT TA = 0 - 70°C; VDD = V DDL = 3.3 V +/-10%; CL = 30 pF; RL = 500 Ohms (unless otherwise stated) PARAMETER SYMBOL CONDITIONS IOH = -8 mA Output High Voltage VOH Output Low Voltage VOL IOL = 8 mA VOH = 2.4 V Output High Current IOH VOH = 2.0 V VOL = 0.8 V Output Low Current IOL VOL = 0.55 V Rise Time1 Tr VOL = 0.8 V, VOH = 2.0 V MIN 2.4 TYP 2.9 0.25 27 39 26 19 MAX UNITS V 0.4 V mA mA 0.5 1.1 2.1 ns 0.5 1.1 2.7 ns Dt VT = 1.5 V;CL=30 pF Cycle to Cycle jitter TCYC - TCYC at 66-100 MHz ; loaded outputs Absolute Jitter1 TJABS 10000 cycles; CL = 30 pF Skew1 Tsk VT = 1.5 V (Window) Output to Output 48 50 52 % ps Phase error1 Delay Input-Output 1 -75 Fall Time1 Tf VOH = 2.0 V, V OL = 0.8 V 1 Duty Cycle 1 1 Tpe DR1 VT = Vdd/2; CLKIN-FBIN VT = 1.5 V; PLL_EN = 0 Guaranteed by design, not 100% tested in production. 0722A—05/07/03 3 3.3 75 100 ps 100 ps 75 ps 3.7 ns ICSVF2510 Electrical Characteristics - Input & Supply TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-10% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Operating current Input Capacitance SYMBOL CONDITIONS VIH VIL I IH VIN = VDD IIL VIN = 0 V; IDD1 CIN1 MIN 2 VSS - 0.3 TYP 0.1 19 MAX UNITS V DD + 0.3 V 0.8 V 100 uA 50 uA CL = 0 pF; FIN @ 66MHz 170 Logic Inputs 4 mA pF 1 Guaranteed by design, not 100% tested in production. Timing requirements over recommended ranges of supply voltage and operating free-air temperature Symbol FOP Parameter Test Conditions Operating frequency Min. 20 Max. 200 Unit MHz Input clock 25 200 MHz frequency Input clock frequency duty 40 60 % cycle Stabilization time After power up 15 µs Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not applicable. FCLK 0722A—05/07/03 4 ICSVF2510 PARAMETER MEASUREMENT INFORMATION From Output Under Test 30 pF 500 Ω Figure 1. Load Circuit for Outputs Notes: Figure 2. Voltage Waveforms 1. CL includes probe and jig capacitance. Propagation Delay Times 2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 133 MHz, Z O = 5 0 Ω, Tr ≤ 1.2 ns, Tf ≤ 1.2 ns. 3. The outputs are measured one at a time with one transition per measurement. Figure 3. Phase Error and Skew Calculations 0722A—05/07/03 5 ICSVF2510 General Layout Precautions: An ICS2509C is used as an example. It is similar to the ICSVF2510. The same rules and methods apply. 1) Use copper flooded ground on the top signal layer under the clock buffer The area under U1 in figure 1 on the right is an example. Every ground pin goes to a ground via. The vias are not visible in figure 1. 2) Use power vias for power and ground. Vias 20 mil or larger in diameter have lower high frequency impedance. Vias for signals may be minimum drill size. 3) Make all power and ground traces are as wide as the via pad for lower inductance. 4) VAA for pin 23 has a low pass RC filter to decouple the digital and analog supplies. C9-12 may be replaced with a single low ESR (0.8 ohm or less) device with the same total capacitance. R2 may be replaced with a ferrite bead. The bead should have a DC resistance of at least 0.5 ohms. 1 ohm is better. It should have an impedance of at least 300 ohms at 100MHz. 600 ohms at 100MHz is better. 5) Notice that ground vias are never shared. 6) All VCC pins have a decoupling capacitor. Power is always routed from the plane connection via to the capacitor pad to the VCC pin on the clock buffer. 7) Component R1 is located at the clock source. 8) Component C1, if used, has the effect of adding delay. 9) Component C7 , if used, has the effect of subtracting delay. Delaying the FBIn clock will cause the output clocks to be earlier. A more effective method is to use the propagation time of a trace between FBOut and FBIn. Figure 1. Component Values: C1,C7= As necessary for delay adjust C[6:2]=.01uF C8,C13=0.1uF C[12:9]=4.7Uf R1=10 ohm. Locate at driver R2=10 ohm. 0722A—05/07/03 6 ICSVF2510 c N In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A -1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D SEE VARIATIONS E 6.40 BASIC E1 4.30 4.50 e 0.65 BASIC L 0.45 0.75 N SEE VARIATIONS α 0° 8° aaa -0.10 L E1 INDEX AREA E 1 2 α D A A2 In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 VARIATIONS A1 N -Ce SEATING PLANE b 24 D mm. MIN 7.70 D (inch) MAX 7.90 MIN .303 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 aaa C 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil) Ordering Information ICSVF2510yG-T Example: ICS XXXX y G - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0722A—05/07/03 7 MAX .311