X20C04
4K
512 x 8 Bit
Nonvolatile Static RAM
DESCRIPTION
• High reliability
—Endurance: 1,000,000 nonvolatile store
operations
—Retention: 100 years minimum
• Power-on recall
—EEPROM data automatically recalled into
SRAM upon power-up
• Lock out inadvertent store operations
• Low power CMOS
—Standby: 250µA
• Infinite EEPROM array recall, and RAM read and
write cycles
• Compatible with X2004
The Xicor X20C04 is a 512 x 8 NOVRAM featuring a
static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (EEPROM). The X20C04 is fabricated with advanced CMOS floating gate technology
to achieve low power and wide power-supply margin.
The X20C04 features the JEDEC approved pinout for
byte-wide memories, compatible with industry standard RAMs, ROMs, EPROMs, and EEPROMs.
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FEATURES
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The NOVRAM design allows data to be easily transferred
from RAM to EEPROM (store) and EEPROM to RAM
(recall). The store operation is completed in 5ms or less
and the recall operation is completed in 5µs or less.
512 x 8
SRAM
Array
E
Row
Select
EC
AL
L
EEPROM Array
ST
O
R
A3–A6
VCC Sense
R
bs
ol
BLOCK DIAGRAM
et
e
P
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
EEPROM, and a minimum 1,000,000 store operations
to the EEPROM. Data retention is specified to be
greater than 100 years.
O
CE
OE
WE
Control
Logic
NE
Column
Select
&
I/OS
A0–A2
A7–A8
I/O0–I/O7
REV 1.0 6/21/00
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Characteristics subject to change without notice.
1 of 15
X20C04
PIN CONFIGURATION
A4
6
23
NC
A3
7
X20C04 22
OE
A2
8
A1
9
A0
10
19
I/O7
I/O0
11
18
I/O6
I/O1
12
17
I/O5
I/O2
13
16
I/O4
VSS
14
15
I/O3
CE
A4
7
A3
8
Description
Address inputs
et
A0–A8
I/O0–I/O7
Data input/output
Write enable
CE
Chip enable
OE
Output enable
VSS
ol
WE
NC
No connect
NE
Nonvolatile enable
28
NC
27
NC
26
NC
9
A1
10
A0
11
NC
12
22
I/O7
I/O0
13
21
14 15 16 17 18 19 20
I/O6
25
OE
24
NC
23
CE
Output Enable (OE)
The Output Enable input controls the data output buffers and is used to initiate read and recall operations.
Output Enable LOW disables a store operation regardless of the state of CE, WE, or NE.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X20C04 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CE or OE is HIGH or when NE is LOW.
Write Enable (WE)
The Write Enable input controls the writing of data to
both the static RAM and stores to the EEPROM.
Ground
PIN DESCRIPTIONS
O
Addresses (A0–A8)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption is reduced.
REV 1.0 6/21/00
X20C04
(Top View)
A8
+5V
bs
VCC
e
PIN NAMES
Symbol
6
29
A2
P
20
NC
5
1 32 31 30
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21
A6
A5
2
t
NC
NC
24
3
I/O5
5
WE
A5
4
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A8
I/O4
25
I/O3
4
NC
NC
A6
NE
A7
26
NC
WE
3
NC
VCC
27
I/O2
VSS
28
2
A7
1
I/O1
NE
NC
VCC
LCC
PLCC
Plastic CERDIP
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls all accesses to
the EEPROM array (store and recall functions).
DEVICE OPERATION
The CE, OE, WE and NE inputs control the X20C04
operation. The X20C04 byte-wide NOVRAM uses a 2line control architecture to eliminate bus contention in a
system environment. The I/O bus will be in a high
impedance state when either OE or CE is HIGH, or
when NE is LOW.
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Characteristics subject to change without notice.
2 of 15
X20C04
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
t
INPUTS
e
P
Power-Up Recall
Upon power-up (VCC), the X20C04 performs an automatic array recall. When VCC minimum is reached, the
recall is initiated, regardless of the state of CE, OE,
WE and NE.
WAVEFORM
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Nonvolatile Operations
With NE LOW, recall operation is performed in the
same manner as RAM read operation. A recall operation causes the entire contents of the EEPROM to be
written into the RAM array. The time required for the
operation to complete is 5µs or less. A store operation
causes the entire contents of the RAM array to be
stored in the nonvolatile EEPROM. The time for the
operation to complete is 5ms or less.
SYMBOL TABLE
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RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE and OE to be LOW with WE and NE HIGH. A write
operation requires CE and WE to be LOW with NE
HIGH. There is no limit to the number of read or write
operations performed to the RAM portion of the
X20C04.
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Write Protection
The X20C04 has five write protect features that are
employed to protect the contents of both the nonvolatile memory and the RAM.
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– VCC Sense—All functions are inhibited when VCC is
3.5V.
– A RAM write is required before a Store Cycle is
initiated.
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– Write Inhibit—Holding either OE LOW, WE HIGH,
CE HIGH, or NE HIGH during power-up and powerdown will prevent an inadvertent store operation.
– Noise Protection—A combined WE, NE, OE and CE
pulse of less than 20ns will not initiate a Store Cycle.
O
– Noise Protection—A combined WE, NE, OE and CE
pulse of less than 20ns will not initiate a recall cycle.
REV 1.0 6/21/00
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Characteristics subject to change without notice.
3 of 15
X20C04
COMMENT
Temperature under bias ....................–65°C to +135°C
Storage temperature ........................–65°C to +150°C
Voltage on any pin with
respect to VSS ......................................... –1V to +7V
D.C. output current ............................................. 10mA
Lead temperature (soldering, 10 seconds......... 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any other conditions above those indicated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Min.
Max.
Supply Voltage
Limits
Commercial
0°C
+70°C
X20C04
5V ±10%
Industrial
–40°C
+85°C
Military
–55°C
+125°C
ro
Temperature
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Parameter
Min.
Max.
Unit
Test Conditions
VCC current (active)
100
mA
NE = WE = VIH, CE = OE = VIL, Address inputs =
0.4V/2.4V levels@ f = 5MHz. All I/Os = Open
ICC2
VCC current during store
10
mA
All inputs = VIH, All I/Os = open
ISB1
VCC standby current
10
mA
CE = VIH, All other inputs = VIH, All I/Os = open
ISB2
VCC standby current
250
µA
All inputs = VCC – 0.3V, All I/Os = open
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC, CE = VIH
e
lCC1
P
Symbol
(CMOS input)
et
(TTL input)
Input LOW voltage
–1
0.8
V
(1)
VIH
Input HIGH voltage
2
VCC + 0.5
V
VOL
Output LOW voltage
0.4
V
IOL = 2.1mA
VOH
Output HIGH voltage
V
IOH = –400µA
ol
(1)
bs
VIL
2.4
POWER-UP TIMING
Symbol
Power-up to RAM operation
(2)
Power-up to nonvolatile operation
tPUR
O
Parameter
(2)
tPUW
Max.
Unit
100
µs
5
ms
CAPACITANCE TA = +25°C, F = 1MHz, VCC = 5V
Symbol
(2)
(2)
CI/O
CIN
Test
Max.
Unit
Conditions
Input/output capacitance
10
pF
VI/O = 0V
Input capacitance
6
pF
VIN = 0V
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
REV 1.0 6/21/00
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Characteristics subject to change without notice.
4 of 15
X20C04
ENDURANCE AND DATA RETENTION
Min.
Unit
Endurance
100,000
Data changes per bit
Store cycles
1,000,000
Store cycles
Data retention
100
Years
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Parameter
MODE SELECTION
WE
NE
OE
Mode
I/O
Power
H
X
X
X
Not selected
Output high Z
Standby
L
H
H
L
Read RAM
Output data
Active
L
L
H
H
Write “1” RAM
Input data high
Active
L
L
H
H
Write “0” RAM
Input data low
Active
L
H
L
L
Array recall
L
L
L
H
Nonvolatile storing
L
H
H
H
Output disabled
L
L
L
Not allowed
L
H
L
H
No operation
e
EQUIVALENT A.C. LOAD CIRCUIT
et
5V
1.92KΩ
Active
Output high Z
Active
Output high Z
Active
Output high Z
Active
Output high Z
Active
A.C. CONDITIONS OF TEST
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input and output timing levels
1.5V
ol
Output
Output high Z
P
L
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CE
100pF
O
bs
1.37KΩ
REV 1.0 6/21/00
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Characteristics subject to change without notice.
5 of 15
X20C04
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Read Cycle Limits
Parameter
X20C04-20
X20C04-25
Min.
Min.
Min.
Max.
Unit
150
200
250
300
ns
tAA
Address access time
150
200
250
300
ns
tOE
Output enable access time
50
70
100
150
ns
(3)
tHZ
(3)
tOHZ
Output enable to output in low Z
0
0
0
0
ns
0
0
ns
Chip disable to output in high Z
80
100
100
100
ns
Output disable to output in high Z
80
100
100
100
ns
Output hold from address change
tOH
0
0
0
0
ns
(3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with
CL = 5pF from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
P
Note:
0
ro
tOLZ
0
ns
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Chip enable access time
Chip enable to output in low Z
300
Max.
Read cycle time
(3)
250
Min.
tCE
tLZ
200
Max.
tRC
(3)
150
Max.
X20C04
t
Symbol
X20C04-15
Read Cycle
e
tRC
et
Address
tCE
CE
OE
bs
VIH
ol
tOE
WE
tOHZ
tLZ
REV 1.0 6/21/00
tHZ
tOH
Data Valid
O
Data I/O
tOLZ
Data Valid
tAA
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Characteristics subject to change without notice.
6 of 15
X20C04
Write Cycle Limits
Symbol
Parameter
X20C04-15
X20C04-20
X20C04-25
Min.
Min.
Min.
Max.
Max.
Max.
X20C04
Min. Max.
Unit
Write cycle time
150
200
250
300
ns
tCW
Chip enable to end of write input
150
200
250
300
ns
ns
Write pulse width
tWR
Write recovery time
tDW
Data setup to end of write
tDH
Data hold time
(4)
Write enable to output in high Z
(4)
Output active from end of write
(4)
Output enable to output in high Z
tWZ
tOW
tOZ
Note:
0
0
100
120
0
0
100
120
0
0
80
0
200
ns
0
0
ns
150
200
ns
0
0
ns
100
5
5
80
100
5
100
5
100
(4)tWZ, tOW, and tOZ are periodically sampled and not 100% tested.
100
100
ns
ns
ns
P
WE Controlled Write Cycle
0
150
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Address setup time
ro
tAS
tWP
t
tWC
tWC
e
Address
et
OE
bs
WE
ol
CE
tAS
tCW
tWP
tWR
tOZ
tOW
Data Out
O
tDW
Data Valid
Data In
REV 1.0 6/21/00
tDH
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Characteristics subject to change without notice.
7 of 15
X20C04
CE Controlled Write Cycle
tWC
t
Address
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VIH
OE
tCW
CE
tWP
WE
tWZ
P
Data Out
tWR
ro
tAS
tDW
Symbol
e
et
STORE CYCLE LIMITS
Parameter
Store cycle time
tSP
store pulse width
ol
tSTC
tNHZ
Nonvolatile enable to output in
HIGH Z
tOEST
Output enable from end of store
X20C04-20
X20C04-25
Min.
Min.
Min.
Max.
5
100
Max.
5
120
80
Max.
X20C04
Min.
5
150
100
Max.
Unit
5
ms
200
100
ns
100
ns
10
10
10
ns
OE disable to store function
20
20
20
20
ns
NE setup time from WE
0
0
0
0
ns
(5) X20C04 VCC min. = 4.5V
The Store Pulse Width (tSP) is a minimum time that NE, WE and CE must be LOW simultaneously.
O
Note:
X20C04-15
10
bs
tNS
tDH
Data Valid
Data In
tSOE
tOW
REV 1.0 6/21/00
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Characteristics subject to change without notice.
8 of 15
X20C04
Store Timing
tSTC
t
tSP
NE
tOEST
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tSOE
OE
WE
ro
tNS
CE
tNHZ
P
Data I/O
Symbol
(6)
tRCP
tRWE
X20C04-25
Min.
Min.
Min.
Recall pulse width to initiate recall
WE setup time to NE
0.1
0
Max.
5
1
Max.
5
0.12
0
1
Max.
X20C04
Min.
5
0.15
0
1
0.2
Max.
Unit
5
µs
1
µs
0
ns
(6) The Recall Pulse Width (tRCP) is a minimum time that NE, OE and CE must be LOW simultaneously to insure data integrity, NE and CE.
O
bs
Note:
X20C04-20
Array recall cycle time
ol
tRCC
Parameter
VCC Min.(5)
X20C04-15
et
ARRAY RECALL CYCLE LIMITS
e
VCC
REV 1.0 6/21/00
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Characteristics subject to change without notice.
9 of 15
X20C04
Array Recall Cycle
tRCC
t
Address
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tRCP
NE
OE
tRWE
ro
WE
P
CE
O
bs
ol
et
e
Data I/O
REV 1.0 6/21/00
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Characteristics subject to change without notice.
10 of 15
X20C04
PACKAGING INFORMATION
t
28-Lead Hermetic, CerDIP, Package Code D28
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1.490 (37.85) Max.
ro
0.610 (15.49)
0.500 (12.70)
0.100 (2.54) Max.
et
0.150 (3.81) Min. 0.200 (5.08)
0.125 (3.18)
ol
0.110 (2.79)
0.090 (2.29)
Typ. 0.100 (2.54)
bs
0.232 (5.90) Max.
e
Seating
Plane
O
0.005 (0.127) Min.
P
Pin 1
0.060 (1.52)
0.015 (0.38)
0.023 (0.58)
0.014 (0.36)
0.065 (1.65)
0.038 (0.97)
Typ. 0.055 (1.40)
Typ. 0.018 (0.46)
0.620 (15.75)
0.590 (14.99)
Typ. 0.614 (15.60)
0°
15°
0.015 (0.38)
0.008 (0.20)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.0 6/21/00
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Characteristics subject to change without notice.
11 of 15
X20C04
PACKAGING INFORMATION
t
28-Lead Plastic, PDIP, Package Code P28
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1.470 (37.34)
1.400 (35.56)
0.557 (14.15)
0.510 (12.95)
Pin 1
0.022 (0.56)
0.014 (0.36)
0.625 (15.88)
0.590 (14.99)
bs
ol
0.065 (1.65)
0.040 (1.02)
0°
15°
Typ. 0.010 (0.25)
O
0.030 (0.76)
0.015 (0.38)
et
0.160 (4.06)
0.120 (3.05)
0.110 (2.79)
0.090 (2.29)
0.160 (4.06)
0.125 (3.17)
e
Seating
Plane
REV 1.0 6/21/00
0.085 (2.16)
0.040 (1.02)
P
1.300 (33.02)
Ref.
ro
Pin 1 Index
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
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Characteristics subject to change without notice.
12 of 15
X20C04
PACKAGING INFORMATION
t
32-Pad Hermetic, LCC, Package Code E32
0.150 (3.81) BSC
0.015 (0.38)
0.003 (0.08)
0.020 (0.51) x 45° Ref.
0.095 (2.41)
0.075 (1.91)
Pin 1
ro
0.022 (0.56)
DIA.
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
TYP. (4) PLCS.
0.200 (5.08)
BSC
P
0.015 (0.38)
Min.
0.040 (1.02) x 45° Ref.
Typ. (3) Plcs.
0.050 (1.27) BSC
et
0.458 (11.63)
0.442 (11.22)
e
0.028 (0.71)
0.022 (0.56)
(32) Plcs.
0.120 (3.05)
0.060 (1.52)
bs
ol
0.458 (11.63)
––
O
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0.300 (7.62)
BSC
0.560 (14.22)
0.540 (13.71)
0.558 (14.17)
––
0.088 (2.24)
0.050 (1.27)
0.400 (10.16)
BSC
Pin 1 Index Corner
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
REV 1.0 6/21/00
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Characteristics subject to change without notice.
13 of 15
X20C04
PACKAGING INFORMATION
0.420 (10.67)
0.030" Typical
32 Places
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0.050"
Typical
0.050"
Typical
0.510"
Typical
0.400"
ro
0.050 (1.27) Typ.
0.300"
Ref.
0.410"
FOOTPRINT
0.495 (12.57)
0.485 (12.32)
Typ. 0.490 (12.45)
P
ol
et
0.453 (11.51)
0.447 (11.35)
Typ. 0.450 (11.43)
0.300 (7.62)
Ref.
e
0.045 (1.14) x 45°
0.021 (0.53)
0.013 (0.33)
Typ. 0.017 (0.43)
Seating Plane
±0.004 Lead
CO – Planarity
—
0.015 (0.38)
0.095 (2.41)
0.060 (1.52)
0.140 (3.56)
0.100 (2.45)
Typ. 0.136 (3.45)
0.048 (1.22)
0.042 (1.07)
0.595 (15.11)
0.585 (14.86)
Typ. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
Typ. 0.550 (13.97)
0.400
(10.16)Ref.
3° Typ.
O
bs
Pin 1
t
32-Lead Plastic, PLCC, Package Code J32
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
REV 1.0 6/21/00
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Characteristics subject to change without notice.
14 of 15
X20C04
Ordering Information
X
X
-X
Access Time
-15 = 150ns
-20 = 200ns
-25 = 250ns
Blank = 300ns
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Device
t
X20C04
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Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = Mil. STD-833
LIMITED WARRANTY
ol
et
e
P
Package
D = 28-Lead Cerdip
P = 28-Lead Plastic DIP
E = 32-Pad Ceramic LCC
J = 32-Lead PLCC
©Xicor, Inc. 2001 Patents Pending
bs
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS AND TRADEMARKS
O
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
REV 1.0 6/21/00
www.xicor.com
Characteristics subject to change without notice.
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