X24C44S

APPLICATION NOTE A V A I LA B L E AN3 • AN7 • AN8 • AN15• AN16 • AN25 • AN29 • AN30 • AN35 • AN36 • AN39 • AN56 • AN69 X24C44 256 Bit 16 x 16 Bit Serial Nonvolatile Static RAM DESCRIPTION • • • • The Xicor X24C44 is a serial 256 bit NOVRAM featuring a static RAM configured 16 x 16, overlaid bit-by-bit with a nonvolatile EEPROM array. The X24C44 is fabricated with Xicor’s Advanced CMOS Floating Gate technology. O bs CE (1) DI (3) SK (2) REV 1.0 6/22/00 du c ro E R AL L ST Column Decode EC Static RAM 256-Bit Row Decode Instruction Register Instruction Decode Nonvolatile EEPROM O ol et BLOCK DIAGRAM R • • Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or RECALLs from EEPROM and a minimum 1,000,000 STORE operations. Inherent data retention is specified to be greater than 100 years. P • • • The Xicor NOVRAM design allows data to be transferred between the two memory arrays by means of software commands or external hardware inputs. A STORE operation (RAM data to EEPROM) is completed in 5ms or less and a RECALL operation (EEPROM data to RAM) is completed in 2µs or less. e • Advanced CMOS version of Xicor’s X2444 16 x 16 organization Single 5V supply Ideal for use with single chip microcomputers —Static timing —Minimum I/O interface —Serial port compatible (COPS™, 8051) —Easily interfaced to microcontroller ports Software and hardware control of nonvolatile functions Auto RECALL on power-up TTL and CMOS compatible Low power dissipation —Active current: 10mA maximum —Standby current: 50µA maximum 8-lead PDIP, Cerdip, and 8-lead SOIC packages High reliability —STORE cycles: 1,000,000 —Data retention: 100 years t FEATURES Control Logic RECALL (6) STORE (7) DO (4) 4-Bit Counter www.xicor.com Characteristics subject to change without notice. 1 of 14 X24C44 PIN NAMES Symbol Serial Clock (SK) The Serial Clock input is used to clock all data into and out of the device. Description CE Chip Enable SK Serial Clock DI Serial Data In DO Serial Data Out RECALL STORE VCC VSS t Chip Enable (CE) The Chip Enable input must be HIGH to enable all read/write operations. CE must remain HIGH following a Read or Write command until the data transfer is complete. CE LOW places the X24C44 in the low power standby mode and resets the instruction register. Therefore, CE must be brought LOW after the completion of an operation in order to reset the instruction register in preparation for the next command. du c PIN DESCRIPTIONS RECALL Input STORE Input +5V Ground DEVICE OPERATION Table 1. contains a list of the instructions and their operation codes. The most significant bit (MSB) of all instructions is a logic one (HIGH), bits 6 through 3 are either RAM address bits (A) or don’t cares (X) and bits 2 through 0 are the operation codes. The X24C44 requires the instruction to be shifted in with the MSB first. e P Data Out (DO) Data Out is the serial data output. It is in the high impedance state except during data output cycles in response to a READ instruction. ro The X24C44 contains an 8-bit instruction register. It is accessed via the DI input, with data being clocked in on the rising edge of SK. CE must be HIGH during the entire data transfer operation. Data In (DI) Data In is the serial data input. STORE et STORE LOW will initiate an internal transfer of data from RAM to the EEPROM array. RECALL ol RECALL LOW will initiate an internal transfer of data from EEPROM to the RAM array. bs PIN CONFIGURATION After CE is HIGH, the X24C44 will not begin to interpret the data stream until a logic “1” has been shifted in on DI. Therefore, CE may be brought HIGH with SK running and DI LOW. DI must then go HIGH to indicate the start condition of an instruction before the X24C44 will begin any action. In addition, the SK clock is totally static. The user can completely stop the clock and data shifting will be stopped. Restarting the clock will resume shifting of data. O PDIP/CERDIP/SOIC CE 1 SK 2 DI 3 DO 4 REV 1.0 6/22/00 X24C44 8 VCC 7 STORE 6 RECALL 5 VSS RCL and RECALL Either a software RCL instruction or a LOW on the RECALL input will initiate a transfer of EEPROM data into RAM. This software or hardware RECALL operation sets an internal “previous recall” latch. This latch is reset upon power-up and must be intentionally set by the user to enable any write or STORE operations. Although a RECALL operation is performed upon power-up, the previous RECALL latch is not set by this operation. www.xicor.com Characteristics subject to change without notice. 2 of 14 X24C44 If CE is kept HIGH for more than 24 SK clock cycles (8-bit instruction plus 16-bit data), the data already shifted-in will be overwritten. WRDS and WREN Internally the X24C44 contains a “write enable” latch. This latch must be set for either writes to the RAM or store operations to the EEPROM. The WREN instruction sets the latch and the WRDS instruction resets the latch, disabling both RAM writes and EEPROM stores, effectively protecting the nonvolatile data from corruption. The write enable latch is automatically reset on power-up. t READ du c The READ instruction contains the 4-bit address of the word to be accessed. Unlike the other six instructions, I0 of the instruction word is a “don’t care”. This provides two advantages. In a design that ties both DI and DO together, the absence of an eighth bit in the instruction allows the host time to convert an I/O line from an output to an input. Secondly, it allows for valid data output during the ninth SK clock cycle. STO and STORE Either the software STO instruction or a LOW on the STORE input will initiate a transfer of data from RAM to EEPROM. In order to safeguard against unwanted store operations, the following conditions must be true: D0, the first bit output during a read operation, is truncated. That is, it is internally clocked by the falling edge of the eighth SK clock; whereas, all succeeding bits are clocked by the rising edge of SK (refer to Read Cycle Diagram). ro – STO instruction issued or STORE input is LOW. – The internal “write enable” latch must be set (WREN instruction issued). – The “previous recall” latch must be set (either a software or hardware recall operation). P LOW POWER MODE Once the store cycle is initiated, all other device functions are inhibited. Upon completion of the store cycle, the write enable latch is reset. Refer to Figure 4 for a state diagram description of enabling/disabling conditions for store operations. e When CE is LOW, non-critical internal devices are powered-down, placing the device in the standby power mode, thereby minimizing power consumption. bs ol et WRITE The WRITE instruction contains the 4-bit address of the word to be written. The write instruction is immediately followed by the 16-bit word to be written. CE must remain HIGH during the entire operation. CE must go LOW before the next rising edge of SK. If CE is brought LOW prematurely (after the instruction but before 16 bits of data are transferred), the instruction register will be reset and the data that was shifted-in will be written to RAM. SLEEP Because the X24C44 is a low power CMOS device, the SLEEP instruction implemented on the first generation NMOS device has been deleted. For systems converting from the X2444 to the X24C44 the software need not be changed; the instruction will be ignored. Table 1. Instruction Set Format, I2 I1 I0 WRDS (Figure 3) 1XXXX000 Reset Write Enable Latch (Disables Writes and STOREs) STO (Figure 3) 1XXXX001 STORE RAM Data in EEPROM Reserved 1XXXX010 N/A WRITE (Figure 2) 1AAAA011 Write Data into RAM Address AAAA WREN (Figure 3) 1XXXX100 Set Write Enable Latch (Enables Writes and STOREs) RCL (Figure 3) 1XXXX101 Recall EEPROM Data into RAM READ (Figure 1) 1AAAA11X Read Data from RAM Address AAAA O Instruction Operation Notes: X = Don't Care A = Address REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 3 of 14 X24C44 WRITE PROTECTION Power-Down Data Protection Because the X24C44 is a 5V only nonvolatile memory device it may be susceptible to inadvertent STOREs to the EEPROM array during power-down cycles. Powerup cycles are not a problem because the “previous recall” latch and “write enable” latch are reset, preventing any possible corruption of EEPROM data. The X24C44 provides two software write protection mechanisms to prevent inadvertent stores of unknown data. du c t Power-Up Condition Upon power-up the “write enable” latch is in the reset state, disabling any store operation. Software Power-Down Protection If the STORE and RECALL pins are tied to VCC through a pull-up resistor and only software operations are performed to initiate stores, there is little likelihood of an inadvertent store. However, if these two lines are under microprocessor control, positive action should be employed to negate the possibility of these control lines bouncing and generating an unwanted store. The safest method is to issue the WRDS command after a write sequence and also following store operations. Note: an internal store may take up to 5ms; therefore, the host microprocessor should delay 5ms after initiating the store prior to issuing the WRDS command. ro Unknown Data Store The “previous recall” latch must be set after power-up. It may be set only by performing a software or hardware recall operation, which assures that data in all RAM locations is valid. SYSTEM CONSIDERATIONS et e P Power-Up Recall The X24C44 performs a power-up recall that transfers the EEPROM contents to the RAM array. Although the data may be read from the RAM array, this recall does not set the “previous recall” latch. During this power-up recall operation, all commands are ignored. Therefore, the host should delay any operations with the X24C44 a minimum of tPUR after VCC is stable. bs CE O SK DI Holding either RECALL LOW, CE LOW or STORE HIGH during power-down will prevent an inadvertent store. ol Figure 1. RAM Read Hardware Power-Down Protection (when the “write enable” latch and “previous recall” latch are not in the reset state): 1 2 3 4 5 6 7 8 1 A A A A 1 1 X* 10 9 11 12 22 23 24 HIGH Z DO D0 D1 D2 D3 D13 D14 D15 D0 *Bit 8 of Read Instructions is Don’t Care REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 4 of 14 X24C44 Figure 2. RAM Write 1 2 3 4 5 6 7 8 9 10 DI 1 A A A A 0 1 1 D0 D1 SK 1 2 3 4 DI 1 X X 22 23 24 D2 D12 D13 D14 D15 6 7 8 I1 I0 P 5 12 ro Figure 3. Non-Data Operations CE 11 du c SK t CE X I2 e X et Figure 4. X24C44 State Diagram ol Power On Power-up Recall O bs RAM Read Enabled RAM Read Enabled RAM Read RCL Command or Recall RAM Read WREN Command Sto or Wrds Cmd or Store RAM Read & Write RAM Read Or Write Store Enabled REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 5 of 14 X24C44 COMMENT Temperature under bias ................... –65°C to +135°C Storage Temperature........................ –65°C to +150°C Voltage on any pin with respect to VSS .........................................–1V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds)........ 300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. du c t ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Min. Max. Supply Voltage Limits Commercial 0°C +70°C X24C44 5V ±10% Industrial –40°C +85°C Military –55°C +125°C ro Temperature D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Symbol P Limits Parameter Min. Max. Unit Test Conditions 10 mA SK = 0.4V/2.4V levels @ 1MHz, DO = open, all other inputs = VIH VCC supply current (TTL inputs) ISB1 VCC standby current (TTL inputs) 1 mA DO = open, CE = VIL All other inputs = VIH ISB2 VCC standby current (CMOS inputs) 50 µA DO = open, CE = VSS All other inputs = VCC – 0.3V 10 µA VIN = VSS to VCC VOUT = VSS to VCC et e lCC ILI Input load current ILO Output leakage current Input LOW voltage VIH(1) Input HIGH voltage VOL Output LOW voltage VOH Output HIGH voltage ol VlL(1) 10 µA –1 0.8 V 2 VCC + 1 V 0.4 V IOL = 4.2mA V IOH = –2mA bs 2.4 O ENDURANCE AND DATA RETENTION Parameter Min. Unit Endurance 100,000 Data changes per bit Store cycles 1,000,000 Store cycles Data retention 100 Years CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol (2) COUT CIN(2) Parameter Max. Unit Test Conditions Output capacitance 8 pF VOUT = 0V Input capacitance 6 pF VIN = 0V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 6 of 14 X24C44 EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST Input pulse levels 5V Input rise and fall times 10ns Input and output timing levels 1.5V t 919Ω 0V to 3V 497Ω du c Output 100pF ro A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Read and Write Cycle Limits (3) Parameter SK frequency tSKH SK positive pulse width tSKL SK negative pulse width tDS Data setup time tDH Data hold time tPD1 SK to data bit 0 valid tPD SK to data valid et e FSK Min. P Symbol Unit 1 MHz 400 ns 400 ns 400 ns 80 ns Chip enable to output high Z tZ Max. 375 ns 375 ns 1 µs Chip enable setup 800 ns tCEH Chip enable hold 350 ns 800 ns tCDS ol tCES Chip deselect POWER-UP TIMING bs Symbol Parameter (4) Power-up to read operation (4) power-up to write or store operation tPUR tPUW Max. Unit 200 µs 5 ms O Notes: (3) SK rise and fall times must be less than 50ns. (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 7 of 14 X24C44 Write Cycle 1/F SK SK tSKL x 1 2 n tCEH tCES CE tDS tDH Read Cycle SK CYCLE # 6 7 8 9 10 n P SK tCDS ro DI t tSKH du c SK CYCLE # VIH I1 tPD Don’t Care tPD1 High Z tZ D0 D1 Dn High Z O bs DO I2 ol DI et e CE REV 1.0 6/22/00 www.xicor.com Characteristics subject to change without notice. 8 of 14 X24C44 NONVOLATILE OPERATIONS STORE RECALL Software Instruction Write Enable Latch State Previous Recall Latch State Hardware recall 1 0 NOP(5) X X Software recall 1 1 RCL X X 0 1 Software store 1 1 STO ARRAY RECALL LIMITS Symbol Parameter Min. Recall cycle time width(6) tRCP Recall pulse tRCZ Recall to output in high Z SET SET SET Max. Unit 2 µs 500 ns 500 ro tRCC SET NOP du c Hardware store (5) t Operation ns P Notes: (5) NOP designates when the X24C44 is not currently executing an instruction. (6) RECALL rise time must be