X28C512JIZ-12

DATASHEET X28C512, X28C513 FN8106 Rev 2.00 June 7, 2006 5V, Byte Alterable EEPROM The X28C512, X28C513 are 64K x 8 EEPROM, fabricated with Intersil’s proprietary, high performance, floating gate CMOS technology. Like all Intersil programmable nonvolatile memories, the X28C512, X28C513 are 5V only devices. The X28C512, X28C513 feature the JEDEC approved pin out for byte wide memories, compatible with industry standard EPROMS. The X28C512, X28C513 support a 128-byte page write operation, effectively providing a 39µs/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. The X28C512, X28C513 also feature DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28C512, X28C513 support the software data protection option. Features • Access Time: 90ns • Simple Byte and Page Write - Single 5V supply • No external high voltages or VPP control circuits - Self-timed • No erase before write • No complex programming algorithms • No overerase problem • Low Power CMOS - Active: 50mA - Standby: 500µA • Software Data Protection - Protects data against system level inadvertent writes • High Speed Page Write Capability • Highly Reliable Direct Write™ Cell - Endurance: 100,000 write cycles - Data retention: 100 years - Early end of write detection - DATA polling - Toggle bit polling • Two PLCC and LCC Pinouts - X28C512 • X28C010 EPROM pin compatible - X28C513 • Compatible with lower density EEPROMs • Pb-Free Plus Anneal Available (RoHS Compliant) FN8106 Rev 2.00 June 7, 2006 Page 1 of 21 X28C512, X28C513 Block Diagram A7-A15 X Buffers Latches and Decoder A0-A6 Y Buffers Latches and Decoder 512Kbit EEPROM Array I/O Buffers and Latches I/O0-I/O7 CE OE WE Data Inputs/Outputs Control Logic and Timing VCC VSS Ordering Information PART NUMBER X28C512D X28C512DM X28C512J X28C513EM PART MARKING ACCESS TIME (ns) X28C512D - TEMP RANGE (°C) PACKAGE 0 to +70 32 Ld CERDIP X28C512DM -55 to +125 32 Ld CERDIP X28C512J 0 to +70 X28C513EM X28C512D-12 X28C512D-12 X28C512DI-12 -55 to +125 32 Ld LCC 0 to +70 32 Ld CERDIP X28C512DI-12 -40 to +85 32 Ld CERDIP X28C512DMB-12 X28C512DMB-12 Mil-STD-883 32 Ld CERDIP X28C512FMB-12 X28C512FMB-12 Mil-STD-883 32 Ld Flat Pack X28C512J-12 0 to +70 32 Ld PLCC X28C512J-12 Z 0 to +70 32 Ld PLCC (Pb-free) X28C512JI-12 -40 to +85 32 Ld PLCC X28C512JIZ-12* (See Note) X28C512JI-12 Z -40 to +85 32 Ld PLCC (Pb-free) X28C512JM-12 X28C512JM-12 -55 to +125 32 Ld PLCC X28C512KM-12 X28C512KM-12 -55 to +125 36 Ld CPGA X28C512PI-12 X28C512PI-12 -40 to +85 32 Ld PDIP X28C512RMB-12 Mil-STD-883 32 Ld Flat Pack X28C512J-12* X28C512JZ-12* (See Note) X28C512JI-12 X28C512RMB-12 X28C513EM-12 120 32 Ld PLCC X28C513EM-12 -55 to +125 32 Ld LCC X28C513EMB-12 Mil-STD-883 32 Ld LCC X28C513J-12 0 to +70 32 Ld PLCC X28C513J-12 Z 0 to +70 32 Ld PLCC (Pb-free) X28C513JI-12 -40 to +85 32 Ld PLCC X28C513JIZ-12* (Note) X28C513JI-12 Z -40 to +85 32 Ld PLCC (Pb-free) X28C513JM-12 X28C513JM-12 -55 to +125 32 Ld PLCC X28C513EMB-12 X28C513J-12* X28C513JZ-12* (Note) X28C513JI-12* FN8106 Rev 2.00 June 7, 2006 Page 2 of 21 X28C512, X28C513 Ordering Information (Continued) PART MARKING ACCESS TIME (ns) X28C512D-15 X28C512D-15 150 0 to +70 32 Ld CERDIP X28C512DI-15 X28C512DI-15 -40 to +85 32 Ld CERDIP X28C512DMB-15 Mil-STD-883 32 Ld CERDIP PART NUMBER X28C512DMB-15 X28C512J-15* X28C512JZ-15* (See Note) X28C512JI-15* TEMP RANGE (°C) PACKAGE X28C512J-15 0 to +70 32 Ld PLCC X28C512J-15 Z 0 to +70 32 Ld PLCC (Pb-free) X28C512JI-15 -40 to +85 32 Ld PLCC X28C512JIZ-15* (See Note) X28C512JI-15 Z -40 to +85 32 Ld PLCC (Pb-free) X28C512JM-15 X28C512JM-15 -55 to +125 32 Ld PLCC X28C513EM-15 X28C513EM-15 -55 to +125 32 Ld LCC X28C513EMB-15 Mil-STD-883 32 Ld LCC X28C513J-15 0 to +70 32 Ld PLCC X28C513J-15 Z 0 to +70 32 Ld PLCC (Pb-free) X28C513EMB-15 X28C513J-15* X28C513JZ-15* (Note) X28C513JI-15 X28C513JI-15 -40 to +85 32 Ld PLCC X28C513JIZ-15* (Note) X28C513JI-15 Z -40 to +85 32 Ld PLCC (Pb-free) X28C513JM-15 X28C513JM-15 -55 to +125 32 Ld PLCC Mil-STD-883 32 Ld CERDIP X28C512DMB-20 X28C512DMB-20 200 X28C512JM-20 X28C512JM-20 -55 to +125 32 Ld PLCC X28C512KI-20 X28C512KI-20 -40 to +85 36 Ld CPGA X28C512KM-20 X28C512KM-20 -55 to +125 36 Ld CPGA X28C513EI-20 X28C513EI-20 -40 to +85 32 Ld LCC X28C513EM-20 X28C513EM-20 -55 to +125 32 Ld LCC X28C513EMB-20 Mil-STD-883 32 Ld LCC X28C513EMB-20 X28C513J-20T1 X28C513J-20 X28C512EM-25 X28C512EM-25 X28C512JM-25 X28C512JM-25 X28C512KM-25 X28C512KMB-25 X28C513EM-25 X28C513EMB-25 0 to +70 250 32 Ld PLCC Tape and Reel -55 to +125 32 Ld LCC -55 to +125 32 Ld PLCC X28C512KM-25 -55 to +125 36 Ld CPGA X28C512KMB-25 Mil-STD-883 36 Ld CPGA X28C513EM-25 -55 to +125 32 Ld LCC X28C513EMB-25 Mil-STD-883 32 Ld LCC *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN8106 Rev 2.00 June 7, 2006 Page 3 of 21 X28C512, X28C513 Pinouts 30 NC 4 29 A14 A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 X28C512 11 22 CE A0 12 21 I/O5 I/O0 13 20 I/O4 I/O1 14 19 I/O3 I/O2 15 18 I/O2 VSS 16 17 I/O1 A2 12 A3 11 A4 10 9 A6 8 7 6 A5 Bottom View A7 NC A15 A12 2 5 NC 4 NC 3 VCC NC CE 24 OE A10 25 26 A11 27 A9 28 A8 29 A13 30 NC 36 34 32 NC 1 WE 35 NC 33 A2 A1 A0 10 11 I/O0 A14 31 A6 A5 A4 54 3 2 A3 A2 8 9 A1 A0 NC 10 11 I/O0 Pin Descriptions Addresses (A0-A15) 25 24 23 12 22 13 15 16 17 18 19 20 21 14 1 6 7 30 32 31 29 28 X28C513 (Top View) OE A10 CE I/O7 27 26 25 24 23 A8 A9 A11 NC OE A10 CE I/O7 12 22 13 15 16 17 18 19 20 I/O6 21 14 I/O1 I/O2 VSS A1 I/O 4 I/O 1 VSS I/O 7 20 16 18 23 27 26 I/O6 3 A0 14 X28C512 (Top View) I/O5 A15 A12 A1 13 8 9 I/O3 I/O4 I/O5 WE A4 A3 A14 A13 A8 A9 A11 A15 VCC WE A13 VCC 31 I/O 6 22 30 32 31 29 1 28 NC I/O3 I/O4 32 2 I/O 5 I/O 3 21 19 6 7 NC A12 1 NC I/O 2 17 A6 A5 A7 NC I/O0 15 54 3 2 I/O1 I/O2 VSS PGA A7 A12 A14 Plastic DIP CERDIP FLAT Pack SOIC (R) A15 NC NC VCC WE PLCC/LCC Pin Names The Address inputs select an 8-bit memory location during a read or write operation. SYMBOL DESCRIPTION A0-A15 Address Inputs Chip Enable (CE) I/O0-I/O7 Data Input/Output The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. WE Write Enable CE Chip Enable Output Enable (OE) OE Output Enable The Output Enable input controls the data output buffers and is used to initiate read operations. VCC +5V VSS Ground Data In/Data Out (I/O0-I/O7) NC No Connect Data is written to or read from the X28C512, X28C513 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28C512, X28C513. FN8106 Rev 2.00 June 7, 2006 Page 4 of 21 X28C512, X28C513 Device Operation DATA Polling (I/O7) Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C512, X28C513 support both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. Page Write Operation The X28C512, X28C513 feature DATA polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C512, X28C513, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Toggle Bit (I/O6) The X28C512, X28C513 also provide another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete, the toggling will cease, and the device will be accessible for additional read or write operations. The page write feature of the X28C512, X28C513 allows the entire memory to be written in 2.5 seconds. Page write allows two to one hundred twenty-eight bytes of data to be consecutively written to the X28C512, X28C513, prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A15) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twenty-seven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively, the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100µs. Write Operation Status Bits The X28C512, X28C513 provide the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. I/O DP TB 5 4 3 2 1 0 Reserved Toggle Bit DATA Polling FIGURE 1. STATUS BIT ASSIGNMENT FN8106 Rev 2.00 June 7, 2006 Page 5 of 21 X28C512, X28C513 DATA Polling I/O7 WE Last Write CE OE VIH VOH HIGH Z I/O7 VOL A0-A15 An An An X28C512, X28C513 Ready An An An An FIGURE 2A. DATA POLLING BUS SEQUENCE DATA Polling can effectively halve the time for writing to the X28C512, X28C513. The timing diagram in Figure 2A illustrates the sequence of events on the bus. The software flow diagram in Figure 2B illustrates one method of implementing the routine. Write Data No Writes Complete? Yes Save Last Data and Address Read Last Address IO7 Compare? No Yes Ready FIGURE 2B. DATA POLLING SOFTWARE FLOW FN8106 Rev 2.00 June 7, 2006 Page 6 of 21 X28C512, X28C513 The Toggle Bit I/O6 Last WE Write CE OE VOH I/O6 * HIGH Z VOL * X28C512, X28C513 Ready * Beginning and ending state of I/O6 will vary. FIGURE 3A. TOGGLE BIT BUS SEQUENCE Hardware Data Protection The X28C512, X28C513 provide three hardware features that protect nonvolatile data from inadvertent writes. Last Write - Noise Protection—A WE pulse typically less than 10ns will not initiate a write cycle. - Default VCC Sense—All write functions are inhibited when VCC is 3.6V. - Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during powerup and power-down, maintaining data integrity. Write cycle timing specifications must be observed concurrently. Load Accum From Addr N Compare Accum with Addr N Compare Ok? Software Data Protection No Yes X28C512 Ready FIGURE 3B. TOGGLE BIT SOFTWARE FLOW The Toggle Bit can eliminate the chore of saving and fetching the last address and data in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28C512, X28C513 memories that are frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 3A illustrates the sequence of events on the bus. The software flow diagram in Figure 3B illustrates a method for polling the Toggle Bit. FN8106 Rev 2.00 June 7, 2006 The X28C512, X28C513 offer a software controlled data protection feature. The X28C512, X28C513 are shipped from Intersil with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. The X28C512, X28C513 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the X28C512, X28C513 are also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. Note: The data in the three-byte enable sequence is not written to the memory array. Page 7 of 21 X28C512, X28C513 Software Data Protection VCC (VCC) 0V Data Addr AAA 5555 55 2AAA A0 5555 Writes ok tWC Write Protected CE  tBLC MAX WE Byte or Page Note: All other timings and control pins are per page write timing requirements FIGURE 4A. TIMING SEQUENCE—SOFTWARE DATA PROTECT ENABLE SEQUENCE FOLLOWED BY BYTE OR PAGE WRITE Software Algorithm Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figures 4A and 4B for the sequence. The three byte sequence opens the page write window, enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. Write Data AA to Address 5555 Write Data 55 to Address 2AAA Regardless of whether the device has previously been protected or not, once the software data protected algorithm is used and data has been written, the X28C512, X28C513 will automatically disable further writes, unless another command is issued to cancel it. If no further commands are issued the X28C512, X28C513 will be write-protected during power-down and after any subsequent power-up. The state of A15 while executing the algorithm is “don’t care”. Write Data 80 to Address 5555 Write Data XX to any Address Note: Once initiated, the sequence of write operations should not be interrupted. Optional Byte/Page Load Operation Write Last Byte to Last Address After tWC Re-Enters Data Protected State FIGURE 4B. WRITE SEQUENCE FOR SOFTWARE DATA PROTECTION FN8106 Rev 2.00 June 7, 2006 Page 8 of 21 X28C512, X28C513 Resetting Software Data Protection VCC Data Addr AAA 5555 55 2AAA 80 5555 AA 5555 55 2AAA 20 5555  tWC Standard Operating Mode CE WE Note: All other timings and control pins are per page write timing requirements FIGURE 5A. Reset Software Data Protection Timing Sequence System Considerations Write Data AA to Address 5555 Write Data 55 to Address 2AAA Write Data A0 to Address 5555 Write Data AA to Address 5555 Write Data 55 to Address 2AAA Write Data 20 to Address 5555 FIGURE 5B. SOFTWARE SEQUENCE TO DEACTIVATE SOFTWARE DATA PROTECTION In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28C512, X28C513 will be in standard operating mode. Because the X28C512, X28C513 are frequently used in large memory arrays, it is provided with a two-line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit, it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is/are outputting data on the bus. Because the X28C512, X28C513 have two power modes, (standby and active), proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7µF electrolytic bulk capacitor be placed between VCC and VSS for each 8 devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. Note: Once initiated, the sequence of write operations should not be interrupted. FN8106 Rev 2.00 June 7, 2006 Page 9 of 21 X28C512, X28C513 Active Supply Current vs Ambient Temperature 14 ICC (RD) by Temperature Over Frequency 70 VCC = 5V 60 12 -55°C +25°C +125°C 50 11 ICC (mA) ICC (mA) 13 5.0 VCC 10 40 30 9 8 -55 -10 +35 +80 +125 Ambient Temperature (°C) 20 10 0 Standby Supply Current vs Ambient Temperature 0.24 3 6 9 12 15 Frequency (MHz) VCC = 5V 0.22 ISB (mA) 0.2 0.18 0.16 0.14 0.12 0.1 -55 -10 +35 +80 +125 Ambient Temperature (°C) FN8106 Rev 2.00 June 7, 2006 Page 10 of 21 X28C512, X28C513 Absolute Maximum Ratings Recommended Operating Conditions Temperature under bias X28C512, X28C513 . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C X28C512I/513I . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C X28C512M/513M . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage on any pin with respect to VSS . . . . . . . . . . . . . . -1V to +7V D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300°C Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C Supply Voltage Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10% CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Specifications SYMBOL Over recommended operating conditions, unless otherwise specified. PARAMETER TEST CONDITIONS MIN MAX UNIT ICC VCC current (active) (TTL inputs) CE = OE = VIL, WE = VIH, All I/O’s = open, address inputs = 0.4V/2.4V Levels @ f = 5MHz 50 mA ISB1 VCC current (standby) (TTL inputs) CE = VIH, OE = VIL, All I/O’s = open, other inputs = VIH 3 mA ISB2 VCC current (standby) (CMOS inputs) CE = VCC - 0.3V, OE = VIL, All I/O’s = Open, Other Inputs = VIH 500 µA ILI Input leakage current VIN = VSS to VCC 10 µA ILO Output leakage current VOUT = VSS to VCC, CE = VIH 10 µA VlL (Note 1) Input LOW voltage -1 0.8 V VIH (Note 1) Input HIGH voltage 2 VCC + 1 V VOL Output LOW voltage IOL = 2.1mA 0.4 V VOH Output HIGH voltage IOH = -400µA 2.4 V NOTE: 1. VIL min. and VIH max. are for reference only and are not tested. Power-Up Timing SYMBOL PARAMETER MAX UNIT tPUR (Note 2) Power-up to read operation 100 µs tPUW (Note 2) Power-up to write operation 5 ms Capacitance TA = +25°C, f = 1MHz, VCC = 5V SYMBOL PARAMETER TEST CONDITIONS MAX UNIT CI/O (Note 2) Input/output capacitance VI/O = 0V 10 pF CIN (Note 2) Input capacitance VIN = 0V 10 pF Endurance and Data Retention PARAMETER MIN MAX UNIT Endurance 10,000 Cycles per byte Endurance 100,000 Cycles per page Data retention 100 Years NOTE: 2. This parameter is periodically sampled and not 100% tested. FN8106 Rev 2.00 June 7, 2006 Page 11 of 21 X28C512, X28C513 Equivalent A.C. Load Circuit A.C. Conditions of Test Input pulse levels 0V to 3V Input rise and fall times 10ns Input and output timing levels 1.5V 5V 1.92k Mode Selection Output CE OE WE MODE I/O POWER L L H Read DOUT Active L H L Write DIN Active H X X Standby and write inhibit High Z Standby X L X Write inhibit — — X X H Write inhibit — — FN8106 Rev 2.00 June 7, 2006 1.37K 100pF Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Page 12 of 21 X28C512, X28C513 AC Electrical Specifications SYMBOL Over the recommended operating conditions, unless otherwise specified. PARAMETER X28C512-90 X28C512-12 X28C512-15 X28C512-20 X28C512-25 X28C513-90 X28C513-12 X28C513-15 X28C513-20 X28C513-25 MIN MIN MIN MIN MIN MAX MAX MAX MAX MAX UNIT READ CYCLE LIMITS tRC Read cycle time tCE Chip enable access time 90 120 150 200 250 ns tAA Address access time 90 120 150 200 250 ns tOE Output enable access time 40 50 50 50 50 ns 90 120 150 200 250 ns tLZ (Note 3) CE LOW to active output 0 0 0 0 0 ns tOLZ (Note 3) OE LOW to active output 0 0 0 0 0 ns tHZ (Note 3) CE HIGH to high Z output 40 50 50 50 50 ns tOHZ (Note 3) OE HIGH to high Z output 40 50 50 50 50 ns tOH Output hold from address change 0 0 0 0 0 ns Read Cycle tRC Address tCE CE tOE OE VIH WE tOLZ tOHZ tLZ Data I/O tOH tHZ HIGH Z Data Valid Data Valid tAA NOTE: 3. tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. FN8106 Rev 2.00 June 7, 2006 Page 13 of 21 X28C512, X28C513 Write Cycle Limits SYMBOL tWC (Note 4) PARAMETER MIN Write cycle time MAX UNIT 10 ms tAS Address setup time 0 ns tAH Address hold time 50 ns tCS Write setup time 0 ns tCH Write hold time 0 ns tCW CE pulse width 100 ns tOES OE HIGH setup time 10 ns tOEH OE HIGH hold time 10 ns tWP WE pulse width 100 ns WE High recovery 100 ns tWPH tDV Data valid 1 tDS Data setup 50 ns tDH Data hold 0 ns tDW Delay to next write 10 µs tBLC Byte load cycle 0.2 100 µs µs WE Controlled Write Cycle tWC Address tAS tAH tCS tCH CE OE tOES tOEH tWP WE tDV Data In Data Valid tDH tDS Data Out HIGH Z NOTE: 4. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to complete the internal write operation. FN8106 Rev 2.00 June 7, 2006 Page 14 of 21 X28C512, X28C513 CE Controlled Write Cycle tWC Address tAS tAH tCW CE tWPH tOES OE tOEH tCS tCH WE tDV Data Valid Data In tDS tDH HIGH Z Data Out Page Write Cycle OE (Note 5) CE tWP tBLC WE tWPH Address* (Note 6) Last Byte I/O Byte 0 Byte 1 Byte 2 Byte n Byte n+1 Byte n+2 tWC *For each successive write within the page write operation, A7-A15 should be the same or writes to an unknown address could occur. NOTES: 5. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. 6. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. FN8106 Rev 2.00 June 7, 2006 Page 15 of 21 X28C512, X28C513 DATA Polling Timing Diagram (Note 7) Address An An An CE WE tOEH tOES OE tDW DIN = X I/O7 DOUT = X DOUT = X tWC Toggle Bit Timing Diagram CE WE tOES tOEH OE tDW I/O6 HIGH Z * * tWC *Starting and ending state will vary, depending upon actual tWC. NOTE: 7. Polling operations are by definition read cycles and are therefore subject to read cycle timings. FN8106 Rev 2.00 June 7, 2006 Page 16 of 21 X28C512, X28C513 Packaging Information 32-Lead Hermetic Dual In-Line Package Type D 1.690 (42.95) Max. 0.610 (15.49) 0.500 (12.70) Pin 1 0.005 (0.13) Min. 0.100 (2.54) Max. Seating Plane 0.232 (5.90) Max. 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) Min. 0.200 (5.08) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) Typ. 0.100 (2.54) 0.065 (1.65) 0.033 (0.84) Typ. 0.055 (1.40) 0.023 (0.58) 0.014 (0.36) Typ. 0.018 (0.46) 0.620 (15.75) 0.590 (14.99) Typ. 0.614 (15.60) 0.015 (0.38) 0.008 (0.20) 0° 15° NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) FN8106 Rev 2.00 June 7, 2006 Page 17 of 21 X28C512, X28C513 Packaging Information 32-Pad Ceramic Leadless Chip Carrier Package Type E 0.300 (7.62) BSC 0.150 (3.81) BSC 0.015 (0.38) 0.020 (0.51) x 45° Ref. 0.003 (0.08) 0.095 (2.41) Pin 1 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) 0.055 (1.39) 0.200 (5.08) BSC 0.045 (1.14) 0.015 (0.38) Min. 0.028 (0.71) 0.022 (0.56) (32) Plcs. DIA. 0.050 (1.27) BSC TYP. (4) PLCS. 0.040 (1.02) x 45° Ref. Typ. (3) Plcs. 0.088 (2.24) 0.458 (11.63) 0.442 (11.22) 0.120 (3.05) 0.458 (11.63) 0.050 (1.27) 0.060 (1.52) -- 0.560 (14.22) 0.558 (14.17) 0.540 (13.71) -- 0.400 (10.16) BSC Pin 1 Index Corner NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: ±1% NLT ±0.005 (0.127) FN8106 Rev 2.00 June 7, 2006 Page 18 of 21 X28C512, X28C513 Packaging Information 32-Lead Ceramic Flat Pack Type F 1.228 (31.19) 1.000 (25.40) Pin 1 Index 1 0.019 (0.48) 0.015 (0.38) 32 0.050 (1.27) BSC 0.830 (21.08) Max. 0.045 (1.14) Max. 0.005 (0.13) Min. 0.440 (11.18) 0.430 (10.93) 0.007 (0.18) 0.004 (0.10) 0.120 (3.05) 0.090 (2.29) 0.370 (9.40) 0.270 (6.86) 0.347 (8.82) 0.330 (8.38) 0.026 (0.66) Min. 0.030 (0.76) Min. NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) FN8106 Rev 2.00 June 7, 2006 Page 19 of 21 X28C512, X28C513 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N32.45x55 (JEDEC MS-016AE ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) 0.050 (1.27) TP 0.025 (0.64) R 0.045 (1.14) ND CL C D2/E2 C L E1 E D2/E2 NE VIEW “A” A1 A D1 D 0.015 (0.38) MIN SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.050 (1.27) MIN 32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.125 0.140 3.18 3.55 - A1 0.060 0.095 1.53 2.41 - D 0.485 0.495 12.32 12.57 - D1 0.447 0.453 11.36 11.50 3 D2 0.188 0.223 4.78 5.66 4, 5 E 0.585 0.595 14.86 15.11 - E1 0.547 0.553 13.90 14.04 3 E2 0.238 0.273 6.05 6.93 4, 5 N 28 28 6 ND 7 7 7 NE 9 9 7 Rev. 0 7/98 NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN (0.12) M A S -B S D S 0.005 VIEW “A” TYP. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 7. ND denotes the number of leads on the two shorts sides of the package, one of which contains pin #1. NE denotes the number of leads on the two long sides of the package. © Copyright Intersil Americas LLC 2005-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8106 Rev 2.00 June 7, 2006 Page 20 of 21 X28C512, X28C513 G36.760x760A Ceramic Pin Grid Array Package (CPGA) 36 LEAD CERAMIC PIN GRID ARRAY PACKAGE 15 17 19 21 22 A 13 14 12 11 16 18 20 23 24 25 26 0.008 (0.20) 0.050 (1.27) A 10 9 27 28 8 7 29 30 6 Typ. 0.180 (.010) (4.57 ± .25) 4 Corners 5 2 36 34 32 4 3 1 35 33 31 NOTE: Leads 5, 14, 23, & 32 Typ. 0.100 (2.54) All Leads Typ. 0.180 (.010) (4.57 ± .25) 4 Corners 0.120 (3.05) 0.100 (2.54) 0.072 (1.83) 0.062 (1.57) Pin 1 Index 0.770 (19.56) 0.750 (19.05) SQ A 0.020 (0.51) 0.016 (0.41) A 0.185 (4.70) 0.175 (4.45) NOTE: All dimensions in inches (in parentheses in millimeters). Rev. 0 12/05 FN8106 Rev 2.00 June 7, 2006 Page 21 of 21