DATASHEET
X28HC64
FN8109
Rev 4.00
June 27, 2016
64k, 8k x 8-Bit 5 Volt, Byte Alterable EEPROM
The X28HC64 is an 8k x 8 EEPROM, fabricated with Intersil’s
proprietary, high performance, floating gate CMOS technology.
Like all Intersil programmable nonvolatile memories, the
X28HC64 is a 5V only device. It features the JEDEC approved
pinout for byte-wide memories, compatible with industry
standard RAMs.
The X28HC64 supports a 64-byte page write operation, effectively
providing a 32µs/byte write cycle, and enabling the entire
memory to be typically written in 0.25 seconds. The X28HC64
also features DATA Polling and Toggle Bit Polling, two methods
providing early end of write detection. In addition, the X28HC64
includes a user-optional software data protection mode that
further enhances Intersil’s hardware write protect capability.
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Inherent data retention is
greater than 100 years.
Features
• 70ns access time
• Simple byte and page write
- Single 5V supply
- No external high voltages or VP-P control circuits
- Self-timed
- No erase before write
- No complex programming algorithms
- No overerase problem
• Low power CMOS
- 40mA active current maximum
• 200µA standby current maximum
• Fast write cycle times
- 64-byte page write operation
- Byte or page write cycle: 2ms typical
- Complete memory rewrite: 0.25s typical
- Effective byte write cycle time: 32µs typical
• Software data protection
• End of write detection
- DATA polling
- Toggle bit
• High reliability
- Endurance: 100,000 cycles
- Data retention: 100 years
• JEDEC approved byte-wide pinout
• Pb-free available (RoHS compliant)
Pin Configurations
4
25
A8
A5
5
24
A9
A4
6
23
A11
22
OE
A10
A3
7
A2
8
A1
9
20
A0
10
19
X28HC64
21
CE
I/O7
I/O0
11
18
I/O6
I/O1
12
17
I/O5
I/O2
VSS
13
16
I/O4
14
15
I/O3
FN8109 Rev 4.00
June 27, 2016
NC
A6
4 3
2 1 32 31 30
A6
5
29
A8
A5
6
7
28
27
A9
8
9
26
25
A4
A3
A2
A1
A0
NC
I/O0
X28HC64
24
23
10
11
22
12
21
13
14 15 16 17 18 19 20
A11
NC
OE
A10
CE
I/O7
I/O6
I/O5
26
VCC
WE
3
I/O4
A7
WE
NC
NC
NC
VCC
27
A7
28
2
I/O2
VSS
NC
I/O3
1
I/O1
NC
A12
A12
X28HC64
(32 LD PLCC)
TOP VIEW
X28HC64
(28 LD PDIP, SOIC)
TOP VIEW
Page 1 of 18
X28HC64
Ordering Information
PART NUMBER
PART MARKING
X28HC64J-70 (Notes 1, 6)
(No longer available, recommended
replacement: X28HC64JZ-70)
X28HC64J-70 CY
X28HC64JIZ-70 (Notes 1, 4, 6)
X28HC64JI-70 ZCY
X28HC64JZ-70 (Notes 1, 4, 6)
TEMPERATURE
RANGE (°C)
ACCESS TIME
(ns)
0 to +70
70
PKG.
DWG. #
PACKAGE
32 Ld PLCC
N32.45x55
-40 to +85
32 Ld PLCC (RoHS Compliant)
N32.45x55
X28HC64J-70 ZCY
0 to +70
32 Ld PLCC (RoHS Compliant)
N32.45x55
X28HC64SIZ-70 (Notes 4, 6)
X28HC64SI-70 CYZ
-40 to +85
28 Ld SOIC (300 mil) (RoHS
Compliant)
M28.3
X28HC64SZ-70 (Notes 4, 6)
X28HC64S-70 CYZ
0 to +70
28 Ld SOIC (300 mil) (RoHS
Compliant)
M28.3
X28HC64J-90 (Notes 1, 6)
(No longer available, recommended
replacement: X28HC64JIZ-90)
X28HC64J-90 CY
0 to +70
32 Ld PLCC
N32.45x55
X28HC64JI-90 (Notes 1, 3, 6)
(No longer available, recommended
replacement: X28HC64JIZ-90)
X28HC64JI-90 CY
-40 to +85
32 Ld PLCC
N32.45x55
X28HC64JIZ-90 (Notes 1, 4, 6)
X28HC64JI-90 ZCY
-40 to +85
32 Ld PLCC (RoHS Compliant)
N32.45x55
X28HC64PIZ-90 (Notes 4, 5)
X28HC64PI-90 CYZ
-40 to +85
28 Ld PDIP (RoHS Compliant)
E28.6
X28HC64PZ-90 (Notes 4, 5)
X28HC64P-90 CYZ
0 to +70
28 Ld PDIP (RoHS Compliant)
E28.6
X28HC64J-12 (Notes 1, 6)
(No longer available, recommended
replacement: X28HC64JZ-12)
X28HC64J-12 CY
0 to +70
32 Ld PLCC
N32.45x55
X28HC64JI-12 (Notes 1, 6)
(No longer available, recommended
replacement: X28HC64JIZ-12)
X28HC64JI-12 CY
-40 to +85
32 Ld PLCC
N32.45x55
X28HC64JIZ-12 (Notes 1, 4, 6)
X28HC64JI-12 ZCY
-40 to +85
32 Ld PLCC (RoHS Compliant)
N32.45x55
X28HC64JZ-12* (Notes 1, 4, 6)
X28HC64J-12 ZCY
0 to +70
32 Ld PLCC (RoHS Compliant)
N32.45x55
X28HC64PIZ-12 (Notes 4, 5)
X28HC64PI-12 CYZ
-40 to +85
28 Ld PDIP (RoHS Compliant)
E28.6
X28HC64PZ-12 (Notes 4, 5)
X28HC64P-12 CYZ
0 to +70
28 Ld PDIP (RoHS Compliant)
E28.6
X28HC64SIZ-12 (Notes 2, 4, 6)
X28HC64SI-12 CYZ
-40 to +85
28 Ld SOIC (300 mil) (RoHS
Compliant)
M28.3
X28HC64SZ-12 (Notes 4, 6)
X28HC64S-12 CYZ
0 to +70
28 Ld SOIC (300 mil) (RoHS
Compliant)
M28.3
90
120
NOTES:
1. Add “T1” suffix for 750 unit tape and reel option.
2. Add “T1” suffix for 1000 unit tape and reel option.
3. Add “T2” suffix for 750 unit tape and reel option.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
6. For Moisture Sensitivity Level (MSL), please see product information page for X28HC64. For more information on MSL, please see tech brief TB363.
FN8109 Rev 4.00
June 27, 2016
Page 2 of 18
X28HC64
Write
Pin Descriptions
SYMBOL
DESCRIPTION
A0-A12
Address Inputs. The Address inputs
select an 8-bit memory location
during a read or write operation.
I/O0-I/O7
Data Input/Output. Data is written
to or read from the X28HC64
through the I/O pins.
WE
Write Enable. The Write Enable
input controls the writing of data to
the X28HC64.
CE
Chip Enable. The Chip Enable input
must be LOW to enable all
read/write operations. When CE is
HIGH, power consumption is
reduced.
OE
Output Enable. The Output Enable
input controls the data output
buffers and is used to initiate read
operations.
VCC
+5V
VSS
Ground
NC
No Connect
Block Diagram
65,536-BIT
X BUFFERS
LATCHES AND
DECODER
EEPROM
ARRAY
Write operations are initiated when both CE and WE are LOW and
OE is HIGH. The X28HC64 supports both a CE and WE controlled
write cycle. That is, the address is latched by the falling edge of
either CE or WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or WE, whichever
occurs first. A byte write operation, once initiated, will
automatically continue to completion, typically within 2ms.
Page Write Operation
The page write feature of the X28HC64 allows the entire memory
to be written in 0.25 seconds. Page write allows two to sixty-four
bytes of data to be consecutively written to the X28HC64 prior to
the commencement of the internal programming cycle. The host
can fetch data from another device within the system during a
page write operation (change the source address), but the page
address (A6 through A12) for each subsequent valid write cycle to
the part during this operation must be the same as the initial page
address.
The page write mode can be initiated during any write operation.
Following the initial byte write cycle, the host can write an
additional one to sixty-three bytes in the same manner. Each
successive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of the
preceding WE. If a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic programming
cycle will commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so long as the
host continues to access the device within the byte load cycle
time of 100µs.
Write Operation Status Bits
The X28HC64 provides the user two write operation status bits.
These can be used to optimize a system write cycle time. The
status bits are mapped onto the I/O bus as shown in Figure 2.
A0–A12
ADDRESS
INPUTS
Y BUFFERS
LATCHES
AND
DECODER
I/O BUFFERS
AND LATCHES
I/O
DP
TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
CE
CONTROL
LOGIC AND
TIMING
OE
WE
DATA POLLING
I/O0–I/O7
DATA INPUTS/OUTPUTS
FIGURE 2. STATUS BIT ASSIGNMENT
VCC
VSS
FIGURE 1. BLOCK DIAGRAM
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The read
operation is terminated by either CE or OE returning HIGH. This
two line control architecture eliminates bus contention in a
system environment. The data bus will be in a high impedance
state when either OE or CE is HIGH.
FN8109 Rev 4.00
June 27, 2016
Page 3 of 18
X28HC64
DATA Polling (I/O7)
The X28HC64 features DATA Polling as a method to indicate to
the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the X28HC64, eliminating additional
interrupt inputs or external hardware. During the internal
programming cycle, any attempt to read the last byte written will
WE
produce the complement of that data on I/O7 (i.e., write data =
0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is
complete, I/O7 will reflect true data.
DATA Polling can effectively reduce the time for writing to the
X28HC64. The timing diagram in Figure 3 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 4 illustrates one method of implementing the routine.
LAST
WRITE
CE
OE
VIH
VOH
HIGH Z
I/O7
VOL
A0–A12
An
An
An
X28HC64
READY
An
An
An
An
FIGURE 3. DATA POLLING BUS SEQUENCE
WRITE DATA
NO
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO7
COMPARE?
NO
YES
READY
FIGURE 4. DATA POLLING SOFTWARE FLOW
FN8109 Rev 4.00
June 27, 2016
Page 4 of 18
X28HC64
Toggle Bit (I/O6)
The X28HC64 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle I/O6 will toggle from HIGH to LOW and LOW
to HIGH on subsequent attempts to read the device. When the
internal cycle is complete, the toggling will cease and the device
will be accessible for additional read or write operations.
WE
The Toggle Bit can eliminate the chore of saving and fetching the
last address and data in order to implement DATA Polling. This
can be especially helpful in an array comprised of multiple
X28HC64 memories that is frequently updated. Toggle Bit Polling
can also provide a method for status checking in multiprocessor
applications. The timing diagram in Figure 5 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 6 illustrates a method for polling the Toggle Bit.
LAST
WRITE
CE
OE
VOH
I/O6
*
HIGH Z
VOL
*
X28HC64
READY
* BEGINNING AND ENDING STATE OF I/O6 WILL VARY.
FIGURE 5. TOGGLE BIT BUS SEQUENCE
LAST WRITE
YES
LOAD ACCUM
FROM ADDR N
COMPARE
ACCUM WITH
ADDR N
COMPARE
OK?
NO
YES
READY
FIGURE 6. TOGGLE BIT SOFTWARE FLOW
FN8109 Rev 4.00
June 27, 2016
Page 5 of 18
X28HC64
Hardware Data Protection
nonvolatile and will remain set for the life of the device, unless
the reset command is issued.
The X28HC64 provides two hardware features that protect
nonvolatile data from inadvertent writes.
• Default VCC Sense—All write functions are inhibited when VCC is
3V typically.
• Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will
prevent an inadvertent write cycle during power-up and
power-down, maintaining data integrity.
Software Data Protection
The X28HC64 offers a software controlled data protection feature.
The X28HC64 is shipped from Intersil with the software data
protection NOT ENABLED; that is, the device will be in the standard
operating mode. In this mode data should be protected during
power-up/power-down operations through the use of external
circuits. The host would then have open read and write access of the
device once VCC was stable.
The X28HC64 can be automatically protected during power-up
and power-down without the need for external circuits by
employing the software data protection feature. The internal
software data protection circuit is enabled after the first write
operation utilizing the software algorithm. This circuit is
Once the software protection is enabled, the X28HC64 is also
protected from inadvertent and accidental writes in the
powered-up state. That is, the software algorithm must be issued
prior to writing additional data to the device.
Software Algorithm
Selecting the software data protection mode requires the host
system to precede data write operations by a series of three write
operations to three specific addresses. Refer to Figures 7 and 8
for the sequence. The 3-byte sequence opens the page write
window, enabling the host to write from 1 to 64 bytes of data.
Once the page load cycle has been completed, the device will
automatically be returned to the data protected state.
Regardless of whether the device has previously been protected
or not, once the software data protection algorithm is used, the
X28HC64 will automatically disable further writes unless another
command is issued to deactivate it. If no further commands are
issued, the X28HC64 will be write protected during power-down
and after any subsequent power-up.
Note: Once initiated, the sequence of write operations should not
be interrupted.
VCC
(VCC)
0V
DATA
ADDR
AAA
1555
55
0AAA
A0
1555
WRITES
OK
tWC
WRITE
PROTECTED
CE
≤tBLC MAX
WE
BYTE
OR
PAGE
FIGURE 7. TIMING SEQUENCE—BYTE OR PAGE WRITE
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA A0
TO ADDRESS
1555
WRITE DATA XX
TO ANY
ADDRESS
WRITE LAST
BYTE TO
LAST ADDRESS
BYTE/PAGE
LOAD ENABLED
OPTIONAL
BYTE/PAGE
LOAD OPERATION
AFTER TWC
RE-ENTERS DATA
PROTECTED STATE
FIGURE 8. WRITE SEQUENCE FOR SOFTWARE DATA PROTECTION
FN8109 Rev 4.00
June 27, 2016
Page 6 of 18
X28HC64
Resetting Software Data Protection
VCC
DATA
ADDR
AAA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
tWC
STANDARD
OPERATING
MODE
CE
WE
FIGURE 9. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 80
TO ADDRESS
1555
WRITE DATA AA
ADDRESS
1555
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 20
TO ADDRESS
1555
FIGURE 10. SOFTWARE SEQUENCE TO DEACTIVATE SOFTWARE DATA PROTECTION
In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an EEPROM
programmer, the following six step algorithm will reset the
internal protection circuit. After tWC, the X28HC64 will be in
standard operating mode.
Note: Once initiated, the sequence of write operations should not
be interrupted.
FN8109 Rev 4.00
June 27, 2016
Page 7 of 18
X28HC64
System Considerations
Because the X28HC64 is frequently used in large memory arrays,
it is provided with a two-line control architecture for both read
and write operations. Proper usage can provide the lowest
possible power dissipation, and eliminate the possibility of
contention where multiple I/O pins share the same bus.
To gain the most benefit, it is recommended that CE be decoded
from the address bus, and be used as the primary device
selection input. Both OE and WE would then be common among
all devices in the array. For a read operation, this assures that all
deselected devices are in their standby mode, and that only the
selected device(s) is/are outputting data on the bus.
Because the X28HC64 has two power modes, standby and
active, proper decoupling of the memory array is of prime
+ 25°C
1.0
+ 125°C
0.8
5.5VCC
1.2
- 55°C
0.6
0.4
NORMALIZED (mA)
NORMALIZED (mA)
ICCRD
1.4
5.5VCC
1.2
0.2
In addition, it is recommended that a 4.7µF electrolytic bulk
capacitor be placed between VCC and VSS for each eight devices
employed in the array. This bulk capacitor is employed to
overcome the voltage droop caused by the inductive effects of
the PC board traces.
ICCRD
1.4
concern. Enabling CE will cause transient current spikes. The
magnitude of these spikes is dependent on the output capacitive
loading of the I/Os. Therefore, the larger the array sharing a
common bus, the larger the transient spikes. The voltage peaks
associated with the current transients can be suppressed by the
proper selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high frequency
ceramic capacitor be used between VCC and VSS at each device.
Depending on the size of the array, the value of the capacitor
may have to be larger.
1.0
5.0VCC
0.8
4.5VCC
0.6
0.4
0M
10M
FREQUENCY (Hz)
FIGURE 11. NORMALIZED ICC(RD) BY TEMPERATURE
OVER FREQUENCY DATA PROTECTION
FN8109 Rev 4.00
June 27, 2016
20M
0.2
0M
10M
20M
FREQUENCY (Hz)
FIGURE 12. NORMALIZED ICC(RD) AT 25% OVER THE VCC RANGE
AND FREQUENCY
Page 8 of 18
X28HC64
Absolute Maximum Ratings
Thermal Information
Temperature Under Bias
X28HC64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +85°C
X28HC64I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any Pin with Respect to VSS . . . . . . . . . . . . . . . . . . . . .-1V to +7V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
32 Ld PLCC Package (Notes 7, 9) . . . . . . .
41
19
28 Ld SOIC Package (Notes 7, 9) . . . . . . . .
46
19
28 Ld PDIP Package (Notes 8, 9) . . . . . . . .
53
21
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
*Pb-free PDIPs can be used for through hole wave solder processing only.
They are not intended for use in Reflow solder processing applications.
Recommended Operating Conditions
Commercial Temperature Range . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage Range
X28HC64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
8. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
9. For JC, the “case temp” location is taken at the package top center.
DC Electrical Specifications
PARAMETER
Over recommended operating conditions, unless otherwise specified.
SYMBOL
TYP
MAX
MIN
(Note 10) (Note 11) (Note 10) UNIT
TEST CONDITIONS
VCC Current (Active) (TTL Inputs)
ICC
CE = OE = VIL, WE = VIH, All I/O’s = open, address
inputs = TTL levels at f = 10MHz
15
40
mA
VCC Current (Standby) (TTL Inputs)
ISB1
CE = VIH, OE = VIL All I/O’s = open, other inputs = VIH
1
2
mA
VCC Current (Standby) (CMOS Inputs)
ISB2
CE = VCC - 0.3V, OE = GND, All I/O’s = open, other
inputs = VCC - 0.3V
100
200
µA
Input Leakage Current
ILI
VIN = VSS to VCC
±10
µA
Output Leakage Current
ILO
VOUT = VSS to VCC, CE = VIH
±10
µA
Input LOW Voltage (Note 12)
VlL
-1
0.8
V
Input HIGH Voltage (Note 12)
VIH
2
VCC + 1
V
Output LOW Voltage
VOL
IOL = 5mA
0.4
V
Output HIGH Voltage
VOH
IOH = -5mA
2.4
V
NOTES:
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
11. Typical values are for TA = +25°C and nominal supply voltage.
12. VIL minimum and VIH maximum are for reference only and are not tested.
Endurance and Data Retention
The endurance and data retention specifications are established by characterization and are not
production tested.
PARAMETER
Minimum Endurance
Data Retention
FN8109 Rev 4.00
June 27, 2016
MIN
MAX
UNIT
100,000
Cycles
100
Years
Page 9 of 18
X28HC64
Power-Up Timing
SYMBOL
TYP
(Note 11)
UNIT
Power-Up to Read Operation (Note 13)
tPUR
100
µs
Power-Up to Write Operation (Note 13)
tPUW
5
ms
PARAMETER
Capacitance
TA = +25°C, f = 1MHz, VCC = 5V
PARAMETER
SYMBOL
TEST CONDITIONS
MAX
UNIT
Input/output Capacitance (Note 13)
CI/O
VI/O = 0V
10
pF
Input Capacitance (Note 13)
CIN
VIN = 0V
6
pF
NOTE:
13. This parameter is periodically sampled and not 100% tested.
Symbol Table
TABLE 1. AC CONDITIONS OF TEST
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
WAVEFORM
TABLE 2. MODE SELECTION
CE
OE
WE
L
L
H
Read
DOUT
Active
L
H
L
Write
DIN
Active
H
X
X
Standby and write High Z
inhibit
Standby
X
L
X
Write inhibit
-
-
X
X
H
Write inhibit
-
-
MODE
I/O
POWER
INPUTS
OUTPUTS
Must be
steady
Will be
steady
Ma y change
from LOW
to HIGH
Will change
from LOW
to HIGH
Ma y change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Equivalent AC Load Circuits
5V
1.92kΩ
OUTPUT
1.37kΩ
30pF
FIGURE 13. EQUIVALENT AC LOAD CIRCUITS
FN8109 Rev 4.00
June 27, 2016
Page 10 of 18
X28HC64
AC Electrical Specifications
Read Cycle Limits Over the recommended operating conditions unless otherwise specified.
X28HC64-70
MAX
(Note 10)
X28HC64-90
MIN
(Note 10)
MAX
(Note 10)
X28HC64-12
MIN
(Note 10)
MAX
(Note 10)
SYMBOL
MIN
(Note 10)
Read Cycle Time
tRC
70
Chip Enable Access Time
tCE
70
90
120
ns
Address Access Time
tAA
70
90
120
ns
Output Enable Access Time
tOE
35
40
50
ns
CE LOW to Active Output (Note 14)
tLZ
0
0
0
ns
OE LOW to Active Output (Note 14)
tOLZ
0
0
0
ns
CE HIGH to High Z Output (Note 14)
tHZ
30
30
30
ns
OE HIGH to High Z Output (Note 14)
tOHZ
30
30
30
ns
Output Hold from Address Change
tOH
PARAMETER
90
0
0
UNIT
120
ns
0
ns
NOTE:
14. tLZ minimum, tHZ, tOLZ minimum, and tOHZ are periodically sampled and not 100% tested. tHZ maximum and tOHZ maximum are measured from the
point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
Read Cycle
tRC
ADDRESS
tCE
CE
tOE
OE
VIH
WE
tOLZ
tOHZ
tLZ
DATA I/O
HIGH Z
tOH
tHZ
DATA VALID
DATA VALID
tAA
FIGURE 14. READ CYCLE
FN8109 Rev 4.00
June 27, 2016
Page 11 of 18
X28HC64
Write Cycle Limits
PARAMETER
MIN
(Note 10)
SYMBOL
TYP
(Note 11)
MAX
(Note 10)
UNIT
2
5
ms
Write Cycle Time (Note 15)
tWC
Address Set-Up Time
tAS
0
ns
Address Hold Time
tAH
50
ns
Write Set-Up Time
tCS
0
ns
Write Hold Time
tCH
0
ns
CE Pulse Width
tCW
50
ns
OE High Set-Up Time
tOES
0
ns
OE High Hold Time
tOEH
0
ns
WE Pulse Width
tWP
50
ns
WE HIGH Recovery (Note 16)
tWPH
50
ns
Data Valid (Note 16)
tDV
1
Data Setup
tDS
50
ns
Data Hold
tDH
0
ns
Delay to Next Write (Note 16)
tDW
10
µs
Byte Load Cycle
tBLC
0.15
100
µs
µs
NOTES:
15. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to automatically complete the internal write operation.
16. tWPH and tDW are periodically sampled and not 100% tested.
WE Controlled Write Cycle
tWC
ADDRESS
tAS
tAH
tCS
tCH
CE
OE
tOES
tOEH
tWP
WE
tDV
DATA IN
DATA VALID
tDS
DATA OUT
tDH
HIGH Z
FIGURE 15. WE CONTROLLED WRITE CYCLE
FN8109 Rev 4.00
June 27, 2016
Page 12 of 18
X28HC64
tWC
ADDRESS
tAS
tAH
tCW
CE
tOES
OE
tOEH
tCS
tCH
WE
tDV
DATA VALID
DATA IN
tDS
tDH
HIGH Z
DATA OUT
FIGURE 16. CE CONTROLLED WRITE CYCLE
OE
Note 17
CE
tWP
tBLC
WE
tWPH
ADDRESS
Note 18
LAST BYTE
I/O
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
*For each successive write within the page write operation, A6–A12 should be the same or
writes to an unknown address could occur.
NOTES:
Byte n+2
tWC
FIGURE 17. PAGE WRITE CYCLE
17. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from
another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
18. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE
or WE controlled write cycle timing.
FN8109 Rev 4.00
June 27, 2016
Page 13 of 18
X28HC64
ADDRESS
An
An
An
CE
WE
tOEH
tOES
OE
tDW
I/O7
DIN = X
DOUT = X
DOUT = X
tWC
FIGURE 18. DATA POLLING TIMING DIAGRAM (Note 19)
CE
WE
tOES
tOEH
OE
tDW
I/O*6
HIGH Z
*
*
tWC
* I/O6 beginning and ending state will vary, depending upon actual tWC.
FIGURE 19. TOGGLE BIT TIMING DIAGRAM (Note 19)
NOTE:
19. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
FN8109 Rev 4.00
June 27, 2016
Page 14 of 18
X28HC64
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE
REVISION
CHANGE
June 27, 2016
FN8109.4
Updated entire datasheet applying Intersil’s new standards.
Updated the Ordering Information table by adding Note 2, updated other tape and reel notes, updated all of the
part marking and added Note 6.
Added Thermal Information (Theta JA, Theta JC, and applicable notes) on page 9.
Added “The endurance and data retention specifications are established by characterization and are not
production tested” to the “Endurance and Data Retention” table.
August 18, 2015
FN8109.3
- Updated Ordering Information Table on page 2.
- Added Revision History and About Intersil sections.
- Updated POD M28.3 to latest revision changes are as follow:
Added land pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
FN8109 Rev 4.00
June 27, 2016
Page 15 of 18
X28HC64
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
0.056 (1.42)
PIN (1)
IDENTIFIER
0.004 (0.10)
0.050 (1.27) TP
0.025 (0.64)
R
0.045 (1.14)
ND
CL
C
D2/E2
E1 E
C
L
D2/E2
NE
VIEW “A”
A1
A
D1
D
0.015 (0.38)
MIN
SEATING
-C- PLANE
0.020 (0.51) MAX
3 PLCS
0.026 (0.66)
0.032 (0.81)
0.050 (1.27)
MIN
N32.45x55 (JEDEC MS-016AE ISSUE A)
32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.125
0.140
3.18
3.55
-
A1
0.060
0.095
1.53
2.41
-
D
0.485
0.495
12.32
12.57
-
D1
0.447
0.453
11.36
11.50
3
D2
0.188
0.223
4.78
5.66
4, 5
E
0.585
0.595
14.86
15.11
-
E1
0.547
0.553
13.90
14.04
3
E2
0.238
0.273
6.05
6.93
4, 5
N
28
28
6
ND
7
7
7
NE
9
9
7
Rev. 0 7/98
NOTES:
1. Controlling dimension: INCH. Converted millimeter
dimensions are not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
(0.12)
M A S -B S D S
0.005
VIEW “A” TYP.
3. Dimensions D1 and E1 do not include mold protrusions.
Allowable mold protrusion is 0.010 inch (0.25mm) per side.
Dimensions D1 and E1 include mold mismatch and are
measured at the extreme material condition at the body
parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic
body.
6. “N” is the number of terminal positions.
7. ND denotes the number of leads on the two shorts sides of the
package, one of which contains pin #1. NE denotes the
number of leads on the two long sides of the package.
FN8109 Rev 4.00
June 27, 2016
Page 16 of 18
X28HC64
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45o
a
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
A
0.0926
0.1043
2.35
2.65
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
B S
MIN
MAX
NOTES
-
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
e
-C-
MILLIMETERS
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
N
28
0o
1.27
28
8o
0o
6
7
8o
Rev. 1, 1/13
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
TYPICAL RECOMMENDED LAND PATTERN
(1.50mm)
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
(9.38mm)
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
(1.27mm TYP)
FN8109 Rev 4.00
June 27, 2016
(0.51mm TYP)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
Page 17 of 18
X28HC64
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-011-AB ISSUE B)
N
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AE
D
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
e
B1
D1
eA
A1
eC
B
0.010 (0.25) M
C
L
C A B S
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.250
-
6.35
4
A1
0.015
-
0.39
-
4
A2
0.125
0.195
3.18
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.030
0.070
0.77
1.77
8
C
0.008
0.015
D
1.380
1.565
D1
0.005
-
0.13
E
0.600
0.625
15.24
15.87
6
E1
0.485
0.580
12.32
14.73
5
e
0.100 BSC
eA
0.600 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
eB
-
L
0.115
4. Dimensions A, A1 and L are measured with the package seated in JEDEC
seating plane gauge GS-3.
N
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
0.204
0.381
35.1
39.7
-
5
5
2.54 BSC
-
15.24 BSC
6
0.700
-
0.200
2.93
28
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be
perpendicular to datum -C- .
17.78
5.08
28
7
4
9
Rev. 1 12/00
7. eB and eC are measured at the lead tips with the leads unconstrained. eC
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
© Copyright Intersil Americas LLC 2005-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8109 Rev 4.00
June 27, 2016
Page 18 of 18
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