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1-888-IN
X40410, X40411, X40414, X40415
4kbit EEPROM
March 28, 2005
Dual Voltage Monitor with Integrated CPU
Supervisor
FN8116.0
• Available packages
—8-lead SOIC, TSSOP
• Monitor Voltages: 5V to 0.9V
• Memory Security
• Independent Core Voltage Monitor
FEATURES
• Dual voltage detection and reset assertion
—Standard reset threshold settings
See Selection table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three voltages or detect power fail
• Independent Core Voltage Monitor (V2MON)
• Fault detection register
• Selectable power-on reset timeout (0.05s,
0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval (25ms,
200ms,1.4s, off)
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• 4Kbits of EEPROM
—16 byte page write mode
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect none or 1/2 of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
APPLICATIONS
• Communication Equipment
—Routers, Hubs, Switches
—Disk Arrays, Network Storage
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Computers
—Network Servers
DESCRIPTION
The X40410/11/14/15 combines power-on reset control,
watchdog timer, supply voltage supervision, and secondary voltage supervision, and Block Lock™ protect
serial EEPROM in one package. This combination lowers system cost, reduces board space requirements,
and increases reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
BLOCK DIAGRAM
SDA
SCL
Fault Detection
Register
Data
Register
EEPROM
Array
Threshold
Reset Logic
Power-on,
Low Voltage
Reset
Generation
+
User Programmable
VTRIP1
+
V2MON
User Programmable
VTRIP2
1
WDO
Status
Register
Command
Decode Test
& Control
Logic
VCC
(V1MON)
Watchdog Timer
and
Reset Logic
-
VCC or
V2MON
RESET
X40410/14
RESET
X40411/15
V2FAIL
*X40410/11= V2MON*
X40414/15 = VCC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X40410, X40411, X40414, X40415
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the minimum VTRIP1 point. RESET/RESET is active until VCC returns to proper operating level
and stabilizes. A second voltage monitor circuit tracks
the unregulated supply to provide a power fail warning
or monitors different power supply voltage. Three common low voltage combinations are available, however,
Intersil’s unique circuits allows the threshold for either
voltage monitor to be reprogrammed to meet special
needs or to fine-tune the threshold for applications requiring higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as x 8. The device
features a 2-wire interface and software protocol
allowing operation on an I2C® bus.
The device utilizes Intersil’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microTriple Voltage Monitors
Device
X4040/11
-A
-B
-C
X40414/15
-A
-B
-C
Expected System Voltages
5V; 3V or 3.3V
5V; 3V
3V; 3.3V; 1.8V
3V; 3.3V; 1.5V
3V; 1.5V
3V or 3.3V; 1.1 or 1.2V
Vtrip1(V)
2.0–4.75*
4.55–4.65*
4.35–4.45*
2.85–2.95*
2.0–4.75*
2.85–2.95*
2.55–2.65*
2.85–2.95*
Vtrip2(V)
POR (system)
1.70–4.75
2.85–2.95
2.55–2.65
1.65–1.75
0.90–3.50*
1.25–1.35*
1.25–1.35*
0.95–1.05*
RESET = X40410
RESET = X40411
RESET = X40414
RESET = X40415
*Voltage monitor requires VCC to operation. Others are independent of VCC.
PIN CONFIGURATION
X40410/14, X40411/15
8-Pin TSSOP
X40410/14, X40411/15
8-Pin SOIC
V2FAIL
V2MON
RESET/RESET
VSS
1
2
3
4
8
7
6
5
VCC
WDO
SCL
SDA
WDO
VCC
V2FAIL
V2MON
1
2
3
4
8
7
6
5
SCL
SDA
VSS
RESET/RESET
PIN DESCRIPTION
Pin
SOIC TSSOP Name
Function
1
3
V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.
2
4
V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to VSS or VCC when
not used.The V2MON comparator is supplied by V2MON (X40410/11) or by VCC Input (X40414/15).
3
5
RESET/ RESET Output. (X40411/15) This is an active LOW, open drain output which goes active whenever
RESET VCC falls below VTRIP1. It will remain active until VCC rises above VTRIP1 and for the tPURST thereafter.
RESET Output. (X40410/14) This is an active HIGH CMOS output which goes active whenever VCC
falls below VTRIP1. It will remain active until VCC rises above VTRIP1 and for the tPURST thereafter.
Ground
4
6
VSS
5
7
SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires
a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to
LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the watchdog time out period results in WDO going active.
2
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
PIN DESCRIPTION (Continued)
Pin
SOIC TSSOP Name
6
8
SCL
7
1
WDO
8
2
VCC
Function
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog timer goes active.
Supply Voltage
PRINCIPLES OF OPERATION
Power-On Reset
Application of power to the X40410/11/14/15 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pins active. This signal provides several benefits.
– It prevents the system microprocessor from starting to
operate with insufficient voltage.
– It prevents the processor from operating prior to stabilization of the oscillator.
– It allows time for an FPGA to download its configuration prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When VCC exceeds the device VTRIP1 threshold value for
tPURST (selectable) the circuit releases the RESET
(X40411) and RESET (X40410) pin allowing the system
to begin operation.
For the X40414/15 devices, the V2FAIL signal remains
actice until VCC drops below 1Vx and remains active
until V2MON returns and exceeds VTRIP2. This sense
circuitry is powered by VCC. If VCC = 0, V2MON cannot
be monitored.
Figure 1. Two Uses of Multiple Voltage Monitoring
X40411-A
5V
Reg
6–10V
1M
Low Voltage V2 Monitoring
VCC
System
Reset
RESET
V2MON
(2.9V)
V2FAIL
1M
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
Low Voltage VCC (V1 Monitoring)
During operation, the X40410/11/14/15 monitors the
VCC level and asserts RESET/RESET if supply voltage
falls below a preset minimum VTRIP1. The
RESET/RESET signal prevents the microprocessor
from operating in a power fail or brownout condition.
The V1FAIL signal remains active until the voltage
drops below 1V. It also remains active until VCC returns
and exceeds VTRIP1 for tPURST.
VCC V2MON
X40414-C
Unreg.
Supply
3.3V
Reg
VCC
RESET
1.2V
Reg
VCC
V2MON
System
Reset
V2FAIL
Notice: No external components required to monitor two voltages.
The X40410/11/14/15 also monitors a second voltage
level and asserts V2FAIL if the voltage falls below a
preset minimum VTRIP2. The V2FAIL signal is either
ORed with RESET to prevent the microprocessor from
operating in a power fail or brownout condition or used to
interrupt the microprocessor with notification of an
impending power failure. For the X40410/11 the V2FAIL
signal remains active until the VCC drops below 1V (VCC
falling). It also remains active until V2MON returns and
exceeds VTRIP2 by 0.2V. This voltage sense circuitry
monitors the power supply connected to the V2MON pin.
If VCC = 0, V2MON can still be monitored.
3
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
Figure 2. VTRIPX Set/Reset Conditions
VTRIPX
(X = 1, 2)
VCC/V2MON
VP
WDO
7
0
SCL
0
7
0
7
SDA
00h
A0h
tWC
WATCHDOG TIMER
Setting a VTRIPx Voltage (x = 1, 2)
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL also toggles from HIGH to LOW (this is
a start bit) followed by a stop condition prior to the expiration of the watchdog time out period to prevent a WDO
signal going active. The state of two nonvolatile control
bits in the Status Register determines the watchdog timer
period. The microprocessor can change these watchdog
bits by writing to the X40410/11/14/15 control register
(also refer to page 19).
There are two procedures used to set the threshold
voltages (VTRIPx), depending if the threshold voltage to
be stored is higher or lower than the present value. For
example, if the present VTRIPx is 2.9 V and the new
VTRIPx is 3.2 V, the new voltage can be stored directly
into the VTRIPx cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the VTRIPx voltage before setting the new
value.
Figure 3. Watchdog Restart
.6µs
1.3µs
SCL
SDA
Timer Start
V1 AND V2 THRESHOLD PROGRAM PROCEDURE
(OPTIONAL)
The X40410/11/14/15is shipped with standard V1 and
V2 threshold (VTRIP1, VTRIP2) voltages. These values
will not change over normal operating and storage
conditions. However, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the
X40410/11/14/15 trip points may be adjusted. The procedure is described below, and uses the application of a
high voltage control signal.
4
Setting a Higher VTRIPx Voltage (x = 1, 2)
To set a VTRIPx threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired VTRIPx threshold voltage to the corresponding input pin Vcc(V1MON), or V2MON. The
Vcc(V1MON) and V2MON must be tied together
during this sequence. Then, a programming voltage
(Vp) must be applied to the WDO pin before a START
condition is set up on SDA. Next, issue on the SDA pin
the Slave Address A0h, followed by the Byte Address
01h for VTRIP1 and 09h for VTRIP2, and a 00h Data
Byte in order to program VTRIPx. The STOP bit following a valid write operation initiates the programming
sequence. Pin WDO must then be brought LOW to
complete the operation.
Note: This operation does not corrupt the memory
array.
Setting a Lower VTRIPx Voltage (x = 1, 2)
In order to set VTRIPx to a lower voltage than the present value, then VTRIPx must first be “reset” according
to the procedure described below. Once VTRIPx has
been “reset”, then VTRIPx can be set to the desired
voltage using the procedure described in “Setting a
Higher VTRIPx Voltage”.
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
Resetting the VTRIPx Voltage
To reset a VTRIPx voltage, apply the programming voltage (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
VTRIP1 and 0Bh for VTRIP2, followed by 00h for the
Data Byte in order to reset VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WDO must then be brought LOW
to complete the operation.
After being reset, the value of VTRIPx becomes a nominal value of 1.7V or lesser.
Note: This operation does not corrupt the memory
array.
CONTROL REGISTER
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
The Control Register is accessed with a special preamble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
one data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Registers" on page 7.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, BP1, and BP0. The
X40410/11/14/15 will not acknowledge any data bytes
written after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address 01Fh,
using the special preamble. Only one byte is read by
each register read operation. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation.
7
6
PUP1 WD1
5
4
3
WD0
BP
0
2
1
0
RWEL WEL PUP0
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 4. Sample VTRIP Reset Circuit
VP
Adjust
V2FAIL
RESET
VTRIP1
Adj.
1
3 SOIC 7
2 X4041x 6
4
VTRIP2
Adj.
4.7K
5
µC
8
5
Run
SCL
SDA
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
Figure 5. VTRIPX Set/Reset Sequence (X = 1, 2)
Vx = VCC, VxMON
Note: X = 1, 2
Let: MDE = Maximum Desired Error
VTRIPX Programming
No
Desired
VTRIPX
Present Value
MDE+
Acceptable
Desired Value
YES
Error Range
Execute
VTRIPX Reset Sequence
MDE–
Error = Actual - Desired
Execute
Set Higher VTRIPX Sequence
New VX applied =
Old VX applied + | Error |
Execute
Set Higher VX Sequence
New VX applied =
Old VX applied - | Error |
Apply VCC and Voltage
> Desired VTRIPX to VX
Execute Reset VTRIPX
Sequence
NO
Decrease VX
Output Switches?
YES
Error < MDE–
Error > MDE+
Actual VTRIPX Desired VTRIPX
| Error | < | MDE |
DONE
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and zeros
to the other bits of the control register.
6
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeros to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next
operation immediately after the stop condition.
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
BP: Block Protect Bit (Nonvolatile)
The Block Protect Bit, BP, determines which blocks of
the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will
prevent write operations to half or none of the array.
BP
Protected Addresses
(Size)
Array Lock
0
None
None
1
100h – 1FFh (256 bytes)
Upper Half of
Memory Array
PUP1, PUP0: Power-up Bits (Nonvolatile)
The Power-up bits, PUP1 and PUP0, determine the
tPURST time delay. The nominal power-up times are
shown in the following table.
PUP1
PUP0
Power-on Reset Delay (tPURST)
0
0
50ms
0
1
200ms (factory setting)
1
0
400ms
1
1
800ms
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
WD1
WD0
Watchdog Time Out Period
0
0
1.4 seconds
0
1
200 milliseconds
1
0
25 milliseconds
1
1
disabled (factory setting)
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded by a start and ended with a stop).
– Write a 06H to the Control Register to set the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
7
– Write a one byte value to the Control Register that
has all the control bits set to the desired state. The
Control register can be represented as qxys 001r in
binary, where xy are the WD bits, s isthe BP bit and
qr are the power-up bits. This operation proceeded
by a start and ended with a stop bit. Since this is a
nonvolatile write cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step
(qxys 011r) then the RWEL bit is set, but the WD1,
WD0, PUP1, PUP0, and BP bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.
– A read operation occurring between any of the
previous operations will not interrupt the register
write operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
FAULT DETECTION REGISTER
The Fault Detection Register (FDR) provides the user
the status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and three
Low Voltage Fail bits are volatile.
7
6
5
4
3
2
1
0
LV1F
LV2F
0
WDF
0
0
0
0
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write
operation directly to the address of the register and
only one data byte is allowed for each register write
operation.
There is no need to set the WEL or RWEL in the
control register to access this fault detection register.
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
Figure 6. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
At power-up, the Fault Detection Register is defaulted
to all “0”. The system needs to initialize this register to
all “1” before the actual monitoring take place. In the
event of any one of the monitored sources failed. The
corresponding bits in the register will change from a
“1” to a “0” to indicate the failure. At this moment, the
system should perform a read to the register and
noted the cause of the reset. After reading the register
the system should reset the register back to all “1”
again. The state of the Fault Detection Register can be
read at any time by performing a random read at
address 0FFh, using the special preamble.
The FDR can be read by performing a random read at
OFFh address of the register at any time. Only one
byte of data is read by the register read operation.
WDF, Watchdog Timer Fail Bit (Volatile)
The WDF bit will set to “0” when the WDO goes active.
LV1F, Low VCC Reset Fail Bit (Volatile)
The LV1F bit will be set to “0” when VCC (V1MON) falls
below VTRIP1.
LV2F, Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls
below VTRIP2.
Data Stable
SERIAL INTERFACE
Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 6.
Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 6.
Serial Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. (See Figure 6).
8
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
Figure 7. Valid Start and Stop Conditions
SCL
SDA
Start
Serial Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. See Figure 8.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
Stop
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Serial Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives
the master access to any one of the words in the array.
After receipt of the Word Address Byte, the device
responds with an acknowledge, and awaits the next
eight bits of data. After receiving the 8 bits of the Data
Byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating
a stop condition, at which time the device begins the
internal write cycle to the nonvolatile memory. During
this internal write cycle, the device inputs are disabled, so
the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 9.
A write to a protected block of memory will suppress
the acknowledge bit.
Figure 8. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
9
Acknowledge
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
Figure 9. Byte Write Sequence
Signals from
the Master
S
t
a
r
t
Byte
Address
Slave
Address
SDA Bus
S
t
o
p
Data
0
A
C
K
Signals from
the Slave
A
C
K
A
C
K
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowledge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page.
This means that the master can write 16 bytes to the
page starting at any location on that page. If the master
begins writing at location 10, and loads 12 bytes, then
the first 6 bytes are written to locations 10 through 15,
and the last 6 bytes are written to locations 0 through 5.
Afterwards, the address counter would point to location
6 of the page that was just written. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time.
Figure 10. Page Write Operation
(1 n 16)
S
t
a
r
t
Signals from
the Master
SDA Bus
Byte
Address
Slave
Address
1 0 1 0 0 0
0
A
C
K
Signals from
the Slave
S
t
o
p
Data
(n)
Data
(1)
A
C
K
A
C
K
A
C
K
Figure 11. Writing 12 bytes to a 16-byte page starting at location 10.
7 Bytes
address
=6
5 Bytes
address pointer
ends here
Addr = 7
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
10
address
10
address
n-1
all inputs are disabled until completion of the internal
write cycle. See Figure 10 for the address, acknowledge, and data transfer sequence.
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
Figure 12. Acknowledge Polling Sequence
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full data
byte plus its associated ACK is sent, then the device
will reset itself without performing the write. The contents of the array will not be effected.
Acknowledge Polling
The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the
device initiates the internal high voltage cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
See Figure 12.
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Random Reads, and Sequential Reads.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. See Figure 13 for the
address, acknowledge, and data transfer sequence.
11
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
ACK
Returned?
Issue STOP
NO
YES
High Voltage Cycle
Complete. Continue
Command Sequence?
Issue STOP
NO
YES
Continue Normal
Read or Write
Command Sequence
PROCEED
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master
must first perform a “dummy” write operation. The master
issues the start condition and the Slave Address Byte,
receives an acknowledge, then issues the Word Address
Bytes. After acknowledging receipts of the Word Address
Bytes, the master immediately issues another start condition and the Slave Address Byte with the R/W bit set to
one. This is followed by an acknowledge from the device
and then by the eight bit word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. See Figure 14 for the
address, acknowledge, and data transfer sequence.
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 15. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected.
This operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FFhex
General Purpose Memory Organization, A8:A0
Address: 00h to 1FFh
General Purpose Memory Array Configuration
Memory Address
A8:A0
000h
0FFh
100h
Sequential Read
Lower 256 bytes
Upper 256 bytes
Block Protect Option
1FFh
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicating it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘101x’. Where
x=0 is for Array, x=1 is for Control Register or Fault
Detection Register.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one operation. At the end of the address space the counter “rolls
over” to address 0000H and the device continues to output data for each acknowledge received. See Figure 15
for the acknowledge and data transfer sequence.
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
Figure 13. X40410/11 Addressing
Slave Byte
General Purpose Memory
Control Register
1
1
0
0
1
1
0
1
0
0
0
0
Fault Detection Register
1
0
1
1
0
0
A8 R/W
1 R/W
0
R/W
SERIAL DEVICE ADDRESSING
Word Address
General Purpose Memory A7 A6 A5 A4 A3 A2 A1
Control Register
1
1
1
1
1
1
1
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FFhex
Fault Detection Register
1
1
1
1
1
1
1
A0
1
1
Figure 14. Current Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
12
S
t
a
r
t
Slave
Address
1 0 1 0 0 0
S
t
o
p
1
Data
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
Figure 15. Random Address Read Sequence
S
t
a
r
t
Signals from
the Master
SDA Bus
10 1
0 0
S
t
a
r
t
Byte
Address
Slave
Address
1
0
A
C
K
Signals from
the Slave
S
t
o
p
Slave
Address
A
C
K
A
C
K
Data
Data Protection
– One bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the operation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation.
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for tPURST.
Figure 16. Sequential Read Sequence
Signals from
the Master
Slave
Address
SDA Bus
A
C
K
A
C
K
S
t
o
p
A
C
K
1
A
C
K
Signals from
the Slave
Data
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
13
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature.......................... -65°C to +150°C
Voltage on any pin with
respect to VSS ...................................... -1.0V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds) ........ 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0°C
70°C
Industrial
-40°C
+85°C
Chip Supply
Voltage
Monitored*
Voltages
X40410/11
-A or -B
2.7V to 5.5V
2.6V to 5V
X40410/11C, X40414/15
2.7V to 5.5V
1V to 3.6V
Version
*See Ordering Info
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)
Symbol
Typ.(4)
Max.
Unit
Active Supply Current (VCC) Read
1.5
mA
Active Supply Current (VCC) Read
3.0
mA
6
10
µA
VIL = VCC x 0.1
VIH = VCC x 0.9
fSCL, fSDA = 400kHz
25
30
µA
VSDA = VSCL = VCC
Others = GND or VCC
Parameter
ICC1(1)
ICC2(1)
ISB1(1)(6)
Standby Current (VCC) AC (WDT off)
ISB2(2)(6)
Standby Current (VCC) DC (WDT on)
Min.
Test Conditions
VIL = VCC x 0.1
VIH = VCC x 0.9,
fSCL = 400kHz
ILI
Input Leakage Current (SCL)
10
µA
VIL = GND to VCC
ILO
Output Leakage Current (SDA, V2FAIL, WDO, RESET)
10
µA
VSDA = GND to VCC
Device is in Standby(2)
VIL(3)
Input LOW Voltage (SDA, SCL)
-0.5
VCC x 0.3
V
(3)
VCC + 0.5
V
Input HIGH Voltage (SDA, SCL)
VCC x 0.7
VHYS(6)
Schmitt Trigger Input Hysteresis
• Fixed input level
• VCC related level
0.2
.05 x VCC
VOL
Output LOW Voltage (SDA, RESET/RESET, V2FAIL, WDO)
VOH
Output (RESET) HIGH Voltage
VIH
14
V
V
0.4
VCC - 0.8
VCC - 0.4
V
IOL = 3.0mA (2.7-5.5V)
IOL = 1.8mA (2.7-3.6V)
V
IOH = -1.0mA (2.7-5.5V)
IOH = -0.4mA (2.7-3.6V)
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)
Symbol
Parameter
Min.
Typ.(4)
Max.
Unit
4.75
V
Test Conditions
VCC Supply
VTRIP1(5)
tRPD2(6)
VCC Trip Point Voltage Range
2.0
4.55
4.6
4.65
V
X40410/11-A
4.35
4.4
4.45
V
X40410/11-B
2.85
2.9
2.95
V
X40410/11-C,
X40414/15-A&C
2.55
2.6
2.65
V
X40414/15-B
5
µS
15
µA
4.75
3.5
V
V
X40410/11
X40414/15
VTRIP2 to V2FAIL
Second Supply Monitor
IV2
VTRIP2
V2MON Current
V2MON Trip Point Voltage Range
1.7
0.9
2.85
2.9
2.95
V
X40410/11-A
2.55
2.6
2.65
V
X40410/11-B
1.65
1.7
1.75
V
X40410/11-C
1.25
1.3
1.35
V
X40414/15-A&B
0.95
1.0
1.05
V
X40414/15-C
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) VIL Min. and VIH Max. are for reference only and are not tested.
(4) At 25°C, VCC = 5V.
(5) See Ordering Information for standard programming levels. For custom programmed levels, contact factory.
(6) Based on characterization data.
EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2)
V
Vref
R
VxMON
V = 100mV
+
C
VREF
Output Pin
–
tRPDX = 5µs worst case
CAPACITANCE
Symbol
COUT(1)
CIN(1)
Note:
Parameter
Max.
Unit
Test Conditions
Output Capacitance (SDA, RESET, RESET, V2FAIL,
WDO)
8
pF
VOUT = 0V
Input Capacitance (SCL)
6
pF
VIN = 0V
(1) This parameter is not 100% tested.
15
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
VCC = 5V
VOUT
5V
4.6k
2.06k
RESET
WDO
SDA
V2MON
30pF
4.6k
V2FAIL
30pF
30pF
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing levels
VCC x 0.5
Output load
Standard output load
16
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
A.C. CHARACTERISTICS
400kHz
Symbol
Min.
Max.
Unit
SCL Clock Frequency
0
400
kHz
tIN
Pulse width Suppression Time at inputs
50
tAA
SCL LOW to SDA Data Out Valid
0.1
tBUF
Time the bus free before start of new transmission
1.3
tLOW
Clock LOW Time
1.3
µs
tHIGH
Clock HIGH Time
0.6
µs
tSU:STA
Start Condition Setup Time
0.6
µs
tHD:STA
Start Condition Hold Time
0.6
µs
tSU:DAT
Data In Setup Time
100
ns
tHD:DAT
Data In Hold Time
0
µs
tSU:STO
Stop Condition Setup Time
0.6
µs
Data Output Hold Time
50
ns
fSCL
tDH
Note:
Parameter
ns
0.9
µs
µs
+.1Cb(1)
300
ns
300
ns
400
pF
tR
SDA and SCL Rise Time
20
tF
SDA and SCL Fall Time
20 +.1Cb(1)
Cb
Capacitive load for each bus line
(1) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
tHIGH
tF
SCL
tR
tSU:DAT
tSU:STA
SDA IN
tLOW
tHD:STA
tHD:DAT
tSU:STO
tAA
tDH
tBUF
SDA OUT
17
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
Write Cycle Timing
SCL
SDA
ACK
8th Bit of Last Byte
tWC
Stop
Condition
Start
Condition
Nonvolatile Write Cycle Timing
Symbol
tWC
Note:
Parameter
(1)
Min.
Write Cycle Time
Typ.(1)
Max.
Unit
5
10
ms
(1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Power Fail Timings
tR
VTRIPX
[
[
VCC or
V2MON
]
]
tRPDL
tRPDX
LOWLINE or
V2FAIL or
V3FAIL
tRPDL
tRPDX
tRPDL
tRPDX
tF
VRVALID
X = 2, 3
18
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
RESET/RESET Timings
VTRIP1
VCC
tPURST
tPURST
tRPD1
tF
tR
RESET
VRVALID
RESET
LOW VOLTAGE AND WATCHDOG TIMING PARAMETERS
Symbol
Min.
Typ.(1)
Max.
Unit
tRPD1(2)
VTRIP1 to RESET/RESET (Power-down only)
5
µs
tRPDX(2)
VTRIP2 to V2FAIL
5
µs
tPURST
Parameters
Power-on Reset delay:
PUP1=0, PUP0=0
PUP1=0, PUP0=1 (factory setting)
PUP1=1, PUP0=0
PUP1=1, PUP0=1
ms
ms
ms
ms
50
200(2)
400(2)
800(2)
tF
VCC, V2MON, Fall Time
20
mVµs
tR
VCC, V2MON, Rise Time
20
mVµs
Reset Valid VCC
1
V
VRVALID
tWDO
Watchdog Timer Period:
WD1=0, WD0=0
WD1=0, WD0=1
WD1=1, WD0=0
WD1=1, WD0=1 (factory setting)
tRST1
Watchdog Reset Time Out Delay
WD1=0, WD0=0
WD1=0, WD0=1
100
200
300
ms
tRST2
Watchdog Reset Time Out Delay WD1=1, WD0=0
12.5
25
37.5
ms
tRSP
Watchdog timer restart pulse width
1.4(2)
200(2)
25
OFF
1
s
ms
ms
µs
Notes: (1) VCC = 5V at 25°C.
(2) Values based on characterization data only.
19
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
Watchdog Time Out For 2-Wire Interface
Start
Start
Clockin (0 or 1)
tRSP
< tWDO
SCL
SDA
tRST
WDO
tWDO
tRST
WDT
Restart
Start
Minimum Sequence to Reset WDT
SCL
SDA
VTRIPX Set/Reset Conditions
VCC/V2MON
(VTRIPX)
tTHD
VP
tTSU
WDO
tVPS
tVPH
SCL
7
0
0
7
0
tVPO
7
SDA
00h
A0h
tWC
Start
01h* sets VTRIP1
09h* sets VTRIP2
03h*
0Bh*
resets VTRIP1
resets VTRIP2
* all others reserved
20
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
VTRIP1, VTRIP2, Programming Specifications: VCC = 2.0–5.5V; Temperature = 25°C
Parameter
Description
Min.
Max.
Unit
tVPS
WDO Program Voltage Setup time
10
µs
tVPH
WDO Program Voltage Hold time
10
µs
tTSU
VTRIPX Level Setup time
10
µs
tTHD
VTRIPX Level Hold (stable) time
10
µs
tWC
VTRIPX Program Cycle
10
ms
tVPO
Program Voltage Off time before next cycle
1
ms
Programming Voltage
15
18
V
VTRAN1
VTRIP1 Set Voltage Range
2.0
4.75
V
VTRAN2
VTRIP2 Set Voltage Range – X40410/11
1.7
4.75
V
VTRAN2A
VTRIP2 Set to Voltage Range – X40414/15
0.9
3.5
V
Vtv
VTRIPX Set Voltage variation after programming (-40 to +85°C).
-25
+25
mV
tVPS
WDO Program Voltage Setup time
10
VP
21
µs
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
PACKAGING INFORMATION
8-Lead Plastic, SOIC, Package Code S8
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0.050" Typical
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
FOOTPRINT
0.030"
Typical
8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
22
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
PACKAGING INFORMATION
8-Lead Plastic, TSSOP, Package Code V8
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.114 (2.9)
.122 (3.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
(4.16) (7.72)
Detail A (20X)
(1.78)
.031 (.80)
.041 (1.05)
(0.42)
(0.65)
All Measurements Are Typical
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
23
FN8116.0
March 28, 2005
X40410, X40411, X40414, X40415
ORDERING INFORMATION
VCC
Range
VTRIP1 Range
VTRIP2 Range
Package
Operating
Temperature
Range
2.9-5.5
4.6V±50mV
2.9V±50mV
8L SOIC
0oC - 70oC
X40410S8-A
X40411S8-A
-40oC - 85oC
X40410S8I-A
X40411S8I-A
0oC - 70oC
X40410V8-A
X40411V8-A
-40oC - 85oC
X40410V8I-A
X40411V8I-A
X40410S8-B
X40411S8-B
X40410S8I-B
X40411S8I-B
X40410V8-B
X40411V8-B
X40410V8I-B
X40411V8I-B
8L TSSOP
2.6-5.5
4.4V±50mV
2.6V±50mV
0o C
8L SOIC
-
-40oC
8L TSSOP
0o C
-
-40oC
1.7-3.6
2.9V±50mV
1.7V±50mV
0o C
8L SOIC
8L TSSOP
-
2.9V±50mV
1.3V±50mV
2.6V±50mV
1.3V±50mV
X40411S8-C
0oC - 70oC
X40410V8-C
X40411V8-C
X40410V8I-C
X40411V8I-C
X40414S8-A
X40415S8-A
X40414S8I-A
X40415S8I-A
X40414V8-A
X40415V8-A
X40414V8I-A
X40415V8I-A
0o C
0o C
8L SOIC
8L TSSOP
-
2.9V±50mV
1.0V±50mV
-
85oC
70oC
-
85oC
70oC
X40414S8-B
X40415S8-B
X40415S8I-B
0oC - 70oC
X40414V8-B
X40415V8-B
X40414V8I-B
X40415V8I-B
X40414S8-C
X40415S8-C
X40414S8I-C
X40415S8I-C
X40414V8-C
X40415V8-C
X40414V8I-C
X40415V8I-C
-
-40oC
8L TSSOP
70oC
X40414S8I-B
0o C
8L SOIC
-
85oC
-40oC - 85oC
-40oC
1.0-3.6
70oC
X40411S8I-C
-40oC
1.3-3.6
-
85oC
X40410S8-C
-40oC
8L TSSOP
70oC
X40410S8I-C
0o C
8L SOIC
-
85oC
Part Number
with RESET
-40oC - 85oC
-40oC
1.3-3.6
70oC
Part Number
with RESET
0o C
-
-40oC
-
85oC
70oC
-
85oC
70oC
-
85oC
PART MARK INFORMATION
8-Lead Package
X4041XX
YYWWXX
0/1/4/5
Package - S/V
A, B, or C
I – Industrial
Blank – Commercial
WW – Workweek
YY – Year
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
24
FN8116.0
March 28, 2005
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