X4045S8Z

DATASHEET X4043, X4045 FN8118 Rev 3.00 December 9, 2015 4k, 512 x 8 Bit CPU Supervisor with 4kbit EEPROM FEATURES DESCRIPTION • Selectable watchdog timer • Low VCC detection and reset assertion —Five standard reset threshold voltages —Adjust low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Low power CMOS — MDE+ Actual VTRIP – Desired VTRIP = Error | Error | < | MDE | DONE Control Register The control register provides the user a mechanism for changing the block lock and watchdog timer settings. The block lock and watchdog timer bits are nonvolatile and do not change when power is removed. The user must issue a stop after sending this byte to the register to initiate the nonvolatile cycle that stores WD1, WD0, BP2, BP1, and BP0. The X4043/45 will not acknowledge any data bytes written after the first byte is entered. The control register is accessed with a special preamble in the slave byte (1011) and is located at address 1FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. Prior to writing to the control register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. See "Writing to the Control Register". FN8118 Rev 3.00 December 9, 2015 Page 8 of 24 X4043, X4045 The state of the control register can be read at any time by performing a random read at address 1FFh, using the special preamble. Only one byte is read by each register read operation. The X4043/45 resets itself after the first byte is read. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation. WD1, WD0: Watchdog Timer Bits The bits WD1 and WD0 control the period of the watchdog timer. The options are shown below. WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds 600 milliseconds 0 1 7 6 5 4 3 2 1 0 1 0 200 milliseconds 0 WD1 WD0 BP1 BP0 RWEL WEL BP2 1 1 Disabled (factory setting) RWEL: Register Write Enable Latch (Volatile) Writing to the Control Register The RWEL bit must be set to “1” prior to a write to the Control Register. Changing any of the nonvolatile bits of the control register requires the following steps: WEL: Write Enable Latch (Volatile) – Write a 02H to the control register to set the write enable latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceeded by a start and ended with a stop). The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. BP2, BP1, BP0: Block Protect Bits (Nonvolatile) BP2 BP1 BP0 The block protect bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of eight segments of the array. Protected Addresses (Size) 0 0 0 None (factory setting) None 0 0 1 180h - 1FFh (128 bytes) Upper 1/4 (Q4) 0 1 0 100h - 1FFh (256 bytes) Upper 1/2 (Q3,Q4) Array Lock 0 1 1 000h - 1FFh (512 bytes) Full Array (All) 1 0 0 000h - 00Fh (16 bytes) First Page (P1) 1 0 1 000h - 01Fh (32 bytes) First 2 pgs (P2) 1 1 0 000h - 03Fh (64 bytes) First 4 pgs (P4) 1 1 1 000h - 07Fh (128 bytes) First 8 pgs (P8) FN8118 Rev 3.00 December 9, 2015 – Write a 06H to the control register to set both the register write enable latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop). – Write a value to the control register that has all the control bits set to the desired state. This can be represented as 0xys t01r in binary, where xy are the WD bits, and rst are the BP bits. (Operation preceeded by a start and ended with a stop). Since this is a nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (0xys t11r) then the RWEL bit is set, but the WD1, WD0, BP2, BP1 and BP0 bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK. – A read operation occurring between any of the previous operations will not interrupt the register write operation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the control register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set. Page 9 of 24 X4043, X4045 SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data trans- fers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. Serial Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 6. Figure 6. Valid Data Changes on the SDA Bus SCL SDA Data Stable Data Change Data Stable Serial Start Condition Serial Stop Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 7. All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 6. Figure 7. Valid Start and Stop Conditions SCL SDA Start Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 8. The device will respond with an acknowledge after recognition of a start condition and if the correct device identifier and select bits are contained in the slave address byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will FN8118 Rev 3.00 December 9, 2015 Stop acknowledge all incoming data and address bytes, except for the slave address byte when the device identifier and/or select bits are incorrect. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not detected. The master must then issue a stop condition to return the device to standby mode and place the device into a known state. Page 10 of 24 X4043, X4045 Figure 8. Acknowledge Response From Receiver SCL from Master 1 8 9 Data Output from Transmitter Data Output from Receiver Start Acknowledge Operational Notes X4043/45 ADDRESSING The device powers-up in the following state: Slave Address Byte Following a start condition, the master must output a slave address byte. This byte consists of several parts: – a device type identifier that is ‘1010’ to access the array and ‘1011’ to access the control register. – The WEL bit is set to ‘0’. In this state it is not possible to write to the device. – SDA pin is the input mode. – RESET signal is active for tPURST. – two bits of ‘0’. – one bit that becomes the MSB of the address. – one bit of the slave command byte is a R/W bit. The R/W bit of the slave address byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. Refer to Figure 8. – After loading the entire slave address byte from the SDA bus, the device compares the input slave byte data to the proper slave byte. Upon a correct compare, the device outputs an acknowledge on the SDA line. Word Address The word address is either supplied by the master or obtained from an internal counter. The internal counter is undefined on a power-up condition. Slave Address Byte Slave Byte 1 0 1 0 SERIAL WRITE OPERATIONS Byte Write For a write operation, the device requires the slave address byte and a word address byte. This gives the master access to any one of the words in the array. After receipt of the word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the data byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 10. A write to a protected block of memory will suppress the acknowledge bit. Figure 9. X4043/45 Addressing Array Control Reg. – The device is in the low power standby state. 1 1 0 1 0 0 A8 R/W A5 A4 A3 A2 A1 A0 Word Address A7 FN8118 Rev 3.00 December 9, 2015 A6 Page 11 of 24 X4043, X4045 Figure 10. Byte Write Sequence Signals from the Master S t a r t Byte Address Slave Address SDA Bus S t o p Data 0 A C K Signals from the Slave Page Write The device is capable of a page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it “rolls over” and goes back to ‘0’ on A C K A C K the same page. This means that the master can write 16 bytes to the page starting at any location on that page. If the master begins writing at location 10, and loads 12 bytes, then the first 5 bytes are written to locations 10 through 15, and the last 7 bytes are written to locations 0 through 6. Afterwards, the address counter would point to location 7 of the page that was just written. If the master supplies more than 16 bytes of data, then new data over-writes the previous data, one byte at a time. Figure 11. Page Write Operation Signals from the Master S t a r t SDA Bus Signals from the Slave (1  n 16) Slave Address S t o p Data (n) Data (1) Byte Address 0 A C K A C K A C K A C K Figure 12. Writing 12-bytes to a 16-byte page starting at location 10 5 Bytes 7 Bytes Address =6 Address Pointer Ends Here Addr = 7 The master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. See Figure 11 for the address, acknowledge, and data transfer sequence. FN8118 Rev 3.00 December 9, 2015 Address 10 Address n-1 Stops and Write Modes Stop conditions (that terminate write operations) must be sent by the master after sending at least 1 full data byte, plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected. Page 12 of 24 X4043, X4045 Figure 13. Acknowledge Polling Sequence Acknowledge Polling The disabling of the inputs during nonvolatile cycles can be used to take advantage of the typical 5kHz write cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the device initiates the internal nonvolatile cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the slave address byte for a write or read operation. If the device is still busy with the nonvolatile cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to the flow chart in Figure 13. Byte Load Completed by Issuing STOP. Enter ACK Polling Issue START Issue Slave Address Byte (Read or Write) Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads. YES Nonvolatile Cycle Complete. Continue Command Current Address Read NO Issue STOP YES Internally the device contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power-up, the address of the address counter is undefined, requiring a read or write operation for initialization. Upon receipt of the slave address byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. Refer to Figure 13 for the address, acknowledge, and data transfer sequence. NO ACK Returned? Serial Read Operations Issue STOP Continue Normal Read or Write Command Sequence PROCEED It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. Figure 14. Current Address Read Sequence Signals from the Master SDA Bus Signals from the Slave FN8118 Rev 3.00 December 9, 2015 S t a r t S t o p Slave Address 1 A C K Data Page 13 of 24 X4043, X4045 Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the slave address byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. After acknowledging receipts of the word address bytes, the master immediately issues another start condition and the slave address byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. Refer to Figure 15 for the address, acknowledge, and data transfer sequence. Figure 15. Random Address Read Sequence Signals from the Master S t a r t SDA Bus S t a r t Byte Address Slave Address 1 0 A C K Signals from the Slave S t o p Slave Address A C K There is a similar operation, called “Set Current Address” where the device does no operation, but enters a new address into the address counter if a stop is issued instead of the second start shown in Figure 14. The device goes into standby mode after the stop and all bus activity will be ignored until a start is detected. The next current address read operation reads from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data. Sequential Read Sequential reads can be initiated as either a current address read or random address read. The first data byte is transmitted as with the other modes; however, the mas- A C K Data ter now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. At the end of the address space the counter “rolls over” to address 0000H and the device continues to output data for each acknowledge received. Refer to Figure 16 for the acknowledge and data transfer sequence. Figure 16. Sequential Read Sequence Signals from the Master Slave Address SDA Bus 1 Signals from the Slave A C K A C K Data (1) A C K Data (2) S t o p A C K Data (n-1) Data (n) (n is any integer greater than 1) FN8118 Rev 3.00 December 9, 2015 Page 14 of 24 X4043, X4045 Data Protection The following circuitry has been included to prevent inadvertent writes: Symbol Table INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW – The WP pin, when held HIGH, prevents all writes to the array and the control register. Don’t Care: Changes Allowed Changing: State Not Known – Communication to the device is inhibited as a result of a low voltage condition (VCC < VTRIP)any in-progress communication is terminated. N/A Center Line is High Impedance – The WEL bit must be set to allow write operations. – The proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. – A three step sequence is required before writing into the control register to change watchdog timer or block lock settings. WAVEFORM – Block lock bits can protect sections of the memory array from write operations. FN8118 Rev 3.00 December 9, 2015 Page 15 of 24 X4043, X4045 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias ................... -65°C to +135°C Storage temperature ........................ -65°C to +150°C Voltage on any pin with respect to VSS ...................................... -1.0V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds) ........ 300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min. 0°C -40°C Max. 70°C +85°C Option -2.7 and -2.7A Blank and -4.5A Supply Voltage Limits 2.7V to 5.5V 4.5V to 5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) VCC = 2.7 to 5.5V Max. Unit Active supply current read 1.0 mA Active supply current write 3.0 mA Standby current AC (WDT off) 1 µA VIL = VCC x 0.1, VIH = VCC x 0.9 fSCL= 400kHz, SDA = open VCC = 1.22 x VCC min ISB2(2) Standby current DC (WDT off) 1 µA VSDA = VSCL = VSB Others = GND or VSB ISB3(2) Standby current DC (WDT on) 20 µA VSDA =VSCL = VSB Others = GND or VSB ILI Input leakage current 10 µA VIN = GND to VCC ILO Output leakage current 10 µA VSDA = GND to VCC device is in standby Symbol ICC1 (1) ICC2 (1) (2) ISB1 Parameter Min. VIL(3) Input LOW voltage -0.5 VCC x 0.3 V VIH(3) Input nonvolatile VCC x 0.7 VCC + 0.5 V VHYS Schmitt trigger input hysteresis Fixed input level VCC related level 0.2 .05 x VCC VOL Output LOW voltage Test Conditions VIL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 400kHz V V 0.4 V IOL = 3.0mA (2.7-5.5V) IOL = 1.8mA (2.0-3.6V) Notes: (1) The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte. (3) VIL min. and VIH max. are for reference only and are not tested. FN8118 Rev 3.00 December 9, 2015 Page 16 of 24 X4043, X4045 CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V) Symbol COUT (4) CIN(4) Parameter Max. Unit Test Conditions Output capacitance (SDA, RESET/RESET) 8 pF VOUT = 0V Input capacitance (SCL, WP) 6 pF VIN = 0V Notes: (4) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS 5V 5V 1533 For VOL= 0.4V and IOL = 3 mA SDA 4.6k Input pulse levels 0.1 VCC to 0.9 VCC Input rise and fall times 10ns Input and output timing levels 0.5 VCC Output load Standard output load RESET 100pF 100pF A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) 100kHz Symbol fSCL Parameter SCL clock frequency 400kHz Min. Max. Min. Max. Unit 0 100 0 400 kHz tIN Pulse width suppression time at inputs n/a n/a 50 0.9 0.1 ns tAA SCL LOW to SDA data out valid 0.1 tBUF Time the bus free before start of new transmission 4.7 1.3 µs tLOW Clock LOW time 4.7 1.3 µs tHIGH Clock HIGH time 4.0 0.6 µs tSU:STA Start condition setup time 4.7 0.6 µs tHD:STA Start condition hold time 4.0 0.6 µs tSU:DAT Data in setup time 250 100 ns tHD:DAT Data in hold time 5.0 0 µs tSU:STO 0.9 µs Stop condition setup time 0.6 0.6 µs tDH Data output hold time 50 50 ns tR SDA and SCL rise time 1000 20 + .1Cb(6) 300 ns tF SDA and SCL fall time 300 20 + .1Cb(6) 300 ns tSU:WP WP setup time 0.4 0.6 s tHD:WP WP hold time 0 0 s Cb Capacitive load for each bus line 400 400 pF Notes: (5) Typical values are for TA = 25°C and VCC = 5.0V (6) Cb = total capacitance of one bus line in pF. FN8118 Rev 3.00 December 9, 2015 Page 17 of 24 X4043, X4045 TIMING DIAGRAMS Bus Timing tHIGH tF SCL tLOW tR tSU:DAT tSU:STA tHD:DAT tHD:STA SDA IN tSU:STO tAA tDH tBUF SDA OUT WP Pin Timing START SCL Clk 1 Clk 9 Slave Address Byte SDA IN tSU:WP tHD:WP WP Write Cycle Timing SCL SDA 8th Bit of Last Byte ACK tWC Stop Condition Start Condition Nonvolatile Write Cycle Timing Symbol tWC(7) Parameter Write cycle time Min. Typ.(7) Max. Unit 5 10 ms Notes: (7) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. FN8118 Rev 3.00 December 9, 2015 Page 18 of 24 X4043, X4045 Power-Up and Power-Down Timing VTRIP VCC tPURST 0 Volts tR tPURST tF tRPD VRVALID RESET (X4043) VRVALID RESET (X4045) RESET Output Timing Symbol Parameter Min. Typ. Max. Unit VTRIP Reset trip point voltage, X4043/45-4.5A Reset trip point voltage, X4043/45 Reset trip point voltage, X4043/45-2.7A Reset trip point voltage, X4043/45-2.7 4.5 4.25 2.85 2.55 4.62 4.38 2.92 2.62 4.75 4.5 3.0 2.7 V tPURST Power-up reset time out 100 200 400 ms tRPD(8) VCC detect to RESET/RESET 10 20 µs tF(8) tR (8) VRVALID VCC fall time 20 mV/µs VCC rise time 20 mV/µs Reset valid VCC 1 V tWDO Watchdog time out period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 tRSP Watchdog Time Restart pulse width tRST Reset time out 100 450 1 200 600 1.4 300 800 2 1 100 ms ms sec µs 200 400 ms Notes: (8) This parameter is periodically sampled and not 100% tested. FN8118 Rev 3.00 December 9, 2015 Page 19 of 24 X4043, X4045 Watchdog Time Out For 2-Wire Interface Start Clockin (0 or 1) tRSP Start < tWDO SCL SDA tRST (4043) RESET tWDO tRST WDT Restart Start Minimum Sequence to Reset WDT SCL SDA VTRIP Set/Reset Conditions VCC (VTRIP) tTHD VP tTSU WP tVPS tVPH SCL 7 0 0 7 0 tVPO 7 SDA A0h Start 01h* sets VTRIP 03h* resets VTRIP 00h tWC * all others reserved FN8118 Rev 3.00 December 9, 2015 Page 20 of 24 X4043, X4045 VTRIP Programming Specifications: VCC = 2.0-5.5V; Temperature = 25°C Parameter Description Min. Max. Unit tVPS WP Program Voltage Setup time 10 µs tVPH WP Program Voltage Hold time 10 µs tTSU VTRIP Level Setup time 10 µs tTHD VTRIP Level Hold (stable) time 10 µs tWC VTRIP Program Cycle 10 ms tVPO Program Voltage Off time before next cycle 1 ms VP Programming Voltage 15 18 V VTRIP Set Voltage Range 2.0 4.75 V Vtv VTRIP Set Voltage variation after programming (-40 to +85°C). -25 +25 mV tVPS WP Program Voltage Setup time 10 VTRAN µs REVISION HISTORY The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION December 9, 2015 FN8118.3 CHANGE Updated Ordering Information Table on page 2. Added Revision History and About Intersil sections. ABOUT INTERSIL Intersil Corporation is a leading provider of innovative power management and precision analog solutions. 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For information regarding Intersil Corporation and its products, see www.intersil.com FN8118 Rev 3.00 December 9, 2015 Page 21 of 24 X4043, X4045 PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) 0.050" Typical 0.050" Typical 0° - 8° 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) FOOTPRINT 0.030" Typical 8 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) FN8118 Rev 3.00 December 9, 2015 Page 22 of 24 X4043, X4045 PACKAGING INFORMATION 8-Lead Miniature Small Outline Gull Wing Package Type M 0.118 ± 0.002 (3.00 ± 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) Typ. R 0.014 (0.36) 0.118 ± 0.002 (3.00 ± 0.05) 0.030 (0.76) 0.0216 (0.55) 0.036 (0.91) 0.032 (0.81) 0.040 ± 0.002 (1.02 ± 0.05) 7° Typ. 0.008 (0.20) 0.004 (0.10) 0.0256" Typical 0.007 (0.18) 0.005 (0.13) 0.150 (3.81) Ref. 0.193 (4.90) Ref. 0.025" Typical 0.220" FOOTPRINT 0.020" Typical 8 Places NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS) FN8118 Rev 3.00 December 9, 2015 Page 23 of 24 X4043, X4045 PACKAGING INFORMATION 8-Lead Plastic Dual In-Line Package Type P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. Half Shoulder Width On All End Pins Optional 0.145 (3.68) 0.128 (3.25) Seating Plane 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) .073 (1.84) Max. Typ. 0.010 (0.25) 0.060 (1.52) 0.020 (0.51) 0.020 (0.51) 0.016 (0.41) 0.325 (8.25) 0.300 (7.62) 0° 15° NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH FN8118 Rev 3.00 December 9, 2015 Page 24 of 24