X5001S8Z

X5001 CPU Supervisor ESIGNS R NEW D N T O F D E D N ME COMME EPL AC E NO T RE ND E D R E nter at e M C M t r O uppo S l N O REC a ic m/tsc n o tersil.c our Tech contact ERSIL or www.in T 1-888-IN DATASHEET FN8125 Rev 1.00 May 30, 2006 FEATURES DESCRIPTION • 200ms power-on reset delay • Low VCC detection and reset assertion —Five standard reset threshold voltages —Adjust low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Selectable nonvolatile watchdog timer —0.2, 0.6, 1.4 seconds —Off selection —Select settings through software • Long battery life with low power consumption — 0 Error = 0 DONE SPI INTERFACE The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device monitors the CS/WDI line and asserts RESET output if there is no activity within user selectable timeout period. The device also monitors the VCC supply and asserts the RESET if VCC falls below a preset minimum (VTRIP). The device contains an 8-bit watchdog timer register to control the watchdog time out period. The current settings are accessed via the SI and SO pins. FN8125 Rev 1.00 May 30, 2006 All instructions (Table 1) and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. Page 7 of 20 X5001 Read Watchdog Timer Register Operation Watchdog Timer Register 7 6 5 4 3 2 1 0 0 0 0 WD1 WD0 0 0 0 If there is not a nonvolatile write in progress, the read watchdog timer instruction returns the setting of the watchdog timer control bits. The other bits are reserved and will return’0’ when read. See Figure 3. Watchdog Timer Control Bits The watchdog timer control bits, WD0 and WD1, select the watchdog time out period. These nonvolatile bits are programmed with the set watchdog timer (SWDT) instruction. Watchdog Control Bits WD1 WD0 Watchdog Time Out (Typical) 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled If a nonvolatile write is in progress, the read watchdog timer register Instruction returns a HIGH on SO. When the nonvolatile write cycle is completed, a separate read watchdog timer instruction should be used to determine the current status of the watchdog control bits. RESET Operation The RESET (X5001) output is designed to go LOW whenever VCC has dropped below the minimum trip point and/or the watchdog timer has reached its programmable time out limit. The RESET output is an open drain output and requires a pull-up resistor. Write Watchdog Register Operation Changing the watchdog timer register is a two step process. First, the change must be enabled by setting the watchdog change latch (see below). This instruction is followed by the set watchdog timer (SWDT) instruction, which includes the data to be written (Figure 5). Data bits 3 and 4 contain the watchdog settings and data bits 0, 1, 2, 5, 6 and 7 must be “0”. Watchdog Change Latch The watchdog change latch must be SET before a Write watchdog timer operation is initiated. The Enable Watchdog Change (EWDC) instruction will set the latch and the Disable Watchdog Change (DWDC) instruction will reset the latch (Figure 6). This latch is automatically reset upon a power-up condition and after the completion of a valid nonvolatile write cycle. Operational Notes The device powers-up in the following state: – The device is in the low power standby state. – A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. – SO pin is high impedance. – The watchdog change latch is reset. – The RESET signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes: – A EWDC instruction must be issued to enable a change to the watchdog timeout setting. – CS must come HIGH at the proper clock count in order to implement the requested changes to the watchdog timeout setting. Table 1. Instruction Set Definition Instruction Format Note: Instruction Name and Operation 0000 0110 EWDC: Enable Watchdog Change Operation 0000 0100 DWDC: Disable Watchdog Change Operation 0000 0001 SWDT: Set Watchdog Timer control bits: Instruction followed by contents of register: 000(WD1) (WD0)000 See Watchdog Timer Settings and Figure 7. 0000 0101 RWDT: Read Watchdog Timer Control Bits Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first. FN8125 Rev 1.00 May 30, 2006 Page 8 of 20 X5001 Figure 5. Read Watchdog Timer Setting CS 0 1 2 3 4 5 6 7 ... SCK RWDT Instruction ... SI W D 1 SO W D 0 ... Figure 6. Enable Watchdog Change/Disable Watchdog Change Sequence CS 0 1 2 3 4 5 6 7 SCK Instruction (1 Byte) SI High Impedance SO Figure 7. Write Watchdog Timer Sequence CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Data Byte Instruction 6 SI SO FN8125 Rev 1.00 May 30, 2006 High Impedance 5 4 3 W W D D 1 0 Page 9 of 20 X5001 Figure 8. Read Nonvolatile Status (Option 1) (Used to determine end of Watchdog Timer store operation) CS 0 1 2 3 4 5 6 7 SCK RWDT Instruction SI Nonvolatile Write in Progress SO SO HIGH During 1st Bit While in the Nonvolatile Write Cycle Figure 9. Read Nonvolatile Status (Option 2) (Used to determine end of Watchdog Timer store operation) CS 0 1 2 3 4 5 6 7 SCK RWDT Instruction SI Nonvolatile Write in Progress SO SO HIGH During Nonvolatile Write Cycle FN8125 Rev 1.00 May 30, 2006 Page 10 of 20 X5001 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias ................... -65°C to +135°C Storage temperature ........................ -65°C to +150°C Voltage on any pin with respect to VSS ...................................... -1.0V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10s) .................... 300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this datasheet) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Commercial Min. 0°C Max. Voltage Option -1.8 -2.7 or -2.7A -4.5 or -4.5A +70°C Note: Supply Voltage Limits 1.8V to 3.6V 2.7V to 5.5V 4.5V to 5.5V PT= Package, Temperature D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min. Limits Typ Max. 5 Unit Test Conditions mA SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open 0.4 mA SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open ICC1 VCC write current (Active) ICC2 VCC read current (Active) ISB1 VCC standby current WDT=OFF 1 µA CS = VCC, VIN = VSS or VCC, VCC = 5.5V ISB2 VCC standby current WDT=ON 50 µA CS = VCC, VIN = VSS or VCC, VCC = 5.5V ISB3 VCC standby current WDT=ON 20 µA CS = VCC, VIN = VSS or VCC, VCC = 3.6V ILI Input leakage current 10 µA VIN = VSS to VCC ILO Output leakage current VOUT = VSS to VCC 0.1 10 µA VIL(1) Input LOW voltage -0.5 VCC x 0.3 V VIH(1) Input HIGH voltage VCC x 0.7 VCC + 0.5 V VOL1 Output LOW voltage 0.4 V VCC > 3.3V, IOL = 2.1mA VOL2 Output LOW voltage 0.4 V 2V < VCC < 3.3V, IOL = 1mA VOL3 Output LOW voltage 0.4 V VCC  2V, IOL = 0.5mA VOH1 Output HIGH voltage VCC-0.8 V VCC > 3.3V, IOH = -1.0mA VOH2 Output HIGH voltage VCC-0.4 V 2V < VCC  3.3V, IOH = -0.4mA VOH3 Output HIGH voltage VCC-0.2 V VCC  2V, IOH = -0.25mA VOLRS Reset output LOW voltage V IOL = 1mA FN8125 Rev 1.00 May 30, 2006 0.1 0.4 Page 11 of 20 X5001 POWER-UP TIMING Symbol tPUR (2) (2) tPUW Parameter Min. Max. Unit Power-up to read operation 1 ms Power-up to write operation 5 ms Max. Unit Conditions Output capacitance (SO, RESET) 8 pF VOUT = 0V Input capacitance (SCK, SI, CS) 6 pF VIN = 0V CAPACITANCE (TA = +25°C, f = 1MHz, VCC = 5V) Symbol COUT CIN (2) (2) Test Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT 3V A.C. TEST CONDITIONS 5V 3.3k 1.64k Output Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x0.5 RESET 1.64k 100pF 30pF A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing 1.8V-3.6V SymboL Parameter 2.7V-5.5V Min. Max. Min. Max. Unit 0 1 0 2 MHz fSCK Clock frequency tCYC Cycle time 1000 500 ns tLEAD CS lead time 400 200 ns tLAG CS lag time 400 200 ns tWH Clock HIGH time 400 200 ns tWL Clock LOW time 400 200 ns tSU Data setup time 100 50 ns tH Data hold time 100 50 ns tRI(3) Input rise time 2 2 µs tFI(3) Input fall time 2 2 µs tCS CS deselect time tWC (4) Write cycle time FN8125 Rev 1.00 May 30, 2006 250 150 10 ns 10 ms Page 12 of 20 X5001 Data Output Timing 1.8V-3.6V Symbol Parameter 2.7V-5.5V Min. Max. Min. Max. Unit 0 1 0 2 MHz fSCK Clock frequency tDIS Output disable time 400 200 ns Output valid from clock low 400 200 ns tV tHO Output hold time tRO(3) Output rise time 300 150 ns tFO(3) Output fall time 300 150 ns 0 0 ns Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Figure 10. Data Output Timing CS tCYC tWH tLAG SCK tV SO SI tHO MSB Out tWL tDIS MSB–1 Out LSB Out ADDR LSB IN Figure 11. Data Input Timing tCS CS tLEAD tLAG SCK tSU SI SO FN8125 Rev 1.00 May 30, 2006 tH MSB In tRI tFI LSB In High Impedance Page 13 of 20 X5001 SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Figure 12. Power-Up and Power-Down Timing VTRIP VTRIP VCC tPURST 0 Volts tF tPURST tRPD tR RESET (X5001) RESET Output Timing Symbol Min. Typ. Max. Unit VTRIP Reset trip point voltage, X5001PT-4.5A Reset trip point voltage, X5001PT-4.5 Reset trip point voltage, X5001PT-2.7A Reset trip point voltage, X5001PT-2.7 Reset trip point voltage, X5001PT-1.8 4.50 4.25 2.85 2.55 1.70 4.63 4.38 2.92 2.63 1.75 4.75 4.50 3.00 2.70 1.80 V tPURST Power-up reset timeout 100 200 280 ms 500 ns tRPD tF (5) VCC detect to reset/output (5) VCC fall time 0.1 ns (5) VCC rise time 0.1 ns 1 V tR VRVALID Note: Parameter Reset valid VCC (5) This parameter is periodically sampled and not 100% tested. PT = Package, Temperature FN8125 Rev 1.00 May 30, 2006 Page 14 of 20 X5001 Figure 13. CS vs. RESET Timing CS tCST RESET tWDO tRST tWDO tRST RESET Output Timing Symbol Parameter Min. Typ. Max. Unit 200 600 1.4 300 800 2 ms ms sec tWDO Watchdog timeout period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 1 tCST CS pulse width to reset the watchdog 400 tRST Reset Timeout 100 ns 200 300 ms VTRIP Programming Timing Diagram VCC (VTRIP) VTRIP tTSU tTHD VP VPE tVPS tVPH tPCS CS tVPO tRP SCK SI 03h FN8125 Rev 1.00 May 30, 2006 0001h 02h 0001h or 0003h Page 15 of 20 X5001 VTRIP Programming Parameters Parameter Description Min. Max. Unit tVPS VTRIP program enable voltage setup time 1 µs tVPH VTRIP program enable voltage hold time 1 µs tPCS VTRIP programming CS inactive time 1 µs tTSU VTRIP setup time 1 µs tTHD VTRIP hold (stable) time 10 ms tWC VTRIP write cycle time tVPO VTRIP program enable voltage Off time (between successive adjustments) 0 µs tRP VTRIP program recovery period (between successive adjustments) 10 ms VP Programming voltage 15 18 V VTRIP programmed voltage range 1.7 5.0 V Vta1 Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C) -0.1 +0.4 V Vta2 Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP. Programmed at 25°C.] -25 +25 mV Vtr VTRIP program voltage repeatability (Successive program operations. Programmed at 25°C.) -25 +25 mV Vtv VTRIP program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV VTRAN 10 ms VTRIP programming parameters are periodically sampled and are not 100% tested. FN8125 Rev 1.00 May 30, 2006 Page 16 of 20 X5001 VCC Supply Current vs. Temperature (ISB) tWDO vs. Voltage/Temperature (WD1, 0 = 1, 1) 1.85 Isb (µA) 14 1.80 1.75 18 Reset (seconds) Watchdog Timer On (VCC = 5V) 17 20 15 Watchdog Timer On (VCC = 3V) 11 Watchdog Timer Off (VCC = 3V, 5V) 0.55 0.35 -40C 1.65 1.55 90°C 1.7 90C 3.1 Voltage 4.5 tWDO vs. Voltage/Temperature (WD1, 0 = 1, 0) 0.85 5.025 VTRIP = 5V 5.000 0.80 Reset (seconds) 4.975 3.525 Voltage 25°C 1.50 1.40 VTRIP vs. Temperature (programmed at 25°C) VTRIP = 3.5V 3.500 3.475 2.525 VTRIP = 2.5V 2.500 -40°C 0.75 25°C 0.70 90°C 0.65 0.60 2.475 0 25 Temperature 1.7 85 tPURST vs. Temperature 275 Reset (seconds) 270 265 260 255 250 245 240 235 -40 FN8125 Rev 1.00 May 30, 2006 25 Degrees °C 4.5 3.1 Voltage tWDO vs. Voltage/Temperature (WD1, 0 0 = 0, 1) 280 Time (ms) -40°C 1.60 1.45 1.0 25C Temp (c) 1.70 90 0.30 0.29 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 -40°C 25°C 90°C 1.7 3.1 4.5 Voltage Page 17 of 20 X5001 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference N 8 14 16 NOTES: Rev. L 2/01 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 FN8125 Rev 1.00 May 30, 2006 Page 18 of 20 X5001 Plastic Dual-In-Line Packages (PDIP) E D A2 SEATING PLANE L N A PIN #1 INDEX E1 c e b A1 NOTE 5 1 eA eB 2 N/2 b2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE A 0.210 0.210 0.210 0.210 0.210 MAX A1 0.015 0.015 0.015 0.015 0.015 MIN A2 0.130 0.130 0.130 0.130 0.130 ±0.005 b 0.018 0.018 0.018 0.018 0.018 ±0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 D 0.375 0.750 0.750 0.890 1.020 ±0.010 E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 E1 0.250 0.250 0.250 0.250 0.250 ±0.005 e 0.100 0.100 0.100 0.100 0.100 Basic eA 0.300 0.300 0.300 0.300 0.300 Basic eB 0.345 0.345 0.345 0.345 0.345 ±0.025 L 0.125 0.125 0.125 0.125 0.125 ±0.010 N 8 14 16 18 20 Reference NOTES 1 2 Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. FN8125 Rev 1.00 May 30, 2006 Page 19 of 20 X5001 Thin Shrink Small Outline Plastic Packages (TSSOP) M8.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M L A D -C- e  A2 A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE c 0.10(0.004) C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX  8 0o 8 7 8o Rev. 1 12/00 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) © Copyright Intersil Americas LLC 2005-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8125 Rev 1.00 May 30, 2006 Page 20 of 20