X5169S8I-2.7A

X5168, X5169 ESIGNS R NEW D NT O F D E (Replaces E ND COMME PL ACEM r a t N OT R E DED R E N te E n e M C M t r O RECSheet NOData al Suppo /tsc June 15, 2006 r Technic ww.intersil.com u o t c ta w r con o TERSIL 1-888-IN X25268, X25169) FN8130.2 CPU Supervisor with 16Kbit SPI EEPROM Features These devices combine three popular functions, Power-on Reset Control, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. • Low VCC Detection and Reset Assertion - Five standard reset threshold voltages - Re-program low VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. • Long Battery Life with Low Power Consumption - 3.3V, IOH = -1.0mA VCC - 0.8 V VOH2 Output HIGH voltage 2V < VCC  3.3V, IOH = -0.4mA VCC - 0.4 V VOH3 Output HIGH voltage VCC 2V, IOH = -0.25mA VCC - 0.2 V VOLS Reset output LOW voltage IOL = 1mA Capacitance V TA = +25°C, f = 1MHz, VCC = 5V. SYMBOL COUT (NOTE 2) 0.4 TEST Output capacitance (SO, RESET/RESET) CIN (NOTE 2) Input capacitance (SCK, SI, CS, WP) CONDITIONS MAX. UNIT VOUT = 0V 8 pF VIN = 0V 6 pF NOTES: 1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested. 12 FN8130.2 June 15, 2006 X5168, X5169 A.C. Test Conditions Equivalent A.C. Load Circuit at 5V VCC 5V 5V 4.6k 2.06k Output Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 RESET/RESET 3.03k 30pF 100pF AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified.) 2.7-5.5V SYMBOL PARAMETER MIN MAX UNIT 0 2 MHz SERIAL INPUT TIMING fSCK Clock frequency tCYC Cycle time 500 ns tLEAD CS lead time 250 ns tLAG CS lag time 250 ns tWH Clock HIGH time 200 ns tWL Clock LOW time 200 ns tSU Data setup time 50 ns tH Data hold time 50 ns tRI(3) Input rise time 100 ns tFI(3) Input fall time 100 ns tCS CS deselect time tWC(4) Write cycle time 13 500 ns 10 ms FN8130.2 June 15, 2006 X5168, X5169 Serial Input Timing tCS CS tLEAD tLAG SCK tSU tH SI SO tRI tFI MSB IN LSB IN High Impedance Serial Output Timing 2.7-5.5V SYMBOL PARAMETER MIN MAX UNIT 0 2 MHz fSCK Clock frequency tDIS Output disable time 250 ns Output valid from clock low 200 ns tV tHO Output hold time 0 ns tRO(3) Output rise time 100 ns tFO(3) Output fall time 100 ns Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing CS tCYC tWH tLAG SCK tV SO SI MSB Out tHO MSB–1 Out tWL tDIS LSB Out ADDR LSB IN 14 FN8130.2 June 15, 2006 X5168, X5169 Power-Up and Power-Down Timing VCC VTRIP VTRIP tPURST 0 Volts tPURST tF tRPD tR RESET (X5168) RESET (X5169) RESET Output Timing SYMBOL PARAMETER VTRIP Reset trip point voltage, X5168-4.5A, X5168-4.5A Reset trip point voltage, X5168, X5169 Reset trip point voltage, X5168-2.7A, X5169-2.7A Reset trip point voltage, X5168-2.7, X5169-2.7 VTH tF MAX UNIT 4.5 4.25 2.85 2.55 4.63 4.38 2.93 2.63 4.75 4.5 3.0 2.7 V 20 Power-up reset time out (5) 100 VCC detect to reset/output 200 mV 280 ms 500 ns (5) VCC fall time 100 µs (5) VCC rise time 100 µs 1 V tR VRVALID Note: TYP VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) tPURST tRPD MIN Reset valid VCC (5) This parameter is periodically sampled and not 100% tested. VTRIP Set Conditions tTHD VCC VTRIP tTSU tVPS CS tVPS tRP tP tVPH tVPH tVPO VP SCK VP tVPO SI 15 FN8130.2 June 15, 2006 X5168, X5169 VTRIP Reset Conditions VCC* tRP tP tVPS CS tVPS tVP1 tVPH tVPO VCC SCK VP tVPO SI *VCC > Programmed VTRIP VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C PARAMETER DESCRIPTION MIN MAX UNIT tVPS SCK VTRIP program voltage setup time 1 µs tVPH SCK VTRIP program voltage hold time 1 µs VTRIP program pulse width 1 µs tTSU VTRIP level setup time 10 µs tTHD VTRIP level hold (stable) time 10 ms tWC VTRIP write cycle time tRP VTRIP program cycle recovery period (between successive programming cycles) 10 ms tVPO SCK VTRIP program voltage off time before next cycle 0 ms Programming voltage 15 18 V VTRIP programmed voltage range 1.7 5.0 V Vta1 Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C) -0.1 +0.4 V Vta2 Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP] (programmed at 25°C) -25 +25 mV Vtr VTRIP program voltage repeatability (successive program operations) (programmed at 25°C) -25 +25 mV Vtv VTRIP Program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV tP VP VTRAN 10 ms VTRIP programming parameters are periodically sampled and are not 100% tested. 16 FN8130.2 June 15, 2006 X5168, X5169 Typical Performance tPURST vs. Temperature VCC Supply Current vs. Temperature (ISB) 205 18 Watchdog Timer On (VCC = 5V) 16 200 195 14 Isb (µA) Time (ms) 190 12 Watchdog Timer On (VCC = 5V) 10 8 6 185 180 175 170 4 165 Watchdog Timer Off (VCC = 3V, 5V) 2 0 -40C 25C Temp (°C) 160 -40 90C 25 90 Degrees °C VTRIP vs. Temperature (programmed at 25°C) 5.025 VTRIP = 5V 5.000 4.975 Voltage 3.525 VTRIP = 3.5V 3.500 3.475 2.525 VTRIP = 2.5V 2.500 2.475 0 25 Temperature 17 85 FN8130.2 June 15, 2006 X5168, X5169 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference N 8 14 16 Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 18 FN8130.2 June 15, 2006 X5168, X5169 Plastic Dual-In-Line Packages (PDIP) E D A2 SEATING PLANE L N A PIN #1 INDEX E1 c e b A1 NOTE 5 1 eA eB 2 N/2 b2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE A 0.210 0.210 0.210 0.210 0.210 MAX A1 0.015 0.015 0.015 0.015 0.015 MIN A2 0.130 0.130 0.130 0.130 0.130 ±0.005 b 0.018 0.018 0.018 0.018 0.018 ±0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 D 0.375 0.750 0.750 0.890 1.020 ±0.010 E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 E1 0.250 0.250 0.250 0.250 0.250 ±0.005 e 0.100 0.100 0.100 0.100 0.100 Basic eA 0.300 0.300 0.300 0.300 0.300 Basic eB 0.345 0.345 0.345 0.345 0.345 ±0.025 L 0.125 0.125 0.125 0.125 0.125 ±0.010 N 8 14 16 18 20 Reference NOTES 1 2 Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. 19 FN8130.2 June 15, 2006 X5168, X5169 Thin Shrink Small Outline Plastic Packages (TSSOP) M14.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M 0.25 0.010 SEATING PLANE L A D -C-  e A1 b A2 c 0.10(0.004) 0.10(0.004) M C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX  14 0o 14 7 8o Rev. 2 4/06 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN8130.2 June 15, 2006