X5648S14T1

DATASHEET X5648, X5649 (Replaces X25648, X25649) FN8136 Rev 0.00 March 17, 2005 CPU Supervisor with 64Kbit SPI EEPROM FEATURES DESCRIPTION • Low VCC detection and reset assertion —Five standard reset threshold voltages —Re-program low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Long battery life with low power consumption — 3.3V, IOL = 2.1mA 2V < VCC  3.3V, IOL = 1mA 2V < VCC  3.3V, IOH = –0.4mA VOH2 Output HIGH voltage VCC - 0.4 V VOH3 Output HIGH voltage VCC - 0.2 V VCC  2V, IOH = -0.25mA VOLS Reset output LOW voltage V IOL = 1mA 0.4 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol COUT CIN (2) (2) Test Max. Unit Conditions Output capacitance (SO, RESET/RESET) 8 pF VOUT = 0V Input capacitance (SCK, SI, CS, WP) 6 pF VIN = 0V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. FN8136 Rev 0.00 March 17, 2005 Page 10 of 18 X5648, X5649 (Replaces X25648, X25649) EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC 5V 5V 4.6k 2.06k Output A.C. TEST CONDITIONS Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 RESET/RESET 3.03k 30pF 100pF A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing 2.7-5.5V Symbol Parameter Min. Max. Unit 0 2 MHz fSCK Clock frequency tCYC Cycle time 500 ns tLEAD CS lead time 250 ns tLAG CS lag time 250 ns tWH Clock HIGH time 200 ns tWL Clock LOW time 250 ns tSU Data setup time 50 ns tH Data hold time 50 ns tRI(3) tFI(3) Input rise time 100 ns Input fall time 100 ns tCS tWC (4) CS deselect time 500 ns Write cycle time 10 ms Serial Input Timing tCS CS tLEAD tLAG SCK tSU SI SO FN8136 Rev 0.00 March 17, 2005 tH MSB IN tRI tFI LSB IN High Impedance Page 11 of 18 X5648, X5649 (Replaces X25648, X25649) Serial Output Timing 2.7-5.5V Symbol Parameter Min. Max. Unit 0 2 MHz fSCK Clock frequency tDIS Output disable time 250 ns Output valid from clock low 250 ns tV tHO Output hold time tRO(3) tFO(3) Output rise time 100 ns Output fall time 100 ns 0 ns Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing CS tCYC tWH tLAG SCK tV SO SI tHO MSB Out tWL MSB–1 Out tDIS LSB Out ADDR LSB IN Power-Up and Power-Down Timing VCC VTRIP VTRIP tPURST 0 Volts tPURST tR tF tRPD RESET (X5648) RESET (X5649) FN8136 Rev 0.00 March 17, 2005 Page 12 of 18 X5648, X5649 (Replaces X25648, X25649) RESET Output Timing Symbol VTRIP VTH Parameter Reset trip point voltage, X5648-4.5A, X5648-4.5A Reset trip point voltage, X5648, X5649 Reset trip point voltage, X5648-2.7A, X5649-2.7A Reset trip point voltage, X5648-2.7, X5649-2.7 Power-up reset time out tRPD(5) VCC detect to reset/output Max. Unit 4.5 4.25 2.85 2.55 4.63 4.38 2.93 2.63 4.75 4.5 3.0 2.7 V 100 200 20 mV 280 ms 500 ns (5) VCC fall time 100 µs (5) VCC rise time 100 µs 1 V tR VRVALID Note: Typ. VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) tPURST tF Min. Reset valid VCC (5) This parameter is periodically sampled and not 100% tested. VTRIP Set Conditions tTHD VCC VTRIP tTSU tVPS CS tVPS tRP tP tVPH tVPH tVPO VP SCK VP tVPO SI FN8136 Rev 0.00 March 17, 2005 Page 13 of 18 X5648, X5649 (Replaces X25648, X25649) VTRIP Reset Conditions VCC* tRP tP tVPS CS tVPS tVP1 tVPH tVPO VCC SCK VP tVPO SI *VCC > Programmed VTRIP VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C Parameter Description Min. Max. Unit tVPS SCK VTRIP program voltage setup time 1 µs tVPH SCK VTRIP program voltage hold time 1 µs VTRIP program pulse width 1 µs tTSU VTRIP level setup time 10 µs tTHD VTRIP level hold (stable) time 10 ms tWC VTRIP write cycle time tRP VTRIP program cycle recovery period (between successive programming cycles) tVPO SCK VTRIP program voltage off time before next cycle 0 Programming voltage 15 18 V VTRIP programed voltage range 1.7 5.0 V Vta1 Initial VTRIP program voltage accuracy (VCC applied - VTRIP) (programmed at 25°C) -0.1 +0.4 V Vta2 Subsequent VTRIP program voltage accuracy [(VCC applied - Vta1) - VTRIP) (programmed at 25°C) -25 +25 mV Vtr VTRIP program voltage repeatability (successive program operations) (programmed at 25°C) -25 +25 mV Vtv VTRIP program variation after programming (0 - 75°C). (programmed at 25°C.) -25 +25 mV tP VP VTRAN 10 10 ms ms ms VTRIP programming parameters are periodically sampled and are not 100% tested. FN8136 Rev 0.00 March 17, 2005 Page 14 of 18 X5648, X5649 (Replaces X25648, X25649) TYPICAL PERFORMANCE tPURST vs. Temperature VCC Supply Current vs. Temperature (ISB) 205 18 200 Watchdog Timer On (VCC = 5V) 16 195 14 Isb (µA) Time (ms) 190 12 Watchdog Timer On (VCC = 5V) 10 8 6 185 180 175 170 165 4 Watchdog Timer Off (VCC = 3V, 5V) 2 160 -40 0 -40 25 Temp (°C) 90 25 Degrees °C 90 VTRIP vs. Temperature (programmed at 25°C) 5.025 VTRIP = 5V 5.000 4.975 Voltage 3.525 VTRIP = 3.5V 3.500 3.475 2.525 VTRIP = 2.5V 2.500 2.475 0 FN8136 Rev 0.00 March 17, 2005 25 Temperature 85 Page 15 of 18 X5648, X5649 (Replaces X25648, X25649) PACKAGING INFORMATION 8-Lead Plastic Dual In-Line Package Type P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. Half Shoulder Width On All End Pins Optional 0.145 (3.68) 0.128 (3.25) Seating Plane 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) .073 (1.84) Max. Typ. 0.010 (0.25) 0.060 (1.52) 0.020 (0.51) 0.020 (0.51) 0.016 (0.41) 0.325 (8.25) 0.300 (7.62) 0° 15° NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH FN8136 Rev 0.00 March 17, 2005 Page 16 of 18 X5648, X5649 (Replaces X25648, X25649) PACKAGING INFORMATION 14-Lead Plastic, SOIC, Package Code S14 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.51) 0.336 (8.55) 0.345 (8.75) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.10) 0.010 (0.25) 0.050 (1.27) 0.050"Typical 0.010 (0.25) 0.020 (0.50) X 45° 0.050"Typical 0° - 8° 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) FOOTPRINT 0.030"Typical 14 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) FN8136 Rev 0.00 March 17, 2005 Page 17 of 18 X5648, X5649 (Replaces X25648, X25649) Ordering Information VCC Range VTRIP Range Package Operating Temperature Range Part Number RESET (Active LOW) Part Number RESET (Active HIGH) 4.5-5.5V 4.5.4.75 8 pin PDIP 0-70°C X5648P-4.5A X5649P-4.5A 14L SOIC 0-70°C X5648S14-4.5A X5649S14-4.5A -40-85°C X5648S14I-4.5A X5649S14I-4.5A 8 pin PDIP 0-70°C X5648P X5649P 14L SOIC 0-70°C X5648S14 X5649S14 -40-85°C X5648S14I X5649S14I 4.5-5.5V 4.25.4.5 2.7-5.5V 2.85-3.0 14L SOIC 0-70°C X5648S14-2.7A X5649S14-2.7A 2.7-5.5V 2.55-2.7 14L SOIC 0-70°C X5648S14-2.7 X5649S14-2.7 Part Mark Information X5648/49 W X Blank = 14-Lead SOIC P = 8 Pin DIP Blank = 5V ±10%, 0°C to +70°C, VTRIP = 4.25-4.5 AL = 5V±10%, 0°C to +70°C, VTRIP = 4.5-4.75 I = 5V ±10%, -40°C to +85°C, VTRIP = 4.25-4.5 AM = 5V ±10%, -40°C to +85°C, VTRIP = 4.5-4.75 F = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.55-2.7 AN = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.85-3.0 G = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.55-2.7 AP = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.85-3.0 © Copyright Intersil Americas LLC 2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8136 Rev 0.00 March 17, 2005 Page 18 of 18